Handbook of Silicon Based MEMS Materials and Technologies (Micro and Nano Technologies)

Handbook of Silicon Based MEMS Materials and Technologies Micro & Nano Technologies Series Editor: Jeremy Ramsden Pr...

Author: Veikko Lindroos | Markku Tilli | Ari Lehto | Teruaki Motooka

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Handbook of Silicon Based MEMS Materials and Technologies

Micro & Nano Technologies

Series Editor: Jeremy Ramsden

Professor of Nanotechnology

Microsystems and Nanotechnology Centre, Department of Materials

Cranﬁeld University, United Kingdom

The aim of this book series is to disseminate the latest developments in small scale technologies with a particular emphasis on accessible and practical content. These books will appeal to engineers from industry, academic and government sectors. 9780815515944

Veikko Lindroos, Markku Tilli, Ari Lehto and Teruaki Motooka, Handbook of Silicon Based MEMS Materials and Technologies (2010)

9780815515838

Waqar Ahmed and M.J. Jackson, Emerging Nanotechnologies for Manufacturing (2009)

9780080964546

Richard Leach, Fundamental Principles of Engineering Nanometrology (2009)

9780815520238

Jeremy Ramsden, Applied Nanotechnology (2009)

9780815515869

Matthew Hull and Diana Bowman, Risk Governance of Nanotechnology (2009)

9780815515432

Nam-Trung Nguyen, Micromixers (2008)

9780815515449

Jean Berthier, Microdrops and Digital Microﬂuidics (2008)

9780815515777

Behraad Bahreyni, Fabrication and Design of Resonant Microdevices (2008)

9780815515739

Francois Leonard, The Physics of Carbon Nanotube Devices (2009)

9780815515784

Mamadou Diallo, Jeremiah Duncan, Nora Savage, Anita Street and Richard Sustich, Nanotechnology Applications for Clean Water (2009)

9780815515876

Rolf Wüthrich, Micromachining Using Electrochemical Discharge Phenomenon (2009)

9780815515791

Matthias Worgull, Hot Embossing (2009)

Handbook of Silicon Based MEMS Materials and Technologies

Veikko Lindroos,

Markku Tilli,

Ari Lehto and

Teruaki Motooka

William

Andrew

Applied Science Publishers

William Andrew is an imprint of Elsevier The Boulevard, Langford Lane, Oxford OX5 1GB, UK 30 Corporate Road, Burlington, MA 01803 First edition 2010 Copyright © 2010 Published by Elsevier Inc. All rights reserved No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from the publisher. Details on how to seek permission, further information about the Publisher’s permissions policies and our arrangements with organizations such as the Copyright Clearance Center and the Copyright Licensing Agency, can be found at our website: www.elsevier.com/permissions. This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein). Notices Knowledge and best practice in this ﬁeld are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary. Practitioners and researchers must always rely on this own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library Library of Congress Cataloguing in Publication Data A catalogue record for this book is available from the Library of Congress ISBN: 978-0-8155-1594-4 For information on all Elsevier publications visit our website at www.elsevierdirect.com Typeset by MPS Limited, a Macmillan Company, Chennai, India www.macmillansolutions.com Printed and bound in United States of America 10 11 12 11 10 9 8 7 6 5 4 3 2 1

Preface

In summer 2006 we were approached by William Andrew Publishing about producing a MEMS related handbook. As the general guideline from the publisher was to keep in mind that they are particularly seek ing book content geared towards practical applications rather than theory. During the summer of 2006 we matured our under standing of the state-of-art as well as the further devel opment and needs of MEMS materials and technologies. As a result of such a maturation process, we understood that there are currently many handbooks and textbooks covering MEMS components, but their focus is more in the device physics and design rather than in mate rials and manufacturing processes. Also, it has been experienced in practice, that there is a need for a book covering starting materials as well as the most impor tant process steps in bulk micromachining fulﬁlling the needs of a device design engineer as well as process or development engineer working in manufacturing proc esses. Although many comprehensive textbooks cover, for instance, silicon from many aspects, they are not worn out in the hands of MEMS engineers, as they are too specialized. That is why a special emphasis was put on silicon, the most important starting material used in MEMS devices, different varieties of silicon wafer types used in MEMS process, material properties and meas urement techniques as well as analytical methods used in the silicon materials characterization. The aim is not to go too deep into the scientiﬁc details but, instead, to give a broader overview tailored for the needs of the MEMS industry. Also, in a similar manner, important selected process steps in MEMS manufacturing are treated to give an overview of the most recent progress. The MEMS industry is now at a turning point; MEMS industry has been so far mainly driven by auto motive and industrial applications—now the industry driver will be consumer electronics, more precisely portable electronics: mobile phones, MP3 players, digital cameras, camcorders, etc. The growth of the MEMS industry is forecast to be close to 20% annu ally, and there will be new entrants in the industry, who need to get basic understanding of the MEMS materi als and processes. Consumer electronics applications are also very cost sensitive. Therefore, it is essentially important to minimize the overall device costs and to

understand the whole supply chain. By applying proper material selection it makes possible to inﬂuence on the MEMS device processing costs. In order to fully under stand the present state-of-the-art and, in particular, the future trends of MEMS technology and industry, the Editors appreciate this opportunity to include the invited introductory overview contribution “Impact of Silicon MEMS – 30 Years After” by Dr. Tapani Ryhänen from Nokia Nanoscience Centre at the University of Cambridge. Based on the above motivation of the present state as well as the further development and needs, we have pre pared the present “Handbook of Silicon Based MEMS Materials and Technologies”. The book consists of ﬁve parts: Part I Silicon as MEMS material Part II Modeling in MEMS Part III Measuring MEMS Part IV Micromachining technologies in MEMS Part V Encapsulation of MEMS components These ﬁve parts are consisting of altogether 42 chap ters written by 73 world class MEMS contributors from 12 countries from Europe, North America and Asia. In addition to the general Editors of the book there were also invited and nominated additional Part Editors for each part of the book; i.e., Markku Tilli for Part I, Teruaki Motooka and Risto Nieminen for Part II, VeliMatti Airaksinen for Part III, Helmut Seidel for Part IV and Ari Lehto and Heikki Kuisma for Part V. During the actual course of the writing process of the book, there were arranged, in addition to the regular edi torial meetings, also “MEMS book author meetings,” once or twice annually, in order to maintain the common scope and objective for a uniform compilation of the book. Finally, the Editors would like to express their great appreciation to all of their fellow contributors for this unique window of opportunity to work with them, resulting in a comprehensive MEMS handbook, which illustrates a global cutting edge knowledge and exper tise within the most vigorously growing industry today. Furthermore, the Editors are grateful for the appropriate and constructive co-operation with the publishers, i.e. William Andrew (WA) and Elsevier, since its acquisition ix

Preface

of WA in January 2009. Our particular thanks go to Dr. Nigel Hollingworth of WA as well as to Matthew Deans, Melanie Benson and Renata Corbani of Elsevier for their valuable co-operation during the course of the work. Finally, the Editors are grateful to the Helsinki

x

University of Technology, which will be a member of the new Aalto University to be established at the begin ning of the year 2010, for providing various premises, such as secretarial and computational services, for the needs of the editorial work.

List of Contributors

Timo Aalto VTT Technical Research Centre of Finland, P.O. Box 1000, FI-02044 VTT, Finland Veli-Matti Airaksinen Helsinki University of Technology, P.O. Box 3500, FI 02015 TKK, Finland Marco Amiotti SAES Getters S.p.A., Viale Italia 77, 20010 Lainate (Milan), Italy Olli Anttila Silfex Incorporated - A Division of Lam Research Corporation, 950 South Franklin Street, Eaton, Ohio 45320, USA Paul A. Anzalone FEI Company, P.O. Box 332, Merrimack, NH 03054, USA Abhinav Bhushan University of California, Department of Mechanical and Aeronautical Engineering - College of Engineering - Bainer Hall - One Shields Avenue-Davis, CA 95616, USA Antonio Bonucci SAES Getters S.p.A., Viale Italia 77, 20010 Lainate (Milan), Italy

Cristina Davis University of California, Department of Mechanical and Aeronautical Engineering - College of Engineering Bainer Hall - One Shields Avenue - Davis, CA 95616, USA Viorel Dragoi EV Group, E. Thallner GmbH, DI Erich Thallner Strasse 1, A-4782 St. Florian/Inn, Austria Simo Eränen VTT Technical Research Centre of Finland, P.O. Box 1000, FI-02044 VTT, Finland Sami Franssila Helsinki University of Technology, P.O. Box 3500, FI-02015 TKK, Finland Alois Friedberger EADS Innovation Works, IW-SI, 81663 Munich, Germany Maria Ganchenkova Helsinki University of Technology, P.O. Box 1100, FI-02015 TKK, Finland Lucille Giannuzzi FEI Company, Hillsboro, OR 97124, USA

Jakub Bruzdzinski The Nordic Hysitron Laboratory, Helsinki University of Technology, P.O. Box 6200, 02015 TKK, Finland

Miguel Gosálvez Dept. Micro Nanosystems Engineering, University, 464-8603 Nagoya, Japan

Robert Candler UCLA Department of Electrical Engineering, Department of Electrical Engineering, 6731-H Boelter Hall, Los Angeles, CA, 90095, USA

Jakub Gronicz The Nordic Hysitron Laboratory, Helsinki University of Technology, P.O. Box 6200, FI-02015 TKK, Finland

Kuo-Shen Chen National Cheng-Kung University, Tainan, Department of Mechanical Engineering, National Cheng-Kung University, 1 University Rd., Taiwan, 70101, R.O.C. Andrea Conte SAES Getters S.p.A., Viale Italia 77, 20010 Lainate (Milan), Italy

Nagoya

Atte Haapalinna Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland Eero Haimi Helsinki University of Technology, P.O. Box 6200, FI-02015 TKK, Finland Kimmo Henttinen Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland xi

List of Contributors

David Horsley University of California, Davis, Department of Mechanical and Aeronautical Engineering, University of California, Davis, One Shields Ave., Davis, CA 95616, USA Akihisa Inoue Tohoku University, Institute for Materials Research, 2-1-1 Katahira Aoba-ku, Sendai 980-8577, Japan

Brandon Van Leer FEI Company, Hillsboro, OR 97124, USA Ari Lehto Helsinki University of Technology, P.O. Box 6200, FI-02015 TKK, Finland Christina Leinenbach Robert Bosch GmbH, P.O.Box 10 60 50, 70049 Stuttgart, Germany

Henrik Jakobsen Institute for Microsystem Technnology, Faculty of Technology and Engineering, Vestfold University College, P.O. Box 2243, N-3103 Tønsberg

Paul Lindner EV Group, E. Thallner GmbH, DI Erich Thallner Strasse 1, A-4782 St.Florian am Inn, Austria

Kerstin Jonsson NanoSpace AB, Uppsala Science Park, SE-751 83, Uppsala, SWEDEN

Veikko Lindroos Helsinki University of Technology, P.O. Box 6200, FI-02015 TKK, Finland

Dirk Kähler Advanced Electronic Packaging, Fraunhofer Institut für Siliziumtechnologie, Fraunhofer Str. 1, D-25524, Itzehoe, Germany

Giorgio Longoni SAES Getters S.p.A., Viale Italia 77, 20010 Lainate (Milan), Italy

Hannu Kattelus VTT Technical Research Centre of Finland, P.O. Box 1000, 02044 VTT, Finland

Jari Mäkinen Okmetic Oyj P.O. Box 44, FI-01301 Vantaa, Finland

Roy Knechtel X-FAB Semiconductor Foundries AG, Haarbergstraße 67, D-99097 Erfurt, Germany

Peter Merz MEMS Department, Fraunhofer Institut für Siliziumtechnologie, Fraunhoferstrasse 1, D-25524, Itzehoe, Germany

Kathrin Knese Robert Bosch GmbH, Automotive Electronics (AE/ EST2), Postfach 13 42, 72703 Reutlingen, Germany

Douglas J. Meyer AZonic Solar, Mesa, AZ, USA 2753 East El Moro Ave, Mesa, AZ 85204, USA

Kai Kolari VTT Technical Research Centre of Finland, P.O. Box 1000, FI-02044 VTT, Finland

Marco Moraja SAES Getters S.p.A., Viale Italia 77, 20010 Lainate (Milan), Italy

Mika Koskenvuori Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland

Teruaki Motooka Dept. of Materials Science & Engineering Kyushu University, Motooka 744, Fukuoka 819-0395, Japan

Heikki Kuisma VTI Technologies Oy, P.O. Box 27, FI-01621 Vantaa, Finland Adriana Lapadatu SensoNor Technologies AS, P.O. Box 196, N-3192 Horten, Norway Franz Laermer Robert Bosch GmbH, Corporate Sector Research and Advance Engineering, Microsystems (CR/PJ-TOP54), Postfach 10 60 50 , 70049 Stuttgart, Germany xii

Gerhard Müller EADS Innovation Works, IW-SI Sensors, Electronics & Systems Integration, 81663 Munich, Germany Shijo Nagao The Nordic Hysitron Laboratory, Helsinki University of Technology, P.O. Box 6200, FI-02015 TKK, Finland Risto Nieminen Helsinki University of Technology, P.O. Box 1100, FI-02015 TKK, Finland

List of Contributors

Roman Nowak The Nordic Hysitron Laboratory, Helsinki University of Technology, P.O. Box 6200,FI- 02015 TKK, Finland

Scott Sullivan Disco Hi-Tec America, Inc., 3269 Scott Blvd. Santa Clara, CA 95054-3011, U.S.A.

Juuso Olkkonen VTT Technical Research Centre of Finland, P.O.Box 1000, FI-02044 VTT, Finland

Tommi Suni VTT Technical Research Centre of Finland, P.O. Box 1000, FI-02044 VTT, Finland

Kuang-Shun Ou Department of Mechanical Engineering, National Cheng-Kung University, 1 University Rd., Taiwan, 70101, R.O.C.

Tuomo Suntola Picosun Oy, Tietotie 3, FI-02150 Espoo, Finland

Jari Paloheimo Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland Riikka Puurunen VTT Technical Research Centre of Finland, Tietotie 3, Espoo, Finland Wolfgang Reinert Advanced Electronic Packaging, Fraunhofer Institut für Siliziumtechnologie, Fraunhofer Str. 1, D-25524, Itzehoe, Germany Steve Reyntjens FEI Company, PO Box 80066, 5600 KA Eindhoven, The Netherlands

Markku Tilli Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland Ilkka Tittonen Helsinki University of Technology, P.O. Box 3500, FI-02015 TKK, Finland Santeri Tuomikoski VTI Technologies Oy, P.O. Box 27, 01621 Vantaa, Finland Örjan Vallin Uppsala University, The Ångström Laboratory, Solid State Electronics, Box 534, SE 75121 Uppsala, Sweden Timo Veijola Helsinki University of Technology, P.O. Box 3000, FI-02015 TKK, Finland

Tapani Ryhänen Nokia Research Centre, Eurolab, c/o Nanoscience Centre, University of Cambridge, 11 J J Thomson Avenue, Madingley Road, Cambridge, CB3 0FF, UK

Eeva Viinikka Culminatum Innovation, Tekniikantie 12, FI-02150 Espoo, Finland

Lauri Sainiemi Helsinki University of Technology, P.O. Box 3500, FI-02015 TKK, Finland

Oliver Wilhelmi FEI Company, PO Box 80066, 5600 KA Eindhoven, The Netherlands

Hele Savin Helsinki University of Technology, Espoo, P.O. Box 3500, FI-02015 TKK, Finland

Piotr Zachariasz The Nordic Hysitron Laboratory, Helsinki University of Technology, P.O. Box 6200, FI-02015 TKK, Finland

Helmut Seidel Universität des Saarlandes, Lehrstuhl für Mikromechanik, Mikroﬂuidik/Mikroaktorik, Postfach 15 11 50, D-66041 Saarbrücken, Germany

Irena Zubel Faculty of Microsystem Electronics and Photonics, Wroclaw University of Technology, Janiszewskiego 11/17, 50-372 Wroclaw, Poland

Parmanand Sharma Tohoku University, Institute for Materials Research, 2-1-1 Katahira Aoba-ku, Sendai 980-8577, Japan

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Overview

Impact of Silicon MEMS—30 Years After Tapani Ryhänen

Nokia Research Centre, Cambridge, UK

Introduction Silicon deforms elastically and is a very robust mechanical material. Silicon has small thermal expansion, high speed of sound and very low intrinsic mechanical losses. There exist various methods for both isotropic and anisotropic etching of silicon. The well controlled anisotropic etching of silicon especially has enabled the fabrication of microscale mechanical structures and devices. When these mechanical characteristics and the micromachining are combined with the mass scale manufacturing solutions from the IC industry, we have a platform for producing micromechanical sensors and actuators in huge volumes at low cost. First mechanical characterization and experiments in chemical wet etching of silicon were already carried out in the 1950s; and the industrial scale MEMS was born in the late 1970s. Today the various devices and even smaller objects of our physical world are becoming extensively connected to the digital information networks. We can say that the physical and digital worlds are merging. Smaller and smaller physical objects can be indexed by RF ID tags and other electrical labels. Small processors and communication capabilities can be integrated into a variety of small physical objects. The microelectromechanical components and systems (MEMS) developed over the past 30 years form the technology platform that enables sensing and even actuation in these small devices. Here the development of MEMS technologies is presented from the perspective of the mobile communication industry—from the rise of automotive applications of MEMS sensors to the expansion of MEMS components into consumer products. We have seen the first

expressions of new user interface concepts based on capabilities to sense, compute and create an action in real time. However, this pervasive capability of sensing, computing and communication means a complete new era of mobile devices and related digital services. This book is a demonstration of the maturity of the silicon MEMS technologies. The silicon micromechanics, measurement electronics and the packaging technologies have all been developed to a level where very large volume manufacturing is possible. We are ready to take the next leap towards the future devices and digital services.

Towards Mass Volumes of MEMS Devices Early Visions When Kurt E. Petersen wrote his famous review [1] of silicon micromechanics in 1982, there existed already eight companies working in the field. He covered nearly two hundred essential references in his paper. Above all the vision of the applications and opportunities was already well understood. Petersen discussed a very broad set of potential applications with commercial significance, such as, accelerometers, pressure transducers, torsional mirrors, resonant gate transistors, light modulators, resonating beam arrays, inkjet printer heads, and microelectromechanical switches. The research community was already formed: for example, the IEEE Transducers conference was organized already in 1969, and the Sensors and Actuators journal was established in 1980. The first large volume application of MEMS was only some years away. xv

Overview

Fig 1 l Resonant gate transistor published in 1968 by William E. Newell and his coworkers [8].

Most of the concepts of micromechanical devices and fabrication technologies go back in time to the 1960s and the early 1970s. The mechanical characteristics of single crystalline silicon, the anisotropic etching of silicon by potassium hydroxide (KOH) and several concepts of micromechanical devices were studied [2–6]. An interesting example of early device concepts is shown in Fig. 1. W.E. Newell and his coworkers [7, 8] published a resonant gate transistor based on a micromechanical resonator made of electroplated gold in 1967. Integration of micromechanical structures, such as resonators, was a natural continuum from the pre-silicon electronics to the early concepts of silicon integrated devices. The first commercial application by Hewlett Packard used a MEMS cantilever based frequency detector in frequency synthesizers in 1980 [9]. In spite of these early concepts, the development of practical commercial applications based on MEMS resonators has taken nearly 30 years, even today very few commercial devices exist besides the scientific instruments, such as, the resonating cantilevers of the atomic force microscopes [10, 11] and the biosensors [12]. The capability to create large arrays of similar components with precise dimensions enabled new device concepts. Furthermore, the possibility to benefit from the fabrication capabilities that were scaling up in the IC industry created the starting point towards the commercial applications of MEMS.

Ink Jet Printer Nozzles Create the Industry This capability to manufacture precise components and arrays of micromachined structures practically enabled the ink jet printers during the 1980s. IBM xvi

demonstrated [13, 14] the value of silicon micromachining to achieve the necessary printing precision with the integrated methods to control and manage the inks in the same micromachined device. The first mass volume application of silicon MEMS was created, and the ink jet printers became the main stream of printing in the growing information technology market. The electrostatic control of ink jets [15] for printing purposes was studied in the beginning of the 1970s. The capability to etch the ink jet nozzles into the silicon wafer using anisotropic KOH wet etching and to integrate the control electrodes into the same device using thin film and semiconductor processes enabled the sufficient miniaturization to improve the quality of ink jet printing to the level where the commercial solutions were possible. Still today the ink jet printer application forms one third of the total MEMS market. Today the printing is expanding as a paradigm to electronics manufacturing [16]. Reel-to-reel manufacturing solutions based on either inorganic or organic inks will be one of the future solutions for manufacturing low cost electronics.

Automotive Applications Drive the Reliability and the Quality The automotive applications of pressure and motion sensors practically created the MEMS industry. The manifold air pressure (MAP) sensor introduced by Ford in the mid seventies was the first micromechanical sensor in mass volumes. The accelerometers [17–19] were introduced to replace mechanical switches in airbag launchers, and later they enabled sophisticated chassis control systems.

Overview

The automotive industry already in the 1980s was characterized by advanced project management and quality control that included all the module manufacturers and subcontractors. The duration of product development projects was long and required a commitment for several years. The MEMS developers soon learned to apply these strict rules of project and quality management. The high requirements for reliability created long development projects with careful testing and verification phases. The automotive applications also created the requirements for the sensor electronics, such as voltage levels and system interfaces, and for the sensor module packaging. Robust system-on-package solutions were created. Operating temperatures and shock tolerance were extremely demanding. In addition, the frequency dependence of the sensors in chassis control and airbag launchers required very careful control of intrinsic gas damping and structural parameters. The motion sensors in automotive applications were soon divided into two categories: the high performance 3–5 g sensors for measurement of the motion of the chassis of the vehicle and the low cost 50–200 g sensors for the airbag launchers. This created the distinct paths for the development of the manufacturing solutions.

Leaps Towards a Generic Manufacturing Platform The two paradigms of micromachining develop almost in parallel. In the beginning the anisotropic etching of bulk silicon to form microstructures into the silicon wafer was a more efficient strategy [20]. The bulk micromachining benefits from the optimal mechanical characteristics of the single crystalline silicon. The doping of the silicon wafers and the optimization of their characteristics for chemical etching required specific development by the wafer manufacturers. Even the simplest MEMS devices require insulating layers. The successful practical method [18, 20] was to use a sandwich of silicon and borosilicate glass wafers. The wafers were bonded together by a so called anodic bonding process. However, the difference in the thermal expansion of the glass and silicon wafers was a problem causing strong temperature dependence and even warping or buckling of the micromechanical structures. The solution was to use only very thin insulating glass layers between silicon wafers [19] . Later the glass manufacturers, such as, Corning and Hoya, introduced glass wafers with thermal expansion characteristics that matched the silicon. Bulk micromachining enabled several different products [20]: pressure sensors, accelerometers, lab-on-chip devices, etc. As the bulk micromachining provided an

inherent wafer level packaging of the micromechanical structures, the very accurate control of the gas damping of accelerometers or the reference pressure of the absolute pressure sensors was feasible. The other paradigm was to grow a polysilicon thin film on top of a sacrificial silicon dioxide layer [21, 22]. The polysilicon film was anchored to the underlying silicon wafer and patterned to form the particular mechanical structure, e.g., the proof mass and the capacitor structures of an accelerometer. When the sacrificial silicon oxide layer was removed, the mechanical structure was released to move. The promise of the polysilicon surface micromachining was in the integration of mechanical structures with CMOS electronics. The approach was very successful in the development of accelerometers for the airbag application that was not as demanding on the acceleration resolution. The thickness of the polysilicon layer determines the proof mass of the accelerometer, and the intrinsic acceleration resolution is inversely proportional to the square root of the proof mass. Thus the smaller mass of the polysilicon structures became a limiting factor for the application that required high acceleration resolution. The control of the intrinsic stress of the polysilicon membranes was challenging and made the release of the micromechanical structures difficult. The deposition of a thick polysilicon layer was eventually developed [22]. After solving the challenge of wafer level encapsulation, the polysilicon surface micromachining provided smaller dimensions at lower cost, possibility for monolithic integration with CMOS devices and allowed more complex mechanical structures. In the mid 1990s two disruptive technologies appeared. The deep reactive ion etching (DRIE) of silicon using an inductively coupled plasma source, the Bosch process [23], made it possible to etch deep high aspect ratio trenches into silicon. Secondly, the development of silicon on insulator (SOI) wafers enabled high quality relatively thick monocrystalline silicon layers for micromechanical structures [24]. These technologies brought together the advantages of the bulk and surface micromachining. Through these innovative processes the MEMS technologies are becoming a true generic technology and manufacturing platform. The CMOS electronics integration with MEMS devices has been an intensive topic of research and development (see Review in [25]). Both pre- and postCMOS integration have been used. The key challenge has been the different pace in the development of MEMS and CMOS processes. In addition, the cost of the area on a CMOS wafer is getting increasingly more expensive; the CMOS components get smaller but the miniaturization of the MEMS devices is constrained by the sensor resolution and the necessary physical size. xvii

Overview Most of the manufacturers have adopted a system-inpackage strategy to overcome the integration challenge. Silicon on insulator (SOI) wafers has also opened a path towards embedding mechanical structures during the wafer manufacturing [26]. This can be a major change in the value chain of the MEMS manufacturing. The primary mechanical structures can be embedded into the SOI wafer by the wafer manufacturer. The device manufacturer can integrate the CMOS circuits on the wafer and finally release the mechanical structures by the DRIE process. The capabilities for large scale manufacturing and foundries capable of producing components in scalable volumes exist today.

Towards Every Pocket New Trends At the end of the 1990s the micromechanical pressure sensors and accelerometers existed in relatively large volumes for the automotive industry. The sensor elements, signal conditioning electronics and the packaging were developed according to the automotive system and environmental requirements. When consumer electronics and mobile phone manufacturers became interested in sensors and other MEMS devices suitable for their products, immediately they faced some challenges: The interface electronics with sufficiently low power consumption and low supply voltage level did not exist. Even though a large variety of packaging standards existed, the miniaturization had not addressed the critical requirement of thinness.

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Strict requirements for sensor performance and reliability increased the cost, and the testing and verification during both product development and production were very expensive procedures. Manufacturing volumes were not yet sufficient for consumer applications, and the lack of long-term commitment from the consumer industry did not support the investments to scale up the production capabilities. Industry dynamics of consumer products and mobile phones were disruptive to the operations of the sensor manufacturers: emphasizing faster ramp-ups, shorter commitments, speed of innovation, and extreme cost consciousness. Figure 2 illustrates the major shifts in the MEMS industry. The consumer products created a demand of lower cost MEMS devices with more relaxed requirements on performance. Especially, measurement electronics and packaging required rethinking. Figure 3 illustrates an example of the miniaturization of accelerometer modules for consumer products, for the game controllers and the mobile phones [37, 38]. In the early 2000s the ground was very fruitful for new innovation, and the global MEMS industry was very optimistic about these new application areas. Figure 4 shows a recent estimate of the growth of the MEMS component volumes [39]. Even the total unit volume of MEMS components is expected to nearly triple during the coming five years, the total annual growth of the revenue is clearly smaller with roughly 14% CAGR. Most of the growth is expected to come from the consumer applications of inertial sensors, silicon microphones and RF MEMS. In addition, the significant growth of microfluidics systems in medical applications, such as,

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Fig 2 l MEMS devices are moving towards consumer products and will enable the embedding of intelligence into human environments, i.e., the ambient intelligence.

xviii

Overview

Fig 3 l Miniaturization of packaged MEMS accelerometers by ST Microelectronics [38].

Fig 4 l The estimated MEMS market trend by the Yole Développement [39].

xix

Overview the drug delivery, may happen during the coming five years. The price erosion of the MEMS components can actually be even more dramatic due to the extreme cost competition in consumer products and mobile phones. Eventually, the new cost structure of MEMS devices will affect the automotive sensor market as well. What are these consumer applications that motivate the annual implementation of half a billion accelerometers, over one billion RF MEMS components and nearly two billion silicon microphones?

Consumer Products From Wristwatch to Wearable Electronics As the wristwatch is one of the miracles of miniaturization in the early 20th century, it is not surprising that sensors measuring the motional and physiological state of a person and the environmental conditions became a part of the wearable wrist devices. These wrist top computers became a driver for the integration of MEMS devices into consumer applications, such as sports, outdoors and wellness. The heart rate monitor, altimeter and the electrical compass with integrated accelerometer to compensate the inclination create benefits to any active persons exercising, skiing or trekking in the wilderness. Even this consumer segment is relatively limited, the applications defined the requirements of battery powered wearable devices: small package and very power efficient operation. The wrist devices created a starting point for wearable electronics applications [40, 41] where the sensors, processors and the user interface are embedded into wearable devices or clothes. The concepts can be used for following the daily activity of a person, measuring physiological parameters, detecting the physical context and location of a person or for observing the environmental conditions. Wearable electronics creates a new platform for digital services when the measured information is connected via Internet to communities of people that benefit from sharing their own data with other members [42]. The measured data from the individuals can be aggregated into meaningful shared information and knowledge. For example, sharing of sports, fitness or wellness data with a reference group enables a person to compare their own performance with the reference group. The measurement of human scale motion by accelerometers and angular rate sensors can be used to extract and recognize relatively complex patterns of human scale motion, such as, walking, running, climbing stairs. Figure 1.5 shows an example of a wearable pilot device developed by Nokia in 2003. The device was capable of detecting motion patterns and recording the daily

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Fig 5 l Nokia Fitness Monitor pilot product that measures and recognizes various motion patterns.

activity of a person. Even more complex motion patterns, e.g., playing golf or exercising yoga, can be recognized, recorded and used to help the person to learn, repeat and to correct these complex motion patterns. Professional training methods thus become possible for any serious amateur sportsman, and eventually, the sports and gaming will merge into various interesting combinations of physical and virtual realities.

Cameras and Projectors The data projectors and projection displays became a new driver of MEMS development after the invention of micromirror devices at the end of the 1980s. The DLP technology by Texas Instruments was ahead of its time in complexity when it was first introduced in 1993 [43, 44]. Based on digitally controllable aluminum micromirrors, the DLP chip enabled the miniaturization of video projectors when the personal computers became the primary tool for creating presentations. The miniaturization of data projectors has made them portable. The further miniaturization depends primarily on the power consumption and efficiency of the light source and the thermal management of the device. In addition to LED projectors also the laser sources, even RGB laser sources [45], are appearing. The micromirror based reflection devices will, however, meet a lot of competition from other technologies, such as, holographic displays that can be much more power efficient [46]. Image stabilization became an essential feature of SLR cameras and their optics. Miniaturized Quartz gyroscopes are used to measure the camera movement in order to control the mechanical actuators compensating the movement. The silicon angular rate sensors

Overview

are becoming an alternative for piezoelectric devices in image stabilization. Digital photography may open new applications for sensors. Automatic rotation of the image requires a mechanical sensor. Advanced image stabilization and more complex algorithms to improve the quality of still and video images are beneficial also for people who are not especially experienced in photography. However, many of these operations can be performed by pure image processing. The automatic generation of metadata for digital images [47, 48] will be primarily based on date, time and location. However, additional sensor information can be used for more complete sets of metadata; light condition, barometric pressure, humidity, temperature, direction, inclination are valuable information in the metadata for the further use and processing of images. Based on the metadata the sharing and searching of the images will become possible in a global scale in various Internet services [49].

Gaming The future of user interface and human machine interaction may already be visible in computer games and game controllers. Ideas for using sensors and haptics in the user interfaces of gaming devices has been developed by several research groups during the last ten years [50]. Figure 6 presents this kind of prototype device developed and published by Nokia Research Center in 2004. The detection of movements and gestures can be used to create an immersive gaming experience; a combination of a near-eye display, advanced audio functionality, gesture and body movement detection and a haptic feedback interface are ways to create virtual reality games or to augment the physical reality by virtual features [51]. Nintendo created a commercial breakthrough with their Bluetooth game control Wii Remote that extensively introduced the motion and gesture control to computer games. The game controller uses a 3D accelerometer for tracking the motion patterns. Game controllers together with an excellent set of games and a very good marketing campaign made the product a real success story in 2007. Nintendo Wii is a viable demonstration of multimodal user interface for augmented or virtual reality concepts and eventually also for remote communication.

Medical Applications of MEMS Devices The health care services are globally challenged by the increasing population in the developing countries and the ageing population in the developed countries, including China [52, 53]. Other global phenomena, such as, obesity, require new solutions and rethinking

Fig 6 l 3D accelerometer and 2D angular rate sensor-based game controllers created by Nokia Research Center in 2004.

of the preventive health care strategy. Furthermore, the Internet connectivity enables the access to personal health information and remote services. The health care services are moving closer to the consumers. Networked professionals are capable of providing more demanding treatments. The health data of an individual can be managed more efficiently and accessed by an authorized institution or a health care professional. The personal health data can be managed in a distributed manner but also accessed by the individual anywhere, anytime. Based on this more easily accessible health data, the health care services can be tailored to fit to the medical history of the patient. Furthermore, the medical treatments can be moved to more convenient and less costly settings. A smaller point-of-care can be responsible for diagnostics and treatments that require an extremely sophisticated environment today. In practice, this means remote health care services in developed countries; for example, capabilities to provide a service for chronic patients or elderly persons at home. In the developing countries, the improvement of health care in the rural areas can be based on similar solutions. Nurses and doctors in rural, remote locations can benefit from the connectivity to large hospitals and their information and diagnostics capabilities. The key driver for this kind of change is the need to find very low cost solutions for health care using new diagnostic tools, remote connectivity and capabilities to efficiently manage the personal health data. Miniaturized diagnostics based on MEMS devices will potentially influence both the future diagnostics and the treatments. Today the most important MEMS devices in medical applications are the microfluidics systems, pressure

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Overview sensors for blood pressure monitoring and the accelerometers for cardiac pacemakers. The largest potential for new applications and business growth is related to microfluidics used in diagnostics and drug delivery. The micromachined structures have made it possible to handle very small samples of liquids in a reliable way. Furthermore, the MEMS miniaturization creates a possibility to use simultaneous parallel measurements in the same system. These highly integrated lab-on-chip solutions [54, 55] change the nature of the in vitro diagnostic devices. Multichannel integrated biosensors, advanced sample handling and new sensitive transducers will enable point-of-care devices that are capable of, e.g., cancer diagnostics or any other analysis of the genomes [56]. The continuous monitoring of physiological parameters of a patient opens opportunities for more precise diagnostics. In addition to monitoring of heart rate, ECG and blood figures the possibility to monitor and register the daily activity and context of the patient during these measurements gives more information that may have a correlation to the physiological data and that can help in the diagnostics. The continuous monitoring and the possible remote connectivity will open a new segment of wearable health care products. The MEMS devices are already used in the in vivo devices: the cardiac pacemakers use accelerometers to detect the activity of the patient in controlling the pacemaker rhythm [57, 58]. This application is a marvelous example of the reliability of the MEMS sensors. The next very potential application will be the implantable MEMS drug delivery systems [59]. The possibilities to integrate timing, sensors and microfluidics actuators into an implantable device will revolutionize the treatment of several chronic diseases, such as, diabetes.

Mobile Phones and Mobile Multimedia Computers The mobile phones have converted to smart phones or mobile multimedia computers. These mobile devices are continuously gaining more dominance. These mobile multimedia devices outnumber personal computers by a factor of five. In some growth markets, such as China and India, the ratio is even higher-close to 10:1. This means concretely over three billion mobile subscribers and over one billion wireless broadband subscribers. By 2010 it is expected that up to 90% of the global population will have mobile coverage. This creates an immense platform to build digital services that are based on remote connectivity. The mobile phones have become digital cameras, music players, internet browsers, mobile TVs in addition to being communication devices that people carry with them always and everywhere. The mobile phones integrate a lot of functionality from consumer appliances and personal computers into a small integrated device. Figure 7 presents potential new arising trends in the mobile communication industry. Currently, the industry is shifting towards Internet-based mobile services. This is a clear consequence of new Internet-based business models and the ongoing convergence of mobile communication, information technologies and consumer electronics. The studies and trials of MEMS components in mobile devices started at the end of the 1990s in the laboratories of both the mobile devices and MEMS component manufacturers. The MEMS provided possible solutions for RF integration, local oscillators, sensors, microphones, displays, power solutions, etc. The most potential applications of

Fig 7 l Mobile industry in shift towards services and ambient intelligence.

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Overview

MEMS in mobile devices are related to the RF implementation, sensors and the audio functionality. On the other hand, practically all the consumer electronics functionalities can be integrated into mobile multimedia computers or at least used in their accessories. The rapidly growing volumes of mobile phones created expectations of large volumes of MEMS devices. However, after roughly ten years of development the impact is still rather modest. Why?

RF MEMS The radio and the antenna implementations in mobile devices are continuously getting more complex. The number of supported radio standards has increased, making the design of the radio chip sets and the antenna solutions more challenging. The promise of MEMS devices has been related to tunable RF components that reduce the number of discrete elements in the radio front end. MEMS RF switches, tunable MEMS capacitors and MEMS resonator-based devices, such as, delay lines and filters, have been the focus of extensive development both in the university and industry laboratories [27–30]. The development of reliable RF MEMS devices has, however, taken much longer than expected in the beginning. There are some fundamental dimensional constraints that make the integration of RF MEMS components to mobile devices challenging: The conductivity of even highly doped bulk silicon or polysilicon is not sufficient for a high enough quality factor for capacitors, inductors or switches in the frequency range of 1–5 GHz.Thus the use of metal film based micromechanical structures is required, leading to several other challenges. The temperature dependence in devices that consist of multiple materials is very difficult to control and reduce. Even practical solutions have been found [35,36]. Low cost system-in-package integration of RF ICs, passive components and MEMS devices is challenging. Voltage levels required to actuate RF MEMS devices are typically much higher than the supply voltage levels of modern ICs. Oscillators based on MEMS resonators at 10 MHz frequency range with low losses (Q~200000) and very good phase noise (−155dBm/ Hz ) have been developed [31, 32]. However, the thermal stability of the devices is still a challenge. MEMS resonators are limited to roughly 10 MHz frequency. At higher frequencies, e.g., in 1–5 GHz range, the fabrication tolerance of narrow electrode gaps, very high control voltages and the lower Q values of resonators limit the development of practical devices. Recently, the development of piezoelectric actuators for MEMS resonators has improved the efficiency of electrical coupling [33,34]. n

n

n

The complexity of the value chain has also made the development slower: the MEMS devices, RF ICs and RF modules have been manufactured in many cases by different manufacturers, according to the specifications of the system integrators. Both technical and commercial challenges in creating integrated solutions have existed. Recent development is clearly bringing the technologies together. The radio communication is gradually developing towards concepts that are generally known as the cognitive radio [60, 61]. The concept is based on the capability of the radio system to sense the available radio resources and the context of the user, assess the situation, dynamically plan and take the actions to allocate radio resources, and finally learn about them. The requirements for the radio front-end implementation are very demanding: the radio spectrum analysis over a broad frequency range and the fast adaptation to the optimal radio band. The power efficient tunable antennas, filters and impedance matching circuits are the fundamental enablers of the future intelligent radios. The technology for the cognitive radio does not exist today; the RF MEMS components may enable some of these required capabilities.

Sensors and Actuators The sensor functionality is clearly becoming a part of consumer products. However, there still exists a challenge in integrating new functionality in devices that are sold in huge volumes. The products are extremely cost sensitive, and the functionality needs to be meaningful for most of the end users. What are these new functions enabled by MEMS sensors? Furthermore, the mobile phone market is driven globally by mobile network operators. What are the benefits and the revenue opportunities for the telecommunication operators of the sensor functionality? So far applications that would motivate a very large scale integration of sensors into mobile devices have simply not existed. The additional cost related to the sensors

n

n

n

Fig 8 l Tunable metal film capacitor design by Nokia Research Center and fabricated by Philips Research.

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Overview and their application software has slowed down the development. The number of possible sensor applications in mobile devices is huge. Table 1 summarizes some possible mobile device applications and their requirements for the sensor system. Even if it is possible to list a large number of use cases and applications, the key challenge is how to make the functionality so generic that it enables this multitude of applications for various consumers. Recently, Nokia has introduced three axis accelerometers in the high end mobile multimedia computers, such as, the models N82 and N95. The application programming interface (API) to the sensors has been published for third parties. Nokia has also produced a multitude of beta applications for fitness and sports [62]. The three axis accelerometer-based motion detection and the GPS based location have been the key data sources. Apple iPhone, LG, Nokia, and Samsung have also used accelerometers for controlling the user interface. Recently, Apple’s novel Appstore business model has enabled development of various accelerometer applications for mobile devices by the software development community. The three axis accelerometer is the key sensor for mobile devices. It enables several possible functions: hard disk protection, gesture recognition, user interface control, activity monitoring, etc. The functionality is generic, and the motion data can create a basis for several applications. The awareness of the context means to be able to recognise the status of the environment, the user, the device itself and of the network. The context awareness is the generic functionality that enables the future intelligent sensing, computing and communication devices. The context awareness is based on merging information and measurements from several different sources. From the embedded sensors it is possible to get, e.g., the activity, the

location, the physiological state of the user and the environmental conditions, such as, temperature, illumination and humidity. Based on this primary sensor data the higher level abstraction of the context of the user can be created. Based on the context information it is possible to build the applications for sports, gaming, gesture-based device control, user interface control and adaptation, automatic generation of image metadata, more sophisticated imaging algorithms, etc. Various sensor applications can be created using a generic software library that consists of routines to compute the various abstraction levels of context.

Silicon Microphone Even the introduction of silicon MEMS microphones [63, 64] into mobile devices has happened much slower than anticipated, the silicon MEMS microphones have clear benefits in comparison to, e.g., electret condenser microphones. The silicon microphones are smaller. They are surface mountable through a standard reflow assembly process. It is easier to protect them against EM and RF interferences. They own better linearity and smaller device-to-device variances in their design parameters. Furthermore, their dependence on temperature and humidity is lower. These benefits are clear in the mobile device applications. However, replacement of an existing technology always takes a long time. The existing technologies have their cost advantages, operational supplier chains, the assembly of existing components has been verified in large volumes, and typically their characteristics fulfill most of the application requirements. In order to be successful any new technology needs to bring some unique advantage that makes a difference to the end user of the product.

Table 1 Sensors and sensor applications in mobile devices

Sensor

Sports

Gaming

Gestures

UI

Metadata

Imaging

Accelerometer (3 axis)

M

M

M

M

I

N

Angular rate sensor

I

N

I

I

Magnetometer

M

N

N

GPS

I

N

M

Barometric pressure

M

Temperature

I

Humidity

N

(M  Must. I  Important. N  Nice to have.)

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M

N N

I N

N

Overview

In the case of silicon MEMS microphones the added value became primarily not from the tangible added value to the end user in the first place. The benefits were related to the manufacturing solutions, and the possibility to use the reflow process simpler testing procedures in production easier implementation into device mechanics The capability to integrate the silicon MEMS microphone more easily with the CMOS electronics makes a real difference. A compact digital microphone module and even a single chip implementation are recently shown to be feasible by Akustica and other manufacturers. Even the cost of such a highly integrated device can be a challenge in consumer electronics, the integrated digital microphones enable multimicrophone arrays that can be used for spacial filtering and directional control. The active noise cancellation algorithms are based on multiple microphones. The digital microphones can be freely placed far from each other, owing to the digital output signals that are resistant to interferences. As the natural language is becoming a more important way to interact with digital devices, applications and services, these novel features and intelligences in the overall audio system are drivers for high quality MEMS microphones with integrated mixed signal electronics.

n

n n

Towards Modular Architectures in Consumer Products The requirements for the MEMS-based technologies in the consumer electronics can be contradictory. There is a clear

tendency towards modularity; the new functionality should be easy to implement in the devices. On the other hand, the large volumes create severe cost constraints. MEMS products with different levels of integration and complexity are needed, e.g., sensors varying from simple indicators to integrated complex intelligent wireless sensors. Figure 9a presents a possible configuration of an intelligent sensor module for a consumer product. The typical features of such an implementation [65] are that the sensors and their primary signal conditioning circuitry are integrated into the same module. However, the system of Fig. 9 has several other interesting features. An integrated low power DSP core and a specific hardware accelerator are used for sensor signal processing. The feedback to the actuators controlled by the sensor signals is computed locally to minimise the control loop delay. The efficient power management circuitry is used to control the various sleep and active states of the device. The regulation of MEMS control voltages and the system clock are integrated into the system. Optionally, a general purpose signal processor can be added for more complex computational tasks, such as, the asynchronous communication with the host processor. The driver for such a high level of integration is the autonomous, energy efficient sensing and signal processing. In many cases, continuous measurements are needed. The modular implementation and careful design of the internal power management of the sensor module are essential. Various wake-up mechanisms, e.g., based on a defined signal threshold or an interrupt from the host processor, can be used. Only the minimal necessary functionality of the system is powered at any time.

Fig 9 l Architecture of an autonomous smart sensor module. (a) Sensor module that can be integrated via asynchronous digital communication interface. (b) Wireless autonomous device with its own energy sources and storage.

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Overview The high signal abstraction level in the system interface of the module enables easier integration to the end product. The processing and recording of sensor signals and the recognition of the motion patterns or the context can be performed by the energy optimized sensor module. These high abstraction states or their recorded time sequences can be requested by the host processor applications. In general, this kind of service oriented architectures (SOAs) are becoming more common in the distributed information technologies [66] but can also be applied to embedded devices [67]. The modular implementation opens a new opportunity for MEMS devices. The low cost and miniaturized integration of a system clock into the module, as illustrated in Fig. 9, is a challenge using a separate Quartz crystal. The MEMS reference oscillators based on silicon resonators are a very potential solution. Currently, the quality of the MEMS-based reference oscillators in the 10 MHz range are becoming feasible. The same type of modular architecture can be applied to other electronics modules: mass storage, projection display, radio modem, etc. The modular implementation will open new possibilities for adding functionality to consumer products. There are several initiatives to define the low power scalable digital interfaces, such as, the USB and the MIPI consortia [68, 69].

Ubiquitous Sensing, Computing and Communication Merged Physical and Digital Worlds The capability to add an index and a digital identity to smaller physical items, such as sales packages and consumer goods, will enable more efficient logistics and quality control from manufacturers to retailers. These commercial solutions will create an information platform that also enables the consumers to get deeper knowledge of their purchased goods. We are talking about the first steps towards the Internet of Things that is a concept of connecting different physical objects to the information networks [70]. These concepts extend towards possibilities to have an Internet address or an URL embedded in the physical objects and thus a possibility to link them into the information networks. The next possible phase of this development has many names [71–74]: Ambient Intelligence, Pervasive Computing, Ubiquitous Computing (see Fig. 7). The networked devices embedded in our physical environment provide sensing, computing and communication services that can be accessed locally. When this localized information is connected to the global information

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networks that are capable of data aggregation, we will live in a responsive environment that knows our preference and adapts to serve our particular needs. The microsystems of sensors, processors and radios are essential enablers of these intelligent environments. The safety and comfort have been the key drivers of automotive sensor applications. The adaptive and intelligent user interface is the driver of consumer applications. The key drivers for the Internet of Things and the Ambient Intelligence will be related to the next big challenges of human societies. The challenge of energy production, the scarce natural resources and the ageing global population are creating a need to optimize the human economical processes. The increasing urban population creates more severe issues with the security and safety of persons and their properties. The environmental challenges of pollution and changes in natural ecosystems will require increasing human care.

Wireless Sensing and Sensor Networks The wireless sensor networks [75–78] are enablers for the Internet of Things and the future ambient intelligence. The sensor networks can be used for optimizing the logistics and transport; the possibilities to localize and to measure the condition of transported goods can be used to optimize logistics cost and energy consumption. The safety and security can be increased by more efficient sensor networks. The wireless sensor networks will enable more precise measurements and denser grids for monitoring of our chemical environment and the atmospheric, hydrological and seismic processes. The building automation and the monitoring of the structural integrity will improve the energy efficiency, the safety of the urban infrastructures and the comfort of living. The solutions for assisted living of elderly or handicapped people can be based on sensor networks embedded in their home environment. The intelligence and computing in a wireless sensor network can be distributed in various ways [78, 79]. In an optimised wireless sensor network, some level of data aggregation is typically calculated in each node in order to reduce the energy consumption related to the communication. In addition, the distance of the sensor nodes is optimized with respect to the necessary transmission power. The very lower power operation of a sensor network requires some complexity in the communication protocols and thus signal processing capabilities. A multitude of possible wireless protocols have been developed for sensors and sensor networks. Table 2 summarizes the key figures of merit of the most important initiatives of wireless sensor radios, the Bluetooth, Zigbee and the Near Field Communication

Overview

Table 2 Comparison of the most important existing sensor radios

Figure of merit

Bluetooth [82]

Bluetooth LE [83]

Zigbee [84]

NFC (RFID) [85]

Range

10 m

10 m

50 m

5 cm

Power

Ref index  1

0.1-0.5

0.6

4 reader/0 tag

Data rate

1 Mbps

1 Mbps

0.25 Mbps

0.4 Mbps

Pairing speed

Slow

Fast

Fast

Inherent

Security

Authentication

Access approval

n/a

n/a

Silicon size

Medium

Tiny

Small

Very small

Typ use case

Accessories

Sensors

Automation

Identification

(NFC) standards. These standards have not been developed and optimized for actual multi-hop sensor network applications. The basic concept of these radios is related to connecting various sensors into a host device, such as, a mobile phone, that can be a gateway into the information networks [80, 81]. A wireless sensor consists typically of a radio, a microprocessor, a small memory, and an energy source in one single robust package. Figure 1.9b presents a possible architecture of wireless sensor that has specific requirements related to the radio communication and autonomous operation: extremely low power consumption enabling energy autonomy, capability to wake-up the system by an external sensor signal or an external radio (i.e., a wake-up radio [86]), and an efficient control of the measurement and signal processing duty cycles. Furthermore, the wireless sensor nodes need to be easy to deploy, self-configuring, extremely robust and fault tolerant. The challenges in developing the energy solutions for the ambient intelligent systems requires new thinking and new technologies. Today business models are still missing, and various societal issues, such as, privacy and security in these novel networks, need to be solved before any broad deployment.

Mobile Phone as a Sensor As discussed before, soon 90% of the global human population will have mobile coverage. In some years these devices have become also sensors and computers that are inherently connected to the global information network. The mobile devices can have several roles in the context of ambient intelligence and sensor networks. The mobile device is already today a user interface towards the global Internet based services and digital

content, and the user interfaces of the mobile devices will have improved capabilities for this multimodal information. Secondly, based on the efficient radio solutions (see Table 2) the mobile devices are also becoming a user interface to access the sensors and other devices in the local environments. Figure 10 presents the paradigm of a mobile device as a trusted personal user interface towards the local and global information. However, the most important new capability is to use the mobile device as a gateway between the local networked environment and the global information networks. The mobile devices all over the world can simultaneously collect information and feed it into computing services that can aggregate the information into meaningful form for the end users. Powerful data mining and search algorithms [87] can be used to extract local information, local history and predictions. Possible examples are pollution and traffic monitoring where the information of individual devices can be aggregated into maps and future projections that are meaningful for the people joining to these services. The mobile solutions for remote health care and continuous monitoring of patients are another clear example of this kind of application. The privacy of the individuals connected to these services is an essential feature of the network operation and the infrastructure. The mobile device itself can be a sensor node of a sensor network. The multiple integrated sensors and their context and location awareness create as such the information that is meaningful to be aggregated into knowledge. The information that can be retrieved from the behavior and the preferences of the consumers is always valuable for service providers. The questions are, with whom the consumers are willing to share their preferences and what do they win by doing so? And what will be the future business models?

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Overview

Fig 10 l Mobile phone as a gateway between local intelligent environment and global digital services and content.

Future of MEMS Technologies Is Silicon Enough? Silicon is a nearly perfect mechanical material and enables the micromachining of very precise structures. There are also some limitations related to the cost and the ultimate material properties. In microfluidics and optical applications, e.g., in diffractive optics, the use of polymer substrates and structures is much more inexpensive in large volumes. The sophisticated technologies for replicating the microstructures into polymer surfaces have been developed [88–91]. The basic idea of the process is to fabricate the primary mechanical structure into the surface of the silicon wafer, deposit a metal film on top of the silicon structure and electroplate a thick metal layer (for example, a nickel layer). When the thick metal layer is removed from the surface of the silicon wafer, we have a mold to replicate the structure on a polymer surface, for example, using injection molding or hot embossing. In RF applications the conductivity of even the very highly doped silicon or polysilicon is not sufficient for a high enough quality factor for tunable RF capacitors, switches or inductors. The use of metal films has been a way to increase performance of the micromechanical components. The use of free standing metal thin films for tunable or switchable structures is shown to be possible. The behavior of metal thin films differs from bulk metals; for example, inelastic deformations are smaller [92, 93]. The novel nanomaterials will create a possible impact in the future MEMS. The use of carbon nanotubes as piezoelectric transducers has been demonstrated with good results [94–99]. The use of bottom up grown sili-

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con nanowires for resonators has been studied [100102]. Nanotechnologies will create new material solutions for MEMS, and possibly some new nanoscale mechanical structures, so called NEMS structures, will become commercially feasible some day. Figure 11 illustrates a concept of a future consumer device based on polymer electronics [103], stretchable electronics [104] and new functional surface materials [105, 106]. The key attributes of such a future device are transformability, compliancy in terms of controllable flexibility and stretchability, extreme thinness and transparency. The integration of functionality will be based on reel-to-real assembly [107] and printing of interconnects [16] together with many active and passive printed components [108, 109]. This kind of device is still very far in the future but the first steps towards the novel integration solutions will be taken within the coming years based on printed electronics. What are the implications to the MEMS module packaging?

Platform for Nanoscience and Nanotechnologies The MEMS has also created capabilities for the probing and manipulation of matter in the nanoscale. The atomic force microscopy based on micromechanical cantilevers and tips is one of the key methods for scanning, imaging and measuring nanoscale objects. The micromechanical probes can be used for accessing nanoscale systems and their dynamical properties. The micromechanical systems will play a significant role in developing the nanoscale electronics, functional nanomaterials and surface structures.

Overview

Conclusions

Fig 11 l A transformable and wearable device, based on stretchable electronics. Industrial design by Jaakko Saunamäki, Nokia [113].

The explosion of digital content in terms of images, music and videos creates an increasing need for high density, low power and intelligent mass storage systems. The magnetic hard disks will not scale to the memory densities that would fulfill these requirements. The micromechanical cantilever array has already been developed for nanoscale mass storage concept. Several companies, such as, IBM, HP, ST Microelectronics and Seagate, have been working for a concept called probe storage [110, 111]. The concept is based on reading, writing and erasing information on the surface of a polymer film, metal film or a magnetic film using a microelectromechanical cantilever and a micromachined tip. The IBM Millipede [112] has a capability to read, write and erase dots on the surface of the polymer film with the pit resolution of 20 nm. The micromachined system is relatively complex with the array of cantilevers and the actuators to move the plate hosting the polymer film. However, the manufacturing of the MEMS system is feasible today; the challenge of the probe memory technologies is the stability of the nanostructures used for the memory.

After over 30 years of development the silicon micromechanics has become a major established industry of its own. The applications in ink jet printer nozzles and automotive sensors had the sufficient momentum to develop technologies that are now applicable to consumer products in large volumes. The requirements of the consumer products have pushed the manufacturers to invent solutions for extreme miniaturization of MEMS devices and their packages. Very low power and low voltage sensor electronics exist as well. The driver for automotive sensors was the safety and comfort of the vehicles. The consumer electronics created sensor applications related to the more sophisticated interaction between the human and the different intelligent devices. The replacement of existing technologies with purely technical arguments never creates an immediate market pull. The integration of new functionality in cost optimized consumer products depends on the real value and novelty to the end user. Understanding of the complete business case and the added value related to all the stakeholders is essential for MEMS component manufacturers. The business models of the consumer electronics are changing as the strong bundling of devices with services and content is becoming a necessity. The new business models will require increasingly fast response time to bring new products to the market. Modular solutions to implement new functionality, such as, tunable RF components for the cognitive radio, low cost integrated reference oscillators for modular electronics, three axis accelerometers for motion pattern recognition and digital silicon microphones for advanced audio systems, are surely needed. The ramping up and down of the production will need to happen very fast because the volumes of particular end products are going to be very difficult to estimate. The global challenges–scarce energy and other natural resources, environmental and heath care challenges, growing urban population–will require more efficient sustainable economics and new ways to guarantee the safety, security and well being of people globally. Sensor networks and ambient intelligence will be enablers of our future sustainable way of living, and the microelectromechanical systems together with arising nanotechnologies are important to make this global implementation of sensing, computing and communication possible.

Acknowledgements We would like to acknowledge the numerous colleagues at Nokia Research Center, especially, Vladimir Ermolov, Kari Hjelt, Antti Lappeteläinen, Jukka Salminen and Henry Tirri, with whom I have worked

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Overview towards microsystems, sensors and their applications in the mobile industry. In addition, I want to express my gratitude to Heikki Kuisma, Markku Tilli and Benedetto Vigna for sharing their deep insights of the MEMS industry.

This chapter is not meant to be a thorough review. We are aware of the very extensive research in various MEMS technologies and their applications. Here we are referring only to some of the key breakthroughs in the ﬁeld.

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52. C.M. Christensen, S.D. Anthony, E. A. Roth, See What’s Next, Harward Business School Press, Boston, 2004. 53. S.E. Frew, S.M. Sammut, A.F. Shore, J.K. Ramjist, S. Al-Bader, R. Rezaie, A.S. Daar, P.A. Singer, Chinese health biotech and the billion-patient market, Nature Biotech. 26 (2008) 37–53. 54. J. Berthier, P. Silberzan, Microfluidics for Biotechnology (Microelectromechanical Systems), Artech House, 2005. 55. O. Geschke, H. Klank, P. Telleman (Eds.), Microsystem Engineering of Lab-on-a-Chip Devices, Wiley-VCH, 2008. 56. J. Kaiser, A Plan to Capture Human Diversity in 1000 Genomes, Science 319 (2008) 395. 57. D.W. Bacharach, et al., Activity-Base Pacing: Comparison of a Device Using an Accelerometer Versus a Piezoelectric Crystal, PACE 15, 1992, pp. 188-196. 58. J.G. Webster (Ed.), Design of Cardiac Pacemakers, IEEE Press, New York, 1995. 59. N.-C. Tsai, C.-Y. Sue, Review of MEMS-based drug delivery and dosing systems, Sensors and Actuators A134 (2007) 555–564. 60. S. Haykin, Cognitive radio: Brain-Empowered Wireless Communications, IEEE on SAC 23 (2005) 201–220. 61. Joseph Mitola III, Cognitive Radio Architecture-The Engineering Foundations of Radio XML, Wiley, 2006. 62. research.nokia.com. 63. P.R. Scheeper, A.G.H. van der Donk, W. Olthuis, P. Bergveld, A review of silicon microphones, Sensors and Actuators A44 (1994) 1–11. 64. G.M. Sessler, Silicon microphones, J. Audio Eng. Soc. 44 (1996) 16–22. 65. T. Ahola, P. Korpinen, J. Rakkola, T. Rämö, J. Salminen, J. Savolainen, Wearable FPGA Based Wireless Sensor Platform, in: Proceedings of the 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society EMBS, 2007, pp. 2288–2291. 66. E. Newcomer, G. Lomow, Understanding SOA with Web Services, Addison Wesley, 2005. 67. www.notaworld.org. 68. www.usb.org. 69. www.mipi.org. 70. ITU Internet Reports 2005: The Internet of Things, 7th edition, 2005.

71. J.M. Kahn, R.H. Katz, K.S.J. Pister, Next Century Challenges: Mobile Networking for “Smart Dust”, in: Proceedings of the 5th annual ACM/ IEEE international conference on mobile computing and networking, 1999, pp. 271–278. 72. C.E. Perkins, Ad hoc networking, Addison-Wesley, 2001. 73. IEEE Personal Communications 8, Special Issue, An Overview of Pervasive Computing, August 2001. 74. J. Weatherall, A. Jones, Ubiquitous Networks and Their Applications, IEEE Wireless Comm. 9 (2002) 18–29. 75. I.F. Akyildiz, W. Su, Y. Sankarasubramaniam, E. Cayirci, A Survey on Sensor Networks, IEEE Communications Magazine 40 (August 2002) 102–114. 76. I.F. Akyildiz, T. Melodia, K.R. Chowdury, Wireless Multimedia Sensor Networks: A Survey, IEEE Wireless Communications 14 (2007) 32–39. 77. K. Martinez, J.K. Hart, R. Ong, Sensor Network Applications, Computer 37 (2004) 50–56. 78. F. Zhao, L.J. Guibas, Wireless Sensor Networks: An Information Processing Approach, Elsevier, 2004. 79. C. Intanagonwiwat, R. Govindan, D. Estrin, J. Heidemann, F. Silva, Directed Diffusion for Wireless Sensor Networking, IEEE/ACM Trans. Networking 11 (2003) 2–16. 80. C.S. Raghavendra, K.M. Sivalingam, T. Znati (Eds.), Wireless Sensor Networks, Springer, 2006. 81. H. Karl, A. Willig, Protocols and Architectures for Wireless Sensor Networks, Wiley-Interscience, 2007. 82. www.bluetooth.com/bluetooth/. 83. www.bluetooth.com/Bluetooth/ Products/Low_Energy.htm. 84. www.zigbee.org. 85. www.nfc-forum.org. 86. L. Gu, J. Stankovic, Radio-triggered wake-up for wireless sensor networks, Real-Time Systems 29 (2005) 157–182. 87. B. Liu, Web Data Mining: Exploring Hyperlinks, Contents, and Usage Data (Data-Centric Systems and Applications), Springer, 2008. 88. E.W. Becker, W. Ehrfeld, D. Munchmeyer, H. Betz, A. Heuberger, S. Bongratz, W. Glashauser, H.J. Michel, V.R. Siemens, Production of Separation Nozzle Systems for Uranium Enrichment by a Combination of X-Ray Lithography and Galvanoplastics, Naturwissenschaften 69, 1982, pp. 520–523.

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Chapter One

1

Properties of Silicon

Markku Tilli and Atte Haapalinna Okmetic Oyj, Vantaa, Finland

1.1 Properties of Silicon

Silicon is an abundant element found in the Earth’s crust in various compounds. Semiconductor and MEMS applications use more than 20000 tons/year (2008) of high-purity silicon. Today most of the silicon used is either N- or P-type, doped with antimony, arsenic, phosphorus (N-type) or boron (P-type); the dopant concentration ranges between 1013 and 1020 dopant atoms/cm3 Si. Intrinsic (no intentional doping) or very slightly doped high resistivity silicon above 1kΩcm is used in small amounts. Statistics pertaining to silicon can be found, for example, in the US Geological Survey 2006 Minerals Yearbook [1]. Quartz, or silicon dioxide, is the most common start ing raw material for puriﬁed silicon for semiconductor and sensor applications, and the Siemens process is the most commonly used in semiconductor-grade silicon pro duction. In the classical Siemens process, metallurgicalgrade silicon, made ﬁrst in an electric arc furnace by reducing quartz with coke, is turned to silicon-hydrogen chloride compounds in ﬂuidized bed reactors and those compounds are converted to TCS (trichlorosilane, or SiHCl3). TCS is puriﬁed by distillation, during which concentrations of impurity compounds having either a lower or higher temperature of volatility than TCS (38.4°C) are reduced. Puriﬁed TCS is fed together with hydrogen into a reactor. In the reactor TCS is decom posing onto hot silicon ﬁlaments forming a pure polysilicon rod. This rod is then used as a raw material for crystal growth, either in rod form or in crushed pieces. There are alternative, newer techniques for purifying silicon; one variant is similar to the Siemens process

but uses silane (SiH4) as a precursor. In some processes, heated silicon ﬁlaments are replaced by silicon particles ﬂoating in ﬂuidized bed reactors; these processes yield granular polysilicon. The result of the puriﬁcation process is high-purity silicon containing very small amounts of foreign dis solved atoms. If the single crystals are manufactured by a Czochralski (CZ) technique, which is most commonly used (�� 90% of the crystals), the impurity level increases, as the growth is made from a quartz cruci ble having some impurities. The result is, however, still acceptable. Typically, most of the contamination of the silicon takes place during actual device manufacturing. Of impurities, metals are generally harmful, with rare exceptions, and their concentration should be as low as possible, typically �� 1012 at/cm3 Si. Oxygen coming from the CZ-crystal growth step as an impurity has a dual role: it has beneﬁcial effects (strengthening of the silicon lattice at high temperatures, gettering effect in semiconductor use) but also has detrimental effects (donor formation, defect generation). Nitrogen is a sec ond example of an impurity, and it can be used in small quantities to enhance silicon properties, especially in IC applications. The current high demand for low-cost solar-grade sili con encourages the exploitation of alternative sources and new puriﬁcation techniques. Currently these meth ods are not able to produce semiconductor-grade silicon pure enough for MEMS applications, although in solar applications these new methods already show prom ising results. Woditsh and Koch [2] and Istratov et al. [3] list some of the available solar silicon puriﬁcation techniques. 3

PA R T I

Silicon as MEMS Material

Silicon is an ideal material for various MEMS appli cations. Silicon is a semiconductor whose resistivity can be adjusted by doping from sub-mΩcm to several kΩcm; it is quite inert in a normal environment, hard, transparent in an infrared regime, and elastic at room temperature with no plastic deformation and with high fracture strength. Finally, a protective stable silicon dioxide can be grown. Silicon crystal has anisotropic properties—mechanical, chemical and electrical—which can be exploited in MEMS component designs. Very large silicon single crystals in various crystal orientations can be made with relative ease. These unique combina tions of properties have placed silicon as the number 1 material in MEMS manufacturing, although it took almost 30 years after the invention of the silicon tran sistor until the potential of silicon as a micromechanical material was widely realized; see Petersen [4]. Table 1.1 Table 1.1 Basic parameters of silicon Atomic number of Si

14

Atomic mass of Si

28 (92.23%) 29 (4.67%), 30 (3.1%)

Crystal structure

diamond

Lattice constant

0.5431

nm

Si atoms

5*1022

atoms*cm�3

Melting point

1687

K

Speciﬁc density

2.329

g*cm�3 at 298 K

Speciﬁc density (liquid)

2.57

g*cm�3

Thermal conductivity

149

W*m�1K�1

Coefﬁcient of thermal expansion 2.56*10�6

m�1K�1 (at 298K)

Speciﬁc heat capacity

19.79 0.705

J*mol�1K�1 J*g�1K�1

Young’s modulus

150

GPa

Speed of sound

8433

m*s�1

Hardness

7

Mohs

Hardness

850

kg*mm�2 (Knoop hardness)

Volumetric compression coefﬁcient

1.02*10�8

kPa�1

Index of refraction (varies with temperature and λ)

3.54

λ 1.1 μm, RT

3.48

4

λ 2 μm, RT

lists some basic parameters of silicon. Some of the para meters depend on doping level as well as temperature and have an effect on MEMS device function. A more comprehensive treatise on basic silicon properties can be found, for instance, in a handbook edited by Hull [5] or in Landolt-Börnstein Group III: Condensed Matter volumes [6].

1.1.1 Crystallography of Silicon Silicon crystallizes into a diamond cubic crystal struc ture (Figure 1.1) in which the atoms are covalently bonded. Other elements, like germanium, in periodic table group IV typically have the same structure. The unit cell contains 8 atoms, and the atoms follow a face centered cubic (fcc) Bravais lattice. In each fcc lattice point there are 2 atoms (motif): one in the lattice point and the second displaced by ¼ of the unit cell length towards the [111] direction. The unit cell length at room temperature is 0.5431 nm. Actually, this value is one of the most precisely known among elements, since silicon crystal can be grown almost perfectly, and the lattice parameter can be measured precisely accord ing to Martin et al. [7] with an uncertainty of about 3…6*10�8. Thus, silicon is a good candidate for vari ous references, for instance, in determining Avogadro’s constant. The density of packing of silicon in this lattice is 34%. The packing density is quite loose compared with that of fcc lattices (some metals, like copper, have this structure), whose packing density is 74%, and that of a body centered cubic structure (for instance, pure iron at room temperature), whose packing density is 68%. The largest empty place in the diamond cubic lat tice is the octahedral hole, which can occupy an atom

Fig 1.1 ● The silicon lattice unit cell. Gray silicon atoms in the lattice are in the fcc position, and light color atoms are shifted from fcc positions toward the [111] direction by ¼ unit cell length.

Properties of Silicon

41% of the size of the host atom. Atoms dissolved in the lattice in empty places are called interstitial atoms; the solubility is called interstitial solubility. The most typical interstitially dissolved (impurity) atom is oxy gen. The maximum oxygen equilibrium content at crys tal growing in the interstitial state can in practice be almost up to 20 ppm, which corresponds to up to 1018 atoms/cm3 Si. Carbon is the second most common interstitial impurity in silicon; in practice the concen tration is �0.3 ppm in semiconductor-grade material. Dopant atoms, of which boron, antimony, arsenic, and phosphorus are commonly used, are in substitutional lattice sites (i.e., replacing silicon atoms), with the exception of very high doping levels (meaning high con centrations above 1018 atoms/cm3 Si), at which a small fraction of the doping elements are electrically inactive and in interstitial places. The maximum substitutional solubility depends on the atom size and some other fac tors; typically it is �1021 atoms/cm3. Germanium is an exception; it is completely miscible.

1.1.1.1 Miller Index (hkl) System A convenient way to describe atomic planes and direc tions in the crystal lattice is to use Miller indexes. When the lattice has maximum symmetry, or is cubic (as the silicon lattice is)—that is, the lattice axes are orthogo nal and the lattice parameters in all directions x,y,z

CHAPTER 1

are identical—the Miller notation is easy to use and is described later. Let us consider an orthogonal coordinate system, with axes x, y, and z, with equal unit vector size, a (Figure 1.2). In Figure 1.2a the plane intercepts the x-axis at a distance a from the origin and is parallel to the y- and z-axes, or intercepts them at �. The inter cept points in each axis are thus a,�,�. Miller indexes (hkl) are constructed in such a way that reciprocals of the intersect points are taken. Thus, in the case of Figure 1.2a, the Miller indexes (hkl) are a/a, a/�,a/� or (100). If the plane intercept points would be ½ a,�,�, Miller indexes of that plane would be (200). A plane intersecting axis y at a and the x and z axes at �, respec tively, is (010). If the plane would intersect axis y at –a, and the x and z axes at �, it is (0-10) or ( 0 l0 ) in Miller notation, where the negative sign is above the index number. A plane(110) means that plane intersect points are a,0,0, 0,a,0, and 0,0,�; with (111), plane inter sect points are, in a similar way, a,0,0, 0,a,0 and 0,0,a. Correspondingly, the (321) plane is a plane with inter sects at points a/3,0,0, 0,a/2,0 and 0,0,a (Figure 1.2f). The convention is that when the plane is marked as (hkl), it means that the plane is only that. If the mark ing is {hkl}, all planes in the same family are included, and in a cubic lattice it means that {khl} includes all 8 identical planes (hkl), ( hkl ), ( hkl ), ( hk l ), ( hkl ),

Fig 1.2 ● Miller indexes.

5

PA R T I

Silicon as MEMS Material

( hk l ), ( hk l) and ( hk l ). Indexes for directions are expressed in square brackets as [hkl]. The direction is perpendicular to the plane. Finally the family of direc tions is expressed as hkl, and again in cubic lattice it includes all identical 8 directions hkl, hkl , hkl , hk l , hkl , hk l , hk l and hk l . Those who would like to have a comprehensive picture of Miller indexes should consult, for instance, Cullity and Stock [8].

1.1.1.2 Stereographic Projection Stereographic projection in crystallography is a helpful and illustrative tool when investigating atomic planes or directions and visualizing various orientation dependent phenomena. In stereographic projection crystal direc tions are projected onto a plane. Construction of stereo graphic projection is made as follows: The crystal lattice is placed in the center point of the sphere and crystal lographic directions are projected onto the sphere’s sur face. A plane touching the sphere in point S is drawn. A line connecting points N and the projection point of the crystallographic direction on the sphere P* is drawn. This line intersects the plane in point P. When all crys tallographic low index directions intersecting the sphere in the southern hemisphere are drawn and projected to plane, a stereographic projection is constructed. This kind of projection preserves angles (but not areas), so it is possible to measure angles between crystallographic directions. This can be done manually using a Wulff ’s net. Silicon based MEMS technology uses commonly (100) oriented silicon wafers; that is, the (100) crystal lographic plane is the surface of the wafer. Less often, wafers with (111) or (110) are used. Some special appli cations may use off-oriented wafers, for instance, where the angle between (111) plane and water surface is 45°. Below are stereographic projections of cubic crystals in (100), (111) and (110) orientations constructed in such a way that the wafer orientation mark (a ﬂat or notch) is facing downward and is of 01 l type. There is useful commercial and free software for con struction of stereographic projections and calculation of angles between directions and planes [9, 10]. A com prehensive presentation about stereographic projections and their use can be found, for example, in Cullity and Stock [8] (Figures 1.3–1.7)

1.1.2 Defects in Silicon Lattice Although single crystalline silicon is almost perfect to a degree where it can be used as a standard to deﬁne Avogadro’s constant, in reality single crystals made either with CZ or ﬂoat zone (FZ) growing methods contain defects, some of which are characteristic to the particular growing method. Furthermore, defects 6

are formed intentionally or unintentionally during the processing of silicon wafers to ﬁnal components. These defects can be classiﬁed as (1) point defects (or their agglomerates), (2) linear defects, (3) planar defects or (4) volume defects. Silicon crystals are grown from the melt. Because of the low diffusivity of the point defects—vacancies and self-interstitials—many of the defects thermody namically at equilibrium concentration at the freezing point are “frozen in” the crystal during cooling phase. Depending on the temperature gradient close to the freezing interface and the time at high temperatures, point defect agglomerates can be formed, too. In IC tech nology COPs (crystal originated particles, or large vacancy agglomerates) have a great impact on thin gate oxide integ rity, for instance. Crystals grown with the CZ method also contain foreign atoms, like oxygen and carbon. Initially they are like point defects or clusters of a few atoms in the crystal at equilibrium in freezing temperature, and at normal device processing temperatures they are supersatu rated, eventually generating volume defects (precipitates) and/or secondary linear or planar defects. A growing oxide precipitate can nucleate stacking fault or dislocation loops around the precipitate. Oxygen can also form electrically or optically active defects, donors, which are discussed later in Section 3.6. Therefore, it is essential to control these defects not only in device manufacturing but also in the crystal growing step. As the relationship of the growth in defects in the crystals and defects in ﬁnished devices is complex and depends on the thermal processing steps, it is beneﬁcial for the crystal grower to know, in as detailed a manner as possible the device manufacturing steps to optimize the behavior of the silicon. Reviews of Falster et al. [11, 12] give an overview of intrinsic point defects in CZ silicon. Linear defects are called dislocations (see Section 11.2). In silicon single crystals grown by CZ or Float Zone methods, or in wafers cut from these crystals, the dislo cation density is practically zero. During the processing of the silicon wafer at higher temperatures, the applied stress may generate dislocations. The origin of these N

S

P* P

Fig 1.3 ● Construction of a stereographic projection.

Properties of Silicon

– 013

– 012

– 023

– 011

– 133 – – 122 – 001 – 113 – 112 – 233 223 – – – 111 103 213 – –– – 323 013 102 – – – 212 322 – 203 –– 313 – –– – 113 – 012 312 211 101 –– – – –– 213 –– 311 –– 302 – 112 023 313 –– 201 – –– 123 –– –– 212 223 –– 301 312 323 –– –– –– –– –– –– –– –– 100 011 133 122 233 111 322 211 311 – 123

–– –– –– – 232 332–– 321 310 221 – –– –– 210 331 – 121 –– 320 231 – – 110 –– 321 131 – – 230 331 – – 221 – 120 – 332 – 231 130 – – 232 – 121 131 –– 010 – 132

–– 132

–– 032 –– 021 –– 031

– 031

– 021

– 032

– 032

– 021

– 132 – – 121 232

– 131

CHAPTER 1

– 031

010

– 130 231 – 332 – 120 221 – 230 331 – 131 321 110 231 320 121 331 210 132 221 321 310 332 232

031 021 032

011

311 211 322 111 233 122 133

323 312 223 301 212 123 201 313 – 112 302 311 213 – 101 – 211 312 113 – 203 – 313 322 – 102 – 212 – – 323 213 103 111 – 223 – – 112 – 233 113 – – 122 001 123 – 133 – 013 – 012 – 023 – 011

023 012 013

Fig 1.4 ● Stereographic projection of (100)-oriented crystal.

stresses can be thermal gradients during temperature transients in heat treatment steps, or mismatch stresses caused by thin ﬁlms or heavily doped areas in combi nation by high temperatures. Movement of dislocations through the crystal lattice causes permanent deforma tion. Dislocations in silicon move on {111} planes along 110 directions. This deformation can be seen visu ally as slip lines. If the deformation is heavy, the wafer warpage may increase. In general dislocations in silicon wafers have adverse effects on device performance, and in the worst case dislocations may even prevent the device from functioning. Dislocations attract impuri ties, and the result can be that moving dislocations leave precipitate colonies behind. Dislocations can also match together two parts of silicon lattices having slightly dif ferent lattice constants. This happens when an epitax ial layer is grown on a substrate and their doping levels differ substantially (see Figure 6.11). These dislocations are called misﬁt dislocations, and normally they are conﬁned in the interface. In MEMS applications where

silicon is etched, areas containing dislocations generally have a non-uniform etch result because of the stress ﬁeld around the dislocation core. A further consequence of the presence of dislocations is a reduction of yield strength at higher temperatures. The yield strength of zero dislocation silicon is higher than silicon having dis locations in temperatures where plastic deformation can occur. This means that once slip has occurred, silicon wafers are more susceptible to additional slip in follow ing thermal treatments. However, dislocation locking by impurity atoms diffusing to the dislocation core or strained area increases resistance to additional slip. Planar defects are called stacking faults. In silicon stacking, faults are along (111) atomic planes and they are surrounded by partial dislocation. A silicon lattice may contain an extra atomic place; this stacking fault is called extrinsic. If an atomic plane is missing, the stack ing fault is intrinsic. Most stacking faults in silicon are of the extrinsic type. Extrinsic stacking faults are formed by excess silicon interstitials; oxidation induced stacking 7

Silicon as MEMS Material

PA R T I

– 011

– 123 – 112 – 213

– 123 – 122 – – 132 233

– 223 – 111

– – – 313 212 323

– 232

– – 132 – – 121

– 032 – 021

– – 231

– – 131

– 031

– 121

– 131 – – – – – – 332 110 130 120 230 – 322 – 231 – 010 221 312 – – 211 130 – 331 – 321 302 230 120 – – – – 231 331 110 131 – 311 031 201 131 – – 320 231 221 – 121 021 331 210 301 121 – – – 221 232 332 310 032 132 321 332 232 132 – – – – – –– 322 311 211 322 111 233 122 133 011 133 122 233 111 100 311

– 101

–– 312

–– 211

– 310

–– 321

– 210

– 311

– 320 – 110

– 321

301 201 302

– 231

– 232 – 121

323 223 123 212 112 313 213 113

101 – 312

023

– – 123 233 – 122 – 133 – 132

013

001

– 013

– 023

– 323 – 212 – – 313 213

– 223 – 112

– 113

– – 103 – 102 203

–– 113

– 012

– 011

– 123

012

203 102

– 103 313 – – 212 213 – 323 – – 113 – 112 – 111 223

– 211 – 322

– – 331 221 – 332

312

– 321

– 211

– 312

– 101

–– 213 –– 112

–– 123

Fig 1.5 ● Stereographic projection of a (111)-oriented crystal.

faults (OISFs) or stacking faults around growing oxide precipitates are typical examples. A large oxygen pre cipitate may generate stacking fault(s) to reduce misﬁt stresses. Wet oxidation of silicon wafer also may induce stacking faults. Intrinsic stacking faults can be found, for instance, in epitaxial layers. Although the largest stacking faults in wafers can extend over several hun dred μm’s, typically the diameter is less than 100 μm. Volume defects in silicon are precipitates. They can be coherent (the lattice of the precipitate is aligned with the host silicon lattice), or non-coherent, when there is a mismatch in lattice alignment. Small precipitates are often coherent, and when they grow, they turn ﬁrst semicoherent, and then non-coherent. Precipitates are nor mally compounds of silicon:silicates or silicon dioxide. Czochralski-grown silicon contains dissolved oxy gen, which is supersaturated at wafer processing tem peratures, unless a special low oxygen content material is used. Extended thermal treatments grow oxygen precipitates. Also, there can be a redistribution of 8

precipitates, in which large precipitates are grown at the expense of small ones. This phenomenon is called an Ostwald ripening process. At a given temperature there is a critical size of precipitate; larger precipitates are grown, provided that there is enough supersaturation at that temperature, and smaller precipitates are dissolved. Using this phenomenon, it is possible to tune both the distribution and size of precipitation, ﬁrst designing a proper lower temperature nucleation step to adjust the size distribution and density of nuclei, and then, at higher temperatures, growing precipitates which exceed the critical size at that temperature. At the same time it is also possible to form a precipitate-free zone below the wafer surface. The precipitate nucleation process depends especially on the properties and thermal his tory of the grown crystal; therefore, silicon wafers from different sources behave differently. However, if, fol lowing thermal cycles, the crystal grower knows what silicon wafers are seeing in the manufacturing steps that follow, it is also possible to adjust the crystal growth

Properties of Silicon

CHAPTER 1

– 110

– 331 – – – 221 – – – 331 332 – – 221 332 – – – – – 230 111 231 – – 231 111 – – – – 232 232 – 120 – – – 223 – – – – – 121 121 233 233 – 223 – – – 130 – – – – 131 131 – 112 – – 122 122 – – 132 132 112 – – – – – – 133 133 123 123 – – 113 010 – – 031 021 – 021– 031 113 032 – 032 011 011 – 023 – 023 – 012 130 012 131 132 – 131 – – 133 133 132 – 013 013 120 – 121 – 121 – 122 123 123 122 – – 231 230 231 232 233 233 232 – – – – – – – – 113 112 223 111 332 221 331 110 331221 332 111 223 112 113 001 001 – – – 323 322 – 323 322 321 320 321 213 – 212 213 – 212 – 211 210 211 – 103 103 313 – – 313 312 – 311 312 102 311 102 310 – 203 203 – 101 101 – – 302 302 201 – 301 201 –– 301 – 100 113 113 –– – –– – 213 213 313 313 –– – – –– 312 312 –– – –– – 212 212 112 112 – 311 311 310 – –– –– – –– 323 323 – 211 211 223 – – 223 –– 210 322 322 –– – –– – 321 321 111 – 320 111 –– 332 –– – 221 –– 331 – 332 – 221 110 – 331

Fig 1.7 ● Wulff net used in measurement of angles in stereographic projection.

Fig 1.6 ● Stereographic projection of a (110)-oriented crystal.

process and crystal properties in such a way that desired results are obtained. If wafers are used in IC manufac turing, the objective normally is to have precipitation on the bulk; the surface area remains defect free, to get the maximum effect out of internal gettering (see Figure 4.7). On the other hand, some MEMS manufacturing processes yield optimum results only if the bulk of the wafer remains essentially precipitate free. COP, a cluster of vacancies, is also a volume defect. The size and density of this defect depend on the crys tal growth process; the average size can be from tens of nm to less than 200 nm. COP has mostly an effect-gate oxide quality in CMOS devices. Because the COP origi nates from crystal growth process involving melt, epi taxial layers are free from COPs (Figure 1.8). “Defect Engineering” can be used successfully in sili con technology to maximize device yield; however, it should be remembered that conventional approaches used in IC manufacturing are not necessary successful in MEMS technology. Reviews by Borghesi et al. [13] on oxygen precipitation in silicon; Bergholz and Gilles 9

PA R T I

Silicon as MEMS Material τ τuy τly

ε

Fig 1.9 ● Schematics of stress–strain behavior of dislocation-free silicon single crystal at elevated temperatures. τuy � upper yield strength, τly � lower yield strength, � � strain. Fig 1.8 ● Defects in primitive cubic lattice. (a) vacancy, (b) interstitial atom, (c) interstitial atom (can be foreign atom or selfinterstitial), (d) dislocation (edge), (e) intrinsic stacking fault, (f) extrinsic stacking fault, (g) non-coherent precipitate.

–1

1000/T (K ) 0.5

1

1.5

2

10000

[14] on defects in general in silicon; and Sinno et al. on

defect engineering in CZ silicon [15] give a good over view of how defects affect IC manufacturing.

1.1.3 Mechanical Properties of Silicon

Silicon is a hard, brittle material, and at room tempera ture under stress silicon single crystal elongates elasti cally until fracture stress appears without signiﬁcant plastic deformation. Therefore, defects (scratches, dents, mechanical damage, etc.) on the surface or periphery of the silicon wafer can cause premature cracking under stress because of the notch effect. Silicon wafers having a rough surface or residual dam age left on the wafer surface (cut wafer, lapped wafer, or ground wafer without stress relief) are more prone to break compared with polished wafers. The ideal, “strong” wafer is double side polished, and the wafer edge is polished and round, also. Samuels and Roberts [16] used pre-cracked bar-shaped single crystal speci mens in four point bending tests and found a brittleductile transition temperature of 545°C at ambient pressure. At room temperature they measured a frac ture stress of 270 MPa. Under 1.5-GPa conﬁning pres sure, the brittle ductile transition temperature can be lowered to 275°C, after Rabier and Dement [17]. For a comparison, Vedde [18] gives, for median fracture strength (at 50% probability level) when using a doublering bending test method, 1.18 GPa for polished CZ wafer and 1.01–1.12 GPa for FZ wafer (different growth processes), compared with an as-cut state from 180 to 220 MPa or 270 to 330 MPa in an as-lapped state. However, these values are here only as indicators, since, in practice testing conditions, the starting mate rial quality, wafer manufacturing processes, and possible 10

τ (MPa)

1000 100 10 1 0.1

Fig 1.10 ● Lower yield strength of silicon vs. deformation temperature. Reprinted from Physica Status Solidi B, Copyright 2000 John Wiley.

post-treatments of the wafers have an inﬂuence on the fracture tendency. At elevated temperatures silicon starts to show plastic deformation. Once the upper yield strength (also called upper yield point) is achieved, dislocations start to gener ate, multiply, and move on slip planes, the stress lowers to the lower yield strength (point), and plastic deforma tion proceeds. When the dislocation density is increasing, dislocations reach each other, slip is prevented, the lat tice hardens, and stress required for further deformation is increased, until fracture occurs. Silicon single crystals made with CZ or FZ techniques have similarly shaped stress–strain curves, provided that the crystals are ini tially dislocation free [19, 20] (Figure 1.9). The value of lower yield strength varies with the temperature, according to Figure 1.10 [17]. At 900°C, the critical shear stress on the (111) plane required to move dislocations is about 8 MPa. Oxygen containing CZ silicon has, in practice, a higher tolerance against slip compared with oxygen-free FZ silicon. The difference is that when the deformation stops, in oxygen containing CZ, silicon dislocations are locked rapidly by diffusing oxygen to dislocations, while in oxygen-free FZ silicon, this locking does not take

Properties of Silicon

3

2

O-treated FZ-Si (O)~ 1017 cm–3

τeff

O-treated FZ-Si FZ-Si CZ-Si

FZ-Si

1 × 106

5

CZ- Si (O) ~ 8×1017cm–3

1

N0(cm–2) 2 × 105

6

T = 900°C , ε˙ ~1.1× 10–4 s–1 N0~106cm–2

τuy , 107N/m2

Resolved shear stress,107 N/m2

4

CHAPTER 1

4 T = 800°C 3

2

0

T = 900°C 10

20

30

40

50

1

Shear strain, %

Fig 1.11 ● Actual result of stress–strain behavior of silicon single crystals having initial dislocation density of 106/cm�2 deformed at 900°C. Oxygen-free FZ-silicon does not have an upper yield point. FZ with added oxygen, as well as standard CZ-silicon, has an upper yield point. Reprinted with permission from Japanese Journal of Applied Physics, Copyright 1980, Japan Society of Applied Physics [20].

place and dislocations can move easily. Once deformed, CZ material shows again an upper yield point consider ably higher compared with the stress required to move dislocations, while FZ silicon starts to deform at a stress level required to move dislocations in constant deforma tion (Figure 1.11) [20]. FZ silicon can be “hardened” by adding oxygen or nitrogen, but, in general, FZ is more prone to slip, which has to be taken into account when designing thermal treatment steps. Oxygen concentration in dislocated silicon crystals has a signiﬁcant effect on upper yield strength. Figure 1.12 shows an upper yield strength dependence on oxygen concentration at 800°C and 900°C, with two different initial dislocation densities [21]. When the initial dislocation density increases, the effect of oxy gen diminishes and the upper yield strength falls. Thus, slipped wafers in thermal treatments (and especially in the cooling phase, where radial stresses in wafers are highest) are more susceptible to further slip with increasing initial dislocation content. It should be noted that silicon wafers in the as-received state typically do not have dislocations; exceptions are some epi wafer types with thick epitax ial layers. In these epi wafers, speciﬁcations allow some maximum amount of slip. The oxygen-related bulk microdefect density has to be minimized in some MEMS processes; this is done by minimizing the initial oxygen content in silicon wafers. The adverse effect is that when such wafers are used, more attention has to be paid to controlling stresses in wafers during thermal processes at temperatures at which silicon is still plastic.

0 0

5

10

Co , 1017cm–3

Fig 1.12 ● Upper yield strength vs. oxygen content of dislocated CZ-silicon at 800°C and 900°C. Silicon crystal with a higher dislocation content has lower strength (τ is the effective stress on the (111) slip plane). Reprinted with permission from Journal of Applied Physics, Copyright 1984, American Institute of Physics.

1.1.4 Electrical Properties Silicon is a group IV element in the periodic table and is a semiconductor with a bandgap of 1.12 eV, which means that pure silicon at room temperature is almost an insu lator. By doping with group III or group V elements, the resistivity of silicon can be varied over a wide range.

1.1.4.1 Introduction—Dopants and Impurities in Silicon Semiconductors are solid materials that have electrical conductivities in between those of conductors and those of insulators. The physical reason causing a material to behave as a conductor, semiconductor, or insulator lies in the availability, or lack thereof, of free current carriers in the material. Semiconductors are characterized by the narrow bandgap between the valence bands, occupied by electrons, and the conduction band, in which electrons move freely according to applied electrical ﬁelds. Intrinsic (i.e., pure) semiconductors act as insulators at room temperatures, but their behavior changes dramatically with temperature, and, more to the point, with small impurities present in the crystal. Very small amounts of electrically active impurities can totally alter the electri cal properties of semiconductors such as silicon. This is because the electrically active impurities either easily donate valence electrons (donors) or accept them, creat ing holes (acceptors). These electrons or holes are free (i.e., not bound to individual atoms). Their movement due 11

PA R T I

Silicon as MEMS Material

to applied electrical ﬁelds carries electrical currents, giv ing rise to the term charge carriers used to denote them. The electrical properties of semiconductor materi als such as single-crystal silicon are thus deﬁned by the impurity concentrations present in the silicon lattice. Impurities are introduced into the starting materials dur ing crystal growth and modiﬁed during device processing by additional doping of the silicon material with electri cally active impurities. In intentional doping of silicon, impurity atoms from group III (acceptors) and group V (donors) are used. The dopants used in crystal pulling, and the conductivities reached with speciﬁc impurity concentrations, are described in more detail in Sections 3.1 and 3.3, Dopants and impurities in silicon crystals. Manipulation of the electrical properties in the struc tures created during MEMS device manufacturing follows practices established in semiconductor device manufactur ing. Techniques used include both very traditional meth ods, such as deep diffusions of dopants, which have been abandoned in mainstream semiconductor processes, and current standard techniques such as ion implantation and epitaxial deposition. While semiconductor-grade starting materials are largely free of other electrically active impu rities, the incorporation of unintentional contamination into silicon during processing can have signiﬁcant effects on the electrical properties of the manufactured devices. Unintentional doping of silicon includes the intro duction of unwanted donors or acceptors to the crystal lattice from the processing environment. These impuri ties can be either group III/V-type atoms misplaced, or other contaminants, such as some transition metals. The generation of electrically active donors also takes place within the single-crystal CZ silicon itself, with out the introduction of additional impurities. CZ silicon always includes a few ppma of interstitial oxygen atoms, originating from the quartz crucible used to hold the melt during crystal pulling (see also Chapter 3). At cer tain temperatures, ranging from 400°C to 550°C, these interstitial atoms create conglomerates of several oxygen atoms within the lattice. Such silicon–oxygen microclus ters are known as thermal donors (TD), as they donate free electrons to the conduction band, inﬂuencing the electrical properties accordingly [22, 23]. The concentra tion is, however, usually below 1E15/cm3, and thus has only very marginal effects on other than high-resistivity silicon. These donors are not stable at temperatures above 600°C, and even for applications requiring high-resistivity silicon, their effect can be suppressed by quick cool ing down over the generation temperature range. This method is called thermal donor anneal (TDA), and while it is effective, it does not prevent the generation of new TD if temperatures in the critical range are used later in the device processing. For further details, see Section 3.6. The use of semiconductors is based on the fact that the charge carrier concentrations are also inﬂuenced by 12

any electric ﬁelds that are present. This can take place intentionally, as, for example, in transistors, but also due to electric ﬁelds generated by surface effects such as charging. These effects are more pronounced in highresistivity silicon, but they bear consideration in general. In the vast majority of cases, the electronics required for the realization of a MEMS-based sensor consist of the basic building blocks of semiconductor electronics used since the birth of the silicon-based semiconduc tor industry and described in the basic handbooks of the industry, such as Sze [24]. In MEMS applications requiring very high resistivity, in ﬁelds such as RF and optical, special considerations apply. The very high resis tivity materials used are obviously strongly affected by even the smallest concentrations of unintended charge carriers. These unintended charge carriers can be intro duced into the material by methods such as TD genera tion (described earlier), oxidation, and contamination of the surface if the donors/acceptors are not subse quently evaporated. In very high resistivity silicon, these effects can be severe, in some cases even leading to type reversal.

1.1.4.2 Piezoresistive Effect in Silicon General Piezoresistive Effect The change in the resistance of metal devices due to an applied mechanical load was ﬁrst discovered by Lord Kelvin in 1857. With the large-scale use of single-crystal silicon in the making of semiconductor circuits, a much stronger piezoresistive effect was discovered in silicon [25]. This discovery forms the basis for practically all piezoresistive MEMS applications.

Strain When a sample is subjected to physical force, the force yields a change in length, dL, that follows the well known Hooke’s law F � kΔL, where k is a material constant. The stress is deﬁned as the applied force per unit area. Stress (σ) is thus given by σ � F/A � kΔL/A � k L ΔL/AL or k εL L/A

(1.1)

where �L denotes the differential deformation, ΔL/L, known as strain. Most solids exhibit elastic behavior for small stress loads. In elastic deformation the strain is proportional to the applied stress and the material fol lows Hooke’s law, which, in the simple case of uniaxial stress, can be written as σ � Y εL

(1.2)

where the scalar Y stands for the modulus of elasticity, also known as Young’s modulus. This material parameter for crystalline materials such as silicon is not omnidirec tional, but varies according to crystal planes.

Properties of Silicon

For strains above certain thresholds, Hooke’s law is no longer valid. This is caused by non-elastic, or irreversible (i.e., plastic) deformation.

The piezoresistive effect is quantiﬁed using the gauge

factor G, describing the relationship between the applied

strain and the change in resistivity. The piezoresistive

effect, and thus also the gauge factor of semiconductor

materials, is several magnitudes larger than the geometri cal effect observed in metals. The effect is observed in

several semiconductor materials, such as germanium,

polycrystalline silicon, and single-crystal silicon.

The large piezoresistive effect in silicon is due to the fact that, instead of a stress-dependent change in geo metry, the effect is ﬁrst and foremost due to the stress dependent resistivity of the material. The strain applied to the lattice causes the anisotropic band structure to deform, giving rise to anisotropic change in the mobility of the current carriers.

Stress in Anisotropic Materials The elastic behavior of isotropic materials can be deﬁned with just two elastic constants, commonly used parameters being the Young’s modulus Y and Poisson’s

ratio ν, but modiﬁed constants known as bulk modulus

K and shear modulus G are also sometimes used. In the

general anisotropic case, the stress state of the mate rial, is deﬁned by a matrix known as the stress tensor, a

3 � 3 matrix in three dimensions. Crystallographic symmetry allows the reduction of

stress tensors in silicon to 6-vector notation. In static

equilibrium, the situation is further simpliﬁed to just 6

independent variables, and the stress tensor can be writ ten as [26]:

⎡σ xx ⎢ ⎢

σ � ⎢σ xy ⎢ ⎢ σ xz ⎣

σ xz ⎤⎥ ⎥ σ yz ⎥ ⎥ σ zz ⎥ ⎦

σ xy σ yy σ yz

(1.3)

Typically, the geometries used in MEMS applications

reduce the situation, as in the case of a piezoresistive

sensing layer created on a relatively thick silicon sub-

strate. For such a layer, the vertical (z) stresses can be

equated to zero, and the stress is reduced to

σ layer

⎡σ xx ⎢ � ⎢⎢σ xy ⎢ ⎢⎣ 0

σ xy σ yy 0

0⎤ ⎥ 0⎥⎥ ⎥ 0 ⎥⎦

(1.4)

This expression can be further simpliﬁed if we limit our discussion to stresses parallel, and stresses perpen dicular, to the direction of current. For practical sensor

systems, this limitation can easily be applied. Thus, the forces can be denoted as σl (parallel stress) and σt (perpendicular or transverse stress).

CHAPTER 1

Strain Effect on Resistivity In metals the conduction/valence bands are partially

ﬁlled with charge carriers, and small changes in band

shape do not affect most of the carriers. In semiconduc tors the shape and dimension of the bandgap has a much

larger effect, and shifts in energy bands due to applied

stress affect the mobility of charge carriers. The result

is resistivity change due to applied stress and gauge fac tors up to two magnitudes larger than those observed in

metals. Because the relative change in resistivity is pro-

portional to strain, it can be written as

Δρ � Y πL εL ρ

(1.5)

For strained anisotropic material, the resistivity is thus no longer scalar and is described through tensor math ematics, similar to the mathematics described earlier for stresses in anisotropic material. Thus, the dependence of the current density J on the electric ﬁeld E is denoted ⎡ ⎡E ⎤ ⎢ρ xx ⎢ x⎥ ⎢ ⎢ E ⎥ � ρ

⎢ xy ⎢ y⎥ ⎢ ⎢ ⎥ ⎢ ρ xz ⎢⎣ Ez ⎥⎦ ⎣

ρ xy ρ yy ρ zy

ρ xz ⎤⎥ ⎡ J x ⎤ ⎢ ⎥ ⎥ ρ yz ⎥ ⎢⎢ J y ⎥ ⎥ ⎥ ⎢ ⎥ ρ zz ⎥⎦ ⎢⎣ J z ⎥⎦

(1.6)

Details of the tensor mathematics explaining the

anisotropic resistivity are described in, for example,

Thomsen [26].

In typical applications the MEMS devices are con structed in such a way that the current in the piezore sistors is either parallel or perpendicular to the direction

of the stress. Also, the vast majority of applications

are made on (100) silicon wafer substrates, with the

substrate oriented in such a way that the resistors are

aligned on the [110] direction on p-type and the [100]

direction in n-type, as depicted in Figure 1.13. These

directions yield the maximum positive and negative piezo coefﬁcients (i.e., the maximum relative resistivity change for a given applied force).

For a system in which the coordinates are chosen to

coincide with the crystallographic axes, the relationship

between the stress tensor and the anisotropic change in

resistivity simpliﬁes due to crystallographic symmetries

of silicon, and can be deﬁned as ⎡ ∂ρ11 ⎤ ⎡ Π11 Π12 Π12 1 ⎢ ⎥ ⎢ ⎢∂ ρ22 ⎥ ⎢ Π12 Π11 Π12 ⎢ ⎥ ⎢ ⎢Π Π12 Π11 1 ⎢⎢∂ ρ33 ⎥⎥ � ⎢

� ⎢⎢ 12 ⎥

∂

ρ 0 0 0 ρ ⎢ 23 ⎥ ⎢ ⎢ 0 ⎢∂ρ ⎥ 0 0 ⎢ 13 ⎥ ⎢ ⎢ ⎥ ⎢

0 0 ⎢⎣∂ρ12 ⎥⎦ ⎢⎣ 0

0 0

0 0

0 Π 44 0 0

0 0 Π 44 0

0 ⎤ ⎡ ∂ σ11 ⎤

⎥ ⎥⎢ 0 ⎥ ⎢∂ σ22 ⎥ ⎥ ⎥⎢ 0 ⎥⎥ ⎢⎢∂ σ33 ⎥⎥ 0 ⎥⎥ ⎢⎢ ∂ σ23 ⎥ ⎥ 0 ⎥⎥ ⎢⎢∂σ13 ⎥⎥ ⎥

⎥ ⎢

Π 44 ⎥⎦ ⎢⎣∂σ12 ⎥⎦ (1.7) 13

PA R T I

Silicon as MEMS Material

(a)

Table 1.2 Independent piezo coefﬁcients for crystalline bulk silicon [25, 27]

10�11 1/Pa

n-Si ND � p-Si NA p-Si NA 2e15[25] 1e18[27] 4e1425

Π11

�102

�6,6

Π12

�53

�1,1

Π44

�14

�138

�103

1 [π11 � π12 � π44 ] 2

�81

(1.8)

(1.9)

The corresponding transversal piezo coefﬁcient then becomes πt �

1 [π11 � π12 � π44 ] 2

(1.10)

For piezoresistors in the �100� plane of an n-silicon substrate, the maximum piezo coefﬁcient is found along the (100) crystal axis, and the piezo coefﬁcients are reduced to πl � π11

(1.11)

and

have contributed to the dominance of bridge circuits in piezoresistive sensing based on silicon. The alignment of piezoresistors to be constructed is governed by the piezoresistive coefﬁcients listed in Table 1.2. Almost universally, the optimal solution is to align the sensing resistors according to maximum pie zoresistive effect, as described by the examples depicted in Figure 1.13. The choices of resistor direction, dicing direction, and anisotropic etching are determined by the crystal orientations. In addition, the speciﬁcation of the crystallographic location of the substrate wafer ﬂat is based on the chosen crystal alignment. The primary ﬂat has historically been located at the �110� direc tion, and dicing along and perpendicular to the primary ﬂat is depicted in Figure 1.13a, c.

Linearity In comparison to many other physical phenomena, the piezoresistive effect is a fairly linear effect. To be exact, the linear equations for piezo coefﬁcients should, how ever, be replaced with higher order polynomials. For resistors aligned on the �110� crystal axis, for maxi mum piezoresistive effect in p-type silicon, a quadratic correction to the transversal piezoresistive coefﬁcient is sufﬁcient for a wide range of doping concentrations and applied stresses. The quadratic correction for p-type sil icon along the �110� crystal axis is of the form [28] ∂ρ � πl σl � πt σt [1 � 6.66 � 1010 σt 1/pa] ρ

(1.13)

yielding a quadratic correction of less than 1% for stresses up to 10 Mpa.

Effect of Temperature and Doping πt � π12

(1.12)

It is immediately observed that for both n- and ptype piezoresistors, uniaxially stressed at respective optimum locations for sensitivity, the longitudinal and transverse piezo coefﬁcients have opposite signs. The advantages offered by this fact in a Wheatstone bridge 14

(c) N-type silicon, Dicing along <100>

Fig 1.13 ● Typical piezoresistor alignments used on MEMSstandard (100) silicon wafers, aligned to utilize maximum piezo coefﬁcients for rectangular membranes of the type used in pressure sensors.

where the common notions of longitudinal piezo coefﬁ cient πl and transversal piezo coefﬁcient πt are used. As an example of a common situation, let us consider the case of a p-type piezoresistor constructed to utilize the maximum piezo sensitivity as described in Figure 1.13a. For such a resistor, which is uniaxially stressed and lying in the (110) direction, the shear strain is zero and the longitudinal piezo coefﬁcient is simpliﬁed to πl �

P-type silicon, Dicing along <100>

p-Si NA 1e19[27]

where Π11, Π12 and Π44 represent three independent piezo coefﬁcients, listed in Table 1.2. In most applications the change in resistivity is limited to stresses parallel and perpendicular to the resistive path. In such cases, the situation is greatly sim pliﬁed [28]. The tensor element becomes a scalar equa tion, and can be written as ∂ρ � πl σ l � πt σ t ρ

(b)

P-type silicon, Dicing along <110>

In addition to the piezoresistive effect, the silicon resis tors exhibit strong temperature dependence. For pie zoresistors with low to moderate doping, the resistivity changes can reach one magnitude for every 100°C. Change in offset is caused by leakage currents, which are strongly dependent on temperature according to Laermer [29]. While in some cases the temperature

Properties of Silicon

dependence can be utilized or ignored, in the vast major ity of cases this must be compensated for. Combined with the effect of doping on the piezoresistive effect, the temperature effect can be corrected with the pie zoresistance correction factor P(N,T). Generally, a higher dopant concentration in silicon reduces the tem perature effect, whereas the higher the temperature, the lower is the effect of doping level. Thus, designing of the resistor requires a trade-off between sensitivity and temperature stability (Figure 1.14). The modern IC technology can provide a mathemati cal solution to the compensation of the piezoresistors, by introducing signal conditioning of the linearity and temperature effect to the sensing setup. This approach provides additional accuracy and ﬂexibility at the cost of some cost and complexity. While the approach is commonly used to improve nonidealities in surface micromachined sensors, the performance of sensing ele ments manufactured from bulk, single-crystal silicon is usually close to ideal when temperature effects are accounted for. Basic solutions for correcting for temperature varia tions include the use of a reference (i.e., a non-strained resistor which is at the same temperature). The differ ence of signal between the strained and non-strained sensors provides the desired signal due to strain only. The other basic technique is to utilize a temperatureindependent circuit—in practice, a bridge circuit. In a Wheatstone bridge circuit application, the four resistors are doped to the silicon and arranged in such a way on the sensing membrane that they react to strain in pairs. In addition to having the advantages in sensitivity, discussed earlier, the bridge circuit can be used to com pensate for temperature effects. The standard setup of a Wheatstone bridge in (100) silicon substrate consists of one pair of resistors aligned to give maximum positive change in resistivity (longitudinally stressed if p-type,

Piezo correction factor P(N,T)

1.6

T = –73 °C

n-Si

1.4 1.2

T = –25 °C

1.0

T = 25 °C

0.8

T = 75 °C T = 125 °C T = 175 °C

0.6 0.4 0.2 1E16

1E17

1E18 ND1/cm3

1E19

1E20

Fig 1.14 ● Piezo correction factor P(N,T) in n-Si as a function of doping level, for various temperatures. Redrawn and modiﬁed from Kanda [30].

CHAPTER 1

transversely stressed if n-type), while the other pair yields the maximum negative change (a perpendicular alignment with respect to the ﬁrst pair of resistors). This bridge circuit provides an output signal which is independent of temperature, assuming that the whole membrane is subjected to equal temperature changes. The circuit output is thus, to a ﬁrst-degree approxi mation, directly proportional to the change in resistiv ity due to the applied stress. The main disadvantage of piezoresistive gauging using bridge circuits lies in the current requirements in the milliampere range, which cause limitations in the use of these circuits in powersensitive applications.

Example of a Piezoresistive Sensor Design Pressure sensing has utilized piezoresistive sensing based on MEMS technology for years and is the ﬁrst widely adopted application of the technology. This is due to the fact that thin micromachined silicon membranes with a piezoresistor bridge implemented on top of them provide a rather ideal solution to the common prob lem of sensing pressure over a known, rather limited range of pressures, over long periods of time and count less cycles of pressure changes, for low cost and no maintenance. A very basic sensing setup is as follows: Starting point: Silicon substrate, N-type, (100) orientation, device dicing along �110� direction. Membrane deﬁned by etching, using an alkali etchant from the backside of the wafer. The long etching is carried out in concentrated KOH or TMAH, requiring a thick protective layer of oxide, or nitride. The tradi tional bulk micromachining has utilized backside pat terning for these cavity-etching processes. Cavity sealed through wafer bonding. The sealing options range from glues and glass frits to fusion bond ing of silicon wafers. Piezoresistors are boron implanted on top of the wafer, at the edges of the membrane, where the stress maxims are located when the cavity pressure differs from the outside pressure. Boron implantation of the ohmic con tacts can usually also be performed at this stage. The basic device is ﬁnished with one or two layers of metals. The dopant proﬁle of a simple implanted and dif fused piezoresistor of the type described is illustrated in Figure 1.15. The denuded zone responsible for the elec trical isolation is shown without bias; with reverse bias, it can be extended to meet the requirements. The basic device outlined earlier follows the geom etry outlined in Figure 1.16. This device has the pie zoresistors located at the stress maximums of the rectangular membrane and along the crystal axis yield ing greatest change in resistivity for a given stress. Also, 15

PA R T I

Silicon as MEMS Material

(a)

(b) V output V input

Fig 1.16 ● Basic MEMS-based sensor application using piezoresistors in �100� silicon. (a) Side view (cross-section along the �110� plane. (b) Top view, with the piezoresistors located in a Wheatstone bridge, along the (110) direction on the top of the silicon membrane. Fig 1.15 ● Basic diffused piezoresistor dopant depth proﬁle. The wafer surface is to the left, and the piezoresistor is hatched. The transition zone under the piezoresistor acts as the electrical isolation. The hatched line (� · · �) on the left denotes free hole concentration, and the hatched line (— · —) on the right side of the transition denotes free electron density, approaching the starting material ND density in the depth of the wafer. The graph is calculated using IC-simulation software ICECREM 4.3 for WINDOWS™ by Fraunhofer Gesellschaft for Integrated Systems and Device Technology (IISB), Erlangen, Germany[31], and the carrier concentrations refer to zero bias.

the shear stresses of the membrane are minimized, the oretically to zero, at the locations of the resistors.

Surface Effects In many cases, the carrier concentration depth proﬁle of the piezoresistor can be very important. Especially in accelerometers, the piezoresistive MEMS-sensor is

often loaded so as to cause compressive strain on one side of the membrane and tensile strain on the other. In such a case the effective piezo coefﬁcient, and thus the sensitivity, is very strongly inﬂuenced by the ratio of carrier concentrations between the membrane sur faces. Also, those piezoresistors whose stress is purely compressive or tensile are affected by the vertical car rier proﬁles, as the greatest strains are located at the very surfaces of the membrane. On the other hand, the carrier concentrations tend to change more rap idly the closer they are to the surface. Because the car rier concentrations near the device surfaces can also be affected by charging of the dielectric layers used to isolate and seal the micromachined structures, a care ful consideration of the design principles used in ana log transistor design is necessary to ensure the reliable operation of the piezoresistive element.

References 1. 2006 Minerals Yearbook, Silicon, published by US Geological Survey, March 2008 (http://minerals.usgs. gov/minerals/pubs/commodity/silicon/ myb1-2006-simet.pdf) 2. P. Woditsch, W. Koch, Solar grade silicon feedstock supply for PV industry, Sol. Energ. Mate. Sol. Cells 72 (2002) 11–26. 3. A.A. Istratov, T. Buonassini, M. D. Pickett, M. Heuer, E.R. Weber, Control of metal impurities in “dirty” multicrystalline silicon for solar cells, Mat. Sci. Eng. B 134 (2006) 282–286. 4. K. Petersen, Silicon as a mechanical material, P. IEEE 70 (1982) 420–457. 5. R. Hull (Ed.), Properties of Crystalline Silicon, Inspec, London, 1999.

16

6. Landolt-Börnstein Group III,

Condensed Matter volume series,

Springer Verlag

7. J. Martin, U. Kuetgens, J. Stümpel, P. Becker, The silicon lattice parameter— an invariant quantity of nature? Metrologia 35 (1998) 811–817. 8. B.D. Cullity, S.R. Stock, Elements of X-ray Diffraction, third ed., Prentice Hall, 2001. 9. �http://www.jmtilli.iki.ﬁ/~juhis/

stereographic/� a free software

10. �http://www.jcrystal.com/products/ winwulff/index.htm� a commercial software 11. R. Falster, V.V. Voronkov, F. Quast, On the properties of the intrinsic point defects in Silicon: a perspective from crystal growth and wafer processing,

Phys. Status Solidi B 222 (2000) 219–244. 12. R. Falster, V.V. Voronkov, The engineering of intrinsic point defects in silicon wafers and crystals, Mater. Sci. Eng. B73 (2000) 87–94. 13. A. Borghesi, B. Pivac, A. Sassela, A. Stella, Oxygen precipitation in silicon, J. Appl. Phys. 77 (1995) 4169–4244. 14. W. Bergholz, D. Gilles, Impact of research on defects in silicon on the microelectronics industry, Phys. Status Solidi B 222 (2000) 5–23. 15. T. Sinno, E. Dornberger, W. von Ammon, R.A. Brown, F. Dupret, Defect engineering of Czochralski single-crystal silicon, Mater. Sci. Eng. 28 (2000) 149–198.

Properties of Silicon 16. J. Samuels, S.G. Roberts, The brittle-ductile transition in silicon. I. Experiments, P. Roy. Soc. Lond. A421 (1989) 1–23. 17. J. Rabier, J.J. Demenet, Low temperature, high stress plastic deformation of semiconductors: the silicon case, Phys. Status Solidi B 222 (2000) 63–74. 18. J. Vedde, P. Gravesen, The fracture strength of nitrogen doped silicon wafers, Mater. Sci. Eng. B36 (1996) 246–250. 19. K. Sumino, H. Harada, I. Yonenaga, The origin of the difference in the mechanical strengths of Czochralski grown silicon and ﬂoat-zone-grown silicon, Jpn. J. Appl. Phys. 19 (1980) L49–L52. 20. K. Sumino, I. Yonenaga, A. Yuasa, Mechanical strength of oxygen doped ﬂoat-zone silicon crystals, Jpn. J. Appl. Phys. 19 (1980) L763–L766. 21. I. Yonenaga, K. Sumino, K. Hoshi, Mechanical strength of silicon crystals as a function of the oxygen concentration, J. Appl. Phys. 56 (1984) 2346–2350.

22. H. Takeno, K. Aihara, Y. Hayamizu, T. Masui, Inﬂuence of rapid thermal annealing on thermal donor formation and oxygen precipitation in Czochralski silicon, in: T. Abe, W.M. Bullis, S. Kobayashi, W. Lin, P. Wagner (Eds.), Defects in Silicon III, Proceeding Volume 99-1, The Electrochemical Society, USA, 1999, 150–161. 23. G.S. Oehrlein, T.Y. Tan, R.L. Kleinhenz, J.L. Lindstrom, On the question of oxygen diffusion during oxygen related thermal donor formation in silicon, in: M. Wittmer, J. Stimmell, M. Strathman (Eds.), Materials Issues in Silicon Integrated Circuit Processing, Mater. Res. Soc. Symp. Proc., 71 (1986) 65–67. 24. S.M. Sze, Physics of Semiconductor Devices, Wiley, New York, 1981. 25. C.S. Smith, Piezoresistance effect in germanium and silicon, Phys. Rev. 94 (1954) 42–49. 26. E.V. Thomsen, J. Richter, Piezo Resistive MEMS Devices: Theory and Applications, Technical University of Denmark, Copenhagen, 2005.

CHAPTER 1

27. J. Richter, O. Hansen, A. Nylandsted Larsen, J. Lundsgaard Hansen, G.F. Eriksen, E.V. Thomsen, Piezoresistance of silicon and strained Si0.9Ge0.1, Sensor Actuat. A 123–124C (2005) 388–396. 28. H. Crazzolara, Hochauﬂösende piezoresistive Siliziumsensoren auf der basis halbleitertechnologischer standardprozesse, Doctoral thesis, Universität Stuttgart, 1994 (in German). 29. F. Laermer, Mechanical microsensors, in: J.G. Korvik, O. Paul (Eds.) MEMS: A Practical Guide to Design, Analysis, and Applications, W. Andrew Publishing, Norwich, NY, 2006. 30. Y. Kanda, Graphical representation of the piezoresistance coefﬁcients in silicon, IEEE T. Electron Dev. (1982) 64–70. 31. Fraunhofer Gesellschaft for Integrated Systems and Device Technology (IISB), Erlangen, Germany.

17

2

Chapter Two

Czochralski Growth of Silicon Crystals Olli Anttila Silfex Incorporated—A Division of Lam Research Corporation, Eaton, OH, USA

Czochralski (CZ) growth of silicon has been named after the Polish scientist Jan Czochralski, who in 1918 published his report on the growth of single-crystal metal ﬁlaments from melt [1]. The present method is largely attributable to Teal and Little and dates back to the early 1950s when it was not yet clear whether single-crystal semiconductor material would have any signiﬁcant advantage over polycrystalline materials and the material of choice was germanium more often than silicon [2–4]. The differences in the method devel oped by Teal and Little were so large compared with the original method by Czochralski that it would prob ably be more just to call it the Teal–Little method [4]. The existence of another method, zone reﬁning, that was originally used to purify germanium polycrystal line material for semiconductor applications and from which the ﬂoat-zone (FZ) method was developed, may have had an inﬂuence on the choice of the name of the method: The abbreviations form now a nice match. In this chapter, only CZ crystal growth is discussed. This is because CZ material dominates the industry by a large margin, crystal availability is good, modern tech niques also allow growth of high-resistivity silicon, and all commercial crystal sizes can be made with CZ tech nique. Only if very high-resistivity silicon (2–3 kΩcm) or silicon without dissolved oxygen is needed, FZ material should be used. Still today, the availability of the highest-purity FZ crystals in 200 mm diameter is limited. Those interested in learning more about the FZ technique should consult, for example, reviews of Dietze [5], Zulehner [6], or Mühlbauer [7]. In late 1950s, Dash signiﬁcantly improved the method of growing silicon crystals by adding a neck ing step to avoid dislocations [8]. This improvement is

routinely used for both CZ and FZ crystals. The role of this step is explained later in more detail. The CZ growth method has remained fundamentally unchanged since, and it is the workhorse that produces the vast majority of single-crystal silicon used even today, almost 50 years after its introduction. Major evolutionary steps have been made; for example, maximum crystal weights are several hundreds of kilograms, magnetic ﬁelds are applied for better control of the melt behavior, all imag inable quality requirements have been reviewed several times, and the productivity has experienced enormous improvements.

2.1 The CZ Crystal-Growing Furnace The CZ furnace is a vacuum furnace that consists of the following subassemblies: crucible lifting and rotat ing system, growth chamber that houses the hot zone (HZ), vacuum interlock, receiving chamber for the grown crystal, and crystal rotating and lifting sys tem. For more details, see Ref. [9], Figure 81 a and b. Modern CZ systems are able to grow crystals up to 450 mm in diameter, with charge sizes close to 500 kg. In MEMS applications, however, the maximum size of the crystal is 200 mm in diameter, and charge size may exceed 100 kg.

2.1.1 Crucible An essential part of CZ growth is that the single semi conductor crystal is pulled out of melt that is contained

19

PA R T I

Silicon as MEMS Material

in a refractory crucible. No solvent is used; that is, the melt consists of the same elements as the growing crys tal. In the case of silicon, the melt is almost pure ele mental silicon, at about 1420°C. The crucible and the crystal are both rotated, and the crystal is slowly pulled upwards in such a manner that a cylindrical body of desired diameter is achieved. Molten silicon reacts with all known materials to the extent that there are very few potential materials for a crucible [9]. The only available crucible material for high-quality crystals is silicon dioxide in its amorphous state, silica. A glimpse at the periodic table of the ele ments and the knowledge of the deleterious impact that most elements have on silicon material quality, even in very minute quantities, lead to only a few candidates. Almost all metals are excluded because the allowed concentrations are only in parts-per-trillion atomic (ppta) range. Group III and group V elements are elec trically active dopants that often may be tolerated to much higher levels, typically to parts-per-billion atomic (ppba) range, but this concentration is also far too low to allow crucibles to be made with compounds of these elements. Ceramic materials are excluded as well, either because they contain one of the aforementioned elements or because they contain other elements whose concentrations likewise must be held very low. Nitrogen (e.g., from silicon nitride crucible) is poorly soluble to the crystals, and the growing crystal tends to strongly reject it. The same applies to carbon. Concentrations of these elements in the melt are then highest very near the freezing interface, and as solubility is approached in the melt, there will be small particles nucleated that destroy the single-crystalline structure of the growing crystal. Furthermore, neither nitrogen nor even less so carbon is allowed in the crystal in levels even close to their solubilities, though nitrogen is sometimes inten tionally introduced into the material, especially for FZ crystals. However, this topic will not be pursued any further here. The situation with oxygen is, fortunately, different. Oxygen is allowed in the crystal in a fairly large concen tration, typically in 10 parts-per-million atomic (ppma) range; and in most applications for silicon wafers, oxy gen is a desired element, in controlled quantities, with clear beneﬁcial effects. Furthermore, oxygen does not tend to be rejected by the crystal; that is, its segregation coefﬁcient is close to unity [10], and there is no risk of oxide particles being created near the freezing interface. In addition to this, silicon has a volatile oxide, contrary to its carbides and nitrides: At high temperatures, in an oxygen-lean environment, silicon tends to form silicon monoxide rather than silicon dioxide. This monoxide is easily volatilizable, with vapor pressure of about 12 mbar at silicon melting temperature [6]. In practice, the vast majority (98–99%) of oxygen that is being dissolved 20

from the silica crucible wall by the highly reactive sili con melt will be evaporated into the grower atmosphere and purged away by the inert gas ﬂow that is mandatory for successful growth. Only 1–2% of the dissolved oxy gen ends up in the growing crystal itself. The introduction of the reactive silicon monoxide to the otherwise inert gas ﬂow is a major factor that causes unwanted reactions on the hot surfaces around the cru cible and melt. The gas ﬂow patterns inside the grower must be designed to take the potentially harmful effects of monoxide into account, especially as the quantity of oxy gen released into the gas ﬂow over one growth may be in the range of hundreds of grams in today’s large furnaces.

2.1.2 Hot-Zone Materials The basic building material for a HZ for silicon CZ crys tal growth is high-purity graphite. The term “hot zone” is used in this book to deﬁne the structural and insulating parts inside of the vacuum compatible chamber of a crys tal grower, which parts are essential in creating a proper temperature distribution around the semiconductor melt and the growing crystal. Furthermore, HZ design largely deﬁnes purge gas ﬂow patterns inside the grower. Graphite is the material of choice because of its good availability as large blocks, its machinability, as well as its high temperature characteristics. Carbon in the form of diamond or graphite has the highest melting point of any element or almost any chemical compound. The mate rial is reasonably strong, especially at high temperatures. It is also a fairly good conductor of electricity and heat. Its electrical conductivity makes it suitable as heater material, and its thermal conductivity is often desirable, as heat needs to be transported from the heater(s) to the crucible and elsewhere inside the HZ. However, radia tion is typically the dominant mode of heat transfer at these high temperatures, especially over long distances. The most commonly used insulator material is graph ite felt, in different forms. The felt is made out of thin ﬁbers, which act as insulation as they block thermal radiation many times over a short distance. Soft felt is woven into a relatively thin sheet of material, which may then be cut into desired shapes and bent over reasonably tight radii. Rigid felt is made of originally similar ﬁber material, but a carbon-containing binder is used to tie the separate ﬁbers to a more solid, self-supporting body. Instead of a binder, chemical vapor deposition (CVD) of carbon may also be used to enhance the mechanical per formance of the material. Oftentimes, the outer surfaces of rigid felt insulation are coated with a more continu ous layer of graphite paint or foil, to reduce erosion and wear as well as particulate contamination. Other types of carbon-based insulation also exist, such as carbon foam. Generally, graphitized materials are clearly preferred,

Czochralski Growth of Silicon Crystals

as graphitization reduces drastically the surface area of the ﬁbers. Therefore, it is much less time consuming to pump a grower into a proper vacuum, as outgassing from these high-surface-area materials is signiﬁcantly reduced. The graphite parts are manufactured initially from ﬁne carboneous particles that are mixed with a carbo neous binder to form a mass that can be molded either by extrusion or in an isostatic press. Higher-quality parts are typically isostatically pressed. The molded blocks are ﬁrst carbonized and ﬁnally graphitized at very high tem perature, close to 3000°C. The parts that are machined out of these blocks are typically puriﬁed in a halogencontaining atmosphere at an elevated temperature to remove metallic contamination in order to comply with requirements by the semiconductor industry. However, even after proper puriﬁcation, the metal contamina tion levels are several orders of magnitude higher than what is allowed for silicon single-crystal material. Care must therefore be taken in the hot-zone design to pre vent contamination from these parts from accessing the melt or the crystal surface. The graphite material is also slightly porous, which makes it possible for the remain ing metals deep inside to reach the surfaces fairly eas ily. Furthermore, silicon monoxide that is present in the purge gas around the graphite surfaces is able to pene trate deep into the bulk of material and react there. Many other materials are used to create HZs. Carbon-ﬁber-reinforced graphite (CFC) is mechanically much stronger; but it is also more expensive and poses more limitations to the design. Silicon carbide (SiC) is in many respects a better-performing material than graph ite; but it has signiﬁcantly higher cost, and large-sized components’ availability is poor. However, SiC is often used as a CVD coating to enhance the lifetime of graph ite parts that are exposed to corrosive silicon monoxide, or to reduce contamination from graphite. The dense CVD coating effectively blocks contaminants inside of the slightly porous graphite material from getting to the surface. Another possibility is CVD carbon, which also forms a very dense layer on top of a graphite part. Other high-temperature refractory materials, such as molybde num or ceramic materials that are compatible with the environment, may be used in locations where there is no risk of contamination to the melt. Molybdenum is often used because of its moderately high cost, as well as its low diffusivity into silicon crystal and its very low segregation coefﬁcient of about 5*10-8 [11], which allows substantial molybdenum contamination in the melt before damaging concentration may enter into the crystal.

2.1.3 Hot-Zone Structure A traditional HZ, as shown in Figure 2.1, contains a

graphite susceptor around the silica crucible (which is

CHAPTER 2

Neck Graphite heater Crystal Silica crucible Meniscus Melt Graphite susceptor Heat shield Spill tray

Fig 2.1 ● Basic HZ structure. The melt is contained in a silica crucible, out of which the crystal is slowly pulled. Around the heater there are insulating elements to reduce heat losses, and a spill tray is located below the melt to collect the melt in case the crucible were to break. Modern HZs may be considerably more complex.

often called quartz crucible), a cylindrical heater, and a heat shield around and below the heater. The susceptor is required because the high temperature causes the crucible to soften, and a proper mechanical support is therefore needed. The susceptor also helps distrib ute heat around the silica crucible a little bit more uniformly. The heater is usually connected to two or four elec trodes at its lower edge, typically by some kind of sup porting elements also made of graphite. The electrodes deliver the required power, which is at least tens of kWs, but often well exceeds 100 kW. The heater is nor mally of picket type, which means that it has vertical slits cut into it in a manner that forces the electric cur rent ﬂow up and down, in opposite directions in neigh boring pickets (see Figure 2.4). The voltage is quite low and amperage is high, mainly because of the high elec trical conductance of the heater, but also because of the poor electrical insulation properties of the inert gas at the low pressure and high temperature normally used in silicon CZ growth. A heater would radiate approximately 400 kW per square meter, at silicon melting point with no insula tion around the HZ. The heat shield drastically reduces the power consumption, and it also helps create a more proper temperature distribution around the susceptor. The insulation itself is usually supported and shielded by structural graphite parts, but these graphite parts have much less impact on the temperature distribution. Typically, only a small fraction of the total power fed to the heater is lost through the insulation. Careful design is needed to control heat losses through such struc tural parts that extend through the insulation, such as the heater supports, as well as at all openings that are needed, including the additional open spaces around 21

PA R T I

Silicon as MEMS Material

the heater supports and any openings for gas ﬂows. Structural parts stretching through the insulation may easily lead to several, or even more than ten kW’s, of additional power losses per such part, and more poorly controlled temperature distribution usually will result. Under the heater there is a so-called spill tray whose function is damage containment in the unfortunate event that the crucible should break while there is melt inside. This is a rare, but risky, situation, as the molten silicon is capable of making its way through the walls of the water-cooled vacuum chamber. Should this happen, there is a signiﬁcant risk of dangerous steam explosion. The role of the spill tray is to collect all mol ten silicon and stop it before it makes contact with the stainless surfaces of the chamber or damages the expen sive mechanisms lower in the grower that are respons ible for crucible rotation and lift.

2.1.4 Gas Flow Silicon CZ growth takes place under a continuous ﬂow of inert gas. A schematic picture of the gas ﬂow pattern is shown in Figure 2.2. Considering the high tempera ture and the reactivity of silicon melt, noble gases are the only ones allowed. Argon is the gas of choice because of its much lower cost than that of other noble gases. Argon has also the advantage of poor thermal conductivity

low pressure argon gas

silica crucible

Si crystal

SiO

Si melt O from crucible

graphite heater

graphite support

Fig 2.2 ● Schematic picture of inert purge gas ﬂow. Oxygen is dissolved from the crucible, and the purge gas removes volatile silicon monoxide from the vicinity of the melt and the crystal. Only a small fraction of total dissolved oxygen ends up in the growing crystal.

22

compared with, for example, helium, and this feature facilitates the effort to insulate hot areas around the melt from the water-cooled vacuum-chamber walls. However, helium remains an option in situations where more efﬁ cient cooling is desirable, for example, to enhance cool ing of the grower after the power has been shut off. Typical gas pressure is in the15–50 mbar range, and gas ﬂow is in the tens to more than 100 standardliters-per-minute (slpm) range. Lowered pressure is used to reduce gas consumption relative to atmos pheric growth. As an example, if the process is running at 60 slpm/25mbar and the receiving chamber of the grower has an inner diameter of 12 inches, the result ing gas velocity in that part of the grower would be 0.5–0.6 m/s, which is enough to ensure clean laminar ﬂow. However, larger pressure would require also a larger mass ﬂow of purge gas, to maintain a ﬂow pattern that would not be overly inﬂuenced by temperature dif ferences in the gas and to avoid undesired thermal con vection. Furthermore, the oxygen containing gas that evaporates from the melt must be transported away in a controlled manner, which requires sufﬁcient volume ﬂow and gas velocity. The reduced pressure also helps with the insulation to a certain degree. The practi cal lower limit is close to 12 mbar, which is the vapor pressure of silicon monoxide in equilibrium with silicon melt at melting point [9]. The monoxide concentration of the melt is close to saturation near the silica crucible wall, where the temperature is also typically a few tens of degrees higher than the melting point. If the pressure is lowered too much, the melt starts to “boil,” as the gas pressure is no longer sufﬁcient to prevent monoxide from escaping in a manner not unlike boiling water. In a traditional HZ, there is a large open space above the melt, which space is limited from above by the water-cooled chamber walls. This large continuous space allows uncontrolled convection to take place as the gas experiences heating from below, and the hot ter and lighter gas wants to travel upwards, against the incoming gas ﬂow. Silicon monoxide from the melt, traveling with this convection and meeting with the chamber wall, condenses on the cool surface. There are also other surfaces above the melt that are not quite that cold, but cool enough for monoxide to deposit. These layers threaten to cause macroscopic particles to fall back into the melt, with a high risk of destroying the single crystalline structure of the growing crystal. Such poorly controlled gas ﬂows also tend to bring in other contamination, such as carbon, from the exposed surfaces of the HZ. There is also a more subtle mechanism through which the evaporating silicon monoxide risks killing the crystal. The saturation vapor pressure of the mon oxide is strongly dependent on the gas temperature. As the monoxide containing gas travels upwards, it cools

Czochralski Growth of Silicon Crystals

down, and tiny monoxide particles are formed. (It is not clear whether these particles are really made of sili con monoxide or whether the composition is rather a very-ﬁne-grained mixture of silicon dioxide and elemen tal silicon.) The poor control of gas ﬂow allows a part of this cloud of tiny particles to go back down towards the melt, and some of them may survive the hotter con ditions until they make contact with the melt surface very close to the freezing interface. Marangoni convec tion (see Section 2.6.4) then takes the particles directly to the crystal, again with a chance of loss of structure.

2.2 Stages of Growth Process The ﬁrst step of a growth run is to charge the silicon into the crucible. Silicon is normally stored in clean double bags, about 5 kg in a bag, though larger contain ers may also be used. Double bags also make it possible to remove the outer bag separately before bringing the bags into the charging area, to reduce any contamination that could be transported into the crucible. The cruci ble may be charged as it already sits inside the grower. In order to save time at the grower and also to avoid contamination, the charge may be prepared in a sepa rate area, after which the full crucible, with or without the graphite susceptor, is transported to the grower and lifted into place. Handling of a full crucible is challeng ing, as its weight varies from tens to hundreds of kgs, depending on hot-zone size; the material is hard and brittle, allowing no shocks or scratching; and contami nation is an eternal foe. The way in which different sizes of silicon pieces are stacked into the crucible is an art of its own kind. During the time that the temperature is raised, the charge experiences signiﬁcant thermal expansion. However, dimensions of the silica crucible remain almost unchanged. There is a clear risk that the expanding charge will chip or even crack the crucible if large chunks are stacked without sufﬁcient caution. Furthermore, the charge takes a considerably larger space before than after it has molten. Normally, the charge extends well above the rim of the crucible, but after melting the crucible is less than two-thirds full. There may be some “hangers” on the walls: chunks that remain attached to the walls; and some of them may interfere with the growth or may chip the cruci ble before falling down. These hangers remain cooler than the crucible, as they are free to radiate heat to the empty space above. Very high power, which could cause the crucible wall to soften and sag, would be required to make them lose contact. Careful stacking of the charge reduces the risk of problematic hanger formation. The batch melts starting from the edges, and a high col umn of silicon chunks, which are fused together, often

CHAPTER 2

forms. This column may create a considerable splash as it falls down. Furthermore, problems in stacking and how the melting is performed may result in a bridge in which the batch is molten from below in such a way that a layer of fused chunks remains connected to the walls, high above the melt level. As this bridge plunges, a severe splash may result. A crack in the crucible is always a serious situa tion, and its consequences must be taken into account in the design of the HZ as well as in the process con siderations. Silicon melt is very ﬂuid and wets various surfaces, and that is why it is capable of penetrating through narrow holes and gaps. Therefore, even though a hole or a crack in the crucible is a rare or very rare occasion, most HZs are designed to take the full silicon or almost full silicon charge into the spill tray. The HZ and silicon melt are both sensitive to any oxidizing components in the surrounding gas, and that is why the growth takes place in inert gas ambient, and at reduced pressure. The growth chamber must there fore be highly vacuum proof, and it must be properly evacuated and purged before the temperature may be raised. Oftentimes a leak test is performed at this stage: The purge gas ﬂow is shut down, the chamber is evacu ated further, vacuum valves are closed, and the pressure in the chamber is monitored. The process is allowed to continue only if the leak rate is under a predetermined level. This is done to ensure that there are no leaks in the system that could introduce air, and thus contami nation, into the melt and the surroundings during the long process hours. Another policy is to perform a leak test after the growth. This kind of test may use tighter acceptance values, as there are no fresh materials that could outgas in the chamber. Therefore, this kind of leak test better ensures the overall vacuum compatibility of the system; and furthermore, the overall cycle time is somewhat shortened. As there is seldom the need to open more than a couple of vacuum seals to remove the grown crystal, clean the furnace, and charge it again, this approach is quite valid, as those seals are carefully cleaned before the furnace is closed for a new run.

2.2.1 Melting The next step, melting, takes a few hours, during which the temperature inside of the HZ is ﬁrst brought to close to 1500°C, and then maintained there to bring enough heat to fully melt the batch. The temperature margin is not very wide, as the silica crucible is already quite soft at those temperatures, and excessive heat is avoided in order to prevent the crucible walls from sagging. Furthermore, the hottest area of the crucible, typically the low corner area, will start to wear as soon as it is in contact with the melt. Excessive heat would enhance the wear and shorten the useful time available 23

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before the material is so worn that difﬁculties are cre ated in maintaining the dislocation-free (DF) structure of the crystal, later in the process. After the whole batch is molten the crucible is lifted to the desired starting position, which is typically higher up than during the meltdown. The temperature is then stabilized to close to the preferred temperature, based on experience about previous growths, and the seed crystal is ready to be dipped. The stabilization of the temperature is customarily controlled by a two-color pyrometer that senses the surface temperature close to where the seed will be dipped.

2.2.2 Neck At the right temperature, the end of the seed will melt away and a meniscus (see Section 2.3.1) will form. As the seed is slowly pulled upwards, new material will be crystallized in the end of the seed, obeying the original crystal structure. The seed is usually not DF at this point, as the temperature shock caused by the contact to the melt tends to create dislocations even if the original seed was free of them. That is why a necking step normally follows (see Figure 2.3), and the same seed may be used over and over again without excessive concerns about whether the DF structure is maintained or not. The basic idea in the necking step, originally intro duced by Dash in the late 1950s [8], is that disloca tions have limited mobility in silicon, and if the crystal is grown rapidly and thin enough, the dislocations will grow out from the sides of the neck and eventually be frozen and excluded from the material. There are a few requirements for this to happen. The dislocations in sili con have a preferred axis in a 110 direction. Should one try to grow a neck of uniform thickness to this crys tal orientation, some of the dislocations would have no difﬁculty in staying within the neck; they would simply

Fig 2.3 ● Neck, crown, and beginning of the body of a crystal. Around the crystal a bright ring, or meniscus, is visible. It is used to control the diameter of the crystal.

24

grow in length together with the neck. The more the growth axis deviates from the nearest 110 direc tion, the easier it will be to get rid of dislocations. That is why other common crystal orientations, (100) and (111), are relatively easy to grow DF, but growth of DF (110) material is much more challenging. The other requirements are that thermal stresses are low, pull speed is high, and to sum up, that the rate of climb of dislocations in the direction of the neck axis remains smaller than the pull rate. A thin neck combined with low thermal gradient reduces stress. The climb, which is essentially silicon interstitials (or vacancies) attaching to the edge of the additional atomic plane, which edge forms the dislocation line proper, is a much slower process than slip. Slip often occurs when silicon wafers are processed, or in the crystal if the DF structure is lost, and also in the end of the tailing step (see Section 2.2.5) as the crystal is detached from the melt. High pull speed also favors silicon vacancies, which slows down the climb towards the melt interface. Pull speed of the order of 3 mm/min is usually ade quate, the thickness seldom much exceeds 4 mm, and a few cm’s in the proper speed/diameter range sufﬁces. The crystals used for today’s bulk MEMS applications are still lightweight enough that a regular Dash neck is applicable to orientations other than (110). However, crystals used for IC applications may be so heavy that a standard neck would no longer be able to carry the weight of the crystal. Several approaches have been used to address this issue, such as enabling the use of a thicker neck, constructing an additional means to sup port the weight, or developing ways to grow DF crystals without any necking procedure at all. However, these approaches are beyond the scope of this book. There exists some confusion about the density of dislocations in CZ silicon crystals. Because of histori cal reasons, speciﬁcations often allow nonzero disloca tion density, for example, less than 100 count/cm2; however, today it is much easier to grow large crystals that contain zero dislocations than it is to grow crystals that contain a small but nonzero number of them. The neck is an effective means of eliminating all linear dis locations from the material, and it is more difﬁcult to create the ﬁrst dislocation into DF material than for an existing one to multiply to a large number. Oftentimes, the neck is grown longer than would actually be required for DF structure. This adds a cer tain safeguard to the quality of material in the end of the neck, but the primary reason for doing this is related to the often slow thermal response of the system: It is desirable that the melt temperature in the beginning of the next step, the crown, is correct to about 1°C. The thin neck acts as a very reproducible temperature sen sor, better than the pyrometers used in the instrumen tation. As soon as the neck diameter and average growth

Czochralski Growth of Silicon Crystals

rate have reached the desired window for a sufﬁcient time, the temperature is also correct.

2.2.3 Crown When the proper length of the neck as well as the right temperature have been reached, the crown is started. Pull speed and temperature are lowered, crystal and crucible rotation speeds may be changed, and melt level may also be adjusted gradually. The purpose is to create suitable conditions in which the crystal acquires diam eter at a proper pace: Too slow results in an unnecessar ily long process time as well as increased probability of structure loss, as the melt is also warmer and therefore less stable than is optimal; on the other hand, too large a growth rate results in structure loss, as the too-cool melt causes an uncontrollable growth rate in some crys tal orientations. The larger the diameter of the crown, the cooler must the melt also be, and that is why there is a con tinual decrease in the heater power/temperature. The typical temperature difference between the end of the necking step and the beginning of the full diameter body is several tens of degrees Centigrade, and most of that is needed during the crown. On the melt surface, diameter increase may be observed (see Figure 2.3), but there are also things tak ing place under the surface, which we cannot see. The freezing interface usually becomes increasingly con vex towards the melt, and that shape has a signiﬁcant impact on the chances of success of the crown and sub sequent steps. A very slow pull speed in crown results in a ﬂat crown shape that is economical when it comes to the usage of original silicon material in the charge. However, the freezing interface then tends to be highly convex, and as it tends to be fairly straight or even con cave in the body, the shape of the freezing interface needs to experience a very signiﬁcant change towards the end of the crown and the beginning of the body. The actual speeds of crystallization near the center axis of the crystal and near the edge will then be very dif ferent, and the loss of structure will be more probable than if those speeds are close to each other. Especially in the case of material doped heavily with antimony or other volatile n-type dopants (which is, in general, more difﬁcult to grow than lightly doped or heavily borondoped material), this change of interface shape may easily be fatal for the crystal. Why this should be so is, however, beyond the scope of this book. On the other hand, if the diameter growth rate is kept small and the pull speed relatively high, the crown shape will be more conical and the freezing interface will experience a smaller change towards the body. This will make it easier to make the transition to the body, but at the cost

CHAPTER 2

of more time spent and poorer silicon material usage. That is why a suitable tradeoff is chosen, with a high probability of success for the crown and early phases of the body, but with as little time and material spent as feasible.

2.2.4 Body The cylindrical part of the crystal, out of which the actual wafers will be fabricated, is called the body. Between this section and the crown there is a transitory period that is sometimes called transition and some times shoulder. The shoulder is started a little before the desired diameter for the body is reached, and the pull speed is raised signiﬁcantly. This cuts the growth in the diameter over a relatively short distance, and ideally the growth turns vertical at the same diameter as is cho sen for the body. At that point, the pull speed is low ered again, to match that of the early body. If the pull speed of the transition is maintained high for too long, the diameter of the crystal will start to diminish again. After completion of the shoulder, the body is started. At this point, some further temperature drop is usually needed, but after a while, the temperature changes will be slow. Diameter is controlled through instantaneous pull speed, most often by using a PID (proportional integrating-derivative) control loop that needs to be tuned properly, and average pull speed is maintained by adjusting the heater power, or temperature. If there is a bottom heater or other additional heaters, their power may be changed in a predetermined manner; or there may be instrumentation to measure the temperature, and a predetermined proﬁle may be followed. Gas ﬂow, pressure, as well as crucible and crystal rotation rates are among the controllable parameters along the body length, and there may be more, such as strength and shape of a magnetic ﬁeld, melt level, etc.

2.2.5 Tail In the end of the body, a signiﬁcant portion of the melt is still remaining, typically at least 10% of the original charge, though in some applications this portion may be smaller. A part of this remaining melt is used to form a so-called tail. This section of the crystal is needed for two purposes: First, there will be thermal shock that will almost inevitably introduce slip dislocations as the crystal is detached from the melt. This slip will proceed a shorter distance upwards than if the growth would have been disrupted at full diameter. In addition, a smaller volume of melt is consumed to produce a tail than to produce a corresponding length of full diameter. Altogether, a longer DF body can be produced from the same amount of melt. Secondly, there may be a desire 25

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to achieve a more uniform thermal history to the end of the body, more comparable to the other parts of the body. Should the crystal be detached at full diameter, the end portion would cool down much more rapidly than if a long tail is grown.

2.2.6 Shut-Off After the tail is complete, power to the heater(s) may be shut off and the crystal pulled into the receiving chamber to cool down. However, the lower end of the crystal may be left to stay for a while inside the HZ, while the power is ramped down slowly, according to a suitable proﬁle followed in order to produce a desired thermal history of the crystal, especially to the last few tens of cms of the body. After the crystal has cooled down sufﬁciently, it is removed from the receiving chamber. This normally happens before the HZ is cold enough that it may be opened for cleaning and recharging, and for a new crys tal to be grown. Cooling of the HZ may be enhanced to save process time, for example, by moving parts inside of the chamber to allow for a more effective escape of heat; by purging the system with a suitable high-volume gas ﬂow; or by adding, for instance, helium into the chamber. The cleaning involves removal of the used crucible and the frozen residual melt (also called pot scrap), vacuuming any silicon-monoxide-containing dust from the surfaces, potential replacement of worn parts, and checking of overall condition of the HZ parts.

2.3 Issues of Crystal Growth In the following sections, diameter control, doping, and HZ lifetime are discussed.

2.3.1 Diameter Control There is a clear-cut balance between the growth rate of the crystal and thermal gradients on both sides of the freezing interface. The growing crystal needs to be cooled, mainly through radiation, and to some extent also by the purge gas ﬂow. Near the freezing interface, the heat ﬂux density can be taken to be equal to the magnitude of thermal gradient times thermal conductiv ity, on both sides of the interface. However, the solidiﬁ cation process releases heat at a rate that is equal to the speed of crystallization times latent heat. In a balanced situation, the external pull speed of the crystal is equal to the rate of solidiﬁcation, and the thermal ﬂux density on the crystal side is larger than that on the melt side by the amount released in the crystallization process. The crystal then tends to grow, maintaining its diameter, at 26

least averaged over time. The time-dependent processes in the melt make temperature gradients at the melt side vary over time, which creates striations to the crystal (see Figure 2.5), but as long as the balance is maintained averaged over time, no major difﬁculties should occur in the diameter control. The crystal diameter is almost always measured opti cally. The melting point of silicon is high enough to give ample intensity for optical measurements, and in prac tice, most of the available light and infrared radiation are ﬁltered out. A traditional way was to observe the bright ring, known as the meniscus, around the crystal with a pyrometer that was focused on a small spot in such a manner that an increase in diameter resulted in a larger signal, as the more radiant meniscus and the lower end of the crystal were taking a larger portion of the spot. More modern measurements rely on video feed that is processed to give either the chord length, obtained by measuring the locations of two points at the meniscus, or several point locations that are iden tiﬁed and a best-ﬁt calculation performed to get the diameter of the meniscus. The luminousness of the meniscus (Figure 2.3) is caused by the reﬂection of light from the melt surface at locations where the surface is curved upwards in such a way that the hotter crucible wall is reﬂected to the eye of an observer. The bound ary between solid and molten material is very difﬁcult to distinguish. The diameter is then measured at some suitable location in that meniscus, a few mms outside of the crystal edge. The physical properties of elemental silicon deﬁne what is known as wetting angle, whose magnitude is 11°: This is the angle between the edge of the growing (verti cal) silicon crystal and the melt, very close to the triple point (edge of the crystal at the solid–melt interface). As the crystal edge is vertical, the melt also turns almost vertically upwards to meet the solid, since the melt has quite a large afﬁnity to the solid. The edge of the freez ing interface is located as much as about 7 mm above the melt level, as measured a couple of cms outside the crystal. The balance between the surface tension of the melt and gravity dictates the shape of the interface near the crystal, that is, the shape of the meniscus. Should there be a need to adjust the diameter, the most commonly used approach is to change the exter nal pull speed. For instance, if the diameter is too large, an increase in the pull speed will begin to change the diameter within a few tens of seconds to a few minutes. However, the increased pull speed does not immedi ately change the speed of crystallization, as it is dictated by thermal balance. In order for the crystal-melt system to adapt to the new situation, three alternatives are pos sible: (1) Heat transfer at the crystal side of the inter face could be enhanced. However, if no changes take place there, this does not happen by itself. (2) Heat

Czochralski Growth of Silicon Crystals

transfer at the melt side could be lowered, but again, no intentional changes are made there. (3) The production of latent heat may be brought back to the original value. As the heat produced at the interface equals the speed of solidiﬁcation times latent heat times the surface area of the freezing interface, the increased pull speed results in decreased diameter. Should the average pull speed, after proper control of the diameter has been established, be off from the tar get, slower means of control are used. The target speed is typically in the 1 mm/min range, depending on the crystal diameter (larger crystals grow more slowly), HZ design (cooler environment experienced by the crys tal allows larger growth rate), and quality issues. Some crystals are grown slowly to establish a suitable balance between growth rate and thermal gradients, which bal ance has an impact on very small vacancy-related defects, known as COPs, in dense IC circuits [12]. A crystal grows more rapidly from a cool melt, and this is again caused by the requirement of thermal balance: Colder melt delivers less heat to the freezing interface, and more heat may then be produced by the crystallization process. Change of the melt temperature has therefore an impact to the average growth rate, the average taken over sev eral tens of minutes. There is a pyrometer watching the heater temperature(s), and a change in that temperature also changes the melt temperature after a signiﬁcant delay. Another possibility is to change the heater power. There are a couple of other possibilities that have a speedier inﬂuence on the thermal balance, to control either diameter or the average pull speed, but these approaches are more seldom used. Thermal radiation at the crystal side may be changed by adding a heater, halogen, or IR lamps [13]; by other means of introduc ing energy to the crystal; or by changing its thermal environment in a more passive way. At the melt side, transport of heat from crucible wall towards the freez ing interface may be changed, for instance, through small changes in crucible rotation rate or magnetic ﬁeld. These measures are faster than control through heater power or temperature, but also more complicated, as these other possible control parameters must also be kept close to their desired average values.

2.3.2 Doping Most material used for MEMS applications is lightly doped with boron or phosphorus, up to a few tens of Ωcm. This corresponds to 1015–1016 dopant atoms/cm3, which translates to only mgs of elemental dopant to a charge of tens of kgs or more. A small quantity like this is very difﬁcult to allot in a consistent manner, and therefore the dopant is usually introduced as-diluted to a larger amount of silicon. A suitable amount of dopant

CHAPTER 2

element may be melted together with silicon to make an alloy in which the dopant concentration is in the 0.01– 0.1% range. If this alloy is prepared carefully so that the concentration is uniform, a very convenient amount of alloy may be mixed with the silicon charge to result in a reproducible concentration in the melt. There is a further advantage in using silicon alloy to introduce the dopant: Very little of the dopant will be able to vaporize during the melting of the charge. In mass production of silicon crystals, this alloy is usually prepared in a very simple manner: A very heav ily doped single crystal is grown, its resistivity proﬁle is measured, and wafers cut from this crystal are used to introduce dopant into hundreds of lightly doped crystals. Low resistivity crystals are usually doped using ele mental dopants. Boron is essentially nonvolatile, and it may be introduced into the charge at the same time as the silicon chunks are laid into the crucible. However, the common n-type dopants antimony, arsenic, and phosphorus are highly volatile, and they are prefer ably put in only after the charge is molten. Antimony is relatively simple to pour into the melt, as it is readily available in granular form; that is, it ﬂows easily from and through various cups and channels, and its density is high enough to take it into the bottom of the melt, with little evaporation or splashing. Arsenic and phos phorus, on the other hand, tend to volatilize at or above the melt, and a signiﬁcant portion may be lost into the purge gas ﬂow. This adds costs, as more dopant will be needed; there will be more dirt in the system, adding to chances of particles and yield losses; and the repro ducibility of the amount of the dopant in the melt will be poorer. Furthermore, there will be added hazards to the cleaning of the equipment because of the additional burden posed by the superﬂuous dopant in the vacuum lines and on other cool surfaces. Various approaches have been developed to introduce these dopants into the melt in a more efﬁcient and cleaner manner. The volatile n-type dopants normally reduce oxy gen concentration in the grown crystals, as oxygen in the melt is depleted more efﬁciently near the gas–melt interface. Volatile oxides of the dopant are carried away by the purge gas just as oxygen is carried as silicon mon oxide, adding to loss of oxygen. The faster evaporation rate of oxygen tends to increase the wear rate of the crucible, and extra care must be taken not to exceed the useful lifetime of the crucible. These dopants have also some effect on surface tension and therefore to the melt ﬂows near the melt surface (see Section 2.6.4).

2.3.3 HZ Lifetime HZ materials have only a limited lifetime, partly

because of high temperatures and partly because of the

27

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Silicon as MEMS Material

Fig 2.4 ● Worn heater after tens or a few hundreds of crystal growth cycles. Silicon monoxide evaporating from the silicon melt reacts with carbon in the heater, attacking the hottest parts ﬁrst.

corrosive action of silicon monoxide. The heater and the susceptor are those parts that typically suffer most rapidly. The heater is sensitized because it runs at a higher temperature than other parts of the HZ, and that is why the reactions with monoxide have the largest impact on it. Furthermore, its picket structure allows gas to attack it from several directions simultaneously, whereas, for example, the cylindrical heat shield made of graphite (sometimes called the heat-shield liner if the insulat ing part is called the heat shield) is attacked only from the inside. The resistivity distribution of the heater is also of major importance. The erosion is normally not uniform, and the power distribution of the heater then changes with its age (Figure 2.4), causing quality and yield problems. In a traditional HZ design, the purge gas, which contains also the corrosive silicon monoxide, is sucked down around the crucible and through and around the heater. Further downstream, the reactivity of the gas has already been reduced. The lifetime of a heater may be as short as just twenty crystals, but with more sophisticated designs, it may be hundreds of crys tals or more. The susceptor is also enclosed in the hottest part of the furnace. Even though its temperature is not quite as hot as that of the heater, the susceptor is mechanically more strained. The main stress is experienced during cooling at the end of the cycle, as the susceptor mate rial starts shrinking when the temperature goes down. However, the coefﬁcient of the thermal expansion of the silica crucible is extremely small, only about onetenth of that of the susceptor material. During the time the temperature was close to the silicon melting point, the crucible was soft enough to have accommodated 28

the shape of the susceptor. During the early part of the cooling, the crucible hardened again, but the susceptor tended to shrink a further couple of mms. This cycle exposes the susceptor to tremendous stress. In order to alleviate the problem, the susceptor is normally cut to several (usually, three) sections. The cuts allow separate sections to move independently. However, in addition to reduced mechanical strength, there is also a further price to pay for this. The intimate contact between the silica crucible and the graphite susceptor, together with the high tempera ture, makes graphite and silica react to form carbon and silicon monoxides, which are both volatile. This reac tion wears the material in locations where there are easy escape paths for the gases and the temperature is the highest. Typically, the wear is the fastest in the vicin ity of the cuts performed to allow susceptor sections to move relative to each other. Furthermore, the result ant production of carbon monoxide creates a signiﬁcant risk of carbon contamination, as the source is close to the melt.

2.4 Improved Thermal and Gas Flow Designs The CZ process has to be designed in such a way that energy consumption is minimized, HZ lifetime is maxi mized, and the crystal quality is good and repeatable. Modeling methods are indispensable in achieving these goals. Modern HZs utilize such structures above the melt that cut direct visibility between the hot crucible wall and the growing crystal, except for the ﬁrst few cms of the crystal above the melt [18]. This allows for bet ter control of the temperature distribution in the crys tal. Temperature gradients over the freezing interface experience smaller variations. Furthermore, growth rate in the body can be made essentially independent of the location in the crystal, contrary to traditional HZs, where achievable growth rates decline towards the end of the body, as the hot crucible rises gradu ally. All this gives a better and more reproducible qual ity. Furthermore, the freezing interface can be made straighter, and thermal stresses in the growing body are smaller, resulting in better growth yields. At the same time, there is a signiﬁcant reduction in power consumption as the earlier intense heat loss from the surface of the melt and the upper parts of the HZ is reduced. The improved thermal insulation results in enhanced lifetimes of the HZ parts, as maximum tem peratures inside the HZ are lowered and the wear of different parts becomes slower and more uniform. The stability of the whole process is further enhanced by the

Czochralski Growth of Silicon Crystals

fact that improved insulation results in a situation where the temperature distribution becomes less dependent on where in the heater the heat is actually produced. In addition to thermal design, any structure above the melt must also be optimized for gas ﬂows. The three main goals for better gas ﬂow conﬁguration, in addi tion to contributing to control of oxygen in the growing crystal, are to reduce the risk of particle formation in such locations, from where a particle may end up in the melt; to protect the melt from gaseous contamination; and to protect the most critical HZ parts from the cor rosive action of the purge gas, after the gas has passed the melt surface. Aforementioned structures that help optimize the temperature distribution around the crystal may also serve to create more laminar gas-ﬂow patterns near the crystal and melt surfaces. However, as it is advantageous to go fairly close to the melt with such structures that help modify temperature distribution, a rule of thumb being that one should go to about one-quarter diame ter of the growing crystal from the melt or even signiﬁ cantly closer, this may be somewhat too close to allow proper gas-ﬂow control near the melt surface. Various schemes have been envisioned to give more independ ence between gas ﬂows near the melt surface and ther mal design in the same area. After the gas has passed by the melt surface and exited the crucible, it will unavoidably hit some hot surfaces and react there (unless some very expensive materials are being used). The resulting carbon monox ide will not get back into the melt if the gas ﬂow is kept laminar after leaving the crucible. However, in order to extend the lifetimes of the heater, the susceptor, and other expensive hot-zone parts, it is preferable that the contact of the gas with these part be kept to a mini mum. Various approaches are available, which, however, all add to the complexity of the hot-zone design.

2.5 Heat Transfer There are three signiﬁcant modes of heat transfer that operate during silicon crystal growth: conduction, con vection, and radiation. Radiation is of major signiﬁcance between sur faces that are separated from each other by a physical gap, but between which there is direct visibility. Most materials that are being utilized absorb heat so efﬁ ciently that heat transferred by reﬂected radiation is less signiﬁcant; but, especially over the melt, it cannot be neglected. The importance of thermal radiation is enhanced by its strong dependence on temperature: the Stefan–Boltzmann law tells us that the radiant power density is proportional to the fourth power of the tem perature. That is why, especially over longer distances,

CHAPTER 2

where the role of conduction is reduced, radiation plays an important and often dominant role. Conduction is the normal mode of heat transfer through a material, solid or ﬂuid. Structural graphite materials are excellent conductors of heat at high tem peratures, much better than, say, stainless steels. On the other hand, insulators are designed in such a man ner that conduction is made difﬁcult. For example, the graphite ﬁbers conduct only along the ﬁbers, and as there is limited contact between ﬁbers, it is difﬁcult for the heat to be conducted through the thickness of an insulating layer. At the same time, the ﬁbrous struc ture cuts the radiation repeatedly over a short distance, making radiation a much less effective means of heat transfer than transfer over free space. Furthermore, insulating material makes it difﬁcult for the inert gas to ﬂow through, cutting or seriously impeding convective heat transfer, too. A silica crucible has quite low thermal conductivity, but it also transfers heat through radiation. The cruci ble is manufactured in a process in which high-purity quartz sand is fused, using, say, an electric arc, into a dense, solid material. However, the outer edge of the crucible contains a large density of small bubbles, which makes radiation less effective. The inside, on the other hand, is fused to be essentially bubble free (why this is made will be explained in Section 2.8), and radiation may pass freely. Sometimes, the bubble structure of the crucible has a signiﬁcant impact on its temperature dis tribution, as the wall may act almost as an optical guide for thermal radiation. In the melt, heat is transferred by conduction and convection. The melt is metallic in nature, its thermal conductivity is at par with graphite, and the conduc tion must be considered as a substantial contributor to overall heat transfer. However, a simple analysis tends to show that convection should play the dominant role. This will be discussed a little later. The crystal also has these two components to the heat transfer, which must be included in analysis. This may sound slightly surprising, since the growth rate of the crystal is small, in 1 mm/min range only. The melt ﬂows, driven by buoyant forces, have 2 to 3 orders of magnitude greater speeds than the typical pull rate. The purge gas ﬂow has two components to the heat transfer, neither of which is usually very large; however, they cannot be ignored, especially where the impact is most signiﬁcant. Even though the furnace pressure is low in the silicon CZ process and argon is a poor ther mal conductor, the presence of the gas has nevertheless a signiﬁcant negative impact on the insulating properties of the used ﬁbrous materials. Another mode of heat loss by the gas ﬂow is created by the need to heat up the incom ing gas itself. Typically, the gas ﬂow is in tens of slpm, and during the passage through the HZ, the temperature 29

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rises by well more than 1000°C. In most cases, a few, but no more than about 5, additional kW escape from the HZ because of the conduction, convection, and heating up of the purge gas, which is relatively little compared with the power of 40 to well beyond 100 kW that the HZs consume. However, the action of the cool incoming purge gas may be quite local on the crystal as well as in the areas close to the melt surface, and then this effect may not be ignored, even if the magnitude of this addi tional, but local, heat loss is only in 1 kW range. The total upward directed heat transfer rates in, say, 150–200 mm crystals seldom exceed 2–3 kW in today’s HZs, though this number may be increased to a very signiﬁcantly larger value.

2.6 Melt Convection The largest CZ crystals grown today weigh several hun dreds of kgs, and the size of the crucible corresponds to that of a small bathtub. The freezing interface is located at the top surface of the melt, and that is why the surface areas are colder than those deep in the melt. As the melt expands with the temperature, warmer melt close to the bottom is less dense, and it tends to rise up towards the surface. The viscosity of molten silicon is somewhat less than that of water; that is, there is very little that the vis cosity does to slow down melt movements. That, com bined with the large volume of the melt, makes it very difﬁcult to control the melt behavior properly. The crys tal sizes grown for MEMS applications are, fortunately, slightly smaller (the present charge sizes seldom exceed 100 kg), but even so, it is a major challenge to create such growth conditions that the instability of the melt does not cause serious impediments to the yield of the growth or to the quality of the growing crystal. The two major approaches to stabilizing the melt, in addition to creating a favorable temperature distribution,

Growth axis

30

are crucible rotation and magnetic ﬁelds. The use of magnetic ﬁelds is very common for large melts and crystals, where crucible rotation tends to be insuf ﬁcient to bring in adequate stabilization. For smaller melts, such as those used for MEMS crystals, magnetic ﬁelds are useful in extending crystal properties beyond what is straightforward to achieve without them, for example, in broadening the available range of oxygen concentration.

2.6.1 Free Convection CZ-grown silicon material shows oxygen and resistivity striations (Figure 2.5) because the melt is heated from below and from the sides, and this kind of temperature distribution is seldom stable. The hotter, less dense melt tends to move upwards, bringing heat with it; and at other locations in the melt the cooler and denser melt goes down. There are two dimensionless numbers that are com monly used to characterize the behavior of a volume of ﬂuid as it comes to free, or natural, convection. The ﬁrst one is the so-called Grashof number (Gr) that tells the ratio between buoyant forces and viscous forces. The buoyancy of the hotter melt closer to the bottom of the crucible is greater for deeper melt, larger temperature differences, and higher value for thermal expansion. Evidently, we do not consider the magnitude of gravity here (in microgravity, it would be much easier to achieve striation-free crystals). The viscous forces are directly related to the viscosity of the melt, which is, as men tioned earlier, quite low. As the Gr surpasses about 107, the ﬂow ceases to be laminar and becomes turbulent. For large silicon melts, Gr is typically around 1010, that is, well above this turbulence limit [14]. However, the value is still so low that the turbulence is not very strong, and the turbulent vortices created by natural convection are relatively large, the smallest ones being in the 1 mm range.

Sample cut

Fig 2.5 ● LPS (Lateral Photovoltage Scanning) [20] map of a lightly doped 150 mm N100 crystal. The sample has been cut out of a 50 mm thick section of the crystal, as shown on right, and then etched. The freezing interface shape may be readily extracted from the map, and information about the amplitude spectrum of axial resistivity striations may also be obtained.

Czochralski Growth of Silicon Crystals

The second dimensionless number is known as the Rayleigh number (Ra), and it describes the ratio between the convection of heat to the conduction of heat. This number may be easily calculated from Gr, as it is the Gr multiplied by the ratio of kinematic viscos ity to thermal diffusivity. As the melt has low viscosity, but high thermal conductivity, this ratio is small, on the order of 0.01. However, as Gr is so large, Ra is also quite large, and based on its value, the convective transport of heat should clearly dominate over conduction. Free convection tends to form distinctly separate areas in the melt, both where hot melt goes up and in other areas where cooler melt goes down. The locations, sizes, and shapes of these areas change continuously; some of these vortices disappear and new ones are formed; and an accurate prediction of the melt ﬂows is extremely difﬁcult, as is often the case with turbulent ﬂows. The growing crystal feels these volumes of differ ent temperatures, and over cold spots the growth rate is greater than over hot spots, where the crystal may actu ally be even melting for a short period. The variations in growth rate have also an impact on the momentary dopant concentration that will be embedded into the growing crystal. These will then be visible as resistivity striations (Figure 2.5). As the crystal is rotated during growth, there is typically some component to the stri ations that is related to the rotation rate. In addition, there are longer-term variations that are related to the time that it takes a new larger hot spot to arrive under the crystal, after the previous one has gone. The tem perature disturbances may also result in the loss of the single crystalline structure; unstable melt behavior typi cally results in poorer yields. In addition to resistivity striations, oxygen striations may be found in a crystal after growth. They have some correlation to resistivity striations, as oxygen originates from the crucible wall and so does heat. However, oxy gen has much lower diffusivity in the melt than heat. Oxygen variations in the melt tend to be more sharply deﬁned; and especially for ﬁne vortices, the correlation between temperature and oxygen may be poor. That is why the time-dependent variations in oxygen concen tration in the crystal do not follow too closely the resis tivity striations. It was mentioned earlier that conduction signiﬁcantly contributes to heat transfer in the melt, too, even though the Ra would suggest otherwise. The main rea son for this discrepancy is forced convection by crucible and crystal rotations and the optional use of magnetic ﬁelds, or other potential means of stabilizing the melt against uncontrolled natural convection. If free convec tion is not the dominant convection mechanism, the inferences derived from these dimensionless numbers (Gr, Ra) may be grossly misleading.

CHAPTER 2

2.6.2 Crucible Rotation

In a typical CZ growth process, the melt as a whole rotates approximately with the crucible. Because of low viscosity, it may take a long time for the melt to adjust its rotation rate to that of the crucible, but this time is short anyway compared with the total proc ess time. Under the crystal, which is normally rotated in the opposite direction, the rotation rate of the melt is slower, just because the crystal opposes the rotation with the crucible. There are, however, exceptions to this general rule; for instance, magnetic forces may be used to make the melt rotate more slowly or faster than the crucible, or the crucible may be rotated in such a manner that its rotation rate changes quite quickly over time. The best known case in which the melt rotates at a rate that is clearly different from that of the crucible is if one uses a transverse magnetic ﬁeld. A static trans verse ﬁeld exerts a strong decelerating force to a rotat ing body of electrically conducting ﬂuid, and the melt will be almost nonrotational, independent of the cruci ble rotation rate. However, this case will be discussed in a little more detail in Section 2.7.1, and other cases will not be touched here at all. Let us assume that the hottest spot in the melt is somewhere near the crucible radius, that is, far from the centerline. This is most often reality, too. The melt there would like to start going upwards, and it is push ing the melt on top sideways, towards the cooler crys tal. The coldest spot is just under the crystal, where the temperature is very close to the melting point. That melt would like to go down, kind of completing the circle with the upward directed ﬂow near the crucible edge. However, the situation is far more complex. First of all, the viscosity is too low to prevent the upward-going ﬂow from turning down just a couple of cms inwards from the crucible wall. And correspond ingly, the downward-going ﬂow somewhere under the crystal would take up a much smaller area than that of the whole (large) crystal, and there would be upwardoriented channels of ﬂow under and close to the crystal, too. This would be the effect of free convection and a large Gr. Secondly, the fairly large velocity component along the circumference of the crucible, the azimuthal velo city, would pose a serious challenge for any ﬂuid volume that would try to make its way too close to the crystal. The ﬂuid would tend to keep its linear velocity when moving radially inwards. However, as the distance from the crucible centerline becomes smaller, the angu lar velocity would increase correspondingly. The same behavior may be seen in the case of tornadoes and hurri canes, where the wind approaching the eye of the storm rotates ever more rapidly. This phenomenon has a major

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impact on the centrifugal force that this ﬂuid volume experiences, whereas the rest of the melt that is rotat ing approximately with the crucible is unaffected. The higher the crucible rotation is, the shorter the distance will be that the ﬂuid volume is able to make towards the center, before the increase in rotation rate will stop it from going any further. An idea of the magnitude of the phenomenon may be gained if we consider a simple numerical example. Let us assume that the crucible rotates at 10 rpm, and we observe a volume of ﬂuid that is at 200 mm radius. Should this ﬂuid try to move inwards, say, to a radius of 180 mm, its rotation rate would tend to go up to 11 rpm. This volume of ﬂuid that rotates at 11 rpm would experience about 100 N/m3 larger centrifugal force than ﬂuid rotating at the original 10 rpm. This so-called body force may not sound very large (gravity makes melt experience a force of about 25000 N/m3), but in practice this difference in centrifugal force is very signiﬁcant. Gravity itself does not cause free con vection, but differences in ﬂuid density do, together with gravity. As a comparison, a vertical column of melt that is 5 K hotter than the surrounding melt, a signiﬁ cant temperature difference, would experience buoyant force that is 20 N/m3, that is, a considerably lesser force than that caused by relatively short radial travel. That is why, for relatively high crucible rotation rates, the melt ﬂow patterns tend to form vortices that are elongated in the vertical direction, and more so if the rotation rate is increased (Figure 2.6). On the other hand, narrow vortices may more easily exchange heat between the warm, upward-directed regions of ﬂow and those colder regions that are going down. This exchange of heat reduces temperature differences between neighboring parts of vortices, and it also reduces the role of convec tion in the heat transfer. In principle, it would be possible to rotate the crucible so rapidly that the rotation alone would result in such small structures that the conductive heat transfer would effectively eliminate temperature differences between upward- and downward-directed portions of the vortices. At the same time, this balanc ing of temperatures would eliminate the driving force

0

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for free convection, and free convection would no longer play a role in heat transfer. However, several tens of rev olutions per minute would be required, and in practice this would be very challenging to realize. Use of a suitable magnetic ﬁeld to support the stabilizing effect of melt rotation would seem to make this approach to stabilizing melt behavior somewhat more realizable [15].

2.6.3 Crystal Rotation The most evident reason for the rotation of the grow ing crystal is to keep its shape essentially round. The semiconductor industry is geared to using round wafers, and there is an abundance of good reasons for the prac tice of using that shape, which the wafer manufacturers must then also follow. However, the crystal rotation has also a signiﬁcant impact on melt ﬂows under the crystal. The classical approximation for the ﬂow under the crystal is that of a rotating disc over stagnant ﬂuid. This case has been widely studied, and it is one of the few situations where a three-dimensional ﬂuid ﬂow may be solved analytically [16]. The resulting ﬂow pattern con tains an upward-directed component that is independ ent of the distance from the centerline of the crystal. There is also a radially outward-directed component that is zero at the freezing interface and very far from it, and it has a maximum value quite close to the interface. In a thin layer, of the order of less than 1 mm thick, the ﬂow is directed radially outwards in a spiral pattern. If the crystal rotation rate is increased, the thickness is reduced proportionally to the square root of the rota tion rate, but at the same time, the velocity of the ﬂow is increased linearly. This adds up to an increase in the mass ﬂow that is directed outwards, which is also pro portional to the square root of the rotation rate. The driving force for this outward-bound ﬂow is the rotational movement that the crystal causes. The melt under the crystal experiences centrifugal force that is strongest at the interface. However, the melt closest to the interface cannot effectively move outward, as the solid surface located just above slows down that portion of the melt. The same viscous forces that make the melt

0.03

0.04

0.05

Fig 2.6 ● Momentary but representative velocity proﬁles for various crucible rotation rates; left at 5 rpm and right at 15 rpm [19]. The results are calculated from two-dimensional simulations; full three-dimensional results would be more complicated. The perpendicular velocity component to the direction of rotation is shown, only. The velocity scale is in meters per second.

Czochralski Growth of Silicon Crystals

rotate in the ﬁrst place prevent it from moving relative to the crystal. Far from the interface, the rotation rate is essentially zero and, therefore, so are the centrifugal force and radial velocity. The viscosity of the silicon melt is so low that only a thin layer under the crystal actually rotates with the crystal, and it is in this layer where the maximum radial velocity can be found. The outward-directed ﬂow is quite important in dis tributing dopants and oxygen more uniformly into the crystal. Typically, the easiest solution for excessively high radial dopant or oxygen gradients is just to increase the crystal rotation rate. However, the solution may some times prove to be more complicated than that. The cool melt from under the crystal tends to reduce thermal gradients outside of the meniscus. Any disturbance out of the cylindrical shape has a better chance of surviving and growing into a signiﬁcant disturbance if the tem perature outside of the crystal increases only gradually. There are always such disturbances because of random ﬂuctuations and because of the anisotropy of the grow ing single crystal. The most prominent anisotropic fea ture is the existence of four vertical growth nodes along the crystal, at 90° intervals, in case of (100) material. The nodes are caused by closed packed {111} planes that try to grow a little longer along the meniscus than other parts of the crystal. If the thermal gradients are made too small, uncontrolled growth over the meniscus and the loss of a single crystalline structure may result. Before that, if the crucible and crystal rotation rates are fairly large, three-dimensional ﬂow patterns will develop near the periphery of the crystal, again at four-fold sym metry, that cause the relatively narrow growth nodes to widen and ﬂatten, and ﬁnally the crystal changes its shape to become somewhat star-shaped. This simple and well-organized ﬂow pattern by crys tal rotation, as approximated by a rotating disc, is only a very partial truth. If we would only rotate the melt and the crystal would be still, the melt immediately under the crystal would rotate more slowly than the rest of the melt and rotation rates would again create a sim ple ﬂow. In this case, the pattern would be identical to what was described previously, but the direction of the ﬂow would be inversed [16]. This kind of conﬁguration would create very large oxygen gradients over the radial dimension of the crystal, as well as a high dopant gradi ent in the case of a volatile dopant, such as antimony in low-resistivity material. As counter-rotation is the industry standard, where both the crucible and the crystal are being rotated, no easy analytical solution for the melt ﬂow exists (even if we would not consider other components of ﬂow, such as free convection). Normally, the crystal is rotated at a clearly faster pace than the crucible. However, because of the much larger surface area in contact with the cru cible, most of the melt, also under the crystal, rotates

CHAPTER 2

in the same direction as the crucible; under the crys tal, at a lower rate than outside of the crystal radius. The melt immediately under the crystal rotates with it, but already, a few mms below, the direction of the rotation is normally the opposite. In between, there is a narrow layer where the actual rotation is close to zero. Above and below, the melt tends to ﬂow outward, again because of centrifugal force, but in between there is a sheath of melt that ﬂows inward. This ﬂow is extremely important for the control and uniformity of oxygen in the growing crystal: The melt under this ﬂow layer is quite oxygen rich, bringing oxygen from the bottom of the crucible; but this layer is more oxygen lean, as it ﬂows in under the crystal after spending some time near the melt-gas interface, where oxygen has been removed from the melt. However, three-dimensional turbulent effects complicate the ﬂow patterns further.

2.6.4 Marangoni Convection and Gas Shear On the melt surface, there is a force that causes the melt ﬂow towards the crystal in such a way that any small par ticle that would fall onto the surface of the melt would have high chances of hitting the crystal, thereby causing it to lose its DF structure. This force and ﬂow is called Marangoni force and ﬂow, and its origin is in the tem perature dependence of surface tension at the melt–gas interface. Surface tension is the phenomenon that causes small water droplets to try to take spherical shape: A volume of liquid wants to minimize its surface area. But it is the temperature dependence of surface tension that creates the Marangoni force, not surface tension itself. Farther away from the crystal, the surface tem perature of the melt is higher, and that is why surface tension there is lower. Marangoni force, whose unit is force per area (N/m2), is therefore directed towards the cooler area, that is, towards the crystal, and its magni tude is larger for a larger temperature gradient. As the melt viscosity is low, this ﬂow has limited impact on the melt behavior deeper down, but the ﬂow velocity right at the surface cannot be ignored. There is another surface force that is opposing the Marangoni ﬂow, in HZs where the purge gas ﬂow or a sig niﬁcant part of it is directed close to the melt. At low pres sure, hot purge gas may have a velocity in the 10 m/s range very near to the melt surface, and this creates a shear that is directed outwards. The magnitude of this shear is often in the same range as the Marangoni force. Especially if low oxygen material is desired, the efﬁcient sweeping of oxy gen containing gases is needed in the vicinity of the meltgas interface, and this translates to high gas velocity. Oftentimes, if melt behavior during CZ growth is simulated computationally, oxygen is considered as 33

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not having an inﬂuence on melt ﬂows. This makes the optimization of the growth process substantially easier, as the melt ﬂows may be modeled on thermal con siderations and forced convections, only. After hav ing modeled the melt ﬂow patterns, one may calculate oxygen distribution in the melt with varying purge gas ﬂows. Proper simulation of the melt ﬂow is a much more laborious exercise than that of gas ﬂow or oxygen distribution. However, if the gas ﬂow is high enough to cause sig niﬁcant shear to the melt interface, or if the cooling effect of the gas ﬂow changes the temperature distribu tion in the crystal and around the crucible by a consid erable amount, this approach is no longer valid. Then the melt ﬂows should be recalculated, adding very sig niﬁcantly to the computational effort, for every major change in the gas ﬂow.

2.7 Magnetic Fields There are two different kinds of static magnetic ﬁelds in widespread use to produce CZ silicon crystals, trans verse and cusp ﬁelds. Almost pure axial ﬁelds are poorly suited, as they tend to prevent transport of oxygen and dopant from under the crystal; and, therefore, the resulting oxygen concentration is high and variation of oxygen and dopant in the radial direction (radial gradi ents) is often large. Magnets weigh usually several tons, and the power may be well beyond 100 kW. However, more powerhungry magnets have been increasingly replaced with superconducting magnets. Sometimes, especially older growers have been modiﬁed to take more lightweight magnets, despite the cost of higher electric current den sity and larger power loss, as the space around the vac uum chamber has been in short supply and the grower frame has not allowed for signiﬁcant excess weight. Furthermore, if low ﬁeld is considered sufﬁcient, mod ern permanent magnet materials together with iron yokes may be applicable. The movement of an electrically conducting ﬂuid in a magnetic ﬁeld causes an electromotive force that is per pendicular to both the ﬁeld and the direction of move ment. This electromotive force tends to create electric currents that, in interaction with the external magnetic ﬁeld, oppose the ﬂuid motion. The ﬁeld strengths typi cal for magnetic CZ (MCZ) processes are sufﬁcient to slow down various ﬂow patterns very signiﬁcantly. This has implications to various crystal properties such as oxygen and dopant distributions; but they also tend to reduce crucible wear, thus extending the lifetime of the crucible, and reduce thermal ﬂuctuations in the melt, which, together with reduced crucible wear, results in better DF growth yields. 34

2.7.1 Transverse Field

A transverse magnetic ﬁeld is created from conventional copper or superconducting coils that are located in the vertical position. Heavy iron yokes are used to shorten the magnetic path and to reduce the important stray ﬁelds. This type of ﬁeld has the unpleasant character istic of breaking the otherwise almost perfect cylindri cal symmetry of the growth geometry. However, as the ﬁeld impacts on melt behavior only, and the melt ﬂows in the case of large crystals deviate from cylindri cal symmetry in a signiﬁcant manner anyway, this loss of symmetry is not as serious a breach as it may ﬁrst seem. The crucible (and melt) rotation is normally rela tively fast in growth, with no magnetic ﬁeld to stabilize the ﬂuid, but this is not the case for the transverse ﬁeld. The lateral ﬁeld, together with melt rotation, would cre ate electric potential differences between the bottom and near-surface regions of the melt. These differences would be of varying magnitudes, depending on the angle between the direction of the ﬁeld and the ﬂuid velocity; and large electric currents opposing the rotation would ﬂow. That is why, under any transverse magnetic ﬁeld, the melt rotation rate would be close to zero, essentially independent of the crucible rotation rate.

2.7.2 Cusp Field Cusp magnetic ﬁeld is essentially a ﬁeld created by two round horizontal coils, with a distance between them, connected in such a way that their magnetic dipoles oppose each other. That is why there is a region of almost zero ﬁeld that is usually close to the freezing interface [17]. The cylindrical symmetry is maintained. A typical shape of cusp ﬁeld is shown in Figure 2.7. This type of ﬁeld also creates electromotive forces as the melt is rotated, but contrary to the transverse ﬁeld, there is little force created that would try to stop the rotation. That is why an MCZ process utilizing the cusp ﬁeld may be very similar to a normal CZ process. Far from the freezing interface, the magnetic ﬁeld is strong est and its impact on reducing melt ﬂows is also great est. In a way, it may be considered that the cusp MCZ purports to grow the crystal from a melt that has been reduced in effective volume by creating circumstances in which the melt close to the freezing interface and below the crystal sees little effect of the ﬁeld, and out side of the crystal radius the melt convection is largely suppressed. Oxygen concentration in an MCZ process is often con sidered to be substantially lower than in an otherwise sim ilar process but with no magnetic ﬁeld. This is not always true. It is proper to say that a magnetic ﬁeld reduces the rate of dissolution of the crucible; that is, introduction

Czochralski Growth of Silicon Crystals

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0.2

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of oxygen into the melt is diminished. However, it also has an impact on melt ﬂows near the melt–gas interface, reducing ﬂows there. It is essentially the balance between the dissolution and evaporation of oxygen that dictates the oxygen concentration in the melt. As the magnetic ﬁeld stabilizes the melt behavior, a more effective means, for instance, in gas ﬂows may be utilized to remove oxygen from the melt, and that is why the use of a magnetic ﬁeld does allow the reach ing of lower oxygen levels. However, a lower oxygen level in the melt does not guarantee low oxygen in the crystal in a straightforward manner. Growth processes are possible in which ﬂow patterns under the crystal are such that if that region is oxygen rich, the crystal also becomes oxygen rich even if the melt outside of the crystal radius has relatively low oxygen contents. Such processes are normally not applied, as it would be quite difﬁcult to control the radial uniformity of oxygen concentration.

2.7.3 Time-Dependent Fields Much more complex magnetic ﬁelds may be devised for better control of melt behavior, and the ﬁelds may also be time dependent. However, these possibilities are beyond the scope of this book.

2.8 Hot Recharging The CZ crystal growth process that has been described earlier depicts a standard batch process, in which one crystal is pulled from the melt. Occasionally, for various reasons, two small crystals may be pulled from a single melt. However, this is a rarer occasion than so-called hot recharging, in which a relatively large residual melt is left in the crucible and new silicon material is added into the melt. The easiest way of doing this is to use

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CHAPTER 2

Fig 2.7 ● Shape of a typical cusp magnetic ﬁeld within the melt volume and lower portion of the crystal. Maximum ﬁeld strength (white color at scale value 1.0) is attained at the crucible corner. Near freezing interface, there is almost no ﬁeld. Solid lines depict the magnetic lines of force.

granular polysilicon, small spheres in the 1–4 mm diam eter range that ﬂow easily, even through small-diameter tubes or other structures, to make the feed. However, because of the limited availability of this material and additional concerns, other types of materials may also be used: Small-sized chunks may be fed in a manner similar to granular material, using larger-sized chan nels. Or a vertical tube-like structure ﬁlled with small chunks may be lifted into the receiving chamber, after removal of the crystal, and a valve in the lower end of the tube opened to allow the charge to be replenished. Furthermore, large rods of material may be put hang ing into the end of the seed cable/shaft and fed into the melt in a well-controlled manner. Or adding to the complexity in a signiﬁcant manner, new silicon may be added as molten from outside of the crucible proper. In all of these cases, the main goal is to reduce cost and save time compared with growing a single crystal from the melt. The cost of the relatively expensive cru cible, which will break during cooling down, will then be shared with a larger number of crystals. The residual melt will also be shared with several crystals, however, with the further expense of somewhat more contamina tion in the end of the last crystal than there would have been at the same position if only one crystal would have been pulled. However, today’s high purity processes typically allow for that. There will usually be some time savings, too, to the cycle time per produced kg of crys tals, as there will be less time needed to heat up and cool down the HZ, again per crystal pulled. A major impediment to the use of hot recharging has been, in addition to the limited availability of granular poly material, the strain that the very long total hot time exposes the crucible to. There is a continual wear in the crucible wall. The possibility that the advancing wear will release small silica particles into the melt and thus cause a structure loss increases as the wear pro ceeds. The way the crucible wall has been fused makes 35

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Silicon as MEMS Material

the near inner surface of better quality than the deep bulk of the material. Over the years, various alterna tives have been pursued to extend the lifetime, either through modiﬁcations to the way the crucible behaves when exposed to reactive silicon melt, or through changes made to hot-zone design and the growth proc ess, in order to reduce the wear at the crucible walls. Some approaches used within the industry today are modiﬁcations to the silica material itself, including the use of high-purity sand for an inside layer, sand that has been manufactured starting from high-purity gases, or fusing this inner layer to contain fewer bubbles and other imperfections that would initiate nonuniform wear that may result in the release of small silica/quartz

particles into the melt. Further possibilities are the application of small quantities of various elements whose role is to enhance the so-called devitriﬁcation of silica, in order to ensure that the wear takes place more uniformly than in the absence of this uniform devitri ﬁed layer, and at the same time the crystal rejects those added elements so powerfully that the concentration in the crystal remains insigniﬁcant. It is recommend to enhance the thermal design of the HZ in such a way as to reduce the crucible inner wall temperatures and thus to diminish wear through the lowered solu bility and reduced intensity of the melt ﬂow patterns, as well as to use various magnetic ﬁelds to stabilize the melt.

References 1. J. Czochralski, Ein neues Verfahren zur Messung der Kristallisations geschwindigkeit der Metalle, Z. Phys. Chem. 92 (1918) 219. 2. G.K. Teal, J.B. Little, Growth of germanium single crystals, Phys. Rev. 78 (1950) 647. 3. G.K. Teal, E. Buehler, Growth of silicon single crystals and single crystal silicon pn junctions, Phys. Rev. 87 (1952) 190. 4. H.R. Huff, From the lab to the fab,

transistors to integrated circuits, in:

C. Claeys, F. Gonzalez, R. Singh, J. Murota, P. Fazan (Eds.), ULSI Process Integration III, The Electrochemical Society Proceedings Series PV 2003– 06, 2003, p. 15. 5. W. Dietze, W. Keller, A. Mühlbauer, Floating zone silicon, in: J. Grabmaier (Ed.), Crystals: Growth, Properties and Applications, vol. 5, Silicon, SpringerVerlag, Berlin, 1981. 6. W. Zulehner, The growth of highly

pure silicon crystals, Metrologia 31

(1994) 255.

7. A. Mühlbauer, Innovative induction melting technologies: a historical review, International Scientiﬁc Colloqium in: Modelling for Materials Processing, Riga, June 8–9, 2006, p. 13. 8. W.C. Dash, Growth of silicon crystals free from dislocations, J. Appl. Phys. 30 (1959) 459.

9. W. Zulehner, D. Huber, Czochralski grown silicon, in: Crystals, vol. 8, SpringerVerlag, Berlin–Heidelberg, 1982. 10. W. Zulehner, Czochralski growth of silicon, J. Cryst. Growth 65 (1983) 189. 11. J. Davis, A. Rohatgi, R. Hopkins, P. Blais, P. Rai-Choudhury, J. McCormick, H. Mollenkopf, Impurities in silicon solar cells, IEEE Trans. Electron Dev. ED-27 (1980) 677. 12. E. Dornberger, W. von Ammon, The dependence of ring-like distributed stacking faults on the axial temperature gradient of growing Czochralski silicon crystals, J. Electrochem. Soc. 143 (1996) 1648. 13. U. Ekhult, T. Carlberg, M. Tilli, Infra red assisted Czochralski growth of silicon crystals, J. Cryst. Growth 98 (1989) 793. 14. M.G. Braunsfurth, A.C. Skeldon, A. Juel, T. Mullin, D.S. Riley, Free convection in liquid gallium, J. Fluid Mech. 342 (1997) 295. 15. O. Anttila, Some observations of growth of CZ silicon and dream of ideal growth, ECS Trans. 3 (4) (2006) 3. 16. H. Schlichting, K. Gersten, Boundary Layer Theory, eighth ed., Springer, 2000.

Further reading G. Müller, J. Métois, P. Rudolph (Eds.), Crystal Growth—From Fundamentals to Technology, Elsevier, 2004.

36

H. Scheel, T. Fukuda (Eds.), Crystal Growth Technology, John Wiley & Sons, 2003.

17. R.W. Series, Effect of shaped magnetic ﬁeld on Czochralski silicon growth, J. Cryst. Growth 97 (1989) 92. 18. O.J. Anttila, M.V. Tilli, V.K. Lindroos, Computer modelling of the temperature distribution in the silicon single crystals during growth and the thermal history of the crystal, in: J.C. Mikkelsen, Jr., S.J. Pearton, J.W. Corbett, S.J. Pennycook, (Eds.), Oxygen, Carbon, Hydrogen and Nitrogen in Crystalline Silicon, vol. 59, Materials Research Society Proceedings Series, 1985, Vol. 59, p. 323. 19. O. Anttila, M. Laakso, J. Paloheimo, J. Heikonen, J. Ruokolainen, V. Savolainen, T. Zwinger, Simulation of silicon Cz growth: where we are now, in: C.L. Claeys, M. Watanabe, P. Rai-Choudhury, P. Stallhofer (Eds.), High Purity Silicon VII, vol. 200220, ECS Symposium Proceedings Series, Vol. 2002–20, p. 65. 20. A. Lüdge, H. Riemann, Doping inhomogeneities in silicon crystals detected by the lateral photovoltage scanning (LPS) method, in: J. Donecker, I. Rechenberg (Eds.), Defect Recognition and Image Processing in Semiconductors 1997, CRC Press, 1997, p. 145.

3

Chapter Three

Properties of Silicon Crystals

Jari Paloheimo Okmetic Oyj, Vantaa, Finland

Many properties of Czochralski (CZ) silicon wafers origi nate partially or totally from the crystal growth used to produce the single-crystalline silicon. For example, the diameter and orientation of the as-grown crystal are already close to those of the ﬁnal wafers. Furthermore, the conductivity type (p or n), selection of the dopant element and its concentration (which induces certain electrical resistivity), oxygen concentration and amount of carbon, and the homogeneity of these concentrations in the microscopic and macroscopic scales all originate from the growth process. Also, other important qualities (e.g., the amount of harmful transition-metal impurities and many of the typical defects encountered in silicon processing) are contributed by the initial crystal mate rial. In the optimal case, the most important quality fac tors of the crystal, considering the planned use of the wafers, are properly identiﬁed beforehand; the allowed range of properties is speciﬁed; the quality is controlled by the crystal-growing process; and the resulting qual ity becomes ascertained from the crystal and/or wafers. Such procedures, if handled properly, give a good starting point for the subsequent device processing on the wafers. Furthermore, feedback about the yield and quality prob lems encountered in wafer and device processing gives useful information for further improvements in the crys tal quality. In the worst case, the crystal may contain too many impurities or defects, or have a tendency toward later defect formation because of insufﬁcient initial infor mation or knowledge, compromises in the crystal qual ity or cost, inherent limitations of the growth process, or some other more accidental reason. The insufﬁcient quality could lead to rejection of the crystal material or wafers or, if unﬁt wafers are delivered to customers, to negative inﬂuence on the yield or quality of their product,

which can be an integrated circuit, discrete device, sensor structure, solar cell, or some other type of application. In this chapter, the typical properties of CZ silicon crystals are reviewed, covering impurities and defects, their effects, control, and incidence. We concentrate on the properties of as-grown crystal, while the contribu tions by wafer processing are only mentioned brieﬂy. Speciﬁcally, the quality factors that have proven to be of the greatest practical importance in the crystal-growing industry for 4–8 in. nominal crystal diameters, which is also the range used in microelectromechanical systems (MEMS), are covered. The connections of impuri ties and defects to the success or failure of later device fabrication on the wafers are indicated where possible; although, due to the extent of the subject, only major items can be covered. More detailed information can be found in the references of this chapter and in the other chapters of this book.

3.1 Dopants and Impurities The CZ silicon crystals contain small amounts of impuri ties of which some are essential, in controlled amounts, for the quality of the crystal and wafers, while other impurities are harmful if their concentration is too high and, thus, the latter elements must be avoided. The acceptor or donor impurities and oxygen, in suitable amounts, are among the former, useful elements. The acceptor and donor dopants are usually elements from groups III and V of the periodic table of elements, the most used ones being boron (acceptor, for p-type crys tals) and phosphorus, antimony, and arsenic (donors, for n-type crystals) (see Table 3.1). These typical dopants 37

PA R T I

Silicon as MEMS Material

Table 3.1 Table of elements indicating substitutional dopant impurities of silicon

Period

Group III

IV

V

2

B(A)

3

Al

Si

P(D)

4

Ga

As(D)

5

In

Sb(D)

The elements most used, in practice, as acceptors and donors in CZ crystals are indicated by (A) and (D), respectively.

are substitutional impurities (i.e., they replace silicon atoms in the lattice) and donate one hole or electron per each acceptor or donor atom to the valence or conduc tion band of silicon, respectively [1, 2]. The acceptors and donors are used to control the charge carrier con centration (and resulting resistivity) and type of charge carriers of the crystal. These parameters are essential considering the operation of the semiconductor devices processed on the wafers [1]. Instead of boron, some other elements from group III could also be used as acceptors in CZ crystals but have certain limitations and are not common in practice. For example, gallium dop ing has been suggested for solar cell applications in order to avoid the initial degradation of the efﬁciency observed in solar cells made of boron-doped CZ silicon [3]. The three donors—phosphorus, antimony, and arsenic—are not replaceable by each other, at least self-evidently, because they have different properties. For example, the different dopant elements have different limits for the lowest resistivity achievable and the amount of axial var iation of resistivity within crystal depends on the dopant. Furthermore, the diffusion and redistribution behavior of the dopants in the wafer during device processing also varies [1]. For some dopants, certain safety issues exist in crystal growing or later processing and may require precautions. In practice, the users of the wafers already specify, for each wafer product, the dopant element to be used in the crystal. Boron and phosphorus are typi cal in lightly doped crystals while all four elements (i.e., boron, phosphorus, arsenic, and antimony) are used in the highly doped case. Oxygen originating from the silica crucible is one of the most characteristic impurities in CZ silicon in con trast to ﬂoat-zone (FZ) silicon, which contains practi cally no oxygen. A suitable oxygen concentration is considered to be among the main quality factors to be controlled in the crystal-growing process. Oxygen in interstitials gives the wafers mechanical strength against thermal, gravitational, or mechanical stress during heat 38

treatments, decreasing the risk of slip dislocation for mation and wafer warping [4, 5]. Furthermore, oxy gen forms precipitates [6–8], which are often used for impurity gettering in device processing where gettering is a method to remove harmful metal impurities from the device region of the wafer [9]. Also too high an oxygen concentration can be harmful if it induces too strong precipitation of oxygen and formation of defects. Nitrogen can be intentionally added to crystals in concentrations around 1015 cm�3 to control the microdefect formation [10], mainly to enhance oxygen pre cipitation or to reduce the size of vacancy-originated defects, and/or to strengthen the crystal [11]. Nitrogen has the potential for commercial applications in largediameter wafers but is not used in standard smallerdiameter CZ silicon wafers and is also not expected to offer beneﬁts in typical MEMS. Only one acceptor or donor dopant element is used in one growth, the other acceptor or donor dopants being avoided because their coexistence could cause a shift of resistivity or other, possibly unpredictable, effects. However, unintentional dopants have several potential sources and cannot be totally avoided, although their concentration can be kept at an acceptably low level. For example, small amounts of aluminum and boron dopants originate to the melt and crystal from standard silica crucibles made of natural quartz containing these impurities. Aluminum is an acceptor and, if present at high concentrations on the wafer surface, has been found to inﬂuence the growth and quality of oxide lay ers grown on wafers [12]. Fortunately, the concentra tions originating from crystal growing, typically 1013 Al atoms/cm3, do not yet cause surface-quality prob lems, although aluminum may already have some effect on the resistivity of the wafers if these have very high resistivities. Dopants from earlier runs may also reside inside the furnace chamber and in the hot zone, or even in the seed crystal, and could end up in the next crys tals if this risk is not properly taken into account in the crystal-growing procedures. The harmful impurities in CZ silicon crystals include carbon, transition-metal impurities (e.g., Fe, Cu, and Ni) [13–16], and alkali and alkali earth metals (e.g., Na). These impurities, as well as accidental dopants, may originate from the starting materials (polysili con, recycled silicon, if used, and dopants), silica cru cible, and materials and contamination of the furnace and the hot zone (see Chapter 2 and, e.g., Ref. [17]). Contamination may also be caused by procedures or mistakes by the operators or malfunction of the crystalgrowing furnace. Carbon is electrically inactive in silicon, while transition-metal impurities may form deep impurity levels within the band gap between the conduction and valence bands, behave as recombina tion centers or as unwanted acceptors and/or donors, or

Properties of Silicon Crystals

form complexes with dopants under certain conditions. Transition metals are also relatively fast diffusers in sili con at temperatures above room temperature; copper, especially, remains quite mobile even at room tempera ture. The transition metals, or their precipitates, may decrease the recombination or generation lifetimes and the minority carrier diffusion lengths, and cause leakage currents in the junctions of the devices, lower efﬁciency of solar cells, quality problems with gate oxides in metal-oxide-semiconductor structures, or even a shift of the resistivity [13, 14, 16, 18]. The exact effect of the metal impurities depends considerably on the metal, its concentration and state, defects formed, and the type and resistivity of the silicon wafer. For example, iron can be very effective in decreasing the recombination lifetime, especially in p-type silicon, while copper is considered to have a greater impact on the lifetime of n-type wafers than on p-type wafers [16].

3.2 Typical Impurity Concentrations The typical concentrations of a few characteristic impu rities in CZ crystals are listed below in Table 3.2. The concentration of the speciﬁed dopant (or, actually, the resistivity value), as well as the oxygen, carbon, and iron concentrations, are routinely measured. The val ues indicated are valid for semiconductor-grade crys tals, where contamination levels are typically low, and are applicable, especially, for nominal crystal diam eters of 4 in., 5 in., 6 in., and 8 in., covering the diam eters used in present and near-future MEMS. In most cases, these carbon and metal concentrations of the asgrown crystal are not the limiting factors, considering the success of device processing, and can be tolerated. However, considerably larger contamination concentra tions of the crystal are possible in some cases (e.g., in solar-grade crystals) if lower-quality production materi als are used for cost reduction, especially if the residual silicon remaining in the crucible after previous growth (so-called “pot scrap”) is recycled into the next charge to replace pristine polysilicon. The solubilities of various elements in silicon crystal at high temperatures can be found in [19] and refer ences therein, and are among the limitations and mech anisms to be taken into account in crystal growth. The actual concentration of the dopant and other impuri ties in CZ growth are typically much below their solu bility at the melting point of silicon, Tm1412°C. The solubility in the melt and crystal in the vicinity of Tm may be approached only in the following anomalous cases: (1) The melt, by mistake or by furnace malfunc tions, becomes highly contaminated by carbon or some other impurity. (2) Very large amounts of acceptor or

CHAPTER 3

Table 3.2 Typical range of concentration of impurities in semiconductor-grade CZ silicon crystals, grown with or without a magnetic ﬁeld

Impurity

Typical concentrations in crystals

Speciﬁed acceptor or donor dopant*

0.1 ppba… 1000 ppma

5 � 1012…5 � 1019 cm�3

Other acceptors or donors

�1 ppba

�5 � 1013 cm�3

Oxygen*

5–18 ppma

2.5 � 1017…9 � 1017 cm�3

Carbon

�0.5 ppma

�2.5 � 1016 cm�3

Iron

�1 ppta

�5 � 1010 cm�3

The concentrations of the impurities denoted by the asterisk (*) are controlled to their optimized and/or speciﬁed values, while other impurities are considered to be contamination. Notice that 1.0 ppma corresponds to 5.0 � 1016 atoms/cm3. The interstitial oxygen concentrations are given in “new ASTM units” (ASTM F 121-83 [24]) and carbon concentrations are given in ASTM F 123-86 units [21].

donor dopants are added to the melt to reach resis tivities below standard levels. If the solubility limit is reached, particles start to form in the melt, especially at the solid–melt interface, probably causing dislocations in the crystal and making the growing of single crystals impossible [20]. For example, according to our experi ments on carbon-contaminated crystals, dislocations start to appear in the CZ crystal and its single crystalline structure is lost if the carbon concentration of the crys tal reaches 11–13 ppma (concentration is expressed in units of ASTM F 123-86 [21], in reasonable agreement with the values for the solubility of carbon reported in the literature, suggesting that silicon carbide particles are responsible for the effect. Still, the standard carbon concentrations in commercial crystals are considerably below the solubility limit. Even if the concentrations of impurities in the crystal are below the solubility at Tm, the solubilities start to decrease with decreasing tem perature, often leading to supersaturation of impurities in the crystal and wafers at lower temperatures. In fact, this supersaturation becomes the driving force for the later formation and growth of impurity precipitates of oxygen and transition metals, for example, if these pre cipitates are ﬁrst able to nucleate. The interstitial oxygen concentration of the crystal Oi can be varied over a relatively wide range by chang ing the process parameters (e.g., the rotation rate of the crucible, the argon gas mass ﬂow, the pressure inside the furnace, the shape and intensity of the magnetic ﬁeld, the hot zone structure, and/or the melt height position) as has been discussed in greater detail in Chapter 2 and in [20, 22, 23], and references therein. Oxygen 39

PA R T I

Silicon as MEMS Material

and carbon concentrations are typically measured by using infrared absorption techniques (for more details, see Chapters 5 and 21). The calibration factors used to calculate the concentration from the measured absorp tion coefﬁcient are not unique. Several different factors have been deﬁned and used, and, thus, the measured or speciﬁed values of interstitial oxygen and substitutional carbon should preferably include a reference to one of the standards to make the values exactly deﬁned. In this chapter, we have systematically used the “new ASTM units” (also called ASTM F 121-83 [24], or DIN) for oxygen and ASTM F 123-86 [21] for carbon. The infra red absorption measurement of oxygen or carbon is accurate and practical in lightly doped p- and n-type crystals, and the Oi of these crystals is routinely meas ured from samples sliced from every crystal; however, the infrared measurement becomes inaccurate or even impossible in highly doped p� and n� crystals because of their strong free-carrier absorption. Therefore, other methods, such as gas fusion analysis (GFA) or secondary ion mass spectroscopy (SIMS), have to be used in such cases (e.g., Ref. [25]). Typical carbon concentrations of 0.1 ppma and almost always �0.5 ppma in crystals largely originate from polysilicon charge and from the carbon of the graph ite parts of the hot zone (for more details on the contam ination mechanisms, see Chapter 2). Fortunately, such amounts of carbon have only a relatively minor impact on crystal and wafer quality and can be tolerated, while much higher concentrations could already enhance oxy gen precipitation in later heat treatments and be harmful [2, 8, 26–28]. In some cases, even the concentration of 0.5ppma could enhance the oxygen precipitation [28], while for considerably higher concentrations of �2 ppma, the effect becomes quite clear [26, 27]; however, the lat ter values are not common in semiconductor-grade CZ crystals. Metal impurities are tolerated in even much lower concentrations than carbon in the crystal and may be detrimental in the ppta levels in some cases. For exam ple, the carrier lifetimes that are important parameters in a variety of device structures [1] can be very sensitive to the iron concentration [18]. In lightly boron-doped, p-type silicon, assuming that iron is in iron-boron pairs, the recombination lifetime of the minority carriers (electrons) is limited to the value τ(μs) ≈ 1.5 � 1013 /NFeB (cm�3 )

(3.1)

where NFeB is the concentration of the FeB pairs (see Ref. [15] and references therein). Also, other impuri ties, defects, and/or high dopant concentrations (low resistivity) [29] may decrease the lifetime. For more information about the detection and identiﬁcation of various metals by using minority carrier recombination 40

lifetime measurements, we refer to [16, 18, 30], and for other metal detection methods, we refer to [14] and references therein. The target for the iron concentration appears quite challenging at ﬁrst glance. Fortunately, the crystal strongly rejects typical harmful metal impurities during growing, as discussed in Section 3.3, leading to much purer crystal when compared with the melt, allowing the crystal to reach the low impurity concentrations needed. For example, a typical iron concentration in the order of 1010 cm�3 in crystal (see Table 3.2), according to Eq. 3.1, would allow the recombination lifetime to have a sufﬁciently high value of about 1000 μs in p-type silicon. However, it is important to note that the values indicated above are for the as-grown crystal, while the connection between the initial metal concentration of the crystal and the lifetime in the ﬁnal device structure is not simple to analyze because of the additional metal contamination and diffusion, precipitation, and/or get tering of metals during wafer and device processing. In fact, the exposure of wafer surfaces to metals in later processing after crystal growing in most cases dominates the metal contamination and should be controlled to tol erable levels, possibly by applying gettering methods [9] to remove the metals from the active surface region.

3.3 Concentration of Dopants and Impurities in Axial Direction The concentration of the dopant, carbon, and metal impurities increases along the crystal body. Thus, wafers fabricated using silicon material from different parts of the crystal may behave differently. Much about the axial concentration proﬁle can already be gleaned by closely looking at the normal freezing equation, which expresses the impurity concentration variation as a function of the solidiﬁed mass fraction of the melt (g): cs (g) � k 0 c0 (1 � g)k 0 �1

(3.2)

Here, c0 is the initial concentration in the melt and k0 is the equilibrium distribution (segregation) coefﬁ cient, which has a characteristic value for each impurity in silicon [31] (see Note 1 [32]). In a relatively typi cal case, the value of g is quite small—a few percent at most—in the beginning of the body, while g 0.9 in the end of the body of the crystal, although the exact values depend on the process details. Table 3.3 below gives the distribution coefﬁcients, k0, of some of the most impor tant impurities in silicon. Oxygen has the highest value of k0 of all elements, k01 [39], while the dopants and especially the transition metals have lower values of k0 and are rejected by the growing crystal. In prac tice, to reach exact agreement between the theoretical

Properties of Silicon Crystals

Table 3.3 Equilibrium distribution coefﬁcient k0 of typical impurities in silicon (see [19] and [31] and references therein, and [39] for oxygen)

Element

k0

O

1

B

0.8

P

0.35

As

0.3

C

0.07

Sb

0.023

Ga

8 � 10�3

Al

2 � 10�3

Na

1.7 � 10�3

N

7 � 10�4

Cu

4 � 10�4

Ni

1 � 10�5…1 � 10�4

Fe

8 � 10�6

segregation behavior and experiments, an effective value keff of the distribution coefﬁcient, slightly dif ferent from k0, should be used instead of k0 in Eq. 3.2 (see Note 2 [33]). According to Eq. 3.2, the concentra tion cs increases (decreases) with increasing g for k0 �1 (k0 � 1), while cs � c0 if k0 � 1. Theoretical concen tration curves for a few typical impurities are shown in Figure 3.1. For impurities that have k0 ��1 (e.g., tran sition metals), the shapes of the curve become almost independent of k0 (i.e., cs(g)k0c0(1 � g)�1, where k0 is a prefactor only), further indicating that the ratio cs/ c0 of the body (g0.0–0.9) varies in the range of k0… 10 � k0. Thus, in principle, CZ growing is an effective method to purify silicon of impurities with k0 ��1. Equation 3.2 predicts the axial concentration proﬁles correctly only if the impurity does not evaporate from the melt surface and additional impurity is not sup plied into the melt during pulling. Considering various dopant elements, boron in p and p� crystals and phos phorus in lightly doped, n-type crystals obey Eq. 3.2 with reasonable accuracy. On the other hand, the nor mal freezing equation is not useful with oxygen which evaporates from the melt surface and is supplied to the melt from the dissolving silica crucible during pulling [22, 34]. The equation should also be used with care with carbon and metal impurities, which are, to some

CHAPTER 3

extent, supplied to the melt during pulling, or with highly doped n� crystals with large concentrations of phosphorus, antimony, or arsenic, which noticeably evaporate from the melt. The oxygen concentration of a crystal preferably should be axially uniform, the values within the given speciﬁcation, and suitable for the planned use of the wafers. Knowledge about the suitable oxygen concentration range is included in the wafer speciﬁcation. In lightly doped products, inter mediate Oi targets are in the range of 13–15 ppma; how ever, signiﬁcantly different targets are also common. The concentration is controlled during crystal pulling (see, e.g., Refs [20, 22–23, 34], and Chapter 2) by using proper val ues for the process parameters for each oxygen target and measurements of the actual result after growth. Examples of the measured oxygen concentration curves of two crys tals with signiﬁcantly different oxygen targets are shown in Figure 3.2. Relatively uniform oxygen concentrations can be achieved in boron-doped p-type and in phosphorusdoped n-type crystals, the typical variation of axial Oi (measured at radius r � 0) being within � 1 ppma from the target value. The dopant has no effect on crystal’s oxygen concen tration in lightly boron- or phosphorus-doped p- or n-type crystals; however, according to the literature, in highly boron-doped p� crystals, the oxygen concentration may be increased by 20% for similar process parameters [22, 34, 35], but this shift depends on the process condi tions and boron concentration and may also be practically negligible. Moreover, the oxygen concentration is not as easy to accurately measure in p� or n� crystals, which also complicates their exact oxygen control. Thus, oxy gen control in p� crystals is less accurate than in lightly doped cases. The precise control of oxygen is even much more difﬁcult in highly doped n� crystals as the dopant evaporates, which has as a consequence that the evapora tion of dopants and the evaporation of oxygen are inter related and cannot be optimized independently by the process parameters. Furthermore, the oxygen evapora tion from n� melt is enhanced, the evaporating oxygencarrying species typically being oxides of the dopant instead of SiO [36]. Because of these reasons, the oxygen concentrations in n� crystals are often relatively low and have a relatively large axial variation [37]. The carbon concentration in the beginning of the crys tals is typically low, 0.0 ppma, according to the infra red absorption measurements. The carbon concentration increases with length at a faster rate than the normal freezing equation (Eq. 3.2) predicts because of the accu mulation of carbon contamination from the atmosphere into the melt during crystal pulling. This additional car bon contamination can be kept at reasonable levels by using suitable hot zone design and growth parameters and procedures, typically leading to low carbon values of �0.5 ppma in the end of the body, typically located 41

Silicon as MEMS Material

PA R T I 1.E+01 1.E+00

cs(g)/c0

1.E−01 1.E−02 1.E−03

k0 = 1 k0 = 0.8 (boron) k0 = 0.35 (phosphorus) k0 = 0.07 (carbon) k0 = 0.0017 (sodium) k0 = 8E-6 (iron)

1.E−04 1.E−05 1.E−06 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Solidified fraction of melt, g

Fig 3.1 ● Concentration of impurities in the crystal vs. solidiﬁed fraction of the melt, g, calculated from the normal freezing equation. The concentration has been scaled by the initial melt concentration, c0.

into the charge before or after melting. It is actually the resistivity that is deﬁned in the wafer speciﬁca tion instead of dopant or charge carrier concentration because the resistivity can be measured relatively easily and accurately. The resistivity and carrier concentrations are connected by the following equations [1]:

16 Oi (ppma) (new ASTM)

15 14 13 12 11 10 9 8

Crystal 1 (high Oi) Crystal 2 (low Oi)

7 6 0

0.2

0.4

0.6

0.8

Solidified fraction of melt, g

Fig 3.2 ● Experimental oxygen concentrations vs. the solidiﬁed fraction of the melt, g, in two lightly doped crystals that have different targets for Oi.

at g0.9. In principle, the precipitation of oxygen in the crystal could be enhanced by intentionally adding small, controlled amounts of carbon into the initial charge, but such attempts would lead to relatively unpredictable or uneven results as the wafers from different parts of the crystal would inevitably have very different carbon concentrations. In practice, low carbon concentrations are preferred in the ﬁnal use of the wafers and, thus, the maximum allowed carbon concentration is quite often given in the wafer speciﬁcation.

� � (qμ p p)�1

for p-type silicon, and (3.3a)

� � (q

μ n n)�1

for n-type silicon

(3.3b)

where q is the elementary charge 1.602 � 10�19 C, μp (μn) is the mobility of holes (electrons), and p (n) is the density of holes in the valence band (electrons in the conduction band). The mobility values of Eqs 3.3a and 3.3b are not constants, but instead are dependent on the dopant densities, mainly at high concentrations of �� 1015 cm�3. The carrier concentration induced by the doping is approximately equal to the dopant density for the typical dopant elements and densities. In the lightly doped region, at concentrations of �1016 cm�3, the resistivities at 23°C are approximately (based on SEMI MF723-0307 [38]) ρ (ohm-cm) ≈ 1.3 � 1016 /N A (cm�3 ) (3.4a) for boron-doped, p-type silicon, and ρ (ohm-cm) ≈ 4.5 � 1015 /N D (cm�3 ) (3.4b) for phosphorus-doped, n-type silicon

Here, NA (ND) is the boron (phosphorus) concentra tion. The simple Eqs 3.4a and 3.4b are only for the lightly 3.4 Resistivity doped case; they have relatively limited accuracy at higher concentrations. However, a more general and accurate The resistivity, ρ, and conductivity type (p-type vs. correlation between the resistivity and dopant concentra n-type) of crystals are controlled by adding precise tion, valid in lightly and highly doped p-type and n-type amounts of the speciﬁed acceptor or donor impurities silicon, can be presented by using parameterized functions, 42

Properties of Silicon Crystals

CHAPTER 3

1.E+04 p-type / boron

1.E+03

n-type / phosphorus

Resistivity (ohm-cm)

1.E+02 1.E+01 1.E+00 1.E+12

1.E+13

1.E+14

1.E+15

1.E+16

1.E+17

1.E+18

1.E+19

1.E+20

1.E−01 1.E−02 1.E−03 1.E−04 Dopant density (cm–3)

Fig 3.3 ● Resistivity vs. dopant density at 23°C, calculated according to SEMI MF723-0307. The two separate curves correspond to boron-doped (p-type) (upper, solid curve) and phosphorus-doped (n-type) silicon (lower, dashed curve).

ρ(g) ≈ ρ(g � 0) � (1 � g)1�k 0

(3.5)

10 9 Resistivity (ohm-cm)

which can be found in SEMI MF723-0307 [38], together with the references to the experimental data on which the ﬁt is based. The resulting accurate curves are shown in

Figure 3.3 and are basically for boron and phosphorus,

although the latter curve is also a relatively good approxi mation for antimony and arsenic. The correlation is very

practical as it allows the calculation of the axial resistiv ity proﬁle if the axial concentration proﬁle is known (e.g.,

from the normal freezing equation) or, correspondingly,

the axial concentration proﬁle if the axial resistivity varia tion is known (e.g., from resistivity measurements).

Figure 3.4 shows typical examples of experimen tal resistivity curves of lightly boron- and phospho-

rus-doped, p- and n-type crystals, indicating a larger resistivity variation along the crystal for the dopant with a smaller value of k0 (i.e., phosphorus in this case) (see Table 3.3). The actual curve shapes can be explained and analyzed by using the relationship of SEMI MF723-0307 [38] and the normal freezing equation (see Eq. 3.2). The resulting ﬁtted values of the distribution coefﬁcients, denoted by k in the ﬁgure, are quite close to the values of k0 in Table 3.3. As a rule of thumb, the concentra tion of boron in p- or p� -type (phosphorus in n-type) crystals will vary by a factor of 1.6 (4.5) within the typical body length of g0.0 to g0.9 in CZ growth because of normal freezing behavior. According to Eqs 3.4a and 3.4b, the resistivity will vary along the body by approximately the same factors as given above for the dopant concentrations. The resistivity in lightly boronor phosphorus-doped crystals approximately obeys the following equation:

8 7 6 5

Resistivity p-type (boron) Resistivity n-type (phosphorus) Theory for boron (with k = 0.77) Theory for phosphorus (with k = 0.34)

4 3 2 0

0.2

0.4

0.6

0.8

Solidified fraction of melt, g

Fig 3.4 ● Experimental axial resistivity variation in typical p-type (boron-doped) and n-type (phosphorus-doped) crystals presented as a function of g in the body. The solid and dashed curves are obtained by ﬁtting the normal freezing equation to the resistivity curve shape. The ﬁtted values of the distribution coefﬁcients are given in the ﬁgure.

Depending on the dopant element and the resistivity speciﬁcation, which deﬁnes the upper (ρmax) and lower (ρmin) limits of the resistivity allowed for the wafers, either the whole crystal or only part of it is within the resistivity speciﬁcation, the latter case giving a lower commercial crystal yield and higher cost per wafer. Figure 3.5 shows the fraction of the body within the resistivity speciﬁcation as a function of the ratio ρmax/ρmin of the limits of the resistivity speciﬁcation. The curves of Figure 3.5 are approximations calculated by using Eq. 3.5, assuming that the resistivity in the beginning of the body at g0.0 is accurately adjusted to be equal to ρmax 43

Silicon as MEMS Material

PA R T I

1.2

80

p-type / boron n-type / phosphorus

60 40 20 0 1

1.5

2

2.5

3

3.5

4

4.5

5

Resistivity/Resistivity at g = 0

Fraction of body within specification (%)

100

Beginning of crystal

1

End of crystal

0.8 0.6 0.4 As (n+) (no evaporation) As (n+) (with evaporation) Sb (n+) (no evaporation) Sb (n+) (with evaporation)

0.2

Resistivity ratio of specification

Fig 3.5 ● Fraction of body within resistivity speciﬁcation in boron- or phosphorus-doped crystals. Here, the resistivity ratio is deﬁned as the ratio ρmax/ρmin between the upper (ρmax) and lower (ρmin) resistivity limits allowed by the wafer speciﬁcation.

and the body ends at g0.9. Although the model in Figure 3.5 is an approximation, it already describes the main trend. The optimal case, with 100% of the body in the speciﬁcation, is only reached for a speciﬁcation that is wide enough (see Note 3 [40]). For example, for a resistivity speciﬁcation 8.0–14.0 ohm-cm (i.e., for ρmax/ρmin � 14.0/8.0 � 1.75), Figure 3.5 suggests that the whole body of a boron-doped p-type crystal can be adjusted to be within the speciﬁcation, while only about 60% of the body of a phosphorus-doped n-type crystal is within the requested range for a similar speciﬁcation, while the rest of the crystal would be unﬁt. The differ ent shapes of the curves give a natural explanation for the fact that relatively wide resistivity speciﬁcations are preferred for phosphorus-doped wafers, while consid erably narrower speciﬁcations are possible for borondoped wafers. Dopants with k0 ��1 (e.g., gallium, which is only rarely used), would result in an even larger resistivity variation compared with that of boron or phosphorus [3]. In highly doped n� crystals—doped with antimony, arsenic, or phosphorus—the resistivity curves cannot be predicted by using Eq. 3.2. This is because the resis tivity curves of n� crystals are contributed by dopant evaporation from the melt, which depends on the dopant element and the process parameters, such as argon gas mass ﬂow, the pressure of the chamber during pulling, the hot zone design, and the dopant concentra tion in the melt. Therefore, the enrichment of dopants in n� crystals is slower and the axial resistivity varia tions smaller than the normal freezing equation would suggest [20, 41], which results in a narrower distribu tion of resistivities within a crystal (see Figure 3.6), which is largely beneﬁcial considering the quality of the wafers. In extreme cases, the resistivity may even increase with the body length position in n� crystals if 44

0 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Solidified fraction of melt, g

Fig 3.6 ● The ﬁgure indicates the theoretical result of the normal freezing equation for antimony- and arsenic-doped crystals and, schematically, the behavior with evaporation. Note that the latter curves, which include evaporation, are not unique, but will vary if any process parameters or conditions affecting evaporation are changed.

evaporation is very strong [20], but this process region is typically not used. Most of the lightly doped CZ crystals have resistivity targets somewhere between 1 and a few tens of ohmcm in the beginning of the body. The highest and low est resistivities achievable in CZ crystals are far beyond this range in both directions, and depend on the dopant and process conditions. If the resistivity target is too low compared with the process capability, it becomes impossible to grow the crystal without dislocations. Typically, the lowest resistivity speciﬁcations for highly doped 6 in. crystals are in the order of �3 mohm-cm for boron and arsenic, �1.5 mohm-cm for phosphorus, and �17 mohm-cm for antimony. These lowest resistivities are, as a general rule, used in the fabrication of power devices, while they are not common in MEMS. The highest resistivities achievable in CZ crystals are above 1 kohm-cm and are only reached by carefully control ling the purity in order to avoid unintentional dopants. The resistivity ranges covered thus correspond to dopant densities within a wide range of 1012…1020 cm�3.

3.5 Radial Variation of Impurities and Resistivity The measured or speciﬁed value of the resistivity or oxy gen concentration typically refer to the value at the radius r � 0 unless otherwise deﬁned, and describes accurately only a fraction of the wafer area, missing the periphery area. The dopant and oxygen concentrations typically

Properties of Silicon Crystals 1.25

2

Scaled resistivity

Oxygen gradient (%)

6 in. p<100> 6 in. n<111>

1.20 1.15 1.10 1.05

0 −2 −4

–75 –60

–45 –30

–100 15

30

45

60

75

Radius (mm)

Fig 3.7 ● Resistivity proﬁles of lightly boron-doped 6 in. p �100� and lightly phosphorus-doped 6 in. n �111� crystals, scaled by the resistivity at r � 0. The differences between the two curves are due to different dopants and orientations.

decrease, and resistivity increases, toward the wafer edge, the resistivity in most cases showing U- or Wshaped curves along the diameter as shown in Figure 3.7. This radial dependence of the dopant concentration adds to the variations of properties of the devices if these are sensitive to the charge carrier density and resistivity of the substrate. Large radial variations in oxygen may result in large variations in oxygen precipitation behavior and gettering efﬁciency or a greater risk of slip formation during thermal cycles. The amount of radial variation of dopants and oxygen also shows dependence on the body length position in the crystal due to the corresponding changes in the process parameters, the amount of the remaining melt, and the melt ﬂow characteristics. The radial proﬁles also vary to some extent from one wafer to the next because the proﬁles are contributed by vary ing concentration striations, caused by ﬂuctuations in the melt ﬂow and/or melt temperature and growth rate of the crystal (see Chapter 2 and Refs [42] and [43]). Examples of the experimental curves for resistivity and oxygen are shown in Figures 3.7 and 3.8, respectively. Relatively high crystal rotation rates and suitable val ues for other parameters affecting the mixing of the melt and its concentration variations are essential for reaching tolerable radial variation in the crystal, although a certain amount of radial inhomogeneity still remains. The radial resistivity variation is affected by the dopant and orientation, and relatively different radial proﬁles are obtained for different products. For example, the variation is greater in phosphorus-doped (n-type) vs. boron-doped (p-type) crystal of the same orientation. In fact, the variation is often greater for the dopants that have lower k0 values, because a small k0 allows and gives rise to greater variations in the effective value keff in the radial direction, while the impurities with k01

8 in. p<100>, Process A 8 in. p<100>, Process B

−6

1.00 0.95 –15 0

CHAPTER 3

–75

–50

–25

−8

0

25

50

75

100

Radial position (mm)

Fig 3.8 ● Measured radial variation of oxygen in lightly borondoped 8 in. p �100� crystals grown by using different process parameters. Here, the oxygen gradient, deﬁned later in Eq. 3.6b, is expressed as a function of the radius of the measurement point.

(such as boron with k00.8 or oxygen with k01) could lead to better radial uniformity. In fact, in boron-doped p �100� crystals, the radial variation of the resistiv ity is only a few percent (see Figure 3.7). On the other hand, as shown in Figure 3.8, the oxygen concentration typically decreases with r due to evaporation of oxygencontaining species from the melt, which leads to lower concentrations at the melt surface and in the melt close to the crystal edge than in the melt below the crystal at r0, where the melt is more protected by the crys tal from oxygen evaporation. Evaporation may also contribute to some extent to the radial resistivity vari ations for the dopants antimony, arsenic, or phospho rus in n� crystals. In n� crystals, the concentration of antimony, arsenic, or phosphorus will decrease and resistivity will increase signiﬁcantly with increasing r (see Figure 3.9). Furthermore, �111� -oriented crystals often have greater radial variation in the resistivity than correspond ing �100�-oriented crystals (see Figure 3.9). This dif ference is due to the formation of a planar {111} facet in the center of the growth interface of the �111� crystal during growing [20, 44, 45], as schematically presented in Figure 3.10. The {111} facet region has a larger effective distribution coefﬁcient than the sur rounding interface (for impurities with k0 �1) because of the fast lateral growth of atomic layers in the {111} facet. This increase in the intake of the dopant leads to a lower-resistivity region in the center of the crys tal and wafers. However, we should point out that the facet is formed in the center of a �111� crystal only if the isotherm of the melting point is convex toward the melt in the center of the growth interface. The facet, in such cases, is due to the difﬁcult nucleation of the close-packed {111} plane, which needs a consider able amount of undercooling to form [44, 45]. In other 45

Silicon as MEMS Material

PA R T I

0

1.3

Scaled resistivity

1.1 1.0 6 in. n+ (100) (As)

0.9 0.8 –30 –15 0

–75 –60 –45

6 in. n+ (111) (As) 6 in. n+ (111) rescaled by 0.87

15

30

45

60

75

Fig 3.9 ● Resistivity proﬁles of As-doped 6 in. n� �100� and �111� crystals, scaled by resistivity at r � 0. The difference between the orientations is due to the {111} facet in �111� orientation, more clearly seen after the curve for �111� is rescaled by a factor of 0.87.

Crystal a b

b

Melt Isotherm Facet

Fig 3.10 ● Formation of a {111} facet in the center of the meltcrystal interface in a �111� -oriented crystal. The facet is only formed if the isotherm of the melting point (T � Tm) is convex in the center region and the crystal orientation is �111� (see the ﬁgure on the left). The facet results in a lower-resistivity region (b) in the core of the crystal and wafers compared with the surrounding “normal” area (a) as shown in the ﬁgure on the right.

cases, such as �111� crystals with a concave interface, or �100� or �110� crystals with either a convex or a concave interface, no facet is formed in the center and the radial resistivity proﬁles remain practically inde pendent of the orientation. Figure 3.9 shows experi mental data on a 6 in. n� �111� crystal in which a {111} facet has decreased the resistivity in the crystal core due to an increase in the value of keff for arsenic by a factor of more than 1.1 in the facet. This effect can lead to considerable radial variation in the resistivity of n� �111� crystals. Also, the resistivity proﬁle of the lightly doped 6 in. n �111� crystal in Figure 3.7 has a contribution from a facet, which, in this case, has a radius of 20 mm. Contrary to the case of dopants and resistivity, a �111� facet has practically no effect on oxygen concentration. Thus, in lightly doped crystals, the radial oxygen variation is almost independent of the crystal orientation, whether it is �100�, �111�, or �110�, and also independent of the dopant. 46

–4

–6

–8

–10

–12

–14

–16

–18

65

70

75

Radial position (mm)

Radius (mm)

a

Oxygen gradient (%)

–2

1.2

Fig 3.11 ● Relative shift in Oi in the vicinity of the crystal edge compared with Oi at r � 0. The results are for a 6 in. p � 100� crystal with a diameter of 157 mm (radius � 78.5 mm) and Oi(r � 0)13.6 ppma. Note that during further processing of the crystal into wafers, the radius in excess of 75 mm is removed. The actual results are indicated by symbols, while the dashed line is only a guide for the eye.

The radial oxygen or resistivity variations in silicon wafers are often described or speciﬁed by “gradient” values, which are deﬁned as the relative change in resis tivity or Oi from the center (r � 0) to a certain radius value (r) closer to the edge, that is Resistivity gradient (%) � 100 � [ρ(r) � ρ(center)]/ρ(center) (3.6a) Oxygen gradient (%) � 100 � [Oi (r) � Oi (center)]/Oi (center) (3.6b)

For example, for oxygen gradient, the measurement point r deﬁned in wafer speciﬁcations is typically 10 mm inward from the wafer edge. Thus, r � 65 or 90 mm in the measurements for a wafer diameter of 150 or 200 mm, respectively (see SEMI MF951-0305 [46]). The typical absolute value of the measured oxygen gra dient in lightly doped �100�, �111�, or �110� crys tals is about 5% or less for the standard measurement position. (In n� crystals, the oxygen gradient values are often much higher but are not routinely measured.) In wafer speciﬁcations, the absolute values of the gra dients in Eqs 3.6a and 3.6b are typically limited to a certain range. Further variations in resistivity and oxy gen take place even up to the crystal surface, as shown for oxygen in Figure 3.11, where the relative shift in Oi (i.e., the oxygen gradient) is indicated as a function of r in Eq. 3.6b. In this particular case, the gradient for r � 65 mm was 4%, but it increased considerably if measured closer to the crystal edge. Oi at r 75 mm was about 14% (or 2 ppma) below Oi at r � 0. The region very close to the edge has the largest gradient values but is also more difﬁcult to measure accurately

Properties of Silicon Crystals

1200

Crystal temperature (°C)

and is not routinely studied. Also note that the excess diameter of the crystal relative to the diameter speciﬁed for the wafer (i.e., some of the material with the highest gradient) is removed by grinding, which slightly improves the quality.

The radial variations in the resistivity and oxygen

are the ones most accurately controlled and speciﬁed among the impurities. However, other impurity con centrations have radial dependence. For example, the iron concentration may increase and, correspondingly, the recombination lifetime in p-type crystal (Eq. 3.1) decreases in the vicinity of the crystal surface, while the core maintains a higher purity. This increased contamination has been found to originate from the diffusion of iron from the furnace atmosphere directly into the hot crystal surface during growth [47]. The surface region inﬂuenced most has a depth in the order of 10 mm in these cases.

CHAPTER 3

1000

Seed section

800

600 Tail section 400 0

2

4

6

8

10

Time after solidification (h)

3.6 Thermal Donors Thermal donors (oxygen donors) are a class of sev eral species of electrically active oxygen complexes, consisting of small aggregates of a few oxygen atoms [48, 49]. Thermal donors are important defects as they are quite common in CZ silicon and may have a harmful and unpredictable/unstable effect on the resistivity and even the conductivity type of lightly doped crystals and wafers if the thermal donors are not properly taken into account. The carrier concentration will be decreased (increased) by the amount of electrons added by the thermal donors (ΔnTD) in p-type (n-type) crystals, leading to a corresponding increase (decrease) in the resistivity. In extreme cases, if ΔnTD exceeds the initial hole concentration of a p-type material, a change in the conductivity type from p to n takes place, and the resis tivity becomes deﬁned by the remaining electrons. The most important thermal donors to be considered in crystal growth are the species formed at relatively low temperatures, at 300–500°C, especially around 450°C, while the species formed at higher temperatures are less important. The concentration of thermal donors depends on the interstitial oxygen concentration Oi and the time spent at the critical temperatures during cooling of the crystal or during subsequent heat treatment of wafers [48, 49]. The generation rate of thermal donors is highest at 450°C, while already considerably lower at 400°C or 500°C, and is proportional to Oin where n 4 at 450°C (i.e., the generation is relatively strongly depending on the oxygen concentration). In FZ silicon, practically no thermal donors are formed as Oi 0 ppma, while in CZ silicon, the Oi level has an important effect on their forma tion rate. The donor concentration increases approximately linearly with the time spent at the formation temperature,

Fig 3.12 ● Measured thermal history of a 6 in. �100� crystal. Source: The curves are from [7], reproduced by permission of ECS – The Electrochemical Society. Time of 0 corresponds to the moment of solidiﬁcation at the melting point.

although it may ﬁnally saturate and even start to decrease after prolonged treatment [49]. According to Ref. [50], the formation of thermal donors is enhanced (suppressed) in heavily doped, p-type (n-type) silicon with a dopant concentration �1016 cm�3. However, the intentional dopant concentration in highly doped crystals typically exceeds the thermal donor concentration considerably and, thus, thermal donors have no detectable effect on the resistivity of p� or n� crystals. The crystal will always experience the 450°C region during the growth process as the crystal cools from the melting point of 1412°C toward room tempera ture. The temperature vs. time behavior during growth (i.e., the thermal history) is a property of each particu lar CZ growth process. Figure 3.12 shows an example of thermal history curves [7] where, as usual, the begin ning of the body has experienced a longer thermal his tory than the end part. According to a simple model, the thermal donor concentration in the as-grown crystal is approximately inversely proportional to the cooling rate at 450°C. The critical temperatures 400–500°C are also encountered during later processing of the wafer and/or devices. In practice, the concentration of ther mal donors in the crystal after growing is often large enough to have a detectable effect on the resistivity of lightly doped p- or n-type wafers. The added electron concentration ΔnTD may exceed 1015 cm�3 after crystal growth at relatively high Oi’s, although ΔnTD is much smaller for low Oi’s. The highest ΔnTD and the greatest 47

PA R T I

Silicon as MEMS Material

effect on the resistivity are typically found in the begin ning of the body, which has a longer thermal history than the end part, although any axial variation in Oi also contributes [7, 20]. Figure 3.13 shows an example of the resistivity behav ior of a p-type crystal in which the boron acceptors are partially compensated by thermal donors after crys tal growth, after letting the crystal cool down to room temperature. The beginning of the body of the as-grown crystal, especially, is almost fully compensated and has a high resistivity. An analysis of the resistivity shift shown in Figure 3.13 leads to the following values of the added electrons: ΔnTD2 � 1015 cm�3 in the beginning of the body and ΔnTD5 � 1014 cm�3 in the end of the body. The results suggest that for this crystal, the body region at �600 mm has experienced a much longer thermal history at the critical formation temperatures compared with the region at �1200 mm, in agreement with the expected differences in the thermal history of the various crystal parts. A comparison of the value ΔnTD1015 cm�3 and Oi15 ppma � 7.5 � 1017 cm�3 indicates that only a minor fraction of oxygen has formed thermal donors, as expected. To prevent the effects of thermal donors, it has been a common practice to heat-treat lightly doped p- and n-type wafers at about 650°C for at least some tens of minutes during wafer fabrication [51]. The treatment at �600°C will effectively eliminate the thermal donors as indicated by the resistivity curves in Figure 3.13. Cooling the wafers relatively quickly from 650°C through the 450°C region to room temperature after the “donorkilling” treatment leaves the thermal donors no time

Resistivity (ohm-cm)

1.E+03 Before donor killing After donor killing

1.E+02

1.E+01

1.E+00 0

200 400 600 800 1000 1200 1400 1600 1800 Length position (mm)

Fig 3.13 ● Resistivity vs. length position in the body of a borondoped p-type crystal. The resistivity has been measured before (upper curve) and after (lower curve) thermal treatment (“donor killing”) of the samples at 650°C, eliminating the thermal donors. The effect of thermal donors is greatest in the beginning of the body. The interstitial oxygen concentration of the crystal is about 15 ppma in new ASTM units. (The lines connecting the points are only guides for the eye.)

48

to reform, and the subsequent resistivity values and con ductivity type will be deﬁned by the “stable”, intentional dopant element boron or phosphorus only. In principle, thermal donors may also be formed or eliminated, even multiple times, during any subsequent wafer or device processing step at 450°C or �600°C, respectively. In extreme cases, the thermal donors existing after ﬁnish ing the processing may cause quality problems or failure of the devices if the remaining resistivity shift is large enough to harm the device properties. For example, the threshold voltage of metal-oxide-semiconductor ﬁeld-effect transistors, processed on lightly doped sub strates, can shift due to thermal donors [52]. Note also that Oi in the wafer may decrease from its initial, crys tal-originated value during device processing as a result of oxygen out-diffusion (typically due to denuded zone formation) or precipitation [51, 53], or Oi may possi bly increase because of oxygen in-diffusion [54]. These changes in Oi have an effect on subsequent thermal donor formation in the regions of the wafer where Oi has shifted (i.e., close to the surface for out-diffusion and in the bulk for precipitation) [51, 53].

3.7 Defects in Silicon Crystals A large variety of grown-in and process-induced defects have been identiﬁed in CZ silicon crystals and wafers (see, e.g., Refs [2, 8, 20, 55]). Some of the defects are directly connected to the success or failure of the crys tal growth process or deﬁned by the growth parameters, while other defects are contributed or dominated by the following process steps from crystals into wafers and, ﬁnally, into devices. Also the ease of detection of the defects varies from simple visual inspection of crystals to more difﬁcult or indirect methods. Crystal defects can also be classiﬁed also according to their dimension ality into point defects, line defects, area defects, and volume defects (see Chapter 1). We will concentrate on those defects that can have a direct connection to the crystal growth and its process parameters, defects that are important considering the intended use of the wafers, and are, in many cases, also measured regularly. Such defects include (slip) disloca tions, twins, bubble inclusions, vacancies and their aggre gates (octahedral microscopic voids that can be detected, e.g., as crystal-originated particles (COPs), on the wafer surface), self-interstitials and their aggregates (large dis location loops), stacking faults (SFs) formed near the wafer surface by oxidation treatments (i.e., oxidationinduced stacking faults [OISFs]), oxygen precipitates, bulk SFs, and dislocation loops. Among these defects, SFs and dislocation loops are often caused by oxygen precipitates (see Chapters 4 and 21). Some of the typi cal defects found in crystals and wafers have a strong

Properties of Silicon Crystals

Temperature (°C)

correlation to the thermal history of the crystal during its growth (see Figure 3.14 where the dominating for mation temperatures of defects [8, 28, 49, 55–59] are approximately indicated). The effect of the defects on the properties and yield of devices processed on the wafers are characteristic to each particular process and application, although certain general trends and risks can be indicated. The defects may lead to failure or decrease the quality of devices or, more speciﬁcally, to a decrease of carrier lifetimes (e.g., metal or oxygen precipitates), an increase of leak age currents in devices (e.g., metal precipitates, dislo cations, or SFs), or quality problems with gate oxides (e.g., voids or other defects such as metal precipitates near the wafer surface) [2, 14, 15, 18, 60]. Decoration of dislocations or SFs by metal impurities may further increase the detrimental inﬂuence of these defects on the junctions of the devices. Considering MEMS fab rication, defects such as oxygen precipitates and SFs may increase the surface roughness and decrease the anisotropy in anisotropic wet etching [61, 62]. Therefore, in MEMS wafers, the highest oxygen concen trations are avoided to suppress the formation of oxygen precipitates and associated defects, especially if wet etching is used to form the structures for the sensors. Furthermore, considering optimized crystal properties and the control of defects, special wafers (e.g., siliconon-insulator (SOI) [see Chapter 7]) often have slightly different requirements and quality risks compared with the more ordinary wafers. Short descriptions of the typical defects in CZ silicon are given from the point of view of crystal growth in the list below, while we refer to the literature for more detailed information.

1400

1300

1200

1100

1000

900

800

700

600

500

400 300

Vacancies, self-interstitials, OISF ring radius (1412°C)

Voids (vacancy clusters) (1000…1150°C)

Dislocation loops (self-interstitial clusters) (1000°C)

Nuclei for oxygen precipitation

(500…800°C)

Thermal (oxygen) donors (450°C)

0

1

2

3

4

5

6

7

8

9 10 11 12 13

Time from solidification (h)

Fig 3.14 ● Thermal history of a crystal (the timescale starting from the moment of crystallization) and the formation temperatures of various defects during crystal growth. The formation temperatures indicated are approximate consensus values collected from the literature. ( The thermal history curve is only schematic.)

CHAPTER 3

Dislocations and slips: The dislocations are line defects, which in silicon lie on the {111} slip planes. The word “slip” is used to denote the formation and propa gation mechanism of dislocations, as well as the visually detectable lines formed on crystal or wafer surfaces by a large number of dislocations. The CZ single crystals are grown as dislocation-free, although, sometimes, due to a disturbance at the melt-crystal interface and/or high thermal stress in the crystal, dislocations may appear, multiply, and propagate in the crystal during growth. The crystal after this point soon becomes multicrystalline [20, 63]. Dislocations are also spread backwards to the already-formed crystal within a characteristic distance of the same order of magnitude as the crystal diameter, while the even earlier region still remains dislocation-free. (In some rare, exceptional cases of highly boron-doped p� crystals, dislocations have been found to propagate along the body without causing polycrystallization [64], contrary to the general behavior.) Dislocations in wafers could have a negative impact on the device yield, and wafers with dislocations already in the beginning also suf fer from further dislocation generation more easily than dislocation-free wafers. Therefore, the dislocated, as well as the even worse, multicrystalline parts of the crystal are rejected from further processing into wafers, which correspondingly decreases the crystal yield. Fortunately, most of the crystals are dislocation-free through the whole body. Furthermore, it is relatively easy to detect the position where the dislocations ﬁrst appeared dur ing growth as the crystal shape changes, especially as its characteristic growth lines are cut and disappear starting from the position where the dislocations appeared [63]. The reason for this external shape change is that the dis locations decrease orientation-dependent differences in the growth at the growth interface [44]. More speciﬁ cally, small {111} side facets at the edge of the interface, responsible for growth-line formation, shrink and, ﬁnally, disappear due to dislocations, which also ends the growth lines. Visual inspection of the crystal, especially the con tinuity of the growth lines and the existence of slip lines on the surface, is among the basic quality control meth ods used for material quality veriﬁcation. Although only dislocation-free material is processed into wafers, which are, thus, initially dislocation-free, the strength of the wafers against the slip formation and plastic deformation in later high-temperature process ing is increased by interstitial oxygen, while formation of large oxygen precipitates exposes the wafers to slip generation [8, 65]. The risk of such plastic deformation can be reduced by selecting the target of Oi properly (although other requirements for oxygen also have to be taken into account) and by keeping the axial and radial variations of Oi within reasonably tight limits. In addi tion to oxygen, dopants at high concentrations have an impact on dislocation generation. According to Ref. [5], 49

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concentration of boron, phosphorus, or arsenic in excess of 1019 cm�3 (resistivity in the sub 10-mohm-cm region) increases the critical stress for dislocation generation. Twins: A twin in silicon crystal corresponds to a defect where the lattice is changed to its mirror image on the other side of a {111} plane, called a “twinning plane” [66]. In �100� and �111� crystals, the vector perpen dicular to the twinning plane is inclined with the growth axis by an angle of about 54.7° or 70.5°, respectively, while in �110� crystal, the angle is either 35.3° or 90.0°, the latter case corresponding to a twinning plane parallel to the crystal axis. Twins may be found after the CZ silicon crystal has lost its single-crystalline structure and is becoming multicrystalline. They are also some times seen even without the loss of structure, although quite rarely. The twins are not allowed in wafers because the twin boundary and the shift of the crystal orientation would probably lead to failure of devices. Thus, the unﬁt region, where the twinning plane penetrates the crystal, is rejected as well as any misoriented material. Bubble inclusions: Relatively large, approximately spherical pits, with sizes up to several millimeters, are occasionally seen on wafer surfaces. These pits originate from small volumes of gas (e.g., argon) remaining as bubbles in the melt after melting [2]. Also, gases in sil ica crucibles [67] or gases originating from post-melting doping or silicon feeding procedures [68] can sometimes contribute to the pocket formation. Some of the bubbles may remain in the melt, possibly at the melt-crucible interface, for quite a long time and ﬁnally become trans ported with the melt ﬂow to the melt-crystal interface where the silicon solidiﬁes around the bubble, causing a void. Wafer slicing, lapping, grinding, etching, or pol ishing may reveal the in-grown bubbles as air pockets on the wafer surface or as holes through the wafer, the latter case being shown in Figure 3.15. Fortunately, the incidence of bubbles in wafers can be kept at a very low level by using suitable crystal-growing and wafer-inspec tion procedures, and bubble inclusions are typically not a major quality issue. The rare wafers with large open pockets of 1 mm are relatively easily detected and identiﬁed by the eye and are rejected in wafer fabrica tion, while much smaller pockets may contribute to the defect count in the ﬁnal surface inspection [69]. However, hidden voids in the bulk of the wafers pass the tests and may sometimes cause local yield losses in device processing, especially if the bubble becomes open after removal of material from the wafer surface. Vacancies and self-interstitials and their clusters: The vacancy- and self-interstitial-related defects have a strong connection to the process conditions used during crystal growth [55, 57, 58, 60, 70] and will be discussed in more detail in Section 3.8 below. OISFs: The OISFs are generated by silicon self interstitials injected into the wafer during oxidation of 50

Fig 3.15 ● Photograph of a 6 in. wafer rejected after slicing due to a large bubble inclusion.

the wafer surface. An OISF test, either a standard one (e.g., SEMI MF1727-0304 [71], SEMI MF1810-0304 [72]) or a test representative of the oxidation cycles in a particular fabrication process, is used to determine a well-deﬁned value for the OISF concentration of the sample wafers. The result has correlation with the tendency of the wafers to form OISFs during oxida tion steps during actual device processing. Figure 3.16a shows an example of OISFs revealed on the surface of a phosphorus-doped n �100� wafer. The OISFs are formed as the injected self-interstitials agglomerate into SFs of an extrinsic type between two adjacent {111} planes, the defects being bound by Frank partial dis location loops [2, 20]. The defects in Figure 3.16 can be seen in positions where SFs intersect the wafer sur face. The lines of the defects on the surface of �100� wafers have two possible directions, which have an angle of 90° between each other, while OISFs in other wafer orientations have their characteristic angles. The OISFs preferably nucleate at defects such as metal pre cipitates, mechanical defects or damage, or oxygen pre cipitates if these exist in the wafer [2], and the OISF density may reﬂect the quality of the crystal, as well as the effects of further processing steps prior to the OISF test. It is quite common for the users of the wafers to spec ify the upper limit for the OISF density of the wafers (e.g., 100 OISFs per cm2). The actual concentration of OISFs in boron-doped p �100� wafers is typically on the order of 1 cm�2 after a standard OISF test, while slightly higher values are often found in phosphorus-doped n �100� wafers, especially in those taken from the region close to the tail of the crystal. On the other hand,

Properties of Silicon Crystals

Fig 3.16 ● (a) Oxidation-induced stacking faults (OISF) on the surface of a lightly phosphorus-doped n �100� wafer. The defects were relatively uniformly distributed over the surface. (b) Example of OISFs in an OISF ring of a highly boron-doped p� �100� wafer. Here, OISFs were concentrated in the narrow ring, while the rest of the area was practically free of OISFs. The ﬁgure is taken from the ring region.

the OISF concentrations in n� crystals doped with anti mony, arsenic, or phosphorus are low. The reason for the higher OISF density in lightly phosphorus-doped, n-type material is still unclear to a certain degree, but the incre ment seems to be contributed, for example, by the ther mal history of the end part of the crystal. Furthermore, impurities may play a role here and the addition of copper into the melt has been found to increase, and aluminum to decrease, the OISF density in phosphorusdoped, n-type crystals [73]. High OISF concentrations are sometimes seen in highly boron-doped p� �100� wafers, resulting from the enhanced oxygen precipitation in the bulk due to high boron concentration. The strong precipitation induces and favors SF formation over the whole thickness of the p� wafer [8, 74], although the result is expected to be sensitive to the resistivity, oxygen

CHAPTER 3

concentration, length position in the crystal, and the cor responding thermal history. Additional heat treatments of the wafers prior to their oxidation may also increase the risk of high OISF density if the wafers have a tendency to form OISFs. In �111� -oriented wafers, the OISF con centrations are typically low and lower than in �100� wafers with the same doping level and dopant. The OISFs can either be distributed relatively evenly over the wafer surface or the distribution may, for example, reﬂect the location of mechanical defects or contamination if such exist. Furthermore, in some cases, a dense “ring” of OISFs is formed, resulting from a certain distribution of interstitials and vacancies, and is controlled by the crystal-growing process conditions [55, 58, 60]. The circular shape and the narrow width of only a few millimeters of the OISF ring allow the distinguishing of the OISF ring from OISFs of other origins. Figure 3.16b shows a microscope picture taken from the ring region of an OISF ring. The origin of the ring will be discussed in more detail in Section 3.8. Oxygen precipitates: The formation and properties of oxygen precipitates and their useful and harmful inﬂu ences [6, 8, 9, 14, 65] are central items, which will be discussed in more detail in Chapter 4. Oxygen precipi tates are typical sources and nucleation sites of SFs and dislocation loops in the bulk and, sometimes, in the sur face region of the wafers; they also have an effect on the mechanical strength of wafers. The precipitation of oxygen is enhanced in boron-doped p� wafers and it is retarded in Sb-doped n� wafers [8, 37, 75, 76], while precipitation behavior is independent of the dopant type and concen tration at lower dopant concentrations of �5 � 1016 cm�3 [75]. The effect of high concentrations of boron or anti mony seems to be valid even for samples that have similar initial oxygen concentrations as the lightly doped refer ence wafers have, although the differences in the oxygen concentrations between these products often contribute considerably to the precipitation behavior seen in prac tice. Also, for n� doped with arsenic or phosphorus, the precipitation is typically retarded [77]. The precipitation in p� wafers, although enhanced in principle, has also been found to have a dependence on resistivity (boron concentration), among other factors. Ref. [35] suggests a considerable reduction of oxide precipitate density in p� for resistivity below a threshold of 7 mohm-cm compared with resistivities slightly above this threshold. However, the exact behavior of p� can be quite sensitive to detailed material and process parameters [78].

3.8 Control of Vacancies, Interstitials, and the OISF Ring The growth parameters and conditions of the crys tal, especially the growth rate, and doping inﬂuence

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the amount of vacancies, self-interstitials, and related defects in the resulting crystal [60, 70, 79–81]. A CZ crystal grown at a high growth rate is known to con tain defects called voids, originating from vacancy clus tering, revealed as COPs, D defects, or ﬂow-pattern defects (FPDs), while at low growth rate, silicon self interstitials form clusters revealed as (large) dislocation loops or A defects [60, 80]. An intermediate growth rate would result in a ring-like OISF region and voids only inside the ring, while the outside region is practi cally void-free, but may contain dislocation loops. The effect of the voids, dislocation loops, and/or OISF ring on the quality and yield of devices depends on the detailed case (exact device structure and its process) and the properties of the defects (e.g., the size distribu tion and density of the voids or dislocation loops). Voids are known to deteriorate the quality of gate oxides [60, 82], while dislocation loops are a potential risk for the yield of certain devices (e.g., Refs. [83]). The theoretical models of the incorporation of vacan cies and silicon interstitials into crystals and the formation of the corresponding defects have been discussed in more detail in review articles such as [55] and [58], so we will not go into the details of the theory or modeling of the defects. Our presentation below is based on the litera ture, as well as our own experience, and will focus on the results that have the greatest importance in practice for understanding the main connections between the crys tal-growing process and crystal quality in order to guaran tee the high quality of the crystal and wafers. The focus is on the CZ crystals, especially on lightly boron-doped p �100� crystals because these are the standard prod uct most frequently discussed in the literature, although relatively similar defects have also been detected in other dopant-orientation combinations [84], as well as in the FZ crystals (see Ref. [60] and references therein). One of the main conclusions of the models and exper iments is that the growth rates (v) of the CZ crystal and the vertical temperature gradient (G) of the crystal in the vicinity of the solid-melt interface, or, more spe ciﬁcally, the ratio v/G, already very accurately predicts whether the resulting crystal at the corresponding length position becomes vacancy-rich (for v/G � Ccrit) or self interstitial-rich (for v/G � Ccrit) [55, 70]). The critical v/G ratio, Ccrit, has been suggested to have a value of about 0.0012–0.0013 cm2/K-min in lightly doped crystals [58, 81]. While either vacancies or self-interstitials domi nate depending on the value of v/G, the concentration of the other minority species becomes negligible due to mutual annihilation of vacancies and self-interstitials. The simple criteria based on the v/G ratio is, according to the literature, due to the larger equilibrium concentration of vacancies at the solid-melt interface at the melting point (compared with that of self-interstitials), favoring vacancies because of the convection by crystal movement 52

during pulling, while, on the other hand, interstitials have a higher diffusivity, favoring a ﬂux of interstitials from the interface into the crystal. The growth rate (which to rea sonable approximation equals the pulling rate of the crys tal during the particular length position in the body) and G inﬂuence these transport processes and the remaining concentration of the point defects. Also, the dopants and impurities inﬂuence the balance between vacancies and self-interstitials [78, 79, 81, 85]. For example, in highly boron-doped p� crystals, the critical value Ccrit of the v/G criteria will increase considerably with increasing boron concentration [81]. The point defect species dominating after the annihi lation process becomes increasingly supersaturated as the crystal temperature decreases, which ﬁnally leads to the formation of larger aggregates—voids in vacancy-rich and dislocation loops in self-interstitial-rich crystals, respec tively. The vacancy-rich crystals are more common of these two among commercial products [55]. The voids typically have a small size of 0.1 μm and their concen tration in standard vacancy-rich material is in the order of 1 � 106 cm�3 (e.g., Ref. [86]) and typically about 100 COPs (small pits detected as particles), with sizes above the detection limit of 0.10 μm are detected on the pol ished 6 in. wafer front surface. In interstitial-rich wafers, however, only a few particles, which are possibly COPs, are detected on the 6 in. wafer surface. The voids are formed during crystal growing at around 1150–1000°C where aggregation of supersaturated vacancies takes place and void-size distribution is formed [56, 57] (see Figure 3.14). The dislocation loops in self-interstitial rich material are much larger, 1–100 μm, compared with voids; have a lower concentration, 104 cm�3; and are formed at 1000°C [56, 79, 80, 87]. In the actual crystal-growing processes, the value of the axial temperature gradient G is not constant, but typically increases (and v/G decreases) with r (see Figure 3.17). In practice, v is controlled by the pull ing rate of the crystal, while G(r) is largely deﬁned by the hot-zone design, although it is also affected to some extent by various growth parameters, including the pulling rate. Curve A in Figure 3.17 corresponds to vacancy-rich and D to interstitial-rich cases, respec tively, while curve C is approximately in the boundary and could basically lead to only relatively few vacancyor self-interstitial-related microdefects [56, 70, 83]. If v/G reaches the critical value at certain r, vacancyrich and self-interstitial-rich regions are formed at different radial regions (see curve B in Figure 3.17). However, in the “mixed-quality” crystals, an OISF ring is typically formed close to the boundary, although slightly toward the vacancy-rich side, at r, where v/G is slightly above Ccrit. The combination of experiments and modeling of G has indicated a critical value of Ccrit,OISF0.00134 cm2/K-min for this v/G ratio where

Properties of Silicon Crystals 0.0025

A

v/G (cm2/ K min)

0.0020

B OISF ring

0.0015

C

Critical v/G for OISF ring

0.0010

D

Critical v/G for v-i boundary v-i boundary

0.0005 0.0000 0

10

20

30

40

50

60

70

80

Radius (mm)

Fig 3.17 ● Simulated v/G vs. r proﬁles for 6 in. crystals with various thermal environments and pulling rates (cases denoted by solid lines A through D). The approximate critical v/G values, denoted by dashed lines, are from [58] and [81], and can be used to estimate the radial position of the interface between the vacancy-rich and self-interstitial-rich regions (v–i boundary) (lower dashed line) and the OISF ring location (upper dashed line), respectively. The arrows indicate the radial positions of the v–i boundary and OISF ring for the growth process of curve B.

CHAPTER 3

wafers have so far not caused signiﬁcant quality prob lems in the majority of cases. On the other hand, largediameter wafers used, for example, for dynamic random access memory (DRAM) fabrication, can have tighter requirements with regard to voids [82, 89] and, there fore, in these cases, controlling the void distribution by using an optimized crystal-growing process and/or additional wafer treatments becomes quite important. Furthermore, in actual crystal production, other quality aspects, discussed earlier in this review, as well as crystal yield and the total production cost of crystal and wafers, have to be taken into account in addition to vacancies, self-interstitials, and the OISF ring when optimizing the process conditions. For example, very low pulling rates lead to lower productivity of crystal growing and may also increase the risk of losing the single-crystalline structure, which are factors that increase the production cost of lightly doped, interstitial-rich material compared with that of vacancy-rich silicon.

3.9 Conclusion the OISF ring appears in lightly doped crystals [81]. The OISF ring shows a highly increased tendency to form OISFs in densities of 1000 cm�2 in the ring in �100� wafers, while few OISFs are found elsewhere. The OISF ring is typically quite narrow, a few millim eters at most. For example, the v/G proﬁle denoted by B in Figure 3.17 is expected to result in wafers with an OISF ring having a radius of 66 mm. The ring origi nates from stable nuclei for oxygen precipitates in the ring region, formed already during crystal growing. Due to these defects, the OISF ring region already shows a reduced recombination lifetime in samples taken directly from the as-grown crystal, without any oxida tion treatments [88]. An example of lifetime deteriora tion at the OISF ring position of an as-grown crystal is shown in Figure 3.18, although this measurement tech nique exaggerates the width of the ring. The OISF ring, voids, and dislocation loops may cause yield losses of the devices processed on the wafers. It is possible to totally avoid the formation of the OISF ring, if necessary or practical, by using suitable proc ess parameters in crystal growing [60, 80] to fulﬁll the quality requirements deﬁned in the speciﬁcation and necessary for the intended use of wafers. The commer cial lightly doped CZ crystals have typically been grown in the vacancy-rich region without an OISF ring, while there has been more variation in the quality of com mercial highly boron-doped p� crystals. Formation and properties of thermally induced defects in p� wafers with or without an OISF ring has been studied in more detail in [74] and [78]. In small-diameter wafers or in MEMS applications, the voids of vacancy-rich standard

We have covered the major properties of CZ silicon crystals in this chapter. The focus has been on those impurities and defects that have the greatest effect on device performance and/or that have proven to be of the greatest importance and interest in the industrial development of the crystal growth process and crys tal quality. By understanding the crystal properties and their connection to the growth process, as well as the inherent limitations of the CZ silicon crystals, it is pos sible to better specify the crystal properties needed and to improve the growth process, as well as the resulting material quality. Improved or more suitable material increases the yield of devices processed on the wafers. The proper CZ silicon used for wafer fabrication is always dislocation-free, contains only relatively insigniﬁ cant concentrations of harmful impurities such as carbon and transition metals, has a reasonably controlled or pre dictable defect formation behavior, and its resistivity and oxygen concentrations are suitable for the intended appli cation. Typical high-quality CZ material has such a low carbon concentration that it has almost no effect on oxy gen precipitation behavior and, similarly, also the amount of various harmful transition-metal impurities (e.g., iron) in the as-grown crystal is typically clearly within accept able limits. Furthermore, the radial and axial uniformity of the properties is important and has been discussed in this review. The radial variation of oxygen and resistiv ity depends on the dopant, resistivity level, and/or crys tal orientation, although other process parameters also inﬂuence the result. In practice, various applications can have quite different requirements for the crystal and 53

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Fig 3.18 ● Map of the recombination lifetime of an 8 in. p �100� wafer, measured by using the microwave photoconductance decay (μ PCD) method. The wafer has a lower lifetime region at a radius of 40 mm, which corresponds to the radius where an OISF ring would

be formed in an OISF test.

the optimization of certain product-speciﬁc properties may be of major concern and challenge. For example, in MEMS wafers, the highest oxygen concentrations are typ ically avoided to keep the bulk defect-free and to make sure that the structures, formed by etching, are of high quality. On the other hand, some other applications may beneﬁt from relatively high oxygen concentration, mainly if strong metal impurity gettering by oxygen precipitates is needed during device processing. Furthermore, the cost of the material is a relevant issue and should be min imized without compromising the quality. For example, an unnecessarily narrow resistivity speciﬁcation leads to a lower commercial crystal yield and, thus, may increase the cost per wafer unless the rejected material has some other commercial use.

The customers’ requirements for the impurities and defects of the crystals and wafers are expected to con tinue to develop in the future as the processed device structures and their complexity, structural dimensions, and processing methods, as well as targets for device per formance, yield, and total cost evolve. The major chal lenge for crystal growth is to answer these expectations.

Acknowledgments Colleagues at Okmetic Oyj, especially the present and former members of the crystal growth R&D group and the laboratory staff, are gratefully acknowledged for their long-term cooperation and contributions to this work.

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40. Note 3: Any other reason for rejecting body material (e.g., oxygen or carbon concentration, dislocations, insufﬁcient crystal diameter or inaccurate doping) can also decrease the yield. 41. K. Izunome, X. Huang, S. Togawa, K. Terashima, S. Kimura, Control of oxygen concentration in heavily antimony-doped Czochralski Si crystals by ambient argon pressure, J. Cryst. Growth 151 (3) (1995) 291–294. 42. T. Carlberg, Some aspects on the formation of striations during crystal growth from the melt , J. Cryst. Growth 85 (12) (1987) 32–39. 43. W. Zulehner, Origin and effects of inhomogeneous impurity distribution in CZ silicon, in: K. Sumino (Ed.), Defect Control in Semiconductors, NorthHolland, Amsterdam/New York/Oxford/ Tokyo, 1990, pp. 143–155. 44. V.V. Voronkov, Statistics of surfaces, steps and two-dimensional nuclei: a macroscopic approach, in: A.A. Chernov, H. Müller-Krumbhaar (Eds.), Crystals, Modern Theory of Crystal Growth I , Springer, Berlin/Heidelberg/New York, 1983, pp. 75–111. 45. K.M. Beatty, K.A. Jackson, Monte Carlo modeling of silicon crystal growth, J. Cryst. Growth 211 (1–4) (2000) 13–17. 46. SEMI MF951-0305, Test Method for Determination of Radial Interstitial Oxygen Variation in Silicon Wafers, SEMI International Standards, 2007. 47. D. Gilmore, T. Arahori, M. Ito, H. Murakami, S. Miki, The impact of graphite furnace parts on radial impurity distribution in Czochralski grown single-crystal silicon, J. Electro chem. Soc. 145 (2) (1998) 621–628. 48. J. Michel, L.C. Kimerling, Electrical properties of oxygen in silicon, in: F. Shimura (Ed.), Oxygen in Silicon, Semiconductors and Semimetals, vol. 42, Academic Press, USA, 1994, pp. 251–287. 49. U. Gösele, E. Schroer, P. Werner, T.Y. Tan, Low-temperature diffusion and agglomeration of oxygen in silicon, in: R. Jones (Ed.), Early Stages of Oxygen Precipitation in Silicon, NATO ASI Series, Kluwer, Dordrecht, 1996, pp. 243–261. 50. K. Wada, Uniﬁed model for formation kinetics of oxygen thermal donors in silicon, Phys. Rev. B 30 (10) (1984) 5884–5895. 51. S. Wolf, R.N. Tauber, Silicon Processing for the VLSI Era, Volume 1: Process Technology, Lattice Press, USA, 1987.

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52. L. Jastrzebski, Silicon crystals for VLSI technologies, in: D.C. Gupta (Ed.), Silicon Processing, ASTM STP 804, American Society for Testing and Materials, Baltimore, 1983, pp. 309–331. 53. T. Abe, W. Qu, High resistivity CZ silicon for RF applications substituting GaAs, in: C.L. Claeys, P. RaiChoudhury, M. Watanabe, P. Stallhofer, H.J. Dawson (Eds.), High Purity Silicon VI, The Electrochemical Society, USA, 2000, pp. 491–500. 54. M. Murata, R. Nayve, T. Mihara, Y. Kondoh, T. Iwamori, Threshold voltage instability due to oxygen thermal donor impurities in metal oxide semiconductor ﬁeld effect transistors, J. Electrochem. Soc. 146 (11) (1999) 4298–4302. 55. T. Sinno, E. Dornberger, W. von Ammon, R.A. Brown, F. Dupret, Defect engineering of Czochralski single-crystal silicon, Mat. Sci. Eng. R. 28 (5–6) (2000) 149–198. 56. N.I. Puzanov, A.M. Eldenzon, The effect of thermal history during crystal growth on oxygen precipitation in Czochralski-grown silicon, Semicond. Sci. Tech. 7 (3) (1992) 406–413. 57. K. Takano, M. Iida, E. Iino, M. Kimura, H. Yamagishi, Relationship between grown-in defects and thermal history during CZ Si crystal growth, J. Cryst. Growth 180 (3) (1997) 363–371. 58. R. Falster, V.V. Voronkov, F. Quast, On the properties of the intrinsic point defects in silicon: a perspective from crystal growth and wafer processing, Phy. Status Solidi (b) 222 (1) (2000) 219–244. 59. K. Sueoka, M. Akatsuka, M. Okui, H. Katahama, Computer simulation for morphology, size, and density of oxide precipitates in CZ silicon, J. Electrochem. Soc. 150 (8) (2003) G469–G475. 60. H. Yamagishi, I. Fusegawa, N. Fujimaki, M. Katayama, Recognition of D defects in silicon single crystals by preferential etching and effect on gate oxide integrity, Semicond. Sci. Tech. 7 (1A) (1992) A135–A140. 61. A. Hölke, H.T. Henderson, Ultra-deep anisotropic etching of (110) silicon, J. Micromech. Microeng. 9 (1) (1999) 51–57. 62. A. Hein, S. Finkbeiner, J. Marek, E. Obermeier, The effects of thermal treatment on the anisotropic etching behavior of Cz- and Fz-silicon, Sensor. Actuator. 86 (1–2) (2000) 86–90.

63. H.M. Liaw, Crystal growth of silicon, in: W.C. O’Mara, R.B. Herring, L.P. Hunt (Eds.), Handbook of Semiconductor Silicon Technology, Noyes Publications, Park Ridge, New Jersey, USA, 1990, pp. 94–191. 64. X. Huang, T. Taishi, K. Hoshikawa, Dislocation-free CZ-Si crystal growth without the thin dash-neck, Int. J. Mater. Prod. Technol. 22 (1/2/3) (2005) 64–83. 65. K. Jurkschat, S. Senkader, P.R. Wilshaw, D. Gambaro, R.J. Falster, Onset of slip in silicon containing oxide precipitates, J. Appl. Phys. 90 (7) (2001) 3219–3225. 66. H.J. Queisser, Properties of twin boundaries in silicon, J. Electrochem. Soc. 110 (1) (1963) 52–56. 67. X. Huang, H. Kishi, S. Oishi, H. Watanabe, K. Sanpei, S. Sakai, K. Hoshikawa, Expansion behavior of bubbles in silica glass concerning Czochralski (CZ) Si growth, Jpn. J. Appl. Phys. 38 (Pt 2, No. 4a) (1999) L353–L355. 68. E. Iino, K. Takano, M. Kimura, H. Yamagishi, Cavities owing to hydrogen in Si single crystals grown by continuously charging CZ method, Mater. Sci. Eng. B36 (1–3) (1996) 146–149. 69. B. Pinto, J. Saito, W. Shen, L. Cheung, A. Wang, New Inspection Technology for 45 nm Wafers, Yield Management Solutions Magazine 9 (1) (Spring 2007) 28–32 KLA-Tencor Corporation. 70. V.V. Voronkov, The mechanism of swirl defects formation in silicon, J. Cryst. Growth 59 (3) (1982) 625–643. 71. SEMI MF1727-0304, Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers, SEMI International Standards, 2007. 72. SEMI MF1810-0304, Test Method for Counting Preferentially Etched or Decorated Surface Defects in Silicon Wafers, SEMI International Standards, 2007. 73. W. Sato, M. Sakurada, O. Tomohiko, K. Kemmochi, Method for the preparation of silicon single crystal, United States Patent, Patent Number 5609682, Date of Patent March 11, 1997. 74. J.-M. Kim, J.-Y. Choi, H.-J. Cho, H.-W. Lee, H.-D. Yoo, Behavior of thermally induced defects in heavily boron-doped silicon crystals, Jpn. J. Appl. Phys. 40 (Pt 1. No. 3A) (2001) 1370–1374. 75. S.K. Bains, D.P. Grifﬁths, J.G. Wilkes, R.W. Series, K.G. Barraclough, Oxygen precipitation in heavily doped silicon , J. Electrochem. Soc. 137 (2) (1990) 647–652. 76. S. Gupta, S. Messoloras, J.R. Schneider, R.J. Stewart, W. Zulehner, Oxygen

Properties of Silicon Crystals precipitation in antimony-doped silicon , Semicond. Sci. Tech. 7 (4) (1992) 443–451. 77. H. Tsuya, Y. Kondo, M. Kanamori, Behaviours of thermally induced microdefects in heavily doped silicon wafers, Jpn. J. Appl. Phys. 22 (1983) L16–L18. 78. E. Asayama, T. Ono, M. Takeshita, M. Hourai, M. Sano, H. Tsuya, Radial distribution of thermally-induced defects in heavily boron-doped silicon wafers, in: H.R. Huff, U. Gösele, H. Tsuya (Eds.), Semiconductor Silicon 1998, The Electrochemical Society, USA, 1998, pp. 546–556. 79. A.J.R. de Kock, W.T. Stacy, W.M. van de Wijgert, The effect of doping on microdefect formation in as-grown dislocation-free Czochralski silicon crystals, Appl. Phys. Lett. 34 (9) (1979) 611–613. 80. S. Sadamitsu, S. Umeno, Y. Koike, M. Hourai, S. Sumita, T. Shigematsu, Dependence of the grown-in defect distribution on growth rates in Czochralski silicon, Jpn. J. Appl. Phys. 32 (Pt 1, No. 9A) (1993) 3675–3681. 81. E. Dornberger, D. Gräf, M. Suhren, U. Lambert, P. Wagner, F. Dupret,

W. von Ammon, Inﬂuence of boron concentration on the oxidation-induced stacking fault ring in Czochralski silicon crystals, J. Cryst. Growth 180 (3) (1997) 343–352. 82. R. Winkler, Inﬂuence of the gate oxide quality on 4Mbit DRAM device failures and reliability, in: C.L. Claeys, P. Rai-Choudhury, P. Stallhofer, J.E. Maurits (Eds.), High Purity Silicon IV, Electrochemical Society Proceedings Volume 96-13, The Electrochemical Society, USA, 1996. 83. L. Mule’Stagno, A technique for delineating defects in silicon, Sol. St. Phen. 82 � 84 (2002) 753–758. 84. D. Gräf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. von Ammon, P. Wagner, Characterization of crystal quality by delineation of COP and the impact on the silicon wafer surface, in: C.L. Claeys, P. Rai-Choudhury, P. Stallhofer, J.E. Maurits (Eds.) High Purity Silicon IV, The Electrochemical Society, USA, 1996, pp. 117–131. 85. M. Porrini, V.V. Voronkov, R. Falster, The effect of carbon and antimony on grown-in microdefects in Czochralski silicon crystals, Mat. Sci. Eng. B 134 (2–3) (2006) 185–188.

CHAPTER 3

86. L. Mule’Stagno, S. Keltner, R. Yalamanchili, M. Kulkarni, J. Libbert, M. Banan, Crystal defect information obtained by multiple wafer recleaning, in: C.L. Claeys, P. Rai-Choudhury, M. Watanabe, P. Stallhofer, H.J. Dawson (Eds.) High Purity Silicon VI, The Electrochemical Society, USA, 2000, pp. 646–659. 87. S. Iida, Y. Aoki, Y. Sugita, T. Abe, H. Kawata, Grown-in microdefects in a slowly grown Czochralski silicon crystal observed by synchrotron radiation topography, Jpn. J. Appl. Phys. 39 (Pt 1, No.11) (2000) 6130–6135. 88. M. Hourai, G.P. Kelly, T. Tanaka, S. Umeno, S. Ogushi, Control of grown-in defects in Czochralski silicon crystals, in: T. Abe, W.M. Bullis, S. Kobayashi, W. Lin, P. Wagner (Eds.), Defects in Silicon III, Proceeding Volume 99-1, The Electrochemical Society, USA, 1999, pp. 372–385. 89. E. Dornberger, D. Temmler, W. von Ammon, Defects in silicon crystals and their impact on DRAM device characteristics, J. Electrochem. Soc. 149 (4) (2002) G226–G231.

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4

Chapter Four

Oxygen in Silicon Eero Haimi Department of Materials Science and Engineering, Helsinki University of Technology, Espoo, Finland

Single crystal (SC) silicon is one of the chemically purest technical materials used in large quantities. However, in spite of the high purity, there are still trace levels of other elements present in SC silicon. A common additional element, besides doping elements, is oxygen. Oxygen is incorporated to SC silicon during crystal growth. In this respect, there is a fundamental difference between Czochralski (CZ) and ﬂoat zone (FZ) crystals. Oxygen is accumulating to CZ silicon, because molten silicon dissolves oxygen from silica crucibles used in the growth process. If it is necessary, reduction of inherent oxygen concentration is possible by using magnetic CZ process. FZ silicon appears in lower oxygen concentra tion, since crucibles are not needed in FZ process. In FZ silicon only residual background concentration of oxygen, due to afﬁnity of oxygen for silicon, is observed. Oxygen and oxygen-related phenomena affect the properties of silicon in several ways. From a technologi cal viewpoint, oxygen in silicon can be either beneﬁcial or harmful depending on application. Oxygen can pro vide strengthening of wafer against plastic deformation during processing. Furthermore, oxygen precipitates can act as traps for fast diffusing metallic contaminants. Without this “gettering effect,” degradation of IC fabri cation yield may take place. On the other hand, oxygen precipitates and oxygen-related thermal donors (TDs) may act as defects and may impair processing or device performance when present at unintended locations. In the following, basic aspects of oxygen-related phenomena in silicon, such as oxygen in silicon solid solution, formation of small oxygen aggregates, oxygen precipitation, precipitation induced defects as well as behavior of oxygen in basic heat treatment procedures, have been overviewed.

4.1 Oxygen in Solid Solution

Oxygen in silicon solid solution is placed interstitially in the lattice. Equilibrium oxygen solubility has been studied with various techniques including IR spectroscopy, gas fusion analysis, secondary mass ion spectroscopy, charged particle activation analysis, and x-ray diffrac tion. Generally results scatter to some extent. A ﬁt of experimental results gathered from several groups is given by Mikkelsen [1] in the form of Eq. 4.1: ⎛�1.152eV ⎞⎟ eq Cox � 9�1022 exp ⎜⎜ [ atoms�cm3 ] (4.1)

⎜⎝ kT ⎟⎟⎠

Corresponding partial phase diagram of the Si–O

system, which shows boundary between the solid solu tion of silicon and the two phase region of silicon and silica, as a function temperature and oxygen concentra tion, is presented in Figure 4.1. The equilibrium solubility of oxygen in silicon at room temperature is smaller by several orders of magnitude than near the melting temperature. In practice, this means that as-grown CZ silicon is supersaturated with oxygen after cooling to room temperature due to slowness of out-diffusion in solid state. Typical oxy gen concentration of CZ silicon wafers range from below 5 � 1017 atoms/cm3 (low) to 5–10 � 1017 atoms/cm3 (medium) to above 1018 atoms/cm3 (high) (5 � 1016/cm3 � 1 ppma). Diffusivity of oxygen is dominated by the proc ess of jumping from one interstitial site to another. Experimental oxygen diffusion data in high temperature range (700–1200°C) is well established. Fitted results 59

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Silicon as MEMS Material

n � number of moles k � Boltzmann constant T � absolute temperature

Figure 4.1 ● Partial phase diagram of the Si–O system.

of diffusion constant [1] from several experiments can be expressed as: ⎛ 2.53eV ⎞⎟ 2 Dox � 0.13 exp ⎜⎜− ⎟[cm �s] ⎜⎝ kT ⎠⎟

(4.2)

It has been shown that oxygen diffusivity in high temperature range does not depend much on wafer orientation, annealing ambient, doping concentrations, nor pulling technique of crystal [2]. Low temperature diffusion data are not so well established. The phenom enon of enhanced oxygen diffusivity has been observed frequently and attributed to different causes such as thermal history, presence of metallic contamination and interactions with carbon or hydrogen (for details see Ref. [2]).

4.3 Precipitation of Oxygen

4.2 Formation of Small Oxygen Aggregates Supersaturation of oxygen in silicon solid solution creates a driving force for oxygen aggregation. It can be shown according to standard thermodynamics (for derivation, see for example Ref. [3]) that corresponding chemical driving force, ΔGchem, as a function of oxygen supersaturation can be approximated as: eq �Gchem � nRT In(Cox �Cox ),

where:

Cox � concentration of oxygen

Ceq ox � equilibrium concentration of oxygen

60

Conceptually, the ﬁrst stage of oxygen aggregation is the formation of O2 dimers from essentially isolated oxygen atoms by diffusion process. The possible role of such constituents as vacancies or carbon in the free energy of dimer formation is under scientiﬁc discussion. Aggregation of larger oxygen clusters than dimers is frequently considered to continue also with atom by atom process, although some evidence exists that oxygen dimers may also be mobile. Formation of small oxygen aggregates has gener ally raised interest in two contexts. In its usual inter stitial conﬁguration, oxygen is electrically inactive in silicon lattice. However, annealing of oxygen-rich silicon (1018 atoms/cm3) in the temperature range 350–500°C, several types of electrically active centers called thermal donors are formed. Furthermore, for mation of so-called new donors has been observed at higher temperatures. TDs have been attributed to the growth of small oxygen aggregates as already discussed in Section 3.6. Another area of interest regarding small oxygen aggregates is nucleation of precipitates. There has been discussion about relationship between pre cipitate nuclei and especially new donors. However, much of nucleation studies do not deal with such issues as detailed structure of the small oxygen aggregate or exact mechanism of their formation process. Instead, the emphasis is placed on the later observed precipita tion behavior. In the present text the same approach is followed. Nucleation is discussed further together with precipitation phenomena in the next chapter.

(4.3)

Precipitation of oxygen in silicon is a diffusion control led solid state phase transformation. In the transforma tion silicon oxide is formed. Formation of silicon oxide within silicon lattice requires that oxygen must diffuse together to form a small volume with correct composi tion, and the atoms must rearrange into correct crystal structure; i.e., both kinetic and thermodynamic require ments must be fulﬁlled. According to the mass balance, the reaction equation of oxygen precipitation in silicon reads: Si + xOi ↔ SiOx

(4.4)

Accurate chemical composition of oxygen precipitates in silicon has been under scientiﬁc debate. It is generally

Oxygen in Silicon

agreed that in SiOx the x is less than 2. The speciﬁc volume of the oxide is about twice as large as that of silicon. Therefore, the oxide precipitates are originally strongly strained. It has been proposed that stress accu mulation during precipitation is relieved at least par tially by ejection of self-interstitials. Consequently, if conservation of mass and volume in addition to point defect balance is included, the reaction Eq. 4.4 is modi ﬁed to [4]: aSi + bxOi ↔ bSiO x + (a − b)Sii

∑ Ai γi + V Δg el

ΔG

~4πγ r2

r r*

(4.5)

In principle, precipitation of a second phase takes place in three steps: a local ﬂuctuation in chemical potential (embryo), formation of a stable nucleus, and precipitate growth. Proposed theories of nucleation of silicon oxide involve both homogeneous and hetero geneous mechanisms and several propositions for the nuclei structure exist. Regardless of the exact char acteristics of the nucleus, some basic thermodynamic concepts can clarify the nucleation process. The driving force of the phase transformation is supersaturation of oxygen, whereas surface energy and strain energy are setting constraining contributions. Consequently, free energy change of the phase transformation ΔG can be expressed as: ΔG � −V Δg chem +

(4.6)

ΔG

~ –(4/3)π(Δgchem–Δgel)r3

Figure 4.2 ● Free energy changes expressed as a function of nucleus radii.

fact a similar type of equation would be obtained for any nucleus shape as a function of its size. Accordingly, the important concept of critical size of nucleus is introduced; if the precipitate is too small it is not thermodynamically stable. Figure 4.2 illustrates graphically free energy changes expressed in Eq. 4.7 as a function of nucleus radii. Critical radius r* of a thermodynamically stable nucleus is obtained by differentiation of Eq. 4.7, which yields: r* =

where: Δgchem � chemical free energy change per volume

2γ (�g chem − �g el )

(4.8)

By substituting Eq. 4.8 to Eq. 4.7, the activation energy barrier against nucleation ΔG* can be expressed as:

Δgel � elastic free energy change per volume γi � interface surface energy components V � volume of the precipitate

�G* =

Ai � interface surface area components In oxygen precipitation, an aggregate of oxygen atoms constituting a nucleus is formed ﬁrst. Once formed, the nuclei can either grow further and form oxide precipi tates or dissolve. This can be elaborated on by looking at the terms in Eq. 4.6 separately. Contributions of sur face energy and strain energy oppose the transforma tion. However, the separate contributions have different dependency on the nucleus size. If we ignore the varia tion of γ with interface orientation and assume that the nucleus is spherical with a radius r, Eq. 4.6 becomes 4 �G = − πr 3(�g chem − �g el ) + 4πr 2 γ 3

CHAPTER 4

(4.7)

This is a function of r that ﬁrst increases up to an acti vation energy barrier maximum and then decreases. In

16πγ3 3(�g chem − �g el )2

(4.9)

For critical radius of nuclei in the case of strain free nucleation (Δgel � 0), manipulation of Eqs 4.8 and 4.3 8.3 yields: r* =

2γv p eq ) kTIn(Cox / Cox

(4.10)

where: vp � the volume of precipitate per oxygen atom in it. Importantly, Eq. 4.10 shows that the critical size of nucleus increases with increasing temperature (because eq of temperature dependency of Cox ). More comprehensive theoretical treatment of critical radius of nucleus takes into consideration also stressrelieving mechanisms with corresponding crystal defect

61

Silicon as MEMS Material

PA R T I

interactions. Hence, an equation for r* can be written in the following form [5]:

r* = r*

2γ (1 + δ − ε) ε )3 XkT eq In (Cox / Cox )(C )(CIeq / CI )ni (C (CV / CVeq )nv − 6μ μ m δε vp

(

)

(4.11) where: CI � concentration of self-interstitials CIeq � equilibrium concentration of self-interstitials CV � concentration of vacancies Ceq V � equilibrium concentration of vacancies δ � linear misﬁt between Si and SiOx lattices (for SiO2 δ0.3) nI � number of self-interstitials emitted nV � number of vacancies absorbed X � ratio of oxygen and silicon in precipitate The compressive strain � in Eq. 4.11 is: ε=

δ 1 + 4μ m /3Kp

where:

μm � shear modulus of silicon

Kp � bulk compressibility of SiOx Interaction of oxygen with the other constituents in association with oxygen aggregation has been observed experimentally. At sufﬁciently high temperature, crystal line solids contain thermally generated vacancies and self interstitials, which are equilibrium point defects in crystals caused by conﬁguration entropy. In the case of dislocation free SC silicon, the material is usually supersaturated with point defects, because lack of other defects acting as point defect sinks. A fundamental observation regarding intrin sic point defects is that silicon crystals can be grown in either a vacancy or a self-interstitial mode and concentra tion of point defects in grown crystals depend on process ing conditions. In general, excess vacancies favor oxygen precipitation, whereas excess self-interstitials suppress it. It has been found that there is quite a sharp transition around 5 � 1011 cm�3 vacancy concentration between enhanced oxygen clustering and “normal” clustering [6]. In addition to crystal growth, changes in point defect con centration may take place during wafer processing. Wafer surfaces act as source or sink of point defects depending on ambient used. Nitration injects vacancies, whereas oxidation is introducing self-interstitials into silicon 62

[4, 7, 8]. Also oxygen precipitation is introducing self interstitials into silicon. Effect of point defects on oxygen precipitation depends also on possible point defect reac tions. (Interested readers may consult references [6, 9] and references therein for further details.) Graphite is used as heating elements in CZ crystal growth furnaces. In partial vacuum of the growth chamber, there may be sufﬁcient oxygen that reacts with unprotected graphite to form carbon monoxide, which dissolves in the silicon melt. Consequently, carbon can be incorporated in the silicon crystal during the growth process. When present at a concentration above 0.5ppm, carbon strongly enhances oxide precipitate nucleation [10]. In case of heavily boron doped silicon (p � -type), it is found that precipitation is enhanced as a function of increasing boron concentra tion [11–13]. Moreover, in heavily boron doped silicon, maximum nucleation rate of oxide precipitates is shifted toward high temperature regions [14]. According to classical, steady state nucleation theory, the nucleation rate J is given by the Volmer-Weber Becker-Döring nucleation rate equation (for derivation, see for example Ref. [15]) J = ZC * ω

(4.12)

where C* is the concentration of critical-sized nuclei and ω is the frequency of attachment of oxygen atoms to the nucleus. The term Z is the Zeldovich factor, which is a correction factor corresponding to the fraction of atoms, which are included in the precipitate nuclei immediately after nucleation. In practice the Zeldovich factor is a ﬁt ting parameter usually in the order of but smaller than 1. The concentration of critical-sized nuclei C* is given by a Boltzmann type of equation: ⎛ �G* ⎞⎟ ⎟⎟ C* = Cx exp⎜⎜⎜ ⎜⎝ kT ⎟⎠

(4.13)

The term Cx is concentration of nucleation sites. In the homogeneous nucleation models Cx is set equal to the interstitial oxygen concentration or more properly interstitial lattice sites in silicon. Heterogeneous nuclea tion models assume that Cx is equal to the concentra tion of some other constituents such as pre-existing oxygen aggregates, vacancies or carbon. The attachment factor ω is given by ω = 4π(r*)2 Cox

Dox da

(4.14)

where da is the interatomic jumping distance. The total number of precipitates per unit volume is calculated from integrating the nucleation rate with the processing time. Basically, nucleation rate of oxide precipitates in iso thermal heat treatment depends on oxygen concentration

Oxygen in Silicon

in solid solution and processing temperature. Furthermore, heterogeneous factors may have an effect on nucleation rate depending on experimental conditions. Nucleation rate increases with increasing oxygen concentration in solid solution. When experimental nucleation rate is plot ted as a function of temperature, a maximum at a certain temperature is observed. This can be explained as follows. When the temperature is very high, the oxygen super saturation is small or non-existing, leading to small driv ing force and nucleation rate. On the other hand, when temperature is very low, diffusion becomes slow, leading to also vanishing nucleation rates. Nucleation rate is not necessary constant in time. Nucleation rates slow down and number per volume of precipitates reach a saturation value in very long anneals. This has been explained with overlapping of diffusion zones surrounding each nucleus during long anneals. As a different type of time dependency, an incubation time in nucleation rate is observed after processes, where sudden cooling and concomitant sudden supersaturation states are developed. In practice, silicon has already pre-existing nuclei before many processing situations. Due to possibility of nuclei dissolution, number per volume of oxygen pre cipitates after non-isothermal heat-treatment programs may differ from pre-existing nuclei density. As discussed earlier, the size of the nuclei should be larger than the critical size in order to be stable. Furthermore, the criti cal nucleus size increases as a function of rising tem perature. Consequently, at high enough heating rate, the growth rate of a nucleus is slower than the increase of the critical size of nucleus resulting in dissolution of nuclei. In Figure 4.3 selection of nuclei capable of growth using two different two-step heat treatment temperatures has been illustrated [16]. First, there is a pre-existing nucleus size distribution. A subsequent anneal selects nuclei larger than the critical size for further growth. An alternative low temperature anneal would select larger proportion of nuclei than respective high temperature anneal. According to experimental observations, total

Precipitate density

Invisible

As-grown

Visible

Annealing

After annealing

Low temp. High temp. rc 10

rc1

100

N(F>rc) N(r>rc1) 1000

10000

Precipitate size (Å)

Figure 4.3 ● Selection of nuclei capable of growing [16]. Source:

Figure reproduced by permission of the Electrochemical Society.

CHAPTER 4

dissolution of pre-existing nuclei causes long time lag in subsequent oxygen precipitation [17, 18]. Precipitates are characterized by their size, shape, crystal structure and number per unit volume. In princi ple, the size and the number per unit volume are inter related at their upper boundary values, because there is a ﬁnite number of oxygen atoms capable of forming precipitates. In practice, the typical number per volume of oxygen precipitates after device processing is between 103 and 1010 cm�3. Diffusion calculations show that for these densities the diffusion zone of each precipitate does not have much overlap. As a consequence, the size of the oxygen precipitates is nearly independent of the number per unit volume of precipitates (Bergholz, 1994). Shape of a precipitate depends on their formation tem perature as well as oxygen supersaturation and doping level of the silicon. Three temperature ranges have been related to the three typical precipitate shapes, i.e., the needle, the platelet, and the polyhedron in lightly doped silicon. At low temperatures (~400–650°C) precipitates grow as needles. In this temperature range the strainenergy contribution to the precipitate total free energy dominates, since the stress-relieving processes (which become important at higher temperatures) play a minor role. At intermediate temperatures (~650–950°C) platelet-shaped precipitates are typical (although they can be formed also during short high-temperature annealing). These precipitates are square formed plate lets at {100} habit planes, with edges along the �110� directions. At high temperatures (above 950°C) strain is completely released and the precipitates take the shape with minimum surface energy. Due to the anisotropy of interface energy, the preferential shape is octahedron with eight equivalent (111) faces (surface energy of silicon is minimum in the (111) planes) instead of the sphere. In the case of heavily doped silicon, precipitate morphology differs from lightly doped silicon. Plateletshaped precipitates are observed in addition to (100)— also in (110)—and (111)-type habit planes [19] and rod-shape precipitates are not formed [11]. According to Fujimori [20], dependence of precipitate morphol ogy on oxygen supersaturation comes from kinetic con siderations. Growth rate of a precipitate increases with increasing supersaturation of oxygen and kinetics of stress-relaxation processes may become a limiting factor. Consequently, for higher oxygen supersaturation, there is a transition zone in boundary temperature between platelet and polyhedron precipitate formation. The crys tal structures of precipitates formed at higher than about 650°C temperatures are amorphous. This is correlated to precipitate morphology. Only needle-type precipitates are observed to be crystalline. At high enough temperatures precipitates do not nucleate in practice. Only precipitate growth becomes signiﬁcant. The kinetics of the precipitation of oxygen 63

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Silicon as MEMS Material

in thermal processing can be studied experimentally for instance by following the diminishing infrared absorption at 1107cm�1 band, characteristic of interstitially dissolved oxygen in silicon. Furthermore, transmission electron microscopy can be utilized in determining size of pre cipitates as a function of heat treatment time. It has been conﬁrmed by many observations, that the time depend ence of experimental results are generally in good agree ment with the theory of Ham [21] for diffusion limited precipitation at temperatures above 650°C [22]. Applying the theory of Ham, Sueoka et al. [23] gives the time (t) dependence of the dimensions L (edge) and d (thickness) of platelet precipitates and l (edge size) of octahedral pre cipitates. These types of model are called deterministic growth models: ⎛ C − Cint ⎞⎟0.5 ⎜ ox ⎟ L = Λ(Dox t)0.5 with Λ = 2 2 ⎜⎜ ox ⎟ ⎜⎝ γπCp ⎠⎟⎟ (4.15a)

0.5

d = δ(Dox t)

⎛ γ(C − Cint )⎞⎟0.5 ⎜ ox ox ⎟ ⎜ with δ = 4 ⎜ ⎟⎟ ⎜⎝ πCp ⎠⎟ (4.15b)

⎛ C − Cint ⎞⎟0.5 ⎜ ox ⎟ l = λ(Dox t)0.5 with λ = (8π)1 / 3 ⎜⎜ ox ⎟⎟ ⎜⎝ Cp ⎟⎠ (4.15c) In order to describe the entire precipitation process from nucleation to precipitate growth, a steady-state nucleation model and a deterministic growth model can be combined at the critical size of the nucleus. This allows simultaneous calculation of oxygen loss, number of precipitates per unit volume and the average precipi tate radius during annealings. Furthermore, precipitate size-distribution can also be evaluated using coarsening model together with an iterative numerical calculation scheme [24]. However, for all nucleus radii smaller than the critical size, an equilibrium size-distribution has to be assumed. This assumption is incorrect when rapid temperature ramping takes place. The most realistic simulation strategy describes growth and dissolution of all nuclei and precipitate sizes statistically. This can be done applying Monte Carlo techniques. The drawback of the Monte Carlo approach is excessive computational load. A simulation model using Fokker-Plank equations can overcome much of the computational problems. Similarly to the Monte Carlo method, growth and dis solution of nuclei and precipitates are described statis tically. However, instead of using random numbers for deciding on growth and dissolution, this is described 64

by a set of chemical rate equations. Furthermore, all chemical rate equations are approximated with a single stochastic partial differential equation applying a math ematical transformation. The resulting equation is called a Fokker-Plank equation. For details of Fokker-Planck modeling see, for example, Ref. [25].

4.4 Precipitate-Induced Defects As discussed earlier, oxide precipitates in silicon are originally strongly strained, because the volume expansion connected with oxide precipitate forma tion. Stress relaxation may take place by ejection of self-interstitials. However, ejected self-interstitials are not necessarily arranged originally in minimum energy conﬁguration and stress relaxation is not necessarily complete. Consequently, precipitate-induced defect formation may take place. The ideal case of stress (and strain) ﬁelds associated to a precipitate formation without any stress-relaxation process can be calculated using standard theory of elas ticity. General calculations of this type show the effect of precipitate shape on elastic energy: lowest elastic energy is associated to platelet morphology, next low est is associated to needle morphology, and the highest elastic energy is associated to polyhedron morphology. An experimental technique to study actual local lat tice strain around oxygen precipitates is convergent beam electron diffraction (CBED) mode of transmis sion electron microscopy. The local lattice strain can be measured from higher order Laue zone (HOLZ) pat terns. Several of this type of study has been published [26, 27]. As a result of strain analysis from HOLZ pat terns, acquired around a platelet type of precipitate, the strain along the normal direction to the precipitate was found to be compressive. Importantly, however, the strain along the parallel direction to the precipitate was found to be tensile. Based on FEM simulation, the strain formation was considered to take place during cooling of the material [28]. In the case of polyhedron precipitates, contradictory results have been published. Otherwise similar behavior to that in the case of platelettype precipitate, but with lower strain levels, has been reported [28]. On the other hand, results obtained with high-resolution electron microscope indicating that polyhedron precipitates exist practically without strain have been reported [29]. An argument in this dis cussion is that amorphous silica cannot support shear stresses above a glass transition temperature at around 950°C [30]. Apparently, uncertainty concerning stress and strain ﬁelds associated to precipitates comes to some extent from the fact that the stress formation is not an equilibrium process, which would depend only on shape and size of a precipitate. Precipitation process

Oxygen in Silicon

involves the inward diffusion of oxygen, the generation of stress at the interface and the outward diffusion of self-interstitials. Consequently, partial stress relaxation takes place already simultaneously with the stress for mation and it is dependent on the process sequence. Self-interstitials formed in the stress-relaxation proc ess associated with oxygen precipitation are likely to be locally supersaturated. The system can further lower its free energy by allowing them to agglomerate. Stacking fault formation is such an agglomeration process. In general stacking faults can be classiﬁed as surface stack ing faults and bulk stacking faults. In the case of sur face stacking faults, oxidation induced stacking faults (OISF) are of interest in the present context. They are usually located as a circular band in the wafer originated from vacancy reactions during particular crystal growth processes. Essential factors in formation of OISF are self-interstitials emitted to silicon due to surface oxi dation [31, 32]. Stacking faults in silicon are always associated with precipitates at their centers providing that mechanical damage and heavy metal contamina tion are excluded as cause of the defects. Transmission electron microscopy observations of several workers conﬁrm this [33, 34]. However, only 0.1 to 1% of the precipitates present in wafers nucleate stacking faults. In detailed TEM work of Sadamitsu et al. (1995) it was shown that OISF forms at platelet-type precipitates. Furthermore, it was observed that one of the �110� edges of a platelet precipitate always lies exactly on the (111) OISF plane. As discussed in the previous chap ter, platelet precipitates have expansive strain ﬁeld in the direction parallel to the precipitate plate. It is well established in other alloy systems that interstitial atoms, having a compressive strain ﬁeld around them, diffuse toward dilatation-ﬁeld gradient from the compression volume to the expansion volume. By analogy Sadamitsu et al. propose that silicon self-interstitials injected from Si/SiOx interface are attracted by the expansive strain ﬁeld around edge of platelet precipitates and subse quently they agglomerate as stacking faults at these locations. According to Marsden et al. [35] the size of a disk precipitate must be greater than a certain critical size in order to act as nucleation center. They deﬁned the minimum size to be 26 nm. Another work by them [36] implies that nucleation mechanisms of surface and bulk stacking faults are similar. Electron microscopy studies reveal that the stacking faults observed in sili con are of extrinsic type and they are bounded by Frank partial dislocation that has (a/3) � 111� type Burgers vector [29]. Infrared laser scattering tomography, scan ning infrared microscopy and x-ray tomography reveal directly the true shape of stacking faults, which have been observed to be predominantly circular [37, 38]. Near the specimen surface the shape may be also oval. A few hexagonal loops observed occasionally are appar

CHAPTER 4

ently multiple faults [37]. (The size of a stacking fault may extend to tens of micrometers in diameter.) The self-interstitials emission during precipitate growth does not necessarily relax all the stresses leaving residual stresses at precipitates. Furthermore, because the thermal expansion coefﬁcient of silicon is larger than that of silicon oxide, an additive compressive strain develops during cooling after precipitate growth [39]. As an additional means of strain relief, prismatic dislo cation loops can be punched-out into the silicon matrix. Normally, this is associated to sufﬁciently large pre cipitates. Punched-out dislocations have been observed frequently in TEM studies [29, 33, 40, 41]. They have been determined to be extrinsic types of dislocation loops that lie in the 110-planes orthogonal to the punch ing direction and have 1/2 � 110� type Burgers vector. Prismatic punching can occur only if the strain energy is large enough for loop nucleation to occur. Taylor et al. [39] established a quantitative criterion for such an event using the theory of Ashby and Johnson [42] for prismatic loop nucleation. Occasionally, also other types of precipitation induced defects, such as dislocation dipoles and irregular dislo cation loops, are observed [29]. However, systematic knowledge of their formation is sparse.

4.5 Behavior of Oxygen in Basic Heat Treatment Procedures Heat treatment procedures that silicon wafers expe rience during MEMS device manufacturing consists frequently of several successive anneals in different tem peratures and gas ambient. To some extent the effects of low-temperature steps, high temperature steps, and ramps between the steps can be treated separately. In the following, behavior of oxygen in basic heat treat ments is discussed. The ﬁrst heat treatment CZ silicon experiences is the in situ annealing after solidiﬁcation in crystal puller. This is usually called thermal history. Thermal history var ies along the crystal axis and radius. Variation along the crystal axis is a consequence of the fact that the seedend portion of a crystal spends more time in the puller furnace than the end portion. The thermal history of the crystal depends also on the shape of the ingot bot tom, the pulling rate, the puller type, the hot-zone con ﬁguration, and the time that the ingot remains inside the puller in the course of growth process. Variations in thermal history affect oxygen precipitation and the for mation of microdefects. It should be emphasized, that the thermal history effect is always present [2]. Various heat treatment procedures have been developed to erase or homogenize the effects of the thermal history. In fact, 65

Silicon as MEMS Material

it has been emphasized [43] that reproducible results in precipitation treatments cannot be obtained without proper homogenization treatment of the samples. A single heat treatment is an elementary step of more complicated thermal processes in silicon device manufac turing. General precipitation behavior in a single treatment can be characterized as follows. When the temperature of a heat treatment step is decreased, the supersaturation of oxygen and driving force for precipitation rises, but the dif fusion coefﬁcient falls rapidly. Consequently, in the pres ence of adequate numbers of nucleation sites, one predicts a small number of large precipitates from a high-tempera ture anneal, and a large number of small precipitates from a low temperature anneal [44]. A common two step heat treatment combination is so called Lo–Hi treatment, where the low-temperature step (600–800°C) leads to the generation or selection of the nucleation centers and the high-temperature one (�1000°C) to precipitate growth. Generally, precipitate density increases with low-temperature anneal time and precipitate size increases with high-temperature anneal time [44]. Furthermore, ramping speed from the low temperature to the high temperature will select the nuclei capable of growing. Complexity of manufacturing of silicon devices has led to the work for ﬁnding standard heat treatments that represent more complicated, multi-step ones, in order to evaluate precipitation behavior of silicon material (Chiou, 1985). An outcome of such a work is the standard ASTM F 1239. Basically, the standard heat treatment is a two step Lo–Hi anneal. As a reference, a single Hi anneal is also performed. The temperatures of Lo and Hi steps are 750 and 1050°C, respectively. Further process details have been explained in the ASTM F 1239 standard. In the standard procedure, precipitation is monitored by measuring the changes in interstitial oxygen concentration with an infrared absorption spectrophotometer. Some general conclusions can be drawn from the observed pre cipitation behavior. Because of the dependency of driving force of precipitation (Eq. 4.3) on oxygen supersaturation, the results of any precipitation test show three character istic regions as a function of initial oxygen concentration of the tested wafers. Namely, zero precipitation, partial precipitation and full precipitation. In Figure 4.4 the gen eral precipitation behavior has been plotted as a function of initial oxygen concentration. Two observations are of signiﬁcance. The boundary value of initial oxygen concen tration when zero precipitation is observed is higher than the equilibrium value from the phase diagram. This is because driving force is needed for precipitation to occur. Secondly, the slope of the curve is relatively steep in the partial precipitation region. The consequence of this type of behavior is that in the partial precipitation region, the high slope of precipitation function transforms the variation of initial oxygen concentration into variation in 66

Precipitated oxygen (Δ[Oi])

PA R T I

[oi]c V,C,N,H,B Isi,P,As,Sb Max. ΔΔ[Oi] Zero precipitation

0

Partial

Min. precipitation

100% precipitation

Initial oxygen concentration ([Oi]o)

Figure 4.4 ● Generic curve showing relation between oxygen precipitation as a function of initial oxygen concentration [47].

precipitation. Comparison of the Hi and the Lo–Hi treat ments indicate the contribution of thermal history of the wafers on precipitation, because the single Hi treatment does not obviously involve a nucleation step at all [45]. In arbitrary Lo–Hi treatments, the position of zero precipitation, partial precipitation and full precipitation region in regard to initial oxygen concentration depend primarily on the heat treatment temperature and time. The additional factors include thermal history, doping density and concentration of point defects and impuri ties. Lower pre-anneal temperature and/or longer preanneal time will push the partial precipitation region toward lower oxygen concentrations as will a higher concentration of vacancies, boron, carbon and nitrogen. In Figure 4.5 micrographs of cross-sectional samples of 110 silicon surfaces are shown after ASTM F 1239 heat treatments as examples. Silicon samples were of p-type with two oxygen concentration levels. The concentration levels were 10 ppma and 15 ppma. Samples were taken from similar parts of the crystal to ensure uniform thermal history. After heat treatments, samples were etched with Wright etchant [46] in order to relieve microdefects. Optical micrographs were taken using differential interfer ence contrast (Nomarski contrast). Precipitates are seen as dots and stacking faults as oriented lines in the micro graphs. The micrographs of the samples with 10 ppma oxygen concentration levels are in the upper row and the micrographs of the samples with 15 ppma oxygen concen tration level are in the lower row, respectively. The micro graphs of the samples that have been heat treated only at 1050°C are in the left column. In the right column are the micrographs of the samples that have been heat treated at 750°C and 1050°C. Full precipitation is seen only in the sample with 15 ppma oxygen concentration level that has been heat treated at 750°C and 1050°C. Micrographs show clearly the effects of Lo–Hi heat treatment and oxygen concentration on oxygen precipitation. If ﬁrst high-temperature heat treatment is long enough, a number

Oxygen in Silicon

100 μm

Cox = 10 ppma, T = 1050 °C

CHAPTER 4

100 μm

Cox= 10 ppma, T1 = 750 and T2 = 1050 °C

100 μm

Cox = 15 ppma, T=1050 °C

100 μm

Cox = 15 ppma, T1 = 750 and T2 = 1050 °C

Figure 4.5 ● Micrographs of silicon surfaces ASTM F 1239 heat treatments.

Figure 4.6 ● Example of a silicon wafer with stacking faults.

Figure 4.7 ● Example of a silicon wafer with DZ. Source: Figure reproduced with permission of Okmetic Oyj.

of large precipitates grow beyond critical size and initiate stacking faults. An example is presented in Figure 4.6. In device processing, annealing programs are occa sionally carried out to “engineer” oxygen precipitation. Probably the most popular of these treatments is a Hi– Lo–Hi annealing, which is otherwise similar to Lo–Hi annealing, but it comprises oxygen out diffusion annealing at comparatively high temperature (�1100°C) as a ﬁrst

step. The result of this treatment is a very low precipitate density near the wafer surface, the denuded zone (DZ), and a high defect density in the bulk, as consequence of oxygen depletion at the top 20–100 μm under the wafer surface. In Figure 4.7 a cross-sectional example of such a wafer after Wright etching is presented. DZ formation in this way is a direct consequence of earlier discussed high slope of precipitation function (Figure 4.4). DZ width 67

PA R T I

Silicon as MEMS Material

(DZW) is inﬂuenced by time and temperature of the out diffusion anneal in the case of similar silicon wafers. For constant temperature anneal, experimental results of DZW can be expressed with a following simple equation (for more details see Ref. [2] and references therein): DZW = A + B × t1 / 2

(4.16)

where A and B are experimental constants and t is annealing time. Another way to “engineer” oxygen precipitation properties in silicon is rapid thermal processing (RTP). DZ can be created by installing a proper vacancy con centration proﬁle which rises from the wafer surface into the bulk [6].

References 1. J.C. Mikkelsen, The diffusivity and

solubility of oxygen in silicon, Mat.

Res. Soc. Proc. 59 (1986) 19–30.

2. A. Borghesi, B. Pivac, A. Sassella, A. Stella, Oxygen precipitation in silicon, J. Appl. Phys. 77 (1995) 4169–4244. 3. R.D. Doherty, R.W. Cahn, P. Haasen (Eds.), Physical metallurgy, third ed., Elsevier, Netherlands, 1983, pp. 933–1030. 4. S.M. Hu, Effects of ambients on oxygen precipitation in silicon, Appl. Phys. Lett. 36 (7) (1980) 561–564. 5. J. Vanhellemont, C. Clayes, A theoretical study of the critical radius of precipitates and its application to silicon oxide in silicon, J. Appl. Phys. 62 (9) (1987) 3960–3967. 6. R. Falster, V.V. Voronkov, F. Quast, On the properties of intrinsic point defects in silicon: a perspective from crystal growth and wafer processing, Phys. Stat. Sol. B 222 (2000) 219–244. 7. S.M. Hu, Formation of stacking faults and enhanced diffusion in the oxidation of silicon, J. Appl. Phys. 45 (4) (1974) 1567–1573. 8. W. Bergholz, D. Gilles, Impact of

research on defects in silicon on the

microelectronic industry, Phys. Stat.

Sol. B 222 (2000) 5–23.

9. V.V. Voronkov, R. Falster, Grownin microdefects, residual vacancies and oxygen precipitation bands in Czochralski silicon, J. Cryst. Growth 204 (1999) 462–474. 10. T.Y. Tan, W.J. TaylorF. Shimura (Ed.), Oxygen in silicon, Academic Press, USA, 1994, pp. 353–390. 11. D.A.P. Bulla, W.E. Castro Jr., V. Stojanoff, F.A. Ponce, S. Hahn, W.A. Tiller, Effects of boron concentration upon oxygen precipitation in Cz silicon, J. Cryst. Growth 85 (1987) 91–96. 12. S. Hahn, F.A. Ponce, W.A. Tiller, V. Stojanoff, D.A.P. Bulla, W.E. Castro Jr., Effects of heavy boron doping upon oxygen precipitation in

68

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

Czochralski silicon, J. Appl. Phys. 64 (9) (1988) 4454–4465. K. Sueoka, M. Akatsuka, M. Yonemura, T. Ono, E. Asayama, H. Katahama, Effect of heavy boron doping on oxygen precipitation in Czochralski Silicon Substrates of Epitaxial Wafers, J. Electrochem. Soc. 147 (2) (2000) 756–762. W. Wijranakula, Oxygen precipitation and defects in heavily doped Czochralski silicon, J. Appl. Phys. 72 (7) (1992) 2713–2723. J.W. Cristian, The theory of transformations in metals and alloys, ﬁrst ed., Pergamon Press, 1965 973 p. N. Inoue, J. Osaka, K. Wada, Oxide micro-precipitates in as-grown CZ silicon, J. Electrochem. Soc. 129 (12) (1982) 2780–2788. T.Y. Tan, C.Y. Kung, Oxygen precipitation retardation and recovery phenomena in Czochralski silicon: experimental observation, nuclei dissolution model, and relevancy with nucleation issues, J. Appl. Phys. 59 (3) (1986) 917–931. N. Inoue, K. Watanabe, K. Wada, J. Osaka, Time-lag in nucleation of oxide precipitates in silicon due to high temperature preannealing, J. Cryst. Growth 84 (1987) 21–35. W. Wijranakula, Morphology of oxide precipitates in Czochralski silicon degenerately doped with boron, J. Appl. Phys. 72 (9) (1992) 4026–4030. H. Fujimori, Dependence on morphology of oxygen precipitates upon oxygen supersaturation in Czochralski silicon crystals, J. Electrochem. Soc. 144 (9) (1997) 3180–3184. F.S. Ham, Theory of diffusion limited precipitation, J. Phys. Chem. Solids 6 (1958) 335. J. Vanhellemont, Diffusion limited oxygen precipitation in silicon: precipitate growth kinetics and phase

formation, J. Appl. Phys. 78 (6) (1995) 4297–4299. 23. K. Sueoka, N. Ikeda, T. Yamamoto, S. Kobayashi, Morphology and growth process of thermally induced oxide precipitates in Czochralski silicon, J. Appl. Phys. 74 (9) (1993) 5437–5444. 24. S. Isomae, Computer-aided simulation for oxygen precipitation in silicon, J. Appl. Phys. 70 (8) (1991)

4217–4223.

25. M. Schrems, T. Brabec, M. Budil, H. Pötzl, E. Guerrero, D. Huber, P. Pongratz, Simulation of oxygen precipitation in Czochralski grown silicon, Mat. Sci. Eng. B 4 (1989) 393–399. 26. T. Okuyama, M. Nakayama, S. Sadamitsu, J. Nakashima, Y. Tomokiyo, Analysis of local lattice strains around plate-like oxygen precipitates in Czochralski-silicon wafers by convergent-beam electron diffraction, Jpn. J. Appl. Phys, 36 (6A) (1997) 3359–3365. 27. M. Yonemura, K. Sueoka, K. Kamei, Analysis of local lattice strain around oxygen precipitates in silicon crystals using CBED technique, Appl. Surf. Sci. 130–132 (1998) 208–213. 28. M. Yonemura, K. Sueoka, K. Kamei, Analysis of local lattice strain around oxygen precipitates in Czochralski grown silicon wafers using convergent beam electron diffraction, Jpn. J. Appl. Phys. 38 (6A) (1999) 3440–3447. 29. H. Bender, Investigation of the oxygen-related lattice defects in Czochralski silicon by means of electron microscopy, Phys. Stat. Sol. A 86 (1984) 2245–2261. 30. W.A. Tiller, S. Hahn, F.A. Ponce, Thermodynamic and kinetic considerations on the equilibrium shape for thermally induced microdefects in Czochralski silicon, J. Appl. Phys. 59 (9) (1986) 3255–3266. 31. R.B. Fair, Oxidation, impurity diffusion, and defect growth in

Oxygen in Silicon

32.

33.

34.

35.

36.

silicon—an overview, J. Electrochem. Soc. 128 (6) (1981) 1360–1368. V.V. Voronkov, R. Falster, Vacancy-type microdefect formation in Czochralski silicon, J. Cryst. Growth, 194 (1998) 76–88. D.M. Maher, A. Staudinger, J.R. Patel, Characterization of structural defects in annealed silicon containing oxygen, J. Appl. Phys. 47 (9) (1976) 3813– 3825. C. Clayes, H. Bender, G. Declerck, J. van Landuyt, R. van Overstraeten, S. Amelinckx, Impact of high temperature processing on bulk defects in Czochralski silicon, Physica 116B (1983) 148–161. K. Marsden, T. Kanda, M. Okui, M. Hourai, T. Shigematsu, Determination of the criteria for nucleation of ring-OSF from small as-grown oxygen precipitates in CZ-Si crystals, Mat. Sci. Eng. B 36 (1996) 16–21. K. Marsden, S. Sadamitsu, T. Yamamoto, T. Shigematsu, Generation of oxidation-induced stacking faults in Czochralski-grown silicon crystals

37.

38.

39.

40.

41.

exhibiting a ring-like distributed fault region, Jpn. J. Appl. Phys. 34 (6A) (1995) 2974–2980. J.R. Patel, A. Authier, X-ray topography of defects produced after heat treatment of dislocation-free silicon containing oxygen, J. Appl. Phys. 46 (1) (1975) 118–125. G. Kissinger, J. Vanhellemont, C. Clayes, H. Richter, Observation of stacking faults and prismatic punching systems in silicon by light scattering tomography, J. Cryst. Growth 158 (1996) 191–196. W.J. Taylor, U. Gösele, T.Y. Tan, SiO2 precipitate strain relief in Czochralski Si: self-interstitial emission versus prismatic dislocation loop punching, J. Appl. Phys. 72 (6) (1992) 2192–2196. T.Y. Tan, W.K. Tice, Oxygen precipitation and generation of dislocations in silicon, Phil. Mag. 34 (4) (1976) 615–631. K. Tempelhoff, F. Spiegelberg, R. Gleichmann, D. Wruck, Precipitation of oxygen in dislocation-free silicon,

CHAPTER 4

Phys. Stat. Sol. 56 (1979)

213–223.

42. M.F. Ashby, L. Johnson, On the generation of dislocation at misﬁtting particle in a ductile matrix, Phil. Mag. 20 (1969) 1009–1022. 43. R. Falster, M. Cornara, D. Gambaro, M. Olmo, M. Pagani, Effect of high temperature pre-anneal on oxygen precipitates nucleation kinetics in Si, Solid State Phen. 57–58 (1997) 123–128. 44. J.G. Wilkes, The precipitation of oxygen in silicon, J. Cryst. Growth 65 (1983) 214–230. 45. H.-D. Chiou, Oxygen precipitation behavior and control in silicon crystals, Solid State Tech. 30 (3) (1987) 77–81. 46. M. Wright-Jenkins, A new preferential etch for defects in silicon crystals, J. Electrochem. Soc. 124 (5) (1977) 757. 47. F. Shimura (Ed.), Oxygen in Silicon, Semiconductors and Semimetals, vol. 42, Academic Press, USA, 1994. 679 p

Further reading A. Borghesi, B. Pivac, A. Sassella, A. Stella, Oxygen precipitation in silicon, J. Appl. Phys. 77 (1995) 4169–4244. S. Sadamitsu, M. Okui, K. Sueoka, K. Marsden, T. Shigematsu, Jpn. J.

Appl. Phys. 34 (SB) (1995) L597–L599. F. Shimura (Ed.), Oxygen in Silicon, Semiconductors and Semimetals, vol. 42, Academic Press, USA, 1994. 679 p

M.D. Chiou, L.W. Shive, in W.M. Bulls, S. Broydo, VLSI Technology, USA, ECS, (1985) pp. 429–435.

69

5

Chapter Five

Silicon Wafers: Preparation and Properties Markku Tilli Okmetic Oyj, Vantaa, Finland

MEMS manufacturing sets, in many respects, special requirements for silicon wafers, and in some processes— for example, those based on bulk micromachining and deep anisotropic wet etching—standard wafers intended for normal semiconductor use may show poor results. Standard polished silicon wafers used in semiconductor manufacturing are extensively standardized by SEMI (Semiconductor Equipment and Materials International) [1, 2]. These standards stipulate most of the important parameters, like dimensions, dimensional tolerances, key measurement techniques, etc. Standards, however, in many situations give only guidelines, and especially when specifying wafers for MEMS use, care has to be taken in actual specifications. Values needed for individual parameters commonly are much tighter than what the standards suggest. This conclusion is obvious when comparing the values found in the newest version of the commonly used roadmap for IC’s, ITRS (International Technology Roadmap for Semiconductors) to values of SEMI standards [3]. MEMS processes are traditionally divided into surface micromachining and bulk micromachining. Unit processes in surface micromachining are close to standard semiconductor processes, and thus wafer specifications usually follow closely the SEMI standards. Silicon wafers used in bulk micromachining applications, however, deviate from features listed in SEMI standards. This is because bulk micromachining processes and techniques differ very much from each other, setting process-specific specification requirements, and some key characteristics of the final MEMS device may be directly inherited from wafer properties and specifications. MEMS devices are often sealed from the environment with cap silicon wafers. These wafers used for

capping may require parameters uncommon to standard IC-wafers, too. A few examples of these differences are wafer thickness, thickness tolerances, flatness, and the common requirement of double-sided polishing of wafers (Table 5.1). There are also some “hidden” features, which are not commonly specified or are difficult to specify—such as the bulk material behavior in different thermal treatments. Similarly, more advanced wafer types for MEMS, epi wafers, and SOI wafers are covered by the SEMI standards only partly. Independent of the final use of the silicon wafer, be it for surface micromachining, bulk micromachining, or

Table 5.1 MEMS/IC wafer key parameter comparison

Parameter

MEMS wafer

IC wafer

Wafer diameter (mm) (mainstream)

150, 200

200, 300

Wafer type

Technology dependent: SSP, DSP, EPI, ThickSOI

SSP, some EPI, ThinSOI

Wafer thickness

Technology dependent: Non standard (common) or SEMI standard

SEMI standard

Wafer resistivity

mΩcm to over kΩcm

Typically up to 30 Ωcm

Bulk properties

Tailored, BMDs often minimized

Gettering important, BMD controlled

71

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Silicon as MEMS Material

capping of the device, main steps of the wafer manufacturing are common. Wafers are cut from the grown ingot, shaped, polished, and cleaned to be ready for further processing into Epi wafers or SOI-wafers, or for device manufacturing. Unit process steps, like polishing, may differ in detail, depending on the wafer thickness or requirement of the double-sided polishing.

5.1 Silicon Wafer Manufacturing Process Silicon crystals, or ingots in the terminology commonly in use, grown with either CZ (Czochralski) or FZ (float zone) technique are typically up to 2 m in length, and they have a small over-diameter to eliminate yield loss in final wafers from diameter fluctuation and small deviations from round shape. Silicon crystal growth and properties are discussed in detail in Chapters 2 and 3. A typical crystal can yield up to more than 2000 wafers, depending on the final thickness of the wafer. The following concentrates on CZ silicon wafer manufacturing; this is because the vast majority of world wafers are from CZ crystals. FZ-wafer manufacturing is essentially similar; there are only some minor differences in the manufacturing. Figure 5.1 shows the generic flow of wafer manufacturing from ingot to polished, cleaned product. The following presentation of

silicon wafer manufacturing is only an overview to help the reader to understand the specifications of wafers without going into deeper details.

5.1.1 Ingot Cutting and Shaping As described in Chapters 2 and 3 of this book, CZ crystals have a resistivity distribution over the length of the crystal, the seed end of the crystal having higher resistivity, and the tail end low resistivity. This distribution depends on the dopant used, and also on the crystal growth process parameters if easily volatile dopants, arsenic or antimony, are used. For example, with phosphorus doping, the resistivity ratio between the neck part and the tail part can exceed 4:1 (see Figure 3.4). Some other characteristics, like oxygen content, can also vary over the crystal length. These, combined with practical manufacturability aspects, dictate that the crystal for further processing needs to be cut in suitable lengths. The limiting factor for length can be the customer resistivity window, the customer oxygen specification window, wafer order size, or optimum wafer lot size in the production. First step is to cut away the head part (shoulder) and tail part of the ingot, leaving the cylindrical part for further processing. At the same time test pieces from both ends of the ingot may be taken for laboratory measurements. For example, resistivity is measured, and thick

Packaging; to Ingot cropping

Wafer marking (laser)

Edge shaping

– Epi – SOI production – End customer

Final inspections Ingot cutting

Wafer clean

Lapping/grinding

– particles – surface defects

Orientation measurement

Wafer cutting (ID or wire cut)

Clean/etch

Final cleans

Cylindrical grinding

Flat/notch grinding

Polishing

Dimensional measurements

Fig 5.1 ● Generic silicon wafer manufacturing flow.

72

Silicon Wafers: Preparation and Properties

slug samples for dissolved oxygen and carbon concentration measurements are made. The operation of cutting tails and shoulders is called cropping. Cropped ingot is cut into pieces of suitable length. If some other requirement (specific customer window) does not limit the piece length, manufacturability optimization requires pieces of around 500 mm in length. The cut piece is usually one manufacturing lot in the subsequent process. First, the accurate orientation has to be measured to locate and mark normally (110) or (100) crystallographic plane or direction with (100) or (111) oriented ingots. When the ingot is in (110) orientation, some other planes or directions may be located. This step is important, since the orientation plane or notch is made according to this measurement. When the manufacturing process is carefully designed and stable, in routine basis, ⫾0.2° final accuracy of the orientation flat or notch is obtained, and ⫾0.1° accuracy is achievable (compared to ⫾0.5° to 1° accuracy required in standard wafer manufacturing, according to SEMI standards). A grown ingot is not perfectly round, as there is diameter fluctuation along the length of the ingot. Cylindrical grinding with diamond tools shapes the ingot round, and at the same time orientation flat or notch is ground. The finished piece of ingot is then ready for cutting to wafers.

CHAPTER 5

wires in a wire-cutting machine. Today, wafers (and from 200 mm up, extensively) are increasingly cut in wire-cutting machines because of productivity reasons. ID cutting, however, retains the flexibility of manufacturing smaller lots, but with higher cost. Table 5.2 shows a comparison of these two cutting methods.

5.1.2.1 ID Cutting ID cutting is done with a thin tensioned diamond blade having a hole in center, and on the inner edge of the hole there is a thin diamond coating. The ingot piece is fed against the blade, Figure 5.2. The blade does not travel ideally straight through the ingot, but it makes a small curve, and preferably the blade is curving towards the ingot. Damage layer of the surface is different between the ingot side and the wafer side surfaces.

Table 5.2 Wafer-cutting method comparison

5.1.2 Wafering The ingot to be sliced into wafers needs a support to hold cut wafers; therefore, a ceramic or graphite beam is glued on the piece of ingot. The ingot can be processed to wafers with two different methods. Either each wafer is cut, one by one, with an ID cutting machine, or the whole piece of ingot is cut with a web of tensioned

ID cutting

Wire cutting

Small lot manufacturing flexibility

⫹⫹

⫺⫺

Volume production, few specifications

⫺

⫹⫹

Thin wafer cutting

⫺

⫹⫹

Wafer warp/bow

⫺

⫹

Wafer orientation control

⫹

⫺

Silicon utilization

⫺⫺

⫹⫹

Productivity

⫺

⫹

Ingot Support beam

Diamond layer

Tensioned blade

Fig 5.2 ● In an ID cutting machine the ingot is supported by a graphite beam. Tensioned cutting blade has a hole, which is coated with diamond particles. Rotating blade is cutting the silicon at a speed of 50 mm/min or higher. Water with or without additives is used as a coolant.

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When wafers are measured after stress relief, they have quite a large taper and warp/bow, and values are larger if the wafer is thin. Typical bow and warp distributions can be seen in Figure 5.3. The wafer taper from cutting step can be removed in subsequent process steps, so it does not appear in the finished wafer. Warp/bow of the as-cut wafer is the sum of two components, permanent warp/bow originating from the irregular travel of the blade through the ingot during cutting and from the removable warp/bow coming from uneven residual damage on the wafer surface. Remaining process steps may change permanent bow and warp only a small amount unless there are thin films or deposited layers on the wafer, which cause asymmetric stress. ID-cutting offers good flexibility in small-lot production, since it makes a wafer at a time, being suitable also for processing short ingot pieces. Wafer orientation control is relatively easy to achieve. The ability to slice thinner wafers is not as good as when using wire cutting, however.

5.1.2.2 Wire Cutting Wire cutting (principle in Figure 5.4) allows simultaneous cutting of hundreds of wafers routinely (depending on the length of the ingot piece and cut wafer thickness), and larger machines are capable of processing well over 1000 wafers at a time when several pieces of ingot are cut at the same time. Figure 5.5 shows an example of taper and warp/bow distribution in volume production. Cutting is done by feeding abrasive, silicon carbide containing slurry, on the wire web. Recently, diamond-abrasive-coated wires have been available, too. In practice the cutting can be done with two wire feeding strategies. Oldest method is such, where wire is traveling from a reservoir spool to an intake spool some tens of meters, then the direction of wire movement is changed, and wire is rewound a little less than what was the forward feed; then again the direction of movement is changed, until the end of wire. In such a

(a)

way one section of the wire is used typically 3 times or more. The latest practice is to feed wire in one direction only, and when the wire is used, the direction of wire movement is reversed. Of this method there are two variations. The more common variant is where all wires run in the same direction, and the other variant is where wires are arranged in such a manner that every other wire runs in the other direction. The latter is claimed to have advantages, such as better taper control over the method where wires are going in the same direction only. Both methods allow wire to be used several times, too. Typical spool contains 200–400 km of wire. Wires are around 120–160 μm thick, and while abrasive is around 12 μm or less (median grain size), the kerf loss is less than 200 μm, compared to ID-cutting where kerf loss can be over 300 μm. Surface damage is also less than that obtained from ID-cutting, but surface waviness is higher. Advantage of wire-cutting in MEMS wafers is that it allows cutting of thin wafers with acceptable yield. Wire cutting is not efficient in producing small lots; in practice tens of thousands of wafers have to be cut with same specifications; otherwise, costs may be prohibitive. Möller’s review [4] of wire cutting gives a good oversight of the process. Independent of the cutting method, wafers are cleaned after cutting, and the supporting beam piece is removed. In addition to cleaning, a slight etch may be used to reduce surface damage to make the wafer mechanically stronger, reduce surface damage, and reduce the stress-related warp.

5.1.3 Wafer Marking Wafer marking is done with a laser, according to SEMI standard M12-0706 [5] or M13-0706, [6] with alphanumeric characters in a specified position near the primary flat or notch. These markings are readable even with the unaided eye, and marks consist of an array of

(b) 300

300

Histogram of BOW (ave)

250

200

Frequency

Frequency

250

Histogram of WARP (ave)

150 100 50

200 150 100 50

0

0 –18

–12

–6

0 BOW (ave)

6

12

18

10

20

30

40

50

60

70

WARP (ave)

Fig 5.3 ● (a) Typical bow distribution of wafers in μms, (b) typical warp distributions in μms of wafers after ID cutting (x-axis scale in μm).

74

Silicon Wafers: Preparation and Properties

CHAPTER 5

dots, Figure 5.6. The difference between the standards M12 and M13 is that Semi M13 standard gives more information; with 18 characters it defines identification number (8 character positions), wafer manufacturer code (2 positions), resistivity identification (4 positions), dopant (1 position), crystal orientation (1 position), and check characters (2 positions). Semi M12 marks wafers with 12 positions, and resistivity, dopant, and crystal orientation information is omitted. A custom marking with additional customer-specific information can be done, too, and the number of characters can exceed 18 positions. Two alternatives for marking are available: deep marking or shallow marking. Deep marking is done usually after wafer slicing and cleaning in order to keep maximum wafer identity information, or after-edge grinding, when, e.g., the wafer location information may be lost to some degree. The dots made by laser are Fig 5.4 ● Principle of wire cutting. (a)

(b)

Histogram of TTV (ave)

600

120 Frequency

500 Frequency

Histogram of Bow (ave)

140

400 300 200 100

100 80 60 40 20 0

0 8

12

16

20

24

28

–10

–5

0

5

10

15

20

Bow (ave)

TTV (ave) (c) Histogram of Warp (ave)

200

Frequency

150 100 50 0 0

8

16

24 32 40 Warp (ave)

48

56

Fig 5.5 ● (a) Typical taper, (b) bow, and (c) warp distributions of wafers after wire cutting (x-axis scale in μm).

Fig 5.6 ● An example of laser marking on a wafer. The code used is according to SEMI M13. (a) Deep laser mark done after slicing, (b) shallow mark done after polishing.

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deep enough to be visible after material removal in the next processing steps. Shallow marking is done after polishing, and in the mark the dots are small depressions with a small hump around the depressions, and it is just visible under suitable illumination. There are advantages and disadvantages with these methods. Deep marking is making deep depressions on the wafer surface. These depressions attract particles, resist removal from depressions is difficult or depression may initiate slip during high-temperature processing steps. Shallow marking may increase particulate levels in wafers, as it is done after polishing. Also, if the “hump” is too high, in wafer-bonding processes, shallow marked wafers may show small voids around the marking. Both marking types are widely used, and if front-side marking is critical, marking can be done on the wafer backside, too.

edges; rounded edge minimizes risk for slipping, too. Edge shaping operation makes the wafer perfectly round (off-cut wafers are oval shaped after slicing), the diameter is adjusted, and orientation flat(s) or notch is dimensioned or made. This operation is done normally with a profiled diamond wheel, and the edge profile is following the shape given by SEMI M1-0307 [2], Figure 5.7. The SEMI standard profile is often not suitable or ideal for MEMS applications. If the wafer will be thinned after processing, wafer edge may as a result be sharp and thus brittle using the standard profile; therefore, asymmetric edge profile can be used. Also, wafer bonding may set specific requirements for the wafer edge shape; typically, for bonding applications, more blunt profile is recommended in order to achieve a good bond up to wafer edge. Examples of some feasible profiles are shown in Figure 5.8. This standard is also specifying identification flats according to Figure 5.9 for wafers up to 150-mm diameter and a notch for wafers 200 mm and larger. However, it is common that 150-mm and smaller wafers deviate from the standard having only one flat, and the

5.1.4 Edge Grinding Silicon wafers after cutting have sharp edges, and they chip easily. Wafer edge is shaped to remove sharp, brittle

B

x

A D

Point

x (μm)

y (μm)

A

120

0

B

508

0

C

100

231

D

0

50

C C/L y

Fig 5.7 ● The wafer edge profile template according to SEMI M1-0707 standard. The actual shape of the wafer edge has to fall within the template.

Table 5.3 Wafer marking codes according to SEMI M13

Character location

Character style

Parameter

Code

Definition

[1–7]

Alpha/numeric

Identification #

A–Z and 0–9

Manufacturer defined

[8]

Numeric

Identification #

0–9

Manufacturer defined

[9–10]

Alpha

Supplier identification

A–Z

Semi assigned codes for each manufacturer

[11–14]

Numeric

Resistivity identification

0–9 and (period)

Resistivity (Ωcm) identification, no accuracy implication

[15]

Alpha

Dopant

B,F,A,S,–

B, P, As, or Sb, or no identification

[16]

Numeric

Crystal orientation

0,1,2,3,5,–

(100),(111),(110),(011), (511), or no identification

[17]

Alpha

Check character

A–H

[18]

Numeric

Check character

0–7

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Silicon Wafers: Preparation and Properties

flat length may be shorter than specified in the standard. This is to save the wafer surface area for devices. A further deviation from the standard may be that the 150 mm wafer has a notch instead of flat. Primarily, flat or notch is usually according to standard along {110} crystallographic plane; however, {100} plane is in some applications used, too.

5.1.5 Lapping/grinding Wafers have, after cutting, a large average wafer-to-wafer thickness variation, as well as large total thickness variation (TTV) within the wafer. TTV in as-cut wafers may exceed 5 μm, and average thickness variation from wafer to wafer can be over 20 μm. Wafer surface is nonuniform, and the residual damage may be uneven and different on different sides. Traditionally, dimensional variations are reduced and an even damage layer is made with dual-side lapping. This is an operation where wafers are rotating in carriers between two very flat, large cast-iron plates, and material removal is done with abrasive slurry containing alumina, optical emery, or silicon carbide powders. After total removal of 50–100 μm wafer, TTV will be well below 1 μm, and average thickness range within a production lot is a few μms. Surface roughness of lapped wafers depends on the lapping slurry, but it is generally less than 0.3 μm (Ra). Lapping can be replaced or supplemented with single-side grinding, Figure 5.11. Good introduction to silicon wafer grinding can be found in references [7–9]. Advances in this technique have been made in recent years, and grinding gives very good flatness and thickness control and low damage depth in finished wafers, and the surface roughness is typically ⬍0.1 μm (Ra). With fine grinding tools, surface roughness values of ⬍2 nm (Ra) and ⬍20 nm (Rz) are achievable. Surface finish, however,

depends on whether grinding is done in ductile or in brittle mode, and in general on the stiffness and on resonance frequencies of the grinding system. Ground wafers show very shallow grinding marks visible to unaided eye under suitable illumination, and this feature has generated resistance to wide acceptance in the history. However, in double-sided polishing these marks are easily removed. Novel grinding systems, simultaneous double-sided grinding, have been introduced, and the results are promising, especially in machining large-size wafers [10]. The ability of these machines to handle thin wafers typical to MEMS applications is still to be proven.

5.1.6 Chemical Etching Lapping or grinding leaves residual mechanical damage on the wafer surface, and wafer edges have residual damage from both lapping and edge-grinding operations. This damage is removed, and wafer is cleaned from impurities coming from mechanical operations in the etching step. The amount of silicon removed depends on the damage depth from previous operations. For etching there are two choices, acidic etch or alkaline etch. Acidic etch can produce smooth surfaces and it is suitable for all wafer orientations and dopants, including very heavily doped silicon; but as an exothermic process, process control is a challenge. Also, the decomposition of chemicals in the acidic mixture makes it challenging to master. Dopant and doping level in wafers affect the final results, too. Especially the brightness of the surface is affected by the dopant level. A typical classical acidic mixture consists of hydrofluoric acid, nitric acid, and acetic acid, based on the classical works of Robbins and Schwartz [11–13]. It has been reported that some additives, either oxidants or, for example, ammonia, can be used to improve the performance of the etchant [14].

P(111) (a)

(c)

N(100) ≤125 mm

N(100) ≥150 mm

N(111)

≥ 200 mm

(b)

P(100)

(d)

Fig 5.8 Examples of the wafer edge profiles. Profiles (a) and (b) are conventional. Profiles (c) and (d) are optimized for wafer thinning after processing. Profile (d) is also suitable for various bonding applications. ●

CHAPTER 5

Fig 5.9 ● Orientation flats for different wafer types and reference notch for 200 mm and larger wafers according to SEMI. Note that, commonly, wafer specifications differ from SEMI standards and are customer specific.

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Second choice is to use alkaline etching. This is done usually with hot potassium hydroxide solution. The process is stable, and thus easy to control. The disadvantage is that certain atomic planes, like (111), etches slowly, and therefore the etchant is practical to (100) wafers. Very heavy boron doping slows the etch speed down, and N-type dopants with very high dopant levels generate unsafe levels of noxious gases unless special ventilation and gas treatments are not made properly. Second difference is that the wafer surface roughness is higher compared with acidic etched surface. However, alkaline etch is superior to retain the flatness of the wafer, and it is as a waste environmentally better than hydrofluoric-containing acidic mixtures. Surface after etching is damage-free if etching is done properly, and appearance is bright. It should be remembered that the surface appearance is not only governed by the etchant, but also prior process steps have a role—how uniform the residual damage from previous processes has been, what has been the depth of damage vs. etch dept, and does the damage have a texture or fine structure, as is the case in grinding.

5.1.6.1 Donor Killing Donor killing (for donors, see Section 3.6) can be done in several manufacturing phases; often, it is done after etching and cleaning by heating the wafer above 650– 700°C for a short time, followed by fast cooling. By doing so, the effect of donors in resistivity is eliminated. Cleaning before donor kill has to be effective to remove surface metals to prevent penetration of fast-diffusing metals into silicon. Donor kill is usually not necessary for heavily doped wafers.

5.1.7 Polishing Wafers for MEMS applications are commonly doubleside polished. This can be done either by polishing first one side, then flipping the wafer over and polishing the second side, or polishing both sides simultaneously between two rotating polishing pads. The latter method is preferred, because it retains the wafer flatness well; however, with thin wafers it is more difficult to master. Polishing is done using alkaline colloidal silica slurry as polishing media. The required material removal depends on the wafer surface roughness. Polishing pads are made of porous polyurethane. The process is mainly chemical, and surface after polishing is free of mechanical damage. Traditional processes are batch-type processing tens of wafers at the same time. Also, CMP-type processes where each wafer is polished individually are today in use. Challenge is to retain the good wafer flatness achieved in previous process steps. Polishing is done in several steps. First there is a material removal step with aggressive slurry, with polishing speed of approx. 1 μm/min or more, resulting in rough but flat surface. There can be a second step, with less aggressive slurry, and final polish is done with a slurry having very low material removal rate and producing a smooth surface. Surface roughness measured with AFM over 1 μm2 field after final polishing is approximately 0.1 nm (RMS). Depending on the process type, wafers can float on the polishing head recess almost freely, wafers can be mounted with wax on polishing blocks, or wafers can be in carriers resembling lapping carriers (see Figure 5.10b). Material removal depends on the previous process steps: A rough surface needs more polishing, in excess

Fig 5.10 ● Lapping machine (a). Wafers are placed in carrier disk holes on lapping plate (b). Carrier disks are rotated by outer and inner pin rings rotating independently from each other and from upper and lower lapping plates. Abrasive slurry (alumina, optical emery, or silicon carbide slurry) is fed between lapping plates, and with carefully selected rotation rates and directions of lapping plates and carrier, the best possible flatness and thickness uniformity of wafers can be achieved.

78

Silicon Wafers: Preparation and Properties

of 20 μm; a smooth, regular surface manages with less than 10 μm. Although polishing slurry contains very fine particles which are easily emitted from the machine, polishing is done in clean room environment; the polishing clean rooms are isolated, however, to control particle introduction to other clean room areas. Polishing accuracy (final thickness, retention of TTV, and flatness) is not as good as in precision grinding or lapping. However, routinely sub-μm TTV values, important, for example, in bulk micromachining, can be obtained. Figure 5.12 shows an example of TTV and thickness distribution in a 150-mm wafer lot.

5.1.8 Clean Room Operations Polished wafer has chemical residues from polishing and particles. A good, and still valid, basic review of silicon wafer cleaning techniques is given, for example, by Hattori [15]. An updated view with references to modern techniques can be found in Reinhardt’s and Kern’s

F

Diamond wheel

Silicon wafer

Fig 5.11 ● Principle of silicon wafer surface grinding. A cup wheel with segmented diamond rim is pressed against co-rotating or counter-rotating silicon wafer sitting on a flat vacuum chuck.

(a)

handbook on silicon wafer cleaning technology (2nd edition) [16]. Typically silicon wafers are cleaned by RCA-type cleaning sequence invented in the 1960s or by more modern modified cleaning solutions [17]. The aim of the cleaning is to remove organics, surface metals, and particles. Organics are removed usually by alkaline solutions with presence of oxidizing agent, and the effect may be enhanced by megasonic agitation and elevated temperature. Oxidizer is important; otherwise, alkaline chemical attacks and etches silicon in an uncontrolled way. The tendency today is to have as diluted chemicals as possible for environmental and cost reasons. A typical effective chemical mixture to remove light organic contamination is DIW (deionized water), ammonia and hydrogen peroxide mixture (APM), or SC-1 in RCA clean terminology, at above 60°C with megasonic (⬎900 kHz) agitation. Organic contaminants as well as metals decompose hydrogen peroxide, and it is possible to use some stabilizers, similar to CDTA, cyclohexane-1,2-diaminetetra-acetic acid (see, for example, Ref. [18]), to enhance the useful lifetime of the cleaning bath. If the organic contamination is very heavy, sulfuric acid–hydrogen peroxide mixture (SPM) eventually diluted with water at temperatures above 100°C can be used. This mixture is called Piranha clean, and it is most commonly used in device-making steps to remove organic thin films, for example, wax residues from waxmounting polishing process. This mixture is also growing a dense oxide layer on the wafer. Silicon dioxide on the wafer surface is removed normally by very diluted (1:100) hydrofluoric acid–water mixture (DHF). Small amounts of hydrochloric acid (HCl) addition are sometimes used; the role of HCl is to remove, for instance, copper from the bare wafer surface. Traditionally, the last steps of cleaning sequences have been metal removal steps in hydrochloric acid–hydrogen peroxide–water mixture (HPM), SC-2 in RCA clean terminology; and elevated temperatures may be used to (b)

LB

–0.00

CHAPTER 5

USL

0.12

0.24

0.36

0.48

0.60

0.72

0.84

LSL

375.0

USL

376.5

378.0

379.5

381.0

382.5

384.0

Fig 5.12 ● TTV (a) and thickness (b) distributions obtainable for double-side-polished 150-mm silicon wafers. Horizontal scale is μm.

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enhance the cleaning effect. This mixture leaves on the wafer surface a thin native oxide containing OH-groups. After final rinses, wafers are dried. Drying can be done by centrifugal drying or with Marangoni method, where wafers are pulled slowly out of wafer under nitrogen flow with a small amount of isopropyl alcohol vapor added [19]. This technique is useful in drying structured wafers. In rinsing step there may be additional metal removals with very diluted acidic water [20]. For example, HCl-concentration in the ppm-range is effective at removing iron on the wafer surface. Figure 5.13 shows an example of a classical (full) cleaning sequence. Today the trend is to minimize chemical usage and simplify the process as much as possible. When the polishing process is producing wafers without heavy organic contamination, sulfuric acid cleans can be omitted, and dilute ammonia–hydrogen-peroxide based chemistries at elevated temperatures with megasonic agitation, combined with dilute hydrofluoric acid or hydrofluoric/ hydrochloric acid clean, followed by hydrochloric acid– hydrogen-peroxide cleans, remove effectively particles

SPM DIW DHF DIW SPM: Sulphuric acid–Hydrogen peroxide–water mixture APM (SC-1) DIW: De-Ionized water DIW DHF DIW HPM (SC-2)

DHF: Dilute Hyrofluoric acid– water mixture (classically, 1:100 to 1:50) APM : Ammonium hydroxide– Hydrogen peroxide–water mixture (classically 1:1:5) HPM: Hydrochloric acid– Hydrogen peroxide–water mixture (classically 1:1:5)

DIW (DHF) DIW Dry

Fig 5.13 ● A classical cleaning sequence used after polishing, effectively removing organic, metallic, and particulate contamination. Steps in gray are commonly used.

80

and organic and metallic contamination. Ozone addition in water can be used to increase the oxidation potential of water to produce a dense oxide layer on the wafer surface. Generally, the surface concentrations of the transition metals levels of copper, nickel, and iron after clean are below 1 ⫻ 1010 atoms/cm2; aluminum, zinc, and calcium levels are slightly above typical transition metal levels; and alkaline elements like sodium are below 5 ⫻ 1010 atoms/cm2. If maximum metal concentrations are specified in wafer specifications, iron can be used as an indicator: (1) if iron level is increased on wafer surfaces, normally other metals are also at higher level; (2) iron is the most common contaminant coming from chemicals (especially in alkaline cleans); and (3) iron is easy to detect and measure at very low concentrations with several methods, with minority carrier lifetime, with DLTS, and with VPD-TXRF techniques. It should be noted that the contribution of surface metals is much higher than contribution from bulk metals from crystal growing in processed wafer with devices. If wafer is 400 μm thick, which is quite common in MEMS applications, and the metal concentration on wafer surface is 1 ⫻ 1010 atoms/cm2 (both on front and backside), and if in thermal treatments all surface metals are diffusing in the bulk, the bulk concentration increases to 5 ⫻ 1011 atoms/cm3. This figure exceeds the contamination level that is found in crystals. If in device manufacturing line ammonia-based clean with uncontrolled chemicals is used as a last step, iron concentration can be up to 1012 atoms/cm2, resulting in, potentially, 5 ⫻ 1013 atoms/cm3 bulk iron contamination level. Here is presented an extreme situation, and in practice only part of the potential metal is diffused in. Surface metal contribution has to be taken into account in designing the device manufacturing process and cleans in it, and this is often neglected, even when the incoming wafer cleanliness is well in control. Surface metals have adverse effects, both in electrical properties (for instance, iron reducing heavily minority carrier lifetime), bulk properties (many metals promoting bulk crystal defect formation), or surface properties (promoting stacking fault generation in oxidation, reducing oxide integrity, or generating epi defects). Especially, crystal defects generated during device processing can decrease MEMS device yield or performance. A good review to the subject can be found—for instance, for iron and for copper—in Refs [21] and [22], respectively.

5.2 Standard Measurements of Polished Wafers Customer wafer specifications define what is measured and reported on finished wafers and are the measurements done either on a specified sampling plan or on all

Silicon Wafers: Preparation and Properties

wafers. Some of the measurements, for example, oxygen concentration, have to be done from special samples made after crystal is grown from thick samples. Many measurements destroy the wafer, increasing the cost of manufacturing—these kind of measurements, if possible, are made at the minimum necessary level. In the following, a brief description of each measurement is given. A list of selected SEMI specifications and standards of commonly used measurements is given in Section 5.4. For a complete list of measurements, the reader should consult Ref. [1].

5.2.1 Oxygen and Carbon Concentration Oxygen is in interstitial sites in silicon lattice, and in CZ silicon it is supersaturated at normal processing temperatures. Typical achievable range in CZ growth process is approximately 6–18 ppma, or 3…9 ⫻ 1017 atoms/cm3 Si expressed in units of SEMI MF 1188-1107 [23]. Carbon lies in substitutional lattice sites, and concentration is typically ⬍0.3 ppma or ⬍1.5 ⫻ 1016 atoms/cm3 Si; measurement is made according to SEMI MF13911107 [24]. Precision measurements are made using double-sidepolished, or bright-etched, 2–4-mm-thick samples cut from grown crystals, using purpose-build FTIR spectrometers. Interstitial oxygen absorbs at 1107 cm⫺1 wave number (9.03 μm wavelength IR-radiation). Current (IOC-88) conversion factor from net absorption coefficient to concentration in ppma is 6.28, and to atoms/cm3 Si 3.14 ⫻ 1017. Earlier conversion factors to ppma were 4.9 (ASTM 1983-factor) and 9.62 (ASTM 1979-factor) and, correspondingly, to atoms/cm3 Si 2.45 ⫻ 1017 and 4.81 ⫻ 1017. Thus, major errors can be made if the conversion factor is not clearly defined, especially as the industry veterans still use the outdated ASTM 1979 definitions. For listings of current conversion factors between old ASTM, new ASTM, JEIDA (Japanese), Gun Biao (Chinese), and IOC-88, see SEMI M44-0305 standard [25]. Carbon is absorbing at 605cm⫺1 wave number, or 16.53 μm wavelength. At room temperature a phonon band has a strong absorption at 610 cm⫺1, which makes a known zero-carbon content reference sample of same thickness and surface properties necessary at room temperature measurements. Oxygen and carbon content measurements can be made also from actual wafers, but with lower accuracy. Accuracy can be improved if a known reference with same thickness and surface properties is available. Especially if only one wafer surface is polished, accuracy is poor, since calculation algorithms are based on the polished silicon surface reflection factor of 0.3. Unpolished surface has lower reflection factor, which

CHAPTER 5

changes internal reflections contributing to the total IR absorption. There are published methods of how to measure oxygen concentration in thin wafers [26].

5.2.2 Metal Concentration Measurements Bulk metal concentrations in silicon wafers are generally very low, and standard practice is to follow only bulk iron level through minority carrier lifetime measurements in lightly boron-doped silicon. Common technique in use is μPCD (photoconductivity decay) method based on photo-induced minority carrier lifetime, according to SEMI MF1535-0707 standard [27]. Carriers are generated by light pulses, and the decay of the carrier density is measured by microwave reflection. Iron concentration can be calculated by comparing minority carrier lifetimes before and after iron–boron pair dissociation in p-type material. Expected minority carrier lifetime result of a good quality ⬎10 ohm-cm p-type material, when surface recombination effects are prevented, for example, with corona-discharge, is above 300 μs. It should be noted that bulk defects, like oxide precipitates from annealing steps, are reducing lifetime, and the real picture of the contamination level can be had only from received wafers without processing. Wafer surface passivation to prevent surface recombination is also important. This passivation can be made with the iodide-methanol method, or with growing an oxide in dry oxygen. Further information on this technique and comparison to results from other common techniques based on surface photovoltage (SPV) and photocurrent collected by a silicon-electrolyte contact (Elymat) can be found, e.g., in the paper of Polignano et al. [28]. Surface metals are commonly analyzed with three techniques: light elements with AAS (atomic absorption spectroscopy) or ICP-MS (inductively coupled plasma mass spectroscopy) and heavier elements with a TXRF (total X-ray reflection fluorescence) analysis. Especially if these techniques are combined with a VPD-method (vapor phase decomposition), [29] where contamination is collected to a small chemical droplet traversed over the wafer, the sensitivity is enhanced in best case to levels of 1 ⫻ 108 atoms/cm2. SEMI MF1724-1107 describes the AAS-method, [30] and SEMI M33-0998 describes the TXRF-method [31]. Surface metals are important, because most of the bulk impurities are coming from surface metals introduced from various process steps. Thus, surface analysis is used not only to control incoming wafers, but especially to control chemicals and process equipment. A common practice is to use high-resistivity p-type wafers with known, high minority carrier lifetime as control wafer for monitoring purposes. 81

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Silicon as MEMS Material

5.2.3 Resistivity Resistivity of the wafer is measured with a contact method using a 4-point probe according to SEMI MF43-0705 and MF84-0307 [32, 33]. This method can be used to map wafer resistivity or to measure the resistivity gradient, SEMI MF81-1105 [34]. As contact methods damage and thus destroy the wafer surface, these methods are used typically for monitoring purposes only with monitor wafers. Polished prime wafers are measured with noncontact methods based on eddy current measurement, according to SEMI MF673-1105 [35]. Noncontact measurements have an accuracy and repeatability of ⬍2–3% once properly calibrated. As measurement systems are used in volume production environment, it is practical to measure only two points from the wafer, centerpoint and R/2- or edge-point (typically, 6 or 10 mm from edge). Probe is collecting information from a large surface area; thus, the method is not able to resolve small-scale variations, like dopant striations. If small-scale resistivity variations need to be measured, a spreading resistance (SPR) measurement is done according to SEMI MF535-0307 [36] and other SPR-related standards. However, the silicon surface preparation and the SPR measurement itself require special skills, and the accuracy of the resistance or carrier density is only indicative, not as good as with a 4-point probe or with eddy-current method results.

5.2.4 Wafer Geometry Wafer measurements for thickness, thickness variation (TTV), and shape (warp, bow) are done with a noncontact capacitive method according to SEMI 1530-0707, [37] and commonly, 100% of wafers are measured. Production equipment frequently combines the resistivity and geometry measurements. One probe station is for resistivity, one station is for dimensions, and typically the equipment has also receiving stations for accepted and rejected wafers. Routinely each wafer is measured for thickness, TTV, flatness, and bow/warp. Since there are many different definitions for flatness and, especially, site flatness, care has to be taken to define correct site size and reference planes, should they be 3-point, global best fit, global front side, global backside, site best fit, what is the PUA percentage (usable area within specs), etc. For instance, lithography process steps may set specific requirements for the flatness definition. SEMI M12 shows flatness decision tree for all possible flatness definition alternatives.

5.2.5 Particles Particles can be controlled visually under bright collimated light according to SEMI MF523-0706 [38]. The 82

human eye is quite sensitive to particles capable of seeing down to 0.3 μm particles. Visually, also, high levels of haze can be seen easily. Haze consists typically of small densely spaced scatterers, like pits, fine particles, or localized roughness; or it can evolve during storage as a result of the atmosphere in the storage cassette combined with suitable incubator. (Then it is called delayed haze or time-dependent haze.) Small (⬍0.3 μm) particles can be seen reliably only with dedicated laser scanners [39]. Automated laser scanners allow measurement of every wafer, too. Care has to be taken when measuring small particles in the 0.1 to approximately 0.16 μm range not to mix particles with COPs born from crystal growth. Crystal originated particles (COP) are small vacancy agglomerates that are harmful in certain CMOS processes. It is common to specify particles only in such size classes, which are known to be harmful for the device manufacturing process.

5.2.6 Other Measurements In each major process step in Figure 5.1 there are several values which are monitored in SPC (statistical process control) programs to keep the manufacturing process stable. Stable process helps to reduce laboratory monitoring of the wafers once correlations between stable process and actual wafer results are established. As a sample basis (ranging from a wafer/lot to daily or weekly frequency), several features in wafers can be measured, like subsurface damage, with preferential etching, oxidation-induced stacking fault content (OISF’s), crystallographic perfection, exact crystallographic orientation, or oxygen precipitation with thermal treatments simulating device manufacturing processes.

5.3 Sample Specifications of MEMS Wafers SEMI provides sample specifications for wafers used in semiconductor application (SEMI, 2007) in standards M1-0707, “Specifications for polished monocrystalline silicon wafers,” [2] and M24-0307, “Specifications for polished monocrystalline silicon premium wafers” [40]. The previous standard’s aim is to specify wafers for general semiconductor use up to 300 mm wafer diameter, while the latter is specifying 150–300 mm wafers for high-end IC’s made with deep submicrometer technologies. In addition, there are other standards focusing on particular issues like M59 “Terminology for Silicon Technology.” Those interested to get the complete view should consult SEMI book of standards [1].

Silicon Wafers: Preparation and Properties

Standardization of wafers for MEMS applications is still in nascent phase. This is because in the past manufacturing processes and device designs and their requirements differ very much from each other; in worst case, every process and device design had its own company-specific wafer specification. The situation is changing because many new manufacturing processes are designed to maximize compatibility with standard CMOS process and because of the introduction of new processes, like deep reactive ion etching. However,

CHAPTER 5

there will still be some unique specified properties left in which MEMS wafers differ from standard CMOS wafers. Dimensional parameters, like TTV, or wafer thickness distribution and the common requirement of double-side polishing are examples. Table 5.4 gives an example specification for 150-mm double-side polished wafers. 200-mm wafer specification is essentially similar; the only difference is that the orientation flat is replaced by a notch. SEMI M1-0707 [2] gives a complete list of properties which may be defined.

Table 5.4 Sample wafer specification

Crystal characteristics Crystal pulling method

MCZ

Crystal orientation

(100) ⫾ 0.2°

Dopant

Boron

Resistivity

3–5

ohm-cm

Centerpoint, SEMI MF673

Radial resistivity variation, max

4

%

Measured at R/2 SEMI MF81

Oxygen content

6–10

ppm

SEMI MF1188

Carbon content

具0.3

ppm

SEMI MF1391

Minority carrier lifetime

NS (not specified)

μs

µPCD, SEMI MF1535

Wafer diameter

150 ⫾ 0.3

mm

SEMI MF2024

Wafer thickness

400 ⫾ 5

mm

SEMI MF533

Orientation flat

[110] ⫾ 0.2°

Flat length

57.5 ⫾ 2.5

mm

SEMI M1

Wafer TTV

具1.0

μm

SEMI MF533

Flatness, global

具1

μm

GBIR, SEMI MF1530

Wafer edge profile

Round

Warp

具40

μm

SEMI MF657

Bow

具40

μm

SEMI MF534

SEMI MF26

Wafer characteristics

SEMI MF847

SEMI M1, SEMI MF928

Front surface characteristics Front surface

Polished, damage-free

Scratches

None

Visual inspection SEMI MF523 (Continued )

83

PA R T I

Silicon as MEMS Material

Table 5.4 (Continued) Stains, pits, mounds

None

Visual inspection SEMI MF523

Particles

⬍20

⬎0.3 μm

Visual inspection SEMI MF523

OISF

⬍100

1/cm2

SEMI MF1727

Metals (Fe,Cu,Ni,Zn,Ca)

⬍1 ⫻ 1010

1/cm2

SEMI M33

Metals (Al)

⬍1 ⫻ 1011

1/cm2

AAS

Laser marking

Deep marking

SEMI M12

Back surface characteristics Back surface

Polished, damage-free

Scratches, mm max

20

Visual inspection SEMI MF523

Stains, pits, mounds

None

Visual inspection SEMI MF523

Wafer packing Cassette

Empak

Wafers in cassette

24

Cassette sealing

Double bag Inert gas fill

5.4 Standards of Silicon Wafers Throughout the industry, SEMI standards annually updated by SEMI are used as a reference and guideline in specifications. These standards have a good coverage over different aspects of silicon technology: from equipment automation, facilities, gases, materials, MEMS, microlithography, packaging, process chemicals, safety guidelines, silicon materials, and process control, to traceability. Sometimes, also national standards, like JEIDA standards in Japan or DIN standards in Germany, are in use. Earlier, commonly used ASTM standards from USA now have been replaced by corresponding and updated SEMI standards. Generally, comparable new standards from different sources are in good harmony with each other. However, oxygen content in silicon wafers is often still, after decades of first conversion factor changes, still specified using old standards of ASTM, pre-1980s, in spite of there having been 2 major revisions after that date. JEIDA and DIN standard conversion factors also differ from early ASTM standards. Thus, care has to be taken when verifying which standard has been in use, to avoid 84

pcs

First slot empty Outer bag aluminum laminate, inner clear plastic

fundamental mistakes, especially when a common (bad) practice here is not to specify the year of the standard. Standards for materials give only guidelines, and their values are applied only if no other value or definition is agreed upon. For instance, wafer thickness variation for 150 mm and 200 wafers according to Semi MI-0307 has to be ⫾ ⱕ 15 (for 200 mm 20) μm and TTV ⱕ 10 μm. For many MEMS applications, these values are far too high—the TTV requirement may be ⱕ1 μm or even in submicrometer range. Semi has published, in November 2007 standard edition, only 5 directly MEMS specific standards. Therefore, general silicon-wafer-related standards are applied if there is no specific MEMS standard available. Below are listed selected standards related to silicon in MEMS applications, (in the order of appearance in November 2007 standard collection): E89-0707 Guide for Measurement System Analysis (MSA) M1-0707

Specification for Polished Monocrystalline Silicon Wafers

Silicon Wafers: Preparation and Properties

CHAPTER 5

Unpatterned Semiconductor Wafer Surfaces

M8-0307

Specification for Polished Monocrystalline Silicon Test Wafers

M12-0706

Specification for Serial Alphanumeric Marking of the Front Surface of Wafers

M13-0706

Specification for Alphanumeric Marking of Silicon Wafers

M16-1103

Specification for Polycrystalline Silicon

M17-0704

Guide for a Universal Wafer Grid

M61-0307

M18-1107

Guide for Developing Specification Forms for Order Entry of Silicon Wafers

Specification for Silicon Epitaxial Wafers with Buried Layers

M62-1107

Specification for Silicon Epitaxial Wafers

M20-1104

Practice for Establishing a Wafer Coordinate System

MS1-0307

Guide to Specifying Wafer–Wafer Bonding Alignment Targets

M24-0307

Specification for Polished Monocrystalline Silicon Premium Wafers

MS3-0307

Terminology for MEMS Technology

MS5-1107

Test Method for Wafer Bond Strength Measurements Using Micro-Chevron Test Structures

M32-0307

Guide to Statistical Specifications

M33-0998

Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means of Total Reflection X-Ray Fluorescence Spectroscopy

M57-0706

Guide for Specifying Silicon Annealed Wafers

M59-1107 M60-0306

Terminology for Silicon Technology E2

Test Method for Time Dependent Dielectric Breakdown Characteristics of SiO2 Films for Si Wafer Evaluation

ME1392-0305 Guide for Angle Resolved Optical Scatter Measurements on Specular or Diffuse Surfaces MF26-0305

Test Methods for Determining the Orientation of a Semiconductive Single Crystal

MF28-0707

Test Methods for Minority Carrier Lifetime in Bulk Germanium and Silicon by Measurement of Photoconductive Decay

M34-0299

Guide for Specifying SIMOX Wafers

M35-1107

Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection

M38-0307

Specification for Polished Reclaimed Silicon Wafers

MF42-1105

M40-0200

Guide for Measurement of Surface Roughness of Planar Surfaces on Silicon Wafer

Test Methods for Conductivity Type of Extrinsic Semiconductor Materials

MF43-0705

Test Methods for Resistivity of Semiconductor Materials

M41-0707

Specification of Silicon-on-Insulator (SOI) for Power Devices/ICS

MF81-1105

Test Method for Measuring Radial Resistivity Variation on Silicon Wafers

M43-0301

Guide for Reporting Wafer Nanotopography

MF84-0307

M44-0305

Guide to Conversion Factors for Interstitial Oxygen in Silicon

Test Method for Measuring Resistivity of Silicon Wafers with an In-Line FourPoint Probe

M46-1101E

MF95-1107

Test Method for Measuring Carrier Concentrations in Epitaxial Layer Structures by Electrochemical Capacitance Voltage (ECV) Profiling

Test Method for Thickness of Lightly Doped Silicon Epitaxial Layers on Heavily Doped Silicon Substrated Using an Infrared Dispersive Spectrometer

M51-0303

Test Method for Characterizing Silicon Wafer by Gate Oxide Integrity

MF110-1107

M53-0706

Practice for Calibrating Scanning Surface Inspections Systems Using Certified Depositions of Monodisperse Polystyrene Latex Spheres on

Test Method for Thickness of Epitaxial or Diffused Layers in Silicon by the Angle Lapping and Staining Technique

MF154-1105

Guide for Identification of Structures and Contaminants Seen on Specular Silicon Surfaces 85

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Silicon as MEMS Material

MF374-0307

Test Method for Sheet Resistance of Silicon Epitaxial, Diffused, Polysilicon, and Ion-Implanted Layers Using an In-Line Four-Point Probe with SingleConfiguration Procedure

MF391-1106

Test Method for Minority Carrier Diffusion Length in Extrinsic Semiconductors by Measurement of Steady-State Surface Photovoltage

MF397-1106

Test Method for Resistivity of Silicon Bars Using a Two-Point Probe

MF523-1107

Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces

MF525-0307

Test Method for Measuring Resistivity of Silicon Wafers Using Spreading Resistance Probe

MF533-0706

Test Method for Thickness and Thickness Variation of Silicon Wafers

MF534-0707

Test Method for Bow of Silicon Wafers

MF576-0706

Test Method for Measurement of Insulator Thickness and Refractive Index on Silicon Substrates by Ellipsometry

MF657-0707

MF671-0707

Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning Test Method for Measuring Flat Length on Wafers of Silicon and Other Electronic Materials

MF950-1107

Test Method for Measuring the Depth of Crystal Damage of a Mechanically Worked Silicon Wafer Surface by Angle Polishing and Defect Etching

MF951-0305

Test Method for Determination of Radial Interstitial Oxygen Variation in Silicon Wafers

MF978-1106

Test Method for Characterizing Semiconductor Deep Levels by Transient Capacitance Techniques

MF1048-1105 Test Method for Measuring the Reflective Total Integrated Scatter MF1049-1107 Practice for Shallow Etch Pit Detection on Silicon Wafers MF1152-0305 Test Method for Dimensions of Notches on Silicon Wafers MF1153-1106 Test Method for Characterization of Metal-Oxide-Silicon (MOS) Structures by Capacitance-Voltage Measurements MF1188-1107 Test Method for Interstitial Oxygen Content of Silicon by Infrared Absorption with Short Baseline MF1239-0305 Test Method for Oxygen Precipitation Characteristics of Silicon Wafers by Measurements of Interstitial Oxygen Reduction MF1366-0305 Test Method for Measuring Oxygen Concentration in Heavily Doped Silicon Substrates by Secondary Ion Mass Spectroscopy

MF672-0307

Test Method for Measuring Resistivity Profiles Perpendicular to the Surface of a Silicon Wafer Using a Spreading Resistance Probe

MF673-1105

Test Method for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gauge

MF674-0705

Practice for Preparing Silicon for Spreading Resistance Measurements

MF723-0307

Practice for Conversion between Resistivity and Dopant or Carrier Density for Boron-Doped, PhosphorusDoped, and Arsenic-Doped Silicon

MF847-0705

Test Method for Measuring Crystallographic Orientation of Flats on Single Crystal Silicon Wafers by Xray Techniques

MF1392-0307 Test Method for Determining Net Carrier Density Profiles in Silicon Wafers by Capacitance-Voltage Measurements with a Mercury Probe

MF928-0305

Test Method for Edge Contour of Circular Semiconductor Wafers and Rigid Disk Substrates

MF1451-0707 Test Method for Measuring SORI on Silicon Wafers by Automated NonContact Scanning

86

MF1388-0707 Test Method for Generation Lifetime and Generation Velocity of Silicon Material by Capacitance-Time Measurements of Metal-Oxide-Silicon (MOS) Capacitors MF1390-0707 Test Method for Measuring Warp on Silicon Wafers by Automated Noncontact Scanning MF1391-1107 Test Method for Substitutional Atomic Carbon Content of Silicon by Infrared Absorption

Silicon Wafers: Preparation and Properties

MF1527-0307 Guide for Application of Certified Reference Materials and Reference Wafers for Calibration and Control of Instruments for Measuring Resistivity of Silicon MF1528-1107 Test Method for Measuring Boron Contamination in Heavily Doped NType Silicon Substrates by Secondary Ion Mass Spectrometry MF1530-0707 Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Non-Contact Scanning MF1535-0707 Test Method for Carrier Recombination Lifetime in Silicon Wafers by Non-Contact Measurement of Photoconductive Decay by Microwave Reflectance MF1617-0304 Test Method for Measuring Surface Sodium, Aluminum, Potassium, and Iron on Silicon and Epi Substrates by Secondary Ion Mass Spectrometry MF1618-1104

Practice for Determination of Uniformity of Thin Films on Silicon Wafers

MF1619-1107

Test Method for Measurement of Interstitial Oxygen Content of Silicon Wafers by Infrared Absorption Spectroscopy with P-Polarized Radiation Incident at the Brewster Angle

MF1724-1104 Test Method for Measuring Surface Metal Contamination of Polycrystalline

CHAPTER 5

Silicon by Acid Extraction-Atomic Absorption Spectroscopy MF1725-1103 Practice for Analysis of Crystallographic Perfection of Silicon Ingots MF1726-1103 Practice for Analysis of Crystallographic Perfection of Silicon Wafers MF1727-0304 Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers MF1771-0304 Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique MF1809-0704 Guide for Selection and Use of Etching Solutions to Delineate Structural Defects in Silicon MF1810-0304 Test Method for Counting Preferentially Etched or Decorated Surface Defects in Silicon Wafers MF1982-1103 Test Method for Analyzing Organic Contaminants on Silicon Wafer Surfaces by Thermal Desorption Gas Chromatography MF2074-0707 Test Method for Measuring Diameter of Silicon and Other Semiconductor Wafers MF2139-1103 Test Method for Measuring Nitrogen Concentration in Silicon Substrates by Secondary Ion Mass Spectrometry

References 1. International SEMI Standards, Semiconductor Equipment and Materials International, November 2007, www.SEMI.org. 2. SEMI M1-0707, Specifications for Polished Monocrystalline Silicon Wafers, Semiconductor Equipment and Materials International 2007, www.semi.org. 3. http://www.itrs.net/ 4. H.J. Möller, Basic mechanisms and models of multi-wire sawing, Adv. Eng. Mater. 6 (2004) 501–513. 5. M12-0706 Specification for Serial Alphanumeric Marking of the Front Surface of Wafers, Semiconductor Equipment and Materials International 2007, www.semi.org. 6. M13-0706 Specification for Alphanumeric Marking of Silicon Wafers, Semiconductor Equipment and

7.

8.

9.

10.

Materials International 2007, www. semi.org. Z.J. Pei, G.R. Fisher, M. Bhagavat, S. Kassir, A grinding-based manufacturing method of silicon wafers: an experimental investigation, Int. J. Mach. Tools Manufact. 45 (2005) 1140–1151. Z.C. Li, Z.J. Pei, G.R. Fisher, Simultaneous double side grinding of silicon wafers: a literature review, Int. J. Mach. Tools Manufact. 46 (2006) 1449–1458. J.H. Liu, Z.J. Pei, G.R. Fisher, Grinding wheels for manufacturing of silicon wafers: a literature review, Int. J. Mach. Tools Manufact. 47 (2007) 1–13. G. Pietsch, M. Kerstan, Understanding simultaneous double-disk grinding; operation principle and material removal kinematics in silicon wafer

11.

12.

13.

14.

15.

planarization, Precis. Eng. 29 (2005) 189–196. H. Robbins, B. Schwartz, Chemical etching of silicon I. The system HF, HNO3, and H2O, J. Electrochem. Soc. 106 (1959) 505–508. H. Robbins, B. Schwartz, Chemical etching of silicon II. The system HF, HNO3, H2O and HC2H3O2, J. Electrochem. Soc. 107 (1960) 108–111. R. Schwartz, H. Robbins, Chemical etching of silicon III. A temperature study in the acid system, J. Electrochem. Soc. 108 (1961) 365–372. Z. Liu, T. Sun, J. An, J. Wang, X. Xu, R. Cui, Silicon etching in HF/HNO3/ NH3*H2O/H2O system, J. Electrochem. Soc. 154 (2007) D21–D29. T. Hattori, Trends in wafer cleaning technology Chapter 32, in: T. Hattori

87

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16.

17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

Silicon as MEMS Material

(Ed.), Ultraclean Surface Processing of Silicon Wafers, Springer-Verlag, 1995. K. Reinhard, W. Kern, Handbook on Silicon Wafer Cleaning Technology, William Andrew Inc., Norwich, 2007. W. Kern, The evolution of silicon wafer cleaning technology, J. Electrochem. Soc. 137 (1990) 1887–1892. H. Saloniemi, T. Visti, S. Eränen, A. Kiviranta, O. Anttila, Improvement of SC-1 bath stability by complexing agents, Phys. Scr. T101 (2002) 226–229. A. Leenaars, J. Huethorst, J. van Onkel, Marangoni drying: a new extremely clean drying process, Langmuir 6 (1990) 1701–1703. O. Anttila, M. Tilli, Metal contamination removal on silicon wafers using dilute acidic solutions, J. Electrochem. Soc. 139 (1992) 1751–1756. A. Istratov, H. Hieslmair, E. Weber, Iron contamination in silicon technology, Appl. Phys. A 70 (2000) 489–534. A. Istratov, E. Weber, Physics of copper in silicon, J. Electrochem. Soc. 149 (2002) G21–G30. SEMI MF1188-1107 Test Method for Interstitial Oxygen Content of Silicon by Infrared Absorption with Short Baseline, Semiconductor Equipment and Materials International 2007, www.semi.org. SEMI MF1391-1107 Test Method for Substitutional Atomic Carbon Content of Silicon by Infrared Absorption, Semiconductor Equipment and Materials International 2007, www. semi.org. SEMI M44-0305 Guide to Conversion Factors for Interstitial Oxygen in Silicon, Semiconductor Equipment and Materials International 2007, www.semi.org. H. Shirai, Oxygen measurements on acid-etched Czochralski-grown silicon

88

27.

28.

29.

30.

31.

32.

33.

wafers, J. Electrochem. Soc. 139 (1992) 3272–3275. SEMI MF1535-0707 Test Method for Carrier Recombination Lifetime in Silicon Wafers by Non-Contact Measurement of Photoconductive Decay by Microwave Reflectance, Semiconductor Equipment and Materials International 2007, www. semi.org. M. Polignano, F. Cazzaniga, A. Sabbadini, G. Queirolo, A. Cacciato, A. DiBartolo, Comparison among lifetime techniques for the detection of transition metal concentration, Mater. Sci. and Eng. B. 42 (1996) 157–163. C. Neumann., P. Eichinger, Ultra-trace analysis of metallic contaminants on silicon wafer surfaces by vapour phase decomposition/total reflection X-ray fluorescence (VPD/TXRF), Spectrochim. Acta, Part B 46 (1991) 1369–1377. SEMI MF1724-1104 Test Method for Measuring Surface Metal Contamination of Polycrystalline Silicon by Acid ExtractionAtomic Absorption Spectroscopy Semiconductor Equipment and Materials International 2007, www. semi.org. SEMI M33-0998 Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means of Total Reflection X-Ray Fluorescence Spectroscopy, Semiconductor Equipment and Materials International 2007, www. semi.org. SEMI MF43-0705 Test Methods for Resistivity of Semiconductor Materials, Semiconductor Equipment and Materials International 2007, www.semi.org. SEMI MF84-0307 Test Method for Measuring Resistivity of Silicon

Wafers with an In-Line Four-Point Probe, Semiconductor Equipment and Materials International 2007, www.semi.org. 34. SEMI MF81-1105 Test Method for Measuring Radial Resistivity Variation on Silicon Wafers, Semiconductor Equipment and Materials International 2007, www.semi.org. 35. SEMI MF673-1105 Test Method for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gauge, Semiconductor Equipment and Materials International 2007, www.semi.orgwww.semi.org. 36. SEMI MF525-0307 Test Method for Measuring Resistivity of Silicon Wafers Using Spreading Resistance Probe, Semiconductor Equipment and Materials International 2007, www. semi.org. 37. SEMI MF1530-0707 Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Non-Contact Scanning, Semiconductor Equipment and Materials International 2007, www.semi.org. 38. SEMI MF523-1107 Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces, Semiconductor Equipment and Materials International 2007, www.semi.org. 39. SEMI M35-1107 Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection, Semiconductor Equipment and Materials International 2007, www.semi.org. 40. SEMI M24-0307 Specification for Polished Monocrystalline Silicon Premium Wafers, Semiconductor Equipment and Materials International 2007, www.semi.org.

6

Chapter Six

Epi Wafers: Preparation and Properties Douglas J. Meyer AZonic Solar, Mesa, AZ, USA

The epitaxial deposition of Si, often referred to as epi, is an essential step in the formation of many MEMS structures. Epi is used as etch stops for forming BESOI (bonded etch-back silicon on insulator) structures, on SIMOX SOI structures to increase the Si thickness above the buried oxide (BOX) and as a means for build ing a combination monocrystalline/polycrystalline struc ture referred to as epi-poly. Epi layers of up to 100 μm, or even more, are used in MEMS structures, although most applications require only 2–20 μm of epi. This brief treatise on epitaxy touches on the funda mentals of epitaxial deposition as well as some speciﬁc examples relevant to MEMS. A comprehensive discus sion of Si epitaxy can be found in the tome edited by Crippa et al. [1].

Load wafer(s) into the process chamber

Purge process chamber

Heat to H2 bake temperature

Perform H2 bake

Heat or cool to deposition temperature

Deposit the epi layer

Cool to wafer unload temperature

6.1 Silicon Epitaxy—The Basics Unload wafer(s)

Epitaxy was invented at AT&T Bell Labs [2] circa 1960 in order to improve doping proﬁle abruptness and increase the operating frequencies of bipolar transis tors. Since then, the use of epitaxy has spread through out the semiconductor industry and can be found in nearly all fabrication disciplines. Although the details of epitaxial deposition recipes are often highly speciﬁc to the precise goals of the process, with respect to MEMS applications, the process can often be represented by Figure 6.1. Silicon substrates (wafers) are loaded into the proc ess chamber and the chamber is then purged with N2, if loading required exposure to air. Hydrogen is intro duced and the process chamber then remains in an H2 ambient throughout the entire process. The chamber is

Etch the process chamber

Fig 6.1 ● The basic epitaxy process recipe.

heated to a temperature sufﬁcient for removing native oxide from the wafer surface as described in Section 6.1.1. Following native oxide removal, the chamber is then cooled, if necessary, to the desired temperature for deposition of the epitaxial layer. The choice of deposi tion temperature, pressure, silicon precursor and doping species are discussed in Sections 6.1.2, 6.1.3 and 6.1.4. After depositing the epi layer, the system is brieﬂy purged in H2 to remove any residual Si and doping gas 89

Silicon as MEMS Material

species and then cooled to the appropriate tempera ture for unloading the processed substrates. After the substrates have been unloaded the chamber may be heated to 1200°C and etched with HCl (gas phase concentration of 50% HCl in H2 in the chamber) or the process chamber is loaded with a new set of wafers and another epi process run is begun. The frequency of process chamber etching is determined by the type of epi reactor (single wafer or batch), the build-up of dopant background in the chamber and the amount of Si accumulated in the process chamber.

6.1.1 Surface Preparation The growth of epitaxial Si fundamentally requires that the deposition occur over a surface that has an atomic spacing very nearly equal to that of Si. The most com mon case of Si epitaxy is that of homoepitaxial growth, where Si epi is deposited on a Si substrate. Si sub strates are normally covered with a native oxide consist ing of 1–3 nm of SiO2 and this amorphous layer must ﬁrst be removed to expose the Si surface. Removal is commonly accomplished by reduction in H2 at an ele vated temperature of 1100°C or more through the reactions: SiO2(s) H2 (v) SiO(v) H2O(v)

(6.1)

SiO2(s) Si(s) 2SiO(v)

(6.2)

and

Equation 6.1 is the dominant process for native oxide removal at low temperatures with Eq. 6.2 becoming important at higher temperatures. This process step is referred to as the hydrogen bake. The presence of H2O in Eq. 6.1 suggests that the H2 bake step is sensitive to the water vapor content of the H2 used in the proc ess. This is indeed highly signiﬁcant and H2O contents of 1 ppm, and preferably 100 ppb, are essential for high quality, stacking fault-free epitaxial processing. Figure 6.2 demonstrates the impact of temperature on the SiO2 reduction rate with a H2 source containing 10 ppb of H2O. Some epitaxial processes have severe thermal budget limitations due to the presence of other structures on the wafer prior to epi. In these cases the native oxide can be removed by liquid phase etching with a dilute HF solution, typically 100:1 deionized water to reagent HF by volume, for a duration of 2–5 minutes at room temperature. Native oxide removal proceeds via the reaction: SiO2(s) 6HF(l) H2(v) + SiF6 (l) 2H2O(l) 90

(6.3)

10

SiO2 etch rate (nm/min)

PA R T I

1

0.1

1200°C 1100°C 1000°C

0.01 0.6

0.7

900°C

0.8

0.9

1000/T (K–1)

Fig 6.2 ● SiO2 etch rate in H2 at 100 kPa.

Rinsing the wafers in ultrapure deionized water (total ionized C content 5 ppb, dissolved O content 50 ppb) after the etch will result in a hydrogen ter minated surface that resists oxidation for several hours in ambient conditions. This allows transportation of the etched wafers to an inert gas purged or vacuum loadlock for staging prior to epitaxial processing. The ex-situ removal of the native oxide enables the hydrogen bake to be performed at a temperature of 850°C or so for 5 minutes and yields an O-free epi/substrate interface. Failure to remove the native oxide prior to deposition will result in amorphous or polycrystalline ﬁlm growth, depending on the temperature of deposition. If a chlorosi lane is used as the Si precursor, the ﬁlm deposited over the native oxide will most likely be discontinuous, or at sufﬁciently low temperatures, no growth will occur at all.

6.1.2 Silicon Precursors and Deposition Temperature The choice of a Si precursor and the deposition temper ature are strongly related to the dopants and structure present on the wafer prior to epitaxy. An Arrhenius plot of the commercially available Si precursors most often used for Si epitaxy is shown in Figure 6.3. The deposition of Si from chlorosilanes can be described by the overall reaction as in SiH(4n )C l n ( v ) (n 2)H2(v) Si(s) nHCl(v) n 2, 3 or 4

(6.4)

Epi Wafers: Preparation and Properties

and for non-chlorinated silanes as Si m H2(m 1)(v) Si(s) (m 1)H2 (v) m 1, 2 or 3 (6.5)

Precursors such as Si2H6 and Si3H8 are extremely expensive compared to SiH4 and the chlorosilanes. Thus, their application is reserved for processes requir ing very thin epitaxy at low deposition temperatures, for example, T600°C. Fortunately, MEMS applications do not normally require such low epi process temper atures, thereby enabling the use of less expensive pre cursors which have higher deposition rates and higher productivity. Further, the use of SiCl4, which was quite common in the 1970s and 1980s, has been curtailed sig niﬁcantly in recent times since it provides no deposition rate advantage over SiHCl3 [3]. In general, it is desirable to choose the Si precursor which provides the highest deposition rate, at the cho sen deposition temperature, in order to maximize pro ductivity. If there are no temperature restrictions on the

10 Deposition rate (μm/min)

SiHCl3 SiH2Cl2

1 SiCl4 0.1

SiH4 Si2H6

0.01

Si3H8

0.001 1200°C1000°C 800°C 700°C 0.0001 0.65 0.85 1.05

600°C 1.25

1000/K (K–1)

Fig 6.3 ● Arrhenius plot for inorganic Si precursors.

CHAPTER 6

process, SiHCl3 is the obvious choice. Coincidentally, it is also the lowest cost Si precursor for epi. There is, however, a practical limitation to this rule. All commer cial epi reactors rotate the wafer support, referred to as a susceptor, in order to achieve acceptable ﬁlm uni formities by a superposition of the deposition proﬁles at various locations within the process chamber. Although there is no hard and fast rule, it is usually desirable to allow the susceptor to make at least 10 revolutions dur ing the deposition step. Thus a single wafer epi reac tor, with a rotation rate of 30 rpm, would suggest a minimum deposition time of around 20 seconds. At a growth rate of 4 μm/min a minimum epi thickness of about 1.5 μm is needed to achieve good ﬁlm uniformity with this precursor. The special case of epi-poly, where both monocrys talline and polycrystalline Si are to be deposited on a wafer, is discussed in greater detail in Section 6.2. Brieﬂy, SiH4 must be used, at least initially, in order to achieve a continuous ﬁlm over the dielectric regions. Epi layers having a thickness 1 μm often use a chlo rosilane (SiHCl3 or SiH2Cl2) following an initial growth with SiH4. The use of SiH2Cl2 as a precursor is usually limited to ﬁlms 2 μm in thickness. Such ﬁlms are common in bipolar and BiCMOS structures where reduced pressure (RP) processing is often required to control As autodop ing, or for selective epitaxy as described in Section 6.5. A comparison of the applicability of the various Si pre cursors is provided in Table 6.1. The choice of deposition temperature is usually imposed upon the epi process by structures (physical and/or doping) which are on the wafer prior to epi. The diffusion of dopants, particularly B and P, in the substrate may place a constraint on the upper temperature of the process. The choice of deposition temperature must then be made with respect to the overall process integra tion strategy. The presence of SiO2 on the wafer surface,

Table 6.1 Comparison of common precursors for Si epitaxy

Thickness range (μm)

Deposition temp. (°C)

Dep. rate range (mm/min)

Reduced press?

Selective epi?

SiGe epi?

Chamber coating

SiCl4

2–100

1150–1250

0.5–2

No

Rare

No

Lowest

SiHCl3

2–100

1050–1200

0.5–5

Rare

No

Rare

Low

SiH2Cl2

0.001–5

650–1100

0.001–2

Yes

Yes

Yes

Moderate

SiH4

0.001–2

500–1000

0.001–1

Yes

Yes

Yes

Signiﬁcant

Si2H6

0.001–0.5

400–800

0.001–0.2

Yes

Yes

Yes

Signiﬁcant

Si3H8

0.001–0.5

400–600

0.001–0.2

Yes

Yes

Yes

Signiﬁcant

91

PA R T I

Silicon as MEMS Material

typically found in selective epi processes or the epi-poly process, may put a constraint on the maximum H2 bake temperature, as discussed in Sections 6.2 and 6.5.

6.1.3 Choice of Doping Species

deposition. Finally, the substrate surface crystal orienta tion may also motivate the pressure of deposition. The growth of epitaxy over a substrate contain ing only B as the dopant species is best performed at atmospheric pressure (AP). Figure 6.4 shows the transi tion region for p-type epi deposited on a p (heavily B doped) substrate. The impact of temperature on the transition region for p epi on a p substrate is demonstrated in Figure 6.5. As the temperature increases, the vapor pressure of B, due to out-gassing from the substrate, also increases

B concentration (atoms/cm3)

Epitaxial layers are doped in-situ during the growth of the layer. The dopants used for epi are usually As or P, for n-type epi layers, and B for p-type epi. The gas phase species for these dopants are AsH3, PH3, B2H6 or, much less commonly, BCl3. The hydride doping spe cies are typically purchased in high pressure gas cylin ders containing 10–100 ppm of the hydride in H2. If 1020 T = 1100C exceptionally high concentrations of doping are neces P = 760 torr 19 sary in the epi layer these dopants can be purchased 10 SiHCl3= 12 g/min as pure components. However, concentrations in the Dep. rate = 4 μm/min range of 1–10% diluted with H2 or an inert gas are more 1018 common. The use of Sb as an n-type dopant in Si epi is excep 1017 tionally rare due to the poor stability (shelf life) of SbH3 and low vapor pressure of SbCl5. If BCl3 or 1016 SbCl5 is used as the doping source, a liquid-vapor deliv ery system (often referred to as a bubbler) is required 1015 Transition width ~ 0.35 μm where H2 or an inert carrier gas is passed through the pure component liquid and the resulting mixture of the 1014 dopant in H2 is delivered to the process chamber. The incorporation of n-type and p-type dopants as 1013 a function of temperature can be summarized as fol 0 1 2 3 lows: Under the conditions of ﬁxed deposition rate,

Depth (μm) ﬁxed pressure and ﬁxed doping species partial pres Fig 6.4 ● Transition region for p-epi on a p substrate.

sure, n-type doping incorporation decreases (resistivity increases) with increasing temperature while p-type

doping incorporation increases (resistivity decreases)

6 0.5 with increasing temperature. Increasing the deposition

Overall rate, at ﬁxed temperature and pressure, will result in a

Trans. Width decrease of n-type or p-type doping incorporation at a

5 ﬁxed partial pressure of the doping species. 0.4 The choice of doping species is almost always deter mined by the type of epi layer (p-type epi requires B)

4 and diffusion caused by subsequent processing of the

0.3 wafer (P diffuses faster than As). Thus, the epi engineer

rarely has any freedom of choice with regard to doping

3 species selection.

The choice of process pressure is most often based on structures present on or in the substrate. Control of autodoping, where dopants in the substrate impact the doping of the epi layer during the initial growth stages, is the primary motivator for process pressure choice. There are, however, two situations in MEMS where the nature of the epi deposition process motivates the choice of process pressure: selective epitaxy and epi-poly 92

3

Cl

2

Deposition rate (μm/min)

dep osi ti

on ra

te

T.W .a

0.2

SiH

6.1.4 Choosing an Operating Pressure

Transition width (μm)

t ra

te =

1μ

m/

mi

n

4

0.1

0 900

1

1000

1100

0 1200

Temperature (°C)

Fig 6.5 Transition width temperature dependence for p-epi on a p substrate. ●

Epi Wafers: Preparation and Properties

providing more available B for incorporation into the growing epitaxial layer and thereby increasing the transition width. As the deposition rate increases, the transition width is reduced due to the surface of the substrate rapidly becoming covered by the epi layer. Based on Figures 6.3 and 6.5, it can be seen that the deposition rate decreases, in the surface reaction rate limited region of the Arrhenius plot as the tempera ture decreases. The combination of B out-gassing and the change of deposition rate yields the resulting graph of transition width vs. temperature, as shown in Figure 6.5. The issue of B autodoping is critical to the success ful growth of high resistivity p-type epi layers over heav ily doped p-type regions such as etch stops discussed in Section 6.3.1. The issue with n-type dopants is more complex. Figure 6.6 compares AP processing with RP (reduced pressure) processing for n-epi deposited over a substrate with n As buried layers. The impact on vertical transition region and lat eral autodoping is clearly demonstrated. This effect is explained by the fact that the gas phase diffusion coef ﬁcient of the As, which out-gasses from the substrate, increases with decreasing pressure, thus providing a means for the As to diffuse away from the wafer sur face, thereby reducing the opportunity for incorpora tion into the epi layer. Thus, operating at RP (P 100 torr) during epi growth over substrates heavily doped with As, either as a buried layer or as the dopant in the substrate itself, is extremely valuable in controlling As autodoping.

1021 Epi

Substrate

1019 AP

1018

When P or B is used as a dopant in the substrate or buried layer, pressure has very little impact on autodop ing. This is due to the rapid solid phase diffusion coef ﬁcients of P and B, compared to that of As, which allow the surface to be replenished with P or B as they out gas from the substrate. In theory, Sb should behave similarly to As with respect to autodoping. However, due to the very low vapor pressure of Sb, the effect of pressure on transi tion region and lateral autodoping cannot be observed by spreading resistance analysis. The use of SIMS (sec ondary ion mass spectrometry) on very thin layers of undoped Si deposited over Sb buried layers does indeed conﬁrm that Sb and As behave similarly [3]. However, the impact of RP on Sb autodoping is only signiﬁcant for layers having thicknesses of 100 nm or so and is, therefore, not of interest for most MEMS applications. There exists a phenomenon known as pattern shift [1], which will cause a buried layer structure to appear at a different position on top of the epi layer than its actual location in the substrate. A diagram of this phe nomenon is provided in Figure 6.7 along with a graph depicting the impact of pressure on pattern shift for a substrate having a (111) surface orientation. This effect is caused by anisotropic etching and growth when a chlorosilane is used as the Si precursor. Substrates which have a surface orientation of (100) do not suffer from pattern shift due to the symmetry of the atomic structure. It should be noted that (100)-oriented sub strates may be cut off-orientation, usually in the direction of the (110) crystal plane. A small off-orientation of 1° or so will not result in a signiﬁcant amount of pattern shift. Larger amounts of off-orientation, say 10° or more, will result in a very observable pattern shift and may motivate the use of RP processing. Selective epitaxy is usually processed at RP (10–100

torr) in order to mitigate loading effects. Selective epi taxy is discussed in greater detail in Section 6.5. The epi-poly process, which is often used in MEMS structures, may need to operate at RP in order to adjust the relative thickness of the monocrystalline and

2

1017 RP

Pattern shift ratio

Doping concentration (atoms/cm3)

1020

1016 1015

1014

0

1

2 Depth (μm)

Fig 6.6 ● Vertical and lateral autodoping over an n As buried layer.

3

CHAPTER 6

1.5 1

Buried layer

Apparent position of b.l. after epi epi

SiHCl3

Si substrate

SiH2Cl2

0.5 0 –0.5 10

100

1000

Pressure (torr)

Fig 6.7 ● Pattern shift on a (111)-oriented substrate using chlorosilane Si precursors for epi.

93

Silicon as MEMS Material

The epi-poly process is used to deposit both mono crystalline and polycrystalline Si ﬁlms on the wafer. Epi (monocrystalline Si) will grow over the exposed Si regions while polysilicon will grow over a dielectric region (either SiO2 or Si3N4), as shown in Figure 6.8. In this application a chlorosilane cannot be used for deposition since the Cl atoms in the gas phase will result in discontinuous growth over the dielectric regions [4]. Thus, SiH4 is most often used as the Si precursor for thin (e.g., 2 μm) ﬁlms. The use of SiH4 for depositing thicker ﬁlms will often result in unacceptable coating of the fused silica process chamber enclosure. In order to deposit ﬁlms 2 μm in total thickness, an initial thin layer of Si (e.g., 0.5 μm or so) is grown from SiH4. The growth is then interrupted and the precursor is switched to chlorosilanes such as SiHCl3. This strategy allows much thicker layers of Si to be deposited with out excessive chamber coating and greatly improves the overall productivity of the process. The switch from one Si precursor to another occurs within the process recipe requiring less than one minute to affect this change. It is also possible to deposit a thin poly-Si or α Si layer over the dielectric in a low pressure chemical vapor deposition (LPCVD) furnace prior to depositing the epi-poly layer. A photolithography step and etch step to expose the monocrystalline Si region which will receive epitaxial growth must then follow this LPCVD process prior to epi. Using this strategy enables a chlo rosilane to be used throughout the entire epi-poly depo sition process, since exposed dielectric regions will not be present on the substrate surface. The presence of dielectric structures on the substrate surface may impose a constraint on H2 bake tempera ture, as discussed for selective epitaxy in Section 6.5. Further, if a certain grain size is required for the depos ited polysilicon region, a speciﬁc temperature will be necessary to achieve that grain size [4]. The impact of deposition temperature on as-deposited, undoped polysilicon grain size, is shown in Figure 6.9 for a total ﬁlm thickness of 200–300 nm.

250

200

150

100

Amorphous

6.2 The Epi-Poly Process

Due to the different crystalline structures of epi taxy and polysilicon, these two layers will often grow at different rates. At low temperatures (T800°C) it has been observed during Si and SiGe epitaxy that epi grows faster than polysilicon at AP [5]. As shown in Figure 6.10, pressure can be used to control this dif ference in order to achieve a polysilicon region thicker than the epi region or vice versa.

Poly-Si grain size (nm)

polycrystalline regions. The epi-poly process is discussed in greater detail in Section 6.2.

50

0 500

700

900

1100

Temperature (°C)

Fig 6.9 ● As deposited poly-Si grain size from SiH4 at AP.

1.5 Si Deposited from SiH4 at 700°C

Si Poly:Epi growth rate ratio

PA R T I

1.0

0.5 0

20

40

60

80

100

Pressure (torr)

Fig 6.8 Deposition of Si on a substrate with oxidized regions resulting in the epi-poly structure. ●

94

Fig 6.10 The impact of process pressure on the poly-Si:epi-Si growth rate ratio. ●

Epi Wafers: Preparation and Properties

6.3 Etch Stop Layers

There are two epi layer structures that are used as etch stops in MEMS applications. The most common method is the use of a very heavily B doped epi layer, as described in Section 6.3.1. A second method using pseudomorphic SiGe is described in Section 6.3.2. The choice of etch stop is dictated by the liquid phase chemistry to be used in the etch process.

6.3.1 Heavily Boron Doped Epitaxial Etch Stop Layers Extremely heavily B doped epitaxy, referred to as p

epi, is often used as an etch stop layer when KOH is used in a liquid phase etching solution [6]. An etch selectivity of 1000:1 is observed for Si doped with B at 1019 cm3 compared to a doping concentration of 1020 cm3, with the higher etch rate observed for the lower doped material [6]. Achieving such high doping concentrations is no small task. Although the solid solubility of B is approximately 1 1020 cm3 at 900°C increasing to 4 1020 cm3 at 1200°C [7] there are several issues which compli cate the process. Very high partial pressures of B2H6 are necessary in the process chamber in order to dope the epi layer to such high levels. Thus, a gas phase doping source of 1–10% B2H6 in H2 is commonly used. Safety concerns are paramount when using such a high concen tration source, since the TLV for B2H6 is 0.1ppm and the LC50 is 80°ppm/h [8] (cf. the TLV of BCl3 is 1ppm while the LC50 is 2541ppm/h, [9]. The decomposition of high concentration doping sources often results in B being deposited on the fused silica process chamber walls and is observed as black lines. These deposits do not etch signiﬁcantly in HCl, but will sublime if heated to very high temperatures (T 1200°C). Even so, it is not possible to clean the chamber adequately with an HCl etch or by sublima tion to allow high resistivity epi layers (ρ 50 Ω-cm) to be deposited with adequate control. Thus, the proc ess chamber used for p

etch stops is often dedicated to this heavily doped process and subsequent higher resistivity epi layers must be grown in a separate process chamber. Cleaning of the fused silica process chamber walls must be accomplished by an ex-situ liquid phase etch in an HF:HNO3 solution. The behavior of dopant incorporation with tempera ture, discussed in Section 6.1.3, suggests that a high deposition temperature and low deposition rate is ben eﬁcial for incorporating high concentrations of B in Si. This is indeed the case for p

epitaxy etch stop dep osition. Thus, deposition temperatures of 1150°C or

CHAPTER 6

more with reduced ﬂow rates of SiHCl3, to reduce the deposition rate, are used in these processes. Further, since incorporation of the dopant is roughly propor tional to the partial pressure in the gas phase, high total pressures of operation are desirable and, therefore, the process is carried out at AP. The B atom is very small compared to Si and, there fore, the large concentration of B in Si causes the p

epitaxial Si layer to have a smaller lattice constant than that of undoped or lightly B doped Si. As a result, a misﬁt dislocation matrix between the p

epi layer and the substrate beneath it will often be observed as shown in Figure 6.11 (Private comm. 2007, M. Tilli and V. M. Airaksinen). These line defects are present at the epi/substrate interface and may cause a corresponding surface rough ness on the top of the epi layer. The smaller lattice con stant of the epi layer on top of the substrate can also lead to bowing of the wafer. The misﬁt dislocation matrix and wafer bowing issues can be solved by counter doping the p

epi layer with Ge, which is a larger atom than that of Si. In theory, 5.6 atoms of Ge per atom of B are required in order to per fectly compensate for the effects of B [10]. Thus, a Ge atomic concentration of 2.2% is needed to compen sate for a B doping level of 2 1020 cm3.

6.3.2 Pseudomorphic Epitaxial SiGe Etch Stop Layers The use of pseudomorphic SiGe as an etch stop is typically driven by the need for very thin layers (e.g., 100 nm) after etching [11]. The KOH etch associated with p

etch stops is not sufﬁciently selective to allow etching to stop in time to achieve the desired

Fig 6.11 ● Misﬁt dislocation matrix with 10 μm of 1 mΩ-cm B doped Si Epi over a p- substrate [9].

95

Silicon as MEMS Material

PA R T I

the BOX of the as-implanted and annealed sub strate of 2 μm. Increasing this thickness to a total of 10 μm via epitaxial growth is a common requirement. Since the formation of a SIMOX substrate includes a 1250°C anneal, there are no fundamental temperature limitations to the epi process. Therefore, the SiHCl3 process outlined in Figure 6.1 is commonly used for this application.

layer thickness. Thus, other etch chemistries such as ethylene diamine pyrolcatechol can be used to achieve the desired post-etch layer thickness for BESOI struc tures [12]. Ge contents of 25–30% are required in order to achieve the needed etch selectivity for such structures. Strain in the SiGe layer is used to achieve etch selec tivity. The layer must be pseudomorphic and, therefore, very thin for high Ge content SiGe layers deposited on Si. Further, the deposition and all subsequent processes must be carried out at very low temperatures (e.g., T 700°C). The critical thickness for SiGe, calculated using the Matthews-Blakeslee methodology [13], is pre sented in Figure 6.12. The deposition of SiGe is usually performed at RP (100 torr). However, for substrates without dielectric features, it can be carried out at AP. Figure 6.13 demon strates the impact of Ge content of the ﬁlm on deposi tion rate and activation energy. Figure 6.14 shows the incorporation behavior of Ge as functions of Ge partial pressure and temperature. A detailed discussion of SiGe deposition is provided in Chapter 10 of reference [1].

100

Deposition rate (nm/min)

Si from SiH4 Ea = 1.6 eV

Ge from GeH4 Ea= 0.2 eV 10

SiGe, Ea = 1.0 eV PSiH4:PGeH4= 20

6.4 Epi on SOI Substrates Epi is commonly used to increase the thickness of Si above a BOX in SOI wafers used for MEMS. SIMOX substrates, often used in sensor applications such as accelerometers [14], have a Si layer thickness over

800°C 700°C 600°C 1 0.9 1.0 1.1 1.2 1000/T

500°C 1.3

1.4

(K–1)

Fig 6.13 Arrhenius plot of Si and SiGe deposition. ●

200

30 625°C

Ge content of SiGe alloy (%)

Critical thickness (nm)

150

100

50

20

700°C

10

SiGe layer thickness limit

0

0 0

20

40

60

80

100

Ge content (%)

Fig 6.12 SiGe layer critical thickness for pseudomorphic structure. ●

96

0

2

4

6

GeH4 partial pressure (mtorr)

Fig 6.14 ● Ge content of SiGe alloy as functions of the deposition temperature and PGeH4.

Epi Wafers: Preparation and Properties

6.5 Selective Epitaxy and Epitaxial Layer Overgrowth Selective epitaxial growth (SEG), where deposition occurs only on exposed Si regions and not on dielectric materials, is achieved by creating a competition between etching and deposition. This is accomplished by using SiH2Cl2 and HCl together during the deposition proc ess. The ratio of HCl:SiH2Cl2 required to achieve selectivity is a function of the deposition temperature and the dielectric material present on the substrate. Figure 6.15 presents the HCl:SiH2Cl2 ratio for selec tive growth in the presence of SiO2. If Si3N4 is present on the substrate higher HCl:SiH2Cl2 ratios are required and the net deposition rate is reduced. Selective epitaxy is processed at RP to reduce the impact of micro-loading effects. Figure 6.16 demon strates the impact of pressure on the SEG deposition rate on features with sizes varying from 1 μm 1 μm to 500 μm 500 μm. The mechanism behind the micro-loading effect is simply one of mass transport via gas phase diffusion. Large exposed Si areas consume more Si precursor than small areas to achieve a given thickness. At high pres sure, the Si precursor becomes depleted while the HCl and Cl etching species are enhanced due to decompo sition of the chlorinated Si precursor. This happens to a greater extent over the larger exposed Si areas than smaller areas. Further, at high pressure, the additional etching species generated by decomposition of the Si precursor cannot diffuse away from the surface as quickly as at lower pressures. There is also an impact on SEG deposition rate due to macro-loading effects. The macro-loading effect is

2 Cl 2

50

1

rat io

De po sit

ion rat e

75

0.5

HC

25

HCl:SiH2Cl2 ratio

1.5

l:S iH

Deposition rate (nm/min)

100

0 700

750

800

850

0 900

Temperature (°C)

Fig 6.15 ● Deposition rate and HCl:SiH2Cl2 gas phase ratio for SEG in the presence of SiO2 dielectric.

Selective epi thickness (nm)

Other more complex epi processes, such as epi over Al2O3, which was itself hetero-epitaxially deposited over a Si substrate, can be used to build unique struc tures [15]. The growth of Si on Al2O3 requires the use of a non-chlorinated Si precursor, since the presence

of Cl will remove Al from the material matrix. Thus, SiH4, processed at AP and a deposition temperature of 900–1000°C, would be the recommended methodology for ﬁlms 2 μm in thickness. If a substantially thicker Si epi layer is required, a chlorosilane can be used follow ing an initial deposition of 0.5 μm of Si from SiH4, as described in the epi-poly process in Section 6.2. It is convenient at this point to note that silicon on sapphire (SOS) is processed in the same manner, using r-plane Al2O3 substrates. Thus, the development of unique RF MEMS structures, which require high Q inductors in the device circuitry, are enabled through epitaxial technology on a sapphire substrate.

CHAPTER 6

100 90 80

760 torr

200 torr

70 100 torr 60

25 torr

50 1×1

5×5

10×10

100×100 500×500

Feature size (μm× μm)

Fig 6.16 ● Micro-loading effects during selective Si epitaxy 50.

caused by the amount of bare Si exposed on the sub strate surface relative to the fraction of the surface cov ered by dielectric. As an example, a substrate with 99% exposed Si will have a much lower overall SEG deposi tion rate than a substrate with only 1% exposed Si. Epitaxial layer overgrowth is a technique which exploits the characteristics of selective epitaxy and is shown diagrammatically in Figure 6.17. SEG Si grows only in the vertical direction until the ﬁrst atomic layer appears above the dielectric. Once this occurs, Si grows both vertically and horizontally. As a result, the region at the center of the dielectric will be thinner than the regions adjacent to the exposed Si regions. The presence of SiO2 regions among single crys tal regions, essential for selective epitaxial structures, may place a constraint on the maximum H2 bake tem perature used for surface preparation. This is due to undercutting of the oxide, as described by Eqs 6.1 and 6.2, in Section 6.1.1 at temperatures 900°C. A dia gram of oxide undercutting is shown in Figure 6.18. 97

PA R T I

Silicon as MEMS Material

Epi after growth

SiO2

Epi during growth

Si substrate

Fig 6.17 ● Epitaxial layer overgrowth during and after deposition.

Oxide undercutting from excessive H2 bake SiO2

Si substrate

Fig 6.18 ● Oxide undercutting of an SiO2 feature due to excessive hydrogen bake temperature.

It is important to recognize that even when Si3N4 regions are used as the dielectric on the substrate sur face, a “pad-oxide” of SiO2 lies beneath the Si3N4 and, therefore, undercutting may still occur.

6.6 Metrology A brief overview of metrology as it applies to epitaxial layers for measurements of thickness, resistivity and defect densities is provided in this section. For greater detail, please refer to Chapter 7 of reference [1] as well as Chapter 16 in Part III of this handbook.

6.6.1 Measurement of Si Epi Layer Thickness Epitaxial thickness measurements are most often per formed using the FTIR (Fourier Transform Infrared spectrometry) technique [16]. This method requires a structure where the epi layer has a relatively low doping concentration (Ndope 1018 cm3) and the region underlying the epi layer has a high doping concentration (Ndope 5 1018 cm3). The refractive index change of Si at high doping concentrations provides the reﬂec tion from the epi/substrate interface necessary for form ing the interferogram essential to this measurement. 98

Most epi layers grown over heavily n-type or p-type substrates meet the doping structural requirements for FTIR measurements of epi layer thickness. It is not necessary, however, that the entire substrate be heavily doped. Indeed, it is often possible to measure epi thick ness over a substrate which has discrete buried layer regions present, if the doping level and surface density of the buried layers is sufﬁcient to appear like a con tinuous region to the beam of incident IR radiation, which is typically 1 mm in diameter for commercial applications. The FTIR technique is capable of measuring epi ﬁlm thickness from 0.5 to over 100 μm. Exceptionally thin epi layers are often measured by spectroscopic ellip sometry [17] or SIMS [18]. Such techniques are rarely needed for MEMS applications, with the notable excep tion of SiGe, as discussed in Sections 6.3.2 and 6.6.3.

6.6.2 Measurement of Epi Layer Resistivity The measurement of resistivity, or doping concentra tion, in epitaxial layers is commonly performed using 4-point probe [19], capacitance-voltage (CV) [20], sur face potential [21] and spreading resistance proﬁling (SRP) [22]. In the extreme case of very thin ﬁlms, SIMS [18] can be used. The 4-point probe measurement does not determine resistivity directly but instead measures the sheet resist ance of the layer with which it is in contact. In order to extract the resistivity of the epi layer, knowledge of the layer thickness is required. The resistivity is then calcu lated by ρ(Ω cm) 104 × t epi × R s

(6.6)

where tepi is the epi layer thickness (μm) and Rs is the measured sheet resistance (Ω or Ω/square). Measurement of the epi layer sheet resistance requires that the underlying substrate be an insulator (e.g., SOI) or of the opposite resistivity type of that of the epi layer (p-type epi requires an n-type substrate and vice versa), where the p-n junction between the epi layer and the substrate electrically isolates the epi layer from the substrate. Often, a single epi layer thickness is used for calcu lating the on-wafer epi resistivity proﬁle. However, in order to accurately determine the epi resistivity proﬁle, the epi thickness at each point where the sheet resist ance is measured must be known. This creates a metrol ogy dilemma since epi thickness, measured by FTIR, must be measured over a heavily doped substrate, as discussed in Section 6.6.1. Further, the use of a heavily doped substrate of opposite type can result in grossly

Epi Wafers: Preparation and Properties

1. The epitaxial layer thickness required to achieve

a doping concentration change from 50% of the heavily doped substrate region to 2 times that of the epi layer. This method yields a 5 μm transition width in Figure 6.19. 2. The epitaxial layer thickness required to achieve

a doping concentration change of 3 orders of magnitude from the heavily doped substrate into the epi layer. This method results in a 2 μm transition width in Figure 6.19. 3. The epitaxial layer thickness required to achieve a

resistivity change from 2 times that of the heavily doped substrate region to 50% that of the epi layer. Note that this is not the same as technique 1 due to degenerate doping effects at high doping concentrations which lead to non-linearity in the doping concentration to resistivity relationship. This technique will result in a value slightly larger than that of method 1. SRP measurements are extremely useful since they can be performed directly on the product substrate. Precision of measurement is /–10% or so, and calibra tion to known standards is essential. The CV technique often uses a mercury (Hg) dot for formation of a Schottkey contact. This technique can be performed on either p or n-type epi layers, however the surface preparation technique for each is different.

1019

1018 Concentration (atoms/cm–3)

erroneous sheet resistance values if the epi layer is thin. This is due to autodoping from the substrate which will compensate the dopant in the epi layer. Thus, a lightly doped test wafer is commonly used for sheet resistance measurement by 4-point probe while epi thickness is measured over a heavily doped substrate. The 4-point probe technique is extremely precise com pared to other techniques discussed below. It is capable of providing repeatable measurements approaching /–0.1% over an extremely wide range of sheet resistances. Depth proﬁle resistivity information for the epi layer is often determined by SRP [22]. The SRP tech nique requires that a small sample be beveled, with the spreading resistance measured by two probes at differ ent positions along the bevel. The extraction of resis tivity from spreading resistance is dependent upon the structure. Thus, if a heavily doped region is immediately beneath the epi layer the algorithm is different from a lightly doped region, which is in-turn different from a region of different doping type [22]. Figure 6.19 shows the SRP of an n-type epi layer on an n substrate. Regrettably, there is no formal deﬁnition for the tran sition region from low to high resistivity (or from high to low doping concentration). However, three tech niques are commonly used.

CHAPTER 6

1017

1016

2 μm

1015 5 μm 1014 0

5

10

15

Depth (μm)

Fig 6.19 ● 20 Ω-cm n-epi layer on n Sb substrate.

P-type epi surface preparation can be achieved by simply allowing the substrate to oxidize in air for 1 hour after epitaxial deposition. Alternatively, the sub strate can be prepared by a wash in SC-1 [23] solution to motivate oxide formation. N-type epi layers often require that the substrate surface be exposed to a hot HNO3 solution for 1 hour and then rinsed prior to making the CV measurement. The CV measurement is limited by doping concen tration and thickness by avalanche breakdown and the requirement of a minimum of 3 Debye lengths of sepa ration from the surface. A plot of the accessible resistiv ity vs. thickness is shown in Figure 6.20. The CV measurement can often be applied to prod uct wafers. Epitaxial p-type on p substrates, or n-type on n substrates can be measured with a single frontside contact in conjunction with a contact on the back side of the substrate (all dielectric materials must be removed from the back of the substrate in order to achieve a low resistance backside contact). The meas urement of opposite types (i.e., p epi on an n substrate or vice versa) require a double front-side contact, since the p-n junction will electrically isolate the backside of the wafer from the region under measurement. Although the CV measurement is not strictly destructive, wafers exposed to the Hg probe are not likely to be returned to the production line out of fear of contamination. Measurement of epi layer resistivity by surface potential provides a noncontact technique applicable 99

Silicon as MEMS Material

PA R T I

imu ma cce ssib le d epth Max

10

Minim um a cc

Resistivity (Ω-cm)

essib le

depth

100

1 0.1

1

10

100

1000

Depth (μm)

Fig 6.20 ● Limits of depth accessible to CV analysis.

to product wafers [21]. A beam of photons is chopped to provide an alternating source of exciting radiation on the wafer surface. The measured surface photo-voltage is then related to the doping level of the Si near the surface. Details of the method are discussed in Refs [21] and [24]. The noncontact nature of this method makes the use of SPV, also referred to as AC-SPV or SCP, truly a unique, nondestructive method for resistiv ity measurement. The use of SIMS [18] for doping concentra tion determination is relegated to very thin layers, typically 100 nm. SIMS is an expensive technique, often costing US $ 1000 per measurement on an out source basis. Accuracy and precision of the measurement are in the order of / 10% at best, assuming a nearly religious adherence to calibration methodologies. The use of SIMS in MEMS applications is extremely rare.

6.6.3 Measurement of Ge in Si and SiGe Epi Layer Thickness The determination of Ge content in Si and SiGe epi taxial layer thickness can be accomplished by a number of different techniques. Rutherford Backscattering (RBS) [25], SIMS [18], spectroscopic ellipsometry [26], photoluminescence (PL) spectroscopy [27], scan ning Auger [28] and X-ray diffraction (XRD) [29] are commonly used. Of these techniques, RBS requires no standards or calibration and is, therefore, often used for

100

generating standards for the others. RBS is capable of providing both SiGe layer thickness and Ge composi tion information. The use of SIMS requires careful calibration to standards and, as previously noted, is an expensive tech nique. It does, however, provide the capability to deter mine depth proﬁle information for Ge content as well as B, P, As, C and O down to a limit of detection in the 1 1016 cm3 concentration range. Regrettably, not all of this information can be obtained in a single meas urement scan, since an O sputtering beam must be used for accurate B measurements and a Cs sputtering beam must be used for O determination. Spectroscopic ellipsometry has demonstrated a capa bility for measuring Ge content in Si and also SiGe layer thicknesses. The use of multi-angle multi-wavelength spectroscopic ellipsometry has been the most successful approach. Fixed-angle, single wavelength ellipsometry has shown some similar capability but does not appear to have a sufﬁcient number of degrees of freedom to yield unique solutions to the mathematical models needed for the independent determination of Ge con tent and SiGe thickness. The ellipsometry technique is considered to be nondestructive. Photoluminescence spectrometry is often carried out at low temperatures (e.g., 77 K or even 4 K) in order to achieve narrow well-deﬁned spectral peaks of high inten sity due to the small energy distribution of electrons at low temperature [30]. More recently, room tem perature PL has been demonstrated in order to make this technique applicable as an in-line analysis tool for semiconductor fabrication [31]. In general, the tech nique involves the optical excitation of carriers in the crystal lattice which are then allowed to recombine in the absence of photons. The resulting location of the spectral peaks, as well as the peak width is used to determine degree of strain, Ge composition and layer thickness. Scanning Auger is useful for the determination of Ge in Si over a concentration range of 5–100% Ge. It is primarily useful for high concentration Ge measure ments where RBS, SIMS, PL and scanning ellipsometry have difﬁculties. Double crystal XRD is a technique which measures the crystal lattice and can, therefore, be applied to Ge content in pseudomorphic SiGe ﬁlms. This technique is relatively fast, allowing a wafer to be proﬁled in less than 1 hour. Commercial tools are available for full wafer inspection and the technique is considered to be nondestructive. The reader is referred to Chapter 10 of reference [1], in addition to Refs [18] and [25] through [31], for further details regarding the measurement of Ge in Si and SiGe layer thickness.

Epi Wafers: Preparation and Properties

6.6.4

Defectivity Measurements

The most distinguishing characteristic of epitaxy over all other semiconductor manufacturing processes is that epi, like substrate manufacturing, is a single crys tal process. Thus, many defects which may occur during epi processing require inspection techniques outside the norm for other processes. Slip is the result of crystal plane movement caused by thermally induced mechanical stresses in a substrate during high-temperature processing. Figure 6.21 dem onstrates the geometric patterns of slip on (100) and (111)-oriented substrates. In extreme cases, slip can be observed by simply looking at a wafer with unaided eyesight. More com monly, wafers are inspected using phase contrast micro scopy (sometimes referred to as dark ﬁeld or Nomarski microscopy) [32], automated optical laser-based surface scanning tools [33] or x-ray analysis [34]. Stacking faults occur when a contaminant on the wafer surface interrupts the growth of a contiguous sin gle crystal layer and polysilicon islands, surrounded by single crystal silicon, are established. Figure 6.22 shows the types of geometries observed for stacking faults on (100) and (111) silicon. Stacking faults can be observed using phase contrast microscopy [32]. In the case where slip is very difﬁcult to observe, or stacking faults are very small (due to a thin epi layer) it can be desirable to decorate these defects with chemical etching prior to observation in a microscope. For (100)-oriented substrates the Secco [35], Schimmel [36] or Wright [37] etch chemistries may be used. Substrates having a (111) surface orientation require

(100) Si

(111) Si

Fig 6.21 ● Slip line geometries on (100) and (111) Si.

CHAPTER 6

the use of Sirtl [38] etch chemistry. Decorative etching is always a destructive technique. The reader is referred to an atlas of crystal defect micrographs [39] for a visual depiction of many macroscopic crystal defects. The measurement of metal contamination on the substrate surface may be accomplished through sev eral methods. For Fe, surface photovoltage [40], is a very sensitive technique which exploits the Fe-B bond energy in p-type Si. Other metals can be detected using a vapor phase decomposition (VPD) technique where the native oxide on the surface of the wafer is captured with a small amount of HF liquid, and the resulting liquid is then analyzed spectroscopically by TXRF or ICP-MS [41]. The measurement of particulate contamination on the substrate surface is accomplished using automated optical laser-based surface scanning tools [33]. Edge crown, shown diagrammatically in Figure 6.23, occurs when mass transport effects at the wafer edge in the epi deposition system cause increased epi growth rate at this area, compared to the rest of the wafer. Surface proﬁlometry, using either a stylus which contacts the wafer surface [42], or a non-contact opti cal proﬁlometer, are the most common methods for measuring edge crown [43]. Edge crown becomes a sig niﬁcant issue as the epi layer thickness increases and is usually only important for layers 10 μm in thickness.

6.7 Commercially Available Epitaxy Systems The choice of a single wafer or batch processing approach for epitaxy is a compromise between ﬁlm properties, productivity and cost. At ﬁrst blush one might expect that productivity and cost are nearly syn onymous. However, the yield to speciﬁcations for sin gle wafer process tools is often higher than batch tools, particularly when exceptionally unforgiving ﬁlm prop erties are speciﬁed. Further, some epi process tools can be purchased on a pre-owned basis for a much

Edge Crown Epi Layer

Si substrate

(100)

(111)

Fig 6. 22 ● Stacking fault geometries on (100) and (111) Si.

Fig 6.23 ● Edge crown formation often associated with thick (tepi 10 μm) epitaxial layers.

101

PA R T I

Silicon as MEMS Material

lower capital cost than a new tool, thus greatly reduc ing the cost-of-ownership (CoO) for processing due to a lower depreciation contribution compared to a new process tool. The reader is referred to the standard SEMATECH model for CoO [44] in order to compare the economics of various process tools. A comparison of process throughput between a sin gle wafer and batch process chamber is provided in Figure 6.24. As the epi layer thickness increases, the batch proc ess tool provides a higher productivity than single wafer processing. The crossover point is a very strong function of substrate diameter, as well as the details and require ments of the process. Thus, it is impossible to quantify this graph without a direct reference to a speciﬁc proc ess requirement and application. The following 2 exam ples illustrate the challenge between batch and single wafer process tool choices. A high-temperature process, for example, growing 20 μm of Si epi from SiHCl3 at 1100°C, would be car ried out at a deposition rate of 4 μm/min on a single wafer process tool, while a batch process tool would only be able to achieve 2 μm/min of deposition rate, due to mass transport limitations in the large batch process chamber. Further, the much larger thermal mass of the batch process tool would require substantially longer heat-up and cool-down times compared to sin gle wafer processing, as well as longer times for loading and unloading a batch of wafers, compared to only one wafer. On the other hand, the single wafer process tool would, by necessity, need to have the chamber etched

Throughput (wafers/hour)

Single wafer epi system

Batch epi system 150 mm substrates

Batch epi system 200 mm substrates

Epitaxial layer thickness (μm)

Fig 6.24 Comparison between batch and single wafer process tool productivities. ●

102

between each run, where the batch system may only need to be etched once every 100 μm or so (every 5 runs in this example). Obviously, the batch process tool has many more wafers present during the proc ess, but the precise number depends upon the design of the batch tool and the wafer diameter. Clearly, a ﬁnal answer cannot be found without at least specifying the details of the batch tool and the wafer diameter. Low temperature processes have both similar and different issues. A selective epi deposition at, say 800°C or less, would likely have similar deposition rates for both the batch and single wafer tools since the deposi tion would be reaction rate limited, not mass transport limited. However, this deposition rate will be quite low. Therefore even a 1 μm ﬁlm may require tens of min utes of deposition, providing an advantage for the batch tool. But the ﬁlm thickness is so thin that the single wafer tool would not require etching between each run. The issues of wafer diameter and batch load/unload time compared to single wafer processing still remain, as do heat-up and cool-down time. Based on these two abstract examples, neither thin epi low-temperature processes nor thick-epi hightemperature processes can be simply assigned to a single wafer or batch process tool. The details of the process speciﬁcations, wafer diameter and speciﬁc process tools available must be considered carefully in order to make the best choice.

6.7.1 Single Wafer Systems Commercial single wafer process tools for Si epitaxy ﬁrst became available in 1988 with the introduction of the Epsilon One from ASM Epitaxy [45], followed by the introduction of the Centura HT by Applied Materials in 1993 [46]. The development of an epi proc ess chamber around the requirements of a single wafer enabled unprecedented control of many issues suffered by batch process tools, most notably the control of slip as well as ﬁlm thickness and resistivity uniformities. On-wafer ﬁlm thickness and resistivity uniformities of 1 and 2%, respectively, are commonly achievable on 200 mm substrates. The basic design concept of the sin gle wafer epi process tool is shown in Figure 6.25. Single wafer process tools use a wafer holder, or sus ceptor, of very low thermal mass compared to batch processing systems. This allows much faster heating and cooling of the process chamber, which in turn greatly reduces the thermal budget of the process. The use of rapid thermal chemical vapor deposition (RTCVD) is essential for high productivity in such architectures. The process chambers used in RTCVD single wafer epi systems are very small in volume, which provide for a much higher mass transport capability compared to

Epi Wafers: Preparation and Properties

batch epi tools. Thus, substantially higher growth rates can be achieved in the mass transport limited regime, as much as 5 μm/min at 1150°C in a single wafer system compared to 2 μm/min in a batch process tool using SiHCl3. Further, autodoping from the substrate is less in single wafer systems due to the increased mass trans port allowing dopant species emanating from the sub strate to escape from the region adjacent to the growing epi layer. The use of a load-lock in conjunction with the proc ess chamber enables loading and unloading of the sub strate at high temperatures, typically in the range of 700°C to as much as 1000°C. The use of such high load/unload temperatures is critical to productivity as it reduces the heat-up time and, far more importantly, greatly reduces the cool-down time to unloading. Due to these high temperatures, and the environment in which the substrates are handled, all substrate load ing and unloading is automated. A very signiﬁcant sec ond beneﬁt of load-locked loading/unloading is that such a conﬁguration enables low-temperature epitaxy, by eliminating exposure of the process chamber to air. This allows the process chamber to maintain a very low background partial pressure of oxygen and water vapor, essential to the successful low-temperature processing of Si and SiGe. Finally, the low background water vapor partial pressure essentially eliminates stacking fault formation (other than oxygen induced related stack ing faults or OSF) since oxide free surfaces are easily achieved by hydrogen bake prior to epitaxy. The single wafer approach to epitaxy has become the work-horse of the Si and SiGe epi industries since the

CHAPTER 6

mid-1990s. However, as previously mentioned, it may not be the optimum choice for some epi processes due to economic and productivity concerns.

6.7.2 Batch Systems Epitaxial deposition systems using batch technology were the dominate methodology for substrate diame ters of 150 mm and less. To a ﬁrst order approximation, a batch epi reactor processes a ﬁxed area of Si (m2) per run, whereas a single wafer tool processes one wafer per run, regardless of substrate diameter. On a throughput basis, the batch process tool has an obvious advantage at smaller substrate diameters. The inductively heated pancake reactor, shown in Figure 6.26 [47], uses RF energy to heat the SiC coated susceptor via eddy currents. This design was hampered by the backside of the wafer being at a higher temper ature than the front-side, which resulted in bowing of the wafer and slip. Cutting a spherical proﬁle into the pockets where the wafers reside greatly reduced this problem. The radiantly heated barrel reactor in Figure 6.27 [48] further reduced the occurrence of slip by heating the substrates from the front using tungsten-halogen lamps. The inductively heated barrel reactor in Figure 6.28 [49] uses RF energy to heat the susceptor. In this design, the induced current ﬂows around the susceptor, unlike the RF pancake where the susceptor is heated by eddy currents.

N2 purged load-locks Fused silica bell jar N2 purged wafer xfr chamber

Wafer xfr robot

Process module

Process module

SiC coated graphite susceptor

Process module

Fig 6.25 Single wafer epi system architecture showing up to 3 process modules on an integrated tool. ●

Gas exit

Gas inlet

RF coils

Fig 6.26 ● The inductively heated “pancake.”

103

Silicon as MEMS Material

PA R T I Fused silica bell jar

Gas inlet

Wafer Waf er φ

Batch

100 mm 125 mm 150 mm 200 mm

>30 32 21 5

Fig 6.29 ● The PE2061S inductively heated barrel epi system from LPE Epitaxy. Used by permission. (Courtesy LPE) Lamps SiC coated graphite susceptor Gas exit

Fig 6.27 ● The radiantly heated “barrel.”

Gas inlet Fused silica bell jar

RF coils

Wafer φ 125 mm 150 mm 200 mm

Batch 10

8

5

Fig 6.30 ● The PE3061D inductively heated pancake epi system From LPE Epitaxy. Used by permission. (Courtesy LPE)

The PE2061S, shown in Figure 6.29 and PE3061D, shown in Figure 6.30, have claimed process capability approaching that of single wafer process tools [49, 50]. The CSD EpiPro-5000, shown in Figure 6.31, claims on-wafer thickness and resistivity uniformity capability of, nominally 1% and 2%, respectively, for processing on 150 mm substrates [51]. As noted previously, the best choice of epi process tool requires consideration of the technical require ments, as well as productivity and economic perform ance. A detailed assessment of what is required and what is desired is essential to realizing the optimal choice.

6.8 Summary Gas exit

SiC coated graphite susceptor

Fig 6.28 ● The inductively heated “barrel.”

104

Si epitaxy processing for MEMS applications is most

often performed at AP and high temperature using

Epi Wafers: Preparation and Properties

Fig 6.31 ● The EpiPro-5000 inductively heated pancake epi system from CSD Epitaxy. Used by permission. (Courtesy CSD)

SiHCl3 as the silicon precursor. Doping of the epi layer is accomplished in-situ using B from B2H6 for p-type

CHAPTER 6

epi and As or P from AsH3 or PH3, respectively, for n-type epi. Epi layers used for etch stops may be either heavily p-type doped, where NA 1020cm3, or pseudomor phic SiGe, with Ge contents of 30%. The choice of epi structure used for the etch stop is based on etch chemistry and the layer thickness required. The epi-poly process, where epi is deposited over single crystal Si and polysilicon is deposited over a die lectric region, is often used in MEMS structures. If the dielectric region is not covered with Si prior to deposi tion, the use of a non-chlorinated Si precursor, usually SiH4, is essential to successful processing. Selective epi can be used to grow Si only on exposed Si regions without deposition on adjacent dielectric areas. Epitaxial layer overgrowth is based on the selec tive epi process methodology and can be used to grow lateral monocrystalline silicon regions over dielectrics. Although single wafer epi systems dominate the Si semiconductor industry as a whole, batch epi systems still play an important role for MEMS. Thick epi lay ers require long deposition times and the CoO for sin gle wafer processing, compared with batch processing for thick epi layers, can far out-weigh the performance advantages of single wafer systems for cost sensitive, high volume commodity MEMS products. Hard, honest cost and technical performance evaluations are essential to choosing the correct epi system architecture.

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41. M., Beebe, Semiconductor International, online internet publication, http://www. semiconductor.net/article/ CA6446686.html?industryid47301, June 2007. 42. Alpha Step IQ Product Brochure, KLA-Tencor, One Technology Drive, Milpitas, CA, 95035, www.kla-tencor. com 43. HRP 240/340 Product Brochure, KLA-Tencor, One Technology Drive, Milpitas, CA, 95035, www.kla-tencor. com 44. W. Trybula, Microelectron. Eng. 83

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7

Chapter Seven

Thick-Film SOI Wafers: Preparation and Properties Jari Mäkinen Okmetic Oyj, Vantaa, Finland

7.1 Introduction

Silicon-on-insulator (SOI) is a semiconductor structure consisting of a layer of single crystalline silicon separated from the bulk substrate by a thin layer of insulator. In SOI wafers the insulator is almost invariably a thermal silicon oxide (SiO2) layer, and the substrate is a silicon wafer. Depending on the type of application, the silicon ﬁlm can be very thin (50 nm for fully depleted transis tors), or it can be tens of micrometers thick. Likewise, the buried oxide thickness ranges from tens of nanom eters to several micrometers. Manufacturing methods of wafers vary accordingly. Silicon-on-sapphire (SOS) is another SOI technology that has some further advan tages for fabrication of CMOS circuitry in microwave applications because of the low-loss dielectric substrate. The SOI structure was created for the ﬁrst time using silicon on sapphire. SOI technology (here referring to forming the SOI structure on a silicon wafer) was devel oped during the 1980s for high-frequency and radiationhard circuit applications [1]. The concept was quickly adopted for the manufacture of pressure sensors [2] and acceleration sensors, and it is now widely accepted as a basic technique for fabrication of sensor elements. Thin SOI wafers for mainstream CMOS applications as well as thick-ﬁlm SOI wafers typically used for microelectro mechanical systems (MEMS) applications are commer cially available from several silicon wafer manufacturers. SOI layer thickness of 1 μm and above is classiﬁed as thick-ﬁlm SOI. Device types using thick SOI include bipolar devices, high voltage and smart power applica tions, and MEMS. Because of the thick SOI and buried

oxide layers, the wafers are generally fabricated by direct wafer bonding. MEMS processes that use thickﬁlm SOI wafers as a substrate have greatly beneﬁtted from the development of the deep reactive ion etch ing (DRIE) techniques, which enable etching of deep, high-aspect-ratio structures. Fundamentally, they com bine typical features of surface micromachining such as comb-like structures and thick device layers of bulk micromachining, enabling sensor elements with small lateral dimensions. Especially when combined with DRIE technology, thick-ﬁlm bonded SOI wafers bridge nearly the entire range of microstructure thicknesses between the conventional surface and bulk microma chining techniques, using only single-crystalline silicon as mechanical material. The technology is not limited by the crystal planes since the SOI layer is patterned with dry etching that is not affected by the crystal ori entation. The mechanical layer is originally from a bulk silicon wafer; therefore it is relatively free of mechani cal stresses. Moreover, the mechanical properties of single crystalline silicon are consistent, and they do not depend on processing of the wafers. In this review the methods of manufacturing bonded thick-ﬁlm SOI wafers used in MEMS applications are described, and typical properties of wafers are sum marized, focusing on data from large-series production of wafers. Emphasis is on the approach that relies on mechanical back-grinding and optical precision polish ing for ﬁnal thinning of the SOI ﬁlm. A comprehensive discussion of semiconductor wafer bonding technology and applications can be found in Refs [3–5], and with a historical perspective in Ref. [6].

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7.2 Overview of SOI

In the following paragraphs an overview of SOI technol ogies with emphasis on MEMS applications is given.

7.2.1 SOI Technologies The interest in SOI wafers for integrated circuits came from the intrinsic performance advantages including high speed, low dynamic power consumption, and sup pression of the parasitic bipolar latch-up effects. At a ﬁxed operating voltage, circuit speed is up to 30% faster and the power consumption can be reduced by a fac tor of three compared with what one can achieve with a standard bulk silicon or epitaxial silicon substrate. The relative advantage over bulk silicon grows even bigger when low operating voltages are used. These advantages are due to two main features, the greatly reduced para sitic junction capacitance and the complete dielectric isolation of individual transistor elements. With sup pressed latch-up it becomes easier to reduce the transis tor size and to increase the packing density. Today SOI is a mainstream CMOS technology with the roadmap (International Technology Roadmap for Semiconductors [ITRS]) for SOI wafers, and with 300-mm diameter wafers for sub-65-nm technology. An exhaustive review on the use of thin SOI material for VLSI CMOS tech nology can be found in Refs [7] and [8]. Historically, several manufacturing techniques were proposed for producing SOI structures. The key chal lenge was to produce a high-quality single crystalline silicon ﬁlm of device grade on top of silicon oxide. The early techniques included zone-melt recrystallization (ZMR) techniques. In ZMR the substrate is a silicon wafer that is thermally oxidized, and the oxide is pat terned to form openings through which the silicon sur face is exposed. A thin, amorphous or polycrystalline silicon layer is deposited on the surface and melted. When the layer solidiﬁes, a single crystal growth is initi ated at the silicon surface. Epitaxial growth is seeded by the substrate, and the growth proceeds laterally from the openings until the lateral growths meet to form a contin uous layer. Epitaxial lateral overgrowth (ELO) relies on a similar kind of approach of growing epitaxial silicon lat erally on a thermal oxide layer with openings to seed the single crystalline growth. It was overly difﬁcult using any of the early techniques to reach the yield and reliability needed for large-series production of wafers. The industry has settled on two manufacturing meth ods. The ﬁrst is SIMOX (Separation by Implantation of Oxygen), and the other is bonded silicon on insulator (BSOI). Both technologies provide the capability of preparing a thin, dielectrically isolated silicon ﬁlm over a large-diameter silicon wafer. In SIMOX, the buried 108

oxide layer is formed by high-dose oxygen ion implanta tion into a silicon wafer. At a sufﬁciently high dose the implanted oxygen atoms can produce a stoichiometric silicon oxide (SiO2) layer. The structure resulting from oxygen implantation strongly depends on the dose and the implant ion energy. During implantation the wafer is kept at the temperature of 400–600°C to anneal the crystal defects and to prevent the crystalline to amor phous transition of silicon. In the subsequent high temperature annealing step, which takes place around 1350°C, most crystal defects are annealed; small oxy gen precipitates dissolve, leaving only the buried oxide layer, and the interface between the buried oxide and silicon becomes planar. The original standard-dose SIMOX material was produced with an oxygen dose of 2 1018 cm2, yielding a 200-nm thick silicon layer and a 400-nm thick BOX layer. The defect density of early SIMOX wafers in excess of 1 109 cm2 was very high. More recent processes combine multiple low-dose implantation and annealing steps, and use the internal oxidation process in order to produce material with thinner BOX and superﬁcial silicon layers, to reduce the defect density in the top silicon layer and to increase the manufacturing throughput [9]. Wafer bonding techniques include the bonding and etch-back SOI (BESOI), Smart Cut, and Epitaxial Layer Transfer (ELTRAN) processes. In all these approaches the process starts with two silicon wafers bonded together. The major difference lies in thin ning of the structure until the top wafer is reduced to its target thickness. A straightforward approach relies on back-grinding and precision polishing of one of the wafers. This method is much applied to thick-ﬁlm SOI wafers for MEMS applications, and it will be discussed in detail. In the bonding and etch-back technique a selective chemical etch is applied. A highly doped p-type ( p

) epitaxial silicon layer is used as an etch stop. A second n- or p-type epitaxial silicon layer that will ultimately form the SOI layer is grown on top of the ﬁrst p

epitaxial layer. This technology attracted attention because of its high crystal quality compared with early SIMOX wafers that were developed around the same time. The newer thin-ﬁlm technologies, Smart Cut and ELTRAN, developed independently at about the same time. The Smart Cut technique uses hydro gen implantation and wafer bonding, followed by split ting of a thin layer along the hydrogen implantation line. It is applied for large-scale manufacturing of thin-ﬁlm SOI wafers for the mainstream CMOS processes. The ELTRAN process was developed by Canon. In its origi nal form it was a bonding and etch-back type of process making use of the extremely high etch rate of porous silicon; later on the process was developed to enable splitting of the bonded wafer pair through the porous silicon layer.

Thick-Film SOI Wafers: Preparation and Properties

Applications can be broadly divided into two areas, CMOS and bipolar devices. This division is seen in the types of SOI wafers used. Thin-ﬁlm SOI wafers suitable for low-power, low-voltage, high-speed CMOS applica tions are limited to SIMOX and Smart Cut methods because of the thickness uniformity requirements. SOI wafers with a 50–80-nm thick silicon layer on 100–140 nm buried oxide are in large-scale production. Typical thickness uniformity requirement is 5% or better. Bipolar applications use thicker SOI in the range of 1–2 μm and above. Thick-ﬁlm SOI can be produced by the BESOI method or, in the higher thickness range, by the back-grinding and polishing method. Starting from an SOI wafer prepared by one of the thin-ﬁlm processes and growing an epitaxial silicon layer is another option to increase the SOI layer thickness.

7.2.2 Processing of Mechanical Devices on SOI Quite apart from the electronic applications, where the dielectric isolation of transistors is the primary advan tage, SOI technology has found applications in MEMS. It provides a precise control of several material param eters and enables unique device conﬁgurations that are not easy to make otherwise. A simpliﬁed process for fabrication of micromechanical devices on thick-ﬁlm SOI wafer using DRIE is illustrated in Figure 7.1. The SOI layer is etched from the front face of the wafer

Figure 7.1 ● A simpliﬁed process of MEMS fabrication on an SOI wafer by DRIE with only one mask level, modiﬁed from Ref. [10]. The SOI layer is thick, most commonly from 4 to 100 μm. The buried oxide (thermal SiO2) layer acts as an etch stop for DRIE because of the high selectivity that can be achieved to silicon etches, and it conﬁnes the isotropic HF release etch.

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with DRIE retaining near-vertical sidewalls. The bur ied silicon oxide acts as an effective etch stop for the anisotropic dry etch. After plasma stripping of the pho toresist, HF etching of the buried oxide layer is used to release the mechanical structures. Selective etching of thermal oxide conﬁnes the isotropic release etch to the oxide layer. Basically very few mask levels are needed to fabricate working devices. Figure 7.2 shows an example of such a micromechanical element on a 20-μm thick SOI ﬁlm. It is a detail of a bulk acoustic mode resonator showing the narrow gap for electromechanical coupling. The structures were etched using high-aspect-ratio reactive ion etching to form the 0.5-μm wide gap with an aspect ratio of 40:1. The buried oxide was etched away via the openings in the device layer to release the mechanical structures. Buried oxide is also used for mechanical anchoring of the ﬁxed structures, and it pro vides electrical isolation. SOI wafers for MEMS are nearly always fabricated by wafer bonding. Figure 7.3 shows a sampling of silicon ﬁlm and buried oxide thicknesses based on a large number of SOI wafer speciﬁcations for MEMS applications. For all practical purposes the SOI ﬁlm thickness varies from 4 to 200 μm. The most common range in this sample is from 5 to 20 μm, but in nearly half of the applications the SOI layer is thicker than 20 μm. The buried oxide thickness is typically from 500 nm to 2 μm. In bonded silicon the thickness of the insulating material can be independently determined prior to the bonding process. This is valid for all wafer bonding techniques discussed above. Of the

Figure 7.2 ● A detail of a bulk acoustic mode resonator showing the narrow gap for electromechanical coupling. The SOI layer is 20 μm thick and the gap is 0.5 μm in width. The structure was fabricated with DRIE using the buried oxide for etch stop and for release etching of the laterally moving parts. Source: Courtesy of J. Kiihamäki, Micronova, VTT.

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Figure 7.3 ● (a) SOI layer and (b) buried oxide thicknesses in bonded SOI wafers for MEMS use. Data are based on a large number of SOI wafer speciﬁcations covering a wide range of microsystem applications.

different manufacturing techniques, back-grinding and polishing can readily produce thick-ﬁlm SOI in this range. A characteristic property of the mechanical thin ning process is that the thickness variation of the SOI ﬁlm is not correlated to the ﬁlm thickness. For the low est thickness range the silicon ﬁlm can be realized also by starting with thin-ﬁlm SOI and then growing a layer of epitaxial silicon. As the thickness increases, the cost of growing thicker epitaxial layers becomes prohibitive and, in addition, the thickness uniformity becomes worse. Use of SIMOX wafers is very limited because of the maxi mum buried oxide thickness around 400 nm, which is thin for the majority of MEMS designs and processes. As a result, the bond, grind-back, and polish type of thickﬁlm SOI wafers are prevailing in MEMS use. This summary does not permit detailing MEMS devices based on bonded SOI wafer technology. Numerous examples can be readily found from the liter ature. Instead, a few examples demonstrating the ways of using the SOI structure in processing of microsystems are given below. 110

MEMS fabrication on thick-ﬁlm SOI substrates has greatly beneﬁtted from the development of mod ern plasma etching techniques for DRIE of silicon. The most commonly applied method of deep silicon dry etching is the Bosch process [11], which relies on switching between two plasmas, one for isotropic etch ing of Si (SF6) and one for deposition of a ﬂuorocarbon polymeric layer for passivation (C4F8). It allows etching of vertical sidewalls at geometries that are controlled by standard photolithography masks, which is a key to a high-aspect-ratio microstructure technology. Compared to wet etching of silicon, more accurate dimensional control is available when using DRIE, which also allows the overall dimensions of MEMS devices to shrink. The etch depth control is more challenging in DRIE process ing than, for example, in anisotropic wet etching. In optimum conditions it is possible to achieve 0.1% uni formity over the wafer in wet etching, but in DRIE etching 1% uniformity is difﬁcult to achieve with largeseries production processes. Standard values are in the range of /1… /2.5%, and in addition the etch rate depends on the aspect ratios. The buried oxide of an SOI substrate can be used as etch-stop because the silicon oxide selectivity is over 100:1 in ﬂuorine-based plasmas used for silicon etching. The SOI device layer uniformity then practically deﬁnes the etch depth. DRIE to the buried oxide layer leads to charging of the oxide in the bottom of the trench by accumulation of the positive ions. Charging causes sideways etching of silicon near the interface and notches are formed. Toolwise the problem has been solved by pulsing of the RF bias as the buried oxide layer is approached to allow for time to discharge the oxide surface. Interestingly, horizontal etching by the notching effect has also been employed to release etching of comb-like structures in SOI wafers [12]. The ﬁrst example is a silicon micromechanical resonator for RF applications (Figure 7.4) demonstrating release of large mechanical structures [13]. It is a two-dimensional bulk-acoustic-wave resonator with a 10-μm thick resona tor plate with dimensions 320μm 320μm. The compo nent was made on thick-ﬁlm SOI wafer using DRIE. The resonator plate was released by HF etching of the buried oxide ﬁlm through 1.5-μm diameter holes arranged in a square matrix to perforate the resonator plate. Another example demonstrates the use of the buried oxide as an etch stop and sacriﬁcial layer to form vacuum cavities in SOI wafer [14]. It uses a standard thick-ﬁlm SOI wafer as a starting material. The vacuum cavities are formed by ﬁrst etching an array of micrometer-sized openings through the device layer by DRIE using BOX as etch-stop. A conformal permeable polysilicon ﬁlm is deposited over the surface. The buried oxide layer is locally removed by HF etching through the pinholes inherent in the thin polysilicon ﬁlm. The openings are

Thick-Film SOI Wafers: Preparation and Properties

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Figure 7.4 ● A silicon micromechanical bulk resonator made on SOI wafer using DRIE. The resonator plate dimensions are 320 μm 320 μm, and SOI ﬁlm thickness is 10 μm. The HF release etching was done through 1.5-μm diameter holes (detail on the resonator plate on right) arranged in a square matrix to perforate the resonator plate [13]. Source: Courtesy of J. Kiihamäki, Micronova, VTT.

then reﬁlled with low-pressure chemical-vapor-deposited (LPCVD) polysilicon, leaving the cavities in low vacuum. After etch-back, a single crystal silicon surface is revealed. The top view infrared photograph of a cavity structure in Figure 7.5 shows the etched and sealed hex agonal cavity as well as the plugs to close the openings that were used for buried oxide etching. The “plug-up” approach provides several attractive features. It forms a vacuum cavity on wafer level, for example, for pressure sensors with internal pressure depending on the closing proc ess. Risk of damage to metallization by HF release etch ing is eliminated, and no lithography over high surface topography is needed. The process uses IC-compatible process steps only, and monolithic integration with CMOS is possible. The approach was demonstrated for making a CMOS integrated pressure sensor [15]. Two further examples include a very high-aspect-ratio structure etched in a thick-bonded SOI layer, sharing features both from surface and bulk micromachining, and a buried cavity etched into silicon under a silicon diaphragm [16, 17]. DRIE provides a way of processing similar comb-drive devices with ﬁnger capacitors that are frequently used in surface micromachining for accel eration sensors or gyroscopes with capacitive readout but using much thicker active layers. Today’s processes make possible etching through a 100-μm SOI layer with a 4-μm gap in large-series sensor element fabrication, implying a 25:1 aspect ratio. This approach provides a high moving proof mass and high capacitance generated from the large area of the vertical sidewalls of the ﬁnger capacitors with highly stable capacitive detection. A buried cavity under a silicon diaphragm is illus trated in Figure 7.6. This has been a primary applica tion of direct bonding in fabrication of MEMS devices [16], but it has more recently been integrated also into the thick-ﬁlm SOI wafer manufacturing process. To

Figure 7.5 ● Top view near infrared micrograph of a hexagonal buried cavity that is formed by HF-etching the buried oxide in an SOI wafer through thin permeable polysilicon ﬁlm that is grown in micrometer-sized openings etched through the device layer. After etching the buried oxide is complete, the holes in the structure layer are ﬁlled with low-pressure CVD polysilicon (see text). The dark ring indicates that the silicon membrane above the cavity is deﬂected by the ambient pressure [14]. Source: Courtesy of J. Kiihamäki, Micronova, VTT.

form a buried cavity under a single crystalline silicon diaphragm, a cavity is ﬁrst etched in the handle silicon wafer. A second wafer is bonded to the cavity wafer and thinned using any of the techniques described later in this section, including mechanical grinding and pol ishing or selective etching. After intermediate proc ess steps, which can also include integration of bipolar or CMOS circuitry, the mechanical structures can be released by dry etching at the very end of the process. The physical dimensions in this process can be varied over a wide range, and they can be controlled with high accuracy. This approach provides several attractive fea tures including release of the mechanical structure at 111

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process times that are not practical when growing very thick thermal oxides. BESOI wafers or thick-ﬁlm SOI wafers based on mechanical thinning of the device layer are fabricated in three basic process steps: 1. Formation of the device layer. When the thinning process is based on nonselective chemical– mechanical polishing, a bare polished silicon wafer is used. In BESOI wafers the etch-stop can be formed by ion implantation or more commonly by silicon epitaxy by growing a two-layer epi structure. 2. Direct bonding of the polished face of the device

wafer with another silicon wafer with thermal oxide, and annealing the wafer pair. The bonded wafer consists of the handle silicon wafer, thermal SiO2 layer, and the device wafer. 3. Thinning down the device layer employing the Figure 7.6 ● A sequence of process steps to form buried cavities under silicon diaphragm by wafer bonding. Cavities are etched by DRIE in the handle silicon wafer and the wafer is bonded to a second wafer (a). The second wafer is thinned using any of the techniques applied in standard bonded SOI wafer manufacturing, such as mechanical grinding and polishing or selective etching (b). The mechanical layer is patterned with dry silicon etching, which releases the mechanical devices (c). Between steps (b) and (c), for example, implantation to form piezoresistors, metallization, or integration of CMOS circuitry can be performed.

the very end of the process with no sacriﬁcial etching, and suppression of electrical and mechanical interaction between the moving microstructures and the substrate. The remainder of this chapter will describe fabrica tion methods for bonded SOI wafers and basic proper ties of wafers, concentrating on thick-ﬁlm SOI wafers.

7.3 Silicon Wafer Parameters for Direct Bonding Bonded SOI wafers are composed of two silicon wafers bonded face-to-face with a buried oxide layer. One can choose the SOI parameters quite freely as the manufac turing process allows a wide range of independent wafer parameter values. The type, thickness, resistivity, and crystal orientation of the SOI layer are independent of those of the handle silicon wafer. The oxide is formed by thermal oxidation before the wafer bonding step, and the thickness of the oxide can be selected according to the considerations of the design of the MEMS device or its fabrication process. The limits to the buried oxide thickness are associated with hydrogen-related voids in the case of very thin oxides (thickness 100 nm) or 112

back-grinding and polishing or selective etching techniques. In this section the factors that inﬂuence direct wafer bonding are discussed; the different techniques for thin ning the device layer are presented in the following sec tions. The requirements for direct wafer bonding are similar for all BSOI wafer manufacturing processes. The ﬁrst reports of direct bonding of polished silicon wafers without an external force such as hydrostatic pressure or electric ﬁeld were reported in 1985–1986 by Lasky [18] and Shimbo and colleagues [19]. In bonded SOI wafer fabrication the bonding is nearly always between two hydrophilic silicon or thermal sili con oxide surfaces. The contacting force is caused by attraction between OH-groups and water molecules on the hydrophilic surfaces, and hydrogen-bridge bonds between the adsorbed water molecules across the two wafer surfaces can form. Once initiated, the bonding area or wave spreads across the entire surface of the sili con wafers. The process is sensitive to the properties of the silicon wafers, and success of direct bonding depends on the ﬂatness of the wafers, quality of the wafer sur face, and the wafer cleaning process. Mirror-polished silicon wafers used in the semiconductor industry today meet such requirements for reasons not associated with direct wafer bonding. The approach based on thinning by mechanical back-grinding and polishing starts from prime polished silicon wafers. The other techniques (BESOI, Smart Cut, or ELTRAN) need additional processing steps such as silicon epitaxy or ion implan tation before bonding the wafers, and those processes must be designed to meet the requirements of direct bonding. The fact that silicon wafers are thin also works in favor of direct bonding, making the requirements less stringent than in the case of bonding thick bulk parts. The direct bonding process requires that tight ﬂatness and roughness tolerances are maintained on the

Thick-Film SOI Wafers: Preparation and Properties

wafers. Macroscopic wafer scale geometry variation such as wafer bow and wafer ﬂatness deviations are accommo dated by elastic deformation of the silicon wafers. Effects of wafer shape on direct bonding have been predicted by comparing the reduction of the total surface energy to the increase of the elastic strain energy accumulated in the bonded wafers [20–22]. The requirement for direct bonding is set by the work of adhesion (energy available per unit area to bond to silicon surface W 2γ, where γ is the surface energy of silicon) that must be sufﬁcient to overcome the increase of the elastic strain energy. Turner and Spearing [22] gave the criterion for direct bonding as (dU/dA)W, where U is the elastic energy accumulated in the wafers, A is the area of the bonded interface, and W is the work of adhesion. This relationship says that the bond front will spread as long as the change in the strain energy per unit area is smaller than the work of adhesion. The quantity dU/dA is a function of the geometry of the wafers and the elastic properties of silicon, whereas W is determined by the type of the two bonding surfaces. One problem in correlating the models with the wafer shape is that the standard measurements of the wafer geometry, such as the total thickness variation (TTV), bow, and warp usually do not give information on the length scale of the variation. Turner and Spearing [22] used their model to predict the effect of wafer bow on direct bonding of blank silicon wafers. For one thing it showed that if bonding begins, the bonding area will advance to the edge of the wafer pair. The other important point to note is the strong dependence on the wafer thickness, which was explicitly noted also in the work of Tong and Gösele [21]. The wafer diam eter does not affect wafer bonding assuming identical wafer thicknesses and curvature of the wafers. In prac tice the effect of wafer diameter comes from standard wafer thickness, which correlates to the wafer size and increases with the wafer diameter. Finally, a speciﬁc case of 100-mm-diameter silicon wafers implies that for a thin wafer (thickness ≤500 μm) the bow can be sev eral tens of micrometers without being an obstacle to direct bonding. Like the bow of the wafer, gaps arising from the TTV of the wafers can be quite easily closed up by the elastic deformation assuming hydrophilic sili con surfaces. Conventional silicon polishing methods can produce wafer ﬂatness in the range of 2–3 μm or smaller, and with the double-side polishing techniques the standard process capability for TTV is 1.0 μm. In grind-back and polish SOI or BESOI wafer manufac turing the device wafer is removed apart from the thin silicon layer sitting on top of the silicon oxide ﬁlm, and one can start with 500-μm-thick device wafers even in the case of a 200-mm wafer diameter. Such wafers can quite easily accommodate the surface ﬂatness variation of a few micrometers by elastic deformation in wafer bonding.

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In addition to the wafer geometry, surface nanoto pography is the other ﬂatness parameter that inﬂuences direct wafer bonding and is accommodated through elastic deformation of the wafers. It measures the sur face topography on a length scale of fractions of a mil limeter to approximately 10–20 mm, and typically has peak-to-valley heights of nanometers or tens of nanome ters. The amplitude and pattern of surface nanotopogra phy is to a large extent deﬁned by the type of polishing (single-sided or double-sided) and the details of the polishing process. In single-side polishing, because of the wax mounting of the wafers, the topography of the etched back surface of the wafer and the ceramic carrier are transmitted to the polished front surface. In a dou ble-side polishing process the wafer is ﬂoating, which basically yields signiﬁcantly lower surface topography. In semiconductor device manufacturing, surface topog raphy can result in variation of the thickness of dielec tric ﬁlms after CMP polishing, with a potential negative effect on the circuit performance and the process yield, and in the latest generations of devices wafer ﬂatness control requires the control of topographical features at the nanometer scale. Turner et al. [23] estimated the effect of surface nan otopography on direct bonding by comparing the elastic strain energy to the work of adhesion. The conclusion was that such topographical features have only a very small effect on bonding of hydrophilic silicon surfaces, and that such variations are easily accommodated by elastic deformation of the wafers. The change of strain energy is small compared even with typical work of adhesion values of 10–20 mJ/m2 reported for direct bonding of hydrophobic silicon surfaces. Compared with typical wafer scale shape variations induced by the TTV or wafer bow, surface nanotopography leads to much smaller values of accumulated elastic strain energy in direct wafer bonding. Clearly, standard polishing proc esses yield silicon wafers with surface nanotopographical features that are unlikely to cause bonding failures. The wafer-bonding-induced local elastic strain in bonded wafers arising from surface nanotopography can be imaged using X-ray topography [24, 25]. X-ray topog raphy of the bonded interface exhibits a roughness-like image of periodic strain contrast. The length scale in the strain pattern resulting from elastic strain qualita tively corresponds to the surface topography. Most of the deformation occurs already during direct bonding of wafers at room temperature, and the high temperature annealing has little inﬂuence on the local stress or the strain pattern. The residual stresses induced by surface nanotopography have been detected and measured also by the infrared grey-ﬁeld polariscope (IR-GFP) [26]. It utilizes transmission of circularly polarized infrared light and measures optical interference generated by stress-induced birefringence. In the presence of stress, 113

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transmitted light becomes elliptically polarized, and change in polarization depends on the applied shear stress. Figure 7.7 shows a shear stress image of a bonded silicon wafer from IR-GFP. It reveals the character istic stress contrast pattern that is related to the sur face topography. The contrast pattern does not appear in the area of the large void of Figure 7.7a that is not bonded, indicating that the residual stress across the noncontacted area is constant. No local stress variation is expected, as there is no surface-topography-induced deformation of the wafer in the area of a void.

Another parameter critical to direct wafer bonding is the surface roughness. It is usually quantiﬁed by local microscopic roughness in very small wavelengths of less than 10 μm and is typically measured using atomic force microscopy (AFM). In this regime wafer bonding capa bility can no longer be characterized by a single parame ter, such as work of adhesion, which describes the initial bonding for wafer deformations signiﬁcantly larger than 1 nm. For known material properties and surface adhe sion force the critical surface roughness at which direct bonding of two pieces will become possible has been estimated using a statistical surface roughness model [27], and an empirical correlation between bonding of silicon wafer surfaces and the roughness spectrum from AFM has been established [28]. An experimental analysis shows a strong correlation between the surface roughness characterized as the root-mean-square (rms) average roughness and the effective work of adhesion [29]. The bonding energy was reported to decrease by a factor of four as the rms-roughness increases from 0.2 to 0.5 nm (Figure 7.8). Compared, for example, to the power spectral density which relates information about the amplitude and spatial frequency of surface roughness, the use of rms average roughness to predict direct bonding of surfaces is oversimpliﬁed. However, in practice hydrophilic polished silicon surfaces will bond spontaneously if the surface rms-roughness is less than 0.5 nm. In direct bonding of hydrophilic surfaces the surface roughness is accommodated by water mol ecules adsorbed on the surface, and by the viscous ﬂow of the interface oxide at elevated temperatures. In case of microscopic surface roughness, elastic deformation of the silicon wafers is insigniﬁcant.

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Figure 7.7 ● Infrared gray-ﬁeld polariscope (IR-GFP) images of a bonded wafer [26]. (a) The shear stress image shows a contact stress ﬁeld at the center of the void, a clearly delineated noncontacted area, and a residual stress pattern characteristic of wafer nanotopography. (b) Shear stress image of fusion-bonded, double-side-polished wafers with large surface nanotopography. (c) A plot of shear stress vs. distance along the line scan in (b).

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Figure 7.8 ● Bonding energy as a function of rms surface roughness. Surface roughness was measured with AFM, and it was modiﬁed by means of chemical etching (BOE or BOE/KOH). Bonding energy is normalized with respect to a reference wafer work of adhesion. Source: Data was replotted from Ref. [29].

Thick-Film SOI Wafers: Preparation and Properties

Optical mirror polishing of silicon surfaces with col loidal silica slurries can meet this requirement quite routinely. A typical rms value of the roughness of ﬁnal polished silicon surface is in the range of 0.1–0.2 nm or smaller. The ﬁnal polishing steps used as the last step in production of prime silicon wafers are designed to produce extremely smooth surfaces that are crucial for semiconductor device manufacturing, in particular the gate oxide quality. The techniques for wafer cleaning must be able to remove contamination on surfaces including particles, organic surface contamination, and metal contamina tion. Another function of the ﬁnal cleaning step is to make the wafer surface hydrophilic, which is the pre ferred state of the surface for direct bonding. Direct bonding of hydrophobic surfaces is possible, but the highly reactive silicon surface could present a problem. After HF dip the surface attracts particle and organic contamination from the HF solution, DI water used for rinsing, and from the ambient air. Moreover, the work of adhesion at room temperature is signiﬁcantly lower for hydrophobic silicon surfaces. Particle contamina tion is responsible for the voids formed during the contacting of wafers at room temperature. Even a rela tively small particle can result in a large noncontacted area around the particle. The void size has been inves tigated by measuring the crack length as a function of the step height using wafers with steps deﬁned by pho tolithography techniques [30]. A step with a height of 0.5 μm between two standard silicon wafers leads to noncontacted area with a diameter of several mil limeters. Thin wafers deform more easily, and reduc tion in wafer thickness leads to a signiﬁcant decrease in the size of the noncontacted area. The change in the sizes of particle originated voids in bonded wafers remains generally small after annealing at elevated tem peratures. One should note that much of the particle contamination is of organic origin, and it is likely that such particles break down or decompose at elevated temperatures. Organic contamination in form of hydrocarbons adsorbed on the silicon surface usually does not lead to void formation at room temperature. However, sur face hydrocarbons act as nucleation sites for voids that are generated upon annealing the wafers above 200°C for the most part by diffusion of hydrogen. Examples of procedures to remove surface organic contamination to prevent the void formation include exposure of the wafers to O2 or Ar at elevated temperatures [31] or treatment of silicon surfaces with periodic acid (H5IO6) aqueous solution, which efﬁciently removes relatively short-chain hydrocarbon molecules from silicon surfaces [32]. Trace metal contamination or airborne molecu lar contamination from the clean room air, introducing boron or phosphorus onto the surface of the wafers, can

CHAPTER 7

be harmful since these elements can change the electric properties of the silicon material. The requirements for surface cleaning in wafer bond ing are fully matching with those in VLSI technology. Therefore, the wafer cleaning procedures based on wet chemistry that are commonly used in semiconductor industry are commonly applied. They are speciﬁcally designed to remove particle contamination, organic contamination as well as surface metals. To give an idea of the cleaning process capability, the particle counts assuming a critical particle size of 90 nm are some tens of particles on a 200-mm-diameter wafer, and today much smaller particle sizes are considered. Typical metal contam ination levels for critical surface metals are much smaller than 1 1010 atoms/cm2. Also, the cleaning proc esses are designed to not increase the surface rough ness which is very critical to wafer bonding. The SOI and advanced CMOS technologies require extremely low silicon and silicon oxide consumption in the clean ing steps with the same or higher performance in terms of particle and metal removal efﬁciency as the thickness of the SOI ﬁlm will decrease to 20 nm. Considering the SC1 step as an example, the tendency is to further decrease the NH4OH concentration, which leads to smaller consumption of silicon and practically no change in the roughness of the silicon surface. In conclusion, standard mirror-polished silicon wafers are good for direct bonding applications in terms of the wafer geometry and the surface quality. The wafer cleaning techniques that are in use in VLSI technology are consistent with the requirements of direct bond ing. The critical features and the processes in wafer manufacturing were originally developed for reasons not related to direct wafer bonding, but primarily to meet the requirements of optical lithography, gate oxide qual ity and the uniformity of thin dielectric ﬁlms.

7.4 Fabrication of Thick-Film BSOI by Mechanical Grinding and Polishing The sequence of steps required to make thick-ﬁlm SOI wafers by mechanical thinning of the device layer is illustrated in Figure 7.9. After wet cleaning and surface inspection, which form the last two process steps of sili con wafer manufacturing, a thermal oxide is formed on the wafers. This oxide later becomes the buried oxide of the SOI structure. The oxide thickness is deﬁned by the requirements of the application, and it most com monly falls in the range from 400 nm to 2 μm (Figure 7.3). In direct bonding the wafers are aligned, keeping a nar row gap between them. In SOI wafer manufacturing the alignment is most commonly based on mechanical 115

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Device wafer

Handle wafer

SOI film is originally part of the bulk silicon wafer. Cleaning to eliminate particle and surface contaminants.

Serves as a substrate for the SOI wafer. Typically a double-side polished wafer with good thickness uniformity. Final cleaning of wafers.

Oxidation Thermal oxidation to form a surface oxide layer that later becomes the buried oxide of the SOI structure.

Direct bonding Cleaning, mechanical alignment, and contacting of the wafer pair integrated in an automated wafer bonder. Bonding in controlled gas ambient or in low vacuum. Post-bond inspection by transmission of infrared light.

Thermal annealing Annealing of the bonded wafer pairs at 1100– 1200°C. Inspection of the bond quality by scanning acoustic microscopy.

Surface grinding Two-step grinding of the device silicon wafer to a target thickness using a high-precision grinder.

Polishing CMP polishing of the device silicon layer to its final thickness. Stock removal and final polishing steps.

Cleaning and final inspection Figure 7.9 ● The sequence of steps required to make a thick-ﬁlm SOI wafer by bonding and mechanical thinning of the silicon device layer. Typically there are some additional process steps (e.g., to form the edge of the bonded SOI wafer, not shown).

ﬂat-to-ﬂat or notch alignment. The initial contact between the wafers is created at a single point so that the bonding wave can propagate in a controlled way across the wafer surface. A batch of bonded wafers is loaded in a furnace and annealed to a temperature of 1100–1200°C. Stepwise mechanical thinning of the device silicon wafer includes a sequence of steps of mechanical grinding and chemical–mechanical polishing for ﬁnal thinning of the SOI ﬁlm. Both are single-wafer processes. The ﬁnal cleaning steps and inspection of the SOI wafers are basically similar to those for standard prime silicon wafers, including measurement of wafer 116

geometry and inspection of surface quality. The differ ent practical aspects of the process are discussed below.

7.4.1 Direct Bonding of Wafers A bonded SOI wafer process typically starts with a wet chemical cleaning of the silicon wafers in a sequen tial immersion batch process. Silicon wafer cleaning sequences based on RCA cleaning provide a practical method for cleaning silicon surfaces for direct wafer bonding. RCA cleaning consists of two solutions, SC-1

Thick-Film SOI Wafers: Preparation and Properties

(Standard Clean 1), which is a mixture of ammonium hydroxide, hydrogen peroxide, and DI water (NH4OH: H2O2:H2O), and SC-2, which is a mixture of hydro chloric acid, hydrogen peroxide, and DI water (HCl: H2O2:H2O). Adaptation of these cleans to the full RCA cleaning sequence includes removal of organic compounds by sulfuric peroxide, SC-1 step to remove particles, and SC-2 step to remove metallic impuri ties [33]. Between the cleaning steps the native oxide is frequently removed from the wafer using dilute hydroﬂuoric acid. The RCA-based wet-chemistry cleaning processes for VLSI technology are designed to remove particles and other contamination, to make a hydrophilic surface, and to not increase the surface roughness. These requirements are fully compatible with wafer bonding. Variations on the cleaning sequence exist and fre quently some steps of the cleaning process are cut out, or alternative cleaning solutions or solution composi tions are used to achieve higher cleaning efﬁciency or to simplify the cleaning process. Examples of such improvements and modiﬁcations include use of sur factants in chemicals to control the surface roughness, ozone cleaning as an alternative to the H2SO4/H2O2 step, combined use of megasonics to enhance particleremoving capability, removal of hydrogen peroxide from SC-2 as HCl is effective in removing metallic impurities by itself, or addition of HCl to dilute HF to increase capability to remove metallic impurities and omission of SC-2 [33]. Figure 7.10 gives an example of a wet clean ing process that is based on the RCA cleaning cycle and that has been successfully used in thick-ﬁlm bonded SOI wafer manufacturing. It only uses the SC-1 clean ing solution which removes particles efﬁciently, but is effective also for removing light organic contamina tion, and uses dilute HCl to remove metallic impuri ties. Drying of the wafer can be a source of substantial particle contamination if it is not performed in a cor rect way. In Marangoni drying the wafer is pulled from the rinse through a layer of liqueﬁed IPA. The wafer is drawn from a water bath while passing a ﬂow of nitro gen with a trace of IPA along the wafer surface. IPA will dissolve in the water, lowering the surface tension. The surface tension gradient induces a Marangoni ﬂow towards the bulk liquid. This will lead to drying of the surface during the slow raising of the wafer. The details of the wafer cleaning processes adopted for large-series SOI wafer production are infrequently disclosed, and it is possible that different proprietary surface treatments are in use to routinely obtain void-free bonded wafers. In Figure 7.11, scanning acoustic microscope images of the bonded interface after annealing at various tem peratures are shown, based on the cleaning process in Figure 7.10. No interface voids are generated upon annealing at any of the intermediate temperatures. Voids

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APM (SC-1) + Megasonic Removal of organic contamination and particles.

DI water rinsing

Dilute HF (DHF) Removal of surface oxide

DI water rinsing

APM (SC-1) + Megasonic Removal of particles.

DI water rinsing

Dilute HCl Removal of metallic impurities.

Drying Marangoni drying.

Figure 7.10 ● An example of a wet cleaning process for blank silicon wafers for direct wafer bonding. It is a typical wafer cleaning sequence based on modiﬁed RCA cleaning.

are frequently formed during heat treatment of the bonded wafer pair, mainly due to hydrogen molecules that are released in the reaction of water in the bonding interface with silicon. Besides the cleaning process, the presence of the thermal oxide forming the buried oxide of the SOI wafer reduces formation of hydrogen-related voids. The open structure of thermal silicon oxides can incorporate hydrogen and other impurities resulting in signiﬁcant reduction of gases in the interface. In case of very thin oxides (thickness 100 nm) formation of voids in the bonded interface is more difﬁcult to avoid, and in silicon-to-silicon bonding void generation almost invariably occurs at 300–400°C anneal [3]. One key function of the wafer cleaning process is to make the wafer surface hydrophilic to enable hydrogen bonding between the surfaces. The hydrophilic proper ties of a silicon surface originate from termination of the surface by polar OH-groups. The aforementioned cleaning solutions typically form a new, clean native 117

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Figure 7.11 ● Scanning acoustic microscope images of the bonded interface after annealing at 600°C (a), 800°C (b) and 1100°C (c). Buried oxide thickness was 500 nm. The wafer cleaning process is basically similar to that described in Figure 7.10.

oxide on the wafer surface after oxide removal in dilute HF. Such native oxides are highly hydrophilic [34]. For example, the SC-1 cleaning step after surface oxide removal forms a thin chemical oxide on silicon with a contact angle 10° indicating a highly hydrophilic OHterminated surface. In case of a native oxide formed by wet chemical cleaning, the reaction to form OH-groups is facilitated by the fact that the surface siloxane bonds are strained and react readily with water. The surface of thermally grown oxide is essentially hydrophobic with only a few OH-groups. Commonly the very last clean ing step is integrated into the wafer bonder. It can be simply a megasonic DI water cleaning but dilute chemi cal cleaning processes are also in use. The initial bonding of wafers right after chemical cleaning is performed in a class ISO 3 or better (class 1, old classiﬁcation) clean room environment. The time between the last cleaning step and bonding is control led to avoid airborne molecular contamination on wafer surfaces. One example of such contamination is boron. In wafer bonding boron becomes trapped in the bonded interface and changes the resistivity or even the type of silicon material next to the bonded interface by boron diffusion. The amount of boron present in the bonded interface increases with the time the wafers are left under cleaning benches. A very low concentration of boron on the surface, on the order of 1 1010 atoms/cm2, is sufﬁ cient to signiﬁcantly change the resistivity of 10 Ohm-cm 118

silicon material within the diffusion length of boron. Consideration of the material in the ﬁlters used in the clean room, adding chemical ﬁlters that absorb boron, and choosing clean room materials that generate less boron can suppress the amount of airborne molecular contami nation on the wafer surface. Wafer pairs are aligned and an initial contact is formed after which bonding proceeds spontaneously across the wafer. In SOI wafer manufacturing mechani cal ﬂat-to-ﬂat (or notch-to-notch) alignment of the two wafers is usually applied. Alignment accuracy is typi cally 50 μm for X, Y-displacement and 0.1° for the rotation of the wafers. The initial contact point can be created at the periphery of the wafers or the initial con tact can start in the center of the wafers. In both cases it is critical to assure that bonding starts from a single point and that the bonding wave can propagate laterally from that point onwards across the entire interface. Bonding under low vacuum (103…102 mbar) is also used in SOI wafer manufacturing. A strong adhe sion at low temperatures has been reported for vacuum bonding [35]. High fracture surface energies can be reached already at temperatures as low as 200°C. It, however, requires very long annealing times not prac tical in large-series wafer manufacturing. Bonding in vacuum has the advantage that no mechanical force is needed to initiate the bonding between the wafers. Also, there is an experimental ﬁnding that in some cases bonding under reduced pressure tolerates higher sur face topography than bonding under normal pressure. The differences between vacuum and ambient air direct wafer bonding were attributed to the increase in the effective contact area and the lack of trapped nitrogen or air when contacting the wafers in low vacuum [36]. The pressure also has a strong effect on the speed of the spreading of the bonded area as the lateral bonding speed is mainly determined by pressing the ambient gas between the wafers close to the propagating bonding front. Typical speed at ambient pressure is in the order of 10 mm/s, and it increases up to 1 103 mm/s when the pressure is 0.1 mbar [37]. For large-series industrial production of SOI wafers, automated production equipment typically integrates some of the process steps for direct bonding. Cleaning of the wafers, mechanical or optical wafer alignment, prebonding at room temperature, and initial analysis of the bonding quality are incorporated in a bonding tool enabling cassette-to-cassette wafer processing. The sin gle wafer cleaning stations combine, for example, brush scrubbing, megasonic cleaning, and wet chemical cleaning procedures; for automated SOI wafer bonding there are also systems with process control for megasonic cleaning, drying, alignment, and bonding in one process chamber. The bonding process is performed automatically, and there are options for wafer bonding in controlled gas

Thick-Film SOI Wafers: Preparation and Properties

ambient or in vacuum. Initial postbond infrared inspec tion of the bonding quality is most commonly checked on the basis of the transmission of infrared light. It can detect voids larger than 0.5–1 mm in diameter and allows for macroscopic bond quality inspection. In case of two hydrophilic silicon or silicon oxide surfaces the bond strength right after direct bond ing at room temperature is around 0.1 J/m2; values reported in the literature typically fall in the range of 0.06–0.2 J/m2. Thermal treatment of the bonded wafer pair is carried out to form a permanent chemical bond whereby the surfaces attach through strong siloxane (Si–O–Si) bonds. A typical condition for the heat treat ment is 1100–1200°C. It is often done in wet oxygen ambience but the ambient gas has no inﬂuence on the bond strength. After 1100°C annealing the strength of the bonded interface is very similar to that of a ther mal SiO2/Si interface, with a crack opened between the bonded wafers propagating randomly inside the oxide and along the two interfaces. The mechanism of hydrophilic wafer bonding and the reactions occurring on the bonding interface are quite well understood. It is based on analysis of the surface energy and correlation of those energies with the dif ferent chemical interactions that can take place in the interface and on spectroscopic information primarily from the multiple internal transmission infrared spec troscopy (MIT-IR). Comprehensive summaries of the bonding mechanism can be found, for example, in Refs [3] and [38]. The initial joining is due to hydrogen bonds between the water molecules bridging the two hydrophilic surfaces. The surface energy around 0.1 J/m2 is in fair agreement with the energy of the hydrogen bond characteristic of OH groups in water and the den sity of OH groups on hydrophilic surfaces, which for a fully hydroxylated silica surface is 4.6 1014 cm2. MIT IR measurements indicate from three to ﬁve layers of molecular water trapped in the interface, and from one to two layers of OH-groups. Annealing of the bonded wafer pair at T 300°C leads to diffusion of the water through the oxide layer to the Si/SiO2 interface where it reacts to form additional low-temperature oxide and molecular hydrogen. The loss of water from the inter face region enables direct coupling of the OH-groups on the opposing surfaces and strong bridging Si–O–Si bonds begin to form. At a given temperature in this range the surface energy increases with time, and the stable state of the bonding interface is achieved only after long anneal ing times. The saturated value of the surface energy is almost constant in the temperature range of 150–800°C [3], indicating that the greater part of the silanol groups in the contacted area are converted to siloxane bonds already at the lower end of this temperature range. The contacted area over which bonding occurs is limited due to the surface roughness. In the temperature range from

CHAPTER 7

300°C to 800°C remaining water from the interface region is lost allowing direct coupling of the OH groups to form Si–O–Si bonds. Water molecules formed in the reaction cause further oxidation of silicon by diffusion to the Si/SiO2 interface. Complete closure of the inter face between the two surfaces occurs above 800°C. It is facilitated by the reﬂow of the silicon oxide layer taking place at this temperature range. Hydrogen is lost from the interface region by diffusion into the silicon bulk. Infrared spectroscopy indicates formation of strained Si–O–Si bonds after annealing at 1100°C, and suggests that annealing to 1200°C and above allows relaxation of the strained bonds. Infrared spectroscopy showed that the same mecha nisms are generally applicable in the bonding interface between two thermally oxidized silicon wafers [39]. The bonded SiO2/SiO2 interface is typically annealed at a higher temperature, 1200°C, to reach the ﬁnal bond ing strength. In large-series SOI wafer production the qual ity of the bonded interface is routinely checked using scanning acoustic microscopy (SAM). It has the ability to detect very narrow planar gaps in the bonded inter face on the basis of reﬂection of the focused acoustic wave. Typically a pulse-echo image is created by ana lyzing the echo that returns when ultrasonic pulse is launched at the bonded wafer pair, and the same trans ducer is used for sending and receiving. In case of an air gap practically all acoustic energy is reﬂected from the buried solid-air interface. The elapsed time before the return indicates depth, and a data gate can be set to analyze only the echoes from the bonded interface. The intensity of the reﬂected energy is recorded at each measuring point during the scan across the wafer area, and a defect map is created. The technique is totally equivalent to acoustic inspection of plastic encapsu lated microelectronics devices (e.g., for failure analy sis). The ultrasonic frequency that is used in bonded wafer inspection is typically from 100 MHz to a maxi mum of few hundred MHz. The smallest detectable defect size in a bonded wafer pair is from 5 to 10 μm. In routine process control measurements the minimum size of void that is detected is signiﬁcantly larger, and it is mainly limited by the scan resolution to have the required throughput in a production environment. As an example, Figure 7.12 summarizes the SAM inspection of bonded wafers taken from medium- and large-series production of thick-ﬁlm SOI wafers. The processes for wafer cleaning and direct bonding were essentially similar to those described above. In more than 90% of the wafers SAM cannot detect any voids larger than 20–30 μm. The average number of voids corresponds to the void density per unit surface area that is signiﬁ cantly smaller than 0.01 cm2. The total area of voids in a wafer is typically much less than 1 mm2. 119

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(a)

1 mm (b)

Figure 7.12 Voids of different sizes are detected by SAM in bonded SOI wafers. The smallest detectable defect size limited by the scan resolution was 20–30 μm. The sample is taken from large-series wafer production and includes more than 1000 bonded wafers. Wafer diameter is 150 mm. ●

Noncontacting areas in the bonded interface are gen erally caused by particles and organic contamination due to poor wafer cleaning procedures and poor wafer surface condition. At the present stage of thick-ﬁlm SOI technology voids are not a fundamental issue, but they remain one of the yield-determining factors in the wafer manufacturing environment. Voids become criti cal when extremely low failure rates are required and no defects larger than a given critical defect size are allowed in the bonding interface. Sensor elements that require hermetic sealing and that cannot be fully tested for very low leakage rates for some critical automotive applications provide a good example. In wafer production the most common way of speci fying the voids in thick-ﬁlm SOI wafers makes use of transmission of infrared light. Both IR light transmis sion and SAM offer nondestructive quick scans but are unable to detect microscopic voids. Another technique that is used in MEMS for inspection of defects beneath the surface that can be used for bonded SOI wafer inspection is infrared light microscopy. IR-GFP provides another angle to trapped particle detection in the bond ing interface (Figure 7.13). Trapped particles and mac roscale defects associated with particles can be found by imaging the residual stress-ﬁelds around the defects. The residual stress at the particle locations is typically from less than 1 MPa to several MPa [40]. The different methods to determine the bond strength and their limitations were reviewed by Vallin et al. in Chapter 19 of this book and in Ref. [41]. The most commonly applied methods include the double cantilever beam (DCB) measurement, the tensile test, the Chevron test, and the blister test methods. Until now any nondestructive methods have not evolved. Of the different methods the DCB measurement, also referred to as the crack opening method, is frequently 120

“a”

“b” “c” “d”

Figure 7.13 ● Magniﬁed IR-GFP images: (a) IR-transmission image, (b) shear stress image. Figure 7.13b shows a macroscale defect, where a single particle “a” has generated a noncontacted area, and several other particles are tapped in the bonding interface. The maximum residual stress is present at location “d” [40].

used and is the only method that is easily suited to wafer production. In DCB measurement a thin blade is inserted into the bonded interface to open a crack, and the length of the crack is measured. The bond strength is derived considering the structure as a system of two cantilever beams that are bent. The crack that is opened is atomically sharp allowing quantiﬁcation of the frac ture toughness. The repeatability of the measurement in measured crack length was estimated to be less than 5%, implying a relative standard deviation in fracture toughness of 20%. To get reproducible results the crack opening should be automated and the measurement should be performed in an inert environment to avoid stress corrosion that is typical of cracks in brittle mate rials. It is related to breaking of the strained bonds at the crack tip by interaction with water, and leads to the crack growth during the crack length measurement of wafer bonds [42]. A major drawback is that it is difﬁcult to insert a blade between two strongly bonded wafers, and direct bonded silicon wafers annealed at 1000°C or above tend to break. The method is therefore mostly limited to low bond strengths. In the Chevron test the load is applied to a specimen with a chevron-shaped notch, and an atomically sharp

Thick-Film SOI Wafers: Preparation and Properties

crack is formed at the tip of the chevron. Successful measurements have been demonstrated on very small test specimen in millimeter size (micro-Chevron tests). It can be used to measure both strong and weak bonds. With blister testing, internal cavities sealed by wafer bonding are pressurized to apply load on the bond ing interface. The bond strength is estimated from the pressure required to initiate the fracture. Both methods can produce good repeatability and reproducibility, and using the micro-Chevron test structure is being devel oped as a standardized method for measuring wafer bond strength. The methods listed have been used in optimization of direct wafer bonding schemes. It is not clear to what extent they are in use to control the bond strength in production environments. The methods are all purely mechanical and destructive, and only sampling-type testing is possible. The DCB measurement does not require sample preparation and is straightforward to implement. The drawback of the method is that it has proven difﬁcult to open the crack between the wafers in case of a permanent chemical bond with a full strength of the bond without breaking the wafers, which is the condition in SOI wafer production. Tensile measure ments require considerable preprocessing of samples and the relatively large scatter would probably limit this method’s use in quality control in wafer production. The other two methods, the Chevron test and the blis ter method, require processing of the test structures in the wafers before direct bonding, and therefore dummy work pieces with test structures are needed. This requirement means the methods are not well suited to the fabrication of standard unstructured bonded SOI wafers. In applications where the buried oxide is used as a sacriﬁcial layer to release mechanical sensor elements, a well-deﬁned oxide etch rate is critical. Evaluation using hydroﬂuoric acid (HF) etching of the buried oxide has been used to test the bond quality. Hydroﬂuoric acid etches the buried oxide faster in the area of low bond strength and can signal differences in bonding in the region of high mechanical bond strength. Comparison of normal high-temperature bonding and plasma-activated bonding indicates that even if the mechanical strengths are identical, the etch rate of the plasma-activated bonding interface can be several times higher [43]. In HF etching of the buried oxide ﬁlm both the etch rate and the proﬁle of the etching front are character istic of the bond quality. For full strength of the bond the etched oxide edge is nearly straight and the bonding interface is identical with the thermally oxidized silicon interface (Figure 7.14). If HF etching proceeds faster along the bonding interface, a notch is formed and the oxide starts to etch also in the vertical direction, resulting in an increase of the effective etch rate. For hydrophilic

CHAPTER 7

Figure 7.14 ● Characterization of bond quality based on etch rate of the buried oxide in HF etching for optimization of bonding schemes. (a) Top view of the SOI wafer after HF etching showing the 20-μm wide trenches etched through the SOI layer to the buried oxide layer and approximately 20-μm distance of buried oxide etching on both sides of the trenches. (b) (SEM) shows a cross-section of an SOI wafer after HF etching of the buried oxide. The original join is between the upper silicon wafer and the thermal oxide.

silicon–oxide bonds the recorded values for the etch rate in 50% HF for a large number of different types of bonded SOI wafers over an extended period of time range from 1.40 to 1.60 μm/min, indicating that the vari ation of the etch rate is well within /10%. A similar test using vapor phase HF etching showed that the vari ation of the etch rate across an SOI wafer corresponding to an average etching distance of 4.9 μm was approxi mately 6% (3σ). The weak preferential HF etch ing along the original bonding interface that can be seen after 1100°C annealing (Figure 7.14) has been associ ated to strained Si–O–Si bonds between the two wafers. Preferential etching can be explained by the fact that the strained Si–O–Si bond is ruptured by an adsorbed water molecule and two OH-groups are formed. Infrared absorption data indicates that relaxation of the strained bonds occurs in annealing to higher temperatures sug gesting a further reduction of the etch rate [38]. 121

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7.4.2 Thinning by Grinding and Polishing The brute-force mechanical thinning of the bonded device wafer employs the grinding and precision chemical– mechanical polishing processes (Figure 7.9). These proc ess steps deﬁne the thickness and the TTV of the SOI layer as well as the properties and quality of the wafer surface. In the conventional wafering process lapping and double-side polishing can produce very good thick ness uniformity, with the TTV across the wafer smaller than 0.5 μm. Those manufacturing processes can pro vide the required wafer form and surface ﬁnish control, but they have no precise thickness target. Therefore, surface grinding technology has been quite universally applied in mechanical thinning of thick-ﬁlm SOI wafers. The most attractive feature of the high-precision sur face grinding process is that it allows accurate control of both the absolute thickness of the wafer and the thick ness uniformity across the wafer. Another advantage is the minimal mechanical crystal damage it produces. The handle silicon wafer is in most cases double-side polished. It allows two-sided processing of the SOI wafer, but also provides the minimum TTV that is critical for the ﬁnal thickness variation of the SOI layer. The grinding process is designed to minimize brittle fracture of silicon in grinding, to assure very high surface ﬁnish, wafer form accuracy requirements, and minimal surface and near surface damage. For a high-precision grinding process of silicon the total grinding tool sys tem needs to be considered. The fundamental grinding tool design requirements include vibration free and rigid grinding tool, very high stiffness between the tool and the silicon wafer, high-resolution motion control, micrometersize abrasive media bonded as a rigid grinding wheel, thermal stability, high-precision metrology system inte grated into the grinding tool, and clean controlled envi ronment [44]. Vertical-spindle type grinding tools with the rotational in-feed grinding conﬁguration are most frequently used. In principle the simple geometry assures ﬂatness of the wafer as the axes of rotation of the spin dle and the wafer are aligned. In practice the grinding tool is not inﬁnitely stiff and the shape of the wafer is controlled by ﬁne adjustment of the angle between the axis of rotation of the wheel and the axis of rotation of the wafer. Pregrinding and ﬁne grinding are usually car ried out in two different grinding stations with diamond cup grinding wheels of different grit size. Fine grinding of silicon wafers refers to grinding with 2000 mesh or ﬁner diamond wheels, corresponding to 3–6-μm grit size. In the SOI wafer grinding sequence the device wafer thickness is reduced very close to the ﬁnal silicon ﬁlm thickness. In volume production of thick-ﬁlm SOI wafers an average TTV across the wafer of 0.5 μm or 122

less and tolerance for the ﬁnal wafer thickness better than 0.5 μm are routinely achieved. Surface and subsurface damage is easily created dur ing grinding of single crystalline silicon which is hard and brittle. Ductile and brittle modes of deformation can occur in a brittle material such as silicon. Brittle and partial ductile chips can be found simultaneously on the surface of a silicon wafer. The diamond particle size speciﬁcation has the most signiﬁcant effect on surface quality and depth of subsurface damage, and the duc tile mode process is associated with small depth of cut. Under optimal grinding conditions a more ductile or partial ductile mode surface can be obtained. For mini mum mechanical subsurface damage from the grinding step, the size of diamond abrasives should be as small as possible. In grinding a self-conditioning state of the grinding wheel must be obtained, implying use of softer bond materials with less wear resistance. The polishing method for silicon is optical chemical– mechanical polishing based on silica slurries. The polish ing step is designed to remove the mechanical crystal damage and to make the mirror surface. The polish ing method and the processes are basically the same as those used for prime grade silicon wafer polishing, and a similar quality of the surface is achieved. Polishing com bines mechanical action with chemical etching using abrasive alkaline polishing slurry with colloidal or fumed silica particles and polyurethane pads. One can reach the required accuracy of the polishing process by using CMP polishing tools that were developed for chemical mechanical planarization of wafers in mainstream semi conductor manufacturing. Most of the CMP machines that are in use are based on rotary polishing tables, but other basic designs such as linear systems are employed as well. The process is typically a single-wafer process. The many options for tool designs, primary tool param eters, and the key elements of the CMP process are reviewed in Ref. [45]. The CMP step has to remove approximately 1.0 to 2.0 μm of silicon to totally remove the mechanical damage created in the ﬁne grinding step. An arche typical polishing method then utilizes a two-step pol ishing process with speciﬁc properties of the polishing pads and slurries. The primary polish which is used to remove most of the silicon material is followed by a step of ﬁnal polishing to produce the smooth surface. Typical values of the polishing removal rates for the stock removal and ﬁnal polishing steps are from 0.5 to 1.5 μm/min and 10 nm/min, respectively. Two critical issues speciﬁc to thinning of the thickﬁlm SOI layer are the control of the ﬁnal layer thick ness (the end-point of polishing), and the uniformity of the silicon ﬁlm. Accurate control of the end-point and the thickness uniformity require the use of a singlewafer CMP polisher, and automated process control for

Thick-Film SOI Wafers: Preparation and Properties

CMP provides the necessary manufacturability, stabil ity, and predictive process results. In the CMP technol ogy different techniques for the end-point detection were developed. Indirect methods of measuring the motor current changes or direct monitoring of changes in the frictional forces to identify the point where the polishing meets the interface between two material lay ers cannot be utilized in SOI wafer polishing. Optical reﬂectometry for in-situ measurement of ﬁlm thickness requires extensive hardware modiﬁcations, and its use is limited by the very thick silicon layers in thick-ﬁlm SOI wafers for mechanical systems. As a result, the inline thickness measurement system integrated with the CMP tool is probably the most extensively used tech nique for the end-point detection. The data from thick ness measurement are used for changing the process time (or any other process parameter) using run-to-run control methods for compensating for changes in the polishing removal rate. Thickness control of the SOI layer better than 0.1 μm (3σ) is achieved in the pro duction environment. One possible embodiment of the thinning process showing the step-wise reduction of the device wafer thickness and the typical thickness tolerance and thick ness uniformity at each step is given in Table 7.1. Controlling the thickness uniformity of the SOI ﬁlm can be further improved by local plasma-assisted chemical etching (PACE). In PACE technology [46] the chemical etching area is conﬁned under a small electrode where plasma is generated. Starting with the map of SOI ﬁlm thickness, SOI wafers are etched locally by controlling the position of the wafers and the dwell time for etching. The whole process consists of SOI substrate fabrication (as described above), PACE

CHAPTER 7

which includes the measurement of the SOI ﬁlm thick ness map, local plasma etching, ﬁlm thickness measure ment after etching, and touch polish and ﬁnal cleaning of the wafers. A short touch-polishing step is necessary since the surface quality is degraded during the plasmaetching process. The technique has been primarily con sidered for fabrication of SOI layers in the range of 0.1–1 μm as an alternative approach to the layer trans fer methods. Typical volume of material removed in the local plasma-etching step is 1–3 μm, and the thickness uniformity of 1.5 nm (rms) for 0.1-μm-thick SOI ﬁlms was reported [47]. The technique has been demon strated also for thick-ﬁlm SOI wafers with active layer thickness up to 30 μm. A similar technique was applied to demonstrate extremely thin and uniform 8-in. SOI wafers [48]. Commercial tools based on local plasma etching exist in the market at least for large-diameter silicon wafer ﬂattening. With the metrology system for SOI ﬁlm thickness measurement they are in principle suited for SOI layer thinning, but volume production of SOI wafers based on the PACE process has rarely been assessed in published papers. The capability of the mechanical thinning process based on conventional back-grinding and CMP proc esses in medium- or large-series wafer production is demonstrated as follows. The SOI layer thickness is most commonly measured on the basis of a Fourier transform infrared (FTIR) technique using a Michelson interferometer. The technique is the same as for sili con epitaxial layer thickness measurement, which is an ASTM-approved method to measure epitaxial ﬁlm thickness, and the same tools are used. There are two implementations of the measurement, one based on the interferogram and one based on spectroscopic analysis.

Table 7.1 Example of possible application of the back-grinding and CMP polishing processes in thinning of 150- or 200-mm diameter thick-ﬁlm SOI wafers

Process step

Si ﬁlm thickness(μm)

Thickness tolerance (μm)

Total thickness variation (μm)

Damage depth (μm)

Device Si wafer

300–400

5

Not critical

None

Handle Si wafer

N.A.

0.5

0.5

None

Rough grinding

25

1

2

15–20

Fine grinding

2

0.5

0.5

1.0

CMP polishing

0.5

0.2

0.5

0

CMP ﬁnal polishing

0.0

0.1 (3σ)

0.5

None

Typical silicon ﬁlm thickness, thickness tolerance, thickness uniformity (TTV) control, and characteristic crystal damage depth after each unit process step are given. Silicon ﬁlm thickness is calculated from the target ﬁlm thickness.

123

Silicon as MEMS Material

124

is critical as it becomes the reference for the control of the thickness of the SOI layer and directly contrib utes to the ﬁnal thickness uniformity of the SOI ﬁlm. A rather typical speciﬁcation limit for the thick-ﬁlm SOI wafer thickness uniformity is 0.50 μm, including the thickness variation from wafer to wafer and the TTV across the wafer. The thinning process has been reﬁned to control the SOI layer thickness uniformity more accurately within 0.30 μm based only on the improve ment of the accuracy of the mechanical thinning process (Figures 7.15 and 7.16); the mechanical thinning process

Figure 7.15 ● Thickness variation (μm) of the SOI layer across a 150-mm-diameter wafer demonstrating the process capability of the mechanical thinning process in large-series wafer production. The target thickness of the SOI layer was 2.5 μm.

(a) 13.0 SOI thickness (μm)

The interferogram-based technique relies on the time domain to extract the ﬁlm thickness. An abrupt inter face with no transition layer is assumed. It does not take into account the ﬁnite width of the interface between the epitaxial silicon layer and the substrate, but it is a good approximation for the silicon-oxide interface of a bonded structure. In the spectroscopic, model-based approach, the instrument measures the reﬂectance of the sample over a wide spectral range, and a calcu lated reﬂectance spectrum is ﬁtted to the measured spectrum. In epi layer thickness measurement, layer thickness, transition layer width, and substrate carrier concentration can be extracted, but for the silicon– oxide interface the ﬁrst principle models to calculate the reﬂectance spectrum are not broadly implemented. The interferogram-based approach is a single-beam measurement. The repeatability of the measurement (≤10 nm) is good compared to typical thickness varia tion of thick-ﬁlm SOI layers, but to correlate the meas urements in a long term for variation in the light source or in the environmental conditions some corrections may be necessary. Also, because the method relies on a single optical beam, there is some variation between the tools, and calibration to some other method is nor mally made. For very thin ﬁlms the interferogram side bursts generated by reﬂection from the interface merge with the center burst, and reference wafers are required to separate the two to extract the SOI layer thickness. Such merging starts to occur when the ﬁlm thickness is 2 μm, and it does not seriously limit the measurement of thick-ﬁlm SOI layers. The upper limit for the thick ness measurement depends on the carrier concentration in the device silicon layer. In lightly doped silicon 200 μm-thick layers and above can be measured. In lowresistivity material another complication besides the absorption of infrared light is the index of refraction of silicon, which becomes a function of the carrier concen tration and the light wavelength. With these limitations the interferogram-based FTIR technique has been used successfully in thick-ﬁlm bonded SOI wafer produc tion with a full range of speciﬁcations for the SOI layer thickness and resistivity. In large-series SOI wafer production the uniform ity of the silicon ﬁlm is driven by two parameters, the wafer-to-wafer variation of the mean layer thickness and the thickness variation across the wafer (TTV of the SOI layer). Final thickness of the silicon ﬁlm is con trolled in the CMP polishing step using the end-point detection or in-line thickness measurement system inte grated with the CMP tool. Within-wafer thickness varia tion is deﬁned by the back-grinding and CMP processes, and equally by the TTV of the handle silicon wafer. The surface grinding process only controls the total thick ness of the wafers using the back surface of the wafer as the reference plane. Minimal TTV of the handle wafer

Mean thickness

Mean + 3σ

Upper limit

Lower limit

Mean -3σ

12.5 12.0 11.5 11.0 70

90

110

130

Wafer number (b) 101.0 SOI thickness (μm)

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Mean thickness Upper limit

Mean - 3σ Lower limit

Mean + 3σ

100.5 100.0 99.5 99.0 0

20

40

60

Wafer number

Figure 7.16 ● Thickness uniformity for thick-ﬁlm bonded SOI wafers. Examples were taken from large-series SOI wafer production. The target silicon ﬁlm thickness was 12.0 μm (a) and 100.0 μm (b). Wafer diameter is 150 mm.

Thick-Film SOI Wafers: Preparation and Properties

has greatly beneﬁtted from signiﬁcant engineering to develop sophisticated ﬁne grinding wheels for silicon grinding with an exceedingly small depth of the crystal damage from the grinding step. Figure 7.16 shows an example of the wafer-to-wafer variation of the ﬁlm thickness taken from SOI wafer production. The error bars in the ﬁgure correspond to the 3σ values from the 9-point FTIR-measurement of the SOI layer thickness. With the in-line thickness measurement system the average ﬁlm thickness can be routinely controlled within 0.1 μm (3σ). The over all uniformity for all wafers and all sites calculated at 3σ level is 0.40 μm. Thickness variation is independ ent of the silicon ﬁlm thickness which is a characteristic feature of the thinning process based on back-grinding and CMP polishing. The distribution of SOI thickness values for all wafers and all sites shows that more than 97% of the surface area is within 0.2 μm of the target thickness (Figure 7.17). A typical SOI wafer speciﬁcation for the back-grinding and polishing process is given in Table 7.2. It represents standard products, and wafer suppliers typically offer tighter speciﬁcation for some of the parameters.

7.4.3 Properties of Thick Bonded SOI Wafers 7.4.3.1 Stress and Wafer Bow The presence of the buried silicon oxide ﬁlm signiﬁ cantly alters the thermal and mechanical behavior of the SOI structure compared with processing of standard

Figure 7.17 ● Thickness of bonded SOI wafers including all sites of all wafers from a 9-point FTIR thickness measurement. Total number of wafers is over 300. Thickness is calculated as the difference from the target thickness. Wafer diameter is 150 mm.

CHAPTER 7

bulk silicon wafers. The thermo-elastic properties of thermal oxide are clearly different from those of silicon, and the buried oxide has a signiﬁcant impact on the room-temperature bow of the SOI wafer and the stress in the active device layer. The most important sources of strain are the differential thermal expansion of sili con and thermal silicon dioxide, and the intrinsic stress of the SiO2 layer. In bonded SOI wafers the strain is accommodated elastically by the build-up of in-plane stresses. When the device wafer is thinned down it results in bending of the structure, and the deformation can be described in terms of a bending radius of cur vature or bow of the wafer. Larger strains induced by processing of SOI wafers can in extreme cases lead to plastic deformation or even delaminating of the silicon ﬁlm. In a bonded wafer the compressive stress in the bur ied thermal SiO2 ﬁlm at room temperature induces bow and a convex shape to the SOI wafer. The intrinsic stresses that occur during the oxide growth depend on the growth temperature and are related to the volume expansion in the oxidation process of silicon. At low oxidation temperature (950°C and below) the lack of free volume typically leads to compressive stress in the growing oxide ﬁlm. At higher temperatures (1000°C) relatively small intrinsic stress exists in thick (100 nm) thermal SiO2 ﬁlms. Viscous ﬂow of the thermal oxide has been used to explain the relaxation of the internal stress. The stresses in thermal SiO2 at room temperature are for the most part due to the differences in the thermal expansion coefﬁcients between silicon (2.6 106 1/K) and SiO2 (5 107 1/K). The stress is compressive and the reported values for the overall mechanical stress including both the internal stress and the ther mal stress vary from 200 to 400 MPa [49]. The stress distribution depends on many parameters such as SiO2 ﬁlm thickness, the oxide growth conditions, pos sible heat treatments after oxidation, and the crystal orientation. The bending of the SOI wafer can be characterized by wafer bow (deﬂection of the center point of the wafer from a reference plane deﬁned by three points taken at the edge of the wafer). For SOI layers that are less than 10 μm thick the ratio of SOI layer thickness to the total thickness is small and the silicon ﬁlm has prac tically no contribution to the bending of the wafer. In this range the wafer bow is deﬁned by the combination of the thicknesses of the handle silicon wafer and the buried oxide ﬁlm. Data on 380-μm-thick 150 mm-diam eter wafers in Figure 7.18 illustrate the bow in bonded SOI wafers comparing the bow values in the handle silicon wafers and in the SOI wafers with 0.5-μm-thick BOX layer. The wafer bow increases from 15 to 15 μm in silicon wafers to 65 to 95 μm in SOI wafers. The bow value can be quite systematically predicted for different 125

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Silicon as MEMS Material

Table 7.2 Example of a thick-ﬁlm bonded SOI wafer speciﬁcation for microelectromechanical systems

Overall wafer

SOI wafer parameter

Typical

Crystal pulling method Wafer diameter, mm Handle wafer thickness, μm Handle wafer thickness tolerance, μm Total thickness variation, μm Bow/warp

Czochralski 150 and 200 380–725

/15 2 Depends strongly on the thickness of handle wafer, BOX, and SOI layer Polished or lapped/etched

Handle wafer backside Silicon ﬁlm

Buried oxide

SOI ﬁlm thickness, μm Thickness tolerance, μm Resistivity, Ohm-cm P-type (Boron) N-type (Phosphorus) N-type (Antimony) Crystal orientation Crystal orientation accuracy

2

/0.5 or /1.0

Buried oxide type Buried oxide thickness, μm

Thermal SiO2 0.2–4.0; formed on handle or device wafer or both wafers

/ 5

Buried oxide uniformity, %

0.00550 0.130 0.010–0.020 100 0.5°

Available

300 (150 mm)

/5 Max / 30 μm if oxide allowed to remain on back surface

/0.3 1000 500 111, 110 0.2°

Speciﬁcation represents typical capability of thinning of wafers by grinding and CMP. Since the mechanical material is originally from a bulk silicon wafer its properties are equivalent to that of Czochralski silicon. Polishing and wafer cleaning processes are basically similar to those for prime silicon wafers, and similar surface quality can be achieved.

types of wafers starting from Stoney’s equation [50], which has been—and still is—widely used to relate the bending of the wafer to the average stress in ther mal oxide. The radius of curvature R increases approxi mately as the square of the handle wafer thickness. The wafer bow, which is proportional to 1/R, then depends on the layer thicknesses as tBOX/tSi2 where tBOX and tSi are the BOX and handle wafer thicknesses. For a given value of strain deﬁned by the thermal oxide, increasing the handle wafer thickness provides an effective way of reducing the bending of the wafer. However, in MEMS applications rather thin handle silicon wafers are often preferred to assist processing of wafers from both sides or to reduce the overall thickness of the sensor ele ments. At the same time the design considerations of the sensor elements or the requirement of robust proc esses usually set some lower limit for the buried oxide ﬁlm thickness. Therefore, bending of the wafers easily becomes an issue, and thick-ﬁlm SOI wafers typically have signiﬁcantly higher bow values than those in prime silicon wafers. One method that is commonly used to reduce the wafer bow is to retain a thermal oxide layer on the 126

back surface of the SOI wafer (Figure 7.18). The bow of the SOI wafer then depends on the relative thick nesses of the buried oxide and the backside oxide, but in practice the wafer bow can be very close to that of the handle silicon wafer. Another way to reduce the bow of wafers is to add a thin silicon nitride layer into a composite buried insulator to balance the compressive stress of thermal oxide. The concept, which requires direct bonding of silicon nitride, has been demon strated but is probably not in common use in SOI wafer fabrication. When the active silicon layer is thick (10 μm), it directly changes the total bow of the SOI wafer (Figure 7.19). The bending moment of the silicon ﬁlm is oppo site that of the substrate wafer reducing the overall bow of the wafer. The magnitude of the wafer bow reduction as a function of the SOI layer thickness also depends on the details of the SOI wafer fabrication process and, for example, forming the buried oxide initially on the device wafer or the handle wafer was seen to produce systematically different behavior. Simulations indicate that the residual intrinsic stress in the SOI layer has a pronounced effect on variation of the overall wafer bow,

Normalized wafer bow

Thick-Film SOI Wafers: Preparation and Properties

CHAPTER 7

1.00 0.75 0.50 0.25 0.00

–0.25

Figure 7.18 ● Bow of bonded SOI wafers with thin device layer (approximately 10 μm or smaller). Handle silicon wafer thickness was 380 μm and the buried oxide thickness was 500 nm. Effect of a balancing oxide with nominal thickness equal to the buried oxide thickness on back surface of the wafer is also shown. The values given are for a 3-point reference plane (reference points on edge of the wafer).

and that even low values of residual stress can signiﬁ cantly inﬂuence the wafer shape [51].

7.4.3.2 Crystal Defects Film quality and crystalline perfection of SOI layers obtained by direct bonding and mechanical grinding and polishing techniques are virtually identical to those of device grade bulk silicon wafers. If the polishing is performed to prime grade standards, the crystalline per fection of the initial bulk Si wafer can be retained. In thick-ﬁlm bonded SOI wafers the device silicon wafer directly deﬁnes the crystal material of the SOI ﬁlm. Accordingly, the crystal quality and defects are corre lated to the control of the crystal pulling techniques. Because of the thick silicon layers, control of the crys tal defects associated with precipitation of oxygen in the bulk of the device wafer needs consideration when deciding upon the silicon material. In the bonded SOI process the device silicon wafer is heat-treated at 1100– 1200°C to form a permanent chemical bond and reach the ﬁnal bond strength; two high-temperature proc ess steps are necessary when thermal oxide is grown on the device wafer to form the buried oxide. In such high-temperature annealing, oxygen incorporated into Czochralski-silicon precipitates, leading to formation of oxygen precipitates in the bulk of the device silicon wafer. In high-oxygen silicon, a denuded zone free of precipitates can form near the silicon oxide interface. If the SOI layer is thin (10 μm) it is in the region of the denuded zone where precipitation of oxygen is greatly reduced, and low concentration of crystal defects in the silicon ﬁlm can be achieved. In thick SOI layers oxygen precipitation in the bulk of the device silicon wafer actu ally deﬁnes the concentration of oxygen-related crystal

0

50 100 SOI layer thickness (μm)

150

Figure 7.19 ● Variation of wafer bow as a function of the SOI layer thickness. The measured values of bow are divided by the value estimated for thin SOI layer (thickness 10 μm) assuming 300 MPa compressive stress in the buried oxide using Stoney’s equation to enable comparison of wafers with different handle wafer and buried oxide thicknesses. The values are lot averages of 150-mm-diameter SOI wafers.

defects in the SOI ﬁlm. Stacking faults then grow on the oxygen precipitates during thermal oxidation of the SOI layer. For oxygen concentration of 14 ppma or higher, the stacking fault density induced by thermal oxidation strongly depends on the actual oxygen concentration in the crystal and the silicon ﬁlm thickness. The choice of crystal material is critical to control oxygen precipitation and thereby, for example, the for mation of oxidation-induced stacking faults (OISF) in a thick device layer. Basically one can use ﬂoat-zone silicon material with inherently low oxygen concentration, or epitaxial silicon wafers. However, it is also possible to use Czochralski (CZ) silicon with reduced oxygen con centration. Figure 7.20 shows the number of OISF as a function of the oxygen concentration in the crystal material of the device wafers. It summarizes data from different types of CZ crystals including weakly doped n- and p-type and highly doped p-type material. The device layer thickness in the wafers is from 8 to 50 μm. In SOI wafers in which the oxygen concentration in the device wafer is 11 ppma or less there is very little or no oxygen precipitation that would lead to the for mation of stacking faults. The OISF density is from 0 to 2 cm2 independent of the type of crystal material or the SOI ﬁlm thickness. Similar OISF densities are typically measured from prime quality polished silicon wafers indicating that the defect density is related to the overall crystal quality rather than the SOI fabrication process. At higher oxygen concentrations from 11 to 13 ppma, OISF start to appear although there is quite a lot of variation according to the type of crystal, layer thickness, and formation of buried oxide, either on the 127

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Silicon as MEMS Material

device wafer or the handle silicon wafer. Finally, when the oxygen concentration is around 15 ppma very high OISF concentrations of 1 105 cm2 or higher can be found. For reference, IC requirements for the oxygen concen tration in polished silicon wafers to control oxygen precip itation for internal gettering of metal impurities are most commonly in the range of 12–16 ppma. In thick-ﬁlm SOI wafers designed for MEMS applications crystal material with lower oxygen concentration is advantageous.

7.5 BESOI Process An alternative method to make thick-ﬁlm bonded SOI wafer is the BESOI. It is basically a layer transfer proc ess which makes use of selective chemical etching for the ﬁnal thinning step of the SOI layer. Heavily borondoped p

type silicon exhibits much lower etch rate than lightly doped n- or p-type silicon in alkaline etching solutions such as ethylenediamine-pyrocatechol-water (EDP), tetramethyl ammonium hydroxide (TMAH), or KOH, and a thin boron-doped layer is the most fre quently used etch stop. In this approach a p

layer is ﬁrst formed on the seed wafer, and a lightly doped nor p-type epitaxial silicon layer that later becomes the SOI ﬁlm is grown on top of the p

layer. The layer is transferred to a second silicon wafer by direct bond ing and subsequent chemical etch-back of the device wafer. The isotropic fast-etching step or mechanical thinning of the device layer is followed by a selective etching step that stops at the p

region. The bur ied etch-stop layer can be formed either by implant ing a high dose of boron to produce a p

type layer and growing an epitaxial layer on top of a boron-doped

OISF density (cm–2)

40 30 20

10

0 5

6

7

8 9 10 11 Oxygen content (ppma)

12

13

Figure 7.20 ● Thermal oxidation induces stacking faults in thickﬁlm SOI wafers. Thermal oxidation was carried out at 1100°C for 2 hours (wet oxidation). Device wafer properties vary including n-type, p-type, and highly p-type silicon. SOI layer thickness varies from 8 to 50 μm. The buried oxide thickness varies from 400 nm to 2 μm, and it was initially formed either on the device wafer or the handle silicon wafer by thermal oxidation.

128

surface layer or by the two-layer epitaxial process to form the p

and the lightly doped active layers. Compared with the direct mechanical grinding and pol ishing techniques, introduction of the etch stop extends the wafer bonding technique to thin ﬁlms and strin gent thickness uniformity requirements. Another major difference is the fact that the presence of the highly boron-doped layer represents the key factor in the defect-generating mechanisms which result from the bonding and thinning process steps. A schematic process ﬂow of BESOI is outlined in Figure 7.21. As a speciﬁc example, a process based on epitaxial etch-stop layer is brieﬂy described. In this process the ﬁrst epitaxial p

silicon layer is grown on a silicon wafer to a boron concentration in excess of 1 1020 cm3, typically using a single wafer atmospheric pressure epi reactor. Thickness of the boron etch-stop layer is in the range of 1–2 μm. Due to the small covalent radius of the boron atom, the equilibrium lattice constant of the highly boron-doped layer is smaller, which causes signiﬁcant lattice contraction of the p

layer. The lat tice mismatch induces strain and, when the critical epi taxial ﬁlm thickness is exceeded, the strain is released by plastic deformation in the form of misﬁt dislocations along the interface. To compensate for the strain the boron-doped layer is codoped with germanium. It is elec trically inactive, has a covalent radius that is larger than that of a silicon atom, and has high solubility in silicon. The strain compensation prevents the propagation of dislocations into the device layer. For full compensation of the stress the amount of germanium in the crystal is approximately six times that of boron [52]. The second lightly doped p- or n-type epitaxial layer is grown on top of the highly boron doped B/Ge etch-stop layer to form a two-layer epi structure. Low temperature epi processes at 1000°C have been used to obtain epi layers with sharp transitions between the epi layers to achieve the required thickness control in selective etching, and to avoid p-type background doping of the device layer. In order to have the interface with thermal SiO2 in the ﬁnal SOI struc ture, a thin thermal oxide is grown on the seed wafer. The device wafer is bonded to the handle silicon wafer with a thermal oxide by joining the wafers at room temperature and annealing the bonded wafer pair. The device wafer is thinned by ﬁrst grinding or rapidly etching in isotropic etching solution to remove most of the device wafer. In the second step, an alkaline aqueous solution such as KOH or TMAH is employed to etch off the remaining silicon until the etching stops at the peak of the boron concentration in the p

layer. The etchstop layer can be removed by another selective etching step, or in some cases also by short nonselective etching or reactive ion etching. The chemical etching process that is designed to stop at the transition from p to the lightly doped layer is based on HF–NHO3–CH3COOH

Thick-Film SOI Wafers: Preparation and Properties

chemistry [53]. The SOI wafer undergoes a ﬁnal touch polish. The touch polish process is designed to minimize degradation of the SOI layer uniformity while achiev ing surface roughness typical of a prime quality polished silicon wafer. It also removes the tail of the boron diffu sion from the p

etch stop layer. The process described above uses a double etch-stop approach. The selectivity of alkaline etching of highly boron-doped silicon is from 1:10 to 1:100 depending

CHAPTER 7

on the type of etching solution and the actual peak con centration of boron. The overall etch selectivity of the combination of the two selective etching steps can be as high as 104:1. Therefore, the ﬁnal thickness variation of the device layer is determined mainly by the toler ances of the epi process and the ﬁnal touch polish step. Thickness uniformity that is better than 10 nm has been reported for thin BESOI layers. In case of thick SOI layers typical of MEMS applications, the thickness

Blank device wafer

Handle silicon wafer

SOI film is originally part of the bulk silicon wafer. Cleaning to eliminate particle and surface contaminants.

Serves as a substrate for the SOI wafer. Final cleaning of wafers.

p++ epi

Thermal oxidation

Epitaxial growth of in-situ B-doped epitaxial layer 20 codoped with Ge. Boron concentration ≥1×10 cm–3, and epi layer thickness from 1 to 2 μm.

Thermal oxidation to form an insulating layer that later becomes the buried oxide of the SOI structure.

Second epitaxial layer Epitaxial growth of second lightly doped n- or p-type epitaxial layer over the p++ etch stop layer.

Thermal oxidation Thermal oxidation to form thin thermal oxide over the double epi layer. Thickness 40–50 nm.

Direct bonding and annealing Cleaning, mechanical alignment, and contacting of the wafer pair. High-temperature annealing of the bonded wafer pair.

Device wafer thinning Back-grinding of the device silicon wafer or isotropic etching to rapidly remove >90% of the device wafer.

Etch-back Etch-back to p++ etch-stop layer using alkaline etching solution (KOH, TMAH, or EDP).

Remove etch-stop layer Removal of p++ layer by selective etching, non-selective etching, or reactive ion etching.

Touch polishing and final cleaning Figure 7.21 ● The sequence of steps required to make thick-ﬁlm bonded SOI wafer by wafer bonding and etch-back, according to Ref. [54].

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uniformity is predominantly due to the thickness vari ation that is introduced by the epitaxial growth of the device silicon layer. In BESOI process the crucial step is the formation of the highly doped p

etch-stop layer. With ion implantation it is difﬁcult to provide a dislocation-free substrate for subsequent epitaxial silicon growth, and the threading dislocations propagate freely into the epitaxial device ﬁlm formed on the implanted surface layer [54]. The selective etch solution sets the lower limit for the concentration of implanted boron which in practice is around 1 1020 cm3. Such a high boron dose causes considerable recoil and displacement dam age but is not able to produce an amorphous silicon ﬁlm that could recover almost totally by reconstruction of the amorphous silicon layer. In addition, the thermal anneal times and process temperatures for the oxidation and bonding steps have to be minimized throughout the process in order to keep the implanted transition layer sharp and to prevent the out-diffusion of boron to the top epitaxial silicon layer. What is left is ion implanta tion damage in the form of large residual dislocation loops that are mostly located at the projected range of boron ions and that are impossible to get rid of. The residual defect density can be reduced to the range of 1 104 or 1 105 cm2. The residual defect problem has been overcome by the double epitaxial process described above [54]. With Ge-doping for strain compensation complete absence of misﬁt dislocations has been demonstrated, and essen tially bulk crystalline quality of silicon can be retained. Besides the propagation of misﬁt dislocations into the device layer unless the strain in the heavily boron doped layer is compensated, another issue related to p

etchstop layers is out-diffusion of boron. Low-temperature epi processes have been used to obtain sharp transition of the doping proﬁle in the boron-doped etch-stop layer. It is necessary to have accurate control of the layer thick ness and a low p-type background doping of the device layer. To maintain a sharp etch-stop layer, the maximum temperature in direct wafer bonding is also limited to below 1000°C until the etch-back step in the process. Yet another defect-generation mode that is characteris tic of silicon epitaxy is related to pyramids and spikes on the surface of the epitaxial layer. If the surface con tains spikes from epi growth they invariably cause local noncontacted areas in the bonded interface similar to those induced by large surface particles. It is one of the major yield-determining factors in large-series produc tion of BESOI wafers. Slip dislocation networks have been observed in such regions, indicating that during thermal annealing the stress at the site of the spike can exceed the critical stress for plastic deformation [54]. A much larger area than the noncontacted region can be affected. 130

An example of BESOI wafer speciﬁcation is outlined in Table 7.3. The double epitaxial etch-stop technique can meet the requirements for SOI ﬁlm quality and crystal line perfection as well as the need for accurate control of the SOI ﬁlm thickness in the manufacturing environment. It is possible to consistently achieve dislocation-free SOI ﬁlms and retain the quality of epitaxial silicon crystal. In the lower end of the thickness range the thickness uniformity is related to the selectivity of the etching processes and the sharpness of the transition layers as well as the ﬁnal polishing step. For thicker lay ers, the thickness control of the silicon epitaxy process becomes dominant.

7.6 Techniques Based on Thin-Film SOI and Silicon Epitaxy There are several thin-ﬁlm SOI manufacturing technolo gies. A short description of the most important technolo gies follows.

7.6.1 Smart Cut Process The Smart Cut technology is ﬁrst and foremost applied in large-scale manufacturing of thin-ﬁlm SOI wafers for CMOS applications. With the Smart Cut process the maximum SOI layer thickness is limited to 1.0–1.5 μm. Combined with epitaxial growth of silicon to increase the SOI layer thickness, the technique can be used to manufacture thick-ﬁlm SOI wafers. The process is

Table 7.3 A part of a commercial speciﬁcation for large-series production of BESOI wafers

SOI wafer parameter

Target values

SOI ﬁlm thickness

0.05–20 μm

Thickness tolerance ()

0.05–1 μm

The larger of 2% or 200 Å

1–2 μm

2.0%

2–20 μm

0.5 μm

Wafer diameter

100–200 mm

Stacking faults

10 cm2

Buried oxide thickness

0–3.0 μm

Oxide pinhole density

1 per wafer

Thick-Film SOI Wafers: Preparation and Properties

brieﬂy described below; for more detailed presentation the reader is referred to the review article [55] and the references therein. The Smart Cut process combines hydrogen implan tation and direct wafer bonding. With this method the thinning steps in grind-back and polish SOI or BESOI processes are circumvented by implantation of the seed wafer with hydrogen prior to direct bonding of the wafer. Hydrogen implantation causes splitting of the entire wafer at a depth corresponding to the projected range of hydrogen upon annealing in the temperature range of 400–600°C. Implantation enables a very pre cise control of the top silicon layer thickness from about 20 nm to about 1.5 μm. The SOI layer uniformity can be /50 Å or even better for the lowest ﬁlm thick ness range, with perfectly controllable layer thickness across large-diameter wafers. The wafer bonding proc ess is designed to preserve the original silicon crystal quality and to prevent the blistering or ﬂaking effects that would occur in unconstrained (nonbonded) hydro gen implanted silicon. The key unit process steps of the Smart Cut proc ess include (i) thermal oxidation of the seed wafer, (ii) hydrogen implantation through the oxide into silicon, (iii) cleaning and direct bonding of the seed wafer to the handle silicon wafer, (iv) heat treatment of the bonded wafer pair in the temperature range 400–600°C lead ing to splitting of the seed wafer, (v) high-temperature annealing to form a permanent chemical bond, and (vi) a ﬁnal polishing step to reduce the surface roughness. The key to this process is to provide a mechanical support in the form of the handle wafer bonded to the hydrogenimplanted seed wafer to prevent blistering or ﬂaking. A thermal oxide is grown on the seed wafer, and this oxide later becomes the buried oxide of the bonded SOI wafer. The oxide ﬁlm is effective in reducing the channeling of the hydrogen ions during implantation. Thermal oxidation contributes to the ﬁnal uniform ity of the silicon layer, and therefore optimization of the oxidation conditions is critical. Splitting occurs at a depth corresponding to the projected range of hydrogen ions, and the implantation energy primarily determines the SOI ﬁlm thickness. Typically the smallest hydro gen dose needed for the splitting to occur is from 2 to 5 1016 H /cm2, and higher doses than 2 1017 H / cm2 would lead to blistering already during the hydro gen implantation step. Splitting occurs if the hydrogen dose is over a threshold value, and therefore the thick ness uniformity is not sensitive to the local variation of the dose across the wafer. Bonding of wafers basically follows the process for direct bonding described in Section 7.4. To provide the mechanical support and to suppress the tendency towards blistering, the interfacial bond strength must be sufﬁcient at the temperature at which the splitting

CHAPTER 7

occurs. This is achieved by designing the cleaning and annealing parameters to produce strongly hydrophilic OH-terminated surfaces and to enforce reactions between the OH-groups linked with hydrogen-bridging bonds to form Si-O-Si bonds. Blistering can take place also in local areas if there is no mechanical support due to noncontacted areas that are induced (e.g., by sur face particles). It leads to macroscopic defects where no silicon ﬁlm is transferred. Low-temperature anneal ing in the temperature range of 400–600°C enforces the splitting of the wafers along the hydrogen implanted zone, and a thin silicon ﬁlm on an oxide layer bonded to the handle silicon wafer leads to the SOI structure. A second annealing step is carried out to form a perma nent chemical bond, and annealing parameters (anneal ing temperature 1100–1200°C) commonly used in hydrophilic wafer bonding are applied. The exfoliated silicon surface is rough compared with silicon surfaces polished to electronic grade stand ards. A short polishing step is needed to reduce the sur face roughness of the as-split wafer to correspond to a standard polished silicon surface. Because of the polish ing step the thickness uniformity and the ﬁnal surface roughness are interrelated. In the new process genera tions of Smart Cut wafers with silicon layer thickness in the range of 200–500 Å and below, it appears that the differences derive from the steps used to reduce the roughness of the silicon surface [55]. Splitting of the surface layer occurs by interaction between the microscopic cavities in the implanted layer. Hydrogen implantation produces ﬁne disk-shaped cavi ties that are conﬁned around the maximum hydrogen concentration located at the projected range of hydrogen, with the density of platelets increasing with the hydro gen dose. The hydrogen-induced exfoliation strongly depends on the chemical interaction that is intrinsic of the H–Si system. The detailed picture of the splitting mechanism was obtained on the basis of a combination of microscopic and spectroscopic techniques including TEM, infrared absorption spectroscopy which provides information on the chemical state of hydrogen on ther mal evaluation of implanted silicon, forward recoil scat tering to measure the total amount of hydrogen, and mass spectrometry [55, 56]. The essential microscopic mechanisms behind the splitting process include hydro gen implantation induced damage and formation of point defects, formation of agglomerated defects and internal surfaces upon annealing, build-up of pressure inside the cavities by increasing amount of H2 released into the platelets, and the restoring force provided by the handle wafer that drives lateral crack propagation. Hydrogen implantation induced splitting occurs in different crystal orientations [57]. The kinetics are orientation dependent, the (100) orientation having the highest rate of blistering. The crystal orientation 131

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dependence was correlated with the atomic densities in different crystal planes, but the underlying blistering mechanisms and the activation energies for splitting are similar for (100), (110), and (111) orientations. The time for onset of splitting is shortest for the (100) ori entation and longest for the (110) orientation at a given temperature. This is consistent with the atomic density in different crystal planes, and the number of bonds that need to be broken for splitting to occur is lowest for the (100) plane and highest for the (110) plane. The Smart Cut process is implemented in large-series production of SOI wafers with very thin silicon ﬁlms, mainly for advanced CMOS applications. The target of such development is towards thinner and more uniform SOI ﬁlms. When moving to 65-nm device generations and below, the silicon ﬁlm thickness also needs to scale down. Currently available silicon ﬁlm thicknesses are in the range of 20–50 nm; the energy of hydrogen implanta tion is then in the range of 5–10 keV. The buried oxide also needs to scale down, and currently the oxide thick ness is 100 nm. The uniformity of the silicon ﬁlm is from 2.5% to 5% (6σ level, including all thickness variation). The thickness of the transferred SOI layer is deﬁned by the hydrogen implantation energy, and it can be adjusted in a wide range. In the highest thickness range the silicon ﬁlm thicknesses up to 1.0–1.5 μm are possible. The buried oxide thickness can also be adjusted in a wide range from about 10 nm to several micrometers. Standard bulk silicon wafers are used as the start ing material for the silicon ﬁlm in the ﬁnal SOI wafer, and the quality of the crystal material is deﬁned by the quality of the silicon wafers. Compared to SIMOX the initial damage to silicon is greatly reduced, due to lower damage caused by each implanted atom and the lower dose. For CMOS applications the seed wafer is typically made of silicon material that is free of COP defects (crystal originated particle) that are formed by agglom eration of vacancies during crystal pulling.

7.6.2 ELTRAN Process ELTRAN is another method to manufacture SOI wafers that was originally developed by Canon. ELTRAN wafers are basically BESOI wafers that are formed by wafer bonding and etching porous silicon. In its original form the process involved epitaxial growth of the active sili con layer on porous silicon in a seed wafer, and the etchback of the device wafer was based on the extremely high etch rate of porous silicon [58]. Later the tech nique was developed to include mechanical splitting at the porous silicon layer to transfer the epitaxial layer on the handle silicon wafer and basically to allow the reuse of the seed wafer. The ELTRAN process is brieﬂy described below. For more detailed presentation the 132

reader is referred to the recent review article [59] and references therein. Several special properties of porous silicon are used in the process. One key to the process is to grow a device quality epitaxial silicon layer on top of porous silicon. Annealing in a hydrogen atmosphere seals the surface pores and smoothes the surface of a porous silicon ﬁlm, allowing the growth of high-quality epitax ial silicon on top of it. Second, the porous layer has a large surface area that contributes to its extremely high etching rate. Compared to single crystalline silicon, the selectivity for etching porous silicon can be as high as 105:1. Another special feature is that the bonded wafer can be split within the porous silicon layer by control ling the internal stress to deﬁne the splitting plane. A schematic ELTRAN manufacturing process based on mechanical grinding [58] starts with forming a porous silicon layer on the seed wafer. A porous silicon layer is formed by anodizing in a solution of HF and ethanol. With the single crystal silicon wafer as the anode, microscopic pores with a diameter of a few nanometers are formed on the surface. A typical density of the pores is about 1 1011 cm2. The thickness of the porous layer around 10μm is sufﬁcient to stop the grinding inside the porous layer. The structure of the porous silicon can be controlled by the concentration of the solution and the current den sity, and it also depends on the resistivity of silicon wafer. By a low-temperature (400°C) dry oxidation of porous Si a thin 1–3 nm oxide is formed on the inner walls of the pores. A thin oxide layer preserves the porous structure in subsequent high-temperature processing. Next the wafers are baked at 1000–1100°C in hydro gen ambient in a CVD epitaxial reactor. Baking in hydro gen makes the surface silicon atoms migrate toward the pores to reduce the surface energy. During the prebake the density of the pores on the surface is radically reduced to less than 1 104 1/cm2. During the hydrogen prebaking a small amount of silicon is provided from the gas phase to increase the number of available silicon atoms and to close all of the surface pores. Single crystal silicon ﬁlm is epitaxially grown on the H2 prebaked porous sili con by conventional silicon epitaxy. The epitaxial layer will form the silicon ﬁlm in the SOI wafer. In case of thin SOI layers a thermal oxide is grown on the epi layer, and the oxide ﬁlm becomes the buried oxide layer. The seed wafer containing the porous silicon layer, the epitaxial silicon layer and the thermal oxide ﬁlm is bonded to a second silicon wafer. The direct bonding process of the wafers is basically identical with the proc ess described previously (Section 7.4). The device wafer is removed by surface grinding, leaving a porous silicon layer on the surface. The porous silicon layer is removed by etching, using a solution containing a mixture of HF and hydrogen peroxide. Because of the extremely high selectivity of etching it does not cause any signiﬁcant

Thick-Film SOI Wafers: Preparation and Properties

degradation of the thickness uniformity of the underly ing epitaxial silicon ﬁlm. The high etch rate is explained by penetration of HF/H2O2 into the pores by capillary forces and etching of the walls sideways until the porous structure collapses. The effective thickness of silicon that must be etched is on the order of the thickness of the wall between the pores, which is only around 10 nm. The etch rate of crystalline silicon in HF/H2O2 is actu ally very low due to the low reactivity of H2O2. Similar selectivity cannot be reached with etching solutions such as HF–HNO3–CH3COOH that react strongly with sili con. After etching the surface is microscopically rough with surface roughness around 10 nm. An atomically ﬂat surface is achieved by means of annealing in hydrogen. Annealing in hydrogen ambient at 1000°C reduces the surface roughness to about 0.1 nm which is similar to the surface roughness of polished silicon wafers. With the hydrogen annealing process to reduce the surface rough ness any degradation of the thickness uniformity related to the polishing processes is avoided. The technique was further developed to include reproducible mechanical splitting within the porous Si layer by means of a water jet. Mechanical splitting is based on a porous layer that has two layers of different pore structure. The ﬁrst porous silicon layer on the sur face must have a small pore size to make possible the growth of epitaxial silicon layer. The second porous layer is optimized to form a double layer structure with differ ent pore sizes to deﬁne the splitting plane. The porous structure is controlled by varying the current density during the anodization process, and it is also affected by the porosity and the thickness of the ﬁrst layer. In mechanical splitting the maximum stress is formed in the second layer close to the interface between the two layers. It is possible to consistently split the wafers precisely along the region of maximum stress and to restrict the splitting plane inside the porous silicon layer [59]. With ELTRAN process the SOI layer is formed by epitaxial silicon growth and the buried oxide is formed by thermal oxidation. Therefore, the thicknesses of the silicon layer and the buried oxide layer can be control led independent of each other, and the thickness of the layers can be varied over a wide range. The thickness uniformity of the SOI ﬁlm is deﬁned by the selectiv ity of porous silicon etching, silicon epitaxy, and silicon etching during the hydrogen annealing to reduce the surface roughness, and can be better than /5% also in very thin SOI wafers. The crystal properties of the active layer are based on epitaxial silicon, and low levels of HF defects (0.05 cm2) and density of Secco etch defects in the range of a few hundred per cm2 have been reached. A minority carrier lifetime of a few hun dred microseconds has been obtained, indicating a high crystal quality of the thin SOI layer [59].

CHAPTER 7

7.6.3 Comparison of Different Methods for Thick-Film SOI Wafer Manufacturing for MEMS There are presently several different approaches to SOI wafer manufacturing. Most of them are primarily designed for thin-ﬁlm SOI wafer manufacturing. The approach based on mechanical thinning is distinct from the other meth ods as it is characteristically a thick-ﬁlm SOI technology. However, in all bonded wafers as well as in SIMOX technol ogy, growing thick epitaxial silicon layers is a feasible means of increasing the layer thickness. SIMOX technology has an additional limitation of a maximum buried oxide thickness

400nm, which is very thin for most MEMS applications. The different bonded SOI technologies are brieﬂy discussed as follows, focusing on requirements and speciﬁcation range in typical MEMS applications and distinguishing between the approach that relies on mechanical grinding followed by chemical–mechanical optical precision polishing for the ﬁnal thinning and the thin-ﬁlm techniques. SOI ﬁlm quality and the defect-generating mecha nisms in SOI wafers depend to a large extent on the fabrication method used. In the bond, grind-back, and polish approach the SOI device layer is originally from a bulk silicon crystal. The critical parameter contributing to the defect formation is precipitation of oxygen. The seed wafer is heat-treated two times at a high temperature lead ing to precipitation of oxygen in silicon crystal and to OISF in later thermal oxidation processes unless the silicon crys tal material is picked properly. In all other bonded wafers the resulting thick-ﬁlm SOI device layer is epitaxial silicon. In BESOI wafers the defect-generating mechanisms are related to formation of misﬁt dislocations because of the high boron concentration in the etch-stop layer. Another mechanism for defect generation is surface defects from epitaxial silicon growth, which cause noncontacted areas in wafer bonding with associated local strain ﬁelds. In the ELTRAN process silicon epitaxy on top of porous silicon surface generates crystal defects (e.g., those seen as Secco etch defects). However, with proper defect engineering all aforementioned techniques including SIMOX are able to provide good-quality SOI ﬁlms. The critical processing parameters that contribute to defect generation in the SOI ﬁlm have been identiﬁed and the processes have advanced to the point of consistently achieving very low defect den sities retaining essentially bulk quality. Like the defect-generating mechanisms, SOI ﬁlm thick ness and thickness uniformity depend on the fabrication method of the wafers. In the bond, grind-back, and polish type of approach the process can directly produce any SOI layer thickness from 2 to 100μm. Another charac teristic feature of this approach is that the thickness uni formity is totally independent of the silicon ﬁlm thickness. The capabilities of today’s silicon grinding and polishing 133

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Silicon as MEMS Material

techniques set the lower limit for the SOI ﬁlm thickness and thickness uniformity control around 0.3μm. It is this thickness nonuniformity which in practice sets the lower limit also to the SOI ﬁlm thickness for this tech nology. In all other approaches, in the thick-ﬁlm range typical of MEMS applications (thickness 2μm), silicon epitaxy deﬁnes the SOI ﬁlm thickness. Apart from the lowest thickness range, thickness uniformity of the SOI ﬁlm is also deﬁned simply by the epi process. In ambient pressure high-temperature single wafer epi reactors the overall thickness uniformity in production environment is typically 2% of the layer thickness. Different techniques and mechanical thinning of the SOI layer and those using silicon epitaxy produce similar TTV of the SOI layer in the range of 15–20 μm thick layers. Smaller thickness variation can be obtained by starting with a thin-ﬁlm SOI wafer and then growing a layer of epitaxial silicon if the target SOI layer thickness is below 10μm. In the higher thickness range, latest above 20μm, the situation is reversed and direct mechanical thinning yields smaller thickness variation than any of the other methods. The key process steps of the different methods for manufacturing BSOI wafers are summarized in Table 7.4. The approach that relies on mechanical grinding and chemical–mechanical optical precision polishing for the ﬁnal thinning of the wafer is a straightforward one. It does not require etch-stop layer formation or ion implan tation steps. There is no additional step of growing a layer of epitaxial silicon to increase the SOI ﬁlm thick ness either. Also, it can start from two prime grade pol ished silicon wafers with no additional processing steps other than thermal oxidation prior to wafer bonding, and the process has a smaller number of critical steps that could interfere with the wafer bonding process even if the process for direct bonding is basically identi cal in the different bonded SOI approaches. Also in MEMS the productivity enhancement has been achieved by migrating to the larger diameter wafers. The transfer from 150 to 200-mm wafer size has already occurred in a number of MEMS manufactures. Bonded wafers are all scaled to 200-mm wafer size. In largediameter wafers the approach that starts from Smart Cut SOI and uses epi process to increase the SOI ﬁlm thick ness could have a greater advantage from the fact that reclaiming of the seed wafer in the process is possible.

7.7 Conclusion Direct wafer bonding associated with mechanical thin ning of the SOI layer is a generic technology that enables the fabrication of thick-ﬁlm SOI wafers. It is perfectly adapted to the range of SOI layer thicknesses that are commonly used in MEMS applications. The selection of wafer type is based strongly on the performance versus 134

Table 7.4 Critical unit process steps for the different methods of bonded SOI wafer manufacturing

Method for bonded SOI manufacturing

Key process steps

Bonding, grinding and chemical–mechanical polishing

Cleaning of wafers Thermal oxidation Direct bonding Back-grinding CMP polishing

BESOI

Silicon epitaxy to form etch-stop and active layers Cleaning of wafers Direct bonding Back-grinding/isotropic etching Selective etching step(s) Touch polishing

Smart Cut

Thermal oxidation of seed wafer Hydrogen implantation Cleaning of wafers Direct bonding at RT Annealing to split the wafers (400–600°C) High temperature anneal Touch polishing

ELTRAN

Anodization to form porous silicon Prebake (CVD epi reactor) Silicon epitaxy Thermal oxidation Cleaning of wafers Direct bonding Mechanical splitting of the bonded wafer Selective etching to remove porous Si layer Annealing in hydrogen

The approach relying on bonding, grinding and chemical–mechanical polishing can directly produce any SOI layer thickness 2 μm. In all other techniques growing a layer of epitaxial silicon to increase the SOI layer thickness would be needed.

overall cost per die and should include all aspects for consideration, not just the starting wafer price. Therefore, the choice of material depends strongly on the application and optimization of the cost and perform ance. The prospect of bonded SOI wafers to be used in large-volume applications is being driven by several fac tors. Especially when combined with DRIE, it reduces the size of the sensor elements, enables unique device conﬁgurations, and also reduces steps in the fabrication processes of sensor elements. Enhanced device perform ance affords a further opportunity for SOI in MEMS.

Thick-Film SOI Wafers: Preparation and Properties

CHAPTER 7

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46. P. Mumola, G. Gardobee, T. Feng, A. Ledger, P. Clapis, P. Miller, Plasma-thinned silicon-on-insulator bonded wafers, in: Proceedings of 2nd International Symposium on Semiconductor Wafer Bonding, vol. 93-29, The Electrochemical Society, 1993, p. 410. 47. K. Mitani, M. Nakano, T. Abe, Contribution of polished surface waviness to ﬁnal SOI thickness uniformity of bonded wafers through PACE process, IEICE Trans. Electron. E80-C (1997) 370. 48. Y. Sano, K. Yamamura, H. Mimura, K. Yamauchi, Y. Mori, Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining, Rev. Sci. Instrum. 78 (2007) 086102. 49. C. Clayes, R. De Keersmaecker, G. Declerk, The oxidation process and Si–SiO2 system properties, in: P. Balk (Ed.), The Si–SiO2 System, Elsevier Science Publishers B.V., Amsterdam, 1988. 50. C. Klein, How accurate are Stoney’s equation and recent modiﬁcations, J. Appl. Phys. 88 (2000) 5487. 51. T. Letavic, H. Baumgart, R. Pinker, S. Merchant, E. Arnold, Thermomechanical device processing issues in bonded SOI wafers, in: Proceedings of First International Symposium on Semiconductor Wafer Bonding, vol. 92-7, The Electrochemical Society, 1992, p. 397.

52. W. Maszara, T. Thompson, Strain compensation by Ge in B-doped silicon epitaxial ﬁlms, J. Appl. Phys. 72 (1992) 4477. 53. S. Iyer, E. Bara, M. Mastroianni, R. Craven, Single-etch stop process for the manufacture of silicon-on-insulator substrates, US patent 5494849. 54. H. Baumgart, T. Letavic, R. Egloff, Evaluation of wafer bonding and etch back for SOI technology, Philips J. Res. 49 (1995) 91. 55. G. Celler, A. Auberton-Hervé, B. Aspar, C. Lagahe-Blanchard, C. Meville, Silicon-on-insulator by Smart Cut process, in: M. Alexe, U. Gösele (Eds.), Wafer Bonding, Applications and Technology, SpringerVerlag, Berlin, Heidelberg, 2004. 56. M. Weldon, Y. Chabal, Hydrogeninduced exfoliations of C–Si, in: R. Hull (Ed.), Properties of Crystalline Silicon, INSPEC, The Institution of Electrical Engineers, London, 1999. 57. Y. Zheng, Orientation dependence of blistering in H-implanted Si, J. Appl. Phys. 89 (2001) 2972. 58. K. Sakaguchi, N. Sato, K. Yamagata, T. Atoji, Y. Fujiyama, J. Nakayama, T. Yonehara, Current progress in epitaxial layer transfer, IEICE Trans. Electron. E80-C (1997) 378. 59. K. Sakaguchi, T. Yonehara, ELTRAN technology based on wafer bonding and porous silicon, in: M. Alexe, U. Gösele (Eds.), Wafer Bonding, Applications and Technology, Springer-Verlag, Berlin, Heidelberg, 2004.

8

Chapter Eight

Silicon Dioxides

Simo Eränen VTT Micro and Nanoelectronics, Espoo, Finland

8.1 Introduction

Silicon dioxide is deﬁnitely the most common insulator material in IC technology and in the other ﬁelds of silicon device fabrication technology. The success of silicon diox ide in device applications stems from its chemical stabil ity and today thoroughly known properties. In the early days of microelectronics silicon had to ﬁnd its way against germanium. The natural thermal oxide of silicon was one of the factors in its success. Germanium oxide is water soluble and decomposes at temperatures above 800°C. In device fabrication silicon dioxides enter and are produced in several different ways. For instance, silicon dioxide can be thermally grown on the silicon surface at elevated temperatures utilizing oxygen or water con taining ambient. In this case the growth is based on the chemical reaction between the silicon atoms and mole cules with the oxygen content. On the other hand silicon dioxides can be deposited on various material surfaces in microelectronics from usually silane (SiH4) and oxy gen gas phases utilizing very diverse deposition chemis tries and equipment. As a consequence the rich variety of growth methods for silicon dioxides appear with the spans of, e.g., densities, porosities, stoichiometries, ﬁlm stresses, refractive indices, electrical breakdown proper ties, doping elements, impurities, and etch rates. In modern integrated circuit technology silicon diox ides serve a large number of different functions for the fabrication and ﬁnal device structures. From the fabrica tion point of view the most essential tasks are diffusion, etching, ion implantation masking, silicon surface passi vation, and ion implantation screening. As to the device functions the silicon dioxides serve as the capacitor

dielectrics, the isolations dielectrics for, e.g., the multi level metallization systems, and the ﬁnal passivation lay ers for the ﬁnished devices. For the MEMS fabrica tion and devices silicon dioxides are utilized as for the integrated circuits, but usually the layer thicknesses are larger and in some applications the optical properties must be considered. MEMS applications do not need ultrathin layers like the MOS gate oxides. On the other hand the nearly conformal growth of thermal oxides is beneﬁcial for the three-dimensional structures that are commonplace in the MEMS. However, the relatively high stress of the thermal oxide prevents utilization for the MEMS structure layers in some cases, and, con sequently, for these layers chemical vapor deposition (CVD) oxides are rather the materials of choice. In this chapter the words silicon dioxide and oxide are used interchangeably. For microelectronics devices the desirable thicknesses of the oxides vary over a huge span of several orders of mag nitude. On one hand the ﬁlm thicknesses in the nanom eter scale are required in the leading-edge digital circuits. At the other extreme, today we see emerging MEMS application with oxide layers of even ten micrometers. Figure 8.1 shows an example of the utilization of dif ferent kinds of silicon dioxides for various purposes in the fabrication of MEMS devices.

8.2 Growth Methods of Silicon Dioxide The following paragraphs describe common oxidation processes found in MEMS manufacturing. 137

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Silicon as MEMS Material

Fig. 8.1 ● Example of utilization of different oxides in MEMS fabrication.

8.2.1 Thermal Oxidation

oxidation on silicon 1,00E+01 W <111> 1100ºC

8.2.1.1 Thermal Oxidation Processes

●

●

●

Oxidizing species are transported from the ambient to the surface, where the oxide is growing. Oxidizing species must diffuse through the oxide onto the silicon–oxide interface. Oxidizing species react with the silicon atoms at the silicon–dioxide interface. 138

D <111> 1200ºC 1,00E+00

oxide thickness (microns)

When a silicon wafer experiences an oxidizing ambient at the elevated temperatures the silicon dioxide is chemi cally grown on the surface. The oxidizing ambient is usu ally steam, and the process is known as wet oxidation. If pure oxygen gas is employed, the process is called dry oxidation. The basic oxidation kinetics has been dealt in sev eral textbooks on silicon technology [1]. The model for oxide growth was proposed in 1965 by Deal and Grove [2]. Their model is also known as the linear–parabolic model and it remains the most important description of oxide growth. The name stems from the fact that for thin oxides the ﬁlm thickness increases linearly with time, but for prolonged processes the thickness varies as the square root of time. The model gives a reasonable representa tion of the oxide growth on Si over a wide range of thick nesses, temperatures and oxidant partial pressures. The Deal–Grove approach is based on three basic mechanisms that govern the oxide growth:

W <100> 1100ºC

1,00E-01

1,00E-02

W <111> 900ºC

1,00E-03 0,10

W <100> 900ºC

D <100> 900ºC

1,00 oxidation time (hours)

10,00

Fig. 8.2 ● Dry and wet oxide growth rates (see text for details) on silicon.

Figure 8.2 shows the growth rates of thermal dry and wet oxides as a function of temperature and silicon crystal orientation. The oxidation rate clearly increases with the temperature. Further, at low temperatures the growth rate has pronounced dependence on the crystal orientation of the surface to be oxidized. In addition,

Silicon Dioxides

CHAPTER 8

2250 2000

tox

2000ppm H2O in O2

1750

Oxide Original silicon surface

0.44*tox

d(Å)

1500
1250

Substrate silicon H2O– O2 off

1000 750

980ºC <100> Si H2O– O2 on

500

Fig. 8.4 ● Consumption of Si during the oxide growth. 250 0 0

50

100 150 200 250

300 350

400 450

1 (min)

Fig. 8.3 ● Inﬂuence of moisture on the dry oxide growth rate. Source: Reprinted with permission from ECS—The Electrochemical Society.

the process in steam is 5–10 times faster than in dry oxidation. These observations are the essential parts of the linear–parabolic model and rest on the nature of the basic mechanisms. All the processes involved speed up with the increasing temperature. For thin oxides the growth is controlled by the surface reaction of the sili con atoms with the oxidizing species. The reaction rate depends on the number of the reaction sites and is, consequently, a function of the crystal orientation. For thick oxides the diffusion transport from the ambient to the oxide–silicon interface becomes dominant. For the water molecules the transport seems to be much more ﬂuent than for the oxygen molecules. In Figure 8.2 the text boxes for each oxidation curve indicates the Si surface crystal orientation [(100) or (111)], the oxidation mode (wet W or dry D), and the process temperature. The curves have been calcu lated using the rate coefﬁcients given by S.M. Sze [3]. Of course, wet and dry oxidation are not well-deﬁned concepts, since to some extent water vapor exists every where. It has been shown that even small amounts of water vapor in the oxygen can have drastic inﬂuence on the linear and parabolic oxidation rate constant. This is shown in Figure 8.3 [4].

8.2.1.2 Consumption of Si During Oxidation As described in the Deal–Grove model the oxidation reac tion takes place at the silicon–oxide interface. Thus, when the oxide grows, silicon is consumed and the interface moves into the silicon. Based on the densities and molecu lar weights of Si and SiO2 it is observed that the thickness of the consumed silicon layer is 44% of the total oxide thickness. This is illustrated in Figure 8.4.

8.2.1.3 Dopant Effects The doping elements like boron, phosphorus, and arsenic are inevitably present in the oxidation processes of the silicon devices as the oxide growth consumes silicon material. This fact has inﬂuences on the oxide growth and on the other hand on the element concen tration distribution. Let us ﬁrst consider the doping element redistribution effects. The important parameters here are the element diffusion coefﬁcients in the silicon and the oxide and the segregation coefﬁcient on the oxide–silicon interface. The diffusion coefﬁcient describes the rapidity of the element movement to ﬁnd its thermodynamical equilib rium position. On the other hand, the segregation coefﬁ cient m (ratio of the dopant concentration on the silicon side to the same dopant concentration on the oxide side of the interface) determines the concentrations of the impurities near the interface of the adjacent phases. For instance, if m 1 the doping elements like to reside on the oxide side. Furthermore, if the diffusion in the oxide is low, a high concentration of dopants will be inside the oxide layer. On the other hand, if the dif fusion of the dopant elements is fast through the oxide, the dopants may have a tendency to escape from the oxide into the gaseous ambient. The latter case leads to a low dopant concentration in the oxide and further to the depletion of the silicon surface. In the opposite case m 1 and the oxide rejects the dopants. If now the dif fusion through the oxide is slow, the dopants will pile up on the silicon side. However, if for m 1 the diffusion is fast, the dopants again can escape into the ambient, which results in the silicon depletion of the dopants. The four cases above are schematically described in Figure 8.5 [5]. Here the case A is valid for boron in the oxidizing environment, whereas the case B is for boron in the H2 atmosphere, where the diffusion constant of boron in the oxide rapidly increases. Case C applies for phosphorus and arsenic, and case D for gallium. The presence of a high concentration of the common doping elements is known to enhance the oxide growth. 139

Silicon as MEMS Material

PA R T I

Case 1: Oxide takes up impurity (m < 1) Oxide

10–2

Oxide Silicon

Silicon CB

CB

10–3 B/A(μ/min)

A

10–4

B

(A) Diffusion in oxide slow

B(μ2/min)

(B) Diffusion in oxide fast

Case 2: Oxide rejects impurity (m > 1)

Oxide

1018

1020

1021

CBC(cm–3)

Oxide Silicon

1019

Silicon CB

Fig. 8.6 ● Inﬂuence of the phosphorus doping on the oxidation

rate constants.

CB

Source: Reprinted with permission from ECS–The Electrochemical Society.

for the linear rate constant above the P concentration of 4 1019cm3. C

D

8.2.1.4 Chlorine Effects (A) Diffusion in oxide slow

(B) Diffusion in oxide fast

Fig. 8.5 ● Dopant redistribution in oxide and silicon during high-

temperature processing.

Source: Reprinted with permission from Journal of Applied Physics.

Copyright 1964, American Institute of Physics.

The mechanisms of growth enhancement however, are not the same for all the dopants. For instance, the segre gation coefﬁcient of boron in the silicon–oxide interface is clearly less than unity and the boron atoms tend to pile up into the growing oxide. In practice the concentra tion of boron atoms is a factor of ten larger on the oxide side than on the silicon surface. In the oxide the boron atoms inﬂuence the silica structure, increasing the diffu sion coefﬁcient of the oxidizing species. However, for the effect to be observable the boron concentration in the oxide must be larger than 1020cm3. The other p-type dopants (i.e., Al and Ga) that have high diffusion coef ﬁcients in the oxide do not cause the same effect [6]. For the high surface concentrations of the group V dopant elements P and As the oxide growth rate enhance ment is observed as well. However, the mechanism is dif ferent. Since the oxide rejects the dopants in this case, the growth enhancement is expected in the linear growth regime. Again, for the effect to be visible the dopant surface concentration must be larger than 1019cm3. Figure 8.6 shows the dependence of the oxidation rate constants on the phosphorus doping level of the silicon substrate [7]. Clearly a marked enhancement is observed 140

Most of the modern oxidation furnace tubes are equipped with chlorine chemistry for the cleaning of the quartz ware at high temperatures. The conventional chlorine compounds were Cl2 and HCl, but today organic Cl compounds have gained the dominant role. The chlorine reacts with the metallic impurities creating volatile reac tion products that are swept away to the exhaust from the oxidation tube. It has also been found that the addition of chlorine into oxygen ﬂow in the dry oxidation process has beneﬁcial effects on the oxide quality. For instance, chlo rine improves the dielectric strength, improves the carrier lifetime in silicon, and reduces the oxidation defects and the oxide charges. In addition, in the dry oxidation process chlorine increases the oxide growth rate. Figure 8.7 shows an exam ple of the dry oxide thickness for various O2/HCl mixtures at 1000°C on the 100 and 111 substrates [8]. It is easily seen that the chlorine addition has an inﬂuence on the thin and thick oxides.

8.2.1.5 Pressure Effects—HIPOX The high-pressure oxidation (HIPOX) technique is employed when it is desirable to increase the oxide growth (e.g., for the growth of thick oxides). The other alternative is the wish to maintain the normal growth rate at decreased temperatures. The HIPOX process is usually run in vertical furnaces in the temperature range from 600°C to 1200°C. The operating pressure can be as high as 25 atm.

Silicon Dioxides

A

1.0

B

1.0 (100) Si orientation

Oxide thickness (μm)

(111) Si orientation Oxide thickness (μm)

CHAPTER 8

0.1 = 10% HCl = 5% HCl = 1% HCl = 0% HCl

0.1 = 10% HCl = 5% HCl = 1% HCl = 0% HCl 0.01

0.01 0.1

1.0

10.0

100.0

Oxidation time (h)

0.1

1.0

10.0

100.0

Oxidation time (h)

Fig. 8.7 ● Inﬂuence of chlorine on dry oxide growth rate. Source: Reprinted with permission from ECS—The Electrochemical Society.

The rate constants in the Deal–Grove model depend on partial pressure of the oxidizing species. The linear rate constant depends linearly on the partial pressure, whereas the dependence of the parabolic constant fol lows the law P0.6…0.8 depending on the temperature range and the ambient. For instance, Lie et al. [9] stud ied the dry oxidation of the 100 and 111 silicon in the temperature range of 800–1000°C and pressure range of 1–20 atm. For the linear rate coefﬁcient they found the linear pressure dependence and for the para bolic rate coefﬁcient the P0.7 law. Altogether the oxide thickness has a sublinear dependence on the oxygen par tial pressure, but at 20 atm the gain on the oxide growth rate is of the order of a factor of ten.

8.2.1.6 Oxidation of Polysilicon The polycrystalline silicon—like crystalline Si—forms an oxide layer in the oxidizing atmosphere. This oxide is an important device layer for, e.g., DRAM cells and sev eral surface micromachined devices. The oxidation rate of polysilicon is very much case dependent, but as a rule of thumb, the ﬁrst approximation of the oxidation rate is that of the crystalline silicon with the equivalent proc ess and doping conditions. The other inﬂuencing factors are the grain size and the accompanying stress, dopant type and concentration, and the grain orientation [1]. Probably due to the stress induced by the grain bounda ries the oxidation rate of the polysilicon is initially faster than for the crystalline silicon. However, for the thicker oxides the kinematic rates become equal, because the growth is governed by the diffusion of the oxidizing spe cies through the oxide. Further considerations on the oxi dation of the undoped and phosphorus-doped polysilicon layer can be found, e.g., in Wang et al. [10]. Figure 8.8 shows an oxide layer grown on a borondoped thick polysilicon layer. In this case the polysili con has been grown utilizing a fast deposition process (40 nm/min) at 680°C. Here the oxidation rate is well

Si substrate

Polycrystalline silicon

Oxide

Fig. 8.8 ● A SEM on 300-nm oxide on thick polysilicon.

in accord with the rate of the crystalline silicon with a moderate doping level.

8.2.1.7 Stress in Silicon Dioxide There are two sources of oxide stress in the thermal oxidation processes of silicon surfaces. The ﬁrst one is the so called residual stress that stems from the differ ent thermal expansion coefﬁcients of silicon and oxide. The thermal expansion of silicon is about ﬁve times higher than that of oxide. Thus, during the cool-down period from the process temperature to the room temperature silicon contracts more, which creates a compressive stress on the order of 100 MPa into the oxide layer. The second source of stress is due to the oxide growth mechanism at the silicon–oxide interface. The SiO2 molecules that are formed during the growth have about twice the volume of the original silicon atoms. This causes compressive stress on the order of 700 MPa into the oxide layer. Experiments have shown that this stress component disappears when the temperature is raised 141

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Silicon as MEMS Material

above 965°C. This is interpreted in a way that the oxide layer can perform a viscous ﬂow above that temperature, thus relaxing the stress inside the ﬁlm [1, 11].

Temperature (°C) 1250

80

1200

1150

1100

60

8.2.2 CVD Oxide Growth Methods In semiconductor fabrication various kinds of insulating, semiconducting, and metallic thin ﬁlms are deposited on the substrates via CVD methods. Usually the CVD ﬁlms are amorphous or polycrystalline. In the CVD growth the gases that contain the desired species for the ﬁlm for mation are reacted in the growth chamber and form the target ﬁlm on the substrate. Unlike in the case of the thermal oxide, the CVD ﬁlms do not usually react with substrate. Thus the ﬁlm growth does not consume the substrate and the ﬁlms can be deposited on several kinds of materials. For CVD a large variety of systems that must exhibit economical ways to produce high-quality ﬁlms in terms of, e.g., uniformity, purity, electrical properties, step 142

50

0.5

0.69 eV

40 30 Size of stacking faults (μm)

Like all the high-temperature processing steps, oxidation

tends to introduce defects into the silicon crystal. The

crystallographic defects in silicon are usually quite mobile

at high temperatures and thus their density, distribution, and type will vary due to the subsequent processing steps. Stacking faults are the most important area defects that degrade the performance of the integrated devices. Oxidation-induced stacking faults (OISFs) have been found to be of the extrinsic type, which suggests that the extra lattice plane is formed by the injection of self interstitials into the lattice during the oxidation [1]. Since stacking faults are surrounded by dislocations, the

fast-diffusing (metallic) impurities can be trapped by these dislocations. This is an extra mechanism for the device degradation, since the trapped impurities tend to increase, e.g., the leakage currents. During the oxidation the OISFs can grow as the proc ess proceeds, but under certain conditions the OISFs can be made to shrink as well. Figure 8.9 [12] shows that above the temperature of 1150°C the growth of the stacking faults during dry oxidation stops and the alreadygenerated defects start to dissolve. In addition, the pres ence of the chlorine compounds during the oxidation is shown to reduce the growth of the OISFs. This is due to the vacancies introduced by chlorine. The vacancies serve as the annihilation sites for the excess silicon atoms and thus partly prevent defect formation [13]. The well-known textbook by Ravi [14] displays a rich variety of the OISFs revealed by the preferential etching and microscopy. The same reference gives an in-depth discussion on the growth mechanisms and dynamics of OISFs.

0.4

x

Oxide thickness |100|

0.3

x

20

0.2

x

15

2.3 eV 0.1

10 8

Oxide thickness (μm)

8.2.1.8 Oxidation-Induced Defects in Silicon

6 5 4 |100|

|111|

5° Off |100|

3 2 0.64

0.66

0.68 3

0.70

0.72

0.74

–1

10 / T(°K )

Fig. 8.9 ● Dynamics of OISF growth.

Source: Reprinted with permission from Journal of Applied Physics.

Copyright 1975, American Institute of Physics.

coverage, and adhesion are employed. The science and technology of CVD includes special knowledge in sev eral ﬁelds of science and engineering like chemistry, thermodynamics, plasmas, gas dynamics, RF aspects, vacuum technology, and mechanical design. In 1966 Grove developed a simpliﬁed model for the deposition of the CVD ﬁlms [15]. The model includes aspects that are similar to those of the Deal–Grove model for thermal oxidation, like the diffusion transport of the reactant species over the boundary layer from the gas phase to the substrate surface. In the CVD case the reac tants form precursors—sometimes called adatoms—that undergo surface migration to the surface sites, where the ﬁlm growth takes place. After the reaction the byprod ucts are transported away from the site to the outlet of the process chamber. Usually the low-pressure CVD (LPCVD) processes run under the surface reaction lim ited mode, where the surface reaction has the Arrhenius type temperature dependence exp(–Ea/kT), Ea being the activation energy. In order to guarantee the uniform ﬁlm growth, it is essential to ensure a uniform temperature over all the substrate surface. Then the arrival rate of the reactant species at the wafer surfaces is not as important,

Silicon Dioxides

CHAPTER 8

CVD processes

Low pressure

Atmospheric

Tube reactor (LPCVD)

Showerhead reactor (SACVD)

ALD reactor

Plasma reactor (PECVD)

ALD

Plasma ALD

Tube (batch)

Epitaxial reactor

Single wafer

Tube reactor

Planar reactor

Barrel (Batch)

Pancake (batch)

Single wafer

Pancake (batch)

Pancake (minibatch)

Fig. 8.10 ● Types of CVD reactors.

since usually the reactor design can guarantee sufﬁcient gas feed at all the important locations of the chamber. For the atmospheric pressure CVD (APCVD) processes the reverse is true. In the mass-transport limited processes like APCVD the temperature control is not so critical. All the reactant species arriving at the substrate surface will take part in the ﬁlm-forming reaction [1]. CVD reactors come in several different designs. The reactors can be of the cold or hot wall type, which means that the reactor walls are either at a lower tem perature than, or at the same temperature as, the wafers. Secondly, the reactor can work at the atmospheric pres sure range (APCVD) or at reduced pressure on the order of 10 mtorr to 1 torr. And, ﬁnally, for the LPCVD systems the energy for the growth reaction is either purely thermal or enhanced with a plasma source. The latter type of reac tor is called a plasma-enhanced CVD (PECVD) system. Figure 8.10 summarizes the types of CVD reactors.

8.2.2.1 CVD Oxides The Chemical Vapour Deposition (CVD) of the sili con dioxides takes several approaches in silicon device manufacturing, where these ﬁlms are utilized to accom plish a large number of different functions. For MEMS devices the most important ones are cavity liners, deep silicon etch masking, trench and hole ﬁlling, sacriﬁcial layers, passivation, and optical tuning layers.

One of the most popular oxide CVD processes is the so-called low-temperature oxide (LTO). This process is based on the reaction of silane (SiH4) and oxygen in order to form an oxide layer at relatively low tempera tures. The process temperatures can vary over a con siderable span from 200°C to 450°C depending on the reactor type, since this deposition process may be per formed in the APCVD, LPCVD, or PECVD systems. An alternative chemistry for the CVD oxide deposi tion is offered by the TEOS systems. TEOS—also known as tetraethyl orthosilicate Si(OC2H5)4—is a liquid com pound that is usually delivered into LPCVD equipment using the nitrogen bubbler. The reaction temperature is higher than for the LTO (around 700°C), but the ben eﬁt is more conformal ﬁlms than in silane chemistry. An extra beneﬁt is the added safety of the processing. The TEOS processes are employed in the PECVD reac tors, as well. In this case the deposition temperatures are below 450°C and the conformality of the ﬁlms is superior compared with that of the silane-based processes. A fur ther approach utilizing the TEOS process is to add ozone (O3) into the TEOS vapor in the APCVD processes. As shown in Table 8.1 one of the aspects of CVD dep osition of the oxides is the possibility of doping the grow ing oxide with network-forming elements (see paragraph 8.3) like boron and phosphorus. For this phosphine and diborane are the most common source gases. The addition of phosphorus into the CVD oxide forms phosphosilicate 143

Silicon as MEMS Material

PA R T I

Table 8.1 Deposition conditions for several CVD oxides

Growth temperature (°C)

Growth rate

Reactants

LPCVD TEOS

680–730

25 nm/min

TEOS

APCVD

250–450

1 μm/min

SiH4 and O2

PH3/B2H6

PECVD

200–400

SiH4 and N2O/NO SiH4 and O2

PH3/B2H6

PECVD TEOS

250–425

800 nm/min

TEOS

TMP/TMB

LPCVD

400–500

300 nm/min

SiH4 and O2

PH3/B2H6

Ozone TEOS

300–400

200 nm/min

TEOS and O3

TEOP/TMB

AP-PECVD

300–500

20 nm/min

HMDSO and O2

glass (PSG). The dopant concentrations are usually rela tively high, reaching a few weight percentages. This results, e.g., in reduced stress and improved step coverage (see paragraph 2.3). An important feature of PSG is the opportunity to ﬂow the material at elevated temperatures (above 1000°C), which leads to the improved surface topography. Adding boron into the PSG will form boro phosphosilicate glass (BPSG) with a lower ﬂow tempera ture than for PSG. The comparison table above summarizes the growth parameters of the various CVD oxides.

8.2.3 Multidimensional Effects So far the oxidation effects on planar surfaces have been considered. In the silicon technology there are, however, a vast number of cases where the oxide layers must be formed on the vertical walls and over the convex or con cave corners in the device structures, where the two- and three-dimensional phenomena become effective. These are common in a huge number of MEMS structures and also in IC devices, including, e.g., the trench capacitors of memory devices and the shallow trench isolation tech nology. A well-known example of the multidimensional effects is the formation of the “bird’s peak” during the LOCOS isolation in CMOS processing. Here the active area of the transistor is protected by a nitride layer during the growth of the thick ﬁeld oxide [16]. The nitride layer effectively stops the diffusion of oxygen species through the ﬁlm, thus preventing oxide growth on the active area. The oxygen can, however, diffuse sideways around the edge of the nitride pattern and form a tapered oxide layer under the outer rim of the nitride. The growth of the thermal oxide on the vertical and horizontal surface is generally understood to take place in 144

Doping

a similar fashion. Consider for instance a thermal oxida tion process on a cavity with vertical walls that has been etched into the silicon substrate. After the process the oxide thickness is equivalent on the horizontal and ver tical surfaces, if the crystal orientations are identical. At the corners, however, the situation is different. The oxidation species have different opportunities to diffuse through the oxide layer in order to react with fresh silicon depending on whether the corner is convex or concave. Consequently, it is expected that the oxide thickness at the concave corners is thinner than at the convex corners. In fact, the situation is more complicated with aniso tropic stress and temperature-dependent oxidation rates. So if the oxide thickness is critical for the device opera tion, each case should be studied three-dimensionally on an individual basis (Figure 8.11) [17, 21]. For CVD oxide ﬁlms the conformality on the surface topography is an important ﬁgure of merit, as well. In practice, people speak about the “step coverage”, which means the ratio of the ﬁlm thicknesses on the vertical and horizontal surfaces. The step coverage of the CVD ﬁlms depends on the interplay of several factors like the arrival angle of the reactants on the speciﬁc point of the substrate surface, the sticking coefﬁcient, and the sur face transport of the precursors on the surface [1].

8.3 Structure and Properties of Silicon Dioxides The thermally grown silicon dioxide on silicon is amor phous (i.e., noncrystalline). The noncrystalline phase likes to develop towards the thermodynamic equilib rium structure (i.e., the crystalline quartz). This proc ess is known as the devitriﬁcation, and the speed of the

Silicon Dioxides

CHAPTER 8

Fig. 8.11 ● Thermal oxide on convex and concave corners.

process is temperature dependent—approaching zero below 1000°C. In several cases the devitriﬁcation is a problem, for instance for the furnace hardware, but it is not usually observed in the device fabrication, because in these cases the high-temperature treatments are much shorter than for the furnace hardware. The structural models for the amorphous silicon dioxide have been explained, e.g., by Revesz [18]. The basic struc tural unit of the silicon dioxide is a tetrahedron formed by a silicon atom and four oxygen atoms. The silicon atom sits in the center of the structure and is chemically bonded to the oxygen atoms in the four corners of the tetrahedron. The oxygen atom has two valence electrons, and thus it has a possibility to form a bond to the silicon atom of the neighboring tetrahedron. Since the oxide is amorphous, all of the oxygen atoms do not form bonds between the adjacent structural units. Consequently, depending on the bonding state of the oxygen atoms, they are referred to as bridging or nonbridging oxygen. The amorphous structure forms a more open network and thus the density of the oxide is less than the crystalline form (i.e., the quartz). Figure 8.12 shows the basic, two-dimensional model of the silicon dioxide as described by Revesz [18]. The structural unit is shown as a triangle. In addition, the picture shows several possible defects in the structure. Further, structural defects (impurities)—substitutional or interstitial—can be present. In modern technology the most important substitutional impurities are boron and phosphorus replacing silicon atoms. These impu rities can be the core of glassy structures and are thus named as the network formers.

Table 8.2 gives an indication of the basic physical prop erties of silicon dioxide. These values apply to the ther mally grown oxides. With the various CVD oxides the situation becomes more complicated, since these may depend on the growth conditions and the subsequent thermal history of the layer. For instance, the CVD oxides deposited at low temperatures have lower density and varying indices of refraction, stoichiometry, and stress. In addition, the etch rates may increase in the standard processing conditions. However, as a rule of thumb the properties of the CVD oxides approach those of the ther mal oxides, when the post-growth annealing tempera tures are approaching the values of the thermal oxidation. Moreover, the PECVD deposition processes may result in additional impurities like hydrogen in the oxide layers.

8.4 Processing of Silicon Dioxides The preceding sections have concentrated on the various aspects of the growth and deposition of silicon dioxides. The present section touches on topics of oxide process ing, cleaning and etching.

8.4.1 Cleaning Usually in microelectronics fabrication the wafer-

cleaning steps are performed before the high-temperature,

layer deposition and/or lithography process steps. The

145

Silicon as MEMS Material

PA R T I

Legend: Si network former Acceptor type network former or intermediate Donor type network former or intermediate Bridging oxygen Non-bridging oxygen Bridging oxygen vacancy (vob)

~

Individual non-bridging oxygen vacancy (vo )

nb ~

~

Non-bridging oxygen interstitial

(associated with the network) (oi,a)

Individual interstitial oxygen

(not associated with the network) (oi)

Univalent anion (e.g., OH– ) in the position of

non-bridging oxygen

Interstitial cation (network modifier or

+

intermediate), e.g., Na Interstitial cation (network modifier or

intermediate), e.g., Ba++

Fig. 8.12 ● A basic two-dimensional model of the silicon dioxide as described by Revesz [18]. The basic tetrahedrons are shown as triangles. Source: Reprinted with permission from IEEE Transactions of Electron Devices, Copyright 1965 IEEE.

Table 8.2 Properties of silicon dioxide Dielectric constant

3.9

Thermal conductivity (W/cm2 °C)

0.014

Breakdown ﬁeld (MV/cm)

6

Thermal expansion coefﬁcient (ppm/°C)

0.05

Density (g/cm3)

2.27

Melting point (°C)

1700

DC resistivity (ohm/cm)

1016

Molecules/cm3

2.3 1023

Energy gap (eV)

9

Refractive index

1.46

intention of the cleaning is to remove particles and pho toresistant residues, metallic impurities, and organic contamination. Usually, in the course of growing fresh oxides or depositing oxide layers on nonmetallic ﬁlms (oxide, polysilicon, silicon nitride), a so-called standard clean (SC) sequence is employed. This consists of three steps usu ally named as SC1, DHF, and SC2. The alkaline SC1 bath is a mixture of hydrogen peroxide and ammonium hydroxide diluted in the DI water. The classical blend is 1:1:5 (NH4OH:H2O2:H2O), but many other blends, especially towards the decreasing reactant concentra tions, have been employed. Here, however, the balance between H2O2 and NH4OH has to be maintained in order to avoid increasing surface roughness of the sili con surface [19]. Normally, the SC1 bath temperature is between 40°C and 80°C. The aim of the SC1 steps is to attack the particles and organic contamination. The DHF (dilute hydroﬂuoric acid) step is applied in order to remove the chemical oxide that grows in the 146

SC1 bath. Here the wafers are immersed into a diluted, room-temperature HF solution for a short time. The last SC2 process targets at the metallic impurities. The bath is a water mixture of HCl and H2O2 at an elevated temperature. The SC2 is important for many active devices like transistors, because the metallic impurities tend to degrade the device performance. However, for MEMS devices, where the metallic impurity contamina tion can be tolerated, the DHF and SC2 can be skipped in several occasions. Another acidic clean that is effective against organic contaminants and metallic impurities is the so-called Piranha solution. The bath consists of a hot (110°C) mixture of H2SO4 and H2O2, and the most frequent use is against the badly damaged photoresists after the plasma etching or ion implantation. When metallic layers—usually aluminum—have been deposited and patterned on the wafers, the aggressive alkaline or acidic baths can no longer be applied. In sev eral fabrication processes, however, the PECVD layers

Silicon Dioxides

or LTO oxidations are needed on the metallization. In these cases usually solvent cleanings using IPA or ace tone are employed.

8.4.2 Etching Etching is a method for the material removal in many industrial processes. In microelectronics fabrication there must exist processes to selectively etch practically all the materials involved in the fabrication ﬂow. That is, there must be a masking material that is relatively insensitive to the etching process. This material covers the chip sites that should not be etched. In addition, the etching proc ess should not be too aggressive for the materials that lie under the layer to be etched. The etching of silicon dioxide has traditionally been done using wet chemicals like HF or BHF/BOE (buffered hydroﬂuoric acid/buff ered oxide etch). In most cases the photoresist serves as the masking material, but for the very thick oxide layers (2 μm) the silicon nitride is preferable. Usually, the oxide wet etching is done employing near-room-temperature processing. For HF etching the etch rate depends on the concentration of the etchant in the water. In order to form the buffered solution, ammonium ﬂuoride (NH4F) is added to the HF bath in order to reduce the attack against the photoresist mask ing layer. NH4F particularly helps to avoid the delamina tion of the photoresist mask on the oxide surface, which decreases the etch undercut below the masking layer. In practice the concentration of HF varies in a large range from 1% to 49% in DIW. The high concentra tions are employed in order to achieve high etch rates (1 μm/min), but the disadvantage is the photoresist delamination. On the other hand, diluted HF baths are for the native oxide removal and silicon surface treat ments. The BOE baths can provide moderate etch ing rates that depend on the ratio of the NH4F to HF concentrations. For instance, the ratio (NH4F:HF) 7:1 at room temperature results in an etching rate of about 100 nm/min. Etching with the HF or BHF solutions stops at the Si– SiO2 interface, and usually there is no risk of the increased Si surface microroughness. However, if the etchant solution is contaminated with metallic ions with a high

CHAPTER 8

electronegativity, like copper, there is a chance that the silicon surface will experience pitting corrosion [19]. Due to the amorphous structure of the silicon diox ide the wet etching is isotropic (i.e., the etching pro ceeds in each direction at the equivalent rate). Thus the etching inﬂuences the dimensions of the layer under the masking material, too. This may create a problem when the size of the etch patterns are shrinking. When the thickness of the ﬁlm to be etched becomes close to the size of the lateral dimension of the ﬁlm pattern, the undercutting due to the isotropic wet etching cannot be accepted. This means that below the feature size of a few microns wet etching calls for an alternative process ing scheme. This anisotropic mode is offered by socalled dry etching that is based on the plasma physics at reduced pressures in the RF-powered reactors. For dry etching in wafer fabrication the reaction cham bers vary a lot in the geometrical conﬁguration, pressure range, materials, RF-coupling mode and etchants that are fed into the chamber in the gaseous phase [1]. For dry etching of silicon dioxide, ﬂuorine-containing molecules such as CF4, SF6, NF3, and CHF3 are normally employed. Other gases like O2, Ar, and He can be added, e.g., for heat transfer, plasma, stabilization, and enhanced ioniza tion. Typical etch rates for the oxides are in the range of several hundred nanometers per minute. Contrary to the wet etching several additional aspects must be consid ered for the dry process. These include the selectivities or etch rates of the etching process to the masking layer (photoresist) and to the materials underlying the oxide ﬁlm. Typical values are 10:1, meaning that the oxide layer is consumed ten times faster than the other materi als. Further, the degree of the anisotropy or the lateral etch rate and the side wall proﬁle must be taken into account. In several cases the etch rate depends on the area to be etched. This is the so-called loading effect. A recommended introduction to these effects can be found in a book by Wolf and Tauber [1]. A recently developed alternative for the oxide etching is HF vapor etching, which is especially suitable for the dry, stiction-free release processes of MEMS structures. This process combines anhydrous HF gas-phase etching with alcohol vapor at reduced pressure [20]. The spe cial feature of the process is the selectivity against other common materials, including aluminum.

References 1. S. Wolf, RN. Tauber, Silicon Processing for the VLSI ERA, second ed., Lattice Press, 2000. 2. B.E. Deal, A.S. Grove, General relationship for the thermal oxidation of silicon, J. Appl. Phys. 36 (1965) 3770.

3. S.M. Sze, Semiconductor Devices. Physics and Technology, John Wiley & Sons, 1985. 4. E.A. Irene, R. Ghez H.R. Huff, E. Sirtl (Eds.), Semiconductor Silicon, The Electrochemical Society, 1977, p. 313.

5. A.S. Grove, O. Leistiko Jr., CT. Sah, Redistribution of acceptor and donor impurities during thermal oxidation of silicon, J. Appl. Phys. 35 (1964) 2695. 6. B.E. Deal, M. Sklar, Thermal oxidation of heavily doped silicon, J. Electrochem. Soc. 112 (1965) 430.

147

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Silicon as MEMS Material

7. C.P. Ho, J.D. Plummer, J.D. Meindl, B.E. Deal, Thermal oxidation of heavily phosphorus-doped silicon, J. Electrochem. Soc. 125 (1977) 665. 8. D.W. Hess, B.E. Deal, Kinetics of the thermal oxidation of silicon in O2/HCl mixtures, J. Electrochem. Soc. 124 (1977) 735. 9. L.N. Lie, R.R. Razouk, B.E. Deal, High pressure oxidation of silicon in dry oxygen, J. Electrochem. Soc. 129 (1982) 2828. 10. Y. Wang, J. Tao, S. Tong, T. Sun, A. Zhang, S. Feng, The oxidation kinetics of thin polycrystalline silicon ﬁlms, J. Electrochem. Soc. 138 (1991) 214. 11. E.P. EerNisse, Stress in thermal SiO2 during growth, Appl. Phys. Lett. 35 (1979) 8.

148

12. SM. Hu, Anomalous temperature effect of oxidation stacking faults in silicon, Appl. Phys. Lett. 17 (1975) 165. 13. C.W. Pearce, V.C. Kannan, Saucer pits in silicon, in: Defects in Silicon, The Electrochemical Society, Pennington, NJ, 1983, p. 396. 14. K.V. Ravi, Imperfection and Impurities in Semiconductor Silicon, John Wiley & Sons, Inc., 1981. 15. A.S. Grove, Mass transfer in semiconductor technology, Ind. Eng. Chem. 58 (7) (1966) 48. 16. J.L. Fay, J. Beluch, B. Despax, G. Sarrabayrouse, Feasibility of an isolation by local oxidation of silicon without ﬁeld implant, Solid State Electron. 45 (2001) 1257.

17. D-B. Kao, J-P. McVittie, W.D. Nix, K. C. Saraswat, Two-dimensional thermal oxidation of silicon-II, modeling stress effects in wet oxides, IEEE Trans. Electron Devices ED-35 (1988) 25. 18. A.G. Revesz, The defect structure of grown silicon dioxide ﬁlms, IEEE Trans. Electron Devices ED-12 (1965) 97. 19. T. FutatsukiT. Hattori (Ed.), Ultraclean Surface Processing of Silicon Wafers, Springer, 1988. 20. W.I. Jang, C.A. Choi, M.L. Lee, C.H. Jun, Y.T. Kim, Fabrication of MEMS devices by using anhydrous HF gas-phase etching with alcoholic vapor, J. Micromech. Microeng. 12 (2002) 297. 21. M. Radi, http://www.iue.tuwien.ac.at/ phd/radi/

9

Chapter Nine

Multiscale Modeling Methods

Teruaki Motooka Kyushu University, Fukuoka, Japan

9.1 Macroscopic and Microscopic Equations In order to analyze the characteristics of MEMS devices, it is usually good enough to use macroscopic or classical equations. For example, mechanical and electromagnetic properties can be respectively described by the Navier’s equation d

∂2 u ∂t 2

∇× c∇u F

(9.1)

and the Maxwell’s equations ∇× D ρ

(9.2)

∂B ∇ ×E ∂t ∇× B = 0

(9.3) (9.4)

and ∇× H = j +

∂D ∂t

(9.5)

Here, in the Navier’s equation u is the displacement vector, (∂/∂r in the Cartesian coordinate system) represents the nabla operator, F is a body force, d and c are the material parameters; density and elastic con stant (generally tensor), respectively. In the Maxwell’s equations, D is the electric displacement vector, E is the electric ﬁeld vector, B is the magnetic ﬂux density, H is

the magnetic ﬁeld intensity, ρ and j are the charge den sity and current density, respectively. These vectors are related with the material parameters (dielectric con stant), μ (magnetic permeability), and σ (electric con ductivity) as follows: D E, B μH, and j σE. In these classical equations, the physical quantities can be deﬁnitely determined as a function of space r and time t. Materials are made by huge numbers of atoms com posed of nuclei and electrons. Electron is one of the most important elementary particles and its motion is governed by the Schrödinger equation which is the basic equation in the microscopic or quantum mechani cal world. For example, the Schrödinger equation of an atom with the atomic number Z can be written as ⎤ ⎡ 2 Z ⎛ 2⎞ Z e2 ⎥ ⎢ � ⎜⎜∇2 Ze ⎟⎟

⎥ ⎢ ⎟⎟ ∑ ∑ i ⎜ ri ⎠ i j ri rj ⎥ ⎢ 2m i1 ⎜⎝ ⎣ ⎦ × Ψ(rr1 ,r2 ,…,rZ ) EΨ (r1 ,r2 ,…,rZ )

(9.6)

where m and e are the electron mass and charge, respec tively, h indicates the Dirac constant, �i is the nabla operator on the i-th electron at the position ri. This is the typical eigenvalue problem. In the left-hand side, the Hamiltonian operator composed of the kinetic energy, attractive potential energy with the nucleus positioned at the center, and repulsive potential energy of the electron system operates on the wavefunction Ψ(r1, r2,…, rz) as the eigenfunction. In the right-hand side, E represents the energy of the atom as the eigen value of the Hamiltonian operator. It should be noted that, in the microscopic world, all physical quantities are operators operating on wavefunctions and the observed values are the eigenvalues of these operators. Since the 151

Modeling in MEMS

PA R T I I

wavefunction is generally superposed by various eigen functions corresponding to each operator, the physical quantity is, unlike that in the macroscopic or classical world, not deterministic, but probabilistic depending on the wavefunction at the time of observation. It is sometimes necessary to analyze MEMS charac teristics not only in the macroscopic scale (typically m size) but also in the microscopic scale (typically nm size). A typical example is the analysis of the I-V characteris tic of a nanopore device for DNA molecular sensing [1]. Figure 9.1 shows a schematic diagram of this device which is generally operated by measuring the reduc tion of K and Cl ionic currents through a nanopore in a solid-state membrane separating two Teﬂon cham bers containing solutions of electrolyte and DNA. DNA molecules are driven from the cis to trans sides through the nanopore by an applied voltage between two elec trodes set apart at a macroscopic distance, typically mm scale. On the other hand, the current reduction is due to DNA translocations at the nanopore. Thus, in order to theoretically obtain the I-V characteristic, it is neces sary to solve appropriate equations in both macroscopic and microscopic scales. One of the basic equations is the Poisson equation,

∇× ε∇ϕ(r ) ρ(r )

where ϕ(r) is the electrostatic potential (ESP) deﬁned as the potential energy of a test unit charge at the posi tion r. Equation 9.7 is deduced from Eq. 9.2 by using the relations E �ϕ and D E ( is generally ten sor and depending on r.) If is a scalar constant, Eq. 9.7 is reduced to a more familiar form, �2ϕ –ρ/. In the classical theory, the potential energy of a sin gle electron at the position r can be expressed as –eϕ(r) by using ESP. However, in the microscopic theory, Eq. 9.7 is only an approximation. For example, the electron potential energy in a many-particle system such as in the atom described earlier is not only a function of r but also depends on the coordinates of the Z-electrons V(r,r1 , r2 ,… ,rZ )

Z Ze2 e2

∑ r i1 r rι

K

Cl

+

K Cl–

Cl– SiO2

A

Si

ssDNA–

Teflon

trans side

V K+

Cl–

Cl–

Fig 9.1 ● Schematic diagram of a DNA microscope. A singlestranded DNA (ssDNA) is translocated through a nanopore.

152

(9.9)

+

–

cis side

(9.8)

In order to solve Eq. 9.7, the electron poten tial described in Eq. 9.8 is averaged over the electron motions with the coordinates r1, r2, …, rz. This can be performed in the framework of the quasi-classical approximation [2] based on the one-electron model in which each electron independently moves in an aver aged potential ﬁeld made by the other electrons. After rather lengthy mathematical manipulations including the determination of the electron charge density ρ(r) by using one-electron wavefunctions, this approach results in the Thomas-Fermi equation ∇2ϕ(r ) C[ϕ(r )]3 / 2

K+

(9.7)

where C is a constant and excellent results are known to be obtained for heavy atoms. A less accurate but more practical approach is usually taken to solve the multiscale problem illustrated in Figure 9.1. For example, M.E. Gracheva et al. [3] treated the DNA transloca tion through the nanopore by using molecular dynamics (MD) simulations, while the Poisson Eq. 9.7 was solved classically but self-consistently by taking account of charge variation in the electrolytic solution due to the existence of the DNA in the nanopore region. Finally, it would be interesting to compare macro scopic and microscopic capacitors. The electrostatic energy stored in a macroscopic capacitance C is Q2/2C (Q: stored charge), while it becomes e2/C for charging single electron (e: electron charge) on a microscopic capacitor such as a quantum dot. In the macroscopic case, charge Q can be stored in capacitance C through an integration of inﬁnitesimally small amount of charge dQ, which gives rise to the factor 1/2. On the other hand, in the microscopic case, the charging process must be discrete in the unit of “quantum of charge”, that is, electron charge e. Exact quantum mechanical

Multiscale Modeling Methods

analysis for putting multiple electrons in a quantum dot is very difﬁcult due to the interactions between many electrons and an appropriate approximation such as the independent-electron model is usually employed for practical calculations.

CHAPTER 9

of linear equations can be written in matrix form if we number the two-dimensional grid points (j,k) in a single one-dimensional sequence by deﬁning i j(K 1) k for j 0,1,…,K and k 0,1,… , M (9.14) and introducing vectors Ui and Bi made from ϕj,k and ρj,k, respectively. Now, Eq. 9.13 can be transformed into

9.2 Computational Methods Macroscopic or classical equations described earlier are partial differential equations (PDEs). Practically, PDEs can be classiﬁed into the boundary- and initial-value prob lems and are numerically solved by using digital comput ers. Here, only the basic ideas for numerical calculations of PDEs are described. More details can be seen in the standard text books, for example, Numerical Recipes: The Art of Scientiﬁc Computing (Press, 2007) [4]. First of all, an appropriate discretization of all continu ous variables r and t as well as the dependent variables must be performed for the numerical treatment. As an example of boundary-value problems, let us consider the two-dimensional Poisson equation in the Cartesian coordinate system ∂ 2ϕ( x, y ) ∂x

2

∂ 2ϕ( x, y ) ∂y 2

ρ( x, y )

ε

(9.10)

Assuming a rectangular region 0≤x≤Lx and 0≤y≤Ly, the dependent variable ϕ(x,y) is represented by the val ues at the discrete set of points x j jΔ,

j 0,1, 2,… ,K

(9.11)

U i M 1 + U i( M 1) U i 1 + U i1 − 4U i = Bi (9.15) which gives rise to a matrix equation AU B

(9.16)

where the matrix A is known and generally called “trig onal with fringes” and the vector B is also known includ ing the given boundary values. The unknown vector U is formally written by A1B and can be numerically calcu lated by using various computer routines. As an example of initial-value problems, let us con sider the one-dimensional wave equation with propaga tion velocity v along the x-axis: ∂ 2 u( x, t ) ∂t 2

v2

∂ 2 u( x, t ) ∂x 2

The independent variables 0≤x≤L and 0≤t can be discretized as x j jΔx,

j 0,1, 2,… ,K

t n nΔt, n 0,1, 2,…

and y k kΔ, k 0,1, 2,… ,M

(9.12)

where is the grid spacing (K Lx and M Ly ). Based on the ﬁnite-difference method for the secondorder derivatives of function ϕ(x,y), Eq. 9.10 can be reduced into the system of linear equations: ϕ j 1,k ϕu j,k ϕ j1,k Δ2

ρ j ,k

ϕ j,k 1 ϕu j,k ϕ j,k1

(9.17)

(9.18) (9.19)

where Δx (KΔx L) and Δt are the space and time steps, respectively. Based on the ﬁnite-difference method for the second-order derivatives, a system of linear equations similar to Eq. 9.13 is obtained: u n 1 2u nj u n1 j j (Δt)2

2

v

u nj 1 2u nj u nj1 (Δx)2

(9.20)

Δ2

ε (9.13)

where ϕj,k ϕ(xj, yk) and ρj,k ρ(xj, yk). In addition to the linear Eq. 9.13 for ϕj,k, the bound ary conditions must be taken into account. For exam ple, in the Dirichlet boundary condition, ϕj,k has been speciﬁed at the boundary points deﬁned by j 0, j K, k 0, and k M. Thus, the unknown values of ϕj,k are for j 1, 2, …, K–1 and k 1, 2, …, M–1. This system

where ujn u(xj,tn). A similar matrix equation like Eq. 9.16 for boundary-value problems can be deduced from Eq. 9.17 and B includes the given initial values for initial-value problems. Especially, for numerically solving the time-dependent Maxwell equations, the ﬁnite difference time-domain (FDTD) method is useful. Various free software programs are available, for example, at http://ab-initio.mit.edu/wiki/index.php/Meep [5]. In the FDTD method, the leapfrog scheme is usually used to simulate time evolution. This scheme is widely used for numerical calculations of many-particle systems. 153

Modeling in MEMS

PA R T I I

In order to show the basic idea of the leapfrog scheme, let us consider the Newton equation describing the movement of the planets [6]. d 2ri (t ) dt

2

G∑ m j i≠ j

ri (t ) rj (t ) ri (t ) rj (t )

3

(9.21)

where ri(t) and mi are the position vector at t and mass of the i-th planet, respectively, and G is the universal gravitational constant. The movement of the i-th planet can be numerically calculated in the leapfrog scheme as follows:

ai (tn ) G∑ m j i≠ j

ri (tn ) rj (tn ) ri (tn ) rj (tn )

3

vi (tn Δt2) vi (tn Δt2) ai (tn )Δt ri (tn Δt) ri (tn ) vi (tn Δt2)Δt

(9.22) (9.23)

tn + Δt/2

x tn–1

Fig 9.2 ● The leapfrog scheme.

154

x tn

t tn+1

HC ESC

(9.25)

where H is the Hamiltonian matrix, S is the overlap matrix, and E is the energy eigenvalue. As an applica tion of the Gaussian03 program for the analysis of a nanopore DNA microscope described in Figure 9.1, the calculated molecular orbital energies of the adenosine, a construction unit of DNA molecules and its dimer dApA made by using a phosphate and terminating at the sites of 5 and 3 are shown in Figure 9.4 [9]. This dimer has odd-number electrons and thus spin-polarized or open-shell calculations were carried out. There exist two kinds of molecular orbitals: that is, α or up-spin

(9.24)

As illustrated in Figure 9.2, the position vector at tn 1(tn Δt) is calculated by that at tn and the velocity vi at tn Δt/2 which is determined by that at tn Δt/2 and the acceleration ai at tn. Besides the ﬁnite-difference method described ear lier, the ﬁnite element method (FEM) is also very popu lar for solving PDEs. In the FEM, discretization is ﬁrst performed by the following process: (1) The continu ous space region of the problem is divided by a set of elements such as triangles and curvilinear polygons. (2) Appropriate basis functions such as piecewise lin ear and polynomial functions are chosen in these ele ments. Then the dependent variables are expanded by these basis functions which results in a matrix equa tion for the expansion coefﬁcients. More information including a commercial package for FEM simulations is available, for example, at http://www.femlab.com/ [7]. Figure 9.3 shows the ESP and electrostatic energy den sity calculated by the FEM for the DNA sensing device illustrated in Figure 9.1. FEMLAB [7] was employed for solving an electrostatic problem based on the macro scopic Maxwell equations described in Section 9.1. The idea of the basis-function expansion is widely used in microscopic or quantum mechanical calcula tions. One of the very popular software packages is Gaussian [8] in which Gaussian-type functions are tn – Δt/2

employed to expand electronic wavefunctions for atoms and molecules. The column vector C made by the expansion coefﬁcients can be determined by solving the matrix equation in the Hartree–Fock–Roothaan method

Fig 9.3 ● Calculated ESP ϕ and electrostatic energy density We. It is assumed that the device (see Figure 9.1) is axial-symmetric and the cell is ﬁlled with water ( 78.4). The top and bottom electrodes are set at –1 and 1 V, respectively. In this model, the Si part in the middle is considered to be also an electrode and the voltage is set at 0 V. Both the contour map of ϕ (1 to –1 V) and color map of (1.44 108–1.92 1017 Joule/m2) indicate that the electric ﬁeld is strongly concentrated in the region near the nanopore. (This ﬁgure can be viewed in colour on the book’s companion website (http://www.elsevierdirect.com/ companions/9780815515944)

Multiscale Modeling Methods

and β or down-spin orbitals. For these relatively large molecules, the geometry optimization was at ﬁrst per formed by using the Hartree–Fock method with the 3-21G* base set. Then, the MO energy levels were cal culated by using the 6-31G(d) Gaussian basis functions and Becke’s three-parameter density-functional formu lation (B3LYP) for the optimized structure. Quantum mechanical calculations described earlier are practically impossible to apply for MEMS systems where a huge number of atoms are involved. One of the most popular methods to simulate atomic-scale behav iors of many-atom systems is MD simulations. In the MD method, atomic or molecular motions are analyzed

CHAPTER 9

by solving the Newton equation. Let us consider, as an example, the system composed of N Si atoms. The classical motions of these atoms are described by the position vectors r1(t), r2(t),…, rN(t) at t and these are determined by solving the N Newton equations m

d 2ri (t ) dt 2

Fi (r1(t), r2(t),… , rN (t))

(9.26)

here m is the mass of the Si atom, 4.66 1026 Kg and Fi is the force working on the i-th atom. In the ﬁrst-principle MD method, Fi is calculated by solving the Schrödinger equation for electrons in the Si atoms, but this approach

Fig 9.4 ● Molecular orbital energies of deoxyadenosine and its dimer dApA. It is noted that the gap between the highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) becomes much smaller upon dimerization. Source: Taken from Ref. [9]. Also in colour on companion website.

Fig 9.5 ● Snapshots of atomic conﬁgurations during nucleation and crystal growth under a symmetric temperature gradient as shown in the top panel: (a) t 0 ns, (b) t 15 ns, (c) t 21 ns, and (d) t 24 ns. These snapshots were obtained by projecting the atomic coordinates in the central 10-Å thick region including the diagonal (110) plane of the MD cell on the (110) plane. Bottom panel shows a magniﬁed view of the enclosed region in the top panel: (a) t 15 ns, (b) t 17 ns, (c) t 19 ns, and (d) t 21 ns. Source: Adapted from Ref. [13].

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is only possible for small systems with at most 1000 Si atoms. For larger systems composed of more than 1000 atoms, Si empirical potentials V(r1(t), r2(t),…, rN(t)) such as the Tersoff [10] and Stillinger-Weber [11] poten tials can be employed and Fi is calculated as F i ∂V(r1(t), r2(t),…, rN (t))∂ri

(9.27)

Note that the existence of electrons is neglected and the force is completely determined by the posi tions of atoms or more exactly nuclei in these empirical potentials. Since MEMS devices are working under a certain temperature and pressure condition, it is better to carry out MD simulations under the same temperature and pressure conditions. The details of these techniques can be seen, for example, in the standard text book [12]. An example of MD simulations of crystallization processes of supercooled liquid Si under a certain temperature condition using the Tersoff potential is shown in the top

panel in Figure 9.5 [13]. Although the Tersoff potential gives rise to high melting temperature near 2550 K, it can well reproduce crystallization processes in solid and liquid Si. Thus, it is considered to be useful to describe nucleation and crystallization processes in Si. A rectan gular MD cell with size of 48.9 48.9 97.8 Å3 includ ing 8192 Si atoms was ﬁrst melted completely at 3000 K for 10 ns (Figure 9.5a). Nucleation ﬁrst occurs at the lower temperature region (Figure 9.5b) and then crys tallization proceeds toward the high-temperature region (Figure 9.5c). The crystalline front-end hits the bottom of the MD cell and then crystallization continues to the top region (Figure 9.5d) due to the periodic bound ary condition. It is remarkable that the (111) surface of the crystallite is predominantly parallel to the z-axis or direction of the temperature gradient. This can be attributed to (1) the trend that the solid/liquid Si inter face is stabilized by forming {111} facets and (2) tem perature dependence of the crystallization velocity.

References 1. C. Dekker, Solid-state nanopores, Nat. Nanotechnol. 2 (2007) 209–215. 2. A.B. Migdal, translated by Leggett, A.J., Qualitative Methods in Quantum Theory, W.A. Benjamin, Inc., 1977. 3. M.E. Gracheva, A. Xiong, A. Aksimentiev, K. Schulten, G. Timp, J.-P. Leburton, Simulation of the electric response of DNA translocation through a semiconductor nanopore– capacitor, Nanotechnology 17 (3) (2006)622–633. 4. W.H. Press, S.A. Teukolsty, W.T. Vetterling, B.P. Flannery, Numerical Recipes: The Art of Scientiﬁc Computing, third ed., Cambridge University Press, 2007.

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5. MIT Electromagnetic Equation Propagation, http://ab-initio.mit.edu/ wiki/index.php/Meep 6. Department of Computer Science,

Princeton University, http://www.

cs.princeton.edu/introcs/94diffeq/

7. COMSOL, http://www.femlab.com/ 8. M.J. Frisch, G.W. Trucks, H.B. Schlegel et al. Gaussian 03, Revision D.01, Gaussian, Inc., Wallingford CT, 2004. http://www.gaussian.com/ . 9. T. Motooka, H. Ueda, K. Harada, M. Fukuda, Electronic structures of DNA molecules and their alignment control on Si(100) substrates with onedimensional lattices, Sci. Technol. Adv. Mater. 7 (2006) 705. 10. J. Tersoff, Empirical interatomic potential for silicon with improved

elastic properties, Phys. Rev. B 38 (1988) 9902. 11. F. Stillinger, T. Weber, Computer simulation of local order in condensed phases of silicon, Phys. Rev. B 31 (1985) 5262. 12. D. Frenkel, B. Smith, Understanding Molecular Simulation, Academic Press, 2002. 13. T. Motooka, S. Munetoh, Moleculardynamics simulations of nucleation and crystallization in supercooled liquid silicon: temperature-gradient effects, Phys. Rev. B 69 (2004) 073307.

10

Chapter Ten

Manufacture and Processing of MEMS Structures Miguel A. Gosálvez Laboratory of Physics, Helsinki University of Technology, Espoo, Finland

10.1 Introduction

The manufacture and processing of MEMS structures is generally referred to as micromachining. It consists of the sequential realization of material deposition, patterning and etching processes that incrementally modify the substrate and/or a multilayer structure on it in order to realize three-dimensional shapes with spe ciﬁc electromechanical functionalities, as discussed in Chapters 22 through 29 of Part IV of this book. Through the years, the set of micromachining proc esses has grown into a mature toolbox offering numer ous alternatives depending on the application and material requirements. In surface micromachining, as an example, the growth of different layers of silicon nitride, oxide, and carbide; metals such as aluminum, copper, titanium, and tungsten; or polymers such as photoresist and polyimide, can be achieved by several methods, including epitaxial growth, thermal oxida tion, sputtering, evaporation, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), spin-on deposition and/or sol-gel dep osition. Some of the ﬁlms are deposited as structural layers, becoming an integral part of the micromachined structure with speciﬁc mechanical, electrical, optical, or thermal properties. Others, however, are sacriﬁcial, eventually removed after serving their purpose tempo rally. Anodic bonding, silicon bonding, and silicon fusion can be used to bring two different substrates together, serving as extreme examples of material deposition before or after other processing steps. Similarly, par tial or total removal of the grown ﬁlms and/or material from the substrate can be achieved by several methods, including isotropic and anisotropic wet etching as well

as dry etching, typically in the form of plasma etching, reactive ion etching (RIE), and deep reactive ion etching (DRIE, also known as the Bosch process). For the reali zation of both growth and etching, selective masking is routinely performed, restricting the material deposi tion and/or removal to carefully chosen regions of the substrate and/or the multilayer structure. This is done by using various patterning techniques, such as optical, X-ray, and electron beam lithography. Although the general concept of modeling the pre vious variety of deposition, patterning, and etching processes has been discussed already almost 20 years ago in the OYSTER, MEMCAD, and other projects [1–4], the realistic simulation of the micromachining of MEMS structures has become progressively pos sible only during the last 10 years [5, 6]. Currently, major software companies such as Coventor Inc. [7] and IntelliSense Software Corp. [8] offer products that enable the micromachining of MEMS structures almost completely virtually in a personal computer. By simply providing a list of the required mask layouts and cor responding lithography processes together with the list of the different material deposition and etching steps, these programs will automatically generate the resulting MEMS structure using a database of material properties and process parameters. Furthermore, the programs can perform a complete thermal, optical, and/or electro mechanical ﬁnite element analysis (FEA) of the result ing MEMS structure, enabling the characterization and comparison of different versions of a device even before stepping into a clean room. Other companies, such as SoftMEMS [9], are trying to position themselves in the MEMS design market, while some projects, such as BICEPS3 [10, 11] or the nationwide Japanese 157

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MemsONE [12], are trying to provide competing—yet affordable—toolboxes for the modeling of microfab rication and multiphysics analysis of the constructed MEMS structures. In this chapter we are concerned with the simulation of micromachining, while the ﬁnite element analysis of the MEMS structures is considered in other chapters. We will present an overview of the currently available simulators, centering mostly on the modeling of aniso tropic etching due to the special challenges posed by this technique as well as its overall importance and gen eralizability, as described below. We will describe the major features of the simulation methods ﬁrst, proceed ing then to present the simulators themselves, including commercial and free tools.

10.2 Requirements for Modeling Micromachining 10.2.1 Database

The simulation of the different micromachining proc esses is possible only if a comprehensive database of different material properties and process parameters is available. As an example, the purely vertical deposi tion of a desired thickness of a material layer on a ﬂat substrate is a simple computational mask, requiring only the addition of a corresponding number of rows to a computational array. However, assigning realistic elec tromechanical properties to the layer—also computa tionally straightforward—can only be done if a database can be used. Companies focused on the modeling of MEMS, such as Coventor and IntelliSense [7, 8], need to provide extensive micromachining databases to ena ble a realistic representation of each modeled layer and, thus, their complex combination to produce MEMS devices. The need for a comprehensive database is shared by many research groups, and open organizations such as the MEMS and Nanotechnology Clearinghouse [13] provide an open material database which can be completed and/or modiﬁed by the members.

10.2.2 Anisotropy When the material is deposited on a non-ﬂat multilayer structure, the propagation of the micromachined sur face may signiﬁcantly depart from vertical growth only. Depending on the actual growth method, the amount of (i) conformal deposition over the vertical and horizontal features of the interface and (ii) shadowing effects by the vertical features may become relevant. As an exam ple, metal deposition by evaporation is known to suf fer from poor step coverage, while sputtering typically 158

results in a more conformal ﬁlm growth, although some thinning is observed at the steps. The realistic propagation of the micromachined sur face becomes especially complex for those micromachin ing processes whose evolution rate depends strongly on the direction of propagation. As an example, wet etching of silicon in alkaline solutions can be strongly anisotropic, as discussed in Chapter 24 of this book. This means that the etch front propagates vertically with a different rate than horizontally and, in fact, the etch rate is different for any pair of directions. As a result, fast etch planes appear at the convex corners of the masking patterns and slow etching planes appear at the concave features. The propagation of the etch front in the presence of a mask becomes highly nontrivial even for a completely ﬂat initial substrate, making anisotropic etching difﬁcult to grasp intuitively. Often regarded as one of the biggest challenges in the modeling of micromachining—even bordering on the black arts—the complexity has led to the development in many companies of secretly kept etch recipes after numerous trial and error tests. Due to the challenges associated with the modeling of etching and its widespread use—grossly accounting for one third of the main micromachining technologies of deposition, patterning, and etching—this chapter will focus mainly on the description of the simulation meth ods for wet etching. In principle, the vertical, conformal, and/or shadowed deposition of material layers can be realized using similar methods.

10.2.3 Morphology An additional ingredient for the modeling of microma chining is the description of the changes induced in the surface morphology during deposition and etching. As an example, the deep vertical walls realized by the Bosch process are typically characterized by scalloping proﬁles. Similarly, anisotropic etching can lead to rugged, stepped morphologies due to the misalignment between the mask and the silicon wafer. And other defects such as pyrami dal and trapezoidal hillocks; zigzag patterns; and round, triangular, or hexagonal pits can appear on the etched surfaces, affecting the electromechanical functional ity of the structure. Thus, being able to simulate these features simultaneously to the overall propagation of the etch front has become a requirement for the realistic simulation of a MEMS structure. As described later, the simulation and understanding of many of these features has been enabled by the use of atomistic simulators.

10.2.4 Compatibility Since MEMS devices are built to perform certain opti cal, thermal, and/or electromechanical functions, it

Manufacture and Processing of MEMS Structures

is desirable to enable the analysis of these properties already at an early stage when only the computational model of a MEMS structure exists. The analysis is typi cally done using ﬁnite element methods (FEM)—or ﬁnite element analysis (FEA)—numerically solving the corresponding coupled thermal, electromagnetic, and electromechanical differential equations. Thus, the com putational model of the micromachined structure needs to be as compatible as possible with the FEM model to avoid possible feature loss during conversion. In this respect, the use of atomistic unit-cell-based methods during the modeling of micromachining provides certain advantages as the cell-nodes can be directly used for the volume and surface creation of the FEM meshes.

10.3 Micromachining As a Front Propagation Problem From the point of view of performing simulations, the previous deposition, patterning, and etching processes share a fundamental feature, namely, that each microma chining process results in the three-dimensional propaga tion of the material surface and/or interface. As a result, the evolving surface may be thought as a complex propagating front, with constituent parts that may split and/or join during one or several stages of the microma chining sequence and typically featuring a multi-valued height proﬁle. Traditionally, the propagation of such fronts is modeled by placing markers (or nodes) along the boundary region and advancing each node in the normal direction accord ing to the local value of the propagation rate, for example, the deposition or etching rate, available from experi ments, interpolations, or physical models [14, 15]. The major drawback of the marker method is that the nodes need to be added, removed, and redistributed along the boundary periodically in order to handle the splitting and joining of the separate parts of the front, resulting in a computationally time-consuming procedure—especially for surface fronts in three dimensions—that is also char acteristically complex from a programming perspective. An alternative to the use of markers is the Level Set method [15]. A typical deposition/etch front in threedimensional space is considered as the zero isosurface of a hypervolume in 4D. More generally, an n-dimensional front is represented as the zero-level set of points of an (n 1)-dimensional function, known as the Level Set function, ϕ. Typically, the extra dimension of ϕ is cho sen to describe the signed distance from any point in the n-dimensional space to the front [14]. The idea is to prop agate the Level Set function in time and to recover the front by extracting the zero level set of points at every time step. Thus, the evolving front is deﬁned as the set � � of points {r } such that φ(r(t ), t ) = 0. Using the chain

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rule, this expression is rewritten in differential form as the Level Set equation [14]: (∂φ /∂t) + R |∇φ|= 0, where R is the propagation rate in the normal direction of the front. This partial differential equation can be numerically solved using ﬁnite difference methods [14, 16]. The most valued feature of the Level Set method is the ability to describe natively the splitting and join ing of different parts of the front by avoiding an explicit treatment of the boundary, which is the problem of the marker methods. However, the Level Set method features a strong dependence on the full knowledge of the propagation rate R at any point and direction in n-dimensional space, requiring the use of an extensive database for the simulations or, alternatively, a suitable physical model to determine the values—or at least an interpolation scheme that makes use of a reduced number of data points to calculate the rest. Although the Level Set approach has been used for the simulation of deposition, etching, and lithography processes [15] and has been applied to the complex case of anisotropic etching [16], much work is still needed to demonstrate that it can rival the geometric and atomistic methods presented in Sections 10.4 and 10.5. Another alternative for the propagation of an inter face is the Phase Field method [17, 18], where the markers and their dynamics are substituted by a par tial differential equation for an auxiliary ﬁeld known as the Phase Field, reminiscent of an order parameter that takes different values in each phase (e.g., 1 and 1) and changes smoothly across the interface, which is modeled to have a ﬁnite (nonzero) width. Different terms can be used in the equation in order to reproduce the interfacial dynamics of the simulated system, typi cally including surface and/or bulk diffusion, concen tration and temperature gradients, viscous terms, etc., and occasionally involving additional equations for some of the observables. The resulting Phase Field equations are typically solved numerically using ﬁnite differ ence discretizations and integrated in time using either explicit or implicit algorithms. As with the Level Set method, the Phase Field models also provide a suitable approach to describing the splitting and joining of the different parts of the interface. Although the method has been successfully applied to solidiﬁcation and frac ture dynamics in metals and alloys, it has not been used to address the propagation of the processed interface in micromachining, remaining unclear whether its use would be practical. For the particularly complex case of anisotropic etch ing the etch front is characteristically facetted and the use of a marker method will result in groups of nodes being placed on the same facet plane, consequently following the same displacement for each time incre ment. This makes it possible to focus on the propagation of the facets themselves instead of the markers, justifying 159

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the introduction of the so-called geometrical method [19–23]. Although described thoroughly in Section 10.4, the essential idea is to abstract the facetted etch front as a set of two fundamental polygons—the upper and lower contours of the front—propagating the upper contour segments horizontally along their normal direc tions while advancing the lower contour segments according to a combination of the motion of the evolv ing ﬂoor and the side-wall facets. The difﬁcult task in this approach is to compute the change in the geometry at each contour corner where two consecutive segments meet, requiring the use of the Wulff-Jaccodine method described in Section 10.4. Although the appearance and disappearance of new/old side-wall facets can be suc cessfully monitored if the time increments are small enough, the results are typically compromised in sys tems where the etching facets can intersect in compli cated ways, which is the same problem faced by any marker-based method. As an alternative to the geometrical, Level Set, and Phase Field methods, one can use a fundamentally dif ferent approach based on an atomistic description of the propagating front. Presented in Section 10.5, the idea of the atomistic methods is to represent the surface by a collection of atoms or cells, similar in spirit to the use of markers but fundamentally different from these in two ways: (i) The surface atoms in the front are part of a larger structure, namely, the bulk of the material, also made of atoms. This is contrary to the markers, whose introduction deﬁnes an isolated region represent ing the front. As a result, the atomistic methods enable a natural description of the splitting and joining of dif ferent parts of the propagating front, also allowing the formation of multi-valued height proﬁles natively. (ii) The surface atoms are not displaced in order to propa gate the front but, instead, the surface sites are (gradu ally) ﬁlled or emptied to represent the advancement of the interface. This is again contrary to the markers, which are themselves propagated in space according to speciﬁc equations of motion. Correspondingly, the nec essary complete knowledge of the propagation rate and direction required to displace the markers is replaced by local growth and/or etch rates for the surface sites, thus reducing the number of data points needed in order to calibrate the atomistic simulations. In addition, the atomistic methods can be seen as particular reali zations of the Phase Field and Level Set methods. As an example, when the ﬁlling and emptying of the sur face sites is performed gradually, the atomistic method represents effectively a phase ﬁeld model whose ﬁeld value changes smoothly between the two extreme val ues across the interface (i.e., empty versus full). In this way, the atomistic methods have positioned themselves as the most suitable alternative for the accurate descrip tion of micromachining as a front propagation problem. 160

10.4 Anisotropic Etching: Geometrical Simulators Many tools have been developed for the simulation and understanding of anisotropic etching. Traditionally, a distinction is made between the geometric (or macro scopic) and atomistic (or microscopic) simulators. The geometrical simulators have primordially focused on the prediction of the propagation of the etch front in silicon micromachining applications. In addition to the descrip tion of the three-dimensional etch front, the atomistic simulators have also focused on the understanding of the changes in the etched surface morphology. The geometrical simulators [19–23] are based on the assumption of an underlying velocity ﬁeld that deter mines the amount and direction of motion for each point on the surface. Since many points belong typically to the same plane (or facet), they can be simultane ously treated by describing the etch front as a collec tion of facets. The idea is to discretize time into small time steps and to propagate each facet along its normal, according to the experimentally measured etch rate. As it turns out, the reduction from points to facets can be further simpliﬁed to two fundamental polygons, as shown in Figure 10.1: (i) the upper contour, contain ing the upper edges of the side walls in contact with the masking layer (i.e., the contour of underetching), and (ii) the lower contour, corresponding to the lower edges of the side walls in contact with the etched ﬂoor. Additionally, one or several cross-section contours may be considered. The upper and lower contours—also referred to as polygons—are completely horizontal while the cross-section polygons are completely vertical. For the upper contour, each side of the polygon is identiﬁed with a crystallographic plane {hkl}, cor responding to a side wall making an angle α{hkl} with the horizontal plane. Each polygon side is advanced horizontally along its normal direction by an amount Δt ⋅ R{hkl} cosα{hkl}, where Δt is the time increment and R{hkl} cosα{hkl} is the projection of the etch rate of {hkl} on the horizontal plane. The change in geometry at each polygon corner is more complicated than a simple intersection of the propagated sides. It is determined using the Wulff–Jaccodine method, which minimizes the surface energy by minimizing the contour perimeter. At each corner, one considers the set of tentative displace ment vectors corresponding to the etch rates (multiplied by Δt) for all horizontal directions between the polygon sides that share the corner, as shown in Figure 10.1c. Each displacement vector is associated with an inﬁnite straight line perpendicular to the displacement vector and passing through the end point of the displacement vector. The new polygon is determined as the set of straight lines and their intersections, which minimizes

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Fig 10.1 ● (a, b) Upper and lower contours used in the geometrical method, showing two cross-sections (B’B’’ and C’C’’). (c) WulffJaccodine method applied to point A (horizontal propagation of upper contour). (d, e) Side view of cross-sections B’B’’ and C’C’’. (f, g) Wulff-Jaccodine method applied to points B and C (propagation in vertical plane). Source: After [19, 23].

the perimeter of the polygon. In this way, some planes may appear while others disappear. In order to monitor the changes in the facets and maintain the accuracy of the simulation, small time steps and depth increments are used (typically, Δt 30 s and Δh = 1μm ). A similar propagation method is applied to the lower polygon, with the exception that the advancement of each polygon side is generally a combination of the etch rates of the ﬂoor and the lower facet of the corre sponding side wall. Once the upper and lower polygons have been propagated, the side wall facets are calcu lated from the available top and bottom polygon sides. If the time increments are small enough, this allows for monitoring of the appearance or disappearance of side wall facets. The same method can be applied for verti cal cross-sections, taking into account that some of the polygon sides are effectively pinned if they are parallel to and in contact with a mask. Examples are shown in Figures 10.1d–g.

In order to obtain the possible displacement vec tors correctly, it is important to select the proper set of crystallographic directions and corresponding etch rates (multiplied by Δt) in the proper crystallographic zone. As an example, Figure 10.1f displays the relevant Δt-scaled etch rates for the 〈010〉 crystallographic zone, while Figure 10.1g shows the relevant rates for the 〈110〉 zone. Note that the propagation of the crosssection polygons is not used as an aid for improving or modifying the propagation of the overall etch front given by the upper and lower contours, but as an addi tional analysis tool. The geometric simulators can successfully describe the propagation of the etch front in complicated geometries. Examples of commercially available simu lators are SIMODE from Amtec GmbH, Germany [24], originally developed by Frühauf and co-workers at the University of Chemnitz, Germany [19]; and FabMeister-ES from Mizuho Information & Research 161

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Institute, Inc., Japan [25], formerly known as MICROCAD, originally developed by Koide and co workers at Hitachi Ltd. [22], Asaumi, and co-workers at Fuji Corp. [23], and Sato and co-workers at Nagoya University [26, 27], Japan. These programs can typically produce simulation results within seconds or minutes, depending on the mask layout, number of time steps, and computer architecture. However, their perform ance is compromised in complex undercut geometries such as those for closely spaced mask windows, where the etch fronts may intersect in a complicated manner. In addition, etching of both top and bottom sides of the wafer poses a difﬁcult challenge as the advancement of the upper and lower polygons becomes nontrivial. The major drawback of the geometric simulators is the need for a full orientation-dependent etch rate data base [26–28]. This is required in order to extract the relevant rates for applying the Wulff–Jaccodine method, depending on the crystallographic zone and the involved polygon sides, as depicted in Figure 10.1. The larger the number of measured etch rates for different sur face orientations, the more displacement vectors can be used, improving the accuracy of the simulations. Even if the propagation of the etch front is, wisely, reduced to the propagation of the upper and lower contours, the geometrical method can be described as some kind of “brute force” approach due to the use of hundreds or even thousands of etching rates. In the atomistic methods, however, the emphasis is placed on reducing the amount of required experimental information to a handful of etch rates.

10.5 Anisotropic Etching: Atomistic Simulators There are two types of atomistic simulator, depend ing on the actual method used for advancing time. The Cellular Automata (CA) methods provide a determin istic, mean-ﬁeld propagation of the interface. They are characterized by a Constant Time Step (CTS) dis cretization of time and a Decide and Perform (D&P) updating scheme consisting of two system-complete evaluation loops inside each time step. In the ﬁrst pass, the algorithm decides which processes need to be real ized and, in the second, the selected processes are performed—effectively realizing them simultaneously (or in parallel). This is shown in Figure 10.2a. On the other hand, the Kinetic Monte Carlo (KMC) methods provide a completely sequential, always stochastic prop agation of the interface. They are based on the use of a single evaluation loop that performs each event as soon as it is decided (Figure 10.2b). In both KMC and CA implementations the atoms of the surface are visited one by one and their neighborhoods 162

are inspected in order to determine the removal rate, deciding whether the atom is removed or remains attached. The essential difference between the methods is that KMC removes each atom as soon as its removal has been decided, while CA ﬁrst determines all the atoms that need to be removed and then removes them simultaneously. Thus, in KMC there is always a small time interval (Δt/N) between two consecutive proc esses, while in CA many processes can take place simul taneously and the time interval is between different groups of processes. In a way, KMC is more atomistic than CA. As a result, KMC is more suitable for under standing the development of morphologic features, such as hillocks, pits, or meandering steps, while CA is more suitable for mean-ﬁeld descriptions, such as the propa gation of the etch front in the wet micromachining of a MEMS structure, where the atomistic nature is less important than the overall average behavior.

10.5.1 Cellular Automata A cellular automaton is a discrete model of the physi cal system consisting of an n-dimensional lattice whose nodes, cells, sites, or atoms can be present in one of many states, where “many” can also be inﬁnite. Based on the current state and number of neighboring sites, the state of each site changes after every time step by applying the same set of rules to all sites simultaneously. A simple example is given in Figure 10.2a. For the simulation of etching one distinguishes between the Discrete Cellular Automata (DCA) and the Continuous Cellular Automata (CCA). They dif fer in the number of states available for each atom site. In DCA the sites have only two states, either occupied (1) or empty (0). For CCA the sites can be partially occupied, leading to inﬁnite occupation values in the continuous range [0,1]. Correspondingly, the atomistic removal rates are either 1 or 0 for the DCA method, but they can take any value in the range [0,1] for CCA. The continuous range of values for the occupa tion of the sites and the removal rates makes possible an improved representation of smooth variations along the direction perpendicular to the surface, enabling the description of continuous motion of the interface in the CCA method. In this respect, the CCA method is very similar to a Phase Field model of the interface, with the continuous occupation of the sites assuming the role of the phase ﬁeld. There is a third type of CA, which can be referred to as a Stochastic Cellular Automaton (SCA). As for DCA, the sites are either occupied or empty, with no other intermediate state. However, the simultaneous removal of identical surface atoms is decided stochas tically according to removal rates that can take any

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CA t + Δt

t Probe N processes Visiting the cells randomly or sequentially is equivalent

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Fig 10.2 ● (a) Decide and Perform loops inside each time step of a CA simulation. (b) Single loop for each time step of a KMC simulation (simple Metropolis version). At time t a stepped surface with a pit is depicted. The processes considered are cell removals. A simple rule is applied consisting of the removal of step cells only.

value in the range [0,1], as for CCA. In a way, SCA is a hybrid between DCA and CCA, having also features that resemble the KMC method. For this reason, the SCA method will be presented after the KMC methods at the end of Section 10.5.2.

Discrete Cellular Automaton (DCA, or BCA Basic Cellular Automaton) The orientation dependence of the etch rate of silicon can be described by a Discrete Cellular Automaton (DCA) that uses a simple choice of atomistic rates, as introduced by Than and Büttgenbach [29]: The removal rate of any surface atom is 1, except for the atoms with three bulk neighbors—characteristic of the stable {111} surface—for which the removal rate is 0. This describes anisotropic etching as a sequence of collective removals where all the current surface atoms are removed simulta neously in each time step—except for the {111} atoms. The method is graphically described in Chapter 24,

Section 24.2.4.1 of this book. DCA is also referred to as the Basic CA method or BCA. Due to the geometrical differences between the dif ferent crystallographic planes at the atomistic scale, the previous rule (i.e., removing every atom except the 111 terrace atoms) results in a different etch rate for each surface. Taking the unit of time as 1 and a as the lattice parameter of the conventional unit cell of silicon, one gets (Section 24.2.4.1): R111 0 , R110 a/(2 2 ), R100 a/4 , R311 a/ 11 , R211 a/(2 6), and similarly for other orientations. The general trend in the dependence of these etch rates with orientation happens to be in good qualitative agreement with some experi ments, such as etching in potassium hydroxide (KOH) at medium concentration, as shown in Figure 10.3a. The BCA method captures the global and local minima and maxima at {111}, {110}, {100}, and {311}, respec tively. However, it cannot describe other etchants, such as the case where R110 R100 , since BCA is limited to the ﬁxed value of R110 /R100 2 . In fact, the rates of 163

Modeling in MEMS

PA R T I I

any one pair of orientations are ﬁxed by the underlying geometry and the given rule, and their relative values can not be tuned to match an experiment. It is only possible to shift up or down the whole set of etch rates for cali bration purposes, typically matching the rate of {100}. In anisotropic etching it is well known that the crystal facets appearing on the etched structures correspond to the slowest etching planes for concave geometries, such as cavities or trenches enforced by using masks, and the observed facets correspond to the fastest etched orien tations for convex shapes, such as the convex corners of square – island masking patterns or the overall surface of a spherical specimen. Due to this feature and the fact that the DCA method reproduces approximately the orienta tion dependence of the minima and maxima in the etch rate, the use of this method can provide a rather realistic picture of the propagated etch front, as shown in Figure 10.3b, c. The micro-needles in Figure 10.3b serve as an example of the etching of convex geometries, while the suspended micro-channels depict the behavior for con cave geometries. The good match to the experiment is limited to etchants that roughly behave as 30–40 wt% KOH and Si{100} wafers. Even in this case examples of disagreement can be found, as shown in Figure 10.3d–f, where etching of the fast planes at the convex corners has advanced more in the experiment than in the BCA simula tion. This is directly due to the rate of {311} being much lower for BCA than in the experiment (see Figure 10.3a).

Continuous Cellular Automaton (CCA) The Continuous Cellular Automaton (CCA) was intro duced by Zhu and Liu [34]. In this method the atoms are associated with removal rates of any value—not restricted to 1 or 0—and the surface sites can be par tially occupied. The propagation of the surface consists of gradually decreasing the occupation of each surface site by an amount equal to the current removal rate of the occupying atom, whose value dynamically changes with the neighborhood. The evolution can be pictured as nonuniform, site-dependent erosion. The use of the D&P double loop ensures simultaneous removal of iden tical sites. For stepped surfaces, this provides an aver age surface propagation mode consisting of the gradual removal of entire atom rows located at the steps, accompanied by a slower continuous “erosion” of the terrace regions. In most cases, the removed rows alter nate according to a predictable sequence.

(b)

160

BCA

Micro-needles

(100)

140 120 100

Exp (311) BCA Exp

40

(110)

Suspended micro-channels

(c)

20 0

(d)

(111)

80 60

0

20 40 60 80 100 120 140 160 180 Angle, degrees Exp (e)

CPU time:371 s

BCA (g)

Depth: 225.82 um Time: 205.64 min

225 um 200 min

BCA

225.82 um 189.49 min

CPU time: 4404 s

Exp

1146 um, 375 cells

Etch rate, microns per hour

(a) 180

Another feature that makes the DCA method suitable for prototyping is the relative speed of the simulations. Compared to the CCA method (see Section 10.5.1), a DCA simulation is typically 4–20 times faster, the rea son being the high total removal rate for DCA as most atomistic rates get the value 1. In spite of this, owing to the D&P double loop, a DCA simulation is typically slower than a KMC simulation (see Section 10.5.2).

(f)

1563 um, 512 cells

CCA

Fig 10.3 ● (a) Etch rate dependence on orientation for the DCA method ( BCA) and comparison to a typical experiment (37 wt% KOH at 90 °C [30]). (b, c) DCA simulations compared to experiments for the manufacture of micro-needles [31] and suspended microchannels [32]. (d–g) Comparison of etching results for DCA method, experimental result (30wt% KOH at 80 °C [33]), mask layout with system dimensions [33], and CCA method. Source: (b) and (c) reproduced with permission by IOP (Fig. 4(e) in Ref. [31]) and Elsevier (Fig. 10(b) in Ref. [32]), respectively. (e) reproduced with permission by Amtec GmbH, Germany (bottom ﬁgure on p. 41 of Ref. [33]).

164

Manufacture and Processing of MEMS Structures

As an example, Figures 10.4a–h show the changes observed in the occupation of different surface sites during a sequence of events consisting of the removal of atoms A and B in alternation. The occupation is described by the size and color of the occupying atoms, with the larger, darker spheres corresponding to a larger occupation and the smaller, lighter spheres being closer to the empty state. The bulk sites, with ETA

T

AR-T

(a)

A

(d)

(b)

BR-T

(e)

B

occupation 1, are represented by white spheres. The ﬁgure shows seven generic atoms: the terrace atoms (T), two step atoms (A and B), the corresponding ter race atoms at the upper edge of the steps (Edge Terrace at A, ETA; and Edge Terrace at B, ETB), and the cor responding terrace atoms restricted by the presence of the step (A-Restricted Terrace, AR-T; and B-restricted Terrace, BR-T). T

180

(h)

A

Co-terrace

A

(f)

BR-T

T

ETB

d

B

(a)-(b): A is removed, B emerges (b)-(f): Occupation of B decreases (f)-(g): B is removed, ETB becomes A (g)-(h): Occupation of A decreases

KOH 50 w/v 90 C (511)

(311) (211)

3473 um, 512 cells

Etch rate, microns per hour

(i) 200

B

α B

(c)

B

d

ETA

T

ETB

Terrace

β AR-T

(g)

CHAPTER 10

(k)

160 (100)

140 120

(111)

100 80

166 um 150 min

(l)

BCA

(911)

60

3473 um, 512 cells CCA

40

(110)

Exp

20

Fit

0 0 20 (111) (j)

40

60 80 100 120 140 160 180 (111) Angle, degrees

Activation energies (eV) for calibrated atomistic rates 100 Atomistic removal rate, A /ms

L, 0.00

H, 0.57 V, 0.60 KR(1)-EMK, 0.47 M, 0.57 ETM, 0.66 ETH, 0.62 K, 0.59 D, 0.57 EMK, 79 EDA, 0.58

10–1 10–2 10–3

CPU time: 206 s Exp

(n)

165 um

(m)

CCA 165 um

A, 0.83

10–4

T, 0.57

10–5 2.7 2.8

CPU time: 2122 s 2.9

3

3.1

3.2

1/ T, K–1

3.3

3.4 3.5

×10–3

Fig 10.4 ● (a–h) Typical time evolution for the CCA method. Average height decreases and time increases from (a) to (b), (c) to (d), and (e) to (f). (i) Example of etch rate dependence on orientation for the CCA method and comparison to the experiment. CCA has been calibrated using the surface orientations marked as “Fit.” (j–m) Comparison of etching results for BCA, experimental result (30 wt% KOH at 80 °C [33]), mask layout with system dimensions [33], and CCA. (n) Atomistic removal rates calibrated at three different temperatures: determination of atomistic activation energies. Source: (k) and (n) reproduced with permission by Amtec GmbH, Germany (ﬁgures on p. 93 and 99 of Ref. [33]).

165

PA R T I I

Modeling in MEMS

In the same way as the etch rates of the different surfaces can be written down exactly for DCA, this can also be done for CCA. In this case, however, the expressions are more complicated, incorporating not only the geometry (through the numerical coefﬁcients and parameter a) but also the relative kinetics; that is, the actual atomisitc removal rates are different from 1 and 0 in general [35]. Considering the generic orientation shown in Figure 10.4a–h, the etch rate is written as R Δh/Δt (Δh A ΔhB )/(Δt A ΔtB ), where Δhj (j A, B) is the change in the average height of the surface when the atoms of type j are removed, which depends on the miscut angle, and Δt j is the corresponding time increment. For this ﬁgure, Δh A d cosα/N and ΔhB d cos β/N, where d 3a/4 is the Si-Si dis tance, N 7 is the number of periodically repeated surface atoms, α is the angle between the normal to the surface and the normal to the “co-terrace” (see Figure 10.4h), and β is the angle between the normal to the surface and the normal to the “terrace” (see Figure 10.4e). Thus, one gets Δh Δh A ΔhB a/ 123 . Since at each time step the occupation of each surface site is decreased by an amount equal to the current removal rate of the occupying atom multiplied by the current time step, the time increments satisfy the fol lowing two equations: ⎡ rART 2rT rETA + rA ⎢ ⎢ 0 ⎣

⎡1⎤ rBRT 2rT rETB ⎤ ⎡ΔtA ⎤ ⎥⎢ ⎥⎢⎥ ⎥ ⎢ ΔtB ⎥ ⎢1⎥ rB ⎣⎦ ⎦⎣ ⎦

(10.1) where (rART 2rT rETA rA )Δt A (rBRT 2rT

rETB )ΔtB 1, or the equivalent, rART Δt A rBRT ΔtB

2rT Δt A 2rT ΔtB rETA Δt A rETBΔtB rA Δt A 1, is the total reduction in the occupation of site A until atom A is removed. Note that the reduction in the occupation sums up necessarily to 1 (right-hand side). In other words, {rART ,rBRT ,(rT ,) 4,rETA ,rETB ,rA } is the full site-type history of atom A, exposed to the etchant during alternating time intervals of duration Δt A and ΔtB . In a similar manner, the second row of the matrix equation describes the total site-type his tory for atom B. In this case it is very simple, since B is removed right after it emerges to the surface. Solving the matrix Eq. 10.1 for Δt A and ΔtB , and using the previous value for Δh, one gets: R

rB (rART 2rT rETA rA ) 59 rB rART rETA rA rBRT rETB a

(10.2) Similarly, one obtains the equations for other surface orientations. As a result, a system of nonlinear equations 166

is obtained, which links the experimental etch rates for the planes to the removal rates for the atoms: R100 R110 R111 R211 R311 R511 R331 R210 R310

a rD 4 a

rM 2 2 a rT rL( T ) 3 rT rL( T ) rH (2rT rV ) a 2 6 rH rT rV rETH rH (rT rV ) a 11 rH rT rV rA a (rD rEDAA )(rETH rV ) rA rH (10.3) 3 3 rD rEDA rETH rV rA rH 2 a (rT rETM )(rM rL(ETM) ) rM 19 a 4 5 a

rT rETM rL(ETM) rM (rM rEMK rK )

2 10

(rKR(1)EMK rK )

Equation 10.3 uses 14 site-speciﬁc rates correspond ing to the most essential terrace, step, kink, and adatom sites [35], including edge-terrace sites, which are located at the upper edge of the steps. There are 7 basic sites (T, M, D, H, V, K, and A, appearing as {111}-Terraces, {110}-Monohydrides, {100}-Dihydrides, {h 2 h h} Horizontal dihydrides, {h 2 h h}-Vertical dihydrides, {h 2 h 0}-Kinks, and {h 1 1}-Alternative-dihydrides, respectively, with h being an integer), 4 edge sites (Edge Terraces at M and H steps, or ETM and ETH, Edge Monohydrides at K steps, or EMK, and Edge Dihydrides at A steps, or EDA), 2 adatom sites or Lollies (L(T) and L(ETM), obtained when removing the 111-Terrace and {h 2 h 2 h}-ETM atoms, respectively) and 1 restricted site, KR(1)-EMK-, appearing on {h 2 h 0}. The actual form of the equations depends on the rela tive values of the removal rates for the step and edgeterrace sites. See Ref. [35] for further details.

Calibration of CCA It is possible to solve the system of equations (Eq. 10.3) for the site-speciﬁc rates in terms of the experimental face-speciﬁc etch rates. A calibration procedure is con sidered, consisting of ﬁnding proper values for the 14 atomistic rates (the unknowns) given the values of the 9 face-speciﬁc rates (the equations) [35, 36]. This is done by minimizing the global error between the experimen tal and calculated etch rates, numerically solving the sys tem. The 9 equations correspond to 7 surfaces from the [110] crystallographic zone, e.g., {111}, {211}, {311},

Manufacture and Processing of MEMS Structures

{911}, {100}, {551} and {110}, and {2} orientations from the [100] zone, e.g., {210} and {310}. Depending on the particular etch rate anisotropy, {551} may be replaced by {331}, {311} by {411}, or {911} by {511}, as some examples. Although there exist additional equa tions for other surface orientations, the number of facespeciﬁc rates containing nonredundant independent information is limited, and incorporating more equations would make the system mathematically over-deter mined. The limited number of equations is not a major drawback for the successful realization of the calibration. As a matter of fact, it is of beneﬁt as it reduces to less than ten the number of experimental etch rates needed for calibration. This is a dramatic decrease as compared to the geometrical methods, which require hundreds and even thousands of etch rates to perform the simulations. Furthermore, the same calibration procedure can be performed consistently at different temperatures for the same etchant at a ﬁxed concentration, thus allowing the extraction of atomistic activation energies [37]. The atomistic removal rates of the fourteen surface sites are calibrated at three different temperatures, and the obtained rate values are plotted on an Arrhenius diagram (rate vs. inverse temperature), as shown in Figure 10.4j. The atomistic activation energy for each surface site is obtained by extracting the slope of a linear ﬁt. The fact that a linear ﬁt can be used underlines the consistency of the calibration method throughout the different tem peratures. The extraction of atomistic activation ener gies enables performing simulations at any temperature for the chosen etchant concentration.

DCA vs. CCA Figure 10.4i shows a typical comparison between the experimental etch rates for the surface orientations in the [110] crystallographic zone and the etch rates obtained with the CCA method after calibration. The experi mental etch rates used for calibration are shown as “Fit,” except for {210} and {310} of the [100] zone, which are not shown. In comparison to BCA in Figure 10.3a, CCA reproduces not only qualitatively but also quantitatively the anisotropic features of the etch rate, including the locations and values of the global and local minima and maxima, as well as the discontinuity in the etch rate at {551}. The comparison of the etched shapes in Figure 10.3d–g shows that CCA describes better than BCA the fast etching planes at the convex corners. While the advancement of these orientations is too slow for BCA, for CCA the planes lag behind the experiment only a small amount. Similarly, Figure 10.4k–n shows a comparison of the etched shapes for a different system, demonstrating the improved accuracy obtained when using CCA. As compared to DCA, a well calibrated CCA simula tor is able to reproduce quantitatively the local and global

CHAPTER 10

maxima and minima of the etch rate dependence on the orientation and is not limited to 30–40 wt% KOH and Si100 wafers. This is shown in Figs 24.4e–h of this book, demonstrating that different etchants can be described well by the CCA method. Generally speaking, CCA is a more accurate method than DCA for the simulation of three-dimensional etch proﬁles of interest in engineering applications. As shown in Figures 10.3d–g and 10.4k–n, the improved accuracy for CCA comes at the expense of longer simulation times (see the quoted CPU times, i.e., the time required for a simulation to be ﬁnished in a computer). Typically CCA is slower than DCA by a fac tor between 4 and 20 times, depending on the system. This is due to the fact that most rates have value 1 for DCA while many rates take rather low values in CCA.

Constant and Variable Time Stepping In its simplest form a CCA simulation proceeds by using a CTS implementation. This simply consists of choosing the size of the time step (typically 1) and performing the double D&P loop inside each step (Section 10.5). In the ﬁrst loop, the occupation of every site is reduced according to the current value of the removal rate of the occupying atom multiplied by the time step. The atoms at the sites reaching zero (or nega tive) occupation are marked for removal. In the second loop, the marked atoms are removed and the state and rate of their neighbors are updated. After this, a new time increment can be performed. It is possible to use an alternative Variable Time Stepping (VTS) procedure, characterized by advancing time just the exact amount required to remove the next atom or group of atoms. To do this one proceeds as fol lows: during the ﬁrst loop the minimum time to remove one surface atom (or a group of atoms having the same time increment) is determined and, in the second loop, only those atoms with this time increment are removed. Note that for the DCA method there is no actual dif ference between the VTS and CTS implementations. Correspondingly, it only makes sense to use CTS when considering the DCA method.

Time Compensation The CCA simulations can be performed using either the CTS or VTS implementations. VTS is suitable for deriving and verifying the analytical equations for the etch rates of the different surface orientations, while CTS is suitable for simulating and developing MEMS engineering applications. Although VTS represents an exact propagation method, CTS is only approximate in nature due to the following: (i) The occupation of one or several sites can become negative just before the removal of the corresponding atom, and (ii) the method enables the simultaneous removal of different groups 167

PA R T I I

Modeling in MEMS

of atoms that should occur sequentially (according to the exact evolution provided by VTS). This occurs since the time step can be larger than the two small est time increments to remove the next two scheduled groups of atoms. As a result, both groups are removed simultaneously, which can be conﬂictive as the removal of the ﬁrst group can sometimes lead to the formation of very active surface atoms which should be removed next instead of the second group. A standard time com pensation (TC) procedure [34] and an alternative back ward TC method [38] can be used to resolve the ﬁrst problem. However, neither of the two methods can eliminate the second problem, its being possible only to minimize it by using small time increments.

Stochastic Cellular Automaton The third type of CA method, the SCA, is discussed after the KMC methods at the end of Section 10.5.2.

10.5.2 Kinetic Monte Carlo Monte Carlo (MC) methods refer to any computational calculation that makes use of random numbers. Kinetic MC (KMC) refers to the description of the time evo lution of a system by considering the kinetics of the different processes, i.e., their rates. New states are sequentially generated by realizing one process per time step, paying special attention to the correct determina tion of the time increment between consecutive proc esses. This is in contrast with the Thermodynamic MC (TMC) method where the measure of time is irrelevant, as the principal objective is the determination of equilib rium properties consisting typically of ensemble averages of the internal energy and other thermodynamic quanti ties. KMC enables the analysis of the evolution of both equilibrium and nonequilibrium systems and, in particu lar, the transient behavior from any given initial state to a completely different state, a problem that is of particular interest in the micromachining of MEMS structures.

Metropolis KMC In its simplest form a KMC simulation proceeds as follows: In each time increment a random number is chosen ( 0 q 1) in order to pick up an atom i, as shown in Figure 10.5a. A removal decision is made by comparing the neighborhood-dependent removal rate ri and a second random number 0 e 1 . If e ri , the atom is removed. The change in the atom types for the surface neighbors and the emergence to the surface of the bulk neighbors leads to a new state of the system. If e is larger, the previous state remains. Irrespective of the atom removal or stay, time is incremented as the inverse of the total number of surface atoms, 168

Δt 1/M. After this, a new time increment can be per formed. This simple procedure is known as Metropolis KMC [38]. It is also regarded as the CTS KMC method because the number of processes M is a constant in many applications, leading to constant time steps.

Fast KMC Simulations Although the outlined method can be easily imple mented, there are typically alternative procedures that can speed up the simulations. If most atomistic removal rates are low, many processes need to be tried before a success is observed when comparing ri and e. To speed up such simulations one may sample the processes according to the removal rates instead of picking up the processes randomly. While performing random pick-ups ensures that the most abundant processes are chosen more often, sampling the rates ensures that the most probable processes—with higher rates—are chosen more frequently. In practice, for each time step, sam pling the rates corresponds to choosing the ﬁrst proc i1 M i ess i for which ∑ j1 rj e ∑ j1 rj ∑ j1 rj , where e is a random number (see Figure 10.5b). This is similar to performing a random pick-up, where one chooses the i1 M i ﬁrst atom i that satisﬁes ∑ j1 1 q ∑ j1 1 ∑ j1 1 , or equivalently, i 1 qM i (see Figure 10.5a). For a given random number e, the determination of the next process i requires visiting the set of all removal rates until the cumulative sum ∑ ij1 rj satisﬁes the previous condition. By considering all the rates as the components of a one-dimensional array, as described in Figures 10.5c–e, ﬁnding the next event consists of searching for the index whose cumulative sum equals or M surpasses the length e ∑ j1 rj (see Figure 10.5f). Since on average the time cost of ﬁnding the event increases linearly with the number of surface atoms M, the method is known as a Linear Search. In the same man ner as the time increment between random pick-ups is the inverse of the total number of current surface atoms ( Δt 1/M 1/ ∑ M j1 1), when sampling the removal rates the time increment is the inverse of the current total removal rate ( i.e., the sum of all the current ato mistic rates, Δt 1/R 1/ ∑ M j1 rj ). Several alternative methods can be used to perform fast KMC simulations based on efﬁciently sampling the removal rates [38, 39]. Typically, this is done by group ing the rates. Each group (or bin) contains several rates and is assigned a rate that is the sum of the contained rates. The bins themselves are subsequently grouped into larger bins, assigning them the corresponding sum of the rates inside each. Grouping is continued for increas ingly larger bins until a single bin eventually contains the sum of all the rates in the system. The procedure leads to a tree structure where the root corresponds to the largest bin and each branch represents a bin containing

Manufacture and Processing of MEMS Structures

(a)

Random pick-up Choose first i that satisfies:

i-1

M

i

1≤ Σ 1 Σ 1 < q· Σ j=1 j=1 j=1

(b)

CHAPTER 10

Linear search i-1

Choose first i that satisfies:

M

i

Σ rj < e· j=1 Σ rj ≤ j=1 Σ rj

j=1

Reactive steps, unreactive terraces

(g)

Removal rates

Metropolis KMC Choose atom i randomly Choose random number e Accept if e ≤ r_{i} Δt= I/M (cons.)

Fast KMC Choose rate ri randomly Always accept Δt = I/R (var.)

(c)

Tree search (TS) Leaves level

Detail of removal rates n+I n (d) Row n

Root level Partial sums

Row n+I

Rates arranged as ID array

Random number (f) Linear search (LS)

(e) Equivalent representation of rates as ID array

Removal rates

Fig 10.5 ● (a) Metropolis KMC method (CTS). (b) Alternative, faster KMC method (variable time step). (c–e) Representation of the removal rates as a one-dimensional array for use in a Linear Search. (f) Linear Search. (g) Tree Search (binary tree).

several bins from the immediately higher level—until reaching the leaves, which correspond to the original rates (see Figure 10.5g). The long linear search between all the rates at the leaf level (Figure 10.5f) is replaced by several short linear searches, each of them inside a bin at a different level (Figure 10.5g). The computa tional cost to ﬁnd the next rate is reduced from O(M) to O(gloggM), where g is the bin size (assumed constant throughout the levels). This can be orders of magnitude faster than the long linear search at the leaf level. As an example, one can use a binary tree with two rates per bin (see Figure 10.5g). In this case, the time to ﬁnd the next rate is O(log 2 M) . Another fast method is K-Level Search (KLS) [40], whose time cost is O( M1/K ) , where K log g M is the number of levels. KLS stands as the most general tree-search method, containing many methods as particular cases, such as the binary, quaternary, and octal trees; the linear search; Maksym’s binning method; etc. [38, 39, 41]. If the number of different processes (N) is small, the Bortz– Kalos–Lebowitz (BKL) or N-fold method can be used [42, 43], having a time cost O(N) independent of M. BKL uses a modiﬁed tree structure with only two levels. The ﬁrst level is the list of the atom rates.

Grouping in the second level is based on the actual val ues of the rates, in such a manner that the processes gathered into each bin have the same rate. Although BKL typically performs fewer searches than KLS, a larger bookkeeping effort is required since the rates of the neighboring atoms are typically modiﬁed and, thus, they need to be moved from one bin to another. Correspondingly, BKL becomes inefﬁcient if second and third neighbors are included and/or if the number of different rates is larger than 10–15, which are typical situations for the simulation of anisotropic etching. This justiﬁes the use of KLS. In practice, the even bin sizes for KLS (g 2, 4, 8,…) ultimately provide the fastest search times as they enable bit-shift implementations of multiplication and division operations used to ﬁnd the location of the atoms in the tree structure [44].

Calibration of KMC The dependence of the process rates on the local envi ronment can be considered as an explicit function of the number of neighbors, e.g., the number of nearest and next-nearest neighbors, n1 and n2. One may assume the existence of a function r(n1,n2) describing the 169

Modeling in MEMS

PA R T I I

removal rate (or, when normalized, the removal prob ability) of an atom in the different conﬁgurations. For instance, it has been shown that anisotropic etching in KOH at medium concentration (e.g., 30–40 wt%) can be described by a Removal Probability Function (RPF):

r( n1 , n2 )

βε n 0 1 1

1 e 1 e

βε (n n 0 ) 1 1 1

βε n 0 2 2

1 e 1 e

βε (n n 0 ) 2 2 2

(10.4)

where β 1kBT , kB is the Boltzmann constant and T is the temperature. This particular analytical form is based on geometrical arguments and visual ﬁtting of simulated and experimental etched proﬁles for a set of mask designs [45]. The use of the RPF reduces the number of adjustable variables from 48 removal rates to 4 physically meaningful parameters ( ε1 , ε2 , n10 , n20 ). As an example, Figure 10.6a shows simula tion results for the KMC method using the RPF model with ε1 0.35 , ε2 0.16 , n10 2.84 , n20 7.0 and T 348K (75°C). Comparison with column (b) of the same ﬁgure shows that the RPF model provides a good description of the etching results for 30 wt% KOH at 80 °C [33]. Mimicking other etchants using the RPF model, however, is not guaranteed to work. In a sense, the RPF model is similar to the BCA method, limited to describe 30–40 wt% KOH in practice. In most cases the dependence on the neighborhood is not treated as a parameterized function but rather as an adjustable matrix (or table) where the process rates rn1 ,n2 can be manually ﬁtted by matching simulations and experiments. This can be based on the comparison

of (i) the simulated and experimental surface morpholo gies, (ii) the etch rates of different surface orientations, and (iii) the shape of the etching proﬁle in the engineer ing applications. As an example, this approach has been used in [46–48] by comparing detailed STM images and KMC simulations of the surface morphologies of stepped {111} surfaces and in [49] by simultaneously matching experimental and simulated morphologies of a wide range of surface orientations (see Figure 10.7). Typically, these calibrations are performed by ﬁrst set ting the rates of the slowest processes, gradually intro ducing changes in the more active rates by isolating and reproducing characteristic morphologic features such as straight, polygonal, or curved steps; triangular, hex agonal or round pits; different types of hillocks; or even macroscopic features such as the resulting shape in the undercutting of masked convex corners. The derivation of a system of equations for KMC similar to that in Eq. 10.3 for CCA linking the experi mental etch rates to the atomistic removal rates is an open, unsolved problem. The difﬁculty is that the expression for the etch rate of any surface orientation depends in a complicated manner on the values of the atomistic removal rates, changing as the atomistic rates are modiﬁed [50]. In principle, only a complex itera tive ﬁtting procedure may succeed in solving this prob lem in the future. As a result, presently the calibration of the KMC removal rates for the simulation of aniso tropically etched MEMS structures cannot be routinely performed as it requires an experienced user capable of isolating, understanding, and reproducing the particular features of the evolving front.

Fig 10.6 ● (a–d) Comparison of simulations and experiment: Octree search KMC method (column (a)), experiment (column (b), 30 wt% KOH at 80 °C [33]), BCA method (column (c)) and CCA method (column (d)). Source: Masking pattern and system dimensions (in microns, column (b)) from Ref. [33]. (b) reproduced with permission by Amtec GmbH, Germany (ﬁgs on p. 31–37 of Ref. [33]).

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Manufacture and Processing of MEMS Structures

Stochastic Cellular Automata The SCA was introduced by Than and Büttgenbach [29]. The surface sites have only two occupation states, namely, fully occupied (1) and empty (0). However, the removal rates of the atoms can take any value in the range [0,1]. The inner structure of a time step is as follows: In the ﬁrst loop, a removal deci sion is made for every surface atom by comparing the neighborhood-dependent removal rate r and a random number 0 e 1 . If e r , the atom is marked to be removed. The random number e can be kept equal for all equivalent atoms—stressing the parallelism and simultaneity—or can be chosen different for each atom. Once all decisions have been taken, the marked atoms are removed in the second loop, and the state and rate of their neighbors are updated. At this point, time is incremented by one unit and the system is ready for a new time step. This procedure corresponds to a CTS implementation. The method is reminiscent of the Metropolis KMC scheme of Section 10.5.2. The dif ference is that SCA operates on the surface atoms syn chronously using the double D&P loop characteristic of the CA simulations while Metropolis KMC operates purely sequentially.

Calibration of SCA The derivation of a system of equations for SCA similar to that in Eq. 10.3 for CCA linking the experimental

CHAPTER 10

etch rates to the atomistic removal rates is an open problem. Refs. [10, 29] consider only the case of the main orientations {100}, {110}, and {111}. However, incorporating more surface orientations is a complex task. Although the face-speciﬁc etch rates of 100 and 110 can be simply assigned to the site-speciﬁc rates for a particular type of atom in each case, the same is not true for other orientations, including {111}. The removal of the terrace atoms on the {111} surface leads to a full layer of addatoms (or lollies), and the actual value of their removal rate will affect the overall etch rate for this surface. As a result, the etch rate of {111} depends on the removal rates of two atoms. Although in this case the dependence is simple, the etch rates for other surface orientations become complex functions of several (probably, many) atomistic rates. The form of these functions has not been determined yet.

KMC vs. CA When comparing KMC and CA simulations, the latter are characterized by an average behavior following exactly the same pattern in equivalent regions of the microma chined system. On the contrary, KMC is stochastic by construction, leading to random features in the etch front, including the formation of round edges between the fast etching planes. For shape comparisons between the etch fronts it is recommended to use the KMC method in systems containing twice the number of unit cells as compared with the DCA and/or CCA systems.

Fig 10.7 ● (a–i) Some typical surface morphologies for different surface orientations using the KMC method. After calibration has been performed, the same atomistic rates are used to simulate the surface morphology of the different surface orientations [49]. Source: (f), (g), (h), and (i) are from Fig. 1(f), 1(c), 1(e), and 1(a) in [49], respectively. Reproduced with permission by IOP.

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This reduces the relative importance of the stochastic features of the KMC front. Simulation results concern ing the use of CCA and KMC for etching applications such as microneedles, microﬂuidics, and other complex processes can be found in Refs [35, 36, 44]. Figure 10.6 offers a comparison of the three simulation methods against the experiment for an etchant (30 wt% KOH at 80 °C [33]) that is particularly suitable for the KMC method using the RPF model and the BCA method. Computationally, KMC is typically faster than either DCA or CCA (see the CPU time values quoted in Figure 10.6). Although the numbers depend on the simulated system and the size of the atomistic neighbor hood as well as on the computer architecture, the com putational cost is typically about 10–40 and 2–4 times slower for the CCA and DCA simulations, respectively. The reason can be found in the two D&P loops of the CA method (see Section 10.5), which have a large impact on the efﬁciency. Considering the CA methods, DCA is faster and can typically ﬁnish a given task within a few tens of seconds up to several minutes, depending on the computer speed, the size of the system held in the computer memory, and the duration of the simu lated etch process. CCA is slower, taking typically from a few minutes to a few hours. Thus, for MEMS applica tions KMC and DCA can be used for fast prototyping and CCA for more accurate simulations.

10.5.3 Atomistic vs. Geometric Simulators Although the calibration of the geometrical simulators is simpler, as they can directly use the measured etch rates while the atomisitic simulators need to convert the face-speciﬁc etch rates into site-speciﬁc removal rates, there are several reasons to favor the use of the atomistic simulations: ■

■

■

Rather straightforward compatibility with the Finite Element Analysis (FEA) tools for the determination of electromechanical, thermal, and/or optical properties. The whole domain is already conveniently discretized, including convex and concave regions and/or protrusions. A realistic description of the surface morphology and its origin is included, enabling an improved understanding of the interplay between the microscopic phenomena and the macroscopic features. The underlying atomistic process can be visualized, and the simulated macroscopic system can be understood better. A reduction in the number of experimentally required parameters is obtained. As an example, the use of CCA signiﬁcantly reduces the number of experimental parameters to just nine as compared 172

with hundreds or thousands of etch rates required by the Wulff-Jaccodine method. ■

■

■

The correctness of the underlying atomistic processes is tested, serving as a screening method for different possible mechanisms. The boundary conditions are greatly simpliﬁed, allowing the use of complex mask designs. Multi-valued surface fronts containing parts which may split and/or join are handled natively without any need for special procedures or geometrical analysis. In this respect, the geometric simulators are not always able to describe wafer perforation e.g., during double-side etching.

10.6 A Survey of Etching Simulators The following is a list of various commercial and non commercial simulators for modeling anisotropic etch ing, listed in alphabetical order. Table 10.1 compares the major features offered by the simulators. This includes the type of simulator (geometric or atomistic), the sup ported substrates (Si, GaAS, etc.), wafer orientations (e.g., Si{100}, Si{110}, etc.), etching conditions (aniso tropic and isotropic etchants, concentrations and temper atures), mask layout tools, support for multiple masking and etching processes (simultaneous use of different masking materials, sequential patterning with different masks, sequential processing by wet and dry techniques, etc.), support for RIE/DRIE, visualization tools, export options, operating system requirements, etc.

10.6.1 ACES ACES stands for Anisotropic Crystalline Etch Simulation. This simulator was released during 1998– 2001 by the Micro Actuators, Sensors and Systems Group (MASS) at the University of Illinois at UrbanaChampaign, Urbana, USA, under a free license policy. Although ACES is no longer an active project, the latest version from 2001 can be downloaded [51]. ACES is an atomistic simulator using a CCA. The time evolution is implemented using CTS and TC for the elimination of negative occupation (see Section 10.5.1). It uses the dynamic method for data storage, which allocates and deallocates memory according to the size of the active slab region [38]. ACES is based on Refs [52, 53].

10.6.2 AnisE The AnisE simulator was marketed in 1997–2008 by

IntelliSense Sofware Corp., from Boston, Massachusetts,

Manufacture and Processing of MEMS Structures

CHAPTER 10

Table 10.1 Wet etching simulators

VisualTAPAS1 SEAES IntelliEtch

MICROCAD2

SIMODE/ Qsimode

ACES

AnisE/SUZANA Etch3D

UI UrbanaChampaign

TU Coventor, Inc. Helsinki UT, Braunschweig Nagoya U

Southeast Fuji Res. Inst. Chemnitz UT U Corp.

Commercialized by

Free, OTM UIUC3

IntelliSense/ Academic4

Free/ IntelliSense1

Academic4

Mizuho Inf. &Res.

Imtec

Availability

1998–2001, 2001

1997–mid2008/ 2005–2007 1994

2007–/ mid-2008–1

2007–

1998–

1998–

Simulator

Atomistic

Atomistic

Atomistic

Atomistic

Atomistic

Geometric

Geometric

Type

CCA

DCA, SCA

Metropolis KMC KMC, DCA, CCA

CCA

Wulff–Jaccodine Wulff–Jaccodine

TimeStepping

CTS TC

CTS

CTS

VTS, CTS TC

CTS TC

CTS

DataStorage

dynamic

dynamic

dynamic

Octree

dynamic

Points/Segments Points/Segments

Substrate

Si, GaAs

Si

Si

Si

Si

Si, quartz

Si, quartz

Orientation

(100), (110), (111)

(100), (110)

3main vicinal any (hkl), incl. vicinal

(100)

any (hkl)

(100), (110)

SOI wafer

No

No

No

Yes

No

No

No

Anisotr. Etch

KOH, TMAH, EDP

KOH, TMAH, EDP KOH, TMAH

KOH, TMAH, KOH:IPA

KOH, TMAH

KOH, TMAH

KOH, TMAH, KOH: IPA

Conc.s/Temp.s

Various

Various

Limited

Various

Various

Wide range

Various

Database

Limited

Limited

Limited

Limited

Limited

Extensive

Limited

Isotr. Etch

Yes

Yes

Extra module

Yes

Yes

?

Yes(estimation)

User-deﬁned rates

Yes

Yes

Yes (difﬁcult)

Yes

Yes

Needs full pattern Needs full pattern

Etch control by…

time, doping

time, frames,

time

time, depth

removed atoms

time, depth, frames, removed atoms

time, depth

etch stop

time, multipleetch stops

Etch top/bott/both

Yes/?/?

Yes/Yes/Yes

Yes/Yes/Yes

Yes/Yes/Yes

Yes/Yes/No

Yes/?/?

Yes/Qsimode/ Qsimode

Mask layout

Arbitrary

Arbitrary

Arbitrary

Arbitrary

Arbitrary

Arbitrary

Arbitrary

Mask editor

Integrated

External (IntelliMask)

External

External

External (L-Edit)

Integrated

External (EMaDe)

Maks ﬁles

DXF, GDSII, CIF, DXF, GDSII GIF, BMP

?

DXF, GDSII, BMP CIF

?

DXF, GDSII, ASCII, GIF

Points

Points, surf, cubes, atoms OpenGL

surf

Outline, facets

Outline, facets

Yes

No

Yes

Using Qsimode

Developed at

Integrated 3D viewer Points, facets

Points, surface

OpenGL

Cross sections

?

Coventor

Surf→ext. viewer Yes

Yes

CTS

OpenGL

(Continued )

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Table 10.1 Continued

ACES

AnisE/SUZANA Etch3D

VisualTAPAS1 SEAES

MICROCAD2

SIMODE/ Qsimode

Measure distances

?

Yes

No

Yes

?

Indirectly

RIE wetetch

Yes

Extra module/Yes Extra module

Yes

No

No

No

Many masks/etches

Yes

Yes

?

Yes

No

?

Only in Qsimode

FEA export

?

For IntelliSuite

For CoventorWare C3D8R (ABAQUS) No

?

ADPL, DirectX

Other exports

VRML, AVImovie VRML, DXF

?

VRML, XYZ, JPG

No

IGES, AVS

DXF, IGES, GDSII

OS

Windows

Windows

Windows

Windows

Windows

Unix

Windows

References

[52, 53]

[55]/[10, 29, 54] [45]

[35, 36, 38, 44, 45]

[57,58]

[22,23,27]

[19]

?

Notes: ? not known (information is not available) 1 Commercial version: IntelliEtch [61]. 2 Presently marketed as FabMeister-ES. 3 Ofﬁce of Tech. Management at U. Illinois Urbana-Champaign [51]. 4 Academic collaboration only.

USA, as part of the IntelliSuite family of MEMS design tools [8]. The tool is an atomistic simulator based on the methods DCA and SCA using CTS. AnisE is based on SUZANA (see Section 10.6.8) and Refs [29, 54, 55]. AnisE was replaced during 2008 by a new simula tor IntelliEtch, a licensed version of VisualTAPAS (see Section 10.6.9).

10.6.3 Etch3D The Etch3D simulator was marketed in 2005–2007 by Coventor Inc., with headquarters in Cary, North Carolina, USA, as part of the CoventorWare package for MEMS design [7]. Etch3D is a simulator using the Metropolis KMC method, i.e., the CTS implementa tion of KMC (see Section 10.5.2). Etch3D is suitable for the simulation of anisotropic etching in 30–40 wt% KOH at 70–90 °C. In addition, it can qualitatively simu late etching in low, medium, and high concentration of both KOH and TMAH. It is based on Ref. [45] and general theoretical arguments about the concentration and orientation dependence of the etch rate of a generic etchant [56].

10.6.4 MICROCAD (presently FabMeister-ES) FabMeister-ES has been marketed since 2005 by Mizuho Information & Research Institute, Inc. [25]. The program is traditionally known as MICROCAD, which was released in 1997 by Fuji Research Institute 174

Corp., Japan, with a focus mainly on the domestic Japanese market. MICROCAD is a geometrical simu lator based on the Wulff-Jaccodine method and using CTS. The program makes use of ODETTE, one of the widest etch rate databases for anisotropic etching. MICROCAD is based on Refs. [22, 23, 27].

10.6.5 SEAES SEAES stands for South East Anisotropic Etching Simulator. This academic simulator from the Key Laboratory of MEMS of the Ministry of Education, Southeast University, Nanjing, China, is only available by directly contacting the main developers, Dr. Zai-Fa Zhou ([email protected]) and Prof. Qing-an Huang ([email protected]). SEAES has been developed since 2005 and is currently under active development. The simulator implements the CCA method and uses CTS with standard TC (see Section 10.5.1), according to our analysis of the original publications [57, 58]. Although there are many similarities between SEAES and the CCA engine in VisualTAPAS (see Section 10.6.9), data storage is different, with SEAES being based on the dynamic method [38]. More information about SEAES can be found in Refs [57, 58].

10.6.6 SEGS Directed Segments, or SEGS, was released under a

free license policy during 1996–1998 by the California

Institute of Technology, California, USA. SEGS is no

Manufacture and Processing of MEMS Structures

longer an active project. The program provided online 3-D isotropic and anisotropic etch simulations based on a hybrid geometrical-cellular method. A description of SEGS is provided in Ref. [59].

CHAPTER 10

available. In the last few years SUZANA has undergone new active developments, including the modeling of DRIE [11]. SUZANA is based on Refs [10, 29, 54].

10.6.9 VisualTAPAS

10.6.7 SIMODE/QSimode SIMODE was developed during 1993–1999 by Frühauf and co-workers at Chemnitz University of Technology, Chemnitz, Germany. Initially, the program was mar keted by Gemac GmbH, Chemnitz. Since 2003, it has been traded by Amtec GmbH, Chemnitz [24]. SIMODE is a software package consisting of a mask design tool (EMaDe), two engines (SIMODE, for the simulation of the etched relief based on the propaga tion of the upper and lower contours, and QSimode, for the simulation of vertical cross-section etches), and the 3D-Viewer. SIMODE itself is a geometric simulator based on the Wulff-Jaccodine method using Constant Time Stepping. For Si100 wafers, simulations can be performed in KOH (30% and 40% at 60 °C and 80 °C), TMAH (25% at 70 °C, 80 °C, and 90 °C), and KOH:IPA (27% at 70 °C). For Si110, simulations are possible for 30% KOH:H2O at 80 °C. Other conditions are provided on request. The program is based on Ref. [19].

10.6.8 SUZANA SUZANA was developed during 1994–1996 by Than and Büttgenbach at the Institute for Microtechnology, Technical University of Braunschweig, Braunschweig, Germany [29, 54]. The program is an atomistic simulator based on the Discrete Cellular Automaton (DCA) and the SCA, using CTS (see Section 10.5.1). For the SCA method, it is not clear whether the random number e is kept constant or is different for equivalent surface atoms (see Section 10.5.2). This program has been the basis for the commercial simulator AnisE since 1997 (see Section 10.6.2). SUZANA itself is not publicly

VisualTAPAS stands for Visual Three-dimensional Anisotropic Processing at All Scales. Inheriting many fea tures from a previous simulator (TAPAS) developed by Gosálvez at Helsinki University of Technology, Helsinki, Finland, VisualTAPAS was further developed by Xing and Gosálvez at Nagoya University, Nagoya, Japan. The program was released in February 2007 and is currently under active development [60]. VisualTAPAS is an atom istic simulator that uses both KMC and CA time-evolution algorithms. This includes a fast Octree Search KLS method for the KMC simulations, and both DCA and CCA for the CA simulations. Variable and CTS are available for both KMC and CA. Standard and Backward TC methods can be used in the CCA simulations. Data storage is based on an octal tree representation of the substrate [38], enabling the simulation of etching for any surface orientation—not limited to {100}, {110}, and {111}—and masking by silicon oxide and/or nitride for the top and/or bottom sides simultaneously. At the time of writing VisualTAPAS has been calibrated to sim ulate KOH (30 wt% at 70 °C and 80 °C; 11 wt%, 40 wt%, and 50 wt% at 70 °C; and 37 wt% at 30 °C, 50 °C, 70 °C, and 90 °C), TMAH (20 wt% at 80 °C), and KOH:IPA (11 wt% and 37 wt% at 70 °C), with more calibrations under work. VisualTAPAS includes the modeling of DRIE. VisualTAPAS is offered as a fully operational, free trial version which expires after starting the program several times (typically 10). A commercial, non-expiring version is available under the name of IntelliEtch [61] from IntelliSense Software Corp. [8]. Academic groups can choose between a free IntelliEtch copy with out support or full support for a modest license fee. VisualTAPAS is based on Refs [35, 36, 38, 44, 45].

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54.

55.

56.

57.

J. Microelectromech. Syst. 9 (2000) 252–261. S. Büttgenbach, O. Than, SUZANA: a 3D CAD tool for anisotropically etched silicon microstructures, Proc. of IEEE European Design and Test Conference (ED & TC 96) (1996) 454–458. J. Marchetti, Y. He, O. Than, S. Akkaraju, Efﬁcient process development for bulk silicon etching using cellular automata simulation techniques, in: SPIEÕs 1998 Symposium on Micromachining and Microfabrication, Micromachined Devices and Components, Santa Clara, CA, USA, September 20–22, 1998. M.A. Gosálvez, K. Sato, A.S. Foster, R.M. Nieminen, H. Tanaka, An atomistic introduction to anisotropic etching, J. Micromech. Microeng. 17 (2007) S1–S26. Z.F. Zhou, Q.A. Huang, W.H. Li, W. Deng, A cellular automaton-based

58.

59.

60. 61.

CHAPTER 10

simulator for silicon anisotropic etching processes considering high index planes, J. Micromech. Microeng. 17 (2007) S38–S49. Z.F. Zhou, Q.A. Huang, W.H. Li, C. Zhu, A 3-D simulator for silicon anisotropic wet chemical etching process based on cellular automata, J. Phys.: Conf. Ser. 34 (2006) 674–679. T.J. Hubbard, E.K. Antonsson, Design of MEMS via efﬁcient simulation of fabrication, in: Proc. of the ASME Design for Manufacturing Conference, Irvine, CA, August 18–22, 1996. http://tfy.tkk.ﬁ/~mag/VisualTAPAS/ Home.html (visited 18.09.2009). http://www.intellisensesoftware.com/ modules/IntelliEtch.html 18.09.2009.

177

11

Chapter Eleven

Mechanical Properties of Silicon Microstructures Maria Ganchenkova and Risto M. Nieminen COMP/Department of Applied Physics, Helsinki University of Technology, Espoo, Finland

11.1 Basic Structural Properties of Crystalline Silicon 11.1.1 Silicon Structure Ground State: Lattice Parameter At ordinary pressure silicon crystallizes in a diamond structure that consists of a face-centered cubic lattice with a basis of two atoms. Each atom constituting this structure is tetrahedrally coordinated and manifests sp3 hybridization. However, at higher pressures there exist a number of high-pressure phases with different struc tures, as we discuss later (Figure 11.1). Lattice parameter is one of the most fundamental characteristics of a crystal. There exist lattice parameter

a

Fig 11.1 ● The diamond structure. Lattice parameter is denoted as a.

measurement methods that give its absolute value with an accuracy of the order of 10�7, namely the Bond method [1] and simultaneous X-ray and optical inter ferometry (XROI) [2]. XROI measurements performed for pure silicon at 22.5°C under vacuum independently by different groups [3–5] gave results that were consistent within estimated errors (Table 11.1) and only slightly higher than those obtained by Cohen [6]). Other measurements reported besides XROI give a broader value range, which is, however, still quite nar row (3 � 10�6 Nm) [8]. All the theoretical calculations using force-ﬁeld methods correctly describe bulk silicon in its diamond structure ground state, giving a value for the lattice parameter that is close to the value that is experimen tally observed (Table 11.2). This is, however, natural, because all the semiempirical potentials, including tightbinding (TB) ones, are constructed so as to provide a correct description of the silicon ground state and use the correct lattice constant as a ﬁtting parameter. The potentials are also ﬁtted so as to accurately describe the energy needed to create small displacements from equilibrium, elastic constants, and phonon frequencies (see the next section). More accurate ab initio calcula tions also reproduce the experimental lattice parameter

Table 11.1 The lattice parameter measured by XROI method (in Å)

[4]

[3]

[7]

[6]

5.427

5.44

5.41

5.38

179

Modeling in MEMS

PA R T I I

Table 11.2 The lattice parameter value (in Å) calculated using different methods

Lenosky TB [9]

Kwon TB [10]

Wang TB [11]

Sockboro TB [12]

Tersoff [13]

SW [14]

EDIP [15]

DFT (Ganchenkova) LDA GGA [328]

5.427

5.44

5.41

5.38

5.432

5.431

5.430

5.395

reasonably well (Table 11.2). However, as seen in the table, DFT (density functional theory) calculations with the use of the LDA (local density approximation) approximation slightly underestimate this value, whereas those using the GGA (generalized gradient approxima tion) approximation lead to the overestimation of it. The temperature dependence of the lattice param eter has been measured by different groups (see for example Refs. [16, 17]. Okada and Tokamuru [17], on the basis of their measurements of the silicon lat tice parameter in the temperature range from 120 to 1500 K, have proposed the following phenomenological relation for the linear thermal expansion coefﬁcient:

{

}

α(T ) � (3.725 1 � exp ⎡⎢�5.88 � 10�3(T � 124 )⎤⎥ ⎣ ⎦ �5.548 � 10�4 T) � 10�66 K�1 (11.1) where T is the absolute temperature (in K). This rela tion is accurate within 2 � 10�7 K�1. The lattice parameter is expressed in terms of the thermal expansion coefﬁcient as ⎤

⎡ a(T ) � a0 ⎢⎢ ∫ α(T )dT � 1⎥⎥ ⎥⎦

⎢⎣ 295.7 T

(11.2)

where a0 is the lattice parameter at 295.7 K, and α(T) varies from 0 to 4.5 � 10�6 K�1 when T changes from 130 to 1400 K.

In addition to the temperature, the silicon lattice parameter can be sensitive to the presence of impuri-

ties, which can lead to both lattice contraction and expansion, depending on the impurity atom size. This lattice contraction/expansion, Δa/a, is proportional to the impurity concentration, CI, and can be expressed as Δa � βCI a

(11.3)

where β is called the expansion coefﬁcient. There are both wanted and undesirable impurities in silicon. Oxygen and carbon are the most frequent impurities and are unwanted. Some X-ray diffractom eter measurements were done for these kinds of impuri ties [18] and expansion coefﬁcients β were determined (Table 11.3). The desired impurities (such as P, B, Sb, etc.) are introduced to the crystal in a controlled way 180

5.456

Table 11.3 Coefﬁcient β estimated for different impurities (in cm3/atom)

Impurity

β

O

(4.4 � 0.2) � 10�24

measured

[18]

C

(�6.9 � 0.5) � 10�24

measured

[18]

B

�5.46 � 10�24 from �4.5 � 10�24 to �5.6 � 10�24 �2.3 � 10�24

calculated measured

[19] [22–24]

measured

[20]

P

�0.77 � 10�24 �0.72 � 10�24 �1.0 � 10�24 �1.8 � 10�24

calculated measured measured measured

[20] [20] [24] [22]

Sb

2.8 � 10�24 2.8 � 10�24

calculated measured

[21] [21]

Reference

and often in concentrations below the level that is

detectable by the lattice parameter measurement tech niques. For cases where it is important to estimate the

lattice expansion/contraction due to dopants (e.g., when

one has to evaluate residual stresses in diffused wafers and devices), an analytical formula has been proposed [8]: ⎡ r � rSi ⎤ 1

⎥ β�⎢ i ⎢ r ⎥ ⎣ Si ⎦ N Si

(11.4)

where ri and rSi are the tetrahedral covalent radii of the dopant and silicon atoms, respectively, and NSi is the number of silicon atoms per cm3. This formula has been applied for the estimates of the expansion coef ﬁcient for a number of dopants, such as P [19], B [20], and [21]. The expansion coefﬁcient calculated using Equation 11.4 agrees well with most of those estimated experimentally.

11.1.2 Silicon Structure Ground State: Elastic Constants and Moduli The elastic constants provide a description of the elas tic response of a solid [25–27]. For single crystals, the

second-order elastic constants describe the linear elastic

Mechanical Properties of Silicon Microstructures

stress–strain response. Higher order elastic constants reﬂect the nonlinear elasticity of the material [26].

11.1.2.1 Harmonic Approximation and Room Temperatures The elastic constants are the system energy second derivatives with respect to the strains, deﬁned as εij �

∂u j ⎞⎟ 1 ⎛⎜ ∂ui ⎟⎟ ⎜⎜ � 2 ⎝⎜ ∂x j ∂xi ⎟⎠⎟

(11.5)

where u is the elastic displacement. Indeed, when the strains are sufﬁciently low, one can approximate the elas tic energy ΔE stored in a uniformly strained crystal as ΔE �

V Cij εi ε j 2

1 ∂2 E V ∂ε 12 1 ∂ 2 E C11 � C12 � , ε � ε1 � ε2 2V ∂ε2 C11 �

C44 �

B �

The elastic constants allow one to calculate the compo nents of the elastic stress from the known elastic strain according to Hooke’s law:

C11 � 2C12 3

1 μ � C44 � (2C44 � C12 � C11 ) 5

(11.10)

1 C12 � (2C44 � C12 � C11 ) 5 ν � ⎡ ⎤ 2 2 ⎢C12 � C44 � (2C44 � C12 � C11 )⎥ 5 ⎣ ⎢ ⎦⎥

(11.11)

and E � 2( 1 � ν )μ

(11.8)

(Note that here the stress and strain components are not in the Voigt but in the standard notation.) The usual way for measuring the elastic constants is the monitoring of ultrasonic velocities as a function of the external static pressure [28]. The ﬁrst measured values of silicon elastic constants were reported by McSkimin and coworkers [29, 30]. Later these constants were deﬁned more accurately by Hall [31] (Table 11.4). There exist several theoretical techniques for the cal culation of elastic constants, including molecular stat ics (MS), molecular dynamics (MD), and Monte-Carlo

(11.9)

and the reverse value—compressibility, K � 1/B, can be determined by imposing hydrostatic loading scheme (that is, ε1 � ε2 � ε3). The experimentally measured values of B and K for crystalline silicon are 97.84 GPa and 1.02 GPa�1, respectively [31], whereas the calcu lated values for B vary within 90–110 GPa. For practical characterization of material elastic prop erties we often use other parameters, such as the shear modulus, μ, Poisson’s ratio, ν, and Young’s modulus, E, which can be expressed in terms of the elastic constant tensor components (in Voigt’s notation) as

(11.7)

1 ∂2 E V ∂ε42

σii � C11εii � C12(ε jj � εkk ) σij � 2C44 εij ,(i � j)

(MC). The interactions between silicon atoms are described either with empirical interatomic potential (the best-known potentials are those of Stillinger-Weber (SW) [13, 14], and Lenosky [35], as well as the modiﬁed embedded atom method (MEAM) potential of Baskes [36] and the environment-dependent (EDIP) potential [37] or in the framework of TB and ab initio formula tions. Typically, the elastic constants are determined as strain derivatives of the calculated stresses or energy. By now, quite a number of theoretical calculations of these values have been reported [9–12, 32–34] (Table 11.4). The calculated elastic constants are sensitive to the choice of the interatomic interaction law, but most of them reproduce the experimental data reasonably well. The crystal bulk modulus B, deﬁned as

(11.6)

where Cij is the tensor of elastic constants, V is the crystal volume, the Einstein summation rule over the repeated subscripts is implied, and Voigt’s notation for the strains is used. The quadratic dependence of elastic energy on strains is usually called harmonic approxima tion. The total number of independent components of the elastic constant tensor depends on the symmetry of the crystal. In particular, crystalline silicon has cubic symmetry, which is fully characterized by only three independent constants:

CHAPTER 11

(11.12)

The deviation of the crystal elastic properties from full isotropy is characterized by either the anisotropy ratio, A, or anisotropy factor, H: 2C44 C11 � C 12 H � 2C44 � C12 � C11 A�

(11.13)

which in silicon are measured to be 1.56 and 574 GPa, respectively. The Voigt formulation is always appropriate for monocrystalline materials. However, for polycrystalline materials it can be used only when the grains of different 181

PA R T I I

Modeling in MEMS

Table 11.4 Comparison of theoretical and experimental values for second-order elastic constants for crystalline silicon (in GPa)

Method

Potential

Ref

C11

C12

C44

υ

μ

B

Y

Theoretical calculations MD

SW Tersoff Lenosky SWmod Baskes

[32]

161 141 164 161 161

80.5 74.0 83.0 80.5 63.3

60.2 68.9 70.5 80.4 76.9

0.291 0.261 0.274 0.250 0.221

46.9 45.3 50.5 53.6 58.2

108 98.1 110 108 97.6

138 138 151 161 164

MS

EDIP TB

[33] [9] [10] [11] [12]

172 167 150 154 128

64.7 66.5 56.3 69.9 75.3

72.8 75.4 89.0 69.0

0.233 0.232 0.177 0.252

65.1 65.4 72.2 58.3

100.5 100.1 87.6 98.1 93.0

161 161 170 146

LDA

[32] [34]

159 162

67.3 63.5

80.0 77.3

0.224 0.221

57.2 66.1

97.9 96.4

140 161

GGA

[32]

151

60.6

79.2

0.209

56.5

90.6

137

Experimental measurements T � 300 K

[29,30] 165.64 63.94

79.51

0.218

68

97.84

T � 300 K

[31]

165.70 63.9

79.6

0.218

60.5

97.8

T � below 100 K

[28]

167.72 64.98

80.36

orientations have the same stress. Otherwise, when the grains have the same state of strain or when long-range internal stress ﬁelds are involved, the Reuss formulation operates better [8].

11.1.2.2 Effect of Pressure At high-elastic strains the harmonic approximation becomes insufﬁcient to correctly describe the elastic energy. This was demonstrated for the ﬁrst time by McSkimin [29], who measured the Cij as a function of the applied hydrostatic pressure up to 8 GPa. He found some deviation of the Cij from the constant values already at some hundreds of MPa. There exist several ways to improve the energy descrip tion. One of these is to assume that the elastic constants themselves are the functions of the applied loads. Several calculations and measurements of the pressure depend ence of the second-order elastic constants have been reported in the literature (e.g., Table 11.5). However, the linear pressure dependence of the second-order elastic constants remains reasonable only up to some stress limit. 182

99.23

Table 11.5 The pressure derivatives of the second-order elastic constants for crystalline silicon

Reference

dC 11/dP

dC 12 /dP

dC 44 /dP

Calculated [38]

4.9

4.9

2.1

Measured [30]

4.2

4.2

2.7

An alternative way to treat the nonlinearity effects is to include the higher than second-order terms in the formal expansion of the elastic energy in strains. The coefﬁcients in these expansion terms are referred to as higher order elastic constants. Cubic crystals have six independent third-order elastic constants Cijk. They are usually described using the Lagrangian form (see for example Ref. [39]. The alternative form is the Eulerian form, where the basic difference lies in the coordinate system being ﬁxed or following the solid under defor mation. These constants have been measured using the ultrasonic method by McSkimin [29] and Hall [31] (Table 11.6).

Mechanical Properties of Silicon Microstructures

CHAPTER 11

Table 11.6 Comparison of theoretical and experimental values for third-order elastic constants for crystalline silicon (in GPa)

Method

C111

C112

C123

C144 � 2C166

C456

[39]

�750

�480

~0

�580

�80

[34]

�810

�422

�61

�555

�61

[31]

�795 � 10

�445 � 10

�75 � 5

�605 � 10

�86 � 5

[30]

�825 � 10

�451 � 5

�64 � 10

�608 � 10

�64 � 5

Reference

Theoretical calculations DFT/LDA

Experimental data T � 298 K

One of the methods used for calculation of the higher order elastic constant was introduced by Nielsen and Martin [39]. It implied the use of the stress theo rem within density-functional theory and exploited the method of homogenous deformation. Later Zhao et al. [34] slightly modiﬁed the methods in a way that allowed their use for complex crystal lattices. The elas tic constant values calculated with these methods repro duce the measured values within 20 GPa, except for the C123 value calculated by Nielsen and Martin [39], which is almost zero (Table 11.6). There are two different expressions for the relation ship between the volume and pressure. The ﬁrst is the Murnaghan equation, which assumes the bulk modulus varies linearly with the pressure:

P�

�B� ⎛ ⎞⎟ B ⎜⎜⎛⎜ V ⎞⎟ ⎟ ⎜⎜⎜⎜ ⎟⎟ � 1⎟⎟ ⎟⎟ B� ⎝⎜⎝⎜ V0 ⎠⎟ ⎠

(11.14)

�B� ⎛ ⎞⎟ B ⎜⎜⎛⎜ V ⎞⎟ ⎟⎟ ⎟ � 1 ⎜⎜ ⎟ ⎟⎟ B� ⎜⎝⎜⎜⎜⎝ V0 ⎟⎠ ⎠⎟

(11.15)

Another relation is found by relating the ﬁrst two terms in the Eulerian stress–strain relation, the Birch equation: P�

�7 /3 ⎛ ⎛ V ⎞�5 /3 ⎞⎟⎟ 3 ⎜⎜⎜⎛ V ⎟⎞ ⎟⎟ B⎜⎜⎜ ⎟⎟ � ⎜⎜⎜ ⎟⎟⎟ ⎟⎟ ⎜⎝ V0 ⎟⎠ 2 ⎝⎜⎜⎜⎝ V0 ⎟⎠ ⎠

⎧⎪ ⎛⎛ ⎞�2 /3 ⎞⎟⎪⎫ ⎪⎪ ⎪ ⎜⎜⎜ V ⎟ 3 ⎟ * ⎨1 � (B� � 4)⎜⎜⎜ ⎟ � 1⎟⎟⎟⎪⎬ ⎜ ⎟ ⎟ ⎪ ⎪ ⎜ 4 ⎝⎜⎝ V0 ⎠ ⎠⎟⎪⎪⎭ ⎪⎩⎪

B� � 4 � �

c111 � 6c112 � 2c123 9B

(11.17)

The Birch equation gives signiﬁcantly better ﬁt than Murnaghan’s one, and in fact no higher order terms are required for describing the PV results within the cal culational accuracy. The calculated values of B� is 3.99 [34], which correlates reasonably well with the value of 4.11, measured at 298 K [31]. In engineering practice one often meets anisotropic (nonhydrostatic) loading schemes. For example, biax ial strain in the (001) plane can arise during the growth of a thin silicon ﬁlm on a (001) substrate with a differ ent lattice constant. In this case the strain tensor can be decomposed into hydrostatic, εh, and shear, εs, parts as 2(1 � 2C12 /C11 ) εxx 3 (1 � 2C12 /C11 ) εs � � εxx � 3 where (as � a f ) εxx � af εh � �

where the bulk modulus derivative in Lagrangian theory is expressed as

P�

where the bulk modulus derivative in Eulerian theory is expressed as

(11.18)

The hydrostatic component of the strain affects only the interatomic bond length, while the shear part changes only the angles between interatomic covalent bonds. In the case of the biaxial strain applied in the (111) plane the elements of the strain tensor are 2C44 ε|| 2C44 � C11 � 2C12 C11 � 2C12 εs � ε|| 2C44 � C11 � 2C12

εh �

(11.16)

(11.19)

where � is the in-plane lattice mismatch strain. 183

Modeling in MEMS

PA R T I I

11.1.2.3 Effect of Temperature, Doping and Defects A number of measurements of the elastic constant tem perature dependence have been reported [29, 31, 40, 41]. For instance, McSkimin [29] scanned the temperature range of 77–300 K, Hall [31] that of 4.2–310) K, and Burenkov et al. [40] up to 1273 K. The data for the tem peratures up to 1477 K are compiled in [41]. According to all the experimental measurements, below 100 K the second order constants remain practically the same as those extrapolated at 0 K (Figure 11.2), as discussed in Section 11.1.2.1 (Table 11.4). At higher temperatures Cij increases linearly with temperature (Figure 11.2) at the rates speciﬁed in Table 11.7. The linear elastic con stant change with temperature is conﬁrmed by theoretical calculations (Table 11.7) [42, 43], where the considered temperature interval was 888–1417 K. The calculated elastic constants and their ratios for different tempera tures are summarized in Table 11.8. Unfortunately, quantitative agreement between the calculated and exper imentally measured values is poor (Tables 11.7 and 11.8). The reason is that the calculations used SW potential,

16.8

C11

16.7 16.6 16.5 16.4

Elastic moduli (GPa)

16.3 C44

8.1 8.0

7.8 5.2 5.1 5.0 4.9 (C11 – C12)/2 4.8 50

100

150

200

250

300

Temperature (K)

Fig 11.2 ● The temperature dependence of the second order elastic constants for pure and n-type doped silicon. The samples of silicon are doped with ~2 � 1019 (P atoms)/cm3. Source: Data from [31].

184

11.1.3 High-Pressure Silicon Structures The silicon ground state structure has been shown to be stable up to the melting point [8]. However, pressureinduced phase transformations have been experimentally observed at high pressures. Twelve different high-pressure phases have been identiﬁed so far (Table 11.10). The con ditions for the phase transformation are different. Some of the phases are thermodynamically stable when pres sure exceeds some critical values and form directly from the cubic phase. The others transform from high-pressure phases. For example, Cannon [47], using X-ray diffraction with synchrotron sources, has shown that the transforma tion sequence with the increase of the pressure is

7.9

0

which is not well ﬁtted to the experimentally measured elastic constants at the ambient temperature (Table 11.4). It has been shown that the temperature dependence of elastic constants in silicon is strongly affected by the doping [31, 45]. This effect has been investigated for the cases of both heavily doped n-type silicon with the carrier concentrations of 2.0 � 1019 cm�3 (phosphorus doping) [31] and 4.8 � 1019 cm�3 (arsenic doping) [45], and for the case of heavily doped p-type silicon with the dopant concentrations of 5 � 1017 cm�3 (boron) and 3 � 1019 cm�3 (gallium) [46]. Quantitatively, doping modiﬁes elastic constants within 1–3%, but qualitatively the temperature dependence can be changed completely (see, for example, Figure 11.2). In addition to doping, silicon elastic constants are affected by the presence of intrinsic point defects. This was investigated theoretically by Allred et al. [33], where they considered interstitials, vacancies, and Frenkel pairs (FPs) using MS method with EDIP potential. For all these kinds of defect, the dependence of the elastic con stants and bulk modulus on defect fractions is found to be linear (see Table 11.9). The different elastic constants change most isotropically by vacancies: The increase of vacancy concentration leads to the softening of the elas tic constants within 1.51–1.74%. In contrast, the increase of interstitial concentration leads to the decrease of C44, the increase of C12 and no change of C11 (Table 11.9). A similar situation is found for FPs. The elastic con stants vary between �0.12–3.25% and �1.92–1.70% for interstitials and FPs, respectively. The effect of the point defect concentration on the temperature depend ence of the elastic constants can also be expected, even though we could not ﬁnd the information about this kind of experimental measurements in the literature.

I – II – XI – V – VI – VII – X This sequence is characterized by the smooth transition from one phase to another, so that phase pairs coexist over a wide range of pressure. When the high-pressure phase is already formed and the decompression experiment is

Mechanical Properties of Silicon Microstructures

performed for this phase, the transformation sequence can be different from the “compression” one and depends on the pressure release condition. Thus, the sequence observed in [64] is V – XI – II – XII – III.

CHAPTER 11

The formation of some high-pressure phases requires also some heating [57] or plastic deformation at moderate temperatures (670–970 K) [59]. An example is the phase Si-IV, which is formed from the metastable

Table 11.7 The temperature dependence rates of the elastic constants, *10�5

Reference Method

Potential

⎛ 1 ⎜⎜ ⎜⎜⎝ C

⎟⎞⎟ dC 11 �1 ⎟⎟ ,K 11 ⎠ dT

⎛ 1 ⎜⎜ ⎜⎜⎝ C

⎟⎞⎟ dC 12 �1 ,K ⎟⎟ 12 ⎠ dT

⎛ 1 ⎜⎜ ⎜⎜⎝ C

⎟⎞⎟ dC 44 �1 ⎟⎟ ,K 44 ⎠ dT

Theoretical calculations [157]

MC

SW

�7.89

�2.36

�16.1

[267]

MD

SW

�6.65

�3.35

�30.4

[41]

�9.66

�14.5

�6.41

[44]

�9.4

�9.8

�8.3

[40]

�9.3

Experimental studies

�10.0

Table 11.8 The temperature dependence of the elastic constants and their ratios (in GPa)

Reference

Method

Potential

T, K

C11

C12

C44

υ

μ

B

Y

[42]

MC

SW

888 1164 1477

141.28 136.96 133.76

75.20 74.56 74.08

51.20 47.36 45.44

0.304 0.312 0.317

43.94 40.90 39.20

97.23 95.36 93.97

114.55 107.34 103.24

[43]

MD

SW

888 1164 1477

139.20 137.12 132.96

75.20 74.24 73.60

52.80 45.60 41.92

0.300 0.316 0.325

44.48 39.94 37.02

96.53 95.20 93.39

115.67 105.11 98.11

[41]

Exp.

888

157.28

60.48

75.20

0.218

64.48

92.75

157.05

1164 1477

152.32 147.84

58.88 57.44

73.12 69.76

0.218 0.221

62.56 59.94

90.03 87.57

152.38 146.41

Table 11.9 The elastic constant and bulk modulus dependence on the point defect fraction (data from [33]). The point defects considered are vacancy (V), interstitials (I), and Frenkel pairs (FP)

Defect

Elastic constant change within the defect fraction interval of 0–0.3%

The defect fraction rate of the elastic constants

ΔC11

ΔC12

ΔC44

ΔB, %

⎛ 1 ⎜⎜ ⎜⎜⎝ C

⎞⎟ dC ⎟⎟ 11 ⎟ 11 ⎠ d η

⎛ 1 ⎜⎜ ⎜⎜⎝ C

⎞⎟ dC ⎟⎟ 12 ⎟ 12 ⎠ d η

⎛ 1 ⎜⎜ ⎜⎜⎝ C

⎞⎟ dC ⎟⎟ 44 ⎟ 44 ⎠ d η

⎛ 1 ⎞⎟ dB ⎜⎜ ⎟ ⎜⎝ B ⎟⎠ d η

V

�1.74

�1.55

�1.51

�1.69

�0.06

�0.05

�0.05

�0.06

I

�0.12

3.25

�1.79

1.29

0.00

0.11

�0.06

0.04

FP

�1.92

1.70

�3.30

�0.40

�0.06

0.06

�0.11

�0.01

185

PA R T I I

Modeling in MEMS

Table 11.10 Crystalline phases of silicon

Structural parameters Notation

Structure

Pressure region

Reference

Si-I

Diamond cubic

0–12.5

[47,48]

Si-II

Body-centered tetragonal (β-Sn)

8.8–16

[48–53]

Pressure regions

Lattice parameters

11.2

a � 0.469 c � 0.258 a � 0.469 c � 0.259 a � 0.467 c � 0.257

12.5 10.3

Si-III (BC8)

Body-centered tetragonal (basis of 8 atoms)

2.1–0

[48–50,54]

0 2

Si-IV

Si-V

Diamond hexagonal

Primitive hexagonal

–

14–35

[56–61]

[48,53]

16 16 18 36

Si-VI

Unidentiﬁed

34–40

[53,62]

Si-VII

Hexagonal close packed

40–78.3

[50,53,63]

41–42 43

Si-VIII

Tetragonal (30 atoms per unit cell)

14.8–0

[64]

Reference

[48] [51] [52]

a � 0.575 α � 109.47° a � 0.575 α � 109.47°

[55]

a � 0.38

[57]

c � 0.628 a � 0.386 c � 0.631

[58,59]

a � 0.255 c � 0.239 a � 0.253 c � 0.237 a � 0.254 c � 0.238 a � 0.246 c � 0.631

[55]

[48,50] [53] [52] [62]

a � 0.252 c � 0.414 a � 0.244 c � 0.415

[50]

a � 0.863

[64]

[53]

c � 0.750 Si-IX

Tetragonal (12 atoms per unit cell)

12–0

a � 0.775

[334]

[64]

c � 0.389 Si-X

Face-centered cubic

78.3–230

[62,63]

87 � 7

a � 0.467

[62]

Si-XI (Imma)

Body-centered orthorhombic

13–15

[52]

~13

a � 0.474 b � 0.450 c � 0.255

[52]

Si-XII (R8)

Trigonal (8 atoms per unit cell)

12–2.0

[55,65,66]

8.2

a � 0.562 α � 110.07° a � 0.571

[55]

2

186

[55]

Mechanical Properties of Silicon Microstructures

Si-III. In [56, 60] Si-I transformation to Si-IV has been described as martensitic transformation after secondary twinning, like that related to deformation twinning. Many theoretical calculations have addressed this problem. All the calculations are based on the calcula tions of the total energies of different structures at zero temperature. Most of the calculations are performed within the ab initio approaches, such as the densityfunctional theory with LDA [67, 68] and GGA [69], or linear mufﬁn-tin-orbitals (LMTO) [69]. In some of the works the full sequence of transformations has been considered [68, 70, 71]. These calculations show good agreement with experimental observations.

11.2 Dislocations in Silicon Extended defects could be classiﬁed with respect to their dimensionality: Dislocations are 1D (linear) defects, grain boundaries and stacking faults are typi cally 2D (planar) defects, and secondary phase pre cipitates are defects of 3D (volume) type. Extended defect effects on the device functionality can be both detrimental (for instance, the degradation of electronic properties of semiconductors) and beneﬁcial (e.g., when their presence enhances the efﬁciency of a chemical reaction or some other process that reduces nonradia tive recombination centers in semiconductors). It is technologically very difﬁcult to grow singlecrystal semiconductor samples for microelectronic and optoelectronic applications that would be totally devoid of extended defects, or, at least, of dislocations. In this sense silicon is nearly the unique exception. It is rela tively easy to grow high-purity silicon single crystals with vanishing dislocation content, which makes silicon an ideal benchmark material for experiment, theory, (a)

CHAPTER 11

and modeling. Unfortunately, in practical applications it is often impossible to avoid the conditions (such as temperature gradients during the bulk crystal growth, or lattice misﬁt in heteroepitaxial growth) that promote the nucleation of dislocations. Dislocations, stacking faults, twins, and internal sur faces are nonequilibrium defects and their density must not depend on temperature according to the Arrhenius exp(�E/kT) law. Their presence adds some contribu tion to the internal energy of the material that depends on the nature of a particular defect and on its linear or surface energy density. The fact that extended defects introduce an excess of internal energy into the crystal raises, in particular, the question of their interaction with atomic defects and impurities.

11.2.1 General Remarks Plastic strain of a crystal in response to shear stress application results from multiple displacements along the crystallographic slip planes. Dislocations are line defects representing the boundary between the region where the slip has already occurred and a still-perfect region of the crystal. Therefore a dislocation line can not terminate in a perfect region of the crystal, but either forms a closed loop or terminates at an internal or external surface or at another dislocation. Away from the dislocation line the crystal is locally only negligibly different from the perfect crystal. One of the basic parameters characterizing a disloca tion is its Burgers vector b, which deﬁnes the amount of slip caused by the dislocation (Figure 11.3). Dislocations with Burgers vector equal to a lattice vector are called perfect; otherwise they are referred to as partial dislo cations. The partial dislocations are always associated (b)

1

1

2

2

S

S F

3

F

t2

b t1

Fig 11.3 ● Comparison of a lattice plane of a faulted crystal containing an edge dislocation (a) and of a perfect crystal (b). When we use a Burgers loop procedure (see text) from S to F both on the perfect and in the faulted crystal, we must perform an extra step to close the loop in the perfect crystal.

187

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with stacking faults. In many materials the stacking fault energies are too high for partial dislocations to exist. However, in some special structures, such as FCC (face centered crystal) lattice, there exists a restricted number of planes with low stacking fault energies. The most energetically stable perfect dislocations in the diamond type lattice have Burgers vectors of ½ �110� type, which correspond to the shortest primitive lattice vectors in silicon. The preferable glide planes are {111}-planes. These two factors deﬁne the operative Burgers vectors and slip planes, so that the preferable slip systems in diamond-cubic crystals are 1/2[110](111), the same as in FCC metals. It is well known that the diamond structure can be interpreted in terms of two interpenetrating FCC lat tices, one of which is displaced by (1/4, 1/4, 1/4) with respect to the other. Due to the coexistence of two FCC sublattices, there exist two different sets of (111) planes, such as, for example, b and B in Figure 11.4. Thus the silicon structure can be considered as a periodic stack ing of three pairs of {111} layers … aA bB cC aA … In this structure, low-energy stacking faults involve the insertion or removal of the pairs of planes aA, bB, or cC. Correspondingly, two types of stacking fault exist: a. cC aA bB | aA bB cC… , called intrinsic stacking fault (ISF), corresponds to the removal of one double layer (cC in this example). Another formation of this stacking fault is a shear of the upper half of the crystal by a/6 �112� , which puts the cC layer into aA position. b. cC aA bB | aA | cC aA bB cC… , called extrinsic stacking faults (ESF), corresponds to the insertion of one extra double layer (aA in this example). These stacking faults are created, for example, when an experimental treatment (such as silicon wafer oxidation) produces excess of interstitials that condense into dislocation loops. The low energy of these stacking faults is a consequence of their atomic structure, where nearest and second

Fig 11.4 ● Preferred dislocation line directions in silicon.

188

nearest neighbor distances and angles between atoms remain unchanged compared with the perfect silicon lattice. Most of the binding energy resides in nearest neighbor covalent bonds, and the energy of the crystal changes only slightly when SF is formed. The double-layer stacking of {111} planes in the diamond structure allows us to distinguish two sets of planes that one could call narrow-spaced planes and widely spaced planes [72, 73]. Following this classiﬁca tion, one can deﬁne two sets of dislocations formed by shear between either the narrow-spaced planes, such as B|c (“glide set dislocations”) or the widely spaced planes, such as b|B (“shufﬂe set dislocations”) [72, 73]. The fundamental difference between these two sets is that narrow-spaced planes are connected by three times more covalent bonds than widely spaced planes. Thus, generally speaking, a low-energy stacking fault can only be created between widely spaced planes. However, it is now commonly accepted that dislocations usually belong to the “glide set” [74], though the local transformations to the “shufﬂe set” can occur in some circumstances, for example when the dislocation absorbs or emits single point defects—vacancies or self-interstitials [75]. Dislocations are often characterized also by the angle β between the dislocation line direction and the Burgers vector. There exist two fundamental types of straight dis locations: edge dislocations, where the Burgers vector b is perpendicular to the dislocation line (β � 90°), and screw dislocations, with b directed parallel to the dislocation line (β � 0°). The edge dislocation in crystalline lattice looks like a line of unsaturated lattice atoms that termi nates an extra lattice half-plane. When β is neither zero nor an integral multiple of /2, the dislocation has a mixed character (combining both edge and screw counterparts). Two types of dislocation in silicon are of special inter est: screw dislocations and 60° dislocations for which β � 60°. These preferred orientations correspond to lower core energies. In terms of the Peierls–Nabarro model of dislocation core [73], these types of disloca tions lie in the valleys of Peierls potential.

Mechanical Properties of Silicon Microstructures

The elastic energy per unit dislocation length, which is conﬁned within a cylinder of radius R around a gen eral straight dislocation, is deﬁned as [73] W μb2 ⎛⎜ 2 sin2 β ⎞⎟⎟ αR ⎜cos � β � ⎟ ln L 4π ⎝⎜⎜ b (1 � ν)⎟⎠

(11.20)

where μ is the shear modulus of the bulk material, ν is the Poisson’s ratio, and α is a parameter representing the core energy of the dislocation. As follows from Equation 11.20, the most stable dislocations are those with the shortest Burger’s vectors b. On the basis of this consider ation, the so-called Frank criterion for the dislocation dis sociation can be formulated. Namely, the dissociation of a dislocation with Burgers vector b1 into a complex system consisting of two partial dislocations (called Shockley partials) with Burgers vectors b2 and b3 occurs if b12 � b22 � b32

(11.21)

An immediate consequence is that a dissociated dislo cation is unstable when the interaction force between partial dislocations is attractive and stable when the interaction is repulsive. The resulting partial disloca tions have different core structures or different Burgers vector orientation and are connected with a low-energy stacking fault. The dissociation decreases the excess internal energy of undissociated defect, which is due mostly to elastic strain. The stacking fault contribu tion to the internal energy of the system is negligible in comparison with the internal energy decrease due to the formation of partials, provided their interaction is repulsive. It should be noted, however, that dislocations lying in the shufﬂe set cannot directly dissociate in par tials, because this process is accompanied by the forma tion of a high-energy stacking fault. In order to make dislocations change their positions, one needs to apply external elastic stress above a cer tain threshold. In general, the minimum stress required to move a dislocation is a function of temperature and the time over which dislocation motion is observed. However, the minimum stress for which dislocation starts to move at zero absolute temperature, which is also referred to as the Peierls stress, is a materialdependent parameter, which can be determined by numerical simulations for each particular dislocation type by molecular-static geometry optimizations. On the other hand, the Peierls stress can be obtained exper imentally from the measurements of the yield stress at vanishingly low temperatures [74]. Thus, the Peierls stress as a measure of intrinsic lattice resistance to dis location motion can be used, in particular, as a means to correlate experiments and simulations. On the atomistic scale, the conservative dislocation motion (or glide) involves local atomic displacements

CHAPTER 11

that proceed through switching one or a few interatomic bonds at a time. Hence, this kind of motion is sensitive to the energetics of bond switching required for dislo cation translation by a unit atomic distance in the glide plane and thus is deﬁned by the core structure of the moving dislocation, because the relative displacement of the core atoms contributes most to the energetics of dislocation motion. From the purely geometrical con siderations, the shufﬂe-set should be energetically more favorable for dislocation gliding than glide-set. Indeed, it was demonstrated by computer simulations (see Refs in [74]) that the shufﬂe-set gliding of the dislocation implies the breaking of the least number of bonds during the dislocation movement, and the glide-set is the set of planes on which dislocations move. Gliding is not the unique mode of dislocation move ment. Another mode, named climb, is a dislocation movement due to building up or eating out of the dis location extra-plane, so that the dislocation crosses its glide planes. Evidently, climb requires addition or removal of atoms and is non-mass-conservative, in con trast with glide, which, as mentioned above, is a mass conservative movement. Due to the necessity for mass transfer, climb contribution to dislocation mobility and plastic deformation is important only in quite special conditions (such as fast particle irradiation), which pro vide a noticeable excess of intrinsic point defects.

11.2.2 Dislocations in Silicon: Simulation Approaches Silicon has been a favorite material for theoretical and experimental investigations of dislocation nature and mobility. However, many issues still remain unresolved. Atomistic modeling coupled with experimental observa tions should be able to resolve these issues. The early dislocation modeling treated the crystal as an isotropic elastic medium. The models belonging to the continuum approach allowed simulations of dis location movement taking into account the long-range interactions between dislocations and the interaction of impurities with dislocations, which were considered impurity sinks or heterogeneous catalysts for precipita tion. Therefore this approach is also called Dislocation Dynamics. However, as early as the 1960s it was real ized that a reﬁnement of these models would only be possible when detailed information about the intera tomic forces was available [76]. Indeed, while the crystal outside the dislocation core region is distorted only slightly and, therefore, is well described within a linear elastic framework, the large lattice distortions inside the core region require atom istic treatment. Because the core structure is the basic fundamental property of the dislocation, which largely 189

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Modeling in MEMS

deﬁnes the dislocation behavior (see e.g., Refs. [77, 78]), one of the central problems of dislocation mod eling is the development of realistic atomistic models of the core. In general, core contribution to the line energy can be evaluated for different dislocation types using interatomic potentials, TB models, and ﬁrst principles methods. During the last few decades there were several attempts to address this problem using semiempirical and ab initio calculations (see Ref. [74] and references therein). In these attempts the core structure was deter mined via the MS geometry optimization, where the total energy was minimized with respect to the atomic positions at zero temperature. The difference between the computational approaches is in the way of descrip tion of interatomic interactions. The simplest approach is to use the so-called valence force-ﬁeld potential, as that proposed by Keating [79], which emphasizes the sp3 bonding picture and adds bond-bending terms of the correct symmetry to a bonding pair potential. The ideology of these potentials stems from the existence of covalent bonds among neighboring atoms with the ﬁxed four-fold atomic coordination. In order to treat atoms with lower coordinations the concept of dangling bonds was introduced. Correspondingly, two parameters were introduced, one for the harmonic bond stretching term, and one for the harmonic bond bending term, which is a function of the scalar product between the vectors con necting the atom to its covalently bonded neighbors. The Kitting potential ideology in various versions and with different parameterizations has been widely used to study the elastic and static properties of cova lent semiconductors [80, 81]. The interatomic range covered by proposed potentials varied from close near est-neighbor distance [14, 79, 80, 82, 83] up to several neighbor shells [84, 85]. Though simple semiempirical potentials are able to reproduce both the elastic constants and the pho non spectra of silicon, they cannot take into account the excess electronic energy of the dangling and overcoordinated bonds, which, according to different esti mates, varies from 0.5 to 2 eV [86–88], [327]. In order to extend the potential validity range away from near-tetrahedral coordination, an ab initio data-ﬁtted EDIP has been proposed, which is able to reproduce quantum mechanical-based dislocation results for the 90° and 30° partials [15]. However, even the best avail able potentials are unable to reproduce all experimental situations. For instance, the screw dislocation mobility, which depends critically on the subtle details of the core struc ture, is poorly described by the existing interatomic potentials. Also, none of the semiempirical potentials can tackle problems related to the charge effects. The fact that defects in silicon can be charged is important 190

for the proper understanding of interactions between intrinsic point defects and the dislocation core, because point defects often act as the controlling factor for dis location motion. The latter effect of electromechanical coupling is expected to result in promising technological applications. All such problems are the subject of the ﬁrst principles calculations. Ab initio density functional theory calculations are considered nowadays to be the most accurate approach among those currently in use. Unfortunately they also have strong limitations, though the situation is expected to improve with the increasing current capabilities of the DFT methods in combination with the development of more powerful computers and better algorithms. In particular, they suffer from the artifacts of boundary conditions in small computational cells. There exist two main approaches to deal with the fact that in any computational approach only a small piece of the crystal (simulation cell) with only a ﬁnite number of atoms is simulated. These are usually referred to as “supercell” and “cluster” methods. The ﬁrst approach implies periodic repetition of a simula tion cell (or supercell), which evidently results in an inﬁnite superlattice of defects. The advantage of this approach is that simulated defects are embedded in an inﬁnite elastic medium. However, where dislocations are involved, the approach faces a number of problems. First of all, the sum of the Burgers vectors in the simu lation cell must be zero in order to avoid the divergence of the elastic strain energy of the crystal. This means that the simulation cell must contain at least two dis locations. Second, due to the periodicity of boundary conditions, dislocations in the supercell can interact with an inﬁnite number of “mirror” dislocations. When the supercell is not sufﬁciently large, these interactions can affect the atomic and electronic structure of the simulated dislocation. Finally, due to the fact that the introduction of a dislocation into a material destroys the translational symmetry of the lattice in a plane orthogonal to the dislocation line, there appear prob lems with lattice mismatch at the cell boundaries. As a possible way to cope with this problem, it has been proposed to distort some of the bond lengths and angles at the boundary of the cell in order to create a periodic structure [86, 89, 90]. Another possible solution, which was extensively used, is a dislocation quadruple method, where a lattice of dislocation quadruples is introduced in the crystal [91]. The second approach is the so-called cluster method, where a ﬁnite cluster surrounding the defect is con structed. In contrast to the supercell approach, this technique allows us to treat an isolated dislocation. However, the cluster method is also not an ideal choice. First of all, the cluster should in any case be sufﬁciently large in order to reasonably reproduce the long-range

Mechanical Properties of Silicon Microstructures

dislocation elastic ﬁeld and minimize the effects of lat tice structure distortions at the cluster surface. Second, one has to care about a proper way of the cluster sur face termination, because the surface atoms are asso ciated with dangling bonds that affect the calculated electronic properties of the cluster. In order to avoid these dangling bonds, they are usually passivated with hydrogen atoms, but, unfortunately, even that does not solve the problem, because the hydrogen atoms inter act with electronic states at the valence and conduction band edges [8]. Thus, all individual dislocation simulation techniques have their shortcomings. In order to compensate for these shortcomings, the modern trend is to combine different methods and approximations. During the last decade, the combination of atomistic and con tinuum approaches became a common approach [92]. Namely, important parameters describing the disloca tion behavior, including their mobility and interactions, are deﬁned from atomistic simulations and then used as input for continuum approach techniques. In principle, such a multiscale approach, covering the broad range of time and length scales, can be used for computational prediction of overall crystal plasticity behavior from the underlying physics of dislocation motion.

11.2.3 Dislocations in Silicon: Dislocation Core Structures Since the dislocation core was found to have a sig niﬁcant effect on crystal plasticity (M.S. Duesbery, review), much effort has been dedicated to quantitative analysis of the dislocation core structure and its effects on the dislocation mobility. Dislocation core can exist in several metastable modi ﬁcations, which differ from each other by in-core atomic bonding topology. The difference between the core structures manifests itself in the difference of the core free energies, which, in turn, determine the stability of a particular core modiﬁcation. Atomistic simulation tools are currently the main approach for the investigation of dislocation core structure. Experiments are usually unable to provide precise information on the core ener gies. However, constantly evolving capabilities of highresolution electron microscopy (HREM) improve the situation with direct observations of the dislocation struc ture [93], thus opening new possibilities for the mutual veriﬁcation of computational and experimental data. For a long time static core properties were analyzed using semiempirical interatomic potentials (see Ref. [8]). At the same time a number of semiempirical TB calculation results of the dislocation core structure were reported [94]. The emergence of new capabilities for accurate ﬁrst-principles electronic structure calculation

CHAPTER 11

allows us to analyze the dislocation core in silicon and other semiconductors using density functional theory (see for example, Ref. [95]). Silicon is an exceptionally “friendly” material for DFT calculations, because its relatively low plane-wave cut-off energy allows quite large supercells to be used for calculations. In combination with a speciﬁc property of dislocations in silicon—that is, narrow dislocation cores—this allows us to incorporate two dislocations into a supercell of reasonable size without overlapping their cores. The resulted DFT total energy is a combi nation of core and elastic energies and its partitioning into these two contributions depends on the choice of the core cutoff parameter (or core reference radius). Therefore, comparing calculated core energies of various metastable core structures, one should be careful to use the same core cutoff parameter for all considered struc tures in order for such comparisons to be meaningful. As already noted, under moderate stress and tem perature conditions the �110� aligned dislocations in silicon dissociate into Shockley partials connected by an ISF. For the predominant perfect dislocations of 60° and screw types, the partials can be of 30° or 90° char acter (Figure 11.5), and the dissociation reaction could be written as 1 / 2[110] � 1/6[121] � 1/6[211] However, in the case of high strains the dissociation of edge dislocations into two 60° partials is also observed. Most of the theoretical studies have concentrated on the glide set dislocations, which dissociate in a straight forward way and on the resulting partial dislocations. The disagreement between experimental measurements of dislocations [72, 96–99] and theoretically predicted dangling bond (unpaired electrons) density led to the conclusion that purely geometrical description of dislo cations as periodic arrays of dangling bonds in the core is not acceptable. On the basis of the TB calculations of band energy as a function of core structure, Jones [100, 101] and Marklund [87, 102] concluded that cores of both 30 and 60° partial dislocations can be partially or totally reconstructed. Later the core reconstruction was conﬁrmed by other atomistic calculations that used a number of different empirical potentials [8, 103–106]. Some examples of the proposed core reconstruc tion are presented in Figure 11.6. As one can see in this ﬁgure, the unreconstructed cores of dislocation lines, which separate the SF from the perfect crystal, contain dangling bonds. This can result in a total energy of the partials that is higher than the energy of their perfect nondissociated counterpart. However, the additional lattice distortions resulting in the pairing of the dan gling bonds (reconstruction) leads to a signiﬁcant energy 191

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Fig 11.5 ● (a) Perfect diamond lattice. Two layers of atoms, immediately above (white) and immediately below (dark) the glide-set (111) plane are shown. Each atom has four bonds, but the fourth bonds are out of the plane and are not shown. Stacking fault can be formed by dark atoms slipping into adjacent centers of the white triangular lattice in three ways. (b) The core of a 30º partial (unreconstructed), as an interface between the stacking fault and the perfect lattice. (c) The core of a 90º partial (unreconstructed).

Fig 11.6 ● Reconstructed core structures of partial dislocations in silicon. (a) DP core of 30º partial. (b) SP core of 90º partial. (c) DP core of 90º partial.

reduction. This model is consistent with the experi mental observations, indicating the observation that less than 3% of the atomic sites in partial dislocation cores have unpaired electrons [107]. As can be observed in Figure 11.6, the reconstruction of 90° and 30° partials occurs by formation of dimeric units oriented across or along the dislocation line, respectively. As a result, in the case of 30° partial dis location the repeat distance along the dislocation core changes from b � 1/2[108] to 2b. This type of recon struction is called double-period (DP) reconstruction. The reconstruction energy (deﬁned as the energy gain per unit dislocation length for the transition from the unreconstructed to the reconstructed conﬁguration) has been estimated in many theoretical works (Table 11.11). As follows from the reconstruction energy values pre sented in Table 11.11, all the calculations conﬁrm that DP reconstruction of 30° partial reduces its core energy quite signiﬁcantly (by 1.02 eV per dimer [109]). The semiempirical calculations with Tersoff [82] and EDIP potentials give the energy values close to that calculated with DFT approach. In contrast with 30° partials, 90° partial dislocation can reconstruct in two different ways (Figure 11.6b, c): by single-period (SP) and DP reconstructions. In the case of the SP reconstruction, the repeat distance along the dislocation is b, but there is no more mirror symmetry 192

Table 11.11 Core reconstruction energy (in eV/B � 3123456) of 3011partials from different calculations. The energy of DP core of (DP) core of 9012 partial is given relative to that of the SP, E

Potential

Reference

30°

SW

(Bualtov 1995)

0.81

Tersoff

[103]

0.54

0.46

EDIP

[110]

0.45

0.80

TB

[111,112] [108] [112]

1.38

0.69 0.69

[113] ~[109] [109] [114] [112] [115]

0.53 0.52 0.44

DFT

90° SP

90° DP

ESP – 0.21

0.42 0.88

ESP – 0.19 ESP – 0.26 ESP – 0.042

with respect to the plane perpendicular to the dislo cation line (Figure. 11.6b). The DP reconstruction is characterized by the break of both mirror and transla tional symmetries (Figure 11.6c). The reconstruction

Mechanical Properties of Silicon Microstructures

(a)

CHAPTER 11

(b)

Fig 11.7 ● Core structures of shufﬂe-set screw dislocation in silicon. The high-energy core atoms are shown in dark color. (a) Core A resides in a hexagonal ring. (b) Core B resides at the boundary between two hexagonal rings.

energy calculations for the 90° partial dislocation have not provided results as consistent as for 30° partials (Table 11.11). Depending on calculation approach the SP reconstruction energy varies from 0.42 to 0.88 eV/b (Table 11.11). However, all the calculations indicate that SP reconstruction energy is slightly higher than that for DP. The reported difference between the SP and DP reconstructions is less sensitive to calculation conditions and is about 0.22 eV/b, except for one DFT calculation [115] where this value was estimated to be ~0.04 eV/b, which would mean the coexistence of these two vari ants at the room temperature. The 60° partials are much less studied than 30° and 90° partials. This is the result of the fact that these par tials are formed only as an edge dissociation product, while the edge dislocation is predominant only in strongly compressed crystals [116]. The structure of the unrecon structed 60° partial dislocation can be considered to consist of two segments (30° and 90° segments) and involves three dangling bonds per repeat distance, which are roughly at an angle of 60° to the dislocation line. Two reconstruction modes are usually considered to be those leading to mini mal cores. The ﬁrst one implies the reconstruction of two dangling bonds from neighboring 30° and 90° segments, leaving one dangling bond per repeat distance uncompen sated. The second reconstruction mode leaves two dan gling bonds in every second 90° segment, which can be reconstructed later as in the usual 90° partial. The shufﬂe-set dislocations have not been considered to the same degree as the glide-set ones. However, the shufﬂe-set perfect screw dislocations can play the pre dominant role in low-temperature deformation. This is a commonly accepted interpretation of some experi ments [8, 117], which demonstrate the change of the deformation mechanism in silicon with temperature decrease (T � 450° C), as manifested in the bend ing of the yield stress temperature dependence curve. Another indication of this is also a change in the dislo cation microstructure [118].

Two different core structures for the perfect screw dislocations on the shufﬂe-set plane in silicon have been proposed, that is—core A [119] and core B [105] (Figure 11.7). Core A is centered at the intersection of two shufﬂe-set planes, whereas core B is at the inter section of a glide-set with a shufﬂe-set of planes. The features of the core A and B structures deﬁne their behavior during the low temperature–high stress experi ments: While dislocations with core A are likely to be involved in cross-slip, the dislocations with core B can dissociate into glide partials. Indeed, the results of ab initio calculations show that core B is a metastable conﬁguration whose energy exceeds the energy of the core A ground state by 0.32–0.38 eV/b [105, 120]. The earlier, less accurate calculations with semiempirical SW potential [14] predicted a lower energy difference of 0.14 eV/b [105]. It has also been demonstrated that core B is likely to be unstable at ﬁnite temperatures with respect to dissociation into glide par tials, whereas core A may be reasonably stable at lower temperatures and can contribute to plastic response.

11.2.4 Dislocations in Silicon: Core Defects The dislocation core can hardly exist as perfect and defect-free. In reality, secondary point-like defects are possible in the dislocation core. Moreover, “recon struction defects” (RD) are introduced during recon struction, such as anti-phase defect (APD), topological solitons, kinks and soliton-kink complexes. Among all the known defects the most important core defects are considered to be kinks, which control the mobility of dislocations at ﬁnite temperatures. Nowadays the major source of the information about the structure and energetics of core defects is computer simulations, whereas experimental evidences are still scarce and limited by the current HREM resolution. 193

Modeling in MEMS

PA R T I I

(a) S1 D

A1

A2

(b)

C

Fig 11.8 ● A solitonic defect in a reconstructed 30° partial dislocation in silicon {111} plane. The dangling bonds are oriented along the dislocation line in the �011� direction. Two possible conﬁgurations (Al and A2) of the three-coordinated silicon atoms are possible (after [124]).

So far all the reported theoretical calculations were con centrated on core defects in the glide-set partial disloca tions, leaving aside the shufﬂe-set perfect dislocations, which play an important role in low-temperature defor mation. Unfortunately, despite the effort spent, even for glide-set dislocations the energetics of core defects remain unclear. This is the main obstacle for the predic tive capabilities of dislocation mobility modeling.

(c)

(d)

11.2.4.1 Reconstruction Defects or Solitons During the process of dislocation core reconstruction irregularities in the reconstruction pairing of dangling bonds can be formed. In the case of the 30° partial recon struction each of the atoms belonging to the dislocation line can choose between two neighbors to bond with (Figure 11.8). As a result, there are two variants of recon struction, which are energetically degenerate and related to each other precisely by the broken-symmetry opera tion, namely translation by b. The soliton is a boundary that separates two perfectly reconstructed domains of opposite phase and is characterized by an isolated dan gling bond carrying atoms in the core. While the soliton on 30° partials is formed by break ing the mirror symmetry along the dislocation line, the symmetry for 90° partials is broken normally to the dis location line. The APD defect on 90° partial has several modiﬁcations: one for SP core and two for DP core, one of which is related to the translational symmetry, while another one is related to the mirror symmetry (Figure 11.9). The “translational” APD of DP core can be considered to consist of short segments of the SP core, the energy of which has been calculated to be ~0.4 eV [121]. Two more RDs have been considered in [121] (Figure 11.9) using the TB method, but were found to have higher energy of about 0.65 eV. 194

(e)

Fig 11.9 ● RD in the partial dislocation cores in silicon, indicated by vertical dashed lines. (a) RDs on 30º partial. (b) RDs on SP 90º partial. (c) RDs connecting DP 90º partial cores that are related by translation symmetry. (d) RDs connecting DP 90º partial cores that are related by mirror symmetry. (e) Combination of RDs in (f) with interstitial and vacancy. The ground state of the DP core is four-fold degenerate.

The values calculated using different approaches for both reconstruction energy and APD formation energy are compared in Table 11.12. As follows from the table, the results depend on the potential used for the calcula tions. However, EDIP gives the energies in close agree ment with ab initio data.

11.2.4.2 Core Vacancies and Interstitials One of the most powerful experimental techniques for the defect identiﬁcation in semiconductors is a combination

Mechanical Properties of Silicon Microstructures

CHAPTER 11

Table 11.12 Reconstruction energy (in eV/bond) and ADP formation energies (eV) (data from [110])

Table 11.13 Kink formation energies (in eV) in 30 partial dislocations in silicon (after [74])

Partial type

EDIP

SW

Tersoff

ab initio

Potential

Reference:

LK

SW

[77]

1.2

SW

(Bulatov 1995)

SW

30°

rec APD

0.45 0.49

0.81 0.82

�0 �0

0.43

90°

rec APD

0.40 0.65

�0 �0

0.37

0.44

of electron paramagnetic resonance (EPR) with electron dipole spin resonance (EDSR). This method applied to silicon samples after plastic deformation has shown several line centers in the spectrum, three of which were ascribed to vacancies inside the dislocation core, because they are not observed for all crystallographically equivalent orienta tions [122]. Kinks were excluded, when Lehto and Öberg demonstrated that these defects are fully reconstructed and possess only shallow levels [115]. Additional analysis of the orientation symmetry of the EPR signal and energy spectrum has shown that the three observed line centers could be ascribed to different vacancy conﬁgurations along the 30º partial [123, 124]. These three conﬁgurations are believed to be a vacancy with three neighboring atoms (V3c), vacancy with four neighboring atoms (V4c), and a linear chain of V3c defects [124]. The annealing experi ments show that the EPR signals associated with these defects disappear at temperatures higher than 800ºC. Justo et al. (Justo, 2000) via ab initio calculations showed that due to the positive binding energy of a vacancy and dislocation, vacancies in silicon tend to agglomerate in dislocation core. Indeed, while a bulk vacancy has the formation energy of ~3.6 eV, the energies of V3c, V4c, and V3c chain are signiﬁcantly lower, having values of 0.9 eV, 2.4 eV, and 1.9 eV per vacancy, respec tively, that clearly deﬁne the driving force for the vacancy redistribution towards dislocations. Moreover, HREM observations of the 30º partial dislocations show a density of core atoms of 0.5–1.5 per core site, suggesting the for mation of vacancy and interstitial segments in the core. In contrast, the same observations of 90ºC partial disloca tions show a perfectly reconstructed core structure with low concentration of vacancy and interstitial defects [75].

11.2.4.3 Kinks Ideally, dislocations are straight and at zero tempera ture occupy the �110� valleys, the low-energy “Peierls valleys” of the crystal. However, with, for example, the temperature increase a dislocation can arbitrarily choose the direction in the glide plane and climb from one glide plane to another one. Such dislocation consists of segments lying in neighboring parallel Peierls valleys in the same glide plane and of segments crossing a Peierls

RK

LC

RC

~0.82

0.82~

1.12

~0.79

[109]

0.98

0.65

1.29

0.79

EDIP

[110]

0.65

0.39

~0.90~ 0.83

TB

[111, 112]

0.35

1.24

0.88

HREM

[93]

0.80

TEM

[126]

0.90

IL

[127]

0.62

2.15

Experiment

Table 11.14 Kink formation and migration energies (in eV) in 90 partial dislocation in silicon (data from [54])

Potential

E eV

Em,eV

Reference

LR/R

LL

RR

LR/R

EDIP

[110]

0.70

0.84

1.24

0.62

Tersoff

[103]

0.12

Tersoff

[77]

0.50

TB

[128]

0.12

1.74.

2.04

1.87

TB

[111,112]

0.12

1.62

DFT

[129]

0.1

1.80

DFT

[130]

0.4

1.09

TEM

[131]

�0.4

�1.2

HREM

[93]

0.74

1.55

Experiment

hill. The dislocation segment where the dislocation line jumps over the Peierls barrier is called kink [73]. Kinks are the most extensively studied dislocation core defects, because their nucleation and migration along the dislocation line are the primary mechanisms of dislocation motion at ﬁnite temperatures [73]. The data on kink formation energy in 30° and 90° partials obtained both experimentally and via theoretical cal culations are summarized in Tables 11.13 and 11.14, 195

Modeling in MEMS

PA R T I I

respectively. As noted above, computational experi ments nowadays give the main contribution to the understanding of the core defect properties, allowing us, in particular, to distinguish between particular defect conﬁgurations, which is impossible to do in experi ments, where effective kink energies are obtained. Unfortunately, there is a poor agreement between the values reported by different groups (see Tables 11.13 and 11.14). This is a consequence of the fact that all the values have been calculated using different semiem pirical potentials and, probably, different calculation conditions (in particular—different treatment of the boundary conditions). Unfortunately the most accurate DFT calculations have not been widely applied to kink problems so far. Even those that are available produce results that are sometimes less accurate than semiem pirical type calculations [125]. The kinks denoted in Tables 11.13 and 11.14 as LK and RK are two different orientations of the kink, namely left (like BC in Figure 11.10) and right (like DE in Figure 11.10) kinks, respectively. It should be noted that the atomic conﬁgurations of LK and RK are differ ent from each other [74]. Other kink types, denoted in the table as LC and RC, are combinations of LK and RK with APDs, respectively. It has been found that over lap of the kink core and APD results in the signiﬁcant decrease of the energy. According to the SW potential calculations (Bulatov, 1995), the LK 1 APD � LC and RK 1 APD � RC reactions give the energy gain of 0.51 eV and 0.84 eV, respectively. However, TB calculations [111] give different values, namely 0.80 eV and 0.42 eV, where C

the LC reaction gains more energy than RC. Based on the SW potential calculations (Bulatov, 1995) it has been sug gested that kink reactions with APD defects can affect the kink migration, increasing or lowering, depending on the reaction type and its activation barrier. Taking into account that 90º partials have two com peting core reconstructions (SP and DP), a much more extended family of kink species can be imagined. The possible kink conﬁgurations are presented in Figure 11.11, where the different types of kinks are labeled according to their geometric characteristics [111]. For SP core four different types of kinks can be con sidered, labeled as LR, RL, LL, and RR in Figure 11.11a, b. However, according to the TB calculations [111] two of them, namely LL and RR, are unstable and spontane ously dissociate into LR and RL kinks emitting RD. For DP core of the 90° partial ﬁve different species of RD and eight topologically different species of kinks have been qualitatively described [109]. However, there has been little quantitative study of these defects, pro viding, at present, no information that could be used for the prediction of the 90° partial’s motion. Despite that, some suggestion has been made from the indirect data indicating the energy reduction due to the kink disso ciation [109]. Thus it has been proposed that kink dis sociation could make more kinks available for the 90° partial dislocation motion. Moreover, the existence of two types of Peierls valleys can also be the reason for the more pronounced mobility of 90° partials in con trast with 30° partial dislocations (Table 11.15). Unfortunately, nowadays it is very difﬁcult or prac tically, impossible to check experimentally the detailed theoretical predictions. The direct observation of kinks has been reported using a special HREM technique [93] that allowed a “plane-on” view of stacking faults using forbidden reﬂections. However, even this tech nique does not allow the imaging of the detailed atomic arrangements in the core of kinks and partial disloca tions; it provides only information about kinks, spacing.

D

B E A

Fig 11.10 ● Schematic representation of kinks on a dislocation line. (a)

LR

(b)

RR

RL

LL

(c)

(d)

LK

LK1

DP

196

LK2

SP

Fig 11.11 ● Kinks in 90º partial. (a) Kink pair LR and RL in a SP 90º partial. (b) Kink pair RR and LL on (SP) 90º partial. (c) A kink pair on DP 90º partial. (d) Dissociation of kinks shown in (c) into partial kinks bounding short segments of SP core (after [74]).

RK

RK1

DP

RK2

SP

DP

Mechanical Properties of Silicon Microstructures

Table 11.15 Kink migration energies (in eV) in 30 partial dislocations in silicon (based on data from [54])

Potential

Reference

LK

RK

LC

RC

SW

(Bulatov 1995)

0.82

0.74

0.22

1.04

EDIP

[110]

1.46

0.89

TB

[111, 112]

1.53

2.10

HREM

[93]

1.55

TEM

[126]

1.30

IL

[127]

1.58

Experiment

Nevertheless, this information is useful for direct com parison with theoretical predictions.

11.2.5 Dislocations in Silicon: Mobility There are two fundamental measures of the lattice resistance to the dislocation motion, namely Peierls stress and Peierls barrier. Both are related to the usually assumed mechanism of the dislocation transfer from a Peierls valley to a neighboring one (called Peierls– Nabarro mechanism [132]), which involves the nuclea tion of kink pairs and their subsequent propagation along the dislocation line until they either recombine or run away from each other, completing translation of the whole dislocation. When the stress is vanishing, the barriers for the kink forward and backward motion are equal. This balance becomes broken, however, when the shear stress in the dislocation glide plane is nonzero. In this case, one of the barriers decreases and the other increases, leading to the directed dislocation motion (glide). The condition, when one of the barriers vanishes completely, implies the reaching of the Peierls stress. Closely related to the Peierls stress is the Peierls barrier, which is the energy barrier that a straight dislo cation must surmount in order to shift to a neighboring Peierls valley. The Peierls barrier is deﬁned as energy per unit length of the dislocation line [72, 73, 96]. In the framework of the Peierls–Nabarro mecha nism the dislocation motion is a stochastic sequence of thermally activated, random kink-pair nucleation and migration events. Thus the dislocation velocity, V, is determined by the balance of kink-pair nucleation and migration rates under stress and can be expressed as [73] V � νD

⎛ E � Em ⎞⎟ τabh2 ⎟⎟ exp ⎜⎜⎜� k kBT kBT ⎠⎟ ⎝⎜

(11.22)

CHAPTER 11

where νD is the Debye frequency; τ is the resolved shear stress on the dislocation; a, b, and h are the dis location period, Burgers vector value, and kink height, respectively; and Ek and Em are the kink nucleation and migration energies, respectively. This model is very suc cessful for the description of the dislocation mobility in silicon and is widely used [74]. Some estimates, both theoretical and experimental, for Ek and Em for partials are summarized in Tables 11.13–11.15. When the tem perature is high enough, the Peierls barrier can totally vanish, which means that kink mechanisms play no or little role. In this case the dislocation mobility is con trolled by the viscous friction, which is deﬁned by the interaction between moving dislocations and phonons and electrons. The Peierls stress, as discussed above, is directly related to the yield stress (i.e., the macroscopic stress above which the crystal deforms plastically). Indeed, being deﬁned as the minimum stress for dislocations to move at zero temperature, the Peierls stress corresponds to experimental measurements of the yield stress at vanishingly low temperatures. The yield stress, τly , is, in turn, temperature dependent and over a wide range of temperatures (T � 700–1200 K) can be expressed as ⎛ Q ⎟⎞ ⎟ τ ly � Cly ε� n exp ⎜⎜⎜ ⎜⎝ nkBT ⎟⎟⎠

(11.23)

where Cly and n are temperature independent con stants, ε� is the strain rate, and Q is an activation energy of about 2 eV [72, 96], thus suggesting that plastic deformation or, in other words, dislocation motion is a thermally activated process. It should be noted, how ever, that beyond this temperature range there is a cer tain deviation from the Arrhenian behavior. At higher temperatures an increase of the activation energy is observed, which is explained either by the change of the self-diffusion mechanism [75, 133, 134] or by the effect of dislocation–dislocation interactions [135]. At lower temperatures both activation energy and yield stress become lower than predicted by Equation 11.23. The core reconstruction has been shown to have a strong inﬂuence on Peierls stress and, hence, on the dis location mobility [110]. It is commonly believed now that the low dislocation mobility in silicon and its brit tleness at low temperatures (T � 0.6Tmelt, where Tmelt is the melting temperature) is due to the high Peierls stress (tens of GPa) for the glide-set partials [8]. Gally et al. [136], in particular, suggested that dislocation nucleation and propagation are insufﬁcient to relieve the stress concentration at the crack tip, resulting in the brittle behavior of silicon. Several attempts to cal culate the Peierls stress have been performed using both semiempirical potentials [137] and ab initio [138, 139]. All of them conﬁrmed the high values of the Peierls 197

PA R T I I

Modeling in MEMS

stress for the glide-set partials. Moreover, Justo et al. [138, 139] have shown a strong relationship between the strength of partial reconstruction and the experi mentally measured activation energy Q of dislocation mobility. Using the SW potential, Ren et al. [137] estimated the Peierls stress of a perfect shufﬂe-set screw dislo cation to be ~5 GPa, but this seems to be an overesti mation [74]. Later ab initio calculations of the Peierls stress for shufﬂe-set screw dislocation gave the value of about 3.3 � 0.2 GPa, which agrees much better with the experimental data on the low temperature shear stress, which give the value of 3.4 GPa [140]. These results are also consistent with the low temperature yield stress measurements, which approach 1 GPa at 300 K [117, 118]. One should remember, however, that the Peierls– Nabarro mechanism is a simpliﬁcation that ignores the fact that dislocations in silicon are dissociated and the partials can strongly interact with each other and move together. This is not a problem in the case when, for instance, due to the large applied stress the partials behave relatively independent of each other. However, when the stress is small and the coupling between partials signiﬁcantly affects the dislocation mobility, that, in particular, has been suggested as an explana tion of the reported low-stress anomalies in dislocation mobility [97]. An attempt to take into account the effect of cou pling between partials has been undertaken by Möller [141], who assumed that below some threshold stress the kink pairs nucleate simultaneously on both par tials, making this event rarer than in the model by Hirth and Lothe. However, this model was not success ful in explaining the experimental data and has been discarded. As an alternative mechanism for dislocation mobility in silicon, it has been proposed that point defects rather than kinks control the lattice resistance to dislocation motion [142, 143]. In order to explain the low stress dislocation mobility, an idea of “weak obstacles” was introduced [72, 96, 144], but that has also been dis carded due to the low concentration of extrinsic defects in silicon [145]. It should be noted, however, that the results pro vided by different experiments represent a consider able scattering that makes their theoretical explanation by means of a single theoretical model problematic. Indeed, a number of measurements for the dislocation velocity within the same temperature and stress range using different experimental techniques (such as selec tive etching, X-ray topography, and transmission elec tron microscopy) have been reported ([86, 97, 131, 146–149], Alexander, 1987) giving absolute values of the velocities that differ by about a factor of two [150]. 198

11.2.6 Dislocations in Silicon: Interaction with Defects and Impurities Dislocations and point defects (including both intrinsic point defects and impurity atoms) can signiﬁcantly affect each other’s behavior. On the one hand, dislocations pro mote spatial redistribution of point defects in a crystal. On the other hand, point defects can control various kinds of activities of dislocations, for example, immo bilizing them. This, in turn, can alter the electrical and optical properties of the material as well as lead to the mechanical strengthening of the crystal by suppressing the generation of dislocations on the macroscopic level. In order to characterize the interaction of point and extended defects, one has to take into account speciﬁc properties of both the extended defects (such as their local topology, charge state, anisotropic strain, and elec trostatic ﬁelds) and point defects. The probability, p, of the occurrence of a certain dislocation–defect reaction leading to the formation of a new state, characterized by the reaction energy gain Ei, depends on temperature and can be approximately expressed as [151] 1

p� 1�

⎛ E ⎞⎟ 1 ⎜ i ⎟ exp⎜� ⎜⎜ k T ⎟⎟ C0 ⎝ B ⎠

(11.24)

where C0 is the mean atomic fraction of point defects in the crystal. According to this equation, the com bination of sufﬁciently high concentration of defects and a noticeable value of the dislocation–defect inter action energy can lead to the point defect concentra tion enrichment around a dislocation, which is called Cottrell atmosphere. The temperature dependencies of the dislocation–defect reaction probability, as predicted by Equation 11.24, are shown in Figure 11.12 for dif ferent point defect concentrations. As follows from this ﬁgure, in order for the defects present in the crystal at concentration of, e.g., 10�6 to be gettered at the dislo cations at temperatures above 900 K, their interaction energy should exceed 1.5 eV. The determination of the defect–dislocation interac tion energy requires accurate microscopic calculations that take into consideration the features of the disloca tion atomic structure. There exist a number of studies on the interaction of intrinsic point defects and different impurities with partial dislocations in silicon. The calcu lation techniques used range from simple valence force ﬁeld potentials to ab initio density functional meth ods. Some calculated values of the vacancy–dislocation binding energies are summarized in Table 11.16. As seen in this table, these energies markedly scatter, showing no agreement even concerning the relation between binding strengths to 30° and 90° partials. While the

Mechanical Properties of Silicon Microstructures

CHAPTER 11

1.2

Ei = 0.5 eV 1.0

p

0.8

A

B

C

D

E

3

0.6

4 0.4

7

6

5

8

0.2

Fig 11.13 ● Atomic conﬁguration of a (111) glide plane with a 30° partial dislocation lying along (110) direction. The black circles represent the atoms of the dislocation core (after [139]).

0.0

C0 = 10−6 1.0

2.0

p

0.8

1.5

0.6 0.4

1.0

0.2

0.5

0.2 0

200

400

600

800 1000 1200 1400

Temperature (K)

Fig 11.12 ● (a) The temperature dependence of p for the inter action energy of 0.5 eV and different impurity atom concentrations 10�n atom�1, where n � 3–8. (b) The temperature dependence of the probability p of the occurrence of the dislocation–impurity atom reaction leading to the formation of Cottrell atmosphere for the impurity concentration of 1 ppma and several interaction energies.

Table 11.16 Binding energies of vacancies and different glide-set partials

Potential

Reference

30°

90°

SW

[77]

2.62

3.0

Tersoff

[77]

2.67

1.69

Kaxiras-Pandey

[329]

0.58

0.94

LCAO

[154]

1.9

DFT

[152]

0.9

2.0

ab initio cluster method calculation by Lehto and Öberg [152] gave the difference between 90° and 30° partials of about 1.1 eV, the semiempirical potential calculations vary from �0.98 to 0.398 eV, depending on the poten tial used. However, all the theoretical works agree on the positive binding energies between vacancies and dislocations in silicon, implying that vacancies in sili con should be captured by dislocation cores. This effect is indeed conﬁrmed experimentally, as discussed in Section 11.2.4 where the core defects are considered.

It should be remembered, however, that no calculations did consider so far the possible effects of different charge states of the defects and dislocations, which can probably have a signiﬁcant effect on all the discussed values. The information about self-interstitial interac tions with dislocations in silicon is scarcely presented in the literature. The work by Justo et al. [139] identiﬁed, in particular, three possible sites for an interstitial in the core of a 30° glide partial dislocation: I1-bridging atoms in the same reconstructed dimer (interstitial between atoms A and B in Figure 11.13), I2-bridging atoms of different reconstructed dimers (between atoms B and C in Figure 11.13), and I3-sharing an APD site (atomic site E in Figure 11.13). Their ab initio supercell calcula tions show that the energy of the interstitial atom in the dislocation core is about 1 eV below that of the lowest energy interstitial in the silicon bulk [153]. The energy of the interstitial in the shufﬂe-set dislocation has been estimated to be 1.59 eV, that is lower than for the glideset dislocation case [139]. Combining the ab initio cal culations with Monte-Carlo and MD simulations, Justo et al. [139] showed that even though the concentration of vacancies and self-interstitials in the dislocation cores is considerably larger than in the bulk, it is still too small to allow the formation of shufﬂe dislocation segments. Similar to intrinsic point defects, some impurities also strongly interact with dislocations with a positive interac tion energy (see Table 11.17). Sumino [155] has proposed two mechanisms of impurity gettering at high tempera tures. In the ﬁrst one, when impurities are supersaturated, dislocations act as preferential sites for precipitation. The second mechanism involves reactions incorporating an impurity atom in the dislocation core. Such precipitates and/or defect complexes in the dislocation core can serve as pinning centers that immobilize dislocations. Impurity atoms that are gettered by a dislocation are usually not distributed continuously but discretely along the dislocation line, as, for example, in silicon doped by [151]. Assuming that the interaction between the dislo cation and a pinning particle is of a short-range nature, the dislocation release rate Γ from the pinning particles under the action of stress τ in the temperature range, 199

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Modeling in MEMS

Table 11.17 The interaction energies of neutral impurities on the 90 partial. B, N, P, As are substitutional, while O is a bond-centered impurity

Impurity

Reaction

Off-core

O

O–O O2–O2 2O–O2

0.3 [335]

B

P

In core

Solitonic state

2.5 [156] 4.5 [156]

High purity Si

0.4 [157] 0.9 [157] 0.6 [157]

2.5 [157]

P–P

0.4 [157] 0 [158] 1.1 [157] 1.7 [157] 2.3 [158]

2.3 [157]

N

N–N N2–N2 2N–N2

0.6 [157] 1.5 [157] 2.6 [157] 0.6 [157]

3.4 [157]

As

As–As As2–As2 2As–As2

0.7 [157] 0.6 [157] 2.1 [157] 0.7 [157]

2.5 [157]

where the unpinned part of the dislocation is easily mobile, can be written as ⎡ E* � τb2 ⎤ ⎥ Γ � LN*ν * exp ⎢⎢� ⎥ * ⎣⎢ N kBT ⎦⎥

(11.25)

where L is the length of the dislocation, N* is the parti cle line density, E* is the interaction energy, ν* is the fre quency of the dislocation vibration, and b is the Burgers vector of the dislocation. The release stress is expressed as ⎡ LN*ν * ⎤⎥ 2 τ R � N* ⎢⎢ E* � kBT ln b Γ ⎥⎥⎦ ⎢⎣

(11.26)

The process of dislocation release from impurity atoms/ complexes governs the dislocation mobility in the low stress range. Indeed, it has been experimentally observed that in the low-stress range in crystals doped with a certain kind of impurity the dislocation veloci ties are zero and increase rapidly toward those found in undoped crystal with increasing stress. In contrast, in the high-stress range the dislocation mobility is limited by the effects of impurities dispersed within the crystal. 200

Screw Dopant 60° partials dislocations concentration, cm�3 υ0, m/s Q, eV υ0, m/s Q, eV

1.2 [335]

B–B B2–B2 2B–B2

P2–P2 2P–P2

Table 11.18 Magnitudes of Q and υ0 for different dislocation types in undoped and doped silicon under a shear stress of 20 MPa (after [151])

1.0 � 104 2.20

3.5 � 104 2.35

P

6.2 � 1018

3.3 � 101 1.66

7.0 � 101 1.74

P

1.5 � 1019

1.7 � 101 1.58

9.5

1.57

Only certain types of impurity atoms are found to have a strong effect on dislocation mobility. So, in the high strain range the light impurities, such as C, O, and N, which are electrically inactive, do not affect the motion of 60° and screw dislocations. The meas ured dislocation velocities in crystals doped with these impurities have been the same as in high-purity silicon under the same stress [151]. In contrast, donor impuri ties, such as P, As, and Sb, enhance the velocity of both 60° and screw dislocations under high stress [97, 146, 149, 159], decreasing the magnitudes of both activa tion energy Q and prefactor υ0 (Table 11.18). Acceptor impurities, such as B, affect the dislocation velocity very little (Table 11.18). The magnitudes of Q for disloca tions in B-doped silicon are only slightly smaller than in high purity silicon. However, in situ X-ray topography experiments [149, 160] show that such impurity atoms as nitrogen, oxygen, phosphorus, and boron tend to immobilize dis locations at stresses below some critical value of ~3– 5 MPa, depending on impurity type and concentration. For example, in O-doped silicon the dislocation veloc ity decreases more rapidly than in the undoped silicon when the stress is close to a critical stress below which dislocations become immobile, while dislocation mor phology changes from the well-deﬁned �110� straight lines to irregular ones [149]. It should be remembered that all the conclusions about the impurity effects on dislocation mobility should be taken with a certain caution, because it is always dif ﬁcult to ensure that there is only one type of impurity in the sample. Moreover, when constructing models describing the impurity effect on dislocation mobility, one should take into account the charge effect on the dislocation velocity. So Patel et al. [161] have proposed a model in which dislocation velocity is proportional to line charge of the dislocation, in order to explain the enhancement of dislocation velocity due to dop ing with donor impurities observed in silicon, assuming

Mechanical Properties of Silicon Microstructures

that the dislocation causes an acceptor level within the band gap. However, on the basis of the model by Haasen [162], called the dislocation charge model, one could argue that a charged dislocation is unstable against the double kink formation, which turned out to be also incorrect to explain the experimental observations. Later Hirsch [116] proposed a model in which the dislocation velocity is proportional to the kink density along it. According to this model, the density of kinks is higher in a donor-doped silicon than in an intrinsic crys tal, if kinks provide acceptor levels at the lower part of the band gap. The same holds for acceptor-doped sili con, when kinks provide donor levels at the upper part of the band gap. In these cases, the dislocation velocity is enhanced in comparison with the intrinsic case. While the pinning effect of impurity atoms is expected, the effect of intrinsic point defects on dislocation mobil ity in pure silicon remains unclear. It was found that climbing 60° dislocations may become unstable during motion (i.e., some segments move faster than others and the dislocation line becomes ragged) [163]. It was postu lated that this is due to vacancy absorption or emission by a dislocation, which in turn modiﬁes the dislocation core. However, detailed atomistic mechanism is lacking. Double cross-slip of screw dislocations also has been pro posed as a mechanism for dislocation point defect interac tion [142]. The motion of screw dislocations after double cross-slip requires jog dragging, which depends on the rate of emission or absorption of point defects. Interaction with intrinsic point defect and climb also seem to be nec essary to explain the forward–backward asymmetry of dislocation mobility observed in [164].

11.3 Physical Mechanisms of Fracture in Silicon 11.3.1 General Remarks

Solids are typically classiﬁed as brittle or ductile, according to how they respond to external loads. Silicon belongs to the class of intrinsically brittle solids. In practice, though silicon single crystal manifests a tensile yield strength (6.9 � l0l0 dyne/cm2 or l06 psi), which is three times higher than that for stainless-steel wires [165, 166], it can yield by fracturing at room tempera ture, while metals usually yield by deforming inelasti cally. In order to explain speciﬁc features of the fracture processes a number of factors, which span many dif ferent length scales, must be properly accounted for. Firstly, the fracture initiation and propagation are dic tated by the microstructure of materials, which, in turn, is controlled by processes occurring at a broad range of scales from atomic to mesoscale. Secondly, the intensity

CHAPTER 11

of stress concentration at the crack tip is mostly deter mined by the macroscopic parameters. Thus a number of factors, such as crystallographic orientation and geometry, the number and size of surface, edge, and bulk imperfections, and the stresses induced and accu mulated during growth, polishing, and subsequent processing are of great concern for the resulting strength of a mechanical component or device. Though monocrystalline silicon is known to be a brit tle material, at temperatures above 0.5Tm (Tm is the melting temperature) limited plasticity under complex loading, such as indentation [167, 168], scratching [169– 171], turning [172–174], grinding, and polishing [175– 177], is observed. This change of the fracture mode is called “ductile-to-brittle transition” (DBT) and has a very sharp character for silicon [178–181], where it often reﬂects the phase transformation of cubic diamond phase to amorphous or metastable crystalline R8/BC8 phases. The fundamental features lying in the basis of the dif ferences between brittle and ductile modes are of atomic nature. In the brittle mode the crack tip remains atomi cally sharp [182, 183], while the stress concentration at the tip causes bond-breaking and cleavage. In contrast to this, in the case of the ductile fracture the stress at the crack tip is relieved by generation and motion of dislo cations, which cause the crack tip blunting and prevent the bond from breaking. In other words, the dominance of the brittle or ductile fracture mode is deﬁned by the preferable mechanism of the stress concentration relief at the crack tip, which depends, in turn, on the relative ease of (i) dislocation generation, (ii) dislocation motion, and (iii) dislocation accumulation at and near the crack tip. In silicon, which has very sluggish dislocation mobil ity, the transition of fracture from brittle-to-ductile mode is limited by the dislocation motion away from the crack tip rather than by nucleation at it. Given the modern trend for the reduction in size of critical components of advanced electrical and mechani cal devices, a clear understanding of the brittle and ductile fracture mechanisms becomes increasingly important. The classical theory of the brittle fracture, as proposed in the 1920s by Grifﬁth [184], is based on continuum thermodynamics. According to this theory, a static crack can be considered to be a reversible thermo dynamic system. The central concept of the theory is that crack growth is energetically favorable if the poten tial energy release rate (during an incremental crack growth), G, equals (or exceeds) the energy absorbed by the fracture process, GIc, which leads to the so-called Grifﬁth criterion for the crack instability, G � GIc In the case of an ideally brittle material, the energy

absorbed by the fracture process is the same as the

201

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Table 11.19 Surface free energies of silicon single crystal planes [119]

Fig 11.14 ● The schematic representation of the low index planes {001}, {110} and {111} in silicon.

energy required to create the new crack surfaces. Correspondingly, crack extension takes place when the crack is supplied with a driving force larger than the speciﬁc energy 2γ (where γ is a free surface energy). The Grifﬁth criterion of a balance between the crack propagation driving force and the material resistance against fracture provides a necessary condition for unstable fracture onset, but cannot explain why and how fracture proceeds. The details of a fracture mechanism are the subject of an atomistic consideration. Nevertheless, the Grifﬁth criterion leads to an important conclusion that a brittle crack in a crystal could be expected to choose a cleavage plane with low surface energy and to propagate on this plane with equal ease in all directions. Indeed, it is well known that while the amorphous and polycrystalline brittle solids behave isotropically, brittle single crystals manifest mostly anisotropic behav ior. In the latter case, the combined anisotropy of sur face energy, elastic constants, and plastic deformation leads to the crack path dependence on the variations of the elastic energy release rate and the surface energy with orientation [185]. This results in the existence of a family of favored crystallographic planes along which the crystal can potentially cleave. In general, these planes are those that have the highest atomic density and maximal interplane separation. In particular, for the silicon single crystal the fracture anisotropy has been reported with reference to the low index plane, such as {001}, {110}, and {111} shown in Figure 11.14 (see for example Ref. [185]); these low index planes, accord ing to the atomic bonding analysis [186], have the sur face free energies, γ, as speciﬁed in Table 11.19. This, in turn, leads to the dependence of the fracture tough ness, whose measure is the critical stress intensity factor KIc on the crystallographic orientation. The investigation of the effect of crystallographic orientation on fracture toughness and the fracture path of silicon single crystal using Vickers microhardness indentation tests [187] has shown that the fracture toughness variation follows the 202

Crystal plane

γ, J/m2 Crystal plane

γ, J/m2

Crystal plane

γ, J/m2

(100)

1.99

(110)

1.41

(111)

1.15

(210)

1.78

(310)

1.89

(410)

1.94

(211)

1.63

(311)

1.80

(411)

1.94

(221)

2.00

(331)

1.72

(320)

1.80

(322)

1.65

(433)

1.45

(522)

1.46

symmetry of the indentation axis with no distinct cor relation with the elastic constants. On the basis of these observations Ebrahim and Kalwani [187] suggested that the fracture path and toughness are signiﬁcantly affected by the inclination angle of cleavage planes rela tive to the indent plane (Figure 11.15). The following relationship was proposed in [188] for the estimation of the fracture toughness: �

3

2

1

KIc � 0.129(c/a ) 2 (ϕ E[hkl] /H)5 ( Ha 2 /ϕ ) where c is the crack length, a is the indent size, ϕ is a plastic constraint factor (~3), E is the Young’s modu lus along the [hkl] direction, and (hkl) is the “indented” fracture plane. It should be noted that this equation can be applied to median cracks with c/a � 2.0. The obvious anisotropy in fracture toughness has been shown also by many other experiments (see Table 11.20, which summarizes the estimated values of frac ture toughness for different fracture planes). Thus, Chen and Leipold [189] measured the fracture tough ness of single-crystal silicon using the controlled surface fracture method, and reported the values of 0.82, 0.90 and 0.95 Mpa m1/2 for the {111}, {110} and {100} ori entations, respectively (Table 11.20). Later, Li et al. [190] used a uniaxial tensile test with single-edge notched tension specimen (Figure 11.16) and the fol lowing formula to estimate KIc as a function of fracture tensile stress, σf, notch length a, and the geometry of the specimen: KIc � Yσ f a where Y is a factor related to crack conﬁguration as Y � 1.99 � 0.41λ � 18.70λ2 � 38.48λ3 � 53.85 λ 4 λ � a/ W where W is the width of the specimen, as shown in Figure 11.16. In contrast to the experimental techniques

Mechanical Properties of Silicon Microstructures

1.4

(a)

(b)

CHAPTER 11

(c)

(111)

KIC(MPA m1/2)

(001) 1.2

(111)

(001) (110)

(110)

(112)

1.0

(112)

(112)

(010) (110)

0.8

(110)

(011)

(110)

(100)

(211) (112)

(121)

(101)

0.6

0

30

60

90

120 150 180

Orientation angle

0

30

60

90

120 150 180

0

30

Orientation angle

60

90

120 150 180

Orientation angle

Fig 11.15 ● The critical stress intensity factor, KIc, versus orientation for the (a) (110), (b) (001), and (c) (1 11) indent plane measured in

Vickers microhardness indentation tests.

Source: Data from [187].

Table 11.20 The fracture toughness values for the {110}, {100}, and (111) fracture planes (data from [187])

Method

KIc, MPa m½

[193]

Double cantilever beam

0.71

Fitzgerald (2000)

Double cantilever beam

0.96–1.65

Reference

Indent plane

{110} Fracture plane

[194]

{100} {110}

Indentation/four-point bend

1.19 1.05

[195]

{100}

Indentation/four-point bend

0.90

[196]

{110} {100} {111} {100}

Vickers indentation fracture

1.18 1.07 1.14 1.12

{110} {100} {111}

Vickers indentation fracture

0.83 1.01 0.81

Uniaxial tensile test

1.00

Double cantilever beam

0.75

[187]

[190]

Indentation/four-point bend

{100} Fracture plane [193] [195]

{100}

Indentation/four-point bend

0.95

[196]

{100} {110} {110}

Indentation/four-point bend

1.13 0.82 1.15

{110} {100}

Vickers indentation fracture

1.25 0.86

Uniaxial tensile test

2.00

[187]

[190]

Vickers indentation fracture

(Continued )

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Table 11.20 Continued

Method

KIc, MPa m½

[197]

Double cantilever beam

0.62

[193]

Double cantilever beam

0.617

Indentation/four-point bend

0.82

Notched/four-point bend

1.34–2.85

Reference

Indent plane

{111} fracture plane

[195]

{112}

[198] [181]

{110}

Double cantilever beam

0.93

[196]

{110}

Indentation/four-point bend

1.18

[187]

{110} {110}

Vickers indentation fracture Vickers indentation fracture

1.14 1.22

below cR, and the dynamic fracture energy, (υ), can be expressed as

B

σ

W

σ

a L/2

L/2

Fig 11.16 ● Single-edge notched tension specimen model (after [190]).

used in [189, 191, 192], which are performed with a bending mode that applied nonuniform stress, the uniaxial tensile test is the most direct measurement method for mechanical properties of MEMS devices. Nonetheless, this experiment completely conﬁrmed the anisotropy of fracture toughness in microscale singlecrystal silicon observed earlier. Moreover, Li et al. [190] also demonstrated an anisotropy of the fracture path in single-crystal silicon, where cracks propagate predomi nantly on {111} and {110} low index planes. At the same time they have shown that fracture paths never occur on the (001) cleavage plane. For the crack propagation stage, Freund [7] within the continuum mechanical considerations proposed the criterion for a crack moving at a temporal velocity. According to this criterion the crack velocity asymp totically reaches an upper bound that is equal to the Rayleigh wave velocity cR, the velocity of acoustic surface waves. The continuum mechanical approach, however, implies the consideration of only the speciﬁc case of a crack propagating along a straight path [7]. In this case, a straight crack propagating at a velocity υ 204

⎛ ν ⎞ Γ(ν ) � G(l,σ)⎜⎜⎜1 � ⎟⎟⎟ ⎜⎝ cR ⎟⎠ All the known experimental and numerical studies show that the crack velocity in silicon never attains cR and lies within the range of (0.7–0.9)cR [199–201]. This is inde pendent of the strain energy release rate, where a very high driving force leads to a path instability which splits the initially continuous crack front and results in the propagation of multiple cracks [199]. Unfortunately, both Grifﬁth’s and Freund’s crite ria are insufﬁcient to predict the cleavage propagation plane. In reality, cleavage is related not only to a certain plane, but to both the cleavage plane and the cleavage direction. Indeed, the fracture process at the atomistic level can be described as a sequence of single stretchto-rupture and relaxation events with associated energy barriers [183, 202–206]. Since the atomic distribution in many cleavage planes is different for different direc tions, the energy barriers are different, too. This phe nomenon was called “molecular crack arrest” or “lattice barrier” and believed to be the source of directional ani sotropy, previously discussed. Thus, as it was already postulated, the nature of the fracture process is ultimately determined by events on the atomic scale. Consequently, the fracture characteri zation requires atomic-scale characterization tools. Even though the growing ability to fabricate and mechanically test high-quality microscale and nanoscale specimens leads to the convergence of computational tools and experimental measurements of mechanical properties to

Mechanical Properties of Silicon Microstructures

the same length scale, the atomistic computer simula tion at present remains the main atomistic scale tool for the fundamental characteristics of the fracture behav ior. Understanding of these processes at the atomistic level connected with the knowledge of the macroscopic behavior of real materials could provide a new level of control in the design of modern applications.

11.3.2 Simulation Approaches Applied to the Fracture From the atomistic modeling point of view there exist several fundamental open questions, such as (i) how pre dictive atomistic simulations of the fracture are and (ii) would it be possible to develop a practical tool for engi neers based on atomistic considerations? One thing that can be safely said is that atomistic modeling will play an increasingly important role in the next decades, espe cially as a part of the multiscale methods, where con tinuum methods will incorporate atomistic information. Many atomistic-based studies have been conducted for cracked or notched specimens to investigate fracture behavior (see, for example, Refs. [200, 207–222]). The ﬁrst atomistic studies of fracture were performed in the early 1970s by Thomson and coworkers [204]. In their simulations they used the so-called “lattice theory”, which exploits the one- or two-dimensional lattice model, where atoms at the lattice sites are connected to nearest neighbors with Hooke’s springs. On the basis of these calculations, Thomson et al. [204] introduced the “lattice-trapping” effect, which means the inability of a crack to advance/heal until loads somewhat larger/ smaller than the Grifﬁth load are reached. Later in the 1980s Leonid Slepyan [223] proposed a completely analytically solvable strip lattice model, in which atoms remain associated with particular points on a lattice, for the study of the dynamic cracks. This model answered four conditions: (1) for moderate strains, dynamic cracks are attracted to steady states; (2) at steady state, there is an intimate connection between the speed of the crack and the wave properties of the medium; (3) there is a minimum velocity below which a crack will not propagate; (4) the crack becomes unstable when the fracture energy reaches some threshold. The lat ter property concerning crack instability reﬂects the inability of cracks to reach the Rayleigh wave that is well-established experimentally for silicon [199–201]. For example, Marder and Gross [201] used the Slepyan technique to calculate a velocity gap and transverse instability during dynamic crack propagation. Unfortunately, in reality fracture phenomena are difﬁ cult to handle in an analytically tractable way. First of all, because there exists no two-dimensional material with snapping Hooke springs between nearest neighbor atoms,

CHAPTER 11

taking into consideration three-dimensionality and a real interatomic interaction is a must. This, together with the fact that a large number of atoms are driven far from equilibrium when a crack propagates, bifurcating and changing direction, makes the real dynamic fracture ana lytically intractable. Thus it requires more realistic largescale atomistic simulations with an adequate description of interatomic interactions. Atomistic studies are often associated with MD that is potentially an important part of multiscale methods describing very complex fracture processes. Indeed, MD analysis has been very actively exploited for the inves tigation, in particular, of dislocation nucleation [156, 218, 219, 224–226] and crack propagation [218, 219, 224, 227]. For single-crystal silicon, MD simulation was carried out for evaluation of deformation and fracture behavior [36, 205, 228–233]. The critical point of these studies is the accuracy in treatment of the atomic inter actions as required for a proper description of fracture. Atomistic modeling of cracks is a rather complicated problem because it requires a correct description of both the long-range elastic interactions and the short-range chemical interactions. This means that one has to use a large atomistic model or embed the atomistic region into a ﬂexible surrounding. Thus one should ﬁnd a rea sonable compromise between the accuracy of the atomic interaction treatment and time expenses in force calcu lations. For a long time fracture has been studied using empirical interaction models (see for example, Refs. [209–211, 222, 228]). However, the obtained results have been found to be interatomic potential-dependent and do not always agree with experiments even quali tatively. So, the ﬁrst attempts to model fracture in silicon were done using the classical Tersoff and Stillinger–Weber [14]) potentials. Later on, EDIP potential [234] was developed and used. However, all these potentials failed due to an incorrect description of the bond-breaking process [223]. For example, even though SW potential properly describes elastic prop erties of silicon and captures well the nonlinear phys ics involved in heating and melting, it does not give a fracture along the experimentally preferred fracture planes (111) and (110) [223]. Furthermore, Holland and Marder [223] and later Kang and Cai [32] showed that at low or moderate strains cracks propagated in a ductile manner due to the large lattice trapping (Table 11.21), when two dislocations open up at the crack tip, blunting it and preventing its propagation. At the same time it has been proven experimentally that silicon manifests brittle behavior and atomically sharp crack tip for fracture along (111) [183, 235]. At very high strains, the crack tip region melts [223]. Furthermore, SW potential simulations evidence for fracture along (100), that is contradictory to the experi mental observations [190] indicating additional potential 205

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Table 11.21 Fracture strength and Young’s moduli of silicon calculated using different interatomic potentials. Young’s moduli presented are for nanowires (NW) at T � 300 K and bulk silicon at zero temperature (in GPa)

Potential

Fracture strength

NW Young’s Bulk Young’s modulus modulus

Fracture behavior

Reference

SW

14.6

123

138

ductile

[32]

Tersoff

26.3

128

138

ductile

[32]

Lenosky

10.2

102

151

ductile

[32]

SWmod

22.7

165

161

brittle

[32]

Baskes

13.2

139

164

brittle

[32]

SW

-

--

114

ductile

[223]

SWmod

-

--

172

brittle

[223]

SW

-

--

151

ductile

[223]

SWmod

-

--

201

brittle

[223]

�110� direction

�100� direction

�111� direction

shortcomings. In order to make cracks in silicon behave in a brittle manner along (111) and (110), the SW potential was modiﬁed (SWmod in Table 11.21) in a way that increased the restoring forces between pairs of bonds. However, this modiﬁcation leads to the rise of the melting temperature up to 3500 K (the experi mental Tm � 1685 K) and the Young’s modulus also gets shifted (see Table 11.21). Despite the fact that EDIP potential [15] is believed to be much more sophisticated for silicon, it reproduces dynamic fracture even more poorly than SW does the crack tip behavior. Baskes and coworkers developed an MEAM poten tial [36, 229], which was used for simulation of a crack motion in silicon [222]. This MEAM potential was also used later by Bailey et al. [228] to investigate a critical value of the stress intensity factor for the crack initiation of various crystal orientations and notch shapes. MEAM potential reproduces well the brittle character of the frac ture in silicon (Table 11.21). However, it does not succeed in describing silicon atom interaction with impurities, such as oxygen, for example. Thus, the most sophisticated description of the interatomic interactions for the simula tion of the dynamics of materials fracture is expected to be given by accurate quantum mechanical formulations. This point has been demonstrated by Gumbsch and cow orkers [202, 205, 232, 236], which analyzed the cleavage 206

fracture processes by ab initio calculations. They showed, in particular, that the bond breaking processes at crack tip are dependent on the fracture planes, a phenomenon that is well documented experimentally, though it cannot be well reproduced by semiempirical calculations. Though classical mechanics may be inadequate for describing the most fundamental aspects of fracture [237], the quantum mechanical approaches also have their own shortcomings. First of all, these methods are very time consuming and require the use of powerful computer facilities, especially, taking into account that for an adequate crack simulation the use of large com putational cells is a must. Secondly, the choice of the pseudopotential approximation should be done carefully. For example, Pérez and Gumbsch [202, 205, 232, 236] used the approximation, which precludes relaxation of core electron states. However, in the case when atomic separations undergo the large changes characteristic for fracture, the validity of this approximation needs to be accurately veriﬁed. A few more ab initio calcu lations have addressed the investigation of the fracture features. Thus, Be’ery et al. [238] demonstrated that cracks propagate at very low velocities under control led conditions in silicon. Later the same group studying the crack deﬂection from the (110) to the (111) cleav age plane in single-crystal silicon as a function of crack tip velocity explained this as evidence of phenomena

Mechanical Properties of Silicon Microstructures

associated with atomistic irreversible energy dissipation mechanisms [239]. Shilo et al. [240], using a combi nation of experimental and theoretical ab initio tools, suggested an importance of a crack interaction with microstructural defects (dislocations) and ramiﬁcations for the stability of the crack front. A number of attempts to incorporate the atomistic data into the continuum methods have been under taken. The most widespread method is to divide the simulation cell into few regions that are treated on dif ferent scales depending on the distance from the crack tip. Some of these multiscale methods, such as a vir tual internal bond (VIB) [241–244] and FEAt [245], treat the crack tip region with MD, whereas the elastic medium around the crack is described by randomized cohesive interactions between material particles and ﬁnite elements. Other methods are the quasi-continuum method [246] and the MAAD method [210, 211]. The latter method couples quantum mechanical description of the crack tip region with empirical potentials used for the outer region.

11.3.3 Lattice Trapping and Cleavage Anisotropy in Silicon As already discussed in Section 11.2.1, silicon has two principal cleavage planes: {111} planes, usually the easy cleavage planes, and {110} planes [179, 190, 247]. Measurements have shown that {110} planes have a slightly lower surface energy, that is, ~2.3 J/m2, than {111} planes, ~2.7 J/m2. The theoretical calculations signiﬁcantly underestimate these values. For example, the fracture toughness calculated using atomic bonding analysis [186] gave the values of 1.41 J/m2 and 1.15 J/m2 for {110} and {111}, respectively. Even the most accu rate density functional theory-based quantum mechani cal methods give values that are closer to those obtained from the atomic bonding analysis than to the experi mental data (~1.73 J/m2 for {110} and ~1.44 J/m2 for {111}) [202, 205]. For both cleavage planes the propagation direction anisotropy is observed. This anisotropy manifests itself in a preferential crack propagation direction, that is, the �110� direction for both {110} and {111} planes [179, 247]. The cleavage on the {110} plane demon strates a much more pronounced propagation anisotropy than on the {111} plane, where it is minimal. According to the Grifﬁth theory [248], a perfectly brittle crack in a crystal is expected to choose a cleavage plane with low surface energy and to propagate on this plane with equal ease in all directions. However, from the atomistic point of view the situation is somewhat dif ferent. Thomson et al. [204] and Sinclair et al. [203]) in the 1970s introduced the so-called lattice trapping

CHAPTER 11

effect, which causes the crack to remain stable and not to propagate until the load is less than the Grifﬁth load. Later the semiempirical MD calculations ([245], Riedle, 1996) showed that lattice trapping may also depend on the direction in which the crack tip bonds are broken and may therefore be different for crack propagation along different crystallographic directions on one cleavage plane. This has been conﬁrmed and extended recently by ab initio calculations, where the anisotropy in frac ture behavior with respect to the propagation direction on {110} plane was also explained as a consequence of a difference in lattice trapping for the different propa gation directions [202, 205]. Pérez and Gumbsch [202, 205] have shown, in particular, that crack propagation in the �110� direction, which is preferable according to the experimental observations [179, 247], takes place via continuous opening of the bonds at the crack tip and leads to a relatively small lattice trapping. In contrast, a crack driven in the �001� direction on the {110} plane mani fests a discontinuous bond breaking, leading to a larger lattice trapping range [202, 205]. Moreover, attempts to achieve propagation in the �001� direction, perpendicu lar to the preferred direction, have always resulted in the deﬂection of the crack plane onto the {111} or {112} planes [202], in full agreement with the experimental observations made by Cramer et al. [199]. The transition from the {110} to the {111} cleavage plane as a func tion of the load-to-fracture has lately also been observed by Muhlstein et al. [249, 250] in fatigue cracks in singlecrystal silicon MEMS specimens. The destabilization of the {110} crack propagation in the �001� direction against deﬂection onto an inclined {111} cleavage plane was interpreted as being a result of the high molecular crack arrest as predicted for the {110}– �001� system by ab initio calculations [199, 202].

11.3.4 Dynamic Crack Propagation At some scale, any fracture is dynamic. For a crack that is already propagating (after initiation), we may say that dynamic effects are important when the crack tip speed is small compared with the stress wave velocities [237]. But even when the crack at the macroscopic scale advances quasi-statically, at the atomic scale the inertia of individual atoms must be accounted for in depicting their separation from one another. Bond rupture is a dynamic process. Measurements and modeling of fracture surface rough ness under dynamic and static loading has led to new insights into the conditions for crack propagation. First, Ramanathan et al. [251, 252] suggested that the rough ness is deﬁned only by dynamic conditions near the crack tip, which, in turn, are affected by the dynamic stress transfer. Then, based on this suggestion, the crack front 207

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Modeling in MEMS

waves were assumed to be responsible for the small-scale, self-afﬁne fracture surface roughness found experimen tally in both dynamic and (macroscopically) static loading [253]. However, this crack front wave theory was found to be inadequate in predictions of the observed exponent of scale dependence. Therefore an alternative model has been suggested, where the roughness originates in multi ple voiding and void coalescence ahead of the main crack, that provides the correct exponent [253]. There have been few attempts to experimentally verify crack front waves [254, 255]. Sharon et al. [255] claim that they observed solitary waves, which may, in fact, be crack front waves. However, Bonamy and RaviChandar [254] argue that the observed solitary waves may be due to an interaction between shear waves and the propagating crack front. Next, the effect of microcracking as an impor tant dissipation mechanism has been widely discussed [256–258]. Microcracks can act as nuclei for macro scopic crack branching leading to the crack roughening and increasing the fracture toughness with crack veloc ity [259–265]. This has also been shown to predict an upper bound for the crack velocity that lies far below the Rayleigh wave speed [260, 261, 263, 264]. At the same time, if microcracks form a cloud, the effective wave speed and therefore the crack speed through the damaged material are reduced [266] and the macro scopic fracture toughness increases. One of the fundamental problems for fracture mechanics is the correct way of stating the criterion for static crack propagation. One of the criteria, widely used in many engineering applications, is based on energy release rate or critical stress intensity factors as discussed in the previous sections. However, sometimes for the case of quasi-static loading, this criterion leads to the prediction of the wrong crack path and fundamentally unrealistic crack-tip conditions. The ultimate answer to the quasi-static fracture criterion may not be approach able by calculations of static behavior alone but may lie in essentially dynamic phenomena [237]. In particular, Ravi-Chandar and Knauss [267], using deeply notched thin sheets of Homalite loaded in mode I by the electro magnetic method showed strong correlation between the onset of crack propagation and the crack-tip stress inten sity factor. Thus for engineering applications, the idea of a dynamic initiation toughness arises in analogy to the frac ture toughness used in quasi-static fracture, where the critical toughness might be a material constant that could be measured in a simple standard experiment [237]. The propagation of dynamically moving cracks has been addressed by a number of the atomistic calcula tions. Most of them were directed towards understand ing of the steady-state propagation, crack speed, and the onset of dynamic instabilities. Both analytical [201] and MD [268] approaches have been applied to this problem. 208

In particular, the analytical calculations that considered one- and two-dimensional structures showed that a dynamically propagating crack can only access a limited velocity of about 20% of the Rayleigh wave velocity. When the crack tip speed reaches half of the Rayleigh wave velocity, the crack manifests a branching instabil ity [201]. MD simulations [268] essentially conﬁrm the analytic results, giving the same estimate for the lower band of forbidden velocities for the straight crack and also revealing an upper critical velocity. Gumbsch et al. [268] also showed that the upper critical velocity for the mode I crack strongly depends on the nonlinearity of the atomic interaction. Thus one should be accurate choosing the form of the atomic interaction description (see also Section 11.2.2). Furthermore, according to MD simulations, the type of crack instability above the critical velocity depends on the crystallographic orientation of the crack and on the crystal structure ([200, 268], Mikkula, 1998). The generation of cleavage steps and dislocation emission are usually observed at lower overloads, while crack bifurcation was only observed at the highest overloads. Dislocation emission usually leads to a pronounced change in crack propagation direction.

11.3.5 Brittle-to-Ductile Transition As discussed in Section 11.3.1, the particular fracture mode, brittle or ductile, is deﬁned by the competition between two processes. These are the extension of the crack by creation of two new surfaces (brittle response) or stress relaxation by the generation of dislocations that blunt the crack tip (ductile response). Silicon under goes a transition between brittle and ductile response at T ~ 873 K. This transition is very sharp function of tem perature and takes place within the temperature range of only 2 K! According to the Grifﬁth criterion (see Section 11.2.1), the energy required for an incremental advance of the brittle crack front is 2γ. The ductile fracture is a more complex process and its description requires a proper account of dislocation nucleation and motion in the neighborhood of the crack tip. The ﬁrst attempt to rationalize the distinction between brittle and ductile behavior was made by Kelly et al. [269]. They postu lated that a material would be ductile if the crack tip stress exceeded the theoretical shear stress before the theoretical tensile stress was reached. Later Rice and Thomson [270] deﬁned a ductile behavior as spontane ous emission of dislocations at the crack tip. According to their criterion, dislocations are considered to be nucleated when they move a distance exceeding some critical distance ac from the crack tip. Then, if ac is smaller than the dislocation core radius, the material

Mechanical Properties of Silicon Microstructures

is considered to be ductile at all temperatures; oth erwise the material is brittle at low temperatures. Unfortunately this criterion predicts a DBT temperature that is much higher than that observed experimentally. A more recent DBT criterion [271, 272], which is the further development of the Rice and Thomson model [270], exploits the unstable stacking fault energy γus, a measure of the nucleation energy for a dislocation of Burgers vector b on the (hkl) plane. According to this criterion, sometimes called the Rice model, dislocation nucleation at the crack tip and therefore ductility is reached when G � αγ us where α is a constant of the order unity, which depends on the geometry of the crack. As an alternative model of the DBT, Hirsch and Roberts [180] postulate that ductility is deﬁned by the motion, rather than the nucleation of dislocations. This model connects the DBT with dislocation mobility and scales with the unstable stacking fault energy γus. Thus, according to the ductility criteria considered, the conditions for both brittle fracture and the nuclea tion and motion of dislocations can be expressed in terms of features of the γ-surface. On the basis of this concept and adopting the view that dislocation nuclea tion is a necessary precursor to dislocation motion, Kaxiras and coworkers [273] proposed a ductility con dition that depends only on two energies, γ and γus, and deﬁned a “disembrittlement parameter” determining to which class a solid belongs: D�

γ γ us

The difﬁculty with using this criterion is that values for γ and γus have to be established from accurate micro scopic calculations. Even then, it is not clear for which slip system or for which cleavage plane these quantities must be evaluated [273]. Kaxiras and Duesbery [274] calculated the general ized stacking fault (GSF) energy surface for both shufﬂe and glide planes in silicon (for the deﬁnition of the shuf ﬂe and glide planes in the diamond structure see Section 11.2.1 using ﬁrst-principles calculations in the DFT/LDA framework. They found that GSF energy, γus, has a value of about 1.81 J/m2 and 2.02 J/m2 for shufﬂe and glide planes, respectively. They also showed that atomic relaxation affects the glide plane energetics more than the shufﬂe plane, indicating that at zero tempera ture the sessile mode will be favored. However, it was found that because of the high entropy the glide plane “under the proper thermodynamic conditions” can have a lower energy than the shufﬂe plane. This led Kaxiras and Duesbery [274] to the conclusion that as the

CHAPTER 11

temperature is increased beyond a critical point, a tran sition from sessile shufﬂe mode to glissile glide mode can occur that can be related to the DBT in silicon. While Rice’s criterion for ductile versus brittle behavior addresses the issue of dislocation nucleation and motion, it does not include any information about the surfaces created due to dislocation emission at the crack tip. Juan, Sun, and Kaxiras [275] found that the energy associated with ledge surface creation is approximately 60% of the energy of the free surface. Assuming an evanescent force law, they incorporated the ledge effects into Rice’s origi nal theory within continuum mechanics and showed that the increase in the necessary loading for dislocation emis sion due to surface traction can be up to 20%. Despite this result, increasing experimental evidence ([162, 276]) seems to indicate that BDT in BCC (body centered cubic) metals is controlled by the mobility of dislocations away from the crack tip. One distinguishing difference between BCC metals and covalent solids such as silicon in terms of the BDT is that the activation energy of the BDT in BCC metals is in general much lower (by an order of magnitude) than the activation energy of bulk slip [277–279], while for covalent solids, the BDT activa tion energy is comparable to activation energy of bulk slip [180, 280]. The much lower BDT activation energy in BCC metals could be interpreted in terms of the strong stress-dependence of the activation energy of slip in the vicinity of the highly stressed crack tip. However, recent discrete dislocation dynamics simulation [281] has shown that the effective activation energy of crack tip plasticity— even with stress-dependent activation energy—is only marginally reduced from the activation energy of bulk slip. This must be interpreted to clearly rule out the mobility of screw dislocations as the only decisive factor and the rate-limiting step for crack tip plasticity and the BDT. It rather suggests that other factors such as the blunting edge dislocations [279, 281], or the crack tip enhance ment of the dislocation emission process itself [282, 283], may play an important role. However, there remain many unknown facts amongst which the role of the initial dis location density of the material and the nature of the dis location sources near the crack tip are the most-needed ones. More experiments, dislocation dynamics simula tions, and in particular more speciﬁc atomistic simulations are required to clarify these questions. Later Kang and Wei [32] similar to the previous models also proposed that fracture behavior is the result of competition between two different failure modes, cleavage on the (110) plane and slip on the (111) plane. On the basis of this proposal they introduced another criterion for the brittle-to-ductile transition deﬁning a “ductility parameter”: A

Sσ c τc 209

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Modeling in MEMS

where σc is the ideal tensile strength, which is the meas ure of resistance against the cleavage on the (110) plane; τc is shear strength, which measures the resistance against slip on the (111) plane; S is the Schmidt factor, the resolved shear stress on the slip system (slip plane and slip direction) per unit tensile strain, and is deﬁned as S � cosϕ cosλ where ϕ is the angle between the tensile axis and slip plane normal and λ is the angle between the tensile axis and slip direction. According to this criterion [32], if “ductility parameter” A � 1, then ductile fracture can be predicted, otherwise when A � 1 the fracture is brittle. The “ductility parameter” has been calculated using different computational approaches [32] (Table 11.22). Unfortunately, it has been found that the resulting value is dependent on the approximation used. So, the MD calculations with SW, Tersoff, and Lenosky empiri cal potentials predict A � 1 and, thus, ductile behavior, whereas MEAM, SWmod and DFT calculations predict A � 1 and brittle behavior.

11.4 Physical Mechanisms of Fatigue of Silicon

Table 11.22 Ideal tensile strength (in GPa), ideal shear strength (in GPa), and ductility parameter , A, for Si nanowire calculated using different computational approaches (data from [156]). Ductile fracture condition is A � 1, brittle fracture is expected when A � 1 S σc Potential Ideal tensile Ideal shear A� strength, σc strength, τc τc

Fracture behavior

Ideal tensile strength along the [110] direction, ideal shear strength on the (111) plane and along [11 � 1]. Schmidt factor S � 0.4082 along the [110] direction. SW

113

19.1

2.42

ductile

Tersoff

41.6

9.51

1.79

ductile

Lenosky

33.5

11.3

1.21

ductile

Baskes

32.0

13.9

0.940

brittle

SWmod

41.0

19.5

0.858

brittle

VASP/LDA

25.2

14.0

0.735

N/A

VASP/GGA

23.0

13.7

0.685

N/A

Ideal tensile strength along the [111] direction, ideal shear strength on the (11 � 1) plane and along [101] Schmidt factor S � 0.2722 along the [111] direction.

11.4.1 General Remarks

SW

38.5

9.51

1.10

ductile

Over the past decade, a vast array of MEMS applica tions, such as pressure transducers, inertial sensors, ink jet cartridge nozzles, and more have emerged and many commercial products ranging from medical to comput ing devices have entered the marketplace. The conven ience and success of silicon material and micromachining technology have made silicon a natural choice for many MEMS applications, such as actuator, power generator, etc. The reliability of these applications is extremely important to ensure their effective performance (“highperformance” applications) and safeguarding human life (“safety-critical” applications). In particular, the mate rials used for the safety-critical applications are often subjected to aggressive mechanical and chemical environ ments, such as, for example, a large number of the cyclic stresses within relatively short periods of time. In a case when cyclic stresses are applied, most materials undergo mechanical property degradation resulting in failure. Fatigue, or the delayed failure of a material under cyclic loading conditions, is very important and is the most commonly experienced form of structural failure, but nevertheless is one of the least understood. As in the fracture process there are two generally accepted types of mechanisms of fatigue: ductile and brittle. The ductile mechanism is usually attributed to the metallic materials and is accompanied by the cyclic accumulation of plastic

Tersoff

102

19.1

1.45

ductile

Lenosky

30.4

11.3

0.73

brittle

Baskes

29.8

13.9

0.58

brittle

SWmod

38.5

19.5

0.53

brittle

VASP/LDA

22.0

14.0

0.43

brittle

VASP/GGA

20.0

13.7

0.40

brittle

210

deformation through the generation and motion of dis locations. The failure, in this case, is the result of the crack nucleation and its crack propagation, either preex isting or created by alternately blunting and sharpening the crack tip. In contrast with ductile materials, brittle materials, to which the single-crystal silicon belongs, manifest very low dislocation mobility at ambient tem peratures as a result of high Peierls forces. This means that if the fatigue takes place in these materials, it fol lows the fundamentally different mechanism for which dislocations are not involved. Indeed, as has been found for some polycrystalline ceramics and ordered interme tallic compounds [284, 285], the fatigue is governed by kinematically irreversible deformations via so-called

Mechanical Properties of Silicon Microstructures

crack-tip shielding mechanisms leading to the cycle dependent degradation of the toughness of the material in the wake of the crack tip. Single-crystal silicon or any other solid with the covalently bonded diamond struc ture, however, do not exhibit any degree of shielding to degrade. Hence, the crack-tip shielding mechanisms would not be expected in these materials. Moreover, there is also little evidence of other extrinsic toughening mechanisms, such as, for example, grain bridging [286]). Moreover, as it is well established experimentally ([195, 286–289] and theoretically [290], bulk single-crystal silicon is immune from both cyclic fatigue and environ mentally assisted (e.g., stress–corrosion) cracking [195, 288, 291–294]. Such immunity to long-lifetime degra dation would clearly be of beneﬁt in applications where periodic mechanical, electrical, or thermal stresses oper ate (e.g., sensor technology, electronic packaging, solar panels, and optical systems) [287]. For all of these reasons, fatigue of silicon was unex pected when Connally and Brown in 1992 [295] dem onstrated that a silicon specimen of micrometer-size dimensions failed prematurely under cyclic fatigue loading in room-temperature air. This ﬁnding has been conﬁrmed in many other studies during the last decade [95, 249, 250, 286, 296]. In these works it has been found that both mono and polycrystalline silicon ﬁlms display failure stresses of approximately half their (single-cycle) fracture strength after fatigue lives in excess of ~1011 cycles. This fact is rather unfortunate because silicon thin ﬁlm is one of the most common materials used in microelectromechanical systems to date. In order to control fatigue damage in silicon-based MEMS devices the understanding of the fatigue mecha nism is of an extreme importance. Within the last decade, there have been several models for silicon fatigue origin proposed (e.g. by native oxide cracking, room-temperature plasticity) [297]. However, there has been no direct exper imental evidence to support any mechanism of silicon fatigue so far. The experimental studies have only estab lished the importance of subcritical crack growth showing that consideration of fatigue-crack initiation and growth must be a crucial part of critical component design.

11.4.2 Single-Crystal Silicon If thin ﬁlm silicon is fatigued at high enough stress amplitudes, cracks will initiate and grow, and the mate rial will eventually fail. Connally and Brown were the ﬁrst investigators who showed that thin free-standing ﬁlm of a single-crystal silicon could undergo cyclic fatigue failure [295]. In that pioneering work they used a notched, electrostatically actuated resonator system with a resonance frequency of 12 kHz and a stress ratio (the ratio of applied stresses) of �1, and demonstrated that

CHAPTER 11

fatigue was caused by slow crack growth that occurred by environmentally assisted cracking in the silica layer that forms on silicon upon exposure to oxygen. They proposed, in particular, that fatigue-crack growth rates are rate-limited by the reaction rates at the crack tip or by transport of reaction species to, or from, the cracktip region [298]. On the basis of this work Connally and Brown concluded that the actual mechanism govern ing crack growth in micron-scale silicon devices is more complex than simple environmentally assisted fatigue of silica, even though water, indeed, accelerates or initiates crack propagation. Following Connally and Brown, Tsuchiya and cow orkers conﬁrmed the inﬂuence of environment on the fatigue behavior in single-crystal silicon ﬁlms [334]. According to their observations the longer the fatigue life, the more the fatigue damage accumulation, even though no direct evidence of this damage were made. They also found that cycling in humid air (78% relative humidity) led to failures in fewer cycles than cycling in dry air (11% relative humidity), which shows that the specimen’s fracture strength and fatigue life are highly affected by the testing environment. These authors attributed their ﬁndings to a mechanism involving oxi dation at a crack initiation site on the silicon surface that allowed further crack growth. These results have been conﬁrmed further by the number of more recent works (e.g., Refs. [299, 300]) providing additional evi dences that silicon ﬁlms manifest much more signiﬁcant degradation over time in air than in vacuum. In order to gain information about the crack initia tion and failure mechanisms, scanning electron micros copy (SEM) and atomic force microscopy (AFM) have been used for the fracture surface examination. It has been shown that there is no evident fracture initiation region in specimens with short lives and that specimens contain ridges, ledges, steps, and other features com monly observed on brittle material fracture surfaces. Furthermore, it has been found that the failure in a short-life specimen progresses by cracking on multiple {111} planes with ﬁnal failure taking place by cleavage on a (111) plane after coalescence of multiple crack fronts, where the dominant mode of the fracture is cleavage [249, 301, 302]. This is the result of the cleav age crystallography of the silicon crystal as discussed in Section 11.2. Cleavage steps, formed on the {111} fracture surfaces as a means of dissipating energy, were addressed by Muhlstein et al. [249] with regard to per turbations in the applied loads, obstacles in the crack path, bifurcation of fast-running cracks, and the coales cence of microcracks. In contrast with the short-life surfaces, for long-life fracture surfaces the initiation region can be clearly identiﬁed and found to be near the surface of the notch. In this case the fracture surface is smooth and 211

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does not contain any steps like the short-life surfaces. The fracture proceeds predominantly along {110}, which is unusual for silicon and suggests that the active cracking mechanism under cyclic fatigue loading is dif ferent from that seen during quasi-static overload fail ure [249]. Sundurarajan and Bhushan [191], however, obtained scanning electron micrographs, which indicate a high-energy fracture on a {100} plane in combination with low-energy cleavage on {111} planes. The frac ture surfaces were found to be smooth, without facets or irregularities. These authors proposed that fracture occurred by low-energy cleavage on the {111} planes, with a fatigue mechanism similar to environmentally assisted cracking. The growth of a subcritical crack is affected also by the way of loading. In a case of monotonic loading a dis crete step-like crack growth process is observed [289, 303]. The increase of the load leads to the unstable fracture mode when the stress intensity, KI, approaches the toughness of the material. Sometimes, however, due to the geometry of the specimen KI can decrease with crack extension leading to the crack arrest [289, 303]. The experimental observations for a constant-load mode show that subcritical cracking only occurs for 0.9 KIc � KI � 0.98 KIc , where KIc is the toughness of the material. This means that subcritical crack growth occurs in the region III in v-KI curves (v is the crack growth rate) where the crack velocity outpaces transport of the environmental species. A crack growth rate is v� CKn, where C and n are constants, and n is higher than 100. Based on that understanding it has been concluded that environmentally assisted subcritical cracking is absent in monotonically loaded micron-scale silicon [289, 303]. For cyclically loaded specimens the crack-growth behavior is observed to be step-like in nature, with unstable crack extension when the maximum applied stress intensity reached the fracture toughness [289, 303]. Under decreasing K conditions, cracks were observed to arrest. The resulting growth rate versus Kmax curves were similar to the curves obtained under monotonic loading, which suggested that the relevant crack-growth process in single-crystal silicon was not true cyclic fatigue. This conclusion was further sup ported by the fact that fracture surfaces under cyclic and monotonic loading were similar. The authors also conclude that fatigue mechanisms involving cracking of a surface reaction-layer would be a viable mechanism.

11.4.3 Polysilicon Similar to the data for single-crystal silicon ﬁlms, all the available experimental observations for the polysilicon specimens say that material failure is affected by factors such as loading conditions, operating frequency, and, 212

most importantly, environment. So, in early work on fatigue in polycrystalline silicon ﬁlms, Van Arsdell and Brown [95] reported the change in resonant frequency of a precracked polysilicon device under fatigue loading in wet air. Speciﬁcally, they observed that the resonant fre quency of the device decreased when it was fatigued in humid air (50% or 75% relative humidity), but remained unchanged when it was fatigued in dry air. These results were interpreted as subcritical crack growth via an envi ronmentally assisted cracking mechanism. On the basis of the fracture surface examination, which showed a transgranular crack path, Van Arsdell and Brown [95] suggested that this environmentally assisted cracking involves the native oxide ﬁlm rather than the polysilicon itself. They claimed that this mech anism would facilitate further growth of the oxide ﬁlm at the crack tip. This mechanism was called “static fatigue” and includes only effects of the environment and stress level, but claims the fatigue behavior is inde pendent of the number of load cycles. Muhlstein et al. [250, 296, 302, 304–308], using the same devices as those used by Van Arsdell and Brown [95] and also transmission electron microscopy (TEM), measured the thickness of the surface silica layers on the specimens. They found that after fatigue cycling to failure the surface oxide thicknesses were up to three times greater in the highly stressed regions than in the nonstressed regions without heating occurring dur ing the test, as was also suggested by Van Arsdell and Brown [95]. The same authors reported TEM studies of one specimen that was cyclically stressed but not to fail ure, which showed several stable small cracks within the thickened surface oxide layer, indicating the presence of subcritical crack growth. Furthermore, it has been shown that the specimens, which were treated with a self-assembled monolayer (SAM) coating during fabrica tion that prevented surface oxide formation, revealed a smaller dependence of lifetime on the peak stress ampli tude. Similar to this, Alsem et al. found that the absence of oxygen and water vapor in a 2 � 10 � 5 Pa vacuum environment completely suppressed the occurrence of delayed fatigue [298]. They also showed that samples tested in high relative humidity (�95% RH) air failed after fewer numbers of cycles than corresponding sam ples tested in ambient air (~35% RH). In light of these results, the fatigue of silicon thin ﬁlms was attributed to a mechanism of sequential, cyclic stress-assisted oxida tion and environmentally assisted cracking of the surface oxide layer which forms upon exposure to moistureand/or oxygen-containing atmospheres, a mechanism that they termed reaction-layer fatigue [298]. In order to support a reaction-layer model Muhlstein et al. [304, 306] performed a ﬁnite-element modeling, on the basis of which they claimed the decrease in natu ral frequency of the fatigue characterization structure

Mechanical Properties of Silicon Microstructures

during testing is consistent with the modeled damage evolution in the form of oxide thickening (�0.5 Hz per nm of oxide growth) and subcritical crack growth (�1 Hz per nm of crack extension) within the oxide. In particu lar, the calculated critical crack size was found to be similar to the experimentally observed maximum crack extension. The fact that this size is less than the surface oxide layer implies that the entire process of fatigue crack initiation, growth, and the onset of ﬁnal failure of the entire structure occurred within the oxide layer [309]. Following these observations and the fact that a crack in the oxide layer must cause failure of the entire structure, the criterion for this mechanism was proposed, which says that the thickness of the oxide layer, h, must be greater than or equal to the critical crack size, ac, to fail the entire structure (i.e., when ac � h). Later, Pierron and Muhlstein [310] expanded this numerical model to account for an alternative failure scenario where stable crack growth in the oxide changes to unstable crack growth when the crack hits the sili con/oxide interface (i.e., when ac � h; this lowered the oxide thickness that is potentially susceptible to reactionlayer fatigue to ~15 nm, compared to ~50 nm required in the previous model). The mechanism also explained the decreasing growth rates observed for cracks propa gating within the oxide layer; as these cracks approach the SiO2/Si interface (with its three-fold modulus mis match), fracture mechanics calculations of the crackdriving force showed that it decreased as cracks got closer to the interface [309]. Thus, the reaction-layer fatigue model involves cyclic stress-enhanced surface oxide thickening, which then undergoes environmentally assisted stress corrosion cracking. The process repeats until a critical crack size is reached, and the silicon itself fractures catastrophi cally. In other words, the fatigue damage occurs only in the surface oxide. While stress corrosion has both a time dependence and a monotonic stress dependence, if the rate-controlling step is the oxide thickening which depends only on the cyclic stresses, the time depend ence of fatigue failure is avoided. However, Kahn et al. [311] argued that TEM, which was used by Muhlstein et al. [306] to obtain the images of surface layers that contain cracks that were then used to support this model, is both unconventional and quite difﬁcult to use to determine the thickness of a surface layer on a sidewall because the microfabricated sidewalls of the polysilicon specimens are neither perfectly ﬂat nor perfectly vertical. Furthermore, they claimed that this type of analysis can not determine whether the thickness of the surface oxide is uniform through the 2000-nm height of the polysili con device, or whether the observed thickness increase is due to redistribution of the initial oxide [311]. Finally, Kahn et al. considered another concern about the SAMcoated results, which showed failures at 107 and 108

CHAPTER 11

cycles (4.2 and 42 min) for specimens with peak stresses of 2.8 GPa. For these devices to fail via the reactionlayer mechanism the SAM must ﬁrst break down, then a surface oxide of sufﬁcient thickness (20 nm) must grow, followed by stress corrosion cracking of the oxide layer, all within the time span of a few minutes. Another mechanism, complementary to reactionlayer fatigue, was proposed on the basis of the surface topology changes with increasing distance from the notch seen in in situ AFM images of the region near the notch, before and after cyclic actuation [312–316]. These changes indicated a role of stress in the evolution of surface topography under cyclic loading and were ascribed to the roughening of the surface oxide layer, which in turn was associated with a mechanism of cyclic stress-assisted dissolution of the surface oxide layer such that deep grooves are formed where the dissolu tion is fastest that could result in fatigue crack nuclea tion. One drawback of this model as stated by Kahn et al. [311] is that cyclic stress-enhanced oxidation has never previously been observed. Though Allameh and coworkers [314, 315] report that their specimens had an initial surface oxide of 2–4 nm, they used the same structures as Muhlstein et al. [306], who showed sur face oxides of about 30 nm. Another concern is that Allameh and coworkers [312–316] used the model based on the stress-dependent surface reaction model of Yu and Suo [317], which involves monotonic stresses, not the cyclic stresses that Allameh et al. used exclu sively. Also, this model has a time dependence, which Bagdahn and Sharpe [318] have shown is not a feature of silicon fatigue as discussed later in this section. Completely different mechanisms for the fatigue of micron-scale polysilicon were suggested by Kahn et al. [286, 308, 319–322] on the basis of results from speci mens tested at varying stress ratios (�3 � R � 0.5) in laboratory air and in a medium vacuum (8 Pa pressure). First, Kahn et al. claimed that fatigue crack initiation and growth occurred during cyclic loading in both air and vacuum, although the process was faster in air. Then these authors suggested a purely mechanical mechanism for the fatigue behavior of silicon thin ﬁlms via subcriti cal cracking of the silicon itself. Further, these authors found that the low-cycle fatigue strength of the electro statically actuated single edge notched microspecimens was affected more by the stress ratio than by the envi ronment. On the basis of this, they concluded that the fatigue mechanism for silicon thin ﬁlms was strongly affected by the compressive portion of the loading cycle, which they reasoned could create a microcrack at the surface due to wedging on surface asperities and allow further crack growth due to a mechanism similar to farﬁeld cyclic compression fatigue of brittle ceramics. Later their investigations of the high-cycle (104 � 3 � 108 cycles) fatigue behavior in air and vacuum found no 213

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fatigue failures in a medium vacuum. On the basis of this work Kahn et al. postulated that thickened surface oxide on newly formed crack surfaces in air could cause wedging effects that would create additional subcritical cracking or that wear debris formed in vacuum could prevent crack closure and therefore decrease crack driv ing force and growth [311]. The fracture–mechanics– based ﬁnite-element modeling used for calculations of the crack-opening proﬁle and the driving force for advance of wedged cracks showed, however, that in compression, such wedges do not cause an increase of the magnitude of the stress-intensity factor, leading to the conclusion that this mechanism cannot contribute signiﬁcantly to the fatigue of silicon thin ﬁlms [298]. Then, in their experiments on mean stress effect on the low-cycle fatigue of Pd-coated undoped and B-doped polysilicon ﬁlm, Kahn et al. [323] found that increasing the amplitude of the cyclic stress with a positive mean stress led to the higher fracture stress, whereas negative mean stress led to the lower fracture stress. They showed, in particular, that a cyclic, but not monotonic, loading had an inﬂuence on the fracture stress and that loading with an applied cyclic stress, with mean stress offset below the fracture stress was followed by a ramp to failure. These low-cycle fatigue results were rationalized in terms of a “weakening and strengthening map”, where weakening occurs when the fatigue strengthening is found at low-fatigue amplitude where the mean stress is highly compressive or highly tensile. No effect was found at low fatigue amplitudes with low mean stress (compressive or tensile). To account for all their observations Kahn et al. suggested three possible fatigue mechanisms. The ﬁrst of these was based on the idea of the microcracking of the silicon and was discarded later as inappropriate as an explana tion of the weakening and the strengthening due to crack tip shielding. A second mechanism was suggested involv ing dislocation activity, which would cause crack-tip blunting in the case of a strengthening effect and cracktip blunting followed by sharpening for a weakening effect. However, in order for this mechanism to operate

there should be a readily detectable dislocation den sity observed, but that is not the case for silicon [311]. Moreover, there has been no direct evidence to date of dislocations at arrested crack tips in silicon; room tem perature dislocation plasticity in silicon has only been observed to date during the high combined compressive and shear loads of an indentation test [324]. Their third proposed mechanism involved grain-boundary plastic ity, where an amorphous grain-boundary region hitting the surface under stress would experience a nonconven tional plastic deformation in shear, which would then cause a residual compressive stress, possibly resulting in the observed strengthening effect. To support this model Kahn et al. presented results of their element mode ling, where they showed that with such grain-boundary plasticity residual compressive stresses could occur. However, as argued by Alsem et al. [298], there is no experimental evidence for these modeled results; fur thermore, the fact that single-crystal micron-scale silicon is also susceptible to fatigue failure is totally inconsistent with any mechanism involving only grain boundaries. Bagdahn and coworkers [318, 325, 326] combined their data on the inﬂuence of frequency on the highcycle fatigue behavior with those of Muhlstein et al., Kahn et al., and Kapels et al. into a single plot of nor malized peak stress versus fatigue lifetime and found that all the data followed the same curve. They con cluded that fatigue lifetime depends only on the number of cycles, not on the total time or the frequency of the test, and ﬁt the results to the equation σf σc

.02 � N�0 f

where σf is the peak stress in the fatigue cycle, σc is the monotonic strength, and Nf is the number of cycles to failure. They also noted an increase in surface rough ness of the top surface of their specimens in the vicin ity of the fatigue fracture [318]. Finally, they concluded that there should be an additional effect (other than the environmental inﬂuences) to account for all the results.

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292. M.D. Thouless, R.F. Cook, Appl. Phys. Lett. 56 (1990) 1962. 293. C.G. van deWalle, F.R. McFeely, S.T. Pantelides, Phys. Rev. Lett. 61 (1988) 1867. 294. B. Wong, R.J. Holbrook, J. Electrochem. Soc. 134 (1987) 2254. 295. J.A. Connally, S.B. Brown, Science 256 (1992) 1537. 296. S.B. Brown, W. Van Arsdell, C.L. Muhlstein, in: K. Wise, S. Senturia (Eds.), Technical Digest––1997 International Conference on SolidState Sensors and Actuators, IEEE, Piscataway, NJ, 1997, p. 591. 297. N.I. Kato, A. Nishikawa, H. Saka, Proceedings of the Advanced Characterization of Semiconductor Materials, Conference, 2000, Elsevier, New York. 298. D.H. Alsem, O.N. Pierron, E.A. Stach, C.L. Muhlstein, R.O. Ritchie, Adv. Eng. Mat 9 (2007) 15. 299. M. Koskenvuori, T. Mattila, A. Haara, J. Kiihamaki, I. Tittonen, A. Oja, H. Seppa, Sens. Actuators A 115 (2004) 23. 300. O.N. Pierron, C.L. Muhlstein, J. Microelectromech. Syst. 15 (2006) 111. 301. K. Komai, K. Minoshima, S. Inoue, Micros. Tech. 5 (1998) 30. 302. K. Minoshima, T. Terada, K. Komai, Fatigue Fract. Eng. Mater. Struct. 23 (2000) 1033. 303. A.M. Fitzgerald, R.S. Iyer, R.H. Dauskardt, T.W. Kenny, J. Mater. Res. 17 (2002) 683. 304. C.L. Muhlstein, S.B. Brown, R.O. Ritchie, Sens. Actuators A 94 (2001) 177. 305. C.L. Muhlstein, S.B. Brown, R.O. Ritchie, D.A. LaVan, A.A. Ayon, T.E. Buchheit, M.J. Madou (Eds.), Materials Research Society Symposium Proceedings, Boston, MA, 2002a, vol. 741. 306. C.L. Muhlstein, E.A. Stach, R.O. Ritchie, Acta Mater. 50 (2002) 3579. 307. C.L. Muhlstein, E.A. Stach, R.O. Ritchie, Appl. Phys. Lett. 80 (2002) 1532. 308. P.A. Warrendale, Mater. Res. Soc. (2003) J3.5.1. 309. C.L. Muhlstein, R.O. Ritchie, Int. J. Fract. 120 (2003) 449. 310. O.N. Pierron, C.L. Muhlstein, Int. J. Fract. 35 (2005) 1. 311. H. Kahn, R. Ballarini, A.H. Heuer, Solid State Mater. Sci. 8 (2004) 71. 312. S.M. Allameh, B. Gally, S.B. Brown, W.O. Soboyejo, in: H. Kahn, M. de Boer, M. Judy, S.M. Spearing

Mechanical Properties of Silicon Microstructures (Eds.), Materials Research Society Symposium Proceedings, Boston, MA, 27–28 November 2000, vol. 657. 313. S.M. Allameh, B. Gally, S.B. Brown, W.O. Soboyejo, in: C. Muhlstein, S. Brown (Eds.), Mechanical Properties of Structural Films, American Society for Testing and Materials, STP 1413, West Conshohocken, PA, 2001, p. 3. 314. S.M. Allameh, P. Shrotriya, A. Butterwick, S.B. Brown, W.O. Soboyejo, J. Microelectromech. Syst. 12 (2003) 313. 315. P. Shrotriya, S.M. Allameh, S.B. Brown, Z. Suo, W.O. Soboyejo, Exp. Mech. 43 (2003) 289. 316. P.A. Warrendale, Mater. Res. Soc. (2001) EE5.8.1. 317. H.H. Yu, Z. Suo, J. Appl. Phys. 87 (2000) 1211. 318. J. Bagdahn, W.N. Sharpe Jr., Sens. Actuators A 103 (2003) 9. 319. H. Kahn, N. Tayebi, R. Ballarini, R.L. Mullen, A.H. Heuer, Transducers ’99: Proceedings of the Tenth International Conference on Solid

State Sensors and Actuators, 1999, Elsevier, New York. 320. H. Kahn, R. Ballarini, R.L. Mullen, A.H. Heuer, Proc. Roy. Soc. London A 455 (1999) 3807. 321. H. Kahn, R. Ballarini, A.H. Heuer, in: D.A. LaVan, A.A. Ayon, T.E. Buchheit, M.J. Madou (Eds.), Materials Research Society Symposium Proceedings, Boston, MA, 2002, vol. 741. 322. H. Kahn, R. Ballarini, J. Bellante, A. H. Heuer, Science 298 (2002) 1215. 323. H. Kahn, L. Chen, R. Ballerini, A.H. Heuer, Acta Mater. 54 (2006) 667. 324. A.M. Minor, E.T. Lilleodden, M. Jin, E.A. Stach, D.C. Chrzan, J.W. Morris Jr., Phil. Mag. A. 85 (2005) 323. 325. J. Bagdahn, J. Schischka, M. Petzold, W.N. Sharpe, Jr., in: Proceedings SPIE Conference on Reliability, Testing, and Characterization of MEMS/MOEMS, San Francisco, CA, 22–24 October, 2001, vol. 4558, pp. 159–168.

CHAPTER 11

326. W.N. Sharpe Jr., J. Bagdahn, in: A. Bolm (Ed.) Proceedings International Fatigue Congress, FATIGUE 2002, Stockholm, Sweden, 2002, vol. 3, p. 2197. 327. A.A. Bonapasta, C. Battistoni, A. Lapiccirella, N. Tomassini, S.L. Altmann, K.W. Lodge, V.V. Bulatov, S. Yip, A.S. Argon, Phil. Mag. A 72 (1995) 453. 328. Ganchenkova et al. (to be published) 329. E. Kaxiras, K.C. Pandey, Phys. Rev. B 38 (1988) 1236. 330. E. Bouchard, J.P. Bouchard, D.S. Fisher, S. Ramanathan, J.R. Rice, J. Mech. Phys. Solids 50 (2002) 1703. 331. T. Tsuchiya, A. Inoue, J. Sakata, M. Hashimoto, A. Yokoyame, M. Sugimoto, in: Technical Digest of the Sensor Symposium, Tokyo, Institute of Electrical Engineers of Japan, 1998, vol. 16, p. 277–280. 332. A. Umerski, R. Jones, Phil. Mag. A 67 (1993) 905.

Additional References V.V. Bulatov, S. Yip, A.S. Argon, Philos. May. A 72 (1995) 453 J.F. Justo, M. Clekoning, W. Cui, V.V. Bulatov, Phys. Rev. Lett. 84 (2000) 2172 H. Alexander, in: F.R.N. Nabarro (Ed.), Dislocation in solids, vol. 7, North-Holland, Amsterdam, 1986, p113. A.M. Fitzgerald, R.H. Dauskardt, T.W. Kenny, Seas. Actuators A 83 (2000) 194–199. J. Riedle, P. Gumbsdi, H.F. Fischmeister, Phys. Rev. Lett. 76 (1996) 3594. R. Mikkula, J. Stadler, F. Krul, H-R. Trebin, P. Gumbch, Phys. Rev. Lett 81 (1998) 3163.

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12

Chapter Twelve Electrostatic and RF-Properties of MEMS Structures Ilkka Tittonen and Mika Koskenvuori Micro and Nanosciences, Micronova, Helsinki University of Technology, Espoo, Finland

12.1 Introduction

– Small size of MEMS and NEMS devices means also

Well-known examples of micromechanical sensors are accelerometers, pressure sensors and cantilevers that are used, for example, as ﬂuid sensors and in various microscopes. In designing and modeling of nano and micromechanical systems the following general aspects should be taken into account:

– Capacitive coupling leads to a novel capacitor of

– The sound velocity depends on the chosen material

and affects the properties of dynamical systems. – Particular design ﬁnally determines basic resonance

modes and frequencies and leads to the modiﬁcation of stiffness. – Any mechanical device has an inﬁnite number of

various mechanical vibrational modes. – Dissipation of mechanical energy is often difﬁcult

to predict, especially since total dissipation is a sum of contributions of intrinsic and external losses of energy. – In case the material is anisotropic (like single crystal

silicon), the mechanical properties depend on the crystal orientation. – Both the capacitive and piezoelectric coupling make

it straightforward to create local forces that can be used in actuation of micromechanical devices. – Capacitive and piezoelectric couplings are also

potential ways to integrate the mechanical systems as part of the electric circuit.

high capacitance values. which value is dynamic and depends on the applied voltage across its gap (bias-voltage UDC). – Small gaps (signiﬁcantly below 1 μm) are still a

challenge for mass fabrication. – Small (capacitive) mechanical sensors may

easily suffer from charging of surfaces, diffusion, contamination and break through currents and may need to be surface passivated or encapsulated. – RF MEMS devices are highly potential candidates as

reference oscillators, ﬁlters and switches. – Finite-element method (FEM) is often more or less

the only way to simultaneously model mechanical, thermal and electric effects. – Often ﬁnite-element modeling leads to higher level

circuit simulations by giving the necessary input parameters.

12.2 Model System for a Dynamic Micromechanical Device A most simpliﬁed way of modeling a micromechanical moving system is to form a lumped element model that contains a minimum number of physical parameters (Figure 12.1). Resonators moving as a response to an external force can be described using at least three different

221

Modeling in MEMS

PA R T I I

Fig 12.1 ● Model system of a dynamic micromechanical system.

parameters: the spring constant k, the effective mass m and the damping constant c. The spring constant depends on the chosen material and the design and in resonant cases also on the particular vibrational mode. The effective mass is a measure of the size of the moving part, but it is also affected by the strength of coupling to the support (substrate, etc.). Damping takes into account both the internal and external sources of energy leakage. Resonators are usually driven using harmonic forces, which are often achieved by capacitive coupling. In such cases the dynamic motion of a micromechanical resonator can be described by the differential equation of motion: mx�� cx� kx Fˆ cos ωt

(12.1)

The ﬁrst term on the left describes acceleration that becomes mediated by the effective mass m, the second term originates from damping which is proportional to the velocity x� , and the third term gives the displacement as a response to the external force via the spring constant k. In some cases (e.g., k3x3) higher order nonlinear terms need to be added for more accurate modeling of the response. The right-hand-side of the equation could be any time-dependent or static actuating force. In case of harmonic excitation with the force amplitude Fˆ, the displacement and the solution to the equation of motion can be found in a closed form:

x

Fˆ m

⋅ 2 ⎛ ⎞ cω ω02 − ω

⎜⎜ ⎟⎟⎟ ⎜⎝ m ⎠ ⎡ ⎛ cω ⎞⎟⎤ ⎜⎜ ⎢ ⎟⎟⎥ ⎢ ⎜⎜ m ⎟⎟⎥ cos ⎢ ωt − arctan ⎜ 2 ⎥ 2⎟ ⎜ ⎢ ⎜⎜ ω0 − ω ⎟⎟⎟⎥⎥ ⎢ ⎠⎟⎦ ⎝⎜ ⎣

(

222

)

As is obvious, the phase of the mechanical motion is usually delayed relative to the excitation signal. The maximum amplitude can usually be found at resonance. At this frequency the phase of the oscillation is 90° behind that of the force. The resonance frequency becomes also affected by damping

2 2

(12.2)

2 1 ⎛ c ⎞⎟ ⎟⎟ ωr ω0 1 − ⎜⎜⎜ 2 ⎜⎝ mω0 ⎟⎠

(12.3)

where ω0

k meff

(12.4)

where k is the mechanical spring constant of the resonator and meff is the effective mass of the resonator. It should be noted that the effective mass is different from the dimensional mass m V·ρ that is derived from the volume V of the resonator and the density ρ of the resonator material. The relationship between the two masses is determined by the vibration mode of the resonator. Some examples can be seen from Table 12.1. In principle the modiﬁcation of the damping could lead to a feasible tuning of the resonance frequency; however, usually this is not easily accomplished in practice. A more detailed effect of damping on the amplitude and phase is shown in Figure 12.2. The dynamic amplitude at the resonance frequency over the static displacement is the Q-factor, Q,

Electrostatic and RF-Properties of MEMS Structures

CHAPTER 12

Fig 12.2 ● Effect of damping on the amplitude and phase response near the resonance frequency that has been normalized to one. Q-factor is varied between 0.1 and 100.

Q

xˆr x st

ω02

(

ω02 − ω 2

)

2

⎛ cω ⎞2

⎜⎜ ⎟⎟⎟ ⎜⎝ m ⎠

≈

mω0 c

(12.5)

The last approximation of Eq. 12.5 is valid, when Q is high (i.e., the frequency shift is negligible). We notice that high damping (low Q) makes the resonance invisible as a function of frequency. Often some acoustic microsystems are heavily gas-damped and do not show any typical resonant behavior. The same holds true also for certain sensors where the operation principle is the detection of the mechanical displacement. Typical of such examples are accelerometers. As an example we study a simple (silicon) beam that is ﬁxed from one end and also a bridge that is being supported from both ends (Figure 12.3). By using FEM one can create exaggerated vibrational mode patterns that are useful in understanding the motion and especially the frequency response. Any (micro)mechanical device can be excited to vibrate in an inﬁnite number of modes. What is maybe not so well known is that FEM calculations give us mode-dependent parameters to be used in lumped models in further analysis of the microsystems. In this case we take a piece of single crystal silicon and assume that it is of isotropic material with length L 100 μm, width w 10 μm and height h 10 μm. For Young’s

modulus for silicon we use E 131 GPa, for density ρ 2330 kg/m3 and for Poisson ratio ν 0.27. These examples reveal that the way of supporting and ﬁxing a micromechanical device drastically affects the boundary conditions and the corresponding dynamic response of the system (Figures 12.4–12.5). One should also note that rather simple equations of motion can be used in many cases to predict response by including the effect of the particular vibration mode on the effective mass (Table 12.2 and Figure 12.6). One should especially notice that the dimensional mass obtained by density times volume does not give the correct resonant frequencies since the coupling to the support modiﬁes the free mass response.

12.3 Electrical Equivalent Circuit The mechanical model presented in the previous chapter is useful in many analyses. Often in practice an electrical circuit simulator is used to obtain detailed information of the behavior of this model as a part of an electronic circuit. It is useful to transform the previous information into a form that is readily usable in circuit design calculations. In electrical domain, the basic resonator consists of reactive components such as inductance and capacitance. Since the mechanical oscillator is in practice always damped, a ﬁnite Q-factor requires a resistive 223

Modeling in MEMS

PA R T I I

Fig 12.3 ● A mechanical bridge that is ﬁxed from both ends. The force is acting in the transverse direction at the center point of the bridge. This system shows also rather strong mechanical nonlinearity, since the stiffness in the longitudinal (horizontal) direction increases with increasing the strength of the force (see Figure 12.6).

load to be included in the equivalent circuit. A series electrical resonance circuit (Figure 12.7) for resonator obeys a differential equation

Table 12.2 Resonant mode frequencies and the corresponding effective mass values of a micromechanical bridge

Mode #

d2q

dq q L 2 R

uˆ ⋅ cos ωt dt C dt

(12.6)

where q stands for charge. This equation is of analogous form with the equation of mechanical motion. If we scale the electrical equations with the electromechanical coupling factor η, where q ηx, we can calculate the corresponding values of the components in this equivalent circuit as

Frequency, f (Hz)

Effective mass, meff (kg)

Bridge supported from both ends (Figure 12.4) 1

7331179

9.46E-12

2

18898040

1.42E-12

3

34302020

4.32E-13

4

52256380

1.86E-13

Beam supported only from one end (Figure 12.5)

Rm Lm

c η2 m

≈

η2 η2 Cm k F and u η 224

mω0 Qη 2 (12.7)

q ηx

1

1228723

3.37E-10

2

7394308

9.3E-12

3

19509020

1.34E-12

4

35484160

4.04E-13

The effective masses are calculated from Eq. 12.4 based on the simulated resonance frequency f and the spring constant k (Figure 12.6). The corresponding resonant modes are shown in Figures 12.4 and 12.5.

Electrostatic and RF-Properties of MEMS Structures

CHAPTER 12

Fig 12.4 ● The ﬁrst four fundamental resonance modes of a beam that is ﬁxed only at one end. The movement of the beam is ﬁxed to take place only in-plane. The amplitudes in each sub-ﬁgure (a–d) are individually scaled and are not therefore mutually comparable.

The strength of the coupling factor η depends on the coupling scheme. Here we use only electrostatic (capacitive) coupling between the mechanical and electrical domain (Figure 12.8). When a voltage difference U is applied between the electrodes of a capacitor C, the electrostatic energy E stored in the capacitor is E=

1 CU 2 2

(12.8)

The value of the capacitance C (in Figures 12.8 and 12.9) depends on the separation of the electrodes (socalled gap size) d, which is varied due to the displacement of the moving resonator, denoted by x and on the capacitance with zero displacement C0 A0/d C

ε0 A C0 d d−x d−x

(12.9)

where A is the effective area between the electrode and the resonator, usually determined by the thick-

ness of the device layer of the wafer and by the width of the electrodes used to excite and detect the movement.

12.4 Electrostatic Force If the biasing voltage used is a DC voltage UDC, the electrostatic force can be calculated as a negative gradient of energy. Using Taylor’s expansion, the electrostatic force can be written as � U 2C0 U 2 ∂C � . F− ux ≈ − 2 ∂x 2d 2 3 n⎤ ⎡ ⎢1 2⎛⎜ x ⎞⎟⎟ 3⎛⎜ x ⎞⎟⎟ 4 ⎛⎜ x ⎞⎟⎟ � ( n 1)⎛⎜ x ⎞⎟⎟ ⎥ u� ⎜⎜ ⎟ ⎥ x ⎜⎜ ⎟ ⎜⎜ ⎟ ⎜⎜ ⎟ ⎢ ⎝d⎠ ⎥ ⎝d⎠ ⎝d⎠ ⎝d⎠ ⎢⎣ ⎦ (12.10) where the capacitance C is deﬁned by Eq. 12.9. 225

Modeling in MEMS

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Fig 12.5 ● The ﬁrst four fundamental resonance modes of a bridge having the two ends ﬁxed. The movement of the beam is ﬁxed to take place only in-plane. The amplitudes in each sub-ﬁgure (a–d) are individually scaled and are not therefore mutually comparable.

drive voltage frequency. This can be seen by calculating the second power of voltage U as

0.12 0.1

y = 1.5077·1014·x3 + 2.0237·107·x2 + 20082·x + 3·10–6

F (N)

0.08

2 U 2 (U DC ûac cosωt)2 U DC

0.06

1 2

ûac cos 2ωt 2U DC ûac cosωt 2

0.04 0.02

(12.11)

and by calculating the force F by inserting Eq. 12.11 into Eq. 12.10 as

0 0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

x (μm)

Fig 12.6 ● Deﬂection amplitude of the bridge shown in Figure 12.3 as the transverse force is increased. As is obvious, weak forces cause a rather linear response, but the system shows also a nonlinear spring constant when strong forces are present. This property can be used to ﬁne tune the resonance frequencies.

From Eq. 12.10 it is evident that the force is proportional to the second power of the voltage. Thus, if the excitation of the resonator is performed with AC voltage, a DC bias voltage is required to create the force that excites the resonator at the frequency of the AC 226

1 2 ûac 2

� 1 ∂C F− . 2 ∂x ⎛ 2 ⎞� 1 2 2 ⎜⎜U DC 1 uac

uac cos 2ωt 2U DC uac cos ωt⎟⎟⎟ ux ⎜⎝ ⎠ 2 2 (12.12) From Eq. 12.12 we can see that the electrostatic force can have components at zero frequency, at ω and at 2ω, when the frequency of the exciting AC voltage is ω. Since we aim at having an excitation at ω frequency, the DC voltage amplitude should typically be stronger than the AC voltage amplitude. Eq. 12.12 also reveals that

Electrostatic and RF-Properties of MEMS Structures

Rs

Rm

Cm

where the factor multiplying x can be interpreted as the electrical spring constant ke

Lm

ZL

Fig 12.7 ● An electrical equivalent circuit presentation of a simple mass-spring system presented in Section 12.2. The shaded parts represent the source and load that are used to excite and detect the resonance, respectively. x Static electrode

m

Y C(t)

Fig 12.8 ● Model system of a dynamical micromechanical device coupled by a time-dependent capacitance C(t).

Static electrode

U F

x

Fig 12.9 ● Electrostatic force depends on the voltage over the coupling capacitance that is generated by the static and movable electrodes.

the DC voltage signiﬁcantly ampliﬁes the excitation strength. As the generated displacement x is typically small compared with the gap size d (i.e., the resonator operates in the linear region), the force can be approximated as ⎛ x ⎞⎤ C ⎡ C U2 F ≈ − 0 ⎢1 2⎜⎜ ⎟⎟⎟⎥ U 2 ≈ − 0 DC ⎝⎜ d ⎠⎥⎦ 2d ⎢⎣ 2d C U uˆ C U2 x − 0 DC ac cos ωt − 0 2DC d d

2 C0U DC

d2

(12.14)

We thus obtain a very useful result that the DC voltage directly leads to one-directional tuning of the resonance frequency of the mechanical resonator. The strength of this tuning can be calculated by replacing the mechanical spring constant k with the sum of electrical and mechanical spring constants k → km ke in case of no damping: ke C U2 ω0 1 − 0 Dc km km d 2 ⎛ C U 2 ⎞⎟⎟ ≈ ω0 ⎜⎜⎜1 − 0 Dc ⎟ ⎜⎝ km d 2 ⎟⎟⎠

F

d

ke −

ω ω0 1 −

k

Movable electrode

CHAPTER 12

(12.13)

(12.15)

This spring softening effect can be seen from Figure 12.10. In various RF applications, this is a very useful property. From Eq. 12.15 it appears, that the electric ﬁeld which is generated by the applied DC bias-voltage UDC can be used to tune the spring constant of the resonator. This opens at least two options: (i) by applying a constant voltage (U UDC) the resonant frequency of the resonator can be tuned and (ii) by applying a periodically changing voltage (U uac), the spring constant can be modulated, this can be used to realize mechanical parametric ampliﬁcation of the electromechanical device [1]. Additional effects caused by the capacitive nonlinearity will be discussed later in more detail. We can thus summarize that for the electrostatic coupling realized via voltage-biased parallel plate transducers the magnitude of the electrostatic force at the excitation frequency ω depends both on the applied AC and DC voltages and also on the gradient of capacitance. It should also be noted, that even when high DC bias voltage is used, the electrostatic coupling leads to a minimal power consumption. If the nonlinear contribution to the excitation force is unacceptable, another way to perform the biasing of a micromechanical device is to keep the charge q instead of the voltage of the capacitor constant. In this case the force becomes F−

q2 ∂ ⎛⎜ 1 ⎞⎟ � ⎜ ⎟ ux 2 ∂x ⎜⎝ C ⎟⎠

(12.16)

As a difference to the voltage biasing, the charge biasing leads to the force amplitude F that is independent of the actual displacement x. 227

Modeling in MEMS

PA R T I I

180

–20 150 V 112.5V 75 V

90

S21 (dB)

37.5 V –60

0

–80

–90

–100

Phase (degree)

–40

–180

5.100M

5.225M

5.350M

5.475M

5.600M

Frequency (Hz) Fig 12.10 ● The bias-voltage UDC is varied between UDC [0…150] V. The effects of increased electromechanical coupling are evident by (i) the increased transmission S21 and (ii) lowering of the resonance frequency (spring softening). For UDC 0 V, there is no output signal.

Another way to reduce the nonlinearity is to use comb-shaped electrodes instead of the parallel plate electrodes. Then the capacitance becomes ε h( Le − x) C 0 d

12.5 Electromechanical Coupling The relation between the AC-voltage and the force is ∂C uac ∂x

U DC

(12.17)

where Le is the length of the comb ﬁnger.

F U DC

since UDC uac. If we assume that the motion is sinusoidal, we get

(12.18)

In addition to the voltage and the vibration amplitude, the motional current also depends on the frequency and the gradient of the capacitance between the electrode and the resonator. By dividing the force with the spring constant and noting that the force is actually multiplied by the quality factor of the device, we get the vibration amplitude at resonance xˆR Q

where the electromechanical coupling factor is η U DC

C ∂C ≈ U DC 0 ∂x d

(12.19)

Therefore, the coupling between electrostatic and mechanical domains depends on the coupling capacitance and the gap size between the electrodes as well as on the DC bias voltage over the gap. Thus, narrow gaps can be used to increase the electromechanical coupling.

12.6 Sensing of Motion The oscillating MEMS resonator can be sensed using a DC-biased electrode. To analyze the motional current induced by this vibration, we can start by writing down the expression for the electrical current im 228

dq d(CU ) ∂C ≈ U DC dt dt ∂t

∂C � ∂C ∂(x� ⋅ sin ωt) U DC ωx ⋅ (12.21) ∂x ∂t ∂x cos ωt η 2ωûac ⋅ cos ωt

(12.20)

ηuˆac C U uˆ ≈ Q 0 dc ac k kd

(12.22)

Thus, the amplitude of the motional current at resonance can be written in a form η 2 uˆac ω U 2 uˆ ωC2 ˆi ≈ Q DC ac2 0 m, R Q k kd

(12.23)

The motional current depends strongly on the electromechanical coupling factor (i.e., DC bias voltage and the gradient of the coupling capacitance). On the other hand, the gradient of the capacitance C/x in Eq. 12.20 can again be approximated by Taylor’s series as dq ∂C ∂C ∂x U Dc U Dc dt ∂t ∂x ∂t ⎛ ⎞⎟ ∂x ⎛ x ⎞2 C ⎜ x U DC 0 ⎜⎜1 2 3⎜⎜ ⎟⎟⎟ �⎟⎟⎟ ⎜⎝ d ⎠ d ⎜⎝ d ⎟⎠ ∂t

imot

(12.24)

Electrostatic and RF-Properties of MEMS Structures

From Eq. 12.24 it is clear that even linear vibrations can result in higher harmonics in the motional current. Therefore, for practical purposes the amplitude of vibration should be maintained at a reasonable level.

The total force exerted onto the resonator is a sum of the electrostatic force (Eq. 12.10) generated by the applied voltage and the mechanical spring restoring force, Fm kx, due to the displacement of the resonator. When the electrostatic force is increased and the resonator becomes more displaced, the spring restoring force also increases leading ﬁnally to the equilibrium position (Figure 12.11). However, when comparing the electrical and mechanical forces in Figure 12.11 it is evident that when the applied voltage exceeds a certain threshold value, the electrical force will always be greater than the mechanical force and no equilibrium position exists. The exact voltage corresponding to this phenomenon is called the pull-in voltage, Upi. The pull-in behavior is observed when the mechanical and electrical forces (and simultaneously also their derivatives) cancel each other. In a static case with one electrode it is given by U pi

km d 2 2C0

(12.26)

From Eqs 12.25 and 12.26 one can observe that the pull-in voltage depends on the coupling strength and on the mechanical spring constant. For capacitive switches the pull-in phenomenon is desired and thus such devices are usually designed for low pull-in voltages—however, low pull-in voltage usually results in a mechanically soft structure which on the other hand reduces the operating speed (frequency) of the switch. For capacitively coupled resonators the pull-in voltage limits the tunability of the resonance of the device. This limit can be seen by inserting the value of the pull-in voltage (Eq. 12.25) into the equation describing tuning (Eq. 12.15). In case of one electrode the maximum frequency tuning is only in the order 16%, since

ω0

2 C0U Dc kmd 2

ω0 1 UDCUpi

8 ≈ 0.84ω0 1 27

|Fe|, U > Upi |Fm|

2

Pull-in point

1.5 1

Equilibrium points

0.5 0

0

0.2

0.4

0.6

0.8

Relative displacement, x/d

Fig 12.11 ● Comparison between the electrostatic force (black curves), Fe and mechanical spring restoring force (gray line), Fm. When the bias-voltage is kept below the pull-in voltage, increasing the displacement the mechanical spring restoring force also increases and the system reaches equilibrium when the forces are equal to each other. However, it is evident that with increasing bias-voltage, the electrostatic force eventually becomes larger than the mechanical spring restoring force and the pull-in occurs.

(12.25)

Similarly, in a static case with the electrodes on both sides of the moving device the pull-in voltage is

ω ω0 1

|Fe|, U = Upi

12.8 Parasitic Capacitance

8d 2 km 27C0

U pi

|Fe|, U < Upi

2.5

Force, F (a.u)

12.7 Pull-in Phenomenon

3

CHAPTER 12

C0U 2pi kmd 2

(12.27)

The capacitive coupling has a signiﬁcant drawback. The capacitor C0, which is used to couple electrical voltage to the mechanical force, also conducts the drive current across the capacitor. The equivalent circuit presented earlier should therefore be corrected by a parallel capacitor, which has the same value as the coupling capacitance C0 (Figure 12.12). The parasitic current is often much stronger than the induced motional current (it is a problem, because both currents oscillate at the same frequency). The ratio of the induced motional current and parasitic current is U 2 uˆ ωC2 Q DC ac2 0 2 ˆi QC0U DC m, R kd ˆi ω uˆac C0 kd 2 p

(12.28)

Thus, high-Q, high DC-voltage and a narrow gap help in improving coupling resulting simultaneously in a lower parasitic current. In addition, we can see that the AC-voltage has no effect on the motional to parasitic current ratio. The effect of the parasitic capacitance can also be seen from the frequency response of the resonator (Figure 12.13). There are also other sources of parasitic capacitance associated with the MEMS-resonators. Read-out electronics circuits are not usually directly integrated with 229

Modeling in MEMS

PA R T I I

MEMS, which means that we need for example bonded wires and packaging to apply resonators. The result is the increase of the parasitic capacitance. One potential option to reduce the effect of parasitic capacitance could be to use a parametric ampliﬁcation scheme, which means that the spring constant is modulated with a frequency ωpump 2ω0/n, where ω0 is the resonant frequency of the device and n is an integer. Usually n 1 and the modulation of the spring constant is performed at the frequency of ωpump 2ω0. Then the parasitic current oscillates at frequency which is different from the desired motional current resulting in the situation that the parasitic capacitances may not anymore be such a severe problem. The other possibility is to use separate electrodes for driving and sensing. If the (parasitic) capacitance between the drive and sensing electrodes is low and the resonator is AC-grounded, most of the parasitic current can be eliminated (in the case of integrated MEMS-resonators).

12.9 Effect of Built-in Potential on Capacitively Coupled MEMSDevices As the strength of the capacitive coupling and also the effects of the capacitive nonlinearity are strongly dependent on the bias-voltage, it is clear that the stability of the bias-voltage is essential when considering the stability of electrostatically coupled MEMS-devices. A DC biased capacitive coupling gap is shown in Figure 12.14. Here the system consists of a static electrode and a vibrating electrode (resonator) and the static electrode is coated with a layer of dielectric. The system is biased with a DC voltage UDC. However, in addition to the applied bias voltage, UDC, the material parameters (work-functions of the materials 1 and 2) and the charges residing in the dielectric layer contribute to the total bias voltage experienced by the coupling gap. When calculating the total bias-voltage in the coupling gap d, we get the result

C0

U UDC ϕ12 Rs

Rm

Cm

QOX C2

where UDC is the applied bias-voltage, 12 is the difference of the work-functions between the two electrodes, QOX is the charge in the dielectric on top of the static electrode and C2 is the capacitance over the dielectric. The additional term to the applied bias-voltage UDC is usually called the built-in voltage Vbi of the system

Lm

ZL

Fig 12.12 ● Electrical equivalent circuit of a resonator including the drive signal and the parasitic capacitance parallel with the RLC-tanks.

Vbi ϕ12

QOX C2

(12.30)

180

–10 0.1 pF

90

10 fF

0

–55 1 fF

Phase (deg)

S21 (dB)

–32.5

0.1 fF –90

–77.5 10 aF

–180

–100 5.100M

5.225M

5.350M

5.475M

5.600M

Frequency (Hz)

Fig 12.13 ● Inﬂuence of parasitic capacitance C0 on the transmission (frequency and phase) response of the resonator. The feed-through capacitor C0 is varied in a range of [0…1 pF].

230

(12.29)

Electrostatic and RF-Properties of MEMS Structures

the resonance frequency of the device as can be seen from Eq. 12.15. The effect could be further increased if the coupling of the MEMS-devices is improved by introducing the dielectric layers in the coupling gap [13]. On the other hand, the spontaneous built-in voltage can also be useful, one such example is the vibrating power harvester system utilizing built-in voltages [14].

UDC

(a)

Qox

xvib

Q2

ϕ1 V2 Static electrode (b)

Q1

ϕ2

d V1 Vibrating electrode

UDC

ϕ12

C2

C1

V2

V1

CHAPTER 12

Fig 12.14 ● . (a) Schematic view of a DC-biased capacitive RFMEMS device illustrating various contributions to the total bias voltage over the air gap and (b) a simpliﬁed electrical equivalent circuit for the system. Source: Reproduced from [7] with permission from IOP Publishing Ltd.

Equation 12.29 reveals that Vbi plays a role in the stability of various MEMS-devices. Even though its origin is rather well known, the effect on the stability has been much less studied. Built-in voltages are generated when two dissimilar materials are brought into contact—it is in principle a direct measure of the difference in the work functions [2]. In practice, however, the observed work functions are modiﬁed due to the thin layers of dielectrics present on the surfaces [3, 4] and vary as a function of the temperature and due to the adsorbents on the surfaces [5, 6]. Therefore, for many practical cases experimental methods are needed to unambiguously determine the built-in potentials of the interfaces. A good example of the effect of the built-in potential in case of a capacitive accelerometer is shown in Figure 12.15 [7]. Here the built-in potential causes the displacement of the proof-mass even in the case of zero acceleration of the device. The built-in potential has also been seen to affect the stability in the MEMSbased voltage-references [8, 9] with what some practical solutions have been found to minimize its effect [10]. For RF-MEMS switches the effect of built-in potential could become an issue by modifying the threshold value of the pull-in voltage, but can also lead to stiction due to the charging of the dielectrics [11, 12]. A similar effect takes place in MEMS-resonators where this voltage modiﬁes the electric spring constant and thus changes

12.10 Further Effects of Electrostatic Nonlinearities from Applications Point of View Electrostatic nonlinearities discussed earlier can generate harmful side-effects in capacitively coupled devices. In the following, these effects are studied in detail with respect to the two perhaps most promising application areas of MEMS-devices in RF-electronics which are ﬁlters and reference oscillators.

12.10.1 Case 1: Capacitively Coupled Filter The narrow resonance of MEMS-resonators gives the possibility of using them as highly selective bandpass ﬁlters. With proper biasing, the input signals at the resonance frequency of the resonator will introduce a force that is ampliﬁed by the quality factor Q of the resonator and therefore the signals at this frequency will be transmitted to the readout electronics. On the other hand, the signals lying outside the resonance passband will generate signiﬁcantly weaker force and are in principle rejected (Figure 12.16a). If a broader passband is required, it can be achieved by parallelizing resonators since the capacitive coupling provides a simple method to couple the input and output signals as long as the impedance matching is taken care of. However, the nonlinearity of the capacitive coupling can seriously deteriorate the performance of the ﬁlter due to the introduced intermodulation distortion (IM). The intermodulation distortion is responsible for converting the off-resonance signals into the resonance band. This is especially harmful in the case of ﬁlter-applications where those signals that are outside the ﬁlter passband would be converted inside the passband (Figure 12.16b). The third order nonlinearity that arises from the capacitive coupling brings along intermodulation distortion even when the vibration is in the linear regime. This can be seen by writing a Taylor’s expansion of the coupling gap capacitance C as C

2 ⎛ ⎞⎟ ⎛ x ⎞3 Aε0 x ⎛x⎞ ⎜ ≈ C0 ⎜⎜1 ∓ ⎜⎜ ⎟⎟⎟ ∓ ⎜⎜ ⎟⎟⎟ �⎟⎟⎟ ⎜⎝ ⎝⎜ d ⎠ (d ± x) d ⎝⎜ d ⎠ ⎟⎠ (12.31)

231

Modeling in MEMS

PA R T I I (a) 8.42 8.4

Vbi = Avg(Vpi2 +Vpi1) Vbi = (–1.51+ 0.1) / 2 Vbi = –705 mV

Capacitance (pF)

8.38 8.36 8.34 8.32

Vpi2

Vpi1

y = 0.03x2 + 0.0437x + 8.3028 Vbi = –0.0437/(2*0.03) Vbi = –728 mV Vbi determined by parabolic fit Vbi determined by pull-in

8.3 8.28 –2.5

–1.5

–0.5

0.5

1.5

2.5

Applied voltage (V)

(b)

(c)

(d)

Vbi

Vbi

UDC

UDC

U

Fig 12.15 ● (a) In capacitive sensors the built-in potential manifests itself as a zero-point offset that can be observed by measuring the capacitance of the sensor as a function of the applied bias-voltage UDC. (b) The capacitance is at minimum when UDC Vbi. (c) When UDC Vbi the capacitance increases due to the electrostatic force. (d) When the voltage between the electrodes (U UDC Vbi) exceeds the pull-in voltage, the electrostatic force draws the electrodes into contact. Source: Reproduced from [7] with permission from IOP Publishing Ltd.

fr + Δf f

Fig 12.16 ● (a) Operating principle of a microelectromechanical resonator used as a ﬁlter. The signals within the resonance band of the device are transmitted to the readout electronics while the signals outside the resonance band are rejected. (b) The principle of third order intermodulation generation. The cubic mixing due to the capacitive nonlinearity of the electrostatic transduction converts the signals outside the resonance band into the resonance band.

232

where C0 is the coupling gap capacitance at rest or C0 A0/d. In practice if two signals at frequencies ω1 ωres Δω, ω2 ωres 2Δω are coupled to the resonator acting as a ﬁlter the cubic (third order) mixing of these signals produces in addition to other contributions a third-order term at frequency 2ω1 ω2 which is identiﬁed as ωres. It is the resonant frequency of the device; therefore, the signal possessing this frequency will be transmitted through the system. This process of IM3 (third order intermodulation distortion) product generation is depicted in frequency domain in Figure 12.16b. To quantify the strength of capacitive nonlinearity, a parameter called the third order intercept point (IIP3) can be measured. It is a measure of how strong off-resonance interferers at frequencies ω1 and ω2 are needed in order to produce equally strong signal in the carrier frequency as if the same power was applied directly at the carrier

Electrostatic and RF-Properties of MEMS Structures

CHAPTER 12

Linear fits to the measured IM products 30 Output signal, Vout (dBmV)

10 –10

Direct excitation of the resonator

–30 –50 Measured intermodulation products

–70 Δω = 1 kHz

–90 –110

Δω = 200 Hz

–130 –150 –30

Δω = 20 kHz –20

–10

0

10

20

30

40

50

Input signal,Vin (dBmV)

Fig 12.17 ● Method of determining the IM3 product that is caused by the capacitive nonlinearity due to the electrostatic transduction. The IM3 product is characterized at three different separations Δω [20, 1000, 20000] Hz from the resonant frequency ω.

frequency. Schematically this is depicted in Figure 12.17. The intermodulation in capacitive devices is studied for example in Refs. [15–18].

Capacitively coupled silicon microresonators have been studied as a replacement for piezoelectric quartz crystals as a central component in reference oscillators for quite some time. It has been shown, that the silicon microresonators are capable of competing with the macroscopic quartz resonators both in terms of short-term stability [19–22] and in long-term stability [23–25]. However, the capacitive coupling used with silicon microresonators brings an interesting contribution to the short-term instability. The short-term stability dictates the spectral purity of the signal. It is usually speciﬁed through the phasenoise referenced at carrier power at certain offset from the carrier frequency (Figure 12.18). For example in order to meet the GSM-speciﬁcations [26] for the receiver sensitivity and blocking, a 13 MHz reference oscillator must meet the phase-noise speciﬁcations Lf 130 dBc/Hz at Δf 1 kHz offset from the carrier and L 150 dBc/Hz far away from the carrier (so called noise ﬂoor) [20]. The strict phase-noise requirements arise from the fact that for practical use the output frequency of an oscillator is multiplied in a phase-locked loop (PLL) to match the carrier frequency (e.g., 900 MHz for GSM-900) and naturally the existing low-frequency noise becomes multiplied in a same process.

3 m

Noise floor

L ∝ 1ω

Lf

L (dBc/Hz)

12.10.2 Case 2: Capacitively Coupled Reference Oscillator

Carrier level

1 L∝ ω

1 L∝ ω

2 m

1 m

1 L∝ ω

0 m

Δf 1

Frequency offset from carrier (Hz)

Fig 12.18 ● Deﬁnition of SSB (single-side-band) noise. The nonlinear mixing of the low-frequency 1/f noise increases the near carrier noise and changes the slope of the near carrier phase-noise from 1/ω2 to 1/ω3.

Typically the single-sideband phase-noise-to-carrier ratio for an ideal oscillator can be approximated by Leeson’s equation [27, 28] L(Δω)

2 1 kb T ⎛⎜ ω0 ⎞⎟ ⎟⎟ ⎜⎜ 4π Evib ⎝QΔω ⎟⎠

(12.32)

from which two important factors can be seen: (i) in practice the phase-noise reﬂects the competition between the mechanical energy Evib of the resonator and thermal noise kbT and (ii) the width of the resonance (1/Q) leads to a bandpass ﬁltering of the noise reducing the noise as the frequency difference to the carrier Δω increases. 233

Modeling in MEMS

PA R T I I

In a more generic form of Eq. 12.32 the noise voltage includes also the noise contribution from the ampliﬁer electronics. L(Δω)

un

2

uac

2

⎡⎛ ω ⎞2 ⎤ ⎢⎜ ⎥ 0 ⎟

⎟ 1 ⎜ ⎢⎜ ⎥ ⎟ ⎢⎣⎝ 2QΔω ⎟⎠ ⎥⎦

(12.33)

where uac is the signal voltage which is usually limited by the nonlinearities of the reference component (i.e., MEMS resonator) and un is the total noise voltage. From Eq. 12.33 the phase-noise can be seen to decrease as 1/ω2. However, for capacitively coupled devices Eq. 12.33 does not take into account the effect of aliasing of the 1/f noise due to the capacitive coupling. In the capacitive transduction gap, the 1/f noise is mixed with the signal voltage produced by the resonator giving an additional noise term. A more accurate equation for the dual side-band noise has been presented in [29] as L(Δω )

un

2

uac

2

Z0

US

ZSW U1

Z0 U2

ZL

UL

Fig 12.19 ● Micromechanical switch (impedance ZSW) connected in series with the transmission line. The transmission line (impedance Z0) is assumed to be perfectly matched to the source and load impedances, ZS and ZL, respectively.

ZS US

Z0

Z0 U1 ZSW

U2

ZL

UL

Fig 12.20 ● A micromechanical switch (impedance ZSW) connected in parallel (shunt) with the transmission line. The transmission line (impedance Z0) is assumed to be matched to the source and load impedances ZS and ZL, respectively.

.

2 ⎡ ⎢⎛⎜ ω0 ⎞⎟⎟ ⎜ ⎢⎜ ⎟ ⎢⎣⎝ 2QΔω ⎟⎠

⎛ 2 2 ⋅ ⎜⎜1 2 Γ Rm uac ⎜⎝

⎤ (12.34) 2 ωc ⎞ ⎟⎟ 1⎥ ⎥ Δω ⎟⎠ ⎥⎦

which leads to Eq. 12.33 using an aliasing factor 0. One can deduce from Eq. 12.34 that the phase-noise will decrease as 1/ω3 instead of 1/ω2 as is the case in Eq. 12.33 due to the mixing of low-frequency ampliﬁer noise present at the resonator input in the capacitive transduction gap. This can easily increase the near carrier noise by more than 30 dB [30]. It is evident from Eq. 12.34 that increasing the vibration amplitude does not help with aliasing of 1/f noise when it comes to the noise that is very close to the carrier frequency as it is produced by mixing of the thermal noise and the signal produced by the resonator. However, the noise ﬂoor becomes lower by increasing the vibration energy of the resonator. Therefore, if capacitive transduction is used to realize an oscillator, attention must be paid to minimize the low-frequency noise of the ampliﬁer or ﬁlter the noise prior to reaching the resonator.

12.11 RF-Properties RF-properties are studied from switching point of view. The intention of this chapter is to discuss some aspects related to the RF-properties, but to be in no way a comprehensive study of the RF-properties of MEMS-devices. A micromechanical switch is usually a MEMS-tunable capacitor that operates either in series or in shunt-mode. A series switch, (Figure 12.19) is used to shortcut (in onstate) or isolate (in off-state) the signal pathway between the input and the output in a transmission line. A shunt 234

ZS

switch (Figure 12.20) shortcuts the transmission line to the ground (in off-state) or isolates the transmission line from the ground (in on-state). In the following, some RFparameters are derived for both series and shunt switches. Again, the devices used are capacitively actuated even though the actuation principle does not signiﬁcantly affect the studied parameters. It should also be noted, that the following is true for a contact switch where in the downstate the switch makes a metal–metal contact between the terminals of the switch and in the up-state the terminals are separated from each other by an air gap showing signiﬁcant capacitance between the terminals. The RF-properties are usually characterized by such concepts as isolation (ISOL), insertion loss, (IL) and reﬂection. Actually both the isolation and insertion loss describe the forward power transmission, S21, of the switch, but the difference is that isolation refers to the case when the switch is in the off state and insertion loss is deﬁned when the switch is in the on state. The switch can be represented as a transmission line with impedance ZSW in Figure 12.19. The forward transmission can be calculated as S21

U2 2U L U1 US

(12.35)

Equation 12.35 assumes that the transmission line is matched to the source and load impedances or ZS ZL Z0. When the voltage at the load UL is calculated the forward power transmission gets the value S21

2

1 Z 1 SW 2Z0

2

(12.36)

Electrostatic and RF-Properties of MEMS Structures

When a MEMS-switch is in the down-state, the switch can be represented by the resistance RS of the metal–metal contact of the switch. With this, the insertion loss of the series switch becomes IL

(12.37)

In the up-state, the switch becomes a capacitor with a capacitance of CS and the isolation can be calculated as ISOL

up 2 S21

2

≈ (2ωCS Z0 )

2

1

1

Z0 2Z SW

2

(12.39)

ISOL

⎛ 2Z SW ⎞⎟2 ⎟ ≈ ⎜⎜⎜ ⎜⎝ Z ⎟⎟⎠

(12.40)

0

As previously stated, in the down-state, the switch can be represented with a resonant circuit; therefore, the impedance of a down-state switch can be written as Z SW

1 RP jω LP

jωCP

1 2π

1 LP CP

(12.43)

2

(12.44)

The insertion loss for the up-state switch is mainly the loss of the transmission line and, therefore, not determined by the switch itself. However, in addition 2 the power reﬂection S11 from the switch must be taken into account according to S11

2

1

1

2Z SW Z0

2

(12.45)

or 2

⎛ ωC Z ⎞2 ≈ ⎜⎜ U 0 ⎟⎟⎟ ⎜⎝ 2 ⎠

(12.46)

where CU indicates the capacitance of the up-state (or open) switch. In addition an important ﬁgure of merit in terms of switches, the so called cutoff frequency, fc, should be noted. It is usually determined by the resistance and capacitance of the switch as f

1 1 2π CS RS

(12.47)

(12.41)

where the resistance, inductance and capacitance denoted with a subscript P indicate the values for downstate switch (connected in parallel). The isolation of the switch can be calculated in three frequency ranges, determined by the LC series-resonant frequency of the switch fLC

down ISOL S21

⎪⎪⎧⎛ 2 ⎞2 ⎟⎟ , f � f ⎪⎪⎜⎜ LC ⎪⎪⎝⎜⎜ ωCP Z0 ⎠⎟⎟ ⎪⎪ 2 ⎪⎛ ⎪ 2R ⎞ ≈ ⎨⎜⎜⎜ P ⎟⎟⎟ , f fLC ⎪⎪⎜⎝ Z0 ⎟⎠ ⎪⎪ 2 ⎪⎛ ⎪⎪⎜ 2ωLP ⎞⎟⎟ , f � f LC ⎪⎪⎜⎜⎜ Z ⎟⎟ ⎝ 0 ⎠ ⎩⎪⎪

S11

By using the condition deﬁned as ZSW Z0 the isolation becomes down 2 S21

⎧⎪ 1 ⎪ , f � fLC ⎪⎪⎪ jωCP ⎪⎨ RP , f fLC ⎪⎪ ⎪⎪ jω LP , f � fLC ⎪⎪ ⎪⎩

and the isolation is the given by

(12.38)

From Eqs 12.37 and 12.38 it is clear that the isolation and the insertion loss of a contact switch can be determined by the contact resistance RS and the upstate capacitance CS of the switch. For a parallel (shunt) switch in Figure 12.20 the operation principle is opposite—when the switch is closed, it provides a large capacitance (usually in the pico farads) to the ground and the source signal is therefore shorted to the ground. When the switch is in the open-state, the capacitance to the ground is small (usually in the femto farads) and the switch does not affect the signal in the transmission line—therefore, the electrical equivalent of a capacitive shunt switch is a parallel capacitor in the up-state and a parallel connected series resonant circuit in the down-state. The forward power transmission is given in Eq. 12.39: S21

Therefore, the impedance of the switch becomes

Z SW

R ≈ 1− S Z0

down 2 S21

CHAPTER 12

(12.42)

The cutoff frequency is the frequency where the ratio of the up-state to the down-state impedance becomes unity. However, as one can deduce from Eq. 12.47 this deﬁnition of the cutoff frequency is actually valid for series switches and for MEMS shunt switches the cutoff frequency is not strictly applicable as the switch inductance usually limits the down-state performance before fc. Due to this and because the MEMS shunt switches usually result in acceptable isolation up to twice their LC resonance frequency, this limit or 2·fLC is used instead of fc [31]. 235

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Acknowledgments The authors would like to thank the following people for the collaboration in the research that has led among other things to the results discussed in this chapter: Nikolai

Chekurov, Osmo Vänskä, Ville-Pekka Rytkönen, Pekka Rantakari, Tuomas Lamminmäki, Tomi Mattila, Aarne Oja, Ari Alastalo, Heikki Seppä, Jyrki Kiihamäki, Hannu Kattelus and Ville Kaajakari.

References 1. M. Koskenvuori, I. Tittonen, A. Alastalo, IEEE Electron Device Lett. 28 (2007) 970–972. 2. N.W. Ashcroft, N.D. Mermin, Solid State Physics, Holt, Rinehart and Winston, Philadelphia, 1976. 3. M. Sze, Semiconductor devices, Second ed., John Wiley & Sons Ltd, 2002. 4. W. Mönch, Semiconductor Surfaces and Interfaces, Springer, 1995. 5. T. Durakiewicz, A. Arko, J.J. Joyce, D.P. Moore, S. Halas, Thermal work function shifts for polycrystalline metal surfaces, Surf. Sci. 478 (2001) 72–82. 6. H. Lüth, Surfaces and Interfaces of Solid Materials, Springer, 1998. 7. M. Koskenvuori, V.-P. Rytkönen, P. Rantakari, I. Tittonen, J. Phys. D: Appl. Phys. 40 (2007) 5558–5563. 8. A. Kärkkäinen, MEMS based voltage references, Helsinki University of Technology, VTT Publications, Espoo, 2006. 9. A. Kärkkäinen, N. Tisnek, A. Manninen, N. Pesonen, A. Oja, H. Seppä, Electrical stability of a MEMSbased AC voltage reference, Sens. Actuators, A 137 (2007) 169–174. 10. A. Kärkkäinen, S.A. Awan, J. Kyynäräinen, P. Pekko, A. Oja, H. Seppä, Optimized design and process for making a voltage reference based on MEMS, IEEE Trans. Instrum. Meas. 54 (2005) 563–566. 11. R.W. Herfst, H.G.A. Huizing, P.G. Steeneken, J. Schmitz, Characterization of dielectric charging in RF MEMS capacitive switches, IEEE Int. Conf. Microelectron. Test Struct. (2006) 133–136. 12. W. Merlijin van Sprengen, R. Puers, R. Mertens, I. de Wolf, A comprehensive model to predict the charging and reliability of capacitive RF MEMS switches, J. Micromech. Microeng. 14 (2004) 514–521.

236

13. V. Kaajakari, A.T. Alastalo, T. Mattila, Electrostatic transducers for micromechanical resonators: free space and solid dielectric, IEEE Trans. Ultrason. Ferroelectr. Freq. Control 53 (2006) 2484–2489. 14. I. Kuehne, A. Frey, D. Marinkovic, G. Eckstein, H. Seidel, Power MEMS—A capacitive vibrationto-electrical energy converter with built-in voltage, Sens. Actuators, A 142 (1) (2007) 263–269. 15. A.T. Alastalo, V. Kaajakari, Intermodulation in capacitively coupled microelectromechanical ﬁlters, IEEE Electron Device Lett. 26 (5) (2005) 289–291. 16. A.T. Alastalo, V. Kaajakari, Third-order intermodulation in microelectromechanical ﬁlters coupled with capacitive transducers, J. Microelectromech. Syst. 15 (1) (2006) 141–148. 17. R. Navid, J.R. Clark, M. Demirci, C.T.-C. Nguyen, Third order intermodulation distortion in capacitively driven CC-beam micromechanical resonators, Proceedings of Technical Digest 14th Int. IEEE Microelectromechanical Systems Conference, 2001, pp. 228–231. 18. M. Koskenvuori, I. Tittonen, A. Alastalo, Towards micromechanical radio: overtone excitations of a microresonator through the nonlinearities of the 2nd and 3rd order, IEEE J. Microelectromech. Syst. 17 (2) (2008) 363–369. 19. L. Yu-Wei, L. Sheng-Shian, R. Zeying, C.T.-C. Nguyen, Low phase noise array—composite micromechanical wine-glass disk oscillator, Proc. IEEE Trans. Electron Devices Meeting 2005 (IEDM 2005) (2005) 287–290. 20. T. Mattila, V. Kaajakari, J. Kiihamäki, A. Oja, H. Kattelus, H. Seppä, M. Koskenvuori, P. Rantakari, I. Tittonen, Silicon micromechanical

21.

22.

23.

24.

25.

26.

27.

28.

29.

resonators for RF-applications, Phys. Scr. T114 (2004) 181–183. V. Kaajakari, T. Mattila, A. Oja, J. Kiihamäki, H. Seppä, Square-extensional mode single-crystal silicon micromechanical resonator for low phase noise oscillator applications, IEEE Electron Device Lett. 25 (2004) 173–175. P. Rantakari, V. Kaajakari, T. Mattila, J. Kiihamaki, A. Oja, I. Tittonen, H. Seppä, Low noise, low power micromechanical oscillator, Proceedings of Technical Digest 13th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers’05), 2005, pp. 2135–2138. M. Koskenvuori, T. Mattila, A. Häärä, J. Kiihamäki, A. Oja, H. Seppä, I. Tittonen, Long-term stability of single-crystal silicon microresonators, Sens. Actuators, A 115 (2004) 23–27. V. Kaajakari, J. Kiihamäki, A. Oja, S. Pietikäinen, V. Kokkala, H. Kuisma, Stability of wafer level vacuum encapsulated single-crystal silicon resonators, Sens. Actuators, A 130–131 (SPEC. ISS.) (2006) 42–47. B. Kim, R.N. Candler, M.A. Hopcroft, M. Agarwal, W.-T. Park, T.W. Kenny, Frequency stability of wafer-scale ﬁlm encapsulated silicon based MEMS resonators, Sens. Actuators, A 136 (1) (2007) 125–131. ETSI TS 100 910 V8.20.0: Digital cellular telecommunications system (Phase 2 ); Radio Transmission and Reception (3GPP TS 05.05 version 8.20.0 Release 1999), 1999. B. Leeson, A simple model of feedback oscillator noise spectrum, Proc. IEEE 54 (1966) 329–330. T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998. V. Kaajakari, J.K. Koskinen, T. Mattila, Phase-noise in capacitively coupled

Electrostatic and RF-Properties of MEMS Structures micromechanical oscillators, IEEE Trans. Ultrason. Ferroelectr. Freq. Control 52 (2005) 2322–2331. 30. V. Kaajakari, J. Rantakari, K. Koskinen, T. Mattila, J. Kiihamaki,

M. Koskenvuori, I. Tittonen, A. Oja, Low noise silicon micromechanical bulk acoustic wave oscillator, Proc. IEEE Ultrason. Symp. 2005 (2005) 1299–1302.

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31. G. Rebeiz, RF MEMS Theory, Design and Technology, John Wiley & Sons Inc., Hoboken, New Jersey, 2003.

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13

Chapter Thirteen

Optical Modeling of MEMS Timo Aalto and Juuso Olkkonen VTT Technical Research Centre of Finland, Espoo, Finland

Optics is related to the processing of silicon MEMS in many ways. For example, photolithography is used to pattern MEMS structures, while ellipsometry and optical microscopy are used to characterize them. However, the use of optics in the fabrication or characterization of nonoptical MEMS is not discussed in this chapter. Instead, we concentrate on the theory and modeling of optical MEMS structures. A typical example of optical MEMS (or micro-optical-electromechanical systems, MOEMS) is a movable mirror on silicon. However, we extend the concept of optical MEMS to also cover static optical structures that are realized on silicon with similar processing methods as those used in the fabrication of movable MEMS structures. Such structures include static mirrors and lenses, optical thin ﬁlm stacks, gratings, waveguides and pixel detectors. Chapter 13 is divided into three main parts. In Section 13.1 we brieﬂy review the optical properties of silicon and some other materials commonly used in MEMS. Next, in Section 13.2, we summarize the fundamental theory of optics to create the necessary background for understanding the practical implementation of optical modeling of MEMS. Finally, the optical modeling methods for silicon-based MEMS are presented in Section 13.3 and illustrated with practical application examples. The examples also serve to provide an overview of typical optical components realized with MEMS technology. Due to the complexity of rigorous optical theory, the vast number of modeling methods, and the large variety of optical applications somehow related to MEMS only a coarse overview of the optical modeling methods for MEMS can be provided here. To get a deeper understanding of the underlying theory, modeling methods

or applications we encourage the reader to resort to the speciﬁc books written about topics such as the fundamentals of optics and photonics [1, 2], optical properties of silicon and other materials [3], numerical modeling [4–9], MOEMS [10], integrated optics [11–13] and silicon photonics [14, 15].

13.1 Optical Properties of Silicon and Related Materials In this chapter we review the most relevant optical properties of silicon and the ways to manipulate them. The optical properties of some other materials commonly used in optical MEMS, such as silicon dioxide and silicon nitride, are also brieﬂy reviewed. We concentrate on the bulk properties, but one should take into account that thin ﬁlms and microstructures, such as waveguides, may have somewhat different properties depending on their process parameters, dimensions, geometry and stress distribution. The two fundamental optical parameters considered here for any material are the refractive index n and the extinction coefﬁcient k. Together they deﬁne the complex refractive index nc = n + ik. The real (1) and imaginary (2) part of the complex dielectric constant (c) are linked to n and k via 2

εc = ε1 + iε2 = ( n + ik)

(13.1)

Absorption coefﬁcient α provides a simple factor eαz that represents intensity attenuation when light 239

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propagates along the z-axis. It is linked to the extinction coefﬁcient k and the free space wavelength (λ0) of light via α = 4πk λ 0

Most non-metallic solids have two main absorption mechanisms, namely, electronic transitions and lattice vibrations. When the wavelength is so short that the photon energy exceeds the electronic bandgap of the material, the photons can excite electronic transitions across the bandgap and the absorption becomes very large. On the other hand, smaller photon energies can efﬁciently excite lattice vibrations. Between these wavelength regions of high absorption there is typically a relatively wide spectral range where both absorption mechanisms are negligible and the material is optically transparent. However, some smaller absorption can also be seen in this region because of material impurities, lattice defects, multiphonon absorption or phonon-assisted electrical transitions. In case of high optical intensity some nonlinear multiphoton absorption processes can also be seen.

(13.2)

The impact of any other parameters is evaluated through their inﬂuence on n and k. Manipulation of light propagation is most often based on the tuning of either one of these fundamental parameters in the medium where light propagates. The wavelength dependencies of n and k are related to each other via the Kramers–Kronig relation [1] (p. 179), which enables the calculation of chromatic dispersion (i.e., wavelength dependence of n) from a measured absorption spectrum. Sometimes it is convenient to express the absorption α in decibels per centimeter (dB/cm), especially when the absorption is very small and light propagates a long distance inside the material. The conversion from the standard SI units (1/m) can be made with the formula α(dB cm ) = 10 ln (10) × α(1 m) =

k × 0.4π ⎡λ0 ln (10)⎤ ⎣ ⎦

13.1.1 Optical Properties of Silicon The n and k of silicon are plotted as a function of wavelength in Figure 13.1. In the near-IR region, where Si is transparent, the monotonic reduction of n between 3.6 and 3.4 as function of λ can be approximated with the Sellmeier-type dispersion formula

(13.3)

In decibel units the propagation of length L in the material of device 1 produces a total absorption loss of α1 αL(dB). The transmission coefﬁcient T for the device is simply the opposite number of the loss (T1 α1). The total optical loss of successive components can be calculated by simply summing up the individual losses (αtotal α1 α2 …). In standard SI units the transmission of device 1 is T1 eαL and the total transmission through successive components is obtained by multiplying (Ttotal eα1α2α3…).

8 6

0.001

n 4 3

0.0001

2

0.00001

1

(a)

0.1 dB/cm 1

10

Wavelength (μm)

+

0.00810461λ12 λ 2 − λ12

(13.4)

3.55

0.01 Sellmeier fit

0.001

0.1 3.5

0.01

5

λ

2

3.6

1

10 dB/cm

0.939816

where λ and λ1 1.1071 μm are given in micrometers. Bandgap absorption becomes strong at approximately 1.2 μm. Thus, silicon is opaque at λ 1.2 μm and not a suitable transmission medium for visible light, for example. For near infrared wavelengths between

10 Sellmeier fit

7

0 0.1

n 2 = 11.6858 +

k

0.0001

n 3.45 3.4

0.00001 10 dB/cm

3.35

0.000001

0.1 dB/cm

0.0000001 100

0.000001 0.0000001 0.00000001

3.3 (b)

k

1 1.5 2 2.5 3 3.5 4 4.5 5 Wavelength (μm)

Fig 13.1 ● Refractive index n and extinction coefﬁcient k of bulk silicon as a function of wavelength (data taken from literature [3]). The two ﬁgures show different parts of the wavelength spectrum. The circles correspond to the analytical dispersion formula based on the Sellmeier coefﬁcients. A vertical line is drawn at 1.2 μm to illustrate the edge of the transparent region. The other straight lines correspond to the 0.1 and 10 dB/cm absorption limits.

240

Optical Modeling of MEMS

approximately 1.2 and 4 μm the absorption of undoped silicon is negligible (0.01 dB/cm). Above 4 μm the absorption again starts to increase due to multiphonon absorption. The wavelength range between approximately 6 and 20 μm includes several multiphonon absorption peaks that partially overlap with each other, as well as some absorption peaks caused by oxygen and carbon impurities. At low temperatures the multiphonon absorption peaks become somewhat smaller and narrower. Between approximately 20 and 100 μm the absorption is fairly constant, so that k increases approximately linearly with λ. The absorption of silicon is strongly dependent on doping. In microelectronics and MEMS it is often preferred to use doped silicon that has lower resistivity than undoped silicon. However, the free carriers (electrons and holes) in doped silicon absorb light, which makes undoped silicon the preferred choice for optical MEMS if light should propagate through silicon. The relationship between resistivity and absorption is illustrated in Figure 13.2.

13.1.2 Manipulation of Silicon’s Optical Properties There are many ways to manipulate the optical properties of silicon. Often the simplest way to change n is heating. The thermo-optical constant [18] of 1.86.104 K1 and the thermal conductivity [16] (p. 54) of 1.41 Wcm1K1 are both quite high in silicon, which enables very efﬁcient and relatively fast thermal tuning of the refractive index.

CHAPTER 13

As explained before (see Figure 13.2), absorption in silicon depends on doping and the related density of free carriers. One can therefore change the absorption by electrically injecting free carriers into silicon. This also induces a refractive index change that can be exploited if the density of free carriers is so low that all light is not absorbed. These effects are commonly used to integrate amplitude and phase modulators into silicon waveguides. This is a much faster process than thermal tuning and with small silicon waveguides modulation frequencies of several GHz have been demonstrated. The optical properties of silicon can also be tuned with an externally applied electric or magnetic ﬁeld, or even with the light itself. The linear electro-optic (Pockels) effect in silicon is normally negligible. However, by breaking the crystal symmetry with stress, for example, it is possible to somewhat tune the refractive index with an externally applied electric ﬁeld. However, the nonlinear optical effects [19] are much stronger and more commonly used. When the optical intensity in silicon becomes sufﬁciently high, the two-photon absorption starts to cause losses or cross-amplitude modulation. Also, light propagating in silicon can generate free carriers, which then cause free carrier absorption and refractive index changes. These effects lead to cross-amplitude modulation and cross-phase modulation. If light propagating in silicon has high intensity and at least two frequency bands, then new frequency bands can be generated around them via four wave mixing. Finally, the interaction of the photons with the phonons of the silicon lattice causes Raman scattering, which enables the realization of Raman lasers and Raman ampliﬁers.

13.1.3 Optical Properties of Other Materials Commonly Used in Optical MEMS

Figure 13.2 ● Absorption of bulk silicon at 1550 nm wavelength as a function of resistivity, based on the approximation that the free carrier density is equal to the dopant density. The two curves correspond to P and B doped silicon, also known as p and n type silicon, respectively. The data is collected from [16] (Figure 1.14) and [17].

In addition to silicon, many other materials are used in optical MEMS. Some of the most important materials are crystalline silicon dioxide (SiO2, quartz), amorphous silicon dioxide (SiO2, fused silica), silicon-rich silica (SiOx), silicon nitride (Si3N4), silicon oxynitride (SiOxNy), and PyrexTM. Typical unwanted or intentional impurities in silica are hydrogen, boron, sodium, potassium, and lead. The transparent region of quartz and pure silica reaches from UV to near IR wavelengths. In practice, however, the impurities cause several absorption peaks. Thus, proper deposition and processing methods must be selected based on the wavelength range of the given application. For silicon dioxide, the n and k spectra are illustrated in Figure 13.3. For other materials the reader can ﬁnd corresponding data, for example, from Ref. [3].

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n

2.75 2.5 2.25 2 1.75 1.5 1.25 1 0.75

10

0.1 Quartz (ordinary ray)

k 0.01

Glass

Glass

0.001 10 dB/cm

0.0001

0.5 0.1 (a)

Quartz (ordinary ray)

1

1 Wavelength (μm)

10

0.00001 0.1

1

10

Wavelength (μm)

(b)

Figure 13.3 ● Refractive index n (a) and extinction coefﬁcient k (b) of silicon dioxide as a function of wavelength. The data are taken from literature [3] separately for crystalline SiO2 (quartz) and amorphous SiO2 (glass).

13.2. Theoretical Background

ni

Before presenting any details of optical MEMS structures or their modeling methods, we shall ﬁrst summarize the fundamentals of the related optical theory. By dropping off one approximation after another we proceed from simple ray optical principles towards full-vectorial ﬁelds and quantum optics. To simplify the discussion we assume that the absorption of the propagation medium is negligible, unless otherwise stated.

ni

nt

qr

qt

qi

nt qt

qr qi

nt

>

ni

nt

<

ni

Figure 13.4 ● Reﬂection and refraction of optical rays at a planar interface separating two transparent media characterized by refractive indices ni and nt. When nt ni, the refracted ray bends toward the surface normal, while for nt ni, the refracted ray bends away from the normal.

13.2.1 Geometrical Optics The simplest model for representing light propagation is called geometrical optics. It describes light as rectilinear rays and is therefore also known as ray optics. Light propagates along the rays with a velocity of c/n, where c is the velocity of light in vacuum (sometimes denoted with c0) and n is the refractive index that describes how light slows down in a given propagation medium. For vacuum n 1 and for most optically transparent materials 1 n 4. The duration of light propagation over a physical distance of L is nL/c, where nL is the corresponding optical path length. For nonuniform medium the propagation time is calculated by the integral 1 n( x, y, z)dL c ∫L

(13.5)

Even in geometrical optics, it is useful to deﬁne the concept of wavelength (λ). In arbitrary medium the socalled “local wavelength” is λ/n, but here we refer by “wavelength” to the vacuum wavelength (λ0), which is inversely proportional to the frequency f of light ( f c/λ0). Geometrical optics is only accurate when the optical structures that inﬂuence light propagation are much larger than the wavelength. A human eye can detect wavelengths that are between approximately 400 and 700 nm. This wavelength range covers all the colors from 242

violet to red and corresponds to so-called visible light. However, the same wavelength spectrum extends from picometers (1012 m) to thousands of kilometers. This chapter concentrates on the so-called optical spectrum which covers the ultraviolet light (10–400 nm), visible light (400–700 nm) and near infrared light (0.7–3 μm). A typical modeling task in geometrical optics is the refraction of a ray at a step-like material interface. This is illustrated in Figure 13.4 and represented by the Snell’s law nisin(θi ) = nt sin(θi )

(13.6)

where θi is the angle of incidence and θt is the refraction angle. The angles are determined with respect to the normal of the material interface. Light originates from material with refractive index ni and refracts (or transmits) into material with refractive index nt. The colorseparating operation of a prism (Figure 13.5) is based on the wavelength dependence of n. Reﬂection of the rays from a step-like material interface is another typical modeling task in geometrical optics. The reﬂection angle θr equals the angle of incidence (θi θr), as illustrated in Figure 13.4. Reﬂections from planar and elliptical mirrors are illustrated in Figure 13.6. When light enters the material interface from the side of the higher refractive index (ni > nt) and the angle of incidence is larger than the critical angle

Optical Modeling of MEMS

CHAPTER 13

the coupling of light into the waveguide. Note that if lateral dimensions of the waveguide core are in the same scale with the wavelength of incident light, coupling efﬁciency must be determined by calculating the overlap integral between the incident ﬁeld and the modes supported by the waveguide. Determination of the waveguide modes is presented in the Section 13.3.4.

13.2.2 Matrix Optics Figure 13.5 ● Wavelength-dependent refraction in a prism made of dispersive material. The different colors of white light are refracted to different angles.

Figure 13.6 ● Reﬂections from a planar mirror and an elliptical mirror. Rays reﬂected from the planar mirror appear to originate from a point behind the mirror. Rays originating from one focus point of the elliptical mirror are reﬂected towards the other focus point.

nair = 1

ncladding ncore θc

θa

Figure 13.7 Total internal reﬂection (θr ≥ θc) and acceptance angle (θa) of an optical waveguide (or ﬁber). The acceptance angle and the critical angle (θc) correspond to the case when the refraction angle is 90°. ●

θc = arcsin ( nt / ni )

(13.7)

light experiences total internal reﬂection and Eq. 13.6 is no longer valid. An example of total internal reﬂection is the lossless light propagation in optical waveguides illustrated in Figure 13.7. The acceptance angle θa and numerical aperture (NA) deﬁned by NA = sin (θa ) =

2 2 ncore − ncladding

(13.8)

describe the ray optical situation where light coupled through the waveguide input facet propagates losslessly along the waveguide at the limit (θc) of total internal reﬂection between the waveguide core and cladding. For a cylindrical waveguide core with a large radius R ( λ) this is a good approximation for evaluating

Often light is tightly conﬁned around the optical axis of the system (mirrors, lenses, etc.) so that the distance (y) and angle (θ) of the rays with respect to the optical axis is small. Then one can apply the so-called paraxial approximation where sin(θ ) ≈ tan(θ ) ≈ θ and cos(θ ) ≈ 1. This signiﬁcantly simpliﬁes the modeling of light propagation as the Snell’s law is converted from a trigonometric equation (Eq. 13.5) into a linear equation niθi = nt θt. The transfer functions of lenses and many other optical elements can then also be linearized, which enables the analysis of cascaded optical elements with numerically efﬁcient matrix methods. Matrix optics is based on the use of paraxial approximation in ray optics. It is commonly used in the design of optical systems, especially in free space optics. Each ray is described as a 2 1 vector that determines its distance (y) and angle (θ) with respect to the optical axis. The impact of an optical element, such as a lens, on the ray is obtained by multiplying the 2 1 vector with the characteristic 2 2 matrix of the element. The matrix elements A, B, C and D in the matrix equation ⎡ y2 ⎤ ⎡ A B ⎤ ⎡ y1 ⎤ ⎢ ⎥ = ⎢ ⎥⎢ ⎥ ⎢ θ2 ⎥ ⎢ C D⎥ ⎢ θ1 ⎥ ⎣ ⎦⎣ ⎦ ⎣ ⎦

(13.9)

are real numbers fully describing the optical element within the paraxial approximation. The subscripts 1 and 2 refer to the rays before and after the element, respectively. The matrices of some common optical elements are given in Table 13.1.

13.2.3 Scalar Wave Model With geometrical optics it is difﬁcult to accurately explain and model such phenomena as interference and diffraction, or to predict the exact amount of light reﬂected from a material interface. Therefore, one often needs to take into account the wavelike and vectorial characteristics of light. Light propagation in isotropic and nonmagnetic medium is rigorously governed by Maxwell’s equations ∇ × E(r, t ) = −μ0 ∇ × H(r, t ) = ε

∂H(r, t ) ∂t

∂E(r, t ) ∂t

(13.10)

(13.11) 243

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PA R T I I

Table 13.1 Characteristic matrices of some common optical elements

⎡ 1 L⎤ ⎥ M⎢ ⎢0 1⎥ ⎣ ⎦

Propagation for length L in homogeneous material

⎡ 1 ⎢ M⎢ 1 ⎢ ⎢ f ⎣

⎡1 L ⎤ ⎥ M⎢ ⎢ 0 ni / nt ⎥ ⎣ ⎦

Refraction at a planar material interface

⎡ 1 0⎤ ⎥ M⎢ ⎢ 0 1⎥ ⎣ ⎦

Refraction at a spherical material interface (positive/negative radius R for convex/concave surface)

⎡1 ⎢ M ⎢2 ⎢ ⎢⎣ R

⎡ 1 ⎢ M ⎢ nt ni ⎢ ⎢ nt R ⎣

L⎤ ⎥ ni ⎥ ⎥ nt ⎥⎦

∇ × εE(r, t ) = 0

(13.12)

∇ × μ0 H(r, t ) = 0

(13.13)

Here, E is the electric ﬁeld, with rectilinear components (Ex,Ey,Ez), H is the magnetic ﬁeld with components (Hx,H y,Hz), μ0 is the permeability of free space, and ε = ε0 εc, where ε0 is the permittivity of free space, and εc is the complex dielectric constant (see Eq. 13.1). E and H are functions of both position r = ( x, y, z) and time t. Taking the curl of both sides of Eq. 13.10 and then substituting Eq. 13.11, one obtains ∇2E − μ0 ε

∂ 2E ∂t

2

⎛ ∇ε ⎞⎟ = −∇ ⎜⎜E × ⎟ ⎝⎜ ε ⎟⎠

(13.14)

where ∇2 = ∂ 2 / ∂x 2 + ∂ 2 / ∂y 2 + ∂ 2 / ∂z2 is the Laplacian operator. When permittivity changes in the spatial region are small, the term ∇ε / ε is so small that it can be ignored and Eq. 13.14 reduces to its homogeneous form ∇2E − μ0 ε

2

∂ E ∂t 2

=0

(13.15)

Note that an exactly similar equation can be derived for the magnetic ﬁeld H. In Cartesian coordinates, Laplacian operator breaks into three uncoupled components, and one obtains the scalar wave equation 2 2 ⎤ ⎡ ⎢∇2 − ⎜⎛ n ⎟⎟⎞ ∂ ⎥ U (r, t ) = 0 ⎜ ⎢ ⎜⎝ c ⎠⎟ ∂t 2 ⎥ s ⎣⎢ ⎦⎥

(13.16)

where U s (r, t ) represents any of the electric or magnetic ﬁeld components, n = ε / ε0 , and c=

244

1 ε0 μ0

(13.17)

0⎤ ⎥ ⎥ 1⎥ ⎥ ⎦

Angular change when light propagates through a thin lens

Reﬂection from a planar mirror

0⎤ ⎥ ⎥ 1⎥ ⎥⎦

Reﬂection from a spherical mirror (positive/negative radius R for convex/concave mirror)

It can be noted here that the intensity (I) of light is proportional to the second power of U s (r, t ), optical power ﬂowing through an area A is obtained by integrating the intensity over the area A and optical energy is obtained by integrating the power over a given time. The solutions to the wave equation are called wavefunctions and they are often presented in complex form to simplify the calculations. There are typically an inﬁnite number of solutions because any linear combination of two solutions is also a solution. By combining various elementary solutions, known as eigenmodes, one can represent any possible solution that fulﬁlls the wave function. Thus, the mathematical analysis of the scalar wave equation concentrates on the eigenmodes. Monochromatic waves with harmonic time dependency represent an important class of solutions to the scalar wave equation. They are represented in the form U s (r,t ) = U(r )e−jωt

(13.18)

where U(r ) is the complex amplitude of the wave function and ω is the angular frequency. By inserting Eq. 13.18 into Eq. 13.16 one obtains the Helmholtz equation

(∇2 + k2 )U = 0

(13.19)

where k= n

ω 2π = n = nk0 c λ0

(13.20)

is the wavenumber and k0 is the free space wavenumber. To avoid confusion it should be noted that the wavenumber shares a common symbol with the extinction coefﬁcient. The two mathematically simplest solutions to the Helmholtz equation are the inﬁnitely wide scalar plane wave (U(r ) = A exp[jk × r]) propagating along

Optical Modeling of MEMS

CHAPTER 13

Figure 13.8 ● Wavefronts and amplitudes of three elementary scalar wave functions: Plane wave, spherical wave and Gaussian beam. Optical axes are presented by black arrows and the width W(z) of the Gaussian beam is shown by black lines. Wavefronts are illustrated by surfaces having a constant color.

the wave vector k = ( kx , ky , kz ) with the amplitude A, and a spherical wave (U(r ) = A exp[ jkr]/ r) originating from a point-like light source. Wavefronts (surfaces having the same phase) and amplitude distributions of these wave solutions are illustrated in Figure 13.8. The paraxial approximation introduced in Section 13.2.2 can also be applied in scalar wave optics. Then the complex amplitude is presented in the form U (r) = U env (r) exp[ jn0 k0 z]

(

)

⎡ W0 ρ2 ⎤ exp ⎢⎢− 2 ⎥⎥ W ( z) ⎢⎣ W ( z)⎦⎥ (13.23) 2 ⎤ ⎡ ρ exp ⎢⎢−ikz − ik + iζ ( z)⎥⎥ 2R ( z) ⎣⎢ ⎦⎥

U ( z,ρ ) = A0

(13.21) W ( z) = W0

where U env (r) is the complex envelope of the wave function. The envelope describes the deviation of the wavefunction from a harmonic plane wave propagating along the z-axis with propagation constant n0 k0 . In the so-called slowly varying envelope approximation (SVEA), it is assumed that U env changes only little within the spatial distance of one wavelength. Then the Helmholtz equation can be simpliﬁed into the paraxial Helmholtz equation ∂U env 1 ⎡ 2 n0 − n 2 k02 − ∇2T ⎤⎥ U env = ⎢ ⎣ ⎦ ∂z i2n0 k0

intensity radius W0. The other ﬁeld parameters can be determined from the equations

(13.22)

where ∇2T = ∂ 2 / ∂x 2 + ∂ 2 / ∂y 2 is the transverse Laplacian operator. In a medium with a refractive index n0, (n02 − n 2 )k02 = 0, which further simpliﬁes the paraxial Helmholtz equation. A particularly important solution to the paraxial Helmholtz equation is a Gaussian beam that can be seen as an intermediate solution between the planar and spherical waves. In general a Gaussian beam can have different width in the x and y direction. However, the following analysis is simpliﬁed by assuming that the Gaussian ﬁeld propagating in free space is cylindrically symmetric around the z-axis, so that the x and y coordinates can be replaced by the radial ρ coordinate (ρ2 x2 y2). Then the ﬁeld distribution of a Gaussian beam focused at the origin (z ρ 0) is ultimately deﬁned by only two parameters, the maximum amplitude A0 and the 1/e2

⎞⎟2 ⎟⎟ ⎟ 0⎠

⎛z 1 + ⎜⎜⎜ ⎜⎝ z

(13.24)

⎡ ⎛ z ⎞2 ⎤ R ( z) = z ⎢⎢1 + ⎜⎜ 0 ⎟⎟⎟ ⎥⎥ ⎜⎝ z ⎠ ⎥ ⎢⎣ ⎦

(13.25)

⎛z⎞ ζ( z) = arctan⎜⎜⎜ ⎟⎟⎟ and ⎜⎝ z0 ⎟⎠

(13.26)

z0 =

π 2 W0 λ

(13.27)

The Rayleigh range z0 deﬁnes the depth of focus (2z0) where the beam width remains close to the minimum width (W ( z) ≤ 2W0). The far ﬁeld divergence angle of a Gaussian beam in radians is θ0 =

λ πW0

(13.28)

which indicates that the smaller the waist (or spot size, 2W0) the larger the divergence angle. Thus, highly collimated beams need to have a large spot size. The radius of curvature (R) of the phase fronts reaches its minimum at z z0, and for the far ﬁeld R(z)z. A Gaussian beam is illustrated in Figure 13.8. The superposition of two or more waves causes interference. Waves with the same or opposite phases produce constructive or destructive interference, respectively. 245

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Interference depends on the spatial and temporal coherence of the waves. In MEMS it is exploited in, e.g., optical thin ﬁlm coatings and various intererometer conﬁgurations. The inﬂuence of obstacles or other inhomogeneities of the propagation medium to light propagation is called diffraction. It is pronounced when the size of the diffracting structures is in the order of the wavelength. In optical MEMS diffraction occurs when light propagates through a small aperture or impinges on a diffractive grating, for example. Diffraction is discussed further in the following chapter.

13.2.4 Fourier Transform in Optics Fourier transform is based on Fourier series that represents periodic functions as an inﬁnite sum of sines and cosines. This kind of decomposition is possible due to orthogonality properties of sine and cosine functions. The Fourier transform is a generalization of complex Fourier series in the limit as the period approaches inﬁnity. The concept of Fourier transformation is further illustrated in Figure 13.9. In practice, Fourier transformation is calculated using the discrete Fourier transform (DFT) that inherently assumes that the input signal is periodic and spectral resolution of the transformation is determined by the sampling step and the number of sample points. If the amplitude of the input signal starts from zero and ends to zero, spectral resolution can be increased adding zero sample points to the end or beginning of the signal increasing the number of sample points. This operation is commonly known as zero padding. Fourier transformation from the time to the frequency domain is typically utilized in analysis of spectral content of short optical pulses or interferograms produced, e.g., in Fourier transform spectroscopy. In optical design of wavelength selective interference ﬁlters, multiplexers, demultiplexers and dielectric mirrors to

be employed with short optical pulses, Fourier transformation is typically used to decompose the incident time domain pulse into monochromatic waves. When e.g., an interference ﬁlter is designed, the ﬁlter response for each monochromatic wave can be then readily calculated using the standard transfer matrix formalism (see Section 13.3.2). The transmitted time domain pulse can be reconstructed from the transmitted monochromatic waves using the inverse Fourier transform. The reﬂected pulse can be treated in the similar manner. The transformation from the spatial domain (x,y) to the spatial frequency domain ( kx , ky ) is utilized strongly in Fourier optics. One of the main results in Fourier optics is the plane wave spectrum presentation of the electromagnetic ﬁeld. Applying Fourier analysis to the Helmholtz Eq. 13.19 (for details, see Section 1.6.1 in Ref. [20]), it can be seen that any electromagnetic ﬁeld component can be represented as a weighted superposition of plane wave solutions: U( x, y ) =

+∞

∫ ∫−∞

(13.29) where U( x, y ) can be electric ﬁeld or magnetic ﬁeld component, and kx and ky are wavenumbers along the x- and y-directions, respectively. The plane wave spectrum A( kx , ky ) (also known as the angular spectrum) is obtained from A( kx , ky ) =

+∞

1 2

(2π ) dxdy

A( kx , ky )exp[−j( kx x + ky y )] (13.30)

Amplitude

Original data Frequency spectrum

t Approximation

∫ ∫−∞

That is, there is a clear Fourier transform relationship between the ﬁeld and its plane wave content. The plane wave spectrum method is extremely useful, for example, in propagation of electromagnetic ﬁelds in a homogenous medium. This is due to the fact that a plane wave can

Field (real) Field (real)

A( kx , ky )exp[ j( kx x + ky y )]dkx dky

t f

Figure 13.9 ● Fourier transformation of an arbitrary function of time (left) into the corresponding frequency spectrum (right). Five examples of the calculated harmonic functions are shown in the middle plot, including the constant term, two low-frequency components and two medium-frequency components. The original data are also compared with an approximation provided by the eleven harmonic functions encircled in the frequency spectrum. The Fourier transformation was realized with DFT applied to 128 data points.

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be propagated over the distance z0 in the z-direction by simply multiplying its complex amplitude by a factor exp[ jkz z0 ], where kz = k2 − kx2 − k2 . Therefore, the y ﬁeld U( x, y ) can be propagated from the plane z 0 to the observation plane z z0 by the integral U( x, y, z0 ) =

+∞

∫ ∫−∞ U(kx , ky )e

jkz z0

exp[ j( kx x +ky y )]

dkx dky

(13.31)

Although the integral extends from to , the limits can be changed to k to k if z0 is larger than few wavelengths. Elements in the plane wave spectrum with kx2 + k2y > k2 are evanescent waves that do not contribute the propagated ﬁeld after few wavelengths away from the plane z 0. It should be noted that when integral (13.31) is numerically calculated using DFT, the calculation grid should be so wide that the ﬁeld amplitude is and stays zero on the grid boundaries. Otherwise, due to the initial assumption of DFT that the transformed signal is periodic, ﬁelds from adjacent periods start to interfere with each other. The plane wave spectrum method is illustrated in Figure 13.10. It can be applied to calculate the free space propagation of light in optical MEMS structures, such as those illustrated in Figure 13.11. More information on Fourier optics and the plane wave spectrum can be found, for example, from Refs [21–23].

CHAPTER 13

is actually electromagnetic radiation that can only be described accurately as the combination of electric (E ) and magnetic (H) vector ﬁeld. The simultaneous analysis of all six vector components (Ex , Ey , Ez , Hx , H y , Hz ) according to Maxwell’s Equations 13.10–13.13 is called vectorial wave optics or electromagnetic optics. For simplicity we assume here that the propagation medium is isotropic and homogeneous, unless otherwise indicated. The ﬂow of energy associated with the propagation of the electromagnetic ﬁeld is presented by the time averaged Poynting vector S = 1 / 2Re E × H* , which is perpendicular to both E and H . For a harmonic plane wave propagating in a medium of refractive index n the amplitude ratio of E and H is [1]

{

}

μ0 |E| = ε0 |H|

(13.32)

where μ0 and ε0 are the vacuum permeability and vacuum permittivity, respectively. They are linked to the speed of light via Eqs 13.17.

Silicon top surface

Fiber

13.2.5 Electromagnetic Optics Lenses

Many optical simulation tasks in MEMS can be carried out by considering light as a simple scalar ﬁeld. However, the explanation of certain optical phenomena requires one to take into account the fact that light

(a)

Silicon trench

(b) Lens

Movable SOI part

Fiber Si substrate DFT{U(x,y)}

Fiber

U(x,y)

(c) A(kx,ky)

Figure 13.10 Illustration of the plane wave spectrum presentation. A ﬁeld U( x, y) can be represented as a sum of plane waves with different directions k , k , k2 − k2 − k2 ●

(

x

y

0

x

y

and amplitudes A( kx , ky ). Here, the length of a plane wave direction arrow is proportional to its amplitude. The color ﬁgure can be viewed on the book’s companion website (http://www. elsevierdirect. com/companion/9780815515944).

)

Movable SOI part

(d)

Figure 13.11 ● Optical MEMS structures with movable mirrors realized into the SOI layer and lensed optical ﬁbers glued into etched trenches. (a) Reﬂection (RVOA) and (b) transmission-type (TVOA) variable optical attenuators. (c) 1 2 optical switch. (d) Cross-sections along the optical path (up), for the ﬁber (left) and for the movable MEMS bar (right). Light propagation between the ﬁbers, including the reﬂection or blocking of the light by the movable MEMS structures, can be calculated with the plane wave spectrum method.

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The time-averaged intensity of a plane wave can be calculated from the scalar amplitude (E0,H0) of either E or H as I =

ε 1 1 1 E0 H0 = n 0 E02 = ncε0 E02 μ0 2 2 2

cμ 1 μ0 2 = H0 = 0 H02 2n ε0 2n

(13.33)

In an arbitrary medium ε0 and μ0 are replaced by permittivity ε and permeability μ. When light propagates in dielectric and optically transparent materials one can generally assume that ε ≈ n 2ε0 and μ ≈ μ0. Electromagnetic optics enables the detailed analysis of polarization. In free space optics, polarization is deﬁned as the orientation of the electric ﬁeld (E) with respect to the plane of incidence that is typically spanned by the wave vector and the z-axis (see Figure 13.15). A plane wave is said to be transverse electric (TE) polarized when the electric ﬁeld vector is perpendicular to the plane of incidence. When the electric ﬁeld vector resides in the plane of incidence and the magnetic ﬁeld vector is perpendicular to the plane of incidence, the plane wave is said to be transverse magnetic (TM) polarized. A plane wave is not necessarily TE or TM polarized, but its polarization state can be expressed as a combination of the TE and TM ﬁelds, taking into account their amplitude and phase differences. In general the resulting polarization is elliptical, as illustrated in Figure 13.12. Linear polarization (Figure 13.12) is obtained when the TE and TM

polarized ﬁeld components have the same (0°) or opposite (180°) phase, or if only one of them is excited. If the TE and TM ﬁelds have identical amplitudes and 90° phase difference the total ﬁeld forms circular polarization (Also shown in Figure 13.12). When light propagates in a waveguide as coupled to a waveguide mode, slightly different naming conventions are used for TE and TM polarizations than with a plane wave. In cylindrical circular waveguides, modes having all magnetic ﬁelds transverse to the direction of propagation ˆz, i.e., Hz = 0 , are called TM polarized, and correspondingly Ez = 0 in TE polarized modes. Waveguide modes with both Ez = 0 and Hz = 0 are called transverse electric magnetic (TEM) polarized. In addition of TE and TM modes, cylindrical waveguides support so called hybrid modes having ﬁnite components of both Ez and Hz. In the case of multilayer slab waveguides (see, e.g., Section 13.3.2), the plane of incidence is deﬁned by the mode propagation vector β and the unit vector parallel to the stacking direction. With this deﬁnition of the plane of incidence, TE and TM polarizations are deﬁned in the same manner as with a plane wave. In waveguides realized on silicon wafers the Ez and Hz components are typically non-zero. Then the hybrid modes that have their electric and magnetic ﬁelds mainly in the plane of the wafer surface and perpendicular to the propagation direction are called TE and TM modes, respectively. In birefringent materials the refractive index depends on the orientation of the electric ﬁeld, i.e., the polarization of light. Then the TE and TM ﬁelds

Figure 13.12 ● Evolvement of the two orthogonal polarization components (TE and TM) and the resulting total vector ﬁeld along the z-axis (or time). Three polarization examples with varying amplitude and phase differences between the TE and TM components are illustrated, namely linear polarization, circular polarization and elliptical polarization. The color ﬁgure can be viewed on the books companion website (http://www.elsevierdirect.com/companion/9780815515944).

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Optical Modeling of MEMS

propagate with different velocities determined by the associated refractive indices nTE and nTM. Birefringence Δn = nTM − nTE can be caused by an asymmetrical crystal lattice or an externally applied stress. The birefringence of waveguides refers to the effective index difference of the TE and TM modes, as will be explained in more detail in Section 13.3.4. The amount of optical power transmitted through and reﬂected back from an interface between materials with refractive indexes ni and nt (see Figure 13.4) can be calculated by taking into account the fact that the tangential components of E and H are continuous across the interface. The calculations are done separately for the two polarizations that have either the electric ﬁeld (TE) or the magnetic ﬁeld (TM) normal to the plane of incidence. The reﬂection coefﬁcients rTE and rTM, and the transmission coefﬁcients tTE and tTM are obtained from the Fresnel equations rTE =

ni cos(θi ) − nt cos(θt ) ni cos(θi ) + nt cos(θt ) tTE = 1 + rTE

rTM =

nt cos(θi ) − ni cos(θt ) nt cos(θi ) + ni cos(θt ) tTM =

ni (1 + rTM ) nt

(13.34) (13.35)

and

(13.36)

(13.37)

Note that the angle θt can be solved from Eq. 13.6. For both polarizations the intensity reﬂection coef2 ﬁcient is R = r and the intensity transmission coefﬁcient T 1 R. At normal incidence the cosinefunctions can be eliminated from the equations. In case of a reﬂection in normal incidence from an interface between air and absorbing material the intensity reﬂection coefﬁcient is R=

(n − 1)2 + k2 (n + 1)2 + k2

(13.38)

where n and k are the refractive index and extinction coefﬁcient of the material, respectively. The transform matrix method presented in Section 13.3.2 can be used to model reﬂection and transmission properties of more complicated stacked structures or interfaces with arbitrary refractive indexes and angles of incidence. The analytical theory of the wave equations and their solutions, as discussed in Section 13.2.3, becomes much more complicated when applied to vectorial ﬁelds instead of scalar ﬁeld. Therefore, one should try to carry out the theoretical (and numerical) treatment for one ﬁeld component at a time whenever possible.

CHAPTER 13

13.2.6 Quantum Optical Model With the wave optical models described above it is difﬁcult to explain and model light-matter interaction, such as absorption and emission of light, as well as many nonlinear optical effects. Some of these phenomena can be modeled by considering light as a collection of discrete particles, but the most accurate model combines the particle and wavelike properties of light. This model is called quantum optics and it explains light as a collection of photons, the elementary “particles” of electromagnetic radiation. The energy of a single photon is E = hc /λ

(13.39)

where h is Planck’s constant. When a photon is absorbed or emitted this amount of energy is transferred between the matter (e.g., electrons, molecules or accelerating charges) and the photon. The energy and the quantum (particle) characteristics of a photon are important for optoelectronic devices, such as lasers, ampliﬁers and detectors that involve active light–matter interaction. Furthermore, the energy of the photons can be fully or partially transferred to other photons via light-matter interaction. Also, the energy of the photons can indirectly inﬂuence the propagation of other photons, for example, by changing the refractive index of the propagating medium. These nonlinear effects are typically effective only when the intensity of light is high. They can be used to realize for example wavelength conversions and all-optical logic. Instead of a solid particle, the quantum optical model treats a photon as a vectorial electromagnetic ﬁeld conﬁned in both time and space. This enables the model to explain also the wavelike characteristics of light. However, according to the uncertainty principle one cannot simultaneously determine the exact spatial location (or detection time) and wavelength of a photon. This uncertainty prevents the realization of ideal optical systems with exactly deﬁned wavelengths, inﬁnite spatial resolution, perfect timing and no noise.

13.3 Numerical Modeling Methods for Optical MEMS The design of optical MEMS mainly relies on numerical modeling methods. Some speciﬁc modeling tasks can be carried out with analytical modeling methods, but in most cases one ﬁrst needs to make some approximations and then numerically solve the simpliﬁed problem. Due to the high frequency and small wavelength of light, accurate optical modeling is signiﬁcantly more complicated than, for example, electrical, mechanical or thermal 249

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modeling of equally large devices. Thus, a proper method for a given optical modeling task must be carefully selected by taking into account the area or volume to be analyzed, the size of structures that inﬂuence light propagation, the properties and homogeneity of the propagating medium (absorption, refractive index, dispersion, etc.), the spectral and temporal characteristics of light, the required accuracy of the results, and the available numerical modeling tools (hardware and software). This chapter brieﬂy introduces the most common numerical modeling methods in optics and demonstrates how they are used in the simulation of optical MEMS. Along with the modeling methods we introduce some examples of optical MEMS devices, such as mirrors, lenses, thin ﬁlm stacks, waveguides, gratings and pixel detectors. To simplify the waveguide analysis we concentrate on step-index waveguides that have a step-like refractive index proﬁle. The reader can ﬁnd information on graded-index waveguides from, for example, Refs [24] and [28]. Also, we do not discuss here the details of light–matter interaction in lasers, ampliﬁers, modulators, detectors and other active optical devices. Numerous commercial tools are available for the numerical modeling of optical MEMS, as well as some free software. Some of the tools are continuously improved and the list of companies offering commercial simulation tools changes frequently. Thus, the tools and the companies are not explicitly listed here.

13.3.1 Ray Tracing Method When all the details of the optical structure are large compared to the wavelength, the ray tracing method is often the simplest and most effective simulation tool. When a ray hits a material interface, it is split to a transmitted ray and a reﬂected ray. The amount of optical power contained in these rays is calculated using Fresnel equations 13.34–13.37. Directions of transmitted rays are obtained from the Snell’s law (Eq. 13.6). If a surface of an optical component includes, for example, an antireﬂection coating consisting of multiple sub-wavelength thick layers, its transmission and reﬂection properties are predetermined using the transfer matrix method presented in the next section. In sequential ray tracing only transmitted rays are considered and optical components are placed on the optical axis in a deﬁned order, being always clear which optical surface a ray hits next. In nonsequential ray tracing, both transmitted and reﬂected rays are taken into account and optical components can be positioned freely in a 3D space. The speed of nonsequential ray tracing depends strongly on the amount of optical surfaces in the model. This is due to the fact that each ray splits into two rays (transmitted and reﬂected) at each optical interface, and ﬁnding surfaces intersected 250

Figure 13.13 ● Ray tracing modeling of a Fourier spectrometer based on electrically movable silicon MEMS mirrors.

Figure 13.14 ● Bottom (left) and top (right) views of large diameter (12 mm) MEMS mirrors with electrically adjustable height and tilt.

next by the rays gets more time consuming with the increasing number of surfaces. Sequential ray tracing is typically used in designing and optimizing lens systems without any scattering surfaces. In the nonsequential mode, one can accurately simulate various light sources (lasers, leds, incandescent lamps, etc.), light propagation through optical elements (lenses, mirrors, lightguides, etc.), collection of light into optically sensitive devices (detectors, sensors, cameras, etc.), light scattering from realistic surfaces, and the illumination of arbitrary objects. An example of using ray tracing in the modeling of an optical system including several MEMS mirrors is illustrated in Figure 13.13. Examples of silicon MEMS mirrors are illustrated in Figure 13.14.

13.3.2 Optical Modeling of Thin Film Stacks Thin ﬁlm stacks are 1D structures that have several applications in optical MEMS. They can be used to realize,

Optical Modeling of MEMS

CHAPTER 13

obtain a numerically stable algorithm. In each layer, kx = n1k0 sinθ is constant due to Snell’s law. Since the wave number in the m:th layer is km = nm k0, the z-component of the wave vector can be expressed 2 as kzm = k0 nm − n12 sin2 θ , which shows that kzm ∀m > 1 can be imaginary only if nm < n1. Waves for which kzm is imaginary are called evanescent waves. Using time harmonic Maxwell’s equations, electric ﬁeld components can be written as j ∂H ym k = zm ωεm ∂z ωεm ( Am exp[jkzm(z − z0m )] − Bmexp[−jkzm(z − z0m )]) exp[jkx ]

Exm = −

(13.41)

Ezm =

Figure 13.15 ● Illustration of a thin ﬁlm stack inﬁnitely wide in the x- and y-directions. In transmission and reﬂectance calculations, light with the incident angle θ is incident in the uppermost layer having refractive index n1. The plane of incidence is illustrated on top of the thin ﬁlm stack. Slab waveguide mode calculations analyze guided electromagnetic modes β propagating along the x-axis.

for example, anti-reﬂection coatings, dielectric mirrors, polarizers, beam splitters, and thin ﬁlm ﬁlters for wavelength multiplexing and slab waveguides. Typically, one is interested in reﬂection and transmission properties of the thin ﬁlm stack or the possible electromagnetic waveguide modes supported by the structure. An example of a thin ﬁlm stack, invariant in the xand y- directions, is shown in Figure 13.15. For the beginning, it is assumed that the structure is illuminated by a TM polarized ( H y , Ex , Ez ) plane wave having incident angle of θ with respect to the z-axis. The refractive index of the incident layer is denoted by n1, and similarly the index of the i:th layer by ni. The z-coordinate of the interface between layers i and i 1 is denoted by zi. Dropping exp[ − jωt] time dependency, the solution of the Hy-component within the mth layer is expressed as H ym = ( Am exp[jkzm(z − z0m )] + Bm exp[−jkzm(z − z0m ]) exp[jkx x]

(13.40) where coefﬁcients Am and Bm are complex amplitudes of forward and backward propagating plane waves, respectively. Local coordinate offsets z0m = (zm+1 + zm )/ 2 with z01 = z1 and z0( M−1) = zM−1 are introduced to

k j ∂H ym = − x H ym ωεm ∂x ωεm

(13.42)

Using continuity of tangential electric and magnetic ﬁeld components across a planar interface, it can be found that m:th and m 1:th amplitude are related via the following transfer matrix equation: ⎤ ⎡A ⎡A ⎤ ⎢ m+1 ⎥ = Tm ⎢ m ⎥ ⎢ Bm+1 ⎥ ⎢ Bm ⎥ ⎣ ⎦ ⎦ ⎣

(13.43)

where ⎡ a (1 + qm )/(2cm ) bm (1 − qm )/(2cm )⎤ ⎥ (13.44) Tm = ⎢ m ⎢ am (1 − qm )/(2dm ) bm (1 + qm )/(2dm )⎥ ⎣ ⎦ Here, am = exp [ jkzm wm / 2] with a1 = 1 , bm = exp [−jkzm wm / 2] with b1 = 1, cm = exp [−jk z(m+1)w m+1 / 2] with c M = 1 , dm = exp[jkz(m+1)wm+1 / 2] with dM = 1, qm = εm+1kzm /(εm kz(m+1) ) , wm is the thickness of the m:th layer, and m = 1,..., M − 1. It is easy to see that the complex amplitudes of the uppermost layer and the lowest layer are related by ⎛ M−1 ⎞ ⎡ A ⎤ ⎡ AM ⎤ ⎢ ⎥ = ⎜⎜ ∏ Tm ⎟⎟⎟ ⎢ 1 ⎥ ⎜ ⎢ BM ⎥ ⎜⎝ m=1 ⎟⎠ ⎢⎣ B1 ⎥⎦ ⎣ ⎦ � ��

(13.45)

=T

where A1 is the initially known amplitude of the incident ﬁeld and BM = 0 since the lowest layer is assumed to be semi-inﬁnite in the z-direction, and therefore, there cannot be any reﬂected wave. Now, the amplitudes B1 and AM can be directly solved from Eq. 13.45. The TE polarized ( Ey , Hx , Hz ) case, that is, the electric ﬁeld is perpendicular to the plane of incidence, can be treated in the similar manner as the TM polarized case. The transfer matrix is otherwise the same for the TE mode, but the qm coefﬁcient is of the form: qm = kzm / kz(m+1). 251

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Reﬂectance (η R ) and transmittance ( ηT ) of the studied multilayer stack can be calculated from ηR =

2 ⎧⎪ k ⎫⎪ A B1 ,ηT = CRe ⎨⎪ zm ⎬⎪ M ⎪⎪⎩ kz1 ⎪⎭⎪ A1 A1

2

(13.46)

where C = 1 for TE polarization and C = ( n1 / n M )2 for TM polarization. Here it is assumed that n1 and nM layers have real-valued refractive indexes. The same transfer matrix formalism that was developed to describe light transmission through thin ﬁlm stacks can be used to ﬁnd slab waveguide modes supported by the structure. Assuming that the waveguide mode propagates along the x-direction (see Figure 13.15), kx is typically denoted by β, and then 2 kzm = k0 nm − β 2. Characteristic to bound waveguide modes is that the ﬁeld amplitude decays exponentially with the perpendicular distance z from the z1 and zM−1 interface. This requirement can be fulﬁlled by setting A1 = BM = 0 in Eq. 13.45 and accepting only such β values that both the real and imaginary parts of kz1 and kzM are positive quantities. Now, to ﬁnd a nontrivial solution to Eq. 13.45, it is required that T22(β ) = 0. Thus, the problem of ﬁnding the bound waveguide modes has reduced to the task to ﬁnd zeros of T22(β ). Note that β enters to Eq. 13.45 via the transverse wavenumbers kzm . If all refractive indexes of the thin ﬁlm stack are real valued, then max{n1 , n M } β / k0 max{n1, n2 ,..., n M }. Within this range of β, local minimums of T22(β ) approaching zero are easily found using a numerical minimum search algorithm. If one or more of the waveguide layers exhibit a complex refractive index, then also β is typically complex-valued and root ﬁnding gets more difﬁcult. However, using the argument principle it can be done relatively easily [25].

13.3.3 Effective Index Method Numerical modeling of optical 3D structures is often difﬁcult, at least if the dimensions are large and the accuracy requirements high. A commonly used method for simplifying the modeling task is the use of the effective index method (EIM) to convert a 3D structure into a 2D structure. Here we assume that a waveguide circuit processed on the surface of a silicon wafer, such as the one illustrated in Figure 13.16, will be modeled as a 2D effective index distribution neff (x,z) calculated for the wafer surface. For each point on the xz-plane, the original refractive index distribution n(y) along the normal of the wafer surface is converted into a scalar neff value by using a slab waveguide mode solver described in the previous chapter. The EIM is most accurate for low-index contrast (ncore ≈ ncladding) waveguides that are fabricated by using thin ﬁlm deposition methods 252

Figure 13.16 ● Photo of an SOI chip having photonic integrated circuits processed on its surface. These circuits are based on single-moded SOI rib waveguides and form thermo-optically controlled 3 3 switch matrices.

and when the normalized intensity distribution I(y) is fairly constant around the xz-plane. It is not suitable for modeling polarization effects.

13.3.4 Calculation of 2D Waveguide Modes Modeling of optical ﬁbers or planar waveguides on silicon typically starts from the calculation of waveguide eigenmodes, unless the waveguides have so many modes that ray tracing is more appropriate. The number of modes depends on the size, shape and refractive index contrast of the waveguide core. As explained in Section 13.3.2 for slab waveguides, each mode of a 2D waveguide cross-section is described by its ﬁeld distribution E(x,y) and effective index neff. The propagating modes have exponentially decaying ﬁelds around the core and, thus, no propagation loss if the materials are nonabsorbing. If the dimensions and the refractive index contrast of the waveguide are sufﬁciently small, the waveguide only supports one propagating mode per polarization (TE TM). Such a waveguide is called single-mode (SM), in contrast to multi-mode (MM) waveguides. For a silicon (or SOI) strip waveguide operating at 1550 nm wavelength the dimensions of the square silicon core surrounded by silicon dioxide must be kept well below 0.4 μm in order to ensure SM operation. However, with a special rib structure (see Figure 13.18) it is possible to obtain SM operation with a much larger core and refractive index than with a traditional waveguide having a square or circular core. An SM silicon rib waveguide, for example, can have dimensions even larger than 10 μm. This simpliﬁes optical coupling between the waveguide and a standard SM

Optical Modeling of MEMS

CHAPTER 13

neff

y n5

n5

n4

n4

n3 n2 n1

x

n5 n4

n5 n4 n3

n5

n5

n4

n4

neff,2 neff,1

n2

n2

n2

n2

n2

n1

n1

n1

n1

n1

neff,1

neff,3 neff,2

neff,3

x

neff,1 neff,2

Figure 13.17 ● Illustration of the EIM being applied to a 2D cross-section of a step-index waveguide based on e.g., silica-on-silicon or polymer technology. The original cross-section is split into ﬁve vertical slices. Effective indices are then calculated for the three unique slices by assuming them as inﬁnitely wide slab waveguides. Finally a 1D effective index distribution is formed to approximate the original waveguide cross-section.

Figure 13.18 ● Waveguide eigenmodes calculated for the shown (a) SOI waveguide cross-section with the EIM (b) and FD methods (c). The two red lines indicate the boundaries of the three vertical slices used in the EIM. Note the imperfect ﬁeld matching at the boundaries. The intensity distribution of the mode is plotted on a color scale shown on the right. The color ﬁgure can be viewed on the book’s companion website (http://www.elsevierdirect.com/companion/9780815515944).

ﬁber, although a larger mode ﬁeld also leads to larger circuit footprint. In addition to silicon-on-insulator (SOI) waveguides, many other waveguides can be fabricated on top of silicon substrates. Silica-on-silicon waveguides with a doped silica core are commonly used especially for passive photonic circuits. Polymers on silicon are also actively studied as a promising low-cost technology especially for electro-optic and MM waveguides. The use of EIM described in the previous chapter simpliﬁes the numerical analysis of a 2D waveguide cross-section into semi-analytical analysis of multiple slab waveguides. By dividing the cross-section into vertical slices and assuming them as separate slab waveguides one can construct an effective index distribution neff(x) and ﬁnally solve it as another slab waveguide. This is illustrated in Figure 13.17. As explained earlier, the EIM does not lead into a good approximation if the index contrast is large and the normalized vertical intensity distribution E(y) varies signiﬁcantly along the x-axis. This can be seen clearly in Figure 13.18. More information on EIM can be found in Refs [26] and [27]. If the waveguide cross-section can be approximated as a combination of a few rectangular areas then the ﬁlm-mode matching (FMM) method can be used to calculate the waveguide modes. It is somewhat similar to

the EIM-based algorithm, but by matching the ﬁelds at all boundaries and by calculating several modes per slice it provides much more accurate results. For an arbitrary 2D cross-section of a straight waveguide the modes can be numerically solved by using either the ﬁnite difference (FD) or the ﬁnite element method (FEM). The former is based on the discretization of the wave equation at the cross-section. Typical FD algorithms use predeﬁned, Cartesian calculation grids. Typical FEM algorithms, on the other hand, create a calculation mesh consisting of triangular elements for which the wave function is solved. The size of the elements can vary, so that most of the calculation effort can be focused on critical areas having large intensity or, for example, material interfaces. The simplest FEM algorithms use a linear approximation for the mode ﬁeld distribution within a single element, but higher order polynomial functions can also be used. The accuracy of the numerical 2D mode solvers can be made almost inﬁnitely high at the cost of increased computational effort. One can always use a ﬁner calculation grid in FD, ﬁner mesh or higher order polynomials in FEM, or more vertical slices and modes in FMM. Mode ﬁelds calculated with EIM and FD-based algorithms for an SM SOI rib waveguide are compared in Figure 13.18. 253

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13.3.5 Bidirectional Eigenmode Propagation Based on the numerically calculated eigenmodes of the 2D waveguide cross-sections it is trivial to analytically study the bidirectional propagation and interference of the modes along the waveguide, assuming that the crosssection does not change along the z-axis. The phase of a mode after the propagation of a certain length can be simply calculated from the effective index of the mode, and the interference of the modes can be calculated by summing up the complex 2D ﬁelds at any cross-section. This method is very efﬁcient for z-invariant structures and step-wise z-variant structures, as well as for multiple reﬂections in resonators, for example. Waveguide bends with constant bending radii can also be analytically modeled. With appropriate approximations the method can also be applied to waveguide structures that vary continuously along the z-axis, such as tapers and various bends. The excitation of the modes at the boundaries between the z-invariant parts is determined by calculating the overlap integral of each mode at one side of the boundary with respect to each mode on the other side of the boundary. The accuracy of the method depends on the number of the modes used, the accuracy of the used mode solver, and the validity of the assumption for z-invariance.

13.3.6 Beam Propagation Method The SVEA, the paraxial Helmholtz Eq. 13.22 and an initially known transverse source ﬁeld E( x, y ) at z = z0 form the basis of the beam propagation method (BPM). When n = n0 in Eq. 13.22, it represents light propagation in a uniform medium having refractive index n0 . Therefore, it can be seen that the right-hand side of Eq. 13.22 consists of two parts: one represents light propagation in a uniform medium, and the second the guiding

function due to the refractive index distribution n( x, y, z). Although these two effects happen simultaneously, it is assumed in BPM that they can be separated and modeled in a sequential manner, which is a valid approximation if light is propagated only over a small distance Δz . The ﬁrst step is to propagate the ﬁeld E( x, y ) in the uniform medium (n0 ) from plane z = z0 to z = z0 + Δz using, for example, the plane wave spectrum method presented in Section 13.2.4. The second step is to add the effect of n( x, y, z) to the propagated ﬁeld E( x, y, z0 + Δz) by multiplying the ﬁeld by a phase shift of exp[ jk0 ( n( x, y, z) − n0 )Δz] . The process is then repeated in steps of Δz to propagate the ﬁeld through the structure of interest. Other BPM algorithms use FDs to discretize the paraxial Helmholtz equation. For more details, see Chapter 7 in Ref. [28], for example. The BPM methods are fast and fairly accurate if light propagates with small angular variations and the propagation medium has small refractive index variations. There are also many variations and extensions to this basic algorithm. So-called wide-angle BPM uses more advanced approximation for the higher order z -derivatives and supports light propagation with larger angular deviations. There are also bidirectional algorithms that enable light to propagate to opposite directions. The 3D BPM algorithms typically model one polarization mode at a time, but also full-vectorial 3D BPM algorithms exist. The main advantage of the BPM is the ability to use a relatively coarse calculation grid. This enables the simulation of 2D areas and 3D spatial volumes that are orders of magnitude larger than those supported by the rigorous modeling methods. Furthermore, the memory requirements are mainly related to the size of the cross-section, so that the length of the simulation region can be easily extended. The basic idea and a practical application example of the 2D-BPM algorithm are illustrated in Figure 13.19.

Figure 13.19 ● Modeling of (a) directional coupler and (b) cascaded multi-mode interference (MMI) couplers with 2D BPM. The former provides a simple visual illustration of the BPM concept. The color ﬁgure can be viewed on the book’s companion website (http://www. elsevierdirect.com/companion/9780815515944).

254

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13.3.7 Finite Difference Time Domain Method In many applications light propagates with large angular variations or through complicated optical structures with large and continuously changing refractive index variations. Then the approximations described above may not be valid and one must resort to rigorous modeling methods, such as the ﬁnite difference time domain (FDTD) method [5–7, 29]. In 1966, Kane S. Yee introduced the FDTD method to solve time-dependent Maxwell’s equations in a spatially ﬁnite computation domain [29]. The FDTD method approximates Maxwell’s equations in the differential form by a central difference operator in both time and space. The electric and magnetic ﬁelds are then represented by their discrete values on the spatial grid and are advanced in time in steps of Δt. Yee’s discrete representation of Maxwell’s equations with a properly sampled spatial grid provides reliable numerical solutions for electromagnetic problems ranging from optical frequencies to microwaves. The FDTD computation domain is typically terminated using absorbing boundary conditions, such as Berenger’s perfectly matched layers [30, 31]and uniaxial perfectly matched layers [32], which provide almost reﬂectionless interfaces to extend the computation domain to inﬁnity. Also periodic boundary conditions can be utilized with the FDTD method [33]. The periodic boundary conditions depend on the wavevector kˆ of an illuminating plane wave (see, e.g., Eq. 13.47), and thus only harmonic single frequency plane waves can be used with obliquely incidence in the traditional Yee’s algorithm. However, there exist more complicated modiﬁed Yee’s algorithms [5] that can handle obliquely incident time domain plane wave pulses. An essential property of Yee’s algorithm is that it introduces no dissipation into the physical problem due to numerical discretization; and, hence energy is conserved. However, it produces nonphysical numerical dispersion, which means that the phase velocity of the simulated wave can differ from the real speed of light varying with the wavelength, direction of propagation, and mesh discretization. It can be shown [5] that the numerical dispersion error diminishes with cell size h as O(h2). Therefore, it can be reduced to an acceptable level by using a grid resolution with 30 points per the smallest wavelength. This requirement limits the area of any 2D FDTD simulation and enables the 3D modeling of only minuscule volumes, at least with standard simulation hardware. The limitations are mainly related to the available RAM memory and elongated computation times. The 3D FDTD simulation of the 4 μm thick SOI rib waveguide mirror illustrated in Figure 13.20 or the pixel detector illustrated in Figure 13.21 already requires a very efﬁcient personal computer (2.5 GB

Figure 13.20 ● Result from the 3D FDTD modeling of a 90° mirror integrated into a single-moded SOI waveguide. The 3D plot shows surfaces of constant ﬁeld (5% of either minimum or maximum ﬁeld) inside the 12 12 6 μm calculation volume. The radical change of the propagation angle prevents the use of simpler modeling methods, such as BPM. The color ﬁgure can be viewed on the books companion website (http://www. elsevierdirect.com/companion/9780815515944)

Figure 13.21 ● Advanced pixel detector on silicon modeled with 3D FDTD. Color ﬁlters and passive waveguide structures have been integrated between the light-collecting lenses (top) and the active detector pixels (bottom). An example result of the simulation is plotted on one 2D cross-section of the simulated volume.

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Input

Output InP

6

4

Si

Air

Si BCB

2 SiO2 4

15

Figure 13.22 ● Result from the 2D FDTD modeling of optical coupling from a single-moded SOI waveguide into an InP detector chip hybrid integrated on top of the silicon chip. Light ﬁrst couples from Si into air and is then reﬂected upwards inside a polymer (BCB) prism. The dimensions are in micrometers. The color ﬁgure can be viewed on the books companion website (http://www.elsevierdirect. com/companion/9780815515944)

RAM). In 2D the simulation area can be signiﬁcantly larger, as illustrated in Figure 13.22. Numerical modeling with FDTD offers many advantages, as long as the region of interest is small enough. For example, the propagation medium can be arbitrarily deﬁned, which supports the detailed modeling of nonlinear effects, polarization effects, dispersive materials [34], large refractive index contrasts, etc. Furthermore, since Yee’s algorithm is developed in the time domain, it can propagate pulsed as well as monochromatic electromagnetic ﬁelds. Using a wide-band time domain pulse, one can solve an electromagnetic scattering problem at multiple frequencies by a single simulation. One of the biggest advantages of FDTD compared to other methods is that it is easy to parallelize [35] and can be run efﬁciently in parallel-processing (cluster-type) computers.

13.3.8 Grating Diffraction Gratings are utilized in many optical applications such as spectrometers, polarizers, wavelength selective ﬁlters, biosensors, and as in- and out-coupling structures in waveguides. MEMS-based dynamic diffraction gratings [36], also known as grating light valves [37], enable fast light switching, modulation, and attenuation via diffraction. A grating light valve consists of alternate conductive ribbons that can be deﬂected towards the substrate by applying a voltage. Ribbons at different heights form a diffractive grating, diffraction properties of which can be changed in a dynamic manner. To obtain optimal optical performance, diffraction gratings must be designed using rigorous numerical methods, such as the Fourier modal method [38, 39] (also known as rigorous coupled wave analysis (RCWA) [40, 41]) and the coordinate transformation method [42–45] (also called the C-method). Grating diffraction problems can also be 256

– H – E

θ kˆ x

y d z

Figure 13.23 ● One dimensional diffraction grating invariant in the y-direction and periodic in the x-direction with period d. The grating is assumed to be inﬁnitely wide in the x- and ydirections. The grating is illuminated by a plane wave having incident angle of θ. The plane above the grating illustrates the plane of incidence (xz-plane). The color ﬁgure can be viewed on the books companion website (http://www.elsevierdirect.com/ companion/9780815515944)

solved by FD and FEMs, but in the analysis of onedimensional gratings, FMM and the C-method are superior in respect of calculation time and memory requirements. Physical principles behind the Fourier modal method are brieﬂy introduced next. Figure 13.23 illustrates a typical grating structure analyzed by FMM. The grating is periodic in the x-direction and it is illuminated by a plane wave having angle of incident θ in respect of the z-axis. The plane of incidence is assumed to be the xz-plane. Here, it is limited to gratings periodic in the x-direction, but equally well the grating could be periodic in both the x- and y-directions. The basic idea in modal methods is simple: The electromagnetic ﬁelds above (region I) and below the grating (region III) are presented using the plane wave spectrum representation (see Section 13.2.4). Due to periodicity of the problem, each scalar ﬁeld component in these homogeneous regions satisﬁes the Floque–Bloch theorem: U s ( x + d, z) = U s ( x, z)exp[ jkxinc d]

(13.47)

Optical Modeling of MEMS

where kxinc = n I k0 sin θ. Substituting the plane wave spectrum representation into Eq. 13.47, one obtains that lateral propagation wavenumbers in the plane wave spectrum can have only discrete values: kxn = kxinc +

2πn d

(13.48)

where n is integer. Thus, the diffracted electric ﬁelds in the region I can be expressed as E I (x, z) =

∞

∑

R n exp[ j( kxn x − kIzn z)]

CHAPTER 13

eigenfunctions, as well as amplitudes of the reﬂected and transmitted plane wave spectrum, are found by applying electromagnetic boundary conditions at the interfaces between the regions I and II and the regions II and III. Propagation angles of transmitted and reﬂected diffraction orders are given by Eq. 13.48. Substituting kxn = n III k0 sin θn into Eq. 13.48, one obtains the grating equation for the transmitted orders: n III k0 sin θn = n I k0 sin θ +

2πn d

(13.50)

(13.49)

n=−∞

where kIzn = ( k0 n I )2 − (kxn )2 , and R n is complex vector amplitudes of the reﬂected ﬁeld. A similar type equation can be written for the transmitted ﬁelds in the region III . In the region II , where the periodic refractive index variation occurs, the electromagnetic ﬁelds are solved as eigenfunctions of Maxwell’s equations. The total ﬁelds inside the grating are then expressed as superpositions of eigenfunctions. Amplitudes of the

The grating equation for the reﬂected orders is obtained by replacing n III by n I. FMM and the C-method are not limited only to the modeling of light scattering from gratings, but they can be applied also to the analysis of aperiodic optical systems like photonic crystals, Bragg gratings, laser resonators, and waveguide in-couplers. Typically, aperiodicity is obtained by introducing an artiﬁcial absorbing layer that separates the adjacent periods from each other. For more information, see Refs [46–48], and Ref. [49], for example.

References 1. B.E.A. Saleh, M.C. Teich, Fundamentals of Photonics, John Wiley & Sons, New York, 1991. 2. R.F. Harrington, Time-Harmonic Electromagnetic Fields, McGraw-Hill, New York, 1961. 3. Palik, E. D. (Ed.) Handbook of Optical Constants of Solids, Academic Press Inc. Orlando, FL, 1985. 4. J. Jin, The Finite Element Method in Electromagnetics, John Wiley & Sons, New York, 2002. 5. A. Taﬂove, S.C. Hagness, Computational Electrodynamics: The Finite-Difference Time-Domain Method, third ed., Artech House, Norwood, MA, 2000. 6. D.M. Sullivan, Electromagnetic Simulation Using the FDTD Method, John Wiley & Sons, New York, 2000. 7. K.S. Kunz, R.J. Luebbers, The Finite Difference Time Domain Method for Electromagnetics, CRC Press LLC, Boca Raton, FL, 1993. 8. D.S.J. Jones, Methods in Electromagnetic Wave Propagation, second ed., IEEE, New York, 1994. 9. G. Bao, L. Cowsar, W. Masters (Eds.), Mathematical Modeling in Optical Science, Society for Industrial and Applied Mathematics, Philadelphia, 2001.

10. M.E. Motamedi (Ed.), MOEMS: Micro-Opto-Electro-Mechanical Systems, SPIE, Bellingham, 2005. 11. A.W. Snyder, J.D. Lowe, Optical Waveguide Theory, Chapman and Hall Ltd, London, 1983. 12. K. Iga, Y. Kokubun (Eds.), Encyclopedic Handbook of Integrated Optics, CRC Press, Boca Raton, FL, 2006. 13. R.G. Hunsperger, Integrated Optics, Theory and Technology, ﬁfth ed., Springer-Verlag, New York, 2002. 14. L. Pavesi, D.J. Lockwood (Eds.), Silicon Photonics. Topics in Applied Physics, vol. 94, Springer, Berlin, Germany, 2004. 15. G.T. Reed, Silicon Photonics: The State of the Art, John Wiley & Sons, Chichester, UK, 2008. 16. R.S. Muller, T.I. Kamins, Device Electronics for Integrated Circuits, second ed., John Wiley & Sons, New York, 1986. 17. R. Soref, Electrooptical effects in silicon, IEEE J. Quantum Electron., QE 23 (1) (1987). 18. N.A. Nazarova, G.I. Romanova, A.D. Yas’kov, Refractometric characteristics of silicon, Sov. J. Optical Technol. 55 (1988) 220–224.

19. R. Dekker, N. Usechak, M. Först, A. Driessen, Ultra-fast nonlinear alloptical processes in silicon-on-insulator waveguides, J. Phys. D: Appl. Phys. 40 (2007) R249–R271. 20. K. Iizuka, Elements of Photonics, John Wiley & Sons, Inc. New York, NY., 2002. 21. J.W. Goodman, Introduction to Fourier Optics, McGraw-Hill, International Edition, Singapore, 1996. 22. M. Mansuripur, The Physical Principles of Magneto-optical Recording, Cambridge University Press, Cambridge, UK, 1995. 23. S.G. Lipson, H. Lipson, D.S. Tannhauser, Optical Physics, third ed., Cambridge University Press, Cambridge, UK, 1998. 24. C.R. Pollock, Fundamentals of Optoelectronics, Richard D. Irwin, Inc, Chicago, IL, 1995. 25. A.A. Stratonnikov, A.P. Bogatov, A.E. Drakin, F.F. Kamenets, A semianalytical method of mode determination for a multilayer planar optical waveguide, J. Opt. A: Pure Appl. Opt. 4 (2002) 535–539. 26. K.S. Chiang, Effective-index analysis of optical waveguides, Proc. SPIE 2399 (1995) 2–12.

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27. K.S. Chiang, Analysis of rectangular dielectric waveguides: effective-index method with built-in perturbation correction, Electron. Lett. 28 (4) (1992) 388–390. 28. K. Okamoto, Fundamentals of Optical Waveguides, Academic Press, San Diego, CA, 2000. 29. K.S. Yee, Numerical solution of initial boundary value problems involving Maxwell’s equations in isotropic media, IEEE Trans. Antennas Propag. 14 (1996) 302–307. 30. J.-P. Berenger, A perfectly matched layer for the absorption of electromagnetic waves, J. Comput. Phys. 114 (1994) 185–200. 31. J.-P. Berenger, Three-dimensional perfectly matched layer for the absorption of electromagnetic waves, J. Computat. Phys. 127 (1996) 363–379. 32. S. Gedney, An anisotropic perfectly matched layer-absorbing boundary conditions for the truncation of FDTD lattices, IEEE Trans. Antennas Propag. 44 (12) (1996) 1630–1639. 33. W.-J. Tsay, Application of the FDTD technique to periodic problems in scattering and radiation, IEEE Microwave Guided Wave Lett. 3 (8) (1993) 250–252. 34. M. Okoniewski, M. Mrozowski, M.A. Stuchly, Simple treatment of multi-term dispersion in FDTD, IEEE Microwave Guided Wave Lett. 7 (5) (1997) 121–123.

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35. C. Guiaut, K. Mahdjoubi, A parallel FDTD algorithm using the MPI library, IEEE Antennas Propag. Mag. 43 (2) (2001) 94–103. 36. M.W. Kowarz, J.C. Brazas, J.G. Phalen, Conformal grating electromechanical system (GEMS) for high-speed digital light modulation, IEEE, 15th Int. MEMS Conf. Digest 5 (2002) 568–573. 37. J.I. Trisnadi, C.B. Carlisle, R. Monteverde, Overview and applications of Grating Light ValveTM based optical write engines for highspeed digital imaging. MOEMS Display and Imaging Systems II, in: H. Urey, D.L. Dickensheets (Eds.), Proceeding of SPIE 5348, 2004, pp. 52–64. 38. L. Li, New formulation of the Fourier modal method for crossed surfacerelief gratings, J. Opt. Soc. Am. A 14 (1997) 2758–2767. 39. P. Lalanne, Improved formulation of the coupled-wave method for twodimensional gratings, J. Opt. Soc. Am. A 14 (1997) 1592–1598. 40. M.G. Moharam, T.K. Gaylord, Rigorous coupled-wave analysis of metallic surface-relief gratings, J. Opt. Soc. Am. A 3 (11) (1986) 1780–1787. 41. M.G. Moharam, E.B. Grann, D.A. Pomnet, T.K. Gaylord, Formulation for stable and efﬁcient implementation of the rigorous coupled-wave analysis of binary gratings, J. Opt. Soc. Am. A 12 (5) (1995) 1068–1076.

42. J. Chandezon, G. Maystre, G. Raoult, A new theoretical method for diffraction gratings and its numerical application, J. Opt. (Paris) 11 (1980) 235–241. 43. J. Chandezon, M.T. Dupuis, G. Cornet, D. Maystre, Multicoated gratings: a differential formalism applicable in the entire optical region, J. Opt. Soc. Am. 72 (1982) 839–846. 44. L. Li, J. Chandezon, Improvement of the coordinate transformation method for surface relief gratings with sharp edges, J. Opt. Soc. Am. A 13 (1996) 2247–2255. 45. L. Li, J. Chandezon, G. Granet, J.-P. Plumey, Rigorous and efﬁcient gratinganalysis method made easy for optical engineers, Appl. Opt. 38 (2) (1999) 304–313. 46. P. Lalanne, E. Silberstein, Fouriermodal methods applied to waveguide computational problems, Opt. Lett. 25 (2000) 1092–1094. 47. T. Vallius, M. Kuittinen, Novel electromagnetic approach to photonic crystals with use of the C method, J. Opt. Soc. Am. A 20 (2003) 85–91. 48. E. Silberstein, P. Lalanne, J.-P. Hugonin, Q. Cao, Use of grating theories in integrated optics, J. Opt. Soc. Am. A 18 (2001) 2865–2875. 49. T. Vallius, J. Tervo, P. Vahimaa, J. Turunen, Electromagnetic approach to laser resonator analysis, Opt. Express 13 (2005) 5994–5999.

14

Chapter Fourteen

Gas Damping in Vibrating MEMS Structures Timo Veijola Department of Radio Science and Engineering, Helsinki University of Technology, Espoo, Finland

14.1 Introduction MEMS structures are surrounded usually by gas, e.g., air, and when they move or vibrate, the structures interact with the surrounding gas. The most dominant effect of the gas is the damping force acting on the vibrating structure, but also spring forces and inertial forces may be important for the operation of the MEMS device. MEMS devices affected by the gas interaction are many: accelerometers [1–3], torsion micromirrors [4–6], optical and capacitive switches [7–11], and generally various resonator structures [12–14]. Generally, the gas motion is a 3D phenomenon and not very easy to analyze. Fortunately, the gas effects are the strongest when the ﬂow takes place in narrow gaps or channels. In practice, considering only these gaps or channels enables the characterization of the gas ﬂow with sufﬁcient accuracy. This reduces the complexity considerably, since the gas ﬁlm can be analyzed in 2D. In such analysis, these gas ﬁlms can be treated as planes interacting with the surfaces of the moving bodies. A typical example of this is the gas ﬁlm in the air gap of the electrostatic transducer discussed elsewhere in this book. The damping in MEMS structures is dominated by their small characteristic dimensions, and leads to the following observations: • The damping force is dominated by the viscosity. • The rareﬁed gas effects are present, especially at pressures below the ambient pressure. • The wavelength of the oscillation is large compared with the dimensions of gas volumes.

The equations for the gas ﬂow analysis are basically the Navier–Stokes (N–S) equations if the air gap is not very small and if the pressure is not below the ambient temperature. Using several assumptions, depending on the analyzed case, these equations reduce considerably and make it possible to derive analytic solutions for the gas ﬁlm forces. These assumptions include small operation frequency, small vibration amplitude, thin gas ﬁlm, and simple structure topology. MEMS structures have air gap heights roughly 1 μm, and the thin ﬁlm makes it necessary to consider the gas rarefaction effects in the gaps. This complicates the analysis, since the N–S equations are not generally usable for rareﬁed gas. The equations for the gas ﬂow are generally nonlinear. There are situations where this nonlinearity is considerable, but in most of the practical cases in vibrating MEMS systems, small vibration amplitudes can be assumed. The following analysis assumes small amplitude vibration, and nonlinearities in gas forces are not discussed here. Here, solid–gas interaction is studied in two main categories: pressure-driven ﬂow (squeeze-ﬁlm effect), and shear-driven ﬂow (slide damping, lateral damping, Stokes damping). Both of them will be studied in a simple, but in many cases sufﬁcient, structure shown in Figure 14.1. MEMS applications, that are not characterized by thin gas ﬁlms, such as piezo-actuated vibrating microbeams, are not discussed here. In the following sections, ﬁrst, the simplest topologies and low frequency operation in the viscous ﬂow regime are studied, then compressibility and gas inertia are added in the analysis, making the applicable frequency range wider. Finally, the viscoacoustic regime 259

Modeling in MEMS

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(a)

z

(b)

z

z

Moving body h0

v(z)

v(z)

hc Fig 14.2. ● Velocity proﬁles of (a) continuum ﬂow and (b) rareﬁed gas ﬂow.

a

b x

y

Steady bottom surface

h

Fig 14.1 ● Structure, dimensions, and coordinates of a gas damper with a thin gas ﬁlm between the body and surface.

for further higher frequencies is discussed brieﬂy. These sections emphasize practical models for designers, and they will not present any new results or models. Special attention is paid to the validity regimes of the models presented in the following.

14.2 Damping Dominated by Gas Viscosity Let us ﬁrst assume viscosity-dominated ﬂow in narrow air gaps. That is, assumption of uncompressible and intertialess ﬂow is made. This is equivalent to small vibration frequency assumption. These conditions also lead to isothermal conditions. The measures for the “small frequency limits” will be discussed later in Section 14.3. In viscosity-dominated ﬂow, the damping force does not depend on frequency and is relative to the viscosity coefﬁcient μ. The viscosity coefﬁcient does not depend on pressure, but it depends on temperature T0 [15]: 3

T C ⎛⎜ T0 ⎞⎟2 μ μR R ⎜ ⎟⎟ T0 C ⎜⎜⎝ TR ⎟⎠

(14.1)

where C is the Sutherland constant, and μR is the viscosity at temperature TR. The viscosity coefﬁcient values for different gases can be found in the literature. For air μR 18.45 106 Ns/m2, TR 308 K, and C 112 K [15].

14.2.1 Squeeze-Film Damping In a squeeze-ﬁlm damper, a body is moving (vibrating) perpendicularly to a surface with a thin gas ﬁlm between the body and the surface. The moving surface squeezes the gas ﬁlm and causes the ﬂuid to ﬂow towards its borders; that is, the ﬂow is pressure-driven. Since the gas ﬁlm is thin, the ﬂuid velocity is much larger in the 260

x- and y-directions compared to the z-direction motion of the surface. Also, the pressure proﬁle across the gap can be considered constant. The velocity proﬁle across the air gap plays an important role in characterizing the damping. In idealistic conditions, this velocity proﬁle is parabolic; see Figure. 14.2a. The velocity v is zero at the surfaces. This type of ﬂow is called Poiseuille ﬂow. The damping can be thought of as a result of the friction between viscous gas layers having different velocities. Due to the gas friction, or ﬂow resistance, in the x- and y-directions, the pressure at the center of the gas ﬁlm will get higher than at the borders. When calculating the damping in squeeze-ﬁlm dampers, the main task is to solve the pressure distribution acting on the surfaces. From that distribution, the force acting on the body (or on the surface) is then integrated. The resulting force F is always proportional to the z-direction velocity w of the body. The damping coefﬁcient, equivalent to the mechanical resistance, or ﬂow resistance Rm, is simply Rm

F w

(14.2)

The negative sign is needed for positive mechanical resistances, because the force is acting in the opposite direction to the velocity. Due to the thin gas ﬁlm assumption, the N–S equations reduce to a much simpler form, called the Reynolds equation. In MEMS applications, the “unsteady ” part of the equation is simply called the Reynolds equation. Squeeze-ﬁlms and the Reynolds equation have been studied in the gas ﬁlm lubrication literature long before any MEMS devices were invented [16–23]. Later, squeeze-ﬁlms in MEMS applications have been studied [2, 4–6, 10, 19, 24–33].

14.2.1.1 Rareﬁed Gas Effects In narrow gaps, the number of gas molecules is small, and the continuum mechanics cannot anymore explain the gas ﬂow. The interaction between the gas and the rigid body plays an important role in this case. For rareﬁed gas, the surfaces behave “slippery ”, and the tangential velocity of the gas is no more necessarily zero at the surfaces than it is in the continuum case.

Gas Damping in Vibrating MEMS Structures

Table 14.1 Flow regimes determined by the Knudsen number Kn

Flow regime

Conditions

Continuum ﬂow

Kn 0.001

Slip ﬂow

0.001 Kn 0.1

Transitional ﬂow

0.1 Kn 10

Molecular ﬂow

10 Kn

CHAPTER 14

Table 14.2 Approximations for Qpr for ﬂow in the air gap of a squeeze-ﬁlm damper

Approximation Qpr

Validity

Accuracy

(a) Slip [17]

1 6K n

Kn 0.05

5%

(b) Generic [2]

1 + 9.638K n1.159

Kn 880

5%

(c) Improved [39]

12K n ˆ π Qp ( ,α ) 2K n π

1% Kn 88, 0.7 α 1

Function Qˆ p is given in Eq. 14.5.

The nonidealistic, or non-continuum, conditions due to the rareﬁed gas lead to a different velocity proﬁle across the gap. This is equivalent to a ﬂow resistance that depends on rareﬁed gas conditions. Figure 14.2 illustrates the velocity proﬁles in the air gap in continuum ﬂow and in rareﬁed ﬂow. The measure for the gas rarefaction is the Knudsen number Kn; that is, the mean free path of the gas λ divided by the air gap height Kn λ/h. The mean free path ⎛p ⎞ λ λ R ⎜⎜⎜ R ⎟⎟⎟ ⎜⎝ p0 ⎟⎠

(14.3)

depends on pressure p0, and λR is the mean free path at reference pressure pR. The mean free path depends also on tempererature [15]. At atmospheric pressure and at room temperature, the mean free path for air is 65 109 m. Depending on Kn, different ﬂow regimes have been named. These are shown in Table 14.1. For example, the Knudsen number for air in a 1 μm air gap is 0.061 at atmospheric pressure, indicating slip ﬂow regime. In the literature, the rareﬁed gas effects are often included in the effective viscosity coefﬁcient μeff. With this approach, the models derived for the continuum ﬂow regime can be reused for rareﬁed gas. This is justiﬁed, since the rarefaction effect just scales the force to be smaller in the squeeze-ﬁlm analysis. One can specify μeff

μ Qpr

(14.4)

where Qpr is the relative ﬂow rate coefﬁcient. Qpr is a function of the Knudsen number Kn. For continuum ﬂow its value is 1, but the rareﬁed gas effects make the value greater than 1. For example, for a 1 μm air gap at atmospheric pressure, Qpr is about 1.4, making the inclusion of the gas rarefaction necessary in the damping analysis. Solving Qpr for rareﬁed gas is not simple, even for trivial topologies. The Boltzmann equation has been solved for

several practical cases [34–38], and many approximations for Qpr with different validity regimes have been reported in [2, 17, 39–42]. Articles discussing rareﬁed gas ﬂow generally are [15, 20, 35–37, 40, 43–51]. Articles discussing MEMS applications are [2, 17, 19, 34, 39, 41, 52–55]. Also, the numerical Direct Simulation Monte Carlo (DSMC) method can be used in studying the gas ﬂow at large Knudsen numbers [42, 56–58]. Table 14.2 shows a few approximations for Qpr, that are results of ﬁtting to the more complicated and more accurate computational results. In the improved ˆ is a function of the approximation in Table 14.2, Q p inverse Knudsen number D π/2Kn and the surface accommodation coefﬁcient α: ⎛1 ⎞ 1 ˆ ( D, α ) D

Q ln ⎜⎜ 4.1⎟⎟⎟ p 1.34 ⎜ ⎝ ⎠ 6 D α π

1.3 ⋅ (1 α ) 0.64 ⋅ αD0.17 α

1.83 6.4 1 0.08 ⋅ D 1 + 1.12 ⋅ D0.72 (14.5)

The surface accommodation coefﬁcient a is 1 for normal engineering surfaces, but for extremely clean surfaces values smaller than 1 have been reported in the literature [37, 47, 59–64]. The slip coefﬁcient, that is practically a multiplier of Kn, should be included in an accurate analysis, but has been neglected here for simplicity, due to its small deviation from unity (about 1%).

14.2.1.2 Modiﬁed, Uncompressible Reynolds Equation The equation for pressure p(x,y) distribution in thin gas ﬁlm at low frequencies is ⎞⎟ ⎛ h3Q dh ⎜ pr ∇ ⋅ ⎜⎜ ∇p⎟⎟⎟ ⎜⎜ 12μ ⎟ dt ⎠ ⎝

(14.6) 261

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The “modiﬁed” refers to the contribution of Qpr in the Reynolds equation. The gap height h(x,y), and the ﬂow rate coefﬁcient Qpr(x,y) are also functions of x and y. After setting the boundary conditions for the pressure or/and the velocity, the pressure distribution p(x,y) can be solved from Eq. 14.6. When small amplitude oscillation and uniform air gap is assumed, Eq. 14.6 can be linearized, resulting in: h03Qpr 12μ

∇2 p w

(14.7)

where h0 is the constant air gap height. Here, the velocity w(x,y) is used instead of dh/dt. Eq. 14.7 can be solved for a few simple geometries, velocity excitations, and boundary conditions. Zero-pressure boundary conditions are used that are valid if the characteristic (in practice, the smallest) surface dimension is much larger than the air gap height. The gas ﬁlm force can be calculated from pressure distribution: a b 2 2

F

∫ ∫ p dx dy

a b − 2 2

(14.8)

For torsion motion about, e. g., the y-axis, the twisting moment is a b 2 2

τ

∫ ∫ xp dx dy

(14.9)

a b − 2 2

In the following, analytic models for certain structures are given. They include rectangular and circular surface geometry and linear and torsion motion. Figure 14.3 shows the topologies for rectangular dampers in linear and torsion motion. Figure 14.4 illustrates the pressure distribution on a square surface in linear and in torsion motion.

14.2.1.3 1D and 2D Dampers in Linear Motion In translational, or linear, motion the z-direction of the body velocity w w0 does not depend on x or y. Table 14.3 summarizes the mechanical resistances Rm solved for rectangular surface geometries. These are usable solutions in many practical cases. The nominal mechanical resistance R0 for a rectangular squeeze-ﬁlm damper is

Fig 14.3. ● Squeeze-ﬁlm dampers in (a) linear and in (b) torsion motion. The arrows indicate the positive actuation velocity.

Fig 14.4. ● Pressure distribution on the surface of a square squeeze-ﬁlm damper in (a) linear and (b) torsion motion.

262

Gas Damping in Vibrating MEMS Structures

R0

a2b2μ

(14.10)

Qpr h03

The function in Table 14.3 for topology (c) is Rlin ( a, b)

M ,N

1 G m1,3,… mn

∑

(14.11)

n1,3,…

where the admittances in the summation are Gmn

π6 ( mn )2 ⎛⎜ 2 b

n2 ⎜m 768 R0 ⎜⎝ a

a ⎞⎟ ⎟ b ⎟⎠

(14.12)

CHAPTER 14

accuracy if a/b does not differ much from 1 (0.1 a/ b 10). If a and b are very different, the sum converges slowly, and Rlin is no more practical in calculating the damping force. A very good approximation for Rlin is usable for any a/b ratios [33] ⎞⎟1 ⎛ ⎜⎜ ⎟ ⎜⎜ 1 1 ⎟⎟⎟ ˆ

Rlin ( a, b) R0 ⎜⎜ ⎟ ⎛ b ⎞⎟ ⎛ a ⎞⎟⎟⎟⎟ ⎜⎜ ⎜ ⎜ W W ⎟ ⎟ ⎜⎝ ⎟⎠⎟⎟ 0⎜ ⎜⎜⎝ 0 ⎜⎜⎝ a ⎟⎠ b ⎠

(14.13)

where the function W0(ξ) is W0 (ξ ) ξ 0.63094ξ 2 0.47456ξ 8.138

The results in Table 14.3 (a)–(d) show that when ab, ab, and ab, the damping resistance is proportional to a3, a2, and a, respectively. The strip plate approximation (a) requires that a 13b and a 64b for errors less than 5% and 1%, respectively. Similar conditions apply for topology (b), too. In Eq. 14.11, the sums run theoretically to inﬁnity, but in practice M 9 and N 9 give sufﬁcient

Table 14.3 Analytic squeeze-ﬁlm damper solutions for few rectangular geometries in linear motion

Topology

Conditions

Rm

(a) Strip plate

ab

b R0 a

(b) Strip plate

ab

a R0 b

(c) Rectangular

Any a and b

Rlin(a, b), Eq. 14.11

(d) Rectangular

Any a and b

Rˆ lin (a,b ) , Eq. 14.13

The nominal resistance R0 is given by Eq. 14.10.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(14.14) The relative error of the approximation is less than 0.02% for any ratios of a and b. The solutions in Table 14.3 assume zero-pressure conditions at all damper borders. If the surface dimension to the air gap height ratio is not very large (100), the elongation model in Section 14.2.2 should be applied. When one or several borders in rectangular topology are completely blocked, the solution Rlin(a,b) can be reused to calculate the damping resistance. Resulting venting conditions and ﬂow directions are illustrated in Figure 14.5, and the resulting ﬂow resistances are shown in Table14.4. For annular shape, similar symmetry conditions do not exist as for rectangular dampers; the closed border cases need to be solved from the linearized Reynolds equation in cylindrical coordinates. Table 14.5 shows solutions for Rm in circular and annular geometries, including the venting conditions. For circular topology the nominal resistance RC is

RC

3πa4 μ 2Qpr h03

(14.15)

Fig 14.5. ● Venting conditions for rectangular dampers in normal motion. Thick lines indicate closed borders, and the arrows indicate the direction of the ﬂow. The letters (a)–(h) refer to the ones in Table 14.4.

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The venting conditions and ﬂow directions for circular and annular geometries are illustrated in Figure 14.6.

14.2.1.4 1D and 2D Dampers in Torsion Motion

where τ is the twisting moment in Eq. 14.9. Table 14.6 Summarizes the solutions for rectangular surface geometries and torsion motion around the y axis The function in Table 14.6 for topology (c) is

For torsion motion around the y-axis, the excitation velocity depends on x, w 2x/aw0. Here, the mechanical resistance for the torsional system is speciﬁed as the relationship between the force and velocity at (x a/2, y 0): Rm

2τ a

(14.16)

Table 14.4 Venting conditions for rectangular squeeze-ﬁlm dampers in linear motion

Case

Closed border(s)

Rm

(a)

None

Rm (a, b)

(b)

a/2 or a/2

1/2 Rlin (2a, b)

(c)

b/2 or b/2

1/2 Rlin (a, 2b)

(d)

2 a/2 and a/2

b R0 a

Rtor ( a, b)

b/2 and b/2

a R0 b

(f)

Neighboring borders

1/4Rlin (2a, 2b)

(g)

One open side

4b R0 a

(h)

One open side

4a R0 b

⎞⎟1 ⎛ ⎜⎜ ⎟ 1 ⎟⎟⎟ ˆ ( a, b) R ⎜⎜⎜ 1

R ⎟ tor 0⎜ ⎛ a ⎞⎟⎟⎟⎟ ⎜⎜ ⎛⎜ b ⎞⎟ ⎜ W W ⎜⎜ 1 ⎜⎜⎝ ⎟⎟⎠ 2⎜ ⎜⎝ b ⎟⎟⎠⎟⎟⎠ a ⎝

ξ (1 0.30487ξ 0.002278ξ 8.354 ) 15 (14.19)

Table 14.5 Analytic squeeze-ﬁlm damper solutions for circular and annular geometries in linear motion

Rm

(a) Circular

Radius a

Rc

(b) Annular

Open borders

(c) Annular (d) Annular

(b)

(c)

(d)

Fig 14. 6. ● Venting conditions for circular and annular squeezeﬁlm dampers. Thick lines indicate closed borders, and the arrows indicate the direction of the ﬂow. The letters (a)–(d) refer to ones in Table 14.5.

Table 14.6 Analytic squeeze-ﬁlm damper solutions for a few geometries in torsion motion

2 2⎞ ⎛ ⎜⎜1 η 4 (1 η ) ⎟⎟R ⎟ C ⎜⎜ ln η ⎟⎟⎠ ⎝

Closed border a

(4η 2 η 4 3 4 ln η )RC

Closed border b

(1 4η

2

Topology

Conditions

Rm

(a) Strip plate

ab

b R0 3a

(b) Strip plate

ab

a R0 15b

(c) Rectangular

any a and b

Rtor(a, b), Eq. 14.17

(d) Rectangular

any a and b

Rˆ tor (a,b ) , Eq. 14.18

)

3η 4η ln η RC 4

4

The nominal resistance Rc is given in Eq. 14.15, and η b/a is the ratio of the inner and outer radii.

264

(14.18)

where the functions W1(ξ) and W2(ξ) are

Cases (a)–(h) refer to the respective letters in Figure 14.5.

Conditions

(14.17)

where Gmn is given in Eq. 14.12 and R0 is given in Eq. 14.10. Also here, in practice M 10 and N 9 gives sufﬁcient accuracy if a/b does not differ much from 1. If a and b are very different, the following approximation for Rtor is usable [33]:

(a)

Topology

1 G m2,4,… mn

∑

n1,3,…

W1(ξ )

(e)

M ,N

Gas Damping in Vibrating MEMS Structures

W2(ξ )

ξ (1 1.8881ξ 1.187ξ 2 79.873ξ 8.506 ) 3 (14.20)

The maximum relative error of the approximation is less than 0.02% for all values of a and b. Venting conditions due to closed borders can be expressed reusing Rtor(a,b) for cases that are symmetric about the y-axis. These are shown in Table 14.7. The ﬂow resistance is nonzero also in case (d) when all borders are closed. The venting conditions and ﬂow directions for rectangular surfaces in torsion motion are illustrated in Figure 14.7.

14.2.2 End Effects in Squeeze-Film Dampers In Section 14.2, the narrow gap was assumed, meaning that the idealized pressure conditions at the damper borders were assumed. In practical MEMS structures, the gap is not always several magnitudes smaller than the characteristic dimension of the surface. This non-ideal behavior at the borders should be taken into account in analyzing the damping force for smaller aspect ratios. This non-idealistic behavior is caused by the ﬁnite ﬂow resistance outside the air gap, making the pressure non-zero at the damper borders.

Table 14.7 Symmetric venting conditions for rectangular squeezeﬁlm dampers in torsion motion

Case

Closed border(s)

Rm

(a)

None

Rtor(a, b)

(b)

b/2 or b/2

1 Rtor (a,2b ) 2

(c)

b/2 and b/2

b R0 15a

(d)

All

6a R0 15b

(a)

CHAPTER 14

Typically, the characteristic dimension to the gap height ratio L/h0 of 100 is large enough to justify the idealized border conditions. For a square topology, for example, the damping is proportional to L4, and when Kn is small, a ratio L/h0 of 100 and 500 in the models in Table 14.3 will have an error of 5% and 1%, respectively. But this is true only for continuum conditions, since the rarefaction effects make the border phenomena relatively stronger. This is due to the fact that the increasing Kn (e.g., decreasing pressure) makes the damping in the gap smaller, but the border effects due to the curved ﬂow ﬁelds are not strongly dependent on Kn. The ﬂow in short-ﬂow channels [46, 65, 66] and in squeeze-ﬁlm dampers with moderate aspect ratios [2, 26, 67, 68] has been discussed in the literature. The accurate analysis of the border effects requires a 3D study of the ﬂow ﬁelds both in the gaps and outside the damper borders. Figure 14.8 shows results of a 2D FEM analysis of a squeeze-ﬁlm damper with very small aspect ratio, a/h0 2.

14.2.2.1 Elongation Model The analytic treatment of the border ﬂow problems leads to complicated models, and here a simpliﬁed model based on 2D FEM simulations is presented. The following “surface extension” model [67] is very simple to apply, and it extends considerably the applicability of the models presented in Tables 14.3, 14.5, and 14.6. The “surface extension” model simply extends the damper border dimensions, relatively to the air gap height. For continuum ﬂow, the extension coefﬁcient is a constant, but the rareﬁed gas makes the extension depend on Kn. When Kn increases, the elongation increases. The extension Δ of each damper border is [67] Δ

1.3 (1 3.3Kn )h0 2

(14.21)

This “surface extension” model is usable also in the FEM solution of the Reynolds equation. In analytic models given earlier in Section 14.2.1, the

(b)

(c)

(d)

Fig 14.7. ● Venting conditions for rectangular squeeze-ﬁlm dampers in torsion motion. Only the solutions that are symmetrical about the y-axis are shown. Thick lines indicate closed borders, and the arrows indicate the direction of the ﬂow. The letters (a)–(d) refer to the ones in Table 14.7.

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−1000

−500

0

500

1000

0

5

10

15

Fig 14.8. ● FEM simulations of the (a) pressure and (b) velocity distribution around a squeeze-ﬁlm damper. Here, the velocity of the surface is constant w0, and the aspect ratio a/h0 2 is very small, making the border effects very strong.

surface dimensions a and b should be used instead of a and b: a ′ a 2Δ

(14.22)

b ′ b 2Δ

(14.23)

With these corrections, the previous models are usable for L/h0 4. (L is the smallest surface dimension.) The model has been derived using FEM N–S solver with slip boundary conditions. The accuracy of the model is not ensured if Kn 0.1.

14.2.2.2 Finite-Impedance Conditions at the Borders A straightforward method to include the border effects is to apply boundary conditions in a form of a non-zero ﬂow resistance (or impedance) at the border. This method can be applied in deriving compact models, and in FEM simulations with the Reynolds solver. For 1D damper structures, the compact models are easy to derive [67], but for 2D geometries the solutions with non-zero border resistances become rather complicated [5]. Also, according to FEM study for 1D gas ﬁlms in Ref. [67], the required correction in the resistance due to border impedances depends strongly on the a/h-ratio of the damper. When the aspect ratio gets small, say, 2, the fundamental assumption made in deriving the Reynolds equation breaks down [67]. Even if the border resistance would be correct, this method still could not give accurate results for small aspect ratios.

narrow microbeam of width b. Separate compact models have been ﬁtted to the results of both simulations. Knudsen number of 0 Kn 1 has been used in the simulations. The damping resistance is given as

Rm

bR0 a

266

(14.24)

where the ﬂow rate in R0 is Qpr 1 6χKn. The two ﬁtted coefﬁcients in N–S simulations (χ 1) are η

0.634 3.231Kn 1.782Kn2 1 1.176 Kn

(14.25)

ζ

0.445 1.844 Kn 0.910 Kn2 1 0.865Kn

(14.26)

and three ﬁtted coefﬁcients to DSMC simulation results are 1 8.834 Kn 1 5.118 Kn

(14.27)

η

0.634 1.572Kn 1 0.537 Kn

(14.28)

ζ

0.445 11.20 Kn 1 5.510 Kn

(14.29)

χ

14.2.2.3 Other Models Both N–S and DSMC simulations have been made in Ref. [26] analyzing the border ﬂow effects in an oscillating

2⎤ ⎡ ⎢1 3η ⎛⎜ 2h0 ⎞⎟⎟ 3ζ ⎛⎜ 2h0 ⎞⎟⎟ ⎥ ⎜ ⎜ ⎢ ⎜⎝ b ⎟⎠ ⎥⎥ ⎜⎝ b ⎟⎠ ⎢⎣ ⎦

Gas Damping in Vibrating MEMS Structures

CHAPTER 14

Table 14.8 Approximations for Qpr in slide damping

Approximation Qpr (a) Slip

Validity Accuracy

1 2K n

Kn 0.1 3%

(b) Cercignani [75] 1.3056K 2 7.5939K π Any Kn n n

1%

0.6528K n π

(c) Veijola [70]

1 2K n 0.2K n0.788e

K / 10 n

Any Kn

0.6%

Fig 14.9 ● Topology of a slide damper. A surface moves with a velocity v tangentially to the surface.

This model can also be expressed as a form of an approximate elongation model: ⎛ 2h ⎞2 ⎛ 2h ⎞ ηh 2Δ 3 1 3η ⎜⎜ 0 ⎟⎟⎟ 3ζ ⎜⎜ 0 ⎟⎟⎟ 1 ≈ 0 ⎜⎝ b ⎠ ⎜⎝ b ⎠ h0 b (14.30) when a relatively small elongation is assumed. If a small Kn is assumed, only the ﬁrst order of Kn is considered, and when η in Eq. 14.25 is used, the elongation for N–S simulations is Δ

1.27 (1 3.90 Kn )h0 2

(14.31)

This result is very close to the elongation in Eq. 14.21. Derivation of a similar elongation model from the DSMC results is also possible, but more complicated, since the differences in Qpr functions should be considered, too. End effects for larger Kn have also been studied, but only for channel outlets [46]. These results are not directly applicable in the typical MEMS squeeze-ﬁlm topology, where the body moves above a surface. The opening angle for the outlet ﬂow is in this case 90°, when the angle in ﬂow-channel studies is 180°.

14.2.3 Slide Damping Figure 14.9 shows the slide damper geometry, that is similar to the geometry of the squeeze-ﬁlm damper. The difference is that now the body moves (oscillates) tangentially with the surface. Such a damper is also called a shear driven damper, lateral damper, or Stokes damper. Typically, slide damping takes place in surface micromachined structures, under (and over) the moving mass, and between the ﬁngers of comb-drives (Figure 14.9) The gas motion is excited by the shear force on

the surface of the moving body. The damping force is also here caused by the friction between viscous gas layers moving, having different velocities. The velocity proﬁle differs dramatically from the previous squeezedamper case. Now the ﬂow velocity proﬁle is linear (in the idealized structure), called Couette ﬂow. There will be no considerable pressure variation across the surface of the damper, making the analysis in the narrow gap relatively simple: The damping force can be considered constant over the damper surface [14, 43, 69–74].

14.2.3.1 Rareﬁed Gas Effects The rareﬁed gas changes the ﬂow proﬁle, but the Qpr functions for the squeeze-ﬁlm damper are no more valid. Also here, the accurate solution of the ﬂow rate coefﬁcient requires the solution of the Boltzmann equation. Table 14.8 shows a few approximations.

14.2.3.2 Damping Force The damping force is F

μA v0 Qpr h0

(14.32)

where A is the surface area and v0 is the surface velocity perpendicularly to the z-axis. As can be seen in the equation, the surface shape does not affect the damping, only its area A.

14.2.3.3 End Effects in Slide Dampers End effects in slide dampers have not been investigated much. In Ref. [71], the edge and ﬁnite-size effects are studied. A simple scaling coefﬁcient for the force is suggested in cases where the gap height is not small compared with the surface dimension. In Ref. [14], the damping in a comb drive is modeled, applying Eq. 14.70 to various parts of the structure and with numerical 3D Stokes solver. The quality factor by the simple model was 58.9, and the Stokes solver gave 267

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a quality factor of 29.8. The measured quality factor was 27. In Ref. [70], a simple elongation model for a slide damper has been presented. It is based on FEM simulations for 2D structure, considering the borders perpendicularly to the oscillating motion. The model suggests that the air gap should be modiﬁed as h0 ′

h0 1 8.5

(14.33)

h0 a

where α is the length of the damper surface. The modiﬁcation of the gap height instead of the surface length is made, since the elongation seems to increase the resistance at the low-frequency regime only.

14.2.4 Perforated Squeeze-Film Dampers Due the manufacturing process, etch holes are needed in relatively large MEMS surfaces above a small air gap. Also, the holes are usable in controlling the damping force. In electrostatic actuators, the holes reduce the damping force dramatically, but affect only slightly the electrical properties of the air gap. In unperforated square squeeze-ﬁlm dampers the damping is proportional to L4, but in perforated dampers the force is proportional to d4, where d is the separation of the perforation holes. Figure 14.10 shows an example of a vibrating MEMS structure with perforations. In analyzing perforated dampers, the low-frequency solution is generally sufﬁcient for MEMS structures up to the MHz frequency range. On the other hand, the distance of the perforations d to the air gap height ratio is not usually large, making the border effects important. In addition, the ﬂow through the perforations contributes

to the damping force and thus needs to be considered in the analysis. These ﬂow channels are usually relatively short, including more challenges to the modeling. The analysis of perforated structures requires generally the consideration of the 3D structure of the air gap, perforations, and the regime around the damper. FEM tools can be used in the analysis, but only for a limited number of perforations and for the continuum and slipﬂow regimes. Due to the challenges explained above, the published models tend to be oversimpliﬁed and they are not very accurate. Often, ﬂow resistances caused by “fringe” ﬂows in the air gap below the perforation and outside the damper borders have been completely ignored, both in deriving the compact models and in FEM simulations. Additionally, in published models, not all force components have always been considered, as shown in Ref. [76]. If the force acting on the perforated plate is calculated, the forces on the sidewalls of the holes should be included, too. Alternatively, the counterforce on the ground surface could be calculated, which is a simpler action to perform. In FEM analysis the sharp corners at the periphery of the perforations contain pressure singularities that are not present in the ground surface pressure. Methods that reduce the 3rd dimension from the structure have been developed to be able to analyze the perforated dampers. The following articles discuss the modeling of perforated dampers [77–92] and reduced-dimension FEM methods [76, 93–96].

14.2.4.1 Flow Patterns Two ﬂow patterns can be distinguished in perforated dampers: closed-border and closed-holes patterns. The ﬂow directions demonstrating these patterns are shown in Figure 14.11. In Figure 14.11a, the ﬂow through the holes dominates, and the ﬂow out from the damper

(a)

(b)

w c

L A

B

A

B

S1 S0

d

Moving plate

Ground surface

Fig 14.10 ● An example of a vibrating MEMS structure with perforations.

268

Fig 14.11. ● Principal ﬂow direction patterns in perforated dampers in (a) closed border case and in (b) closed holes case.

Gas Damping in Vibrating MEMS Structures

borders is negligible. In Figure 14.11b, the ﬂow in the air gap dominates, and the holes can be assumed to be blocked. In practice, both ﬂow patterns may exist in perforated dampers. Since the gas outlets in both ﬂow patterns are separate, the ﬂow channels can be thought of as parallel channels; that is, the ﬂow resistances of these independent patterns are in parallel: R12

1 1 1

R1 R2

(14.34)

R12 can be used as a rough model that includes both ﬂow patterns. Figure 14.12 illustrates the gradual change from a closed-holes (small holes) case to a closed-border case (large holes).

14.2.4.2 Closed Damper Borders For a regular grid of perforations and relatively large perforations, a repetitive pressure pattern exists in the air gap. This equals the closed-borders case in Figure 14.11a. In such a case, the analysis can be limited to a rectangular regime around each perforation, called a perforation cell. The holes may have a staggered conﬁguration instead of the regular grid, making the cell shape hexagonal instead of rectangular. The velocity between the neighboring cells can be assumed to be zero. Now the force can be written simply as F NR p w

(14.35)

CHAPTER 14

where N is the number of perforations and Rp is the mechanical resistance of the perforation cell. Rp consists of ﬂow resistances of the air gap regime, intermediate regime under the hole, in the perforation, and above the perforations. The simplest model for Rp results, if the radii of the holes are much larger than the air gap, in making the zero-pressure assumption valid at the hole periphery. Assuming a circular perforation cell with an effective radius of rx, instead of a rectangular or hexagonal cell, the annular solution with closed outer borders, shown in Table 14.5 (c), can be applied. To maintain the same surface area, the effective radius is speciﬁed to be rx ax π , where ax is the length (and width) of the square perforation cell. An improved compact model for Rp has been given in Ref. [87] as a sum of several ﬂow resistances identiﬁed inside the cell: R p RS RIS RIB

rx4 r04

( RIC RC RE ) (14.36)

where rx and r0 are the outer and inner radii of the cylindrical perforation cell, respectively. Figure 14.13 shows the topology of the cylindrical perforation cell, and Figure 14.14 shows the lumped mechanical resistances used in modeling the ﬂow resistance of the cell. The ﬂow resistance Rp of the perforation cell consists of lumped ﬂow resistances and their effective elongations. The equations have been derived partly analytically and partly by ﬁtting the elongation

Fig 14.12. ● Simulated pressure patterns act on the bottom surface of a square (40 μm 40 μm), perforated squeeze-ﬁlm damper with 64 perforation and an air gap of 1 μm. (Due to symmetry, only a quarter of the structure is simulated and shown.) The hole diameter is (a) 1 μm, (b) 2 μm, (c) 3 μm. The relative pressure scale is shown in (d). The patterns have been simulated using the 3D N–S solver.

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and z

RE 8πμr0 ΔE hc

Rs above is equivalent to the resistance given for the annular damper in Table 14.5 (c). The effective elongations in the previous equations are

r

h0

(14.42)

rX

0.56 0.32 ΔS

r0

Fig 14.13 ● Topology and dimensions of an axisymmetric perforation cell.

r0 r2

0.86 02 rx rx

1 2.5Kn ,ch

(14.43)

⎛ r 2 ⎞⎟ 1 0.732Kn ,tb ⎛⎜ r0 hc ⎞⎟ ΔB 1.33⎜⎜⎜1 0.812 02 ⎟⎟ fB ⎜⎜ , ⎟⎟ ⎜⎝ h0 h0 ⎟⎠ ⎜⎝ rx ⎟⎟⎠ 1 Kn ,ch (14.44)

p=0

where

RE

fB (α, β ) 1

p4

A4

RC

RS U1

A3

U3 p3

RIS

RIC pI U2 RIB p2

A1 p1

U0 p0 A0

and

A2

ΔE

A0

12πμrx4 ⎛⎜ 1 rx r02 r04 ⎞⎟⎟ 3 ⎜

ln ⎟ (14.37) ⎜ 8 2rx2 Qch h03 ⎜⎝ 2 r0 8rx4 ⎟⎟⎠ 6πμ(rx2 r02 )2

ΔS

(14.38)

(14.39)

RIC 8πμr0 ΔC

(14.40)

8πμhc Qtb

0.944 ⋅ 3π(1 0.216 Kn ,tb ) 16 2 4⎞ ⎛ r ⎜⎜1 0.2 0 0.754 r0 ⎟⎟ f ⎛⎜⎜ r0 ⎞⎟⎟ ⎟ E ⎟ ⎜⎜ rx2 rx4 ⎟⎟⎠ ⎜⎜⎝ h0 ⎟⎠ ⎝

(14.47)

where fE (α ) 1

α3.5 178(1 17.5Kn ,ch )

(14.48)

The relative ﬂow rate coefﬁcients and Knudsen numbers for the ﬂow in the air gap and in the hole are Qch 1 6 Kn ,ch , Qtb 1 4 Kn ,tb , Kn ,ch λ /h0 , and Kn ,tb λ r0 , respectively.

14.2.4.3 Open Damper Borders and Holes

RIB 8πμr0 ΔB

RC

270

r0 h02

(14.45)

(14.46)

models to FEM simulations by varying the coefﬁcients in heuristic equations [87]. The lumped resistances are

RIS

7.11(43β 3 1)

⎛ r r 2 ⎞⎟ ΔC (1 0.6 Kn ,tb )⎜⎜⎜0.66 0.41 0 0.25 02 ⎟⎟ ⎜⎝ rx rx ⎟⎟⎠

Fig 14. 14. ● Mechanical resistances used in modeling the ﬂow in different regions in a perforation cell.

RS

α4 β 3

(14.41)

If the perforations cannot be considered large enough, the pressure increases at the center of the damper and breaks down the repetitive pressure pattern. There is a net ﬂow in the air gap, similarly as in the nonperforated case. This is illustrated in the pressure distribution in Figure 14.12. To analyze this situation, the ﬂow resistance of the perforation cells is assumed to be equally distributed on the

Gas Damping in Vibrating MEMS Structures

damper surface. This is equivalent to the case where the surface has a constant ﬂow resistance in the z-direction. Using this approach, an augmented Reynolds equation is written [97] h03Qpr 12μ

∇2 p Yp p w

(14.49)

where Yp is the speciﬁc acoustic admittance due to perforations. This equation can be analytically solved for certain surface topologies. Also, this equation can be solved with an FEM solver. The solution for Eq. 14.49 for a rectangular geometry results in a similar equation to the ones for the compressible Reynolds equation:

Rd

⎧⎪m 1, 3,5,… , ⎪⎨ ⎪⎪⎩ n 1, 3,5,… 1 m , n G ( a ′, b ′ )

mn Rmn

∑

1

(14.50) where Gmn(a,b) has been speciﬁed in Eq. 14.12 and Rmn

64 NR p m2 n 2 π 4

(14.51)

14.3 First-Order Frequency Dependencies The increasing vibration frequency breaks down the pure viscous ﬂow assumption and (a) makes the damping depend on frequency, and (b) introduces additional forces proportional to the displacement (spring forces) and proportional to the acceleration (inertial forces). The dominating frequency dependency in MEMS squeeze-ﬁlm dampers is due to the gas compressibility. In slide-ﬁlm dampers, the dominating frequency dependency is due to the inertial force, that is, the gas mass. In the following, frequency domain analyses of vibrating structures are presented and the variables are expressed as complex numbers, having an amplitude and phase angle relative to the excitation. Here, analogously to the electrical analysis, a mechanical impedance representation is used: The real part is the damping force, and the imaginary part is the spring or inertial force. This is emphasized here since in the squeeze-ﬁlm literature, often, the force is given relative to the displacement, making the spring force the real part and the damping force the imaginary part.

CHAPTER 14

The variables in the analysis are the complex valued coefﬁcients p and w. The actual time domain quantities are ˆp peiωt p0

(14.52)

ˆ weiωt w

(14.53)

where the angular frequency ω 2πf. The relation between the force and velocity is presented here as mechanical impedance Zm

F w

(14.54)

The damping coefﬁcient is equivalent to Re(Zm).

14.3.1 Compressible Squeeze-Films The compressibility is an out-of-plane phenomenon, similar to the ﬂow-through perforations in Section 14.2.4. This explains the similarity between Eq. 14.49 and the following linearized (modiﬁed) Reynolds equation for compressible ﬂow: h03Qpr 12μ

∇2 p iω p

h0 w p0

(14.55)

where p0 is the static pressure. The ratio of the compressible force and the viscous damping force is an important relation, which is usable in determining if the compressibility effect (frequency dependency) is needed in calculating the damping force. There are two similar measures for the compressibility effect: (a) the cutoff frequency fc, the frequency when the real and imaginary parts of the force are equal, and (b) squeeze number σ that gives an estimate for the relative contribution of the compressible force at a certain frequency: σ

12μ L2ω

(14.56)

Qpr p0 h02

where, L is the characteristic dimension (smallest dimension) of the surface. Generally, if σ1, the compressibility (and frequency dependency) can be ignored in the analysis. In the frequency-dependent analysis, also the inertial forces will have inﬂuence to the impedance of squeeze-ﬁlm dampers. The measure for this is the Reynolds number Re

Qpr h2ρ0 μ

ω

(14.57)

where ρ0 is the gas density. Here, the contribution of Qpr is included in the speciﬁcation of Re. If Re1, the 271

Modeling in MEMS

PA R T I I

inertia needs not to be considered. Usually, in thin gas ﬁlms in MEMS structures, the inﬂuence of the compressibility is usually much larger than the inﬂuence of the inertia. But, if the frequency is increased, the gas will inevitably resonate in the air gap at some frequency fce/(4L), where L is the characteristic (longest) dimension of the surface, and ce is the effective speed of sound in the gap, smaller than the speed of sound in vacuum c0 [98]. For a damper with an air gap length of 100 μm, the ﬁrst resonance occurs approximately at 800 kHz. To model the damper behavior correctly at such frequencies, the viscoacoustic model discussed in Section 14.4 is necessary. In the following, a few solutions of Eq. 14.55 for simple topologies will be presented. These cases have also practical use.

14.3.1.1 1D Damper in Normal Motion Assuming a damper with a rectangular surface, ab, and that the velocity w is a constant w0, a 1D solution for the pressure distribution in the x-direction can be solved analytically. After integrating the pressure over the surface, the mechanical impedance is Zm

12aR0 ⎡ K⎤ 2 ⎢1 tanh ⎥ 2 ⎢ K 2 ⎥⎦ bK ⎣

APLAC 8.40 User: TKK/RAD Circuit Theory Group Thu Oct 30 2008 1.00 k /k0

1.2 Rm /R0 1

0.75 0.8 0.50

0.6 0.4

0.25 0.2 0.00

0 0.1

1.0

10.0

100.0

1.0k

ω/ω0

Fig 14.15 ● Frequency response of a 1D squeeze-ﬁlm damper in linear motion: Re(Zm)(––) and Im(Zm) (– – –), both normalized to R0. The spring coefﬁcient k (––.––.) is shown on the right-hand scale relative to k0.

APLAC 8.40 User: TKK/RAD Circuit Theory Group Thu Oct 30 2008 0.100 Rm /R0

0.60 k/k0

0.075

0.45

0.050

0.30

0.025

0.15

(14.58)

where K

iω ω0

(14.59) 0

and ω0

Qpr p0 h02 12a2μ

(14.60)

If ω 0, Eq. 14.58 reduces to case (b) in Table 14.3. If ω approaches inﬁnity, the impedance is Z∞

12aR0 ω0 k 0 iωb iω

k0

abp0 h0

1.0

10.0 ω/ω0

100.0

1.0k

Fig 14.16 ● Frequency response of a 1D squeeze-ﬁlm damper in torsion motion: Re(Zm)(––) and Im(Zm) (– – –), both normalized to R0. The spring coefﬁcient k (––.––.) is shown on the right-hand scale relative to k0.

(14.61)

14.3.1.2 1D Damper in Torsion Motion

where (14.62)

Figure 14.15 illustrates the frequency response of real and imaginary parts of the impedance. Also, the spring coefﬁcient k Re(iω Z m ) is shown. The response in Fig. 14.15 shows that the cut-off frequency is about fc 1.6ω0 and the spring coefﬁcient approaches slowly k0. 272

0.00 0.1

Similarly, as in the previous case, we assume a damper with a rectangular surface, ab, but now the velocity of the surface is a result of torsion motion around the y-axis w (2x/a)w0. The 1D solution for the pressure distribution in the x-direction can be solved analytically. After calculating the twisting moment around the y-axis, and reducing the force to a/2, the impedance is Zm

12aR0 ⎡ 1 4 2 K⎤ ⎢ 2 coth ⎥ 2 ⎢ K 2 ⎥⎦ bK ⎣ 3 K

(14.63)

Gas Damping in Vibrating MEMS Structures

where K and ω0 are speciﬁed in Eqs. 14.59 and 14.50. If ω 0, Eq. 14.63 reduces to case (b) in Table 14.6. If ω approaches inﬁnity, the impedance is Z∞

4aR0 ω0 k 0 3iω iωb

(14.64)

Figure 14.16 illustrates the frequency response of real and imaginary parts of the impedance. Also, the spring coefﬁcient k Re(iω Z m ) is shown. The response in Figure 14.16 shows that the cut-off frequency is about fc 7.0ω0 and the spring coefﬁcient k approaches slowly k0/3.

14.3.1.3 2D Damper in Normal Motion Solution for Eq. 14.55 for a rectangular surface for any a and b and uniform velocity w0 is Zm

M ,N

∑

m1,3,… Gmn n1,3,…

1

iωCmn

(14.65)

modiﬁed dimensions will make the compressible force too large. It is possible to compensate this by reducing the elongation from the compressible part, and by reducing the pressure in the Reynolds equation, respectively.

14.3.2 Slide Damper with Inertial Effects The damping in the slide damper is inﬂuenced by the gas inertia when the frequency of the oscillation is increased or when the air gap is relatively large [43, 69, 71–74, 99]. The measure of the intertial force compared to the viscous forces is the Reynolds number Re, speciﬁed in Eq. 14.57. If Re1, the inertia needs not to be considered. In case of a slide damper, the Stokes equation ρ0

π 4 ( mn )2 64k0

(14.66)

Here, k0 is the spring coefﬁcient at inﬁnite frequency in Eq. 14.62.

∂v( z) ∂ 2 v( z) ν ∂t ∂z2

M ,N

1 G

iωCmn m2,4,… mn

∑

(14.67)

n1,3,…

(14.69)

14.3.2.1 Continuum Region The resulting complex damping impedance is [72] Zm

For a velocity excitation w 2x/aw0, the mechanical impedance, reduced to a/2, is

(14.68)

where v η/ρ0 is the kinematic viscosity.

14.3.1.4 2D Damper in Torsion Motion

Zm

∂U

μΔU ∇P ∂t

where U is the velocity vector and ρ0 is the gas density, reduces to a 1-dimensional form (pressure P is in this case missing):

where the values for Gmn are given in Eq. 14.12 and Cmn is Cmn

CHAPTER 14

μ Aq tanh( qh0 )

(14.70)

where q iω /ν . Typical for the slide damping is that the damping force is non-zero even for inﬁnite air-gap height. If the frequency of oscillation is high enough, it might be necessary to include the forces acting on the top surface of the body in the calculations.

where the values for Gmn are given in Eqs 14.12 and 14.66.

14.3.2.2 Rareﬁed Gas

14.3.1.5 Circular Geometry

Considering the slip conditions, the impedance of the damper is [70]

Frequency-dependent solutions of the compressible Reynolds equation with circular and annular topologies have been presented in [16, 21, 22].

14.3.1.6 Frequency-Dependent Border Effects In the frequency-dependent case, the elongation model in Section 14.2.2 is not directly applicable, since the

Zm

η Aq[1 qλ tanh( qh0 )] 2qλ (1 q2λ2 ) tanh( qh0 )

(14.71)

Here, λ is the mean free path. At small frequencies, Zm in Eq. 14.71 reduces to resistance Rm

μA (1 2Kn )h0

(14.72)

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To include the improved behavior at large values of Kn, the Qpr functions in Table 14.8 (b) or (c) could be used to correct Zm by multiplying it with Qpr ,a Qpr ,b or Qpr ,a Qpr ,c , respectively. Qpr,a refers to Qpr in Table 14.8 (a). Similarly, a little more complicated model has been presented in Ref. [41], and in Ref. [100] the oscillating Couette ﬂow problem is solved over the whole range of the Knudsen number and oscillation frequency. The results are presented in tabular format. The assumption for this model is that the velocity of the oscillation vv0, where v0 is the most probable molecular velocity v0

2kBT0 m

(14.73)

where kB is the Boltzmann constant and m is the molecular mass.

14.4 Viscoacoustic Models At relatively high frequencies, the wavelength in the gas might become comparable with the surface dimensions. Analyzing the squeeze-ﬁlm damping in small air gaps in such a case is still possible, utilizing the viscoacoustic wave propagation model [101–103]. For an air gap, an equation similar to the Reynolds equation can be formed, and again, solved for simple geometries. Such a model considers the viscous, compressible, and inertial force together with a frequency-dependent transition from isothermal to adiabatic thermal conditions.

The reduced narrow-gap equations are in normalized form [101]: g ∂p 1 ∂2 u

2 2 kγ ∂x s ∂z

1 ∂ 2T s2φ2 ∂z2

i

γ 1 p γ

(14.79)

where the shear wave number is s h0

ρ0 ω μ

(14.80)

and φ

μcP κ

(14.81)

is the square root of the Prandtl number, k ωh0/c0 is the reduced frequency, γ cP cV is the speciﬁc heat ratio, dimensionless gap height g h0 a, and surface aspect ratio η b/a. The constants κ, c0, cp, and cv are the thermal conductivity, speed of sound, and speciﬁc heats at constant pressure and constant volume, respectively. The velocity variables u, v, and w are normalized with c0, and the variables p, ρ, and T are normalized with p0, ρ0, and T0, respectively.

14.4.2 Acoustic Reynolds Equation An equation similar to the Reynolds equation can be derived from the narrow-gap equations above. Here, slip boundary conditions have been applied, making the equation better applicable in MEMS applications, such as RF MEMS resonators [98, 104, 105]. g 2 B( s, Kn ) ⎛⎜ ∂ 2 p 1 ∂2 p ⎞ ik ⎜⎜ 2 2 2 ⎟⎟⎟ pw ⎟ ⎜⎝ ∂x ikγ n ( φ s , KT ) η ∂y ⎠

14.4.1 Narrow-Gap Equations

iu

iT

(14.82) where B( s, Kn )

(14.74)

i s (2 is2 Kn ) tanh( i s 2) i s s2 Kn tanh( i s 2)

(14.83)

and g ∂p 1 ∂2 v iv

2 2 η kγ ∂y s ∂z

0

1 ∂p kγ ∂z

(14.75)

(14.76)

⎡ ⎤1 γ 1 ⎢ n(φ s, KT ) 1 B(φ s, KT )⎥ ⎢⎣ ⎥⎦ γ and KT is the thermal Knudsen number KT

g

∂u ⎛⎜ g ⎞⎟ ∂v ∂w

⎜ ⎟

ikρ ∂x ⎜⎝ η ⎟⎟⎠ ∂y ∂z p ρ T

274

(14.77)

(14.78)

(14.84)

2 αT αT

⎡ 2γ ⎤ Kn ⎢ ⎥ ⎢⎣ γ 1⎥⎦ φ2

(14.85)

where αT is the energy accommodation coefﬁcient and γ is the speciﬁc heat ratio. n is the polytropic constant that models the thermal conditions between isothermal and adiabatic.

Gas Damping in Vibrating MEMS Structures

After applying the boundary conditions at the damper borders, solutions of the pressure p(x,y) from Eq. 14.82 are made similarly as for the ordinary linearized Reynolds equation. The major difference here is that now all the coefﬁcients in the solution are complex valued.

14.5 Simulation Tools There are various commercial tools available for numerical simulation of the gas forces in MEMS systems. The tools can be divided into physics-level simulation tools such as FEM solvers, and system-level tools such as circuit simulators. In the following, both of these are brieﬂy discussed.

14.5.1 Physics-Level Numerical Simulation Tools Three categories for numerical physics-level tools can be distinguished, depending on the gap sizes and the aspect ratios between the surface dimensions and the gap, and on the rareﬁed gas conditions: • N–S solver with slip conditions: Continuum or slip conditions are valid, and the aspect ratio is smaller than about 10. • Reynolds solver with effective viscosity and border effect included: Squeeze-ﬁlm analysis is valid for any Kn but the aspect ratio should be larger than 10. • Atomistic solver: Kn 0.1 and the aspect ratio is larger than 10. In the following, these alternatives are analyzed in more detail.

14.5.1.1 Navier–Stokes Solver N–S solver is a very powerful tool in analyzing gas damping phenomena in MEMS structures. But the N–S solver as a general numerical tool is not so tempting in practice as it ﬁrst sounds. This is because the problem size easily grows intolerably large, especially in 3D simulations. This may happen for relatively simple structures, if accurate simulation results are needed. In addition, for accurate simulations, considerable volumes outside the gaps should be included in the simulated volume, further increasing the problem size. The applicability of the N–S solver is also limited by the rareﬁed gas effects. Using slip conditions, accurate simulations result only if Kn 0.1. In analyzing oscillating systems, the harmonic solvers (frequency domain solvers) are much better suited than the transient solvers, where the amplitude and phase information must be extracted after simulations of several cycles with harmonic excitation.

CHAPTER 14

If the oscillation frequency is low, stationary N–S or Stokes solver can be applied. In this case, the excitations are constant velocities. Due to the reduced set of equations, such simulations are faster than the usual N–S simulations. N–S solvers are available in many commercial [106– 108] and public domain [109] FEM tools. To include also the higher frequency acoustic regime, harmonic “viscoacoustic” solvers for the linearized N–S equations are very useful [110].

14.5.1.2 Reynolds Solver The use of the Reynolds solver is a very tempting alternative for squeeze-ﬁlm problems, since the ﬂow problems will be solved in 2D. To extend the validity regime to small gaps and low pressures, the effective viscosity is easy to apply. The accuracy of the results can be considerably improved in many practical structures if non-zero-pressure-boundary conditions are applied, as explained earlier in Section 14.2.2. The tools mentioned above contain the Reynolds solver. In certain structures, e.g., perforated dampers, it is also very tempting to reduce the third dimension and enable simulations in 2D with the augmented Reynolds solver. The augmented solver includes the ﬂow admittance term shown in Eq. 14.49. Such implementations are available at least in Comsol Multiphysics [108] and in Elmer [109]. Two different methods can be applied with the augmented solver: (a) the homogenization method, where the perforations are removed from the simulated 2D topology and Yp is a constant directly calculated from the perforation cell resistance Yp; and (b) the PPR method, where Yp is non-zero only at the apertures of the perforations. In the latter case, Yp excludes the ﬂow resistance in the air gap [96].

14.5.1.3 Atomistic Solvers If Kn is larger than 0.1 and the Reynolds solver cannot be applied, then an atomistic simulation method such as the DSMC method [56] is needed. The DSMC method models gas ﬂow with simulating molecules in probabilistic simulation to solve the Boltzmann equation [50]. The DSMC is a powerful method for simulating high Knudsen number rareﬁed ﬂows in complex geometries [53].

14.5.2 System-Level Simulation Tools To be able to analyze the operation of a whole MEMS device alone or with the interfacing electronics, system and circuit-level tools are available. Gas damping models in such simulation tools may vary from a single resistance to larger circuits with nonlinear resistive and dynamic 275

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Modeling in MEMS

equivalent circuits [2], or VHDL and SIMULINK models [111]. Such models are usually called compact models. These models may have been derived analytically for certain structures, leading to parameterized models; that is, the models are functions of dimensions and gas parameters. Several models presented earlier in this chapter are examples of such models. Alternatively, the models may be based on arbitrary or physics-based mathematical functions, whose parameters have been

ﬁtted using FEM simulations. The perforation cell model in Section 14.2.4 is an example of such a model. Also, model-order reduction methods are usable in reducing the degrees of freedom from meshed FEM or ﬁnite-difference models to much simpler compact models with fewer degrees of freedom. Automated tools are available in building system-level components from FEM simulations [11, 106]. System and circuit simulators and models are also discussed in [84,112–116].

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15

Chapter Fifteen

Introduction to Measuring MEMS Veli-Matti Airaksinen TKK Micronova, Faculty of Electronics, Communications and Automation Helsinki University of Technology, Espoo, Finland

15.1 On MEMS Measurements Silicon-based MEMS technology is a direct offspring of the much larger silicon-integrated circuit technology. The basic fabrication processes, as well as most of the tools and materials, are based on those developed for IC manufacturing. For this reason many of the measurement requirements and techniques are also common with the IC technology. However, the special properties of MEMS devices put a different emphasis on the importance of different parameters and therefore also on the measurement techniques needed. For instance, various electrical measurements are of much smaller importance in MEMS than for ICs. On the other hand, measurements of mechanical properties are naturally much more dominant for MEMS. For a review of the role of measurements in the semiconductor industry, the reader is advised to consult the review by Keefer et al. [1]. Measurements have two main functions, process development and process control. In process development the aim is to optimize the manufacturing process (and device); for process control the goal is to maintain the stability of the process. It should be emphasized that it is usually much more cost effective to characterize the process rather than the product. Maintaining a stable and controllable process will guarantee good products, provided that the basic design is sound. Generally, four different main types of characteristic can be used for process control: material properties, defects, geometry and dimensions of structures, and device operation. Practically every process step will require one or several ways of characterizing some of these key parameters.

In Part III of this book we introduce the main measurement techniques of particular importance to silicon-based MEMS. Because MEMS is mainly concerned with relatively large three-dimensional moving structures, the main emphasis from the device point of view is not on their electrical, but rather the structural and mechanical, properties. Generic techniques that are commonly and widely used outside the MEMS ﬁeld are mostly excluded. These include optical and electron microscopy, atomic force microscopy, and device-scale electrical measurements. In addition, some methods common in mainstream semiconductor processing such as lithography-related critical dimension and overlay measurements are also left out. The main areas that are covered include the following: – properties of silicon substrates and thin ﬁlms

(Chapter 16) – static and dynamic displacement in moving

structures (Chapter 17) – residual stress (Chapter 18) – strength of bonded interfaces (Chapter 19) – focused beam techniques (Chapter 20) – oxygen-related defects in silicon (Chapter 21)

One of the deﬁning characteristics of MEMS processes is that there is no such thing as a generic process. The dimensions and geometries of MEMS devices vary according to the process technology and intended use, leading to a large variation in the fabrication processes. However, the basic materials tend to be the same and are mostly limited to those commonly used in the silicon IC technology.

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A summary of the measurements is given in Table 3.1. As the silicon wafer is the substrate and provides the material for active devices, its properties are of crucial importance for the whole processing sequence. The dimensions and shape of the wafer directly limit achievable size uniformity in the processed structures, and consequently also limit the capability of the manufacturing process. Surface defects and particles have a similar yield-lowering effect as in mainstream IC-manufacturing, leading to very tight limits on the quality and cleanliness of the wafer surface. The measurements used to characterize silicon wafers are discussed in Chapter 16. Interstitial oxygen and larger oxygen precipitates formed during thermal treatments affect signiﬁcantly the mechanical properties of the wafer, as well as its behavior in wet etching. The different ways to characterize oxygen and related defects are covered in Chapter 21 (Table 15.1). Wafer bonding has become important for MEMS processing due to the increasing use of silicon-on-insulator (SOI) wafers. Wafer bonding is also commonly used for the hermetic packaging of devices. Key issues for bonding include thickness and uniformity of the SOI layer, bonding strength, and possible voids in the bonded interface. The various ways to characterize these parameters are discussed in Chapters 16 and 19. Thin ﬁlms are used as insulators or conductors, as sacriﬁcial layers for releasing moving structures, for masking layers in lithography and etching, or as active device layers. Thin ﬁlm materials range from insulating oxides and nitrides to metals and silicon itself. The most important measurements are those for layer thickness and uniformity, stress and strain, and optical properties; these measurements can be found in Chapters 16 and 18. The main characteristic of MEMS devices is that they invariably include one or several moving parts, usually cantilevers, beams, or membranes of various shapes, thicknesses, and lateral dimensions. Etching is one of the key process steps for the fabrication of such structures. Self-terminating etching processes with the help of etch-stop layers preferably are used; however, this is not always possible. In such cases precise control of the etching process can be of crucial importance, necessitating the accurate measurement of the depths of etched trenches and etching rate variations. For devices, the key issues for metrology include measuring the dimensions, deﬂections, and motion of such structures. The techniques for these measurements are described in Chapter 17. Chapter 20 introduces dual-focused beam techniques for the modiﬁcation and destructive testing of MEMS structures. These relatively new techniques allow electron beam imaging of the structures while they are simultaneously being milled with a focused ion beam, 284

thus enabling three-dimensional device structures to be characterized with extremely high resolution.

15.2 Variation and Mapping There are several possible measurement strategies. For process monitoring, one can either use separate test wafers or measure directly from product wafer. Test wafers generally affect process throughput and increase the cost. However, in many cases their use cannot be avoided, because measurements suitable for product wafers do not exist. For device characterization, either one can use special test structures, or in some cases the properties of actual devices can be tested. If sufﬁciently fast non-destructive methods exist, one can measure multiple sites on every wafer. For reasons of cost, 100% inspection of wafers is normally economical only when the measurement is non-invasive and the throughput of the measuring equipment is very high, allowing the inspection of perhaps 100 or more wafers per hour. Often this requirement is not met and sampling is necessary. If the measurement is slow or destructive, only a few locations on some of the wafers can be tested. For a given measurement to be useful, it is important that the data produced are comparable with different operators, at various locations, using different equipment. The capability of the measurement can be a severe limitation for the achievable capability of the process. For accurate control, the variability of the measurement must be much smaller than the variation of the process itself. Therefore, the analysis of the measurement system itself forms an important part of process control. The key parameters describing measurement system performance are precision and accuracy. Precision describes the inherent variability of the measurement and consists of two parameters: repeatability and reproducibility. Repeatability is the short-term variation of the measurement when it is repeated with a single sample several times during a short period. Reproducibility is the variability of the average values when measured by several different operators, possibly using different instruments. Any type of characterization that involves subjective inputs by the operator will have poor reproducibility. A good example of this situation is given by various types of visual inspection. Accuracy (also called bias or error) describes the ability of the measurement to produce results that are close to “true” values: It is deﬁned as the difference between the average of many measurements and a known reference value. Also of interest is the stability of the measurement, i.e., how much accuracy drifts over longer periods. The procedure for the determination of these parameters is called a gage repeatability and reproducibility (R&R) study or

Introduction to Measuring MEMS

CHAPTER 15

Table 15.1 Metrology and parameters covered in this book

Object

Monitored processes

Parameters measured

Wafer/process properties described

Effects on device, processing

Measurement Chapter techniques

Silicon wafer

Crystal growth

Resistivity

Doping level and type conductivity

Electrical contacts

4-point probe

Crystal growth

Oxygen concentration

Oxygen concentration, and oxygen-related defects

Wet etching, wafer Eddy current hardness Size variation of etched FTIR structures, lithography SIRM

Slicing, lapping, polishing, and cleaning

Wafer thickness, diameter

Accuracy of slicing and lapping

Device uniformity, yield

16 21

Capacitive probe 16

Wafer shape: bow, warp, Effectiveness of polishing thickness variation and cleaning Surface defects, particles Wafer bonding

Roughness Thickness

Grinding and polishing process Quality of bonding

FTIR

16

18 FTIR, acoustic microscopy, bonding strength measurements

Voids Bonding strength Thin ﬁlms

Layer thickness Deposition, oxidation, grinding and polishing, etching

Deposition/oxidation rate Removal rate in polishing, grinding, or etching

Size and size variation of structures

Removal rate

FTIR

16

Reﬂectance

Etch rate and uniformity Deposition

Optical constants

Stability of deposition process (composition, structure)

Distortion of structures Chemical composition

Ellipsometry

16

Deposition, ionimplantation

Resistivity

Doping level, dose

Termination of wet etching, distortion of structures

4-point probe, CV

16

Proﬁlometry

18

Residual stress

Interferometry 3D structures Devices

Lithography, Height deposition, etching Residual stress

Deposition process, etch selectivity

Size and shape of structures

Proﬁlometry

16

Height, width, length

Size and shape

Dimensions of moving structures

Optical interferometry

17

Deﬂations

Deﬂections

Motion

Resonant frequencies

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measurement system analysis (MSA) [2]. The determination of accuracy requires the use of standard samples, which can be traced back to primary standards. Unfortunately, such standards do not exist for all measurements. However, for many purposes, good accuracy is not even needed as long as the measurement has sufﬁcient precision and stability. These can be determined with suitable internal standards. For a stable manufacturing process, one needs to characterize and control the variability of the measured characteristics. For this purpose, it is useful to consider several different types of variations: – Within-wafer variations – Wafer-to-wafer (or within-batch) variations – Batch-to-batch variations

Within-wafer variation describes the variability between different sites on the same wafer. This type of variation describes the spatial uniformity of a given process step (or steps), as the whole wafer surface is generally processed either simultaneously or at least during a very short period. In order to quantify within-wafer variation, one naturally needs to do the measurement at several different sites on the wafer. The choice of sites should be such that the whole wafer can be characterized with as few measurements as possible. For many slow measurements, either 5 or 9 sites is considered a suitable number. Within-wafer variations (R) have two different deﬁnitions according to SEMI standards [3, 4]. SEMI M2 -1296 : R (max min)/ average SEMI M11- 0697: R (max min)/(max min) The 5-point calculations used in SEMI deﬁnitions will not in general produce the correct mean value and may also grossly underestimate within-wafer variations. Naturally, the measurement will describe the layer better if the number of measurement points is increased and if all values are used in the calculations. Already with 17 measurement points one can often reach very satisfactory results [5]. Wafer-to-wafer variation is commonly deﬁned as the variation of the within-wafer center value, or average value. For demanding applications, one can also use the standard deviation of all measured points on all wafers. The edge of the wafer can signiﬁcantly affect the results of many measurements. To prevent spurious results due to edge effects, sites that are too close to

286

the edge are excluded. For smaller wafers, this edge exclusion has been quite large, for instance, 12 mm in the Semi M11 standard. For cost reasons, there is a tendency to reduce the edge exclusion zone, 3 mm being a common value for 200 mm wafers.

15.3 MEMS Measurement Challenges Many MEMS measurement needs are related to material and processing problems. There still exist quite a few issues for which good measurement solutions do not yet exist. These include thin-ﬁlm properties and particularly surface, dimensional, and shape measurements of processed structures [6]: – Through-ﬁlm stress gradient before release. – Surface properties: friction, stiction, and surface

charge on processed device structures. – Dimensional and shape of side walls in high aspect

ratio structures. Thin ﬁlms often tend to have relatively high internal stresses. Compressive stress easily causes buckling of the released thin-ﬁlm structure, so tensile stress is preferable. In addition, the vertical stress gradient within the ﬁlm should be low to prevent deﬂection. The mapping of thin-ﬁlm stress gradient prior to release would be of substantial beneﬁt in quick identiﬁcation of processing-related problems. As MEMS devices are reduced in size and capacitive coupling gaps are reduced, surface effects become more prominent. In particular, surfaces may gradually accumulate charge even within the packaged device, leading to changes in operating characteristics or possibly to stiction problems. Surface charge is related to the chemical composition of the surface. Therefore, techniques for the characterization of either the charge state or the chemical composition of surfaces would be needed. Many silicon MEMS devices include deep-etched structures with very high aspect ratios. The characterization of the shape and dimensions of such structures can be very challenging. Conventional stylus proﬁling is generally unsuitable due to the large depth and narrow lateral extent. Optical proﬁling works better for deep structures, but even these techniques lose their effectiveness when the gaps become too narrow.

Introduction to Measuring MEMS

CHAPTER 15

References 1. M. Keefer, R. Pinto, C. Dennison, J. Turlo, The role of metrology and inspection in semiconductor processing, in: K. Seshan (Ed.), Handbook of Thin Film Deposition Processes and Technologies, second ed., Noyes Publications, 2002 (Chapter 6). 2. AIAG, Automotive Industry Action Group, Measurement Systems Analysis (MSA) Reference Manual, 1994. 3. Semi, Semiconductor Equipment and Materials International, Semi M2-

1296, Speciﬁcations for silicon epitaxial wafers. Book of SEMI Standards (1997), 1997a. 4. Semi, Semiconductor Equipment and Materials International, Semi M110697. Speciﬁcations for silicon epitaxial wafers for integrated circuit (IC) applications. Book of SEMI Standards (1997), 1997b. 5. V.-M. Airaksinen, Epitaxial layer characterization and metrology, in: D. Crippa, D.L. Rode, M. Masi (Eds.),

Silicon Epitaxy, Semiconductors and Semimetals, vol. 72, New York, Academic Press, 2001 (Chapter 7), p. 232. 6. M. Da Silva et al., Workshop on Metrology Needs for Micro/Nano Technologies, Pittsburgh, PA, September 22, 2005.

287

16

Chapter Sixteen

Silicon Wafer and Thin Film Measurements Veli-Matti Airaksinen TKK Micronova, Faculty of Electronics, Communications and Automation, Helsinki University of Technology, Espoo, Finland

16.1 Important Measurements

In silicon MEMS the silicon wafer provides both the substrate and the material for the active device layer. Additionally, polished silicon wafers are often bonded on the processed wafers to form hermetically enclosed pack ages. Mainly three types of wafers are used: polished bulk, epitaxial, and silicon-on-insulator (SOI) wafers. If device processing is performed from the top side only, single side polished wafers are sufﬁcient. It is quite common, though, to process the wafer from both sides; in these cases double-side polished (DSP) wafers are used. Polished bulk wafers are essentially uniform through out, and membrane or cantilever structures are proc essed on these wafers either by depositing thin ﬁlms or with the help of very accurately controlled etching proc esses. Epitaxial and SOI wafers contain multiple layers that provide the active layers needed for the devices, as well as etch-stop layers for accurate, easily controllable etching processes. The most important wafer characteristics are shown in Table 16.1. For each type of wafer the main requirements are sufﬁcient thickness uniformity of the substrate and of the possible device layer, as well as a low defect density. In addition, the electrical resistivity of the wafer needs to be sufﬁciently close to the requirements. MEMS device processing requires a smooth, polished wafer surface; suf ﬁciently ﬁne surface roughness is particularly important for successful wafer bonding. MEMS structures typically contain thin dielectric and conducting ﬁlms. The characterization of these is often

based on methods similar to those used on silicon wafers, particularly for measuring thickness, electrical resistivity, and surface quality and roughness. These measurements are also covered in this chapter. However, the important subject of stress measurements is treated separately in Chapter 18. Likewise oxygen measurements of silicon wafers are discussed in Chapter 21. The purpose of this section is not to cover the many techniques in depth. Instead, the reader is directed to the many excellent reviews on measurements published else where. In particular, Schroder [5] provides good reviews of many of the basic measurements. SEMI Standards pro vide accurate descriptions of several widely used meas urement techniques of silicon wafers, including resistivity [4], wafer geometry [1], surface roughness and quality [19], as well as oxygen and carbon content.

16.2 Wafer Shape The shape of the silicon wafer can have a big impact on several fabrication processes and product yield. Ideally the wafer is a perfectly round and ﬂat disk of uniform thickness with the edges rounded to the desired proﬁle. While wafer diameter is usually not an issue, the wafer does deviate from the ideal shape to some extent due to deformations and thickness variations. Wafer ﬂatness is deﬁned as the variation of wafer thickness relative to a reference plane. The ﬂatness of the wafer can be described either by a global ﬂatness value or as the maximum value of site ﬂatness. The reference 289

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Table 16.1 Important wafer characteristics and measurement techniques

Characteristics

Parameters

Measurements

Wafer geometry

Wafer thickness

Capacitive

Wafer warp, bow, and ﬂatness Thickness of thin ﬁlms

Resistivity

Defects

Thickness of epitaxial layer(s), SOI

FTIR

Thickness of dielectric layers

ellipsometry, reﬂectance

Wafer resistivity

4-point probe, Eddy current

Resistivity of epitaxial layer

4-point probe, CV, SRP

Resistivity of SOI and thin ﬁlms

Same as wafer

Surface defects and particles

Laser scanning

SOI interface defects (voids)

Acoustic microscopy

Microroughness

Laser scanning

Oxygen/bulk micro defects

FTIR Wet etching, SIRM, OPP

plane can be chosen in several different ways, depending on the parameter measured:

(a) tmin

tmax

– three points at speciﬁed locations on the front surface TTV = tmax – tmin

– least square ﬁt to the front surface – least square ﬁt to the median surface (middle of wafer)

(b) Median surface Bow

– least square ﬁt to the back surface – ideal, straight back surface (where the wafer is

pulled straight against a ﬂat chuck) The deﬁnitions of the most common deviations are shown in Figure 16.1. They are total thickness variation (TTV), bow, and warp. These and other shape param eters are deﬁned in the SEMI standards, which also give detailed instructions on measurements [1]. Non-idealities in wafer shape can affect the capability of several device processing steps, including etching, bonding, and lithog raphy. For instance, TTV has a direct effect on the thick ness of the membrane obtained by through-wafer wet etching, and so may have a major inﬂuence on the prop erties of the resulting device. Bow and warp often are exacerbated during wafer processing due to additional residual stresses. For this reason, specifying the maximum allowable values of these parameters is of considerable importance. Wafer shape is characterized with non-contact capaci tive scanners, which are capable of measuring the thick ness and shape of the rotating wafer at high speed. The wafer is located between two probes. The distance between these probes is accurately known, and the gap between the wafer and the probes is obtained from the capacitance at each measurement point. For warp and 290

3-point reference plane (c)

Reference plane

Warp

Median surface

Fig 16.1 ● Basic deformations of silicon wafers (exaggerated): thickness variation (a), bow (b), warp (c).

bow measurements the wafer should not be distorted by the measuring process, and therefore has to rest freely on the chuck. For accurate measurement of the thick ness proﬁle, the wafer can be pulled into contact with the lower electrode. The capacitive measurement is very fast, and complete mapping of the wafer shape is accomplished in a few seconds. This instrument can also provide quantitative residual stress measurements of uni form layers because stress affects the shape of the wafer by inducing additional bow. Capacitive measurements

Silicon Wafer and Thin Film Measurements

CHAPTER 16

Table 16.2 Wafer shape parameters

Parameter

Global/local

Explanation

Reference plane

RPD Reference plane deviation

G or L

Deviation of wafer surface relative to the reference plane.

Any.

FPD Focal plane deviation

G or L

Deviation of focal point from wafer surface.

Any.

TIR Total indicator reading, Total indicator runout

G or L

Smallest distance of two planes, parallel to the reference plane, enclosing between them all points of the front surface.

Any.

GBIR Global back surface referenced ideal range

G

Maximum variation of wafer thickness.

Ideal ﬂat back surface.

TTV total thickness variation

G

Old name for GBIR.

Sori

G

Difference of maximum positive and negative deviations of the front surface from reference plane.

Least square ﬁt to front surface.

SBIR Site backside referenced ideal range

L

Maximum thickness variation within site.

Ideal back surface.

LTV Local thickness variation

L

Old name for SBIR.

SFQR Site front-side referenced least squares range

L

Range of the positive and negative deviations from the front surface.

Least square front plane for the site area.

Warp

G

Range of distances of the median surface from the reference plane (unclamped wafer).

3 points, or least square ﬁt to backside.

Bow

G

Deviation of center point of median surface relative to the reference plane (unclamped wafer, ½ of wafer thickness subtracted).

3 points, or least square ﬁt to backside.

have also been used successfully for determining thick ness proﬁles of conducting layers deposited on the wafer (i.e., epitaxial or polysilicon layers), or material removal from the wafer (for instance, by etching or polishing). For such uses the wafer has to be measured before and after processing, and the change in thickness is obtained by subtraction of the results (Table 16.2).

16.3 Resistivity In order to achieve the desired electrical characteristics, silicon is doped either n-type (As, P, or Sb doping) or p-type (B doping). Typical concentrations of dopant atoms vary from 1014 cm�3 up to 2 � 1020 cm�3; that is, from about 2 � 10�7% to 0.4%. More typically the doping level is given as the corresponding electrical resistivity, which better describes the behavior of the material in electrical circuits. Resistivity is determined by the concentration

of mobile charge carriers in the material, as well as their mobility μ (ability to move in an electric ﬁeld). As shown in Eq. 16.1, the resistivity ρ is roughly inversely propor tional to the concentration of the free carriers (n). ρ�

1 q�μ�n

(16.1)

Here q � unit charge, a constant. Mobility μ is not constant, however, but depends slightly on n, and empir ical parameters are needed for the conversion between carrier concentration and resistivity [2, 3]. Resistivity is a characteristic of bulk material. For con ducting thin ﬁlms, resistivity is often given as sheet resist ance Rs, which is simply resistivity averaged over the layer thickness, t: Rs �

ρ t

(16.2)

291

292

Table 16.3 Comparison of different techniques for measuring carrier concentration and resistivity

Noncontact measurements

Mercury probe– capacitance voltage (Hg–CV)

Spreading resistance roﬁling (SRP)

Eddy current gauge

Air-gap surface photovoltage (SCP)

Air-gap surface photovoltage CV (Epimet)

Parameter measured:

Sheet resistance

Carrier concentration

Resistivity

Resistivity

Carrier concentration

Carrier concentration

Precision/accuracy:

Excellent/good

Good/excellent

Poor

Good

Good/excellent

Excellent/good

Sample damage:

Damaged surface

No damage, possible contamination

Locally destructive

No damage

No damage

No damage

Speed:

Moderate

Poor

Very slow

Very high

Very high

Moderate

Mapping:

Yes

Coarse mapping

No

Yes

Yes

Limited

Depth proﬁling:

No

Moderate depth

Unlimited depth

No

No

Moderate depth

Advantages:

Simple to use

Depth proﬁling

Unlimited depth proﬁling

Fast

Fast

Fast

Large resistivity range

No sample preparation

No sample damage

Depth proﬁling

No sample damage

Large resistivity range

No sample damage

Fast

Usually no sample preparation Suitable for:

Bulk; thin ﬁlm if insulated from substrate

Bulk or thin ﬁlm near surface

Both bulk and thin ﬁlms

Bulk

Bulk or thin ﬁlm near surface

Bulk or thin ﬁlm near surface

Mainly used for:

Bulk wafers

Epitaxial layers

Epitaxial layers

Bulk wafers

Epitaxial layers

SOI

Bulk near surface

Bulk or Epitaxial layers (near surface)

Milling

No preparation

Surface passivation

(Surface passivation)

Suitable for bulk measurements only

Does not work for highly doped wafers

Does not work for highly doped wafers

Epitaxial layers Thin ﬁlms Sample preparation:

Chemical cleaning

Surface passivation

Sample limitations:

Thin ﬁlms require insulating substrate, or pn-junction

Does not work for highly doped wafers

Measuring MEMS

4-point probe (4-pp)

PA R T I I I

Contact measurements

Silicon Wafer and Thin Film Measurements

Sheet resistance is formally given in units of ohm, but usually its value is given as “ohms per square” (Ω/�) because sheet resistance is identical to the resistance of a square of any size made of the thin ﬁlm. If the ﬁlm thickness is known, sheet resistance can be converted to resistivity, and vice versa. The most important ways of measuring resistance and carrier concentration are the four-point probe (4-pp), mercury probe capacitance-voltage measurement (Hg– CV), spreading resistance proﬁling (SRP), and eddy current measurement. In addition, two optical non contact measurements have gained some importance in recent years. The properties of these measurements are compared in Table 16.3. The main limiting factor differ entiating the various techniques is the residual damage caused to the wafer by the measurement. Clearly the non-contact methods have an advantage in this respect. A short description of each method follows. For fur ther details the reader should refer to the references.

16.3.1 Four-Point Probe The 4-pp uses four sharp probes arranged in a linear array. A known current (I) is injected between two probes, and the resulting voltage drop (V) is measured with the other two probes. 4-pp is used to measure the sheet resistance of bulk wafers and thin ﬁlms, including epitaxial layers. The main limitation of 4-pp is that for thin ﬁlm meas urements the current has to be conﬁned within the layer, usually requiring an insulating layer or junction under neath to prevent current leakage through the substrate. 4-pp measurements are explained in SEMI standards. (See Ref. [4]; for a good summary see Ref. [5].) In the usual case where four in-line probes are used to measure a very thin sample, the sheet resistance of the layer is simply proportional to the ratio of voltage and current. ⎛ V ⎞ ρs � C � ⎜⎜ ⎟⎟⎟ ⎜⎝ I ⎠

(16.3)

The proportionality constant C is dependent on the probe geometry and also requires corrections—for edge effects, lateral sample dimensions and thickness—which are automatically calculated by the instrument. Standard wafers have to be used for the calibration of the instru ment. The average resistivity, ρ, of the layer can be cal culated directly by multiplying sheet resistance and layer thickness (Eq. 16.2). Layer thickness must be known accurately. The 4-pp is best suited for the measurement of fairly thick, low resistivity layers. Blunt probes and a small probe force must be used for thin layers (thickness less than a few microns) in order to avoid pressing the probe tips through the layer into the substrate. In any case, the probe tips will scratch the surface of the wafer.

CHAPTER 16

A V

Wafer

Fig 16.2 ● Principle of the 4-pp measurement.

If accurate resistivity mapping is required, thickness var iations of the thin ﬁlm should be taken into account by using local thickness in Eq. 16.2. Another limitation is the possibility that the thickness of the electrically con ducting layer may differ from the metallurgical thickness [6]. 4-pp can be used in a true mapping mode to meas ure several tens of points per wafer, as each point takes only a few seconds (Figure 16.2).

16.3.2 Mercury Probe–CapacitanceVoltage Measurement In Hg–CV a metal-semiconductor Schottky-diode is formed by pressing a capillary ﬁlled with mercury against the semiconductor surface [5]. The instrument measures the capacitance of the depletion region and the concen tration of ionized dopant atoms, N, at the depth W is calculated from the voltage dependence of capacitance: N(W ) �

constant ⎡ d ⎛ 1 ⎞⎤ ⎜ ⎟⎟⎥ A2 � ⎢ ⎢⎣ dV ⎜⎜⎝ C 2 ⎟⎠⎥⎦

(16.4)

Due to the strong dependence of N on the junction

area, A, the area has to be determined and maintained very accurately. Limited depth proﬁling is achieved by changing the bias voltage, V. The main advantage of Hg–CV is that it allows quick, non-invasive depth pro ﬁling combined with a limited mapping capability. The method works with both bulk wafers and thin ﬁlm struc tures. Hg–CV can be used to measure resistivities in the range of 1–100 ohm-cm (corresponding to carrier con centrations 1014–1016 cm�3). Surface leakage currents are the most common cause of problems in CV, usually requiring some type of surface conditioning prior to the measurement. An additional advantage of Hg–CV is that it can be used to monitor the permittivity and thickness of dielectric materials. Hg–CV does not damage the sample, but possible mercury contamination is an issue. 293

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16.3.3 Spreading Resistance

The SRP measurement is the method of choice for pro ducing accurate resistivity proﬁles in the vertical (depth) direction [4]. Most typically SRP is used for characterizing multilayer structures, for instance epitaxial layers, or areas doped by implantation or diffusion. SRP is an invasive technique because a wedge-shaped sample must be pre pared, usually by angle lapping so that the bevel extends beyond the layer-substrate interface. The resistance between two probes is measured at different locations along the lapped surface. The resistance is proportional to the resistivity of the underlying material. The propor tionality has to be calibrated by comparison with uniform calibration samples. Thickness scale is obtained from the accurately measured bevel angle (Figure 16.3). The measured resistance data must be converted to a resistivity proﬁle with a layer-by-layer algorithm. To pro duce correct results, proﬁling usually should reach all the way to the bulk silicon. A typical SRP proﬁle is plotted in Figure 16.4. For maximum accuracy, calibration meas urements have to be done frequently. SRP is operator

R

dependent, and good reproducibility is difﬁcult to main tain. Also, resistivity mapping with SRP is impractical. SRP allows resistivity measurements over a very wide range (0.0005–2000 ohm-cm) and is a very useful tech nique for the measurement of transition widths in n/N� and p/P� structures, autodoping proﬁles on patterned wafers, and layer thicknesses and resistivity proﬁles in multilayer structures.

16.3.4 Eddy-Current Gauge Sheet resistance measurements of bulk silicon wafers are commonly done with an eddy-current gauge. An induc tive circuit generates a high frequency magnetic ﬁeld, which causes circulating eddy-currents in the wafer. These currents cause a power loss, which is detected by the gauge and is used to calculate sheet resistivity [5]. No physical contact between the sensor and the wafer is needed. The accuracy of the resistivity measurement is dependent on the distance between the sensor and the wafer surface. The calibration is done using calibra tion standards and depends on the frequency of the AC magnetic ﬁeld. The operational measurement range is limited to sheet resistance values under about 5 ohms, corresponding to a resistivity of 0.15 ohm-cm for a 300 μm-thick wafer.

16.3.5 Surface Photovoltage

Conducting layer

Substrate

Fig 16.3 ● Principle of the spreading resistance measurement.

Fig 16.4 ● Spreading resistance depth proﬁle of a highly doped epitaxial etch stop layer sandwiched between a low doped epitaxial layer and silicon substrate.

294

Two types of instruments based on the non-contact resistivity measurement based on surface photovoltage (SCP) are currently available: air-gap AC surface photo voltage (SCP) and air-gap AC surface photovoltage CV (Epimet). The SCP is based on an optical technique for the meas urement of dopant concentration [7, 8]. A modulated, low-intensity beam of light generates mobile charges near the semiconductor surface, thus causing a small SCP, which is detected by an electrode positioned above the wafer. From the measured photovoltage the surface deple tion width is determined and the concentration of ionized dopant atoms can be calculated. SCP is a very fast meas urement allowing full wafer mapping without any edge exclusion. SCP is well suited for the measurement of high resistivity layers up to and above 1000 ohm-cm. The low resistivity limit of about 0.01 ohm-cm is set by the requirement that the semiconductor is non-degenerate. The disadvantage of the method is that depth proﬁling is not possible. Also, the wafer surface must be brought to strong inversion with correct surface treatment. Air-gap ac-SPV CV is a combination of capacitance voltage measurement and SCP. The commercial instru ment is called Epimet; see Ref. [9]. The electrode is brought very close to the wafer surface, and a bias voltage

Silicon Wafer and Thin Film Measurements

is connected between the electrode and the wafer. The sample is excited with modulated light, and the deple tion width is obtained from the ac photocurrent signal. Epimet has a limited proﬁling range and also requires a large edge exclusion. The major drawback is the relatively slow measurement, which makes mapping impractical. However, Epimet can measure wafers without surface treatment.

16.4 Thickness of Thin Films 16.4.1 Reﬂectance Measurements and FTIR Optical reﬂectance measurements are widely used for measuring metallic, semiconductor, and dielectric layers. In principle these measurements can provide a wealth of information and can be used to determine the following: – Layer thicknesses – Indices of refraction – Absorption coefﬁcients

CHAPTER 16

and the bottom of the silicon layer. Therefore, a rela tively high reﬂectivity is needed at the layer/substrate interface. In SOI wafers the reﬂectivity is always sufﬁ cient, but for epitaxial layers a highly doped (low resis tivity) substrate is required. As sketched in Figure 16.5, the main part of the infrared beam is reﬂected from the wafer surface and a small part from the bottom interface of the layer. As the length of the interferometer arm changes, constructive interference occurs at different positions for the beam reﬂected from the surface and for the beam reﬂected from the interface. The resulting spectrum has intense central peaks caused by the reﬂec tion from the wafer surface and weaker “sidebursts” due to the reﬂection from the interface. The thickness of the silicon layer is obtained directly from the separation of the two sidebursts. FTIR is a reliable technique with good precision. Its accuracy is limited by the lack of suitable reference wafers. Because the sidebursts have a complicated shape, their exact location can be difﬁcult to determine, especially for thin layers. To avoid these problems, the interferogram can be transformed into a reﬂectance spectrum. The thickness of the silicon layer can be obtained by ﬁtting a calculated spectrum to the experimental result [11].

– Surface roughness and damage – Porosity – Composition – Crystallinity – Wafer curvature

Measurements can be made with monochromatic light, or over a broad range of wavelengths, even spanning the entire spectrum from near ultraviolet to the infrared. A single angle or multiple angles of incidence can be used, ranging from normal (perpendicular to the surface) to grazing incidence (almost parallel to the surface). The light may be either unpolarized or polarized, and in addi tion to intensity, the polarization of the reﬂected light can be analyzed. Some instruments are also capable of meas uring the power spectral density (PSD) of the reﬂected radiation. The determination of any of the parameters previously listed requires ﬁtting the measurement results to a physical model of the optical properties (i.e., dielec tric function). For structures containing multiple layers, compositional gradients, roughness, or porosity, the ﬁt ting of such models is complicated and ambiguous. The Fourier transform infrared reﬂectometer (FTIR) is commonly used for measuring the thickness of rela tively thin silicon layers, for instance SOI or epitaxial layers. FTIR is based on a Michelson interferometer that contains one moving and one ﬁxed mirror [10]; for a block diagram of a Michelson interferometer, see Figure 17.3 in Chapter 17. FTIR takes advantage of the inter ference of the beams reﬂected from the wafer surface

16.4.2 Ellipsometry Ellipsometry is a very sensitive, non-destructive optical reﬂectance measurement with unequaled capabilities for thin ﬁlm metrology. As the optical properties of thin ﬁlms are affected by the composition, thickness, conductivity,

Fig 16.5 ● Principle of layer thickness determination by reﬂectance measurement with an FTIR.

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and porosity, ellipsometry can provide information on all of these parameters. The principle of ellipsometry is sim ple: The change in the polarization of light reﬂected from the sample surface is measured by taking the amplitude ratio of two perpendicularly polarized beams. The angle of incidence can be varied. For isotropic, non-absorbing layers the measurement is usually done by using a single wavelength (for instance with a HeNe laser at the wave length of 632.8 nm). More complete characterization of complex structures can be achieved if the wavelength is scanned over a broad range (“spectroscopic ellipsom etry”) from ultraviolet to the infrared. For a review of ellipsometry, see Ref. [12]. Because ellipsometry is based on the ratio of two measured values, it is very accurate, and reproducible. It is relatively insensitive to scatter and ﬂuctuations, and requires no standard sample or reference beam. When the measured data are ﬁtted to a physical model of the layer, the refractive index, absorption coefﬁcient, and thickness of the layer can be determined. Single layers or even complex, multilayer stacks with thicknesses ranging from nanometers to microns can be measured. However, the ﬁtting may be quite complicated for non-uniform, multilayer structures. A special feature of ellipsometry is that porous layers can be included in the model, allowing the porosity of extremely thin layers to be determined (Figure 16.6).

16.4.3 Proﬁlometry A proﬁlometer is an instrument used to measure the height proﬁle of a surface in order to quantify its rough ness or shape. Typically proﬁlometers are used for checking the heights of structures such as steps, ridges, or trenches formed on the wafer during processing. The achievable vertical resolution is in the nanometer level, though lateral resolution tends to be poorer. There are two main types of proﬁlometers: contact and optical (non-contact).

Contact Proﬁlometers In a contact proﬁlometer a sharp stylus is pressed verti cally against the sample surface with a controlled force and moved laterally across the sample. Both the vertical and lateral positions of the stylus are recorded during the scan, producing a graph of small surface variations in the vertical direction as a function of position. A typical proﬁlometer can measure small vertical features ranging in height from 10 to 65000 nm. The horizontal resolu tion is affected by the radius of the stylus, which can range from 5 μm to about 25 μm, as well as scan speed, scan length, and steep slopes. Therefore, very small and high features cannot be reproduced accurately. Due to the mechanical contact between the stylus and sub strate, only reasonably hard samples can be measured. Contact proﬁlometers are among the most common and basic instruments used in microfabrication. Their advan tages include ease of use and affordability. The main dis advantages are slow measurement, which precludes the measurement of large areas, and the mechanical contact between the stylus and sample causing possible contam ination or damage to the sample surface.

Optical Proﬁlometers An optical proﬁlometer is a non-contact method for pro viding much of the same information as a stylus-based proﬁlometer. There are many different techniques cur rently being employed, such as vertical scanning interfer ometry, phase interferometry, confocal microscopy, and digital holography. The main advantages of optical pro ﬁlometers are low damage, speed, and resolution. Because the measured surface is not touched by a mechanical probe, the sample is not damaged and very high measure ment speeds can be reached, allowing mapping of large areas. The lateral resolution is mainly limited by the spot size and can be an order of magnitude better than that for contact proﬁlometers [13].

16.4.4 Contamination and Surface Quality Automated Surface Inspection

Fig 16.6 ● Principle of an ellipsometer. Polarized light strikes the sample, and the change in polarization is analyzed. Angle of incidence, φ, can be variable.

296

Instead of being perfectly ﬂat and clean, the wafer sur face tends to contain imperfections consisting of rough ness, defects, and contaminants. All of these may affect critical fabrication processes, for instance lithography, thin ﬁlm deposition, etching, and—particularly in MEMS processing—wafer bonding. Surface roughness, as well as defects and particles on the wafer surface, are all detected and measured with optical methods. Large surface defects and particles can be detected with visual inspection and identiﬁed with microscopy. These labor intensive techniques are of limited use in a production

Silicon Wafer and Thin Film Measurements

environment, however, and automated inspection has to be used. Scattering of light from the silicon surface is used to measure the number and size of particles and to identify surface defects [14, 15]. Automated optical scanning surface inspection systems (SSISs) have been developed for this purpose. SSISs also provide defect site coordinates, which other defect review and inspec tion equipment can use to locate defects for further analysis. For particle measurement the SSISs are cali brated by using polystyrene latex spheres (PSL). The sizes of irregular particles are classiﬁed as PSL equiva lents, and the actual physical size of a particle may dif fer considerably from the PSL equivalent value. Laser scatterometry also provides information on the micro roughness of the surface [16]. A schematic of an SSIS is shown in Figure 16.7. Basically the scanner has a laser light source, a mechanism to scan the focused beam over the wafer surface, and vari ous detectors. Normal or oblique incidence and different polarizations (s, p, or circular polarization) can be used for the incident laser beam. Three different parts of scattered and reﬂected light can be measured to gain information about the surface quality: the directly reﬂected, specular, beam (usually called “bright ﬁeld”); diffusely scattered light (“dark ﬁeld”); and backscattered light. Intensity, polarization, and direction of the reﬂected light can be measured. The direct, specular reﬂection dominates on a polished wafer. Surface structures such as steps or mounds cause slight changes in the intensity and direction of the specular beam, which can be used to identify cer tain surface defects. Surface defects and microroughness scatter light diffusely into the dark ﬁeld detector. It is also possible to collect light scattering into large as well as small angles and to use this information for further

classiﬁcation of defects. Subsurface defects scatter light efﬁciently towards the light source, and this backscat tered light can be used to identify such defects.

16.4.5 Microroughness Surface roughness can have an adverse effect on wafer bonding; therefore, it is important to characterize the wafer surface prior to this critical process step. Microroughness is usually given either by the root-mean-square (rms or Rq) value or by the average (Ra). Rq is the standard deviation of topographical deviations. Ra is the average deviation of the surface height from the mean level [17]. Roughness depends on the scale in which the measurement is made. For microroughness this spatial frequency range can be somewhere from 0.01 to 100μm�1. The results of dif ferent measurement techniques are directly comparable only if their spatial frequency ranges are identical. Because roughness depends on the spatial frequency scale, a full evaluation requires the measurement of the PSD function which describes how roughness depends on the spatial fre quency over all length scales of interest. Rq is essentially the integral of the PSD function [18, 19]. Due to the effect of different crystallographic orientations of silicon on processes such as polishing and etching, the topography of the wafer surface is non-isotropic and PSD should be evaluated in two perpendicular directions. There are several commonly used alternatives for measuring microroughness: stylus proﬁlometry [20], scanning probe microscopy, optical proﬁlometry, or laser scatterometers (SSISs). The most popular way in a pro duction environment is scattering measurements with an SSIS, because the roughness information is obtained

Dark-field detector Backscattered

light detector

Bright-field detector Laser source Scattered beams

CHAPTER 16

Fig 16.7 ● Principle of a surface scanning inspection system. Many different conﬁgurations are possible, with the incoming beam either normal or oblique, multiple dark ﬁeld detectors of various sizes and positions, and split bright-ﬁeld detectors capable of measuring minute changes in the direction of the specular beam.

Specular beam

Wafer

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at the same time as the wafer is inspected for surface defects and particles. In the scattering measurement the non-specular, low-intensity light is collected over a large range of scattering angles. If there are no par ticles or defects on the surface, the main source of scattered light is microroughness. This signal is called haze because it is related to the visible haze seen with a collimated bright light in visual inspection. The haze value given by the laser scanner is proportional to the square of the Rq roughness value. However, the scat tering intensity is strongly affected by the orientation of the surface features and by the optical design of the instrument. The spatial frequency range depends on the geometry of the optics and the wavelength; in practice it is generally between 0.2 and 3 μm�1. Therefore, haze values given by different types of laser scanners usually are not directly comparable. By careful calibration the

haze measurement can provide quantitative data on sur face roughness. For more direct quantitative measurements of the topography the surface is usually proﬁled with either a scanning probe microscope (SPM) or an optical proﬁler. The SPM is generally used in the tapping mode to mini mize possible damage to the wafer and probe. The lower spatial frequency limit is given by the inverse of the scan length (L), and the upper limit by the ratio of measure ment points to L. Therefore, to cover the spatial frequency range of an SSIS haze measurement, a relatively large scan area of 5 � 5μm2 must be used with the SPM. An opti cal proﬁler based on an interference microscope can also be used to determine the PSD function. The spatial fre quency range is naturally dependent on the optics, the magniﬁcation, and the wavelength of the light; but it can typically be comparable to that achieved with the SPM.

References 1. The determination of the size and shape of silicon wafers is described in the following standards: SEMI MF533 0706, SEMI MF534-0707, SEMI MF657-0707, SEMI MF928-0305, SEMI MF1390-0707, SEMI MF1530 0707, SEMI MF1451-0707, SEMI MF2074-0707, International SEMI Standards, http://wps2a.semi.org, 2007. 2. W.R. Thurber, R.L. Mattis, Y.M. Liu, J.J. Filliben, Resistivity-dopant density relationship for phosphorus-doped silicon, J. Electrochem. Soc. 127 (1980) 1807–1812. 3. W.R. Thurber, R.L. Mattis, Y.M. Liu, J.J. Filliben, Resistivity-dopant density relationship for boron-doped silicon, J. Electrochem. Soc. 127 (1980)

2291–2294.

4. Resistivity measurements, the conversion between resistivity and carrier concentration, and the determination of resistivity variations of silicon wafers are described in the following standards: SEMI MF43-0705, SEMI MF81-1105, SEMI MF84-0307, SEMI MF374-0307, SEMI MF397 1106, SEMI MF525-0307, SEMI MF673-1105, SEMI MF674-0705, SEMI MF723-0307, SEMI MF672 0307, SEMI MF1529-1104, SEMI MF1392-0307, International SEMI Standards, http://wps2a.semi.org, 2007. 5. D.K. Schroder, Semiconductor Material and Device Characterization, third ed., John Wiley & Sons, Inc, New York, 2006.

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6. V.-M. Airaksinen, Epitaxial layer characterization and metrology, in: D. Crippa, D.L. Rode, M. Masi (Eds.) Chapter 7 in Silicon Epitaxy, Semiconductors and Semimetals, vol. 72, Academic Press, New York, 2001, p. 255. 7. M.C. Nguyen, A. Danel, Use of non contact techniques in characterization of silicon epi growth process, Electrochem. Soc. Proc. 90-13 (1998) 432–443. 8. A. Danel, Cactérisation des Propriétés de Surface du Silicium par Analyse de Charges: Méthode SCP—surface charge proﬁler. Thése pour le titre de Docteur, L’Institut National Polytechnique de Grenoble, 1999. 9. S. Liberman, Non-contact surface resistivity measurements on production wafers, in: In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing, SPIE Proc., vol. 3215, 1997, pp. 35–40. 10. P.R. Grifﬁths, J.A. De Haseth, Fourier Transform Infrared Spectrometry, Wiley, New York, 1986. 11. B. Harbecke, B. Heinz, V. Offermann, W. Theiss, Far infrared spectroscopy, in: G. Bauer, W. Richter (Eds.) Optical Characterization of Epitaxial Semiconductor Layers, Springer Verlag, Berlin, Heidelberg, 1996, pp. 225–252. 12. H.G. Tompkins, E.A. Irene (Eds.), Handbook of Ellipsometry, William Andrews Publications, Norwich, NY, 2005. 13. SEMI, International SEMI Standards, SEMI MS2-0307, Test method for

14.

15.

16.

17.

18.

19.

20.

step-height measurements of thin, reﬂecting ﬁlms using an optical interferometer, http://wps2a.semi.org, 2008c. P.-F. Huang, S. Uritsky, C.R. Brundle, Unpatterned wafer defect detection, in: A.C. Diebold (Eds.), Handbook of Silicon Semiconductor Metrology, 2006, pp. 515–546. C.R. Brundle, S. Uritsky, Particle and defect characterization, in: A.C. Diebold (Eds.), Handbook of Silicon Semiconductor Metrology, 2006, pp. 515–546. J.C. Stover, Scatterometry: Principles, Applications, Limitations and Future Prospects, in: W.M. Bullis, D.G. Seiler, A.C. Diebold (Eds.) Semiconductor Characterization: Present Status and Future Needs, American Institute of Physics, Woodbury, 1996, pp. 399–412. J.M. Bennet, L. Mattson, Introduction to Surface Roughness and Scattering, Optical Society of America, Washington, DC, 1989. B.W. Scheer, J.C. Stover, Development of smooth-surface microroughness standard, Proc. SPIE 3141 (1997) 78–87. SEMI M40-0200, Guide for Measurement of Surface Roughness of Planar Surfaces on Silicon Wafer, International SEMI Standards, http:// wps2a.semi.org, 2000. DIN 4768. Determination of Values of Surface Roughness Parameters Ra, Rz, Rmax by means of Electrical Contact (Stylus) Instruments; Terminology, Measuring Conditions.

17

Chapter Seventeen Optical Measurement of Static and Dynamic Displacement in MEMS David Horsley Department of Mechanical and Aeronautical Engineering, University of California, Davis, CA, United States of America

A variety of optical techniques have been developed for the characterization of mechanical motion in MEMS devices [1–4]. Broadly speaking, these techniques can be placed into subcategories based on the direction of motion (in-plane or out-of-plane) and measurement area (full-ﬁeld or single-point). A variety of optical metrology instruments, including some developed exclusively for MEMS applications, are available to perform these measurements. Specialized applications, such as those requiring very high measurement bandwidth, may require the construction of custom instrumentation. Even when commercial instruments are available for a particular application, there are a variety of reasons to choose whether to buy or build a custom instrument including cost, ease-of-use, reliability, and maintenance.

17.1 Camera-Based Measurements Cameras based on array photodetectors, such as chargecoupled device (CCD) and CMOS imagers, are low-cost and easy to integrate with computer-based image acquisition and analysis software. Although high-speed cameras with frame-rates exceeding 10000 frames per second (fps) are available, in many cases it is desirable to measure device motion at frequencies far above this range. Even conventional cameras operating at standard video frame-rates (30–60 fps) can be used to measure periodic motion at high frequencies. The simplest (and lowest resolution) method is to capture a blurred image of the vibrating device and measure the amplitude of

the blur envelope surrounding the moving elements. When the motion is in-plane, a standard microscope with a high-power (50 to 100) objective can be used to capture the blurred image, as shown in Figure 17.1. The resolution of this technique depends on the image contrast but generally ranges from 0.1 to 0.5 μm. Higher precision can be obtained through stroboscopic measurements in which the sample is illuminated with a pulsed light source. Here, the time over which the image is captured is governed by the light pulse duration rather than the frame-rate of the camera. A timing diagram for stroboscopic measurement is shown in Figure 17.2. If the pulse duration (tp) is short relative to the period of motion (T), a snapshot image of the moving device will be captured. By synchronizing each light pulse to the signal driving the MEMS

(a)

(b)

(c) 8 μm 10 μm

Fig 17.1 ● Measuring in-plane vibration using a blur image. (a) Optical image of an electrostatic comb-drive captured at 20 magniﬁcation. (b) 50 image of the interdigitated comb teeth at rest. (c) 50 image of the interdigitated comb teeth when the device is driven at its resonant frequency. The measured peakto-peak displacement is 8 μm.

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P(t)

V(t)

is constructive or destructive. For a light source with wavelength λ, the intensity at the detector as a function of the displacement of the MEMS device z can be expressed as

Z(t)

1 0.5

I( z) I1 I2 2 I1I2 cos(Δϕ 4π z λ )

0 Δ –0.5

tp

–1 0

0.2

0.4

0.6

0.8

1 t/T

1.2

1.4

1.6

1.8

2

Fig 17.2 ● Timing diagram for stroboscopic imaging. The MEMS device is driven with a waveform V(t), and undergoes periodic motion Z(t). Light pulses P(t) with duration tp are synchronized to V(t) and delayed by Δ to capture a snapshot at a particular point in the cycle of motion.

device, a snapshot can be captured at a particular point in the cycle of motion. Sequential images of the device can then be collected by varying the delay (Δ) between the drive signal and the light pulse. In-plane rigid body motion has been measured with 2 nm resolution using this approach [5]. Semiconductor light sources, such as light emitting diodes (LEDs) and laser diodes, are suitable light sources as they are capable of fast modulation and have high optical intensity. High brightness LEDs and laser diodes with intensities in the 1–10 mW range have been used to capture images of structures driven at 1 MHz frequencies [5, 6] using light pulses of duration tp10 ns. At least one commercial instrument that can collect in-plane measurements at frequencies up to 1 MHz with 2 nm accuracy is available [7].

17.1.1 Interferometry Out-of-plane motion in MEMS is conveniently measured using an interferometer, which is a displacement measuring instrument based on the interference of coherent light beams. A variety of interferometers have been utilized for MEMS characterization, and a number of excellent descriptions of interferometry are available in textbooks [8, 9]. The basic concepts of interferometry are illustrated in Figure 17.3, which shows a Michelson interferometer. Light from a monochromatic or quasi-monochromatic light source is split into a measurement and a reference path, using a beam splitter. The light in the measurement path reﬂects off the surface of the MEMS device, whereas the light in the reference path is reﬂected by a ﬂat reference mirror. The reﬂected light beams combine and interfere at the surface of the photodetector or camera. The difference in the optical path length of the two beams results in a phase difference, determining whether the interference 300

(17.1)

where I1 and I2 represent the intensity of the measurement and reference beams and Δϕ is the phase difference due to any initial imbalance in the optical path lengths. Assuming Δϕ 0, the intensity is plotted as a function of displacement z in Figure 17.3. The intensity function consists of a series of periodic interference fringes with the bright and dark fringes spaced by z λ/4. The position resolution of the interference measurement depends on the fringe visibility V, which is the ratio of the fringe amplitude to the average intensity: V

2 I1I2 I1 I2

(17.2)

Maximum fringe visibility (V 1) is achieved when the two beams have equal intensity (I1 I2). In practice, the actual fringe visibility at a given phase difference will depend on the coherence length of the source, as discussed below. To measure motion at a single point on a MEMS device, the interferometer’s measurement spot can be focused to roughly 1 μm diameter using a microscope objective, or by coupling the interferometer into a standard microscope. Optical images of the laser spot from a commercial interferometer (Polytec OFV-512) focused onto MEMS structures are shown in Figure 17.4. Single-point measurements made using high-speed photodetectors allow high-frequency motion to be measured—MEMS devices operating at frequencies in the GHz range have been characterized in this way [10]. To collect information about vibration mode-shapes using a single-point interferometer, a sequence of measurements can be collected at a regular grid of points across the surface of the device. At each point, the magnitude and phase of the displacement signal with respect to the input signal driving the MEMS device is recorded. After recording the displacement magnitude and phase at each point in the grid, a three-dimensional image of surface displacement can then be constructed.

Phase-Shifting Interferometry As an alternative to single-point measurements, fullﬁeld interferometric measurements of device topography and displacement can be performed. In a full-ﬁeld measurement, an image of the MEMS device crossed by interference fringes, referred to as an interferogram, is collected with a camera. The device topography can be

Optical Measurement of Static and Dynamic Displacement in MEMS (a)

(b)

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1 0.9

Light source

0.8

Detector

RM

MEMS device

Intensity (AU)

0.7 Beamsplitter

0.6 0.5 0.4 0.3 0.2 0.1 0

0

0.5

1 z/λ

1.5

2

Fig 17.3 ● (a) Block diagram of a Michelson interferometer. (b) Intensity as a function of normalized displacement, z/λ.

Fig 17.4 ● Optical images of the measurement beam of a commercial interferometer focused to a small spot on MEMS devices. (a) Side view with the laser focused onto the sidewall of a silicon MEMS structure. Scalloping on the sidewall scatters the reﬂected beam, making it appear to be larger. The scale bar is 15 μm wide. (b) Top view with the laser focused on a 3 μm wide silicon ﬂexure. The scale bar is 10 μm wide.

extracted using phase-shifting interferometry (PSI), in which a sequence of interferograms is collected while controlled variations in the relative phase of the measurement and reference path are introduced. The interferograms are then analyzed together to compute the topography of the device under test. Controlled phase shifts can be introduced through a variety of methods; one method is to place the reference mirror on a piezoelectric stage and translate the stage by a controlled increment before collecting each interferogram. The simplest phase-stepping algorithm requires three interferograms acquired at 90° phase increments; a more vibration-insensitive algorithm requiring ﬁve interferograms was developed by Hariharan [11]. An example set of ﬁve interferograms and the computed surface topography are illustrated in Figure 17.5. Combining PSI with stroboscopic illumination allows simultaneous measurement of motion across the entire device surface, speeding the process of measuring vibration mode-shapes [6, 12–14]. PSI allows dynamic and

static topographic measurements with a vertical resolution of roughly 1 nm [13]. However, the bandwidth of stroboscopic measurements is currently limited to approximately 1 MHz [6], several orders of magnitude below the maximum bandwidth of a single-point instrument.

Fiber Optic Interferometers In addition to the free-space designs described above, interferometers may also be constructed using optical ﬁber. One design, the ﬁber Fabry Perot interferometer (FPI) [15], is illustrated in Figure 17.6. Light from a ﬁber-coupled laser passes through a 2 2 splitter which splits the light equally into two output ﬁbers. The ﬁrst output is either connected to a photodetector to provide a reference measurement of the input laser intensity or terminated (e.g., by submersion in indexmatching ﬂuid) to minimize back-reﬂections. The second output is terminated by a ﬂat cleaved (or polished) ﬁber end-face which is positioned close to the MEMS 301

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PA R T I I I

(a)

(b)

1

Surface height (μm) Peak-to-valley = 4.2 (μm)

10.2 mm

1.5 2 2

3

4

1

0

0.5

–2

0

–4 500

0.5 –1

400 300

5

Fig 17.5 ● Measurements of the surface topography of a 10.2 mm diameter MEMS deformable mirror (DM) using PSI. (a) Five interferograms of the DM surface. The phase of the reference beam is incremented by π/2 radians between each interferogram. (b) Resulting surface topography extracted from the interferograms, showing a peak-to-valley surface deformation of 4.2 μm.

–1.5

200 100

600 700 400 500 300 200 0 100

(a)

–2

(b) Laser 2 × 2 splitter

v(t)

z(t)

To reference photodiode or terminate Fiber probe

MEMS device

Silicon

SMF

Photodiode

Fig 17.6 ● (a) Block diagram of ﬁber FPI measurement setup. (b) Photograph of a polished SMF connector end face positioned next to a silicon MEMS device for testing.

device. The cleaved end-face functions as both a beamsplitter and a reference mirror: Roughly 4% of the light is reﬂected backwards, forming the reference beam, while the remaining light is transmitted, reﬂecting off the MEMS device. Both reﬂected beams interfere and return to the splitter where half the returned light is directed to a photodiode for measurement. Note that since the light passes through the splitter twice, 75% of the input intensity is lost in the splitter. In addition, an optical isolator may be required at the laser output to prevent feedback from back-reﬂected light. The ﬁber FPI has a number of advantages over freespace interferometers. First, because the measurement and reference beams share a common path, the ﬁber FPI is considerably more robust to vibration than a conventional Michelson interferometer. The ﬁber probe allows precise positioning of the measurement spot, and the spot diameter is quite small as it emerges from the ﬁber (5–10 μm for single mode ﬁber (SMF), depending on the measurement wavelength), allowing measurements to be collected on the sidewalls of deep-etched MEMS devices. However, this convenience comes at the price that the ﬁber must be precisely aligned and positioned very close to the MEMS device to yield maximum fringe 302

visibility. For example, if a MEMS device with a polished silicon surface (35% reﬂectivity) is to be tested, the ﬁber end face should be positioned less than 100 μm from the device and aligned within 1° of normal incidence. Larger separation, increased angular misalignment, or reduced reﬂectivity from the MEMS surface will reduce the fringe visibility and degrade the position resolution.

Choosing a Light Source—Coherence Length In an interferometer, the coherence length of the light source determines the optical path difference at which the fringe contrast falls to zero. For a source with center wavelength λ0 and linewidth Δλ, a simple estimate of the coherence length Lc is provided by: Lc λ02 Δλ . Long coherence length sources include HeNe (Lc2 m) and diode lasers (Lc400 μm). White-light sources, such as tungsten ﬁlament lamps (Lc1 μm) have very short coherence length, while monochromatic LEDs (Lc10 μm) fall somewhere in between. Certain applications such as PSI require the use of long coherence length sources to maintain high fringe contrast over large optical path differences. Short coherence length sources are used in

Optical Measurement of Static and Dynamic Displacement in MEMS

white-light or vertical scanning interferometry (VSI). In VSI, highly localized interference fringes appear when the difference in the measurement and reference path lengths is shorter than the coherence length. Surface height measurements are made by scanning the reference path length and recording the location of the fringes on the sample. VSI is very well suited for making topography measurements in the presence of large steps (discontinuities), a challenging problem for other interferometers.

17.1.2 Displacement Read-Out and Resolution A number of methods are available to recover the displacement signal in a single-point interferometer. Fringecounting has a wide dynamic range but relatively poor resolution (λ/20). Also, because the cosine term in Eq. 17.1 is an even function, the direction of motion is ambiguous, making it difﬁcult to use fringe counting to measure oscillating motion. The direction ambiguity can be eliminated by reading two simultaneous interference measurements that are in quadrature [16]. Alternatively, if the MEMS device moves with an amplitude much smaller than the fringe width ( z(t ) << λ/8), motion can be measured by detecting small-signal AC variations in the intensity signal. Such a measurement is made by ﬁrst adjusting the relative phase of the reference and measurement beams (Δϕ) by moving the reference mirror position. As illustrated in Figure 17.3b, the small-signal position sensitivity is maximized when Δϕ π/2 Nπ (N 1,2,3 …). However, depending on the dominant noise source, the signal-to-noise ratio (SNR) may be maximized at another location [17]. Slow path length changes due to thermal shifts create variations in the position sensitivity and cause the DC intensity to drift over time; a path-stabilized interferometer solves this problem by using closed-loop feedback to adjust the reference mirror position. The position resolution in an interferometer is determined by the SNR. A variety of noise sources are present in the interference measurement, including mechanical vibration, relative intensity noise (RIN) from the light source, photon shot noise, and electronic noise in the photodetector circuit. Assuming that mechanical vibrations are suppressed, the dominant terms are the RIN and the shot-noise, since electronic noise is small, provided that the light source has sufﬁcient intensity. The theoretical shot-noise limited resolution of a path-stabilized interferometer operating at λ 633 nm has been estimated [17] as 5.6·1015 m/Hz, or 5.6 pm in a 1 MHz measurement bandwidth. Without path stabilization, the SNR may be considerably reduced. Furthermore, the presence of other noise sources and reduced fringe contrast (V 1) combine to degrade

CHAPTER 17

the resolution of practical interferometers. Nevertheless, demonstrated resolutions for interference measurements range from 3 pm [10] to a few nm [15].

Heterodyne Interferometry: The Laser Doppler Vibrometer The interferometers described above are based on the interference of laser light with the same wavelength (frequency) and are therefore classiﬁed as homodyne interferometers. In a homodyne interferometer, the detection frequency is relatively low, making the interferometer sensitive to low-frequency noise sources such as 1/f noise in the photodetector, intensity drift in the light source, and ambient light variations. In a second category of interferometer, the heterodyne interferometer, a frequency difference Δf is imposed between the measurement and reference beams (e.g., by passing one of the beams through an optical modulator). The result is that the intensity signal is modulated with Δf as a carrier frequency: I I1 I2 2 I1I2 cos (2πΔft 4π z(t )λ ) (17.3) The theoretical shot-noise limited resolution of a heterodyne interferometer operating at λ 633 nm has been estimated [17] to be 7.9·1015 m/Hz, or 7.9 pm in a 1 MHz measurement bandwidth. Since heterodyne interferometers can achieve this resolution without the need for closed-loop path stabilization, they are relatively easy to use. One popular heterodyne interferometer is known as a laser Doppler vibrometer (LDV). For a MEMS device moving with a constant velocity v, the cosine term in Eq. 17.3 becomes: cos (2πΔf 4π vt λ ) cos 2π(Δf fd )t

(17.4)

where fd 2v/λ is the Doppler frequency. The Doppler frequency is recovered using detection techniques similar to those employed in FM radio receivers. An example of commercial LDV, the OFV 3001 [18], employs a frequency shift Δf 40 MHz and has a maximum detection bandwidth of 1.5 MHz. Assuming that the surface of the MEMS sample is highly reﬂective, the velocity resolution of this instrument ranges from 0.3 to 5 μm/s in a 10 Hz measurement bandwidth, depending on the speciﬁc velocity decoder employed and the frequency range of the measurement. For a MEMS device that is undergoing sinusoidal motion, the velocity resolution can be interpreted in terms of displacement resolution. Assuming the device moves sinusoidally at a frequency f0, the minimum detectable displacement amplitude is given by amin vmin/(2πf0), where vmin is the velocity resolution. For example, the instrument has a speciﬁed resolution of 0.6 μm/s for signals up to 50 kHz, implying that if f0 50 kHz, the displacement resolution is amin2 pm. 303

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References 1. V. Annovazzi-Lodi, S. Merlo, M. Norgia, Characterization of silicon microstructures by feedback interferometry, J. Opt. A: Pure Appl. Opt. 4 (6) (2002) S311–S317. 2. A. Bosseboeuf, S. Petitgrand, Characterization of the static and dynamic behaviour of M(O)EMS by optical techniques: status and trends, J. Micromech. Microeng. 13 (4) (2003) S23–S33. 3. W.M. van Spengen, R. Puers, R. Mertens, I. De Wolf, Characterization and failure analysis of MEMS: high resolution optical investigation of small out-of-plane movements and fast vibrations, Microsyst. Technol. 10 (2) (2004) 89–96. 4. M.B. Sinclair, M.P. de Boer, A.D. Corwin, Long-working-distance incoherent-light interference microscope, Appl. Opt. 44 (36) (2005) 7714–7721. 5. C.Q. Davis, D.M. Freeman, Using a light microscope to measure motions with nanometer accuracy, Opt. Eng. 37 (4) (1998) 1299–1304. 6. J.A. Conway, J.V. Osborn, J.D. Fowler, Stroboscopic imaging interferometer for MEMS performance measurement,

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7.

8. 9.

10.

11.

12.

13.

J. Microelectromech. Syst. 16 (3) (2007) 668–674. A.O. Ong, F.E.H. Tay, Motion characterizations of lateral micromachined sensor based on stroboscopic measurements, IEEE Sens. J. 7 (1–2) (2007) 163–171. E. Hecht, Optics, third ed., AddisonWesley, Reading, MA, 1998. P. Hariharan, Optical Interferometry, 2nd ed., Academic Press, San Diego, CA, 2003. J.E. Graebner, B.P. Barber, P.L. Gammel, D.S. Greywall, S. Gopani, Dynamic visualization of subangstrom high-frequency surface vibrations, Appl. Phys. Lett. 78 (2) (2001) 159–161. P. Hariharan, B.F. Oreb, T. Eiju, Digital phase-shifting interferometry—A simple error-compensating phase calculation algorithm, Appl. Opt. 26 (13) (1987) 2504–2506. M.R. Hart, R.A. Conant, K.Y. Lau, R.S. Muller, Stroboscopic interferometer system for dynamic MEMS characterization, J. Microelectromech. Syst. 9 (4) (2000) 409–418. C. Rembe, R.S. Muller, Measurement system for full three-dimensional

14.

15.

16.

17.

18.

motion characterization of MEMS, J. Microelectromech. Syst. 11 (5) (2002) 479–488. D.A. Horsley, H. Park, S.P. Laut, J.S. Werner, Characterization of a bimorph deformable mirror using stroboscopic phase-shifting interferometry, Sens. Actuators, A: Physical 134 (1) (2007) 221–230. T.J. Tayag, E.S. Kolesar, B.D. Pitt, K.S. Hoon, J. Marchetti, I.H. Jafri, Optical ﬁber interferometer for measuring the in situ deﬂection characteristics of microelectromechanical structures, Opt. Eng. 42 (1) (2003) 105–111. H.C. Seat, A pseudo dualcavity extrinsic ﬁbre Fabry-Perot interferometric vibrometer, Sens. Actuators, A: Physical 110 (1–3) (2004) 52–60. J.W. Wagner, J.B. Spicer, Theoretical noise-limited sensitivity of classical interferometry, J. Opt. Soc. Am. B: Opt. Phys. 4 (8) (1987) 1316–1326. Polytec, OFV 3001 Laser Doppler Vibrometer User Manual, Waldbronn, Germany, Document ManVib-OFV3001–1202–05e.

18

Chapter Eighteen MEMS Residual Stress Characterization: Methodology and Perspective Kuo-Shen Chen and Kuang-Shun Ou Department of Mechanical Engineering, National Cheng-Kung University Tainan, Tainan, Taiwan

18.1 Introduction Residual stress characterization in microelectromechanical systems (MEMS) structures is of inherent importance in various respects. First, from the device perspective, the existence of residual stresses essentially changes the performance and reduces the structural integrity and longevity of MEMS devices. Second, MEMS techniques actually provide a new tool for studying the mechanical properties of materials such as modulus, hardness, and state of stresses. As a result, in recent years there has been rapid growth in the ﬁeld of MEMS residual stress characterization. Readers are encouraged to refer to the many excellent books or papers to gain the fundamental knowledge on MEMS design and fabrication [1–5]. For MEMS and microelectronics, the existence of residual stresses can seriously inﬂuence the reliability and dynamical characteristics of devices. From the structural integrity perspective, one must predetermine or control the residual stress level to prevent structural failures and for mechanical design [6]. As a result, the mechanical properties of MEMS materials should be characterized. One can refer to the many excellent publications on this issue [7–11]. Among all mechanical properties, characterization of residual stress is of particular importance. The existence of tensile residual stress in thin-ﬁlm structures usually results in cracking of the ﬁlms. On the other hand, the existence of residual stress could also effectively change the effective stiffness of structures and, therefore, the system dynamical parameters such as natural frequencies, which must be accurately determined for device performance prediction. An accurate characterization of the state of residual stress is, therefore, essential for the

success of such devices. For a detailed description on conventional residual stress characterization techniques, please consult the references [12–15]. Residual stresses can be deﬁned as those stresses that remain in a material or structure after manufacturing and processing, in the absence of external forces or thermal gradients. All residual stress systems are selfequilibrating; the resultant force and moment, which they produce, must be zero. It is important to note that residual stress measurement techniques invariably measure strains rather than stresses, and the residual stresses are then deduced using material parameters such as Young’s modulus and Poisson’s ratio together with an appropriate mechanical constitutive model. Residual stress occurs in materials and mechanical components during manufacturing from many ﬁlm growth processes. The origins of residual stresses may be classiﬁed as mechanical, thermal, or chemical. Mechanically generated residual stresses are often a result of manufacturing processes that produce non-uniform elastic or plastic deformation. On a macroscopic level, thermally generated residual stresses are often the consequence of non-uniform heating or cooling. Coupled with the material constraints in the bulk of a large component these thermal nonuniformities can lead to severe thermal gradients and the development of large internal stresses. Microscopic thermally generated residual stresses can also be developed in a material during fabrication and processing as a consequence of the coefﬁcient of thermal expansion (CTE) mismatch between different phases or constituents. On the other hand, chemically generated stresses can develop due to volume changes associated with chemical reactions, precipitation, or phase transformation. Chemical surface treatments and coatings can lead to the generation of 305

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substantial residual stress gradients in the surface layers of the component. Based on these demands, residual stress characterization naturally becomes an important research ﬁeld for MEMS. The situation is further complicated by the complexity of the fabrication process of MEMS structuring. In addition, due to practical constraints in fabrication processes and size scales, many well-established residual stress characterization techniques in macroscale cannot be applied and new methods must be developed. Numerous novel characterization methods speciﬁed for MEMS have been proposed and the goal of this article is therefore to brieﬂy review the characterization techniques and their associated mechanics for providing a generic understanding of stress measurements.

18.1.1 Origin of residual stress in MEMS structures The origin of stresses in thin ﬁlms, microelectronics, and MEMS structures has been reviewed extensively by many researchers, such as Drener and Nix [16–19]. Fundamentally, it can be classiﬁed into two major categories, that is, the thin-ﬁlm deposition or growth generated intrinsic stress and the mismatch between thermomechanical properties of materials [9, 20]. The ﬁrst issue on the residual stress characterization one must bear in mind is that strictly speaking; stress (and residual stress) is an intensive and intrinsic property and is generally not measurable. It must be deduced based on a speciﬁc mechanical model and data from other measurable properties such as load and deformation. Figure 18.1 shows the schematics of the residual stress measurement process. Therefore, how to accurately measure these measurable quantities is just one critical issue. Proper mechanical models are also required to correctly map the measured data into ﬁnal residual stress values. Both issues contribute to the ﬁnal uncertainties of mechanical properties. The overall accuracy of the residual stress measurement is a compromise between these two issues. That is, for each residual stress measurement technique, one should be careful about not only its measurement resolution but

MEMS specimen & testing system design

Experimental investigation

Mechanical model

Fig 18.1 ● The procedure of residual stress measurement.

306

also the fundamental constraints and limitation associated with the modeling for data conversions. In general, the residual stress characteristic techniques related to MEMS can be classiﬁed as following: a. Wafer-level curvature measurement: This method utilizes global bending deformation due to the presence of residual stress in layer structures. This method has been widely applied for wafer-level thin-ﬁlm stress measurement. b. Material-level non-destructive measurement: Use X-Ray Diffraction (XRD), neutron deﬂection, Raman Spectroscopy, or photo-acoustic microscopy to determine either the distorted lattice spacing or the wave propagation speed in a material. c. Residual stress measurement using MEMS specimens or structures: This has been a major MEMS research activity for the past two decades. Many novel MEMS structures, including beam, membrane, and spiral structures, as well as novel methods utilizing solid mechanics principles, have been proposed for MEMS stress characterization. d. Material-level destructive measurement: In this category, methods such as indentation fracture or nanoindentation are also developed to characterize mechanical properties of bulk or thin-ﬁlm materials, including residual stresses. In this work, only categories a and c are introduced. For categories b and d, readers are encouraged to refer to the many research works available in the literature.

18.2 MEMS residual stress characterization techniques 18.2.1 Curvature measurement The most widely applied or acknowledged thin-ﬁlm stress measurement method is the curvature measurement of beam or plate structures. As shown in Fig. 18.2, by measuring the warpage information of a structure, followed by proper conversion mechanics, it is possible

Load, displacement, frequency measurements

Residual strains & stresses

MEMS Residual Stress Characterization: Methodology and Perspective

to extract the stress information. Consider a composite ﬁlm-substrate wafer shown in Fig. 18.3. The ﬁlm thickness and Young’s modulus are df and Ef, respectively, and the corresponding substrate values are ds and Es. Stoney’s formula published one hundred years ago links the ﬁlm stress and the wafer curvature as [21] σf

Es ds2 1 6 R (1 ν s )d f

(18.1)

Commercial ﬁlm stress characterization utilizes systems such as KLA Tencor to measure the proﬁle of a wafer and uses Eqn. (18.1) to convert the measured curvature to the ﬁlm stress. A laser scanner is usually used to characterize the deformation proﬁle of a wafer. The radius of curvature, R, is subsequently calculated from the scanned data. By Eq. (18.1), it is possible to determine the ﬁlm stress σf through measurement of R. However, it must be emphasized that the Stoney’s formula is based on one-dimensional linear elastic beam theory (or linear circular plate theory). If the stiffness of ﬁlm cannot be neglected or the ﬁlm is highly stressed, this approach could result in signiﬁcant modeling errors [21] and bifurcation is expected for an even higher deformation. Because all curvature-based ﬁlm stress measurement systems, for example, the KLATencor FLX Series, use Stoney’s equation to convert the

CHAPTER 18

measured data into the ﬁlm stress, one must be careful to examine the ﬁnal stress values obtained by the measurement system. Notice that the wafer curvature measurement can also be achieved by full-ﬁeld methods such as the shadow moiré technique. Chen, et al., developed a shadow moiré system to characterize the wafer-level thin-ﬁlm residual stress [22]. Figure 18.4 shows a typical wafer warping map using such a technique. In comparison with instruments such as KLA-Tencor, full-ﬁeld methods can provide integrated information in a relatively short time. Finally, works to discuss the stress for multilayer thin ﬁlms or ﬁlm/substrate systems under large deformation were developed to improve the accuracy or to extend the applicability of the curvature measurement methodology [23, 24].

18.2.2 Bulge Test Method Bulge test is a method used to determine the material properties of thin ﬁlms, such as Young’s moduli, Poisson’s ratios, and residual stresses. As shown in Fig. 18.5 [25], in the bulge test, uniform pressure is applied to one side of a freestanding thin-ﬁlm window, causing it to deﬂect outward. The stress and strain in the ﬁlm can

Thin film coated wafer

Deformation/ warpage characterization Wafer bow or curvature Geometry and material properties

Mechanical modeling

Film stress

Fig 18.2 ● Schematic plot of curvature measurement. Source: Reprinted with permission from Chen et al. [22], Copyright 2004 IEEE).

Fig 18.4 ● A typical wafer warping image obtained by shadow moiré technique. Source: Reprinted with permission from Chen et al. [22], Copyright 2004 IEEE).

Bow

Film Substrate df ds R

a

Fig 18.3 Schematic plot of a warped wafer. ●

Source: Reprinted with permission from Chen et al. [22], Copyright 2004 IEEE).

Fig 18.5 ● Schematics of bulge tests.

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be determined from measurements of pressure (P) and the window’s deﬂection (h). The bulge test is a ﬂexible technique, permitting the characterization of a ﬁlm’s elastic, plastic, and time-dependent deformation, and has been extensively discussed and employed. By measuring the lateral deﬂection and by incorporating subsequent ﬁnite element (FE) analysis, one can extract the Young’s modulus, Poisson’s ratio, and the residual stress from the test data. This method is particularly useful for measuring stress in low modulus tensile materials such as polyimides. The same micromachined test structures can also be used for adhesion testing (also known as blister testing), which is a logical extension of the bulge technique: the pressure applied to the sample is increased until the ﬁlm starts to de-bond from the substrate, forming a circular “blister ” which can be grown steadily larger. This type of test structure ensues from shaping a silicon diaphragm by conventional anisotropic etching, followed by applying the coating, and ﬁnally, removing the supporting silicon from the back with the SF6 plasma. Pressure to the suspended ﬁlm can be applied by a gas or by a point-load applicator. By elasticity, it can be shown that the pressure (p)–deﬂection (h) relation for moderate deﬂections can be expressed as [26] ⎛ E ⎞⎟ t 3 p C1 2 h C2 ⎜⎜ h ⎜⎝1 ν ⎟⎟⎠ a4 a σ0 t

σ0 th a2

(1.996 0.613ν )

Et h3 (1 ν ) a4 (18.3)

And, for a very long rectangular window, p

308

4Et

h3

3(1 ν 2 ) a4

2σ0 th a2

18.2.3 Buckling Method The sudden buckling collapse due to excessive compressive stresses has been used as a method to evaluate the lower bound of residual stress level of elastic MEMS structures for many years. Consider an elastic column with length L and ﬂexural rigidity EI shown in Fig. 3.5, the critical load P for causing structural instability is [30] P

(18.2)

where σ0 and t are the residual stress and the ﬁlm thickness, respectively; C1 and C2 are geometry dependent shape factors; and a is the characteristic length of the membrane. For example, for a circular membrane, a is the radius and C1 and C2 are 4 and 8/3, respectively. A more accurate numerical solution indicated that C2 can be expressed as 8(1.0150.247ν)/3 [25]. The relation in Eqn. (18.2) can simultaneously determine σ0 and E/1ν. Plotting pa2/th vs. (h/a)2 should yield a straight line. The residual stress can be extracted from the intercept, and the biaxial modulus is proportional to the best ﬁtted slope. For non-circular membranes, such as square or rectangular shape diaphragms, the result is more complicated. Using an energy minimization scheme, it can be shown that the deﬂection for a square ﬁlm with residual stress can be expressed as [25] p 3.393

In MEMS material characterization, the bulge test has been applied for characterizing the residual tensile stress of polyimide ﬁlms by Allen [27] and heavily doped polysilicon deposited on thermal oxide, BPSG, LPCVD nitride [28], and silicon-rich silicon nitride [25]. All of those tests use square window fabricated by KOH etch. Poilane, et al., [29] applied the bulge test to measure the mechanical Young’s and residual stress of polyimide ﬁlms deposited on a GaAs substrate by creating a rectangular window. In parallel, they also utilized a nanoindentation test to cross check. They found that E 2.8 0.5 GPa and the residual tensile stress linearly decreased with the membrane thickness and the value is between 12 and 25 MPa for a ﬁlm thickness between 5.5 and 2.2 μm.

(18.4)

n 2π 2 EI L2

, n 12 , ,3

(18.5)

and the critical load is deﬁned as the load with the smallest n. That is, Pcr π 2 EI /L2 and the critical stress 2 2 σ cr (π EI )/AL , where A is the cross-sectional area of the column. The results vary with different boundary conditions. Nevertheless, the effect of boundary conditions can be represented by deﬁning the effective length L’ of a column, that is, L’ KL and use L’ to replace L in Eqn. (18.5). For example, for a ﬁxed-ﬁxed column, K 0.5. For a more realistic model by considering the compliance of boundaries, residual stress for each buckled beam is determined as [31]. σR

Eπ 2 ⎛⎜ A2 t 2 ⎞⎟⎟ ⎜

⎟ ⎜ 3 ⎟⎠ L2EF ⎜⎝ 4

(18.6)

where A is the amplitude of the buckling deﬂection, LEF is the effective beam length, and t is the beam thickness. The shape of buckle is sinusoidal and the deﬂection z(x) can be expressed as [31] z(x )

A ⎛⎜ 2π x ⎞⎟ ⎟⎟ ; LEF /2 x LEF /2 ⎜⎜1 cos 2⎝ LEF ⎟⎠

(18.7)

Figure 18.6 indicates a set of typical ﬁxed-ﬁxed beam MEMS structures subjected to the inherent residual stress.

MEMS Residual Stress Characterization: Methodology and Perspective

CHAPTER 18

Poly 2 100 μm

bFF

LFF

(a)

(b)

Fig 18.6 ● (a) Schematic layout plot of a ﬁxed-FB and (b) interferometry measurement to indicate the buckling of ﬁxed-FBs. Source: Reprinted with permission from Masters et al. [31], Copyright 2001 ASTM.

Poly 2

Ro br

R

Poly 1 + bb μm 100μ

Fig 18.7 ● A series of polysilicon Guckel’s rings fabricated using MUMP process. Source: Reprinted with permission from Masters et al. [31], Copyright 2001 ASTM.

Beam structures can only characterize compressive residual stress. For tensile residual stress, the so-called Guckel’s rings [32] should be used (see Fig. 18.7). These structures will buckle once the internal tensile residual stresses exceed their corresponding speciﬁc critical value. Notice that because this type of specimen can only show whether the internal stress exceeds the critical stress or not for a given single test structure, an array of structures with systematically varied geometry parameters are usually required to obtain the accurate value and the resolution of the measured stresses depends on the geometrical resolution of the test structures. These beams can be fabricated using surface micromachining techniques and the goal of the test structure is usually to characterize the in situ residual stress generated during the entire fabrication process. The residual stress of the structure will be laid between the

critical stress of the longest buckled beam and the shortest unbuckled beam. For a given upper/lower bound, the only method to enhance the resolution is to increase the number of beams and this could effectively increase the overall specimen size, which requires considerable wafer space. In addition, in order to be measurable, the deﬂection must be greater than the resolution of common interferometers, which is in the order of 10 μm. The typical size of test structure is at ~0.20 mm2 per structure and the resolution of this type of specimen residual strain is around 1 μ (0.35 μ) as discussed by Masters, et al. [31].

18.2.4 Relief of Stressed Structures Both clamped-clamped beams and ring structures need to be implemented in entire arrays of structures and they do not allow easy integration with active microstructures 309

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due to space constraints. As opposed to those structures, one might use vernier gauges to measure the displacement of structures induced by the relief of residual strain. This idea was ﬁrst explored by Kim [33] and further modiﬁed by others [34, 35]. This type of device measures residual strain (and, therefore, stress) by using an ampliﬁcation device and a vernier gauge. This method requires only one structure, but the best resolution for strain measurement reported is usually only 0.02% for 500 μm beams [3]. Other types of direct strain measurement devices are the T- and H-shaped structures [36]. In general, a longer ampliﬁcation beam will achieve a better resolution, but it also represents a larger specimen and is more sensitive to out-of-plane deformation, structure survivability, and external damages. Short beams, on the other hand, are less sensitive and more robust, and the conversion between deformation and residual stress is much more dependent on ﬁnite element simulation. The typical occupation area for a single rotating pointer structure is approximately 1 mm2 [31]. A micromachined strain gauge capable of measuring tensile or compressive residual stress shown in Fig. 18.8 developed using only one structure and can be fabricated in situ with active devices, determines tensile or compressive strain under optical microscopes, has a ﬁne resolution of 0.001 %, and is resistant to the out-ofplane strain gradient [37]. When the device is released in the sacriﬁcial etch step, the test beam (with a length Lt) expands or contracts, depending on the sign of the residual stress in the ﬁlm, causing the compliant slope beam (length Ls) to deﬂect. The indicator beam (length Li) attached to the deforming beam at its point of inﬂection rotates through an angle θ, and the deﬂection

δ is read on the vernier scale. The residual strain εf is calculated as εf

2Lsδ 3 Li Lt C

(18.8)

where C is a correction factor required by the presence of the indicator beam. This specimen has been used to characterize residual stress of polysilicon and nitride ﬁlms [37, 38]. Similar design of the indicator type structure was built by Gianchandani and Najaﬁ [35], Ericson, et al., [39], Zhang, et al., [40, 41], and Pan and Hsu [42], using the same type of mechanism. By reading an integrated scale in an SEM or an optical microscope, internal stress was measured with a resolution better than 0.5 MPa. In comparison with the clamped-clamped beam or ring method, this type of device shows a signiﬁcant reduction in the required test area. These structures were limited in resolution by the minimum feature size of the technology used and the out-of-plane displacements caused by stress gradients, and non-uniform beam thickness can inhibit device sensitivity.

18.2.5 Raman Spectroscopy Raman spectroscopy is already being used for the study of semiconductors [43]. It allows the identiﬁcation of the material and yields information about phonon frequencies, energies of electron states and electron– phonon interaction, carrier concentration, impurity content, composition, crystal structure, crystal orientation,

LA LC W Pointer

O

LB

(a)

(b)

Fig 18.8 ● (a) Schematic plot of a vernier micro strain gage and (b) a typical design. Source: reprinted with permission from Masters et al. [31], Copyright 2001 ASTM and (b) a typical design (source: reprinted with permission from Lin et al. [37], Copyright 1997 IEEE).

310

MEMS Residual Stress Characterization: Methodology and Perspective

temperature and mechanical strain [44]. The phenomenon of Raman scattering and the effects of mechanical stress on the Raman spectrum of single-crystal silicon have been extensively studied and documented [45]. Englert, et al., used Raman spectroscopy to characterize the stress state of polysilicon ﬁlms deposited on sapphire substrate [46]. As shown in Fig. 18.9 [44], in micro-Raman spectroscopy, monochromatic radiation such as a laser light is focused on the sample through a microscope to a spot size of 1 μm. The laser beam irradiates the sample causing the scattered photons to lose a quantum of lattice energy (phonon) relative to the incident photons. The scattered light, which carries the Raman signals, is collected and directed into a spectrometer. The spectrometer measures the intensity of the Raman signal as a function of frequency. When the sample is unstressed (no applied strain), the spectrometer measures a reference spectrum. When the device is placed in a stressed state, the Raman spectrum displays a shift in frequency with respect to the reference spectrum: ⎡1 1⎤ Δω ⎢ ⎥ ⎢λ λs ⎥⎦ ⎣ i

(18.9)

where λi and λs are the wavelength of the incident and scattered radiations, respectively. Detailed derivation can be found elsewhere [47]. This quantity is called the Raman shift and is typically reported in units of cm1. For ω0 521 cm1, and using the phonon deformation potential of Anastassakis, et al. [43], we obtain σ xx ≅ 434Δω

(18.10)

and using the phonon deformation potentials of Chandrasekhar, et al. [48], one also obtains σ xx ≅ 518Δω

(18.11)

In both Eqn. (18.10) and (18.11), σxx is expressed in units of MPa and Δω in cm1. Corresponding to any measured change in the Raman shift, therefore, is a uniquely determined value of the local uniaxial stress in the ﬂexure. The locality of the measurement is determined by the spot size, which is typically around 1 μm. De Wolf et al., [49] showed a typical strain map for simple LOCOS structures: long Si3N4 stripes with different widths on a silicon substrate [49]. These nitride lines are under tensile stress due to the deposition process. As a result, they compress the Si atoms in the substrate under them causing compressive stress, and they pull at the Si atoms next to the lines, causing tensile stress. This ﬁgure shows the measured shift of the frequency of the Si Raman peak when scanning along a line across the width of such stripes and the residual stress existing in silicon can be obtained by Eqn. (18.9–18.11). In other MEMS and semiconductor applications, Starman, et al., [50, 51] applied μRS to examine and characterize the residual stress in MUMPs polysilicon with different kinds of post-deposition thermal processing to seek stress reduction solutions. Cho, et al. [52] also applied μRS to characterize the stress of a silicon membrane (fabricated via KOH etch) with electroplating permalloy ﬁlms for magnetic actuator applications. Gogotsi, et al. [53] used μRS to characterize the phase transformation and stress generation during wafer slicing and polishing processes.

18.2.6 Vibration Method Ultrasonic techniques for the measurement of stress are based on the variation of the wave speed (i.e., the acoustoelastic effect). which can be conceptually described by the relation V V0 Kσ

Lens

[0,0,1]

[1,1,0] Silicon Incident radiation Scattered radiation

Fig 18.9 ● Schematic illustration of backscattering Raman spectroscopy. Each spectrum corresponds to a stress measurement from a volume 1λμm3 of silicon. Source: Reprinted with permission from Srikar et al. [44], Copyright 2003 IEEE.

CHAPTER 18

(18.12)

where V0 is the velocity of a wave in an unstressed medium, σ is the stress and K is a material dependent parameter known as the acoustoelastic constant. Detailed derivation of the acoustoelastic constant and its complete crystallography orientation dependence can be found elsewhere [54]. In general, waves are launched by a transmitting transducer, propagate through a region of the material, and are detected by a receiving transducer. The technique is often called pulse-echo (monostatic) if the same transducer is used for excitation and detection, and as pitch-catch (bistatic) if different transducers are used. In MEMS, this conﬁguration can be realized by designing piezoelectric SAW devices. On the other hand, for constrained structures, their resonant frequencies shift if residual stresses exist. This 311

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is because the natural frequency is proportional to the square root of the equivalent stiffness of the structure and the stiffness can be changed by the presence of residual stress. Basically, the existence of tensile residual stress will stiffen the structure and increase the natural frequency, and vice versa. For a beam simply supported at both ends, the natural frequency can be expressed as [10, 55] ⎡ ⎤ 12σ R L2 ⎥ π h E⎢ f 2 ⎢ 1 2 2 ⎥ ρ⎢ 2 12 L π Eh ⎥ ⎣ ⎦

(18.13)

where E, ρ, h, L, and σR are the Young’s modulus, density, thickness, length, and residual stress of the beam. A more accurate expression obtained by Wylde [56] using Rayleigh’s quotient for fB beam is

ωn2

(2π )4 ⎛⎜ EI ⎞⎟ 1 (2π )2 ⎛⎜ σ R ⎞⎟ 1 ⎟⎟

⎜ ⎟ ⎜⎜ (18.14) 3 ⎜⎜⎝ ρ ⎟⎟⎠ L2 3 ⎜⎝ ρ A ⎟⎠ L4

A typical testing system is schematically shown in Fig. 18.10. Zhang, et al., [57] reported on the simultaneous measurement of the Young’s modulus and residual stress in single-crystal silicon beams with clamped boundaries at both ends. If the beam is very ﬂexible (i.e., a string), the frequency is simply f ≈

1 σR 2L ρ

(18.15)

structures [59]. Therefore, the structure’s frequencies are usually measured under vacuum conditions in order to obtain accurate mechanical properties. Manceau, et al., used plate vibration techniques to measure the residual stress of electrolytic nickel coating [60].

18.2.7 Electrostatic Actuation: the M-Test Method The M-Test concept is based on an array of microelectromechanical test structures (cantilever beams (CB), ﬁxed-ﬁxed beams (FB), and clamped diaphragms (CD)) of varying dimensions [61]. They are all suspended above a ﬁxed ground plane by a gap (see Fig. 18.11, [61]). In each case, a voltage is applied to the upper movable conductor, causing it to deﬂect downward toward the underlying ﬁxed ground plane due to the electrostatic attraction. At a critical “pull-in” voltage, VPI, the upper conductor becomes unstable and spontaneously collapses (or pulls in) to the ground plate (also schematically shown in Fig. 18.11). The pull-in voltage is related to the test structure’s geometry and intrinsic material properties. In comparison with other methods, such as tensile testing or optical method, this method has the advantage of rapidly changing the loading state and testing a batch of specimen simultaneously. However, the modeling is far more complicated and indirect than these traditional methods. The pull-in voltage can be expressed as [61]

Kim and Allen [58] used this expression to evaluate the tensile residual stress in microfabricated polyimide structures. It is important to note that air damping and squeezed-ﬁlm damping can also lead to signiﬁcant shifts in the resonant frequencies of microfabricated CCD

VPI

γ1n

⎡ ⎢⎣

ε0 L2 Dn (γ2n ,k,L) ⎢1 γ3n

contact

Monitor

+

2 μm Polysilicon

Head

g0 ⎤ ⎥ W ⎥⎦

(18.16)

2 μm freespace gap

Vc Silicon

–

(a)

M-test cantilever

0.5 μm Nitride

Output PZT drive Tracking Attenuator

Vacuum pump

Fig 18.10 ● Schematic plot of dynamic tests.

312

Input Spectrum analyser

Normalized gap (g/gO)

Pull-in effect Laser-doppler vibrometer

Vacuum chamber

(b)

1 Stable region

Unstable region 0

0

Normalized voltage (Vc/Vpi)

1

Fig 18.11 ● Schematic plot of the CB in M-test. (a) A schematic of testing structures and (b) a schematic plot to show the pull-in effect. Source: reprinted with permission from Osterberg and Senturia [61], Copyright 1997 IEEE.

MEMS Residual Stress Characterization: Methodology and Perspective

CHAPTER 18

where 2 ⎡⎣1 cosh(γ2n kL/2)⎤⎦

(γ2n kL/2)sinh(γ2n kL/2) σ tg 03

(18.17)

3 g 3 represent the and B Et 0

and k 12S/B and S stress and bending parameters. The numerical constant γin can be found in [61]. where n 1, 2, 3 represent the CB, FB, and CD cases, respectively, and L is the beam length or the radius of the test diaphragm. For a given test structure set, once the pull-in voltages are obtained, the S and B parameters can be determined through a correlation process. Together with the thickness and initial air gap measured by metrology characterization, it is possible to extract the material properties (speciﬁcally, E and ν) and the residual stress σ of the material. One major problem of the M-test is the trade-off between modeling complexity and accuracy. The preceding analyses are based on ideal situations. However, in reality, the imperfection of MEMS structures could significantly increase the modeling errors. These imperfections include compliant supports, existence of built-in imposed bending moment due to stress gradient, substrate curvature, and so on. Certain types of these imperfections have been considered to obtain a better model. Nevertheless, the method is now being successfully applied to structures with high residual stress and compliant supports [62], at least for the purposes of monitoring process uniformity and repeatability. However, it is difﬁcult to create a model to account for all imperfections issues.

18.2.8 Indentation Characterization Indentation testing is a simple method to determine material properties such as Young’s modulus and microhardness, fracture strength and toughness. Zhang, et al., developed a semi-empirical formulation to assess residual stresses in SiO2 and Cr thin ﬁlms deposited on Si wafers using Vickers indentation fracture tests [63]. In direct analogy, considerable efforts have been made to develop nanoindentation techniques to characterize microscale structures, and commercial instruments have been developed [64]. In a typical test, a diamond tip with well-deﬁned geometry (i.e., spherical, Vickers, Berkvitch, or cone type) is contacted onto the test structure, and the depth of penetration (h) is measured as a function of the applied load (F). A schematic plot of F–h curve is shown in Fig. 18.12. Readers can refer to ref [65] for more technical detail. In general, compressive residual stress would enhance the material hardness and vice versa (see Fig. 18.13). By examining the F-h curves from both computer simulation and experimental data with systematic dimensional analysis, it is possible to extract the residual stress of structures [66].

Loading

Load, F

Dn 1

Unloading

S

Depth, h

hmax

Fig 18.12 ● A typical nanoindentation load-deﬂection curve. Source: reprinted from Chen et al. [66], Copyright 2008, with permission from Elsevier.

Fig 18.13 ● Finite element simulation to indicate the effect of residual stress. The compressive stress tends to enhance the material hardness and vice versa. Source: reprinted from Chen et al. [66], Copyright 2008, with permission from Elsevier.

Another way to determine the level of residual stress is to examine the shape of the pile-up occurring at the edge of the contact circle. Deviations in shape give some information about the level and sign of residual stress within the specimen. In addition, one may also like to examine the critical load to initiate cone cracks in brittle material to determine the magnitude and direction of surface residual stresses in brittle materials. Yet another method uses the size of median cracks generated with sharp indenters in brittle solids as a means of determining the level of residual stresses arising from tempering. The level of residual stress can be determined as [67] σR

χ(P* P ) 1.16c2

(18.18)

where P* and P are the loads that produce cracks of the same radius c in tempered glass with a residual stress 313

Measuring MEMS

PA R T I I I

and annealed glass, respectively, and, for a Vickers indenter, where χ

1 π

3/2

tan 68

(18.19)

Deviations in shape of the load-displacement response from the ideal shape could also be used as an indication of residual stresses, but experiments show that the effect is too small to be measured accurately [68–69]. Recently, Taljat and Pharr [70] also derived a formula based on spherical indentation. The residual stress can be expressed as ⎛ 4E* ⎞⎟ a ⎟⎟ σ R Y ⎜⎜⎜ ⎜⎝ 3.3π ⎟⎠ R

(18.20)

where E* is the so-called reduced modulus, Y the yield strength, and (a/R) is the indentation strain.

18.3 Perspective and Conclusion 18.3.1 Perspective The mechanical nature of MEMS implies that the state of stress of MEMS devices is critical for their performance and reliability. These facts are critical for the longevity of any MEMS devices during service. As a result, the way to access the residual stresses generated during fabrication and the development of associated MEMS residual stress control techniques are important. Due to the size limitation, this article can only provide a very brief introduction on the MEMS residual stress characterizations. There are more methods in MEMS stress characterization than introduced in this article. With the continuous growth of MEMS technology and new techniques, new requirements shall continuously provide driving forces to stimulating the development of novel characterization techniques. In comparison with material testing in conventional scale, characterization in MEMS scale is usually much more difﬁcult due to constraints in specimen fabrication, handling, mounting, and applying load. In addition, transduction is also an important concern. That is, available sensors and actuators are constrained by the size of test specimens. Besides, the tiny dimension of test devices also imposed problems on the resolution of instrumentation; that is, the measured quantities now are close to the limitation of instruments. For example, a very small deformation may represent a signiﬁcant strain and the resolution of experimental results could be very rough for MEMS scale material characterization. It is also important to point out that most MEMS residual stress characterization activities focus on obtaining 314

the measurable quantities such as force and deformation. However, as addressed previously, residual stresses or strains are intensive and nonmeasurable quantities. They must be deduced from the measurable force and deformation data, together with models from mechanics of materials, theory of elasticity, or photonics. In many MEMS material characterization publications, researchers directly utilize simple formulas from mechanics or materials textbooks. Without carefully paying attention to examining the basic assumptions and understanding the restrictions as well as the limitations of these formulas, signiﬁcant errors could result. In certain types of mechanical testing—for example, uniaxial tensile testing— the modeling is relatively straightforward. However, in many other testing methods, such as ﬁxed-ﬁxed beam bending, bulge, M-test, and even nanoindentation, the modeling complexities and uncertainties are much higher and the generic formulas can only handle the ideal situations. Numerical methods such as ﬁnite element analysis are usually required in extracting the ﬁnal results. However, some characterization methods usually involve coupling between different energy domains and the complexity in solution process may make it difﬁcult to obtain accurate results. At present, it seems that most MEMS residual stress characterization efforts are focused on the aspect of experimental measurement, including inventing novel MEMS structures and new MEMS testing methods. On the other hand, the mechanics for converting the obtained raw data into the ﬁnal residual stress information is usually adapting the classical mechanics of solids. In certain cases, these classical formulas must be modiﬁed to reﬂect the reality met in MEMS structures. Therefore, in the future, in parallel to the continuous improvement in experimental work, extensive effort should also be paid to modeling to convert the test data into the ﬁnal result accurately. Due to the size effect in instrumentation and the uniformity and controllability in the fabrication process, the scattering and conﬁdence of MEMS material characterization are always signiﬁcant concerns. Since the characterized properties are “measured” by manipulating the measured data and specimen geometry through certain models, the uncertainties in all measured quantities and specimen geometry are accumulated in the ﬁnal results. In general, smaller specimens yield higher levels of uncertainty and this concern may eventually impose limitation to the further dimension reduction in specimen design. It is expected that in the future, as the scale is expected to be further shrunk down, the material characterization would face more challenges in both the accuracy of experimental measurement and the modeling to precisely account for the size-dependent effects. Due to its inherent importance for device reliability, although it would face more difﬁculties, residual stress characterization, would still be an important research subject in the future.

MEMS Residual Stress Characterization: Methodology and Perspective

18.3.2 Conclusion In this article, the MEMS residual stresses characterization techniques are brieﬂy introduced and the fundamental principle of residual stress characterization methods is addressed. Because a well-understood material property of MEMS materials is essential for device design, performance estimation, fabrication, and even commercialization,

CHAPTER 18

and a strong size or process dependent nature of material properties, it is important to perform material characterization, especially the residual stresses, once the process parameter varies. In addition, as stated previously, the appropriate mechanics models for data conversion, the statistical techniques to handle the expected scattering of testing data are also essential for a successful material characterization including residual stresses.

References 1. K.-S. Chen, Techniques in Residual Stress Measurement for MEMS and Their Applications. in MEMS/ NEMS Handbook: Techniques and Applications, Vol. 4, Ch. 9, pp. 263–340, Edited by C. T. Leondes, Springer-Verlag, 2006. 2. W. Trimmer (Ed.), Micromechanics and MEMS: Classic and Seminal Papers to 1990, IEEE Press, 1997. 3. M.J. Madou, Fundamentals of Microfabrication, CRC Press, 1997. 4. G. Kovacs, Micromachined Transducers Sourcebook, McGraw-Hill, 1998. 5. M. Gad-el-Hak (Ed.), The MEMS Handbook, CRC Press, 2002. 6. K. Petersen, Proc. Silicon as Mechanical Materials IEEE 70 (1982) 420–457. 7. W.N. Sharpe, A new technique for measuring the mechanical properties of thin ﬁlms, IEEE J Microelectromech. Syst. 6 (1997) 193–199. 8. W.N. Sharpe, Mechanical Properties of MEMS Materials, in: M. Gad-el-Hak (Ed.), The MEMS Handbook, CRC Press, Boca Raton, FL, 2001. 9. S.M. Spearing, A critical review of microscale mechanical testing methods used in the design of microelectromechanical systems, Acta. Mater. 48 (2000) 179. 10. V.T. Srikar, S.M. Spearing, Full ﬁeld water level thin ﬁlm stress measurement by phase-stepping shadow moiré, Exp. Mech. 43 (2003) 238–247. 11. L.B. Freund, S. Suresh, Thin Film Materials, Stress, Defect Formation and Surface Evolution, Cambridge University Press, 2003. 12. J. Lu (Ed.), Handbook of Measurement of Residual Stresses, Fairmont Press, Liburn, GA, 1996. 13. P.J. Withers, H. Bhadeshia, Residual stress part I – measurement techniques, Mater. Sci.Technol. 17 (2001) 355–365. 14. P.J. Withers, H. Bhadeshia, Residual stress part 2 – nature and origins, Mater. Sci. Technol. 17 (2001) 366–375.

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61. P.M. Osterberg, S.D. Senturia, M-TEST: a test chip for MEMS material property measurement using electrostatically activated test structures, IEEE J. Microelectromech. Syst. 6 (1997) 107–118. 62. R.K. Gupta, Ph.D. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1997. 63. T.-Y. Zhang, L.-Q. Chen, R. Fu, Measurements of residual stresses in thin ﬁlms deposited on silicon wafers by indentation fracture, Acta. Mater. 47 (1999) 3869–3878. 64. W.C. Oliver, G.M. Pharr, An improved technique for determining hardness and elastic modules using load and displacement sensing indentation experiments, J. Mater. Res. 7 (1992) 1564. 65. A.C. Fischer-Cripps, Nanoindentation, Springer, 2002, Ch. 3. pp. 36–58. 66. K.-S. Chen, T.-C. Chen, K.-S. Ou, Development of semi-empirical formulation for extracting materials properties from nanoindentation measurements: residual stresses, substrate effect, and creep, Thin Solid Films 516 (2008) 1931–1940. 67. S. Chandrasekhar, M.M. Chaudhri, Indentation cracking in soda-lime glass and ni-zn ferrite underknopp and conical indenters and residual stress measurements, Phil. Mag. A67 (1993) 1187–1218. 68. T.Y. Tsui, W.C. Oliver, P.M. Pharr, Inﬂuence of stress on the measurement of mechanical properties using nanoindentation part 1: experimental studies in an aluminium alloy, J. Mater. Res. 11 (1996) 752–759. 69. A. Bolshakov, W.C. Oliver, G.M. Pharr, Inﬂuence of stress on the measurement of mechanical properties using nanoindentation: part II: ﬁnite element simulations, J. Mater. Res. 11 (1996) 760–768. 70. B. Taljat, G.M. Pharr, Mat. Res. Soc. Symp. Proc 594 (2000) 519–524. 71. L. Elbrecht, U. Storm, R. Catanescu, J. Binder, Comparison of stress measurement techniques in surface micromachining, J. Micromech. Microeng. 7 (1997) 151–154. 72. T. Ikehara, R.A.F. Zwijze, K. Ikeda, A new method for an accurate determination of residual strain in polycrystalline silicon ﬁlms by analyzing resonant frequencies of micromachined beams, J. Micromechan. Microeng. 11 (2001) 55–60.

19

Chapter Nineteen

Strength of Bonded Interfaces Örjan Vallin1 and Kerstin Jonsson2 1

Uppsala University, Uppsala, Sweden NanoSpace AB, Uppsala, Sweden

2

Integrated circuit technology and its later development, microsystem technology, make good use of wafer bonding. The bond strength is considered one of the most important characteristics to determine about a bond. Bond strength measurements contribute to the understanding of chemical reactions behind the bonding process, bonding optimization, and quality assurance. In many cases, the survival of the wafer bond in later processing steps, or the performance of the ready-made component, proves that the bond is good enough. In other cases, it must be determined whether rough estimates will sufﬁce or if more reliable data are desired. The intended use should determine the choice of method. In this section, commonly used bond test methods are brieﬂy presented together with suggestions of improvement. A more complete treatise is given by Vallin et al. [1]. For reliable measurements, it is not enough to consider the measurement procedure only—the mathematical modeling of raw data is equally important. Solid mechanics shall ﬁrst be addressed, as it is the base of the models valid for bond strength measurements.

19.1 Solid Mechanics In order for fracture to occur, it is necessary that the local stress at the crack tip reaches the theoretical strength of the material and that the fracture is accompanied by a global reduction of energy in the material. Immediately before fracture, the crack driving and crack resisting forces are equal. From this, two material parameters can be derived, both called fracture toughness. One is deduced from system energy considerations

and the other from local stress, strain, and displacement at the crack front. System energy considerations yield the fracture toughness, also called critical energy release rate, as GIc

δ2 ∂C δ F 2 ∂C Fδ ∂C , where C 2 2 ∂A 2C ∂A F 2C ∂A (19.1)

The tree equivalents show that it is possible to determine fracture toughness through load F only, from load and load-point displacement δ, or from displacement alone. If the compliance C of the structure is known as a function of crack area A, GIc can readily be determined. The other approach yields the fracture toughness as KIc σ F ⋅ Y ⋅

a

(19.2)

This is also called the critical stress intensity factor and depends on the fracture stress σF, a geometry factor Y, and the crack length a. Tabulated values for Y can be found for simple crack and loading geometries [2]. Complicated cases demand numerical calculations. Strictly, this equation is only valid for atomically sharp cracks. It is approximate for short cracks of small opening angle and for long cracks of arbitrary opening angle. For brittle materials, Eqs 19.1 and 19.2 are related through KIc

E* ⋅ GIc

(19.3)

E* is the effective Young’s modulus that is prevalent under plane deformation, a condition always fulﬁlled for

317

Measuring MEMS

PA R T I I I

brittle specimen larger than micrometer size. It considers the lateral contraction through Poisson’s ratio, ν, as E*

t

δ

E

t

(19.4)

1 ν2

a

Fig 19.1 ● Schematic drawing of a double cantilever beam test. The beams are forced apart by insertion of a thin blade into the bond interface. The crack length a is a measure of adhesion.

19.2 Double Cantilever Beam Test Method The most commonly used method to measure strength of wafer bonded interfaces is the double cantilever beam (DCB) method, which is often called the crack opening or the razor blade method. Using this method, the bonded samples are forced apart by inserting a thin blade into the bond; see Figure 19.1. The length of the resulting crack is a measure of bond strength. The raw crack length can be used for simple strength comparisons of geometrically identical samples. To enable comparisons between geometrically different samples, equations are used to calculate the bond strength in terms of critical energy release rate, GIc. In wafer bond literature, the cohesive surface energy, γc, is often used instead. This is half the value of GIc. The equations derived for DCB measurements are based on beamlike geometries. In the simplest form, the model assumes that a forced displacement only gives rise to bending stress in the beams. Shear stress is neglected, and so is stress in the uncleaved part of the specimen. Several experimentally veriﬁed models taking these effects into account have been derived. A suitable expression for anisotropic silicon was derived for laminates [3] and reads GIc

3 ⋅ E* ⋅ δ 2 ⋅ t3 16 ⋅ a

4

⋅

1 ⎛ ⎞4 ⎜⎜1 χ ⋅ t ⎟⎟ ⎜⎝ a ⎟⎠

(19.5)

E* is the effective Young’s modulus along the beam, δ is the blade thickness, t is the beams’ thicknesses, and a is the crack length. χ is given by χ

2 ⎞ ⎛ ⎛ s11 ′ ⋅ s22 ′ ⎞⎟⎟ ⎟⎟⎟ s44 ′ ⎜⎜ ⎜ ⎜3 2⎜⎜1

⎟ ⎟ ⎜⎜⎝ 11 ⋅ s11 ′ ⎜⎜⎜ 1.18 ⋅ s44 ′ ⎟⎟⎠ ⎟⎟⎟ ⎝ ⎠

(19.6)

Here, the s’ii are the compliances for the beams. s’11 is the along-the-beam direction, and s’22 is orthogonal to the crack surface. s’44 is the shear compliance oriented parallel to the crack front. The factors 11 and 1.18 are empirical. As the expression (19.5) seems complicated, it is tempting to use the ﬁrst term only. This may result in a gross and geometry dependent overestimation of GIc. 318

The full equation can, however, readily be put into a spreadsheet computer program for repeated calculations. Details are presented in Ref. [1], together with instructions on how to derive equations for dissimilar beams. The compliance constants for unrotated crystallographic directions can be found tabulated for each material. To achieve reliable results, the measurement has to be performed with care. As mentioned above, the samples should be of beam shape. Other sources of error are related to the crack length, especially as it is raised to the power of four in Eq. 19.5. Efforts have to be made to accurately measure crack length. If measurements are conducted in air, stress corrosion can be a problem, as the steady-state crack length will be inﬂuenced by air humidity. To avoid this phenomenon, the measurement has to be conducted in inert atmosphere, like nitrogen, or the crack length has to be measured with a continuously moving blade [4, 5].

19.3 Tensile Test Method Tensile tests have a long history within the ﬁeld of wafer bonding and are still often used to measure the strength of bonded interfaces. With this method, bonded samples are glued onto pull studs ﬁtting a tensile strain test machine; see Figure 19.2. The studs are thereafter pulled apart, and the maximum force, occurring at separation, is recorded. For identical test geometries, the fracture force can be used for bond strength comparison. To enable comparison between different sample geometries, tensile strength models and fracture toughness models have been used. The tensile strength is deﬁned as the maximum tensile stress that a material can sustain without fracture. While tensile tests are readily used to measure the tensile strength of ductile materials, it is not easy to do this for brittle materials. As brittle materials do not deform plastically, they are sensitive for misaligned loads. With asymmetrical loading, edge defects will cause premature fracture. In order to make geometrically independent comparisons, fracture toughness can be calculated. By introducing

Strength of Bonded Interfaces (a)

Bonded area

(b)

CHAPTER 19

Mechanical clamp

(a)

Test cavity Silicon wafer Bond to be tested Silicon wafer

Inlet pressurised gas 12 9

(b)

2

13

Fig 19.2 ● Tensile test structure with notches to promote fracture initiation at the bond. As the chip area is larger than the pull stud, the rough diced chip edges will not be stressed. In addition, problems with surplus glue ending up at the bond are avoided. To circumvent glue-line fracture, the wafer-bonded area is smaller than the glued area. The measurements are in mm. Source: Reprinted with permission from [6]. Copyright 2003: Elsevier.

fracture-causing cracks at the bond, fracture toughness KIc can be determined according to Eq. 19.2 [7, 8]. Tensile tests are associated with large scatter in measurement data. When the test samples are designed wisely, Figure 19.2, the scatter can be reduced to about 10%. Notches have been introduced to promote fracture at the bond interface. The wafer-bonded area has been made smaller than the glued area to circumvent glue-line fracture. The chip area is larger than the pull stud area to avoid stressing the rough diced chip edges.

19.4 Blister Test Method Blister tests were used early in wafer bonding and have regained interest lately. An internal cavity at the bond interface is pressurized pneumatically or hydrostatically until fracture occurs, Figure 19.3. The fracture pressure is a measure of the bond strength. The fracture pressure can be used for comparison between identical test geometries. For the most commonly used square-cavity geometry, analytical models for fracture toughness are lacking, but with ﬁnite element analysis a solution might be found. For circular cavities, the critical energy release rate can be deduced as GIc

⎛ 8 ⋅ αs ⋅ t 2 ⎞⎟⎟ ⋅ ⎜⎜⎜1

⎟ (19.7) 32 ⋅ E ⋅ t ⎜⎝ 3 ⋅ r 2 ⋅ (1 ν )⎟⎟⎠ 3 ⋅ p2 ⋅ r 4 *

3

Fig 19.3 ● Cross-section of a blister test setup where the test sample is mechanically clamped in the gas load ﬁxture, (a) and a lateral infrared image of a bonded test sample where the gasinlet, supply channel, and test cavity can be seen (b). Source: (a) is reprinted with permission from [9]. Copyright 2000: The Electrochemical Society; the full ﬁgure is reprinted with permission from [1]. Copyright 2005: Elsevier.

where p is burst pressure, r is the cavity radius, E* is the effective Young’s modulus, αs is the shear coefﬁcient, t is the wafer thickness, and ν is the Poisson’s ratio. Commonly, αs is set to 1.5. The ﬁrst term in the equation is related to bending, the second to shear. For long rectangular cavities, the expression reads GIc

2 ⎞ ⎛ ⎜⎜1 6 ⋅ αs ⋅ t ⎟⎟ ⋅ ⎟ ⎜ 24 ⋅ E* ⋅ t3 ⎜⎝ a2 ⋅ (1 ν )⎟⎟⎠

p2 ⋅ a 4

(19.8)

where a is the length of the shortest cavity side. On comparison, the rectangular shape should be preferred for anisotropic materials, as problems with directional dependent elastic moduli are diminished. The blister test has the potential of giving low scatter, mainly thanks to the homogenous load. Unfortunately, ﬁxation of the pressure inlets introduce scatter if it is done with glue on an area right below or above the cavity. Experimental work has shown large reduction in scatter down to 2 to 4% when the gluing has been 319

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replaced with mechanical clamping away from the cavity; Figure 19.3. An advantage with the blister test is that an inert pressure medium can be chosen to avoid stress corrosion.

19.5 Chevron Test Structures The introduction of a specially formed notch, the chevron, Figure 19.4, into the bond under test has improved measurements. Initially, the crack emanates from a welldeﬁned location. Chevrons have been implemented for various load conﬁgurations, such as tensile, three-point bending, and blister tests. For point-loaded samples, the stress intensity factor is given by KI

F w⋅

L

⋅Y

(19.9)

where F is the applied load, and w and L are the length and width, respectively; Figure 19.4. The geometry factor Y for chevron shaped specimens consists of two factors. The ﬁrst is equal to that of straight-notched specimen, while the second one describes the chevron geometry Y

w ⋅ L ⋅ E* ∂C ⋅ ⋅ 2 ∂a

a1 a0 a a0

(19.10)

where E* is the effective Young’s modulus and ∂C/∂a is the derivative of the compliance with respect to the crack length. For instance, the compliance presented

(a)

for the double cantilever beam test can be used, if the geometry resembles beams. Initially, the crack exhibits a stable growth with increasing load, since the crack width increases when the crack propagates. Here, simultaneous measurement of force and crack length gives fracture toughness. When the crack reaches a critical length, the growth becomes unstable, which leads to catastrophic failure. As this crack length depends only on geometry and loading conditions, the critical load itself is a measure of bond strength. Thus, the measurement procedure is simpliﬁed.

19.6 Summary and Outlook Several techniques for the determination of the strength of bonded interfaces coexist. Common to these is that good measurements only can be made with a holistic approach to the experimental setup, where every source of measurement error is addressed. Furthermore, careful mathematical modeling or numerical analysis is needed to obtain geometry independent values. Nondestructive methods would be desirable, but up until now, no such reliable methods have been developed. The main reason is that it is difﬁcult to ﬁnd physical models that describe fracture with entities other than purely mechanical. For blister tests, the introduction of chevron structures shows a promising way to perform nondestructive tests on wafers in production, if areas are reserved for the structures. The cavity itself does not have to be broken; instead, the pressure is limited to levels below critical values and the crack-lengthto-pressure ratio could be used to calculate the bond strength [10].

(b)

F

L

L

t w

w(a)

t

a0

a0

a

a a1

a1 F

Fig 19.4 ● Schematic drawing of a chevron notched specimen under point load. View of fracture plane (a) and side view of the specimen (b). Under load F, the crack, starting from a0, has reached a, where the local width is w(a). Source: Reprinted with permission from [1]. Copyright 2005: Elsevier.

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References 1. Ö. Vallin, K. Jonsson, U. Lindberg, Adhesion quantiﬁcation methods for wafer bonding, Mater. Sci. Eng. R: Rep. 50 (4–5) (2005) 109–165. 2. Y. Murakami (Ed.), Stress Intensity Factors Handbook, vols. 1 and 2. Pergamon, Oxford, UK, 1987. 3. J.G. Williams, End corrections for orthotropic DCB specimens, Comp. Sci. Technol. 35 (4) (1989) 367–376. 4. K.-T. Wan, N. Aimard, S. Lathabai, R.G. Horn, B.R. Lawn, Interfacial energy states of moisture-exposed cracks in mica, J. Mater. Res. 5 (1) (1990) 172–182. 5. Y. Bertholet, F. Iker, J.P. Raskin, I. Pardoen, Steady-state measurement

of wafer bonding cracking resistance, Sens. Actuators A: Phys. 110 (1–3) (2004) 157–163. 6. H. Takagi, R. Maeda, T. Suga, Waferscale spontaneous bonding of silicon wafers by argon-beam surface activation at room temperature, Sens. Actuators A: Phys. 105 (1) (2003) 98–102. 7. J. Bagdahn, D. Katzer, M. Petzold, M. Wiemer, The inﬂuence of sharp notches on the strength of directly bonded components 31 August–5 September 1997, in: Proceedings of the Fourth International Symposium on Semiconductor Wafer Bonding: Science, Technology, and Applications,

Electrochemical Society, Paris, France, 1997. 8. H. Takagi, R. Maeda, T. Suga, Roomtemperature wafer bonding of Si to LiNbO3, LiTaO3 and Gd3Ga5O12 by Arbeam surface activation, J. Micromech. Microeng. 11 (4) (2001) 348–352. 9. J. Köhler, K. Jonsson, S. Greek, L. Stenmark, Weibull fracture probability for silicon wafer bond evaluation, J. Electrochem. Soc. 147 (12) (2000) 4683–4687. 10. M. Rabold, A. Doll, F. Goldschmidtboeing, P. Woias, The modiﬁed blister test method, J. Electrochem. Soc. 154 (7) (2007) 647–652.

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20

Chapter Twenty

Focused Ion and Electron Beam Techniques Oliver Wilhelmi1, Steve Reyntjens1, Brandon Van Leer2, Paul A. Anzalone2 and Lucille A. Giannuzzi2 1

FEI Company, Eindhoven, The Netherlands FEI Company, Hillsboro, OR, USA

2

20.1 Brief Introduction to DualBeam Instrumentation A DualBeamTM is a focused ion beam (FIB) column and a scanning electron microscope (SEM) on the same platform. A general review of FIB and DualBeam theory, applications, and techniques may be found in the text edited by Giannuzzi and Stevie [1]. Commercial FIB columns generally use Ga ions and are available with energy ranges from 500 eV to 30 keV, beam currents from 1 pA to 65 nA, with ultimate resolution of 5 nm. Commercial SEM columns are available with energy ranges from 200 eV to 30 keV, with beam currents up to 200 nA, with an ultimate resolution of 0.9 nm. The FIB or SEM can be directly used for fabrication of MEMS/ NEMS structures. Ion beam or electron beam assisted chemical vapor deposition (CVD) is accomplished by scanning the beam in the presence of a suitable precursor gas (e.g., organometallic). Electron beam writing may be performed in electron sensitive polymers such as PMMA. In addition, enhanced ion beam sputtering or electron beam etching can be accomplished by scanning either beam in the presence of a chemically reactive gas. The electron or ion beam energy and spot size (i.e., beam current) may be varied to yield different milling or deposition characteristics. At the eucentric position of the sample stage, the FIB and SEM operate with both beams at a common coincidence point on the sample. Thus, the SEM can image any FIB procedure (i.e., either milling or deposition) either intermittently or simultaneously throughout the process. This allows for direct feedback or end-pointing of any FIB procedure.

DualBeam techniques may be utilized to either directly fabricate MEMS/NEMS devices or to site speciﬁcally section and image MEMS/NEMS devices—for example, for materials characterization, failure analysis (FA), or quality control of the MEMS/NEMS structures.

20.2 FIB for Direct Milling and Deposition of Structures FIB milling can be used to site speciﬁcally remove material to create MEMS/NEMS devices. Examples in FIB milled devices are shown in Figure 20.1 below. Figure 20.1a is a FIB milled Fresnel lens in Si, and Figure 20.1b shows several nano-ﬂuidic devices that were site speciﬁcally FIB milled in Si using the ﬁducial mark in the upper left portion of the ﬁeld of view for reference. The Fresnel lens was milled using predeﬁned concentric circles, and the nano-ﬂuidic structure was FIB milled directly from a bitmap ﬁle. The width of a single ﬂuidic device is 5 μm, and the width of the smallest FIB milled line in the device is 90 nm. The FIB can also be used to site speciﬁcally deposit structures either in the plane or out of the plane of the substrate. Figure 20.2a shows a structure that was deposited using the bitmap ﬁle shown in the inset at the bottom of the ﬁgure. The deposit height varies where different bitmap grayscale values deﬁne unique dwell times of the beam. Figure 20.2b shows a 3D example of spirals fabricated by controlling the dwell and overlap position of the beam in time. 323

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Fig 20.1 ● (a) FIB milled Fresnel lens. (b) FIB milled nano-ﬂuidic devices.

Fig 20.2 ● (a) FIB deposited structure. (b) FIB deposited 3D spirals.

20.3 SEM for Direct Deposition or Lithography of Structures Figure 20.3a shows an example of electron beam deposited concentric rings of cones deposited from a Pt-based organometallic precursor gas. Each cone base is 200 nm, and the cones are spaced 500 nm apart. The SEM can also be used for electron beam lithography applications using metallization and lift-off techniques as shown in Figure 20.3. 324

20.4 DualBeam Applications of FA and Characterization of MEMS Devices An extremely useful application of the DualBeam is for direct characterization, quality control, and FA of MEMS structures. The microscopic optical semiconductor mirror device that is the backbone of the Texas Instruments DLP® projection systems is a well-known commercially available MEMS structure. Figure 20.4

Focused Ion and Electron Beam Techniques

CHAPTER 20

Fig 20.3 ● (a) Electron beam deposited cones; (b) electron beam lithography of a test structure in GaAs.

shows an SEM image of a FIB cross-section mirror device. The Si substrate and multi-metal layers can be seen in the semiconductor MEMS device. The arrows point to various defects in the device. A missing piece of the top mirror is shown. In addition, cracks in the pivot arm holding the mirror can be seen. Defects in metal 1 and metal 2 layers are also observed. Thus, the DualBeam can be used to directly prototype or manufacture MEMS devices as well as characterize the devices made by the DualBeam or by some other process.

Reference 1. L.A. Giannuzzi, F.A. Stevie (Eds.), Introduction to Focused Ion Beams, Springer, 2005, New York.

Fig 20.4 ● An SEM image of a FIB cross-sectioned DLP® mirror MEMS device. The arrows indicate various defects in the MEMS device.

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21

Chapter Twenty One

Oxygen and Bulk Microdefects in Silicon Hele Savin1 and Veli-Matti Airaksinen2 1

Department of Micro and Nanosciences, Faculty of Electronics, Communications and Automation, Helsinki University of Technology, Espoo, Finland 2 TKK Micronova, Faculty of Electronics, Communications and Automation, Helsinki University of Technology, Espoo, Finland

21.1 Measuring Oxygen in Silicon 21.1.1 Oxygen in Silicon Crystalline silicon grown with the Czochralski method contains high concentrations of oxygen, in the range of 5 1017 1 1018 atoms per cubic centimeter. Oxygen atoms initially occupy interstitial sites in the crystal lattice. However, due to high-temperature thermal treatments oxygen can agglomerate to form precipitates, which can be quite large clusters of oxygen combined with crystal defects (for details see Chapter 4). Oxygen increases the mechanical strength of silicon substantially, leading to increased resistance to plastic deformation, a particularly important property during high temperature processing. Oxygen precipitates, on the other hand, affect wet etching, causing defective etched surfaces. Oxygen content is an important parameter and has to be controlled to maintain consistent, desirable wafer properties. The main methods for the quantitative determination of interstitial oxygen are infrared spectroscopy, gas fusion analysis (GFA), and secondary ion mass spectroscopy (SIMS) [1, 2]. The quantitative determination of oxygen precipitation is based on the comparison of interstitial oxygen concentrations measured prior to and after precipitation treatment [3]. However, this technique does not provide any information on the density and size distribution of precipitates. Such data can be obtained with chemical etching, scanning infrared

microscopy (SIRM), light scattering tomography (LST) or optical precipitate proﬁler (OPP).

21.1.2 Fourier Transform Infrared Absorption Spectroscopy Fourier transform infrared (FTIR) spectroscopy is the most common method for measuring interstitial oxygen. It is based on the absorption of light by the antisymmetric vibrations of Si2O complexes, or wave-number of 1107 cm1 (corresponding to the wavelength of 9.033 μm). This technique is calibrated with 2-mm-thick, double-side polished standard samples. Often, to be able to use production wafers, measurements are made from thinner slices down to 0.4 mm, and suitable transfer standards have to be used for calibration. The measurement is also affected by the surface ﬁnish of the wafer, as this affects the multiple reﬂections inside the sample. The conversion factor for converting the absorption coefﬁcient to oxygen concentration has been determined in several different standards. Several of the older calibration factors are still used, in addition to the newest, IOC-88, and to avoid confusion one should always take care to make sure of the standard used. As shown in Table 21.1, the discrepancies in the values given by the ASTM calibrations compared with the IOC-88 are quite signiﬁcant. Infrared absorption measurements work well only for relatively high-resistivity silicon. For carrier concentrations

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Table 21.1 Conversion factors for intrinsic oxygen concentration

Relative conversion factor IOC-88

1

New ASTM

0.78

Old ASTM

1.533

JEIDA coefﬁcient

0.965

Guo Biao (old edition)

0.987

From Ref. [4].

above 1 1016 cm3 (corresponding to a resistivity below 1 ohm-cm in n-type silicon, and below 3 ohm-cm in p-type silicon) the absorption by free carriers affects the measurement, and calibration samples with identical free-carrier concentrations have to be used. High free-carrier concentrations reduce the intensity of the transmitted light and the method becomes unsuitable for normal use below about 0.1 ohm-cm (even though cryogenic absorption measurements of very thin samples down to 0.03 ohm-cm have been reported). Infrared absorption measurements have also been developed for the characterization of uncut silicon ingots. Such instruments are capable of automatic mapping of carbon and oxygen concentrations, and allow fast, accurate control of crystal growth parameters.

21.1.3 GFA For GFA, silicon samples are inserted in a graphite crucible, together with high-purity nickel as a metal ﬂux, and are melted by heating the sample in an inert gas to about 2000°C. Interstitial oxygen reacts with carbon, forming carbon monoxide (CO) gas which is detected with an infrared detector. GFA needs to be calibrated against samples with known concentrations of impurity. GFA allows the simultaneous detection of nitrogen as well as oxygen. An important disadvantage of GFA is that it measures the total oxygen concentration present in the sample, including oxygen precipitates.

21.1.4

SIMS

In SIMS the sample is bombarded with an ion beam in an ultrahigh vacuum chamber, and the secondary ions sputtered from the sample are analyzed with a mass spectrometer. To reduce the background caused by adsorbed water, the sample has to be heated in a vacuum before the measurement. The oxygen background is checked with a very low oxygen content 328

piece of ﬂoat-zone silicon. For calibration an additional high-resistivity sample with a known oxygen content is included in each batch of samples. Like GFA, SIMS measures the total oxygen concentration. SIMS can achieve a reproducibility better than 2%.

21.2 Measuring Bulk Microdefects Oxygen precipitates and related defects in the silicon bulk are often referred to as bulk microdefects (BMDs). The measurement of these defects can be quite complicated as the defect sizes are often in the nanometer scale. The most common and by far the simplest method used today for measuring the BMD density is called preferential etching. More advanced methods include IR optical systems (e.g., SIRM and LST, which can reveal the size of the defects besides their density). This subchapter lists the methods that can measure the common properties of BMDs.

21.2.1 Preferential Defect Etching The preferential etching of defects is based on the use of a special etching solution, which has a higher etch rate around the microdefects compared with the surrounding defect-free silicon. Consequently, etching reveals the defects intersecting the surface by a small etch pit (precipitates) or a groove (grain boundaries, stacking faults) so that the defects become visible in an optical microscope. The actual defect density is then obtained by counting the etch pits from the microscope image. Notice that the size of the etch pit depends on the size of the defect, its location in the removed surface layer, and the stress related to the defect. Therefore this method can only be used for measuring the BMD density—not the defects’ size distribution. Several possible etching solutions can be used for preferential defect etching in silicon, such as Dash, Sirtl, Secco, Yang, and Wright. Each of these solutions has a characteristic etching behavior that depends on the surface crystallographic orientation and topography. For instance, Dash etch reveals dislocations in all crystallographic orientations but it needs a very long etching time. Sirtl and Yang etching are better suited for (111) and (110) than (100) surfaces. Secco reveals defects in all orientations but it often results in anomalies. The Wright etch is widely used as it is effective in all orientations and works over a wide resistivity range (0.02– 20 ohm-cm). However, its composition is more complex than Secco and Yang and it is in some cases less sensitive to dislocations. In conclusion, there is no single defect etch that is superior to others and therefore the choice of etching solution should be based on the speciﬁc needs and samples under study. Figure 21.1 shows a typical

Oxygen and Bulk Microdefects in Silicon

CHAPTER 21

Fig 21.1 ● Wright-etched silicon wafer showing etch pits due to oxide precipitates and stacking faults. Fig 21.2 ● A SIRM image showing BMDs in silicon. The scanned area is 200 μm by 200 μm. Source: Courtesy of SEMILAB Co., Ltd.

image of a silicon wafer containing oxide precipitates and related defects after Wright etch. Detailed instructions on how to use the above etches are given in Ref. [5]. Advantages of preferential etching include cheap and easy measurement, high sensitivity, and applicability to large wafer areas. In addition, preferential etching can be performed either on cleaved cross-sections or on the polished wafer surfaces. The weakness of the method lies in the unclear interpretation of the results (many artifacts are possible). The interpretation is also complicated by the fact that the detection limit for small precipitates is usually unknown.

In principle, SIRM is capable of measuring the density and size distribution of the microdefects as a function of wafer depth. The densities it can measure accurately cover the range from 107 to 1011 cm3. Typical spatial resolution is in the range of 1–2 μm. The minimum defect size SIRM can measure is of the order of 30 nm. It is important to notice that SIRM measurement needs no surface preparation and the whole measurement can be considered as nondestructive. A comprehensive literature review on detection of BMDs by SIRM is given in Ref. [6].

21.2.3 Light Scattering Tomography 21.2.2 SIRM SIRM is a relatively new technique for measuring BMDs. It is based on the focused infrared laser beam that forms a probe inside the wafer, allowing lateral and vertical scanning. Because most of the BMDs are smaller than the wavelength of the infrared laser (1 μm) the light is scattered, which can be detected and collected either directly or by interferometric techniques. The collected data is used for constructing a 3D map of the defects in the wafer. The scattered light is proportional to the volume of the defect, which makes SIRM very sensitive also to defect size variations. Figure 21.2 shows a typical SIRM image of BMDs. The defects in a SIRM image appear as bright spots if they are in focus and as dark spots if they are slightly out of focus. A software program is used to count the defect density. Typically the scanned area can be set laterally from 50 μm 50 μm to 200 μm 200 μm and vertically about 5 μm deep. The volume of this size can be scanned in about 1 minute.

Light scattering tomography (LST) measurement requires a cleaved cross-section sample and is therefore considered a destructive method, unlike SIRM. During the measurement an infrared laser beam is focused into a wafer through the polished front surface. Bulk defects scatter the laser light to 90° from the incident beam, which is then detected by an infrared camera. LST is capable of measuring the denuded zones (DZ), BMD density, and size distribution of the defects. The sensitivity for detecting small precipitates is slightly better (10 nm) than that of SIRM (Figure 21.3) [7].

21.2.4 Optical Precipitate Proﬁler In the OPP an infrared laser beam is split into two linearly polarized light beams that are focused in the wafer bulk through the polished front surface. The defects in the bulk cause a phase difference between the beams, which is measured by the polarization analyzer to reveal the defects. In principle OPP can be used to detect 329

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Fig 21.3 ● A cross-section of LST measurement showing voids of different sizes. Source: Courtesy of SEMILAB Co., Ltd.

single defects, the DZ depth, and DZ uniformity across the entire wafer. In addition it can be used to measure surface contamination as well as polishing defects [8].

21.2.5 Other Methods

detected by minority carrier lifetime methods, such as surface photovoltage (SPV) or microwave photoconductivity decay (μ-PCD). The beneﬁts of carrier lifetime measurements include fast and contactless measurement; also, lateral distribution of the defects can be estimated from the measured lifetime map. However, interpretation of the results can be quite challenging if other recombination centers are simultaneously present in the wafer. For instance, lifetime degradation due to metal contamination cannot always be separated from BMDs. Even though the additional contamination could be excluded, minority carrier lifetime measurement can be used only to estimate the amount of precipitated oxygen: The density or the size of the defects cannot be directly measured. Figure 33.18 shows an example of the minority carrier lifetime map caused by oxygen precipitates. The morphology of BMDs is affected by the anneal history, doping level, carbon content, and stress [9]. The defect morphology can be studied in detail, for instance, by transmission electron microscopy (TEM).

Oxygen precipitates and related defects act as recombination centers in silicon. Therefore they can be easily

References 1. G. Stingeder, S. Gara, S. Pahlke, H. Schwenk, E. Guerrero, M. Grasserbauer, Quantitative determination of oxygen in silicon by combination of FTIR-spectroscopy, inert gas fusion analysis and secondary ion mass spectroscopy, Fresenius Z. Anal. Chem. 333 (1989) 576–852. 2. Test methods for determining interstitial oxygen content are covered by the following standards: SEMI MF1188-1105, SEMI MF1619-1105, SEMI MF1366-0305, International SEMI Standards, http://wps2a.semi. org, 2005. 3. SEMI MF1239-0305, Test method for oxygen precipitation characteristics

330

of silicon wafers by measurement of interstitial oxygen reduction, International SEMI Standards, http://wps2a.semi.org, 2005. 4. SEMI MO44-00-0305 Guide to conversion factors for interstitial oxygen in silicon, International SEMI Standards, http://wps2a.semi.org, 2005. 5. ASTM Standard F 47-94, Standard test method for crystallographic perfection of silicon by preferential etch techniques, in: 1996 Annual Book of ASTM Standards, Am. Soc. Test. Mat., West Conshohocken, PA, 1996. 6. P. Török, L. Mule’stango, Applications of scanning optical microscopy in materials science to detect bulk

microdefects in semiconductors, J. Microsc. 188 (1997) 1–16. 7. N. Nango, T. Ogawa, T. Irisawa, Minimum size of oxygen precipitates in Czochralski silicon wafers detected by improved light scattering tomography, Jpn. J. Appl. Phys. 44 (2005) 5898–5902. 8. D. Guidotti, M.A. Taubenblatt, S.J. Batchelder, R.L. Kleinhenz, A.A. Dupnock, Non-intrusive mapping of subsurface defects in semiconductors, Appl. Phys. A 55 (1992) 139–143. 9. C. Claeys, J. Vanhellemont, Advances in the understanding of oxygen and carbon in silicon, Solid State Phenom. 6–7 (1987) 21.

22

Chapter Twenty Two

MEMS Lithography Sami Franssila and Santeri Tuomikoski* Department of Materials Science and Engineering, Helsinki University of Technology, Espoo, Finland

Optical lithography is the mainstay of patterning in MEMS: 1X contact/proximity exposure and, to a lesser extent, 5X reduction step-and-repeat systems constitute the bulk of all patterning steps. MEMS patterning is not driven by exposure wavelength reduction and related resolution improvement, but rather by process robustness, etch resistance, thick resists, double-side alignment, and the special needs for severely 3D structures. This chapter discusses lithography in four sections: (i) issues to be answered before wafer processing begins; (ii) issues during lithography process; (iii) photoresist behavior in the process steps after lithography; (iv) special issues concerning thick photoresists.

22.1 Lithography Considerations Before Wafer Processing Before the ﬁrst wafer is exposed, many decisions regarding the patterning process have been ﬁxed. These include mask design, and the actual fabrication of physical mask plates which have to be consistent with the chosen photoresist. Layout design must take into account lithographic alignment tolerances, and the layout design rules concerning minimum lines and spaces, required overlaps, recommended and/or forbidden shapes, etc. Alignment marks must be designed in the *

Currently at VTI Technologies Oy.

photomasks, and the sequence of alignments ﬁxed for all the process steps. Because linewidths are usually not an issue in MEMS devices, photomasks for contact/proximity 1X exposure tools are reasonably priced: 500 ¤/$ is typical for 5 in. soda lime masks with 2–3 μm minimum lines (approximate prices in 2009). Mask size is usually one inch larger than the wafer size: 100 mm (4 in.) wafers are exposed with 5 in. mask plates. If linewidths are smaller than 2 μm, quartz masks must be used instead of soda lime and price will be higher. Larger plates are more expensive; for example, 7 in. soda lime mask costs 1000 ¤/$. Mask prices may go up considerably, depending on extra services or quality guarantees: If 100% checking and defect repair is required, then prices tend to be much higher. Prices will vary according to defect speciﬁcation; e.g., 2 defects/in2 (dpsi) larger than 2 μm will be cheaper than 0 dpsi speciﬁed mask. Similarly, critical dimension (linewidth) tolerances can be made tighter or looser, e.g., 0.15 μm or 0.50 μm. Masks for reduction steppers (a.k.a. DSW aligners) are called reticles. Normally, patterns on reticles are scaled 5X (also other scaling factors are used). Scaling allows easier and, hence, lower-cost mask fabrication but limits maximum area of processed devices, typically to chip size 20 20 mm on wafer. Quite often, reticles can be 5 in. soda lime masks even with submicron linewidths on wafers. There are special alignment marks reserved for the stepper: They are located outside the chip area, and they are not copied on the wafer. It is also possible to use cheap plastic masks (polymer ﬁlms), which is typical in the printed circuit board industry. These ﬁlm masks are fast to make and cost a 333

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few tens of euros/dollars. Minimum feature size is typically in the range of 20–50 μm. For research purposes, this is adequate in many cases for noncritical levels like bonding pads or ﬂuidic ports. In addition to poor resolution, these masks have much worse line-edge roughness than chrome masks. Their opaqueness in UV needs to be checked, especially for thick resists/long exposure times. Film masks have also poor stability against humidity, meaning tighter process control is needed. Several mask design software programs are available, from simple freeware for university systems to full-scale professional sets. It is important to understand the output format of the software: Not all mask shops accept all design formats. GDSII, the standard format for integrated circuit design, is widely accepted, and so is, normally, Autocad DXF; but HPGL or Gerber may not be applicable everywhere. Conversion between formats is possible, but it is often a source of errors or dimensional roundings. Overviews of photomask technology are given in references [1, 2].

22.1.1 Photoresist Selection Resist polarity, negative or positive, and mirroring need to be speciﬁed in conjunction with mask order. Mask design can be converted to either polarity by the mask shop irrespective of the way drawing is done, and once resist polarity is ﬁxed, mask polarity will follow. The resist type should be considered based on requirements in the lithography step, like resistance for plasma etching, adhesion in wet processes, or for some special requirements like sidewall angle. Positive photoresist chemistry deﬁnes that they are not mechanically very strong, but they can easily be stripped away. Negative resists have opposite properties: Some of them are mechanically very strong, but hard to remove. Therefore, those are not necessarily good for patterning, but can be used as such as structural materials in MEMS components. Negative photoresists are based on many different chemistries, e.g., bisazide, epoxy, and polyimide materials have been used as negative photoresists. The cross-linking density of the material is deﬁned by the chemistry of the monomers, which also deﬁnes the properties of the ﬁnal structure. With high cross-linking density, mechanical strength of the materials increases and high aspect ratios can be achieved, assuming correct exposure. In addition to the basic positive/negative choice, resist selection can depend on, e.g., sensitivity (photospeed), resolution, exposure wavelength (i-line 365 nm, h-line 405 nm, g-line 436 nm), exposure latitude, contrast, solvent safety (harmful cellosolve acetate and xylene are used in many older generation resists, but modern resists have, e.g., MEK or PGMEA as the solvents), or glass transition temperature (typically in the range of 100–150°C 334

for positive resists, and above 200°C for many negative and lift-off resists [LOR]). The process step following lithography partly determines resist choice: Vertical sidewalls are good for plasma etching, negatively sloped sidewalls (a.k.a. retrograde) are suitable for lift-off, and positively sloped resist walls are suitable for wet etching or as mould for a casting process. Positive resists typically have 75–85° sidewall angles, while negative resists tend to display sidewall angles over 90° (a.k.a. retrograde proﬁles). Some widely used photoresists are brieﬂy described in Table 22.1. Resist manufacturers usually provide a series of resist formulations that cover a wide thickness range, using the same basic chemistry (and same developer): e.g., AZ series with 1505, 1512HS, 1514, 1518, 1529 have corresponding thicknesses of 0.5 μm, 1.2 μm, 1.4 μm,

Table 22.1 Some widely used photoresists

Material

Polarity

Thickness

Exposure and applications

AZ series

Positive

1–100 μm

UV-exposure; general purpose, electroplating, etching mask

S series

Positive

1–50 μm

UV-exposure; general purpose, electroplating, etching mask

PMMA

Positive

up to mm

X-ray and e-beam exposures; lift-off, electroplating

THB series

Negative

5–100 μm

UV-exposure; electroplating, etching mask

SU-8

Negative

Up to mm

UV, X-ray, and e-beam exposures; electroplating, etching mask, structural components for microﬂuidics and MEMS

Polyimide

Negative

1–50 μm

UV-exposure; electroplating, etching mask, structural components for microﬂuidics and MEMS

Dry-ﬁlm

Negative

50–100 μm

UV-exposure; electroplating, etching mask, structural components for microﬂuidics and MEMS

MEMS Lithography

1.8 μm, and 2.9 μm at 4000 rpm spin speed (and viscosities ranging from 6.3 cSt to 80 cSt at 25°C). Similarly, negative resists SU-8 2005, 2010, 2015 have thicknesses roughly corresponding to 5 μm, 10 μm, and 15 μm (and viscosities of 45 cSt, 380 cSt, and 1250 cSt, respectively). In addition to different thicknesses, these formulations can be optimized relative to thermal stability, wet etch adhesion, exposure speed (HS for High Speed), lift-off, or other properties. Shelf-life of resists is typically 6–12 months under proper storage conditions; but resist spinned on a wafer should be exposed within hours, to avoid water absorption and loss of sensitivity.

22.2 Wafers in Lithography Process In this section the process sequence of lithography is described in a chronological fashion. Table 22.2 gives an outline of a prototypical positive resist process, with some values for process parameters, which will be discussed in more detail later on. Comprehensive overviews of photolithography can be found in references [3–6] with the older ones still highly relevant for contact/proximity lithography practiced in the MEMS community. Review articles on lithography that are of MEMS interest concentrate mostly on thick resists [7–10].

22.2.1 Dehydration Bake Cleaning steps are performed to provide known starting conditions, irrespective of previous process steps or waiting period. Dehydration bake removes adsorbed water Table 22.2 Standard lithography process

Step

Values for 1.5 μm thick AZ resist

Dehydration bake

Oven, 30 min, 100°C

Priming

HMDS—vapor coating

Photoresist application

Spin-coating, 1.5 μm thick, 5000 rpm

Edge bead removal

(optional)

Soft bake

90°C, on hot plate, 1 min

Alignment

Machine speciﬁc

Exposure

50–100 mJ/cm2 (Hg lamp)

Post-exposure bake

Not required

Development

1 min, 1% TMAH, 20°C

Hard bake

110°C, hot plate, 1 min

Post-treatments

(optional)

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vapor, and in itself ensures better adhesion; but priming, a special adhesion promotion step, is often performed. Vapor or dip coating of HMDS (hexamethyldisilazane) will keep moisture away and ensure that hydrophobic resist will adhere to wafer. One popular resist, SU-8, does not require priming, while most resists do.

22.2.2 Resist Application 22.2.2.1 Spin Coating Spin coating dominates standard resist applications, but spray coating has advantages in coating highly 3D proﬁles. Wet etched 54.7° angles can be better coated by spray; but, usually, resist thickness uniformity with spray is inferior to spin coating. In spin coating optimized processes can have 0.1% uniformity for thin resists planar wafers, and a few percent can be achieved for tens of micrometers thick resists. Photoresists are typically comprised of three major components (PMMA is an exceptional one-component resist): • base resin, e.g., novolak, bisazide, or epoxy • photoactive compound, e.g., DNQ (diazonaphtoquinone) or hexaﬂuoroantimonite salts • solvent, e.g., MEK (methyl-ethyl ketone), PGMEA (methoxy-propyl acetate) Base resin determines mechanical and chemical properties like adhesion, solubility in developer, temperature stability, and etch resistance. Photoactive compound is responsible for spectral absorption behavior and resist sensitivity, and therefore pattern contrast and resolution. The solvent modiﬁes viscosity and evaporation, and is of tantamount importance in spin coating. Photoresist thickness after spincoating is determined mainly by resist viscosity (η) and spin speed (ω) (Eq. 22.1): t ∼ η 2 ω 2 1

1

(22.1)

Using one formulation, spin speeds from 500 rpm to 5000 rpm result in a factor of three thickness change; in order to span a larger thickness range, other formulations are needed. These can be prepared by resist thinning (viscosity decrease); but because the solvent is responsible for evaporation rate and drying behavior and, therefore, ﬁlm quality, it is not necessarily easy. For instance, MEK and PGMEA evaporation rates are different and result in different drying rates. Spin-coated liquid should theoretically end up with a planar horizontal surface. However, for various reasons this is not always the case. Surface tension of liquid can cause deviation from planarity, and if there are large etched recesses on the wafer, these will not be perfectly planarized. Figure 22.1 shows schematic views of resist application. 335

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Due to solvent evaporation, the resist dries faster on the outer rim of the spin-coated wafer. This leads to bumps known as edge bead. In, for example, mask oxide etching before KOH silicon etching it is advantageous that the resist covers the edges of the wafer well, leaving oxide on the edges. This improves the mechanical stability of the wafer, which is otherwise compromised by KOH attack during extended etching. Most often, however, edge bead needs to be removed. This is usually done by solvent spraying of wafer edges after coating, in a process dubbed EBR, for edge bead removal. It can be done either automatically or manually (by reducing the spinning speed to a speed that is not anymore making the resist layer thinner and dispensing solvent to the edge of the wafer). Alternatively, edge beads can be mechanically wept away. Typically, EBR removes resist from a few millimeters of the wafer edge. This area is, of course, lost, but chip yield at the very edges would be low anyway.

22.2.2.2 Spray Coating Spray coating overcomes the cavity depth problem in MEMS lithography: While spin-coated resist thickness can change by a factor of two in an etched recess, spraycoated resist has a nearly conformal coverage over wetetched geometries [11, 12]. Additionally, spray coating is insensitive to cavity shape and position on a wafer, factors which result in even more non-uniform spincoated ﬁlms. Spray coating is done on a slowly rotating wafer (100 rpm) to ensure uniform coverage of structures of different orientations. While not truly conformal, spraydeposited resists are superior to spin-coated resists over severe topography, with 10% uniformities achievable. Problems in spray coating have to do with viscosity optimization: Low viscosity (20 cSt) is needed for proper droplet generation and smooth layers, but such resists will also ﬂow more easily to ﬁll recesses. Resist choice and machine parameters such as atomizer pressure and angle will affect results.

22.2.2.3 Dry-Film Resists One technique which is of considerable interest in MEMS applications is laminate resists (dry-ﬁlm resists). They come as sheets of negative acting material without solvent, with thicknesses usually in the 20- to 100-μm range. Thicker layers can be easily obtained by multiple layers, because there is no need for soft baking, because there is no solvent to be removed from the material. Some examples include SU-8 3000 [13], Etertec HQ6100 [14], DuPont MX5000 [15]. These are laminated on top of substrates by hot-roll lamination. The main advantage of dry-ﬁlm resists is that resist thickness is independent of underlying topography. Resolution is not 336

as good as with spin- or spray-coated resists, but the simplicity of application is a major advantage. Especially in structures where prefabricated grooves and cavities need no further patterning, dry resists provide an easy way to overcome problems with severe topography. Dry-ﬁlm resists are typically limited to noncritical applications, with 1:1 to 3:1 aspect ratios (20–50 μm minimum linewidths).

22.2.2.4 Casting As an alternative option for thick photoresist application, casting has been used [16]. The thickness is deﬁned by spacer ring, and the material is cast between two plates. The spacer ring is placed on top of the substrate and normally ﬁxed, for example, by mechanical clamping. The spacer ring thickness deﬁnes the thickness of the resist layer. This method is suitable especially for extremely thick, millimeter layers. The layer thickness is accurately deﬁned, but one should have specially made spacer rings for each desirable thickness.

22.2.2.5 Other Techniques Truly conformal resist coverage even in the corners of deep reactive ion etched (DRIE) grooves can be obtained by electrodeposited resists (e.g., PEPR 2400ED and Eagle 2100 ED) [16]. This is the main advantage, but a major limitation is the requirement of a conductive substrate, which means that the techniques are only applicable to certain process steps. There is also limited availability and support for ED resists and infrastructure, like electrochemical cell designs.

22.2.3 Soft Bake Soft bake (prebake) removes solvent, and the resist is dried before it is loaded into a mask aligner. Optimizing the drying process ensures that resist thickness is uniform across the wafer, and the resist has low mechanical stress and is free of cracks. If removal of solvent is inadequate during soft bake, gas bubbles may be generated during exposure. It is worth noticing that the most commonly used photoinitiator DNQ releases gaseous nitrogen during exposure. However, the amount is relatively small, and in thin resists nitrogen diffuses easily without bubble formation. However, when exposing thick layers, bubble formation is a potential problem. Soft bake time increases as a function of resist thickness: 4 μm SU-8 is soft baked (95°C) for 2 minutes; 40 μm resist requires 5 minutes. Soft bake temperature is important because too-high temperature degrades the photoactive compound and leads to loss of sensitivity (exposure time needs to be increased). Soft bake time is not as critical as temperature.

MEMS Lithography

Edge beads

Decline

Resist Substrate (a)

Resist spinning over topographies Removed edge beads

Resist

Substrate (b)

Resist spinning + edge bead removal + optimized soft bake Spacer ring

Resist

Substrate (c)

Resist casting over topography Resist

Substrate (d)

Dry resist laminated over topography

Resist Substrate (e)

Spray - coated resist over topography

Fig. 22.1 ● Schematic views of resist application over topographies on substrate. (a) Standard spin-coating. (b) Optimized spin-coating process with edge bead removal. The photomask can be brought to direct contact with mask. (c) Resist casting using spacer ring. (d) Dry-ﬁlm lamination does not ﬂow inside the cavity. (e) Conformal resist over cavity by spray coating.

22.2.4 Alignment Alignment is based on speciﬁc alignment targets (a.k.a. alignment marks or keys) which are designed for this purpose, and they are completely independent of device structures (Figure 22.2). This procedure eliminates feature size and shape effects from the alignment process and enables copying of alignment structures from previous designs. Sometimes, an additional zero-level alignment

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key needs to be fabricated because, e.g., diffusion as the ﬁrst step does produce contrasting structures that could be seen in optical microscopes. Usually, silicon or silicon dioxide etching is used to form the zero-level keys. Even if alignment is correctly performed, overlay of mask layers may be imperfect. During mask making, a number of errors can take place: misplacement of structures or various distortions, and in projection lithography optical imperfections of the imaging optics can cause image distortions, etc. It can also happen that the masks of different levels might have errors in origin of coordinates. It is useful to do test alignment and exposure with a new set of masks before commencing wafer processing.

22.2.4.1 Double-Side Alignment Double-side alignment usually requires double-side polished (DSP) wafers. The backside of an SSP wafer is etched, and its roughness is in the micrometer range, making all but very simple lithography impossible. Early work on double-side alignment used throughwafer etching to create small, thin membranes as alignment marks [17]. This obviously adds process complexity and calls for careful further processing to preserve the thin membranes in the alignment marks. Machine-dependent double-side alignment has utilized infrared alignment through a silicon wafer. The IR method works for silicon because silicon is transparent in the infrared, but alignment accuracy is limited to 5–10 μm. Two-sided exposure has also been implemented, with the two masks aligned to each other before the double-side resist coated wafer was brought into the gap between the masks. Working with both sides of the wafer resist coated is standard, for protection of one side, but having both sides defect-free for patterning is demanding. The current technology of double-side alignment is based on separate top and bottom microscopes (Figure 22.3). The bottom microscope can detect and store the bottom alignment marks of a wafer, and this information is used with the top microscopes and the mask alignment marks. One must be careful in designing the alignment marks for double-side processing not to create a mirror image of pattern by accident. Correct double-side alignment does not guarantee perfectly aligned features after etching. Etching nonidealities in anisotropic wet etching can result in misalignment: For example, wafer thickness variation leads to lateral shift of edges of etched structures, or differences in crystal plane selectivities result in similar lateral shift during through-wafer etching.

22.2.5 Exposure Exposure dose of resist is affected by a number of factors, with sensitivity and thickness being the most important. 337

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Alignment mark on wafer Alignment mark on mask

Fig. 22.2 ● Alignment keys: standard thin resist; for thick resist.

Wafer

Mask

Chuck Focusing and storage of mask alignment marks

BSA splitfield microscope

Mask alignment mark

Wafer alignment mark

Focusing of substrate alignment marks

Alignment

Fig. 22.3 ● Double-side alignment with backside split-ﬁeld microscopes. Source: Courtesy Süss MicroTec Lithography GmbH.

As a rule of thumb, order of magnitude increase in thickness requires an order of magnitude increase in exposure time. Typical micrometer-thick AZ positive resists require in the order of 50–100 mJ/cm2 exposure dose, which translates to a few seconds exposure time with 10–20 mW/cm2 from a standard 350 W mercury lamp. Thick 50 μm AZ resist would then require in the order of 338

a minute in the same tool. For negative resists, exposure time depends on photoinitiator type, and dose requirements can vary heavily: 2 μm SU-8 requires 80 mJ/cm2, and 40 μm SU-8 requires 160 mJ/cm2. Contact/proximity aligners typically have four operating modes: proximity, soft contact, hard contact, and vacuum contact. Resolution (line plus space) in proximity

MEMS Lithography UV exposure

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Evaporation

g

l

Photoresist

UV exposure

Evaporation

Device wafer g l

Contact less

Self - aligned

Fig. 22.4 ● Patterning at trench bottom: lithography vs. lift-off using planar masks/stencils (top) and conformal 3D masks/stencils (bottom). Source: From Ref. [27] by permission of Elsevier.

Table 22.3 Resolution in contact/proximity printing

Contact mode

Resolution

Proximity

2.5 μm

Soft contact

2 μm

Hard contact

1 μm

Vacuum contact

0.7 μm

printing is a function of exposure wavelength λ and proximity gap (g): W ∼

0.7λg

(22.2)

This translates to a few micrometers for typical gaps of 5–10 μm. In Figure 22.4 the etched depth of the cavity adds to the gap, and the effect on resolution is extreme. In contact mode diffraction effects are minimized and better resolution is achievable. For best resolution, vacuum contact is used to minimize diffraction effects at chrome pattern edges. The more intimate the contact between the mask and the resist is, the better the resolution, as shown in Table 22.3. However, physical contact between the mask and the resist may

damage the mask and lead to printable defects in the following exposures. The resolution depends additionally on wafer ﬂatness via uniformity of the gap across the wafer. Clean room humidity, temperature, and vibration control also affect results via resist sensitivity and tool mechanical stability. Using thinner resist enables smaller line-widths, but with less etch resistance and higher probability of defects in resist. Uncontrolled resist thickness variation can have major effects via interference effects: For example, 50-nm deviation in nominally 1-μm-thick resist can result in 50% increase in required dose (and subsequent throughput reduction). Alternatively, 20% linewidth variation can occur if dose is not corrected for thickness change. On highly reﬂecting substrates like aluminum or gold, exposure dose can be halved. Similarly, on glass wafers 50% dose increase is required compared to silicon. Sometimes, reﬂections from cavities in glass wafers can cause unwanted exposure. Equation 22.2 is not valid for thick resists, which are always much thicker than the exposure wavelength. Gap minimization does reduce diffraction effects also for thick resists, but, additionally, wavelength selection (and ﬁltering) to reduce absorption in resin plus choice of low absorption resin and high sensitivity photoactive compound are important for sidewall control [18]. 339

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Overexposure in positive resist tends to turn the proﬁle into retrograde, while underexposure leads to shallow slope. It is customary to perform an exposure test using a blanker that allows only a part of a wafer to be exposed, e.g., a quarter. Different exposure times, e.g., 2 s, 4 s, 8 s, and 16 s, are then exposed, and the wafer is developed and visually examined for optimum exposure time. For step-and-repeat systems focus and exposure matrix is easily generated by changing parameters site by site. Resist aspect ratio depends on resist contrast, spectral distribution of the lamp and light collimation, plus resist mechanical strength. Resist-aspect ratios of 10:1 have been achieved in AZ positive resists, and 20:1 is typical of negative working SU-8 with UV exposure, with 100:1 demonstrated. Some thick negative resists which compete with SU-8 as being easily strippable, like JSR THB-151N, are usually limited to low-aspect ratios, while offering high photospeeds, superior to thick positive resists [19]. Some photoactive materials like ORMOCERs are still treacle-like after soft bake, and contact with the mask is undesirable. The soft bake is mainly done to remove air bubbles from the ﬁlm. The soft bake time has no effect on the viscosity of the layer. To avoid contact with the mask, exposure of such materials is to be done in proximity mode. The gap control in exposure becomes extremely critical when the structure size goes down.

22.2.6 Post-Exposure Bake Post-exposure bake (PEB) is different from hard bake (post-bake). PEB is done immediately after exposure to ﬁnish off the chemical processes initiated by exposure, for example, diffusion of photogenerated specie. In positive resists PEB is usually not required, but it is essential in negative resists: It ﬁnalizes the reactions started during exposure. Normally, only photoinitator reacts directly with UV-light, and PEB completes the reactions with the resin. PEB can be used in a few cases to improve positive resist images. If monochromatic (laser) exposure is used, pronounced standing waves are generated in the resist, resulting in undulating sidewall proﬁle not unlike Boschprocess undulation. Standing wave pattern can be reduced or eliminated by PEB step which diffuses the photogenerated specie. Image reversal is the process where the polarity of a resist image is reversed after exposure. This is useful when a mask exists in one polarity, but a different polarity would be needed. Obviously, using resist of opposite polarity will result in the same ﬁnal outcome. Using speciﬁcally formulated image reversal resists like AZ 5214E, a standard masked exposure is done, and the wafer is then baked. During this bake the special 340

cross-linking agent reacts in the exposed areas with the photoactive compound, resulting in insoluble product. The bake temperature is 110–120°C, depending on process details, and it is critical to 1°C. After crosslinking, a ﬂood exposure is done, e.g., 200 mJ/cm2, which results in increased solubility on the areas that were protected by the mask during the masked exposure. The resulting resist pattern is a negative image of the photomask. The negative sloped sidewalls that this process gives are useful in lift-off and the hardened resist is also more resistant in harsh plasma etching and ion implantation.

22.2.7 Development Development is about exposed/unexposed resist dissolution rate differences. When this ratio is high (10:1), vertical resist walls can be produced. Low ratio leads to sloped resist walls (which sometimes may be advantageous). Underexposure leads to resist thinning as the development rate ratio of exposed and unexposed parts of the resist is reduced. Positive resists are developed in dilute alkaline solutions, while negative resists are normally developed by organic solvents; but some modern negative resists are alkaline developed. The selectivity of the developer between exposed and nonexposed areas is important for achieving accurate high-aspect ratio structures. In ma-N 400 resist this ratio is 20:1, and in ma-N 1400 it is 6:1 in alkaline developers. Normally, the development result is better if stirring is applied to speed up the development process. The stirring can be mechanical agitation or ultrasound. Afterward, the development wafers are rinsed with organic solvent or with water, depending on the resist material. Developers for positive resists are usually dilute alkaline solutions. Sodium and potassium-based developers (known as MIB, for metal-ion-bearing), basically dilute NaOH or KOH solutions (e.g., AZ351B and AZ400K), are undesirable in fabs producing CMOS. Metal-ionfree (MIF) developers are based on TMAH, for example, AZ326MIF. Development parameters will affect linewidth and resist proﬁle, in combination with the exposure. Positive resists have a small process window but usually high resolution, while negative resists have large process tolerance but usually poorer resolution due to swelling in the development step. Post-bake (also known as hard bake) induces physical and chemical changes in the resist image. Post-bake temperature is kept below glass transition temperature of the resist (typically in the range 100–150°C for most resists) to avoid thermal ﬂow. On the other hand, postbake above Tg has been used to create hemispherical

MEMS Lithography

resist dots, useful as microlenses, or as masters for casting and imprinting fabrication of lenses. Even below Tg temperature, several processes take place: Volatile compounds and water are desorbed, resist oxidizes and shrinks, and reactions between resist components take place. Post-bake is useful for adhesion improvement after developer has attacked substrate/ resist interface, because moisture is removed and the bond between resist and surface strengthened.

22.2.8 Post-Treatments Post-treatments include various techniques to modify resist for following process steps. A typical treatment would be UV-ﬂooding, which hardens resist. This is useful for chlorine plasma etching or ion implantation.

22.3 Processing After Lithography After the resist pattern is in place, wafers can experience several different process steps, which have their own speciﬁc requirements for resists. And after wafer processing, resist removal is affected by the processes which the resist underwent. Wet-etching quality depends critically on resist adhesion. Wet etchants do not etch resist in most cases, but liquid penetration between substrate and resist leads to adhesion loss. Resists have been tailored speciﬁcally for wet etching, with low molecular weight and good adhesion. The same applies to electroplating and electroless plating. Wet-etching processes are mostly immersion processes where the etchant attacks both sides of the wafer. In many MEMS applications, protection of backside ﬁlm is essential, and there are a few approaches to this. Using plasma etching circumvents the backside etching problem. Alternatively, a protective coating can be spun on the wafer backside. Photoresist is often used for convenience, but cheaper, nonphotoactive polymers can be used. Protek and CYTOP polymers are often used in harsh environments (HF, KOH) while resists are ﬁne for more dilute etchants (e.g., BHF). Plasma etching (RIE) is usually hard on resists. Selectivities 1:1 to 10:1 are typical, limiting etched depths to a few micrometers or tens of micrometers. High-density plasmas of the type used in DRIE utilize smaller bias voltages than older RIE, enabling great reduction in ion bombardment, and thus much higher resist selectivities, in the order of 100:1. This enables throughwafer etching with thick resist mask, a great simpliﬁcation compared with oxide masked etching. Lift-off depends on resist proﬁle: Negative (retrograde) proﬁle is advantageous for poor step coverage

CHAPTER 22

needed in lift-off. Therefore, either negative resists or image reversal resists are favored. Some manufacturers label these products LOR, for lift-off resists. These products offer good adhesion and high undercut rate, and they are used in a bilayer scheme: A thicker LOR is applied ﬁrst and baked (at high temperature, 150–200°C) to optimize its development rate. A thinner imaging resist is then applied on top of LOR, exposed, and developed. The high development rate of LOR will create a T-shaped proﬁle advantageous for lift-off. Positive resists with positively sloped angles can also be used, but then metal thickness is limited to a fraction of resist thickness. With LOR double-layer structure, the LOR is somewhat thicker than the required metal thickness, and the imaging resist can be optimized for linewidth. Using a diffuser plate to randomize exposing UV, positive resists have been used to create negative slopes suitable for lift-off [20]. For lift-off applications, resist surface layer can be hardened, which then results in an overhang proﬁle beneﬁcial for poor step coverage. Solvent soaks are utilized, and the overhang depends on soak time and solvent content. Some of the solvents used are extremely hazardous and toxic, and not much used today. Lift-off has a limitation compared with etching, because large chunks of material ﬂoat in the lift-off bath. This can be detrimental to cavities and other prefabricated structures, even though lift-off might have been chosen exactly because those structures make layer patterning by etching impossible. Photoresists are simple sacriﬁcial layer materials in surface micromechanics, suitable for both polymer/ polymer and polymer/metal combinations. Resists are compatible with sputtered and evaporated structural layers [21], and suitable for electroplating as well [22]. Depending on sacriﬁcial gap height, thicknesses of resist layer can range from a micrometer to hundreds of micrometers. Removal of resist sacriﬁcial layers can be done either by dry methods like oxygen plasma stripping (preferred in small gap structures) or by standard wet removal. SU-8 has been used as a plating mold which can be removed simultaneously with both AZ and Sseries positive resist sacriﬁcial layers [23]. Removing SU-8 structures from a substrate, a sacriﬁcial polymer layer of PMGI has been used. This PMMA-derived polymer can be etched away in dilute TMAH solution which does not attack SU-8 [24].

22.3.1 Lithography Over Severely 3D Topography Lithography on severely 3D surfaces is possible by, e.g., spray-coated resists, but there are alternative approaches. Peeling masks (nested masks) utilize two 341

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different hard masks and two lithography steps before any deep etching steps. This technique is described in DRIE (Section 23.5.5). Shadow masks (stencils) can be used to eliminate photoresist from the patterning process [25, 26]. In a typical application, shadow mask and evaporation are used to create metallization pattern directly on wafer. The technique is simple for large feature sizes and large alignment tolerances, but becomes increasingly difﬁcult if resolution or alignment requirements increase. For example, bowing of the stencil due to deposited metal changes the apparent solid angle seen through the stencil, changing linewidth. For nanostencils clogging of the apertures by the deposited metal quickly diminishes the aperture, limiting metal thickness. Apparently, donut-shaped structures are difﬁcult to make by lift-off, requiring multilevel processing of the stencil. Shadow mask can be used to deposit metal on the bottom of a deep structure, but solid angle considerations limit the achievable linewidth, as shown in Figure 22.4. But optical lithography is similarly compromised, as the gap between mask and resist inevitably increases. Spray-coated thin conformal resist will help to maintain some linewidth control, but a large gap will limit performance. Shadow masks can be made to conform to 3D structures on the wafer, enabling intimate contact between the stencil and the wafer to be patterned. This works for both optical lithography as well as lift-off metallization (Figure 22.4) [27]. Shadow masks can also be used in etching: For instance, a chemical sensor sensing ﬁlms that do not tolerate photoresists can be patterned by removing selected areas by plasma etching through a stencil mask. While evaporation is a line-ofsight method, ensuring no deposition under the stencil, plasma etching is a mixture of chemical and physical processes, and some underetching will inevitably take place. This undercut is heavily process dependent.

22.3.2 Photoresist Removal Resist removal (a.k.a. stripping or ashing) depends on resist nature and the preceding process steps. Positive resists that have undergone room-temperature processing, like wet etching, pose no stripping problems. However, elevated temperatures and plasmas may make resist removal very difﬁcult. Oxygen plasma and ozone treatments are generalpurpose methods suited for most applications. They are especially good when cavities and other highly 3D structures exist on the wafer, as they induce no surface tension effects. Wet removal methods include sulfuric acid, which is a very powerful oxidizing agent. Its use is limited 342

by its chemical aggressiveness, which excludes its use after metals are deposited on the wafers. Solvents like acetone can be used, and there are a number of speciﬁc stripper solutions, e.g., amine based. Ultrasound agitation can be used to speed up resist removal, but with resonating MEMS structures and other fragile elements its use is limited. Often, multi-step resist removal must be used. For example, plasma ashing removes a carbonized top layer, and wet remover is used for the remaining layer. Alternatively, a plasma cleaning step can be done after wet removal. For thick resists, three-step removal of trichloroethylene (TCE), acetone, and methanol has been used [28]. SU-8 is notoriously difﬁcult to remove. As a plasma etch, mask thickness can be tailored so that almost all SU-8 is consumed during etching, minimizing resist removal, but this is difﬁcult to optimize when etch loads change. Alternatively, a release layer can be used underneath SU-8: polymer like PMGI [24]. Sometimes, swelling and the resulting adhesion loss can be used to remove resists: Polyimide has been removed by NaOH treatment [29].

22.4 Thick Photoresist Lithography Resists may be considered thick when they are thicker than 5 μm. The distinction to thin resists comes from exposure, or more speciﬁcally, absorbance. DNQ photoactive compound in positive resists absorbs strongly, and the surface layers prevent exposure of the layers underneath. Continued exposure causes bleaching of DNQ (absorbance reduction by a factor of 10) which enables bottom part of resist to be exposed. However, exposed DNQ exhibits residual absorption, which means that exposure times increase as a function of thickness. This sets a practical limit to positive resist thicknesses to 50 μm. In negative resists based on photoacid generator, the reactive acid molecule is produced throughout the volume of the resist, and absorbance is not affected by the exposure. Therefore, thick layers can be exposed in reasonable times. Negative resists up to 2 mm have been exposed with UV-exposure [30]. In X-ray lithography exposure dose is usually not the limiting factor, but the achievable thickness is deﬁned by mechanical stability of the microstructures. Thick resist performance is normally judged by sidewall angle and aspect ratio. Aspect ratio is deﬁned here by the resist structure height ratio to the structure width (or cavity width). Normally, the sidewalls are not perfectly vertical, and therefore the aspect ratio should be taken from the largest or from average width of the structure or cavity. Similarly, sidewall angle is difﬁcult

MEMS Lithography

to deﬁne, because the cross-sectional shape of the structures varies depending on the resist and exposure system type. Thick photoresists can produce in polymers structures that resemble DRIE structures. In Figure 22.5, pillar arrays fabricated of epoxy photoresist SU-8 are shown. Height of the pillars is 400 μm, and the pitch 80 μm (40 μm pillars with 40 μm spaces). A closer look at such pillars can be seen in Figure 22.9. In the best case, the lithographic structures have clearly better structure shapes, compared to DRIE structures. Bottoms of DRIE structures are often rounded, while resist structures have rectangular feet. Bosch process leaves scalloped walls in the tens or hundreds of nanometers amplitude, while lithographic walls have roughness in the range of 10 nm. This is highly important in certain MEMS applications, for example, in the fabrication of optical components. Electroplating into high-aspect ratio thick photoresist molds is a major application. Both mold master fabrication by plating as well as usage of plated structures as the ﬁnal devices are practiced. With X-ray lithography, the former is usual, while with UV-exposure the speed and cost allow direct fabrication of the ﬁnal metal parts. References [19, 22, 23, 28–33] discuss thick resist lithography for plating applications.

CHAPTER 22

Table 22.4 Process ﬂow examples for SU-8

Process step

Notes

50 μm thick layer

Application

SU-8 50

Spin-coat 30 s with Spin-coat 30 s with 2800 rpm 800 rpm

Soft bake

On hot plate

10 min at 65°C and 30 min at 65°C and 20 min at 95°C 80 min at 95°C

In oven

60 min at 90°C

200 min at 90°C

Depends on aligner

750 mJ/cm2

1100 mJ/cm2

Post-exposure On hot bake plate

Slow heating to 95°C, hold for 7 min

Slow heating to 95°C, hold for 20 min

In oven

35 min at 90°C

75 min at 90°C

Exposure

200 μm thick layer

Slow cooling or relaxation at room temperature for at least 15 min Development

Immersion to PGMEA

8 min

Rinsing

2-propanol 2 min

22 min

2 min

22.4.1 Thick Resist Processing The thick photoresist patterning is very similar to thin resists, but they have some special features that should be taken into account while processing. This chapter concentrates on those differences. A few examples of process ﬂows for thick resist layers are shown in Tables 22.4 and 22.5.

15 23

kv mm

x

34 500

x y z

μm

29270 44592 0 00 8

#

1

ZEISS D S M 950

Fig. 22.5 ● An example of microﬂuidic reservoir with pillar arrays fabricated of negative photoresist SU-8.

Table 22.5 Thick AZ processing [28, 31]

Resist

AZ4562/9260

Thickness

40 μm

Application

Dispense static, spread 10 s at 250 rpm Spin-coat 2000 rpm in a closed bowl spinner

Soft bake

84°C, 50 min oven 115°C, 2 min hot plate or: 40°C–90°C ramp for 15 min 60 min at 90°C

Rehydration

60 min in air at room temperature

Exposure

3000–3500 mJ/cm2 (5–10 min)

Develop

Immersion 10–20 min (1:4 AZ400K:DIW)

Hard bake

Optional: max. 90°C for 1–2 h in oven

22.4.2 Thick Resist Application Application of thick photoresists is done, by default, by spin-coating, as is the case with thin photoresists. Manufacturers suggest spinning speeds for their materials, but these should be double-checked if very accurate layer thicknesses are required. Normally, the spin process has lower spin speed ﬁrst to spread the material around 343

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the wafer and then second step to deﬁne the ﬁnal thickness. Dispense volumes are typically 1–10 ml, with viscous resists and large wafers requiring somewhat larger dispensed volumes. Thick resists are easier to spin-coat in a closed spinner bowl design. This has several reasons: Ambient is better controlled; e.g., minor humidity changes are overridden by saturated solvent vapors from the resist, and slow drying prevents rapid viscosity changes which might otherwise lead to radial thickness nonuniformity. In addition to solvent volatility, local air speed above the wafer also affects resist drying. In a closed bowl, airﬂow patterns are under better control. All this results in more uniform thick resist layers. An extra drying step at lower rpm can be added to the thick resist spin process: This will allow further drying with only a minor effect on resist thickness. Edge beads become signiﬁcant when thick layers of photoresists are spin-coated on the wafers. Compared to thin resists, edge beads in thick layers are mostly caused by surface tension of the resists, and therefore their effect is larger. For layers above 50 μm, edge bead is comparable or greater than the proximity gap in exposure, and therefore starts to limit performance. Edge bead removal shrinks the patternable area, but clearly improves the patternability of the layers because the contact between mask and the resist becomes better.

22.4.3 Soft Bake Soft bake is done in a convection oven, on a hot plate, or by infrared heaters. Solvent removal from the material is diffusion limited, and therefore the baking times increase when thicker layers are patterned. Normally, hot plates are faster for the soft bake as can be seen in Figure 22.6, but, depending on the plate size, only few wafers can be processed simultaneously. The hot plate should have very homogenous temperature distribution; otherwise, the baking results in uneven properties to the layer. Ovens load several wafers at the same time, but wafers have to be kept in a horizontal position to avoid resist ﬂow. At elevated temperatures viscosity is smaller, and therefore resist ﬂows easily. Therefore, hot plate or shelves of the oven should be perfectly horizontally leveled. Even a slight change in the angle can cause huge resist thickness variation over the wafer. An easy, but not so elegant, method to compensate this is to rotate the wafer during baking. Oven baking is normally done at one temperature, but because hot plates can be ramped much faster in temperature, hot plate baking can be done at two temperatures. If the material has glass transition temperature at the baking temperature range, it is recommended to keep the wafer at that temperature for some time before proceeding to the ﬁnal temperature. This relaxes 344

Fig. 22.6 ● Soft bake times for different resist thicknesses and bake methods. Source: From Ref. [45] by permission of micro resist technology GmbH.

the stresses in the material. For the same reason, it is also recommended to avoid rapid changes in the temperature after the baking. When the wafer has stabilized to room temperature, wafers can be exposed. Multiple layers of thick resists can be patterned and in some cases well aligned on top of each other. However, the development of the layers should be done simultaneously; otherwise, the application of the next layer becomes problematic [34]. Normally, the step coverage properties (over cavities with lower depth than the resist depth) of thick photoresists are good. However, the resists are normally highly viscous, and therefore resist application by spin-coating does not necessarily result in good resist proﬁles. Good step coverage is achieved only during the soft baking when the viscosity of the resist is lowered and, therefore, resist ﬂow is accelerated. This compromises layer thickness control and uniformity across the wafer. This can be seen schematically in Figure 22.1. Casting method solves this problem because resist ﬂows into all cavities already during casting.

22.4.4 Thick Resist Exposure With thick resists, only direct contact exposure is widely used. Proximity exposures can be used, but the sidewall quality is compromised: Structures will have nonvertical sidewalls due to the gap between mask and the resist. Projection exposures have the same kind of problem, because the light is focused only in one plane, the resist above and below that plane have different images, and the result is a barrel-like resist proﬁle. More detailed accounts of thick resist exposure and sidewall proﬁle optimization can be found in [18, 35, 36]. In addition to standard exposure, resists on glass wafers can be exposed

MEMS Lithography

20 7 x

CHAPTER 22

kv mm

15 9 x

2000

3000

5 μm

#

kv mm

5

#

1

DSM 950

μm

1

DSM 950

Fig. 22.7 ● T-topping on left and ﬁltered exposure on right.

from the backside [32]. This has the effect of positively sloping proﬁle for negative resist. Exposure times required for the photoresist layer depend heavily on the aligner optics and the wavelength spectrum used for exposure. Therefore, the exposure times recommended by the material manufacturers should not be followed automatically, but the correct exposure times should be tested for each aligner. Exposure light should not be absorbed at the base resin; only the photoinitiator molecule should interact with the light. If the resin is absorbing light, the structures will have a T-shaped cross-section known as T-topping. This effect is caused directly by the absorbance of light. It can be eliminated by adding suitable ﬁlters to the light path or changing the aligner lamp to one with correct wavelength. The problem can be seen in Figure 22.7 for relatively thin layers of resists, but it is pronounced when thickness increases. As a general rule, most polymers start to absorb at wavelengths of around 350 nm and below that. Therefore, usage of broadband mercury lamp exposure does not give good results unless the aligner is equipped with a ﬁlter that cuts wavelengths below 350 nm. It is also possible to add a ﬁlter on top of mask wafer stack. The easiest method depends on the mask aligner used. For the highest aspect ratios, special methods have to be applied. The nonidealities of the exposure methods cause variations in the resist structure. The most signiﬁcant feature that causes exposure nonidealities is nonplanar surfaces. Edge beads or other nonidealities in resist thickness cause a gap between the mask and the resist layer in contact exposure. This gap causes T-shaped structures in negative photoresists and rounded-corner shapes in the positive photoresist. Often, the result of this looks like the result caused by slight absorption of light to the resist. The phenomenon follows from Fresnel diffraction. The problem can be improved by better planarization of the layers, and

especially, edge bead removal should help the situation. One option is to use additional materials in lithography. If the air gap between mask and photoresist is ﬁlled with material having a similar refractive index to that used in photoresist, the problem is compensated and the resist proﬁle should be optimal [35].

22.4.5 Thick Resist PEB In the case of negative photoresists, PEB is required to cross-link the material. For positive photoresists this step is not normally required. This baking step is done on hot plate or in convection oven. It is crucial that the temperature is high enough for complete cross-linking, but too-high temperatures should be avoided because of stress generation. Part of the stress is caused by cross-linking shrinkage, and this cannot be controlled by temperature, but only by cross-linking density. The shrinkage with commercial thick photoresists is normally low, and the main source of stresses comes from thermal expansion coefﬁcient difference between substrate and the resist [37]. This stress can be so high that wafers are visibly bowed. By adjusting the cross-linking density (stopping baking before complete cross-linking), the material becomes more ﬂexible. This can be used for stress reduction and also for tailoring device properties in MEMS components. However, it is worth noticing that lower cross-linking density changes also other material properties like long-term stability.

22.4.6 Thick Resist Development The development of thick resists is normally done by immersion development, but some materials can also be spray developed. Development of thick resists is diffusion limited, and development time increases as a function 345

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of thickness. Development is also slower in narrow grooves compared with large open areas. With some negative resists, cracking of the resist layer can occur during the development. This is due to organic solvents diffusing into the resist. It can be visualized as cracking of the top layer. Higher cross-linking density will improve the tolerance for cracking. Post-bake (hard bake) is not normally required for thick negative resists. This step densiﬁes the resist layer either by further cross-linking or by further evaporation of volatile compounds. The temperature of the post-curing depends on the material, but normally the temperature is higher than earlier baking steps (e.g., 120–150°C). With some negative resists, this can be used for removal of small cracks that appeared during development. However, it is worth noticing that it also creates higher stresses in the structures. Therefore, the need for this step should be evaluated based on the application. For applications using thick resist for patterning other layers, post-curing is normally good because it improves the strength of the material in the following process steps.

22.4.7 Thick Resists as Sacriﬁcial Materials In electroplating applications, positive photoresists play a major role, because those are easier to remove after plating. For high-aspect ratio electroplating, the standard procedure has been to use PMMA as a photoresist and synchrotron X-ray exposure for patterning. With this kind of setup, aspect ratios up to 100:1 can be achieved, but difﬁcult and expensive X-ray exposure limits the use of this technique. The X-ray exposure followed by electroplating is commonly known as Lithographie Galvanoformung Abformung (LIGA) [33]. For high-aspect ratio structures with UV-patterning, the only material enabling close to similar performance is epoxy photoresist SU-8. Aspect ratios up to 190:1 have been demonstrated [35], and 20:1 ratios are easily achieved by standard UV-lithography using SU-8. However, SU-8 has problematic material removal after the electroplating, and therefore it is not optimal material for such applications. For lower-aspect ratios the selection of the materials becomes larger. Thick photoresists for electroplating applications have been reviewed, for example, in Ref. [9]. Even complicated 3D electroplated structures have been demonstrated using normal positive thick photoresists [22]. Thick resists can replace dielectric or metal masking layers in DRIE. This is a considerable simpliﬁcation in process ﬂow as it eliminates hard mask deposition and etching steps. Normally, positive resists are also used for these kinds of applications because they are easy to strip 346

Fig. 22.8 ● An example of microﬂuidic chip fabricated with negative photoresist patterning. All the structures are of epoxy photoresist SU-8, and silicon and glass plates are used for mechanical support.

after the etching step. However, negative resists normally enable better etching resistance in DRIE [38].

22.4.8 Thick Resists as Structural Materials In MEMS-components thick photoresists have been used for several purposes. In some applications the whole functional component is fabricated of thick photoresists, but it can be used also together with silicon and glass microfabricated structures [39]. Patterning of thick resist enables easier fabrication processes for component, compared to, for example, fabrication of silicon. Photoresist structures are also softer materials, and, therefore, mechanically moving parts can move with lower forces and the movement distances are larger. This enables, for example, more sensitive sensors and actuators with wider moving range [40]. However, the long-term stability is normally compromised compared to hard materials like silicon. Microﬂuidics has a number of applications of thick photoresists. Thick resists have been used for fabrication of static microchannels [37, 41] and also for mechanically moving structures like for pumps and valves [42]. For microﬂuidic channels, wall material has minor mechanical requirements (and mostly surface chemistry issues with analytes), and therefore thick resists are suitable materials for such applications. Fast and easy fabrication process, together with transparent channel material, favors fabrication from resist materials. Optically transparent channels enable ﬂuid detection through the channels and easy integration of optical components to the microﬂuidic systems [43].

MEMS Lithography

15 kv 7 mm x

200 50 μm

X Y Z

36442 35922 20994

#

1

DSM 950

Fig. 22.9 ● High-aspect ratio SU-8 pillars bonded adhesively with another layer of SU-8.

CHAPTER 22

Adhesive bonding is a standard procedure in ﬂuidic device fabrication. The materials normally used as adhesives are glue-type of materials that are thermally, chemically, or UV-cured. However, thick resists are also suitable for these kinds of applications. Some of the negative resists have good bonding capabilities: SU-8, polyimides, and benzocyclobutene have all been successfully used for adhesive bonding. These materials enable fully lithographic fabrication process for complex multilayer structures. Bonding can be accomplished by UVexposure through transparent substrate [37, 41] (Figure 22.8) or by ﬁrst patterning the layers by lithography and then bonding the cured structures by a commercial wafer bonder [44]. An example of adhesive bonding by SU-8 is shown in Figure 22.9. The pillars are fabricated in one lithographic step of SU-8, and then another layer of SU-8 is bonded on top of the pillars.

References 1.

S. Rizvi (Ed.), Handbook of Photomask Manufacturing Technology, CRC, 2005. 2. B.G. Eynon, B. Wu, Photomask Fabrication Technology, McGrawHill, 2005. 3. W.M. Moreau, Semiconductor Microlithography, Plenum, 1991 (3rd printing). 4. J.R. Sheats (Ed.), Microlithography Science and Technology, CRC, 1998. 5. H.J. Levinson, Principles of Lithography, second ed., SPIE Press Monograph vol. PM146, 2005. 6. K. Suzuki, B.W. Smith (Eds.), Microlithography: Science and Technology, Marcel Dekker, 2007. 7. A. del Campo, C. Greiner, SU-8: a photoresist for high aspect ratio and 3D submicron lithography, J. Micromech. Microeng. 17 (2007) R81–R95. 8. H. Miyajima, M. Mehregany, High-aspect-ratio photolithography for MEMS applications, J. Microelectromech. Syst. 4 (1995) 220–229. 9. E. Koukharenko, M. Kraft, G. Ensell, N. Hollinshead, A comparative study of different thick photoresists for MEMS applications, J. Mat. Sci. Mater. Electron. 16 (2005) 741–747. 10. J. Shaw, J. Gelorme, N. LaBianca, W. Conley, S. Holmes, Negative photoresists for optical lithography, IBM J. Res. Dev. 41 (1997) 81–94. 11. N.P. Pham, E. Boellelaard, J. Burghartz, P. Sarro, Photoresist coating method for the integration of

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18. Y. Cheng, C.-Y. Lin, D.-H. Wei, B. Loechel, G. Grutzner, Wall proﬁle of thick photoresist generated via contact printing, J. Microelectromech. Syst. 8 (1999) 18–26. 19. V.S. Rao, V. Kripesh, S.W. Yoon, A.A.O. Tay, A thick photoresist for advanced wafer level packaging applications using JSR THB-151N negative tone UV photoresist, J. Micromech. Microeng. 16 (2006) 1841–1846. 20. H.S. Lee, J.-B. Yoon, A simple and effective lift-off with positive photoresist, J. Micromech. Microeng. 15 (2005) 2136–2140. 21. P.F. van Kessel, L. Hornbeck, R. Meier, M. Douglas, A MEMSbased projection display, Proc. IEEE 86 (1998) 1687–1704. 22. J.-B. Yoon, C.-H. Han, E. Yoon, C.-K. Kim, Monolithic fabrication of electroplated inductors using threedimensional photolithography of a thick photoresist, Jpn. J. Appl. Phys. 37 (1998) 7081–7085. 23. I.-H. Song, P.K. Ajmera, Use of photoresist sacriﬁcial layer with SU-8 electroplating mold in MEMS fabrication, J. Micromech. Microeng. 13 (2003) 816–821. 24. A. Nakajima, P. Kim, N. Honda, K. Hikichi, M. Esashi, S. Tanaka, Fabrication and high-speed characterization of SU-8 shrouded two-dimensional microimpellers, J. Micromech. Microeng. 17 (2007) S230–S236.

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25. M. Graff, S.K. Mohanty, E. Moss, A.B. Frazier, Microstenciling: a generic technology for microscale patterning of vapor deposited materials, J. Microelectromech. Syst. 13 (2004) 956–962. 26. G.M. Kim, M.A.F. van den Boogaart, J. Brugger, Fabrication and application of a full wafer size micro/nanostencil for multiple length-scale surface patterning, Microelectr. Eng. 67–68 (2003) 609–614. 27. J. Brugger, C. Andreoli, M. Despont, U. Drechsler, H. Rothuizen, P. Vettiger, Self-aligned shadow mask technique for patterning deeply recessed surfaces of micro-electromechanical systems devices, Sens. Actuators, A 76 (1999) 329–334. 28. D.H. Lee, D.E. Park, J.B. Yoon, S. Kwon, E. Yoon, Fabrication and test of a MEMS combustor and reciprocating device, J. Micromech. Microeng. 12 (2002) 26–34. 29. R. Bischofberger, H. Zimmermann, G. Staufert, Low-cost HARMS process, Sens. Actuators, A 61 (1997) 392–399. 30. H. Lorenz, M. Despont, P. Vettiger, P. Renaud, Fabrication of photoplastic high-aspect ratio microparts and micromolds using SU-8 UV resist, Microsyst. Technnol. 4 (1998) 143–146. 31. S. Roth, L. Dellmann, G.-A. Racine, N. de Rooij, High aspect ratio UV photolithography for electroplated structures, J. Micromech. Microeng. 9 (1999) 105–108. 32. K. Kim, D.S. Park, H.M. Lu, W. Che, K. Kim, J.-B. Lee, C.H. Ahn, A tapered hollow metallic microneedle array using backside exposure of

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23

Chapter Twenty Three

Deep Reactive Ion Etching Franz Laermer1, Sami Franssila2, Lauri Sainiemi2 and Kai Kolari3 1

Robert Bosch GmbH, Stuttgart, Germany Helsinki University of Technology, Espoo, Finland 3 VTT, Espoo, Finland 2

Reactive Ion Etching (RIE), also known as plasma etching or dry etching, and its extension deep reactive ion etching (DRIE) are processes that combine physical and chemicals effects to remove material from the wafer surface. Simultaneous ion bombardment-enhanced desorption, ion induced damage, spontaneous chemical etching, radical generation, ﬁlm deposition and other processes contribute to etching performance. The etch rate of the RIE process is substantially higher than the etch rate of purely physical processes. Ions, however, are present in very minor quantities (0.001% of all species in the chamber) so the name RIE is a misnomer, but it is widely used. Compared to wet etching, the most important feature of RIE is the capability of directional (anisotropic) etching without relying on crystal planes of the material. Plasma etch process variables (such as radio frequency (RF) power, pressure, etch gas ﬂow rates and temperature) can be varied to optimize etch rate, selectivity, sidewall angle or other responses. DRIE is an extension of RIE that enables high-rate etching of deep and narrow structures. Typically DRIE also offers better selectivity and process controllability than RIE. DRIE reactors differ from traditional RIE with their two RF generators for independent control of plasma generation and ion bombardment, lower-pressure range, fast mass ﬂow controllers (MFCs) or fast-acting valves in pulsed processes and a wider temperature range from liquid nitrogen cooled platen (typically –120°C) to up to 400°C in compound semiconductor etching.

23.1 Etch Chemistries 23.1.1 RIE Chemistry Etchant phase, gas or liquid, has been used as a dividing factor: wet etching in liquids vs. dry etching in gaseous environment, usually in vacuum [1].Wet etching depends on solubility of etch products, and dry etching on their volatility: solid gaseous etchant ⇒ volatile products 3 Si (s) 2SF6 (g ) 2 O2 (g ) ⇒ 3 SiF4 (g) 2SO 2 (g) Si(s) 2 Cl2 (g ) ⇒ SiCl44 (g ) Many halides, ﬂuorides, chlorides, bromides and iodides are volatile, as are oxyhalides [2, 3]. Typical etch products include SiF4, SiCl4, NF3, WF6, AlCl3 when silicon or metals are etched with SF6, CF4, Cl2, BCl3, SiCl4. High boiling point (low volatility, or non-volatile) halides include AlF3 and CrF2 which necessitate chlorine plasma etching for etching aluminum and chromium. The fact that volatility in vacuum under ion bombardment is not an unambiguous property, etchability of a material under certain conditions is always a matter of engineering judgment. While copper chlorides are deﬁnitely non-volatile, and copper cannot be etched by Cl2 gas, aluminum–copper alloys with up to 4% copper can 349

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be etched in Cl2. This is because ion bombardment can assist in desorption of loosely bound specie which would not otherwise be desorbed. Elevated temperature can be used to enhance desorption, but the use of photoresist mask often sets limits to this. Silicon and its compounds can be etched in ﬂuorine, chlorine or bromine plasmas, with SiF4, SiCl4 or SiBr4 as the main reaction products [4, 5]. Toxicity and tighter safety requirements make chlorine and bromine gases less popular, but they are widespread in integrated circuit fabrication for the better proﬁle and linewidth control in shallow etches. For DRIE applications there is an additional drawback: chlorine (and bromine) processes are inherently much slower than ﬂuorine processes. Oxide and nitride plasma etching is customarily done with CHF3, C2F6, C3F8 or c-C4F8. The ratio of carbon-toﬂuorine is important to control selectivity to silicon [6]. High ﬂuorine content results in silicon etching, while a more balanced carbon–ﬂuorine ratio enables high selectivity against silicon. Oxide and nitride can be etched in SF6 and CF4, but such chemistries exhibit poor selectivity against silicon and 1:1 to 3:1 nitride to oxide selectivity. In addition to etchant gases, additive gases are used: oxygen, hydrogen, argon, helium, nitrogen. They modify plasma chemistry and physics, thermal characteristics and surface chemistry. In SF6/O2 and CF4/O2 plasmas oxygen scavenging controls the amount of free ﬂuorine [7]. Oxygen is an active ingredient in many etching processes, for example, photoresist stripping where CO2 and H2O are generated as photoresist is etched. Oxygen is also important for anisotropy mechanism: deposition of SiOxFy ﬁlms is essential for sidewall passivation in silicon etching in SF6/O2 plasmas. Diamond (and diamond-like materials a-C:H, DLC) and practically all polymer etching processes use oxygen, possibly with argon or ﬂuorinecontaining gases. Etch gases CHF3 or C4F8 lead to deposition of ﬂuoropolymer ﬁlms of the type (CF2)n which passivate sidewalls and minimize lateral etching. Etch rate and anisotropy are manifestations of balancing etching and deposition reactions properly as in Bosch DRIE process. By tailoring the balance between erosion and deposition processes, RIE can produce perfectly vertical sidewalls, and the sidewall angle can be tailored over a wide range, from fully isotropic to positively tapered to negatively tapered (a.k.a. retrograde).

23.1.2 Other Dry Etching Processes Even though dry etching is often used as a synonym for plasma etching, dry etching includes many etching process that do not employ RF ﬁelds or vacuum [8–12]. These include processes used in release etching 350

in surface micromechanics, for example, spontaneous chemical etching of silicon in XeF2 gas or silicon dioxide etching in hydroﬂuoric acid (HF)–methanol vapor: Si(s) 2XeF2 (g ) ⇒ SiF4 (g) 2 Xe(g) SiO2 (s) 2HF2− (ads) 2MH ( ads) ⇒ SiF4 ( ads)

H 2 O(ads) 2M(ads) ⇒ SiF4 (g) Ion beam etching (IBE; also known as ion milling) relies on energetic argon ions and differs thus from RIE. Chemically active species are missing in IBE, and etch product volatility is not an issue. IBE rates are very low compared to RIE, 20–100 nm/min only. RIBE, for Reactive Ion Beam Etching, uses reactive ions, for example, ﬂuorine or chlorine, but etching mechanism is dominated by physical bombardment at low pressures. CAIBE, Chemically Assisted Ion Beam Etching, is a similar combination process where chemically active gas jet and broad inert ion beam have a synergistic effect. The latest extension of IBE is focused ion beam etching (FIB), which is capable of direct maskless writing of nanostructures. FIB typically relies on a well-focused gallium ion beam which erodes the surface. The applications of FIB are usually in prototyping of nanostructures. The biggest problems of the ion beam techniques are their low throughput and redeposition of the sputtered material.

23.2 Equipment Parallel plate reactors in which both plasma and DC bias voltage are created using one capacitively coupled plasma (CCP) source are prototypical RIE reactors. The wafer is placed on top of the RF driven electrode (commonly 13.56 MHz) which is typically in direct contact with plasma glow. This ensures a reasonable etch rate but makes the controllability of etching difﬁcult. Plasma is generated from selected etch gases. Because the electrons have high mobility compared to ions, the electrode charges negatively in RF driven plasmas [6]. This DC bias voltage between the plasma and the electrode generates ion bombardment towards the electrode. In order to achieve adequate plasma density quite high RF powers are used. Because the plasma generation and bias voltage are coupled, the wafer is exposed to heavy ion bombardment (high energy levels at comparatively low ion currents). The main etching mechanism of the masking material is typically physical sputtering. Therefore the masking material is etched relatively fast in this kind of RIE equipment. The typical etch rate of silicon is 0.1–1 μm/min and selectivity against the photoresist mask is usually below 5:1. Anisotropy is based on the directionality of the ion bombardment and the sidewall passivation which originates from eroded and

Deep Reactive Ion Etching

redeposited photoresist mask. No seperate sidewall passivation step is used, and therefore aspect ratios are usually limited to 2:1. The division between RIE and DRIE can be made according to etch rate, selectivity, aspect ratio capability or reactor type. DRIE reactors have a few novel features compared with RIE. They are typically equipped with two RF power generators instead of one. High-density plasma is generated using inductively coupled plasma (ICP) source. Using an ICP source one to two orders of magnitude higher plasma density is achieved than with CCP sources (for example, 1010 vs. 1012 ions/cm3). Therefore also the etch rate is roughly 1–2 orders of magnitude higher. In DRIE reactors the wafer is not involved with plasma generation and often in a remote position from the plasma, which eases the process controllability. Bias voltage is controlled separately by the second power source, which is capacitively coupled. This arrangement allows the use of low bias voltages that increases selectivity considerably. With DRIE equipment the selectivity of photoresist mask is one order of magnitude higher than in conventional RIE, 10–100:1 vs. 1–10:1 and aspect ratios up to 20:1 are routinely fabricated. The parameters available for DRIE process optimization include: etchant gases ﬂow rate of the chosen gases RF-power (coil power in ICP) bias voltage (CCP power in ICP) process pressure temperature Flow rate, pressure and reactor volume are related via residence time, τ. This represents the dwell time of molecules in the reactor before being swept away by pumping: ● ● ● ● ● ●

τ (p/p0 ) (V/F), Here p0 1 atm 760 Torr, V is the volume of the reactor and F the ﬂow rate of the feed gas. For a DRIE reactor typical values may be taken as V 10 liters, F 0.1 liters/min (100 sccm); p 10–100 mTorr, which gives 0.1–1 sec residence time. This time sets limits for gas switching in a pulsed Bosch process, although the volume of the plasma source itself is more important than the chamber volume (see below). The key process outcomes of a (D)RIE process are as follows: etch rate anisotropy/sidewall angle mask selectivity substrate selectivity etched surface quality throughput

● ● ● ● ● ●

CHAPTER 23

These must be optimized for particular applications, and compromises must be made: enhanced deposition of sidewall passivating polymer may improve the sidewall proﬁle but reduce the etch rate, or minimized undercut can result in residues at the trench bottom.

23.2.1 DRIE Reactor Requirements Bosch and cryo-processes utilize similar DRIE reactors, but both processes have their own special requirements. Pulsed etch-deposition approach is possible with simple low-density plasma RIE reactors but only at very low etch rates [13]. Many DRIE applications call for structures tens or hundreds of micrometers deep, and etch rate is a very important consideration. The switched nature of Bosch process calls for high speed MFCs, with sub-second settling times, or alternatively fastacting valves to open and close gas lines to the process chamber at high switching speed. Short step times also necessitate a gas line design to minimize delays. In order to reduce the polymer deposition on the chamber walls and pumping lines, they should be heated, as the deposition of ﬂuorocarbon polymer to unwanted surfaces creates particle contamination. In the Bosch process the ratio of ions to free radicals is important. If the relative ion concentration is too high, the proﬁle control is lost. By placing the wafer far enough from the plasma glow and/or adjusting a sufﬁciently high chamber pressure, it is possible to create a sufﬁcient ratio of free radicals to ions because of short decay time of ions. Without ICP or comparable remote high-density plasma sources it is impossible to create an adequate ratio of free radicals to ions. DRIE reactor requirements for glass etching will be dealt with in Section 23.3.3.1. Today three major different conﬁgurations of ICP sources are predominant (compare Figs. 23.1a–c). In the ﬁrst type of reactor (Fig. 23.1a), a ﬂat coil antenna placed on top of a dielectric window (chamber lid) excites the plasma immediately below the window. Process gases ﬂow in from the sides and/or through the center of the window. Due to the large area covered by the coil, plasma generation is homogeneously distributed, and proﬁle control from wafer center to wafer edge is excellent, with no or only minor proﬁle tilting. The lid may be ﬂat or a dome type, and correspondingly the antenna may be a planar or a three-dimensional spiral. In general, the wafer position is located quite close to the plasma generation zone to maintain the uniformity beneﬁts from the homogeneous plasma excitation as much as possible. The proximity to the plasma generation and electric ﬁeld impact zone may sometimes cause problems with etching proﬁles mainly for the high power/high etching-rate conditions, which stem from the high densities of ions and hot electrons in relation to the densities of radicals. 351

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Fig. 23.1 ● (a) Inductively coupled plasma source with ﬂat excitation coil on top of the reactor window. (b) ICP source with excitation coil wound around large dielectric vessel. (c) ICP source with small dielectric vessel and magnetic collimator located below.

In the second type of plasma source (Fig. 23.1b) the coil is wound around a dielectric vessel. This conﬁguration represents the classical ICP source. Process gases are ﬂowing through the vessel from its top toward the wafer below, passing the area of excitation in the vicinity of the antenna coil. The driving electromagnetic RF ﬁeld depends strongly on the distance away from the coil, which gives rise to a signiﬁcantly inhomogeneous plasma excitation which is strongest within a torus close to the antenna coil position. As a consequence of non-uniform plasma generation, etching proﬁles show inherent tilting from wafer center to edge. To reduce the tilting effect, the vessel and coil diameters are normally designed much larger than the wafer diameter. This large-vessel design, however, lowers the average power density of the driving radio frequency (RF power divided by the area enclosed by the coil, typically in the order of 0.5–1 W/cm2), and a large amount of process gas passes through the center of the reactor where only little excitation happens. As a consequence, a large 352

fraction of the gas is unused and dilutes the active species generated elsewhere. This lowers the achievable ion and radical densities and, thus, etching rates. The wafer position can be chosen close to or remote from the plasma generation zone, depending on the applied power level. In a third conﬁguration (Fig. 23.1c), in order to increase source power densities (RF power/enclosed area) and gas breakdown efﬁciencies of the inductive plasma, rather small vessel diameters ( wafer diameter) are used. As one further consequence, extended center areas with only little excitation density and large amounts of process gas ﬂowing through with low radical (and ions) generation rates are excluded. Process gas left unexcited would dilute the concentration of radicals (and ions) generated elsewhere in the higher density excitation zones and must be avoided for high-rate etching. Resulting from its small source diameter and excitation volume, this ICP source conﬁguration yields strong proﬁle variation and tilting from wafer center to edge,

Deep Reactive Ion Etching

which needs correction measures to improve the uniformity of etching results. These include the following provisions, or combinations thereof: Spacers or magnetic multipole buckets between plasma generation and wafer areas as extended drift zones, to cool down and homogenize the plasma, and reduce the ion and electron concentrations at the wafer location. Mechanical apertures, funnels, focus rings, etc., to redirect and homogenize the plasma towards the wafer. Magnetic lens arrangements and magnetic collimators for etching rate and/or proﬁle homogenization. The advantage of this type of source is the very high RF power density (in the order of 20–50 W/cm2) which can be applied to reach high etching speed and to supply a reasonably high radicals/ions ratio at the wafer location. Etch rates up to 50 μm/min and good uniformity, very low proﬁle tilting, and minimum proﬁle disturbances are achievable by proper tuning and optimization of the individual components of such reactor conﬁgurations. In addition, the small plasma generation volume and short residence time therein represent a prerequisite for “ultrafast gas-switching” in a Bosch process. In the cryo-process the temperature of the wafer plays an important role. Besides the capability to cool the wafer down to cryogenic temperatures, accurate wafer temperature control during the process is also essential because the wafer temperature directly affects the sidewall proﬁles. Cryogenic cooling of the wafer stage is done using liquid nitrogen. The wafer is mechanically or electrostatically clamped on the cooled stage and helium pressure is applied on the backside of the wafer. Because of the high thermal conductivity of the helium, heat transfer from stage to wafer is improved. Clamping must be tight to prevent helium leaks to the chamber. Leaks compromise not only the accurate temperature control of the wafer, but also the plasma conditions. In principle, the cryo-process can be operated using a CCP source, but the etch rate and the selectivity would be considerably lower. ●

●

●

23.3 DRIE Processes 23.3.1 DRIE of Silicon The main DRIE techniques are Bosch and cryo-processes [14–16]. The Bosch process is also known as a “switched process” or “time domain multiplexed process.” Both Bosch and cryo-processes use purely ﬂuorine-based plasma chemistry, since ﬂuorine-based etching processes for silicon offer superior etch rates and high mask selectivities. In particular, simple photoresist masking

CHAPTER 23

and easy resist removal make ﬂuorine processes attractive. However, because of the high chemical reactivity and spontaneous etching nature of the ﬂuorine radicals, and the high volatility of the silicon ﬂuorides, the etch is intrinsically isotropic. Since ﬂuorine radicals do not need ion activation to initiate or enhance their reaction with silicon, or to remove the reaction products from the silicon surface, anisotropy can only be achieved by the inclusion of sidewall passivation schemes to the process. All existing DRIE technologies are mainly distinguished and characterized by the way sidewall passivation is achieved, which is the key to anisotropy of the etch process.

23.3.1.1 Bosch Process Etching techniques which make use of relatively hardto-remove compounds as passivating layers, like the silicon oxides or oxyﬂuorides resulting from silicon surface oxidation, suffer from drawbacks. The complete removal of hard passivation from the trench bottom without leaving micromasking residues requires energetic ion impact, eventually in combination with added scavenging agents. Excessive ion sputtering and the use of scavengers reduces the selectivity towards the masking materials. This is especially true in the case of photoresist masking. There is a fundamental tradeoff between a clean trench bottom and a high mask selectivity. To overcome this tradeoff and reach both high mask selectivities and a trench bottom free from residues, hard-to-remove passivating compounds should be avoided in the process. A technique which avoids the formation of such compounds is the deposition of smooth polytetraﬂuoroethylene (PTFE)- or Teﬂon®-like ﬁlms on the silicon surface during etching. Early published work describes the importance of balancing between etching and polymerizing species, and effects of changing this balance for both Si- and SiO2-etching [7]. Plasma-polymerization can be achieved by the generation of (CF2)n-type radicals in the plasma, starting from precursor gases like triﬂuoromethane (CHF3), or preferably hexaﬂuoropropene (C3F6) or octaﬂuorocyclobutane (RC318®, C4F8), the latter being a non-toxic and stable dimer of tetraﬂuoroethylene (TFE, C2F4). The deposited smooth passivating ﬁlm consists of a network of long linear (CF2)n chains with only little cross-linking, which can be easily removed from the etch ﬂoor by low-energetic ion-bombardment without leaving back residues. A mixture of sulfur hexaﬂuoride gas for the ﬂuorine radical supply and octaﬂuorocyclobutane gas for the supply of polymer forming radicals can be used in the plasma to achieve both passivation at the sidewall and etching at the etch ﬂoor, yielding anisotropic proﬁles in silicon. In addition, having ﬂuorocarbons in the process is to some extent scavenging undesired hard passivation from the 353

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Fig. 23.2 ● Basic Mechanism of the “Bosch Process”: The protecting Teﬂon®-like ﬁlm deposited onto the structures during the passivation step is cleared from the trench ﬂoor and driven deeper into the trenches during the (intrinsically isotropic) ﬂuorine-based etching step.

ﬂoor, like silicon oxides from oxygen background gas, or oxygen precipitates in the silicon material itself. However, the presence of ﬂuorine radicals as etching species and of Teﬂon® forming monomers as depositing, ﬁlm-forming species together in the plasma, at the same time, leads to recombination and mutual extinction of both kinds of species. This makes a “mixed process” not easy to control for deeper etches and lowers process performance mainly with respect to etch-rate. These drawbacks appear more relaxed for plasma sources of very high excitation density like the ICP (see later), but still the potential of the “mixed process approach” remains limited to shallow trenches with a depth in the order of 10 μm. The recombination problem is solved by the patented “Bosch process” technology [17], which is a variation of the Teﬂon®-based sidewall passivation technique. Fig. 23.2 illustrates the process mechanism: Passivation and etching gases are introduced separately and alternately into the process chamber and exposed to a high-density plasma, during the so-called passivation and etch cycles, respectively. The high-density plasma is generated by microwave surfatron or inductive radio frequency excitation. During each passivation cycle, a thin Teﬂon®-like ﬁlm is deposited onto the walls of etched structures from C4F8-precursor species. Some scavenging of oxides from the silicon etch ﬂoor may also happen during or after the Teﬂon® deposition step. During the subsequent etching cycle, part of this ﬁlm is removed from the coated sidewall by off-vertical ion impact and driven deeper into the trench (similar to erosion of photomasks and their redeposition to the sidewalls in some classical RIE etches). At the same time, the trench bottom is cleared of ﬂuorocarbon polymer and etched by ﬂuorine radicals released from SF6 in the plasma. Switching times between steps normally range from a few seconds up to one minute, depending on tolerated sidewall roughness. 354

Since the impact of low energy ions is enough to remove the passivating polymer ﬁlm, mask selectivity reaches very high values, for example, 150:1 for photoresist and 300:1 for SiO2 hard masks. If harder passivating polymers were used, more aggressive ion impact would be required, and selectivity toward the masking material would be reduced as a consequence. Transport of the sidewall ﬁlm, that is, removal and redeposition of Teﬂon®-material, yields some local anisotropy of the etching steps which would otherwise be completely isotropic, in the vicinity of the sidewall, but does not adversely affect the main etching reaction away from the sidewall. Sidewall roughness is thus reduced despite the discontinuous process. Since plasma polymerization is non-conformal, in narrow trenches ﬁlm formation preferentially takes place at the trench opening, leaving deeper sidewall regions with less deposited passivating ﬁlm, the ﬂow of polymer material along the sidewalls toward the trench ﬂoor also provides a more uniform sidewall passivation over the trench depth. Fig. 23.3 shows typical structures, proﬁle forms, and characteristic sidewall scalloping as the result of standard “Bosch DRIE” process recipes. The discontinuous nature of the process overcomes a number of problems related to anisotropic etching: First, the recombination loss of reactive species which will not coexist, by gas phase reactions causing their pairwise extinction, is excluded by separating them in the timedomain. This is most important for the volume of the plasma source itself, where species are generated at high concentration levels and where recombination would be strong. Outside the high-density source area, in a more diluted state, coexistence of species is easier to achieve and some mixing there, in the space between the source and the substrate, can be tolerated. This allows switching times to be reduced to well below the chamber residence time

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Fig. 23.3 ● Trench proﬁles and sidewall structure resulting from a typical “Bosch DRIE” process recipe.

Fig. 23.4 ● Design of the gas supply to the plasma chamber for “ultrafast switching” between long etching cycles and very short passivation cycles. A three-way fast magnetic valve is supplying either etching gas to the plasma source or passivation gas bursts from the buffer tank. MFCs are running at constant ﬂow.

without drawbacks in the etching rate, mask selectivities, and proﬁle control. Passivating and etching species are kept separate in the limited volume of the high-density plasma excitation zone, but some overlapping of the species happens on their way down the chamber from the plasma source to the substrate. In a process like that, etching cycles of 1–2 seconds’ duration are interrupted by very short passivation gas bursts of e.g., 100–200 ms duration. The tendency for the etch cycle/passivation cycle time ratio to increase with decreasing passivation cycle time is even greater for very short passivation cycles, yielding ratios of 10:1 or even higher. This corresponds to a process which is etching practically all the time, with very short interruptions by passivation gas bursts. In general, MFCs are unable to switch that fast. Fig. 23.4 shows a design of the gas supply to the process chamber which enables “ultrafast gas-switching conditions” [18]. Both MFCs for etching and the passivation gas are running at constant gas ﬂow. A fast-acting electromagnetic valve supplies the etching gas to the

plasma chamber, while the passivation gas is fed to a buffer tank located close the source inlet. See section 23.4.6 for further discussion. Actuation of the valve blocks the etching gas for a short moment, and the passivation gas accumulated during the etching period ﬂushes into the plasma chamber. This design results in minimized scalloping (see Section 4.3.3 for more discussion). One of the ﬁrst papers describing some of the new applications enabled by the “Bosch process” technology is given in [19]. There has been a continuous progress in the technology, with a number of established equipment suppliers offering dedicated equipment tools for a wide range of purposes, from research up to high-volume manufacturing. Starting from a few μm/min in the early days of DRIE, etch-rates have reached values in excess of 50 μm/min in silicon and are driven even further by new requirements coming from through-wafer-interconnect and chip-stacking technologies emerging in the semiconductor ﬁeld. Typical Bosch process parameters and etch responses are shown in Table 23.1. Rate enhancements result from improvements in both process and equipment technology. The leading equipment for DRIE of today, fulﬁlling the requirements of industrial use, is clearly the ICP source.

23.3.1.2 Cryogenic DRIE Cryogenic RIE dates back to 1988, when it was noticed that by cooling the wafer during the RIE, the rate of chemical reactions on the sidewalls could be reduced dramatically, leading to improved anisotropy [20]. Selectivity between silicon and masking material is also improved at cryogenic temperatures [21, 22]. The ﬁrst results achieved with an industrial etching tool were demonstrated in [23]. The reason for reduced chemical reactions on sidewalls is the silicon oxyﬂuoride (SiOxFy) layer that forms during the cryogenic etching process in SF6/O2 plasma. Fluorine has a very low adsorption coefﬁcient to passivating SiOxFy layer and, therefore, a very 355

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Table 23.1 Typical parameter settings for “Bosch process” using different ICP conﬁgurations

Table 23.2 Typical process parameters of cryo-DRIE processes that result in vertical sidewalls

Parameters

Parameters

Process 1 [16]

Process 2 Process 3 [15] [27]

ICP power [W]

1000

600

1200

CCP power [W]

2

2

(80 V bias)

O2 ﬂow rate [sccm]

6

2

8

SF6 ﬂow rate [sccm]

40

200

80

Pressure [mTorr]

10

14

13

Temperature [°C]

110

110

90

Standard High-Rate High-Rate Conﬁguration Conﬁguration Conﬁguration (Fig. 23.1b) (Fig. 23.1c) & “Ultrafast Switching” (Figs. 23.1c & 23.4)

ICP Power

800 W

2700 W

2700 W

CCP Power

8W

10 W

10 W

SF6-Flow

130 sccm

500 sccm

500 sccm

Etch Cycle Time 7 s

10 s

1.6 s

Etch Cycle Pressure

5 Pa

9 Pa

9 Pa

C4F8-Flow

100 sccm

200 sccm

25 sccm

Dep. Cycle Pressure

2.5 Pa

4 Pa

--

5s

0.2 s

9 μm/min

8 μm/min

Selectivity PR:Si 40: 1

140 : 1

120 : 1

Selectivity SiO2:Si

100: 1

300 : 1

300 : 1

Open Si Area on 6”

15%

15 %

15 %

Dep. Cycle Time 5 s Net Etching Rate (for wide trenches)

3 μm/min

23.3.1.3 Cryo-DRIE Processes

low reaction probability. Etching can proceed downwards because ion bombardment removes the passivating layer from horizontal surfaces [24, 25]. Cold temperatures also reduce spontaneous reactions of free radicals according to the Arrhenius rate law, also improving anisotropy. Still, the main reason to enhance anisotropy is the passivating SiOxFy layer. The high etch-rate in SF6/O2 plasma is due to a high concentration of ﬂuorine radicals. Oxygen controls the quality of the passivating layer. It is the most important parameter when optimizing the sidewall tapers [117]. If the O2 content is too low, an isotropic proﬁle results. Oxygen ﬂow that is too high leads to overpassivation and the formation of silicon grass residues, also known as black silicon. With the cryo-process, sidewalls of the etched structures are smooth, but the etch-rate of silicon is typically lower than in the Bosch process. Because the passivation 356

layer is only ca. 10 nm thick, low energy ion bombardment is enough to remove it from horizontal surfaces [25]. Therefore, the applied bias voltage can be very low and extremely high selectivities can be reached. The downside of the cryogenic temperature is that not all photoresists can stand it, and they shatter like glass during cooling. Thick photoresists are especially prone to cracking. Therefore, hard masks such as silicon dioxide must often be employed [16, 26].

It is typical in plasma etching that exact process parameters are heavily equipment and application dependent. Three different processes are presented in Table 23.2. All have been used to create anisotropic proﬁles. It can be seen that all of these processes utilize process temperatures around –100 °C and all also have similar process pressures, but gas ﬂows and RF powers differ remarkably. ICP power and SF6 ﬂow are the main determinants of etch-rate. The ﬂow rate of oxygen is used to control the quality of the passivation layer, which affects the sidewall angle and undercutting. The sidewall angles of etched features are reported to be near 90 degrees in all three processes. An example of an etch proﬁle is shown in Fig. 23.5.

23.3.2 Etch Masks for Silicon 23.3.2.1 Photoresist Mask The fastest and the simplest way to create patterns is to use photoresist as an etch mask. Typical photoresist thicknesses in the micrometer range limit the etch depth to a few tens of micrometers (assuming a typical RIE selectivity of 5:1) or to hundreds of micrometers (assuming typical DRIE 100:1 selectivity). It is possible to use thicker photoresists, but the minimum linewidth

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Table 23.3 Typical hard mask materials and their most commonly used deposition and patterning methods and applications

Material Deposition Patterning

Fig. 23.5 ● In the cryo-process, vertical sidewalls are easily obtained. Process parameters from Table 23.2, process 1.

increases. Both elevated and cryogenic temperatures are detrimental to photoresists. With the implementation of helium backside cooling in (D)RIE reactors, the problems with photoresist damage (carbonization) have largely been eliminated. Removal of burnt photoresist can be troublesome. At cryogenic temperatures photoresists suffer from cracking [16]. More information concerning photoresists can be found in Chapter 22, which concentrates on lithography.

23.3.2.2 Hard Masks Because of the limitations of the photoresists, hard masks such as silicon dioxide, metals, and metal oxides are often utilized. They offer higher selectivity and also a wider temperature range than photoresists. Hard masks, however, add process complexity. A hard mask has to be deposited and patterned before etching. Deposition of the hard mask material might include high-temperature processes, and the non-idealities in the hard mask etching process degrade the quality of ﬁnal structures. The most common hard mask materials are listed in Table 23.3. Selectivity between silicon and silicon dioxide in conventional RIE is 10:1 to 50:1 and in DRIE approximately one order of magnitude higher. SiO2 can be etched easily and selectively using CHF3 in RIE or wet etching with HF. Oxidation of silicon is a high-temperature step and it limits the use of SiO2. CVD SiO2 can be deposited at lower temperatures, but its quality is inferior to thermal SiO2. Aluminum is a good mask material because of its wide availability in microfabrication facilities and exceptionally high selectivity in ﬂuorine-based RIE processes [16]. Plasma etching of aluminum is possible when using Cl-based chemistry, but usually aluminum is etched using isotropic wet etching, which broadens the original patterns. The thin wedges resulting from wet etching are quickly eroded by plasma, and the edge of

Application

SiO2

(PE)CVD, thermal oxidization

HF (wet), CHF3 plasma (dry)

Deep etching, hightemperature etching

Al

Sputtering, evaporation

H3PO4 (wet), Cl2 plasma (dry)

Extremely high selectivity process

Al2O3

Sputtering, ALD

HF (wet), SF6 plasma

Extremely high selectivity process

Cr

Sputtering

HClO4/ Extremely high Ce(NH4)2(NO3)6 (wet) selectivity process

Ni

Plating

Patterned plating

Quartz etching

the hard mask recedes, widening the trench (or narrowing a ridge). With vertical walled plasma etched hard masks, this is not an issue. In ﬂuorine-based plasmas an aluminum mask is known to generate microroughness. Microroughness is initiated by sputtering and redeposition of the aluminum to the etch ﬁeld, where it acts as a micromask. Some metal oxides, such as aluminum oxide (Al2O3), can also be used as hard masks. The properties of metal oxide hard masks depend on both the chemical nature of the oxide and its deposition process. Some thin metal oxides can be patterned using RIE, which improves the ﬁnal result, but in most cases wet etching is needed in patterning. Deposition of metal oxide can also require special tools such as atomic layer deposition (ALD) equipment.

23.3.3 DRIE of Glasses Silica (pure SiO2) and glass (SiO2 mixed with other metal oxides) are used as substrates when optical transparency, electrical insulation, low thermal conduction, and/or biocompatibility are required. Silica and glass also overcome many limitations of polymers because of their low auto-ﬂuorescence, mechanical wear resistance, reusability, and smooth surfaces. Plasma etching of glass requires ions with high energy and high directionality because the oxide bonds are strong. C4F8, C2F6, and CHF3 are used as etch gases because they exhibit high selectivity with standard masking materials [28, 29]. Alternatively CF4 or SF6 can be used [30– 32], but silicon masking does not provide good selectivity. The glass horizontal surface is covered by a ﬂuoropolymer layer during etching, and the role of this layer is not passivation but is essential to COx and SiFx reaction product 357

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formation. In the absence of carbon, CO2 formation is hindered, and a lower etch rate will result. Liquid or gaseous HF is generally used for isotropic etching of glass. When anisotropic etching characteristics are required, there are many competitive methods to plasma etching for structuring glass. Those include drilling, laser ablation [33], plasma jet [34], powder blasting [35], and ion beam milling [36]. The choice between the anisotropic methods depends on the number and shape of the required features. Drilling is the fastest and simplest method for making a small number of low aspect ratio holes. Laser ablation is comparable to drilling in terms of speed, but it also requires optimization of the ablation process for each glass composition, thickness, and required sidewall proﬁle. A plasma jet can be used if mechanical stresses, fractures, and drilling waste are to be avoided. In powder blasting, particles harder than the substrate hit the surface of the substrate with high velocity, leading to erosion of the substrate. By using an elastic mask that is not eroded, it is possible to form moderate aspect ratios in glass, and furthermore, the angle of attack can be adjusted to yield non-vertical features. The efﬁciency of powder blasting is not dependent on the composition of glass.

23.3.3.1 Equipment Aspects While the main constituent of glass, SiO2, forms volatile ﬂuorides at room temperature, other oxides commonly used in glass (Na2O, K2O, CaO, MgO, Al2O3, Fe2O) introduce an accumulation of non-volatile ﬂuorides in the plasma chamber. The main exception is the Pyrex/boroﬂoat constituent B2O3. Plasma etching of glass requires a platen design with proper clamping, cooling, and charge conduction, and RF power sources suitable for stable high-power processing. Clamping can be realized with two different methods, mechanically or electrostatically. The electrostatic clamping ensures an uncovered processing surface, but is problematic with bowed or dielectric wafers. Because of high ion energies and low thermal

conductivity of glasses, high temperatures are present. Hence, sufﬁcient cooling of the platen must be ensured to avoid the burning of a photoresist mask or the cracking of other masking ﬁlms or even the substrate. When polymerizing plasma precursors are used, the walls of the plasma chamber should be heated to minimize polymer deposition on the walls and to extend the processing time between cleans. After a period of etching, the deposited polymer alters the plasma composition [37] and eventually peels off and lowers yield. To extend the lifetime of the turbomolecular pump, which is generally used as the high vacuum pump in glass RIE and DRIE systems, and to allow the combination of high gas ﬂows and low processing pressure in DRIE systems, a big turbo is recommended. For example, if a 500 sccm He ﬂow rate is used with a 6 mTorr process pressure, stable processing requires a pumping speed in excess of 1500 l/s.

23.3.3.2 Masking Materials The basic thin ﬁlm mask materials for plasma etching of silica ﬁlms are photoresists. Amorphous silicon (a-Si) and metals, e.g., nickel [32, 38], chromium [39], and aluminum, can also be used. Furthermore, many other masks, such as AlN and Al2O3, have been used [123] and silicon wafers have been studied as masks [28][119]. Of these, a-Si and Si cannot be used in SF6 because the etch rate of silicon is always much higher than that of glass. However, the thin masks AlN and Al2O3 show the highest etching selectivity with SF6 involved, if moderate ion energies are used for the non-polymerizing plasma precursor.

23.3.3.3 Glass Etching Processes The etch-rate of silica ranges from 150 to 700 nm/min on a 150 mm wafer with the usual etch load (10–15%). Various glass etching processes with various etch mask materials are listed in Table 23.4.

Table 23.4 Etch parameters and etch rates for oxide and mask materials (nm/min)

Mask

Flows (sccm)

Bias (V)

Coil (W)

Pressure (mTorr)

Rate SiO2/mask

PR

10 C4F8, 8 H2, 174 He

700

1350

3

300/40

a-Si

15 C4F8, 300 He

1200

1150

7

500/25

SU-8

25 C4F8, 50 He

1700

1100

8

700/300

Si

25 C4F8, 50 He, 12 O2

1500

1050

7

600/180

Ni

80 C4F8, 10 O2

600

1200

6

550/25

Al2O3

17 C4F8, 70 SF6

250

800

30

150/1.5

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For an ICP RIE reactor STS AOE™ with photoresist masks SPRT700 or AZ4562, etch selectivity increases and heat load is suppressed when low RF powers are used. However, the etch-rate, uniformity, and sidewall proﬁle would beneﬁt from higher RF powers. The processes with photoresist masks in Table 23.4 have been used for 90° sidewall proﬁles in deposited (PECVD) silica, silicon oxynitride, and silicon nitride thin ﬁlms. The process with a-Si mask has been used for etching both deposited and bulk silica. This process is more aggressive (1200 V vs. 700 V bias) and it cannot be used with a photoresist mask. In general, if resist starts to fail due to an excessive ion attack or an elevated temperature, it turns brown or gray. At this stage, the pattern transfer is usually successful, but if the resist cracks, the pattern transfer fails. If higher aspect ratios are pursued (4:1 for 10–100 μm features and 2:1 for throughwafer structures), the process with an SU-8 mask can be used. With a lower noble gas ﬂow rate and increased bias voltage, a better penetration of ions and radicals into high aspect ratio structures is achieved. Oxygen addition is necessary if deeper than 150 μm features with 3:1 aspect ratio are required. The process with silicon wafer as mask for very deep etching avoids the formation of plasma polymer between the Si mask and the glass substrate and, to a certain extent, on the bottom of the etched features [Kolari, 2007b]. The process with an electroplated nickel mask has been used for etching Pyrex. The process with an alumina mask has been used for etching silica with about 100:1 etching selectivity. This process can also be used for etching silicon anisotropically when the C4F8 ﬂow is increased to 50–80 sccm. It must be noted that all the etching parameters may differ from one piece of equipment to another, even with the same manufacturer, and the outcome is furthermore dependent on the properties of the mask. For example, the glass etching process depends on the details of resist proﬁle.

23.3.3.4 Sidewall Proﬁles While ion bombardment ensures verticality in glass etching, it is also the cause of many unwanted features. The high ion energies cause trenching and often also faceting of the mask, so that the edges of the mask are eroded faster than the bulk of the mask. This nonvertical slope of the mask edge transfers to glass. This has been suggested to be a consequence of the sputter yield differences on sloped surfaces of the mask. Also, the negative net charging of the platen electrode due to faster moving electrons of the plasma and subsequent positive charging of the glass may lead to an enhanced ion hit rate to the mask edge regions due to repulsion of the glass for the positive ions. Basically, 90 degree proﬁles are achieved when faceting is minor and the

CHAPTER 23

process is optimized in terms of RF power, pressure, platen temperature, and gas ﬂows. Etching with high ion energies leads to low etching selectivity. This helps to reduce notching. By increasing the bias voltage (platen power), the sidewall ﬁnish can be altered from footing (concave etch bottom) to trenching (convex etch bottom).

23.3.3.5 Surface Roughness and Micromasking The surface damage on glass is of the same magnitude as on silicon, but the macrosurface roughness develops differently. While the Bosch process on silicon yields lateral undulation (scalloping), the uneven ion ﬂux to the edges of the mask enhances the roughness of the edges of the mask, leading to vertical striations on the etched glass sidewalls. Depending on the edge quality of the mask and on the process conditions, this roughness is tens to hundreds of nanometers. When the facet of the mask hits the substrate, the bumpy surface becomes smoother due to even more ion bombardment. Micromasking in glass etching is similar to silicon etching: small particles of mask material sputter off and land on areas to be etched. In high aspect ratio structures of glass, the polymer unable to leave the bottom or the sidewalls is ﬁrst observed as roughness. Excess polymerization eventually leads to a total halt to the etching on glass.

23.3.4 DRIE of Silicon Carbide Silicon carbide (SiC) is an attractive MEMS material because of its good endurance in hot and corrosive environments. Most SiC process technologies are also compatible with silicon process technologies, but etching of SiC is difﬁcult because of the chemical inertness. Deep etching of SiC relies on inductively coupled high-density SF6 plasma and energetic ion bombardment. The etchrate of SiC in atomic ﬂuorine is extremely low. Therefore, energy provided by ion bombardment is essential in order to obtain reasonable etch-rates (300 nm/min) [40]. The beneﬁt of low reactivity is that no sidewall passivation is needed to enhance anisotropy. The downside is that heavy ion bombardment (a platen power of 50–100 W) also enhances the mask material etch-rate and selectivity becomes a problem. Therefore, hard masks such as nickel, indium-tin-oxide, and aluminum are used in SiC etching. Because of sputtering and the redeposition of mask material, etched surfaces are often rough.

23.3.5 DRIE of Polymers Polymers are not often patterned by RIE, as the alternative techniques of photolithography, casting, hot embossing/ imprinting, and injection molding are well developed. 359

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Table 23.5 Two Bosch processes for DRIE of PMMA [41]

Table 23.6 RIE processes for polyimide and SU-8

Etch parameter/response

Process 1

Process 2

Etch parameter/response

Polyimide [43]

SU-8 [44]

ICP power etch [W]

800

800

Power[W]

500

200

CCP power etch [W]

120

120

O2 ﬂow [sccm]

35

50

ICP power passivation [W]

600

600

CF4 ﬂow [sccm]

8

0

CCP power passivation [W]

0

0

SF6 ﬂow [sccm]

0

2

O2 ﬂow rate [sccm]

50

100

Etch rate [μm/min]

0.7

1.5

C4F8 ﬂow rate [sccm]

85

85

Etch passivate cycle [s]

11 9

8 7

Etch rate [μm/hr]

10

15

Aspect ratio [height/width]

10:1

20:1

Polymers can be etched by oxygen plasmas using silicon, metal, and oxide masks. Even photoresist masks have been used, but the mask must usually be thicker than the layer to be patterned because selectivity between polymers is difﬁcult to obtain. Polymer etch-rates are also heavily dependent on the equipment and the chosen plasma chemistry. Different polymer types can also have very different etching properties. A Bosch process for polymer etching involves an O2 etch step followed by a C4F8 passivation step. A small amount of ﬂuorine containing gas such as SF6 or CF4 can also be introduced into plasma to enhance the etch rate. Polymethyl methacrylate (PMMA) has been etched with a rather slow rate (0.25 μm/min) to create high aspect ratio structures using STS equipment [41]. Detailed parameters of two different PMMA etch processes are presented in Table 23.5. Similar results have been obtained for parylene in PlasmaTherm equipment. Aspect ratios of parylene structures were only 2:1 [42]. Polyimide (Kapton E) and SU-8 polymer RIE parameters etch rates are presented in Table 23.6. Polyimide was etched in a STS oxide DRIE system [43] and SU-8 with Plasma Technology Plasma-Lab PC-5100 RIE equipment [44].

23.4 DRIE Advanced Issues and Challenges

Optimization of rate can have a negative effect on sidewall proﬁle control and vice versa. This chapter discusses some of the issues of ﬁne-tuning DRIE processes, and the non-idealities that may occur.

23.4.1 Vertical Sidewalls DRIE and wet etching of 110 silicon both result in vertical walls. The availability of 110 silicon is limited, and only simple structures (grooves, ridges) are possible because of crystal plane effects in the ends of the structures. DRIE is able to produce vertical walls in any crystal direction, as discussed earlier, but with some non-idealities associated with it. Mirror-like surfaces are more difﬁcult to achieve by DRIE than by wet etching. While cryo-DRIE results in smooth sidewalls, the Bosch process with its undulating sidewall proﬁle is disadvantageous in many applications where exact verticality and smoothness are needed, e.g., mirrors or optical ﬁlters. These non-idealities are depicted in Fig. 23.6. The Bosch process of Table 23.7 has been optimized for vertical walls for optical applications. Its rate is fairly slow (2.4 μm/min) as a tradeoff for minimizing scallops. Bragg reﬂectors with vertical silicon–air multilayer structures have been made by DRIE [46]. A Fabry-Perot interferometer in the plane of the wafer is, thus, possible and can be integrated with actuators for tuning. These processes resulted in sidewall angles of 89.62–90.65 degrees, with good uniformity of sidewall angle across the wafer. With further optimization, 0.3 degrees was achieved.

23.4.2 Sloped Sidewalls Practical DRIE processes are optimized with respect to etch rate and uniformity, but other issues have to be tackled simultaneously: etch rate depends on etchable area, feature size, and shape, all of which become more prominent for high aspect ratio structures. 360

In addition to achieving vertical sidewalls, DRIE enables sloped walls. The negative sidewall angle can be put to beneﬁcial use in fabricating diverging or converging nozzles: a retrograde DRIE etch proﬁle can be connected to

Deep Reactive Ion Etching (a)

(b)

δp

(c)

δs

δr

Fig. 23.6 ● Sidewall non-idealities: (a) parallel deviation, (b) spherical deviation, (c) surface roughness. Source: From Ref. [113].

Table 23.7 Process parameters optimized for vertical sidewalls [45]

Parameter

Passivation

Etch A

Etch B

Pressure (mTorr)

22

23

23

Cycle time (s)

5

2

6

C4F8 (sccm)

70

0.5

0.5

SF6 (sccm)

0.5

50

100

Ar (sccm)

40

40

40

CCP power (W)

1

9

9

ICP power (W)

825

825

825

ﬂuidic inputs either on the wafer backside (converging) or on the front side (diverging) [47]. Positively sloped sidewalls are of great interest in polymer casting and imprinting applications, where masters have to be detached from the cast/molded piece and retrograde angles must be avoided. Silicon DRIE is a major method for making masters for PDMS casting and hot embossing. Alternative techniques include silicon wet etching and SU-8 thick photoresist, which both offer excellent sidewall quality: 10 nm surface roughness is routinely obtained. Silicon offers more durable material properties, but the master fabrication is more tedious. The quality of optimized DRIE silicon masters is acceptable for applications in optoﬂuidic chips: PDMS ﬂuidics and focusing optics have been replicated from silicon masters with excellent performance [48, 49]. Positive tapering is beneﬁcial for step coverage in the following thin ﬁlm deposition steps. Through-vias have been made in a three-step process consisting of a highrate DRIE step and a photoresist strip/clean, followed by a speciﬁcally tailored isotropic tapering step [50]. This has enabled separation of sidewall angle control and etch rate from each other. A typical tapering step consists of SF6/O2 (180/18 sccm) with 700/30 W ICP/platen powers at 12 mTorr (65% APC). The process is done at 10°C.

CHAPTER 23

The etch rate was 1.5–2 μm/min and a time of 20 minutes was used. This leaves the bottom of the deep (300 μm) via vertical but tapers the top to 50–100 μm. In a microrocket application, a negative tapered nozzle was required. This was accomplished by a SF6/C4F8/ O2 process with the following parameters: 200–300 sccm SF6, 80–150 sccm C4F8, 10 sccm O2, 2500W/800 W coil power (etch/passivation), 15–30 W (etch), and 10–20 W (passivation) platen power, with 5–12 s etch and 3–5 s passivation power [47]. In cryogenic DRIE it is relatively simple to play with sidewall tapers, as seen in Fig. 23.7. Three different etching recipes for vertical sidewalls were given in Table 23.2. Increasing the oxygen proportion leads to a positive taper, while increased SF6 leads to negative slopes. In cryogenic DRIE it is also possible to attain sidewall proﬁles that are dependent on the crystallographic structure of silicon [15]. When extremely low temperatures (ca. –130°C) and low ion energies are used, the crystallographic structure of silicon can be seen at the bottom of the cavity, Fig. 23.8. High process pressure also increases the tendency to crystallographic dependent etching.

23.4.3 Loading Effect (Area Dependent Etch Rate) Loading effect refers to etch rate dependence on etchable area [51, 52]. This is a very general concern in chemical engineering and has its roots in reactant supply and consumption balance. When the etchable area is small, etch gas ﬂow can supply enough reactive species, but with higher etchable area, a deﬁciency of reactants may develop. A higher gas ﬂow will compensate for this, but it may be undesirable to increase the ﬂow rate for other reasons, e.g., pumping speed limitations or sidewall proﬁle control. The loading phenomenon exhibits itself on various scales: in batch reactors, the rate depends on the number of wafers in the reactor; in a single wafer reactor, it depends on the chip design. On the microscale, loading manifests itself between dense and isolated structures. The very high etch rates stated for DRIE systems (e.g. 50 μm/min) usually refer to very small etchable areas (e.g., 1% of wafer area). Etchable area also inﬂuences etch uniformity: for the Bosch process, 1.5% uniformity over 150 mm has been reported, at 20% loading, with deterioration for higher loads, especially at the edges. In contrast to silicon DRIE, the glass etch rate is not signiﬁcantly dependent on the load.

23.4.4 RIE Lag and ARDE RIE lag refers to the common observation that small features are shallower than large features. This effect is not seen in shallow etching, but when aspect ratios 361

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Fig. 23.7 ● Changing the SF6/O2 ratio in cryo-DRIE changes the sidewall angle. Negative sidewall tapers are attained when using a high SF6/O2 ratio.

Fig. 23.8 ● Crystallographic dependent etching can be observed at extremely low temperatures and low ion energies.

exceed 1:1, RIE lag manifests itself. ARDE, Aspect Ratio Dependent Etching, is a similar effect, with a slower etch rate observed for higher aspect ratio structures. But ARDE is a dynamic effect: The rate decreases for all linewidths as aspect ratios increase. RIE lag is a “static” effect that can be observed from a single SEM micrograph. ARDE thus manifests itself as a decelerating etch rate for longer etch times [53]. Both effects depend on the fact that reactant and product transport to and from high aspect ratio structures is limited by gas dynamics in narrow features. There are also other factors that inﬂuence the lag: Passivation layer deposition is also an aspect ratio dependent process, and passivation removal etch is an ion-enhanced process. The balance between etching and passivation can change, leading to etch stop [54] or to inverse RIE-lag because of excessive passivation (good step coverage) in large areas, with small areas (less perfect sidewall passivation) being etched faster. It is possible to end up with a lag-free process for a wide range of aspect ratios by adjusting the counteracting etching and deposition lag effects. The etching step has an individual lag effect which depends mainly on, and increases with, 362

the etching step pressure (the supply of etching species and desorption/removal of reaction products). The deposition step also shows an individual lag effect, which depends on, and increases with, the deposition step pressure (the supply of passivating polymerizing species), and also on the composition and hardness of the passivating polymer material itself, the latter being determined by the ion current, ion energy, and substrate temperature of the deposition step [55]. The substrate temperature deﬁnes the minimum length of polymer radical chains which can be adsorbed to the wafer surface. The lower the temperature, the shorter are the polymer chains which stick and remain stuck to the surface; the higher the temperature, the longer the polymer chains need to be in order to stay on the surface. Having a chain distribution which includes also the shorter lengths corresponding to the lower temperature case yields stronger cross-linking of the polymerized material, which makes it denser, more robust, and harder to remove by ion impact. Thus, polymer removal gets more ion-driven and deposition lag increases. Substrate temperature and deposition step pressure are the key parameters used to decide on the deposition step lag. Whatever parameter(s) may be chosen to achieve DRIE lag balancing, it is always at the cost of a reduced overall etching rate in the wide trenches. One more difﬁculty with lag adjustment comes from the fact that the aspect ratio changes dynamically as etching proceeds. The shape of the etchable feature affects the etch rate [56]. Holes of 5 μm diameter are etched slower than trenches 5 μm wide. Making narrow structures side-by-side with large features, e.g., a pillar ﬁlter and a liquid reservoir, or sniffer holes in a microreactor, results in larger areas being deeper than the small ones. The etch rate of glass is dependent on the aspect ratio, and the effect is greater than with silicon. High aspect ratios are possible for small features, but high aspect ratios in large features (hundreds of micrometers in size) are limited by the mean free path of the ions and radicals

Deep Reactive Ion Etching

composing the plasma. Low process pressure, dilution by a noble gas, and the addition of oxygen, which scavenges excess polymer formed from C4F8 and CHF3, can be used to increase aspect ratios. Unfortunately, for this kind of process, the etching selectivity decreases and faceting becomes more pronounced.

23.4.5 Scalloping The Bosch process results in scalloping sidewall due to the pulsed process. The amplitude of scalloping can be minimized to 20 nm by shortening the pulse lengths [46]. However, etch rate may be sacriﬁced. Balancing the etch and passivation pulse ratio and pulse overlaps leads to a less compromised solution. Using ultrafast passivation gas pulses (see Fig. 23.4) of a duration on the order of 100 ms, switched by fast magnetic valves, and using etching cycles of a duration on the order of 1–2 seconds will result in hardly any scalloping remaining at all, at etching speeds not inferior to the standard cycling conditions. However, it must be taken into account that the overall sensitivity of the process toward micromasking by all kinds of surface contaminants increases signiﬁcantly, yielding enhanced microroughness at the trench bottom. This process yields very smooth sidewalls with hardly any remaining sidewall scalloping ( 10 nm), as is depicted in the SEM pictures of Fig. 23.9. Vertical etching processes without signiﬁcant sidewall scalloping bear an inherent risk for micromasking the trench ﬂoor, which, together with the high mask selectivity, may lead to the formation of residues, microroughness, and even microneedles from even minor contamination on the etch surface. Having a sidewall with a periodic nanostructure or ripple on the order of some 10 nm in size is an advantage in this respect: Micromasks smaller than the characteristic dimension

CHAPTER 23

of the scallops are undercut and extinguished from the surface, leaving behind no etch residues. Only if the size of a micromask exceeds the critical dimension limit which the process can tolerate by undercutting will it cause a potential residue problem. This is a drawback of ultrafast gas switching where the sidewall scalloping is practically gone: The latter process recipes are more critical with respect to the formation of microroughness, resulting from micromasking effects that start from a random distribution of incidental contaminants on the etched surface. Scallops can also be treated after DRIE by thermal oxidation, polysilicon deposition and oxidation, and wet etching or combinations thereof [57]. This is discussed in more detail in Section 23.6.

23.4.6 Notching Effect The notching effect (a.k.a. footing effect) is seen when high-density plasma etching reaches an insulator surface (e.g., silicon-on-insulator (SOI) buried oxide or oxide on the backside of the wafer in through-wafer etching) [58, 59]. Charging of the interface leads to ion deﬂection and ion-enhanced sideways etching at the insulator– silicon interface [60]. The dielectric trench ﬂoor charges differently with respect to silicon sidewalls as a consequence of the different angular distributions of differently charged species. Predominant negative species (electrons) have little or no directionality, whereas positively changed species (ions) reach the substrate with an orientation perpendicular to the surface. Thanks to their directionality, a large fraction of the incoming ions can reach the dielectric bottom of even a high aspect ratio trench, and part of them get stuck and accumulate there. In contrast to the ion behavior, most of the incoming electrons get trapped by the structural sidewalls. Strong electrical ﬁelds build

Fig. 23.9 ● SEM pictures of the sidewall resulting from a high-rate “Bosch process” using an ultrafast switching recipe: hardly any horizontal scalloping is visible at the sidewall anymore. Some vertical striations are visible in the lower part of the left-hand side SEM picture, indicating the beginning of microroughness formation at the trench bottom, which also affects the sidewall. The overall etching rate in this case is 8 μm/min.

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up between the positively charged dielectric bottom and the negatively charged silicon sidewalls, redirecting incoming ions to the interface area between silicon and the dielectric layer [58, 61]. Where the redirected ions hit the structure sidewalls, deep notches are cut into the silicon near the dielectric interface (see Fig. 23.10a as a typical example after overetching at the dielectric etchstop). The notches affect the mechanical properties of the fabricated silicon structures in an unpredictable way and represent a serious particle source in manufacturing. A lot of development effort has been put into the suppression of notching for its strong practical relevance. However, notching has also been utilized as a release etch step: The joining of two lateral etch fronts acts as a dry release method without the isotropic character of SF6 plasma release [62, 63]. Since charging and the resulting electrical ﬁelds are the driving forces behind notching, all technical solutions are aiming at a reduction of charge separation in

high aspect-ratio trenches. Pulsing the substrate bias as depicted in Fig. 23.11 gives accumulated charges in the structure a chance to neutralize. Bias breaks with no or little ion impact between the bias bursts with a strong ion impact must be long enough in relation to a characteristic time constant for the leakage currents to discharge. Pulsing is feasible for both RF (13.56 MHz or 2 MHz) and LF (low-frequency) (380 kHz) biasing. LF biasing has some intrinsic advantages with respect to less charging because both electrons and ions are able to follow the (slowly) alternating electrical ﬁeld, the latter despite their heavy masses. As a consequence, in contrast to high-frequency biasing, the electrons are more directed toward the substrate and reach the dielectric trench bottom more easily. This results in a slower and somewhat reduced buildup of charges at the dielectric interface, which is even further reduced by pulsing the bias voltage. The disadvantage of using LF biasing, in contrast to higher frequencies, is that ion energies are

Fig. 23.10 ● (a) Notching phenomenon from overetch at the dielectric etch stop of SiO2, without appropriate countermeasures. (b) Notch-free etch stop on SiO2 after 100% overetch, with the above-described countermeasures taken.

LF or RF Generator (380kHz /13.56 MHz)

Low/High Frequency Carrier 380 kHz / 13.56 MHz

LF Pulse (e.g. 40 Hz, 30%) Low-Frequency Pulse Packages (e.g. 40 Hz)

Fig. 23.11 ● Suppression of notching by Pulsed Substrate Bias Power: RF substrate biasing (low, mid or high frequency) is modulated by a train of short pulses, e.g., at a 40 Hz repetition rate.

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less well-deﬁned and cover a wider spectrum of energies. The latter complicates process control. In addition, matching units for LF biasing are not as well established and stable as for biasing at the high-frequency standard of 13.56 MHz. Typical pulse repetition frequencies are in the range of 30–300 Hz, with duty cycles (pulse on/period time) between 5% and 50%. A more powerful solution for the suppression of notching is described in [64], which represents a combination of a sophisticated pulsing scheme for the substrate bias power and pulsing of the plasma source power. Fig. 23.12 illustrates this method, both the hardware conﬁguration and the pulse-train at the substrate electrode. Switching off the plasma source power periodically yields peaks of negatively charged ions (anions), which are generated in the afterglow when the plasma breaks down and the cooling electrons are caught by neutral gas molecules. In contrast to the undirectional electrons, the anions do reach and effectively neutralize positively charged ions at the dielectric trench ﬂoor during substrate bias power breaks, i.e., when the substrate is not repulsive toward negative charges. Typical repetition rates for the plasma power are between 1 kHz and 5 kHz, at a duty cycle of about 50%. Repetition rates for the substrate bias power are, e.g., 100 kHz for the fast pulse train and 40 Hz for the slow pulse train,

CHAPTER 23

respectively. The substrate biasing scheme depicted is an attempt to emulate LF biasing conditions into RF biasing, with higher peak voltage levels and lower average currents to the substrate electrode, and a reduced charge buildup resulting from the fast modulated pulse train at a low duty cycle. The goal is to emulate some of the advantages of using LF biasing, without incurring the disadvantages. Note that because the carrier frequency is still at 13.56 MHz, standard RF matching is applicable. Using this approach, extremely strong overetch is tolerated without notching; see Fig. 23.10b for an example of a 100% overetch on silicon dioxide.

23.5 DRIE Applications Silicon DRIE steps can have very different roles in the process, and their optimization depends on disparate requirements. Shallow etching is usually associated with good linewidth control (undercut elimination), sidewall smoothness, and sidewall angle control. Deep or through-wafer etching is mostly concerned with rate and mask selectivity, and to a lesser degree with sidewall angle and quality. Intermediate applications can have any mix of requirements. All of these are affected by the device design, through size and shape dependent non-idealities and loading.

Fig. 23.12 ● Anti-Notching Scheme for combined pulsing of Plasma Source Power and Substrate Bias Power. Left: Hardware conﬁguration for pulsed plasma source and substrate electrode. Right: Pulsing scheme at the substrate electrode: RF carrier (13.56 MHz) is modulated by a fast train of short pulses (100 kHz) combined with a slow pulse modulation (40 Hz).

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Silicon DRIE steps can be positioned anywhere in the process ﬂow, but typically deep or through-wafer etches are done at the very end of the process because of wafer fragility after deep etching. Film deposition on DRIE etched structures usually requires highly conformal processes like (LP)CVD, ALD or electroplating. Photoresist spinning on deep structures becomes difﬁcult or even impossible on through-etched wafers, as a vacuum chuck cannot hold the wafer. Alternatives such as dry ﬁlm resists and electrodeposited resists are discussed in Chapter 22 on lithography. Regardless of difﬁculties in resist application after the ﬁrst DRIE step, in many applications multiple DRIE steps are performed in device fabrication.

Constrictions of various sorts, including converging– diverging structures, are essential, for example, in microthrusters, capillary valves, [72, 73] and nozzle-diffuser micropumps [74]. Filters with narrow pass gaps can be made by DRIE but not by wet etching (there are also other approaches to do this, e.g. by bonding and sacriﬁcial layer techniques). The design of suspensions, torsion bars, cantilevers, and other mechanical elements is greatly facilitated by DRIE [75]. Actuation forces/voltages can be tailored by delicately fabricated suspensions, and resonators of beam, square, disk, and other shapes made, depending on the requirements of the device design.

23.5.2 Small Feature Sizes 23.5.1 Free Shape Structures Silicon DRIE is independent of silicon crystal structure, and this enables the fabrication of all possible shapes, some of which are illustrated in Fig. 23.13. This is utilized all over MEMS. In wristwatches, springs can take any shape, and also other silicon microparts, such as wheels and gears, can be made any shape. They can also be made lighter by etching the central parts away, leaving “hollow” teeth in gears [65]. The blades of a powerMEMS microcompressor can be designed for optimum ﬂuid dynamics [66] and micronozzles, and emitters and oriﬁces can be optimized for plume shaping, when DRIE is used [67–69]. Various microreactors, separation systems, mixers, fuel atomizers, and micropower combustion systems make use of meandering, radial, or spiraling channels enabled by DRIE [70, 71]. Shape freedom has implications for the ﬂow proﬁle, as the channel cross-section can be kept constant on turns, or widened or narrowed.

DRIE is essential in the fabrication of small features. DRIE is capable of reproducing accurately practically any features that have been deﬁned by lithography. In trench DRAM technology, silicon trenches 100 nm wide and 10 μm deep are fabricated. Making small lines and gaps in MEMS is limited by lithography cost, which is not a limitation of DRIE. Nanosized gaps can be made by deposition and polishing techniques [76], and etched gaps can be partially reﬁlled to reduce the actuation voltage, e.g., in capacitive sensors and comb drive actuators. Photonic crystals require feature sizes smaller than the wavelength of interest, typically in the range of 100 nm in the visible range. DRIE is one candidate for making photonic crystals. DRIE enabled small features can be closed by deposition, creating closed channels and/or cavities [15]. If wet etching was used, the larger size of the opening would necessitate much thicker ﬁlms for closure. Similarly, if membranes are perforated for isotropic release etching,

Fig. 23.13 ● Shape freedom and small feature size capability of DRIE: microdispenser nozzles for bioanalysis and micro oriﬁces for ﬂuid dynamics studies [78, 120].

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wet etched perforations would compromise the membrane area and mechanical properties, and reduce the advantage of perforations. Small feature sizes are also essential for many actuators; for example, thermal hydrogel actuators work faster when actuation takes place over a very short distance. Using DRIE, pillars can be closely spaced, covered by hydrogel, essentially providing individual actuation for a multitude of hydrogel valves, all of which have to expand only a little to close the channel [77]. Fluid dynamics studies of microﬂows utilize DRIE for making accurately dimensioned microchannels and oriﬁces [78]. Membrane structures with small holes are useful in many drug delivery, fuel cell, and cell probing applications. These membrane holes are later covered, e.g., by Naﬁon-ﬁlm for ionic conductance or by cells or Langmuir-Blodgett ﬁlms for cell membrane transport studies. In a patch clamp application, holes with submicron apertures have been etched in 20 μm thick silicon membrane [79]. In catalysis studies, a small DRIE fabricated capillary leak into a mass spectrometer enabled increased sensitivity and fast response times. Integration of a microreactor with a mass spectrometer also minimized dead volumes [80]. Nanopillars can also be utilized in chemical microsystems. Nanopillars of 100 nm width have been fabricated using cryogenic DRIE and silica nanoparticles as etch masks, resulting in aspect ratios up to 20:1. Desorption/ ionization on silicon mass spectrometry (DIOS-MS) exploits the exceptionally high surface area of a nanopillar structured surface. Black silicon fabricated with DRIE can also be used as DIOS plate material [81].

23.5.3 High Aspect Ratios DRIE enables high aspect ratio structures. Holes and trenches with 10:1 to 20:1 aspect ratios can be fabricated, and pillars with aspect ratios up to 50:1 have been demonstrated: 300 nm feature size, 15 μm structure height [82]. These high aspect ratio structures are

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usually limited to one feature size and shape, or else RIE-lag will affect results. In the fabrication of high aspect ratio trenches, the effective etch rate is reduced with a rising aspect ratio of the trenches. There is a changing balance between passivating and etching species, and a trend toward more passivation with the higher aspect ratios is reached during the etch. In addition, the amount of ions reaching the trench ﬂoor slowly diminishes for reasons of aperture effects at the trench opening, in combination with the angular distribution of the ions. As a consequence, proﬁles tend to develop positive slopes and trenches end up tipping when their aspect ratios reach values of higher than typically 20:1. Given the condition of having trenches all within a similar range of widths, there is a solution to this problem: During the progress of the etch, the process recipe is adapted stepwise or continuously [83, 84] (e.g., to reduce the amount of passivation in the process). For example, passivation cycle time or passivation gas ﬂow can be ramped down steadily. As an alternative, etching cycle time or etching gas ﬂow can be ramped up steadily. Although other options, like source power, bias power, or pressure ramping do exist, changing cycle times is the most obvious parameter ramping strategy for affecting the etch:deposition-balance in a predictable and straightforward manner. With the use of parameter ramping, trenches of 50:1 aspect ratio can be fabricated, while keeping the sidewalls straight and vertical. In hard disk drive actuators, stiffness of the actuator head can be increased by using more complex geometries instead of simple beams. For example, DRIE is essential in the fabrication of 5 μm thick, 200 μm high beams [85]. Applications for high aspect ratio structures include various trapping devices. Depending on the feature size, either micro- and nanobeads are trapped, or macromolecules like DNA; see Fig. 23.14. Out-of-plane microneedles make use of DRIE [86, 87], especially when hollow needles for injection or

Fig. 23.14 ● Si DRIE pillar structures: a) Liquid chromatography column [121]; bead trapping device [122]; DNA separation matrix [82].

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suction are needed, while wet etching is suited for simple needles and tips. Needle density can be increased by using DRIE. Electrospray tips have been microfabricated by various means, but DRIE offers means to integrate multiple nozzles with through-wafer ﬂuidic inlets. Through-wafer DRIE limits the minimum nozzle size to ca. 10 μm nozzle diameter [67].

23.5.4 Deep Structures When through-wafer structures are needed, many workers have reduced etch time by working with thinner than standard wafers (e.g., 380 μm thick 150 mm wafers or 200 μm thick 100 mm wafers) at the expense of mechanical strength of the wafer. But the DRIE depth extends to the full wafer thickness. Over 600 μm deep etches for chemical sensors have already been demonstrated [88], and there are no fundamental limitations for even deeper trenches or via holes. Microturbine/ combustor applications are typical through-wafer applications [89, 90], as are ﬂuidic microneedles [86, 91], drug delivery devices [77], and ﬁltering and suction devices [92] and fuel cells [93]. DRIE is used extensively to remove bulk silicon from the wafer backside, an auxiliary step that was traditionally accomplished by wet etching of silicon [94]. It has been used in various devices (e.g., in freestanding infrared focal plane arrays [95], microneedles [96], ﬂow and shear stress sensors [97], microreactors [98], micromirrors and optical attenuators [99], capacitive force sensors, accelerometers, and even micro pinball games [100]). While, in the wet removal of bulk silicon, boron p

etch stop is used, most of the above-mentioned applications rely on SOI buried oxide for etch stop, or alternatively, thermal oxide in the case of bulk wafers. Through-wafer vias are currently being developed for advanced packaging applications in microelectronics. Typical via diameters are 10–50 μm, i.e., 10:1–30:1 aspect ratios. High-rate DRIE is essential, but taper control is also sought after [50]. This will be discussed further in the section that follows. In some applications deep vias are not etched through, but plated with metal and exposed by backside grinding/polishing [101]. Etched depths are then limited to, e.g., 100 μm (3:1 to 10:1 aspect ratios).

23.5.5 Multidepth Structures In addition to the single lithography-single etched depth approach, DRIE can be used to fabricate more delicate shapes by utilizing gray-scale masks [66]. In gray-scale lithography, the photoresist is shaped to have non-uniform thickness, and the DRIE step is tailored to have resist selectivity compatible with resist height proﬁle. 368

In a microcompressor application, the trailing edges of turbine blades were made 140 μm high compared with 340 μm high leading edges [66]. This technique bears a resemblance to the earlier techniques of photoresist planarization and microlens production, where 1:1 resist selectivity was used to transfer the exact replica of the resist pattern into the substrate. Utilizing RIE-lag to create multidepths in a single etch step depends on mosaic design of well characterized elementary structures and wet etching to remove the walls between the compartments [102]. This technique will be discussed in more detail in Section 23.6. In order to overcome the problem of patterning wafers with deep structures, a peeling mask (a.k.a. a nested mask) approach has been developed. Two lithography steps are used to pattern two layers of mask materials on a silicon surface prior to the ﬁrst silicon etching step. A combination of mask materials (e.g., oxide-resist or oxide-nitride or aluminum-oxide) must enable selective mask removal. After the ﬁrst DRIE step, selective removal of the upper mask (by, e.g., oxygen plasma ashing of resist mask; or HF etching of oxide mask; or phosphoric acid etching of aluminum), more etchable area is exposed, while the non-etched lower mask (e.g., oxide or nitride) still protects selected areas. The second DRIE step both etches the newly opened area and continues deeper in the original areas [103].

23.5.6 DRIE as a Deposition Tool A DRIE reactor can be used as a CVD-like deposition tool by changing process parameters and gases. An important example is the deposition of (CF2)n from CHF3 or C4F8 source gases. This is the basis of anisotropy in the Bosch process, but such ﬁlms have been used in their own right in microﬂuidics to render surfaces hydrophobic. Deposition rates of 300 nm/min are typical. Patterning of these ﬁlms can be done by oxygen plasma with standard photoresist masking and acetone resist stripping, as Teﬂon-like ﬁlms are chemically very tolerant. Alternatively, lift-off techniques [104] or shadow mask techniques with oxygen plasma can be used [105]. Deposition of a Teﬂon-like ﬂuoropolymer ﬁlm on top of a nanostructured silicon surface makes the surface ultrahydrophobic. Lithographically deﬁned patterns can be turned to completely wetting in oxygen plasma, because the ﬂuoropolymer is etched and underlying silicon nanostructures are oxidized. This way, completely wetting areas can be created side by side with ultrahydrophobic surface. This chemically modiﬁed nanostructured silicon surface exhibits a high wettability gradient, which allows the tailoring of complex droplet shapes and the designing of passive droplet splitters [106].

Deep Reactive Ion Etching

23.6 Post-DRIE Etch Treatments The next process step after DRIE can be wet etching or plasma etching, in order to modify the DRIE etch proﬁle, to improve surface quality, or to create new structures by combining smaller individual structures. Combining DRIE and anisotropic wet etching can produce unique structures. For example, 111 silicon cannot be etched by the standard KOH, TMAH, or EDP etchants, but if an initial trench has been etched by DRIE, fast etching crystal planes are exposed, and wet etching can proceed [107]. If this is combined with spacer structures to protect sidewalls and another DRIE step, freestanding 111 silicon structures can be made. The SCREAM process (for Single Crystal Reactive Etching And Metallization) is a process which combines a DRIE anisotropic etch step with an isotropic plasma release etch step (and further processing) [108]. Isotropic etching releases the silicon beam, but the process is limited by the fact that loss of silicon in the vertical direction is related to beam thickness. Similar combinations of DRIE and isotropic etch have been utilized in making microﬂuidic channels. In this case, a sealing ﬁlm by LPCVD ﬁlls the narrow DRIE entry channel and coats the inner wall of the much larger isotropically etched channel; see Fig. 23.15. The mechanical strength of etched structures is strongly related to their surface quality. For instance, microrocket engines with 300 atm pressures put silicon under gigapascal stresses. Surface quality can obviously be optimized in DRIE, but it may be useful to implement a separate smoothing etch step at the end of the process, rather than redesign the whole DRIE process

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[109, 110]. Tests show that both wet etch and dry etch smoothing works: a 100–150% increase in strength has been seen after a smoothing etch has removed a 2–3 μm thick surface layer. Wet etching in, e.g., KOH, TMAH or EPW/EDP, will smooth plasma etched surfaces. If a slow etching plane is reached, surface quality similar to that produced by wet etching will result [111, 112]. KOH:IPA polishing etch after DRIE can improve average sidewall surface roughness remarkably: after etching, an Ra of 150 nm was measured, and after KOH:IPA, 39 nm [45]. Oxidation will consume silicon, and trenches will be narrower after oxidation, and consequently wider after etching the oxide away. If narrowing is desirable, polysilicon deposition plus oxidation can achieve both narrowing and smoothing [57]. Oxidation and polysilicon deposition plus oxidation are also used if insulating structures are required. For example, in electrophoresis devices high voltages are needed and silicon is not an option as a material [82]. Smoothing will also occur by annealing silicon at 100°C in a hydrogen atomosphere. In dye lasers the perfect reﬂectivity of sidewalls is essential, and Bosch process walls must be post-processed to achieve this. On 111 silicon, hexagonal (honeycomb) cavities have been etched, and a post-DRIE wet etching in EPD was used to obtain vertical and smooth walls, Fig. 23.16. This structure has then served as a mold for polymer casting. KOH etching of 110 silicon can similarly be used to improve mirror performance (as evidenced by optical ﬁnesse measurements): Parallel deviation can be made as small as 10 nm, while spherical deviation is practically eliminated (1 nm) and surface roughness is a few tens of nanometers [113]. A combination of RIE-lag and wet etching of sidewalls can be utilized either to eliminate RIE-lag or to

Si(111)

oxidization

(110) (011)

(101)

(101)

(011)

patterning

(110)

dry etching <110>

etching by EPW baking of solution

Fig. 23.15 Sealed microchannels: DRIE trench sidewalls protected by thermal oxide during isotropic channel formation etch step. After buffered hydroﬂuoric acid (BHF) etching of oxide, LPCVD nitride has been deposited to seal the channels [15].

stripping of laser cavity

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Fig. 23.16 ● Wet reﬁnement of undulating Bosch process sidewalls: (111) slow etching planes revealed by EPD etching. Source: From Ref. [110].

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create multidepth microstructures in a single etch step. This requires that the larger patterns be redrawn on the mask as a mosaic of smaller structures. If all mosaic elements are the same size, RIE-lag is eliminated; if they are different in size, multiple etched depths are obtained [102]. The sidewalls between the mosaic pixels are removed by a wet etch step to create larger sloping or terraced structures. A similar technique using isotropic plasma etching has also been described [114]. RIE in combination with electrochemical etching of silicon enhances shape freedom in electrochemical pore etching. If anisotropic wet etching is used to create the initial pits for electrochemical etching, the usual limitations of crystal plane dependence manifest themselves, limiting initial pits to inverse pyramids and trenches. Using RIE, initial pits of any shape can be made, enabling circular and curving shapes to be made [115].

release methods include vapor etching (HF; oxide sacriﬁcial layer), plasmaless dry etching (XeF2 [8, 9], BrF3 [12] or ClF3 [11]; silicon or SiGe [10] as sacriﬁcial layer, and isotropic plasmas (SF6; silicon sacriﬁcial layer). In RIE etching, the details of ﬁlm deposition, doping, and annealing effects can usually be neglected in the ﬁrst approximation. In alkaline wet etching of silicon, heavy boron doping reduces the silicon etch rate in KOH and TMAH by a factor of ten or more, but DRIE processes are doping independent. Plasma etch rates of PECVD nitride and LPCVD nitride are similar, but their wet etch rates can differ remarkably, and the same applies to different CVD oxides even to a greater extent: factors of 3–10 wet etch rate differences are not uncommon. General considerations for and against RIE are summarized as follows: Factors favoring RIE over wet etching: some materials can only be etched by plasmas for many materials, RIE processes are simpler than wet processes photoresist masking works well for many (D)RIE applications etching one side only, and often no protection is needed on wafer backside high rate: 5–50 μm/min for silicon DRIE vs. 1 μm/min for KOH wet etching sidewall angle can be engineered by changing process parameters practically any linewidth can be made high aspect-ratio structures can be made elimination of stiction problems by dry release etch step real-time monitoring possible by optical techniques DRIE can be implemented fairly easily as a post process into CMOS process ﬂow ●

23.7 Choosing between Wet and Dry Etching While a beaker and a hot plate will do for many wet etching processes, plasma etching requires substantial capital expenditure. Therefore, it has to offer process capabilities beyond those of wet etching. For many materials, there is the choice of both wet and RIE processes. Silicon, silicon dioxide, aluminum, tungsten (and other refractory metals), and glass/quartz can be etched by either method. Diamond, silicon carbide, titanium carbide and gallium nitride are materials that do not have wet etch processes, but RIE processes do exist. For some materials, neither RIE nor wet processes exist (e.g., many magnetic garnets). Then IBE can be used to pattern them, or else molding or deposition together with polishing can be used for patterning. Platinum and gold (and other noble metals) can be wet and dry etched, but both processes are difﬁcult since the aggressive etch conditions damage the resist mask. These materials are often patterned by lift-off rather than by etching. Gold can also be electroplated easily. Copper is easily wet etched by various etchants, but all RIE processes have remained experimental so far. If narrow features or high aspect ratio copper structures are desired, either a plating or a deposition/polishing (damascene) process must be used. Releasing structures by isotropic undercut etching in wet solutions is prone to stiction when capillary force exceeds the mechanical spring force of a cantilever, beam, or plate, leading to contact. Dry release techniques avoid stiction by avoiding liquid phase processing. Dry

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Factors favoring wet etching over RIE: selectivities are often excellent in wet etching wet etching is simple wet etching is not capital intensive wet etching has a high throughput in batch mode easy to work with any wafer size and shape, and to process pieces of wafer some materials that are hard to etch with RIE are easily wet etched surface quality of hydroxide etched silicon is superior to that of plasma etched wet etching removes surface damage created by energetic processes

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for transdermal liquid transport, J. Microelectromech. Syst. 12 (2003) 855–862. 92. R.B. Maxwell, et al., A microbubblepowered bioparticle actuator, J. Microelectromech. Syst. 12 (2003) 630. 93. J. Yeom, et al., Microfabrication and characterization of a siliconbased millimeter scale PEM fuel cell operating with hydrogen, methanol, or formic acid, Sens. Actuators B 107 (2005) 882–891. 94. B.W. Chui, et al., Low-stiffness silicon cantilevers with integrated heaters and piezoresistive sensors for high-density AFM thermomechanical data storage, J. Microelectromech. Syst. 7 (1998) 69. 95. X. Wang, et al., IR imaging using a cantilever-based focal plane array fabricated by deep reactive ion etching technique, Appl. Phys. Lett. 91 (2007) 054109. 96. S.-J. Paik, et al., In-plane singlecrystal-silicon microneedles for minimally invasive microﬂuid system, Sens. Actuators A 114 (2004) 276– 284. 97. A.A. Barlian, et al., Design and characterization of microfabricated piezoresistive ﬂoating element-based shear stress sensors, Sens. Actuators A134 (2007) 77–87. 98. R.M. Tiggelaar, et al., Fabrication of a high-temperature microreactor with integrated heater and sensor patterns on an ultrathin silicon membrane, Sens. Actuators A 119 (2005) 196–205. 99. K. Isamoto, et al., A 5-V operated MEMS variable optical attenuator by SOI bulk micromachining, IEEE Sel. Topics Quantum Elect. 10 (2004) 570. 100. M. Bring, A. Sanz-Velasco, H. Rödjegård, P. Enoksson, Micro pinball game demonstrating an easy MEMS transfer process using room temperature plasma bonding, J. Micromech. Microeng. 13 (2003) S51–S56. 101. T. Rowbotham, et al., Back side exposure of variable size through silicon vias, J. Vac. Sci. Technol. B 24 (5) (2006) 2460. 102. J. Kiihamäki, H. Kattelus, J. Karttunen, S. Franssila, Depth and proﬁle control in plasma etched MEMS structures, Sens. Actuators 82 (2000) 234–238. 103. L. Sainiemi, T. Nissilä, V. Jokinen, T. Sikanen, T. Kotiaho, R. Kostiainen, R.A. Ketola, S. Franssila,

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Fabrication ﬂuidic characterization of micro-pillar array electrospray ionization chip, Sens. Actuators B Chem. (2007) doi: 10.1016/ j.snb.2007.09.077. H. Andersson, W. van der Wijngaart, P. Griss, F. Niklaus, G. Steeme, Hydrophobic valves of plasma deposited octaﬂuorobutane in DRIE channels, Sens. Actuators B75 (2001) 136–141. K. Kolari, A. Hokkanen, Tunable hydrophilicity on a hydrophobic ﬂuorocarbon polymer coating on silicon, J. Vac. Sci. Tech. A 24 (2006) 1005. V. Jokinen, L. Sainiemi, S. Franssila, Complex droplets on chemically modiﬁed silicon nanograss, Adv. Mat. (2008). S. Park, et al., Mesa-supported, single-crystal microstructures fabricated by the surface/bulk micromachining process, Jpn. J. Appl. Phys. 38 (1999) 4244. N.C. MacDonald, SCREAM MicroElectroMechanical Systems, Microelect. Eng. 32 (1996) 49–73. K.-S. Chen, et al., Controlling and testing the fracture strength of silicon on the mesoscale, J. Am. Ceram. Soc. 83 (2000) 1476–1484. K.-S. Chen, et al., Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE), J. Microelectromech. Syst. 11 (2002) 264. H. Kattelus, Wet reﬁnement of dry etched trenches in silicon, J. Electrochem. Soc. 144 (1997) 3188. M. Sasaki, et al., Anisotropically etched Si mold for solid polymer dye microcavity laser, Jpn. J. Appl. Phys. 39 (2000) 7145. S.-S. Yun, S.-K. You, J.-H. Lee, Fabrication of vertical optical plane using DRIE and KOH crystalline etching of (110) silicon wafer, Sens. Actuators A 128 (2006) 387–394. T. Bourouina, T. Mazuzawa, H. Fujita: The MEMSNAS process: microloading effect for micromachining 3D structures of nearly all shapes, J. Microelectromech. Syst. 13 (2004). K. Grigoras, A.J. Niskanen, S. Franssila, Plasma etched initial pits for electrochemically etched macroporous silicon structures,

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chromatography, Anal. Chem. 70 (1998) 3790–3797. 122. H. Andersson, W. van der Wijngaart, P. Enoksson, G. Stemme, Micromachined ﬂow-through ﬁlterchamber for chemical reactions on beads, Sens. Actuators B67 (2000) 203–208. 123. K. Kolari, High etching selectivity for plasma etching glass with AlN and Al2O3 masks, Microelect. Engin. (2008).

24

Chapter Twenty Four

Wet Etching of Silicon M.A. Gosálvez1, I. Zubel2 and E. Viinikka3 1

Laboratory of Physics, Helsinki University of Technology, Espoo, Finland Faculty of Microsystem Electronics and Photonics, Wrocław University of Technology, Wrocław , Poland 3 Culmination Innovation Oy Ltd, Espoo, Finland 2

24.1 Basic Description of Anisotropic Etching: Faceting Wet etching consists of the use of an alkaline or acidic solution (the etchant) to chemically remove material from the surface of a sample. Etching has its origins in an artistic technique, developed in the ﬁfteenth century, consisting of covering a metal surface—such as that of a knight’s armor—with a waxy material, removing part of the wax to create the desired decorative pattern, and ﬁnally dipping the surface in an acid solution to chemically remove the metal from the wax-unprotected areas, thus transferring the pattern to the metal. In addition to metals, etching can also be used to create patterns in many other materials. In the area of micro/nano electro-mechanical systems (MEMS and NEMS), functional shapes and patterns are typically created in silicon and other substrates [1]. Instead of the concentrated acids used for metals, alkaline solutions such as potassium hydroxide (KOH) [2], tetramethylammonium hydroxide (TMAH) [3], or ethylene diamine pyrocatechol (EDP, also EDA) [2, 4] are commonly used to etch silicon. Similarly, instead of wax-like masks, the pattern transfer is based on materials that are inert to the chemical attack by these etchants, such as silicon oxide (SiO2) and silicon nitride (Si3N4) [2]. As an example, wet etching can be used to produce square diaphragms and V-grooves on Si{100} wafers as well as deep vertical grooves on Si{110} [4], as shown in Figure 24.1a–c. More complicated structures such as three-dimensional

accelerometers and comb-drive resonators, as shown in Figure 24.1d–e, can be achieved by sequentially etching on different masks and/or by additional dry-etching techniques, as described later. Recently, conformal wet etching of curved microchannels has been achieved by a single etch step and mask [7], as shown in Figure 24.1e. For crystalline samples like silicon, anisotropic wet etching refers to the case where certain crystal lattice orientations, such as {111}, are etched at a lower rate than others, such as {110}. In simple terms, such planes are difﬁcult to etch as their atoms have stronger bonds and/or a larger number of them. Combined with the use of mask patterns, the etch-rate anisotropy becomes a most valuable property, as it provides a low-cost, precise means for the production of three-dimensional shapes delimited by smooth, shiny facets, leading to complex structures with multiple functionalities. Typically, the crystal facets appearing on the etched structures correspond to the slowest etching planes for concave geometries, such as cavities and trenches enforced by the use of masks [8], but the facets are governed by the fastest etched orientations for convex shapes, such as the corners of square islands [9] and the overall surface of a spherical specimen [10–12]. The formation of crystal facets due to etching is referred to as faceting. Today, anisotropic etching remains a popular method for the fabrication of MEMS and NEMS devices. In MEMS, bulk micromachining refers to the etching of the substrate, which can be achieved by isotropic or anisotropic liquid phase (wet) etching as well as by plasma phase (dry) etching, as explained subsequently. In comparison, 375

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Fig 24.1 ● Wet etching using a single mask and a single etch: diaphragm (a) and V-groove (b) on Si{100}, and deep vertical grooves on Si{110} (c). (d) 3D monolithic accelerometer realized by wet etching of Si{100} in several steps (Fig. 3 from Ref. [5], reproduced with permission by IOP). (e) Dry-etched comb-drive resonator released using wet etching (Fig. 4(d) from Ref. [6], reproduced with permission by JJAP). (f) Conformal, round-feature preserving, wet etching on Si{100} (Fig. 6 from Ref. [7], reproduced with permission © 2008 IEEE).

surface micromachining creates the structures on top of the substrate by successive deposition and selective etching of thin sacriﬁcial and/or functional layers of various materials (see Chapter 28). Both bulk and surface micromachining can be realized with wet or dry etching, or a combination of both.

24.1.1 Isotropic and Anisotropic Wet Etching The isotropic or anisotropic character of wet etching is due to the relative importance of diffusion transport of the reactants and/or products, in comparison with the kinetics of the reactions taking place at the surface. If all the surface reactions are fast, the rate of etching is then controlled by the supply and deployment of the reactants and products, which is a diffusion process. In this case, all surface atoms are removed at similar rates, and as a result, the overall etch rate is not sensitive to the particular orientation of the surface. Diffusioncontrolled etching is isotropic and, thus, characterized by the formation of round etch proﬁles [13]. However, if there are wide differences in the removal rates of the different atoms (site-dependent rates), etching is then 376

controlled by the reaction kinetics—that is, by the relative values of the removal rates [14–17]. Since different surface orientations contain different amounts of different surface sites [18], kinetics-controlled etching is anisotropic, characterized by the apparition of crystalline facets (faceting). Typical isotropic and anisotropic etchants of silicon are presented in Section 24.8, including essential data for microfabrication.

24.1.2 Etchant Selectivity, Mask Alignment, and Etch Stop At minimum, etching is based on the combined use of a substrate, a mask, and an etchant. Thus, there are three critical aspects for its successful application: (i) the etchant selectivity, (ii) the alignment accuracy between the mask pattern and the crystalline lattice of the substrate, and (iii) the ability to stop the process at the desired moment during the evolution. In addition, substrate features such as the surface quality and the presence of bulk microdefects can have an important effect, as discussed in Section 24.5. Perhaps the most important of the previous aspects is the etchant selectivity. Ideally, an etchant must etch the substrate without etching the mask. For surface micromachining, the etchant must

Wet Etching of Silicon

entirely remove the top layer of a multilayer structure without damaging the underlying and/or masking layers. The selectivity, deﬁned as the ratio of the etch rates in two materials, characterizes the ability of the etchant to perform selective micromachining. Of the many known silicon anisotropic etchants—such as NaOH, KOH, LiOH, CsOH, RbOH, NH4OH, EDP, TMAH, hydrazine, NH4OH-added HF, NH4F, HF/NH4F mixtures, etc.—only KOH, EDP, and TMAH are able to provide enough selectivity against the various masking materials while preserving realistic silicon etch rates. Although conventional photolithography routinely ensures accurate transfer of the pattern design onto the mask layer (see Chapter 22), keeping the features aligned with the underlying crystalline structure of the substrate can be a challenge [19]. A small misalignment can result in unexpected underetching (see Section 24.5) and/or may induce additional step ﬂow propagation (see Refs [19, 20]), leading to deviations in device geometries as well as the formation of spurious morphologies. Another important parameter is the ability to stop etching when desired. Although this can be done simply by keeping track of the etched time, more sophisticated approaches allow a more precise and ﬂexible control of the etched depth and/or device shape [1, 21]. Most approaches are based on passivating silicon by forming a thin silicon oxide layer that resists etching. In the electrochemical passivation method, an external voltage is applied to the silicon sample at the desired moment in time, resulting in the formation of the oxide layer [22] and stopping etching. A similar effect can be achieved without using an external potential, when a highly boron doped layer is used on top of a lower doped substrate of either p or n-type. Etching automatically stops when it reaches a p-type boron-doped region that has an impurity concentration exceeding 2 1019 atoms/cm3 (boron etch stop) [23]. In the applications, such as the fabrication of thin p-type silicon membranes, the bottom side of the wafer is p-doped to a depth D W − H, where H is the desired etching depth from the n-type top side and W is the wafer thickness. This completely relaxes the need for monitoring the etch time. Alternatively, etching the p-type region and stopping at the n-type silicon can be achieved by applying a positive voltage. The resulting electrochemical etch stop method, which reverse-biases the pn-junction for the whole duration of etching, is probably the most suitable and successful etch stop technique [24]. No current ﬂows to the p-type region due to the reverse-bias and, as a result, this region is etched as it would be normally. Once the p-type silicon has been removed and the junction disappears, the n-type silicon is etched under the positive bias voltage, which results in the formation of the oxide layer, passivating the surface and stopping etching. Thus, thin n-type membranes can be formed.

CHAPTER 24

In addition to relaxing time control, this allows lower doping impurity levels for improved mechanical properties of the resulting structure (e.g., reduced internal stress) and/or better compatibility with microelectronic circuitry fabrication. As an alternative to the electrochemical methods, silicon-on-insulator (SOI) wafers can also be used to control precisely the etch depth down to the buried silicon oxide insulator layer [25]. The growth of epitaxial layers for such purposes is considered in Chapters 5 and 6.

24.1.3 Advantages of Wet Etching Versus Dry Etching In recent years alternative technologies such as deep reactive ion etching (DRIE) have penetrated the traditional territory of the wet etchants (see Chapter 23). Such dry etching techniques produce vertical material removal that conforms to the mask design—which may include curved features—independently of the crystallographic alignment between the mask and the sample. Similarly, other technologies including epitaxial and conformal growth, such as atomic layer deposition (ALD; see Chapter 26), and surface micromachining, using a succession of thin ﬁlm deposition and selective etching (see Chapter 28), provide additional levels of complexity and ﬂexibility to the realization of the microstructures. However, the higher costs and limitations of batch processing by these new technologies still make chemical etching the most affordable method for the reliable production of three-dimensional structures with multipurpose functionalities. If wet etching can be used to deliver a similar intermediate or ﬁnal structure, then typically this option is preferred. In practice, most of the time, the fabrication of a MEMS device involves an increasingly sophisticated combination of all these different technologies. To mention some examples, anisotropic etching has been used alone and in combination with other techniques to produce a wide range of devices such as pressure, acceleration, angular rate and gas-ﬂow sensors, actuators, nanoprobes, nanowires, nanochannels, micromirrors, laser cavities, optical switches, alignment grooves, microvalves, and many others. The wide prevalence of anisotropic etching is not only due to its ease of use and low cost, but also to the fact that it can provide very smooth surfaces [16, 26–28] with no physical damage to the bulk structure of the material and very precise angles between the developed facets. At minimum, wet etching is needed for the release and controlled undercutting of freestanding and suspended structures [13, 29–31], which is intractable by other microfabrication techniques. It is also needed for cleaning and/or surface preparation [32]. In addition, anisotropic etching is an outstanding technique for the production of device features at the nanometer scale, 377

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such as nanowires, which are assembled on stepped surfaces resulting from wet etching [33, 34]. Wet etching is a versatile technique, as it provides many possibilities by varying the etchant concentration and temperature [2, 11, 12, 35–39] (see Sections 24.10 and 24.11), as well as the amount of impurities [40–43] and stirring state [44–47] of the etchant, depending also on the doping type and level in the substrate [24]; the application of an external bias potential [48–52]; or the use of etchant additives such as surfactants [53–58], alcohols such as isopropanol [59–61], and other oxidizing agents [62, 63]. It is typically pointed out that anisotropic etching depends too strongly on the crystalline structure of the substrate, thus limiting device design to a restricted number of ﬂat surface orientations without curved features. However, the realization of conformal etching following curved and straight mask features from the use of a wet etchant has been reported recently (Figure 24.1f).

24.2 Beyond Faceting: Atomistic Phenomena In spite of the widespread and technological maturity of anisotropic etching for applications, the complexity of the process—involving chemical and electrochemical reactions sensitive to a multitude of parameters—has traditionally prevented a satisfactory understanding of this technique. Experimental, theoretical, and computational work in the last two decades has led to an important change of mentality. Although the etch rate anisotropy leads to faceting, the description of anisotropic etching as the propagation of a collection of crystallographic planes is an oversimpliﬁcation. Anisotropic etching is not considered anymore as a macroscopic process involving the propagation of an evolving facetted surface, but rather, it is regarded as a manifestly non-equilibrium process dominated by atomistic phenomena that shape the particular morphology and control the kinetics of each surface orientation. The most important microscopic processes are brieﬂy presented next. (See, e.g., Ref. [18] for further details.)

24.2.1 Pit Nucleation and Step Flow Typically, the Si{111} crystallographic surface is very stable against etching and, as a result, etching proceeds by the removal of atoms from the steps formed between {111} terraces, as shown in Figure 24.2a. As a result of the propagation of the steps, complete terrace layers are etched away, providing a mechanism for the propagation of the overall surface. If a surface does not have any steps, pits are slowly generated by the direct removal of stable terrace atoms, as shown in Figure 24.2b. This process is speeded up by the existence of lattice defects 378

such as stacking faults and/or dislocations perpendicular to the surface, acting as pit nucleation centers. In the absence of such defects, the nucleation of the pits is predominantly an electrochemical process (see Section 24.3) that can be minimized by (i) using single polished {111}-wafers (cathodic protection of the polished side by the rough face, which acts as a sacriﬁcial anode [28]), (ii) etching in Ar or Ne atmosphere, in order to remove dissolved oxygen from the etchant phase [16, 28], and (iii) etching with a small bias potential [27, 28]. The relative rates of pit nucleation and step ﬂow give rise to two scenarios: (i) If pit nucleation is relatively infrequent, most atom removals will occur at the pit perimeter, where precursor step sites are available, eventually transforming the perimeter into distinguishable steps as more atoms are removed (Figure 24.2b). As a consequence of the propagation of the pit-delimiting steps, the pit will grow planarly and ﬁnally will coalesce with other pits, thus completing the removal of a layer of material. (ii) If pit nucleation occurs often, the surface is roughened and irregular-looking steps may form and propagate, or not form at all—depending on the relative rate of pit nucleation and step propagation.

24.2.2 Micromasking Micromasking refers to the presence of numerous, independent, simultaneous, small-scale, blocking locations on the surface due to the formation of insoluble compounds or the deposition of relatively stable agents that do not react with the etchant, such as atoms, molecules, or larger clusters whose size is well below the micron scale. Hydrogen bubbles, polymerized residues, reaction products and/or SiO2 precipitates, regrowth of silicon, semipermeable silicate particles, and (metal) impurities can act as micromasking agents [64]. Among all morphologic features that can be explained only by the presence of micromasks, the most important are the pyramidal and trapezoidal hillocks appearing on Si{100} and Si{110}, respectively, as shown in Figure 24.2c–d, and the so-called noses of the zigzag structures appearing on exact and vicinal {110} surfaces [18]. Although having an atomistic micromasking origin, these morphological defects can grow large enough to reach the micron scale, becoming relevant for the design and development of MEMS structures. The stability of the pyramidal and trapezoidal hillocks as a function of the etchant concentration depends on the fulﬁllment of the four conditions shown in Figure 24.2c [18, 42], as described in detail in Section 24.2.4.

24.2.3 Diffusion Diffusion refers to the time delay between the surface atomistic reactions and the transport of the reactants

Wet Etching of Silicon

(a)

(b)

Pit nucleation

Vicinal {111} toward {100}

Vicinal {111} toward {110}

Step flow

Step flow

Step propagation

{111} Terraces

{111}

{111} Terraces

Pyramidal hillocks

] ] 10 01 [1 [0

[110] – [110]

...on Si{110} {111}

1}

...on Si{100} (2) (1) (3)

Trapezoidal hillocks

(d)

10 μm

10 μm

(f)

Well aligned mask pattern on Si{113} wafer

(g)

(113) wafer 2.5° (111) terraces (or ‘striations’)

(100)

(997) step bunches on vicinal {111} due to inhomogeneities Inhomogeneities lead to bunching

(111) pieces of nitride

Acc.V Spot Magn Det WD 5.00 kv 3.0 100% SE 24.3

No inhomogeneities, no bunching

Mask misalignment induces exposure of vicinal {111}

(113)-wafer 0°

~110°

nm 50

(4) (1) Micromasking of apex (2) Floor moves down fast (3) Edges are stable (4) Facets are very stable (e)

~70°

~{ 31

(c)

CHAPTER 24

200 μm

Acc.V Spot Magn Det WD 5.00 kv 3.0 100% SE 28.6

(997)

200 μm

Fig 24.2 ● Essential atomistic mechanisms of wet etching: (a–b) pit nucleation and step ﬂow; (c–d) micromasking enables the formation of pyramidal and trapezoidal hillocks; (e–g) diffusion inhomogeneities in the etchant give rise to step bunches. All morphologies are frequently met during the development of MEMS devices.

and/or products to the regions of consumption/production. When etching is anisotropic and thus there are wide differences in the removal rates of the different atoms, the diffusion of the different species can result in the formation of etchant inhomogeneities. These refer to concentration depletion regions and/or localized temperature gradients around the active locations, such as the steps. The presence of such inhomogeneities leads to changes in the local etch rate, eventually affecting the overall etched morphology by means of an ampliﬁcation mechanism as time passes. As an example, it has been shown experimentally, and theoretically through simulations, that the formation of step bunches on vicinal Si{111} surfaces (see Section 24.4.4) is strongly dependent on the formation of such inhomogenous regions in the etchant [65]. Similarly, the zigzag structures characteristic of the morphology of Si{110} (see Section 24.4.3) are mainly

the result of similar etchant inhomogeneities [66]. It is also believed that the shallow round pits on Si{100} (see Section 24.4.2) are due at least partly to similar inhomogeneities of circular shape [18]. All of these morphologic features have been observed during the development of MEMS structures [18, 19, 67].

24.2.4 Orientation Dependence of the Etch Rate (M.A. Gosálvez and I. Zubel) The dependence of the silicon etch rate on the crystallographic orientation of the etched substrate and solution composition can be connected to the differences in the local neighborhood of the exposed surface atoms, such as the numbers of neighbors, dangling bonds, and surface bonds. The arrangement of the atoms on the 379

Micromachining Technologies in MEMS

PA R T I V

SM

(a)

SM

(b) (110)

[110]

SM

SM SM

TD TD

SM

(110) (551) (331) (221)

SM

(331)

SM TMSM TM SM TM

(111) TM

(111)

(h 1 1)

SM TM SM TM SM TM

SD TD TM

SD TM SD TM SD TM SD

(331)

(311) SD TM TM SD TM TM SD

(h +2 h h)

(221)

(211)

(211)

TM

SM TM TM SM TM TM SM

(111)

SD

TD TD

(411)

(h +2 h +2 h)

TM

(100) (511)(311) (211) (334) (100)

TD TM SD

(441)

TD

(100)

(110)

TM

(331)

(443)

TD

TD

(h h 1)

(211)

TM TM TMTM TM TM

(100) (c)

(111)

H

R331 = α

3Δt

(110)

=

D cosα 3Δt

=

a

D=

a 2

19 (110)

, cosα =

6 19

, Δt = 1 2 α

(110) D

(331)

(331)

(110) (331) D H

Δt

Δt

(331) Δt

α

Fig 24.3 ● (a) The four key surface sites: SM, TM, SD, and TD. (b) Crystallographic cut of several surfaces displaying the key sites. (c) Derivation of the etch rate for {331} (simple cellular automaton model).

different planes has been described and classiﬁed in different ways, resulting in different models of etching [16, 17, 59, 61, 68–75]. The most accepted classiﬁcation identiﬁes four key surface sites, as shown in Figure 24.3a, b: (1) the terrace monohydrides (TM), appearing on {111} terraces; (2) the step monohydrides (SM), located at the steps of vicinal {111} surfaces inclined towards {110}—which form a series of planes globally referred to as the {h 2 h 2 h} and {h h 1} families, where h is an integer, also including {110}; (3) the step dihydrides (SD), located at the steps of vicinal {111} surfaces inclined towards {100} (identiﬁed as the {h 2 h h} and {h 1 1} families); and, (4) the terrace dihydrides (TD), located on {100} “terraces”. The classiﬁcation into monohydrides and dihydrides is based on the fact that the etched surfaces are mostly terminated by hydrogen atoms during etching, with a minor amount of terminations by OH (see Section 24.3). Similarly, the step and terrace division of the surface sites is based on the step-ﬂow nature of the process (see Figure 24.2a, b). In a simpliﬁed picture anisotropic etching can be thought of as a sequence of removals of low-coordinated atoms—such as the step atoms (SM and SD) and {100}-terrace atoms (TD)—while not affecting the {111}-terrace atoms (TM). Here, the atom coordination refers to the number of neighbors, typically different for different surface sites. In a more realistic picture each surface site has a different 380

rate of removal, in such a way that high-coordinated atoms are typically removed less frequently. The site-speciﬁc nature of anisotropic etching is ultimately due to the existence of different energy barriers for the removal of the different surface atoms. Although the underlying explanation is still debated, the site speciﬁcity is probably the combined result of several features and mechanisms, including the following: (i) the number of surface and bulk bonds (or, equivalently, the number of surface and bulk neighbors). The bonding energy of the surface bonds is lower (breaking is easier) than for the bulk bonds due to the back-bond weakening effect of the terminating hydrogen (H) and/or hydroxyls (OH). The presence of more surface bonds (or, correspondingly, more surface neighbors) increases the etching rate, and the planes having atoms linked with surface bonds solely—like, for instance, {110} and {311}—tend to exhibit the highest etching rates. (ii) Coordination. As shown in Section 24.6, the removal of a surface atom requires that both water molecules and hydroxyl ions are available in the etchant phase close to the surface site. As a result, the larger the amount of empty space around the site (i.e., the lower the atom coordination, the higher the reactivity). Correspondingly, the step and kink sites are expected to be more reactive than the terrace sites. (iii) Selective site blocking by large cations and/or etchant additives. Although typically {110} should be a fast orientation, it is known to become a local minimum of the

Wet Etching of Silicon

etch rate in KOH IPA and low concentrated TMAH. This is attributed to a selective blocking mechanism by the large cations (such as TMA ) and long additive chains (such as IPA and others, like surfactants), favoring attachment to the monohydride sites. (iv) Steric hindrance for OH-termination. The presence of OH groups as local terminations on the surface can modify the attachment likelihood for additional hydroxyls in the proximity. As a result, surface sites with hindering OH-terminations are less reactive than similar sites that have the same number of OH-terminations without steric hindrance. (v) Strainmodiﬁed nonideal tetragonal geometry. The local strain in the tetrahedral geometry of a surface site can be used as an indicator of reactivity, since the more strained sites should present a lower energy barrier to achieve the postulated, highly strained transition state. Finally, (vi) structural rigidity needs to be considered also since being linked to several rigid bulk atoms or to easily deformable atoms—as in molecules—can make a signiﬁcant difference for the success of the reaction. Although each of the previous mechanisms stresses a different aspect of the atom removal process, many of them are interrelated and typically should be considered together. Generally, it is possible to qualitatively explain the relative reactivity of the different sites by using a combination of the previous mechanisms, especially the atom coordination and the numbers of surface and bulk neighbors.

24.2.4.1 A Simplistic Model of Anisotropic Etching: BCA The anisotropic etching of any crystallographic plane can be described simplistically as a sequence of collective removals where all current surface atoms are removed simultaneously, except for the ones located at TM sites. As an example, the {211} surface of Figure 24.3b is etched by removing all the step atoms (SD) simultaneously, leaving the terrace atoms (TM) untouched, whereafter the surface will present new step atoms that can be removed again. By repeating the process sequentially many times, the advancement of the overall crystallographic plane along its normal direction is obtained. Due to differences in the geometry of the removed atoms for the different crystallographic planes and in the overall distance advanced along the surface normal, the previous model results in a different etch rate for each surface, as described for {331} in Figure 24.3c. Taking the unit of time as t 1 and a as the lattice parameter of the conventional unit cell of silicon, one gets R100 a / 4, R211 a /(2 6 ), R331 a / 19 ,

R110 a /(2 2 ), R311 a / 11, R221 a /(2 19 ),

R111 0, … … (24.1)

CHAPTER 24

with similar expressions for other surface orientations. The general trend in the dependence of these etch rates with orientation happens to be in good qualitative agreement with some experiments, such as etching in KOH at medium concentration (e.g., 30–40 wt% KOH). However, this simple model cannot describe other etchants for which R110 R100, as the ratio is limited to the ﬁxed value of R110/R100 2. In fact, the relative rates of any one pair of orientations are ﬁxed by the underlying geometry of crystalline silicon and the given rule of removing every surface atom except TM. The model does not have any free parameter and, as a result, the relative values of the face-speciﬁc etch rates cannot be ﬁtted to the etch rates of a given experiment. As described in Section 10.5.1 of this book, the previous simplistic model actually describes the operation principle of a basic cellular automaton (BCA), which considers that the rate of removal of the atoms is either 1 (for most sites) or 0 (for TM). This method can be used to simulate etching in 30–40 wt% KOH.

24.2.4.2 A Realistic Model of Anisotropic Etching: CCA A more realistic model of etching should consider removal rates that can take any possible value between 1 and 0. The larger values will lead to more frequent removals, while the smaller values will characterize stable sites such as TM. In the same way as the expressions for etch rates of the different surfaces can be written exactly for the BCA model, similar expressions can be derived for the present method. In this case, however, the expressions are more complicated, as they incorporate not only the geometry (through the numerical coefﬁcients and parameter a) but also the relative kinetics—that is, the actual removal rates of the atoms— differing from 1 and 0 in general. Some examples of the face-speciﬁc etch rates obtained in such a model are (see Section 10.5.1 for details) R100 ( a / 4)rD , R110 ( a /(2 2 )) rM , R111 ( a / 3 ) rT rL(T) , R311 a / 11 (rH (rT rV ))/(rH rT rV rA ), 2 R331 a / 19 ((rT rETM )(rM rL(ETM ) ) rM )/ (rT rETM rL(ETM ) rM ), … (24.2) where rX is the removal rate of atom X and the following notation has been used: T TM, M SM, D TD, H horizontal SD, V vertical SD, ETM terrace site at the upper edge of an SM step, L(T) lolly site appearing after removing the T atoms, L(ETM) lolly site appearing after removing the ETM atoms, A another 381

PA R T I V

Micromachining Technologies in MEMS

monohydride site. Note that when the removal rate is 1 for all atoms except TM, which gets 0 (i.e., rM rD rH rV rA rETM rL(T) rL(ETM) 1 and rT 0), the equations become identical to the face-speciﬁc etch rates of the simplistic model. Thus, the current model generalizes the previous simplistic model. As described in Section 10.5.1, this generalized model corresponds to a continuous cellular automaton (CCA) that can be used to simulate etching in a wide variety of etchants and conditions. The model contains various tunable parameters (namely, the atomistic etch rates rM, rD, rT, etc.) and, as a result, the relative values of the face-speciﬁc etch rates can be ﬁtted to the experimental etch rates of different etchants in different conditions. Technically speaking, instead of removing all the surface atoms simultaneously at every time step (except for the TM sites), the advancement of the surface in this model consists of simultaneously decreasing the occupation of every surface site by an amount equal to the current removal rate of the occupying atom—which can change as the neighborhood changes—multiplied by the time step. When the occupation reaches a value of zero, the atoms are removed. For stepped surfaces, this provides an average surface propagation mode consisting of the gradual removal of entire atom rows located at the steps, accompanied by a slower continuous “erosion” of the terrace regions.

24.2.4.3 Orientation Dependence of the Etch Rate Figure 24.4a presents the etch rate dependence on orientation according to the BCA and CCA models described previously, comparing them to an experiment. As can be seen, BCA agrees qualitatively with this particular experiment, describing the global and local minima and maxima at {111}, {110}, {100}, and {311}, respectively. CCA reproduces not only qualitatively but also quantitatively all the features of the etch-rate anisotropy, including the discontinuity in the etch rate at {551}, which is due to a change in the step-ﬂow character of etching when passing from the {h 2 h 2 h} surface family to the {h h 1} family. The improved agreement is also demonstrated in Figures 24.4b–d, which show the etch-rate diagram that results from etching a spherical specimen according to the BCA and CCA models as compared with a similar experiment. Figures 24.4e–h serve as typical examples of the etch rate anisotropy in low and high concentration of a typical etchant (KOH), showing also the changes in the anisotropy due to the addition of a typical alcohol to the solution (IPA; see Sections 24.4 and 24.8). The ﬁgure shows that the orientation dependence can be described well by the CCA model in all cases. Conceptually this means that the particular anisotropy of many etchants can be explained as being the result of a particular combination of values 382

for a reduced set of site-speciﬁc removal rates. The BCA model corresponds to a particular choice of those rates (1 for all sites, except for TM, which gets 0), and thus it may describe (even quantitatively) the anisotropy of some particular etchant. However, in general it cannot explain the orientation dependence of many other etchants, such as the examples shown in Figures 24.4e, g, and h.

24.2.4.4 Other Models The previous models describe anisotropic etching as a sequence of collective removals where in each time step either (i) all current surface atoms are removed simultaneously—except for the TM atoms—(limited BCA model), or (ii) the occupation of all the atoms is reduced and a collective removal of the resulting zerooccupation atoms is performed (versatile CCA model). Anisotropic etching can also be modeled as a pure sequence of single atom removals, based on visiting stochastically the atoms with higher removal rates more often. This can be done by using the Kinetic Monte Carlo (KMC) method, as described in Section 10.5.2. However, the derivation of similar face-speciﬁc etch rates as a function of the atom-speciﬁc removal rates—as done for the CCA method—remains an open question for the KMC method. The different features of the CA and KMC models are compared in Section 10.5, of this book. In an alternative simpliﬁed vector model by Wind and Hines [59] the overall etch rate is expressed as a vector sum in terms of two velocities: R(α) vstep sin(α) vterr cos(α), where α is the angle shown in Figure 24.3c. As compared with the BCA model, this description introduces two free parameters (vstep and vterr), and as a result, it can describe the different experiments better. In practice, a larger number of parameters can be used as different steps, and terrace velocities can be considered to represent the etch rate in the different regions (e.g., the {h 2 h 2 h}, {h 2 h h}, and other families of planes). As shown in Figure 24.4e–h, this model can differ signiﬁcantly from the experiment, especially at the regions where the etch rate displays sharp discontinuities. In a sense, this model stands between the BCA and CCA models. In principle, anisotropic etching can also be modeled by the phase ﬁeld and level set methods (see Section 10.3 of this book). As in the case of KMC, these methods provide advanced, ﬂexible, and versatile simulation tools, and they cannot be categorized as simpliﬁed, analytically solvable models.

24.3 Beyond Atomistics: Electrochemistry The removal of the surface atoms during wet etching of silicon is a complex process that involves both chemical

(551)

140

CHAPTER 24

(F) 80

(e) 80 BCA CCA Exp

(b) Etch rate in 50% KOH

(a) Etch rate in 12% KOH 70

70

60

60

120 100

(111)

80 60

(110)

(311)

40

(100)

20 0 0

20

40 60 Angle, degrees BCA

80

Etch rate (micro/h)

(a)

KOH 50 w/v 90°C

180 160

Etch rate (micro/h)

Etch rate, microns per hour

Wet Etching of Silicon

50 40 30 20

(b)

40 30 20

Experiment data Step flow based CA Vector model

10

50

Experiment data Step flow based CA Vector model

10

0

0 0

20

40

60

80 100 120 140 160 180

0

20

40

60

Angle (degrees)

(h)

(g) 80 CCA

(c) Etch rate in 12% KOH/IPA

Etch rate

{100}

(d)

Experiment data Step flow based CA Vector model

50 54.73

40

(100)

(111)

(111)

(110)

30

{111}

50 40 30

20

20

10

10

Experiment data Step flow based CA Vector model

0

0 {110}

(d) Etch rate in 50% KOH/IPA

60

Etch rate (micro/h)

max

Etch rate (micro/h)

60

Experiment

80 70

70

(c)

80 100 120 140 160 180

Angle (degrees)

0

20

40

60

80 100 120 140 160 180

Angle (degrees)

0

20

40

60

80 100 120 140 160 180

Angle (degrees)

min

Fig 24.4 ● (a) Comparison of the etch rate dependence on orientation for an experiment (37 wt% KOH at 90°C), and the BCA and CCA models. (b–d) Stereographic projection of the etch rate from a spherical specimen: (b–c) BCA and CCA models (30 wt% KOH at 70°C), (d) experiment (34 wt% KOH at 70°C). (e–h) Etch rate dependence on orientation for the CCA model and several experiments [76]: (e) 11 wt% KOH, (f) 37 wt% KOH, (g) 11 wt% KOH/IPA, and (h) 37 wt% KOH/IPA at 70°C.

and electrochemical reactions [27, 28]. The latter involve the participation of free-charge carriers, giving rise to measurable currents and allowing for the possibility that the etching process will be affected with an external voltage [47–51]. As shown in Figure 24.5, wet etching takes place through sequential oxidation and etching reactions. The chemical (Figure 24.5a) and electrochemical (Figure 24.5b) reaction routes provide two alternative mechanisms for the oxidation of the hydrogenterminated silicon atoms before the actual removal (etching) of the resulting hydroxyl-terminated silicon atoms (Figure 24.5c). The oxidation step is the ratelimiting process and, as a result, the surface of silicon is predominantly H-terminated during wet etching [16, 26]. Once H has been replaced by OH, a fast sequence of chemical steps—represented as “etching” in Figure 24.5c—leads to the removal of the silicon atom, as a Si(OH)4 product. The triggering effect due to the OH ligand is attributed to the difference in electronegativity

between Si and O, resulting in the polarization and weakening of the backbonds. The overall chemical reaction is ≡ Si H H2O OH →≡ Si OH (oxidation )

H 2 OH (≡ Si)3 Si OH 3H2O → 3( ≡ Si H) (etching )

Si(OH)4 Although the hydroxyl group OH– plays an important role as a catalyst spectator in the substitution of H by OH in the oxidation step and as a backbond weakening agent in the etching step, the active species is actually a polar molecule, typically H2O in the alkaline solutions, or HF in a solution containing ﬂuoric acid. After the etching step, the Si(OH)4 product diffuses to the solution bulk, where the high pH environment decomposes it into a silicate 383

PA R T I V

Micromachining Technologies in MEMS

Chemical oxidation

a

transition state

Slow Bulk

Solution

Bulk

Solution

H-terminated

c

Etching

Bulk Solution

OH-terminated + 3H2O Electrochemical oxidation

b

Fast Bulk

Bulk

OH-terminated

H-terminated

slow Bulk

Solution

H-terminated

Bulk

Solution

Dissociation and H2O attack

Bulk Solution + 2eCB

OH-terminated

Silicon Oxygen Hydrogen

Fig 24.5 ● Cartoon-like description of the sequential oxidation and etching reactions during etching. Only the nearest bulk atoms in the neighborhood of the surface site are depicted.

SiO2(OH)22– and two protons 2H [2]. The protons can further recombine with hydroxyls to form water. Similar reactions can be written for dihydride and trihydride terminated atoms having two and one backbond(s), respectively. In agreement with the experiments, the previous reactions are independent of the source of hydroxide ions—be it KOH, NaOH, TMAH, etc.—simultaneously explaining the formation of hydrogen bubbles and the H-termination. In addition, the site dependence or anisotropy is qualitatively explained. Since it is necessary to have both a water molecule and a hydroxyl ion in the proximity of the substituted H, the number of H terminations and the amount of empty space around them are important factors that determine the reactivity, being larger for the sites with more H terminations and increased exposure to the etchant or, equivalently, a smaller atom coordination and a larger number of surface neighbors (see Section 24.2.4). For an equal number of H-terminations, the least steric hindrance wins. Being the rate-limiting process, the site dependence of the rate of oxidation explains the anisotropy of the whole reaction. The overall electrochemical reaction differs in the oxidation step only, which is: ≡ Si H H2O → Si OH 2H 2e (electrochemical oxidation ) As before, the water molecule is the active species, reacting directly with a dangling electron that results from a random thermal dissociation of Si–H. The reaction with the water molecule produces two electrons in the conduction band (CB). An anodic potential applied by the use of an external voltage source and a counter electrode is considered to drive the ﬁrst dangling electron away from the surface state to the CB, favoring 384

attack by H2O and speeding up wet etching. Since the dissociation leaves enough space for the reaction with water—which involves one molecule, instead of two for chemical oxidation—and dissociation may occur at any site, the electrochemical oxidation step is rather unselective and, thus, isotropic (albeit involving a higher activation energy due to double electron injection). As a result, the amount of anisotropy depends on the relative participation of the two oxidations and can be modiﬁed with an applied potential. For further details see Refs [2, 28, 63, 67].

24.4 Typical Surface Morphologies (I. Zubel and M.A. Gosálvez) This section provides an overview of the typical surface morphologies that can be observed during/after wet etching on different surface orientations. Although the precise origin of most morphologic features is still under debate, we have tried to offer a uniﬁed explanation of the mechanisms that may be responsible. The presented morphologies have been collected into two ﬁgures, namely, Figure 24.6 and Figure 24.7, with some additional cases being presented in Figure 24.2. Although other cumbersome morphologies can be found in particular experiments, most cases can be related to one of the morphologies presented here. In this sense, we present and discuss what could be referred to as the standard surface morphologies.

24.4.1 Si{111} The etched Si{111} surface is typically very smooth. As described in Figure 24.6, at low concentration the surface

Wet Etching of Silicon (a)

(b)

High concentration

<112> <121>

<111>

<112>

<211> <110>

<211>

<121>

<121>

<211> <121>

<112>

<211>

<112>

Low concentration

<112>

: Step-monohydrides (SM, [112] family) (c)

CHAPTER 24

(d)

: Step-dihydrides (SD, [112] family)

50 nm

50 nm

(e)

(g)

(f)

Fig 24.6 ● Etch pits on {111}. (a–b) Schematics of the SM and SD steps available on Si{111}. (c–e) Top view of etch pits (simulated). (f–g) Examples of experimental etch pits, obtained in 10 and 25 wt% TMAH, respectively. (x50 and x10 magniﬁcation, respectively.)

shows triangular pits, with the three sides aligned to the three possible SM steps appearing on {111}. The perimeter of the pit is made of SM steps. At high concentration triangular pits are also observed, in this case with the sides aligned to the three possible SD steps on {111}. The pit perimeter contains SD steps. The triangular pits look as if they are rotated 60° when the low and high concentration shapes are compared. At medium concentration the pits are hexagonal, having three SM sides and three SD sides. The hexagonal pits suffer a gradual change in shape as the concentration is decreased, shortening the length of the three SD sides while increasing the length of the three SM steps, eventually becoming the SM-only delimited triangles at low concentration. Similarly, the hexagonal pits become gradually the highconcentration SD-only delimited triangular pits by shrinking the three SM sides and expanding the other three SD sides as the concentration is increased. These changes in the pit shapes can be easily explained by assuming that the SD sites are more reactive than the SM sites at low concentration and that the relative reactivity of the two sites is gradually reversed as the concentration is increased, becoming equal at medium concentration and fully reversed at high concentration. Instead of the concentration, a gradually increasing external bias potential can also be used to drive a similar transformation [51]. The {111} etch pits can be rather deep in the experiments; as shown in Figure 24.6g, they look like inverted

pyramids. This depth is typically related to the thermal history of the crystal and is due to the presence of bulk microdefects such as oxygen interstitial precipitates and/or dislocations, which act as pit nucleation centers (Section 24.5). The dislocations lie perpendicular to the {111} surface, enabling pit nucleation to occur layer after layer along the same dislocation, hence generating the tips of the inverted pyramids. The explanation for the pit boundary shape is as described before.

24.4.2 Si{100} At low KOH concentration the most characteristic feature of Si{100} is the formation of pyramidal hillocks, as shown in Figure 24.7m for 5 M KOH. At low magniﬁcation the hillocks appear as regular pentahedra composed of four lateral {111} crystallographic planes lying on a {100} base (see Figure 24.2c). Viewed closely, the hillocks reveal more complicated features, such as a multiple apex (distributed between many points) and rough edges and facets having steps, pits, and other defects. Depending on the particular conditions, the hillocks may completely cover the surface. When the KOH concentration is increased, the hillocks are removed, improving the roughness, as shown in Figure 24.7n for 10 M KOH. Also, the addition of IPA to the solution signiﬁcantly improves the roughness, even at low concentration, as shown in Figure 24.7o. Although alcohol addition 385

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KOH + IPA

KOH + Tertbutanol

(a)

[10 M KOH] (b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

(j)

(k)

(l)

(m)

(n)

Masked mesa structure (p)

(o)

(100)

(100)

(311)

(311)

(331)

(331)

(110)

(110)

5 M KOH

(q)

5 M KOH

10 M KOH

KOH + IPA

KOH + Tertbutanol

Fig 24.7 ● Examples of typical surface morphologies for {110}, {331}, {311}, and {100} in KOH at low (5 M) and high (10 M) concentration, and in KOH with IPA/tertbutanol.

generally results in smoother surfaces than in pure 10 M KOH, the obtained morphology is not fully deprived of the hillocks and a small number of stable pyramids persist. The density of “persisting” hillocks increases with the length of the carbon chain of the added alcohol, as shown in Figures 24.7o, p. In general, the formation of hillocks on an etched surface requires four simultaneous conditions, as indicated in Figure 24.2c [18]: (1) the existence of a micromasking agent that stabilizes the apex atom/s; (2) fast downward motion of the ﬂoor surface; (3) stable side edges; and (4) very stable lateral facets. The micromasking agent can be a (partially) insoluble reaction product (such as a silicate), an etchant impurity (such as Cu or Pb), or an etchant inhomogeneity (such as a hydrogen bubble, which is an example of a completely depleted etchant region). The etchant inhomogeneities refer in general to the formation 386

of inhomogeneous patterns in the etchant concentration and/or temperature in the close vicinity of the surface, and are typically formed due to the slow transport of the reactants and/or products, which cannot immediately follow the removal activity of the atoms at the surface (see Section 24.2.3). Concerning the pyramidal hillocks on {100}, it is believed that the previous three agents— especially the H2 bubbles—can act as micromasks for the hillocks. Considering that the SD and TD sites are more reactive than the SM sites at low concentration and that the relative reactivity is reversed at high concentration, as described in Section 24.4.1, the four conditions for hillock formation are fulﬁlled at low concentration: The TD atoms at the ﬂoor surface are removed fast, producing signiﬁcant amounts of hydrogen bubbles that can act as micromasks; the TM atoms at the four lateral facets are very stable; and

Wet Etching of Silicon

the SM atoms at the four side edges are removed quickly compared with TM but slowly compared with TD. On the other hand, at high concentration the removal of the TD atoms becomes slower than that of SM atoms—thus, conditions (2) and (3) are not fulﬁlled—and the hillocks cannot be formed even if micromasking takes place. The addition of alcohols at low concentration effectively removes the micromasking by the hydrogen bubbles—thus, condition (1) is not fulﬁlled—and the hillocks cannot be formed. This effect is due to the tensioactive character of the alcohols, which effectively reduces the hydrogen bubble lifetime by modifying the wettability of the etchant/surface interface. However, a small fraction of the added alcohol molecules act as micromask precursors or become micromasks themselves by blocking some SM sites generated during etching (see Section 24.8.4). This explains the persistence of a small number of very stable pyramids. Similar effects apply also for other tensioactive additives such as surfactants. At high concentration, the hillocks are absent and the etched Si{100} surface is characterized by the formation of shallow round pits, as exempliﬁed in Figure 24.7q for 45 wt% KOH at 80°C. The pits appear also at low concentration as very shallow features between the pyramidal hillocks. Although the origin of these pits is still debated, they probably result from the formation of ring-like etchant inhomogeneities due to the rate of mismatch between (i) the removal of the surface atoms at the stepped perimeter of initially square-shaped pits—progressively reshaped during etching to become circular—and (ii) the diffusion transport of the reactants and/or reaction products [18]. Their formation can be intensiﬁed by the existence of bulk microdefects, as shown in Figure 24.8e (Section 24.5).

24.4.3 Si{110} The Si{110} surface etched in low-concentration KOH displays a typical V-groove pattern, as shown in Figure 24.7a and its insert, often described in the literature as a zigzag structure due to the shape of the cross-section or as a columnar structure due to the elongated nature. At ﬁrst look, each V-groove results from the development of two {111} planes inclined 35.26° with respect to the wafer surface. However, the two planes appear frequently as stepped {111} surfaces, with a smaller inclination angle towards the wafer surface, depending on the particular etching conditions. Increasing the concentration removes the zigzag pattern, but the surface is still rough, as shown in Figure 24.7b and considered in the last paragraph of this section. The addition of alcohol to the etchant signiﬁcantly improves the roughness,

CHAPTER 24

as shown in Figures 24.7c, d. Similarly, the addition of other surfactants in KOH also has a positive effect, although the roughness improvement is not as dramatic. According to the crystallographic geometry of {110}, the SM atoms form long parallel chains that can be viewed as steps and can deﬁne the longitudinal axis of the V-groove structures. The zigzags are probably the result of the formation of elongated etchant inhomogeneities due to the removal activity at the SM steps and the slow transport of the reactants/products [18]. The inhomogeneities accelerate or decelerate some steps and eventually produce step bunches similar to those found in stepped {111} surfaces (see Sections 24.4.4 and 24.4.5). The alcohols selectively block the etching of the SM atoms, slowing down their removal. This provides extra time for the diffusion processes to take place, thus damping the formation of the inhomogeneities. As a result, the overall etch rate is slower and the morphology is smoother when the alcohols or surfactants are added. At high concentration Si{110} can exhibit trapezoidal hillocks, as shown in Figure 24.2d. These hillocks are different from the ones observed on {100} at low concentration, with facets made of {h 2 h h} surfaces (instead of {111}), such as {311}, with the particular orientation depending on the experimental conditions. As the names indicate, the base of the {100}-hillocks is a square, whereas it is a trapezoid for the {110}-hillocks. The formation of the trapezoidal hillocks on {110} requires the same four general conditions as for pyramidal hillocks on {100} [18, 42] (Section 24.4.2). Contrary to {100}, for {110} the conditions are fulﬁlled at high concentration and not at low concentration, explaining the experimental observations. In particular, at high concentration micromasking by H2 bubbles (condition (1)) is likely to occur given the large activity of the {110} ﬂoor surface – where the SM atoms are being removed fast (con. (2)). In addition the SD atoms at the side edges are quite stable (con. (3)), and the combination of SD and TM atoms at the {311} lateral facets results in very stable surfaces (con. (4)).

24.4.4 Misoriented {111} Towards {110}: {hⴙ2 hⴙ2 h} and {h h 1} Families At low concentration the surface morphology of {331}, {221}, and other similar stepped {111} surfaces is characterized by the formation of rather straight steps, as shown in Figure 24.7e. On the other hand, at high concentration many steps can be delineated by zigzag lines, resembling a sequence of side-by-side triangles, as shown in Figure 24.7f and its insert. We refer to these as triangular steps (also, polygonal steps). The addition of alcohols (or surfactants) to the solution signiﬁcantly reduces the roughness, similar to the case of {110}, as shown in Figures 24.7g, h. 387

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These surface morphologies are well understood, as they simply reﬂect the change in the reactivity of the SM and SD sites as the concentration is increased. At low concentration the SM sites are less reactive than SD and remain at the crystallographic steps of the {h 2 h 2 h} and {h h 1} surfaces, explaining the straight steps. However, at high concentration the SM sites become more reactive and their removal leads to the appearance of the more stable SD steps, thus explaining the triangular steps. This is identical to the transformation of the hexagonal and triangular pits with concentration described in Section 24.4.1. Note that at low concentration the straight steps on {h 2 h 2 h} and {h h 1} correspond to the formation of the V-groove structures on {110}, while at high concentration the triangular steps on {h 2 h 2 h} and {h h 1} correspond to the trapezoidal hillocks on {110}. As for {110}, the alcohols and surfactants block many SM sites, slowing down the etch rate of these surfaces and damping the formation of etchant inhomogeneities, thus resulting in a smoother morphology. Generally, it can be stated that the alcohols and surfactants reduce the etching rates and improve the morphology of the planes containing SM sites. It is typical in the experiments to see steps whose height is several hundreds of nanometers, as in Figures. 24.7e, f. These “macrosteps” contain hundreds of one-layerhigh atomistic steps, all bunched together into a single step. These step bunches are believed to be a consequence of the formation of etchant inhomogeneities, similarly as for the zigzag structures on {110} and the shallow round pits on {100} [18, 65]. An initial ﬂuctuation in the step velocity slows down a step, which is then caught by the step running behind it. The step pair consumes locally more reactants and/or produces more reaction products, thus amplifying the reactant depletion (or product buildup) of the local inhomogeneity. As a result the pair runs more slowly and is caught by a third step. This ampliﬁes again the local inhomogeneity and slows down the group further, making possible the incorporation of additional steps and thus yielding a step bunch. Due to similar step velocity ﬂuctuations in other regions of the same surface other step bunches are formed, resulting in a macro-stepped surface characterized by a particular distribution of the step heights. A similar morphology is obtained if the ampliﬁed inhomogeneities speed up the steps instead of slowing them down [18, 65].

24.4.5 Misoriented {111} Towards {100}: {h 2 h h} and {h 1 1} Families The {h 2 h h} surfaces such as {755}, {533}, and {211} are rough after etching in KOH. However, the {h 1 1} surfaces—starting with {311}—are smooth, although at 388

high magniﬁcation some submicron convex features can be recognized (see Figures 24.7i, j). In the solutions containing surfactants or alcohols, the roughness of all these substrates undergoes radical worsening, with bulky hillocks being observed, as demonstrated in Figures 24.7k, l. The shapes of the hillocks are analogous to the shapes of mesa structures etched on these substrates through oxide masks, as shown in the insert of Figures 24.7k. However, the additives do not affect signiﬁcantly the etch rates of these planes, mildly reducing them only. In addition to the comparison with the morphology of the limiting {111} and {100} surfaces, the roughness of {h 2 h h} and {h 1 1} is understood by considering the relative reactivity of the SM and SD sites, similarly as for {h 2 h 2 h} and {h h 1} in Section 24.4.4. At low concentration, SD is more reactive and SM is more stable, resulting in a modiﬁcation of the straight crystallographic steps (containing SD sites) into triangular steps containing the SM sites. This corresponds to the formation of pyramidal hillocks on {100}. At high concentration, the reactivities are reversed, resulting in SD steps that appear straight on {h 2 h h} and {h 1 1}. This corresponds to the formation of shallow round pits on {100}. As for the {h 2 h 2 h} and {h h 1} stepped surfaces, step bunches can also be formed in {h 2 h h} and {h 1 1} due to the amplifying effect of the etchant inhomogeneities on the step velocities. As for {100}, the alcohols act as precursors for numerous micromasks or act themselves as micromasks, impeding locally the etching process on the planes containing SD sites. This is due to the blocking effect by the additives on SM sites generated during etching (see Section 24.8.4). The difference with respect to {100}—which develops fewer hillocks after alcohol addition—suggests that the formation of SM sites occurs more strongly on the vicinal {100} surfaces.

24.5 Effects from Silicon Wafer Features (E. Viinikka) The silicon wafer plays a key role for the successful realization of anisotropic wet chemical etching. All the four typical items used to characterize a silicon wafer affect the etching result: (1) orientation issues, (2) wafer dimensions, (3) surface quality, and (4) bulk features. For MEMS applications the most typical silicon orientation processed by wet chemical etching is Si{100}. Anisotropic etching of this surface utilizes the considerably smaller etch rate of the {111} crystal plane. When adequate wafer material and etching conditions are used, etching reveals perfectly smooth {111} sidewalls at an angle of 54.7° with the {100} wafer surface, as described in Section 24.1. In addition to the different etch rates, the electrochemical nature of these planes is different: {100} is electrochemically less noble, acting

Wet Etching of Silicon

as a sacriﬁcial electrode and protecting the exposed {111} surface [27, 28, 77, 78]. In addition to Si{100} wafers, {110}-oriented wafers can be utilized to create vertical {111} sidewalls with wet etching [79]. However, the Si{110} material is typically more expensive than Si{100}. Other orientations are neither used nor available in large numbers. The orientation dependence of wet etching is discussed in Sections 24.2.4 and 24.3. The role of the primary ﬂat orientation accuracy is of fundamental importance for wet etching. As the mask openings are routinely aligned with the primary ﬂat, the accuracy of the ﬂat orientation affects the result of etching. Poor orientation results in irregularities in the geometry and/or sidewalls of the etched cavities, as shown in Figure 24.2e, f. In problem debugging the orientation mismatch is relatively easily recognized, as shown in Figure 24.8a. As a wafer speciﬁcation, a ﬂat orientation accuracy of 0.2° typically ﬁts demanding wet etching processes (see Ch. 5), however 0.1° is also available [80]. For comparison, the standard speciﬁcation for the primary ﬂat orientation accuracy in microelectronics wafers is only 0.5°. The wafer shape and its variation may affect directly the feature distribution of the ﬁnal MEMS product. For example, a large TTV (total thickness variation) may lead to a corresponding variation of cantilever or membrane thicknesses in the ﬁnal product when time-controlled etching is used (see Section 24.1.2). TTV 1 μm typically ﬁts demanding processes [80]. Cleanliness of the wafer surface assures problemfree annealing. As an example, metal contamination, easily diffused in the bulk during thermal treatments,

CHAPTER 24

induces and ampliﬁes defect formation [81, 82]. This in turn results in irregularities of the etched patterns and their {111} planes. However, the surface metal levels typically speciﬁed by the IC industry (e.g., Fe 1010 atoms/cm2) ﬁt the MEMS requirements as well. Surface roughness is to be taken into account especially in the context of wafer level encapsulation and the selected bonding technique. For example, successful fusion bonding demands 1 nm roughness and very clean surfaces [83, 84], whereas glass frit bonding and eutectic bonding have been reported to tolerate even 2 μm topography [83, 84]. In practice, a wet etching and glass-frit-bonding-based process may tolerate considerably higher surface roughness. Furthermore, even if the surface is as rough as the etched backside of a single-side polished wafer, the bonded interface quality can be controlled to some extent by IR, for instance in SOI quality check [80]. Furthermore, even if the surface is as rough as the etched backside of a single-side polished-wafer, the bonded interface quality can be controlled by IR [80]. In addition to roughness, glass frit and eutectic bonding techniques are more tolerant towards particles [83, 84]. The wafer bulk affects not only the processing but also the quality of the etched surfaces. Firstly, the etch rate is bound with bulk resistivity. Seidel et al. have shown that the etch rate remains relatively constant until a certain resistivity level is reached, decreasing then abruptly and steeply with resistivity [23]. For Si{100} and 60°C KOH, this transition occurred at around a boron concentration of 1019 atoms/cm³, that is, around 0.01 ohm-cm. Thus, when going down to the mOhm cm level, the slow etch rate starts to affect the process

Fig 24.8 ● (a) Misalignment between etched cavity and mask opening. (Intentional mismatch, SEM image). (b–c) Micrographs of Si{100} wafer cross-sections revealing no bulk crystal defects (b), and Oi precipitates and OISFs or dislocation loops in the bulk (c). 2 μm was removed by Wright etchant to reveal the crystal defects. (d–e) Micrographs of {111} etched groove sidewall and {100} bottom surface showing triangular and round pits, respectively.

389

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capacity, which should be taken into account when one is designing the process. On the other hand, this feature can also be applied on purpose, by using either implanted or epitaxially grown etch stop layers (for epi wafers, see Chapter 5). There are certain beneﬁts in using a borongermanium co-doped stress-free Epi etch stop layer when compared with n/p structures (where the wafer and the epi layer are of different types). Primarily, there is no need for electrochemical etching, thus avoiding the use of clamps, which saves wafer area. In addition, there are no problems due to uneven etching, originating from local leakage. Although the use of large dopant amounts in epitaxial reactors is generally avoided in microfabrication facilities due to contamination hazard for other epitaxies, epi wafers from dedicated reactors are currently a possibility offered by some wafer suppliers. Oxygen content is probably the most important wafer speciﬁcation detail when the etched surface quality is considered. In Cz silicon there is always some interstitial oxygen (Oi), as described in detail in Chapters 1 and 2 of this book. In the semiconductor industry relatively high oxygen content is desired to generate oxygen precipitates, in order to obtain reasonable internal gettering of undesired impurities [81, 85]. However, the Oi precipitates and related crystal defects—like oxygen-induced stacking faults (OISFs) and dislocation loops—cause problems in anisotropic etching, as the bulk defects affect the local etch rate. The variation in etch rates results in rough {111} side walls and underetching, and thus inaccuracies in the etched cavity dimensions [86, 87], as shown in Figures 24.8c–e. It is possible to cope with this problem by using Oi levels typical for IC wafers and designing a “high-lowhigh” thermal treatment forming a uniform distribution of very small precipitates in the wafer bulk. This results in rough surfaces, but underetching is relatively predictable [80]. However, the easiest approach is just to use wafers with Oi level designed for MEMS applications. Oi levels of 10–14 ppma (new ASTM—83) ﬁt most of the applications, but 10 ppma is sometimes needed to obtain ultimate smoothness and accurate shape for the etched cavity [80]. However, it is possible to obtain OISF-originated irregularities with a heavy temperature treatment even if very low Oi level material is used. Thus in sensitive applications the annealing steps should be carefully considered. Some roughness is typically observed on the {100} plane of the etched cavities. Although the pits have been related to bulk micro defects [88], some studies reveal that the effect of the etching process is more pronounced than that of the initial Oi level [87]. The large round shapes on the etched {100} plane have also been explained as the result of bubble formation in the etching process, and various ways have been employed to totally or partially eliminate the bubbles, in order to obtain 390

smoother surfaces [50, 54, 55]. (See Section 24.8.4 for a description of the use of alcohol and surfactant additives as a solution to the problem.) In addition to these, the roughness and related structures could be connected with inherent diffusion-related ﬂuctuations in the composition of the etchant [18], as discussed in Sections 24.4 and 24.8.4. Thus, even though a low Oi level has sometimes been observed to decrease the number of large, round shapes on the bottom of the etched cavities (see Figure 24.8e) [80], there are other factors affecting the etched {100} surface quality as well. In addition to the bare Oi level, the tendency of the wafer bulk to develop micro defects is connected to carbon content [89] and bulk metal content, as well as to the crystal growth details. Thus the most sensitive applications may demand a carefully tailored MEMS silicon crystal.

24.6 Convex Corner Undercutting The use of wet etching for the micromachining of a typical released accelerometer mass involves the emergence of convex corners, where considerable undercutting is typically observed, as depicted in Figure 24.9a. At the atomistic scale, the convex corners expose low coordination atoms with high removal rates, thus inducing the emergence of fast etching planes as the sloping facets or bevels [67]. These facets are typically {311} or {221}, as indicated in the ﬁgure, but other {hkl} planes are possible, such as {331} or {411}. The amount of underetching and the particular orientation of the facets depend on the choice of etchant, concentration, temperature, and etch time. Although undercutting is extensively used for the fabrication of suspended structures such as cantilever beams, preferably it is avoided for the fabrication of mesa structures and proof masses as it results in poor control of the shape and size of the microstructures. The fast etching planes appearing at the convex corners are actually saddle points of the etch rate [90]. This means that the observed planes (e.g., {311}) are the orientations with maximum etch rate of all planes in the [001] crystallographic zone but with minimum etch rate of all planes in the [310] crystallographic zone. The saddle maximum determines angle α, while angle φ results from the saddle minimum. The formation of “footings” (or faceted structures observed in some experiments next to the etched ﬂoor) and their disappearance after additional etching is related to the difference in the etch rates of {311} and {110}. When the etch rates are similar and R110 R311, the footings appear initially but disappear gradually as etching continues, since the two orientations propagate with similar but different rates. In

Wet Etching of Silicon

Ideal convex corner

CHAPTER 24

Top view SiO2

α

l

Undercutting

> 00 <1 <110>

SiO2 {11

}

1}

α φ

} {311r o } {221

11

54

{1

.74

H

{100}

Si

(a)

Undercutting at convex corner

(b)

Fig 24.9 ● (a) Undercutting at a convex corner in wet anisotropic etching. (b) Some mask compensation designs to avoid undercutting.

this discussion the aforementioned {311} can be substituted by {221}, {331}, or other orientations, depending on the particular conditions. The search for a compensation method to avoid underetching seems as old as bulk micromachining itself. Most typically, a mask compensation pattern is added to the mask design around the target corner to slow down etching locally, retaining the desired sharp edges at the target corner by underetching the compensation pattern. Dozens of different patterns with varying complexity have been suggested [91], a few of which are shown in Figure 24.9b. The square, triangle, 110beam (typically L-shaped) and 100 -diagonal are the basic structures from which other shapes are derived. Given an etchant, the analysis and accurate design of these compensating geometries require the experimental measurement of (i) the angle φ between the beveling planes and the wafer surface, (ii) the angle α between the mask edge and the beveling planes, and (iii) the undercutting ratio I/H. For design purposes, the dimensions of the different compensating structures can be expressed as a function of the etch depth H [91]. In most cases, the use of compensation patterns leads to satisfactory results. The basic problem associated with the compensation designs is the large amount of additional space required for their incorporation, discouraging their use for the fabrication of chip isolation grooves and/or 90° bent V-grooves where less space is available than is required for the compensating structures. This is one of the reasons that dry etching has gained popularity, as it removes completely the need to use any compensation patterns. Nevertheless, the search for new anisotropic etchants has improved the situation [91].

24.7 Examples of Wet Etching This section presents typical examples of anisotropic etching, showing how it can be used alone and in combination with other processing techniques. A rather unusual example combining many micromachining processes is considered in more detail due to its pedagogical value. A thorough review of the hundreds of different structures that can be micromachined by involving wet etching is out of the scope of the present book.

24.7.1 Single Mask, Single Etch As shown in Figure 24.1, anisotropic etching can be used to produce deep vertical grooves, square diaphragms, V-grooves, and U-grooves on {110} and {100} silicon wafers by the use of a single mask and a single etch. For Si{100}, Figure 24.1b describes the crystallographic orientation of the groove walls, depending on the alignment of the mask and the type of etchant. When the mask pattern is aligned with the 110 direction, {111} walls with vanishing underetching are developed for all etchants. However, when the pattern is aligned with 100, the groove walls are {100} or {110}, depending on which orientation has a smaller etch rate. In both cases, clear underetching occurs. For KOH, the etch rate of {100} is lower, and it appears at the walls at 90° from the wafer surface. For EDP, KOH with added isopropyl alcohol (KOH IPA), and KOH with added NC-200 surfactant (KOH NC200), the walls are made of {110}, 45° off the wafer surface. In contrast to EDP and KOH IPA, KOH NC200 additionally enables the 391

Micromachining Technologies in MEMS

realization of mask-conforming anisotropic etching in a single etch step with a single mask, although restricted to etching depths of about 30–50 μm (Figure 24.1f). A less conventional example of a single etch with a single mask is the micromachining of silicon inserts by using Si{113} wafers for the manufacture of disposable plastic razors [19]. In addition, different types of microneedles can be fabricated in a single etch step by exploiting the occurrence of undercutting for square, round, and rhombic mask patterns [4, 92]. There are, however, more sophisticated methods for higher aspect ratio microneedles, as considered next.

24.7.2 Etching Top and Bottom Sides

24.7.5 Anisotropic Etching with Nitride and Oxide Masks, Local Oxidation, Etch Stop, and Wet Release As an example of a complex micromachining process based on wet etching, we consider here an unconventional procedure to realize a typical seismic mass by an elaborate bundle of micromachining processes designed to protect the convex corners [97]. Since an ideal convex corner on an Si{100} wafer is made by the intersection of two {111} facets (see Figure 24.9a), the idea is to realize one of the facets ﬁrst and to passivate it with oxide for protection during a subsequent anisotropic etch that will reveal the second {111} facet. For simplicity and accuracy, the etch depth is controlled by using an SOI wafer, consisting of a top silicon layer, a buried insulator layer such as silicon oxide, and a bottom handle silicon layer. The process starts by masking the top silicon layer with SiO2 (oxide) and Si3N4 (nitride). The nitride mask leaves two elongated openings, as shown in Figure 24.10a, while the oxide mask lies below the nitride, with the shape (a)

Si Si

Sometimes, vertical etching can be realized by mechanical dicing instead of DRIE etching, and the resulting structures can be further processed and/or tuned by wet anisotropic etching to produce high-aspect ratio microneedle arrays, such as for painless delivery in medical 392

Si

SiO2

Below Si3N4

Si3N4 SiO2

SiO2

Si3N4

Si

SiO2

Insulator

Si

Si

SiO2

Si Insulator

Si Etch insulator

(f)

Si

Si

Si

Si

Released mass

Si Insulator

SiO2

Insulator

Insulator A’

Si

Si

SiO2

Si3N4

Remove SiO2

(e)

A’

Si

(d) Remove Si3N4 and etch

Si3N4

Below Si3N4

Insulator

Insulator

Si

Grow SiO2(LOCOS)

Si

Si3N4

Si3N4 A

Insulator

A

Si

SiO2

Si

Si (c)

Si3N4

Si3N4

Below Si3N4

Insulator

24.7.4 Combination of Mechanical Dicing and Wet Etching

Etch through opening

A’ Si3N4

24.7.3 Combination of Dry and Wet Etching Very often, wet etching is applied for the release of MEMS structures that are shaped using DRIE etching. Sometimes, dry etching is used to assist wet etching. Some examples of typical release applications are the realization of typical surface/bulk micromachined comb-drive resonators on Si{111}, such as the case shown in Figure 24.1e; the micromachining of prismatic beams on Si{001} [30]; and the release of suspended torsional resonators on Si{111} [31]. An example of dry-assisted convex corner protection for wet etching can be found in Ref. [95].

(b)

Grow SiO2; then SiN4

A

Insulator

The complicated 3D accelerometer of Figure 24.2d is obtained by only using wet etching [5]. The system consists of one monolithic accelerometer with three seismic masses sensitive in the three perpendicular directions, suspended by four high-aspect ratio beams. The process simply uses two steps: an initial double-side masked etching and a ﬁnal maskless etching. “Maskless etching” refers to etching bare regions, especially edges and convex corners, or speciﬁc areas containing these features, obtained in a previous etch step using a mask [93]. Most often, maskless etching is typically applied to regions such as cantilever and/or suspension beams for the creation of suspended features. Another example of double-side etching is the machining of thin {111} plates in a Si{100} wafer, using different masks for the top and bottom wafer sides [94].

applications [96]. The fabrication of microneedles using only anisotropic etching is analyzed in Ref. [92].

Insulator

PA R T I V

Removed insulator

Si

Fig 24.10 ● Processing steps for the realization of perfect convex corners on an SOI wafer. In (b) and (c), the nitride layer is transparent and the cross-section A–A is similar to that in (a).

Wet Etching of Silicon

shown in Figure 24.10b, leaving unmasked two larger areas that contain the elongated openings. A ﬁrst anisotropic etch is performed, resulting in two grooves, as shown in Figure 24.10b, displaying the SOI buried insulator at their bottom. The etched grooves are then passivated by local oxidation of silicon (LOCOS), as shown in Figure 24.10c, and the nitride layer is removed. A second anisotropic etch reveals the {111} planes at the non-oxide areas (Figure 24.10d). As a result of the two anisotropic etches, the two {111} facets that shape each convex corner have been formed. By fully removing the oxide layer, the complete mesa structure is revealed, standing on top of the buried insulator layer, as shown in Figure 24.10e. The structure is ﬁnally released by etching away the insulator layer.

CHAPTER 24

and Ta. The etch rate anisotropy ratio is about 35:1 for {100}:{111}. Although EDP was used actively in the 1970s, 1980s, and early 1990s [1, 4], it is toxic, is very corrosive, ages very fast, and is not allowed in areas designated for the fabrication of microelectronics. Hence, alternative etchants such as KOH and TMAH are preferred nowadays.

24.8.2 KOH KOH admits the use of Si3N4, SiO2, Cr, and Au as masks. Although the selectivity is poor between Si and SiO2 (100), it is very good for Si3N4 (1000). KOH is comparatively safe, easy to use, and nontoxic and provides excellent etching proﬁles. It has an etch rate anisotropy ratio of about 160:80:1 for {110}:{100}:{111} at 35 wt% and 70 C°, changing signiﬁcantly for other conditions. Typical concentrations and temperatures are 30–50 wt% and 60–90°C. The presence of an alkali metal (potassium, K ) makes it completely incompatible with MOS and CMOS processing. The molecular weight and speciﬁc gravity of KOH water solutions are considered in Section 24.13. The orientation-dependent etch rate of silicon in KOH has been measured at different concentrations

24.8 Popular Wet Etchants Basic data are provided for the most popular isotropic and anisotropic wet etchants.

24.8.1 EDP EDP is also referred to as EDA (Ethylene DiAmine) [4]. It can be masked by SiO2, Si3N4, Au, Cr, Ag, Cu,

Table 24.1 An incomplete survey of silicon etch rate measurements in KOH, indicating concentration, temperature, and surface orientation

Ref.

[KOH] (wt%)

T (°C)

Main hkl

Zhou 2007 [107]

30,40,50

70

100

110

No

211,311,411,331,210,310, 320,530

50

100

110

111

many, in [110]-zone and [100]zone

Tanaka 2004 [38]

10,15,20,28,32,35,38, 80,100,110,115,120, 100 40,42,45,47,50 125,130,135,140,145

110

No

No

Wind 2002 [105]

5,7.5,11.5,17,25.5,37 30,50,70,90

100

110

111

many, in [110]-zone

Tan 2001 [36]

35

40,50,60,70,85

100

No

111

No

Zubel 2001 [104]

15,23,32,40,54

60,70,80

100

No

No

331

Shikida 2000 [37]

17,25.5,42.5,51

70

100

110

No

210,221,320

34

40,70,80,90

100

110

111

210,211,221,310,311,320, 331,530,540

Sato 1999 [103]

34

70

100

110

111

210,211,221,310,311,320

Sato 1998 [11]

30,40,50

70

100

110

111

210,211,221,310,311,320, 331,530,540

Herr 1992 [102]

10,19,27,34,40

90

100

110

No

211,311,411,221,331,441

Seidel 1990 [2]

10,15,20,25,…,60

20,30,40,…,90,100

100

110

No

No

Nguyen 2006 [106] 23

Other hkl

393

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and temperatures by Price [98], Kendall [99], Palik [100], Seidel [2], Glembocki [101], Herr [102], Sato [11, 103], Shikida [37], Zubel [104], Tan [36], Wind [105], Tanaka [38], Nguyen [106], and Zhou [107], among others. A selection of the more recent and/or (subjectively) inﬂuential measurements is given in Table 24.1, which describes the concentrations, temperatures, and surfaces that were probed. The works by Tanaka, Shikida, and Sato have been compiled into a commercial database (ODETTE) with numerous orientations and many concentrations and temperatures in KOH and TMAH solutions [108]. The data for {100}, {110}, and {111} are freely available within a visualization program [109]. Figure 24.4 in Section 24.2.4 provides several examples of the orientation dependence of the etch rate in KOH. Section 24.9 gives the etch rates in 35 wt% KOH for different temperatures. The experimental and theoretical aspects of the concentration dependence are considered in Section 24.10. The addition of surfactants and alcohols is considered in Sections 24.8.4–24.8.7.

24.8.3 TMAH SiO2, Si3N4, Cr, and Au can be used as masks. With the formula (CH3)4NOH, the TMAH water solutions are regarded as relatively nontoxic, easy to use, and MOS/CMOS compatible. Nevertheless, the cation TMA can cause breathing difﬁculties and damage nerves and muscles after contact with small amounts. TMAH has an etch rate anisotropy ratio of about 70:35:1 for {110}:{100}:{111} at 20 wt% and 80°C. The etch proﬁle strongly depends on concentration, which is typically between 10 and 25 wt%. Typical

temperatures are 60–80°C. Although the etch rate anisotropy is low as compared with KOH, TMAH has nice characteristics, the most outstanding being the high selectivity between Si and SiO2, and the absence of harmful ions for the electrical circuits integrated with the MEMS structures. While etchant circulation and stirring are less signiﬁcant for KOH, etching in TMAH is more sensitive to diffusion effects, especially at low concentrations (e.g., 10 wt%) where the repeatability of the etch rate values is low. The molecular weight and speciﬁc gravity of TMAH are given in Section 24.13. The orientation-dependent etch rate of silicon in TMAH has been measured at different concentrations and temperatures by Tabata [3], Zubel [60], Shikida [37, 110], Chen [111], Cheng [112], Yang [54], and Pal [58], amongst others, as given in Table 24.2. As for KOH, Shikida et al.’s data for {100}, {110}, and {111} are freely available [109], and the etch rates for many other orientations are commercially available [108]. Section 24.9 shows the etch rates in 25 wt% TMAH for different temperatures. The concentration dependence is considered in Section 24.10. The addition of surfactants and alcohols is considered in Sections 24.8.4–24.8.7.

24.8.4 Addition of Alcohols and Surfactants (I. Zubel and M.A. Gosálvez) The etchants are often modiﬁed with different additives as this can improve the roughness of the etched wafer orientation and/or the facets developed during etching. This must be done carefully as the etching anisotropy

Table 24.2 An incomplete survey of silicon etch rate measurements in TMAH, indicating concentration, temperature, and surface orientation

Ref.

[TMAH] (wt%)

T (°C)

Pal 2007 [58]

10,20,25

60

100

No

No

No

Yang 2005 [54]

10

60,70,80,90,100

100

No

No

No

Cheng 2004 [112]

25

60

100

110

111

No

Chen 2001 [111]

2–25

70–90

100

No

No

No

Shikida 2001 [110]

25

70

100

110

111

210,211,221,310,311,320

Shikida 2001 [37]

10,20,25

80

100

110

111

25

70,80,90

100

110

111

210,211,221,310,311,320, 331,530,540 221,320

Zubel 2001 [60]

5,10,15,20,25

70,80

100

110

No

331

Tabata 1992 [3]

5,10,15,22,30,40

60,70,80,90

100

110

111

No

394

Main hkl

Other hkl

Wet Etching of Silicon

also is typically modiﬁed. The additives are usually tensioactive compounds, such as alcohols, or typical surfactants. Generally, at high etchant concentrations these additives reduce the etch rate and improve the morphology of the planes containing SM sites ({h 2 h 2 h} and {h h 1} surfaces exact and vicinal {110}), while they do not affect signiﬁcantly the etch rate of planes with SD sites ({h 2 h h} and {h 1 1} surfaces exact and vicinal {100}), although they cause the development of numerous hillocks on these surfaces. The previous behavior can be explained for both the SM and SD surfaces by considering the following two major features of both (alcohol and surfactant) additives: (A) the preference to block the SM sites, probably due to a particular afﬁnity to be adsorbed at OH-terminated sites, which are more likely on the monohydride steps; and (B) the tensioactive character, effectively reducing the lifetime of H2-bubbles on the surface by modifying the wetting characteristics of the etchant.

CHAPTER 24

Comparison of KOH and TMAH solutions with additives

5M KOH

5M KOH+IPA

25% TMAH

TMAH+TRITON

(110)

(331)

(311)

Fig 24.11 ● Comparison of morphologies obtained in KOH and TMAH with alcohol (IPA) and surfactant (TRITON) additives TRITON refers to Triton X-100 (polyoxyethylene octylphenol). IPA refers to isopropylalcohol. See Fig. 24.12 for more details.

24.8.4.1 Exact and Vicinal {110} The overall etch rate of SM-containing surfaces is reduced due to (A). In turn, this results in less hydrogen evolution—thus reducing micromasking by H2 bubbles— and less etchant inhomogeneities (as fewer removals provide more time for the transport of the reactants and products to reach the active regions)—thus reducing the roughening effects from step bunching. As a result, smoother surface morphologies are obtained. In addition, micromasking by H2 bubbles is further reduced due to (B), improving the roughness even more.

24.8.4.2 Exact and Vicinal {100} Micromasking by H2 bubbles is reduced due to (B), thus improving the morphology. However, SM sites are generated during the etching of these surfaces, sporadically experiencing the onset of some micromasks due to the blocking by the additives (A), thus leading to rougher morphologies (formation of hillocks). The resulting morphology is a competition between the effects from (A) and (B), which, typically, the micromasking mechanism (A) wins. This leads to rough surfaces displaying hillocks. It is important to notice that the blocking of SM sites on exact and vicinal {100} surfaces occurs only on a reduced number of sites, in contrast to the exact and vicinal {110} surfaces where blocking occurs systematically all over the surface and does not lead to hillocks. As examples of the addition of alcohols to KOH, the effects of IPA and tert-butanol on the surface morphology of the different surfaces have been considered in detail in Section 24.4. As shown in Figure 24.11, very similar results are obtained for TMAH itself and for

TMAH with TRITON, which serves as a typical example of a surfactant additive. Comparison of the morphologies from KOH with alcohols and TMAH, with and without surfactants, suggests that the TMA ion plays the role of a surfactant or an alcohol. Addition of TRITON enhances the inﬂuence of TMAH, and {110} and {331} become smoothest when etched in TMAH TRITON.

24.8.5 Addition of Alcohols to KOH and TMAH (I. Zubel) For KOH, alcohols such as propanols, butanols, and pentanols, as well as diols, are used (Figure 24.12a, b). Usually, the alcohols improve the roughness of {100}, especially at low concentration. The solubility of the alcohols in KOH solutions is limited, and usually a saturated solution is needed to improve the roughness. Typically, the lower the KOH concentration, the more alcohol is necessary for a smooth ﬁnish. The addition of the alcohols results in a reduction of the etch rate of {110} and its vicinal orientations, such as {221}, {331}, and {441}, as shown for several alcohols in Figure 24.12b and for IPA (iso-propyl alcohol or isopropanol) in Figure 24.12c. The alcohols with longer carbon chains than the propanols cause a higher reduction, with the strongest reported effect being for tert-butanol. This means that, besides the length of the carbon chain, also the shape of the molecule plays a role in reducing the etch rate. This might be connected with a different solubility of the alcohols in the KOH solutions. For instance, the low solubility of pentanols may explain the absence of an etch rate reduction [113]. 395

Micromachining Technologies in MEMS

PA R T I V

221 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0

KOH

Alcohols H OH H

Rhkl / R100

(a)

H C C C H H H H

(b)

331

441 1. 10M KOH Propanols: 2. 5M KOH+propanol-1 3. 5M KOH+isopropanol Butanols 4. 5M KOH+butanol-1 5. 5M KOH+isobutanol 6. 5M KOH+butanol-2 7. 5M KOH+tert-butanol

1

2

3 4 5 Kind of alcohol

6

10M KOH

H H H H H

5M KOH + IPA

2.5

(100)

(311)

0.5

H H H H H

(211)

1

(111)

H H H

(331)

H C C C OH

1.5 (110)

H OH H

Rhkl / R100

2 Diols

TMAH H H

H H

0

H H H H H

(c)

C

- anionic SDSS - cationic ASPEG - non-ionic PEG - non-ionic NC-100 - non-ionic NC-200 - non-ionic NC-300 NCW-601 - non-ionic TRITON X-100 - non-ionic

0

OH C C C C C OH

H

O C OH

7

H H H H H H C C C C C OH

(d)

50

100 [deg]

Angle of inclination of (hkl) toward (110)

R

O C C

OH

H H n

Fig 24.12 ● (a) Examples of alcohol and diol additives for KOH solutions. (b) Etch rate reduction for {221}, {331}, and {441} after addition of alcohols. (c) Typical etch rate dependence on orientation with and without alcohol addition. (d) Examples of surfactant additives for TMAH.

The surface tension may play some role also. All alcohols and diols have a tensioactive character and cause a reduction in the surface tension. The heavier the alcohol is, the larger the reduction in the surface tension and the lower the solubility at a particular solution concentration. Although the drop of surface tension caused by the diols is comparable to that of the propanols, the etch rate does not decrease as dramatically [114]. This is probably connected with a higher solubility of the diols in water solutions and consequently in KOH solutions. As a result, the choice of tensioactive compound should probably be a compromise between the lowering of surface tension and the solubility in KOH solution. In TMAH, the alcohols dissolve very well and their addition improves the roughness of etched {100}, especially at low concentrations [60], without affecting the ratio R110:R100.

otherwise act as micromasks—thus preventing the formation of pyramidal hillocks. The effects of IPA and other alcohols have been extensively studied by Zubel et al. [60, 61, 104, 113, 115, 116]. Complementary reports can be found in Refs [2, 98]. Due to the polar nature of the alcohols, the etch rate reduction for the family of {hh1} surfaces is thought to reﬂect a preferential adsorption of the alcohol molecules at hydroxyl terminated sites, which occur more frequently on these surfaces due to the particular geometry of their step structure [18]. The same argument explains the similar effect from surfactants added to KOH and TMAH as well as from the cations of TMAH (Section 24.8.4).

24.8.6 Addition of IPA to KOH

The addition of surfactants to KOH and TMAH can modify the etching rate anisotropy, reducing the undercutting at the convex corners and improving the surface roughness. For instance, both {100} and {110} can be simultaneously smoothened by the addition of NC200 in low-concentrated TMAH, eliminating also the undercutting, as a bonus [57, 58]. Of the various ionic and nonionic surfactants (see Figure 24.12d), including anionic SDSS, cationic ASPEG, and neutral PEG, NCW, triton, etc. [53–58, 117], the ionic increase the etch rate of {100} [54, 55] while the nonionic reduce it [56, 57, 61]. Although there is not enough experimental data for complete assurance, {110} becomes slower

IPA or (CH3)2CHOH is frequently added to KOH solutions and, to some extent, to TMAH solutions also. In KOH, it reduces the etch rate of {110} and vicinal orientations ({hh1} and {h 2 h 2 h}), and accelerates vicinal and exact {111}, but does not affect signiﬁcantly the rate of vicinal and exact {100}. The fact that the {hh1} surfaces become slow enough strongly reduces the undercutting of convex corners. Additionally, IPA improves the surface roughness of {100} due to an increased wettability of the resulting etchant, which reduces the stability of hydrogen bubbles—which may 396

24.8.7 Addition of Surfactants to KOH and TMAH

Wet Etching of Silicon

than {100} for both ionic and nonionic surfactants [56, 57, 61]. As an important difference, the ionic surfactants are incompatible with IC fabrication. The surfactants affect the surface tension of the solid–liquid and vapor–liquid interfaces, modifying the wetting ability of the host etchant, as evidenced by the change observed in the droplet and bubble contact angles. Due to the hydrophobic–hydrophilic nature of the head–tail structure of the surfactant molecules and the inherent periodicity of their long tail [57]—which repeats the same building block—the molecules tend to be located at any available interface. Thus, the surface tension is affected by the formation of weak bonds between certain atoms of each repeated block and the water molecules. In most cases, the modiﬁed surface tension leads to smaller droplet contact angles and thus larger wetting ability [54, 55]. This enhances hydrogen bubble detachment—which improves the surface roughness—and promotes diffusion of the reactants and/or products in the boundary layer. In addition, the molecule head is thought to block preferentially the monohydride step sites characteristic of exact and vicinal {110}, in a similar manner to the alcohols and heavy etchant cations. As a result, the etch rate anisotropy is modiﬁed. For TMAH, the best results are achieved with nonionic compounds like PEG, NC-200, and TRITON, which simultaneously improve the roughness of {100} and {110}. They also cause a reduction in the etch rate of {110} even at high TMAH concentrations [55–57]. Typical surfactants with bulky molecules are rarely used in KOH solutions. Among the different choices, only SDSS causes a lowering of the surface tension and an improvement in the roughness of {100} [55]. Other compounds have been used to improve the roughness of Si{100} [118].

24.8.8 Isotropic Etchants The paragraphs that follow summarize typical isotropic etchants used in MEMS and their etch rates, according to Refs [119–122]. The composition is given as the volume ratio. R etch rate at room temperature, unless speciﬁed otherwise. HNO3 nitric acid. NH4F ammonium ﬂuoride. HF hydroﬂuoric acid. BHF buffered HF. CH3COOH acetic acid. H3PO4 phosphoric acid. A percentage in a bracket is the weight percent concentration in water solution. For silicon: (1) HNO3 H2O NH4F, e.g., 126:60:5 of HNO3 (70%) H2O NH4F (40%), R 150 nm/ min; (2) HNO3 H2O HF, e.g., 6:2:1 of HNO3 (69%) H2O HF (50%); (3) HNA, mixing hydroﬂuoric, nitric, and acetic acids, e.g., 1:3:8 of HF (49%) HNO3 (70%) CH3COOH (99%), R 1–3 μm/min; for a volume ratio of 4:7:11, R 3–5 μm/min.

CHAPTER 24

For silicon oxide (thermal): (1) HF, typically 10:1 of H2O HF (49%), R 26 nm/min; (2) BHF, e.g., 5:1 of NH4F (40%) HF (49%), R 130 nm/min; for 6:1 BHF, R 120 nm/min; (3) P-etch, i.e., 60:3:2 of H2O HF HNO3, R 12 nm/min. For comparison, R 2 nm/min in KOH IPA (20wt%, 80°C). Due to a less compact structure, oxides grown by chemical vapor deposition (CVD) have faster etch rates by about 25–30%. For silicon nitride: (1) H3PO4, e.g., 85% by weight, R 4.5 nm/min (stoichiometric nitride) and 2.7 nm/ min (silicon-rich nitride) at 160°C; (2) BHF, e.g., 5:1 of NH4F (40%) HF (49%), R 1.3 nm/min for Si-rich nitride. Etch rate values are for CVD nitride. For comparison, R1.4 nm/h in 20 wt% KOH IPA at 80°C.

24.9 Temperature Dependence of the Etch Rate For a chosen concentration and surface orientation, the etch rate R follows an Arrhenius behavior as a function of temperature T: R R0 eEa / kBT ⇔ log R log R0 Ea /kBT (24.3) 5

where kB 8.617 10 eV/K is Boltzmann’s constant. By measuring the etch rate at different temperatures and plotting y logR against x 1/kBT, one can determine the apparent activation energy Ea and prefactor R0. This enables the calculation of the etch rate at any temperature. As an example, Table 24.3 shows the values of Ea and R0 for {100}, {110}, and {111} at 34–37 wt% KOH and 22–25 wt% TMAH according to different experiments. A plot of the corresponding temperature dependence is given in Figure 24.13. Variations of 30– 40% in the etch rate are normal between measurements. The etch rates for {111} are large for Wind et al. [105] and Xing et al. [109], and moderately large for Seidel et al. [2], especially at high temperature. According to Tan et al. [36], this is due to the spatial proximity of the masking patterns—such as the spokes of the wagon wheel and fan structure—and ultimately it is the result of diffusion effects. Since the aim in micromachining is to maximize device density, these etch rates can be suitable for the design of MEMS structures with comparable spacing between the patterns. On the other hand, the use of widely spaced patterns allows minimizing transport effects and enables the determination of the true energetics of the surface-reaction-limited process. The unmasked DRIE pre-etched wagon wheel used by Wind et al. produces excessively large etch rates, around {111}, since the wedge geometry exposes many low coordination atoms [51, 106]. 397

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Table 24.3 Activation energy Ea and prefactor R0 for the etch rate of Si{111}, Si{110}, and Si{100} in 35 wt% KOH and 25 wt% TMAH, comparing the calculations and measurements

R calculated [R measured] (μm/h) Etch

Ref.

hkl

Ea (eV)1

R0 (μm/h)1

50°C

70°C

90°C

KOH

Shikida 2000 [37] 34 wt%

111 100 110

0.48 [0.50] 0.62 [0.62] 0.60 [0.60]

7.31e 06 4.44e 10 5.17e 10

0.20 [–] 9.55 [–] 20.48 [–]

0.56 [0.54] 34.97 [37.74] 72.36 [77.52]

1.38 [1.204] 110.98 [91.084] 222.49[193.624]

Seidel 1990 [2] 34wt%

1112 100 110

0.74 [0.70] – [0.61] – [0.60]

5.47e 10 [3.10e 10] [3.66e 10]

0.17 [–] 9.40 [–] 15.90 [–]

0.78 [–] 33.74 [–] 55.87 [–]

3.09 [–] 105.19 [–] 170.98 [–]

Tan 2001 [36] 35 wt%

111 100 110

0.52 [0.53] 0.62 [0.62] –

1.84e 07 4.16e 10 –

0.15 [0.15] 9.59 [9.85] –

0.43 [0.43] 34.99 [35.56] –

1.14 [0.943] 110.65 [84.733] –

Wind 2002 [105] 37 wt%

111 100 110

0.55 [0.67] 0.56 [0.60] 0.56 [0.58]

3.93e 08 6.06e 09 1.21e 10

1.08 [1.53] 9.41 [9.73] 19.66 [20.53]

3.41 [3.26] 30.69 [30.85] 63.97 [68.11]

9.49 [8.60] 87.91 [86.48] 182.78 [172.05]

Xing [109] 2007 35 wt%

111 100 110

– – –

– – –

– [1.30] – [16.75] – [33.24]

– [3.66] – [42.36] – [83.02]

– [7.21] – [117.20] – [236.00]

70°C

80°C

90°C

TMAH

111 100 110

0.71 [–] 0.65 [0.66] 0.39 [0.39]

1.56e 10 6.40e 10 1.83e 07

0.67 [0.50] 17.48 [16.74] 38.77 [35.16]

1.32 [1.30] 32.62 [32.40] 56.13 [54.60]

2.51 [2.82] 58.82 [60.00] 79.63 [84.00]

Shikida6 2001 [37] 111 25 wt% 100 110

0.73 [0.69] 0.65 [0.64] 0.64 [0.62]

2.55e 10 5.51e 10 7.05e 10

0.53 [ 0.54] 15.83 [15.42] 28.82 [30.48]

1.06 [1.26] 29.49 [29.70] 53.17 [48.54]

2.04 [1.385] 53.10 [45.965] 94.83 [86.165]

Zubel 2001 [60] 25 wt%

–– –– ––

– – –

–– – [15.54] – [19.20]

–– – [26.82] – [33.42]

–– –– ––

Tabata 1992 [3] 22 wt%

111 100 110

1

[Value] is from source. Ea and R0 determined by using {110}:{100}:{111} 160:100:1 at 22°C and 50:30:1 at 100°C, as stated by Seidel. 3 Measured at 85°C. 4 Measured at 86°C. 5 Measured at 87.5°C. 6 To obtain Ea and R0, additional etch rate data from Ref. [112] for 60°C were used. 2

For KOH, Table 24.3 shows that the apparent activation energy is about 0.6 eV for {100} and {110}, typically slightly larger for {100}. In fact, Tanaka et al. [38] have demonstrated that Ea remains constant for the two planes even when the concentration of KOH is varied. On the other hand, Ea 0.5 eV for {111}, although larger values (e.g., 0.7 eV) have been reported, presumably due to the diffusion transport effects arising from 398

the reduced spacing between the mask patterns. For TMAH, Ea is about 0.65 eV for Si{100} at 25 wt%. Tabata et al. [3] report that it varies linearly between 0.5 and 0.75 eV in 5–40 wt%. For Si{111}, Ea is about 0.7 eV. For Si{110}, the value is controversial, as Tabata et al. [3] report Ea 0.4 eV for 5–40 wt% while Shikida et al. [37] measured about 0.65 eV at 25 wt%. The difference might originate in the use of magnetic stirring by Shikida et al.

Wet Etching of Silicon KOH

(b) Shikida Seidel Wind 111 100 110

102 101 100 10–1 2.8

3 1/ T, K–1

3.2

3.4 ×

10–3

Etch rate, microns per hour

Etch rate, microns per hour

(a)

CHAPTER 24

TMAH 102 Tabata Shikida 111 100 110

100

2.8

3 1/ T, K–1

3.2

3.4 × 10–3

Fig 24.13 ● Etch-rate dependence on temperature for Si{100}, Si{110}, and Si{111} in (a) 34–37 wt% KOH, and (b) 22–25 wt% TMAH solutions. Equation 24.3 is used with values for Ea and R0 from several experiments, as described in Table 24.3.

But what does the measured activation energy mean? The apparent activation energy should be understood as the energy barrier of a characteristic energy-well where the most-frequently-removed atom is located before removal. This energy must be supplied in order to extract the atom from the surface. In contrast to extended belief, the apparent activation energy does not correspond to the energy barrier for the removal of the most abundant surface atoms, such as those located at the terraces in a vicinal {111} surface. Wet etching is primordially a step-ﬂow process, mostly resulting from the removal of kink atoms appearing at the steps. Thus, the most typical (and most frequent) process is the removal of these kinks; and correspondingly, the relevant energy is that for their removal [123]. In a more detailed picture the apparent activation energy not only is identiﬁed as the energy barrier for the most frequent process, but also has to include other contributions from less frequent processes [123]. Mathematically, the activation energy is a simple weighted average over the distinct energy barriers, Ea

M

∑ wα ( Eα EαN )

(24.4)

α1

where α denotes the surface site type (e.g., TM, SM, SD, etc. See Section 24.2.4), M is the number of different site types, Nα is the number of atoms located at sites of type α, rα r0α eEα / kBT is the removal rate for the atoms of type α, Eα is the microscopic activation energy for the removal of the atoms of type α (i.e., the energy barrier of each distinct energy-well), N and Eα is an energy correction due to the existence of variations in the numbers Nof atoms with temperature ( Nα Nα (T ) N0α eEα /kBT ) . The weights M wα rα Nα / ∑ α1 rβ Nβ (referred to as success fractions) reﬂect the actual numbers of realized removals as fractions of the total number of removals,

instead of the actual abundance of each energy-well ( wα ≠ Nα / ΣαM1Nα ) . Thus, in going from {111} to {100} or {110}, the dominant contribution to the apparent activation energy corresponds essentially to the energy barrier for the removal of the kinks (followed by the smaller contributions from less and less reactive atoms), modiﬁed in a different manner at each orientation, according to the corresponding temperature variation in the number of kinks (and the other less-reactive atoms). In general, the previous expression explains that the activation energies for {100} and {110} can be similar or different, and describes how the activation energy for {111} can be larger, equal, or smaller [123]. In particular, Ea for {111} does not correspond to the energy barrier for the removal of the terrace atoms.

24.10. Concentration Dependence of the Etch Rate 24.10.1 Experimental Considerations (I. Zubel) Aqueous solutions of KOH and NaOH are often used as anisotropic etchants of silicon. Due to the small dimension of the Na ions and their harmful penetration into the bulk of the substrate, they are, preferably, avoided during fabrication. The variation of the etch rate of Si{100} and Si{110} as a function of the concentration of KOH and NaOH is shown in Figure 24.14a, b. The curves show peak values at roughly the same medium concentration for both orientations, and the relation R110 R100 holds. Other hydroxides from the ﬁrst group of the periodic table, such as RbOH and CsOH, are rarely used in practice. The characteristics of the corresponding etch rate, as shown in Figure 24.14c, signiﬁcantly depart from the trends shown in Figure 24.14a, b. 399

Micromachining Technologies in MEMS

PA R T I V Solutions of 1st kind R100

(c)

R110

R100

R100 1.2

1

1

1

0.8 0.6 0.4 0.2

Normalized etch rate

1.2

0

0.8 0.6 0.4 0.2 0

0

20

40

(b)

R100

0.8 0.6 0.4 0.2

20

40

60

0

c (%wt) RbOH (CsOH)

(d)

R110

R100

(f)

R110

1

1

0.2 0

Normalized etch rate

1

Normalized etch rate

1.2

0.4

0.8 0.6 0.4 0.2 0

0

20 40 c (%wt) NaOH

60

40

R110

1.2

0.6

20

60

c (%wt) KOH (+IPA)

1.2

0.8

R110

0 0

60

c (%wt) KOH

Normalized etch rate

(e)

R110

1.2 Normalized etch rate

Normalized etch rate

(a)

Solutions of 2nd kind

R110

0.8 0.6 0.4 0.2 0

0

10

20

30

0

c (%wt) TMAH

20

40

60

c (%wt) KOH + pentanediol

Fig 24.14 ● Normalized etch rates for {100} and {110} in: (a–b) solutions of 1st, and (c–f) 2nd kinds.

In particular, the relation R110 R100 is valid in the range of low concentrations [2, 124–130]. TMAH is the most commonly used organic solution. The features shown in Figure 24.14d for the etch rate as a function of TMAH concentration are similar to the inorganic solutions containing bulky metal ions Me

(Rb , Cs ), shown in Figure 24.14c. The etching of Si{100} experiences the peak value already at low concentration, where the etch rate of Si{110} is very low. As a result, R110 R100 is valid in the low concentration range. As the concentration is increased, R110 becomes equal to R100, and surpasses it if the concentration is increased further [104, 111, 131–133]. The etchants are often modiﬁed with different additives to improve the roughness or to modify the anisotropy, as described in Sections 24.8.4–24.8.6. As an example, the addition of two different alcohols reduces the etch rate of {110} in such a manner that R110 R100, as shown in Figure 24.14e, f [60, 98, 113, 114]. Comparison of Figures 24.14a–f suggests a classiﬁcation of the etchants into two categories. The 1st kind includes the solutions of pure inorganic hydroxides with small cations, for which R110 is high and the relation R110 R100 is valid in the whole concentration range. 400

The process is out of equilibrium in terms of the transport of the reactants and/or reaction products, which makes the etched surfaces rather rough. The small ions K and Na do not play any important role in the etching process. The 2nd kind includes solutions with large ions like Cs , Rb , and TMA , as well as large-sized tensioactive additives like alcohols and surfactants, including also the effect from small impurity ions like Cu [41], all of which cause a reduction of the etch rate of exact and vicinal {110} while simultaneously smoothening these orientations. Probably the lower etch rates allow the onset of equilibrium between the different processes responsible for etching. It is likely that the state where diffusion becomes the rate-limiting process is the condition that provides smooth surfaces in the vicinity of {110}. (See Sections 24.1.1 and 24.4) Figure 24.12c shows the orientation dependence of the etch rate in 10 M KOH (a common etchant for MEMS fabrication) and 5 M KOH saturated with IPA as typical examples of solutions of the 1st and 2nd kinds, respectively. Alcohol addition results in considerable reduction of the etch rates for the {hh1} and {h 2 h 2 h} surfaces while not signiﬁcantly affecting the {h11} and {h 2 h h} orientations [61].

Wet Etching of Silicon

24.10.2 Theoretical Considerations

⎡ f ⎤1 / 4 R k0 ⎡⎢( a0 a1 f a2 f 2 )ρH2O ⎤⎥ ⎢ ⎥ ⎣ ⎦ ⎢⎣ w ⎥⎦

The concentration dependence of the etch rate of silicon in KOH and TMAH has been studied by several groups. For KOH, Seidel et al. found that the etch rate of Si{100} and Si{110} can be expressed as [2], Ea /kBT

R R0 e

1/ 4

k0 [KOH]

4 Ea /kBT

[H2O] e

(24.5) where [x] denotes the molarity or molar concentration of x, measured in mol/l. For {100}, k0 2480 μm/ h(mol/l)–4.25 and Ea 0.595 eV. For {110}, k0 4500 μm/h(mol/l)–4.25 and Ea 0.60 eV. Thus, one can easily calculate the etch rate for any concentration and temperature, as shown in Figure 24.15. Since [KOH] [OH–], this expression is considered to reﬂect the molecularity of the reaction shown in Section 24.3, where four water molecules are used and one hydroxyl ion assists in the removal of each silicon atom. At low concentrations, the etch rate increases as the number of hydroxyls [OH–] increases. At high concentrations, however, increasing the concentration reduces the number of water molecules [H2O], thus reducing the etch rate. As a result, a maximum in the etch rate appears at an intermediate concentration. This maximum has been observed at about 25 wt% KOH [2, 37, 100, 101, 104], and also for other etchants with light cations [104]. The case for heavier cations, such as TMAH, is controversial, as the maximum has been observed by some [37, 110] but not by others [3]. Seidel’s expression captures what is considered to be the basic trend of the etch rate as a function of orientation. Seidel’s expression can be written in terms of the weight percent concentration (p) or, equivalently, the weight-fraction (f p/100) as (see Section 24.13),

Si{100}

(a)

0

20

40

KOH concentration, wt%

60

Etch rate, microns per hour

Etch rate, microns per hour

50

(24.6)

where w 56.11 g/mol and wH2O 18.02 g/mol are the molecular weights of KOH and water, respectively; ρH2O 1000 g/l is the density of water; and a0 0.9927, a1 0.8666, and a2 0.3051 are expansion coefﬁcients for the speciﬁc gravity as a function of the weight fraction. (See Section 24.14.) In principle, the same equation can be used for TMAH with w 91.18 g/mol, a0 1.12, a1 0.4, a2 0. However, corresponding values for k0 and Ea are not available. Glembocki et al. elaborated further on the molarity model for KOH and conjectured that the Arrhenius prefactor can be written as follows [101]: R0 k0 [OH ]a ([H2O] m[OH])b

(24.7)

Due to the multi-site nature of the surfaces, with various amounts of mono-, di- and trihydride terminated atoms, an average noninteger exponent (a) is expected for [OH–]. (For tri- and dihydride-terminated surface atoms, three and two hydroxyls, respectively, will be involved in the oxidation step instead of one for the monohydrideterminated atoms.) Similarly, not always four water molecules are lost in the removal of each silicon atom, since the product of the reaction is transformed and water molecules are formed, as explained in Section 24.3. Thus, a noninteger exponent (b) is expected for [H2O]. In addition, water molecules are lost in forming hydration shells around the hydroxyls and etchant cations. As a result, the effective number of water molecules is [H2O] – m [OH–], where m is an average number of water molecules in the hydration shells. Since [K ] [OH–] [KOH],

Si{110} 150

90°C 80°C 70°C 60°C 50°C

100

0

⎡1 f ⎤ 4 ⎥ eEa / kBT ⎢ ⎥ ⎢w ⎢⎣ H2O ⎥⎦

(b)

150

CHAPTER 24

90°C 80°C 70°C 60°C 50°C

200 150

Fig 24.15 ● Etch rate dependence on concentration and temperature for Si{100} and Si{110} according to Eq. 24.6.

100 50 0

0

20

40

60

KOH concentration, wt%

401

PA R T I V

Micromachining Technologies in MEMS

an expression like [H2O] – m [OH–]–n [K ] is not needed. The previous models highlight the central role of OH– and H2O in the reaction and explain the concentration dependence of the etch rate as a tradeoff between the numbers of molecules of the two species. However, Wind et al. reported that neither Seidel et al.’s nor Glembocki et al.’s expression can ﬁt their data [105]. Similarly, the data of Shikida and co-workers [37] cannot be satisfactorily ﬁtted, using Seidel’s expression. An alternative explanation for the appearance of the etch-rate maximum as a function of concentration for the different surface orientations considers the amount of surface OH-coverage as the direct cause [73]. The OH-coverage is expected to increase with concentration, resulting in gradually increased etch rates. However, the OHs tend to form clusters around already-OH-terminated sites, and when the coverage is large enough this leads to steric hindrance for OH-termination, which effectively reduces the etch rates. Zubel et al. comment that the hydration model is valid as a qualitative explanation of the concentration dependence for light-cation etchants, such as KOH, NaOH, and LiOH. However, for heavier and larger cations, such as Rb , Cs , and TMA , additional sitedependent blocking by the cations must be considered [104]. The addition of IPA and other alcohols to KOH solutions leads to similar selective blocking effects [104], as described in Sections 24.8.4.7 and 24.10.1. Gosalvez et al. have suggested that the atomistic mechanism leading to selective blocking by the large cations, alcohols, and surfactants is the existence of a polar (Coulomb) interaction between the cations and/or additive molecules and the temporary OH-terminated surface sites. According to ab-initio calculations, the OH-termination is more likely to be found on SM sites [18].

24.11 Other Variables Affecting the Etch-Rate Values In addition to (1) the etching temperature and (2) the concentration of the etchant, there is a number of parameters that are known to affect the values of the etch rate. These are (3) loss of reaction species; (4) loss of liquid phase due to evaporation; (5) solution stratiﬁcation; (6) diffusion transport—stirring state and type (mechanical, magnetic, etc.), mask pattern spacing, and structure geometry; (7) amount of substrate already dissolved in the etchant; (8) etchant impurities; (9) etching time; (10) applied voltage; (11) galvanic interaction between the etched facets; (12) illumination; (13) substrate impurities and doping; (14) substrate microstructure (dislocations, grains, etc.); (15) substrate stress (e.g., ﬁlms); and (16) addition of surfactants, alcohols, and oxidizing agents to the etchant. 402

24.12 Experimental Determination of Etch Rates The major methods for the determination of the etch rates can be divided into in-situ and ex-situ, depending on whether the measurement is realized while the sample is in the etchant (during etching) or outside it (after etching). Typical ex-situ measurements keep track of the etch time and make use of one of the following methods to determine the distance advanced by the surface: (1) a standard square mask opening on a wafer with the required {hkl} orientation, measuring the etched depth with a mechanical proﬁler; (2) a wagon wheel mask pattern on Si{100} or Si{110}, measuring with an optical microscope the amount of undercutting—that is, the retraction perpendicular to the radial direction of each spoke [2]; (3) a convex spherical specimen, measuring the change in size and shape with a mechanical proﬁler [10–12, 37]; and (4) a DRIE pre-etched wagon wheel microstructure initially shaped as a cake readily cut into wedges, measuring with an optical microscope the amount of wedge retraction, radially from the center [51, 59]. The in-situ methods determine the instantaneous etch rate by using (1) optical beam or laser interferometry based on multiple reﬂection of the transmitted beam and interference with the reﬂected beam, leading to an alternation of constructive and destructive coupling as the optical path length in the substrate varies continuously due to the thinning of the material [134, 135]; (2) continuous image collection by optical microscopy, allowing, for example, the measurement of the amount of underetching by image processing [51, 52, 136]; and (3) electrochemical voltammograms, where relatively fast potential scans are performed periodically during etching to determine the maximum anodic current, which is known to decrease as the original masked {100} or {110} surface is transformed into a more complex etch front containing other orientations, especially {111} [136]. The rate of decrease in the peak current is proportional to the etch rate.

24.13 Converting Between Different Measures of Concentration The etch rates in the literature are typically given as using three popular measures of concentration: (i) molarity, as in 6 M EDP; (ii) weight percentage, as in 25 wt% TMAH; and (iii) weight-volume percentage, as in 50% w/v KOH. Transformation formulas between them are given here. The molarity (M) or molar concentration is the number of moles of solute (n) per one liter of resulting

Wet Etching of Silicon

solution (VT total volume): M n/VT. It is measured in mol/l, molar, or M. The weight percentage (p) or weight–weight percentage or mass percentage is the ratio of the mass of the solute (m) to the total mass of the resulting solution (mT), expressed as a percentage: p 100 (m/mT). It is dimensionless and designated as using wt% or % w/w. A similar measure is the mass fraction (f): f m/mT p/100. The weight–volume percentage (q) or mass–volume percentage or percent weight per volume or molality denotes the mass of the solute expressed in g per 100 ml of the resulting solution. It is typically designated as % m/v or % w/v. In addition, the volume percentage (v/v) can also be used as a measure of the etchant concentration. The following formulas can be used to convert between the three measures, as explained next:

The molarity M is written in terms of the mass fraction f by expressing the number of moles n in terms of the mass of the solute m; that is, n m/w, where w is the molecular weight or formula weight of the solute, measured in g/mol. For instance, w 56.11 g/mol for KOH and w 91.18 g/mol for TMAH. Thus, M n/ VT m/wVT. Using the mass fraction, m fmT, one gets M ρTf/w, where ρT mT/VT is the density of the solution. To relate the density of the solution ρT to that of water ρH2O, the speciﬁc gravity (s ρT/ρH2O) is used. For KOH solutions, the speciﬁc gravity depends on concentration and temperature [137]. To a good approximation, we ﬁnd that it can be written in terms of the mass fraction: s a0 a1f a2f2, where a0 0.9927, a1 0.8666, and a2 0.3051. Similarly, s 1.1 – 1.02 for 5 – 25 wt% TMAH, giving a0 1.12, a1 0.4, a2 0. For etching temperatures in 20–100°C, the density of water is approximated by ρH2O 1000 g/l. Thus, the molarity gets the form M ρTf/w 1000 (a0 a1 f a2 f 2)f/w. Since the mass fraction of water in the same solution is 1 – f, the molarity of water is MH2O ρT(1 – f)/wH2O 1000(a0 a1f a2f2) (1 – f)/wH2O, where wH2O 18.02 g/mol. The curves and values given in Figure 24.16 have been obtained using the previous conversion formulae. They can be used to convert quickly between weight percent volume percent and molality for both KOH and TMAH.

M from p: Determine f p/100, then use: M 1000 (a0 a1f a2 f 2) f/w. p from M: Solve P( f ) a2 f 3 a1 f 2 a0 f (w/ 1000)M 0 for f in [0,1], then get p 100f. M from q: M 10q/w. q from M: q wM/10. p from q: Solve P(f) a2 f 3 a1 f 2 a0 f q/100 0 for f in [0,1], then determine p 100f. q from p: Determine f p/100, then use q 100 (a0 a1 f a2 f 2)f.

35

14.3 KOH

70

12.5

60 50 7.5

40 30

5

Molarity (M)

10

20 2.5 10 0

0

(a)

10

20

30

40

50

Molality or Weight-volume percent (q)

Molality or Weight-volume percent (q)

80

CHAPTER 24

Weight percent (p)

3.5

30

3 25 2.5 20 2 15

1.5

10

1

5 0

0 60

3.84 TMAH

0.5 0

5

10

15

20

25

30

0 35

Weight percent (p)

(b)

KOH p 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 q 5.18 10.82 16.94 23.56 30.71 38.40 46.67 55.53 65.00 75.11 85.89 M 0.92 1.93 3.02 4.20 5.47 6.84 8.32 9.90 11.58 13.39 15.31

TMAH p 0.50 q 0.56 M 0.06

1.00 1.12 0.12

1.50 1.67 0.18

2.00 2.22 0.24

2.50 2.78 0.30

5.00 10.00 15.00 20.00 25.00 30.00 5.50 10.80 15.90 20.80 25.50 30.00 0.60 1.18 1.74 2.28 2.80 3.29

q p M

5.00 10.00 15.00 20.00 25.00 30.00 40.00 50.00 60.00 70.00 80.00 4.83 9.29 13.46 17.36 21.04 24.52 30.99 36.92 42.40 47.51 52.31 0.89 1.78 2.67 3.56 4.46 5.35 7.13 8.91 10.69 12.48 14.26

q p M

0.50 0.45 0.05

1.00 0.90 0.11

1.50 1.35 0.16

2.00 1.80 0.22

2.50 2.25 0.27

5.00 10.00 15.00 20.00 25.00 30.00 4.54 9.23 14.10 19.17 24.46 30.00 0.55 1.10 1.65 2.19 2.74 3.29

M p q

4.00 5.00 6.00 7.00 8.00 10.00 12.00 14.00 1.00 2.00 3.00 5.39 10.34 14.91 19.18 23.19 26.96 30.55 33.95 40.32 46.18 51.63 5.61 11.22 16.83 22.44 28.05 33.67 39.28 44.89 56.11 67.33 78.55

M p q

0.05 0.41 0.46

0.10 0.82 0.91

0.15 1.23 1.37

0.25 2.05 2.28

0.50 4.13 4.56

1.00 1.50 2.00 2.50 3.00 3.50 8.39 12.80 17.36 22.10 27.03 32.20 9.12 13.68 18.24 22.80 27.35 31.91

Fig 24.16 ●

403

PA R T I V

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25

Chapter Twenty Five

Porous Silicon Based MEMS Gerhard Müller1, Alois Friedberger1 and Kathrin Knese2 1

EADS Innovation Works, München, Germany Robert Bosch GmbH, Automotive Electronics, Reutlingen, Germany

2

25.1 Porous Silicon Background Porous silicon (PS) was ﬁrst discovered by accident in 1956 by Uhlir Jr. and Ingeborg at the Bell laboratories when developing surface-polishing procedures for silicon and germanium wafers [1]. This early work was considered a failure as it was found that the silicon was not removed in a layer-by-layer fashion. Rather, a spongelike structure formed at the silicon surface. Depending on preparation conditions, pore diameters ranged from a few nanometers up to about one micrometer. A ﬁrst application of PS was in the ﬁeld of siliconon-insulator (SOI) technology [2]. There, Si wafers were made porous at the top surface and epitaxial silicon was grown on top of the PS layers. Subsequent oxidation of the PS formed thick SiO2 layers that insulated the epitaxial layers from the substrates. Renewed interest in PS was raised in the late 1980s when it was argued that PS might display quantum conﬁnement effects. Soon thereafter, Leigh Canham [3] and, independently, Lehmann and Gösele [4] showed that nanoporous silicon (NPS) exhibits an efﬁcient orange photoluminescence when illuminated with UV light. This discovery generated an explosion of interest in NPS, as NPS technology seemed to offer a road towards silicon light-emitting devices. Several books and review articles have since been devoted to this subject [5–7]. Whereas quantum conﬁnement effects arise out of the constrained geometry of the lamellae that separate neighboring pores in the NPS, NPS has also attracted attention because of the pores themselves. This internal pore structure in NPS leads to an enormous internal surface area which may range up to 800 m2/cm3 [8]. Together with

the constrained geometry of the pore-separating lamellae, this makes NPS an extremely surface-dominated material. This surface sensitivity has relevance for applications in the realm of catalysis [9], fuel cells [10, 11], as well as in the ﬁeld of physical [12], chemical [13], and gas sensors [14, 15]. Very likely, the discovery of “explosive porous silicon” [16] is the most striking demonstration of the surface reactivity in NPS. Last but not least, the dense network of interpenetrating pores makes NPS a heterogeneous two-phase material with interesting optical properties. Optical interference ﬁlters [17, 18] and antireﬂection coatings for solar cells [19] are applications that build on this heterogeneous two-phase structure.

25.2 PS Sacriﬁcial Layer Technologies Whereas the above lines of research all build on fundamental and applied interests in the material properties of the PS itself, NPS has also attracted attention due to its potential as a sacriﬁcial layer material. This latter line of research was motivated by the fact that PS formation is sensitive to the doping proﬁles that can be created inside silicon wafers. Secondly, once formed, it was found that PS layers can be easily removed from the remaining bulk silicon by using dilute chemical etches which easily attack the PS but leave the remaining bulk silicon intact. These properties opened up a range of possibilities for generating three-dimensional microstructures in bulk silicon [12, 18]. Several types of microsensors and microactuators have since been realized with the help of PS technologies. 409

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More recently, macroporous silicon (MPS) has attracted major interest as a microstructuring technology as well [20, 21]. MPS can be formed in n-type silicon under illumination, yielding long, straight pores with pore diameters and wall thicknesses in the micrometer range. A trigger for this interest was the observation that large regular arrays of macropores can be formed by lithographic pore initiation. This possibility seems to be most promising for the formation of two- and three-dimensional photonic crystals [22] and for the fabrication of microﬂuidic devices [23]. With regard to other bulk and surface micromachining technologies which can be applied to silicon, the distinguishing features of PS sacriﬁcial layer technologies are as follows: – Microstructure geometries can be deﬁned by the

lithographical design of masking layers; – the lateral PS proﬁle is determined by the shape of

electrical ﬁeld lines during PS processing rather than by crystallography; – the etching of the silicon substrates can be

conﬁned to the front side of the silicon wafers;

i.e., protection wafers for the rear side of the micromachined wafers are not required; – the vertical extent of the micromachined structures

can be varied over a large range extending from nearsurface up to bulk silicon microstructures; – the micromachined structures consist entirely of

low-stress bulk crystalline silicon; – the use of hydroﬂuoric acid (HF) as an etching agent

guarantees enhanced CMOS compatibility. Figures 25.1 and 25.2 show some representative silicon microstructures that have been formed using NPS and MPS technologies.

25.3 PS Fabrication Technology PS forms when silicon is immersed in HF under conditions of current ﬂow. A ﬁrst arrangement that can be used to form PS is shown in Figure 25.3 [26]. There, the Si wafer to be treated separates a volume of HF, forming a double-cell arrangement. The electrolyte in each cell is contacted

Fig 25.1 ● Thermal ﬂow sensor with heatable silicon carbide (SiC) bridges before (left) and after (right) removal of the NPS sacriﬁcial layer [24].

4.2 μm

Fig 25.2 ● Regular array of macropores formed in n-type silicon under illumination. The modulation of the pore width was achieved by varying the illumination intensity during pore etching [25]. Source: © Wiley-VCH Verlag GmbH & Co. KGaA. Reproduced with permission.

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by a platinum (Pt) grid. Both grids are connected to a potentiostat, and a current is forced through the doublecell arrangement. For proper operation it is important that the two half-cells are contacted exclusively through the Si wafer and that any leakage currents around the wafer are avoided. Such conditions can be attained by O-ring seals along the periphery on both sides of the wafer. When Si wafers are immersed in HF/H2O electrolytes, quasi-Schottky barriers form at both interfaces [27, 28] and nonlinear current-voltage characteristics emerge. Typical I-V characteristics are shown in Figure 25.4. These demonstrate that the form of the I-V characteristics sensitively depends on the kind and concentration of dopant impurities in the Si wafers. The form of these I-V characteristics can be qualitatively explained in terms of the band-bending proﬁles that develop at the anode side of the wafers (Figure 25.5). The characteristics above can be understood by way of example. Considering the case of a p-type wafer, the current inside the wafer is supported by electronic holes (h ). On the anode side of the wafer, i.e., the side

CHAPTER 25

facing the negatively biased Pt grid, the electronic holes emerge at the free surface and discharge there F ions which abound in the liquid electrolyte: F h → F

(25.1)

The neutral F atoms, in turn, corrode the silicon surface by breaking Si–Si bonds and by forming Si molecular ions which can dissolve in the liquid electrolyte: 2F Si 4HF → H2SiF6 H2

(25.2)

The opposite side of the wafer, which faces the positively biased Pt grid, stays intact. There, H3O ions are discharged upon interaction with the Si surface by trapping valence electrons, thereby forming H2O and H2: H3O e → H2O 12 H2

(25.3)

As this rear contact ultimately has to supply the holes that are needed to sustain the PS formation process

Fig 25.3 ● Electrochemical double-cell arrangement for PS formation: (left) Cell architecture; (right) Equipment photograph. Sapphire windows allow for an optional front- or rear-side illumination.

Fig 25.4 ● I-V characteristics produced by the double-cell arrangement shown in Figure 25.3. As the rate of PS formation depends on the current density through the wafer, biasing at a voltage V0 0.5 V, p, p , and n wafers can be anodized, while moderately doped n-Si remains largely intact.

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Fig 25.5 ● Band-bending proﬁles developing at the anode side of p, p , n, and n wafers.

at the anodic side, it is important to a make good Ohmic contact to the cathodic wafer side. This can be accomplished by performing a p contact implantation prior to the PS formation. Alternatively, blue-light illumination can be used to reduce the contact resistance. In order to allow illumination during processing, the electrochemical cell in Figure 25.3 is equipped with two transparent and HF-resistant sapphire windows. Similar considerations obviously apply for p wafers. In n-type wafers PS formation cannot proceed in the dark, as such wafers hardly contain any electronic holes that could neutralize F ions and thus initiate a PS formation process. In n-type wafers PS can only be formed when holes are photo-generated. In this case the photogenerated holes are attracted to the solid/liquid interface on the anodic side by the upward band bending that exists there. N silicon is exceptional insofar as PS formation can proceed there also in the dark. The reason is that the band-bending proﬁle at the anodic surface of the n Si is so steep that it becomes transparent to electron tunneling. Adsorbed F ions therefore can discharge and thus become chemically active by injecting their excess electron into the Si conduction band. Further considering the fact that in all cases considered above, it is only H3O ions that are discharged at the cathodic side with no chemical reaction taking place on the Si side, less complex single-cell electrochemical arrangements can also be used. As shown in Figure 25.6, such arrangements only expose the anodic side of the wafer to the HF, whereas electrical contact to the cathodic side of the wafers is made via standard metallic contacts. Attaining Ohmic backside contacts again requires a p contact implantation and a metallization step prior to the PS formation. 412

25.4 Microscopic Processes Underlying PS Formation In order to arrive at a deeper understanding of the electrochemical processes that lead to the formation of PS, it is important to consider the energetic conditions that prevail at the solid–liquid interface. On the solid side, the relevant electron energies are the conduction and valence band edges, Ec and Ev, and their positions relative to the vacuum energy, Evac. The relevant energetic parameters on the liquid side are the electro-chemical potentials of the H3O /H2O and the F2/2F redox couples. In a strongly acid electrolyte like HF/H2O, the electrochemical potential is roughly at a position 4.5 eV below Evac (Figure 25.7). With Eredox at this level, all the ﬂuorine atoms in the liquid are completely converted to F ions, and a signiﬁcant fraction (1 mol/l) of the H2O molecules abounds in its positively ionized form H3O . Turning to the solid side of the junction, we note that Eredox is roughly halfway in between the conduction and valence bands; i.e., it coincides with the intrinsic position of the Fermi level in silicon. This means that forming an actual contact between a silicon wafer and an HF/H2O electrolyte, the direction of the charge exchange across the solid/liquid interface and therefore the direction of the band bending, depends on whether the wafers are n- or p-type. Establishing thermal equilibrium between solid and electrolyte, the Si band edges therefore will bend downwards at the surface of p-type wafers and upwards in n-type wafers. In order to understand PS formation, the chemical bonding at the silicon surface needs to be considered. Creating a crystallographic surface by cleaving involves cutting covalent bonds and thus creating a layer of dangling, i.e., unsaturated bonds at the cleavage surface. On a free surface most of

Porous Silicon Based MEMS

Pt grid electrode

CHAPTER 25

Temp. sensor Front-side contact Rear-side contact

HF

Si wafer

Air

Au contact

Sapphire window

Fig 25.6 ● Single-cell arrangement for PS formation.

Fig 25.7 ● (left) Positions of the conduction and valence band edges in silicon and of the electrochemical potential in a strongly acid HF/ H2O electrolyte relative to the vacuum level Evac; (right) form of the surface band bending in p- and n-type Si after immersing the silicon wafers and after establishing thermal equilibrium between silicon and liquid electrolyte.

these dangling bonds will reunite, forming weak bonds as indicated in Figure 25.8. Given the strong directionality of the silicon sp3 bonds, it is clear that the reconstructed Si–Si bonds will be relatively weak and therefore likely to break. Once broken, these form pairs of dangling bonds. Dangling bonds in turn form localized electronic states in the bandgap which can

easily communicate with the extended electron states in the conduction and valence bands. In the course of such charge exchange interactions, the surface dangling bonds may acquire either of three charge states: positive, neutral, or negative. Which of these states predominates depends on the electron availability, i.e., on the position of the Fermi energy at the Si surface. The charge on the dangling 413

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bonds in turn determines in which way the unsaturated surface bonds can interact with the charged or neutral molecular constituents in the liquid electrolyte. These possibilities are displayed in Figure 25.9 considering the cases of an n- and a p-type Si surface. The actual dissolution process that breaks out silicon atoms from the surface is sketched in Figure 25.10. This latter picture shows that a silicon ionic species that may become dissolved in the liquid electrolyte is formed once the two dangling bonds on a single surface Si atom become terminated by two ﬂuorine atoms. The two strong Si–F bonds destroy the sp3 hybridization of the surface atom, and an Si–F2 molecule is released into the liquid electrolyte. Due to its strongly positive redox potential, the SiF2 acquires two electrons from its chemical environment, becoming ultimately dissolved in the liquid electrolyte.

Recognizing the fact that F-termination of Si dangling bonds precedes Si dissolution into the liquid electrolyte, we note from Figure 25.9 that there is a very clear asymmetry in the number of Si–F bonds at the solid–liquid interface when we consider p- and n-type surfaces. Because of the predominant positive surface charge at p-type surfaces, such surfaces are much more attractive to Si–F bonding than n-type ones. P-type surfaces, therefore, become rapidly attacked in HF/H2O electrolytes, whereas n-type surfaces tend to stay intact. The other point apparent from Figure 25.10 is that positive surface dangling bonds are consumed in the dissolution process. Maintaining a thermal equilibrium between positively charged, neutral, and negatively charged dangling bonds therefore requires a resupply of two holes to the newly emerging surface dangling bond sites, i.e., a hole current to ﬂow through the Si wafer to keep the etching process going.

Si Si Si Si Si Si Si

Fig 25.8 ● Bond reconstruction at the three major crystallographic planes of silicon.

Fig 25.9 ● Schematic densities of band and dangling bond states at the surface of n-type (left) and p-type Si (right). The energetic positions of the differently charged dangling bond states have been displaced from each other for ease of graphical presentation. The relative numbers of positive, neutral, and negative dangling bond states depend on the surface Fermi energy. The electronic charge of the dangling bonds in turn determines how these states may interact with the positive, neutral, and negative molecular constituents of the liquid electrolyte.

414

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Considering Figure 25.10, it is a striking fact that— on an atomic scale—the PS formation process and the process of anisotropic silicon etching in alkaline solutions look fairly similar. The common aspect is that individual Si atoms are liberated from the solid surface by terminating the emerging surface dangling bonds either by F or by OH ions, respectively. Whereas PS formation is an isotropic process, KOH etching is very sensitive to the surface orientation and thus anisotropic. The isotropic nature of the PS formation process can be traced back to three important differences: • Si–F bonds are stronger than Si–OH ones. Si–F surface bonds therefore inﬂuence the sp3 electron conﬁguration of the surface Si atoms much more heavily than Si–OH ones. As a consequence, the Si–Si back bonds, which keep the surface Si atoms connected to the Si bulk, are destabilized to a much

Fig 25.10 ● Molecular mechanism of Si dissolution in HF/H2O liquid electrolytes.

CHAPTER 25

larger extent in HF/H2O electrolytes as compared to alkaline ones; • In an alkaline electrolyte the electrochemical potential is at Evac 3.7 eV. As a consequence the surface Fermi energy is pinned at a position close to the conduction band edge. Most of the surface dangling bonds will therefore attain a negative charge and thus will be unlikely to form Si–OH bonds. In acid HF/H2O electrolytes, on the other hand, the surface energy is pinned at around midgap. The much larger number of positive surface dangling bonds largely enhances the probability of forming two destabilizing Si–F bonds at the same surface Si site; • In contrast to alkaline KOH etching, PS formation is a current-driven process. Randomly forming perturbations of the originally planar etch front tend to focus electrical ﬁeld lines, thus supplying more charge carriers to these irregularities. Depending on the electrical bias, this can either result in pore formation or in electro-polishing. The process of current focusing is essential for an understanding of pore formation in PS and thus sketched in more detail in Figure 25.11 [29, 30]. The remaining question is what determines the pore size and the thickness of those lamellae that separate neighboring pores. In the early days of PS research two limiting cases were discussed. These relate to (i) quantum conﬁnement and (ii) to space charge limitation. These elementary models explain certain limiting cases as, for instance, NPS formation in p-type Si [5, 31, 32] or MPS formation in illuminated n-type Si [33, 34], but need to be complemented by further details to explain more complex features as, for instance, macropore formation in un-illuminated p-type Si [35].

Fig 25.11 ● Focusing of electrical ﬁeld lines at randomly forming irregularities at the silicon surface. Depending on the relative abundance of F ions (low bias voltage) or electronic holes (high bias voltage) either pore formation or electro-polishing is observed [29, 30].

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Turning to NPS formation in p-type Si ﬁrst, the process limiting the lamella width is believed to be an inherently quantum mechanical one (Figure 25.12). Whereas current focusing at the pore tips drives pore formation into the direction of the electrical ﬁeld lines, the isotropic nature of the dissolution process tends to widen the emerging pores laterally. This lateral growth stops when the thickness of the remaining lamellae has been reduced to the nanometer range. At this dimension, quantum conﬁnement effects set in that widen the band gap in the lamellae regions, resulting in a reduced supply of electronic holes to the lateral pore walls. A different situation arises during the photoelectrochemical etching of n-type wafers. Forming macropores in n-type Si, the wafers are illuminated from the backside and photo-generated holes are attracted to randomly forming or intentionally initiated etch pits at the front side. There, current focusing again favors etching at the pore tips. Etching of the pore walls is less efﬁcient due to the current focusing at the pore tips and the high-resistivity space charge zones that develop inside the pore walls. Wall etching is considered to seize when the lamella thickness has shrunk to twice the depletion layer width. As the extent of space charge zones in moderately doped n-type regions is in the order of micrometers, much larger pores and thicker lamellae develop in n-type material (Figure 25.13). An interesting aspect of the MPS process is that lithographical prestructuring can be used to deﬁne those spots on the surface where macropores will ultimately start to

Fig 25.12 ● Limitation of lateral pore growth in p-type Si due to quantum conﬁnement effects in the lamellae regions [31].

416

grow. In this way regular arrays of pores with a deﬁned lattice constant can be formed (see Figure 25.2). Due to the space-charge-limited passivation of the pore walls, lattice constants in the range between 0.5 μm and 8 μm can be realized with the aspect ratio of the macropores reaching values in the order of 100–500. Furthermore, as the diameter of the emerging pores depends on the supply of photo-generated holes to the pore tips, variations in the backside illumination may be used to modulate the pore diameter as the pores grow.

25.5 Formation of Silicon Microstructures 25.5.1 Structure Delineation Three-dimensional structures in bulk silicon can be formed when the process of PS formation is conﬁned to speciﬁed areas of the Si wafers. The most straightforward way of forming spatially conﬁned PS sacriﬁcial layers is to use p-type Si substrates and to conﬁne the process of PS formation laterally by employing photo-lithographically structured masks on the wafer surface. This process is illustrated in Figure 25.14. There, it is also indicated that a wide choice of materials can be used to limit the PS formation process to the desired regions. In principle, any kind of material can be used that can be deposited onto silicon and that can withstand the aggressive chemical environment of a HF/H2O electrolyte. Materials of choice are noble metals [36], dielectric materials (hydrogenated amorphous silicon carbide, a-SiC:H) [37], siliconcompatible multi-layer ﬁlms (e.g., poly-Si/Si3N4) [38, 39], semiconductor thin ﬁlms (β-SiC [24], n-type poly-Si

Fig 25.13 ● Photo-electrochemical pore etching in backsideilluminated n-type wafers [28].

Porous Silicon Based MEMS

(P. Kreisl, private communication), n-type epitaxial Si [40, 41]) and, last but not least, p-type [42] and ntype bulk Si [26, 43]. In the past all these possibilities have been used to realize silicon devices. Very often, combinations of such materials had to be used to arrive at a reliable passivation of those areas which needed to be protected against an electrochemical attack. We will come back to a discussion of such passivation aspects after having reviewed the basics of the structure delineation in bulk Si wafers. The attraction of such PS sacriﬁcial layer technologies relates to the fact that PS layers can be formed after a CMOS-compatible pre-processing of the silicon wafers. This kind of pre-processing can be carried out in all kinds of silicon foundries. Secondly, the PS sacriﬁcial layer technology holds the potential that—after the PS formation—there is still a ﬂat wafer surface that allows a number of application-speciﬁc, thin-ﬁlm, and lithography steps to be carried out. As shown in Figure 25.15, the removal of the PS sacriﬁcial layer belongs to this

Fig 25.14 ● Formation of spatially conﬁned NPS sacriﬁcial layers in a p-type Si substrate.

CHAPTER 25

application-speciﬁc back-end of the process sequence. A subdivision of the entire process sequence into a CMOS front-end and an application-speciﬁc back-end is an important prerequisite in enabling technically and economically feasible cooperations of silicon foundries and high-tech SMEs active in specialized ﬁelds of sensor and actuator technology. Returning to the problem of conﬁning PS formation to mask-deﬁned regions, we note that bulk silicon has excellent mechanical properties and that PS formation is sensitive to the doping level in bulk silicon. Building on this fact, Bischoff et al. [44, 45] have devised a number of processes that allow forming three-dimensional silicon microstructures consisting entirely of bulk Si by forming doping proﬁles in the surface and subsurface regions of Si wafers, using ion implantation and drive-in procedures. These processes are sketched schematically in Figure 25.16. The general idea behind these processes is that silicon will dissolve electrochemically, once electronic holes are constantly supplied to certain parts of the Si/liquid electrolyte interface. The ﬁrst process (a) is one of the possible realizations of the basic microstructuring process displayed in Figure 25.14. With this process PS etch depths up to 20 μm were reached under constant-current conditions. At this point the n-type surface layers started to corrode as well due to changes in the bias conditions that developed inside the wafer as the PS formation was driven towards larger depths. Using a process variant that keeps the surface potential of the n-type surfaces constant, much larger etch depths of the order of 160 μm were obtained. The other three processes (b, c, and d) are photovoltaic processes. In these processes the pre-processed silicon wafers simply need to be immersed into the liquid electrolyte and

Fig 25.15 ● Modularization of a sensor or an actuator fabrication process into a CMOS-compatible front-end and a device-speciﬁc back-end process.

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Fig 25.16 ● Processes for forming three-dimensional Si microstructures using ion implantation and drive-in processes to delineate areas of electrochemical or photo-electrochemical attack [44, 45].

illuminated with above-bandgap light. The built-in junction ﬁelds then separate the photo-generated electronhole pairs, causing a fraction of them to diffuse to the differently doped surface regions. With p- and n-type surface regions collecting charge carriers of different signs, electrical ﬁelds automatically develop at the wafer surface that keep the electrochemical corrosion process going. With the p /p process shown in Figure 25.16b, recesses in the silicon wafer up to 6 μm in depth could be formed. With the npn process in Figure 25.16c arrays of 300-nm thick Si cantilevers over 4-μm-deep recesses were formed. The photo-electrochemical np process, ﬁnally, allowed arrays of 300-nm Si cantilevers over 90-μm-deep grooves to be formed (Figure 25.16d). On the whole, these experiments revealed that suitably shaped doping proﬁles in Si wafers may be used to produce three-dimensional microstructures. The obtainable vertical dimensions of these structures could be varied over a range extending from those typical of surface up to bulk micromachining. As the process of PS formation is a largely isotropic one, vertical and lateral etch processes proceed at a similar rate. A perforation of the surface masking layers therefore needs to be considered when structures with large lateral extent need to be undercut. This problem is visualized in Figure 25.17. Another approach towards undercutting large lateral structures was undertaken by Zeitschel et al. [37]. These latter authors exploited the fact that the PS formation 418

Fig 25.17 ● (left) Platform consisting of n-type silicon as formed by the process displayed in Figure 25.16a; (right) perforation as a tool for undercutting large laterally extended structures.

process tends to follow the direction of the electrical ﬁeld lines inside an Si wafer. In order to produce electrical ﬁeld lines inside an Si wafer that drive the etch fronts into lateral directions the back surface of a p-type wafer was isolated by means of an n implantation. Ohmic p

backside contacts were only formed in those positions directly underneath an extended platform structure that had been delineated at the front surface using an ntype implantation. The electrical ﬁeld line distribution in such wafers and the resulting effects of ﬁeld focusing on the etch progress are shown in Figure 25.18. From the cross-section through an incompletely processed device the etch fronts can clearly be seen progressing

Porous Silicon Based MEMS

CHAPTER 25

Fig 25.18 ● (left) Electrical ﬁeld line focusing in a p-type wafer; (middle) lateral etching under conditions of ﬁeld line focusing; (right) backside of a fully processed n-type Si platform revealing four converging etch fronts.

Fig 25.19 ● pn junction embedded into an n-type passivation layer: (left) doping proﬁle; (middle) realized device structure; (right) IV characteristics of embedded diode.

from the peripheral p-type access holes at the front surface towards the p back-surface contact holes. Further evidence for an electrical ﬁeld line guided process can be obtained from the optical micrograph that has been taken on the back surface of a fully processed platform that had been broken free from its Si suspensions. An important extension of the base process sketched in Figure 25.16a is that active electronic functions can be integrated into free-standing silicon structures such as hotplates, cantilevers, etc. This possibility emerges from the fact that p-type regions embedded into an n-type well are electrically insulated from the bulk p-Si wafer by a reverse-biased pn junction ﬁeld. An etch process at the surface of the embedded p-type regions therefore cannot be sustained. A result obtained on a bidirectional thermal mass ﬂow sensor with a central heater meander and upstream and downstream pn-junction temperature sensors is shown in Figure 25.19. The embedded pn junctions exhibited diode ideality factors of n 2, indicating the dominance of recombination limited diode currents.

25.5.2 Passivation Layers The results above demonstrate how doping proﬁles in the subsurface regions of preprocessed Si wafers can be used to guide the PS formation process inside Si wafers to form three-dimensional microstructures with embedded

electronic devices. The example in Figure 25.18, in particular, has shown that in principle very large undercuttings are possible without employing dense patterns of perforation holes. Aiming at a high process yield, the above pn junction techniques need to be supplemented by more elaborate surface passivation techniques. The need for such supplementary passivation technologies arises out of the following problems and necessities: • Using unprotected n-type regions, large vertical and lateral etch depths cannot be reached. The reason is that etch rates in the order of a few micrometers per minute require cell voltages that signiﬁcantly exceed the turn-on voltages of Si pn junctions (0.6 eV). Under such conditions n-type layers tend to become corroded as well. • In case active electronic functions such as pn junctions are to be integrated into free-standing Si bridges, highly doped p and n regions are required which extend up to the free surface. When directly exposed to HF/H2O electrolytes, such regions tend to etch with a high rate. An extra protection therefore is required. • In case MOS capacitors and ﬁeld effect transistors are to be integrated, gate and ﬁeld oxides need to be protected against the aggressive liquid electrolyte. 419

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As PS formation occurs under conditions of current ﬂow, an obvious choice for improved passivation layers would be using electrically insulating dielectric layers. Standard oxide and nitride dielectric layers, in common use in the CMOS technology, however, are readily dissolved in HF/H2O electrolytes. A promising way out, however, was the discovery that hydrogenated amorphous silicon carbide (a-SiC:H) is highly resistant to HF [37]. Such layers can be deposited in plasma-enhanced chemical vapour deposition (PECVD) reactors at moderate deposition temperatures at around 300 to 350°C [46], containing high concentrations of bonded hydrogen [47]. With regard to bulk Si, such passivation layers possess a high level of built-in compressive stress, which can be lowered by thermal annealing and H-effusion. Soon after this discovery such layers were employed as masking materials in the PS sacriﬁcial layer technology [30, 48]. Lang and co-workers successfully demonstrated the fabrication of bolometers and thermal mass ﬂow sensors, using the PS technology. The beneﬁt obtained using a-SiC:H passivation layers instead of pn junction passivation techniques is shown in Figure 25.20. Whereas pn junctions readily fail as

p-Si

a-SiC:H

p-Si n-Si

n-Si

HF/H2O

HF/H2O

+

p-Si

+

F–

HF/H2O –

–

Fig 25.20 ● (left) pn junction passivation under zero-bias (top) and anodic bias (bottom) conditions; (right) a-SiC:H passivation layer on top of a conventional pn junction passivation structure under anodic bias (top); a-SiC:H passivation as deposited on top of an n Si contact region.

a-SiC:H

p-Si n-Si

the wafer-internal bias voltage becomes more anodic than 0.6 V, the a-SiC:H layers can easily withstand higher voltages because of their much larger bandgap (2.5 eV). Signiﬁcantly higher voltages and larger etch rates in p-type materials can therefore be employed without a residual attack on the n-type regions. Although being successful for small undercuttings and short PS formation times, a-SiC:H passivations showed a tendency to fail, once very long PS processing times in the order of several hours under high bias conditions were used. As shown in Figure 25.21, such ﬂaws, in general, were initiated in those areas which covered n regions on the Si wafer surface. Friedberger et al. [49] suggested that this problem is due to electron tunneling through the many localized bandtail states that abound in the amorphous a-SiC:H ﬁlms. This process, which is indicated in the bottom right-hand side of Figure 25.20, makes a-SiC:H accessible to a residual electrochemical attack. Once pinholes have been formed in the a-SiC:H, the underlying n Si layers are rapidly degraded, causing the a-SiC:H to lift off. A fully satisfactory solution with regard to passivation was found by Friedberger et al. [49]. These latter authors developed a double-layer passivation technique

n-Si

HF/H2O F–

+

–

n+-Si

Fig 25.21 ● (left) Mask design for an a-SiC: H passivation layer for enabling a large lateral underetching underneath an n-type platform structure. Two surface n regions for enabling contacting and heating of the hotplates can be seen in the periphery and extending into the four Si suspensions; (right) fully released Si platform showing ﬂaws in the a-SiC:H passivation layer after very long processing in HF/H2O.

420

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that consistently uses thin ﬁlms belonging to the standard repertoire of CMOS lines. These double layers consist of Si3N4, which is highly insulating but only moderately stable in HF, and poly-Si, which is stable in HF but unstable in case of an additional current ﬂow. In their passivation technique both layers cooperate in that the poly Si protects the underlying Si3N4 against the HF and in that the insulating Si3N4 prevents a current ﬂow through the topside poly-Si layer. The electronic performance of such passivation layers is demonstrated in Figure 25.22. With regard to a-SiC:H, the better performance of this double-layer passivation is explained by the still wider bandgap of Si3N4 and its largely reduced density of localized bandtail states that arise from the high-temperature deposition and the concomitantly increased structural order. Other attractive features of this double-layer technique are that the individual layer thicknesses can be adjusted to yield a low overall tensile stress and that both layers can be removed after the PS sacriﬁcial layer process, selectively, with regard to gate and ﬁeld oxide layers that might be used for the realization of active electronic devices inside the freestanding Si structures. Using this technique, large platforms with dimensions of approximately 500 μm 300 μm were successfully thermally insulated, as will be described further in Figure 25.30. The electronically

Fig 25.22 ● Band bending proﬁle through a poly-Si/Si3N4 passivation layer deposited on top of an implanted n/n region at the surface of a p-type wafer. A current ﬂow through the nitride layer is safely inhibited under anodic bias.

Fig 25.23 ● Protection of n surface areas by overlapping passivation layers.

CHAPTER 25

active components in the Si platforms withstand the PS sacriﬁcial layer process. Using the above kinds of passivation layers, special care needs to be taken when n surface areas need to be protected. As during activation and drive-in anneals, n

layers have a tendency to spread vertically and laterally, a sufﬁcient overlap of the passivation layers beyond the design size of the n regions needs to be taken into account. Very long PS formation processes could be sustained, allowing for 10-μm overlaps (Figure 25.23). An overview on passivation layer techniques and PS depths obtained with these techniques is presented in Table 25.1.

25.5.3 PS Stability Once the PS had been formed in predeﬁned areas of the wafer, the question arises of how to remove the PS with regard to the undisturbed bulk Si. The ease with which this can be done depends on the morphology of the PS: Highly porous NPS layers with extremely thin lamellae are easier to remove than lower-porosity materials with concomitantly thicker lamellae. Forming high-porosity NPS is clearly the method of choice in all those cases in which the PS removal is the ﬁnal processing step. In many sensor and actuator processes, however, this is not the case. In these latter cases additional lithography and thin-ﬁlm deposition steps need to be carried out on a sufﬁciently ﬂat PS surface. NPS material cannot be used under such circumstances, as these high-porosity layers tend to shrink and eventually to collapse as the NPS is removed from the etchant solution and dried to enable follow-on processing steps. Reasonably ﬂat surfaces can be obtained using lower-porosity material, albeit at the expense that such layers are harder to remove with good selectivity to the bulk Si. Turning to the problem of PS removal ﬁrst, we note that—depending on the porosity—the thickness of the lamellae in p-type PS can range from a few up to about 100 nm, depending on the initial doping and the PS processing conditions. Further considering that the entire PS network is accessible to a liquid etchant, removing a thickness of silicon corresponding to the average lamellae thickness means that an entire sacriﬁcial layer with vertical and lateral dimensions of 100 μm or more will be removed. As there is no chemical selectivity against the remaining bulk Si structures, bulk Si layers with a thickness comparable to the average lamellae thickness will be removed from the bottom of the n-type drive-in regions. Such small amounts of Si can easily be removed by roomtemperature KOH etching. As NPS exposes a huge surface to the KOH, care needs to be taken that the process of PS dissolution is carried out in a reasonably slow and controlled way. In order to avoid excessive formation of 421

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Table 25.1 Comparison of passivation layer techniques

Mask material

Etch rate

PECVD SiN

Undercut

Max. PS depth

Remarks

Reference

250 nm/min

Mask may delaminate in high-stress and over n

regions

[50]

PECVD SiC

None

Mask may delaminate in high-stress and over n

regions

[30, 48]

n-Implantation

None

1:1

Wafer thickness

Rough surfaces due to junction leakage at high cell voltages

[49]

SiO2/poly-Si

None

1:1

Wafer thickness

Underetching of SiO2; 50% of mask undercut

[50]

LPCVD SiN

25 nm/min

1:1

10–30 μm

Etch rate thickness dependent

[50]

LPCVD SiN/poly-Si

None

1:1

Wafer thickness

Negligible lateral etching of LPCVD SiN

[49]

Table 25.2 Porous silicon dissolution techniques

Etchant

Etch rate (μm/min)

Remarks

Reference

Diluted TMAH

1–5 μm/min

Fails after partial oxidation of PS

[50]

Diluted KOH

5–10 μm/min

Can be used on [49, 50] partially oxidized PS

10% HF

22–25 μm/min

To be used after dry [30, 48] oxidation of PS at 950°

Fig 25.24 ● Ease of PS sacriﬁcial layer removal following unintentional surface oxidation treatments.

H2 bubbles, the porosiﬁed Si wafers need to be processed through a cascade of increasingly more concentrated KOH (1%, 5%, 10%) solutions [30, 48, 49]. Another consequence of the high speciﬁc surface area of NPS is that, once formed, NPS layers may easily oxidize as the wafers are stored in the lab as they wait for further processing steps (see Figure 25.24). A short HF dip, therefore, might be necessary before processing through a KOH cascade. Concerning NPS dissolution, some authors also advocate for an intentional dry oxidation of the NPS at 950°C and subsequent removal of the porous SiO2 in dilute HF [30, 48] (Table 25.2). An advantage of this latter method is that excessive H2 bubbling is avoided. However, care needs to be taken with regard to mechanical stresses that may be generated upon oxidation of the NPS. Moreover, the use of dilute HF for the NPS removal requires that thin-ﬁlm structures on top of the wafer surface are either able to sustain such a treatment or that these are properly passivated. Another approach to removing PS sacriﬁcial layers is high-temperature annealing in a reducing H2 atmosphere. 422

In this way potential problems with unintentional PS oxidation are avoided and the nanometer-sized silicon particles in the NPS are caused to sinter and to evaporate onto the more massive bulk silicon structures in the immediate neighborhood. In this latter case cavities with smooth surfaces and well-deﬁned geometries can be obtained (cp. Chapter 25.6.3). The second issue relates to the problem of PS stability. PS stability is required whenever the sensor or actuator process requires lithography and thin-ﬁlm steps to follow the PS formation process. PS stability is related to the level of porosity and to the mechanical stability of the pore-separating Si walls. Ensuring PS stability, maintaining at the same time a sufﬁciently high porosity to allow easy PS removal, requires insight into those processes that determine the porosity of the PS layers. As detailed in Chapter 25.4, the elementary process of silicon removal is bond breaking, rebonding of the released Si atoms to the molecular and atomic constituents of the HF electrolyte, and ﬁnally forming dissolvable negative Si molecular ions. This elementary process of

Porous Silicon Based MEMS

CHAPTER 25

Fig 25.25 ● (a) Mass removed per square centimeter of wafer surface as a function of charge circulated through this same wafer area; (b) penetration of the PS etch front into the same wafers as in (a) as a function of the mass removed [51].

bond breaking and ion formation is operative in all kinds of silicon (p, p , n, n ) and also under all conditions of current ﬂow, illumination, and electrolyte composition. This universality of the key elementary process is reﬂected in Figure 25.25a which plots the mass removed from 1 cm2 of silicon wafer as a function of the charge that had been circulated through this same wafer area. The results of Figure 25.25a can be summarized as follows: d (Δm ) α PS dQPS

(25.4)

In this equation, Δm (g/cm2) is the mass removed from 1 cm2 of wafer surface and QPS (As/cm2) is the charge circulated through this same surface element. αPS (g/As) is a universal constant that characterizes the elementary etch process. From Figure 25.25a it follows that, in agreement with the explanations in Chapter 25.4, roughly two electronic charges need to be circulated through the wafer to remove a single Si atom from the surface: α PS 0.5 Si atoms/elementary charge

(25.5)

With QPS JPS t, it further follows that globally the mass removal rate is proportional to the current density JPS that had been applied in the PS formation process: d (Δm ) α PS ⋅ JPs dt

(25.6)

This once again applies to all kinds of silicon (p, p , n, n ) and all conditions of PS formation. This kind of universality is lost when one considers the progression of the etch front into silicon wafers with time, i.e., the etch rate. Figure 25.25b shows that in spite

of the universal behavior with regard to mass removal, etch fronts move at different speeds as wafers with different background doping are porosiﬁed. Figure 25.25b moreover shows that the silicon removal rate may vary as the etch front penetrates deeper into the wafers. These differences in etch front propagation can be related to changes in the PS morphology. Writing Δm πρSIL, an equation for the propagation of the etch front is obtained: ⎛ 1 ⎞ ⎛α ⎞ d (L ) ⎜⎜ ⎟⎟⎟ ⋅ ⎜⎜⎜ PS ⎟⎟⎟ ⋅ JPs ⎜⎝ π ⎠ ⎜⎝ ρ ⎟⎠ dt Si

(25.7)

Here L is the depth of the PS/bulk Si interface below the surface, ρSi and ρPS the bulk Si and the PS mass densities, and π the relative pore volume of the PS: π

ρ Si ρ PS ρ Si

(25.8)

The decisive factor in Eq. 25.7 is the porosity or pore fraction π, which characterizes the PS morphology. There have been many investigations into the phenomenon of pore formation. These reveal that π is largely a function of the following materials and processing parameters: ⎛ κ ⎞ π π ⎜⎜⎜doping, JPS ,illumination, Si ⎟⎟⎟ ⎜⎝ κel ⎟⎠

(25.9)

Here, κSi and κel stand for the speciﬁc resistivities of the Si wafer and the electrolyte, respectively. Concentrating on the processing of p-type Si wafers under dark conditions, the results of Figure 25.26 show that π varies with the current density JPS and the background acceptor doping NA. These latter data, in particular, reveal that mechanically stable PS material is largely 423

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produced using moderate current densities and relatively heavily doped p-type material. Following this strategy, most authors studying NPS sacriﬁcial layer technologies advocate using p-type material with speciﬁc resistivities in the range from 0.1 Ωcm to 20 Ωcm. Under these latter conditions reasonably ﬂat and stable PS surfaces can be obtained that allow photolithographic processing of thin-ﬁlm structures on top of the PS sacriﬁcial layers. Optimally ﬂat surfaces, which additionally allow high-quality epitaxial ﬁlms to be deposited, require p surfaces which produce dense low-porosity materials at the wafer surface. An interesting possibility is forming a heavily doped p-type surface on a moderately doped p-type substrate. In such a case a stable surface PS layer can be formed on an NPS layer with a much higher porosity in the subsurface regions. The possibilities arising out of this latter technique are further demonstrated in Chapter 25.6.3.

25.6 Application Examples Following the description of the individual technological building blocks, we present in this ﬁnal section a

Fig 25.26 ● Porosity π of PS as a function of the current density JPS and the p-type background doping [32].

number of device demonstrators using PS as a sacriﬁcial material.

25.6.1 Airbag Igniters An actuator application that promises a large market potential are airbag igniters. In a car accident, airbag igniters trigger an explosive charge that ﬁlls an airbag within milliseconds to reduce the effects of the impact on the passengers inside the car. Depending on the direction of the impact, several airbags need to be ﬁred in a precisely deﬁned time sequence to achieve optimum protection. Building such complex safety systems requires electronic airbag igniters to exhibit highly reproducible properties to allow successful integration into safety bus systems. Semiconductor technologies are best suited towards solving this problem: ﬁrstly because the silicon technology offers the required precision, and secondly because batch processing promises low cost. On a functional level, airbag igniters are one-shot thermal devices that become irreversibly destroyed when used. During use such igniter devices have to generate within a very short time temperatures much larger than the Si melting temperature, and they also need to generate an intense mechanical shock wave during the ignition event. Such requirements can be satisﬁed using silicon microstructures that exhibit the phenomenon of “explosive evaporation”. Semiconductor devices that exhibit this phenomenon can be made using PS sacriﬁcial layer technologies. Figure 25.27a shows that such a device consists of a heavily doped n-type silicon bridge formed at the surface of a moderately doped p-type silicon wafer. Such bridges can be formed by ion implantation and a subsequent drive-in diffusion. In a second step the doped silicon bridge is thermally insulated by forming PS in all those surface areas that were not converted to n-type conductivity. Figure 25.27b shows that in this way the doped silicon bridge becomes successively under-etched and thermally insulated by PS as the etching proceeds from the unmasked surface areas.

Fig 25.27 ● Airbag bridge igniter: (a) schematic device layout; (b) n-type silicon bridge thermally insulated from the p-type substrate by PS formation.

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The thermal insulation provided by the PS layer causes Joule heat to pile up inside the silicon bridge when current is passed through it. Figure 25.28 shows that the PS layer provides enough thermal insulation to allow heating the silicon bridge well beyond its melting point (Tm1412°C). Melting and recondensation of evaporated silicon is evidenced by the small silicon spheres deposited on the damaged substrate (Figure 25.28a). The phenomenon of explosive evaporation is further demonstrated by the data of Figures 25.28b–d. Figure 25.28b,c shows the current and light transients that occur during bridge heating. Figure 25.28c, in particular, shows in greater detail that a sharp current increase is observed after a short constant-current period (200 μs). This time delay corresponds to the time required for heating the bridge to its intrinsic temperature. After this temperature has been reached, the exponentially increasing conductivity of the silicon bridges causes large amounts of current ( 1 A) to be passed through the tiny bridge and huge amounts of heat to be generated there. As due to the thermal insulation this heat cannot be conducted away, a rapid thermal runaway occurs, leading to the phenomenon of explosive evaporation. This latter interpretation is corroborated by Figure 25.28d which displays the resistance variation as derived from the current and voltage transients that can be observed during the ignition process. From the electrical and geometrical data of the device it can further

CHAPTER 25

be ﬁgured out that peak power densities in the order of Pmax108W/cm3 are generated. In this way peak temperatures up to 3000°C may be attained and a mechanical shock wave is initiated as the evaporated silicon suddenly requires roughly 1000 times more space than the initial silicon bridge. Such conditions are favorable for triggering explosive charges as in airbag safety devices.

25.6.2 Field Effect Gas Sensors Building on the experience gained in the successful realization of airbag igniters, we have realized a second set of thermal devices, namely, micro gas sensors. Both metal oxide and catalytic gate ﬁeld effect devices have been realized. In this chapter we focus on this latter kind of device, as this can demonstrate the successful protection of delicate MOS devices that had been preprocessed into the ultimately freestanding silicon bridges. The entire process chain leading to such devices is shown in Figure 25.29, and ﬁnal results are displayed in Figure 25.30. Except for the formation of ﬁeld and gate oxides, the process chain of Figure 25.29 is largely the same as in the case of the airbag igniters. In summary, the PS sacriﬁcial layer process with the improved passivation layer technology allows for the fabrication of thermally insulated hotplates which serve as a platform

Fig 25.28 ● (a) Airbag igniter after explosive evaporation; (b) current and light transients through the Si bridge during the process of explosive evaporation; (c) current and light transients in the pre-explosion phase; (d) variation of the bridge resistance as evaluated from the measured current and voltage transients.

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for the described gas sensors. While the sensors can be operated at high temperature, the air cushion formed after PS removal ensures thermal insulation and, hence, low power consumption [53].

25.6.3 Pressure Sensors MEMS pressure sensors are widely employed in the automotive industry and other industrial sectors as well as in various kinds of medical instruments. Typical

Fig 25.29 ● Process sequence leading to thermally insulated catalytic gate ﬁeld effect gas sensors.

automotive applications include manifold absolute pressure (MAP) and barometric air pressure (BAP) measurement in engine control units. Other applications are tire pressure, fuel tank, or airbag monitoring systems [54, 55]. Micromechanical pressure sensors are also increasingly used in consumer electronics, as, for instance, in altimeters inside mobile phones or in climate-control and navigation systems. All applications demand smallsize, low-cost, and high-accuracy pressure sensors. In MEMS pressure sensors, the key element is a diaphragm containing piezoresistors which can be formed by ion implantation or in-diffusion. Applied pressure deﬂects the diaphragm and thereby changes the resistance of the piezoresistors. By arranging the piezoresistors in a Wheatstone bridge, an output signal voltage can be generated [55]. Since single-crystal silicon exhibits much higher piezoresistive coefﬁcients than poly-crystalline silicon, most piezoresistive pressure sensors employ single-crystal silicon membranes with integrated piezoresistors. Such sensors are conventionally fabricated by anisotropic etching with KOH [56], requiring expensive backside and wafer bonding processes. Advanced methods rest upon isotropic undercutting of single-crystal silicon layers epitaxially grown on expensive SOI substrates [57]. In the following, the surface micromachining Advanced Porous Silicon Membrane (APSM) technology is presented, which was ﬁrst introduced at Bosch in 2002 [58]. This method enables the fabrication of self-sealing singlecrystal silicon membranes covering a vacuum cavity by using PS as a smart sacriﬁcial material. The APSM process offers a high degree of freedom in designing different membrane geometries, a fully CMOS-compatible process

Fig 25.30 ● Top row: Results of sacriﬁcial layer etching (a) cross-section through the air cushion forming after the PS release; (b) catalytic gate MOS capacitor after removal of the Si3N4/poly-Si passivation layer. The n-type Si hotplate serving as a platform for the MOS capacitor has dimensions of approximately 500 μm 300 μm and a thickness of a few micrometers. Bottom row: (c) high-frequency CV characteristics of the MOS capacitor after PS formation, PS release, and passivation layer removal; (d) gas response towards a train of H2 pulses (bridge temperature 150°C).

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ﬂow, and a high level of integration. The membrane formation is embedded in a standard mixed-signal process to fabricate an integrated piezoresistive pressure sensor. Most of the necessary membrane fabrication steps are simultaneously used for the ASIC integration, with the anodic etching of the PS representing the only additional process step. Furthermore, this technology requires only frontside processing. Thus, very cost-efﬁcient integrated pressure sensors can be obtained. The main process steps of the APSM technology are (a) anodization, during which the silicon substrate is locally porosiﬁed by electrochemical etching in concentrated HF, (b) thermal rearrangement of the PS, and (c) epitaxial growth on top of the rearranged PS double layers.

25.6.3.1 PS as Seed Layer for Epitaxial Growth During the process of anodization, silicon atoms are dissolved from the crystal lattice. Since the remaining atoms stay on their atomic positions, the porous matrix retains its lattice arrangement. This allows for epitaxial growth of single crystal silicon layers on top of a PS seed layer. At elevated temperatures above 400°C in nonoxidizing atmospheres, PS starts to rearrange and coarsen its morphology [59]. The driving force is the minimization of the surface energy. In isolated pores the surface energy reduction is achieved by arranging surface atoms along crystal planes with the lowest speciﬁc surface energy {(100) and (111)}. This leads to faceted pore shapes. Further, pores can reduce their total surface area, which results in pore shrinkage. Considering PS double layers, it has been shown that the rearrangement leads to solidiﬁcation of the low porosity layer and dissolution of the high porosity one [60]. At the interface of PS and vacuum (equivalent to 100% porosity) the same effect leads to the sealing of surface pores.

p-Si

CHAPTER 25

However, the change of the PS morphology during thermal treatment is highly constricted by contamination of the internal surface with adatoms. A thin layer of native oxide, for example, stabilizes the morphology up to temperatures of 900°C in a nonreducing atmosphere [61]. Hence, to use thermal rearrangement of PS as a reproducible process step, any kind of surface contamination has to be avoided.

25.6.3.2 Fabrication A schematic overview of the membrane fabrication is shown in Fig 25.3.1. Starting material is a moderately p-doped silicon substrate with (100)-orientation. First, a deep n and a shallow p -implantation are performed in the substrate. Since the n -regions are not porosiﬁed during the anodization [62], they serve as lateral conﬁnements for the membrane regions inside the bulk substrate. The n -wells are designed as quadratic frames enclosing shallow p -areas. The p -areas subsequently serve as single crystal seed layers for the epitaxial growth of silicon. Additionally, a silicon nitride layer is deposited onto the wafer to avoid porous etching of the substrate surface except for the membrane regions themselves. The subsequent anodic etching in concentrated HF is performed in a double-cell arrangement as shown in Figure 25.31. The anodization is carried out in a two-step process. First, the p -Si layer is etched, using a low current density resulting in a mesoporous silicon layer with a porosity of about 45%. Second, the subjacent p-Si is anodized with an increased current density leading to an NPS layer with a porosity of about 70% buried underneath the mesoporous layer (Figure 25.31a). Afterwards, the silicon nitride layer is removed in the same HF cell (Figure 25.31b). In a chemical vapour deposition (CVD) reactor the substrate is then exposed to a H2 atmosphere at ambient pressure. At temperatures between 900°C and

p-Si

vacuum cavity

Fig 25.31 ● Process ﬂow of the APSM process: Si-substrate (a) before anodization, (b) after anodization, (c) after hydrogen prebake, (d) after single-crystal epitaxy.

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Mesoporous seed layer

Nanoporous cavity layer

Fig 25.32 ● Cross-sectional SEM micrograph after anodization of a mesoporous seed layer and a buried nanoporous cavity layer.

(a)

(b) 1 μm Sealed mesoporous Si

1 μm

Rearranged nanoporous Si

1100°C the hydrogen desorbs any residual native oxide from the PS surface. As soon as the oxide has been removed, both PS layers start to rearrange: The surface pores in the mesoporous layer are thereby sealed, while the buried NPS starts to merge into one single cavity (Figure 25.31c). In the same CVD reactor, an epitaxial Si-layer is grown, using the sealed mesoporous silicon as a seed layer. Upon completion of the epitaxial layer, all PS has completely rearranged leaving one single cavity (Figure 25.31d). The thickness of the epitaxial layer (10 μm) deﬁnes the membrane thickness. The hydrogen enclosed inside the cavity diffuses through the silicon during subsequent high-temperature processes, leaving a vacuum. Figure 25.32 shows the cavity region after anodization. In the whole membrane region a double porous stack with an upper mesoporous layer and a buried nanoporous layer was generated. Figure 25.33 displays the cavity region after hydrogen prebake. Driven by the minimization of the free surface energy, both PS layers start to rearrange. The buried NPS layer shows a coarsened morphology (Figure 25.33a). The surface of the enlarged pores is strongly faceted, which is due to the low surface energy of speciﬁc crystal faces. The upper mesoporous layer is sealed, providing the seed layer for the epitaxial growth (Figure 25.33b). Since the rearrangement of PS is a thermally 428

Fig 25.33 ● Cross-sectional SEM micrograph after hydrogen prebake, (a) rearranged NPS with strongly facetted pore surface and (b) sealed mesoporous seed layer.

activated process, it continues with each high-temperature process, even in the sealed cavity, until ﬁnally a single cavity is formed. Figure 25.34a, b shows the membrane and cavity regions after the deposition of an approximately 10 μm thick silicon membrane. The PS has now completely rearranged, creating a single vacuum cavity. The Si epitaxial layer is grown onto the sealed mesoporous silicon. Since the mesoporous silicon layer, and thereby the Si growth, is perfectly single crystalline, a high-quality single-crystal silicon layer is formed. The mesoporous layer is part of the membrane and has been completely smoothed by the thermal rearrangement (Figure 25.34a). Due to the vacuum inside the hermetically sealed cavity, the membrane is slightly bent under atmospheric pressure (Figure 25.34b).

25.6.3.3 Piezoresistive Pressure Sensor The APSM technology was successfully embedded into a standard mixed-signal process to fabricate an integrated piezoresistive pressure sensor for automotive applications [58]. By utilizing the high synergy between MEMS and ASIC fabrication, a cost-effective fabrication can be achieved. Figure 25.35a shows a fully processed MAP sensor chip. Four piezoresistors are implanted at the

Porous Silicon Based MEMS (a)

CHAPTER 25

Fig 25.34 ● (a) Cross-sectional SEM micrograph of single-crystal Si-membrane after epitaxial growth; (b) Optical micrograph of Simembrane. The enclosed vacuum leads to a deﬂection towards the substrate.

(b)

Si-epitaxy

Vacuum cavity

p-Si

5 μm

200 μm

Fig 25.35 ● Picture of a fully processed MAP sensor: (a) sensor element after dicing, (b) sensor element bonded to premold housing, and (c) complete sensor module.

membrane edges and connected into a Wheatstone bridge. The monolithically integrated ASIC provides a constant supply voltage and is also used for signal processing as well as for temperature and offset compensation. Figure 25.35b shows the sensor element bonded to its premold housing, and Figure 25.35c presents a view onto the complete sensor module.

25.7 Summary and Conclusions PS micromachining (PSSM) technologies form a group of technologies that build on the use of PS as sacriﬁcial layers. Release of the PS sacriﬁcial layers can result either in freestanding thin ﬁlm structures or in low-stress bulk silicon structures containing electronic elements such as piezoresistors, pn-junctions or MOS capacitors. PSSM technologies allow 3D silicon microstructures to be formed at the surface of silicon wafers without affecting the back surface of the wafers. The vertical dimensions of the released microstructures can range from a fraction of a micrometer up to several micrometers. The dimensions of air or vacuum gaps underneath released microstructures can range from a few micrometers up to the full wafer thickness. PSSM technologies

therefore combine the advantages of relatively massive bulk silicon microstructures with the advantages of top-surface silicon processing. PSSM technologies employ electrochemical etching in HF/H2O/ethanol electrolytes for the PS formation. As the PS formation is sensitive to the background doping and illumination of the silicon wafers, microstructures can be vertically delineated by forming suitably shaped surface and subsurface doping proﬁles in silicon wafers. Such proﬁles can be formed by ion implantation and drive-in diffusions. Lateral conﬁnement of the microstructures can be achieved by employing CMOS-compatible passivation layers such as low-pressure chemical vapour deposition (LPCVD) nitride and poly-silicon. Such layers can also be used to protect electronic elements embedded in bulk silicon microstructures from the aggressive HF/ H2O/ethanol electrolytes. Removal of the PS sacriﬁcial layers can be performed at the end of sensor and actuator process sequences, either using diluted silicon etches or by employing sintering and evaporation techniques. Full process compatibility with CMOS and mixedsignal electronic technologies has been demonstrated, and the ﬁrst industrial products based on PSSM techniques have been launched in the automotive markets. 429

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62.

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Detection of hydrocarbon species using silicon MOS capacitors operated in a non-stationary temperature pulse mode, Sens. Actuators, B 106 (2005) 489–497. M.J. Madou, Fundamentals of Microfabrication: The Science of Miniaturization, second ed., CRC Press, Boca Raton, 2002. M.-H. Bao, Micro Mechanical Transducers, second ed., Elsevier, 2004. H.-J. Kress, F. Bantien, J. Marek, M. Willmann, Silicon pressure sensor with integrated CMOS signalconditioning circuit and compensation of temperature coefﬁcient, Sens. Actuators, A 25 (1991) 21. Y. Suzuki, T. Kudo, K. Ikeda, Accurate, cost effective absolute pressure sensor, in: Digest of Technical Papers Transducers ’97, 1997, p. 258. S. Armbruster, F. Schäfer, G. Lammel, H. Artmann, C. Schelling, H. Benzel, H. Weber, H.-G. Vossenberg, J. Muchow, S. Finkbeiner, F. Lärmer, P Ruhter, O. Paul, Monocrystalline silicon membranes grown on sintered porous silicon for an integrated pressure sensor, in: Proceedings of SENSOR 2003, 2003, pp. 185–190. R. Herino, A. Perio, K. Barla, G. Bomchil, Microstructure of porous silicon and its evolution with temperature, Mater. Lett. 2 (1984) 519. N. Ott, M. Nerding, G. Müller, R. Brendel, H.P. Strunk, Structural changes in porous silicon during annealing, in: Proceedings of PSST, 2002, p. 36. A. Halimaoui, Porous Silicon – Science and Technology, Lecture 3, Springer, 1994. M.I.J. Beale, J.D. Benjamin, M.J. Uren, N.G. Jew, A.J. Cullis, An experimental and theoretical study of the formation and microstructure of porous silicon, J. Cryst. Growth 73 (1985) 622–636.

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Chapter Twenty Six

Atomic Layer Deposition in MEMS Technology Riikka L. Puurunen1, Hannu Kattelus1 and Tuomo Suntola2 1

VTT Technical Research Centre of Finland, Espoo, Finland Picosun Oy, Espoo, Finland

2

26.1 Atomic Layer Deposition: An Introduction Atomic layer deposition (ALD) belongs to the general class of chemical vapor deposition (CVD) methods, and it can be deﬁned as “a ﬁlm deposition technique that is based on the sequential use of self-terminating gas–solid reactions” [1]. ALD is known for its ability to deposit conformal inorganic material layers on complex threedimensional substrates and also for its subnanometer

scale precision and reproducibility. The systematic use of the self-terminating reaction chemistry in the growth process leads to the unparalleled nanoscale control of ALD ﬁlms, illustrated for example by the conformal ALD-Al2O3 layer grown inside a micromachined gear in Figure 26.1. The possibility of applying sequential self-terminating surface reactions for controlled modiﬁcation of oxide surfaces was reported as early as in 1967 [3]. The sequential processing for thin ﬁlm manufacturing was introduced in the 1970s as “Atomic Layer

Fig 26.1 ● Illustration of the unparalleled conformality of ALD ﬁlms, which can readily be utilized in MEMS. Aluminum oxide grown inside a MEMS gear by the ALD trimethylaluminum/water process. Source: Reprinted with permission from [2]. © 2003, American Institute of Physics.

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Epitaxy (ALE)” [4], originally for the production of electroluminescent thin ﬁlm displays, which became the only commercial application of ALD for almost twenty years. A renewed interest in ALD, with focus on semiconductor manufacturing, arose in the 1990s. Since the year 2000 ALD has become an enabling technology for readout heads of high-density hard disks and for high-packing-density DRAM memory chips. Both applications utilize the unequalled conformality of the ALD growth. In microprocessor manufacturing ALD is becoming a key technology for ultra-thin “high-k” gate dielectrics for 45 nm CMOS technology, thereby enabling the continuous performance improvement of processors in accordance with Moore’s law. Regarding MEMS, ALD is an emerging technology. The ﬁrst conference papers reporting ALD for MEMS appeared in 2002, and there appear to be no commercial MEMS products yet where ALD layers would have been utilized. There are indications, however, that ALD can in some cases be a truly enabling technology for certain MEMS designs. Our group at VTT for example has fabricated three-dimensional MEMS magnetometers using ALD-Al2O3 as a lowtemperature high-quality electrical insulator, whereas conventional PECVD silicon nitride proved to be unsuccessful [5, 6]. The purpose of this section is to acquaint a MEMS engineer with the basic operation principles of the ALD technique and brieﬂy introduce him/her to the already developed ALD materials and processes. More detailed descriptions of ALD can be found in recent reviews, of which we recommend those of Refs [1, 7, 8]. This chapter also describes the basic characteristics of ALD reactors, introduces some general characteristics of ALD ﬁlms, and brieﬂy reviews the applications suggested for ALD in MEMS so far.

26.2 Operation Principles of ALD ALD is a cyclic process based on repeated reaction cycles that consist of self-terminating reaction steps followed by a purge or evacuation step. Typically at least two reactants, a metal reactant and a non-metal reactant, are used. A schematic illustration of the four typical steps of an ALD reaction cycle is given in Figure 26.2. The ﬁrst step is the reaction of the ﬁrst reactant (typically the metal reactant); the second step, the removal of the unreacted reactant and the gaseous reaction by-products (a purge or evacuation); the third step, the reaction of the second reactant (typically the non-metal reactant); and the fourth step, again, removal of the unreacted reactant and the gaseous reaction by-products (a purge or evacuation). To increase the ﬁlm thickness, reaction cycles are repeated. 434

Substrate before ALD Step 1

Step 4 ALD cycle Step 2 Reactant A Reactant B

Step 3

By-product

Fig 26.2 ● Schematic illustration of an ALD reaction cycle. ALD growth occurs through repeating cycles consisting of steps of self-terminating reactions (Steps 1 and 3) separated by removal of the excess reactants and gaseous by-products by purge or evacuation (Steps 2 and 4).

The requirement of self-terminating reactions (i.e., saturating and irreversible) means that the reactions continue as long as there are suitable reactive sites on the substrates, after which the reactions stop by themselves. The amount of material adsorbed with time during the reaction and purge are illustrated in Figure 26.3 for self-terminating reactions as well as, for comparison, for other types of adsorption not suited for ALD. Complete separation of the reactions by purge/evacuation is needed in ALD to avoid simultaneous presence of the reactants in the gas phase and consequent uncontrolled CVD growth. With separate, self-terminating reactions, it is the details of the gas–solid interaction (the reactants, the process temperature, and the substrate) that deﬁne the amount of material deposited per cycle, making the process highly reproducible. Because of its operation principle based on separate, self-terminating reactions, ALD has many favorable properties. The most distinctive difference with other vapor-deposited ﬁlms is the conformality: Uniform ﬁlms can be grown at low temperatures on 3D structures with extreme aspect ratios (Figure 26.1). Other commonly acknowledged advantages include the uniformity of the ﬁlms, automatic control of the stoichiometry of the ﬁlms, high ﬁlm density, pinhole-freeness, easy process and thickness control, and low deposition temperatures. There are also two main limitations in ALD. The ﬁrst limitation is the slowness of the process: Typical growth rates on ﬂat substrates are in the order of 0.1–1 nm/ min. On substrates with high-aspect-ratio 3D topography, the rates are still lower. The slowness of the process is a direct consequence of the use of self-terminating reactions, which gives rise to all the favorable properties of ALD, also. The second limitation is the somewhat limited material and process selection. ALD

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Amount adsorbed

Amount adsorbed

(d)

(a)

Time

Time

Time

(e) Amount adsorbed

(c) Amount adsorbed

Amount adsorbed

(b)

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Time

Time

Fig 26.3 ● Examples of how the amount of material can vary with time in different types of adsorption followed by a purge (the starting of the purge is indicated by the vertical dashed line): (a) irreversible, saturating reaction (i.e., self-terminating reaction as in ALD), (b) reversible saturating adsorption, (c) a combination of irreversible and reversible saturating adsorption, (d) irreversible nonsaturating adsorption, and (e) irreversible, saturating adsorption not allowed to saturate.

relies on carefully selected surface chemistries, and proper chemistries do not exist (or have not yet been found/developed) for all materials that could be of interest for MEMS and other applications.

26.3 ALD Processes 26.3.1 General Requirements for the Reactants In ALD growth, reactants are transported through the gas phase to the growing ﬁlm. The reactants can be gases, liquids, as well as solid materials at room temperature, but they need to possess a sufﬁciently high vapor pressure at the temperature of their vaporization to enable transportation through the gas phase. The reactants must not decompose thermally, neither at the vaporization temperature nor at the ALD growth temperature. Ideally, the gaseous reaction by-products formed from the reactants during the ALD ﬁlm growth should not interact with the surface after desorption, and they should also be noncorrosive towards the substrate material and the reactor materials. In reality, however, compromises often need to be made regarding the reactivity and corrosiveness of the by-products.

26.3.2 Metal Reactants Several types of volatile metal compounds have been used as reactants in ALD. The most typical classes of reactants are illustrated in Figure 26.4. The metal reactants used in ALD can be roughly divided into two groups, inorganic and metal organic, and these can

be further categorized in elements, halides, alkyls, cyclopentadienyls, alkoxides, β-diketonates, alkylamides (silylamides), and amidinates [1]. Each type of reactant has its beneﬁts and drawbacks regarding reactivity, stability, gaseous by-products and impurities left in the ﬁlms. For example, alkyls, which are organometallic reactants containing a direct metal– carbon bond, are generally very reactive, but stable alkyls are not available for many metals and the deposition temperatures are limited because of the decomposition of the reactants. Chlorides, which belong to the general class of halides, are reactive, stable at a broad temperature range and available for many metals, but the deposited ﬁlms may suffer from chlorine residues and ﬁlm thickness gradients formed by secondary reactions of the HCl released in the metal chloride reaction. More detailed discussion on the metal reactants and their properties can be found, for example, in the reviews of Refs [1, 7].

26.3.3 Non-Metal Reactants The most commonly used types of non-metal reactants in ALD are the “hydrides” of the non-metal elements: water (H2O), ammonia (NH3), hydrogen sulphide (H2S), etc., that are used to grow oxides, nitrides, and sulphides, respectively. The advantage of these types of reactant is their generally high stability and reactivity in a broad temperature range, including high temperatures. However, these “hydrides” do not react efﬁciently with all types of metal reactants, and other types of reactants are sometimes needed. They may have oxidizing or reducing nature, or they can be “energy-enhanced” through the use of plasma. For a general description 435

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Cl

Typical metal reactants

“Thermal” ALD

Metal organic

M

M O

Chloride Isopropoxy (O iPr)

Organometallic

N M Diethylamido (NE t2)

O M Methyl (Me)

M Cyclopentadienyl (Cp)

M

O

Typical non-metal reactants

Inorganic

H2S

H2O NH3

Plasma-enhanced ALD

H2

N2 O2

2,2,6,6-Tetramethyl3,5-heptanedionato (thd)

Fig 26.4 ● Examples of metal and non-metal reactants used in ALD processes. The metal reactants can be simple inorganic reactants or more complex metal organic reactants, of which organometallic reactants (with a direct metal–carbon bond) form their own subclass. The non-metal reactants are most often simple molecules such as water, ammonia, or hydrogen sulphide. In PEALD, molecular elements are used.

of the many other types of non-metal reactants used in ALD, the reader is referred to more specialized reviews [1, 7]. Ozone is typically used for the deposition of metal oxides in combination with metal β-diketonate reactants. Water is often incapable of reacting with the particular metal reactant, whereas ozone can oxidize the organic ligands. Ozone not only oxidizes the ligands, however, but also the substrate surface, which may inhibit its use in some cases. The limited lifetime of ozone limits the use of ozone-based processes if structures with extreme aspect ratios are to be coated. In addition to using stable non-metal reactants in “thermal” ALD, more energetic reactants have been developed in various “energy-enhanced” forms of ALD, of which plasma-enhanced ALD (PEALD) is perhaps most important. In PEALD, the reactivity of non-metal reactants is increased by ionizing them with a plasma generator. The plasma can be either remote plasma or direct plasma, leaving the species interacting with the ﬁlm somewhat different. Both types of plasma can be used for reactants such as H2, O2, N2, and NH3. The use of plasma is in some cases the enabling method—for example, for making certain metallic ﬁlms, H2 plasma has been the only option. Deviation from “thermal ALD” and the use of PEALD also has drawbacks, however, such as more difﬁcult process control, more complex and therefore more expensive equipment, limited 3D coating capability (due to limited lifetime of the reacting species), and possible plasma damage to the samples. 436

26.3.4 Materials Made by ALD An abundance of ALD processes has been developed or tested over the years. Figure 26.5, from the review of Ref. [1], gives an overview of the two-element materials made in ALD investigations (up to February 2005). Most typically, ALD has been used for the growth of metal oxides, but there are many examples of metal nitrides and metal sulphides made by ALD. Other classes of compound materials made by ALD are selenides, tellurides, arsenides, and ﬂuorides. Rather recently, there has been a lot of interest and some successes also in the development of ALD processes for single-element ﬁlms, i.e., different metals. For further information on the individual processes, the reader is referred to the recent review by Puurunen [1] and its references.

26.3.5 Multi-Element Films by ALD In addition to two-element and single-element ﬁlms, there is also interest in the deposition of multi-element ﬁlms by ALD. Due to its high degree of control, ALD is very well suited for manufacturing multi-element ﬁlms. The elements can be evenly dispersed throughout the ﬁlm, or low concentrations of doping can be used. Multi-element ﬁlms can also be grown in the form of (nano)laminates, utilizing the nanometer-precision of ALD to engineer the material properties by controlling the layer thicknesses. It needs to be noted, though,

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Fig 26.5 ● Overview of the materials made by ALD using two-reactant ALD processes (as in February 2005).

that although combining different two-element ALD processes in multi-element processes may seem straightforward, unexpected effects can appear as a result of the interaction between the different reactants. Such effects can be, for instance, the etching of some ﬁlm constituents out of the ﬁlm, and the (catalyzed) decomposition of some of the reactants. Careful selection of reactants is therefore needed when multi-element ﬁlms are to be deposited.

26.4 Characteristics of ALD Processes and Films 26.4.1 Growth per Cycle in ALD Processes ALD is a cyclic process, and the material deposition in ALD occurs in discrete steps. A schematic representation of the mass changes during ALD processing is shown in Figure 26.6. During the reaction of the ﬁrst ALD reactant or the metal reactant (Step 1), the mass adsorbed typically increases, and during the following purge/evacuation (Step 2), the mass adsorbed stabilizes to a certain value. During the reaction of the second ALD reactant or the non-metal reactant (Step 3), the mass can either increase or decrease, depending on the mass difference of the ligands to be removed and the replacing surface species. During the following purge/evacuation (Step 4), the mass adsorbed again stabilizes to a given

Mass adsorbed

Source: Reprinted with permission from [1]. © 2005, American Institute of Physics.

Average deposition rate Growth per cycle

ALD cycles, (time)

Fig 26.6 ● Example of how the mass deposited can vary with the number of cycles (or time) in ALD. During the self-terminating reactions of the reactants (Steps 1 and 3), the mass deposited changes (the change can be positive or negative), and during the removal of the excess reactants and gaseous by-products (Steps 2 and 4), the mass deposited stabilizes to a given value.

value. The mass difference before Step 1 and after Step 4 gives the growth per cycle in ALD, which can be expressed as mass, thickness, atoms per unit surface area, etc. The slope of the growth curve (amount adsorbed vs. time) gives the average growth rate or deposition rate—although somewhat confusingly, it is quite common in ALD studies to term the amount deposited per cycle the “growth rate”. When expressed as thickness, the growth per cycle in ALD processes is commonly in the order of 0.01–0.1 nm, the particular value depending on the material, the reactants used, and the growth temperature. Contrasting the impression given by the name of the technique, “atomic layer deposition”, the growth per cycle is typically only a fraction (about 5–50%) of a monolayer of the material 437

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being deposited; full monolayer growth occurs only in exceptional cases. For most ALD processes, the origin of the particular values of growth per cycle are not properly understood or described. A favorable exception seems to be the widely studied ALD-Al2O3 process from AlMe3 and H2O reactants [1]. The growth per cycle can remain constant with temperature, increase with increasing temperature, or decrease with increasing temperature, gradually or in steps—the detailed value of the growth per cycle as well as the trend with temperature depend on the details of the surface chemistry of the particular process. Whatever the details, the temperature dependency of the growth per cycle and growth rate in ALD is weak when compared to other CVD processes.

26.4.2 Growth Mode in ALD Processes As in any other deposition process, there are different growth modes possible also in ALD. It is often assumed that ALD should follow the “layer-by-layer growth” or “two-dimensional growth”, which would result in atomically smooth layers. In some cases true layer-by-layer growth can be achieved, as is exempliﬁed by the indium arsenide–gallium arsenide superlattice in Figure 26.7. However, in processes where the growth per cycle is less than a monolayer, some three-dimensional growth in any case will take place. In addition, in several occurrences, island growth has been noticed to occur due to the lack of reactive sites on the substrate, exempliﬁed by the ZrO2 process on hydrogen-terminated silicon (Figure 26.7). Because of the deviation of ALD growth modes from perfect two-dimensional growth, a monolayer-equivalent of the ALD material typically does not yet cover the substrate fully, but a slightly thicker ﬁlm will be needed.

26.4.3 Conformality and Uniformity of ALD Films ALD leads by its nature to conformal growth of uniform ﬁlms even in highly demanding 3D topographies,

provided that the reactants used follow the basic ALD criteria and the processes are properly tuned to fulﬁll the saturation condition of the reactions. For a properly tuned, well-behaving ALD process, we estimate that a conformality of higher than 95% in high aspect ratio structures and thickness uniformity (one standard deviation) in the order of 1% should be achievable also on large wafer sizes (diameter 150, 200, 300 mm). It is not self-evident, however, that all processes studied as ALD automatically result in the growth of conformal and uniform ﬁlms. Proper tuning of the processes will be needed, especially for demanding aspect ratios, to ensure full saturation of the reactants and complete removal of the unreacted reactant and gaseous reaction products between the reactions. The choice of ALD reactor plays also a role in how well this can be achieved. Furthermore, it is possible that some processes that have been so far only studied in small research-scale ALD reactors will not completely fulﬁll the basic requirement of self-termination of the reactions because of non-idealities present in the process (e.g., reactant decomposition) that have remained unseen in the small-scale experiments. Consequently, such processes may be difﬁcult to scale up to the larger wafer sizes needed in MEMS fabrication. Also in PEALD, the aspect ratios where conformal growth can be achieved will inherently be limited by the stability of the reactants. PEALD is a rather new technique, and its limits have not yet been fully addressed.

26.4.4 Impurities in ALD Films In general, the impurity levels in ﬁlms grown in welloptimized ALD processes are low. However, some trace impurities originating from the ligands of the reactants can almost always be detected. For example, in Al2O3 ﬁlms grown from AlMe3 and H2O, low levels of carbon and hydrogen can always be measured (in the order of 0.1 at% for 300°C deposition), and in ﬁlms grown from metal chloride reactants, some chlorine can be detected. Many studies show that the

Fig 26.7 ● Illustration of the two extremes of the growth modes in ALD: (LEFT) TWO-dimensional growth in the ALD of indium arsenide– gallium arsenide superlattice growth. Reprinted with permission from [9]. © 1992 IEEE. (Right) Island growth in the ZrO2 deposition on hydrogen-terminated silicon. Reprinted from [10]. © 2002, with permission from Elsevier.

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impurity levels are often higher the lower the ALD temperature.

Sometimes, other parameters such as the reactant doses also play a role.

26.4.5 Pinholes in ALD Films

26.4.7 Stress of ALD Films

ALD is generally considered to produce pinhole-free ﬁlms. The deﬁnition of “pinholes” depends on the application, however, and especially for ﬁlms with thicknesses of just some nanometers, surprises with pinholes may sometimes be encountered. Perhaps the most typical reason for the presence of pinholes in ALD ﬁlms is the fact that ALD growth has been carried out on a substrate with low concentration of reactive sites, where the ALD growth can begin. In such cases, the ALD growth will occur in islands. The separation of the individual islands, as well as the average ﬁlm thickness at which complete closure of the ﬁlm occurs, depend on the characteristics of the substrate. In such cases, the average ﬁlm thickness may be even tens of nanometers before the substrate gets completely covered with the ﬁlm. Various treatments of the substrate surface, or the deposition of a thin “adhesion layer ”, may help in eliminating island growth. Also due to the less than monolayer growth in ALD, very thin layers (equivalent of some monolayers of material deposited) processed with ALD may not yet be fully continuous and cover the substrate completely. VTT’s experiments have shown, for example, that an ALD-Al2O3 ﬁlm of 1 nm is not yet functional as an etch mask in deep silicon etching, whereas 2 nm is already functional and “pinhole-free” in the etching experiment. Use of solid sources is often thought to lead to particulate contamination in ALD ﬁlms, which can result in pinholes. However, avoiding particle contamination from solid sources seems to be an issue of proper reactor engineering rather than an inherent problem related to the use of solid reactants in ALD.

Most ALD layers appear in compressive or tensile stress. Part of the stress originates from a purely thermal component due to the ALD growth at an elevated temperature and the subsequent cooling; differences between the coefﬁcients of thermal expansion are responsible for this. However, there may also be growth-related stress in the ﬁlms. Little systematic data has been published on the stress of ALD layers so far, and basic research on the stress issues needs to be made. Example of the stress of ALD-Al2O3 ﬁlms grown at VTT are shown in Figure 26.8 [6]. Krautheim et al. [11] and Tripp et al. [12] have also published results regarding the stress of ALD-Al2O3, and the results of different groups are roughly in agreement. The presence of a deposition-method-related stress component is evident on the basis of these results.

26.4.8 Chemical Stability of ALD Films The stability of ALD ﬁlms in different chemical environments depends mostly on the ﬁlm material itself but also to some extent on its deposition conditions, which affect the ﬁlm crystallinity, the impurity contents, and the stress. While some ALD-grown ﬁlms can be resistant in the most aggressive environments, some ﬁlms such as ALD-Al2O3 have been found to slowly dissolve even in deionized water [6]. A general trend is that the etch rates of the ﬁlms increase with decreasing ALD temperature. Such behavior has been detected, for example, by Puurunen et al. [6], who amassed

600

26.4.6 Crystallinity and Roughness of ALD Films Materials deposited by ALD can be amorphous, polycrystalline, or, in rare instances, single crystalline. Whether a ﬁlm grows amorphous or polycrystalline in ALD depends mainly on the material itself. Some materials, such as aluminum oxide, are amorphous at the typical deposition temperatures (say, at least 100– 500°C), regardless of the reactants they are made of. Many other materials tend to grow in crystalline form, but the extent of crystallization, the crystalline phase, and the roughness depend on reactants, the temperature, the substrate, and the thickness of the ﬁlm deposited.

Tensile stress (MPa)

0°

90°

400

200

0 0

100

200

300

ALD temperature (°C)

Fig 26.8 ● VTT data for the tensile stress of as-deposited ALDAl2O3 on silicon (100) as a function of temperature [6]. The solid lines show the contribution of the (estimated) thermal stress component. In addition to stress of thermal origin, there clearly is an intrinsic, deposition-method-related stress component.

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data for ALD-Al2O3 and TiO2 ﬁlms grown at different temperatures for a large collection of chemicals relevant to MEMS processing.

26.4.9 Patterning of ALD Films For effective use of ALD ﬁlms in MEMS fabrication, patterning methods for the ALD ﬁlms are needed. Since the use of ALD layers in MEMS is so recent, there is limited information of photolithographic patterning of the layers, and in general a lot of development is needed. The most commonly used ﬁlm material appears to be ALD-Al2O3, which can be patterned with both wet chemical methods (e.g., buffered HF, heated H3PO4; see Ref. [6]) as well as dry etching (etching with chlorine-based chemistries is used, e.g., at VTT). In recent years there have been interest and advances in “pre-patterning” ALD layers. Basically two methods have shown success: depositing the ALD ﬁlm on a prepatterned resist and performing a lift-off process afterwards, or using blocking agents to transform part of the surface into an unreactive state with respect to the ALD reactants. In principle, ALD indeed offers excellent possibilities for area-selective deposition, since the growth of ALD ﬁlms is based on the interaction of gaseous reactant molecules with surface reactive sites, and if reactive sites are absent, no growth can occur. In practice, the success of the surface blocking depends highly on the perfection of the blocking and the details of the ALD process (the reactants). More information on the details of area-selective ALD can be found in the recent review of Knez et al. [13].

26.5 ALD Reactors 26.5.1 Process Requirements, Reactor Types The basic requirement of an ALD reactor is to create conditions for the ALD process, to supply necessary reactants at the required reaction temperature, one at a time, into interaction with the substrate surface. A reaction cycle in an ALD process consists of at least two different reaction sequences separated by purge sequences. For high-quality ALD material a key property of a reactor is its ability for a strict separation of the process sequences. The reactor alone cannot guarantee qualiﬁed ALD material—the chemistry of the processes is exceedingly important, as well as proper handling of the chemicals. Favorable ALD chemistry assumes highly reactive reactants, resulting in a stable add-on layer as the reaction result on the substrate surface at each reaction sequence. For reasonable process times, a key property of an ALD reactor is its ability to rapidly switch between process sequences. The speed, however, is not only an attribute of the reactor, but it also depends, e.g., on the type and size of the substrates and reaction chemistry of the process. The surface-controlled material buildup in the ALD process ensures uniform thickness, provided that the dose of the reactant is adequate to give saturated monolayer coverage over the whole substrate in each reaction sequence. Surplus of reactant is removed from the reaction zone in the purge sequence following each reaction sequence. To prevent condensation of reactants,

26.4.10 Tuning the Material Properties by Nanolamination

440

Refractive index at 633 nm

Because of its control in the nanometer range, ALD offers great possibilities for the engineering of material properties by the growth of nanometer-range multilayers (“nanolaminates”) or mixed multi-element materials. By nanolamination of suitable materials with complementary properties, one can accurately adjust the properties of the layers. Optical, electrical, and morphological properties can in principle all be adjusted. Typical examples would be the engineering of the refractive index of a material by nanolamination of high and low refractive index materials, exempliﬁed by VTT’s results for the ALD-Al2O3/TiO2 nanolaminates in Figure 26.9, or engineering the dielectric constant of a material in a similar manner. Another characteristic example of utilizing nanolamination is the termination of crystallinity buildup in thick layers by incorporating thin amorphous ALD-layers to periodically terminate the crystalline growth.

2.5

2.3

2.1

1.9

1.7

1.5 0.0

0.2

0.4

0.6

0.8

1.0

Estimated TiO2 volume fraction

Fig 26.9 ● Example of engineering material properties by ALD nanolamination: the refractive index of Al2O3/TiO2 nanolaminates, grown at 150°C, as a function of the TiO2 content. The TiO2 volume fraction has been calculated from the cycling ratio, assuming a constant growth per cycle of 0.088 and 0.046 nm for Al2O3 and TiO2, respectively (Unpublished data by VTT).

Atomic Layer Deposition in MEMS Technology

the feeding lines from the reactant sources to the reaction chamber are kept at least at the temperature of the source. In most reactor designs the walls of the reaction chamber are kept at the process temperature. A result is that ALD growth of material occurs on the walls; however, condensation of reactants and possible gaseous reaction by-products are prevented and the formation of particles in the reaction zone is minimized. The surface control character of the ALD allows considerable freedom in supplying the reactants to the substrates. The reactant ﬂux may be supplied vertically upwards or downwards onto the substrate as in vacuum evaporation or CVD (Figure 26.10), but the ﬂux may also be supplied in the direction of the substrate surfaces (Figure 26.11). The latter case results in multicollision conditions for effective material utilization and also makes it possible to handle big batches of substrates in a small volume (Figure 26.12).

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26.5.2 Application Requirements, Figures of Merit The ﬁgures of merit of an ALD reactor are related to the demands of the processes, the application, and the operational properties of the reactor: Process requirements: – the ability of handling reactants with different

chemical properties at temperatures needed to create the necessary vapor pressures – the speed of supplying each reactant to the reaction

zone and into interaction with the substrate surfaces – the temperature range of the reaction chamber

needed for the processes to be used – supply of possible extra energy (plasma, RF-power,

ozone, etc.) needed in the process – the absence of particulates, as much as possible

(a)

– the speed and perfection of purging the surplus of

(b)

reactants and possible gaseous reaction products from the reaction zone after each reaction sequence Application requirements and productional aspects: – the type and size of the substrate or substrates – throughput, loading, and unloading of substrates – integration to production lines like cluster tools

Source controlled deposition

Surface controlled deposition

Fig 26.10 ● (a) Buildup of material in source controlled deposition processes like vacuum evaporation, sputtering, and CVD. The thickness of the resulting thin ﬁlm follows the effective rate of the reactant ﬂux onto the surface. (b) Buildup of material in surface controlled ALD process. Uniform thickness is obtained, provided that, in each reaction sequence, the reactant ﬂux is high enough to give full monolayer coverage on the whole substrate area.

Fig 26.11 ● Supply of reactants in the direction of the substrates results in high material utilization efﬁciency. The transport velocity of the reactant gas is typically in the range of 1–10 m/s. Thermal velocity of molecules in the transport ﬂux is up to two orders of magnitude higher, resulting in multiple collisions of the reactant molecules onto the substrate, thus ensuring an effective ﬁlling of available bonding sites on the substrate surfaces.

User demands, environmental and economical factors: – software with a user-friendly interface – in situ monitoring of the process – high material utilization capability – minimal number of parts needing cleaning or

maintenance and easy access to them A successful ALD process produces highly reproducible, uniform material layers on the substrate. The

Fig 26.12 ● The surface control feature of the ALD allows reactant feed through a cassette of substrates.

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result is a combination of the merits of the reactor used, the chemistry of the particular process, and the skills of the user to combine and optimize the capabilities of the reactor and the demands of the particular process. In well-designed reactors the need for cleaning and maintenance is minimized but still absolutely necessary for guaranteeing the desired result. In hot wall reactors all the walls and construction parts in the reactor zone are at the same temperature as the substrate, which means that ﬁlm growth occurs equally on all the surfaces. In well-designed hot wall reactors, such parts are either disposable or easily cleanable and recycled after a certain number of processes. The hot wall design assures a minimum risk for undesired side reactions at reactor walls. In cold wall reactors, following the traditional CVD reactor architecture, reactant or partial reaction results may condensate on the walls, which may result in impurity contamination in the ﬁlms grown. Reactors designed for research purposes may comprise a versatile selection of sources for gaseous, liquid phase, and solid reactants; a wide temperature range for both the source system and the processing space; and the ability to fast reaction sequence, as well as fast loading and unloading of the substrates. Versatility of the processing space regarding the shape and type of substrates may also be a demand of a research reactor. In MEMS production, the dominant substrate format is 150-mm silicon wafers, but 200-mm process lines are rapidly emerging. ALD reactors for medium-sized wafers have been available only recently. Production reactors are designed for a deﬁned process, for speciﬁc substrates and for throughput. A production reactor may be a part of a cluster tool which deﬁnes the loading and unloading systems of the reactor. Production environment sets tough requirements to the handling of reactants and the cleaning and maintenance procedures to ensure failure-free operation.

26.5.3 Building Blocks of ALD Reactors Main building blocks of an ALD reactor are illustrated in Figure 26.13. A reactor shall be equipped with source systems for all reactant types (gaseous, liquid, solid) needed in the processes speciﬁed. Sources are equipped with a heating system to keep each reactant at the temperature needed to generate the necessary vapor pressure. To prevent condensation of reactants in the feeding lines and valves, both the lines and valves are kept at least at the source temperature of each reactant. Transport of the reactants from the sources to the reaction chamber may be enhanced with inert gas ﬂow during the feeding sequences. Reactant valves are critical parts of an ALD reactor. During their effective lifetime, valves perform fast pulsing of reactants thousands or even millions of times at a temperature characteristic to each reactant. Some reactants are chemically aggressive materials which limit the choice of construction materials of the valves. Typical opening and closing times of ALD valves are from 0.1 to 1 second. In presently used reactors pneumatic valves with an elastic seal are most commonly used. Valves with an elastic seal allow reactant temperatures up to about 200°C. At temperatures above 200°C reliable valving is obtained by controlling the reactant ﬂow with inert gas [14]. Inert gas valving allows pulsing practically without temperature limitations other than that set by the material used in the reactant feeding lines. For preventing material buildup in gas lines, reactants reactive with each other are fed to the reaction chamber in separate feeding lines.

26.5.4 Operational Aspects Most ALD reactors are designed for operation at inert gas atmosphere at pressures from 1 to 10 mbar. The inert gas, typically nitrogen, is used for the transport of the

HL

B

V

L

Z S

LC

HZ

Hs G SA

SB

F

P

C

Fig 26.13 ● Main building blocks of an ALD reactor. SA, SB: sources for metallic and non-metallic reactants; V: reactant and purge gas valves feeding lines; G: purge gas supply; Z: the reaction zone; B: reactor body, vacuum chamber; HS, HL, HZ: heating system for sources, gas lines, and the reaction zone; C: control system for valving and temperatures; L, LC: load lock and the loading/unloading system for the substrate (S); F: ﬁlter in the exhaust line; P: vacuum pump.

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reactants from the sources to the reaction zone and for effective purging of the surplus of the reactant and possible gaseous reaction results after each reaction sequence. For low impurity concentration in the inert gas and for effective spreading of the reactants on substrate surfaces in the reaction chamber, a low inert gas pressure is advantageous. The lower limit of the inert gas pressure is set by the demands of effective transport and purging which are dependent on the reactor geometry and volume, as well as the type of reactants used. The reactant pressure in a reaction sequence shall be sufﬁciently high to supply the necessary number of reactant molecules to the substrate surface during the reaction sequence. The number of atoms on a solid surface is of the order of 1015 atoms/cm2, which gives the maximum density of reactant molecules to be captured by the substrate surface in a reaction sequence. The number of molecules in an ideal gas is N pV/kT, which, at the temperature of 500 K, corresponds approximately to 1015 molecules per mbar·cm3. The necessary dose of reactant in a reaction sequence is roughly D (mbar cm3) A(substrate)(cm3)/η, where η is the material utilization factor characteristic to the particular reaction and the reactor used.

26.6 Applications for ALD in MEMS

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often operate at temperatures around 200–400°C— although one must note that this rule is only a rough guideline, and the temperature range of each process depends on the reactant pair used. The ﬁrst signiﬁcant deviation from the rule is the ALD of dielectric layers for thin-ﬁlm electroluminescent devices, in use in large-scale production, where the growth is based on metal chloride reactants and the ALD temperature is around 500°C. There are also ALD processes that work at very low temperatures, even close to room temperature (e.g., the trimethyl aluminum/water process to deposit Al2O3), as well as ALD processes that fulﬁll the ALD criteria even at high temperatures such as 800°C (e.g., the hafnium tetrachloride/water process to deposit HfO2). The materials, deposition temperatures, and the resulting ﬁlm conformality of ALD are compared to those of “conventional” MEMS layer deposition techniques in Table 26.1. In conventional MEMS processing, there are methods capable of low-temperature layer deposition (PECVD, sputtering, spinning) as well as methods resulting in highly conformal ﬁlm growth (Si oxidation, LPCVD polysilicon and silicon nitride). However, the combination of low-temperature growth and conformality is unique to ALD. It is evident that the low-temperature growth combined with conformal ﬁlm deposition can lead to many applications for the ALD technique in MEMS fabrication.

26.6.1 General The use of ALD in MEMS is attractive, since ALD can increase the material selection available for MEMS processing as well as offer layers with complementary properties, compared to the traditional MEMS fabrication techniques. Since ALD is best suited for the deposition of nanometer-range ﬁlms, in MEMS, the role of ALD will most likely be the modiﬁcation of structural elements with thin “assisting” layers rather than their use as structural layers. If and when the NEMS (nanoelectromechanical systems) era will begin, the typical thicknesses of ALD layers may be suitable for their use as structural layers, as well. In the following, we ﬁrst compare ALD with the traditional MEMS layer deposition techniques and then brieﬂy review the published examples of the use of ALD layers in MEMS. Another recent review of the use of ALD in MEMS was published by Stoldt [15].

26.6.2 ALD vs. Other MEMS Layer Deposition Techniques ALD is a ﬁlm deposition method known to result in conformal ﬁlms at rather low deposition techniques. As a rule of thumb, we generalize that ALD processes most

Table 26.1 Film conformality obtained with different deposition methods, with typical materials and temperatures for each method indicated

Layer deposition method

Typical materials

Typical deposition temperatures

Film conformality

Si oxidation

SiO2

800°C

Excellent

CVD

Si, SiO2, Si3N4, …

400°C

Good

PECVD

SiO2, Si3N4, …

150°C

Poor

Sputtering

Mo, Al, Au, …

50°C

Poor

Spinning

Photo resist

100°C

Poor

ALD

Metal oxides, metal nitrides, …

Excellent Typically 200–400°C, but even down to room temperature and up to 800°C, depending on the process (i.e., the reactant pair)

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26.6.3 Materials with Speciﬁc Electrical Properties Aluminum oxide is perhaps the most common material to be grown by ALD, and it has also been used in MEMS applications for low-temperature conformal growth of electrically insulating layers. Hoivik et al. [16] demonstrated ALD-Al2O3 as an electrically insulating coating in electrostatically actuated, released polysilicon cantilever beams. In VTT’s work, ALD has even been an enabling technology in the design of a rather complex process for fabricating a 3D micromechanical compass based on the Lorenz force [5]. In this compass design, metal hillocking limited the further processing to below 250°C, and since a pinhole-free electrical insulator was needed between the coil metallization, ALD Al2O3 was used. The fabrication was successfully ﬁnished, and the components performed as modeled [5]. ALD-Al2O3 has also been used as a low-temperature insulating ﬁlm in optical switches [17]. The development of “high-k” ALD ﬁlms, which are insulating dielectric ﬁlms with a high dielectric constant, have been the subject of intense worldwide research efforts since the late 1990s due to their interest in IC manufacturing. High-dielectric-constant ALD dielectrics have promising applications also in MEMS, in RFMEMS in particular. Potentially, in RF-MEMS switches one could at the same time maximize the down-state capacitance of the switch through the high dielectric constant and, through proper engineering of the leakage current, prevent charging of the dielectric through buildup of static charge. Consequently, it should be possible to avoid or postpone stiction failure. For the purpose of simultaneously processing a high-k material and controlling the leakage current, nanolaminates of Al2O3 and ZnO were proposed [15, 18]. The resistivity could be controlled to some extent, and the dielectric constant κ was 7.

26.6.4 Materials with Speciﬁc Optical Properties For optical applications, the controllability of ALD layers in the nanoscale is a clear advantage. The layer thicknesses of single dielectric ﬁlms can be accurately controlled, and it is possible to grow stacks of layers for application, for example, as anti-reﬂection and highreﬂection coatings, beam splitters, and Fabry–Pérot ﬁlters. Nanolamination further enables the accurate tailoring of the optical properties of the material. There are few examples where ALD layers have been applied for optical purposes in MEMS (MOEMS). Tripp et al. [19] manufactured multilayers consisting of 1.5 nm Al2O3 and tungsten (W) ﬁlms by ALD for X-ray 444

reﬂectivity enhancement of poly-silicon micromirrors, taking advantage of the nanoscale control of ALD growth. Hahtela et al. [20] demonstrated a quarterwavelength layer of ALD-Al2O3 on silicon oscillators as an anti-reﬂection coating.

26.6.5 Materials with Speciﬁc Chemical and Other Properties A variety of materials has already been deposited with ALD (Figure 26.5), and there are certainly still possibilities of developing completely new ALD processes. It is therefore evident that materials can be implemented in MEMS with properties aimed for a certain application, e.g., inertness in certain environments, biocompatibility, lubrication, anti-stiction properties, etc. Chemical inertness in certain environments can evidently be beneﬁcial for MEMS. The inertness can be taken advantage of during the fabrication of the MEMS devices, for example, as mask layers or etch stop layers, or alternatively, as surface modiﬁcation that protects the ﬁnal MEMS device in aggressive environments (passivation). The environment could also be protected from the MEMS device, as would be the case for biocompatible coatings. ALD-Al2O3, for example, has exhibited extraordinary properties in the deep etching of silicon: Etch selectivity of Al2O3:Si on the order of 1:50000 has been obtained, enabling the use of just some nanometers-thin Al2O3 layers as effective mask and etch stop layers in deep silicon etching [21, 22]. ALD-Al2O3 and TiO2 have also functioned as mask layers in the HF vapor etching of sacriﬁcial SiO2 layers [23]. ALD layers can also be used to protect the underlying MEMS structures in thermal treatments in various gas environments. ALD-Al2O3 coating of Au/Si beams was found to suppress the inelastic deformation of the beams during isothermal holding [24, 25]. ALD-Al2O3 layers protected also Au/Cr/Si microcantilevers during low-temperature annealing, by partly stabilizing the structure and by preventing the diffusion of Cr and grain boundary separation [26]. The reduction of friction by depositing a thin layer by ALD has been the focus of several studies. For this purpose, “conventional” ALD materials have been used, such as Al2O3 [2, 16], TiO2, and ZrO2 [27], with improved results compared to the lubricating and wearresistant properties of the native oxide of silicon. Also, a new ALD process has been deliberately developed for friction reduction, namely, the WF6/H2S ALD process to deposit solid WS2 lubricant [28, 29]. The use of nanometer-thin ALD layers to alter the chemical properties of the MEMS surfaces in order to adsorb certain molecules (adhesion layers) has gained attention, especially regarding the reduction of stiction

Atomic Layer Deposition in MEMS Technology

problems through the use of hydrophobic coatings [30]. Similar hydrophobic coatings, generated by adsorbing a hydrophobic monolayer on ALD-Al2O3, has been used to prevent moisture penetration in small openings of MEMS devices [31]. ALD has also been proposed for the fabrication of nanoscale energetic materials for MEMS. A metastable intermolecular composite of Al–SnO2, where the SnO2 was made by ALD, showed the desired quick and violent reaction [32].

26.7 Outlook ALD can offer signiﬁcant advantages in MEMS processing compared to traditional ﬁlm deposition methods, when modiﬁcation of the surfaces with ﬁlms in the thickness range of nanometer to tens of nanometers are

CHAPTER 26

needed. Combining the low-temperature deposition with near-perfect ﬁlm conformality is an obvious beneﬁt of ALD ﬁlms. This can be further combined with the deposition of ﬁlms with special electrical, optical, chemical, or other functionalities, or with ﬁlms of engineered properties that have been achieved through nanolamination. ALD is a newcomer to the MEMS ﬁeld and also to the integrated circuit industry. However, since recently, there are several vendors offering new reactors suitable for MEMS research, development, and small-scale fabrication on 100- to 200-mm wafers. Although ALD layers are in many aspects attractive to MEMS fabrication, the suitability and competitiveness of ALD depends on the needs and speciﬁc requirements of the particular MEMS application. What will be the ﬁrst breakthroughs in the use of ALD in MEMS fabrication remains to be seen.

References 1. R.L. Puurunen, Surface chemistry of atomic layer deposition: a case study for the trimethylaluminum/water process (review article), J. Appl. Phys. 97 (2005) 1–52 Art. 121301. 2. T.M. Mayer, J.W. Elam, S.M. George, P.G. Kotula, R.S. Goeke, Atomic-layer deposition of wear-resistant coatings for microelectromechanical devices, Appl. Phys. Lett. 82 (2003) 2883–2885. 3. A.M. Shevjakov, G.N. Kuznetsova, V.B. Aleskovskii, Interaction of titanium and germanium tetrachlorides with hydroxylated silicon dioxide, in: Proceedings of 2nd USSR Conference on High Temperature Chemistry of Oxides, November 26–29, 1965, Leningrad, USSR: Nauka, 1967, pp. 149–155 (in Russian). 4. T. Suntola, J. Antson, Method for producing compound thin ﬁlms, US Patent 4 058 430, November 15, 1977. 5. J. Kyynäräinen, J. Saarilahti, H. Kattelus, T. Meinander, M. Suhonen, A. Oja, H. Seppä, P. Pekko, H. Kuisma, S. Ruotsalainen, M. Tilli, 3D micromechanical compass, Sensor Lett. 5 (2007) 126–129. 6. R.L. Puurunen, J. Saarilahti, H. Kattelus, Implementing ALD layers in MEMS processing, Electrochemical Society Transactions, Vol. 11, Iss 7 (3rd Symposium on Atomic Layer Deposition Applications), 2007, pp. 3–14. 7. M. Ritala, M. Leskelä, Atomic layer deposition, in: H.S. Nalwa (Ed.),

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Handbook of Thin Film Materials, Vol. 1, Academic Press, 2002, pp. 103–159. H. Kim, Atomic layer deposition of metal and nitride thin ﬁlms: current research efforts and applications for semiconductor device processing (review article), J. Vac. Sci. Technol. B 21 (2003) 2231–2261. A. Usui, Atomic layer epitaxy of III–IV compounds: chemistry and applications, in: Proceedings of the IEEE, vol. 80, 1992, pp. 1641–1653. W.F.A. Besling, E. Young, T. Conard, C. Zhao, R. Carter, W. Vandervorst, M. Caymax, S. De Gendt, M. Heyns, J. Maes, M. Tuominen, S. Haukka, Characterization of ALCVD Al2O3– ZrO2 nanolaminates, link between electrical and structural properties, J. Non-Cryst. Solids 303 (2002) 121–133. G. Krautheim, T. Hecht, S. Jakschik, U. Schroder, W. Zahn, Mechanical stress in ALD-Al2O3 ﬁlms, Appl. Surf. Sci. 252 (2005) 200–204. M.K. Tripp, C. Stampfer, C.F. Herrmann, C. Hierold, S. George, V.M. Bright, Low stress atomic layer deposited alumina for nano electro mechanical systems, in: Technical Digest of the 13th International Conference on Solid-State Sensors, Actuators and Microsystems, Transducers ’05, Seoul, Korea, June 5–9, 2005, pp. 851–854. M. Knez, K. Nielsch, L. Niinistö, Synthesis and surface engineering of complex nanostructures by atomic

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(Eds.), Proceedings of SPIE, vol. 5720, Micromachining Technology for MicroOptics and Nano-Optics III, 2005, pp. 241–251. O. Hahtela, P. Sievilä, N. Chekurov, I. Tittonen, Atomic layer deposited alumina (Al2O3) thin ﬁlms on a high-Q mechanical silicon oscillator, J. Micromech. Microeng. 17 (2007) 737–742. J. Dekker, K. Kolari, R.L. Puurunen, Inductively coupled plasma etching of amorphous Al2O3 and TiO2 mask layers grown by atomic layer deposition, J. Vac. Sci. Technol. B. 24 (2006) 2350–2355. N. Chekurov, M. Koskenvuori, V. M. Airaksinen, I. Tittonen, Atomic layer deposition enhanced rapid dry fabrication of micromechanical devices with cryogenic deep reactive ion etching, J. Micromech. Microeng. 17 (2007) 1731–1736. W.S. Yang, S.W. Kang, Comparative study on chemical stability of dielectric oxide ﬁlms under HF wet and vapor etching for radiofrequency micro electromechanical system application, Thin Solid Films 500 (2006) 231–236.

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layer deposition of tungsten disulphide solid lubricant thin ﬁlms, J. Mater. Res. 19 (2004) 3443–3446. T.W. Scharf, S.V. Prasad, M.T. Dugger, P.G. Kotula, R.S. Goeke, R.K. Grubbs, Growth, structure, and tribological behavior of atomic layer-deposited tungsten disulphide solid lubricant coatings with applications to MEMS, Acta Mater. 54 (2006) 4731–4743. C.F. Herrmann, F.W. DelRio, V. M. Bright, S.M. George, Conformal hydrophobic coatings prepared using atomic layer deposition seed layers and non-chlorinated hydrophobic reactants, J. Micromech. Microeng. 15 (2005) 984–992. H.V. Panchawagh, F.F. Faheem, C.F. Herrmann, D.B. Serrell, D.S. Finch, R. L. Mahajan, A ﬂip-chip encapsulation method for packaging of MEMS actuators using surface micromachined polysilicon caps for BioMEMS applications, Sens. Actuators, A 134 (2007) 11–19. C. Rossi, K. Zhang, D. Esteve, P. Alphonse, P. Tailhades, C. Vahlas, Nanoenergetic materials for MEMS: a review, J. Microelectromech. Syst. 16 (2007) 919–931.

Chapter Twenty Seven

27

Metallic Glass Parmanand Sharma and Akihisa Inoue Institute for Materials Research, Tohoku University, Sendai, Japan

27.1 Introduction Nanotechnology is frequently discussed these days as an emerging frontier for the development of various future devices. Micro and/or nanoelectromechanical systems (MEMS/NEMS) are the basis of future nanotechnologies, because they combine miniature sensors and actuators with electronics. Progress in this field demands the capability to fabricate nanostructures in a variety of materials with accuracy at the nanometer scale and sometimes at the atomic scale. Nanofabrication aims at building nanoscale structures, which can be adopted as components, devices, or systems, in a large quantity with potentially low costs. The past three decades have seen the critical length scales of the component devices decreased by a remarkable amount, from 15 μm in the case of the first integrated circuit, to the 180 nm routinely obtained today [1]. Can this phenomenal rate of increase in integration density be sustained indefinitely? The answer is clearly negative, in the sense that the size of the constituent atoms imposes a fundamental limit on the minimum length scale that can be ultimately attained. But even if the current rate of miniaturization continues apace, this fundamental limit remains many years off; the challenges faced by the microelectronics industry are more immediate.

27.1.1 Lithography Issues For example, the resolution limit in conventional projection optical lithography is determined largely by the well-known Rayleigh’s relation. To obtain higher resolutions, shorter wavelength light and lens systems with

larger numerical apertures are required. In general, the minimum feature size that can be obtained is almost the same as the wavelength of light used for the exposure. At present, the most advanced mass-produced large-scale integrated (LSI) circuits have a critical dimension of 180 nm. This is achieved by using partially coherent light from a KrF excimer laser with a wavelength of 248 nm, in combination with some resolution-enhancement techniques such as off-axis illumination, phase shift mask, and optical proximity correction, as well as advanced resist systems. To further reduce the critical dimension, wavelength reduction is being actively pursued. The semiconductor industry is pushing to reduce pattern sizes down to 22 nm by 2010. The challenges of following such a road map are multifold, and one of the biggest challenges is to create nanoscale patterns. As the pattern size decreases, the fabrication cost and the complications involved in obtaining the nanoscale structures also increase drastically, which resulted in several other techniques for delineating patterns below 100 nm. These include electron beam lithography, nanoimprint lithography (NIL), near-field optical lithography, and direct patterning on a nanoscale with scanning probe microscope and focused ion beam (FIB) techniques [2–9]. Critical issues such as resolution, speed, reliability, and accuracy of patterns all need to be considered in developing these new lithographic techniques. In the context of mass production of nanoscale structures, most of these techniques have low throughput capability with a high production cost. However, NIL is one of the most promising technologies for the fabrication of future nanostructures/devices, because of excellent resolution (sub-25 nm), high throughput, ease of use, and costeffective process. A rich variety of literature is available 447

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on different types of lithographic techniques [2–9]. As the present chapter aims to describe the fabrication of metallic nanostructures using imprint lithography therefore, here we will discuss this process further. Imprint lithography is basically a molding process in which the features on the mold or die define the patterns created on the bulk/thin films of polymer/glass. The process of imprint lithography is described in Figure 27.1. In conventional imprint lithography, a thin film of polymer is spun on the substrate or a material to be patterned. The mold is pressed against the substrate coated with the polymer film and placed on a stage that is heated up to a certain temperature known as imprinting temperature. The imprinting temperature is normally above the glass transition temperature, Tg (the temperature above which the material behaves like a liquid) of the polymer thin film. A certain amount of time is required for a thermal equilibrium to be reached, usually known as imprinting time. After the nanoscale features of the mold have been imprinted, the mold is removed. The removal of the mold and the substrate coated with a polymer film takes place below the Tg of the polymer coating. For proper imprinting of mold features on the polymer thin film, optimization of imprinting conditions such as temperature, pressure, and the time of imprinting is required. Once the mold features are replicated in the polymer film, an anisotropic etching process such as reactive ion etching (RIE) is used to remove the residual polymer film left in the compressed areas. The leftover polymeric patterns on the substrate can be used as a mask for dry etching or deposition of another film material or

as a functional element for some other purposes. A similar process can be applied to bulk polymer to obtain the high-aspect-ratio microstructures (Figure 27.1b). Imprint lithography appears to be a simple process for fabrication of 10- to 100-nm-range features at affordable cost. However many issues need to be addressed. A multilevel capability that requires level-to-level alignment is one of the major issues that needs to be solved. Piezo-driven techniques appear to have the potential of alignment on the order of 10 nm. Another issue is the thermal expansion coefficient of mold and the substrate, which is important when a temperature over 100oC is typically required in the imprinting step. A thermal mismatch between the die and the substrate where patterns are being transferred can result in pattern distortion or a stress buildup during the cooling cycle, which can affect the pattern fidelity. Often it is desirable to do patterning at low temperatures or reduce the thermal expansion mismatch. Also, the imprinted patterns should maintain their mechanical integrity during separation of mold from the substrate. In the imprinting process the most widely used resist material is PMMA poly (methyl methacrylate). A great opportunity exists for developing new materials for mold and the substrate.

27.1.2 Materials-Related Issues We have discussed the lithographic techniques useful for fabrication of nanoscale structures. Nevertheless, lithographic techniques are not the only important issues in

Fig 27.1 ● (a) Conventional imprinting/ nanoimprinting (NIL) process utilizing thin ﬁlms on a substrate for fabrication of nanostructures, and (b) imprinting or hot embossing process utilizing bulk materials.

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the fabrication of nanoscale structures; there are several materials-related issues. Materials selection for MEMS/ NEMS fabrication is based on the careful consideration of the material’s properties with regard to its intended application [10, 11]. For example, many MEMS devices such as pressure, chemical, and biosensors rely on actuation of membrane structure, and require a high-fracture toughness material for enhanced durability and shock resistance [12, 13]. On the other hand, for fabrication of controlled nanostructures, the material should be machinable down to the atomic level. Currently, the materials used for MEMS/NEMS fabrication are mostly crystalline or polycrystalline. Silicon, polysilicon, and silicon nitride are generally used for mechanical elements, aluminum as the electrical conductor for power and signal transmission, and silicon oxide as a sacrificial layer to allow the release of moving or deforming mechanical elements. Upon miniaturization, the size of the microstructures is generally no longer negligible with respect to the component size as used in many microsystems and submicron applications. The classical law of mechanics holds that mechanical properties are independent of sample size; however, the results of experiments and molecular dynamic simulations indicate that the crystals exhibit strong size effects at the submicron scales [14–19]. The occurrence of this problem is directly related to the ratio of grain size to the sample dimension. As the sample dimensions decrease to the same order of magnitude as the grain size, the mechanical (also other properties such as magnetic, etc.) properties of the individual grains will dominate the properties of the materials. The strong anisotropy of the mechanical properties of the grains, combined with the variation in orientation of the individual grains, will lead to strong variation in forming/patterning properties of the material. Moreover, reduction in sample dimensions greatly influences the free surface energy. In the presence of a free surface, a grain is under less constraint, and is able to deform at a substantially lower stress than the bulk. In most of the cases, a pronounced strengthening has been found at a decreasing specimen scale. Less attention was given to the intrinsic role of the microstructure in each of these experimental setups, whereby precise granular structure (grain size, grain orientation, and prior deformation history) was not considered as an important influencing factor. If the number of grains gets small, clear microstructural effects will contribute. Only a few studies seem to deal with microstructural contributions. For example, systematic investigations of fatigue damage and dislocation structures in thin Cu films with different thicknesses (0.2–3.0 μm), and grain sizes (0.3–2.1 μm) were carried out by Zhang et al. [15]. It was found that the dislocation arrangements in thin films are controlled by both film thickness and grain size. Extrusions occur in larger grains. However, the dimensions of the

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extrusions decrease with decreasing film thickness and grain size, and interface-mediated damage such as grain boundary, twin boundary cracking, and grain boundary diffusion become more prevalent. Fatigue cracking in the larger grains occurs along extrusions as well as at the intersections of the extrusions with the grain boundaries, which is similar to what occurs in bulk materials. Cracking in submicrometer-thick films with larger grains and in all the films with submicrometer grains occurs entirely along grain boundaries and twin boundaries without extrusion formation. Therefore, we can say that the grains and grain boundaries are the important detrimental factors in deciding the mechanical or nanofabrication properties of the materials. One can account for this problem by considering single crystal materials, but again the strong anisotropies along the different planes decide the materials properties and microfabrication or nanofabrication abilities. In principle, the ideal material for nanoscale fabrication is a material free from anisotropies, grain, and grain boundaries. Such types of materials are known as amorphous/glassy. As we have pointed out, lithography and the processes associated with it are the backbone of nanotechnology. In the lithographic processes the fine patterns are first transferred on a material known as “resist”, and subsequently these patterns are transferred to the actual material by selective etching. Therefore photoresist materials and their properties are very important in obtaining the nanoscale structures. Interestingly, most existing resist materials are based on polymers and have an amorphous structure which is most suited for the nanoscale fabrication (as discussed in the preceding paragraph). Although resist materials possess many beneficial features for nanoscale fabrication, they have intrinsic limitations due to large molecular size. The ultimate resolution of a resist or photoresist is largely determined by the size of an individual molecule which is presently between 5 and 10 nm for a photoresist macromolecule, depending on molecular weight and three-dimensional structures. Although low molecular-weight resist materials are expected to provide the needed breakthrough for reducing the pattern size and the surface roughness, they may crystallize and hence lack the ability to form a uniform amorphous structure. Recently, amorphous molecular glasses are becoming a promising class of new photoresist in addition to the traditional polymeric materials [20–21]. Amorphous molecular glasses are low molar-mass materials that do not crystallize on the time scale of use and that form a uniform transparent thin film that lacks grain boundaries and exhibits isotropic properties. Unlike classical polymeric resists, which consist of molecules with a distribution of molecular weights, molecular glasses may be truly monodispersed (size 1 nm) with well-defined molecular structures that lack chain entanglement. Sub-50–nm 449

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patterns have already been demonstrated in molecular glass resist by using the extreme ultraviolet lithography technique [22, 23]. Researchers believe that molecular glasses will become a promising class of new photoresist materials. Polymer materials are widely used for fabrication of MEMS devices such as biochemical sensing or optical functionality. Polymers are flexible, biologically compatible, available in many varieties, and can be fabricated in 3D shapes. Although polymers possess amorphous structure, there are several issues associated with using polymers for specialized MEMS or NEMS applications. Thermal and chemical stabilities of the polymers are poor. The dimensions of the polymer patterns change with time because of water absorption from the environment. Polymer molecules are large and sometimes can be several microns long; therefore achieving smoothness and precision is challenging compared with single crystal silicon. Usually dimensions of polymer components are typically large, and the tools used to fabricate them are not designed for micron- or submicron-scale precision. Submicron-scale features can be made by hot-embossing or imprint lithography techniques, but the stability of those features is poor because of low Young’s modulus, hardness, and wear resistance exhibited by the polymers. It is also difficult to handle thin films of polymers because of low stiffness. The processing techniques for different types of polymers are different, and the environment in which they are processed is quite different from the MEMS fabrication. The integratability with silicon electronics and other functional materials (such as piezoelectrics, ferroelectrics, metals, etc.) is also challenging. Therefore one can say that polymer-based MEMS can be particularly advantageous in low to moderate performing devices, which are low cost or even disposable. However, for MEMS/NEMS devices that need to be operated in harsh environments, there is a need for a better material. Recently amorphous carbon has emerged as a promising class of new material for MEMS [24]. This material is known to possess excellent tribological properties, low stiction surfaces, chemical inertness, and high elastic moduli. The high-quality amorphous carbon films are generally produced by a filtered cathodic vacuum arc deposition technique. The challenges with this material lie in integrating the relatively new deposition processes with the well-established processes of the silicon microelectronics industry. Moreover, the films deposited on silicon substrates exhibit high intrinsic stress, and the delamination of the films occurs at lower thickness values of approximately 180–200 nm. Therefore, in order to overcome the limitation of film thickness and grow thicker films, intrinsic stress in the film must be reduced. The other potential materials for MEMS fabrication can be amorphous/glassy metals. Amorphous metals have 450

properties that are very different from their crystalline counter parts. The combination of properties exhibited by amorphous/glassy metals suggests that the incorporation of these materials into MEMS devices could enable the design of MEMS/NEMS devices with significantly improved performance and reliability. For example, glassy metals have properties similar to polymers, which allows mass production of nanoscale structures at lower cost. Unlike polymers, the micro/nanoscale structures made with glassy metals exhibit far more superior mechanical and functional properties. Therefore in this chapter we will focus on the properties of amorphous/glassy metals that can make these materials a future material for fabrication of various types of MEMS/NEMS devices which can be operated in harsh environments.

27.2 Glassy/Amorphous Metals Glassy/amorphous metal is a metallic material with a disordered atomic scale structure (Figure 27.2). It is characterized by a limited number of diffuse halos in xray, electron, and neutron diffraction, and no sharp diffraction contrast in high-resolution electron microscopy. The first synthesis of glassy metal that drew wide attention among materials scientists occurred in 1960 when Klement et al. [25] reported that a liquid Au–Si alloy, when rapidly quenched to liquid nitrogen temperature, would form an amorphous solid. Prior to this, thin layers of amorphous metals had been prepared by both vapor deposition and electrodeposition methods at least as early as the 1930s, but these studies were not followed up in a continuous line of research. As the glassy or random state of atoms in a material has higher energy than a crystalline one, therefore formation of such a state in a material is rather difficult. This is the reason why it took more than 30 years to produce an amorphous/glassy alloy in ribbon form (bulk). Metallic glasses are formed through the continuous cooling of molten alloys. Figure 27.3 illustrates the temperature dependence of molten liquid’s volume (or enthalpy) at constant pressure. When cooling below the freezing temperature Tm occurs, molecular motion slows down. If the liquid is cooled sufficiently fast, crystallization can be avoided. Eventually molecules or atoms will rearrange so slowly that they cannot adequately arrange in a periodic configuration in the available time allowed by the cooling rate. The liquid’s structure therefore appears “frozen” on the laboratory time scale. The rate of change of volume or enthalpy with respect to temperature decreases continuously to a value comparable to that of a crystalline solid up to a temperature Tg, known as glass transition temperature. The liquid to glass transition occurs in a narrow temperature interval near Tg. The resulting material is a glass (Figure 27.3).

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Fig 27.2 ● Characteristic features of glassy alloys: (a) HRTEM image showing disordered atomic arrangement, (b) electron diffraction pattern exhibiting broad halos, (c) XRD pattern showing only a broad diffraction peak, and (d) differential scan calorimeter curve showing well-deﬁned glass transition temperature (Tg) and crystallization temperature (Tx).

Fig 27.3 ● Temperature dependence of molten liquid’s volume and enthalpy change.

When the molten liquid is cooled slowly, there is more time available for configurational arrangement of atoms, and below Tm, the rate of change of volume or enthalpy with respect to temperature decreases discontinuously and the resulting material is crystalline (Figure 27.3). In the case of pure metals, an extremely high cooling rate (which is difficult to achieve at laboratory scale) is required to beat the crystallization process. A real breakthrough in the development of metallic glasses occurred in the late 1980s and early 1990s, when several metallic glass alloy systems that require low cooling rates were discovered by Inoue and coworkers [26–30]. The key behind this success was the involvement of different kinds of elements in the alloy systems. The significantly different atomic sizes of the elements in the alloy lead to low free volume in the molten state,

resulting in orders of magnitude higher viscosity than other metals or alloys. The extremely rapid cooling and the presence of significantly different atomic-size elements in the molten alloy are necessary to avoid crystallization. The detailed experimental investigations performed on different kinds of glassy alloy systems by Inoue and coworkers lead to three empirical rules for the formation of bulk metallic glasses (BMGs). These rules are known as Inoue rules and are (1) use of multicomponent systems containing three or more elements, (2) significantly different atomic size ratios, 12%, and (3) the mixtures should have large negative heats of mixing. By considering these empirical rules, it is possible to produce bulk amorphous alloys by using two kinds of production techniques, solidification and consolidation. The solidification techniques are water quenching, copper mold casting, high-pressure die casting, arc melting, unidirectional melting, suction casting, and squeeze casting, whereas the consolidation techniques are hot pressing and warm extrusion of atomized amorphous powders in the supercooled liquid region. Bulk glassy alloys of diameters 10 mm in La- and Mg-based alloys, 30 mm in Zr-based alloys, 5–6 mm in Fe- and Ti-based alloys, 75–80 mm in Pd-based alloys, and 3 mm in Ni-based alloys were produced [31–38]. The shape and the outer appearance of glassy metal alloys produced in different forms such as bulk, rods, porous, pipes, rings, and tapes are shown in Figure 27.4. The discovery of these BMGs in different forms and shapes opened up a new materials science and technology field and significantly enhanced their practical applications in engineering and biomedical fields. 451

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Fig 27.4 ● Shape and outer surface appearance of some metallic glass alloys including (a) massive, (b) cylindrical rods, (c) porous with diameter 10 mm, (d) pipes, (e) sintered magnetic core (outer diameter 20 mm, inner diameter 10 mm, thickness 4 mm), and (f) tapes.

An almost essential tool in any laboratory for studying metallic glasses is differential scanning calorimetry (DSC). In this technique the sample and the inert reference of similar mass are subjected to identical thermal programs, and the heat flow between the two is monitored. This technique was originally developed for polymer research, and is ideally suited to study the metallic glasses on account of their large enthalpy change upon crystallization. The typical shape of the DSC curve for glassy metal is shown in Figure 27.2d. From this curve three important parameters: Tg, Tx, and ΔTx are obtained. Tg is glass transition temperature, Tx is crystallization temperature, and ΔTx is known as the supercooled liquid region and is the difference of Tx and Tg. At Tx sharp changes have been observed in electrical resistivity, elastic modulus, magnetic coercivity, and saturation magnetization, and all have been used to monitor the crystallization process. The values of Tg, Tx and ΔTx depend on the alloy system, and in some cases Tg is not observed. The alloy system that exhibits a well-defined ΔTx region is considered “glassy ”, while the alloy system for which this region is not detected is considered “amorphous”. It should be noted that both glassy and amorphous systems showed similar characteristics in their x-ray (broad peak) and electron microscope studies (random arrangement of atoms). Recently some differences were observed in magnetic properties [39]. It has been found that the soft magnetic properties of Feand Co-based glassy alloys are much superior to those of Fe- and Co-based amorphous alloys. Relatively lower coercivity, higher permeability, and higher saturation 452

magnetization were observed in the case of glassy alloys. The reason for these enhanced properties in the case of glassy alloys is thought to be the more homogeneous atomic scale configuration in the case of glassy alloys compared with amorphous alloys. Moreover, the existence of a noticeable ΔTx region in glassy metals (which is not present in amorphous systems) can make a huge difference from the application point of view. Especially for mass production of a MEMS/NEMS component, a large ΔTx region is needed. Glassy metals, like plastics or polymers, tend to soften (viscosity changes over several orders of magnitude) when heated in this region, which allows fabrication of 2D/3D micro/nanostructures using the imprint lithography technique.

27.3 Properties of Metallic Glasses Amorphous/glassy metal alloys have the features of new alloy compositions and new atomic configurations which are different from those for crystalline alloys. These features have enabled the appearance of various kinds of characteristics such as good mechanical properties, useful physical properties, unique chemical properties, and excellent surface properties which have not been obtained for conventional crystalline materials. Figure 27.5a summarizes the relationship between tensile strength and Young’s modulus for typical bulk glassy alloys, together with corresponding data for conventional crystalline alloys [40]. In comparison with the

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Fig 27.5 ● (a) Relationship between tensile strength (σt,f) and Young’s modulus (E) for bulk glassy alloys along with the data for crystalline metallic alloys. (b) Flexural stress-deﬂection curves of Zr-based bulk glassy sheets of thickness 3 and 4 mm prepared by a squeeze casting technique.

tensile strength of conventional crystalline alloys at the same Young’s modulus, the strength values of the bulk glassy alloys are about three times higher. In addition, the slope of the tensile strength vs. Young’s modulus curve corresponds to the elastic elongation limit; it is 1.9% for bulk glassy alloys, much higher than for conventional crystalline alloys. Figure 27.5a also shows a high-tensile strength exceeding over 2000 MPa in the case of glassy alloys, which has not been obtained in the case of conventional crystalline alloys. More recently, it was found that the strength of bulk glassy alloys increased to 3200 and 5200 MPa in the case of Febased and Fe–Co-based glassy alloys, respectively. For these alloys tests were performed in the compression mode. However, the high values of fracture strength and Young’s modulus lie on the same straight line which is extrapolated from the linear relationship shown in Figure 27.5a. This good agreement indicates that the deformation and fracture modes of bulk glassy alloys are independent of alloy component and strength level. In addition to uniaxial tensile fracture strength of glassy alloys, it is useful to know the bending fracture strength, which is very important for the fabrication of moving MEMS structures. Zr- and Pd-based bulk glassy alloy sheets with thicknesses up to 6 mm prepared by the squeeze casting technique were found to exhibit much higher bending fracture strength than tensile fracture strength. Figure 27.5b shows the bending flexural stress deflection curves of Zr55Al15Ni10Cu20, Zr55Ti5Al10Ni10Cu20 and Zr52.5Ti2.5Al15Cu20 glassy alloy sheets subjected to the three-point bending test at room temperature. The torsional elastic and rupture strength values of glassy alloys were also measured by using rod specimens of 10 mm in diameter

and compared with plain carbon (0.4 mass%C) steel. It was found that the elastic twist angle was about 16 degrees for Pd40Cu30Ni10P20 metallic glassy alloy, that is, about six times larger than the plain carbon steel. In addition, elastic shear stress was about 900 MPa, which is again three times (300 MPa) higher than the plain carbon steel. The maximum impact fracture stresses obtained from Charpy impact load-displacement curves for Zr55Al10Cu30Ni5 and Pd40Cu30Ni10P20 glassy alloy sheets prepared by copper mold casting are 1615 and 1749 MPa respectively. The impact fracture energy was 63 kJ/m2 for the Zr-based alloy and 70 kJ/m2 for the Pd-based alloy. The Charpy impact fracture energy of the Zr-based BMG alloys is strongly dependent on the preparation method, and very high impact fracture energies of 120–135 kJ/m2 are obtained for Zr5560Ti05Al10Ni10Cu20 glassy alloy sheets. These values exceed that of the conventional age-hardened Albased (100–120 kJ/m2) high-strength alloy prepared by powdered metallurgy. Some MEMS devices may be subjected to a very high number of fatigue cycles during their service lifetimes. This raises the possibility of fatigue being a limiting factor on the allowable stress levels or the useful life. Some studies report the fatigue strength of Zr- and Pd-based glassy alloys with notched shape samples. The fatigue strength endurance limit defined by the minimum applied cycle stress ratio at 107 cycles is about 0.04 for Zr-based BMGs and 0.23 for Pd-based BMGs. In addition to fatigue, wear resistance is also important for MEMS components such as microgears, etc. The wear resistance of BMGs increases linearly with hardness in a given material class. The wear resistance of metallic glasses was found to be much higher than that of the 453

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ceramics of the same hardness, suggesting that the wear mechanism does not involve brittle fracture [41, 42]. The comparison tests of the reliability for Zr-based BMG and GCr15 steel (the same as American brand 52100 or German brand 100Cr6) were performed under identical test conditions and geometries. Failure of GCr15 bearing rollers had already begun after running for 1932 min (525074 km), whereas Zr-based BMG rollers running for 3168 min (860991 km) exhibit no visible scale-off on the surface [42]. Although the hardness of Zr-based BMG and GCr15 steel is similar, the wear resistance of Zr-based BMG is much higher than the steel, and this is due to the much higher compressive strength and fracture ductility of Zr-based BMG compared with GCr15 steel. Another interesting property of metallic glasses useful for MEMS applications is their high corrosion resistance [43, 44]. Since the extremely high corrosion resistance of glassy/amorphous Fe–Cr–P–C alloys was reported in 1974, a variety of corrosion resistant amorphous/glassy alloys were developed. It was also shown that alloying elements have a great influence on the corrosion resistance besides the aspect of microstructure; glasses exhibit far less restriction on alloying than crystalline materials. The high corrosion resistance of glassy alloys is also attributed to their chemical homogeneity and lack of structural defects. The improved corrosion resistance of glassy alloys is not only based on their structure itself but also on their ability to promote passive amorphous oxide formation. Studies on Fe–Cr–Mo–C–B bulk glassy alloy exhibiting a large supercooled liquid region showed lowered corrosion rates in the range of 104 to 102 millimeters per year in 1–12 mol/HCl solution at room temperature as well as a wide passive region and low passive current density in the range of 102 to 100 A/m2. Zr-based alloys are known to exhibit unique chemical as well as electrochemical corrosion resistance. Corrosion studies on bulk Zr55Cu30Ni5Al10 glassy alloy showed a rapid formation of passivation layers in 0.1 M Na2SO4 and 0.1 M NaOH solutions. Studies on bulk glassy alloys revealed an increased corrosion resistance up to one to two orders of magnitude higher than polycrystalline alloys with the same alloy composition. In addition to very good mechanical and chemical properties, Fe- and Co-based glassy/amorphous alloys exhibit very good soft magnetic properties, in particular high saturated magnetic flux density (Bs) for the former alloys and high permeability with zero saturated magnetostriction for the latter alloys [45]. The new Fe-based (Fe–B–Si–Zr and Fe–B–Si–Nb) glassy alloys have high Bs values of 1.40–1.53 T and low coercivity (Hc) of 2.9 to 3.7 A/m. Furthermore, the effective permeability at 1 KHz for their melt-spun glassy alloy ribbons is in the range of 14400–17300. The amorphous/glassy metal alloys have also attracted increasing interest as precursors to produce nanocrystalline 454

alloys containing a remaining amorphous phase by partial crystallization. These so-called nanocomposite materials exhibit good mechanical properties, soft and hard magnetism, high magnetostriction in low applied fields, and high catalytic properties which have not been obtained for amorphous or crystalline single-phase alloys. Based on these research results, the scientific and engineering importance of amorphous/glassy metals has increased significantly and opened up a new materials science and technology field (Figure 27.6). A variety of literature is available on the development and characterization of their physical and chemical properties [25–45]. As the focus of this chapter is on the applicability of glassy metals in the area of MEMS/NEMS, therefore in the next section we will describe the fabrication of micro/nanoscale 2D/3D structures using BMGs.

27.4 Microfabrication Ability of BMGs 27.4.1 Superplasticity of Metallic Glasses in Supercooled Liquid Superplasticity is the unusual property of a material which allows thousands of percent elongation at elevated temperatures. Under normal conditions, conventional alloys do not stretch uniformly, but form a neck-down region and then fracture after elongations of only 100% or less. It is well known that the fine fibers of oxide and fluoride glasses are produced by utilizing the viscous flow deformation of supercooled liquid which can be obtained in a wide temperature range before crystallization and the elongation reaches the order of 105% to 106%. If the similar wide supercooled liquid region is obtained for metallic glass alloys, the glassy alloys are expected to exhibit extremely large elongation exceeding 104%. Figure 27.7 shows the relation between the true flow stress and strain rate for glassy alloys in a supercooled region. La55Al25Ni20 alloy was subjected to testing in the supercooled liquid region [46]. A good linear relation is observed, and the slope corresponding to strain-rate sensitivity (m-value) is 1.0, which is characteristic of Newtonian viscous flow behavior. Similar m-values were also obtained for other metallic glass alloys [47–50]. The strain rate is also found to increase with increasing deformation temperature. This means that the normal viscosity coefficient λ decreases exponentially with an increase of temperature. This relation is expressed by the well-known Andrade equation λ AeB/T for viscous fluid. Figure 27.7c shows the temperature dependence of viscosity in a supercooled liquid region for a few metallic glass systems along with normal oxide glasses, indicating that the viscosity of metallic glasses is quite

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Fig 27.6 ● New material science and technology ﬁelds opened up by the stabilization of supercooled metallic liquids.

Fig 27.7 ● Tensile true ﬂow stress as a function of stress rate for metallic glass alloys in a supercooled liquid region: (a) La55Al25Ni20, (b) Zr55Al20Cu30Ni5, (c) normal viscosity of metallic glasses and oxide glasses in the supercooled liquid temperature range, and (d) changes in the sample morphology by stretching glassy La55Al25Ni20 alloy at 500K (in supercooled liquid region).

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close to that of normal oxide glasses [51]. These results indicate that the deformation of metallic glasses in supercooled liquid occurs through an ideal superplastic deformation mode. Considering that the m-values of superplastic crystalline metallic alloys are in the range of 0.3 to 0.6, it is concluded that the metallic glasses have much better superplastic deformability. As an example, Figure 27.7d shows the changes in the shape and outer surface morphology by stretching the La–Al–Ni glassy alloy with a diameter of 3 mm in a supercooled liquid region [46]. The total elongation of the alloy was found to be as large as 1.5 105%.

27.4.2 Microformability of Glassy Metals It is expected that the excellent superplastic deformability of the metallic glasses in a supercooled liquid region enables the fabrication of the macro- and micrometersized machinery parts with various shapes. Saotome and Inoue [52] recognized BMGs as a potential material for the fabrication of MEMS devices in 1994. However, the ability to plastically deform metallic glasses in the vicinity of Tg was recognized in the early days of metallic glass researches by Leamy et al. [53] in 1972. Saotome, Inoue, and coworkers applied a superplastic microforming process (also known as imprint) to La55Al25Ni20 BMG as well as to fine-grained Al–78Zn alloys, and studied the deformation behavior [47, 52, 54, 55]. In their study, a V-groove die made from silicon (100) having different widths of die throat (Wd) was used. The percentage of inflow area Af to the V-groove area Ag, Rf Af/Ag and the curvature of the peaked point in the specimen ρ were measured by image analysis (Figure 27.8). In the case of Al–78Zn alloy under

(a)

the same flow stress, strain rate is dependent on the grain size, and the strain-rate sensitivity exponent m was 0.5 at a temperature of 500K. The percentage of filled area in the V-groove (Rf) increases as the forming time increases and reaches 90% within 200 s for each loading condition. The %Rf is dependent on the grain size and the width of the die throat (Wd). For the grain sizes of 0.7–2.5 μm, and Wd 21 μm, the %Rf was almost the same, however it decreases with decreasing Wd. In the case of Wd 2 μm and grain size 1.2 μm, the forging was almost impossible due to the deformation mechanism of the grain boundary sliding and grain rotation. It was therefore concluded that the materials with smaller grain size exhibit better microformability. In the case of glassy alloys, in the temperature range of ΔTx, the percentage of inflow area Rf increases with increasing forming time, and reaches above 98% for Wd 10 μm in the time of 1000 s. For Wd 2 μm, the Rf was about 92% under a stress of 10 MPa. A large area forging of micropyramids of base 7 or 20 μm with a spacing interval of 100 μm was also fabricated on La55Al25Ni20 and Zr65Al7.5Cu27.5 BMGs [52]. Since the Tg of La55Al25Ni20 BMG is 480K and Zr65Al7.5Cu27.5 BMG is 640K, this difference in Tg produces a new utilization of Zr65Al7.5Cu27.5 BMG as a die material for La55Al25Ni20. The micropyramids forged on ZrAlCu BMGs were used to forge the concave pyramids on LaAlNi BMG at a temperature of 500K. The superplastic micro/nanoformability of BMG was also studied in La60Al20Ni10Co5Cu5 glassy alloy [49] similar to the La55Al25Ni20 glassy alloy. The La60Al20Ni10Co5Cu5 alloy has Tg and Tx at 451K and 523K, respectively, with a large value of ΔTx of 72K. The width of the V-groove Wd was from 200 nm to 2.0 μm. The forming time was 1000 s under a constant load of 10 MPa at a temperature of 500K. It was observed that the alloy exhibits Newtonian viscous flow in the

(b) Microforming in supercooled liquid state of amorphous alloy

Deformed specimen

Af Specimen Amorphous alloy

Deformed specimen

Wd Ag

Grain size Dg = Width of V-groove Wd

Grain size Dg << Width of V-groove Wd

V-grooved die of (100) Si

Curvature r

r: Curvature of a deformed specimen into the V groove die Rf = Af / Gf : Percentage of flow area into the V groove Af : Formed and inflow area into the V-groove Ag : Area of V groove Wd: Width of die throat = 1, 2, 5, 10, 20 μm

Fig 27.8 ● An evaluation system and deformation mechanism of microformability for superplastic materials: (a) superplastic alloy of polycrystalline aggregates and (b) glassy alloy in supercooled liquid region. In the case of ﬁne-grained superplastic alloy, the deformation mechanism is grain boundary sliding and grain rotation in polycrystalline aggregate. In the case of glassy materials the excellent microformability is accompanied with Newtonian viscous ﬂow in the supercooled liquid region.

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ΔTx region under low stress. The coefficient of viscosity decreases exponentially with temperature, and the alloy exhibits a tendency of weaker temperature dependence than in the case of the ternary La55Al25Ni20 BMG (Figure 27.7c). The La60Al20Ni10Co5Cu5 BMG exhibits superior formability in the micrometer-scale as well as in the nanometer-scale range (Figure 27.9). The index Rf decreases with a decrease in Wd and becomes Rf 61% for Wd 200 nm. Experiments were also carried out on other BMG alloy systems which include Zr-, Pd-, Pt- and Ni-based [47, 48, 54, 56, 57]. In comparison with similar formability tests on granular Al–78Zn alloy, microformability of BMGs was confirmed to be superior due to its homogeneous, isotropic deformation in the microscopic length scale (Figure 27.9).

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27.5 Nanoforming Ability of Glassy Metals (Below 100 nm) Recently many research groups have demonstrated the excellent microforming ability of BMGs in different alloy systems [58–66]. However very little is known about their nanoformability (below 100 nm). One of the hurdles in studying the nanoformability is to fabricate the suitable nanometer-scale dies. Generally, the nanostructured hard dies used for the NIL process are prepared by transferring a pattern in photoresist on a hard substrate using electron beam lithography, RIE, wet chemical etching, or electroplating [6, 67–71]. The most commonly used material for die fabrication is quartz. The insulating

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Fig 27.9 ● SEM microphotographs of (a) V-groove die of 1.5 μm in width, (b) corresponding La60Al20Ni10Co5Cu5 deformed BMG, (c–d) AFM images of La60Al20Ni10Co5Cu5 deformed BMG with a die of (c) Wd 0.5 μm, and (d) 0.2 μm, (e–f) microforged specimens of Al–78Zn ﬁne grained super plastic alloy. The mean grain size 1.2 μm, forging pressure is 10 MPa, temperature is 520K, and time is 1200 s for (e) Wd 2 μm and (f) Wd 6 μm. The effect of granular structure on the ﬁneness of the patterns is noticeable in the case of BMG and nanogranular materials.

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nature of quartz imposes a lot of restrictions during fabrication and inspection of dies. For example, a thinner layer of Cr is needed to suppress the charging during the e-beam exposure. Loss of a critical dimension during etching of the Cr-layer makes fabrication very difficult, especially when the feature sizes are below the 100-nm range [68]. Since the ultimate resolution of the imprint lithography depends on the minimum feature size in the die, defect inspections are necessary. However, the defect inspection is compromised because of the absence of a conductive layer on the final quartz die. Particularly for higher Tg (100°C) materials, such as metallic glasses, thermal expansion mismatch between the die and the forming material should not occur in order to avoid a stress build up during the cooling cycle, which can affect the pattern fidelity. Often it is desirable to do patterning at low temperatures or reduce the thermal expansion mismatch. In view of the above considerations it is better to have a nanoscale die made from metallic materials. The electrically conducting nature of metallic die material resolves the problem of die inspection and also simplifies the process of die fabrication by using a single-step machining technique such as FIB. Recently FIB has become an increasingly popular tool for fabrication of various types of nanostructures for different applications [72–75]. FIB has several advantages over other techniques used for nanofabrication. For example, it allows very rapid implementation of complex patterns without application of master nor resist. The sub-10-nm spot size of FIB enables patterning of diverse nanostructures at very high resolution. When compared to electrons, ions (like Ga) are much heavier and can strike with greater energy at relatively shorter wavelengths to directly transfer patterns on hard materials without major forward and backward scattering. In addition to various advantages, FIB also suffers with some disadvantages. Sputtering is a major mechanism for material

1 μm (b)

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(a)

180 160 140 120 100 80 60 40 20 0

removal in FIB and its efficiency is normally represented by the sputter yield. In general sputter yield is dependent on the materials composition (or more precisely the atomic species and their binding energies) and grows as the ion energy increases. Therefore the FIB etching of multielemental alloys can result in the modification of surface composition. The sputtered atoms which are ejected from the material condense back to the surface that is redeposited on the sides of the fabricated patterns. Redeposition reduces the fabrication rate and the aspect ratio of the patterns. Redeposition sometimes also makes it hard to predict the final geometry of the fabricated nanostructures. Another problem with FIB is the Ga implantation in the fabricated nanostructures.

27.5.1 Nanometer Scale Dies for Imprinting and FIB Machining of BMG Recently Saotome et al. [76–77] studied the nanoforming of metallic glasses by using the FIB technique. They selected Zr-based BMG and glassy carbon and studied the resolution and efficiency of FIB machining for these materials. Figure 27.10a, b show the SEM micrographs of FIB-machined surfaces of glassy carbon and Zr-based BMG for 3 μs dwell time and 400 scans. The set dimensions are 4 μm in length and 20 to 100 nm in width. It was observed that the machined depth increases with increasing machining width and the machining efficiency of Zr-based metallic glass is better than that of glassy carbon (Figure 27.10c). In the series of experiments, glassy carbon and Zr-based BMG exhibit suitable nanoworkability. The resolution and efficiency depend on the characteristics of the material, the irradiation beam conditions, and both the working width and the length. As the imprint process for metallic glass requires heating at a temperature corresponding to the Tg of the

(d) (c) (f) 1 μm (e) Zr-based BMG 1 μm

Glassy carbon 0 200 100 Set value of machining width/nm

1 μm

Fig 27.10 ● FIB-machined surface of (a) glassy carbon and (b) Zr-based BMG. (c) characteristic relationship between machining width and depth. SEM images of dies of (d) glassy carbon and (e) Zr-based BMG after heating at 620K and (f) glassy carbon die after heating at 1230K.

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imprinting material, therefore the effect of heating was also studied so that they can be used as a die. Both Zrbased dies and the glassy carbon dies were heated to 620K in a vacuum of 103 Pa. This temperature is less than the Tg of Zr-based BMG. A small amount of gallium oxide on the surface of glassy carbon was observed, whereas no trace of gallium precipitation on the surface of Zr-based BMG was observed (Figure 27.10d, e). The precipitation of gallium oxide on the surface of glassy carbon was more clearly observed when these dies were heated at 1230K for 1.8 ks (Figure 27.10f). These observations clarified that the Ga ion implantation in BMG during FIB fabrication is not a serious problem like in the case of glassy carbon. However, in the case of deeper and wider structures, a more efficient method is required because the direct milling approach is very time consuming. Very recently Kawasegi et al. [78] reported a method of submicrometer-scale rapid patterning on Zr-based BMG using a combination of FIB irradiation and wet chemical etching. A Zr-based BMG surface irradiated with Ga ions can be selectively etched in HN (HF:HNO3:H2O 1:657:387 by weight) solution. This simple and rapid fabrication process can fabricate structures with depths of several tens to hundreds of nanometers. This is dependent on the type of irradiating ion and is a result of the presence of a Ga ion that induces a change in the etching characteristics without affecting the glassy nature of BMG. Figure 27.11a shows the atomic force microscope (AFM) topographic image of Zr-based BMG irradiated with 30 keV Ga ions at various doses between 422 and 3801 μC cm2. At low doses no change was observed in the irradiated area. However at high doses, the irradiated area was sputtered (Figure 27.11a). Structures of several hundred nanometers deep appeared after etching in HN solution, which were significantly deeper than before etching (Figure 27.11b). The shape of the

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structure can be controlled principally by the dose and the etch time (Figure 27.11c). This method is significantly faster than the direct ion milling, which would take about 112s to fabricate an 80-nm-deep structure over an area of 5 5 μm2. In stark contrast, this method requires an irradiation time of 0.46 s and an etch time of 3 s. For a larger area the difference will be even larger.

27.5.2 Nanoforming of BMG with FIB Fabricated Dies Zr-based BMG and glassy carbon dies fabricated with FIB were further utilized to demonstrate the nanoforming ability of BMGs [76–77]. Pt48.75Pd9.75Cu19.5P22 BMG was selected as a material for superplastic nanoforming because it has relatively lower Tg (506K) and a large supercooled liquid region of 76K. The working temperature for nanoforming was 560K, which is much lower than the Tg (682K) of Zr-based BMG dies. Figure 27.12a, b shows the SEM and three-dimensional AFM images of glassy carbon and Zr-based BMG dies and their imprint on the Pt-based BMG. It can be noticed that the corners of the specimen forged with glassy carbon die are more round than Zr-based BMG die (Figure 27.12c, d). This is due to the higher contact angle between the glassy-carbon die and the deformed material. In addition to materials characteristics (viscosity and surface tension), die geometry, and surface roughness, the contact behavior during deformation also affects the micro/nanoformability, so the contact angle and the friction between the material and the die surface should also be considered. At nanoscales shearing of patterns was observed in the case of patterns imprinted by glassy carbon dies (Figure 27.12e, g), whereas no such shearing was observed in the case of imprinting done by Zr-based BMG dies

Fig 27.11 ● Change in the FIB-irradiated Zr-based BMG surface after etching in HN solution. (a) AFM topographic image after irradiation by Ga ions at doses of 422–3801 μC cm2, (b) same area after etching in HN solution for 3 s, and (c) change in depth of the irradiated area at various doses, before and after etching in HN solution for 3 s. Source: After Ref. [78].

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(a)

(b)

1 μm

(c)

300 nm

(e)

200 nm

1 μm

(d)

300 nm

(f)

(g)

200 nm

(h)

0

0 30 nm

3.5 μm 100 nm

30 nm

3.5 μm 100 nm

200 nm

200 nm

Fig 27.12 ● SEM images of nanoforged surfaces of Pt-based BMG with FIB machined dies of (a) glassy carbon and (b) Zr-based BMG. (c) 3D proﬁle of (a), (d) 3D proﬁle of (b). (e) and (f) are SEM images of glassy carbon and Zr-based BMG die, and (g) and (h) are corresponding imprints on Pt-based BMG.

(Figure 27.12f, h). This seems to be due to the difference in thermal expansion between the die and the forged material. The thermal expansion coefficients are 3.7 106 K1 for glassy carbon, 1.0 105 K1 for Zr-based BMG, and 1.2 105 for Pt-based BMG. Therefore the effect of thermal expansion between the die and the forged BMG should be considered seriously for the nanoimprinting.

27.6 Applications of BMGs in MEMS Based on the above-described progress in fundamental studies, the bulk glassy alloys have already been used as practical engineering materials. The Zr55Al10Cu30Ni5 and Zr50Ti5Al10Ni10Cu25 BMGs were commercialized in 1998 as striking-plane materials for golf clubs, in drivers and iron putters [31, 39, 79]. Unique mechanical properties of BMGs were also used to develop a highly sensitive Coriolis mass-flow meter using sensing pipes made from Ti–Zr–Ni–Cu–Sn BMG [39]. The Ti-based glassy alloy pipes can produce greater elastic deformation from forced vibrations than the conventional SUS316 stainless steel pipes. The sensitivity of Ti-based BMG sensor was confirmed to be as much as 28.5 times higher than the conventional SUS316 stainless steel. Fe–Mo–B–Si glassy alloy balls 1 mm in diameter were mass produced and commercialized as shot pinning balls with unique characteristics unobtainable with any kind of crystalline alloy balls [80]. The glassy alloy shot has a much longer endurance time up to final rupture, which is 8 to 10 times longer than that for the cast-steel shots or high-speed alloy-steel shot. To utilize the unique mechanical properties of high strength, low Young’s modulus, and large elastic elongation, Zr-based glassy alloy springs of diameter 11 mm were fabricated [81]. Zr-based BMGs were also used as a casing material for clocks, watches, and cell 460

phones, and also as electromagnetic shielding plates. In chemical applications Ni–Nb–Zr-based glassy alloy sheets exhibit hydrogen permeation about 2.2 times greater than that of conventional Pd23 mass%Ag alloy [82–83]. The Ni-based glassy alloys with high corrosion resistance have been used as separators for polymer electrolyte fuel cells. It was confirmed that the fuel cell using Nibased glassy alloy separators exhibits good performance without any appreciable degradation during continuous operation up to 600 h. Used as magnetic materials, Febased soft magnetic glassy alloys have been fashioned into consolidated magnetic cores for power supplies such as common choke coils and noise filters [39]. The Fe-based glassy alloys exhibiting extremely high permeability (105) were used as yoke materials in linear actuators. The resulting linear actuator exhibits higher Lorenz force than actuators using electromagnetic soft iron and permalloy with ferrite-type permanent magnets. The generation of higher Lorenz force indicates that the linear actuators using the Fe-based glassy alloys magnetic yoke cores can be small, strong, and fast and can also save energy. Besides these numerous practical applications of BMG alloys, recent fundamental understanding in nano/ microformability opens up new utilization in the development of various micro- or nanomachine components. Here we will give some of the very recent efforts made in the development of MEMS with BMGs.

27.6.1 Pressure Sensors Regarding the issues of environmental problems, low energy consumption and improvement of safety, miniaturized pressure sensors with high sensitivity have been required in order to reduce toxic smoke and CO2 gas from auto exhaust. For such uses, pressure sensors have been constructed with a metallic diaphragm and deposited strain gauge [38, 39, 84]. A conventional metallic diaphragm is prepared by fine polishing of cold-forged

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Fig 27.13 ● Appearance and output voltage (sensitivity) of Zr-based metallic glass diaphragm pressure sensor and its comparison with conventional SUS630 diaphragm-based sensor.

SUS630. However, the miniaturization of pressure sensors is at its limit due to the limitation of the cold-forging technique. In addition there is a limitation in the improvement of the performance, such as the sensitivity and high pressure resistance of the sensor, because performance mainly depends on Young’s modulus and the strength of the diaphragm material. The measurement sensitivity of the pressure sensor is determined by the strain at the bottom plane of the diaphragm. Larger strain () leads to higher sensitivity. The strain can be expressed as ε=α

Pa2 Et

2

(27.1)

where α, P, a, E and t are a constant, the applied pressure, the effective diameter of the diaphragm, Young’s modulus and thickness, respectively. The metallic glass alloys are highly promising for producing miniaturized diaphragms with high sensitivity and high pressure resistance due to their low Young’s modulus and high strength. Moreover, the good imprintability and castability of glassy alloys are appropriate for mass production of net-shape diaphragms. Ni- and Zr-based metallic glasses were chosen for the fabrication of diaphragms, and the results were compared with the similar diaphragm made with conventional SUS630. Ni- and Zr-based glassy alloys exhibit high strength (Ni-based 2700 MPa; Zr-based 2000 MPa), and low Young’s modulus (Ni-based 135 GPa; Zr-based 100 GPa) compared with SUS630 (strength 1200 MPa, E 200 GPa). Figure 27.13 shows the outer appearance of the diaphragm with deposited strain-gauge on the bottom plane along with the sensitivity compared with

a standard SUS630 sensor. The calculated sensitivities for Ni and Zr-based sensors are 1.5 and 2.9 times higher than that of the SUS630, respectively. However, the experimentally measured sensitivity ratio for a Zr-based diaphragm sensor treated with excimer-laser reaches as high as 3.8 times. This improvement of 0.9 in the sensitivity ratio is attributed to the homogeneity of the deposited strain-gauge.

27.6.2 Microgeared Motors It is important to fabricate high-torque motors with diameters 5 mm. The smallest diameters for commercialized geared motors developed to date were 12 mm in 1980 and 7 mm in 2000. Super-small geared motors of 1.5 and 2.4 mm in diameter were developed from 2004 to 2006 [38, 39, 85–87]. This was achieved by utilizing the high strength of metallic glasses along with their ability to provide precision and surface flatness. A Ni53Nb20Zr8Ti10Co6Cu3 metallic glass was selected, and three kinds of microgear parts were prepared by injection-casting. The so-called sun carrier (Figure 27.14a) consists of sun gear with a module of 40 μm and a tip diameter of 647 μm located on a carrier plate of 1700 μm and three sets of shaft pins for the planetary gears (Figure 27.14b) that, combined with the sun gear, act as the gear reduction system transmitting torque to the output shaft (Figure 27.14c). The newly developed sun carrier exhibits good dimensional accuracy with maximum surface roughness less than 2 μm and pin diameter tolerance within 2 μm. Using these BMG gear parts, micromotors were constructed. The appearance and the durability test 461

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Fig 27.14 ● Appearance and durability of microgeared motor 2.4 mm in diameter constructed by using three super-precision sun carrier gears made of Ni-based glassy alloy.

results of a microgeared motor 2.4 mm in diameter that uses three super precision sun-carrier gears made of the Ni-based (Ni53Nb20Zr8Ti10Co6Cu3) glassy alloys are shown in Figure 27.14. It was confirmed that the microgeared motor can generate a torque of 2 mNm at a rotational speed of 680 rpm. In addition, the life of the motor was found to be 100 times longer than that of a micromotor of the same size made with SK tool steel gears. Further miniaturization and higher dimensional accuracy have been achieved in a microgeared motor with an outer diameter of 1.5 mm. This motor exhibits a torque of 0.44 mNm, which is 20 times that of a vibrating motor of 4 mm outer diameter used in mobile phones. The lifetime of this motor exceeds 1000 h. The significant improvement in the performance of microgeared motors made with metallic glass is due to the combination of many unique factors: higher yield strength, higher stiffness, higher hardness, larger elastic elongation, better wear resistance, and corrosion resistance exhibited by Ni-based glassy alloy in comparison with SK tool steel. Super small and high-power geared motors with much longer lifetimes are expected to find applications in various kinds of microprecision machines such as microsurgical instruments, microlathes, biped walking robots, and so on. 462

27.6.3 Optical Components Optical components such as gratings have fine periodic patterns with periodicity corresponding to the wavelength of light. Plastic is usually used for their fabrication and suffers with poor mechanical properties and low corrosion resistance along with incompatibility with high temperature usage. In this respect, metallic glasses are useful in the fabrication of reflective optical components because of excellent micro/nanoformability along with good mechanical properties exhibited by these alloys. Fabrication of periodic nanostructures (Figure 27.15) showing reflectance from 1% to 50% at λ 530 nm has already been demonstrated in Pt-based BMG by the nanoimprinting technique [76]. The diffraction gratings of 1 μm interval are also fabricated on Pt-based BMG [88]. These nanoimprinted optical components of metallic glasses are useful for numerous applications and under various conditions. Fabrication of holograms with metallic glass is also demonstrated (Figure 27.16). Generally, holographic interference is generated by two light beams and the fringes are recorded on photosensitive materials, such as photographic plate. Reflection holograms are useful for the secure identification of various goods and are made of reflection coating on a convex–concave surface

Metallic Glass

(b)

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(f)

(d) (a) 1 μm

1 μm

50% (0.96)

1 μm

30% (0.57) (g)

(c) 100 μm

1 μm

1 μm

1% (0.02)

1μ m

Reflectance ratio :52% (1)

0.2 μm

(e)

1 μm

13% (0.25)

Fig 27.15 ● Periodic structures made on Pt-based metallic glass by nanoimprint. Reﬂectance ratio for (b) to (e) was measured at about l 530 nm. (f) and (g) are the diffraction grating of 1 μm intervals.

(c)

5 μm

1μ

m

(b)

0.5 μm

(a)

1 μm

2 mm

Fig 27.16 ● (a), (b) Hologram made on Pt-based metallic glass by nanoimprint technique, and (c) holographic reﬂected image (Japanese character meaning “Friends”).

structure of polymer film. Compared with polymer holograms, metallic glass holograms are simpler to fabricate and do not require a reflection coating. Another demonstration of metallic glass for optical applications is the fabrication of gapless microlens arrays [89].

27.7 Metallic Glass Thin Films: A Pathway to Integrated MEMS It is demonstrated that the BMGs have interesting mechanical, chemical and functional properties, which are very promising for fabrication of various MEMS devices. In fabrication of MEMS devices it is often required to integrate different kinds of materials in a single device to perform various complicated operations. The major problem associated with bulk materials is that they are very difficult or sometimes impossible to integrate with silicon IC technology or with other functional materials like piezoelectric or ferroelectrics. Moreover, material requirements are for the sample size to be small, so the bulk materials need lot of preprocessing (dicing, polishing, etc.) to meet the dimensionality and surface quality conditions to fabricate micron-size structures. In order to overcome these limitations and

be able to realize the full potential of excellent properties of metallic glasses R&D efforts should be devoted to fabricate them in thin-film form. However, most of the research in the area of metallic glasses focuses on production of bulk materials with larger and larger dimensions, and a very limited number of efforts have been made for the fabrication of thin films [90–105]. Therefore, we will consider fabrication and characterization of metallic glass thin films in more detail. The thin-film deposition process involves three main stages: (i) production of appropriate atomic, molecular, or ionic species, (ii) their transport to the substrate through a medium, and (iii) condensation on the substrate. Formation of thin film takes place via nucleation and a growth process, forming a network structure which slowly gets filled and gives a continuous film. The initial nucleation and its growth depend upon the thermodynamic parameters of the deposit, the substrate surface, the place of origin, and the transport medium. Depending upon the individual state of atomic, molecular, or ionic species of matter, the techniques used for thin film deposition are broadly classified into two categories: liquid phase and vapor phase deposition. The details of the various techniques are well covered in review articles in the literature [106–108]. Here, we 463

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will consider only the technique which is useful for the production of metallic glass thin films, “sputtering”. Sputtering techniques are widely used in industry for deposition of oxides and manufacture of semiconductors and metallic thin films, and are well established for reproducibility and deposition over a large area. In the sputtering process, a solid material (known as target) is subjected to a stream of impinging particles (that is, Ar ions) of sufficient energy that some of the surface atoms will acquire enough energy to be liberated from the surface. The process of ejecting atoms from the surface is known as “sputtering”. As they scatter throughout the vacuum environment, some of the atoms come to rest on the substrate surface and coalesce to form a “sputter-deposited” thin film. Depending on the instrumental configuration, the sputtering technique can have different names, like RF/DC diode sputtering, magnetron sputtering, helicon sputtering, balance/unbalanced magnetron sputtering, cosputtering etc. The details about their advantages and disadvantages are well listed in numerous books and review articles [106–108].

27.7.1 Zr-Based Metallic Glass Thin Films and Their Characterization The first basic requirement for the deposition of metallic glass thin films by sputtering is the sputtering target. The sputtering target is usually a circular disc (or it can be rectangular depending on the equipment) of diameter between one and several inches. As we have noticed metallic glass alloys are made up of three or more different kinds of elements in a specific composition range, therefore the sputtering target material must have a similar composition, and is not usually available commercially. Therefore sputtering targets for deposition of metallic glass thin films need to be custom made. The multielemental alloy sputtering targets can be easily made by arc-melting or radio-frequency melting of a mixture of metals in a vacuum or inert-gas atmosphere. Another way to fabricate the sputtering target is to mix the powders of different metals and sinter the mixture at an elevated temperature under high pressure in a die of required dimensions. This technique of making the target or solid discs from powders is known as spark plasma sintering (SPS). Out of a large number of BMG alloy compositions, first we will describe the deposition and characterization of Zr-based metallic glass thin films [96–98, 102] because we have noticed that in bulk form it has excellent glass-forming ability with a large supercooled liquid region and good mechanical and chemical properties. For deposition of thin films, the Zr55Al10Cu30Ni5 alloy sputtering target was made by the arc-melting technique. Appropriate amounts of pure metals (99.99%) of Zr, 464

Al, Cu and Ni were weighed and arc melted under an argon atmosphere in a water-cooled copper die. The arc melting was performed many times to obtain a uniform distribution of all the elements in the target. Thin films were deposited on a silicon (Si) substrate by the magnetron sputtering technique. The sputtering chamber was evacuated to a base pressure of 5 106 Pa, and a high-purity argon gas (grade 1) was introduced to obtain the different sputtering gas pressures (0.1 to 0.5 Pa). In order to obtain the good quality of thin films, sputtering parameters such as sputtering pressure, power to the target, target to substrate distance, and deposition temperature need to be optimized. For deposition of Zr-based glassy thin films, the target to substrate distance was fixed at 60 mm, and 100 W DC power was applied to the target. Zr–Al–Cu–Ni films of thickness 0.1 to 5.0 μm were deposited. A significant difference in the composition of the films (CZr 48.4 at.%; CAl 11.6 at.%; CCu 31.2 at.%; CNi 8.7 at.%), and the sputtering target (CZr 54.6 at.%; CAl 9.3 at.%; CCu 31.0 at.%; CNi 5.1 at.%) was observed. This can be explained on the basis of sputtering yield, which is defined as the quantity of material removed per incident ion. When a multielement target is sputtered, the sputtering yield of one element is often greater than the other elements. The sputtering yield is generally dependent on atomic masses and the surface binding energies of the different elements present in the sputtering target. Since light mass atoms have larger cross-sections for being hit by an incoming ion, and more of them are set into motion, there is preferential sputtering of lighter elements. For similar masses, lower binding energy elements have preferential sputtering. Therefore in order to get the required composition in the film, the sputtering target composition needs to be adjusted according to the sputtering yield of different elements present in the target. After deposition of the films it is necessary to characterize them in terms of adhesion on the substrate, surface quality such as surface roughness, crystal structure, mechanical, and chemical and electrical properties. The adhesion tests were carried out by tape, and scratching by tweezer, and it was found that the glassy thin films have very good adhesion on silicon. Typical characterization results, which prove that the Zr–Al–Cu–Ni thin films are in a glassy state, are shown in Figure 27.17. The x-ray diffraction (XRD) and the high-resolution transmission electron microscope (HRTEM) studies showed that the Zr–Al–Cu–Ni thin films are completely glassy. The films were also found to exhibit a glass transition temperature (Tg) at 693K, and a crystallization temperature (Tx) at 788K with a large supercooled liquid region (ΔTx) of 95K, which are close to the values reported for the bulk Zr55Al10Cu30Ni5 metallic glass. Furthermore, the surface analysis with an AFM reveals that the films are free from the granular growth structure and are very smooth with

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Fig 27.17 ● Zr–Al–Cu–Ni thin ﬁlm (a) XRD, (b) DSC and inset shows the AFM topographic image, and (c) SAED pattern along with an HRTEM image.

(a)

(b)

(c)

Fig 27.18 ● SEM images of indents: (a) indent made at 8 mN force, (b) indent made by crushing the tip at high load, and (c) shear bands observed near the indents show the presence of plasticity in the ﬁlms.

the average roughness 0.2 nm. In terms of mechanical properties, Zr–Al–Cu–Ni film of thickness 4.5 μm showed enhancement in hardness (10.3 GPa, measured with a microindenter with a force of 15 mN) in comparison with the bulk alloy of almost similar composition. However, our very recent measurements on films of similar thickness (0.9 μm) showed a hardness value of 6.8 GPa (measured with nanoindentation with a maximum force of 1 mN). The SEM observations of indents on thin films (Figure 27.18) showed pilling up of material and the presence of shear bands, indicating the presence of plasticity. It appears that the hardness is dependent on the film thickness and needs further investigations. Recently, sample size dependence of mechanical properties for Zr–Al–Cu–Ni bulk glassy alloy was investigated by Chen et al. [109]. In this study, micropillars of diameters from 2 to 28 μm were fabricated by FIB etching of BMG. The mechanical tests were performed in the compression mode. Interestingly, it was observed that the fracture stress increases with a decrease in pillar diameter and reaches a maximum for the pillar diameter of 4.5 μm. Further decrease in the pillar diameter results in a decrease in fracture stress. We noticed that the Zr-based metallic glass thin films have good surface and mechanical properties along with a large range of supercooled liquid temperature. In order to be good MEMS materials films should have

good corrosion resistance at least in the solution, which is used for the chemical etching of silicon. This is necessary because many integrated MEMS require chemical etching of silicon substrate in order to make freestanding microstructures. Therefore, corrosion behavior of Zr-based glassy thin films was also studied in a solution of 30 wt.% KOH in water, which is generally used for the anisotropic etching of silicon. A slight increase (before test Ra 0.2 nm, after test Ra 1.1 nm) in surface roughness was observed for the film left in KOH solution for 3 h at 70°C. The electrical polarization measurement that is generally used to test the corrosion resistance of a material points towards the high corrosion resistance and pitting free corrosion of these glassy films. Glassy alloy films were also compared with the SiO2 thin films that have high corrosion resistance in KOH, and are generally used as a protective layer for selective etching of silicon. Thermally grown SiO2, and Zr–Al–Cu–Ni thin films have the same surface morphology, that is, very smooth surfaces without granular structure (inset of Figure 27.17b), while the sputtered SiO2 films are observed to have a granular structure (Figure 27.19b). Moreover the sputtered SiO2 films were found to have very poor corrosion resistance in KOH, compared with thermally grown SiO2 and sputtered Zr–Al– Cu–Ni glassy thin films, because of the presence of grain and grain boundaries which acted as a weak point. 465

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Fig 27.19 ● Fabrication of Zr–Al–Cu–Ni glassy alloy thin ﬁlm membrane (a) process, (b) surface topography of sputtered SiO2 showing the nanogranular structure that explains the poor corrosion resistance of these ﬁlms compared with thermally grown SiO2 and Zr–Al– Cu–Ni glassy thin ﬁlm which has a very smooth and grain-free structure [Figure 27.17(b) inset], and (c) photograph of the glassy alloy thin-ﬁlm membrane on Si.

To demonstrate the very good masking ability or corrosion resistance of Zr–Al–Cu–Ni glassy alloy thin film, glassy alloy thin-film membranes were fabricated. The process for the fabrication of membrane is shown in Figure 27.19a. Zr–Al–Cu–Ni glassy thin film was deposited on both the faces of silicon substrate (0.525-mmthick and one inch square, polished both sides), but one face was physically covered by a mask (double-sided tape or thin metal foil) before deposition. In this way, a silicon substrate covered by the protecting layer on both the sides with some bared area (silicon windows) at one side was obtained. To get a Zr–Al–Cu–Ni glassy thin film membrane, the sample was kept in 30 wt.% KOH solution at 70°C for 19 h (Figure 27.19c). The success in fabrication of glassy thin film membranes on silicon substrate will open their application in fabrication of various types of sensors with enhanced sensitivity. For example, we have described the pressure sensor with metallic glass diaphragm, which possesses the high sensitivity. In addition to Young’s modulus, diaphragm thickness is inversely square to the sensors’ sensitivity (Eq. 27.1), therefore thinner diaphragms will lead to much higher sensitivities.

Among the various kinds of polymers tested, it was found that except for polycarbonate (PC) the glassy films have reasonably good compatibility with polymers like fiber-reinforced polybutylene terephthalate (PBT), polyphenylene sulphide (PPS) with glass fiber filler etc. Interestingly, glassy films exhibit very good adhesion on polyimide (known as Keptone), which is most commonly used in a variety of electrical and electronic uses at both high and low-temperature extremes: wire and cable tapes, formed coil insulation, substrate for printed circuit boards, motor slot liners, magnet wire insulation, transformer and capacitor insulation, magnetic and pressure sensitive tapes, and tubing. Figure 27.20 shows the Zr-based glassy thin films deposited on a flexible thin foil of Kepton polymer. Zr-based glassy thin films were also deposited in multilayers with other glassy thin films like La-based films. The cross-sectional observation of this multilayered structure revealed very sharp interface with good adhesion among the layers (Figure 27.20c cross-sectional sample made by FIB etching). Mechanical testing of these micron sized pillars made of multilayered glassy thin films showed enhanced plastic deformation compared with monolithic glassy films.

27.7.2 Compatibility with Other Materials

27.7.3 Tailorable Magnetic Properties

In order to test the compatibility of Zr-based glassy thin films with other materials, films were deposited on a variety of substrates such as oxides, semiconductors, metals, and polymers. After deposition had occurred, tape tests were performed for the adhesion. It was found that the Zr-based glassy thin films have very good adhesion to the metals, semiconductors, and oxides. 466

In addition to mechanical and chemical behavior, functional properties such as magnetism are also important for the fabrication of high-density memories, magnetic sensors, and magnetoelectronic and magneto-optic devices. Controlled growth and tailorable magnetic properties are required for the realization of these magnetic devices. Magnetic anisotropy and the Curie temperature (Tc) of a film are the key parameters, because

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Fig 27.20 ● (a) Zr-based metallic glass thin ﬁlms on ﬂexible polymer, (b) SEM image showing the good surface quality free from cracks (scale bar is 1 mm), and (c) Zr-based glassy alloy multilayered with La-based glassy alloy (scale bar 2.5 μm). Each layer thickness is 200 nm, white contrast layer is Zr-based and black is La-based.

Fig 27.21 ● (a) In-plane hysteresis loops measured at RT for the Co–Fe–Ta–B ﬁlms of different thickness. Inset shows the variation in Hc, and Mr/Ms ratio with ﬁlm thickness and the typical shape of the hysteresis loops observed for the thick ﬁlms. (b) AFM topographic image, showing the typical surface of the ﬁlms. (c) MFM image of 5.5-μm-thick ﬁlm in virgin state. (d–g) MFM images of ﬁlm after exposure to magnetic ﬁeld: (d) 5.5-μm-thick ﬁlm (e) 2.5-μm-thick ﬁlm (f) 0.63-μm-thick ﬁlm (g) 0.04-μm-thick ﬁlm (Area of AFM and MFM images is 20 20 μm2).

the former governs the magnetization or spin direction, and the latter tells about the existence of spin ordering up to a particular temperature (Tc). The ability to control magnetic anisotropy and Tc of a magnetic material is very much desirable from the application point of view. In general, the crystal structure of a material dictates its magnetic properties. As crystal structure is unique for a particular material, tailoring of magnetic properties is very difficult because they are dependent on the atomic positions, which are fixed by the crystal lattice. It is noticed that the small variations in atomic positions can result in a drastic change in magnetic properties or more precisely the magnetic anisotropy. The ideal situation for tailoring the magnetic properties of a material is to have the ability to change its interatomic distances. It is difficult in the case of crystalline materials, but it is possible for amorphous/glassy materials because their atoms are not bound to a particular lattice. In order to demonstrate the tailorable magnetic properties of glassy thin films, Co–Fe–Ta–B glassy thin

films were deposited and the effect of Zr dilution on magnetic and structural properties was studied [99, 100, 103]. The glassy Co–Fe–Ta–B films exhibit a very smooth surface (Ra 0.2 nm) with a large value of ΔTx 41K region and high thermal stability of glassy phase. Deposited thin films (0.04 μm) at RT are magnetically soft (Figure 27.21a). The magnetic domain state for the thin film is like a single domain (Figure 27.21g). The thicker films have out-of-plane magnetization with a stripe domain structure at RT (Figure 27.21c–f). Although the glassy state is not supposed to have anisotropy, short-range atomic ordering/stress can result in anisotropy. It was observed that the heat treatment is effective in removal of this anisotropy by relaxing the atomic structure. The Co–Fe–Ta–B glassy thin films of thickness less then 2.5 μm have very different magnetic behavior at low temperature (Figure 27.22). The same film exhibiting stripe domain structure that is perpendicular magnetic anisotropy at room temperature exhibits an 467

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Fig 27.22 ● (a) M(T) curves for Co–Fe–Ta–B ﬁlms having different values of ﬁlm thickness measured under an in-plane magnetic ﬁeld of 10 Oe, (b) M(T) curves for 0.63-μm-thick ﬁlm measured under different in-plane magnetic ﬁelds, and (c) in-plane hysteresis loops for 0.63-μm-thick ﬁlm measured at different temperatures.

in-plane single-domain-like state at low temperature. This means that the magnetization direction changes from in-plane single-domain-like to out-of-plane multidomain with increasing temperature (Figure 27.22a, c). This phenomenon is known as spin reorientation transition (SRT), and is mostly observed in the case of ultrathin ferromagnetic multilayers consisting of few monolayers. In the case of glassy thin films SRT persists up to the thickness of 2.5 μm [99, 100]. The value of SRT temperature (TSRT) in the as-deposited films strongly depends on the film thickness and the applied in-plane magnetic field during the measurements. The value of TSRT shifts towards the lower temperature with increasing film thickness and towards high temperatures with increasing in-plane magnetic field (Figure 27.22a, b). The value of TSRT for a particular film thickness can be tailored by heat treatment, which causes an irreversible change in TSRT. After heat treatment TSRT shifts towards the higher temperature. The SRT observed in the present case is not governed by the temperaturedependent magnetocrystalline or interface anisotropy, which is supposed to be the main cause for SRT in ultrathin films. On the basis of our experimental results on the thick Co–Fe–Ta–B glassy films and the reported data on ultrathin films, it is concluded that the atomic randomness and the stresses are the main causes for the occurrence of SRT. It is worthwhile to point out that the SRT phenomenon was not observed in the case of bulk glassy alloy of similar composition. In addition to tailorable magnetic properties, these films are also mechanically hardest. The Co–Fe–Ta–B films remain amorphous by the dilution with Zr up to 27.8 at.% [103]. However, the Curie temperature decreases linearly with an increase in Zr concentration. These results suggest that the magnetic properties such as magnetic anisotropy (SRT) and Tc can be tailored in case of glassy magnetic thin films and are quite promising for versatile magnetic manipulations and device development. 468

27.8 Micro/Nanofabrication Ability of Glassy Thin Films 27.8.1 Three-Dimensional Microforming Three-dimensional microforming of metallic glass thin films is mostly demonstrated by Hata and coworkers using the Zr–Al–Cu and Pd–Cu–Si glassy thin films deposited by sputtering technique [110–113]. MEMS conical spring actuators were fabricated by silicon micromachining combined with heating of patterned metallic glass thin films to a supercooled liquid state. Figure 27.23 shows the lift-off process which fabricates planner spiral shape structures of thin-film metallic glass. Figure 27.23a–g shows the schematic view of the method used for viscous flow microforming of patterned glassy film. In this process, arched aluminum foils were placed between the substrate and a microjig (Figure 27.23h). Using an infrared heating device, the substrate was heated to 678K at a rate of 10K/min in the vacuum chamber, and maintained there for 300 s. At 678K, the foils were softened and deformed by the substrate weight. The microjig pushed up the center of the glassy thin film spiral beam through a hole of the substrate (Figure 27.23i). Then the spiral beam of thin-film metallic glass exhibiting the viscous flow in a supercooled liquid state was microformed into a three-dimensional conical spring. Figure 27.23j, k show the SEM image of the microconical spring and section profile before and after microforming. A further electrostatic microactuator was fabricated as an application of the microconical spring. By combining the microforming ability of glassy thin films in a supercooled liquid region with conventional micromachining, Hata and coworkers fabricated various three-dimensional microstructures of glassy thin films, such as on chip variable microinductors, microlens actuators for optical flying heads, and microdome shape structures [111–113].

Metallic Glass (a)

(b) SiO2

Cr

(c) Al

(f)

Polyimide

(g)

Microjig

(d)

(e)

(h) Microjig

(i)

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TFMG

Spiral beam

Infrared light

Al foil

(k)

Y μm

(j)

500 400

Before forming

300 200 100 0 500 400

After forming

300 200 100 0 –100 0 100 200 300 400 500 600 700 800 X μm

Fig 27.23 ● Micromachining process of metallic glass microconical spring: (a) patterning of SiO2 and Cr-layer, (b) spin coating of polymide layer and patterning of Al-layer, (c) RIE of polymide layer and sputtering of thin-ﬁlm metallic glass (TFMG), (d) removing polymide and Cr layer (lift-off), (e) wet etching of silicon by KOH, (f) deformation using microjig (g) SEM image of microspiral beam, (h) and (i) schematic view of method used for microforming (j) SEM image of microconical spring, and (k) section proﬁle of the spring. Source: From Ref. [110].

27.8.2 Direct Milling by FIB To test the nanoscale patterning ability of the Zr-based glassy thin films, an FIB technique with a Ga ion source was used. Effects of working conditions on the nanoworkability of glassy as well as crystalline thin films (semiconducting ZnO, Pt, and Cr) were studied [98–102]. The resolution and ability of nanopatterning were found to depend on the material characteristics, irradiation beam condition, and dimensions of the fabricated patterns. A large variety of test structures having line width from micrometer to nanometer and depth below 150 nm (measured by AFM) were fabricated. Figure 27.24 shows the SEM and AFM images of the FIBfabricated patterns on crystalline (Pt thin film), and glassy (Zr–Al–Cu–Ni) thin films. Smooth etching of the film surface can be noticed for the metallic glass in contrast with crystalline thin films, which showed an uneven etching due to the presence of grain and grain boundaries (Figure 27.24). The absence of granular structure in the case of glassy alloy thin films allows fabrication of even complex patterns (Figure 27.24b, d, e) at the nanometer scale. It was observed that the sharpness and the capability

to fabricate small structures depend on grain size. Smallgrain-sized film showed a better patterning ability than the film having relatively larger grain size. However, the best patterns (smallest and finest) that we could fabricate were on the glassy (Zr–Al–Cu–Ni) thin films. A pattern of line width as small as 17 nm could be written repeatedly on the glassy Zr–Al–Cu–Ni thin films (Figure 27.24f). In the most stable beam conditions (FIB) a line width of 12 nm was also obtained and further reduction was limited by the instrument.

27.8.3 Imprinting in a Supercooled Liquid Region The polymer-like formability of metallic glass thin films in their ΔTx region can also be used for the fabrication of three-dimensional (3D) micro/nanostructures using the NIL imprinting process [102]. The superplastic microforming ability of glassy Zr–Al–Cu–Ni thin films deposited on Si substrate is demonstrated using a silicon V-groove die (Figure 27.25a). In this process, the glassy alloy thin film was heated in a vacuum to a temperature in the ΔTx region, and then 469

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Micromachining Technologies in MEMS Fig 27.24 ● SEM images of FIB fabricated patterns. (a) Pt thin ﬁlm showing the effect of granular structure on the patterning ability of a material, (b) complex pattern “Pikachu” character fabricated on glassy ﬁlms, which are free from granular structure (c) nanoscale line patterns on glassy ﬁlm, (d) logo of Institute for Materials Research fabricated on glassy ﬁlms, (e) AFM image of nanoword “Laboratory of Advanced Materials,” and (f) AFM analysis of 17nm line pattern which was fabricated repeatedly on glassy alloy thin ﬁlms.

Fig 27.25 ● Superplastic micro/ nanoforming of Zr–Al–Cu–Ni thin ﬁlms in ΔTx region by using micro/nanodies (a) SEM image of V-groove silicon die, (b) and (c) SEM and AFM images of imprinted pattern on the glassy alloy thin ﬁlm, (d) and (e) 3D AFM images of ZnMnO granular die, showing the needle-shaped grains, (f) inverse image of ZnMnO die obtained from AFM analysis software, (g), (h), and (i) imprinted nanoholes on the glassy alloy thin ﬁlm created by using the ZnMnO nanodie. The diameter of the hole marked with an arrow in (i) is 34 nm.

a die was compressively loaded with a pressure ranging from 10 to 20 MPa. Figure 27.25b, c show the SEM and AFM images of the imprinted pattern of the silicon V-groove die (Figure 27.25a) on the glassy alloy thin film. AFM analysis reveals the excellent reproduction of die features on the glassy alloy thin film and proves the superb microforming ability of the thin films. In order to demonstrate the nanoforming ability of these films, a ZnMnO (Mn 1.5 at.%) granular thin-film die, which possesses a needle-like granular structure perpendicular to the substrate (Figure 27.25d, e) was used. Figure 27.25g–i show the imprinted pattern of the 470

ZnMnO die on the glassy Zr–Al–Cu–Ni thin film. Large area imprinting of nanoholes (Figure 27.25i the size of the hole shown by the arrow mark is 34 nm) can be noticed in Figure 27.25g. In order to verify the proper imprinting of ZnMnO die, extensive AFM analyses of both the die and the imprinted patterns were carried out. Figure 27.25f shows the inverse pattern of ZnMnO die obtained from the AFM image analysis software; for proper printing, it should resemble the imprinted patterns on the Zr–Al– Cu–Ni glassy thin films. Although it is very difficult to obtain an image of the die and the imprinted patterns corresponding to exactly the same locations, the image

Metallic Glass

scanned over an area of 2.0 2.0 μm2 at different locations of the imprinted Zr–Al–Cu–Ni thin films (Figure 27.25f), and the inverse of ZnMnO die (Figure 27.25h) were found to be similar. The above experiment clearly demonstrates very good patterning ability on Zr-based glassy thin films,

CHAPTER 27

using the NIL imprinting process. It is worth mentioning that in addition to nano-patterning, the ΔTx region of metallic glass thin films is also useful for hermetic bonding of MEMS devices/components at lower processing temperatures than conventional eutectic bonding.

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Chapter Twenty Eight

28

Surface Micromachining Christina Leinenbach1, Hannu Kattelus2 and Roy Knechtel3 1

Robert Bosch GmbH, Stuttgart, Germany VTT Technical Research Centre of Finland, Espoo, Finland 3 X-FAB Semiconductor Foundries AG, Erfurt, Germany 2

In the early 1980s a new type of technology for the fabrication of micro electro-mechanical systems came into being [1]. In contrast to classical bulk-micromachining, which uses the single crystal silicon substrate itself as functional material for forming the desired devices by advanced anisotropic wet- or dry-etching technologies, this new technology uses thin ﬁlm layers deposited on the substrate surface as functional material. For this reason it was termed surface micromachining. Whereas bulk micromachining often requires processing steps from the backside of the wafer, including front-to-backside alignment in lithography, all processing steps in surface micromachining are performed from the front side of the substrate, thus rendering it more compatible with standard microelectronic technologies and also with increasing wafer sizes. Some of the pioneering companies who have adopted a surface micromachining process as the basis of their microsensor fabrication are Analog Devices and Motorola, both from USA, as well as Bosch from Germany, amongst others. Typical devices are pressure sensors and inertial sensors for acceleration and angular rate measurement, primarily used in automotive applications such as airbag, motor management or the electronic stability program (ESP) [2, 3]. More recently, new applications in mobile phones, computer peripherals, and games have become numerous. In the following, an overview of different types of surface micromachining processes is given. Conventionally, surface micromachined MEMS devices use polycrystalline silicon (polysilicon) as functional device layer, combined with silicon dioxide as sacriﬁcial material. For some

applications, like micro mirrors and RF-MEMS switches, metal is used as a functional layer. This will be regarded in detail in Section 28.3. Another alternative is the use of socalled silicon-on-insulator (SOI) wafers to produce highquality surface micromachined devices in a single crystal silicon layer (cf. Section 28.4). The main disadvantage of the latter approach is the high price of the wafer material.

28.1 Polycrystalline Silicon-Based Micromachining 28.1.1 Overview For the fabrication of a surface micromachined device, a sequence of thin layers must be subsequently deposited and structured on the front surface of a silicon wafer. Schematically, the cross-section in Figure 28.1 illustrates the process ﬂow and the layer sequence. First, a silicon dioxide layer serves to electrically insulate a highly conductive polysilicon that is used as buried wiring layer for the interconnection of the functional layer parts. Alternatively or in addition to this, the buried polysilicon material can be applied as a counter electrode in some sensor types. The deposition of a subsequent silicon dioxide supplies the insulation of the buried wiring layer from the functional layer and at the same time serves as the sacriﬁcial layer material, to be removed later in the process. On top of the stack, the silicon-based functional layer and a metal are deposited and structured individually. 473

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Fig 28.1. ● Schematic cross-section of the layer sequence, as used for the fabrication of inertial sensors: silicon substrate, insulating layer, buried polysilicon wiring layer, sacriﬁcial and insulating layers, and functional thick epi-polysilicon ﬁlm.

The metal in the outer area of the sensing elements contacts the buried wiring level of the sensor. Deposition techniques are low pressure, LPCVD, and plasma enhanced, PEVCD, chemical vapor deposition. The metallization for the electrical contact is typically generated by a sputter deposition process. A special technology that is applied to realize thick polycrystalline silicon is an epitaxial deposition process at temperatures above 1000°C, so-called thick epi-polysilicon. Lithography is used to deﬁne the lateral geometries of the structures on the wafer surface. The mechanical silicon elements—such as freestanding cantilevers or resonating structures—are patterned anisotropically by dry etching into the functional silicon. Typically, a deep reactive ion etching step, DRIE, is applied; see Figure 28.2. One of the most widespread processes is the so-called Bosch DRIE (cf. Chapter 23) [4]. The moving structures are ﬁnally released from the substrate by a sacriﬁcial etching process, where the material underneath the functional layer is partially removed selectively by isotropic wet, or semidry or dry etching. Attack of the functional layer must be avoided during this release step to secure the mechanical characteristics of the freestanding sensing structures. Finally a bulk-micromachined capping wafer, Figure 28.3a, or a thin membrane layer, Figure 28.3b, is used for the encapsulation of the sensing elements on the wafer level.

28.1.2 Functional Layer Development of basic technologies and pioneering introduction of MEMS products with thick polycrystalline silicon layers were done by Robert Bosch GmbH, a major supplier for automotive equipment. Polycrystalline silicon provides high potential as a functional layer material and is used to realize applications, such as accelerometers and gyroscopes. Low values of stress and stress gradient of the structural layer are essential for high performance of the micromachined devices. Polycrystalline silicon as a prevalent structural material in MEMS applications achieves the desired stress-related properties. The fabrication temperatures 474

Fig 28.2 ● SEM picture of silicon structure fabricated by DRIE.

are higher than 900°C to ensure the required material quality. Thin polycrystalline silicon MEMS-functional layers are only a few micrometers thick. The deposition of these layers is generally realized by CVD-processes. The epitaxial deposition process features a polycrystalline silicon layer with a thickness of more than 10 μm [2]. For the deposition an epitaxy reactor is used. The thick epi-polysilicon starts from a thin polycrystalline silicon layer as a seed for the epitaxy process. The combination of doping and subsequent annealing cycles yields optimized electrical and mechanical properties for functional layers. Doping proﬁle and structural-induced stress gradients compensate each other to result in a very small warpage of the freestanding sensing elements after release [5, 6]. The availability of a material with very low mechanical stress gradients enables the fabrication of surface micromachined functional elements for accelerometers and gyroscopes [7]. An alternative to polycrystalline silicon as MEMSfunctional layer material is polycrystalline silicon

Surface Micromachining

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Fig 28.3 ● SEM picture of (a) capping wafer (bulk-micromachined) for sensor encapsulation of a gyroscope, and (b) thin ﬁlm sensor encapsulation: detail of a membrane layer on top of epi-polysilicon sensor structures.

Fig 28.4 ● (a) SEM picture of polycrystalline silicon germanium test structures for in-plane rotational vibration, and (b) SEM micrograph of LPCVD-SiGe with polycrystalline microstructure.

germanium (poly-SiGe), Figure 28.4a. A key advantage of this alloy is the opportunity to cut down the deposition temperatures considerably. This allows the cost-effective integration of MEMS components on preprocessed wafers containing active integrated electronic circuits [8–10]. The presence of germanium results in a substantial reduction of the required deposition temperatures for the SiGe alloy to grow in polycrystalline morphology. Depending on the Ge-content, the transition temperature from amorphous to polycrystalline texture can be lowered down to 450°C as compared to 580°C for poly-Si [11, 12]. The mechanical properties of the polycrystalline thin SiGe ﬁlms such as stress gradient are caused by the microstructure varying over the ﬁlm thickness, as shown in Figure 28.4b. An optimization

of the SiGe crystal structure might be achievable by alloying with other elements (reducing the strain in the crystal lattice) or by choosing appropriate CVDdeposition parameters [9]. Reduced stress gradients allow the production of SiGe MEMS with high demands like gyroscopes. Poly-SiGe deposition techniques like LPCVD processes suffer from low deposition rates (2–30 nm/min). A higher deposition rate of up to several 100 nm/min can be obtained using plasma-enhanced CVD processes allowing for thick ﬁlm deposition within a reasonably short amount of time [8]. In comparison with the well-known epi-polysilicon material, the mechanical stress gradient of low-temperature fabricated poly-SiGe needs to be further optimized. 475

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28.1.3 Sacriﬁcial Layer Using conventional silicon dioxide as sacriﬁcial layer material, the release of the functional silicon structures is achieved by removal of the silicon dioxide in a hydrogen ﬂuoride (HF) based etchant (either wet or vapor phase). Great care must be taken to prevent sticking of mechanical sensor elements during or immediately after the release etch, and during sensor operation: Since mechanical forces ( pullback forces from the mechanical springs), electrostatic forces, Van-der-Waals adhesion forces, and chemical bonding forces appear on the same scale of sizes, extended parts which enter into contact with each other are hard to release again. Note that drying liquids, through their surface tension, tend to pull structures together and bring them into unwanted contact. To prevent stiction during or immediately after the release etch, dedicated techniques had to be developed: Vapor phase etching in hydroﬂuoric acid vapor as an alternative to liquid phase etching prevents the formation of droplets underneath the released structures and completely avoids any need for subsequent drying [13]. Wet etching in hydroﬂuoride acid liquid requires either mechanical ﬁxations of the sensor structures in the form of photoresist spacers, etc., which can be plasma-ashed in an oxygen plasma stripper after the etch-and-dry procedure [14], the use of supercritical drying like CO2 [15], or freeze-and-dry procedures based on the sublimation of organic solvents [16], thereby avoiding going through a liquid phase during the ﬁnal drying procedure. A new sacriﬁcial layer and etching technology for the surface-micromachining of MEMS is poly-SiGe in combination with polysilicon as active functional layer. Applying a new plasmaless dry etching technique based on ClF3gas, SiGe can be etched with an extremely high selectivity of up to 5000:1 with respect to silicon; see Figure 28.5. This dry sacriﬁcial release process opens new opportunities for enhanced design freedom, and increased underetching ranges and speed, and offers full compatibility

to most dielectric and metal materials, and to monolithic integration with electronic circuitry on the same chip. Using SiGe as silicon-based sacriﬁcial material vs. polysilicon does not demand explicit protection of silicon functional structures by thin-ﬁlm layers, thanks to the high selectivity between both materials. This, together with the extremely high under-etching speed and etching range, considerably expands the process portfolio for the fabrication of novel surfaced micromachined systems [17].

28.1.4 Surface Micromachining Application—Accelerometer Today a preferred technology for surface-micromachined sensors uses about 10- to 20-μm-thick poly- or monocrystalline silicon for the active structures [18]. The mass and comb-structure arrangement is fabricated by Bosch DRIE, which has reached a high level of accuracy and maturity over the past few years, mainly driven by applications like the accelerometer and gyroscope. As an example, Figure 28.6a shows an SEM picture of

Fig 28.5 ● SEM cross-section of freestanding beams made from polysilicon functional layer on top of poly-SiGe sacriﬁcial layer after structuring by DRIE and under-etching the SiGe-layer in ClF3-gas for structural release.

Fig 28.6 ● Accelerometer from Robert Bosch GmbH: (a) detail of structure, (b) schematic structure.

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a front airbag accelerometer from Robert Bosch GmbH fabricated in a 10-μm-thick polysilicon technology [19]. The gaps between the interdigitated ﬁngers are only 2.5 μm wide, resulting in a base capacitance of the differential capacitor arrangement in the order of 0.5–1 pF. Capacitance changes for full-range acceleration are typically an order of magnitude smaller. Figure 28.6b illustrates the working principle of this type of accelerometer: Acceleration moves the seismic mass out of position and changes the gaps of the interdigitated differential comb capacitor arrangement. The resulting capacitance changes are converted into an electrical signal. During operation, sticking can be prevented by mechanical stoppers restricting the surface areas which could possibly get in contact with each other, for example, in an overload situation. In addition, appropriate coatings are widely in use such as plasma-deposited teﬂon-like layers or self-assembled monolayers (SAMs) exhibiting very low surface energy, to proﬁt from their reduction of adhesion forces by several orders of magnitude [20]. Should structures get in contact, the remaining adhesion forces are easily overcome by the pullback forces from the mechanical springs.

28.2 Integration Concepts Monolithic integration seems to be a good choice for evaluation of capacitive surface-micromachined sensors, given their low base capacitance values (in the order of 0.5 pF), if a high sensitivity and resolution is needed. The small capacitances are an immediate consequence of the surface-micromachining approach, with small size and layer thickness. A decision to go for monolithic integration is even more supported by shrink tendencies aggressively targeting the size of the sensor core, e.g., toward 50*50 μm2. In an IC process, surface area is getting expensive due to the accumulation of process costs through up to 30 masking levels. Chip yield, i.e., the total number of functional chips per wafer, directly determines the ﬁnal chip price. Integrating a sensor process into an IC process necessarily adds to the chip size, reduces overall yield (larger size, higher chip failure risks), and increases total process complexity and costs. The resulting higher costs have to compete with the extra costs for the mounting and wire bonding efforts in a two-chip solution—provided the two-chip solution can meet performance requirements. There are some advantages in hybrid integration concepts: Hybrid integration is a modular approach; both sensor and electronics can be developed and processed separately, which reduces development time and costs, risk, and time-to-market. This includes the ﬂexibility of easily switching over to a new generation of sensor

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elements or a new IC process generation, having both processes completely decoupled. In addition, ﬂexibility with respect to sensor packaging is high in a two-chip hybrid solution, offering a number of opportunities both for inner and outer sensor packaging. The choice is much more restricted if compatibility to a surrounding delicate circuit area must be maintained. Thin-ﬁlm hermetic packaging of the sensor cores as part of a MEMS-ﬁrst integration concept points to a completely new direction of technology which is on its way to entering the market for timing devices as a ﬁrst application ﬁeld [21]. This breakthrough technology may probably change the pros and cons of monolithic integration in the future for a wider range of applications, including inertial sensors.

28.2.1 Monolithic Integration— Gyroscopes Gyroscopes are in most cases built as hybrid solutions today, with sensor and electronics as two separate chips. With Coriolis forces being very small, the electronic evaluation circuit has to resolve capacitance changes on the order of a few tens of atto-Farads (aF). These extremely small capacitance changes are hidden by parasitic capacitances in the order of 10 pF, mainly from conducting lines, large bondlands, bond wires, and the EMI protection diodes for the ampliﬁer inputs. Obviously, these large parasitics represent a signiﬁcant limitation to the achievable performance of the gyroscope. Monolithic integration offers opportunities for reducing parasitics by more than an order of magnitude, to below 1 pF, with a corresponding increase in sensor performance (omission of bonding pads, wires, and input protection network, together with new circuit concepts like baseband evaluation) mainly with respect to signal-to-noise ratio. For purely surface-micromachined gyroscopes, given their small sizes and capacitances, monolithic integration is a potential option to be considered not mainly for cost but for performance arguments.

28.3 Metallic MEMS 28.3.1 Roles of Metallic Thin Films in MEMS There are different roles for metallic thin ﬁlms in MEMS. Perhaps the most important ones can be listed as follows: Micromirrors for projection displays RF-switches and variable capacitors Mold inserts The device that makes Texas Instruments a leading company in the MEMS market is the Digital Micromirror ■ ■ ■

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Device (DMD), a key component in DLP® projectors [22]. It is fully based on metallic MEMS, and the miniature mirrors and their supportive springs are made of metallic alloy rather than silicon. The main reason for using metals in this application is that high processing temperatures (400°C) are not tolerated when devices are monolithically integrated over fully processed CMOS memory wafers. Of course, the mirrors also need to be better optical reﬂectors than silicon is. Another ﬁeld where metallic materials are needed is RF-MEMS but for different reasons from those given above. The electrical conductivity must be higher in RF applications than semiconductors can offer [23]. Usually, as high conductivity is needed as possible in parts where RF current is carried. The layers also need to be relatively thick, often several micrometers, depending on frequency of operation and application. High-precision, high-aspect-ratio—typically, unmovable—parts can be made of various materials using a method called LIGA [24]. It is based on ﬁlling a 3D structure by electroplated metal. Techniques like LIGA are, however, beyond the scope of this book.

Table 28.1 Indicative properties of metals relevant in MEMS. Values may vary in different sources and also differ for thin ﬁlms from bulk data

Material

Electrical resistivity (108 Ωm)

CTE (ppm/°C)

Young’s Density modulus (g/cm3) (MPa)

Copper

1.7

17

120

8.9

Gold

2.4

14

78

19

Aluminum

2.8

23

69

2.7

Molybdenum

6

5.4

220

10

Mo–N 110 (amorphous ﬁlm)

–

240

8.7

Mo–Si–N 1000 (amorphous ﬁlm)

4

190

5.1

3

170

2.3

Si

5000

28.3.2 Important Properties of Metals in MEMS Applications 28.3.2.1 Electrical Conductivity It is clear that the electrical conductivity of semiconductors is not satisfactory for all needs of MEMS. The most prominent driver for MEMS based on good conductors is RF-MEMS. The insertion loss is at an acceptable level in several cases only if noble metals or aluminum are used. Aluminum is favoured if processing has to be completed in a waferfab compatible with active device (CMOS) integration; otherwise, gold or copper are good candidates. Electrical resistivities for some metals relevant in MEMS are listed in Table 28.1.

Fig 28.7 ● Properties of polycrystalline ﬁlms vary with ﬁlm thickness due to gradual grain growth.

28.3.2.2 Low-Temperature Processing

28.3.2.3 The Importance of Controlling the Microstructure

Sometimes MEMS structures have to be completed over delicate materials or device wafers that do not tolerate high processing temperatures. Metals, in contrast to doped and activated semiconductors, can be deposited at or near room temperature, for example, by sputter deposition or electroplating. Low temperature brings along the possibility of using polymeric sacriﬁcial layers instead of silicon oxide, and oxygen plasma for their removal. This property is successfully used in manufacturing the DMD [22], simplifying device packaging and improving yield. Polymeric sacriﬁcial layers can be left in place during wafer dicing and removed at a late stage of the process ﬂow, sometimes even after mounting in the package.

All elemental metals are polycrystalline at room temperature. During deposition initial nucleation takes place at localized centers and the crystallites gradually grow while the deposition proceeds. Film structure is nearly amorphous at early stages while well ordered toward the top part of the ﬁlm; see Figure 28.7. Such evolution of the ﬁnal ﬁlm structure results in mechanical properties that are dependent on ﬁlm thickness. Also, properties for polycrystalline ﬁlms often vary in different parts of the processing chamber due to variations in the effective angle of incidence of the depositing and bombarding atoms and ions. Microstructural variations reﬂect many important properties, from the point of view of MEMS, such as stress.

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10 Film stress transition pressure AR sputtering unless noted

4

Cylindrical - post magnetrons

2

Pressure (APa)

1

Nb Zr

V Ni Ti SS Cr/Kr Al Cr Tension Mo / Xe 0.2

Ta Ta w Gd

Rh

Pt Mo/Ne

Mo

0.4

Rectangular planar magnetrons

Mo

0.1

Fig 28.8 ● Vertical stress gradient causes delaminated beam to bend.

Compression 0.04

Cr

0.02

28.3.2.4 Stress A very important property for self-supported metallic structures or membranes is stress. The membrane must have a low biaxial residual stress and a low stress gradient in the vertical direction. Otherwise, the membrane will bow up or down, resulting in a large change in the actuation voltage [23]. Sometimes, the beams delaminated from the substrate roll up severely (Figure 28.8). In sputter-deposited ﬁlms, the net intrinsic ﬁlm stress is a function of a multitude of process parameters, of which probably the most important is the atomic mass of the target metal relative to that of the sputtering gas (mtarget/mgas), usually argon. Light metal ﬁlms tend to be under tensile stress; heavy metals, compressively stressed [25]. The best tuning parameter for controlled stress is argon pressure. Increasing the pressure drives the ﬁlm toward tensile state, although usually in a very nonlinear fashion. Empirically, a transition pressure has been observed, dependent on mtarget/ mgas and the conﬁguration of the sputtering system, where relatively abrupt structural change takes place (Figure 28.9) [25]. When sputtering takes place below the transition pressure, intensive argon bombardment of the growing ﬁlm results in compression; above that, gas-phase collisions inhibit such “atomic peening”. Since the average incident angle of the bombarding atoms is also inﬂuential, it is seldom possible to get good uniformity of stress over the entire lot in large batch reactors. Single-wafer sputtering tools with a target much larger than the wafer offers improved stress control for MEMS. In electroplating the ﬁlm stress can be a severe issue as well. As in the case of sputtering, the stresses have been observed not to be of thermal origin only but an intrinsic, depositionrelated term sums up. Transition metals appear to be in highest tension. Practical hints in controlling the stresses in electroplated ﬁlms are given in Ref. [26].

0.01 0

1

2

3

4

5

Mass ratio (Mt / Mo)

Fig 28.9 ● Argon transition pressure vs. atomic mass of sputtercoating material for tensile-to-compressive stress reversal in various metallic ﬁlms [25].

28.3.2.5 Coefﬁcient for Thermal Expansion Thermal cycling of the metal ﬁlms is practically unavoidable. Film deposition, passivation, and packaging take place at elevated temperatures. Upon cooling down thermal stresses are accumulated, the more the larger is the difference between the coefﬁcient for thermal expansion (CTE) of the ﬁlm relative to that of the substrate. Unfortunately, the best electrical conductors differ most in that respect from silicon. Sometimes, speciﬁcally in the case of aluminum having a low melting point, thermal stresses relax through generation of protrusions (hillocks, whiskers). They can short an air gap in a MEMS device. See Table 28.1 for CTE values.

28.3.3 Amorphous Metallic Alloys As discussed previously, it is very difﬁcult to control the microstructure, and thus properties, of polycrystalline metallic ﬁlms reproducibly, especially in large batch reactors. The stress not only varies in different parts of the reactor but can also be several hundred MPa different on a single wafer when measured along perpendicular directions [22, 27]. A possibility to circumvent the problem is using amorphous metallic alloys (See Chapter 27). Since all solid elemental metals are polycrystalline at room temperature, the simplest amorphous metallic materials are binary alloys. When two dissimilar elements are intermixed in proportions that cannot conform to a speciﬁc compound, they may constitute an 479

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0

600

2

Counts

9

400 300

Partial pressure of nitrogen (%) in the sputtering plasma

5

500

Labels:

13 17 26

200 100 0 35 36 37 38 39 40 41 42 43 44 45 2θ (°)

Stress, compressive (Mpa)

700

0 –200 –400 –600 –800 –1000 –1200 –1400 –1600 –1800 –2000

Mo target

Amorphous Mo–N Parallel to target Perpendicular to target 0 5 10 15 20 25 Relative nitrogen partial pressure (%)

30

Fig 28.10 ● (a) When Mo–N ﬁlms are deposited between 13% and 17% nitrogen in the sputtering gas, X-ray diffraction shows amorphous structure; (b) the same, amorphous compositions (13–17% nitrogen in the sputtering gas) show uniform stress distribution over the wafer, not dependent on bow measurement direction [27].

amorphous alloy. There are rules reported in the literature according to which the formation of the amorphous structure can be predicted (See Chapter 27) [28]. An example of binary amorphous alloys is the ﬁlm formed by sputtering molybdenum in a nitrogen-containing ambient with nitrogen concentration between Mo and Mo2N, 0n33 at.% N; see Figure 28.10a. Ternaries and more complex alloys can have further improved stability with crystallization temperatures approaching or exceeding 1000°C. Of these, for example, Ta–Si–N and Mo–Si–N have been tested in micromechanical structures and devices [29, 30]. It has been shown that for Mo–N, the dependence of stress on measuring direction relative to the sputtering target attitude is smaller the more nonordered the structure is (Figure 28.10b). Amorphous ternary Mo– Si–N shows further improved properties (Figure 28.11). Its net stress can be tuned to zero by optimizing the argon pressure during sputtering, and the vertical stress gradient is minimal. It has also been observed that amorphous hinges are essential in developing reliable micromirror devices for commercial manufacturing [31]. Ti–Al amorphous alloys are the key for the success of DMD of Texas Instruments.

28.4 SOI-Wafer-Based Surface Micromachining 28.4.1 Beneﬁts of SOI Wafers for Surface Micromachining In addition to the sacriﬁcial layer based surface micromachining technologies introduced so far, which use polycrystalline silicon, silicon germanium, or metals as mechanical active layers, SOI-wafer-based surface 480

Fig 28.11 ● Polycrystalline molybdenum ﬁlms show 300–400 MPa difference in stress values measured in two perpendicular directions on the wafer, while amorphous Mo–Si–N ﬁlms show no difference. It is impossible to tune the former into a zero stress state, but for the latter it is straightforward [27].

micromachining technologies are now state-of-the-art and commercially available as MEMS foundry technologies, as offered, for example, by X-FAB Semiconductor Foundries [32]. This special substrate provides many technological beneﬁts, despite being cost intensive. However, the main advantage is that the moveable structures are made from a single crystalline device layer of 15μm, and hence have excellent, well-deﬁned mechanical properties and high reliability. From a technological point of view, the buried oxide layer can be used in different ways: as an etch stop layer during the structuring of the device silicon, for protection of the device layer during under-etching, or as a sacriﬁcial layer. As a result, the rather complex and expensive SOI starting material provides many advantages and technical and technological features which make it worthwhile

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Fig 28.12 ● Relationship of SOI wafer conﬁguration to surface micromachined structure.

to use. Figure 28.12 shows the relationship between an SOI wafer and a surface micromachined structure made from it.

28.4.2 Technology The SOI-wafer-based surface micromachining technology has been developed for capacitive inertial sensors. It provides a capacitive readout of the seismic mass movement as the sensor signal but also electrostatic actuation, so that it is suitable for acceleration and vibration sensors as well as for complex microsystems such as gyroscopes. For the realization of the complex mechanical structures (seismic mass, comb drives, readout capacitors), trenches and holes are etched anisotropically in the 15-μm-thick device layer of the SOI wafer, down to the buried oxide, retaining the shape of the mechanics. For this isotropic silicon structuring, the Advanced Silicon Etch process is used (c.f. Chapter 23) to realize perpendicular smooth sidewalls which subsequently act as capacitor plates in the application. For advanced shape control of all structures, a deep submicron precise stepper exposure is used. This provides a general high precision, and in particular, good matching in differential mechanics as often used in gyroscopes. The minimal gap between the capacitor plates is deﬁned in the design rules as 2 μm to enable reproducible, well-controlled etching. So ﬁnally, an aspect ratio of the trenches and of the capacitor plate height to a gap of 7.5:1 is reached, which is a very good value for manufacturing high-performance capacitive sensors. In order to release the mechanical structures, the sidewalls of the etched silicon structures are passivated with CVD oxide, and the buried oxide is opened at the bottom of the trenches. By using isotropic etching into the handle wafer silicon, the structures are then under-etched and their ends released. During this etching step, the essential mechanical structures are packed into a protective oxide all around, so that they are not attacked in any way. In this process, the structure width deﬁnes whether a structure becomes moveable

if it is smaller than 4 μm or remains ﬁxed if larger than 30 μm in all directions. This large gap in structure size for moveable and ﬁxed structures is related to the fact that the under-etching depends strongly on the size of neighboring etch areas beside the structure being under-etched. The larger these are, the larger the underetching will be. However, from this set of rules, a safer design of moveable and ﬁxed structures becomes possible. Subsequently, any remaining oxide is stripped from the mechanical structures by HF fume etching, so that only pure single crystalline silicon remains. Fume etching is used because an isotropic etch process is required, and any wet etching would cause sticking of the easy-tomove mechanical structures, particularly in the areas of comb drives. Because a sharp tipped shadow of active mechanical structure is etched by the under-etching into the handle wafer, there is no risk of sticking to the ground. Finally, as a result of this etching, the mechanical structures are free of intrinsic stress, while the anchor points ﬁxed by the buried oxide of the SOI wafer to the base have not introduced appreciable stress into the structures. The microstructured stress-free single crystalline silicon provides the best conditions for high performance reliable MEMS devices (Figure 28.13). To improve the electrical behavior of these types of device, reﬁlled insulation trenches are processed prior to the fabrication of the mechanical structures. These trenches separate the moveable structures as well as the bond pads from the surrounding chip, and allow deﬁned electrical contacting of the different MEMS elements by metal wiring. However, the main beneﬁt of the trenches is the reduction of parasitic capacitances, which greatly increases the performance of any capacitive sensor. Furthermore, an insulation layer between the device layer silicon and the metal layer in the area surrounding the mechanical structures provides the possibility of complex low parasitic electrical wiring around the mechanical structure. Finally, the mechanical structures are sealed with a capping wafer using glass frit wafer bonding. The capping wafer is prestructured with through-holes to reach the bond pads after bonding, 481

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Fig 28.13 ● Example of MEMS structure realized by SOI-waferbased surface micromachining.

and cavities over the sensor structures to reduce damping. This bonding provides an effective protection of the very sensitive mechanical structures at the wafer level, and makes standard wafer probing, dicing, and assembly processes possible. Due to the planarizing effect of the soft glass frit during bonding, metal lines for driving and sensing signals can be embedded in the glass and hermetically sealed by this, so that low pressures for high Q-factures can be realized in the sensor cavity. Because capacitive sensor elements, which typically provide low signals, are generally EMC sensitive, the back and front sides of the bonded wafer stack are metallized to enable effective shielding by connecting the cap and base to ground. Figure 28.14 shows the general process ﬂow of the surface micromachining foundry technology for gyroscopes and other inertial sensors.

28.4.3 Design Support and Special Features The introduced SOI-wafer-based surface micromachining process is a ready-to-use MEMS Foundry Technology offered by X-FAB Semiconductor Foundries AG., described by process [33] and design rule [34] speciﬁcations. The process speciﬁcations contain all wafer-process-related information required in the design process and for assembly. The main process ﬂow, including sensor and capping wafer as well its bonding, is described, and in addition, the wire bond pad conﬁguration. Special tables provide data on the starting SOI wafer, layer thicknesses, operation conditions (voltages, current densities), process control parameters, and structural/geometrical, electrical, and parasitic parameters. The design rule manual deﬁnes all process layers and describes the rules for these layers, using minimum widths such as for the mechanical structures, or ﬁxed widths as for the insulation trenches, and minimum spacings such as for the metal lead through 482

ducts under the glass frit. In addition, the relationships of the process layers to each other are deﬁned by enclosure, extension overlap, and spacing rules. Even if the surface micromachining process is, in principle, layer related and the 3D character of the resulting MEMS structure is mostly deﬁned by the device layer thickness and isotropic under-etching, very complex geometries are typical which cannot be completely controlled in a layer-based design process. Therefore, the surface micromachining process was modeled using a process simulation tool (Coventor, Inc., MEMulatorTM [35]), which enables the transition of a GDSII design ﬁle into a 3D model to check critical design elements and to optimize these for manufacturing. Figure 28.15 shows an example and a comparison with a real structure. In order to build up a capacitive inertial sensor design, for example, for the manufacturing of gyroscopes, special design elements such as comb drives, anchors, anchored silicon contact lines, or ﬁxed-to-moved transition elements are required in each case. These elements are part of the design rule speciﬁcation. They are described as devices rules under consideration for the technological aspects of such special geometric conﬁgurations. As an example, the comb drive element will be introduced here. Figure 28.16 shows the principle drawing of this kind of comb drive together with the main rules. MECH is an abbreviation for the mechanical structure layer. W1MC is the width of the comb drive ﬁnger and has to be in the range of 2 μm (photolithographic and etch resolution) to 6 μm (for safe release under-etching). The minimum gap between two mechanical silicon structures is S1MC, deﬁned as 2 μm. To prevent bending and sticking of the comb drive ﬁngers during wafer processing and operation, the ﬁnger length is limited to 75 times the ﬁnger width, i.e., to 150 μm in the most frequently used case of 2 μm wide ﬁngers (rule W4MC), but it can be up to 450 μm for 6-μm-wide ﬁngers. The anchored line of the ﬁxed part of the comb drive must be 35 μm wide to prevent complete under-etching. By use of these types of device rule, complex structures are given to the MEMS designers to achieve a fast design process, but by providing ranges of design measures (e.g., 2–6 μm ﬁnger width) and additional rules linked to these by calculation formulae, design ﬂexibility is guaranteed. In addition to these special elements described in the design rule manual, the technology provides a wide variety to the MEMS designer for designing highperformance MEMS elements. The metal wiring on the insulation layer in the periphery of the mechanical structures, with line width and gaps of 4 μm, allows a complex wiring with shielding lines and also metal wiring inside the mechanical structure on ﬁxed anchored elements. In addition, crossings of metal lines can be realized if one of the crossing lines is connected down to

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(a) Insulation trench etching in starting SOI wafer

(b) Insulation trench filling and surface planarization

(c) Metal layer deposition and structuring

(d) Trench etching mechanical structures and BOX opening

(e) Sidewall passivation and trench bottom opening

(f) Isotropic under-etching of the moveable structures in the handle wafer

(g) Stripping etch mask, side wall, and buried oxide

(h) Cap wafer (with outer side contact) bonding using glass frit

Fig 28.14 ● General process ﬂow of the surface micromachining foundry technology for gyroscopes and other inertial sensors.

a trench-insulated part of the device wafer (Figure 28.17). Therefore, one-and-a-half metal layers are actually available for complex wiring. Additionally, very complex mechanical structures can be realized in this surface micromachining technology due to the fact that moveable structures of width from 2–6 μm can be combined together with anchors and

ﬁxed structures of different sizes. This provides the opportunity to the designer to realize electromechanical compensation structures, special distributed seismic masses, or comb drive variations. This, in combination with the standard technology, can be used for a wide range of applications from high-performance gyros for navigation and automotive to low-cost customer applications. 483

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Fig 28.15 ● 3D Model of a gyroscope structure and comparison with the realization.

Anchored line

W1MC MECH

MECH

S1MC

W4MC

Comb Rule W4MC W7MC

Maximum MECH width for length of an under etched 2 μm finger in a comb structure........150 μm Minimum MECH width for a silicon anchor line near a comb structure........35 μm

Length of finger To omit sticking the ratio between finger length and finger width has to follow the rule: W4MC ≤ 75 * W1MC for W1MC = 2–6 μm

W7MC S1MC

Fig 28.16 ● Design rule example of device element comb drive (extracted from design rule spec).

28.4.4 Qualiﬁcation

Fig 28.17 ● Complex metal wiring opportunities in the surface micromachining foundry technology: (a) wire crossing via ﬁlled trench insulated device layer island, (b) complex metal wiring close to mechanical structure.

Additionally, engineering support is provided to the customer before and during the design phase, enabling the customer to create a design ﬁtting all requirements from production and application aspects. 484

The Surface Micromachining technology is qualiﬁed for automotive applications. By using testing based on JEDEC JP001 [36] standard accelerated aging tests, such as temperature cycling (65°C/150°C), autoclave (121°C/100%RH), and high-temperature bake (175°C), a high reliability with respect to both electrical and micromechanical properties has been proven. Additional mechanical shock and vibration testing conﬁrmed overload robustness of the mechanical structures, which is reached by stopper structures in the active working directions and bumpers at capping wafers, both of which are described in the design rule speciﬁcation. Finally, the wafer bonding interface of the gyroscope chips was tested regarding bonding strength (stud pull test) and hermeticity (resonance behavior). In both cases, the high bond strength and hermeticity found after processing was not inﬂuenced by the three reliability tests mentioned above. Consequently, the technology can be used for high-quality demanding applications such as automotive gyroscopes, even if a ﬁnal device qualiﬁcation is still required, in order to pay

Surface Micromachining

attention to inﬂuences of the actual design and the chip packaging.

28.4.5 Fields of Application The described MEMS foundry process based on SOI wafers is running in a state-of-the-art MEMS line, using modern equipment (e.g., stepper for exposure of the mechanical 2-μm-structures). It can be used not only for high-quality and very precise applications, but also for gyroscopes targeting the low-cost consumer market. In addition to gyroscopes, the technology is well suited to other inertial sensors such as acceleration or vibration gauges, while it can be also used for thermal sensors or MEMS resonators. The application ﬁelds of the ﬁnal MEMS elements are also very wide. Due to a high performance and reliability level and high degrees of freedom in design, they can be used for automotive, medical, consumer, industrial, and other applications. The single crystalline active silicon layer of 15 μm thickness provides excellent mechanical properties and reliability for all MEMS applications. Providing a well-described automotive-qualiﬁed MEMS foundry technology is a contribution to the beginning of standardization in MEMS processing.

28.4.6 Alternative SOI-Wafer-Based Surface Micromachining Technologies In addition to the described process, there are also other SOI-wafer-based technologies. The buried oxide of the SOI wafer can be used as a sacriﬁcial layer. After creation of mechanical structures these can be released by isotropic (fume) etching of the buried oxide. This is a classical under-etching again depending on the width moved, and ﬁxed structures can be realized (Figure 28.18). However, the approach suffers from two serious disadvantages: The gap provided by the removed buried oxide of a few 100 nm thick is very small, so that thin ﬁlm damping effects are really critical. In addition, sticking of the structures down onto the handle wafer can easily occur related to residual stress, humidity, or charges. Both issues can be resolved by using highly advanced SOI wafer substrates. Anti-sticking SOI wafers are reported in the literature [37]. Before bonding the handle and later the device wafer, surfaces are micro-roughed

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and both covered with later buried oxide, which is polished to make them bondable (roughness planarization). After the release etching of the buried oxide in the sense of sacriﬁcial layer etching, the silicon structures cannot stick down onto the handle wafer, because both corresponding surfaces are rough. If a larger precise gap is required, a double-layer SOI wafer can be used. In this case, the under-etching can be done by silicon etching in the lower (ﬁrst) device layer, and from this, very precise gaps in the range of several hundred nm to a few micrometers can be realized. If more complex SOI wafers with buried cavities under the later moveable mechanical structures are used, a very simple surface micromachining process is possible [38]. The membrane with a thickness of several tens of micrometers over the cavities has to be structured only by advanced silicon etching to get moveable structures for capacitive acceleration sensors or gyroscopes. By this, more simple etching steps with increased aspect ratio of the trenches/structures to the thickness of up to 1:50 are possible (Figure 28.19). Since in this technology variant under-etching is no longer required, compact masses without holes are possible, which simpliﬁes the design process and increases the sensitivity of seismic mass based sensors, due to their increased mass value. In addition to the fact that very special substrates have to be used, a major technology drawback is the over-etching when the ﬁrst membranes are already etched to ﬁnish etching at all chips of the wafer. If there is an oxide on the bottom of the cavity, reﬂected etch radicals during the over-etch can damage the back surfaces of the micromechanical structures. Without oxide in the cavities there will be a shadow of the mechanical structure etched into the cavity area, which can negatively inﬂuence the sensor performance. As a result, ﬁnally, for this rather simple technology, the etching is a highly sophisticated process step. All of these examples of alternative SOI-waferbased surface micromachining technologies ﬁnally show that it is possible to transfer process steps of the essential micromachining process to special engineered substrates. This transfer is not only related to the processing, but also to the costs. Thus, a rather simple process using complex and by this, expensive, substrates ﬁnally reaches the same costs as a rather complex foundry process which requires only standard SOI wafers. Additionally, by using prestructured SOI wafers, process

Fig 28.18 ● Alternative SOI-wafer-based surface micromachining technologies, (a) using buried oxide as sacriﬁcial layer, (b) double SOI structure, under-etching in ﬁrst thin silicon layer.

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Fig 28.19 ● Surface micromachining using pre-structured SOI wafers.

ﬂexibility is lost, because a larger amount of special substrates have to be prepared in advance, while design changes must ﬁt to the substrates. Additionally, there are limitations to the cavities and the membranes in size and shape. Large membranes require supporting pillars to prevent fractures during device wafer thinning. Even if these pillars can be used as anchors in the mechanical structures, they must have a large area (some hundreds of square micrometers), because they need to be bonded

well during SOI–wafer bonding. In ﬁnal conclusion, none of the introduced technology variants can be recommended as the best one. Rather it must be checked which surface micromachining process ﬁts best with the application, its required performance, the targeted device size, and price. However, the SOI-wafer-based foundry technology provides the highest degree of freedom and ﬂexibility in design and technology, and therefore this was introduced in detail.

References 1. J.M. Bustillo, R.T. Howe, R.S. Muller, Surface micromachining for microelectro-mechanical systems, Proc. IEEE 86 (1998) 1552–1574. 2. C. Gahn, S. Finkbeiner, M. Fürtsch, A. Kaschner, M. Offenberg, The Bosch silicon micromachining foundry service, in: Proceedings of the 16th European Conference on Solid-State Transducers (Eurosensors XVI 2002), Prague, Czech Republic, Paper T1A4, 2002. 3. J. Marek, MEMS technology from automotive to consumer, in: 20th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2007), Technical Digest, Kobe, Japan, 2007. 4. F. Laermer, A. Schilp, Method of anisotropically etching silicon, US-Pat. d5501893, 1996. 5. K. Funk, H. Emmerich, A. Schilp, M. Offenberg, R. Neul, F. Lärmer, A surface micromachined silicon gyroscope using a thick polysilicon layer, in: 12th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 1999), Orlando, USA, 1999, pp. 57–60.

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6. M. Offenberg, F. Larmer, B. Elsner, H. Muenzel, W. Riethmuller, Novel process for a monolithic integrated accelerometer, in: 8th International Conference on Solid-State Sensors and Actuators and Eurosensors IX (Transducers 1995, Eurosensors IX), vol. 1, Stockholm, 1995, pp. 589–592. 7. A. Thomae, R. Schellin, M. Lang, W. Bauer, J. Mohaupt, G. Bischopink, L. Tanten, H. Baumann, H. Emmerich, S. Pinter, K. Funk, G. Lorenz, R. Neul, J. Marek, A low cost angular rate sensor in Si-surface micromachining technology for automotive applications, in: SAE 1999 World Congress, Detroit, Tech. Paper 199901-0931, 1999. 8. C. Leinenbach, J. Cassemeyer, S. Kronmueller, F. Laermer, H. Seidel, Silicon germanium for new MEMS applications, in: International Conference and Exhibition on Micro-, Electro-Mechanical, Opto and Nano Systems, München, Deutschland, 2005, pp. 215–222. 9. T. Fuchs, C. Leinenbach, S. Kronmueller, F. Laermer, T. Thomas, K. Robb, H. Seidel,

W. Frey, Industrial applications of poly-silicon-germanium as functional MEMS material, in: 206th Meeting of the Electrochemical Society, Honolulu, USA, 2004, pp. 1001–1013. 10. A. Scheurle, T. Fuchs, K. Kehr, C. Leinenbach, S. Kronmueller, A. Arias, J. Cebal-los, M. A. Lagos, J. M. Mora, J. M. Muñoz, A. Ragel, J. Ramos, S. Van Aerde, J. Spengler, A. Mehta, A. Verbist, B. Du Bois, A. Witvrouw, A 10 μm thick poly-SiGe gyroscope processed above 0.35 μm CMOS, in: 20th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2007), Technical Digest, Kobe, Japan, 2007, pp. 39–42. 11. C. Rusu, S. Sedky, B. Parmentier, A. Verbist, O. Richard, B. Brijs, L. Geenen, A. Witvrouw, F. Larmer, F. Fischer, S. Kronmuller, V. Leca, B. Otter, New low-stress PECVD poly-SiGe layers for MEMS, J. Microelectromech. Syst. 12 (2003) 816–825. 12. J. Tsai, A. Tang, T. Noguchi, R. Reif, Effects of Ge on material and electrical properties of polycrystalline Si1xGex for thin-ﬁlm transistors,

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J. Eletrochem. Soc. 142 (1995) 3220–3225. M. Offenberg, B. Elsner, F. Laermer, Vapor HF etching for sacriﬁcial oxide removal in surface-micromachining, in: Electrochemical Society Fall Meeting, vol 94, Miami Beach, USA, 1994, pp. 1056–1057. T. Core, R. Howe, Analog Devices, WO 93/21536. G. Mulhern, D. Soane, R. Howe, Supercritical carbon dioxide drying of microstructures, in: Proceedings of the 7th International Conference on Solid-State Sensors and Acutators (Transducers ’93), IEEE Electron Devices Society, Yokohama, Japan, 1993, pp. 296–298. H. Guckel, J.J. Sniegowski, T.R. Christenson, F. Raissi, The application of ﬁne-grained, tensile polysilicon to mechanically resonant transducers, Sens. Actuators A21 (1990) 346–351. C. Leinenbach, H. Seidel, T. Fuchs, S. Kronmueller, F. Laermer, A novel sacriﬁcial layer technology based on highly selective etching of silicongermanium in ClF3, in: 20th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2007), Technical Digest, Kobe, Japan, 2007, pp. 65–68. M. Offenberg, F. Laermer, B. Elsner, H. Muenzel, W. Riethmueller, Novel process for a monolithic integrated accelerometer, in: Transducers ’95, Stockholm, 1995. M. Offenberg, H. Muenzel, D. Schubert, O. Schatz, F. Laermer, E. Mueller, B. Maihoefer, J. Marek, Acceleration sensor in surfacemicromachining for airbag applications with high signal/noise ratio, SAE 960758, 1996. R.W. Ashurst, C. Carraro, R. Maboudian, W. Frey, Wafer level

anti-stiction coatings for MEMS, Sens. Acutators, A (2003) 104. 21. W.T. Park, R.N. Candler, S. Kronmueller, M. Lutz, A. Partridge, F. Yama, T.W. Kenny, Wafer-scale ﬁlm encapsulation of micromachined accelerometers, in: Twelfth International Conference on Solid State Sensors, Actuators and Microsystems, Transducers ’03, Boston, 2003. 22. P.F. Van Kessel, L.J. Hornbeck, R.E. Meier, M.R. Douglass, A MEMS-based projection display, Proc. IEEE 86 (1998) 1687–1704. 23. G.M. Rebeiz, in: RF MEMS: theory, design, and technology, John Wiley & Sons, NJ, USA, 2003, pp. 157–184. 24. E.W. Becker, W. Ehrfeld, P. Hagmann, A. Maner, D. Münchmeyer, Fabrication of microstructures with high aspect ratios and great structural heights by synchrotron radiation lithography, galvanoforming, and plastic moulding (LIGA process), Microelectron. Eng. 4 (1986) 35–56. 25.D.W. Hoffman, Perspective on stresses in magnetron-sputtered thin ﬁlms, J. Vac. Sci. Technol. A 12 (1994) 953–961. 26. J.W. Dini, in: Electrodeposition: the materials science of coatings and substrates, Noyes Publications, NJ, USA, 1993, pp. 279–303. 27. H. Kattelus, M. Ylönen, M. Blomberg, Amorphous Mo–N and Mo–Si–N ﬁlms in microelectromechanical systems, Fatigue Fract. Eng. Mater. Struct. 28 (2005) 743–749. 28. M.-A. Nicolet, I. Suni, M. Finetti, Amorphous metallic alloys in semiconductor contact metallizations, Solid State Technol. (1983) 129–133. 29. C. Linder, A. Dommann, G. Staufert, M.-A. Nicolet, Ternary Ta–Si–N ﬁlms for sensors and actuators, Sens. Actuators, A 61 (1997) 387–391.

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30. M. Ylönen, T. Vähä-Heikkilä, H. Kattelus, Amorphous metal alloy based MEMS for RF applications, Sens. Actuators, A 132 (2006) 283– 288. 31. J. Tregilgas, How we developed an amorphous hinge material, Adv. Mater. Process. 46 (2005) 49. 32. www.xfab.com. 33. Process speciﬁcation XM-SC surfacemicromachined capacitive MEMS XM20A17—discrete inertial sensor document PS_20_02 Release 1.0, February 2005 X-FAB Semiconductor Foundries AG, www.xfab.com. 34. Design rule speciﬁcation XM-SC surface-micromachined capacitive MEMS XM20A17—discrete inertial sensor document DR_20_02 Release 1.0, February 2005, www.xfab.com. 35. http://www.coventor.com/MEMS. html. 36. JEDEC/FSA joint publication: foundry process qualiﬁcation guidelines (Wafer Fabrication Manufacturing Sites) JP001.01 (Minor Revision to JP001, September 2002) May 2004 JEDEC Solid State Technology Association Fabless Semiconductor Association, http://www.jedec.org/download/ search/JP001-01.pdf. 37. B. Aspar, C. Lagahe-Blanchard, N. Sousbie, J. Margail, H. Moriceau, New generation of structures obtained by direct wafer bonding of processed wafers, ECS Transactions vol. 3, No. 6 Semiconductor Wafer Bonding 9: Science, Technology and Applications, 2006, ISBN 1566677506-X. 38. M. Trächtler, T. Link, J. Auber, P. Nommensen, Y. Manoli (HSG-IMIT, Villingen-Schwenningen,GERMANY), Single-chip, three-axis gyroscope using SOI-technology, Symposium Gyro Technology Karlsruhe, September, 18/19, 2007.

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Chapter Twenty Nine

Silicon Based BioMEMS: Micromachining Technologies Abhinav Bhushan and Cristina E. Davis Department of Mechanical and Aerospace Engineering One Shields Avenue, University of California, Davis, CA, USA

29.1 Introduction to Silicon Based BioMEMS Devices BioMEMS, or Bio-Micro-Electro-Mechanical Systems, integrates microsystems technology with applications in biology and the life sciences. As a truly interdisciplinary ﬁeld, bioMEMS brings together various engineering disciplines, chemistry, medicine and biology [1, 2]. One of the common themes among these biological applications is that they deal with liquids [3]. Combined with microﬂuidics, bioMEMS devices provide a necessary platform for high-throughput analysis of complex biological systems. These studies can lead to a better understanding of the molecular basis of diseases, which could enable earlier disease detection. Two important design qualities that are frequently identiﬁed for bioMEMS technologies are: devices that allow for lower healthcare costs and devices that provide faster analysis of clinical samples [4, 5]. These goals are partially achieved by miniaturizing the instruments, which in turn can potentially lower capital and operating costs for industry. Disposable and miniature clinical diagnostic systems are mechanisms to increase patient throughput in pointof-care clinical settings. Driven by the advances in injection molding technology, this new category of MEMS technologies has the potential to produce disposable analytical parts to detect biomarkers of speciﬁc diseases. These disposable parts can be made of polymers,

such as polycarbonate and poly(methyl methacrylate) (PMMA), which are easy to mold and have a fast production cycle time [6, 7]. While disposable parts are useful for in vitro and lab-based diagnostics, there is also recent interest in developing in vivo MEMS-based medical devices and implantable sensors [8–10]. Since some molded polymers used in MEMS devices are not always biocompatible, silicon can be the material of choice for implanted sensors or drug delivery systems. Using silicon also imparts great ﬂexibility in manufacturing the devices because silicon micromachining processes are very well characterized on the industrial scale. Silicon electrochemical, resistive, capacitive, optical, and ﬂuorescence sensors can potentially be integrated more easily with other silicon components of bioMEMS devices. BioMEMS devices have the potential to be scaled up for mass production and are expected to have a tremendously positive impact on the medical device industry and in coming decades. The most common applications of silicon-based bioMEMS devices are deoxyribonucleic acid (DNA) sequencing chips [11, 12], DNA synthesis chips [13, 14], polymerase chain reaction (PCR) chips [11, 12], protein separation and analysis tools [15, 16], microassay applications [17–21], and electrochemical biosensors [21–24]. Although many bioMEMS applications are quite worthy of extensive commentary in this chapter, we have selected four case studies to highlight developments in a few application areas, and they illustrate the use of silicon bioMEMS devices for biomedical applications. 489

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29.2 Silicon BioMEMS for Health Care 29.2.1 Case Study: Microneedles for Drug Delivery There are many methods to administer medicine to patients, including oral ingestion, topical skin administration, and injection via syringe. All of these methods have advantages and drawbacks. In addition to being painful and causing patient discomfort, syringe injection can potentially release high concentrations of the drug to the entire body. This can cause unintended systemic effects that are correlated with drug side effects. In a newer method to deliver medication into the bloodstream or into certain tissues preferentially, a transdermal patch can also be placed on the skin [25–29]. This has the added advantage of releasing drugs into the body more slowly over longer time durations. The patch surface in contact with the skin is coated with the drug or vaccine and relies on diffusion of the drug across the epidermis skin barrier. In many cases, the epidermis restricts the transport of medicine and is prone to peel off under sweat or water. The most popular transdermal patches are the nicotine patch, which releases nicotine into the body to limit addiction to tobacco smoking, and the hormone replacement therapy patch. A new class of transdermal devices is a microstructured array of hollow microneedles [30–50]. When applied to the skin, these microneedles pierce the topmost layer of the skin, opening micropores. As shown in Figure 29.1, a needle only penetrates about 100 μm into the outer surface of the skin, also called the stratum corneum [30]. The needle does not enter the blood capillaries, which restricts bleeding, and the device is not painful since the needles are not long enough to pierce the buried nerve layers in the skin. This method can deliver drug molecules inside the epidermis to local tissue, and then the drug can diffuse over time into the bloodstream. Since the skin slows down the transport of the drug from the transdermal patch to the blood stream, the transdermal microneedles are more efﬁcient

and faster in administering the drug. Often the needles are coated with drug molecules or contain liquid drugs that can be injected directly into the body through the needles. The arrangement of the needles in an array allows the patch to cover a large area for delivering the drug and increases the redundancy of the drug system due to a failure of the individual needles. A process to fabricate an array of out-of-plane, single-crystal silicon microneedles is brieﬂy described by Stoeber and Liepmann [30] and is illustrated in Figure 29.2. These 40 μm diameter, 200 μm long, tapered conical polymer microneedles, arranged in a pitch of 750 μm are fabricated using an integrated lens technique for transdermal drug delivery. On an oxidized doublepolished silicon wafer, 40 μm wide lumens are lithographically patterned by dry etching the oxide. Using this as an etch mask, the silicon wafer is etched with the Bosch process. After protecting the etched surface and the front of the wafer with silicon nitride, the front side of the wafer is patterned to create a mask to facilitate isotropic etching of silicon to result in the desired needle shape. The dry etch using SF6 plasma results in a rough surface. An isotropic wet etch using HNO3:H2O:HN4F smooths the surface of the silicon. Because of the poor selectivity between the silicon oxide and bare silicon under wet etching, the silicon nitride protective layer serves as the etch mask. Finally, the remaining silicon dioxide and silicon nitride are removed in concentrated hydroﬂuoric acid. Figure 29.3a shows the microneedles in comparison with a 25G5/8 hyperdermic steel needle, which has an outer diameter of 530 μm. Figure 29.3b shows an array of eight microneedles attached to a typical plastic syringe. Using these hollow microneedles, methyl nicotinate was successfully administered into

1. SiO2 deposition

5. Pattern frontside

2. Pattern backside

6. Isotropic silicon etch

3. DRIE

7. Stripping SiO2 and N4Si3

Injection Stratum corneum ~ 20 μm

Needle Epidermis ~ 0.1mm

Capillary

4. N4Si3 deposition

Single crystal silicon Silicon dioxide

Nerve

Dermis ~ 0.6 – 3 mm Subcutaneous fat

Silicon nitride Photoresist

Fig 29.1 ● Typical cross-section of human skin.

Fig 29.2 ● Process steps to fabricate silicon microneedles.

Source: Reprinted with permission from [30]. © 2005 IEEE.

Source: Reprinted with permission from [30]. © 2005 IEEE.

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the volar forearms of human patients [46]. The patients also reported no sensation of pain during injection.

29.2.2 Case Study: Neural Implants and BioMEMS Prosthetics There is considerable interest in developing technologies that can establish a stable neural–computer interface in prosthetic systems [51–58]. This could potentially be useful for restoring sensory and motor functions to patients suffering from the breakdown of normal signaling pathways. The current brain–computer interface (BCI) approaches, including those using surface electroencephalogram, lack functional stability due to cell and tissue reactive responses that occur around implanted devices. The body’s response results in the formation of a dense cellular sheath around the implanted electrode

CHAPTER 29

arrays, which increases the device impedance and leads to a loss of device functionality. Retterer et al., have developed three-dimensional probe structures with microﬂuidic channels for local drug delivery and diffusion-mediated delivery of therapeutic agents into the tissue exhibiting reactive responses to implanted devices [51]. The probes were fabricated by a complementary metal–oxide–semiconductor (CMOS) compatible process, combining deep reaction ion etching (DRIE) with surface micromachining (see Figure 29.4). In the ﬁrst step, two layers of silicon dioxide are deposited and patterned by plasma enhanced chemical vapor deposition (PECVD) and reactive ion etching (RIE) to form the width of the ﬂuidic channels. Low stress silicon nitride (200 MPa) deposition via low-pressure chemical vapor deposition (LPCVD) is carried out to form the structural wall of the channel. Following this, via holes are etched using RIE. The sacriﬁcial oxide is then etched completely in hydroﬂuoric acid. The vias are sealed by depositing silicon dioxide using PECVD. A 500 μm cube, fabricated by double-sided DRIE, is provided on the back of the wafer to handle the device. For this, the wafer is covered with photoresist. The exposed silicon is etched

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h) Silicon

Silicon nitride

Fig 29.3 (a) 25G5/8 needle shown next to an array of single crystal silicon out-of-plane needles and (b) an array of eight 200 μm microneedles is mounted on a piece of silicon which is attached to the tip of a plastic syringe.

Fig 29.4 ● Process to fabricate the neural prosthetic probe with integrated microﬂuidics.

Source: Reprinted with permission from [30]. © 2005 IEEE.

Source: Taken with permission from [51]. © 2004 IEEE.

●

Silicon dioxide

Photo resist

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Fig 29.5 ● SEM image of model silicon prostheses with integrated microchannels. Source: Taken with permission from [51]. © 2004 IEEE.

using a Bosch DRIE process. Since this process does not rely on an etch stop, silicononinsulator (SOI) wafers can be used to produce devices with a deﬁned size. A PECVD silicon dioxide ﬁlm is deposited over the backside of the wafer to protect it from damage during further processing. The silicon dioxide and silicon nitride ﬁlms on the front of the wafer are now patterned by RIE to deﬁne the proﬁle of the device. The exposed silicon is etched by DRIE and the silicon dioxide is etched using RIE to open the ﬂuid inlet and outlet ports, completing the formation of the microﬂuidic channels. A scanning electron microscope (SEM) image of the ﬁnal device is shown in Figure 29.5. In one of the experiments, the devices were ﬁxed to polyvinyl (PVC) Tygon tubing, inserted into anesthetized adult Sprague–Dawley rats, and left there for 30 minutes, 1 hour, and 5 hours. At speciﬁed times, the brain tissue was sliced, mounted, and imaged using a scanning confocal system mounted on an inverted microscope (see Figure 29.6). After insertion, TR-transferrin diffused into nearby neural tissue and ﬂuorescence signals were recorded as both diffused and localized signaling. Fluorescence signals were observed as far as 400 μm from the insertion site, suggesting that drug delivery by diffusion, without the need for pumps and valves, is a viable alternative.

29.3 Silicon BioMEMS for Biological Detection 29.3.1 Case Study: Bacteria Detection Using Microarrays Many types of biosensors have been proposed for detection of biological molecules [59–62]. As an alternative 492

Fig 29.6 ● (a) Consecutive 100 μm thick coronal slices were cut parallel to the device shaft. (b) The position of an inserted device is shown here. Source: Taken with permission from [51]. © 2004 IEEE.

to commercial high density microarrays, which are complex to use and can cause quenching of the used ﬂuorophors through contaminants, interdigitated (IDA) gold nano-electrodes, with thiol-modiﬁed oligonucleotides immobilized on the IDA, were used to identify and quantify pathogens [60]. The ﬂuidic chips, each 9 mm by 10 mm and carrying 16 electrode positions of 500 μm diameter each, were fabricated on standard 6 in. silicon wafers. The IDA gold array electrodes consist of two interlocking comb-like structures with 204 ﬁngers, each 800 nm wide, and with a 400 nm gap between anode and cathode ﬁngers (see Figure 29.7a). Silicon dioxide was grown thermally on the wafers. The gold electrode structures were patterned by photolithography on the oxide layer. A thin layer of tantalum was deposited for adhesion before a ﬁnal 120 nm gold layer. The patterning was competed by a lift-off process. A 5 μm thick photoresist layer was used for passivating the device—only the electrode area and the contact pads were left exposed. The biochips were positioned in a polycarbonate cartridge called eBioChipstick and connected to the fully automated Array Analyzer “eMicroLISA” (see Figure 29.7b). Five different capture probes were spotted on the electrodes using a piezoelectric nanoplotter to target ﬁve bacteria that are simulants of pathogens: Escherichia coli, Pseudomonas aeruginosa, Enterococcus faecalis, Staphylococcus aureus, and Staphylococcus epidermidis. An ampliﬁed signal was obtained by the large number of oxidation and reduction steps of the enzyme label and the enhanced lateral

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Fig 29.7 ● (a) Design of the electrical biochip microarray. (b) Fully automated “eMicroLISA” with the different components. Source: Taken with permission from [60].

Fig 29.8 ● (a) Schematic of the spotted pattern of the microarray. PC positive control. (b) Schematic showing the electrochemical reactions. Source: Taken with permission from [60].

diffusion of the electroactive molecules to the electrode surface (see Figure 29.8). The study to detect speciﬁc bacteria was performed in three phases—Phase I, during which the solution was introduced into the ﬂow cell at a constant ﬂow rate; Phase II, during which the system reached an equilibrium; and Phase III, when the ﬂow was stopped. The position speciﬁc detection and identiﬁcation of ribonucleic acid (RNA) was accomplished for all of the ﬁve bacteria. The electrical array read-outs after normalization for each of the targets made it possible to identify the bacteria. Through this technique, it was also possible to detect two different bacterial RNA with different concentrations on a single array (see Figure 29.9).

29.3.2 Case Study: MEMS Mass Detection The ability to detect small amounts of materials, including biological entities such as pathogenic bacteria, is important for medical diagnostics, detection of infectious agents, mass based ﬂow cytometry, and sizing of colloidal particles. Engineered micro- and nano-mechanical systems serve as multifunctional, highly sensitive, immunospeciﬁc biological

detectors. Mass sensing techniques, including quartz crystal microbalance and microcantilevers have been used to distinguish between different biological samples. Another technique, surface plasmon resonance, where the optical signal is related to the mass, is also widely used. These methods, with a sensitivity ranging from 1 ng to 1 pg, require the biological entity to be anchored to a surface. Burg et al. demonstrate a cantilever device with microﬂuidic channels that can resolve mass differences with a precision of 300 ag [63, 64]. This device allows measuring the properties of micro and nanoscopic particles in the liquid phase. The cantilever devices were fabricated using silicon micromachining on SOI wafers with an integrated electrostatic drive electrode under the cantilever (see Figure 29.10). The devices were vacuum sealed at submillimeter pressure. Bypass channels for ﬂuid delivery were etched into the Pyrex wafers, drilled ultrasonically, and bonded to the silicon wafer by anodic bonding. An SEM image of the device is shown in Figure 29.11a. The sensors were attached to a printed circuit board and wirebonded directly to the board. The ﬂuidic interconnects to the chip were made by a Teﬂon manifold and perﬂuoroelastomer o-rings, leading to a seal reliable for pressures up to 150 psi (see Figure 29.11b). One 493

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Fig 29.9 ● Current and column plots of the 18 electrodes. (a) The different phases of the current responses for a positive signal of Escherichia coli, Pseudomonas aeruginosa total RNA, the positive control, and a negative control are compared. (b) Plot of the absolute signals. (c) Plot of the normalized signals. Source: Taken with permission from [60].

Fig 29.10 ● Fabrication and packaging process to fabricate the suspended cantilevers with integrated microchannels. Source: Taken with permission from [63]. © 2006 IEEE.

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Fig 29.11 ● (a) SEM image of the cantilever and the glass frit. (b) Packaging of the sensor chip. Source: Taken with permission from [63]. © 2006 IEEE.

of the applications of the sensor is to detect protein binding. For this, the channel was coated with Avidin. The corresponding change in the sensor resonant frequency change was equivalent to 300 ng/cm2 of the adsorbed protein. On injecting biotinconjugated bovine serum albumin (bBSA), an increase in signal was recorded due to the BSA attached to the surface. These microchannel resonators can thus be used for label-free detection of biological molecules in liquid (see Figure 29.12).

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Fig 29.12 ● (a) Fluid ﬂows continuously through a microchannel etched out on a suspended cantilever. Sub-femtogram mass resolution is obtained by shrinking the dimensions to micrometer scale and packaging the cantilever under vacuum. (b) Species that bind to the channel wall greatly exceed the number of free molecules in the ﬂuid, which enables speciﬁc detection by immobilized receptors. (c) The resonance frequency of the cantilever is monitored continuously by the optical lever method where the displacement of the cantilever is detected by measuring the deﬂection of a laser beam focused on to the tip of the cantilever. Source: Taken with permission from [63, 64]. Reprinted by permission from Macmillan Publishers Ltd: [Nature], [63, 64], © 2007. © 2006 IEEE.

29.4 Conclusions and Future Research Areas Overall, there are four key issues that dominate the development of silicon BioMEMS devices—delivery, performance, complexity of fabrication, and costs. It 495

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is important for new technology to offer advantages in all of these areas to successfully replace conventional devices. Devices on the microscale are, in general, more efﬁcient than corresponding bench-top instruments. Although MEMS devices are fabricated using techniques similar to those used to create integrated circuits, they often involve a physical or analytical function to be performed. These devices routinely have feature sizes ranging from a few millimeters to submicrometers. Typical MEMS devices are designed for in vitro diagnosis, though interest for in vivo applications is growing. Maintaining biocompatibility of devices for in vivo studies is critical. The case studies presented here

have innovatively interfaced the BioMEMS devices with the macroscopic world, enabling an effective delivery of drugs into the body or measurement of an important biological property. More research and development is needed to ﬁnd robust manufacturing processes that will lead to large-scale fabrication and a lower cost/device. The ability to control physical characteristics up to the nanometer scale is appealing for BioMEMS applications. In addition, the application of MEMS technology in novel areas such as in vivo imaging, stents, single-cell detection for disease diagnostics, and tissue engineering may lead to increased understanding of the human body to improve health and lives.

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30

Chapter Thirty

Introduction to Encapsulation of MEMS Heikki Kuisma VTI Technologies Oy, Vantaa, Finland

30.1 Early Work on Bulk-MEMS Devices When early micromachined devices (later called bulkMEMS devices) were created from a silicon wafer by etching, it was soon found that a single silicon wafer was not sufﬁcient for creating practical functional devices. Even for a simple pressure sensor, it was necessary to join two wafers together. Many early pressure sensors consisted of a silicon wafer anodically bonded to a glass wafer [1, 2]. Besides pressure sensors other early devices were made out of several wafers for a number of reasons. An early accelerometer [3] consisted of three wafers, one silicon wafer and two glass ones, to achieve mechanical rigidity and to provide protection from environmental inﬂuences. Another example, a gas chromatograph on silicon wafer [4], made use of a bonded glass wafer for sealing the spiral groove on the silicon wafer, thus forming a spiral column. In addition to bonding silicon and glass together by anodic bonding, metal alloys were also used for siliconto-silicon bonding [5]. Later silicon direct bonding and bonding by low temperature melting glass [6, 7] were used for pressure sensors and other devices. While encapsulating provided the required protection and vacuum space it also prevented direct electrical contacting of the devices. Electrical vias were needed through the hermetic encapsulation. Most of the early electrical vias were horizontal, in the plane of the wafer [1, 3, 8, 9]. The horizontal vias utilized different electrical isolation methods that would pose minimal load to the device in the form of spurious capacitance or resistance. Common to horizontal vias was that the surface

of the lower wafer needed to be accessed. A part of the upper wafer was thus cut or etched away and a nonplanar surface resulted. This basic via formation is still in use for the majority of the MEMS inertial sensors. Vertical vias were also introduced quite early. The Ford SCAP sensor [10] was a very modern looking device with through-the-(glass) wafer vias and solder bump contacts. Among the ﬁrst ideas for an isolated via through a silicon wafer was a pressure sensor with glass ﬁlled trenches [11].

30.2 Encapsulation in Surface Micromachining The early examples of encapsulated MEMS did not consider the encapsulation as the “zero level” packaging as it has been later called but as an essential part of the threedimensional device itself. When surface micromachining was introduced the three-dimensionality was scaled down in vertical dimension. It was created by ﬁlm deposition and sacriﬁcial etching instead of wafer bonding. All the electrical functions were included in the stack of ﬁlms. The ﬁrst commercial surface micromachined devices did not utilize wafer-level encapsulation, but relied on a ﬁrst-level hermetic packaging [12]. It was much more costly than non-hermetic plastic packaging. The MEMS structures were very sensitive to environmental inﬂuences, and special methods had to be created for processes—for example, dicing the MEMS wafers without damaging the delicate structures [13]. Soon capping with a second wafer was adopted for surface micromachined devices also and is used today at all major suppliers of inertial sensors. 501

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30.3 Protection of the MEMS Device The ﬁrst and most important aim of the encapsulation is to protect the sensitive MEMS structures mechanically, chemically and electrically. Mechanical protection is needed to prevent mechanical touching and penetration of ﬂuids both during manufacturing and use. First-level packaging may take care of these issues. But one of the main tasks remains: to protect the MEMS device during packaging operations like dicing, pick and place and plastic over-moulding. Wafer-level encapsulation will solve these issues. First-level packaging is often semi-permeable to contaminating chemicals like water. One of the requirements of the encapsulation is to improve moisture resistance of the MEMS device. Other chemicals may also be important case by case. Finally, the encapsulation can provide additional EMI protection. This protection is needed from high electric ﬁelds at radio frequencies. Also the MEMS device may be sensitive to stray coupling of signals from the device or to the device. A grounded encapsulating wafer prevents this unwanted coupling.

30.4 Controlled Atmosphere Depending on the bonding process the pressure after sealing is between a few tens and a few thousands of Pascals. Anodic bonding is among the best in this respect and low temperature melting glass frit among the worst. If a lower than one hundred Pascal pressure is required some kind of getter has to be used. It can be a specially engineered and fabricated getter material or just a side function of some materials that are used in MEMS. For example, silicon acts as an oxygen getter in silicon direct bonding. The requirement for the early pressure sensors was to create a hermetic vacuum space, which would act as a reference pressure chamber of an absolute pressure sensor. Later this construction has been dominant in the industry even for relative or differential pressure sensors, which need a pressure inlet to one or both sides of the thinned diaphragm. In this case a pressure inlet hole is drilled or etched to a second wafer, which is bonded to the ﬁrst one that carries the diaphragm. The second wafer is also often made very thick to reduce packaging induced stress at the diaphragm. In some cases electrical functions like stationary electrodes of a capacitive sensor are also added to the second wafer. In principle, achieving a good vacuum is the aim, but the actual reference pressure is not very important as long as there is no outgassing or adsorption during use and the thermal expansion of the gas has a minor effect on the thermal error. 502

MEMS gyros and resonators beneﬁt from a very low gas damping. Depending on the dimensions the required pressure is typically well below one hundred Pascals. This is difﬁcult to achieve without gas absorption either by a real getter or by a structural material with some gettering properties. Accelerometers require a well controlled but quite high pressure to achieve the required damping characteristics. In many cases sealing at the atmospheric pressure is a good compromise. In some critical applications one may be forced to use higher sealing pressure than the atmospheric pressure.

30.5 Structural Functions Besides protection and controlled atmosphere, the early work on MEMS utilized wafer bonding for achieving other structural functions. Wafer bonding is used for creating capacitor structures for capacitive sensors. Especially anodic bonding is extremely good in retaining the required control of the distance between the electrodes. Many capacitive pressure sensors and some accelerometers and angular rate sensors still rely on this special feature enabled by wafer bonding. Another structural function that is utilized is to add thickness for isolating the mechanical mounting stress. This is particularly important for piezo-resistive pressure sensors, which are very stress sensitive. A thick enough base wafer will mechanically isolate the MEMS wafer, which must be kept quite thin for the sake of economy of the etching process. Today some of these structural functions and many new ones may be obtained by using bonded silicon-oninsulator (SOI)-wafers that have become quite important for MEMS.

30.6 Wafer Bonding Methods The majority of the MEMS sensors today use glass frit bonding for attaching a capping wafer on a MEMS structural wafer. A mixture of glass powder and some binding chemicals is applied on the surface of the capping wafer by stencil printing. The capping wafer is bonded to the MEMS wafer under controlled gas pressure and controlled force. The glass frit bonding is simple but leak control has proved to be quite difﬁcult, dimensional tolerances are poor and residual gas pressure is high. Anodic bonding is used for many pressure sensors and some accelerometers and angular rate sensors. In this method the polished surfaces of silicon (or poly-silicon) and alkaline borosilicate glass are brought to initial contact at elevated temperature by mechanical force and

Introduction to Encapsulation of MEMS

to more intimate contact by electrostatic force due to applied voltage. The voltage will also cause an electrochemical reaction between the glass and silicon creating a permanent covalent bond. Anodic bonding produces extraordinary dimensional accuracy and one to two orders of magnitude lower residual pressure compared to glass frit bonding. The leak tightness is also guaranteed better than with other bonding methods due to the progressively growing electrostatic force when the surfaces get closer. The drawback of this method is the limitations in device design due to the high electrostatic forces during bonding Silicon direct bonding is mainly used for manufacturing SOI-wafers, including SOI with cavities. The requirement for surface smoothness is an order of magnitude more stringent than with anodic bonding. The initial contact is achieved with a mechanical force. The initial wafer bonding is achieved by chemical forces related to hydrogen bonds. Finally, these bonds are converted to covalent bonds by thermal treatment. The high temperature treatment and the requirement for extreme surface quality limit the applicability of this bonding. Metal alloy bonding is sometimes used for wafer-towafer bonding. The possible alloys include AuSi, AuSn and AlGe [14]. The wafers are brought into contact by mechanical force at elevated temperature. Melting of the alloy will join the wafers. In spite of long history there are only a few cases of industrialization of this wafer-bonding method. Thermo-compression of structured gold layers is reportedly used today for wafer bonding in mass production of MEMS devices [15].

30.7 Sealing by Film Deposition Sacriﬁcially etching a layer between or underneath the structural layers is the standard procedure for releasing moveable structures in MEMS. This concept has been extended to protecting and sealing layers. The uppermost capping layer has small openings that allow the etchant to penetrate in and the etching products to be transferred out. These openings are then sealed by additional ﬁlm deposition that will close them before material starts to grow inside the capped space. The Epi-Seal process developed by Bosch [16] is an example of commercially successful applications of this capping technique. The drawback is the limited span that can be capped with the relatively thin ﬁlm without introducing supporting posts within the MEMS structures.

CHAPTER 30

Fig 30.1 ● Horizontal vias are optimal for packaging of two dies in a package with interconnection by wire bonding. Vertical vias enable the use of WLP methods and die stacking as in VTI’s Chip-on-MEMS concept [17].

30.8 Via Technologies Electrical vias are needed for electrical access to the MEMS structures. The most common way to make vias today was discussed earlier: the horizontal vias. The details of isolation differ from case to case. Generic to horizontal vias is the stepped surface of the device with electrical contact pads at the lower level than the upper cap surface. In wire bonded devices this stepped feature may be used for advantage to protect bonding wires. Via isolation may be dielectric or may be based on pnjunction isolation. Direct horizontal thin ﬁlm metal vias across an anodic bonding interface have also been used. Vertical vias through either the encapsulating wafer or the wafer carrying the MEMS structures would be beneﬁcial to the MEMS industry. They would improve the area usage. Also they would enable other wafer-level packaging (WLP) features to be applied to the MEMS wafer like bumped IO contacts and stacking of devices. Vertical vias were used already in the early 1980s but the breakthrough of a generally accepted via technology has been delayed. Some companies are successful with a proprietary vertical via technology, such as VTI Technologies who employ the technology ﬁrst introduced in [11]. It is however expected that the development of through silicon vias for integrated circuit wafers will ﬁnally result in generic vertical vias for MEMS also. Figure 30.1 shows the state-of-the-art encapsulation of MEMS having horizontal vias which consume some area but make the device very suitable for wire bonding. As a reference it also shows a device that is utilizing vertical vias that enable the combination of the IC and MEMS device on wafer scale for creation of a true chip scale package with low cost.

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References 1. T.A. Nunn, A silicon absolute pressure transducer for biomedical applications, in: Stanford University Technical Report No. 4610-1, October 1977. 2. C.S. Sander, J.W. Knutti, J.D. Meindl, A monolithic capacitive pressure sensor with pulse-period output, IEEE Trans. Electron Device ED-27 (1980) 927. 3. L.M. Roylance, J.B. Angell, A batchfabricated silicon accelerometer, IEEE Trans. Electron Device ED-26 (1979) 1911. 4. S.C. Terry, J.H. Jerman, J.B. Angell, A gas chromatograph air analyzer fabricated on a silicon wafer, IEEE Trans. Electron Device ED-26 (1979) 1880. 5. W.H. Ko, J. Hynecek, S.F. Boettcher, Development of a miniature pressure transducer for biomedical applications, IEEE Trans. Electron Device ED-26 (1979) 1896. 6. K. Petersen, P. Barth, J. Poydock, J. Brown, J. Mallon Jr., J. Bryzek, Silicon fusion bonding for pressure sensors,

504

7.

8.

9.

10.

11.

12.

in: Technical Digest IEEE Solid State Sensor and Actuator Workshop, June 1988. K.E. Petersen, Silicon as mechanical material, Proc. IEEE. 70 (5) (May 1982) 420–457. A. Lehto, Capacitive pressure detector structure and method for manufacturing same, US Patent 4,597,027, June 1986. H. Kuisma, Absolute pressure transducer, US Patent 4,609,966, September 1986. G.M. Giachino, R.J. Haeberle, J.W. Crow, Method for manufacturing variable capacitance pressure transducers, US Patent 4,386,453, June 1983. H. Kuisma, Pressure sensor construction and method for its fabrication, US Patent 4 875 134, October 1989. Analog Devices ADXL50 Product Data Sheet, 1993.

13. T.R. Spooner [US], K.P. Harney, Method and device for protecting micro electromechanical systems structures during dicing of a wafer, US Patent 6 555 417, April 2003. 14. S. Nasiri, A.F. Flannery Jr., Method of fabrication of a Al/Ge bonding in a wafer packaging environment and a product produced therefrom, US Patent 7 442 570, October 2008. 15. F.S. Geefay, Method for sealing a semiconductor device and apparatus embodying the method, US Patent 6,836,013, 2004. 16. R.N. Candler, et al., Long-term and accelerated life testing of a novel single-wafer vacuum encapsulation for MEMS resonators, J. MEMS. 15 (2006) 1446–1456. 17. H. Kuisma, Wafer Level Packaging of MEMS, Smart Systems Integration Conference, Barcelona, April 2008.

31

Chapter Thirty One

Silicon Direct Bonding Kimmo Henttinen1 and Tommi Suni2 1

Okmetic Oyj, Vantaa, Finland VTT, MEMS and Heterogeneous Integration, Espoo, Finland

2

Direct bonding generally means joining of two pieces together without an intermediate layer or external force. If the surfaces are ﬂat, clean and smooth, they can stick together when brought into contact and form a weak bonding based on physical forces at room temperature. The physical forces can be van der Waals type of forces, hydrogen bonding, capillary forces or electrostatic forces [1]. Without subsequent annealing the bonding between the wafers is reversible. After wafer contacting the physical forces can be converted to chemical bonds by annealing. This may increase the adhesion between the surfaces up to the cohesive strength of the material in concern. The type of the bonding is determined by the chemical species on the surfaces. In the case of silicon the direct bonding falls into two main categories depending on the surface chemistry: Hydrophilic bonding, in which the surface has silicon oxide with silanol groups (Si–OH) on the top and hydrophobic bonding, in which the surface is basically bare silicon.

31.1 Hydrophilic High-Temperature Wafer Bonding Hydrophilic bonding is used commercially for example to produce SOI-wafers and microelectromechanical structures. In a typical case one of the silicon wafers has been thermally oxidized while the other has a thin native or chemical oxide on top. TEM image of the bonded interface between thermal oxide and hydrophilic silicon surface is presented in Figure 31.1.

Thermal oxide

Silicon

100 nm

Fig 31.1 ● Cross-sectional TEM image of bonded interface between thermal oxide and silicon.

Also, it is possible to use chemical vapor deposited (CVD) oxides or sputtered oxides, if the requirements for cleanliness, smoothness and ﬂatness are met. One of the problems associated with wafer bonding is unbonded areas called interface bubbles or voids. Voids can form during the room-temperature contacting of the wafers or they can also be induced during the subsequent annealing steps. During wafer contacting each wafer has to deform elastically in order to achieve the conformity of the two surfaces. In practice, the ﬂatness variation of 1–5 μm over 150 mm silicon wafers poses no problems for wafer contacting, because wafers can accommodate this scale of surface waviness. Bow and warp of 150 mm wafers up to several tens of μm or even 100 μm are also

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Fig 31.2 ● Scanning acoustic microscopy image of a wafer pair bonded without sufﬁcient cleaning. The voids (represented in the image as white areas) are induced by particles and/or other contamination on the wafer surfaces.

tolerable. However, particles that are trapped between the wafers cause unbonded areas. During room-temperature bonding the wafers have to deform around the particles, leaving typically circular unbonded areas (Figure 31.2). Particle induced voids can be relatively large, for example, a 1 μm particle may cause a void with a diameter of few millimeters. The size of the void due to a certain particle is a strong function of the wafer thickness. Thin wafers can more easily deform around particles and other surface non-idealities. Cleanliness is very important in wafer bonding because surface contamination has direct inﬂuence on both the structural and electrical properties of the bonded interface. For example, boron contamination in a form of B2O3 from clean room air may chemically adsorb on the wafer surfaces leading to boron rich layers near the bonded interface. Boron contamination can be minimized with proper clean room construction and ﬂushing the wafer surfaces with DIwater just prior to wafer contacting. Microroughness of the wafer surface is a local parameter that is also very crucial in wafer bonding, because the physical forces that keep the wafers together at room temperature are short range forces. Microroughness is normally measured with atomic force microscopy (AFM) or scanning tunneling microscopy (STM) and quantiﬁed with parameters like root mean square (RMS) or average roughness (Ra). Practice has shown that surface roughness less than 3–5 Å is adequate for direct bonding of hydrophilic silicon wafer surfaces. 506

In theory, two wafers of almost any material can be bonded together if their surfaces are sufﬁciently ﬂat and clean so that the surface molecules can get close together and interact with physical van der Waals type of forces. However, it is not always possible to obtain “optically smooth” materials with polishing. Therefore, it is important to activate the bonding surfaces in order to alleviate the surface smoothness requirements. One possible way to activate the bonding surfaces is wet chemical cleaning. Standard wet chemistries used in semiconductor industry are fully applicable to wafer bonding. The basic cleaning steps based on hydrogen peroxide (RCA 1 and RCA 2 cleans) yield hydrophilic surfaces and they also remove particles and metallic contamination from silicon and silicon oxide surfaces. The hydrophilic silicon wafer surface contains Si–O–Si and Si–OH bonds. The surface hydroxyl groups (–OH) are polarized and therefore very reactive to water. As two hydrophilic silicon surfaces are contacted in the initial state, the two surfaces form the bond via water molecules (Figure 31.3a). During annealing these water molecules diffuse out from the interface, dissolve into the surrounding material or react with surfaces forming more silanol groups (Si–OH). Once these water molecules are removed, a bond is formed between silanol groups (Figure 31.3b). During further annealing, opposing silanol groups react according to reaction 31.1: SiOH + SiOH = SiOSi + H2O

(31.1)

During this reaction more water molecules are released and Si–O–Si bonding is formed (Figure 31.3c) (Figure 31.4). The water molecules from the bonded interface diffuse into the silicon dioxide on the surfaces. If the water reaches the silicon, it reacts with it to form silicon dioxide and hydrogen according to reaction. Si + 2H2O = SiO2 + 2H2

(31.2)

The remaining hydrogen does not react with silicon and may cause problems in the form of trapped gas, which is detectable with an IR camera or scanning acoustic microscopy as voids (Figure 31.5). However, hydrogen has a high solubility into SiO2 and by having an oxide layer of thickness 50 nm on at least one wafer surface, hydrogen-induced voids can be avoided. The required amount of oxide on the surfaces for completely dissolving the hydrogen depends on the amount of water present at the interface. The water content can be tuned by changing the hydrophilicity of the surfaces and by using different bonding atmospheres, for example, vacuum bonding.

Silicon Direct Bonding (a)

CHAPTER 31

(b) o o o

o o o

Si o H H o H H H o o H H H o

Si o Bonding interface

Si o o

Si o o

Bonding interface

H H o

o

(c) o o o o

o o o Si o H o H

Si o H o H Si o o o

Si o o

o

Fig 31.3 ● The reactions at the bonded interface between two hydrophilic silicon surfaces are (a) bonding via intermediate water molecules, (b) bonding between two OH groups by van der Waals forces, and (c) formation of Si–O–Si bonds [1]. The evolution of the bond strength as a function of the bond annealing temperature is depicted in Figure 31.4.

Surface energy (mJ/m2)

High temperature bonding 3000 2500 2000 1500 1000 500 0 0

200

400

600

800

1000

Annealing temperature (°C)

Fig 31.4 ● Evolution of the bond strength as a function of annealing temperature for high-temperature bonding. The wafers were cleaned with SC1-clean prior to wafer contacting. Bond annealing time was 2 hours.

31.2 Hydrophobic HighTemperature Bonding of Silicon In hydrophobic Si bonding, silicon is directly joined to another silicon wafer without an intermediate oxide layer, that is, not even native oxide. It has been suggested that this bonding method could replace epitaxial growth in some applications. For example, bonding of two lightly doped silicon wafers can produce abrupt and lightly doped p-n junctions that are not possible to obtain by other techniques. Hydrophobic bonding may also be used to fabricate compliant substrates for high quality heteroepitaxial growth by twist bonding. In this

Fig 31.5 ● Scanning acoustic microscopy image of a wafer pair with hydrogen induced voids at the bonded interface. Both wafer surfaces had only 2 nm thick native oxide, which cannot accommodate all of the hydrogen formed during the process.

method a thin layer of material is transferred to a host material of the same material, by introducing a large twist angle between them [2]. As the native oxide on the silicon surface is removed by HF acid etching the free silicon surface is terminated by Si–H and Si–F groups. In water Si–F bonds are replaced by Si–OH but the majority of the surface is still 507

(a)

Encapsulation of MEMS Components (b) Si Si Si

Si

Si Si

Si

H F F H F H

H

H

F Si Si

F H F

Si

Si

(c)

Si Si

Si

Si Si Si Si Si Si Si Si

Fig 31.6 ● Bonding of hydrophobic silicon wafer contains three main phases that are (a) bonding via HF molecules, (b) bonding via H and F atoms with van der Waals forces and (c) formation of Si–Si bonds during high temperature annealing.

covered by Si–H rendering hydrophobic surface. The hydrophobic surface is quickly contaminated with hydrocarbons; therefore, the wafers should be quickly contacted or stored in a vacuum after removal of the silicon dioxide layer [3]. Hydrophobic bonding is also more sensitive to surface roughness than the hydrophilic bonding, since there are no water molecules between the surfaces. The bonding mechanism for hydrophobic silicon surfaces that are contacted after a dilute HF dip is presented in Figure 31.6. At ﬁrst the HF molecules form a bridge between two silicon surfaces. At temperatures from 150–300°C, the HF molecules are rearranged and additional bonds are formed. During annealing at 300–700°C, hydrogen desorbs from the surfaces and Si–Si bonds are formed according to reaction 31.3 [1]: SiH + SiH = SiSi + H2

(31.3)

During annealing at 700°C, surface diffusion of silicon takes place and closes the microgaps between the surfaces [1]. Hydrogen formed during the bonding process may cause voids at the bonded interface if no escape route for the hydrogen gas exists.

suitable for every application. A low-temperature bonding process may be needed if the wafers are pre-processed, contain temperature-sensitive materials or components, or have different thermal expansion coefﬁcients. The most common methods used for low-temperature hydrophilic direct wafer bonding are based on plasma. In these methods the wafer surface or surfaces is/are activated with a short plasma treatment prior to the wafer contacting. Numerous plasma processes have been reported for bond strengthening. The most often reported plasma gases are argon, nitrogen and oxygen. Sometimes it is advantageous to have a short wet cleaning step between activation and bonding [4]. After this, a strong bonding is achieved at low temperatures (Figure 31.7); even room-temperature processes have been reported [5, 6]. Low-temperature bonding is also possible by using surface activation methods other than plasma. Takagi et al., have reported strong bonding between silicon wafers at room temperature after surface activation with Ar ion beam [7]. Different chemical activation methods have also been published [8], but their effectiveness is not as good as plasma activation. Low-temperature hydrophobic wafer bonding is mainly done using ultra-high vacuum (UHV) bonding [9, 10]. Other reported methods involve fabrication of an amorphous silicon layer by arsenic implantation, B2H6 or argon plasma treatment or sputter deposition [11].

31.3.1 Plasma Activation Based LowTemperature Bonding The bond-strengthening inﬂuence of short plasma activation is clear and has been reported in numerous articles. However, the mechanism behind this effect is still unclear. The ﬁnal answer may not be just one effect of the plasma but a combination of many. 3000 Surface energy (mJ/m2)

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2500 2000

O2-plasma, 45s RCA1 Ar-plasma, DIW rinse

1500

No activation, DIW rinse

1000 500 0

31.3 Low-Temperature Direct Bonding of Silicon Direct wafer bonding of silicon wafers is a robust and simple method to fuse two wafers together, but it is not 508

100

200

300

400

Annealing temperature (°C)

Fig 31.7 ● Bond strength as a function of annealing temperature for different bonding processes. Plasma activation time was 30 seconds, bonding was done in air and annealing time was set to 2 hours.

Silicon Direct Bonding

During plasma treatment, many processes take place simultaneously. The plasma contains charged and neutral particles. The charged particles can be ionized atoms or molecules and electrons. These particles can react chemically with the wafer surface. During plasma processes a bias voltage is usually applied. This induces bombardment of the particles on the wafer surface, creating a sputtering effect. During plasma processes, UV radiation is also formed and it can have an effect on the chemistry of the wafer surface by breaking Si–O and Si–H bonds [12]. It has been reported by Farrens et al., that the oxide layer thickness on a silicon wafer increases by 1–1.5 nm during oxygen plasma exposure. They believe that this oxide layer contains free radical ions from the plasma, which enhance the bond strength at low temperatures by increasing the atomic mobility of reacting species at the interface [6]. The plasma has also been found to create highly hydrophilic surfaces. Reiche et al., have measured contact angles of below 2° between water droplet and wafer surfaces after plasma exposure [13]. This behavior has been found to last for several days [13]. The inﬂuence of plasma exposure on the surface roughness has been reported by many research groups [4, 13–15]. The data are controversial because some results show roughening [4, 13] and some smoothing [14, 15] of the surface. Charging of the wafer surface is also said to be the reason for higher bond energies for plasma-activated samples [6]. During plasma exposure the surface becomes charged due to implantation of the ions, ionization of the oxide and breakage of the bonds on the wafer surface, creating dangling bonds [16]. Charging of the oxide leads to electric ﬁelds, which may affect the general chemical properties of the oxide and also the ion transport [17]. The intermediate water at the bonded interface has to be removed before SiOH groups can react and form Si–O– Si bonds (Figure 31.3c). This is assumed to take place by oxygen reacting with silicon while hydrogen dissolves into the oxide. If one of the oxides is thin, the water can reach the silicon and form silicon dioxide, even at low temperature. With thick oxides, the diffusion length for water to reach the silicon is longer, which is assumed to be the reason for weaker bond strength between SiO2–SiO2 surfaces than between Si–SiO2 surfaces [4]. It is suggested that the plasma increases the kinetics of water removal from the bonded interface [4, 15, 18]. This is considered to take place due to a porous oxide layer formed by the plasma [4, 15, 18]. The porosity of the layer is suggested by the increased oxide etch rate in SC-1 solution [4, 15], by a higher etch rate during buried oxide etching with HF [19] and by X-ray reﬂectivity at the bonded interface [15]. Bond strengths as a function of annealing temperature for wafer pairs bonded with and without plasma activation are depicted in Figure 31.7.

CHAPTER 31

31.3.2 UHV Low-Temperature Hydrophobic Bonding UHV bonding has also been reported as a method for making room-temperature hydrophobic bonding [9, 10]. First the wafer pair is bonded in the same way as in hydrophobic bonding (SC-1, HF dip, wafer contacting) but no annealing is done after wafer contacting. The bonding is done at this state only to protect the surfaces during transportation to the UHV chamber. After the wafers are placed in the UHV chamber and the base pressure is pumped down to 1010 mbar, the wafers are separated. By using an elevated temperature of 450°C the hydrogen termination is removed leading to a surface with reactive dangling bonds. The wafers are cooled to room temperature and subsequently contacted in the UHV atmosphere. The measured bonding energy is close to the bond strength of the bulk silicon [9].

31.4 Direct Bonding of CVD Oxides Thermally grown oxides on prime polished silicon wafer surface can be bonded without further treatments. However, it is possible to use CVD oxides to replace the thermal oxide. This is usually done to avoid the high temperatures needed for thermal oxidation (800°C). The deposition temperatures for CVD oxides vary from 150°C to 500°C and therefore the process may be used on wafers containing temperature sensitive devices. Also, the deposition rate is fast compared to thermal oxidation and the process is not self-limiting. CVD SiO2 can also be grown on non-silicon materials and used as an intermediate bonding layer between different wafer materials. However, the CVD oxides also have some drawbacks compared to thermally grown oxide. The thickness uniformity is not in the same level with thermal oxide and the as-deposited oxide surface is usually too rough for direct bonding and requires a pre-bonding polishing step (Figure 31.8). Electrical and physical properties are also inferior to thermal oxides. In MEMS applications the CVD oxides can be used to planarize the surface before bonding. The steps on the surface of a MEMS wafer can be ﬁlled with CVD oxide and then CMP can be used to planarize and polish the surface for bonding [20]. The CVD oxides do not have the stoichiometric composition like thermal oxide and they contain impurities like Si–H and Si–OH [1]. These impurities have a tendency to outgas from the oxide when the deposition temperature is exceeded (Figure 31.9). Therefore, the bond annealing has to be lower than the deposition temperature or the CVD oxide needs to be heat treated before bonding to avoid bubble formation at the bonding interface (Figure 31.10). 509

Encapsulation of MEMS Components

PA R T V (a)

Image statistics

(b)

Img. Z range Img. Mean Img. Raw mean Img. Rms (Rq) Img. Ra

Image statistics Img. Z range Img. Mean Img. Raw mean Img. Rms (Rq) Img. Ra

26.533 nm 0.000001 nm 21.323 nm 3.323 nm 2.649 nm

1.294 nm –0.000003 nm 0.453 nm 0.126 nm 0.099 nm

1

1

2

2

X 1.000 μm/div μM

Z 20.000 nm/div

X 1.000 μm/div μM

Z 20.000 nm/div

Fig 31.8 ● (a) AFM image of as-grown LPCVD oxide. (b) AFM image of polished LPCVD oxide surface.

Fig 31.9 ● Scanning acoustic microscope image of silicon to PECVD oxide wafer pair after annealing at (a) 400°C and (b) 600°C for 2 hours.

31.5 Direct Bonding of CVD Silicon CVD polysilicon layers are commonly used in MEMS applications. If polysilicon forms the surface layer on the silicon wafer, the encapsulation (bonding to glass) is usually carried out by anodic bonding, which is not as sensitive to surface roughness as direct bonding. However, in some applications, it would be desirable to use direct bonding of polysilicon. After deposition the surface of the CVD polysilicon layer is too rough for direct bonding. The surface roughness depends on the used deposition method and the thickness of the polysilicon ﬁlm, for example, with 510

thick atmospheric pressure chemical vapor deposited (APCVD) ﬁlms roughness peak to peak value can be a couple of microns [21]. These layers require CMP processes with high removal to achieve bondable surface. Usually the CMP process has two steps, one step to “planarize” the surface and a second one to smooth it. With the two step process the polysilicon surface can be smoothed to a level of 3 Å RMS [21]. There is also the possibility to bond deposited silicon layer when it is in near amorphous state and then crystallize it with high-temperature annealing after bonding. Amorphous CVD silicon has much lower surface

Silicon Direct Bonding

CHAPTER 31

Fig 31.10 ● Scanning acoustic microscope image of Si to PECVD oxide wafer pair after annealing at 1100°C for 2 hours. PECVD oxide was pre-annealed before bonding at 1000°C for 2 hours.

Fig 31.11 ● Scanning acoustic microscope image of polysilicon to thermal oxide wafer pair made by bonding the silicon ﬁlm in amorphous state and then crystallizing it during bond annealing at 1100°C for 2 hours.

roughness (1–2 nm RMS) than polycrystalline silicon and it is much easier to polish. With CMP removal of only 50 nm the surface roughness can be reduced to 1 Å RMS. The amorphous silicon layer can then be bonded to an oxidized silicon wafer and during high-temperature

bond annealing at 1100°C the amorphous silicon layer crystallizes into polycrystalline form. The crystallization does not cause voids to the bonded interface (Figure 31.11). The problem is the low deposition rate of amorphous ﬁlms (only some nm/min).

References 1. Q.-Y. Tong, U. Gösele, Semiconductor Wafer Bonding, John Wiley and Sons, Inc., 1999. 2. F.E. Ejeckam, Y.H. Lo, S. Subramanian, H.Q. Hou, B.E. Hammons, Lattice engineered compliant substrate for defect-free heteroepitaxial growth, Appl. Phys. Lett. 70 (13) (1997) 1685–1687. 3. A. Plössl, G. Kräuter, Wafer direct bonding: tailoring adhesion between brittle materials, Mater. Sci. Eng. R 25 (1999) 1–88. 4. T. Suni, K. Henttinen, I. Suni, J. Mäkinen, Effects of plasma activation on hydrophilic bonding of Si and SiO2, J. Electrochem. Soc. 149 (6) (2002) G348–G351. 5. S. Bengtsson, P. Amirfeiz, Room temperature wafer bonding of silicon, oxidized silicon and crystalline quartz, J. Electron. Mater. 29 (7) (2000) 909–915. 6. S.N. Farrens, J.R. Dekker, J.K. Smith, B.E. Roberds, Chemical free room

temperature wafer to wafer direct bonding, J. Electrochem. Soc. 142 (11) (1995) 3949–3955. 7. H. Takagi, R. Maeda, T. Suga, Waferscale spontaneous bonding of silicon wafers by argon-beam surface activation at room temperature, Sens. Actuators A 105 (2003) 98–102. 8. H. Takagi, R. Maeda, Direct bonding of two crystal substrates at room temperature by Ar-beam surface activation, J. Cryst. Growth 292 (2006) 429–432. 9. S. Senz, A. Reznicek, T. Akatsu, G. Kästner, R. Scholtz, U. Gösele, UHV-bonding: electrical characterization of interfaces and application to magnetoelectronics, in: H. Baumgart, C. Hunt, S. Bengtsson, T. Abe (Eds.) Semiconductor Wafer Bonding: Science, Technology and Applications VI, The Electrochemical Society, 2001, pp. 48–61.

10. A. Reznicek, S. Senz, O. Breitenstein, R. Scholtz, U. Gösele, Electrical and structural investigation of bonded silicon interfaces, in: H. Baumgart, C. Hunt, S. Bengtsson, T. Abe (Eds.) Semiconductor Wafer Bonding: Science, Technology and Applications VI, The Electrochemical Society, 2001, pp. 48–61. 11. Q.-Y. Tong, Q. Gan, G. Hudson, G. Fountain, P. Enquist, R. Scholtz, U. Gösele, Low-temperature hydrophobic silicon wafer bonding, Appl. Phys. Lett. 83 (23) (2003) 4767–4769. 12. A. Paskaleva, E. Atanassova, Damage in thin SiO2–Si structures induced by RIE-mode nitrogen and oxygen plasma, Solid-State Electron. 42 (5) (1998) 777–784. 13. M. Reiche, K. Gutjahr, D. Stolze, D. Burczyk, M. Petzold, The effect of a plasma pretreatment on the Si/Si

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bonding behaviour, in: U. Gösele, H. Baumgart, T. Abe, C. Hunt, S. Iyer (Eds.) Semiconductor Wafer Bonding: Science, Technology and Applications IV, The Electrochemical Society, 1997, pp. 437–444. 14. D. Pasquariello, M. Lindeberg, C. Hedlund, K. Hjort, Surface energy as a function of self-bias voltage in oxygen plasma wafer bonding, Sens. Actuators A: Phys. 82 (1–3) (2000) 239–244. 15. H. Moriceau, F. Rieutord, C. Morales, S. Sartori, A.M. Charvet, Surface plasma activation before direct wafer bonding: a short review and recent results, in: K.D. Hobart, S. Bengtsson, H. Baumgart, T. Suga, C.E. Hunt (Eds.) Semiconductor Wafer Bonding: Science, Technology and Applications

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VIII, The Electrochemical Society, 2005, pp. 34–49. A. Paskaleva, E. Atanassova, Electrical stress and plasma-induced traps in SiO2, Microelectron. Reliab. 40 (2000) 933–940. S. Weichel, Silicon to silicon wafer bonding for microsystem packaging and formation, PhD Thesis, Mikroelektronik Centret, Technical University of Denmark, 2000. P. Amirfeiz, S. Bengtsson, M. Bergh, E. Zanghellini, L. Börjesson, Formation of silicon structures by plasma-activated wafer bonding, J. Electrochem. Soc. 147 (7) (2000) 2693–2698. T. Suni, J. Kiihamäki, K. Henttinen, I. Suni, J. Mäkinen, Characterization of bonded interface by HF etching method, in: C. Hunt, H. Baumgart,

S. Bengtsson, T. Abe (Eds.) Semiconductor Wafer Bonding: Science, Technology and Applications VII, The Electrochemical Society, 2003, pp. 70–75. 20. T. Suni, K. Henttinen, A. Lipsanen, J. Dekker, H. Luoto, M. Kulawski, Wafer scale packaging of MEMS by using plasma-activated wafer bonding, J. Electrochem. Soc. 153 (4) (2006) G299–G303. 21. H. Luoto, T. Suni, K. Henttinen, M. Kulawski, Direct bonding of thick ﬁlm polysilicon to glass substrates, in: K.D. Hobart, S. Bengtsson, H. Baumgart, T. Suga, C.E. Hunt (Eds.) Semiconductor Wafer Bonding: Science, Technology and Applications VIII, The Electrochemical Society, 2005, pp. 194–204.

32

Chapter Thirty Two

Anodic Bonding Adriana Cozma Lapadatu1 and Henrik Jakobsen2 1

SensoNor Technologies AS, Horten, Norway Faculty of Science and Engineering at Vestfold University College, Horten, Norway 2

32.1 Introduction In its most used form, the anodic bonding process consists of joining silicon with borosilicate glass [1]. Ceramics can also be used instead of glass [2]. Bonding of glass and ceramics can also be done against metals [3], alloys and other semiconductors, provided the thermal expansion coefﬁcients of the two materials are closely matched. There are metals, like Al, Ni, Cr, and Fe, which because of the thermal mismatch cannot be sealed to glasses in their bulk form, but can be bonded as thin ﬁlms or foils [4]. The anodic bonding process, known also as “ﬁeld assisted sealing”, or “electrostatic bonding” was described for the ﬁrst time by Wallis and Pomerantz in 1968 [1, 4]. Since then, it became an important step in the fabrication of microelectromechanical systems (MEMS). Joining silicon wafers with glass wafers by anodic bonding has proven to be a reliable method for packaging at wafer level for many applications. Basically, anodic bonding is a relatively simple process that provides high-quality hermetic seals. It involves bonding of silicon to borosilicate glass wafers at elevated temperature, using the assistance of a high electrostatic ﬁeld. The bonding temperature is fairly low (300–450°C), allowing the process to be performed at the end of the fabrication sequence. There is however a long way from the experimental setup which can demonstrate the method to a reliable and fast industrial tool used for the production of microsensors. A good design of the structures to be bonded, together with

the last developments of the sealing equipment, permit nowadays fast and reliable bonding over a whole wafer, for multiple-wafers stacks and for more wafers simultaneously. The main disadvantage is the thermal residual stress in the bonded structures even though the thermal expansion coefﬁcients of silicon and glasses that are used in this process are fairly close to each other [3]. In order to reduce this stress, new glasses have been developed to better match the silicon temperature coefﬁcient of expansion. Joining two silicon wafers by anodic bonding using a thin intermediate glass ﬁlm, deposited by sputtering [5–8] or by vacuum evaporation [9, 10], has also attracted the attention of both research and industry.

32.2 The Mechanism of the Anodic Bonding The anodic bonding is an electrochemical process that relies on the polarization of the alkali-containing glasses. It can be achieved by setting the two wafers together on a hot plate (300–450°C) and applying a high DC voltage to the pair (400–1000 V), such that the glass is negative with respect to the silicon. The glass polarization phenomenon has been extensively studied, both experimentally and theoretically, in steady state or slowly varying conditions [11–14]. When a DC voltage is applied to such a glass at elevated temperatures, the alkali cations are depleted from the vicinity 513

Encapsulation of MEMS Components

PA R T V

Before bonding Cathode

Na

+

Na Na

+

Na

+

Glass

Na

+

+

Na

Depleted region

+ After bonding

Silicon Anode

Fig 32.1 ● The mechanism of the silicon–glass anodic bonding.

of the anode and transported towards the cathode, as illustrated in Figure 32.1. For most of the glasses used for anodic bonding the conduction is primarily realized by Na ions and in a very small extent by K ions. As the positive alkali ions are displaced towards the cathode, they leave near the anode an alkali-depleted region. Its depth increases in time and depends on the applied voltage [13]. Because of the surface roughness, the initial contact between silicon and glass occurs only at a few locations. The two wafers are separated over almost their entire area by a small gap (see the detail in Figure 32.1), as indicated by interference fringes present at the interface. Due to the fact that the rest of the glass is conductive, almost the entire applied voltage is shared between the growing alkali-depleted layer and this gap. The resulting electric ﬁeld is very high, in the order of several MV/cm. Since electrostatic forces of attraction are largest where the gap is narrowest (i.e., around the periphery of the contact points) the nearby regions will be the next to be pulled together. In this way, the area of contact spreads outwards from the initial contact points across the entire wafer. This is clearly shown by the disappearance of the interference fringes from the interface. A large electrostatic ﬁeld persists in the depletion layer, maintaining the parts under appreciable electrostatic pressure. When silicon and glass are in intimate contact, chemical reactions take place at the interface, resulting in the oxidation of the silicon substrate and, hence, in permanent bonds between silicon and glass. There is no general agreement on the chemistry of the interface reactions [13, 15], but the formation of a thin oxide layer during bonding has been proved experimentally [16]. The wafers to be bonded must be previously polished to a smooth surface and carefully cleaned because the electrostatic forces that press them together are strongly inﬂuenced by the wafers’ separation. As an example, Figure 32.2 illustrates the effect of the wafer 514

Fig 32.2 ● The electrostatic pressure as a function of the separation between the two wafers, for an applied voltage of 1000 V and an alkali depleted region of 0.1 μm. Parameter is the oxide thickness (incremented in steps of 0.1 μm).

separation on the electrostatic pressure that develops between silicon and glass when the depleted region is 0.1 μm thick (i.e., at an early stage of the bonding) [17]. As the bonding proceeds, the depleted layer increases and the electrostatic pressure decreases correspondingly. Figure 32.2 shows that it is more difﬁcult to achieve intimate contact between the wafers when the surface irregularities are larger or an oxide is present at the interface. If the oxide is too thick, bonding does not occur at all because the bonding voltage will primarily be over the oxide and not over the interface gap. Moreover, the process time increases dramatically with increasing oxide thickness. Surface roughness, topography steps, and foreign particles on the mating surfaces must all be well controlled for a good bonding. The foreign particles produce nonbonded regions around them, whose dimensions depend on the height of the particles, the bonding temperature and voltage. For small steps and low surface roughness, the intimate surface contact required for bonding can

Anodic Bonding

Expansion ΔL/L (ppm)

2000 Si

1500

7740

1000

500

0 –400 –50 0

100

200

300

400

500 600

Temperature (°C)

Fig 32.3 ● The thermal expansion coefﬁcients of Silicon and Corning #7740 for the temperature of interest for anodic bonding.

be achieved by elastic, plastic or viscous deformation due to the high electrostatic pressure developed during bonding [18]. Therefore, the anodic bonding is less sensitive to the imperfections of the two surfaces than silicon–silicon direct bonding. Standard polished silicon wafers pose no problem for bonding. As the device density and complexity increase, the requirements which must be fulﬁlled by the anodic bonding equipment are more and more severe. Accurate alignment with tolerances in the μm range is required. For the bonding of multiple wafer stacks (often glass–silicon–glass), the alignment is complicated by the fact that one must “see” through the silicon wafer. The bonding yield depends on the ability to ensure a uniform heating and voltage distribution over the wafers. The necessity to bond in controlled environments (gas composition and pressure) adds up to the challenges. With the transition of microsystem technology from the development stage to industrial production, a high throughput becomes compulsory for cost efﬁcient production.

32.3 Glasses for Anodic Bonding The most used glass materials for anodic bonding are Corning 7740 (commonly mentioned by the trademark “Pyrex”) and Schott Boroﬂoat. Both these types are “old” compositions developed for other applications several decades ago. They were found to be suitable for anodic bonding due to their sodium content and the close match between their temperature coefﬁcients of expansion to that of silicon. Figure 32.3 shows a comparison between the thermal properties of silicon and Pyrex #7740 for the temperatures of interest for anodic bonding.

CHAPTER 32

Corning 7070 is another glass material suitable for anodic bonding. It does not match the thermal expansion coefﬁcient of silicon as well as Corning 7740 does and it is a more difﬁcult glass to bond, requiring higher temperatures and voltages. In addition a number of other glass materials from various companies with different properties of interest to anodic bonding and MEMS has been presented by the respective companies and through research papers. These are mainly in use for research applications and have not yet found their way to the volume industry.

32.4 Bonding Parameters Monitoring the electrical current through the wafer pair is a method to follow the development of the bonding process. Initially, the bonding current increases sharply due to the increase in the contact area as the wafers are pulled into intimate contact by the electrostatic forces. Subsequently the current gradually decreases until it reaches a relatively stable value. At that moment, the bonding process is completed. Figure 32.4a, b show typical current–time characteristics, measured during bonding of silicon and glass pieces with an area of 1 cm2. Parameters are the applied voltage and the bonding temperature, respectively. The higher the temperature and/or the voltage the higher the peak current and the smaller the time required for a complete bonding. The magnitude of the total electrical charge gives some information about the strength of the bond. The glass thickness is another important factor that affects the results of the bonding process (Figure 32.4c). A thicker glass means a higher electrical resistance, decreasing the effective applied voltage to the glass/silicon interface and thus generating a weaker bond. It also induces higher stress in the silicon wafer, as will be described in a later paragraph. Bonding can also be performed in vacuum. Due to a much better heat transfer, the bonding is achieved much faster at atmospheric pressure than in vacuum. At intermediate pressures electrical breakdown of the gas in the bonding chamber occurs. The theoretical maximum voltage that can be applied without gas breakdown as a function of pressure is given by the Paschen’s law [19]. This sets limits on the pressure range that can be used. During a typical 800 V/400°C bonding of common micromechanical structures sparks occur if the pressure of the gas in the bonding chamber is in the range of 2 102 to 100 mbar. These values may be somewhat different for different gas compositions and different conﬁgurations of the bonding equipment. Even when bonding in high vacuum, one has to take care to avoid plasma discharging that may occur in the 515

Encapsulation of MEMS Components

PA R T V (a)

3.5 3 1000 V

I ( mA )

2.5

800 V

2 1.5

600 V

1

400 V

0.5 0 0

20

40

60

80

100

Time (s) Bonding temperature is 400 ºC (b)

3.5 400ºC

3 2.5 I (mA)

375ºC 2 1.5

350ºC

1

300ºC

0.5 0 0

50

100 Time (s)

150

200

Bonding voltage is 1000 V 1000 V; air, 1 atm.

(c) 3.5

400ºC / 0.5 mm glass

3 I (mA)

2.5

400ºC / 1.5 mm glass

2 350ºC / 0.5 mm glass

1.5

350ºC / 1.5 mm glass

1 0.5 0 0

10

20

30

40

50

60

Time (s)

Fig 32.4 ● Current–time bonding characteristics having as parameters: (a) the voltage, (b) the temperature and (c) the thickness of the glass and the temperature.

residual gas in the sealed cavities. This residual gas is a result of the gas release from the inner surfaces of the cavities and of the reactions which lead to bonding (Figure 32.4).

32.5 Bond Quality, Failure Modes and Characterization The evolution of the bonding current is a valuable source of information about the progress of the bonding 516

process. In a typical processing sequence the bonding current, the temperature, the applied voltage and the pressure in the bonding chamber are monitored continuously. For high volume production, a high-quality seal must be ensured, meaning hermeticity over the product lifetime, high mechanical strength and low residual stress in the bonded structures. Often a low, well controlled gas pressure is required in the sealed cavities. These parameters are nearly impossible to measure quantitatively as 100% sampling on product chips. The measurements are destructive and/or time consuming, often requiring special test structures. Characteristic values for a certain process can be obtained during product and process development. The bond strength can be measured by fracture tests, such as pressure, pull, shear or bending tests [20]. The obtained values depend on the geometry of the test structures and on the method used to apply the force. Usually, they are found in the range 5–45 MPa [4, 20, 21]. Considerably larger values (120–250 MPa) are reported in [22], resulting from three-point bending tests performed on very small-sized specimens placed inside a scanning electron microscope. The main reason for these high values is a good surface ﬁnish and cleanliness of the test specimens and the fact that smallsized samples accommodate fewer strength-reducing microﬂaws. It is a commonly observed phenomenon that the cracking occurs in glass, which is often interpreted as the seal being stronger than the glass. According to the studies presented in [20], this behavior is rather a reﬂection of the asymmetric stress that develops during interfacial cracking between two dissimilar materials. The interface constitutes an irregularity and stress concentrations are unavoidable at irregularities. There are three main stress components that contribute to the fracture: the externally applied loads, the thermal mismatch between the two dissimilar materials and the stress caused by the compressed foreign particles at the interface. The hermeticity of the seal can be veriﬁed by “bombing” the devices in gases like He, N2 or air at elevated temperature. Long-term measurements of different parameters of the bonded devices can reveal the increase of the pressure in the cavities in the case of a leaking seal. Note that after long-time exposure at temperatures above 300°C, the diffusion of gas across 30– 200 μm bonded regions and in the materials themselves can be substantial even if the seal is hermetic at room temperature [23]. Through consideration and experience, it has been found that in production the best method for screening the dice with faulty bonding areas is the visual inspection (microscopy) after dicing the wafer [24]. Non-bonded

Anodic Bonding

CHAPTER 32

the bonding current; glass composition gradients from Na electromigration. The initial curvature of the wafers also inﬂuences the value of the stress in silicon.

32.7 The Pressure Inside Vacuum Sealed Cavities

Fig 32.5 ● The thermal strain induced in the silicon at the bond interface. (Bonding at: 1000 V).

areas will appear in visual inspection as voids or areas with deviating appearance. Typically this will show up as areas with signiﬁcantly lighter gray color or, if the separation between glass and silicon is larger, it will be visible as colored interference fringes.

32.6 The Thermal Residual Stress The thermal residual stress generated during cooling from the bonding temperature to room temperature is another criterion to evaluate the bond quality. It is caused by the difference between the thermal expansion coefﬁcients of silicon and glass. Figure 32.5 shows the strain in silicon at the interface as a function of the bonding temperature, as calculated from curvature measurements performed before and after the bonding process [25]. Similar results were obtained on the same samples by Raman spectroscopy. In all experiments, 400 μm thick silicon wafers were used. The glass wafers had a thickness of either 0.5 mm or 1.5 mm. As shown in Figure 32.5, bonding with thicker glass induces higher stress in silicon. Bonding at the lower end of the processing temperature range induces a compressive thermal residual stress in silicon. The higher process temperatures conduct to tensile stress in silicon. For a given silicon thickness, there is for each thickness of the glass wafer an intermediate temperature that provides a no-stress bond. For the 0.5 mm thick glass that temperature was found to be 315°C, while for 1.5 mm glass it is around 260°C. The stress-free temperature may vary slightly from batch to batch because the thermal expansion coefﬁcients do so [26]. Beside the presented thermal considerations, there are some other stress inducing effects that contribute to a compressive component of the stress in silicon [27]: temperature gradients over the silicon and/or glass during bonding; self-heating due to resistive dissipation of

Many micromechanical devices need a low pressure in their cavities. For sealed absolute pressure sensors for example, this avoids the problems induced by the temperature dependency of the gas in the reference cavity. A low reference pressure may also be a condition imposed by the range of the input signal and the required resolution. For accelerometers, the cavity pressure determines the damping and, thus, their dynamic behavior [28]. The high-quality factors required in resonant structures for high-resolution and wide dynamic range can only be obtained by reducing the air damping and thus the pressure [29]. In IR sensors, thermal conductance between the sensing element and its package, and thus the pressure, must be minimized for high sensitivity. Anodic bonding in high vacuum is possible, but it has been observed that the residual gas pressure in the cavities after bonding is higher than the pressure in the bonding chamber [30, 31]. The gases released from the inner surfaces of the cavities and those generated in the reactions which lead to bonding are trapped in the cavities and inﬂuence the performance of the sealed devices. The residual gas pressure from anodic bonding of bulk micromachined sensors can be as low as a few mbar. A residual pressure of approximately 1 mbar was reported for anodic bonded resonant structures [32]. However, for capacitive pressure sensors with very low cavity volume, the residual pressure was reported to be as high as 500 mbar [30]. Innovative techniques are required in order to solve the problems of residual gases, examples reported so far being the use of getter materials and diffusion barriers to gas atoms [30, 33].

32.8 The Effect of the Anodic Bonding on the Flexible Micromachined Structures An important issue for the design of the micromechanical structures to be electrostatically bonded is how to avoid the bonding/sticking of the ﬂexible silicon parts to the glass. For the usual dimensions of the micromachined devices and very small separation gaps, the electrostatic forces are high enough to produce collapse of the ﬂexible parts onto the glass (as illustrated in Figure 32.6). Therefore, special precautions must be taken to 517

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Encapsulation of MEMS Components

Fig 32.6 ● Illustration of the electrostatic collapse that can lead to permanent bonding or sticking.

Fig 32.8 ● Positive charges in the glass and/or in the passivating oxide over a pn-junction will cause accumulation layers on the surface of n-type silicon and/or surface depletion or inversion layers on p-type silicon.

adhesion forces after contact. The latter can be achieved by minimizing the surface energy or by reducing the real contact area, for example, by using stand-off bumps or by increasing the roughness of the surface.

32.9 Electrical Effects Fig 32.7 ● Shield electrodes may be used to avoid electrostatic collapse and sticking.

avoid these problems. The alternatives include: increasing the gap between the silicon and glass to values for which the electrostatic attraction decreases to safe values; the selective use of intermediate layers that prevent bonding; the use of a shield electrode that keeps the silicon and the glass at the same potential in the regions not to be bonded (as shown in Figure 32.7). The ﬁrst of these solutions is not suitable for capacitive devices since they require small gaps in order to provide acceptable mechanical sensitivities. When using a shield electrode, special care must be taken with its shape, because electrostatic forces develop in any region without shield and, depending on the opening size and on the ﬂexibility of the silicon underneath, may cause an undesired bonding. If the ﬂexible parts do come into contact with features on the glass wafer, even if permanent bonding does not occur they may remain attached after the bonding voltage is switched off. This is the so-called “sticking” phenomenon and is caused by the interaction forces that act as soon as the separation distance between two surfaces becomes small. It can occur during the bonding process or later on, during the operation of the device. Sticking can be prevented either by avoiding direct physical contact between the parts or by reducing the 518

The presence and the movement of the positive and negative ions through the glass, the formation of a thin oxide layer at the interface, the related charging effects and the high electric ﬁeld developed during bonding can have important effects on the electrical characteristics of the active silicon devices. The alkaline ions and various charging effects may decrease the breakdown voltages of the surface p –n junctions and increase the leakage currents after bonding. These effects are reduced when an oxide is present at the bonding interface [34]. It has been shown that after bonding the draincurrent/gate-voltage characteristics of MOS transistors shift towards more negative threshold voltages, indicating a higher positive surface charge in the gate oxide. This shift may be caused by an induced increase of the oxide charge as indicated by additional measurements on MOS capacitors [35] and/or by sodium contamination from the glass (Figure 32.8). These charging and contamination problems are difﬁcult to overcome and control if anodic bonding is to be used on the active side of semiconductor devices such as modern integrated circuits (CMOS and BiCMOS).

32.10 Bonding with Thin Films As an alternative to the bonding with bulk glass, the silicon–silicon anodic bonding with a thin intermediate

Anodic Bonding

glass layer takes advantage of the relatively low-temperature speciﬁc to the anodic bonding and the low residual stress characteristic to the bonding of two wafers made of the same material. Because the glass layer is very thin (few micrometers), its inﬂuence on the thermal behavior of the bonded ensemble is negligible for most applications [36]. The glass layer can be deposited either by sputtering [5–8] or evaporation [9, 10]. The former is a very slow process and requires a considerable time to deposit suitable glass layers. Although successful bonding with very thin glass layers (20 nm) at low voltages (10 V) has been reported in the literature [8], other authors noted that layers thinner than 0.5 μm do not bond [6, 7]. Evaporation yields three orders of magnitude higher deposition rates (up to 20 nm/s) compared to sputtering, making this process more suitable for production. The bonding procedure with intermediate glass is basically the same as the one described for bulk glass, with the mention that the negative voltage is applied to the glass-coated wafer. Nevertheless, some particularities arise from the conﬁguration of the wafer pair, as described later. Since at the bonding temperature silicon acts as a metal, an equipotential surface establishes immediately across the glass-coated silicon wafer, regardless of the shape of the cathode of the bonding equipment; therefore, bonding begins simultaneously at many points. This is beneﬁcial for the speed of the process but may result in trapped gas at the interface and thus in nonbonded regions. With proper design, the otherwise trapped gas can escape in etched cavities or through channels connected to the wafer edge. As far as the bonding temperature is concerned, it has conﬂicting effects. On one hand, the deformability of the glass layer increases with temperature; hence, its capability to overcome the imperfections of the surfaces [18]. The mobility of the sodium ions also increases with temperature, thus decreasing the glass resistivity and increasing the electrostatic forces developed between the two surfaces in contact. On the other hand, the breakdown voltage of the glass layer. Hence, the maximum voltage that can be used for bonding decreases as the temperature increases. Consequently, both the opposition to bonding and the bonding driving force are limited at higher temperatures. One important problem encountered in the bonding with sputtered layers is the production of a glass layer that can withstand the high electric ﬁeld required for bonding. Point defects in the glass layer, hard foreign particles present at the interface, and small defects at the edges of the wafer originating, for example, from handling determine the breakdown to occur at much smaller electric ﬁelds than for defect-free layers. An improvement can be obtained if the glass is depos-

CHAPTER 32

ited on top of a thermally grown oxide layer and if the wafer is thermally annealed prior to bonding. Such a treatment (for example, 3.5 hours at 550°C in nitrogen) is also recommended for stress relief in the sputtered layers [8]. Because of the lower applied voltage, the electrostatic forces that develop during bonding are lower than in the case of the conventional anodic bonding, making this process much more sensitive to the surface imperfections. Although there has been some time since this method was ﬁrst proposed, there are still no reported industrial break-throughs for bonding with sputtered glass, probably because of the presented drawbacks. Some researchers believe that the evaporated glass is a potential breakthrough for industrialization of siliconto-silicon anodic bonding for packaging of micromechanical devices [37]. The much higher deposition rates allow thicker and, hence, more breakdown-resistant glass layers to be obtained in shorter times. 5–7 μm thick glass layers were successfully used to bond two silicon wafers, with high yield, practically 100%, at bonding temperatures higher than 350°C. A high compressive stress (225 MPa) exists in the as-deposited layers, but it is reported that this stress can be relieved by annealing at around 340°C. A bonding-induced, relatively small compressive stress has been noted. It is mainly inﬂuenced by the geometry and the applied force of the bonding electrodes. The deposition and bonding parameters still need to be optimized and the process to be proved successful for the bonding of wafers containing microstructures, in industrial conditions.

32.11 Conclusions The anodic bonding is by its physical and chemical nature a method with a high potential resulting in close to perfect hermetic seals. There are adverse effects acting on the bonded structures, which must be taken into account and dealt with during the process and product development. This technique is then a reliable tool for the wafer-level bonding of microelectromechanical structures and similar devices (optics, ﬂuidics, BIOMEMS). The method is used in an increasing number of industrial products and it is also offered as part of industrial foundry services (www.multimems.com). More work needs to be done to reduce and control the pressure of the residual gas in bonded cavities, to minimize the negative effects on the mechanical ﬂexible parts, to develop robust designs that limit ionic contamination and charging effects when bonding on and near electrically active devices. More work is also needed on thin ﬁlm bonding to develop it to become a reliable industrial process. 519

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References 1. Pomerantz, US patent 3,397,278, 1968. 2. K. Gustafsson, B. Hok, S. Johansson, T. Murray, Sensor. Mater. 2 (1988) 65. 3. Pomerantz et al., US patent 3,417,459, 1968. 4. G. Wallis, D.I. Pomerantz, J. Appl. Phys. 40 (1969) 3946. 5. A.D. Brooks, R.P. Donovan, J. Electrochem. Soc. 119 (1972) 545. 6. H. Hebiguchi, S. Shoji, M. Esashi, Tech. Digest 9th Sensor Symposium, 1990, p. 31. 7. A. Hanneborg, M. Nese, H. Jakobsen, R. Holm, J. Micromech. Microeng. 2 (1992) 117. 8. J.W. Berenschot, J.C.E. Gardeniers, T.S.J. Lammerink, M. Elwenspoek, Sensor. Actuators A 41–42 (1994) 338. 9. R. de Reus, M. Lindahl, Tech. Digest International Conference on Solid-State Sensors and Actuators (Transducers‘97), 1997, p. 661. 10. W.B. Choi, et al., J. Vac. Sci. Technol. B 15 (1997) 477. 11. J.M. Proctor, P.M. Sutton, Spacecharge development in glass, J. Am. Ceram. Soc. 43 (4) (1960) 173. 12. P.M. Sutton, Space charge and electrode polarization in glass: II, J. Am. Ceram. Soc. 47 (5) (1964) 219. 13. D.E. Carlson, K.W. Hang, G.F. Stockdale, J. Am. Ceram. Soc. 55 (1972) 337. 14. D.E. Carlson, J. Am. Ceram. Soc. 57 (1974) 291. 15. B. Schmidt, P. Nitzsche, K. Lange, S. Grigull, U. Kreissig, Tech. Digest. European Conference on Solid-State

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17. 18. 19. 20.

21.

22. 23.

24.

25.

26.

Transducers (Eurosensors XI), 1365, 1997. H. Baumann, S. Mack, H. Münzel, Semiconductor Wafer Bonding Physics and Applications III: Proc. vol 95-7 Electro Chemical Society Inc. Pennington, NY, 1995, p. 471. A. Cozma Lapadatu, PhD Thesis, K.U. Leuven, 1999. T.R. Anthony, J. Appl. Phys. 54 (1983) 2419. F. Paschen, Ann. Phys. 37 (1889) 69. E. Obermeier, Semiconductor wafer bonding III: science, technology and applications, in: C.E. Hunt, H. Baumgart, S.S. Iyer, T. Abe, U. Gosele (Eds.), PV 95–7,212, The Electrochemical Society Proceedings Series, Pennington, NJ, 1995. S. Johansson, K. Gustafsson, J.Å. Schweith, Sensor. Mater. 4 (1988) 209. S. Johansson, K. Gustafsson, J.Å. Schweith, Sensor Mater. 3 (1988) 143. M.M. Visser, S.T. Moe, A.B. Hanneborg, J. Micromech. Microeng. 11 (2001) 376. H. Jakobsen, A. Cozma Lapadatu, G. Kittilsland, Tech. Digest, 6th International Symposium on Semiconductor Wafer Bonding: Science, Technology, and Applications, San Francisco, USA, September 2–7, 2001. A. Cozma, R. Puers, Characterisation of the electrostatic bonding of silicon and pyrex glass, J. Micromech. Microeng. 5 (1995) 98. Sealing Glass, Corning Tech. Pub., 1981.

27. E. Peeters, PhD Thesis, K.U. Leuven, Belgium, 1994. 28. K. Minani, T. Moriuchi, M. Esashi, Tech. Digest, International Conference on Solid-State Sensors and Actuators (Transducers‘95), 1995 p. 240. 29. T. Corman, P. Enoksson, G. Stemme, Sens. Actuator A 61 (1997) 249. 30. H. Henmi, S. Shoji, Y. Shoji, K. Yoshimi, M. Esashi, Sens. Actuator A 43 (1994) 243. 31. S. Mack, H. Baumann, U. Gösele, H. Werner, R. Schögl, J. Electrochem. Soc. 144 (1997) 1106. 32. T. Corman, P. Enoksson, G. Stemme, Sens. Actuator A 66 (1998) 160. 33. Y.T. Cheng, W.T. Hsu, L. Lin, C.T. Nguyen, K. Najaﬁ, Tech. Digest International Conference on Micro Electro Mechanical Systems, MEMS 2001, 18. 34. A. Cozma Lapadatu, H. Jakobsen, R. Puers, Tech. Digest, International Conference on Solid-State Sensors and Actuators (Transducers‘99), 1416. 35. K. Schjølberg-Henriksen et al., Tech. Digest. European Conference on Solid-State Transducers (Eurosensors XIV), 2000. 36. R. Holm, T. Kvisterøy, H. Jakobsen, A. Hanneborg, P. Ohlckers, Tech. Digest, International Conference on Solid-State Sensors and Actuators (Transducers) 1991, p. 978. 37. S. Weichel, Silicon to silicon wafer bonding for microsystem packaging and formation, PhD Thesis, Mikroelektronic Centret, Technical University of Denmark, 2000.

33

Chapter Thirty Three

Glass Frit Bonding Roy Knechtel X-FAB Semiconductor Foundries AG, Erfurt, Germany

Glass frit bonding is a widely used technology to cap and seal micro-electromechanical systems on the wafer level using structured capping wafers, mostly made from silicon. Glass frit bonding technology provides a wide range of possibilities for the bonding of wafers at process temperatures below 450°C. Nearly all the surface layers commonly used in silicon micromachining can be bonded using glass frits. Due to the use of melted glass in the bonding process, the main advantages of glass frit bonding are excellent hermetic sealing, high process yield, lower stress at the bonding interface, the possibility of incorporating metallic lead-throughs, high bonding strength, and good reliability. The process consists of three main steps: screen printing of a glass paste, thermal conditioning, and thermo-compressive bonding.

33.1 Bonding Principle Glass frit wafer bonding is based on low-melting-point glass as an intermediate bonding layer. The bonding process is thermo-compressive. The glass material, which is normally deposited on the cap wafer, softens during heating and wets the surface of the second wafer due to mechanical pressure. During the cooling process, a strong hermetic wafer bond is formed. At the bonding temperature the glass is soft enough to ﬂow and cover surface steps and roughness, such that the glass frit acts as a planarizing and sealing interlayer between the two wafer surfaces to bond. This is the main reason for the

Fig 33.1 ● Glass-frit bonding interface.

high process stability. The thermal expansion of the glass material is adapted to silicon, so that the stress in the wafer stack is very low. Figure 33.1 shows a crosssection of a glass frit bonding interface, and Figure 33.2 a principle process overview.

33.2 Glass Frit Materials The glass frit bonding requires low-melting-point glass with a process temperature1 of less than 450°C to be suitable to bond fully-processed MEMS wafers with standard aluminum metal structures. To reach such low process temperatures, lead or lead silicate glasses must be used.

1

The relevant process temperature for the glass used for glass frit bonding is the so-called wetting temperature, which is reached when, during heating, the viscosity of the amorphous glass becomes low enough to wet the surface to bond by self-ﬂowing. 521

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Cap wafer structuring Glass frit screen printing Thermal [°C] 600 450 300 glass frit 150 0 conditioning

Encapsulation of MEMS Components

Processing MEMS wafer

[min]

Wafer to wafer alignment

Table 33.1 Overview of commercially available glass frit materials for glass frit bonding

Vendor

Material

Process Description/ temperature remarks

Ferro Corporation [1]

FX11-036

425–450°C

–noncrystallizing glass frit material –provided as readyto-use paste

CN33-246

425–450°C

–silver-ﬁlled glass frit for conductive glass frit bonding –based on FX11-036

G018-173

430°C

–available as powder and paste –glass thermal extension adapted to silicon; no ﬁller required –crystallizing glass

Bonding 430°C

Fig 33.2 ● Process ﬂow of glass-frit bonding.

The glass has to be transformed into a viscose paste which can be deposited by screen printing. Therefore, the low-melting-point glass must be milled into a powder with a recommended grain size of less than 15 μm. Mixing this powder with an organic binder forms the printable paste. By adding inorganic ﬁllers, the properties of the ﬁnally melted glass frit can be inﬂuenced (e.g., the thermal expansion coefﬁcient can be adapted to silicon). Normally this mixing of the rather high-viscose glass paste is done using special mills to give a homogeneous mixture of all the components. However, by adding additional solvents, the viscosity can be lowered, if required, for processing. Glass frit materials are available from various vendors. Table 33.1 provides an overview of some glass frits suitable for MEMS wafer bonding, but it cannot be completely comprehensive, since any vendor or user can create glass frit materials with special characteristics by melting new glasses and mixing special pastes. The most widely used glass frit in industrial practice is Ferro FX11-036, which is provided as a ready-to-use product. This is based on a noncrystallizing lead silicate glass as the low melting active bonding component, which gives very stable, reproducible processes in thermal conditioning and bonding. The following description summarizes this material: The paste FX11-036 consists of a Lead-Borosilicate-Glass (70–80% mass) as the active low melting bonding glass, a Barium-Borosilicate-GlassCeramic (up to 15%) as a ﬁller to reduce the thermal expansion coefﬁcient of the lead glass from 9 106K1 to around 8.6 106K1, a polymerizing binder (Trimethylpentanediol-Monoisobutyrat 10–25%), a polymerizing agent (Isobutyl-Methakrylat up to 5%), and Terpineol (up to 5%) as a solvent. The particle size of the glass components is speciﬁed to be lower than 15 μm, but is typically lower than 1 μm (90%). The viscosity of the paste is in the range of 300–600 poise. Further information on the material is provided by the vendor in the process speciﬁcation [3] and the material safety sheet [4]. To reach the required low process temperature for glasses, i.e., a wetting temperature below 450°C, it is necessary 522

Schott Glass [2]

to use lead glasses or lead-containing Borosilicate glasses, even though lead is currently prohibited for use in electronics. However, the RoHS instruction [5] contains, in the appendix, lead in the glass of electronic devices. On the other hand, the automotive lead instructions [6] allow up to 6 g lead per car, but a typical glass frit bonded inertial sensor (chip 5 5mm2) contributes less than 1 mg. From this, glass frit bonding can be seen to be compatible to the actual environmental instructions. Additionally, glass experts do not see any environmentally friendly alternative to lead in order to obtain low melting glasses. Therefore, lead-containing glass frits will very probably be used for many years.

33.3 Screen Printing Screen printing provides an in-situ deposition and structuring of the glass frit material. The main advantage is the possibility of material deposition on cap wafers with high steps or holes. Furthermore, no additional effort, like photolithography, is necessary for structuring. Using screen printing, the paste can be deposited and structured in one step. Screen printing should be done on the less sensitive, less critical wafer, normally the capping wafer, because it is a fairly rough process with mechanical contact of the mesh to the wafer. For printing, glass frit paste Polyester meshes are used. Due

Glass Frit Bonding Printed structure Squeegee Mesh Screen F Opening

CHAPTER 33

Printing paste (glass frit)

V

Mesh travel Chuck Wafer fixing

Frame

Wafer

Fig 33.3 ● Schematic drawing of a screen printing mesh and the screen printing principle.

500

2500

2000

1000

1500

160000 80000 Z(Å) 0

1000 800 Y(μm) 600 400 200 0 0

to their very ﬁne wires in comparison to metal meshes, in the diameter range of 30 μm, these allow a printed wet paste thickness of 35–40 μm, as suggested by the paste vendors. The mesh openings are deﬁned by the maximum paste particle size of 15 μm and should be 3 times larger, i.e., 45 μm. The mesh is adhered to a frame typically 3–4 times larger then the printing area (wafer size) and coated with a thin photosensitive screen layer. After the photochemical structuring, this layer deﬁnes the print structures like the bond frames, but the mesh provides a ﬂexible support for them (Figure 33.3). Because the mesh is typically mounted at an angle of about 35°, the print structure edges normally do not run parallel to the mesh wires. The screen printing itself is a complex process, depending on the shape and size of the structures to print, the mesh (tension, material, mesh counts), the printing material (especially its viscosity), and the print equipment (squeegee), as well as on the printing parameters (printing speed, squeegee pressure, screen travel). Therefore, in practice it must be adapted and optimized for every setup and application. The principle of screen printing is shown in Figure 33.3, while additional information on meshes and printing can be found in [7]. As mentioned earlier, the screen printing of the glass frit is a complex process, and the shape as well as the dimensions of the printed structure depend on the printing process parameters and the paste viscosity. Nevertheless, some general design rules for the screen printing structures can be recommended. All screen printing structures in one chip design, and preferably in the complete wafer layout, should have the same printing width. The printing thickness depends on the printing width, since the broader a structure is, the thicker it will be printed; but bonding requires a homogeneous printing thickness for complete sealing and homogenous bond pressure distribution. Figure 33.4 illustrates this effect in the corners of standard bond frames, but at a tolerable, low level. The minimum design width of the screen printing structures is 150 μm, if closed glass frit lines such as are necessary for hermetic bonding are required (Figure 33.5). A screen opening of 150 μm corresponds to about 2–3

X(μm)

Fig 33.4 ● Proﬁle printed frames.

Narrowest closed structure

151 μm 189 μm

Design measures

110

130

150

Critical regarding hermeticity μm 170 190

Fig 33.5 ● Design rules for minimal structure widths.

completely opened mesh points, so that this is also, from the theoretical side, the required minimum for a closed line printing. It is possible that the one mesh opening is closed by adhering paste, and in this case one opening at least remains to bring the paste onto the wafer. Due to a slight under-ﬂowing of the paste under the mesh, which is typical for a safe printing process, the printed line width is increased by about 10%. The minimum space between two lines in the design must be 120 μm if a gap without any glass paste of about 100 μm has to remain after the screen printing (Figure 33.6). This point is not so important for the bonding, but interesting if, e.g., a 523

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dicing street between two bonding frames has to be free of glass frit. In addition to the minimal geometries of the screen-printed bond frames, we must also consider their relationship to the active structures which have to be sealed, but must be free of any glass frit to guarantee their function (e.g., moveability). Critical for this are the rounding of inner corners due to surface tension of the paste during the printing (Figure 33.7), the alignment of the mesh and its stretching at printing, as well as the glass ﬂowing and misalignment at bonding. Figure 33.8 illustrates all these effects, which need to be considered in the bond frame and chip design to achieve an optimum solution. Finally, all of these technological effects of the screen printing and bonding result in an increase of the bond area required on the MEMS wafer by a factor of 3 in relation to the minimum required mesh opening. This is not adaptable for economic MEMS manufacturing. Therefore, the use of a self-aligning glass frit screen printing is recommended. By this principle, the bond frame is deﬁned by highly precise silicon etching of

the bond frame at the capping wafer. As shown in Figure 33.9, the silicon area beside the required bond frame must be lowered by anisotropic wet or dry silicon etching, so that the bond frame area remains as a silicon ring which will be completely covered in the screen printing process if a mesh with an opening about 100 μm larger on each side (screen print alignment and mesh stretching) as the silicon structure is used, and because the screen printing works only at the original wafer surface and not in the etched areas, the glass paste stops at the silicon structure edges. By this, the glass frit bond structures are very well deﬁned in geometry, placement can be reached (Figure 33.10), and the total bond frame width on the MEMS wafers is reduced to about 200 μm.

33.4 Thermal Conditioning Prior to the bonding, thermal conditioning is necessary in order to transform the paste into a real glass. During this preconditioning, the binder and solvent are burned

Smallest realized distance

Inner corner rounding at screen printing due to surface tension

Flown glass paste 40

60

80

100

120

160 μm

140

Fig 33.6 ● Design bond rules for minimal structure spacing.

Fig 33.7 ● Corner rounding.

Minimum mesh opening 150 μm Increase at screen printing 20 μm per side Flowing at bonding 40 μm per side Screen printing misalignment ± 90 μm Mesh alignment and stretching Misalignment at bonding ± 10 μm Total area requirement MEMS wafer 470 μm in width Active areas finally free of glass frit

524

Corner rounding 300 μm

Fig 33.8 ● Bond frame area requirements MEMS wafer.

Glass Frit Bonding

out and the glass is premelted. The process step is very important to prevent voids due to gas generation by organic residuals during bonding inside the bonded glass, which would lower its strength and reliability (Figure 33.11). During the thermal conditioning proﬁle (Figure 33.12) of the glass paste, the organic binder has to be burned out completely. In the ﬁrst step at 120°C, the paste is dried, and in addition, the binder polymerizes to form very stable structures suitable for storing and shipment (e.g., if the screen printing is done by a subcontractor) if

CHAPTER 33

required. For the essential binder burn out, the paste is heated to an intermediate temperature of 340°C, where the glass does not yet fully melt, in order to allow outgassing of the organic additives. During the subsequent premelting, where the material is heated to the process temperature and fully melts, a compact glass without any gas inclusions is formed. Because the glass frit is hygroscopic, the bonding should be done at least for a few hours after this proﬁle, or an additional temperature step at 120°C for a minimum of 20 minutes should be performed just before bonding.

33.5 Bonding Process

Mesh Opening

Misalignment Required print area Realized print

Self-alignment of glass frit screen printing at structures etched in silicon

Fig 33.9 ● Principle of self-aligned screen printing.

Standard screen printing at flat surface

Self-aligned screen printing limited by surface steps

Fig 33.10 ● Screen printing results.

The bonding is a thermo-compressive process. By heating up the glass to the wetting temperature in the temperature range of 425–450 °C, its viscosity decreases to the point where it wets the bonding surface. Material from the surface layer fuses into the glass on the atomic level, and a strong bond is formed during cooling. The bonding temperature is the critical bonding parameter because it must be high enough to guarantee good wetting of the bonding surface with the glass, as the initial process for bond formation. The bond pressure gives only some support for the wetting and equals wafer geometry inadmissibility such as bow and warp. Therefore, this can be in the range of 300–1500 mbar for the bonding of 6 in. wafers. The ﬂowing of the glass frit during bonding can be controlled by the pressure, since the higher the pressure, the stronger the ﬂowing will be. A slight ﬂowing of the glass is required for good surface wetting and hermetically sealed bonding. However, too strong ﬂowing may give the risk that the glass can ﬂow onto active structures, disturbing their function. Wide wafer bonding areas are required in the design if strong ﬂowing is demanded. The cooling of the bonded wafer pair is only critical at the higher temperatures where the bond is ﬁnally formed. However, to prevent thermal cracking of

Fig 33.11 ● Voids in glass frit caused by insufﬁcient heat treatment of the glass paste.

525

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Encapsulation of MEMS Components

Fig 33.12 ● Thermal proﬁle and mechanism of the transformation of the glass frit paste in glass.

the wafers or the bonded interface by thermal shocks, the wafer stack has to be cooled below 200°C before removing from the bonding chamber. In principle, the bonding can be done in any gas at atmospheric pressure, as well as over, under, and at vacuum pressure ranges. However, as mentioned earlier, the bonding temperature is the most important process parameter, so that its control recipes must be adapted to the pressure-dependent heat transition in the bond equipment. Figure 33.13 illustrates the glass frit bonding process, step by step, based on the bonding machine logging and a picture sequence from partially processed bond frames. The challenge of glass frit bonding is to handle the soft bonding material between the two wafers to bond. The material must be soft enough to wet the surface for bonding the wafers and seal the MEMS structures, but not too soft to ﬂow into them. Because the process window for optimum glass ﬂowing during bonding is very small (5–10K, which is approximately the temperature control accuracy of the bonding equipment; see Figure 33.14), and is additionally effected by the screen printing, it is suggested that ﬂow stopping structures should be introduced in the MEMS or capping wafer design. These can be grooves or sloped cavity edges which are ﬁlled or covered by the glass frit, providing a lateral ﬂow stop, because, by its good wetting behavior, the glass frit 526

ﬁlls the surface steps ﬁrst (Figure 33.15). Even if a low glass viscosity is required for good bonding, and especially for good sealing, too low a viscosity is also critical, because, during bonding, out-ﬂowing of the glass from the bond frame structure by wetting only one of the bonding surfaces is possible. This causes the glass material to be locally missing to ﬁll the bonding gap between the two wafers, resulting in open or very narrow bond frame areas, as shown in Figure 33.14a. During ﬂowing, there is a dismixing of the glass components as seen in Figure 33.15, where only the low viscous lead glass is ﬂowing, while at the bonding temperature, solid ﬁllers remain as printed. So far, no negative dismixing aspects are known from practice, but too strong a ﬂowing and dismixing might cause reliability or stress issues because of differences in the thermal expansion of ﬁller rich and poor areas in the bonding frame. Another issue of the soft glass of bonding is the possible shifting of the wafers during bonding by sliding over each other at the viscous glass layer. Even if the alignment before bonding is very exact (1–2 μm alignment accuracy can be easily achieved using state-of-theart alignment tools and target structures), the post bond alignment could be worse as a result of this shift. To reach a tolerable shift of less than 10 μm during bonding, all possible force components parallel to the bonding

Glass Frit Bonding

450 400 350 300 250 200 150 100 50 0

Process steps Wafer loading machine reset

Printed bond frame before bonding

Switch off bond pressure Lifting bond tool Remove clamps Wafer unload 450 Temperature chuck heater 400 Temperature tool heater 350 300 250 Tool pressure 200 150 100 50 0 0 10 20 30 40 50 60 Time in min Wafer Wafer Time at Final Wafer heating temperature cooling unloading cooling at pressure at pressure Lowering bond tool Applying bond pressure Heating Start cooling

Pressure in mbar

Process parameters

Temperature in °C

Bond Contact tool position actions Wafer loading

CHAPTER 33

Start of the bond process

Surface wetting by the glass frit

Glass frit flowing

Fig 33.13 ● Overview of glass frit bonding process.

(a)

(b)

(c)

Optimum bonding Bonding temperature too low (390°C), glass still temperature (425°C) too highly viscous to flow good bonding, but no flowing out of structures

Bonding temperature too high (450°C), glass too soft, flowing out of structures, but without wetting of both bonding surfaces

Fig 33.14 ● Glass frit ﬂowing during wafer bonding.

interface must be eliminated in the machine setup: exact perpendicular pressure tool movement to the wafers, pressure plates adapted to the thermal expansion of the silicon (e.g., from silicon carbide) to prevent expansion tolerances, and exact chuck and ﬁxture leveling. Because, ﬁnally, all these adjustments cannot be done absolutely exactly, it is necessary to perform the glass bonding with closed clamps (Figure 33.16).

Only this extra ﬁxation of the wafer alignment during the bonding can provide a post bond alignment in the expected range. If the essential clamping elements are ceramic rolls, they do not provide a strong force parallel to the wafer surface, so that they do not prevent the radial thermal expansion of the wafers and are not critical regarding stress in the bonded stack. The clamps should be kept closed until the bonded stack is cooled 527

Encapsulation of MEMS Components

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to lower than 300°C, when the glass becomes hard again. Due to the nonplanar surface of the glass frit, spacers are not necessary if bonding at a certain pressure (over, under pressure or vacuum) or if gas has to be sealed in the cavities at bonding. In any case, gas can pass through the nonbonded glass frames at areas where they are locally slightly thinner. Therefore, the spacers must not be moved between the clamped wafers which would be critical regarding alignment and wafer surface quality. Even if, in the best case, a post bond alignment accuracy of a very few micrometers is possible, misalignments of 10–20 μm should be considered in the design of the bonding frame for a stable process.

glass and a very thin glass mixture layer occurs at the interface, which forms a strong bond between the glass and the wafer. The amount of glass solving depends on the layer to bond and the thermal budget of the bonding process. Thermal oxide can be solved in the glass up to a thickness of several hundreds of nanometers, and even a complete layer thickness can be solved if it was initially in this range. Silicon is solved signiﬁcantly less, and from silicon nitride and aluminum only a few atomic layers are usually solved in the glass frit. The SEM image in Figure 33.18 illustrates the solving behavior of different layers to bond at a cross-section of a lead through a duct of an MEMS sensor.

33.6 Physics of Bonding The requirement for forming a stable glass frit bond is to heat up the glass material to a temperature high enough to reduce its viscosity to enable the wetting of the wafer surface. This wetting means the complete covering of the wafer surface with glass over the area of the bonding frame. Figure 33.17 shows very good wetting of a silicon surface by the glass frit, indicated by a low edge angle. If the glass and the wafer surface are in good contact, wafer surface layers can be solved in the Fig 33.17 ● Good wetting of a silicon surface by the glass frit indicated by a low contact angle. Sensor structure Flow stop at KOH etched cavity edge side wall, by wetting the KOH etch flank and filling the increasing gap Flowed lead glass component Filler rich glass component shape as screen printed

Fig 33.15 ● Glass ﬂowing and stopping.

(a)

Fig 33.18 ● Solving behavior of different layers in glass frit.

(c)

(b)

Clamp springs Clamps with rolls Possible Clamping force gas flow Glass frit 3 μm 32 μm

1 μm

2 μm

Fixture Bonding without clamps

528

Bonding with clamps

Principle glass frit bonding with closed clamps

Fig 33.16 ● High accuracy aligned glass frit bonding examples and principle. (a) Bonding without clamps. (b) Bonding with clamps. (c) Principle glass frit bonding with closed clamps.

Glass Frit Bonding

By solving the surface layers in the glass frit, the glass chemical equilibrium is disturbed, especially during bonding of the silicon surface. Strong chemical reduction reactions are occurring, and organic lead balls are growing in the bond interface glass frit silicon. These lead dissolvings are not critical for the bonding strength [8], but disturb the electrical insulation behavior of the glass frit, because they grow by thermal loading (Figure 33.19).

CHAPTER 33

During an extensive series of experiments and production, it was shown that the glass frit bonding is a very stable and safe technological process for joining processed wafers together. Process inﬂuences were investigated, and the interface was characterized. Using glass frit bonding, nearly all surface materials commonly used in microsystems technologies (silicon, silicon oxide, silicon nitride, aluminum, or glass, e.g., Pyrex ®) can be bonded, without any special process adaptation, with high process yields. Activation of the bonding surface is not necessary, and hydrophobic surfaces are bondable as well as hydrophilic. One of the main advantages of glass frit bonding is the possibility of bonding rough wafer surfaces, enabled by the wetting effect of the glass at the bonding temperature. This is very important, because often the bonding surfaces of processed wafers are left rough by preceding plasma etching or deposition steps. Metallic lead-throughs can be realized by glass frit bonding, since the viscous glass covers the steps of metal lines and seals them hermetically (Figure 33.20). In this way active structures inside a hermetically sealed cavity can be easily contacted. This is important for high-quality or high-frequency signal transport. The glass frit is a dielectric material. Measurements have shown that up to up 50 V and 125°C, additional passivation is not necessary to prevent leakage currents between the metal lines crossed by the glass frit. However, passivation of the metal under and beside the glass frit is

recommended for reliability reasons. Accelerated humidity tests have shown that metal structures (aluminum) close to the glass frit may be attacked slightly by reaction products or by humidity. The bonding interface needs to be strong enough to withstand subsequent process steps such as dicing and packaging. Furthermore, the bonding has to ensure good protection of the active structure during the lifetime. Pull tests have shown that the bonding interface is strong enough to fulﬁll these requirements, and can be achieved with anodic bonding (20 MPa, related to bond frame area). In pull tests, it was shown that the glass frit bond strength is very high. The breaking behavior is dominated by the glass, and normally the glass–silicon interface is stronger than the glass itself. Typically, an alternating fracture occurs in the glass frit interlayer. Because the glass is a brittle material, this kind of fracture must be explained by defects in the glass which might be microvoids in the glass or sharp notches at the ﬁller particles. For practical use, the bonding strength is high enough, so that an improvement of the glass properties is not necessary. Hermetic sealing is often required to ensure the correct functioning and sufﬁcient reliability of the capped micromachined components. Therefore, hermeticity investigations were performed with the glass frit bonded devices. Because of the lack of MEMS hermeticity testing standards, resonant structures were chosen whose frequency behavior depends on the gas pressure in the space surrounding the structures. The structures we used show resonant behavior only when moving in vacuum (Figure 33.21), and therefore provide a very sensitive pressure indication. Testing several resonant structures has shown that a vacuum of about 1–5 mbar can be sealed using glass frit bonding. After different kinds of loading, no shift of the sealed cavity pressure was observed. The bonding glass interlayer has a typical thickness of from 5 to 10 μm. This is high enough to provide working gaps (sticking prevention, deﬁned damping) over capped moveable structures, but the tolerances are still too high for functional gaps (counter electrodes on cap).

Fig 33.19 ● Elementary lead dissolving at silicon glass frit bonding.

Fig 33.20 ● Metallic lead through duct in glass frit.

33.7 Characteristics

529

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Encapsulation of MEMS Components

Standardized sensor output

Because the thermal expansion coefﬁcient of the used Ferro glass frit (FX-11 036) is about 7 106K1, although ﬁller particles are used for its lowering, mechanical stress was found in the glass frit layer prior to bonding. Thin perforated cap wafers showed bow values of up to 450 μm; however, after the bonding, this stress is compensated by the bonded wafers of nearly the same thickness, so that it cannot inﬂuence the structures in the active sensor layer, as test structures and sensor characterizations have shown. From the reliability point of view, the fracturing behavior of the glass can be slightly inﬂuenced by thermal shocks and humidity. Rapid thermal shocks (190 air to 25°C water) have shown a signiﬁcant decreasing of the fracture load of bonded chips. During the thermal shock, initial fractures in the glass grow, driven by thermo-mechanical stress caused by the differences in the thermal expansion coefﬁcients of silicon and glass. These shocked samples fail at lower loads. On the other hand, pull tests after humidity storage showed an increased fracture strength. The reason, therefore, is a rounding of defects in the glass at the outside of the bond frame by removing a very small amount of the slightly humidity-sensitive glass. As a result, the defect level is reduced and the bonding strength increased. 2 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 0 100

33.8 Conductive Glass Frit Bonding By using a silver-particle-ﬁlled conductive glass frit, in addition to the classical nonconductive glass frit in a single thermo-compressive bonding step, wafers can be joined mechanically, and local contacts formed between the MEMS and the capping wafer, in order to allow the cap to be used as an active electrical element, such as a signal conditioning ASIC, an electrical shield, or a sensor counter electrode in the wafer level system integration. The material used for the conductive glass frit bonding is CN33-246, commercially available from Ferro Corporation (Data sheet CN33-246). This material is based on Ferro FX11-036, widely used in silicon-based micromachining for glass frit cap wafer bonding. In contrast to the standard glass frit, CN33-246 is densely ﬁlled with ﬁne silver particles (typically, 2 μm) at a content of about 80%. Because the silver particles dominate, they form conductive paths in the glass matrix after processing. Figure 33.22 shows the structure of a ﬁred conductive frit, and Figure 33.23, the forming of conductive paths [9].

Silver particles

Hermetic sensor Non-hermetic sensor

1000

Glass matrix

10000

Clustered silver particles as conductive path

Log frequency (Hz)

Fig 33.21 ● Hermeticity evaluation using resonant structures.

Fig 33.23 ● Principle of forming conductive paths in the frit.

Fig 33.22 ● SEM images of silver-ﬁlled conductive glass frit.

530

Glass Frit Bonding

Even if the conductive glass frit CN33-246 is not suitable for providing a mechanically strong and reliable bond between two silicon wafers due to its high silver content, it can be used in addition to the XF11-036 bonding and sealing glass. Therefore, the conductive glass frit needs only to ensure a good electrical contact. Because the active low melting point glass components in both frits are the same, each material can be bonded with the same process parameters. As a result, a mechanically strong bond with hermetic sealing and electrical contacts is similarly formed.

CHAPTER 33

33.9 Cost of Glass Frit Bonding Even if the glass frit bonding provides a very safe process and many excellent bond interface properties, the process costs are rather high and have to be considered in the cost calculation of the MEMS product that the glass frit bonding is used for. The costs are driven by the glass frit material, complex processing (screen printing and thermal conditioning), and the fact that the bonding is not a batch process, requiring a bonding time of about 45 minutes per bonded stack.

References 1. Ferro Corporation, 1000 Lakeside Avenue Cleveland, Ohio 44114-7000 USA www.ferro.com 2. SCHOTT Electronics GmbH, Christoph-Dorner-Strasse 29, 84028 Landshut Germany, www.schott.com/ epackaging 3. MEMS & Sensor Materials 11-036 Sealing glass, in: Process Speciﬁcation FERRO Electronic Materials, Santa Barbara, California, Rev. 1200 2002. 4. FERRO 11-036 SEALING GLASS for low temperature processing, in: Product

Safety Sheet FERRO Electronic Materials Santa Barbara, California, 1999. 5. Restriction of Hazardous Substances Directive (RoHS) 2002/95/EC, adopted in February 2003 by the European Union, valid since July 1, 2006. 6. http://www.cleancarcampaign.org/lead. shtml 7. Screen Printing Precision, Product Catalog with technical information, Könen GmbH Otto-Hahn-Straße 40 D-85521 Ottobrunn, Germany, www.koenen.de

8. B. Böttge, Mechanische und Mikrostrukturelle Eigenschaften von Silizium-Lotglas-Silizium und SiliziumLotglas-Stahl Verbindungen, Master Thesis TU Bergakademie Freiberg, 2006. 9. R. Knechtel, Halbleiterwaferbondverbindungen mittels strukturierter Glaszwischenschichten zur Verkapselung oberﬂächenmikromechanischer Sensoren auf Waferebene, PhD-Thesis TUChemnitz, 2007, ISBN 3-89963-166-8.

Additional Reference Data Sheet Hybrid Microcircuit materials CN33-246 Low Temperature Silver Conductor, Ferro Electronic Materials, Rev 1200, http://www.ferro.com/

531

34

Chapter Thirty Four

Metallic Alloy Seal Bonding Dr. Wolfgang Reinert and Dr. Peter Merz Fraunhofer Institute for Silicon Technology ISIT, Itzehoe, Germany

34.1 Motivation

Long-term stability of seal Good to excellent moisture endurance Long shelf life of premanufactured cap wafers Although metallic alloy bonding comprises these outstanding characteristics, it is often considered difﬁcult to handle this technology on wafer-level due to limitations regarding wafer topography, intrinsic stress, and ﬂow control of surplus metal melt. The aim of this chapter is to indicate solutions to those shortcomings in order to enable a wider use of metallic seal bonding in future applications.

■ ■

Metallic alloy bonding uses an intermediate metal layer to solidly join two or more stacked components. The metal seal ring must primarily effect a high mechanical bond strength and a low gas or liquid media permeation. In addition, low-stress impact from the intermediate metallic layer is desired to avoid strained devices. The technology of metal seal bonding includes solder and eutectic bonding, thermo-compression bonding, solid diffusion bonding, and active metal bonding. A major driving force for the introduction of metallic alloy bonding for MEMS processing was the advantage of low processing temperature, below 450°C, such that common IC metals e.g. Aluminum could withstand this bonding process without degradation. It can be applied on wafer level as well as for single device encapsulation with premanufactured caps. This bonding technology has a number of interesting characteristics that are very beneﬁcial for high-quality and high-density device encapsulation on wafer-level: Medium to low bond temperature Excellent hermeticity Very low outgassing enables ﬁne vacuum High joint strength Narrow seal ring geometry Lead-free materials Moderate surface roughness requirements Low scratches and defect sensitivity Ohmic contact to cap enabling vertical electrical vias Process ﬂow compatibility with getter integration and activation ■ ■ ■ ■ ■ ■ ■ ■ ■

■

■

34.2 Properties of Metallic Seal Bonds All metallic seal bonding technologies have a driving force to a thermodynamically stable end condition in common, but in general the bonding process is stopped at a certain intermediate transition state. The transition process itself is thermodynamically driven by minimizing the Gibbs free energy of the system which involves contributions of mixing enthalpy, liqueﬁcation, and melting enthalpy, recrystallization enthalpy, volume enthalpy, and chemical potential. In general, the metal seal surfaces are geometrically transformed during the bonding process either due to elastic and plastic mechanical deformation or due to melting. This surface conversion process exposes fresh metal atoms for a reaction with a joining partner, reducing the negative effect of possible surface contaminations. Oxide layers break, organic contaminant ﬁlms may get dissolved, and topographies and scratches may be compensated and ﬁlled with joining material. This property enables an extended storage 533

Encapsulation of MEMS Components

PA R T V Diffusion bonding

Solder bonding

A

A

A

A

A

B

A A

ALiquid ALiquid

B

A

A

Eutectic bonding

A

A B

TLP bonding

A A

ABLiquid Eutectic

A A

ABEutectic

B B

BLiquid

A(+B)

Fig 34.1 ● Basic metallic alloy seal bonding types.

time of premanufactured cap and device wafers in nitrogen cabinets, compared to direct bonding. Depending on the metal layer thickness, a certain tolerance against particles in the seal frame area exists. Those particles either are pressed into the seal frame metallization or get embedded into the alloy formed during the seal bonding process. For active metal bonding, where a thin metal layer with a thickness of a few nanometers is used, this effect is not present. It is still good practice to remove any particles or organic contamination from wafer surfaces prior to the bonding operation, e.g., by RCA or Piranha cleaning procedures. Environmental regulations generate a growing interest in metallic seal bonding as almost all metallic bonding techniques are lead free. In comparison to this, glass frit wafer bonding is based on a 70 wt% lead containing glass frit, and no useful alternative low coefﬁcient of thermal expansion (CTE) glass chemistry without lead or bismuth is feasible up to now. The wide selection range of metallurgies and bonding techniques reduces the dependence on a supplier of critical materials, as the metal deposition technology is state-of-the-art and often available in-house. This makes cycle times, logistics, and communication much easier. In order to achieve a reliable package sealing against moisture and other environmental gases and liquids, a metal seal is known to be superior to other bonding techniques [1]. Both the solubility and the diffusivity are extremely low, and in general gas permeation effects 534

through the bulk of the seal frame can be neglected, even for lifetime requirements of more than 15 years. Still, the interaction with water or moisture is a sensitive issue in respect to long-term corrosion of the metallic seal frame or the adhesion-promoting layer below the seal frame. Care has to be taken for metal systems in order to avoid aggressive galvanic elements. The corrosion effect may also become even more serious due to intrinsic stress and large cathode areas within the seal frame, accelerating anodic metal solution.

34.3 Metal Systems for Seal Bonding Metal seal bonding may be classiﬁed according to the dominant phase composition and the correlated reaction kinetics. Four classes are relevant for technical demands: diffusion bonding, soft soldering, eutectic bonding, and transient liquid phase (TLP) bonding; see Figure 34.1. Other metallic bonding technologies, like hard soldering, may also be feasible but are excluded from this technology description due to the high bond temperatures above 450°C that make these joining metallurgies less attractive for MEMS encapsulation. Most of the metal seal bonding technologies require metal frames on both wafers, as shown in Figure 34.1. Eutectic AuSi bonding is the only method where only one joining partner requires a metal

Metallic Alloy Seal Bonding

frame. Here a cap wafer is manufactured with a gold ring metallization, and the MEMS wafer provides a silicon frame area for the metallurgical reaction. During diffusion bonding, two seal rings of highmelting-point metals are pressed together and a diffusion weld is generated. Solder bonding is performed with two low-melting-point solder frames that wet each other or with one solder frame that wets a solid metal surface. The solder volume in this case is large, and intermetallic phase formation has only a small effect. Eutectic bonding is performed either with two seal frames in eutectic composition or with two seal frames A and B that have eutectic composition when they alloy with each other. TLP bonding applies a thin reactive metal layer on at least one seal frame side that becomes consumed by intermetallic phase formation during the seal formation process. The metallic seal bonding technologies have different reliquiﬁcation properties when heated up again. TLP bonding has a much higher remelting temperature than the bond temperature due to the fact that the formed intermetallic phases in general have a high melting point. Eutectic bonding and solder bonding will remelt around or slightly above the sealing temperature. Diffusion bonding realizes a very high liquidus temperature, much above the bond temperature, but without any foreign alloying addition, as in the case of Au to Au or Cu to Cu diffusion bonding (also called thermocompression bonding). Table 34.1 gives the typical bond temperatures for different metal systems. In general, the need for a low bond temperature below 400°C to form a hermetic seal can be fulﬁlled with many metallic seal bonding technologies. While the process temperatures are still some 20–40°C higher than the liquidus temperature of the alloy formed to speed up the reaction kinetics, the peak temperatures of most processes are still tolerable. Especially low seal remelting temperatures, as in the case of soft soldering and AuIn bonding, may become problematic, if the devices are exposed to an SMT reﬂow process with a temperature in the range of 245–265°C. This may generate problems as the soft solder seal becomes liquid and loses hermeticity due to incoming air.

34.4 Soft Soldering Wafer bonding with soft solder is a very fast process, as the necessary bond temperature is low and the alloy is already formed. The solder wetting kinetics take place within seconds, so a hold time at peak bond temperature of a few minutes is sufﬁcient to secure a homogeneous temperature distribution over the wafer pair. The liquid melt wets the joining metal frame and forms a metallurgical bond. The solder ﬁlls nonplanarities and gaps,

CHAPTER 34

Table 34.1 Types of metal seal bonding and related typical peak process temperatures

Bonding technique

Types of metal seal bonding

Transient liquid phase bonding

CuSn to Cu

280

AgSn to Ag

250

AgIn to Ag

250

AuSn to Au

260

Eutectic bonding

Diffusion bonding

Soft soldering bonding

Ultra-thin metal ﬁlm

Metal system

Bond temperature (°C)

NiSn to Ni

300

AuIn to In

175

Au to Si

400

Au to SiGe

400

Au to Ge

400

Al to Ge

425

AuSn to Au

300

AuIn to Au

160

Au to Au

380

Cu to Cu

350

SnAg to Cu/Ni/Au

240

SnPb to Cu/Ni/Au

210

SnBi to Cu/Ni/Au

160

SiO2Ti to Si

400

thus reducing the need for high bond pressures. While cooling down, intrinsic mechanical stress in the soft solder is reduced by material creep. Since much liquid material is available that also does not solidify by intermetallic phase reaction, the bond pressure has to be carefully adjusted to limit melt being pressed out. After the bond is formed and cooled down it will have the same melting characteristics again when heated up for the next time. The bondline strength at elevated temperatures (e.g., SMD reﬂow) is very weak, and packaging stress may change the geometry of the seal in this state. The main solder alloy used today is SnAg. Solder alloy is applied by electroplating, stencil printing, or sputtering. According to Sparks, electroplating offers the best combination of solder thickness, uniformity, and hermeticity [2]. Stencil printing deposits solder paste (e.g., SnAg3.5 or SnAg3.5Cu0.5) on a structured metal seal frame with a subsequent reﬂow to form a solid solder alloy seal frame on top of a wettable metal frame. A print pattern as a line of open holes in the metal stencil is well suited. The amount of material deposited can be controlled mainly by the stencil thickness, the hole diameter, and the pitch of the 535

Encapsulation of MEMS Components

openings. After reﬂow in a nitrogen convection oven, ﬂux residues have to be cleaned off with care. It is often the case that solder accumulates at frame edges during the ﬁrst reﬂow. This effect causes solder squeeze-out, forming solder balls that may reduce the device yield. The metallic seal formed by soft soldering is hermetic, with reduced outgassing issues, although water, hydrogen, and oxygen outgassing was observed for solder sealed microcavities. The source of the outgassing could not clearly be identiﬁed. A getter integration will be very problematic because the high activation temperature of the getter is much above the bond temperature itself. Aggressive intermetallic phase growth will be the result, especially when the seal frame metal is electroless plated NiP/ﬂash Au. A sputtered NiV/Cu or electroplated Ni/Cu metallurgy is less affected by hightemperature process steps.

34.5 Eutectic Bonding During the eutectic wafer bonding, a eutectic alloy composition is generated, forming the seal. A eutectic alloy is a metal composition of two or more solid phases that precipitate at constant temperature from one uniform liquid phase. Those two or more phases are completely unsoluble in solid state. The eutectic point of a melt is the point at which the composition of the components is exactly in a state that both constituents solidify from the melt directly. This point lies below the melting point of the single alloy constituents due to crystallization hampering. For noneutectic composition of the melt, the overconcentrated constituent will solidify ﬁrst, still being embedded by liquid melt, until the eutectic composition of the remaining melt is reached. Finally, the rest of the melt solidiﬁes at the melting temperature of the eutectic. Thus eutectic wafer bonding takes advantage of the material properties of two joining partners to form a eutectic, which has a lower melting point than each of the joining partners themselves. Eutectic bonding on wafer level requires the compatibility of the joining partners or the joining metal layers and the tolerance of the device to the required bond temperature. The practical bond temperature is some tenth degree higher than the speciﬁc eutectic temperature. In larger industrial-scale applications, eutectic wafer bonding is based on two main gold alloys: Au97Si3 with a liquidus temperature of TL 363°C (see Figure 34.2) and Au80Sn20 with a liquidus temperature of 280°C. Other compositions, like Pd–Si or Al–Au, are known but have not found the same acceptance due to toohigh eutectic temperatures over 450°C and too-brittle joint layer. AuSi, AuSn, and AuGe eutectic joints are generally thermally and chemically stable and exhibit 536

a high mechanical yield strength without the tendency of whisker growth [3]. The necessary metal layers are deposited either as metal system or as multi-layer system, in each case with adhesion promoter (e.g., Ti, Cr, W) and often with metallic diffusion barrier (e.g., TiN, Pt, Ni). The metal layer will then be structured to form a closed seal frame or, if required, to form localized electrical contact spots within or outside the seal frame. The low melting point eutectic is formed during the wafer bonding due to diffusion of Si into the gold layer. The use of Au-Si eutectic for the hermetic sealing of surface micromachined sensors has the advantage that a metal ring is only required on one side. As one partner has to offer silicon for the joint, the MEMS component wafer has the active part. In this case the MEMS wafer can be manufactured in a CMOS compatible process ﬂow including a hydroﬂuoric acid (HF) release etch step. The cap wafer will be processed with a gold (ring) metallization. When joining two silicon wafers with AuSi, the seal-forming process can be realized with two different approaches. If the seal frame metal system on a cap wafer with adhesion promoter and diffusion barrier to the gold layer is applied, the eutectic forming reaction takes place only with the exposed silicon of the MEMS wafer. A SiO2 layer below the metal seal frame will prevent a reaction with the cap wafer even for very high temperatures and exposure times; see Figure 34.3.

1414°C

T

PA R T V

1064°C Liquid Liquid + (Si)

Liqu. + (Au) 363°C

E (Au) + (Si)

0

18,6

50

Au

%Si

100 Si

Concentration C in atom % — silicon

Fig 34.2 ● Phase diagram of the Au–Si system: 18.6 atom% Si in the AuSi-eutectic represent 3 wt% soluted Si.

Metallic Alloy Seal Bonding

The AuSi-wafer bond process is typically performed at around 400°C, achieving a high-fracture-strength joint in the range above 100 MPa [4, 5]. The eutectic AuSn-wafer bond process can be performed with a peak temperature around 300°C for 5 minutes. It is necessary to understand that the seal ring AuSn and Au will be pressed together and heated for just one time. This approach usually works very well, without troubles generated by intermetallic phase formation prior to seal forming. The metal system applied for AuSn bonding may be chosen with the accurate stoichiometry to achieve eutectic composition. In this case the metal deposition process tolerances will have a large effect on the eutectic composition. An alternative approach is a targeted gold surplus with a relatively thin Tin layer. This second approach can be grouped to TLP sealing processes, but has the beneﬁts that only a small amount of liquid melt is formed and that the seal bond line thickness changes geometry only little. Although the bondline thickness is generally in the range of some micrometers when electroformed seal

Cap

SiO2 Plated Au 3,2 μm

Adhesion promoter: 20 nm Ti Diffusion barrier: 30 nm Pt Plating base: 100 nm Au

AuSi eutectic Si SiO2 Device

Fig 34.3 ● Schematic layer construction with SiO2 diffusion barriers for controlled single-sided AuSi eutectic formation.

CHAPTER 34

frames are used, this joining method generates less intrinsic stress due to the smaller difference between solidiﬁcation temperature and operating temperature when compared with AuSi-bonding; see Figure 34.4. The process integration of the necessary AuSn metallization is more complicated, as both wafers have to be metallized with non-CMOS compliant metals (e.g. Au, Sn). Many materials, such as Ti used as adhesion promoter in the plating base metal system, are etched rapidly during the release etch of microstructured sensor details in HF to remove an oxide sacriﬁcial layer [6]. It is therefore necessary to check this underetching effect, especially in areas of high topography, and to provide wide enough seal ring geometries. The exposed tin layer will degrade in HF and is even removed in an RCA clean.

34.6 TLP Bonding TLP bonding creates a metallurgical seal by forming a thin liquid phase of one low melting component of the intermediate layer system. This liquid phase wets the metallic joining partner, thus compensating topographies. In a later state, the melt chemically solidiﬁes due to the formation of intermetallic compounds with other joining materials in the bond layer. TLP bonding combines the planarization capabilities of a solder process with the high melting temperature of a diffusion process to create an approach well suited for MEMS packaging [6]. The technology is a diffusion soldering process. Performed well, the formed metal seal is in a thermodynamically stable state with a remelting temperature much above the bond temperature; see Table 34.2. Some precautions during the wafer bonding step have to be taken because the low melting materials commonly used in this bond technique oxidize quickly.

Fig 34.4 ● AuSn solder bond (a) and AuSi eutectic bond (b). Detail of the joint layer shows massive gold penetration into the poly-Si bond layer.

537

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Encapsulation of MEMS Components

Table 34.2 TLP bond material combinations and their formation and post-bonding melting temperatures [7]

Metal system

Bonding process

Remelt temperature

CuSn to Cu

4 min at 280 °C

415 °C

AgSn to Ag

60 min at 250 °C

600 °C

AgIn to Ag

120 min at 175 °C

880 °C

AuIn to In

0.5 min at 200 °C

495 °C

NiSn to Ni

6 min at 300 °C

400 °C

AuSn to Au

15 min at 260 °C

278 °C

This effect can be reduced by bonding in nitrogen or, even better, in a vacuum; but a thin native oxide will always be present. The oxide layer may increase in thickness when a longer outgassing step of the loaded wafer pair is performed in the wafer bonder at high temperature to drive off any adhering water molecules, as the bond chamber background pressure still offers some oxygen together with water molecules that can accelerate an oxidation reaction. Evacuating the bond chamber and cyclic nitrogen purge will be helpful to dry and outgass the wafers before sealing the cavities. Outgassing below 150°C is recommended. The heatingup step to bond temperature should be performed as fast as possible to avoid premature intermetallic phase formation often seen on the frame with the low melting material. High bond forces that create compressive pressure on the seal rings in the range of 3–5 MPa are beneﬁcial to break the oxide layer during the bond step [7]. TLP bonding suffers from heavy melt outﬂow if thick melting layers are applied. The outﬂow will be most difﬁcult to control and will seriously affect the device yield. One way to reduce this effect is to provide a melting layer only on one joining partner ring metallization and to limit the layer thickness to below 1 μm, which, of course, reduces the planarization capabilities of this bond technology. If the layers are electroplated, this very thin layer may be challenging to manufacture, keeping in mind that also the plating base has to be removed from the wafer. The thickness of the melting layer is critical and must be under control over the entire wafer. Using thicker layers, TLP becomes a kind of soft soldering technique, as not all the melting material will become consumed and the effect of a high remelting temperature is not achieved. This effect is the more pronounced as time on peak bond temperature is reduced to increase wafer throughput. A way 538

to compensate for this is to further increase the peak bonding temperature or by applying higher bond forces to press out any remaining liquid material. Having unreacted low melting material in the bond can be detrimental at a later stage, when packaging stresses react on the cap during further processing steps at high temperature, e.g., SMD reﬂow soldering at 265°C peak. The micro package may suffer lateral shift of the cap relative to the sensor due to the weak seal joint in molten state. The base ring metallization reacts with the low melting point material, e.g., tin or indium. Those two metals are quite aggressive at high temperature. When choosing the thickness of the ring metallization, it is better to increase the thickness of the underlying metal or to use an additional diffusion barrier, e.g., nickel, to the adhesion promoter to avoid a reaction zone with tin or indium reaching the adhesion promoter layer. Stresses may be caused that increase the chance of delamination or increased moisture attack.

34.7 Diffusion Bonding Diffusion bonding generates a continuous metallurgical bond between two soft electroplated metals by solidstate diffusion without forming a liquid phase. The bond formed can be very strong and will have a high melting point much above the bond process temperature. Preferably Au-to-Au or, with some more effort, Cu-to-Cu is chosen as bond partner metallization, but the process should work also with other metals or even dissimilar metals as well. Gold has the beneﬁt not to oxidize and to remain soft, while copper is prone to oxidization and work hardening [8]. To achieve a high-quality bond, a few requirements have to be met. As for all diffusion-driven processes, high temperature accelerates the diffusion and usually a long bond time in the range of one to several hours is necessary. As no liquid phase is formed, a high bond pressure is required to ensure good contact between the two joining metals. Air gaps will impede the diffusion process, but also a contamination layer may act as diffusion barrier. Care has to be taken to present very clean and oxide-free surfaces. An ultraviolet-ozone clean will help to remove organic surface contaminants [9]. In the case of integrated getter thin ﬁlms, a mild wet chemical treatment will help to condition the getter and all exposed surfaces [4]. Argon plasma treatment may be helpful as well, but it is not recommended if ﬁne vacuum has to be achieved. Argon outgassing during the high bond temperature into the sealed cavity has been observed [10]. The bond time at peak temperature is reported to be in the range of a few minutes [9].

Metallic Alloy Seal Bonding 1) Oxide for hard mask 2) Front to backside lithography 3) Oxide opening 4) KOH etching

CHAPTER 34

Fig 34.5 ● Cap wafer process ﬂow for eutectic AuSi sealing.

5) Oxide for electrical isolation 6) Spray coating lithography 7) Plating base /diffusion barrier 8) Seal ring electroplating

9) Getter deposition

34.8 Ultra-Thin Metal Film Bonding Strong metal wafer bonding may also be achieved with very thin metal layers. In the metal bonding carried out by Yu et al. [11], a thermally oxidized Si wafer was covered with a 30 nm Ti layer and bonded to a de-oxidized silicon wafer. With a bond temperature of 400°C and pressure applied, a strong and nearly void-free wafer-towafer bond was demonstrated. The microstructure analysis of the intermediate bond region revealed that the stack is composed of a very thin layer of low-temperature titanium silicide and unreacted Ti in solid solution of Si and oxygen due to diffusion. Interdiffusion-assisted solid-phase reaction is believed to be responsible for the strong bonding obtained at low temperature. The mechanical interfacial strength between Si/Ti was observed to be stronger than SiO2/Ti.

34.9 Metallic Seal Ring Design and Process Technology A dedicated design and technology setup is needed for a high-quality and reliable metallic bond. Many aspects may inﬂuence the selection of a speciﬁc bond process. In general, the ﬁnal seal ring design is a trade-off between process integration and compatibility, restrictions to subsequent processing, stress and adhesion properties, costs, and environmental aspects. In Figure 34.5 a process ﬂow for the production of a cap wafer for eutectic gold silicon bonding is shown [12]. An oxide layer is used as electrical and chemical isolation to the device and cap wafer. Cavities are etched to the cap wafer by anisotropic etching (KOH, TMAH) or DRIE. Prior to electroplating an adequate plating base must be deposited. In general this plating consists of a multi-metal layer stack. A thin layer of Ti or

Cr is deposited by evaporation or sputter technology to achieve a good adhesion to silicon or oxide surfaces. Here a ﬁlm thickness of 10–50 nm is sufﬁcient. Since these metals may disturb the soldering or eutectic phase formation, a diffusion barrier layer is beneﬁcial. For this purpose Pt, Pd, or TiN layers with a thickness of up to 100 nm are suited. Finally, the actual plating base is deposited to allow higher plate currents in the subsequent electroplating process. Therefore, a thin gold layer is sputtered or evaporated; see Table 34.3. For the deﬁnition of the gold lines, a lithography step over the deep cavity topography is required. Here a dedicated spray coating process gives excellent conformal coating uniformity. For the electroplating of a thick gold layer, a fountain plater is recommended. Although the authors found the electroplated seal ring metallization on evaporated plating base to work extremely well, alternative metal layer deposition techniques may realize good results as well. Metal stacks can be sputtered or evaporated and patterned by a wet etch process or by lift-off processes. Table 34.3 lists a few metal systems that can be used for metallic seal bonds. While metal deposition on MEMS wafers may be restricted due to topography and process sequence (e.g., to avoid removal of metal from deep trenches), ASIC wafers will have different restrictions. As ASIC wafers are sensitive to radiation damage, deposition by evaporation may not be allowed because of radiation damage due to X-rays generated by the e-gun heater. In this case, sputter deposition may be the only alternative to directly deposit the seal frame or the plating base with an additional electroplated frame. The Argon working gas of the sputter process will become trapped in the deposited metal layers and will outgass at high temperatures above 350°C during the sealing process. This is a problem when targeting ﬁne vacuum inside the cavities using a high sealing temperature process (e.g., eutectic AuSi at 400°C, etc.). Residual cavity pressures as high as some mbar of Argon can be found in this case. 539

Encapsulation of MEMS Components

PA R T V

Table 34.3 Metal plating systems for seal frames

Deposition technology

Layer structure (nm) adhesion promoter/diff. barrier/bond layer

Comment

Evaporation

Si/Ti 20/Pt 100/Au 400

–for eut. AuSi

SiO2/Cr 10/Au 400

–for eut. AuSi

Si/Ti 20/Ni 100/Au 500/Sn 200

–for near eut. AuSn

Si/Ti 20/Ni 100/Ag 600/Sn 200

–for SnAg TLP

Si/Ti 20/TiN 60/Au 500

–for eut. AuSi

Si/TiW 20/NiV 200/Au 500

–for eut. AuSi

SiO2/Al 600/NiV 800/Cu 600 Sn

–for soft soldering

PB Cu 3000/Sn 1000

–for CuSn TLP

PB Au 3000/In 1000

–for AuIn TLP

PB Au 4000/Sn 2000

–for eut. AuSn

PB Au 3000

–for eut. AuSi

Sputtering

Electroplating

AuSi bond temperature cycle Outgassing 450

Activation

Bonding

T1

Cooling down T2

T1,T2 (°C)

400 350 300 250 200 150 0.30

1:00

1.30

2.00

Wafer bond cycle time (hours:minutes)

Fig 34.6 ● Exemplary wafer bond temperature–time proﬁle for AuSi eutectic bonding with getter activation.

Prior high-temperature outgassing of the wafers is not really effective to achieve ﬁne vacuum. A way to improve the situation is either to avoid sputtering or the use of an alternative higher-atomic-weight working gas that will outgass at much higher temperature.

34.10 Process Guidance of Metallic Alloy Bonding The eutectic AuSi vacuum wafer bond cycle with integrated getter can be characterized by four process phases. In the ﬁrst phase, the aligned wafer pair is loaded to the bond chamber and heated up to around 250°C for outgassing of absorbants without a premature getter activation and saturation; see Figure 34.6. The outgassing step is performed in vacuum for 30 minutes and may 540

be improved by one or two dry nitrogen purge cycles. The hot nitrogen atmosphere increases thermal coupling between the chucks and the wafer pair and dries the wafer surfaces. The outgassing step will help to use the getter capacity for vacuum lifetime enhancement in the vacuum package rather than for an initial vacuum generation. In the next step, the spacers between the wafer pair can be pulled, and the wafers are clamped with the upper chuck pressing the wafer pair ﬁrmly together. If required, a deﬁned damping atmosphere will be backﬁlled into the device cavities in this step, just before the wafers are pressed together. The temperature is now increased to a speciﬁed getter activation temperature, e.g., 350°C, that is still a little below the temperature of the eutectic point, and no eutectic formation will occur during this time. Depending on the required getter characteristics, an activation time

Metallic Alloy Seal Bonding

of 25 minutes may be sufﬁcient, keeping in mind that the activation will still proceed for the remaining bonding process. The temperature is thereafter increased to around 400°C as fast as possible. The eutectic forms a liquid phase within a short time. The peak temperature should still be held for some minutes to enable homogeneous temperature distribution over the wafer pair. The generated liquid eutectic is pressed out of the seal, and the joint line thickness becomes very thin, e.g., less than 0.5 μm. After the eutectic seal is formed the wafer pair is cooled down to the basic temperature of the chucks for loading operation. It is recommended to have the bond chamber evacuated until the eutectic is solidiﬁed. A nitrogen purge at 300°C may help to cool down the chucks faster. Heating and cooling rate, as well as temperature and force distribution, will be greatly inﬂuenced by the efﬁciency of the wafer bonder machine construction discussed in Chapter 37. The eutectic AuSn-wafer bond process can be realized, without any prior annealing process of the AuSnseal ring, with a peak temperature around 300°C. If only a hermetic seal with high pressure Argon backﬁll atmosphere is desired, the bond cycle setup can be quite simple. It is recommended to have the chuck temperature always above 150°C to speed up the bond process. Higher temperatures will also be possible without affecting the mechanical integrity of the wafer pair. The AuSn-seal must be kept below 200°C before heating up to peak temperature to avoid premature intermetallic phase formation. After wafer loading, the process cycle goes on with a short outgassing delay, Argon backﬁll is then initiated, and the wafers are pressed together by the heated chucks. The temperature is brought up as fast as possible to 300°C and held for 5 minutes, although the seal formation process requires less time. The cooling process can be performed with maximum cooling rate to achieve a higher process throughput. A typical process cycle time is around 45 minutes, depending on the machine capabilities. The major bond parameters impacting the bond quality and process duration are time settings, temperature, bond force, and heating/cooling rates. The programming of gas purge, vacuum, timing of spacer retraction, and upper chuck distance to wafer are regarded as less critical parameters. The total time of this exemplary eutectic wafer bonding process is about 2 hours. The long duration caused by extensive outgassing and getter activation time limits the productivity of the wafer bonder considerably. A different process methodology may be more helpful to increase the productivity of the wafer bonder. With a shorter outgassing phase of only some minutes, higher loading/unloading temperature, and a post-bond getter activation in an external batch oven, the total bond cycle may be shortened to around 1 hour. The time on

CHAPTER 34

peak bond temperature is a particularly critical parameter that will inﬂuence the local stress distribution in the seal. Extended joining times (time on peak temperature) will increase the gold diffusion into Si, especially poly-Si. This effect can signiﬁcantly change the microstructure of the silicon, causing intrinsic stress that either causes temperature bias offsets or even limits the lifetime of the device. A second effect caused by too-long joining time may be a change of sensor characteristics due to annealing. This should be checked in every speciﬁc case. Temperature has a large impact on the metallurgical reaction kinetics. While the formation of the eutectic composition is possible at exactly the eutectic temperature, the authors do not recommend being too close to this point. Potential surface contaminations will have a large impact on the joint formation. A somewhat higher process temperature accelerates the reaction kinetics and compensates for surface contaminations that may hamper the eutectic formation. Overtemperature will thus help to increase the bond yield and joint homogeneity over a full wafer. It is necessary to calibrate the chuck temperature and to investigate the temperature homogeneity over the wafer, using a multi-channel (e.g., 18 channels) temperature probing wafer. This test gives a ﬁrst impression of the tool capabilities, but temperature distribution may be different when the wafer pair is pressed together very hard. Based on this measured temperature, the bond proﬁle will be programmed. Offsets that are often in the range of more than 10°C can be compensated so that the coolest point on the chuck will be heated up above the desired peak temperature. Heating and cooling rates not only inﬂuence the cycle duration but also impact the bond quality. During fast heating steps, careful temperature monitoring is required to detect temperature overshooting due to nonoptimized control parameters of the wafer bonder. A high cooling rate can help to limit the peak temperature duration and control the outﬂow of surplus eutectic melt or at least limit the lateral wetting length. The cooling rate after eutectic solidiﬁcation was not found to be critical in terms of reliability. The chemical surface condition of the exposed SiMEMS wafer is a parameter that affects the bond quality very seriously. The reaction kinetic of the eutectic formation process is inﬂuenced in the presence of a native oxide layer. Even a thin silicon oxide layer of some nanometer thickness is a very efﬁcient diffusion barrier preventing the diffusion of silicon into gold. Depending on the type of release etch process and utilized chemistry, the exposed Si surface may be more or less prone to oxidation during wafer storage. It is good advice to monitor the storage time between release etch and wafer bonding carefully and correlate this delay time with seal reliability ﬁndings. 541

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References 1. R.K. Traeger, IEEE transactions on parts, Hybrids Packaging PHP-13 1977. 2. D. Sparks, G. Queen, R. Weston, G. Woodward, M. Putty, L. Jordan, S. Zarabadi, K. Jayakar, Wafer-towafer bonding of nonplanarized MEMS surfaces using solder, J. Micromech. Microeng. 11 (2001) 630–634. 3. J.Y. Tsai, C.W. Chang, Y.C. Shieh, Y.C. Hu, C.R. Kao, Controlling the micro-structures from the gold–tin reaction, J. Elect. Mater. 34 (2005) 182–187. 4. W. Reinert, High vacuum wafer bonding technology, AuSi eutectic wafer bonding with integrated getter thin ﬁlm for long term stable high

542

5. 6.

7.

8.

vacuum, in: Spezialausgabe über Wafer Bond Technologie, 2005. M.J. Madou, Fundamentals of Microfabrication, CRC Press, 2002. W.C. Welch III, J. Chae, K. Najaﬁ, Transfer of metal MEMS packages using a wafer-level solder transfer technique, IEEE Trans. Adv. Packag. 28 (2005) 643–649. W.C. Welch, K. Najaﬁ, Nickel–tin transient liquid phase (TLP) wafer bonding for MEMS vacuum packaging, presented at Transducers & Eurosensors, Lyon, 2007. S.M. Spearing, C.H. Tsau, M.A. Schmidt, Gold thermocompression wafer bonding, Massachusetts Institute of Technology, Cambridge, MA, 2005.

9. M.A. Schmidt, Wafer-to-Wafer Bonding for Microstructure Formation, 1998. 10. W. Reinert, Neon Ultra-Feinlecktest zur Vorhersage der Vakuumerhaltung resonanter Mikrosensoren, Technische Fakultät, Christian-AlbrechtsUniversität, 2007. 11. J. Yu, J.J. McMahon, J.Q. Lu, R.J. Gutmann, 200mm Silicon Waferto-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions, 2005. 12. P. Merz, W. Reinert, K. Reimer, B. Wagner, PSM-X2: Polysilicon surface micromachining process platform for vacuum-packaged sensors, in: Konferenzband Mikrosystemtechnik-Kongress 2005, D/Freiburg, VDE Verlag, pp. 467–470.

35

Chapter Thirty Five

Bonding of CMOS Processed Wafers Roy Knechtel X-FAB Semiconductor Foundries AG, Erfurt, Germany

Wafer bonding at the end of the wafer processing is a common method in MEMS fabrication, where a kind of wafer level assembly is performed by mounting protective caps over the mechanically sensitive MEMS structures. This seals the functional cavities, to stabilize chips or to apply other functional elements such as optical windows (Figure 35.1). Very often at least one of the wafers to be bonded has been processed by CMOS1 technology, either fully as an ASIC wafer, partially as a discrete MEMS sensor wafer, or additionally as an integrated MEMS sensor wafer. This chapter describes the special bonding processes and conditions required for bonding these types of highly sophisticated, processed CMOS wafers. In addition, by wafer bonding at the end of wafer processing, wafer level integration is possible if functional elements are mounted by the bonding process. Such functional elements might be signal condition ASIC’s for MEMS structures which simultaneously are used as protective and sealing caps, caps with a rewiring layer for ﬂip chip bonding, or counter electrodes for capacitive sensors or EMV shielded caps. In all these cases, not only is mechanical wafer bonding required to assemble the essential cap structure, but also electrical contacting between the bonded wafers in order to obtain real system integration within the bonded stack. This kind of electrical contacting between the bonded wafers can be realized simultaneously in the wafer bonding process, e.g., by using a conductive glass frit for contacts in standard (nonconductive) glass frit bonding [1] or

by pressing on contacts realized in anodic bonding by using the very high bond surface energy as a contact force [2]. However, it is also possible to ﬁrst bond the wafers mechanically, and then perform the contacting by classical wire bonding [3] or metal deposition and photochemical structuring. Figure 35.2 gives a short overview on system integration through wafer bonding, to illustrate the requirement of bonding of CMOS processed wafers. Discussion of the contacting technologies is not the topic of this chapter and would overload it. In this chapter the special aspects, requirements, and limitations of the bonding, i.e., of the mechanical joining of CMOS processed wafers, are introduced.

35.1 General Aspects, Requirements, and Limitations of CMOS-Compatible Wafer Bonding CMOS processed wafers in the context of this chapter are wafers which have been processed in a complete or modiﬁed CMOS process, and normally contain electrical elements such as transistors, resistors, and capacitors made by implantations, insulation, and metal layers. The ﬁnal layer is mainly a passivation which is opened up at the bond pad areas to allow contacting of the last metal layer by wire or ball bonding. If a complete CMOS process is used, IC’s such as ASIC’s will be present on the

1

CMOS Complementary Metal-Oxide-Semiconductor. CMOS technology is the main class of process for the production of standard and application-speciﬁc integrated circuits (ASICS). CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog and mixed signal circuits, such as image sensors, (sensor) data converters, and highly integrated transceivers for many types of communication.

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light

Protective MEMS capping

MEMS chip stabilization relative pressure sensor

MEMS cavity sealing absolute pressure sensor

Optical window application

Figure 35.1 ● Wafer bonding applications at the end of MEMS wafer process.

System integration by wafer bonding and metal line/bond wire wafer-to-wafer contacting

Cap contacting by bond wires, re-wiring at cap and flip chip bumps [3]

Conductive glass frit contact

Figure 35.2 ● Examples of wafer level integration and wafer-to-wafer contacts by wafer bonding.

wafers and may exist together with lateral integrated MEMS sensors (e.g., integrated pressure sensors). Alternatively, a reduced or modiﬁed CMOS process in combination with micromachining will result in MEMS sensors using some layers of the CMOS process (implantation, wiring at discrete pressure sensors, for example). In both cases, the limitations and requirements for wafer bonding of the processed wafers are the same. During the bonding step itself, as well as during the pretreatment before bonding and during the potential bond annealing, the already processed CMOS or CMOS-like structures on the wafers must not have their characteristics, quality, and reliability inﬂuenced. CMOS IC’s are very complex, critical systems, with designs based on well-characterized, modeled primitive devices and IP blocks which are collected in technology-based libraries for design tools. Any change in the characteristics of any primitive device or IP block would require a recharacterization and a model update to ensure the performance of the library, optimal designs, and functions of the ﬁnal devices. Therefore, any post-processing of CMOS processed wafers, micromachining or wafer bonding, must not change the characteristics of the CMOS elements. To ensure this, the following points must be considered: ●

●

The maximum temperature, even for short processes must be limited to 450°C to prevent any unwanted alloying and structural changes in the aluminum metallization. The total thermal-time budget, even for lowtemperature processes (200–400°C) must be minimized to prevent diffusion-based changes in the CMOS structures, such as changes in doping proﬁles or metal degradation. 544

●

●

●

●

●

●

Aggressive acid-based wet chemical treatment for bonding activation, such as used for typical cleaning, is prohibited, because this would attack open metal areas. Electrical discharges during bonding (anodic bonding) or during plasma pretreatment prior to bonding must be avoided. The bonding process must prevent the trapping of charges in or close to the bonding interface, which can change the charge characteristics of the CMOS devices. The bonding process must not introduce mobile ions (sodium, potassium, gold, etc.) into the CMOS structures. (In particular, the gate oxide is critical.) The bonding must not change the mechanical stress characteristics of the active CMOS layers; this is especially important for the matching behavior of symmetric circuitries. The bonding must not introduce any parasitic effects such as parasitic capacitances, high ohmic leakage current paths, or shorts to the ICs.

Finally, all the demands to ensure no changes in the CMOS characteristics require adaptation of the known bonding processes, or at least tests to check that there are no negative inﬂuences on the circuitry. Some bonding processes such as high-temperature direct or fusion bonding, as established in SOI wafer manufacturing, categorically cannot be used for CMOS wafer bonding (aggressive activation, annealing temperature too high). Others, such as gold-based metal bonding, are very critical due to the risk of ionic contamination of the CMOS wafers or CMOS processing equipment.

Bonding of CMOS Processed Wafers

In the following, some examples are shown of how CMOS wafers can be bonded and how it can be proven that the bonding does not inﬂuence the behavior of the CMOS structures.

35.2 CMOS-Compatible Low-Temperature Wafer Bonding As already mentioned, the classical high-temperature direct or fusion bonding (Chapter 31) is not suitable for processed CMOS wafers because the aggressive acid-based activation as well as the 1000°C annealing for bond strengthening after prebonding would destroy the CMOS structures. To circumvent this, CMOScompatible low-temperature direct wafer bonding technologies have been developed [4, 5]. In these processes, the aggressive wet chemical surface activation was replaced by plasma activation. For the plasma generation, a different kind of gas to those normally available in clean rooms, such as O2 (preferred and mostly used gas) can be used, and also CO2, N2, or HNO3. The plasma creates free radicals at the bonding surface on which hydroxyl-groups are attracted either by rinsing in DI water or just from the air humidity. During the mechanical prebonding by pressing two activated bonding surfaces together in a controlled atmosphere such as vacuum, these hydroxyl groups are linked together to form a semi-stable bond which can be hardened to the strength of crystalline silicon by annealing at temperatures of between 200°C and 400°C. The higher the annealing temperature, the shorter can be the annealing time, but at 400°C at least 2 hours are recommended. Thus, ﬁnally, the thermal budget is more or less ﬁxed, but the annealing temperature can be chosen within the low-temperature range. This low-temperature bonding process is fully CMOS-compatible, since it is based only on plasma activation, which can be done at fairly soft plasma conditions (low power, short time) in commonly used barrel etchers or also in etching chambers with single wafer chucking in which the chuck protects the nonactivated wafer side. This allows us to achieve plasma activation without inﬂuencing the CMOS structures. DIwater rinsing is helpful for the activation, but as already mentioned, not really required, so that the plasma activation is also an option for freely moveable MEMS structures which must not come in contact with water with respect to sticking issues. In addition, the annealing temperature–time relationship offers a wide range in order to ﬁnd the optimum annealing conditions. Even if the described CMOS-compatible activation, bonding, and annealing process sequence is very reproducible in practice, the main prerequirement is that the surfaces are bondable, which means they have to be ﬂat (low wafer bow, no elevated structures in the bond

CHAPTER 35

areas), clean (free of particles and process residuals), and smooth. This means a ﬁnal well-polished surface with a remaining roughness of very few nm, which can be best proven by performing a bonding test. Unfortunately, this type of high-quality surface is not typical for processed CMOS wafers. On the front side, the topography of the structured CMOS layer typically does not provide ﬂat bonding areas in the range of some hundred μm which are required as bonding areas, and even if this size of area could be realized, it would normally have too high a microroughness due to various plasma processes (CVD layer deposition, plasma etching), so that the surface is not bondable. The back side of CMOS wafers is normally only lapped as a result of the raw wafer process, not polished, and so is not direct bondable. Additionally, the back side is usually damaged by wafer handling and chucking. Therefore, before doing any direct bonding of CMOS-processed wafers, chemical mechanical polishing (CMP) of the bonding surface is necessary in most cases. This abrasive process planarizes the structured layer proﬁles and results in well-polished surfaces which can be efﬁciently bonded. The CMP should be done directly before bonding. Another option for bonded surfaces is to cover the initially polished surfaces—for example, a polished wafer back side—with a few micrometers thickness of inorganic layers such as silicon dioxide or nitride, which can withstand the CMOS process and provide sufﬁcient protection of the bonding surface against mechanical damage. Just before bonding, this protective layer must be removed, preferably by wet chemical etching, to prevent any damage of the bonding surface during stripping. Then ﬁnally, these kinds of surface can be bonded very efﬁciently. CMOS-compatible low-temperature wafer bonding is an attractive process if the bond surfaces can be protected during the CMOS wafer processing or can be freshly polished before bonding. The bonding process, including the plasma activation and annealing, is very reproducible and quite cost efﬁcient because the prebonding as a single wafer process is fast (room temperature) and the activation and annealing can be done as batch processes. Figure 35.3 shows some examples of this bonding process from the ﬁeld of silicon MEMS pressure sensors.

35.3 Anodic Bonding of CMOS-Processed Wafers The anodic bonding of silicon wafers to sodium-containing glass wafers with thermal expansion close to silicon (e.g., Schott Boroﬂoat 33, Hoya SD2 or Corning Pyrex #7740) is based on the ionic drift of the sodium ions at increased temperature (300–450°C) in a high-voltage ﬁeld (about 1000 V or higher). This ionic drift effects a depletion zone at the bonding interface on which a 545

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IR-image

Diced discrete absolute pressure sensor chip

IR-image

Bond defect

Bonded stack of discrete absolute pressure sensors, back side cavity sealing by unstructured silicon wafer, sensor wafer back side protected by oxide nitride layer in CMOS process

IR-images Diced discrete relative pressure sensor with direct bonded silicon base wafer with powder blasted holes in it, base wafer during powder blasting protected by oxide layer

Bonded stack of CMOS integrated absolute pressure sensors, back side cavity sealing by unstructured silicon wafer, sensor wafer back side polished by CMP after CMOS process

Figure 35.3 ● Example of the usage of CMOS compatible low-temperature semiconductor direct bonding.

high-voltage drop down presses the wafers strongly together. Simultaneously, oxygen ions drift in the glass to the bonding interface. Finally, a very strong bond is formed by anodic oxidation (see Chapter 32). This bonding process provides several challenges to allow it to be used for bonding processed CMOS wafers, as discussed in the following: Mobile Ion Contamination: The glass must necessarily contain sodium ions, which become mobile during the bonding process, and a signiﬁcant portion of these is removed from the glass at the outer side of the glass wafer where it contacts the electrodes of the bonding equipment. If these mobile ions reach the CMOS circuitry, they will degrade the insulation behavior of the gate oxide of the MOS transistors and alter their characteristics. In particular, these mobile ions are extremely critical for EEPROM cells which have to store charges for a very long period, which is only possible with a very good insulation gate oxide free of any mobile ions. Therefore, special passivation is recommended if anodic bonding is to be done at the active front side of CMOS processed wafers or comparable MEMS wafers. The passivation should consist of a gettering layer for mobile ions, such as a Boron-PhosphorusSilicate-Glass-Layer (from a plasma CVD process), a blocking layer for the mobile ions, such as silicon nitride, and an efﬁciently bondable ﬁnal layer (e.g., a CVD silicon oxide) [6]. The blocking layer prevents the drift of mobile ions to the critical structures in all cases such as wafer handling, bonding, testing, dicing, and so on. The gettering layer can ﬁx any mobile ions which cross the blocking layer, while very good, reproducible bonding can be achieved at the efﬁciently bondable ﬁnal layer of the passivation. 546

With this passivation layer stack, CMOS structures can be protected well during anodic bonding. Further details on the ionic inﬂuences of anodic bonding can be found in [7]. Charge Effects: During anodic bonding, a depletion zone is formed in the bonded glass close to the bonding interface, which is free of mobile ions at the bonding temperature. However, ﬁxed charges in this zone can inﬂuence the ﬁeld transistors under the glass and passivation. The inﬂuence of these ﬁxed charges is not well investigated, but it is known that a short anneal (several minutes at around 400°C) of the bonded layers can balance the charges in the bonding depletion zone, and as a result of this, good CMOS parameters can be attained also after anodic bonding. Voltage Effects: Since a high voltage, typically in the range of 1000–2000 V, is required for anodic bonding, electrical structures can be damaged during bonding. The anodic bonding of the back side of CMOS wafers is uncritical because almost all of the bonding voltage drops at the bonding interface (the gap between the wafers to bond or at the depletion zone) and currents do not really ﬂow, but only charges are moved. More critical is anodic bonding at the front side of CMOS wafers, where the voltage drop is near the electrical structures and can damage these, even if, in particular, pn-junctions are ﬂooded with thermally generated charge carriers at the bonding temperatures. To protect the electrical structures it is recommended not to apply the bonding voltage at the back side of the CMOS wafers, but close to the bonding interface by contacting the ground, for example, to the last metal layer (special contacts at bonding ﬁxtures

Bonding of CMOS Processed Wafers

Side view diced anodic bonded integrated pressure sensor chip with glass base

Silicon

IC

12

Optimal voltage and current characteristic without any spikes for anodic bonding of sensitive wafers

Volt Current

800 400

8 4

0 –400

0

500

Bond current (mA)

Anodic bonded glass base wafers with powder blasted holes at the back side of integrated relative pressure sensors

Anodic bonding IRPS (Glass wafers with hole) 1200

Bond voltage [V]

Glass

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1000

1500

0 2000 –4 –8

–800

–12

–1200 Time (sec)

Figure 35.4 ● Examples of anodic bonding CMOS processed wafers.

and a recess in the glass wafer are required). By this, and by using special designs, the bonding areas can be contacted directly, and the bond voltage will not drop over the sensitive CMOS structures. Even though this method requires some effort, it provides very good protection and at the moment appears to be the only safe way to perform anodic bonding at the front side of CMOS wafers. Discharging Effects: During anodic bonding, discharges of the high bonding voltage must be prevented, because they would damage the electrical structures by uncontrolled local currents. The key to preventing this type of discharge is the design. Small gaps and overhangings should not be included in the design, or this kind of critical feature should be grounded. During processing, overhanging of the wafer edges or of electrode wafers must be prevented as typical discharging geometries. The bonding should be done at atmospheric pressure or under high vacuum, since at medium pressures (plasma conditions) discharges are much more probable. If perforated glass wafers have to be anodically bonded, metallized glass electrodes should be used instead of metal electrodes. A depletion zone also occurs at the glass electrodes and prevents discharges in the perforations. Because the spikes in the voltage– current diagram indicate discharges, it can be easily checked whether the bonding process is free of discharges as required. Stress Effects: The joining of dissimilar materials such as glass and silicon by anodic bonding induces mechanical stress into the stack, which can inﬂuence the electrical parameters. Even if the thermal expansion of the glasses used for anodic bonding is close to that of silicon, the thermal mismatch of both materials is not zero and depends on the temperature [8]. Therefore, it is recommended to perform the anodic bonding at a temperature of

around 300°C, where the thermal mismatch during bonding, as well as after cooling, is very low. These examples have shown that the anodic bonding of CMOS wafers is very difﬁcult, but it is possible to achieve if all protective actions are carried out. It is also worth making this effort, because anodic bonding is a very safe, reproducible process, providing hermetic, strong bonds with long-term stability. Figure 35.4 shows examples of the anodic bonding of CMOS wafers.

35.4 CMOS Wafer Glass Frit Bonding In Chapter 33, glass frit bonding was introduced as a universal bonding process for silicon based micromachining, but this bonding technique is also CMOS compatible and very well suited for bonding processed CMOS wafers. The bonding temperature of 430–450°C is rather high but is still under the limit for CMOS wafers, and a time of just a few minutes is needed at this temperature. The screen printing and thermal conditioning of the glass paste can normally be done on the less critical wafer, but even if required for any reason, both can also be carried out on the CMOS wafer, because screen printing does not damage the passivation, and also the additional thermal budget from the glass frit conditioning (binder burn out, glass premelting) is not critical for the CMOS circuitry, as described later. The glass frit has an excellent wetting behavior for any typical microsystem technology layer, as shown in Figure 33.20, so will planarize any surface topography of the CMOS layers up to about 7 μm, while surface roughness is also not relevant. Because the glass frit comprises mainly lead silicate glass, no ionic contamination problems are expected. To investigate possible inﬂuences, such as stress, temperature, or ionic effects, of the glass frit on the CMOS 547

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Encapsulation of MEMS Components Glass frit on test inserts Slight influence of the glass frit on the slope of lowvoltage p-channel transistors

Glass frit Probe Pads

Glass frit structures printed on a completely processed CMOS wafer for investigation of influences of the glass frit on the CMOS parameters

Most CMOS parameters without any influence of glass frit, as shown in this map of leakage current

Figure 35.5 ● Results of testing inﬂuence of glass frit on CMOS structures.

structures, wafers with blocks of many test structures, such as different transistors, resistors, and capacitors, from 0.6 μm CMOS technology were screen printed with glass frit. The screen printing was done on top of the standard passivation in such a way that the test structures were covered with glass frit, but the contact pads were left free to allow measurement of the glass frit after thermal conditioning and bonding process simulation. Every second test structure block in both directions on the wafer was covered by glass frit, while the others were left blank (Figure 35.5). From this chess-ﬁeld-like structure it was possible to compare the parameters of the same, locally neighbored CMOS structures with and without glass frit. In Figure 35.5, two wafer map examples are shown to illustrate typical measurement results. The leakage current map did not show any inﬂuence of the glass frit. This indicates that neither the stress of the glass frit nor the ions in the glass frit cause leakage currents in the CMOS transistors. This map was typical for almost all of the measurements, but for a few parameters a clear inﬂuence of the glass frit was found in the wafer maps, such as in the slope of a low-voltage p-channel MOS transistor which is also shown in the same ﬁgure. The chess-ﬁeld-like pattern in the parameter map (areaproportional boxes for the measurement position for the parameter) indicates that the slope is higher if this transistor is covered by glass frit. However, for this parameter, as well as in all the other cases where the inﬂuence of the glass frit was found, the differences in the parameters of structures with and without glass frit was very low, mostly less than 10% of the parameter speciﬁcation range; so the inﬂuence of the glass frit can be concluded to be negligible because it is lower than the differences in the values of two different wafers. 548

Another aspect of glass frit bonding with a possible negative inﬂuence on the electrical parameters of CMOS wafers are elemental lead precipitations. These precipitations are related to the glass chemistry of the bonding process. When, for example, silicon is bonded with glass frit, the silicon surface is oxidized by a redox-reaction, in which the lead glass is reduced to elemental lead, forming lead balls. These lead balls can further grow at increased temperature (size up to 2 μm in diameter), and ﬁnally form conductive paths for leakage currents or can reduce the breakthrough voltage (Figure 35.6). Even if the occurrence and growth of the lead precipitates can be managed by the thermal budget of the glass frit, since the lower the temperature–time load of the glass, the lower the possibility for critical lead precipitates, it is strongly recommended that the glass frit be kept away from conductive layers (metal, silicon, polysilicon) which are active in the electronics. For CMOS wafers, the glass frit bonding should always be done on the passivation, and it must be considered that a few hundred nanometers of this will be solved in the glass frit. In summary, it can be concluded that the glass frit method is well suited to the bonding of CMOS-processed wafers and does not have any critical inﬂuence on the CMOS structures through mechanical stress, mobile ions, or the process temperature budget if the bonding is done on sufﬁcient passivation and the glass frit is kept away from the open, electrically active elements such as bond pads. In Figure 35.7, some examples of CMOS wafers with glass frit bonded optical widows and caps are shown. The critical feature during glass frit bonding was rather the area consumption of the glass frit bond frame (150…200 μm in width), but not an inﬂuence

Bonding of CMOS Processed Wafers

Critical lead precipitates in glass frit close to lead-through lines, which effects reduced breakthrough voltage and leakage currents at the leadthroughs

Prevention of critical lead precipitates in the same configuration by reduced thermal budget in the glass frit processing

CHAPTER 35

Detailed view and dimensions of balllike lead precipitates in the interface of silicon glass frit which can influence the insulation behavior of the glass

Figure 35.6 ● Lead precipitation behavior of glass frit.

3D SEM view at optical glass windows bonded by glass frit wafer bonding on top of CMOS wafer with ICs for UVapplications

Optical image of an optical window showing the window and the glass frit bond frame as well as the CMOS structures

Thin silicon cap bonded using glass frit onto a CMOS wafer with integrated micro-thermal MEMS devices for protection of freestanding structures

Figure 35.7 ● Examples of glass frit bonded wafers with CMOS, optical, and MEMS structures.

of the CMOS parameters, so that in all cases, the CMOS structures were fully functional after the glass frit bonding.

35.5 Adhesive Bonding of CMOS Wafers Adhesive wafer bonding based on organic adhesives— such as polyimides, polymers, or resists such as SU8—as a joining interlayer between the wafers to be bonded [9] is very probably the most suitable bonding technology for CMOS wafers. The more or less soft adhesive acts as an active bonding agent already at room temperature and planarizes the topography of the CMOS up to about 75% of its thickness. To cure and harden the adhesives, only

low temperatures (50–200°C) or some UV-light (adhesive glass wafer bonding) are required. Due to the remaining softness of the adhesives, the stress introduced into the bonded stack is fairly low, and ionic contamination from the adhesives is not expected. Overall, the inﬂuence of the adhesive bonding on CMOS structures is negligible, and the bonding strength is normally sufﬁcient. The main disadvantage of adhesive bonding is the outgassing behavior. During curing of the adhesive, organic gasses (mostly solvents) are released, not only into the environment but also into cavities sealed by the bonding. There they can change the working atmosphere (cavity pressure) or can cause corrosion. While this outgassing issue can be managed by thermo-compressive bonding of fully cured adhesives (SU8), all organic adhesives are ultimately sensitive to humidity, their properties change as a result of water absorption, and they are not 549

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hermetic, so that gasses and moisture can diffuse through the bond frame into sealed cavities. Sealing the organic adhesives in the bonding interface by thin metal layers appears to be possible [8], but requires a high processing effort. For these hermeticity and stability reasons, adhesive bonding is not widely used for MEMS structure capping in high-performance and safety-relevant applications. Nevertheless, if hermeticity and long-term stability are not really required (e.g., optical windows, disposables), adhesive bonding may be the safest and easiest way to bond processed CMOS wafers without any inﬂuence on the electrical parameters.

35.6 Conclusions The bonding of fully processed CMOS wafers is a challenge because many requirements must be fulﬁlled in order to avoid inﬂuencing the electrical structures and circuitry. However, it has been shown for different bonding processes that it is possible to achieve if the process physics and chemistry are well known. The discussions in this chapter are only examples, and for each case of bonding CMOS wafers it should be examined how the process can be optimally carried out to prevent any inﬂuence on the CMOS wafer parameters.

References 1. R. Knechtel, Wafer to wafer 3Dintegration using conductive glass frit bonding, in: Proceedings Conference Smart Systems Integration , Paris, France, March 27–28, 2007. 2. Z. Kádár, Integrated Resonant Magnetic Field Sensors, PhD Thesis 1997, Delft University, Delft University Press ISBN 90-4071411-8. 3. J. Frömel, M. Wiemer, T. Gessner, AVT als Basis erfolgreicher MEMS-Kommerzialisierung, J. Mikroproduktion 01/2007, Carl-Hanser Verlag, München, pp. 10–14.

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4. A. Berthold, Low-temperature waferto-wafer bonding for microchemical systems, PhD Thesis Technical University Delft 2001, ISBN 9075095-78-3. 5. M. Reiche, M. Wiegand, V. Dragoi, Plasma activation for low-temperature wafer direct bonding, in: 5th International ECS Symposium on Wafer Bonding: Science, Honolulu: Technology and Application, 1999. 6. Patent EP000001270507A2, Passivation of anodic bonding regions in micromechanical systems.

7. K. Schjølberg-Henriksen, Degradation of SiO2 caused by anodic and plasma activated wafer bonding, PhD Thesis, SINTEF ICT, Blindern, Oslo, Norway, 2003. 8. M. Harz, H. Engelke, Curvature changing or ﬂattening of anodically bonded silicon and borosilicate glass, Sens. Actuators A55 (1996) 201–209. 9. F. Nicklaus, Adhesive wafer bonding for microelectronic and systems, Royal Institute of Technology Stockholm Sweden, PhD Thesis, 2002, ISSN 0281-2878, Universitetsservice US AB.

36

Chapter Thirty Six Non-destructive Bond Strength Testing of Anodic Bonded Wafers Roy Knechtel X-FAB Semiconductor Foundries AG, Erfurt, Germany

Bonding strength and, related to this, hermeticity are the main quality aspects in wafer bonding. This is also true for anodic bonding, which is widely used because it is normally a very robust and reproducible process. The anodic bond in most cases is very strong, and due to the different elastic properties of glass and silicon (Young’s Modulus, Poisson ratio) pull testing and crack propagation tests are almost impossible to perform.1 However, here also process inﬂuences, such as surface roughness, residuals of previous processing steps, aging of the electrodes due to the sodium in the glass wafers, or cracks in the glass, can lower the bonding strength locally or across a complete wafer. In order to detect this, a test structure is introduced here, which allows inline evaluation of the quality of an anodic bonding interface in terms of surface energy, as a standard test on every wafer during production processing [1]. This is based on the creation of small non-bonded areas in the vicinity of small steps in the bonding interface. Using Finite Element Analysis (FEA) simulations, it was possible to calculate the surface energy of the monitored bonding processes.

36.1 Testing Principle From practical experience it is known that non-bonded areas occur in the bonding interface around elevated structures, such as particle contamination or surface steps from wafer processing. In accordance with the Maszara blade test [4] and bond-test structures using deep-etched

steps [5] it was found that the size of the non-bonded area correlates with the surface energy of the bonding interface, depending only on ﬁxed known wafer parameters such as the structure height, the wafer thickness, and the Young’s Modulus. Since these non-bonded areas can be investigated or measured very easily, test structures have been designed to use this effect for bonding strength measurement. In order to integrate the test structures into complex microsystem technologies, existing layer thicknesses have to be used to create the steps. In the ﬁrst approach, 100 100 μm steps were formed using a 1-μm thick aluminum layer on top of the silicon wafer. To prevent plastic deformation of the step during bonding, it was covered with a hard, 500-nm thick silicon nitride passivation layer, as well as the bonding area itself. The steps led to non-bonded areas in the vicinity of the step, as shown in Figure 36.1a, which were then measured under a microscope to evaluate the bonding surface energy. In the second approach, 150-nm-high steps were formed using a metal layer on the glass wafer as a series of multiple steps. Standard lithographic techniques were applied in order to form a row of 100-μmlong 25-μm-wide lines. The spacing between the lines was varied between 30 and 100 μm. From 100 μm down to 70 μm, the spacing was decreased by 5 μm each time; from 70 μm down to 60 μm and from 40 μm down to 35 μm, it was decreased by 2.5 μm; and between 60 and 40 μm, the step spacing was reduced by 2 μm each time. The width of the lines was limited by the fabrication

1

For example, during tensile loading the maximum stress occurs in the glass under an angle of approximately 30° to the bonded interface [2]. Thus, failure will occur in the glass even if the strength of the interface is lower than the glass strength. However, it is known from experimental investigations that failure can also occur in the bonded interface if no proper bonding parameters were chosen [3].

551

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(b)

Elevated structure (step)

1

1 2

Nonbonded area

2

γ1 > γ2

γ1 < γ2

Fig 36.1 ● Principles of non-destructive strength testing (a) single step, (b) multiple step structures.

(b)

Open

Closed

Step N + 1

Open

Closed

γ (J/m2)

Step N

1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 200

(c)

length nonbonded area 280 μm 2 γ = 0,8 J/m

300

400 500

600 700 800

γ (J/m2)

(a)

2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 20

Lowest bonded gap lmin=60 μm γ = 0.65 J/m2

40

Length of non-bonded area (μm)

60 80 Distance (μm)

100

Fig 36.2 ● FEA-based calculations and examples for single- and multiple-step bond test structures.

process. The length of 100 μm was chosen in order to integrate the structure into 200-μm-wide dicing streets. As a function of the bonding energy, the areas between the multi-steps will be bonded or not, as shown in Figure 36.1b. Thus, the bonding strength is ﬁnally indicated by simply checking which is the ﬁrst bonded gap. Hence, this principle is very easy to use, and most of the following descriptions are related to it.

36.2 FEA In order to determine the surface energy from the measured length of the non-bonded areas, FEAs were performed. This is required because the analytical beam or plate bending theory cannot be applied here, since the length of the non-bonded area is always signiﬁcantly smaller than the wafer thickness. For determination of the surface energy values, a 2D model based on a crack-closing algorithm was developed (Figure 36.2a). In an iterative process, nodes were merged, leading to an increasing of the bonded area. The surface energy is determined using the energy release rate, which is calculated from the difference in elastic energy of the whole model between two steps [6]. For silicon, orthotropic elastic parameters (E11 E33 169 GPa, E22 130 GPa, ν12 ν23 0.36, ν31 0.06) were used in the simulation. For the glass, 552

isotropic properties were used with a Young’s Modulus of E 63 GPa and a Poisson’s ratio of ν 0.2. The steps themselves were considered as displacements in the simulation. Furthermore, it was assumed that no bonding occurs between the surface of the steps and the glass. The single-step structure model had symmetry conditions only on the step side. The multiple-step structure had symmetry conditions on both sides. Using FEA, the dependency between the surface energy γ and the length of the unbonded area were calculated, with the wafer thicknesses and the step height being constant. For the single-step structure, the surface energy increases with decreasing non-bonded area in the simulation. Therefore, the derived surface energy values can be plotted directly versus the length of the non-bonded area, as shown in Figure 36.2b. Knowing the length from experimental measurements, it is possible to calculate the surface energy from this result. For the multi-step structures it was assumed that the initial bonding contact occurs in the center between two lines, and that the bonding area will be enlarged during the bonding process. At the initial contact, a high surfaceenergy is required for bonding, since only a small area is available. During the enlargement of the bonding area, the determined surface energy value passes a minimum, after which the surface energy increases again. This is

Non-destructive Bond Strength Testing of Anodic Bonded Wafers

(a)

(b)

CHAPTER 36

(c) 1.2 1

γ(J/m2)

0.8 0.6 Bond strength strongly dependent on bonding parameters

0.4

Bond process Ideal process range disturbed by constant bonding discharges decreased strength strength

500 V 1000 V 1500 V 2000 V

0.2 Fracture image pull test chips from wafer with lowest surface energy– remaining glass on silicon

0 250

300

350

400

450

500

Bonding temperature (ºC) Influence of bonding parameters on surface energy measured by multi-step bond test structure

Wafer flat Example of bonded rows of multiple-step structures indicating slightly different bonding energies over bonded glass silicon stack

Fig 36.3 ● Results of experiments with multi-step bonding structure.

caused by the increased amount of strain energy that is required to bend the wafers in the vicinity of the step. In order to generate a bond, at least the amount of this minimum in energy is necessary; thus, the minimum value was chosen as the characteristic surface energy for a given step distance. The minimum surface energy required for bonding was calculated for the different step distances and plotted versus the step distance. Knowing the distance where no bonding occurs from the experimental measurements, it is possible to calculate the surface energy using the results shown in Figure 36.2c. To increase the accuracy of the FEA, 3D models based on the same approaches can be used in both cases [7].

36.3 Results For the single-step test structure described above, a typical length of 280 μm was detected, as shown in the detail of Figure 36.2a for a standard bonding process (1200 V, 430°C, bonding on passivation), by analyzing the optical images of the test structures after bonding. Using the FEA results shown in the same ﬁgure, a corresponding surface energy of 0.8 J/m² was determined. Due to the limited resolution of the length measurement, experiments with varied bonding parameters were not performed. For the multi-step structure, Figure 36.3c shows optical microscopy of a test series. Five test structures are shown, placed at different locations on the same wafer. The smallest observed bonded step distances are 65 μm (center), 62.5 μm (lower), 60 μm (upper and right), and 58 μm (left). Using the FEA results shown in Figure 36.2c, this gives surface energies of 0.61 J/m² (center), 0.63 J/m² (lower), 0.65 J/m² (upper and right), and 0.68 J/m² (left). The achieved resolution of the test pattern is around 0.025 J/m².

In Figure 36.3b, the surface energy values (average values of each wafer) are shown for different bonding voltages as a function of the bonding temperature. It was found that the interface energy increases between 300°C and 350°C, while an increase in the applied voltage increases the surface energy. In the range between 350°C and 400°C, the surface energy was almost uninﬂuenced by the bonding temperature, and the inﬂuence of the bonding voltage was reduced. At bonding temperatures above 400°C, the surface energy was reduced, and interestingly, the highest voltage led to a stronger reduction of the surface energy. It can be concluded that the optimal bonding parameters for bonding of anodic blank silicon to glass wafers are in the medium range of 1000–1500 V at 350–450°C. In these ranges, the inﬂuences of various parameters (e.g., machine related) are very low. However, at higher temperatures and voltages, the surface energy decreases because discharges during the bonding signiﬁcantly disturb the bonding process. Additionally, the bond test structure results were veriﬁed by stud pull testing of diced chips from the test wafers. Even for the wafer with the lowest bond interface energy, very high fracture strength values were measured, and it was not possible to crack the bond interface. From this experiment, experiences found in practical anodic bonding were conﬁrmed, illustrating the relevance of this test method and its suitability for practical application. This type of multi-step bonding strength test structure was introduced in a production mask set at 5 positions, so that it was possible to monitor the bonding quality of around 150 process wafers (Figure 36.4a). It was found that this kind of monitoring is important, because differences in bonding strength were seen, even when the bond strength of all the wafers was high enough for further processing and application. The main reason for 553

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Surface energy anodic bonding γ (J/m2)

0,80

Lo tC Lo Lot D t Lo E tF Lo tG Lo t Lo H t Lo I tJ Lo tK Lo tL Lo tM Lo tN Lo tO Lo tP Lo tQ

tA Lo tB

1 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 Lo

Surface energy anodic bond g(J/m2)

(a)

0,70 0,60 0,50 0,40 0,30 0,20 0,10 0,00

Lots and wafers

0,72 0,74 0,71 0.73 0,73

6 in. wafer area (flat)

Fig 36.4 ● Statistical results of anodic bonding process monitoring using a multi-step bonding test structure.

the differences in the bonding strength is thought to be the condition of the bond electrode, while no systematic dependence on the position on the wafer was found (Figure 36.4b; average surface per position on wafer). Finally, it can be concluded that in particular, the multiple-step bond test structure provides a very good bonding strength measurement method for immediate

quality checking after the anodic bonding of each wafer. It is very simple to use by counting the bonded area in the scale of a microscopic image. The structure requires less wafer area, and can be easily integrated into existing technologies since different types of layer can be used for realizing the required steps. A high level of relevance was shown in experiments and production processing.

References 1. R. Knechtel, M. Knaup, J. Bagdahn, A Test Structure for Characterization of the Interface Energy of Anodically Bonded Silicon-Glass Wafers, Published by Springer-Verlag GmbH, Microsystem Technologies ISSN: 0946-7076 (Paper) 1432-1858 (Online) Issue: Volume 12, Numbers 5 Date: March 2006 Title: Wafer-bonding workshop for MEMS technologies (WBW-MEMS), 11–12 October 2004; DOI: 10.1007/s000542005-0036-4. 2. M. Knaup, M. Busch, J. Bagdahn, H.-G. Maschke, A failure criterion for

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interface notches in silicon/glass anodic bonds, Microsyst. Technol. (2003) 281–288. 3. P.E.W. Labossiere, M.L. Dunn, S.J. Cunningham, Application of biomaterial interface corner failure mechanics to silicon/glass anodic bonds, J. Mech. Phys. Solids 50 (2003) 405–433. 4. W. Maszara, G. Goetz, A. Chaviglia, J.B. McKwitterick, Bonding of silicon wafers for silicon on insulator, J. Appl. Phys. 64 (1984) 4943–4949. 5. J.A. Plaza, Effect of silicon oxide, silicon nitride, and polysilicon layers on

the electrostatic pressure during anodic bonding, Sens. Actuators A67 (1989). 6. P. Kohnke, ANSYS User’s Manual for Revision 6.1, Volume I Procedures. SAS Inc., Houston, 3–161, 2002. 7. F. Naumann, M. Ebert, J. Bagdahn, Numerical veriﬁcation of indicator structures in anodically bonded silicon-glass wafers based on interface energy, in: 2nd International Workshop on Wafer Bonding for MEMS Technologies, Halle/Saale, Germany April 9–11, 2006.

37

Chapter Thirty Seven

Wafer-Bonding Equipment Viorel Dragoi and Paul Lindner EV Group E.Thallner GmbH, St. Feoriun, Austria

Observed and studied since ancient times, adhesion between two clean ﬂat surfaces started to attract the interest of the semiconductor industry during the 1970s. Various companies introduced applications using the spontaneous adhesion between two silica or optical glass surfaces [1] as well as the electric ﬁeld-assisted bonding between glass–metal (ﬁrst reported in 1969 [2], known today as “anodic bonding”) or glass–silicon. These applications were typically using home-made ﬁxtures and apparatus. The need for dedicated wafer-bonding equipment rose in industry due to the high number of potential applications foreseen for this technology in the late 1980s. Specialized wafer-bonding equipment development was the only path to ensure the levels of productivity, reliability and reproducibility required by manufacturing processes. Development of dedicated wafer-bonding equipment started in the early 1990s. In the beginning equipment was primarily a combination of semi-automated systems which, in most of the cases, were replacing home-made solutions with in situ alignment and bonding. Early applications were usually requiring alignment of the two substrates’ edges only before bonding by using mechanical ﬁxtures (mechanical alignment). The newly developed MEMS devices required more often precise optical alignment of the two substrates. The major differences between main speciﬁc features of the two process steps involved in aligned wafer bonding (alignment: sensitive to vibrations and wafers contact with equipment tooling, and wafer bonding: rough processes often involving contact force, heating, vibrations) raised the need for separation of the two steps. EV Group introduced to MEMS industry the aligned wafer-bonding process separation principle (Figure 37.1) in 1992 when

the ﬁrst manufacturing equipment based on this principle was installed [3]. This manufacturing approach, which nowadays represents an industry standard, considers two different process steps: in the ﬁrst process station the two wafers are precisely aligned and mechanically ﬁxed on a wafer holder (named usually bond chuck) which is then transferred to the second station (bond chamber) to perform the wafer-bonding process. Separation between alignment and bonding steps brings a major economic advantage for production activities: as speciﬁc process time for optical alignment per wafer pair is 2–10 times shorter than process time for wafer bonding (depending on bond process type), a single optical alignment station can serve a few separate bond stations. By technical considerations process separation allows increased alignment accuracy as high temperature, contact force, vacuum, process gasses and voltage (process parameters typically required for wafer bonding) would imply severe design limitations to a micrometer-range precise optical alignment system. Volume manufacturing requirements were initially driven by automotive applications such as pressure sensors, accelerometers and gyroscopes. Early MEMS production was carried mainly on 100 mm diameter wafers, but conversion to 150 mm diameter was of great importance for increasing yield, throughput and decreasing products costs. Fully automated bond aligners and wafer bonders with robot handling systems enabling cassetteto-cassette operation were developed. In the last decade consumer products became increasingly important and thus this type of application became the main driving force for equipment development as fully integrated cluster systems including 555

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1 2 Wafers to bond

Bonded wafers Reused

Bond chuck

Bond chuck

Wafer bonder Bond aligner

Contact force 1

1

2 2 Left Right

Top/bottom heating

Electric field

(–)

Wafer-to-wafer alignment

Aligned wafers clamped on bond chuck

+

– (+) Chamber evacuation

Process gas purge

Fig 37.1 ● Process separation principle for aligned wafer bonding.

wafer-to-wafer alignment and bonding modules. Numerous new applications require wafer bonding of CMOS wafers to MEMS mechanical wafers. These applications are currently the main driving force for MEMS conversion to 200 mm diameter substrates. While MEMS processing mostly uses IC compatible manufacturing techniques there are a great variety of substrate materials, thicknesses, wafer sizes and MEMSspeciﬁc processes. Probably one of the most basic topics illustrating the lack of a mutual understanding in MEMS ﬁeld is terminology. It is well known to any person familiar with this industry that even the main ﬁeld is known under different names with regional use: MEMS (Micro-Electro-Mechanical Systems) in USA, Asia-Paciﬁc region and partially in Europe, MST (Microsystems Technology) in part of Europe (mainly in Germany) or Micromachines (speciﬁc for Japan). With the continuous growth of MEMS markets, the need for adopting speciﬁc MEMS standards in design, manufacturing, testing and packaging is becoming more critical. The complexity of the MEMS devices and processes brings certain challenges to the implementation of worldwide standards. Efforts for bringing manufacturing techniques to an acceptable level industry-wide need to be considered with respect to IC standards, which are not applicable for the ﬁeld of MEMS. It is very important to establish common concepts, terminologies and evaluation methods in order to promote research, manufacturing and commercialization of MEMS devices with higher efﬁciency and lower costs. Equipment manufacturing also would have beneﬁts if speciﬁc technology-related items would be subject to international 556

standards, as it has only been a few decades in the mainstream microelectronics industry. Some efforts in the direction of MEMS standardization and coordinating activities in this respect are ongoing worldwide, an example in this direction being the MEMS Standardization Committee supported by SEMI [4]. Wafer bonding is also a particular ﬁeld suffering from a lack of standardization. In this chapter we will deﬁne the speciﬁc terms used for technology description in order to avoid any possible misinterpretation. One example of a term which sometimes has different meanings is “pre-bonding”. In this chapter the term is used for the process step in which two wafers are brought in contact, typically at room temperature (RT). In this case, adhesion between two substrates occurs due to low energy molecular bonds (e.g., generated by van der Waals forces) and are very low, allowing just pre-bonded substrates’ handling between process stations but not enough for further processing. Typically bond strength is increased through a thermal annealing which is transforming the weak bonds into strong covalent bonds, enabling bond strengths in the range of bulk fracture strength of initial substrates.

37.1 Aligned Wafer-Bonding Requirements for MEMS Applications The main quality requirements for a wafer-level bonded MEMS device include bond strength, hermeticity,

Wafer-Bonding Equipment

alignment accuracy and overall bonding yield, given by the number of defects. Bond strength must be sufﬁcient to withstand harsh conditions that occur both in subsequent process steps (e.g., grinding, lapping or dicing) and during the lifetime of the device (for example, a differential pressure sensor). Bond strength is measured typically using customized device-dependent test structures based on tensile testing, shear test or burst tests. Numerous device manufacturers are using just qualitative evaluation of bond strength to observe if wafers survive harsh mechanical process steps like grinding or dicing. Hermeticity is required to improve the life expectation and reliability of certain types of devices, as a change in atmosphere might change the working parameters of the MEMS devices. The following types of hermetic sealing were identiﬁed for MEMS devices: • Moisture sealing: no moisture penetrates the sealing • Gas sealing: particular gas type does not penetrate the sealing • Low vacuum sealing: encapsulated vacuum level is 102 mbar ÷ 1 bar • High vacuum sealing: encapsulated vacuum level is 102 mbar • High pressure sealing: encapsulated vacuum level is 1 bar Wafer bonding for MEMS devices is used to create engineered substrates as starting materials (thick-ﬁlm SOI wafer), as ﬁrst level encapsulation (capping) and also for integration of micromechanical and electronic components. Depending on the device design different requirements on the post-bond alignment are applicable. Engineered substrates and certain capping processes (e.g., for absolute pressure sensors’ applications) require mechanical alignment of wafers. Mechanical pins are used to reference the wafer perimeter and the major ﬂat (or notch). In such applications typically one or both wafers are not patterned. Alignment requirements are driven by needs of subsequent processes and typical alignment values are in the range of 50 μm translation and 0.1° angular accuracy. Wafer-to-wafer alignment requirements for encapsulation processes are mostly driven by the need to maximize the use of substrate, which is associated subsequently with a decrease of the sealing line’s width. For such applications both wafers are patterned and optical alignment approaches are used. Typical device design rules foresee a 3 sigma post-bond alignment accuracy ranging from 2 to 25 μm (depending on alignment and bonding method—see Figure 37.4).

CHAPTER 37

Advanced 3 D packages integrating multiple functional layers and innovative MEMS device designs are now driving the post-bond alignment accuracy requirements further down to the sub-micrometer range.

37.2 Wafer Aligners Wafer-to-wafer alignment technology is a very dynamic ﬁeld as the requirements in terms of alignment accuracy are continuously increasing. For each application the right combination of wafer-bonding/alignment technology has to be selected for the best result. Wafer-to-wafer alignment accuracy is inﬂuenced by various factors during the bond process. Among them the most signiﬁcant are compression of intermediate layers (for intermediate layers bonding such as eutectic, adhesive bonding or glass frit wafer bonding) and different thermal expansion of the two bonding partners or of rigid interface bond layers (e.g., metal patterns). For such bond processes typically there are two alignment speciﬁcations: post-alignment accuracy (accuracy provided exclusively by the optical alignment equipment) and post-bonding accuracy (the ﬁnal accuracy measured after bonding, when the bonded interface is already rigid. With respect to these factors, direct (fusion) bonding methods are most compatible with high alignment accuracy. Two main types of wafer-to-wafer alignment methods are used in MEMS technology: • Mechanical alignment: the major ﬂats/notches of the two wafers are aligned one to each other. Typically a setup of pins and mechanical actuators is used to accomplish this task. Alignment accuracy strongly depends on the tolerances of wafer dimensions. For SEMI standard wafers the alignment accuracy is 50 μm and /0.03° (Notch) or /0.1° (Flat) (for wafer diameters up to 300 mm). Alternatively to mechanical actuators commercially available robot handling systems with optical prealigners can be used to position the wafers. This approach is typically less accurate (about 100 mm and 0.1°) but allows for a free programmable offset angle between the wafers. • Optical alignment: the two wafers are precisely aligned using optical alignment equipment (Figure 37.2). In this case, high alignment accuracy is expected (typically in the range of 0.5–25 μm).

37.2.1 In situ Alignment and (Pre-) Bonding In both mechanical and optical alignment methods an in situ alignment approach provides best accuracy. In 557

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Screen with alignment keys and vernier features Microscope Top wafer holder Top wafer Bottom wafer 6 Axis alignment stage

Fig 37.2 ● Schematics of optical bond alignment stage.

situ refers to the fact alignment and pre-bonding steps are performed on the alignment stage at RT and close to ambient pressure. The bond strength after this step must be either ﬁnal or sufﬁcient to transfer the wafer stack to subsequent processing (e.g., thermal annealing) without affecting alignment accuracy. Two different bonding methods are frequently used with an in situ process: • Direct bonds (or molecular bonds) which allow a prebonding step at RT between mirror polished surfaces (Rms 0.5–2 nm for Si or SiO2 surface) and support a spontaneous bond when contact is established. After pre-bond the strength is sufﬁcient to allow for a transfer of the aligned stack to an annealing furnace. Cleanliness of both wafers and alignment equipment are of utmost importance since particles prevent contact of wafers at molecular level. • UV bonds which utilize a UV-curable adhesive as interlayer: the exposure to UV light takes place subsequently to the optical alignment and wafer contact. One of the wafers must be transparent to UV light. Usually in situ alignment and bonding are carried out in clean room ambient. In situ alignment and bonding for devices within precisely controlled ambient (e.g., humidity, Oxygen-free) or high vacuum require complex equipment, which is typically not used in manufacturing.

37.2.2 Ex situ Alignment and Bonding Process Separation Precise in situ alignment in the bond chamber is not possible for bonding technologies requiring high contact force and high temperature for the wafer-bonding process. 558

Due to this, the two processes are separated in two steps (Figure 37.1). In this process separation, the ﬂow is the following: • Wafers are loaded to the wafer-to-wafer aligner (bond aligner). • Wafers are aligned (manually or automatically) and mechanically ﬁxed on a bond chuck. If controlled atmosphere is required at the bonding interface (inside devices) the two wafers are mechanically separated by spacers. • Bond chuck is loaded to the bond chamber. The bond chamber can be evacuated down to high vacuum range and bonding is performed after spacer removal by applying contact force and heating from two sides. Optical alignment can be performed in two different ways: direct alignment (when one wafer is transparent to light—visible or infrared (IR)—and the alignment keys from both wafers are observed in live mode) and indirect alignment methods (wafers are not transparent and one wafer is aligned using as reference the digitized image of a second wafer).

37.2.3 Direct Alignment Methods Transparent Alignment One wafer is transparent to visible light, allowing generation of a live image of both wafers. During alignment the wafers are separated by a small gap (separation gap) which preferably is smaller than the microscope’s focal depth. When wafers are ﬁxed onto a very ﬂat chuck, focal depths between 15 and 100 μm provide a safe separation gap, so wafers do not come in contact during optical alignment process. Visibility through substrate material is either a material property (glass or fused silica wafer transparency) or is ensured by perforations in the substrate (e.g., etched through holes).

IR Alignment Transparent alignment can be extended by using IR radiation (1000 nm ÷ 1700 nm) instead of visible light. For good optical image quality the light on the backside of the wafer facing the microscope objectives must not be scattered by topography or surface roughness. In best case scenarios this wafer is double side polished. Both transmission (IR light source opposite to microscope relative to wafer stack) and reﬂection (IR light source in microscope) setups can be used with good results. Other limitations of the process are governed by all steps that reduce the IR transparency of the substrate: • High doping concentration in Si causes reduced IR transmission. • Non transparent functional layers (e.g., metals) produce light scattering and interference patterns which make difﬁcult alignment process.

Wafer-Bonding Equipment

Top side objective

CHAPTER 37

Locate bottom wafer alignment marks with top objectives Digitize image Store position

Bottom wafer

Top wafer Align top wafer to digitized image

Bottom side objective Positioning system

Restore bottom wafer position Bring wafers in contact

Fig 37.3 ● Function principle of SmartView® front-to-front alignment.

• Metal layers can be designed into an IR bond alignment process by opening up a sufﬁciently large window around the alignment keys.

37.2.4 Indirect Alignment Methods Backside Alignment In this process, one wafer has alignment keys deﬁned on the front-side, while the second has alignment keys deﬁned on the backside. After loading the ﬁrst wafer its alignment key’s position (later to be enclosed in bonded interface) is digitized and stored. The second wafer is aligned to the digitally stored reference image. The ﬁnal alignment accuracy for this type of process is affected also by errors induced by potential front-to-back lithographic processes used for deﬁning alignment keys. Front-to-Front (Face-to-Face) alignment: In this wafer-to-wafer alignment approach the alignment keys are located on the front sides of the two wafers and will be enclosed in the bonded interface. An original front-to-front alignment method was developed for applications requiring very high alignment accuracy: SmartView® alignment (Figure 37.3). This process uses two pairs of microscopes with the same focal axis, one for each alignment key. The optical alignment process ﬂow is: • First wafer is loaded into the bond aligner; • The alignment keys are located using top microscope and their image is digitized and stored by the software; • Second wafer is loaded into the bond aligner;

• Alignment keys are located with the bottom microscope; • The alignment keys of the bottom wafer are overlapped to the alignment keys on the digitized image of ﬁrst wafer using high precision x–y mechanical stages; • After completing the alignment, the two wafers are mechanically ﬁxed on the bond chuck which may then be transferred to a bond chamber. The main advantage of this method is that due to a very small z-travel range of the wafers in the optical aligner when wafers are brought into contact directly or with spacers, alignment accuracy below 1 μm is achievable for wafers up to 300 mm diameter [5, 6]. Alternative front-to-front technologies with microscopes introduced between wafers provide the beneﬁt of two live images during alignment. However optical errors (optical axis not perpendicular to substrate) and subsequent motions, speciﬁcally the very large Z-axis movement in the range of centimeters, may have signiﬁcant impact to the overall alignment results. Figure 37.4 shows an overview of the main wafer-towafer alignment techniques. In order to make sure the desired process beneﬁts from all the advantages of the wafer-to-wafer alignment method, the following items have to be considered for process choice. First of all, wafer design has to consider the alignment method to be used. It is important to know from the design stage the alignment method of choice in order to include the dedicated bond alignment keys in wafer layout design. 559

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Bond alignment methods Mechanical alignment

Optical alignment

Flat-to-flat (notch-tonotch alignment)

Direct alignment Transparent alignment

Example:

SOI bonding (Si to Si)

Accuracy:

+/–50 μm, +/–0.1° (flat), +/– 0.03° (notch)

Si to glass alignment for anodic bonding +/–0.5 μm IR alignment

Robot load accuracy

Example:

Hybrid orientation wafers (flats/notch at angle)

Accuracy:

+/–100 μm, +/ –0.1°

Si–Si alignment for 3D interconnect +/–0.5 μm

Indirect alignment Backside alignment

Si-Si alignment (capping process for MEMS) +/–1.5 μm Face-to-face alignment

Si–Si alignment for 3D interconnect +/–1.0 μm

Fig 37.4 ● Overview bond alignment methods.

The choice of wafer alignment method is based on substrate type and features, device-speciﬁc requirements and requested alignment accuracy. Alignment key selection is a very important step in process deﬁnition. For a speciﬁed alignment method the alignment accuracy and the alignment process reliability depend on the alignment keys’ shape, dimensions and position on the wafer. Guidelines for alignment key design can be found in the SEMI Standard MS1-0307: “Guide to specifying wafer–wafer bonding alignment targets” [4].

37.3 Wafer Bonders Selection of the appropriate wafer-bonding process and subsequently the suitable type of bonding equipment for speciﬁc products is of great importance. Table 37.1 summarizes some of the main items which need to be considered in selecting bond technology and equipment. 560

The logical choice of process and equipment starts from the device design stage by considering the main device requirements which would allow the choice of the most appropriate alignment type and bond process. Table 37.1 shows the main conditions required by the most used wafer-bonding processes. Once the main technical criteria are established and technology is chosen, equipment selection can be made based also on required manufacturing conditions (environment, production volume and throughput). Numerous MEMS wafer-bonding processes are using similar equipment features, even if bond principle is different. This situation allowed the development of the “universal bond chamber,” which allows multi-process use. However, products with very special requirements imposed equipment developments for particular manufacturing conditions. Two main types of bond chamber are available for wafer-bonding technology: • thermal bond chambers • room-temperature bond chambers

Wafer-Bonding Equipment

CHAPTER 37

Table 37.1 Parameters inﬂuencing bond technology selection

Criteria

Item

Selection

Materials restrictions

Materials chemistry

– – – – – –

Surface pre-treatment Intermediate layers (if used) Bond force Bonder tooling Prevent destruction of structures (e.g., metallization) Minimize stress induced by different thermal expansion coefﬁcients of materials

– – – – –

Alignment type and bond process Aligner and bonder tooling Bond process type Interface materials when high thermal conductivity required Interface materials if speciﬁc transparency required

– – – – –

Pre-cleaning type Handling method Pre-cleaning type Handling method Bonder tooling to avoid contamination

Mechanical properties Bond process temperature

Speciﬁc device requirements

Alignment accuracy Hermeticity Thermal conductivity Transparency

Contamination

Particles Organics Metal ions

Device operation regime

Working temperature

There are also two types of room-temperature bond chambers: • bond chambers for “clean bonds” (metal ions-free chamber for molecular bonding) • chambers allowing radiation curing of materials used as bonding layers (e.g., UV)

37.3.1 Thermal Bond Chambers Available typically as “universal bond chamber ”, such equipment contains features allowing performing almost any bond process. Table 37.2 is summarizing the main features of a standard commercially available bond chamber on EVG®500 equipment series. The process chamber is optimized to provide very accurate control of the critical process parameters. Figure 37.5 shows a schematic cross-section drawing of a bond chamber. The use of a bond chuck with ﬂat solid surface which may be transferred from bond aligner to bonding system offers some important advantages: • Wafer stack is in contact with the very ﬂat surface of the chuck: this allows uniform transfer of heat as well as uniform distribution of contact force required by some bond processes.

– Bond process – Interface layers (if used)

• As wafers come in contact only with the chuck surface and a removable plate mounted on the top heater, contamination can be limited to particular sets of tooling. Contamination which may occur in a MEMS-related bond process can be: metal ions (when using Na resulting from anodic bonding, Au or Cu), organic (after using the bond chamber for polymer bonding), and particles. • The chuck plate has a thermal mass which helps to avoid thermal shocks when the chuck is unloaded from the bottom heater at temperatures above RT. Low temperature variations may lead to wafer breakage during unloading, especially when using two different materials for bonding. The bond chuck is designed to accommodate the requirement of controlled atmosphere encapsulation in devices. In such a process, substrates typically contain etched cavities and they must be loaded to the bond chamber with their surfaces separated in order to allow ﬁrst establishing the desired environmental conditions in the bond chamber and then contacting the wafers. Substrate separation is assured by the use of three spacers with typical thicknesses in the range 30–500 μm. Spacers (also named sometimes “ﬂags”) are typically made out of sheets of bare metal, coated metal or even plastic or quartz glass, depending on the equipment and process type. 561

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Table 37.2 Main features of commercially available bonding equipment

Bond chamber features

Parameter

Comments

Substrate size

– SEMI standard wafer size; – Custom size and small pieces optional

Loading mode

– Manual – Automatic

Automatic loading: – load wafers to bond chucks outside bonder – load wafers to the bonder and all handling is fully automated (“cassette-to-cassette” process)

Temperature range

RT ÷ 650°C (controlled ramping, 1°C steps)

– Top/Bottom heaters, independently controlled – 1% for 150 mm and 2% for 200 mm diameter wafers

Chamber atmosphere

– Low vacuum (103 mbar) – High vacuum (105 mbar) – Overpressure (3 bar)

Maximum contact force

3.5 kN, 7 kN, 10 kN, 40 kN, 60 kN, 100 kN

Maximum force value is chosen by production needs

Voltage

2000 V, 50 mA

Used for anodic bonding only

Operation

Recipe controlled, through graphic user interface (GUI)

Force Mechanical clamp

Mechanical clamp

Top side heater

Spacer

Spacer Bond chuck Bottom side heater Wafers

Fig 37.5 ● Schematic cross-section drawing of a standard thermal bond chamber.

Besides the positive role of spacers in encapsulation processes, it has to be considered that spacers’ thickness may inﬂuence the alignment accuracy due to increased vertical travel range of substrates to come in contact. For this reason it is very important to choose the best compromise between bond process—alignment accuracy—atmosphere encapsulation, when choosing the type of tooling in the bond chamber. Wafer-to-wafer alignment accuracy is inﬂuenced by various factors during the bond process. Among them the most signiﬁcant factors can be mentioned: compression of intermediate bond layers which induces shifts (for bonding with intermediate layers as for eutectic bonding, adhesive bonding or glass frit bonding), different thermal expansion of the two bonding partners which induces run-out-type errors and the z-travel range 562

of the wafers when brought in contact (e.g., given by thickness of the spacers used in the bond setup). For such bond processes two alignment speciﬁcations are deﬁned: post-alignment accuracy (accuracy provided exclusively by the optical alignment equipment) and post-bonding accuracy (the ﬁnal accuracy measured after bonding, when the bonded interface is already rigid). Due to the large variety of applications and bond processes there is a large need for equipment ﬂexibility. For this reason, wafer-bonding equipment vendors are able to supply with their systems various types of tooling able to accommodate from standard substrates (e.g., SEMI standard semiconductor wafers) to very customized substrates (e.g., small pieces of wafers, square or asymmetric substrates, thick substrates, transparent substrates, etc.).

Wafer-Bonding Equipment

CHAPTER 37

Table 37.3 Process parameters for main wafer-bonding processes used in MEMS manufacturing

General method

Electric Field

Direct binding

Bind process

Anodic

Silicon direct (SDB)

CMOS compatible

Temperature range

1000°C 440°C 200°C Room Temp.

Plasma activated SDB

Intermediate layer Glass frit

Eutedic/ Metal Solder diffusion (metal–metal)

fx1

fx1

fx1

Vacuum compatibility

Low 1 mbar High 102 mbar

Surface roughness Requirement (both surfaces)

1 μm 20 nm 2nm 0.5 nm

Environment Requirement

Cleanroom Class

100

10

10

Sensitivity to particles

Low Medium High

fx1

Adhesive (e.g., BCB)

Epoxy (UV Epoxy (thermally cured) cured)

fx1

1000

1000

1000

fx1

1000

10

1000

: Fully compliant fx1: Compliant with certain limitations or boundary conditions : Not compliant

In order to allow speciﬁc processes bond chucks can be manufactured from different materials (e.g., materials with speciﬁc conductive properties such as stainless steel, titanium, aluminum, graphite, silicon carbide or silicon nitride, special ceramics, or electrical/thermal insulators like Teﬂon® [7] or PEEK™ [8]). As wafer-bonding processes are typically sensitive to particles contamination, bond chambers are designed considering such factors as: • Mobile parts located inside bond chamber (e.g., spacers pulling mechanism) do not generate particles • Chamber layout allows easy cleaning and minimizes potential contamination retention. Wafer-bonding processes require different ambient conditions in the process chamber (Table 37.3). Equipment is typically able to ensure the following types of environment: • Low vacuum: realized with oil-free roughing pumps, vacuum levels from ambient pressure to 5102 mbar.

• High vacuum: realized with the use of turbo molecular pumps, vacuum levels from 5102 mbar to 5105 mbar. • Gas at controlled pressure: realized by using evacuation/gas purge cycles in order to evacuate air completely and have desired gas atmosphere (typically inert gasses as nitrogen, SF6, or reducing gasses as forming gas—mixtures of 4% H2 dissolved in inert gasses as nitrogen, argon, helium). • over pressure: pressurized gas (up to 3 bar pressure) which requires special safety features of the chamber. As most of the wafer-bonding processes include a thermal step, accurate temperature control is a crucial topic. For example, an EVG®500 series bond chamber allows independent programming of heating/cooling for the two heaters: different temperature values from RT to maximum 650°C as well as different temperature ramps (in 1°C steps, ranging from 1°C to 45°C per minute). 563

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37.3.2 Room-Temperature Bond Chambers “Clean” Bond Chambers This type of process chamber is typically used for molecular bonding processes (known also as “direct” or “fusion” bonding) and consists of a hardware setup which has to meet very particular criteria. An example of such a special setup is the pre-bond chamber used for silicon-on-insulator (SOI) manufacturing or for MEMS wafer-bonding applications using CMOS wafers. For this speciﬁc product the bond process and bonder hardware have to fulﬁll very strict requirements: • No particle contamination (required particle levels for manufacturing: 0.015 LPD added in pre-bond chamber, measured for 0.15 μm particle size). • No metal ions contamination (ion levels for critical metallic elements such as Fe, Cu, Al, Zn, Mn have to be in the range of 109 atoms/cm2). • No stress at the bonded interface induced by prebonding process. In order to fulﬁll these criteria the chamber parts coming in contact with wafers are made out of materials such as Teﬂon®, PEEK™ or similar materials which meet the ﬁrst two criteria mentioned above. Besides the contamination requirement the stress at the interface is crucial in determining the ﬁnal product quality (e.g., for manufacturing of thin and ultrathin SOI substrates by ion implantation methods). A stressed bonded interface is usually not a major issue if the substrates bonded are not further thinned down, but in case of thinning (one substrate thinned from a few hundred micrometers down to a few hundreds of nanometers— layer transfer by hydrogen implantation—or few tens of micrometers—mechanical thinning by grinding and polishing) the stress at the interface will generate in the thin layer pattern distortion or even cracks. The following factors are important in minimizing stress in pre-bonded interfaces: • Bottom wafer in contact with chuck surface across entire surface. • Flatness of the bond chuck (surface in contact with bottom wafer). • Position of bond front initiation. • Force used for bond force initiation.

Bond Chambers for Radiation-Cured Bonding Layers A particular category of materials are used as bonding layers, typically deposited onto substrates by using spinor spray-coating and in order to act as bonding layers need radiation curing (typically UV). There are a few 564

important advantages of this process, as well as some limitations. One of the advantages provided by the UV bonding process is room-temperature processing and, subsequently, high throughput, as there is no thermal step involved. The major limitations of such a process are the need for at least one UV-transparent substrate and the limited hermeticity which can be achieved by using UV-curable materials. The important requirements UV-bond chamber needs to fulﬁll are: • High UV illumination uniformity. • High vacuum compatibility. • Existence of spacers. • Possibility to use different process gases.

37.4 Aligned Wafer Bonding: Equipment Solutions for MEMS Manufacturing Sections 5.3.1 and 5.3.2 presented the general concepts and made a general presentation of the main requirements speciﬁc for wafer-to-wafer alignment and waferbonding equipment. This section aims to present a few examples of equipment solutions which are used in MEMS manufacturing. First it should be mentioned that equipment development was driven not only by the technical device developments but also by the typical MEMS industry business models. One typical situation is the existence of fabless companies and MEMS foundries. The typical MEMS company is small (with some exceptions), so there are a number of important companies working only on design and testing of devices, while their production is carried out by service provider companies possessing all equipment for running the full process ﬂow. In such cases, it is of great importance that equipment ﬂexibility is very high in accommodating various applications and each individual equipment has to be capable of running as many processes as possible. For such situations waferbonding equipment has a cluster tool structure and includes individual process stations. This allows various processes such as single wafer cleaning, surface preparation, wafer-to-wafer alignment and wafer bonding to be performed inside the same equipment. Integration of all stations in a single piece of equipment enables fully automated “cassette-to-cassette” processes with high reliability, minimizes the number of wafer handling steps (important for substrates containing fragile structures) and considerably decreases the total equipment footprint (important for fabs, as MEMS manufacturing environment is typically a cleanroom class 1000 or better).

Wafer-Bonding Equipment

CHAPTER 37

Fig 37.6 ● (a) EVG620 semi-automated wafer-to-wafer aligner and (b)EVG520IS semi-automated wafer-bonding equipment.

Another speciﬁc type of MEMS industrial organization is the start-up company which splits from a pure R&D organization and goes into manufacturing activities. Such a company typically has low starting capital and focuses on developing a limited amount of products (sometimes even a single product). For such a company it is very useful to have the possibility to invest in simple manual equipment useful for R&D work which can be later upgraded to accommodate pilot line production and ﬁnally move to volume manufacturing with no need to change the process ﬂow. An example of such equipment is EVG®600 series (wafer-to-wafer aligners) or EVG®500 series (wafer bonders). These equipment series enable easy transfer of process recipes from manual systems to integrated high volume equipment without any major change; thus, a product developed on a manual R&D system can be easily transferred to volume manufacturing equipment. Moreover, EVG®600 aligner platforms allow further upgrade with an automated handling unit that enables a fully automated processes. EVG®500 series bonders are conﬁgured with single bond chambers, but additional bond chambers can be added to the same control unit. Figure 37.6 shows two examples of commercially available standard semi-automated systems: an EVG®620 wafer-to-wafer aligner and EVG®520IS wafer-bonding equipment. Besides the equipment dedicated to perform the wafer-to-wafer alignment step and wafer-to-wafer bonding step, other types of equipment are sometimes necessary for performing wafer-bonding-related processes: • Single wafer-cleaning equipment consists of a spinner unit and uses different chemistries for cleaning: simple deionized water rinse or megasonic rinse,

diluted chemicals (e.g., max. 2% NH4OH) and solvents rinse (isopropanol, acetone). The goal for this cleaning process is particles removal. • Substrate coating equipment is used typically for spin- or spray-coat substrates with materials (usually resists or other types of polymers) which are used as bonding layers. Typically coating equipment requires a hot plate for soft baking the deposited layers: manual systems would use a stand-alone hot plate, while the automated systems would have a number of hot plates integrated in the equipment conﬁguration. • Plasma activation equipment can be used for some bonding applications requiring direct bonding (molecular bonding) of substrates at low temperature (wafer-bonding process is considered low temperature if maximum temperature does not exceed 400°C). Plasma treatment of substrates prior to bonding enables a surface chemistry modiﬁcation resulting in higher bonding energy at RT. This subsequently leads to considerably lowering the thermal annealing temperature and time. For example silicon hydrophilic bonding would require a thermal annealing at 1000°C for a few hours to reach a bond strength in the range of bulk fracture strength of material, while with plasma activation of the same substrates the required thermal annealing would be at 200–400°C for 1–3 hours, with the same result. Wafer-bonding equipment operation is based on the use of a graphic user interface (GUI) based on customized software. Software has to allow accurate programming of process recipes and control of all parameters, as well as real-time monitoring and displaying of process parameters. 565

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Different login levels are available, especially for equipment installed in volume manufacturing, which requires accurate control of production processes as well as the possibility to track products through the process chain: • Administrator level: full access to all equipment functions, access granted only to equipment engineers performing equipment maintenance and calibration. • Engineering level: full access to all process-programming functions, access granted only to process engineers authorized to deﬁne new process recipes. • Operator level: access to loading process recipes, access granted only to operators running production activities (no access to programming or equipment functions). A few examples of equipment solutions for particular MEMS applications will be presented further. If Tables 37.1 and 37.3 presented main process features useful in choosing the appropriate wafer-to-wafer alignment and bonding technology, this example illustrates the criteria which inﬂuence the choice of equipment type for speciﬁc application, depending on the production mode. Example: Application: One CMOS wafer needs to be bonded to a silicon wafer by direct bonding. Wafers need to be aligned with 2 μm precision. Process details: CMOS wafer would require a maximum temperature of 400°C in order not to destroy metal patterns. This indirectly leads to front-to-front alignment and for bonding, plasma activated wafer bonding. I. Equipment for R&D-type process: • Manual single wafer-cleaning system for particles removal

Single wafers manual loading

• Semi-automated plasma activation system • Front-to-front wafer-to-wafer aligner • Manual wafer-bonding system Process ﬂow (Figure 37.7): • Wafers are manually loaded to cleaning system for megasonic cleaning. • Wafers are manually transferred to plasma activation system for surface activation. • Wafers are manually loaded to the wafer-to-wafer aligner. Alignment is performed and wafers are mechanically ﬁxed on a bond chuck inside the aligner. • The bond chuck is manually transferred to the bonding system. • After bonding, bonded wafers are manually unloaded from the bond chuck and it is transferred back to the aligner for next process. II. Equipment for low/medium volume production: • Automated single wafer-cleaning system for particles removal • Semi-automated plasma activation system • SmartView® front-to-front wafer-to-wafer aligner • Automated wafer-bonding system Process ﬂow (Figure 37.8): • Full wafer cassettes are manually loaded to cleaning system for megasonic cleaning. • Cassettes are manually transferred to plasma activation system for surface activation. Wafers are manually handled in plasma activation system.

Single wafers Single wafers Wafers on chuck: Bonded wafers manually manual transfer manual transfer manual chuck transfer unloaded from bond chuck Surface Megasonic Optical Bond activation cleaning alignment process

Empty bond chuck manually transferred to aligner for next process

Fig 37.7 ● Process ﬂow for aligned plasma activated wafer-bonding process (R&D equipment solution). Wafers cassettes Wafers cassettes Wafers cassettes Wafers on chuck: Bonded wafers manually loading transfer transfer manual chuck transfer unloaded from bond chuck Surface Megasonic Optical Bond activation cleaning alignment process

Empty bond chucks manually transferred to aligner for next process

Fig 37.8 ● Process ﬂow for aligned plasma activated wafer-bonding process (low/small volume equipment solution).

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• Wafers are manually loaded to the wafer-to-wafer aligner. Alignment is performed automatically and wafers are mechanically ﬁxed on the bond chuck inside the aligner. • The bond chuck is manually transferred to the bonding system. Several chucks are loaded to the bonder and equipment will automatically load/unload chuck to bond chamber and run process recipes. • After bonding, bonded wafers are manually unloaded from bond chucks and bond chucks are transferred back to aligner for next process. III. Equipment for high volume production: Integrated system (e.g., EVG GEMINI®, Figure 37.9) consisting of the following process stations: • Single wafer-cleaning module for particle removal (same as on stand-alone cleaning equipment). • Plasma activation chamber (same as on stand-alone system). • Front-to-front wafer-to-wafer alignment module.

Fig 37.9 ● GEMINI® Fully automated integrated system for plasma activated aligned wafer-bonding process (high volume equipment solution).

• Automated wafer-bonding system (including 1–4 bond chambers). • One robot with optical pre-aligner for feeding wafers from cassettes to cleaning station, plasma chamber and optical aligner. • One robot able to handle bond chucks, as well as wafers (double end effector). Process ﬂow (Figure 37.10): • Full wafer cassettes are manually loaded to integrated system loading ports. • Robot transfers one wafer from ﬁrst cassette to cleaning station. • Clean wafer is automatically transferred to plasma activation chamber, then wafer from second cassette is loaded to cleaning station. • Surface activated wafer is automatically transferred to optical aligner, then second wafer is transferred from cleaning station to plasma activation chamber. • Second wafer is automatically transferred from plasma chamber to optical aligner. • Optical alignment is performed automatically, then wafers are mechanically clamped on bond chucks inside the aligner. • Second robot handles the bond chuck to bond chamber, and the bond process is automatically performed. • After the wafer-bonding step, the bond chuck is automatically transferred to an integrated cooling station. Chuck and bonded wafers are chilled from unloading temperature to RT. Unloading temperature may range from 100°C to 250°C, depending on the types of substrate. Unloading temperature has to be very carefully chosen, as if it is too high substrates may break due to thermal shock. • Cool chuck is transferred automatically to the wafer unloading station. • Bonded wafer pair is automatically un-clamped and then bonded pair is transferred to a cassette.

Fully automated integrated system

Wafers cassettes Wafers automatic Wafers automatic Wafers automatic Bond chucks loading transfer transfer transfer automatic transfer Megasonic cleaning

Surface activation

Optical alignment

CHAPTER 37

Bond process

Automatic transfer for wafers unloading Cassette with bonded wafers is unloaded from equipment

Bond chucks unload

Bond chucks cooling to RT

Bonded wafers unload to cassette

Bond chucks transferred to buffer station for reuse Bond chucks buffer station

Bond chucks moved to wafers unload stations

Fig 37.10 ● Process ﬂow for aligned plasma activated wafer-bonding process in a fully automated integrated equipment (high volume equipment solution).

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• Empty bond chuck is transferred to a buffer station from which it can be automatically loaded to optical aligner for next processes. • Cassette with bonded pairs is unloaded from equipment. The same types of equipment solutions are available for other different processes. If for the R&D and low volume production equipment choice is somehow clear

(each process step needs to run in individual equipment) for high volume integrated systems the conﬁguration needs to be very precisely deﬁned. Integrated systems can be conﬁgured as customized equipment dedicated to speciﬁc applications (especially when a certain degree of contamination control is mandatory) or as universal systems capable of accommodating various types of applications.

References 1. J. Haisma, G.A.C.M. Spierings, Contact bonding, including direct bonding in a historical and recent context of materials science and technology, physics and chemistry. Historical review in a broader scope and comparative outlook, Mat. Sci. Eng. R 37 (2002) 16–20. 2. G. Wallis, D.I. Pomerantz, Field assisted glass-metal sealing, J. Appl. Phys. 40 (10) (1969) 3946.

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3. http://www.evgroup.com 4. SEMI—Semiconductor Equipment and Materials International, http://www. semi.org 5. V. Dragoi, P. Lindner, M. Tischler, C. Schaefer, New challenges for 300 mm Si technology: 3d interconnects at wafer scale by aligned wafer bonding, Mat. Sci. Semicond. Proc. 5 (4–5) (2003) 425.

6. LeaDiCioccio, New heterostructures and 3D devices obtained at CEA-LETI by the bonding and thinning method, ECS Trans. 3 (6) (2006) 19. 7. Teﬂon® is a trade mark of DuPont. 8. PEEK™, also referred to as polyketones, are composite materials obtained from aromatic dihalides and bisphenolate salts by nucleophilic substitution.

38

Chapter Thirty Eight

Encapsulation by Film Deposition Rob N. Candler Department of Electrical Engineering University of California, Los Angeles, CA, USA

38.1 Introduction Encapsulation by deposition of a thin ﬁlm is an attractive alternative to wafer bonding due to the possibility of reduced thickness and area of a packaged device, as well as elimination of the need for a capping wafer. Surface micromachining advancements in the 1980s and 1990s enabled device and encapsulation layers each to be only tens of μm thick. By combining this with thinning of the wafer backside via chemical mechanical polish (CMP), a fully packaged MEMS device with thickness 100 μm could be realized. This reduced thickness could prove to be critical, as the consumer electronics market continues to push for smaller (in area and thickness) and cheaper sensors, with thicknesses of fully packaged sensors being pushed below 1 mm toward 500 μm. The primary beneﬁt ﬁlm deposition has over wafer bonding is reduced area and height of the packaged device. The reduced area comes by avoiding the large bond rings, which can be hundreds of μm wide, that are required for screen-printed glass frit-type bonding. While anodic bonding is an option that can reduce the bond ring footprint, challenges for it remain, such as overall thickness and sensitivity to wafer curvature. As mentioned above, there is pressure from the consumer electronics industry to reduce the thickness of fully packaged sensors. Two silicon wafers bonded together are already at the thickness limit for consumer sensors, and this is without even considering next-level packaging (e.g., injected molded plastic package). While the wafer thickness can be reduced, performing CMP on both wafers can be costly. Also, avoiding the raw material cost of an

additional wafer is also an advantage, assuming the cost of the additional fabrication steps in ﬁlm deposition do not cancel these savings. Despite the limitations of wafer bonding, it is a more mature technology than encapsulation by thin ﬁlm deposition, and many products packaged with wafer bonding are successfully on the market. However, recent applications requiring the cost and size reduction available with encapsulation by thin-ﬁlm deposition are beginning to come to market [1]. In the following sections, a variety of methods for encapsulating MEMS with ﬁlm deposition will be discussed, along with their respective advantages and limitations.

38.2 Packaging Needs It is worthwhile to examine the key requirements of packaging before discussing available technologies, since it is the requirements that should drive the technology selection. Robustness, a property strongly dependent on thickness of the package, is critical for stability of the encapsulation during back-end processing (e.g., wire bonding and injection molding) and subsequent use of the device. When encapsulating with a thin ﬁlm or encapsulation thickness is a concern because the encapsulation layer can deﬂect or break when subjected to post-encapsulation processes or even pressure differences between the cavity and ambient environment. Practically, this creates a tradeoff between encapsulation ﬁlm thickness and maximum unsupported area of the encapsulation over the device, where a thicker ﬁlm will provide a more robust encapsulation and allow 569

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for a larger unsupported area but will be more difﬁcult and costly to deposit. Cost is very important but also difﬁcult to compare across the wide range of available technologies. Generally, using materials and processes that already exist in CMOS technology can help reduce costs. CMOS compatibility is frequently listed as a beneﬁcial property of thin-ﬁlm encapsulation processes, as integration of the CMOS and MEMS on the same wafer can provide performance and cost beneﬁts. This integration is not always implemented, due to the complexity of combining a zero-level MEMS packaging process with a CMOS process. For CMOS-compatible thin-ﬁlm encapsulation, two general approaches exist: (1) MEMS-last (after CMOS) processes that use low temperature processes to avoid problems with the CMOS thermal budget, and (2) MEMS-ﬁrst (before CMOS) processes that use a silicon encapsulation that can withstand subsequent CMOS processes. Maximum gap between structures is important, as it determines the maximum deﬂection of the devices. While not critical for some applications such as resonators, it is important for others such as gyros, where a large deﬂection is desirable. Package pressures should generally be at low (i.e., vacuum) levels for vibrating devices (e.g., resonators and resonant gyroscopes) and at high levels for devices that require damping (e.g., accelerometers). Packaging pressure is determined by the pressure at the ﬁnal sealing step, outgassing of encapsulated materials, or postsealing gas diffusion steps. Hermeticity is critical for packaging of most sensors but is not always reported, as data collection for longterm hermeticity can require several months or more of dedicated experiments. Deposition of sealing material onto the device can be detrimental because it changes both the structure dimensions and gaps. Thermal budget is important not only for potential CMOS integration but also for some applications where metal devices need to be encapsulated (e.g., RF MEMS switches).

38.3 Technologies and Methods All methods described for thin-ﬁlm encapsulation begin with deﬁnition of the MEMS device on top of a sacriﬁcial layer followed by covering of the device with another sacriﬁcial layer (e.g., silicon dioxide, photoresist, other polymers). The maximum gap width that can be etched into the device is often determined by the relative thickness of this top sacriﬁcial layer to the underlying device layer (Figures 38.1 and 38.2). A thin ﬁlm of material (e.g., metal, silicon, silicon dioxide, silicon nitride, or polymer) is deposited over 570

Fig 38.1 ● For the case where the device layer, tdevice, is thicker than the sacriﬁcial sealing layer (tcovering), tcovering must be at least half of wgap for an effective seal. This typically sets wgap to a few μm or less.

Fig 38.2 ● For the case where the sacriﬁcial sealing layer, tcovering, is thicker than the device layer, there typically is not a gap limitation, because the sealing layer can ﬁll up the gaps. However, it will likely limit the device layer, tdevice, to 10 μm (with 3 μm being more typical) because of difﬁculty depositing thick sacriﬁcial layers.

the sacriﬁcial covering layer and structured to allow for release of the sacriﬁcial layers above and below the device. At this point, there are three fundamental methods by which thin-ﬁlm encapsulations are constructed to allow removal of the sacriﬁcial layers (and therefore release of the device): side access port, top access port and permeable material (Figure 38.3). The relative merits of the three methods for release port are compared in Table 38.1. After release of the device (e.g., via liquid phase etch, vapor phase etch, or thermal decomposition), the release paths are sealed with an additional sealing step. A common requirement for this seal is that some measure be taken to avoid electrically shorting the device during the sealing step. Methods that can be used to avoid this electrical shorting include sealing with a dielectric material or avoiding deposition on the entire structure by using (1) a layer that seals quickly, (2) a nonconformal deposition method, or (3) a selective sealing process. One sealing technique frequently used is commonly referred to as “reactive sealing”; in this case a chemical reaction

Encapsulation by Film Deposition

Substrate

CHAPTER 38

Substrate

Fig 38.3 ● Options for release path when encapsulating with a thin ﬁlm include (a) side access port, (b) top access port, and (c) permeable material. All pictures are shown before (left) and after (right) etch of sacriﬁcial material.

occurring at the wafer surface results in material deposition and cavity sealing. Techniques for each of the three methods and their reported performance are given in the following sections.

38.3.1 Side Access Port One of the early references to encapsulation with a thin ﬁlm was a concept for pressure sensors, in which the encapsulation layer was also the deﬂecting membrane [2].

A very innovative approach was developed that used epitaxial deposition for both the structural and sacriﬁcial layers [3]. Selective release of the structure was accomplished by electrochemical etching, with the sacriﬁcial and structural layers having different levels of in-situ doping for selective etching. Sealing of the wafer was also performed in a silicon epitaxial reactor, and the device was annealed in a nitrogen furnace to force the hydrogen in the cavity to diffuse out, leaving a pressure below 0.15 Pa. The 10-μm-thick cap could withstand 100 MPa pressure with the robustness aided by the 571

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Table 38.1 Comparison of different release port methods

Release port method

Advantage

Disadvantage

Side access port

Robust cap possible

Slow release

Little deposition on structure Top access port

Permeable material

Robust cap possible Quick release

Signiﬁcant deposition on structure

Little to no deposition on structure

Membrane not robust when thin

short cap span in one direction, and long-term stability was reported to be within 0.01% for 1 year. A later version of the technology involved wet etching of the wafer backside to create a resonant pressure sensor [4]. Silicon nitride was used around the same time as an alternate material to seal cavities [5]. Points of interest include release of the structure via sublimation and use of a thin device layer to enable full reﬁll of the structure and large displacement structures, as illustrated in Figure 38.2. Large displacement structures were also fabricated in a silicon nitride-sealed cavity by depositing a thick (7 μm) silicon dioxide sacriﬁcial covering layer [6]. In other work, silicon nitride was used to provide an optically transparent window for sealing polysilicon microlamps [7]. A 2.5-μm encapsulation was deposited, and a gettering from the microlamp was identiﬁed as a potential cause of a decrease in ﬁnal cavity pressure. Another technique combined sublimation at ambient pressure for device release before sealing with silicon nitride [8]. The inﬂuence of the reactive sealing process on ﬁnal seal pressure via the number of reactants and products is given by

Pcavity Pprocess

Tambient nproducts Tprocess nreactants

(38.1)

where Pcavity is the pressure of the cavity after sealing, Pprocess is the pressure during the sealing process, Tprocess is the temperature during the sealing process, Tambient is the temperature at which the sensor is operator, and nproducts/nreactants is the ratio of moles of products to reactants in the reactive sealing process. A resonant pressure sensor was reported with short-term stability as good as 0.01 ppm for 27000 hours of continuous operation without failing [9], and a cavity sealed reactively with polysilicon achieved a pressure 2 mPa at 510°C for several hours with no long-term drift of pressure [10]. More recently, an RF MEMS switch was 572

encapsulated and sealed with silicon dioxide and silicon nitride with little change in device performance [11]. Alternative sealing materials have also been considered. A comparison of silicon and aluminum sealing showed that the nonconformality of aluminum evaporation prevented the 50 nm of deposition of sealing material on the device caused by silicon sealing [12]. Challenges for metal sealing include management of stress as well as the trade-off between faster release time with quicker sealing time (and less deposition of the sealing material on the structure) encountered when sizing release access ports. The ability to deposit thick (e.g., 40 μm) layers with electroplating allowed for nickel to be used as an encapsulation layer [13]. The process was low temperature (250°C) with an 8-μm photoresist layer for sacriﬁcial covering of the device. An 800-μm 800-μm cap was released with 5 μm of deﬂection. One problem associated with this method was outgassing after the low temperature seal. Polycrystalline diamond is another material used for encapsulation and is favorable because of its chemical and mechanical robustness. A process was proposed where selective growth of polycrystalline diamond was used to avoid deposition of the diamond on the structure, and electrical feedthroughs through the encapsulation were deﬁned with doping [14]. However, one issue that remained was deﬂection of the 4-μm encapsulation layer.

38.3.2 Top Access Port An early example of MEMS encapsulated with a thin ﬁlm using top-etch access holes involved a nitride encapsulation and MEMS-ﬁrst integration with CMOS. Special attention was paid to annealing the MEMS to avoid issues of thermal stress during CMOS processing [15]. Another approach involved a process that did not violate the temperature budget of CMOS, allowing for the possibility of MEMS after CMOS integration [16]. Also of interest in this approach is the use of hydroﬂuoric acid (HF) vapor for structure release without the use of critical point drying (CPD) to avoid stiction/adhesion. The encapsulation was able to withstand 100 Bar, with pillars intermittently used to assist in supporting the encapsulation. Another method used focused ion beam deposition of silicon dioxide to seal small openings (14 μm 14 μm) by creating a series of overlapping structures [17]. Epitaxial deposition of polysilicon has been used to deposit a 20-μm-thick encapsulation layer that was sealed with silicon dioxide with electrical contacts routed vertically through the encapsulation [18]. A further development sealed the device with selective epitaxy of polysilicon, with the high temperature (1000°C) of the sealing process leading to a high degree of long-term stability (1 year) [19, 20]. In other work, silicon was used

Encapsulation by Film Deposition

as an alternative to silicon dioxide as a sacriﬁcial covering layer where silicon was both the device and sacriﬁcial material, and silicon dioxide was used to isolate the sacriﬁcial silicon from the device silicon [21]. This provided the advantage of relatively fast rates of silicon deposition but had the drawback that any pinholes in the isolating silicon dioxide could allow the device silicon to be etched along with the sacriﬁcial silicon. A low-temperature process (120°C) was developed for encapsulation of RF MEMS switches. The process involved electroplating metal onto a photoresist mold, creating holes smaller than those that could easily be lithographically deﬁned. A sacriﬁcial photoresist was removed with acetone to release the device, followed by sealing with a viscous photoresist. The sealing photoresist did not provide hermeticity, but this was not seen as a necessary feature for the given application [22]. Another low-temperature (180°C) process was proposed that involved plating aluminum over a photoresist mold for formation of the cap layer. The sealing step was performed by reﬂow of indium that had been subsequently deposited [23].

38.3.3 Permeable Material Permeability of a material can be achieved in one of two ways to allow for removal of sacriﬁcial products: (1) by depositing a material that is thin enough to be permeable to etch chemicals and byproducts, or (2) by purposefully etching a material to generate a porous structure. The main challenge of the ﬁrst method is that a support structure typically needs to be added to provide mechanical strength to the thin membrane such that only small windows of the thin membrane can exist in a continuous span. The cost for this is extra processing steps. For the second method, an etch, typically electrochemical, needs to be developed to achieve the appropriate pore size and density. In previous work, polysilicon ﬁlms 100 nm thick were used as permeable membranes to allow etching of sacriﬁcial silicon dioxide by HF [24, 25]. Heavy doping was used to enhance permeability [25], and a pressure change in encapsulated devices 15% was reported over a period of 6 months [24]. A gyroscope was encapsulated with permeable polysilicon sealed by silicon nitride, and cavity pressure remained under 400 Pa for 20 months, although some increase in pressure was measured during that time [26].

CHAPTER 38

Also interesting to note is that pillars were placed every 75 μm to limit deﬂection of the cap under the pressure difference between the cavity and ambient environment. One case of porosiﬁcation without electrochemical etching involved balancing tensile and compressive stresses in a onestep LPCVD (Low Pressure Chemical Vapor Deposition) polysilicon deposition process [27]. With this method and CPD, membranes as large as 9 mm 12 mm were released. A ﬂexible process for encapsulation of devices utilized a photodeﬁnable polymer with thermally decomposed sacriﬁcial material [28, 29]. The polymer encapsulation was spin coated for thin gaps or dispensed for larger gaps and topology [28]. Resonant frequency (1.3%) and quality factor (10%) changes or shifts before and after packaging of resonators were observed, possibly due to residues [29]. Because the polymer seal is not hermetic, an additional metal coating was proposed to improve hermeticity [28]. Electrochemical etching was used to porosify a 1.5 μm polysilicon layer [30], which is stiffer than a layer thin enough to be permeable and can therefore span larger distances without the need for supporting posts or deposition of a reinforcing layer. No deposition was seen on the structures after reﬁll with polysilicon, and the pressure was unchanged for 1 year. One challenge with this technique is that stress induced during the porous etch requires an anneal immediately after completion of the etch, which limits the process to die-level rather than wafer-level applications. Additional work used porous alumina to exploit its low deposition temperature and dielectric properties [31, 32].

38.4 Summary Encapsulation via deposition of a thin ﬁlm has seen many forms, with encapsulation materials varying from silicon to dielectrics, metals, and polymers. The method of access can be from the side, top, or through the material, with trade-offs existing between release time and deposition on the structure. Additional trade-offs exist between thickness of encapsulation (time required and ﬁlm stress) and maximum span of unsupported cap. Overall the variety of techniques for encapsulation with a thin ﬁlm has covered a range of devices including pressure sensors, accelerometers, gyroscopes, resonators, and RF switches.

References 1. A. Partridge, M. Lutz, B. Kim, M. Hopcroft, R.N. Candler, T.W. Kenny, et al., MEMS resonators: getting the packaging right, in: SEMICON-Japan, 2005.

2. H. Guckel, D.W. Burns, Planar processed polysilicon sealed cavities for pressure transducer arrays, Proc. Int. Electron Devices Meeting (1984) 223–225.

3. K. Ikeda, H. Kuwayama, T. Kobayashi, T. Watanabe, T. Nishikawa, T. Yoshida, et al., Three-dimensional micromachining of silicon pressure sensor integrating resonant strain

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gauge on diaphragm, Sens. Actuators A A21–A23 (1990) 1007–1010. K. Ikeda, H. Kuwayama, T. Kobayashi, T. Watanabe, T. Nishikawa, T. Yoshida, et al., Silicon pressure sensor integrates resonant strain gauge on diaphragm, Sens. Actuators A A21–A23 (1990) 146–150. H. Guckel, J.J. Sniegowski, T.R. Christenson, F. Raissi, The application of ﬁne-grained, tensile polysilicon to mechanically resonant transducers, Sens. Actuators A A21–A23 (1990) 346–351. L. Lin, R.T. Howe, A.P. Pisano, Microelectromechanical ﬁlters for signal processing, J. Microelectromech. Syst. 7 (3) (1998) 286–294. C.H. Mastrangelo, J.H.-J. Yeh, R.S. Muller, Electrical and optical characteristics of vacuum-sealed polysilicon microlamps, IEEE Trans. Electron Devices 39 (6) (1992) 1363–1375. R. Legtenberg, H.A.C. Tilmans, Electrostatically driven vacuumencapsulated polysilicon resonators: Part I. Design and Fabrication, Sens. Actuators A A45 (1994) 57–66. D.W. Burns, J.D. Zook, R.D. Horning, W.R. Herb, H. Guckel, Sealed-cavity resonant microbeam pressure sensor, Sens. Actuators A A48 (1995) 179–186. J.D. Zook, W. Herb, A. Yongchul, H. Guckel, Polysilicon sealed vacuum cavities for microelectromechanical systems, J. Vac. Sci. Technol. A (1999) 2286–2294. K.D. Leedy, R.E. Strawser, R. Cortez, J.L. Ebel, Thin-ﬁlm encapsulated RF MEMS switches, J. Microelectromech. Syst. 16 (2) (2007) 304–309. M. Bartek, J.A. Foerster, R.F. Wolfenbuttel, Vacuum sealing of microcavities using metal evaporation, Sens. Actuators A 61 (1997) 364–368. B.H. Stark, K. Najaﬁ, A lowtemperature thin-ﬁlm electroplated metal vacuum package, J. Microelectromech. Syst. 13 (2) (2004) 147–157.

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14. X. Zhu, D.M. Aslam, CVD diamond thin ﬁlm technology for MEMS packaging, Diamond Relat. Mater. 15 (2006) 254–258. 15. J.H. Smith, S. Montague, J.J. Sniegowski, J.R. Murray, R.P. Manginell, P.J. McWhorter, Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS, Proc. SPIE Micromachin. Microfab. 1996. 16. R. Aigner, K.-G. Opperman, H. Kapels, S. Kolb, “Cavity Micromachining” technology: zeropackage solution for inertial sensors, Proc. Transducers (2001) 186–189. 17. R. Puers, S. Reyntjens, Fabrication and testing of custom vacuum encapsulations deposited by focused ion beam direct-write CVD, Sens. Actuators A A92 (2001) 249–256. 18. R.N. Candler, W.-T. Park, H. Li, G. Yama, A. Partridge, M. Lutz, et al., Single wafer encapsulation of MEMS devices, IEEE Trans. Adv. Packag. 26 (3) (2003) 227–232. 19. R.N. Candler, M. Hopcroft, B. Kim, W.-T. Park, R. Melamud, M. Agarwal, et al., Long-term and accelerated life testing of a novel single-wafer vacuum encapsulation of MEMS resonators, J. Microelectromech. Syst. 15 (6) (2006) 1446–1456. 20. B. Kim, R.N. Candler, M. Hopcroft, M. Agarwal, W.-T. Park, T.W. Kenny, Frequency stability of wafer-scale ﬁlm encapsulated silicon based MEMS resonators, Sens. Actuators A A136 (2005) 125–131. 21. A. Hoechst, R. Scheuerer, H. Stahl, F. Fischer, L. Metzger, R. Reichenback, et al., Stable thin ﬁlm encapsulation of acceleration sensors using polycrystalline silicon as sacriﬁcial and encapsulation layer, Sens. Actuators A A114 (2004) 355–361. 22. A.J. Gallant, D. Wood, Surface micromachined membranes for wafer level packaging, J. Micromech. Microeng. 15 (2005) S47–S52. 23. R.H. Rico, J.-P. Celis, K. Baert, C. Van Hoof, A. Witvrouw, A new generic surface micromachining module

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for MEMS hermetic packaging at temperatures below 200°C, microsyst. Technol. 13 (2007) 1451–1456. K.S. Lebouitz, A. Mazaheri, R.T. Howe, A.P. Pisano, Vacuum encapsulation of resonant devices using permeable polysilicon, in: Twelfth IEEE International Conference on Micro Electro Mechanical Systems. MEMS ‘99, 1999, pp. 470–475. Y. Kageyama, T. Tsuchiya, H. Funabashi, J. Sakata, Polycrystalline silicon thin ﬁlms with hydroﬂuoric acid permeability for underlying oxide etching and vacuum encapsulation, J. Vac. Sci. Technol. A 18 (4) (2000) 1853–1858. T. Tsuchiya, Y. Kageyama, H. Funabashi, J. Sakata, Polysilicon vibrating gyroscope vacuumencapsulated in an on-chip micro chamber, Sens. Actuators A 90 (2001) 49–55. G.M. Dougherty, T.D. Sands, A.P. Pisano, Microfabrication using one-step LPCVD porous polysilicon ﬁlms, J. Microelectromech. Syst. 12 (4) (2003) 418–424. P. Monajemi, P.J. Joseph, P.A. Kohl, F. Ayazi, Wafer-level MEMS packaging via thermally released metal-organic membranes, J. Micromech. Microeng. 16 (2006) 742–750. P.J. Joseph, P. Monajemi, F. Ayazi, P.A. Kohl, Wafer-level packaging of micromechanical resonators, IEEE Trans. Adv. Packag. 30 (1) (2007) 19–26. R. He, C.J. Kim, On-wafer monolithic encapsulation by surface micromachining with porous polysilicon shell, J. Microelectromech. Syst. 16 (2) (2007) 462–472. R. He, C.J. Kim, A low temperature vacuum package utilizing porous alumina thin ﬁlm encapsulation, Proc. IEEE MEMS (2006) 126–129. R.H. Rico, B. Du Bois, A. Witvrouw, C. Van Hoof, J.-P. Celis, Fabrication of porous membranes for MEMS packaging by one-step anodization in sulfuric acid, J. Electrochem. Soc. 154 (9) (2007) K74–K78.

39

Chapter Thirty Nine

Via Technologies for MEMS Kimmo Henttinen Okmetic Oyj, Vantaa, Finland

Advanced packaging methods are needed to make miniaturized integrated devices containing chips that have been fabricated using various technologies. Wafer level 3-dimensional (3D) integration is an emerging technology where planar devices on wafers are stacked and interconnected using through wafer vias (Figure 39.1). The main drivers for 3D integration are better electrical performance, lower power consumption and noise, improvement of form factor, lower cost and increase of the functionality of a device. 3D integration is a hot research and development topic because of huge market potential for 3D stacking and heterogeneous integration of various materials and devices. Today, this technology already exists in production for some image sensors, and it is now expanding to memories and processors and MEMS packaging. The implementation of the 3D integration means that one has to master several techniques and process sequences namely, through wafer via fabrication, wafer thinning and alignment and bonding of thin chips with vias. The various approaches for 3D can be classiﬁed

according to the sequence in which the preceding processes are carried out. There already exist many good articles and books about 3D integration [1] and we are not trying to cover the whole subject. The main manufacturing techniques for through silicon vias (TSV) and through glass vias are presented in this chapter. In MEMS area, through wafer vias open a way to wafer level packaging with signiﬁcantly reduced die sizes and heterogeneous integration of MEMS, ICs and sensors. In general, TVS are categorized by the time when the vias are fabricated relative to the IC or MEMS fabrication process. The major classiﬁcations include the following [1]: • TSVs fabricated either before or during the IC or MEMS fabrication process • TSVs fabricated after the complete IC or MEMS fabrication The ﬁrst one can still be divided to front end of line (FEOL) TSVs where vias are prepared before the IC wiring process and to back end of line (BEOL) TSVs where vias are prepared during the IC wiring process.

Fig 39.1 ● Schematic illustration of 3D integration of various devices (a) using vertical TVS and (b) the use of the through wafer vias in the MEMS packaging.

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Highly doped polysilicon and single crystalline silicon vias fall into the 1st category and they are covered in Sections 39.1.1 and 39.1.2. Metallic TSVs that are fabricated in the BEOL can consist of either tungsten (W) or copper (Cu) and they are described in Section 39.1.3. Silicon vias can tolerate high temperatures, and in principle a wafer with conductive and insulated silicon vias can go through the complete manufacturing process of MEMS or ICs. Metallic vias, like copper vias, have to be processed at low temperatures, and they also need special precautions in order to prevent harmful diffusion of metals into the active silicon crystal that may cause device contamination. Diffusion barriers for copper are described, for example, in the references [1] and [2]. The conventional plasma etching techniques cannot be used for the patterning of copper lines due to lack of volatile copper species at low temperatures. Therefore, the deep submicron IC metallizations are realized by using so called damaschene process, that is, ﬁlling of dry etched trenches with electroplated copper followed by chemicalmechanical polishing (CMP) of copper. Nowadays, very similar methods are also used to prepare through silicon Cu vias, although each process step has to be adjusted to meet the requirements of TSVs, instead of damaschene process. In copper damaschene the depth of the etched trenches is less than 1 μm, whereas the depth of the TSV can be much above 100 μm.

39.1 Overview of TSV Technologies The main obstacles for commercial implementation of MEMS devices are often related to packaging and interconnection problems because many applications need full hermetic cavity through the use of getters and specialized bonding technologies. Silicon wafer with insulated electrical vias can be used as an interposer between MEMS and ASIC chip providing a route to true wafer level packaging concept. The beneﬁts of such silicon interposer include good thermal match between the chips and the interposer and furthermore, the possibility of integrate passive devices, cavities and micro-cooling channels into the via wafer. Via wafers can also be used for the wafer level packaging or encapsulation of MEMS devices by bonding via wafer onto the MEMS wafer. Usually, the main purpose of the through wafer interconnects is to get electrical access to the device from the backside of the device. This way less space is needed for interconnects on the front that is the active side of the chip. The most common way to prepare through wafer vias is to ﬁrst fabricate a hole through the wafer and electrically insulate the hole and subsequently ﬁll it with conductive material. The hole can be fabricated either 576

through a wafer or the other option is to prepare a blind hole, that is, a hole that is not etched totally through the wafer. Blind holes can normally be processed smaller than the through holes making the hole ﬁlling easier and more cost effective. It is very challenging to process wafers that are thinner than 100 μm in thickness, and the wafer handling complications increase with wafer diameter. Presently, most via processes on IC wafers are aiming for individual IC chips considerably thinner than 100 μm. The same trend is also true for MEMS wafers that make blind vias attractive also for MEMS applications. There exist many techniques to fabricate holes into silicon wafers. The most common methods for 3D devices are deep silicon etching (DRIE) and laser ablation. Sawing, sand blasting and ultrasonic can also be used for the machining of silicon, but they are not generally applicable to vias because of contamination, process integration and other issues. Standard silicon wet etching techniques and electrochemical etching can also be employed for the hole fabrication with some limitations. DRIE method was introduced by Bosch in the mid-1990s and commercialized by several equipment manufactures [3]. The method uses SF6 gas to rapidly etch silicon and C4F8 to generate ﬂuorocarbon polymer deposit to passivate the sidewalls of the vias during the etching. The process is capable of high selectivity and very vertical via sidewalls. Nowadays, the Bosch process is the workhorse of modem Si MEMS technology. DRIE is described indepth in other chapters of this book. The basics of laser ablation of silicon are presented in Section 39.1.3.

39.1.1 Single Crystal Vias Single crystal silicon vias can be fabricated from highly doped standard silicon wafers by insulating a section of silicon laterally (Figure 39.2). The idea is to etch a trench that forms a closed loop and ﬁll it with an isolating material [4]. In order to keep the silicon via plug in position, the trench is not etched completely through a wafer. Following the trench etch, the wafer is subjected to a high temperature ﬁlling of the trenches by a dielectric

Fig 39.2 ● Schematic cross-section of via wafer with etched and dielectric ﬁlled trenches. Source: Photo reproduced by permission of Silex Microsystems AB.

Via Technologies for MEMS

material. Reliable insulation can be achieved with thermal oxidation. After thermal oxidation the open space in the trenches can be ﬁlled with chemical vapor deposition (CVD) of silicon oxide or polysilicon. Finally, a chemicalmechanical polishing (CMP) process is applied to the backside of the wafer. This step removes the material that still keeps the silicon plugs connected to the bulk. It has been reported that single crystal silicon vias can be formed through a 600 μm silicon using a sub 50 μm pitch. As the via pitch approaches 50 μm, the neighboring vias have to share the same isolating trench. The typical trench width is in the order of 10–20 μm. The resistance of the vias depends on the resistivity of the starting wafer material, that is, dopant type and concentration and also on the dimension/geometry of the vias. The maximum dopant concentration is limited by the solubility of the dopant into the silicon crystal. N-type crystals can have higher dopant concentration than P-type crystals. Typically, the measured resistance for the vias through standard silicon wafers is from few ohm to 100 ohm. These resistance values are too high to be used for any real RF-applications. Another limitation is that the starting wafer material has to be highly doped in order to achieve reasonable conductivity for the via. For example, in some detector applications high resistivity substrate material might be needed. Thermal oxidation yields reliable insulation between the vias so that the isolation resistance is typically over 10 Mohm. The wafer with doped and insulated silicon vias can go through standard MEMS processing because it can stand even temperature over 1000°C. This type of via ﬁrst process is usually preferred in MEMS applications, because the completed MEMS device is often very delicate and cannot go through any further postprocessing steps. In the previous method the vias were insulated by the ﬁlling of the etched trenches. It is also possible to machine or etch recess areas on highly doped starting wafer and subsequently apply an electrically insulating material, such as glass, in molten state onto the machined side of the substrate (Figure 39.3) [5–7].

Melted glass

CHAPTER 39

First the silicon surface is etched or otherwise machined to obtain silicon bumps, which are required to extend through the glass layer. The silicon is also processed for deep narrow grooves that almost separate the silicon areas from each other, only small isthmuses are left at the bottom of the silicon wafer. The shape and dimensions of the areas and grooves are determined by the processing methods used for the machining. Typical machining methods are standard silicon wet and dry etching techniques and sawing. After groove preparation the glass powder is spread [5, 6] or a glass wafer is attached [7] over the wafer surface and melted until the glass ﬁlls the grooves. Subsequently, both sides of the wafer are ground to expose the silicon bumps on the front side and to expose the glass ﬁlled grooves on the backside. Alternatively, the isthmuses may be removed by grinding after the capping wafer is bonded to the MEMS wafer. The silicon areas are totally insulated from each other, when the silicon isthmuses are removed. Glass surface on the front side can be polished in order to obtain bondable surface. As the used glass material contains metallic impurities, like sodium, the via wafer can be bonded using the anodic bonding method. This enables a route to wafer level encapsulation of MEMS devices, because anodic bonding yields reliable hermetic joints, and the doped silicon vias enable electrical access into the capped device without destroying the hermecity of the package. The horizontal glass layer thickness on the surface of the via wafer is typically about 100 μm and the vertical grooves can be about 200 μm wide if manufactured by dicing saw or 50–1000 μm when manufactured by RIE. The resulting wafer may consist of thousands of insulated silicon islands in a glass matrix. Each isolated island may function as an electrical feed through (i.e., via) that has low parasitic capacitance and high isolation resistance. The resistivities of the vias are also in this case dictated by the dimensions of the vias and the resistivity of the starting wafer. The mechanical strength of this type of composite wafer poses some limitations to the lowest achievable thickness of the wafer, for example, VTI technologies has reported the lowest freestanding thickness of about 400 μm and lowest thickness 80 μm when grinding is done after bonding.

Grinding and polishing

39.1.2 Polycrystalline Silicon Vias Highly doped Si

Grinding

Fig 39.3 ● Schematic cross-section of a via prepared by glass inlay method [5, 6]. Glass is melted until it ﬁlls the surface with bumps and the machined grooves. Subsequently, wafer is ground on both sides and the front side is polished for anodic bonding resulting in isolated silicon islands.

Polysilicon vias have been reported for sensor and MEMS applications [8, 9]. From the integration point of view, the front-end polysilicon vias are relatively easy to integrate into the industrial production. A silicon wafer with insulated and conductive polysilicon vias is essentially like a standard silicon wafer for the device manufacturer. Typically, the process ﬂow consists of through 577

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(b)

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(d)

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Fig 39.4 ● Typical process ﬂow for in-situ doped polysilicon vias consists of DRIE etching of the blind hole into the silicon (a), insulation of the hole with thermal oxidation (b), ﬁlling of the hole with LPCVD in-situ doped polysilicon (c) and removal of the excess polysilicon (d). Finally, the wafer is thinned down until the polysilicon vias are exposed. The thinning can be carried out either before or after the device manufacturing.

Thermal oxide Void

Doped poly-Si

<Si>

Wafer surface

Fig 39.5 ● Cross-section SEM image of the mouth of the polysilicon ﬁlled via. The diameter of the via is about 50 μm and the depth of the via (wafer thickness) is 400 μm. The narrowing at the mouth of the via has caused a void or unﬁlled region that is about 45 μm below the wafer surface.

hole or blind hole preparation, insulation of the holes for example with thermal oxidation, the ﬁlling of the hole with polysilicon and ﬁnal removal of the excess polysilicon (Figure 39.4). The polysilicon can be doped with diffusion process or alternately in-situ doped LPCVD polysilicon deposition can be used. If in-situ doped LPCVD deposition is used for the ﬁlling of the via, the dopants have to be electrically activated by high temperature annealing (~1000°C). Thermal annealing can also be used to adjust the stresses of the polysilicon layer. In principle, the polysilicon via technology is versatile, but it has some technical challenges that are connected to uniformity of the polysilicon growth and via ﬁlling. The conformality of silane based LPCVD process is not ideal and, therefore, it is easy to generate a void inside the via (Figure 39.5) that may cause reliability problems. Therefore, it is very important to control the shape of the via so that complete via ﬁlling can be achieved within reasonable process time. 578

Once again the resistance of a via is governed by the dopant concentration and the via dimensions. Theoretically, the maximum conductivity is limited by the solubility limit of the dopant atoms. In practice the LPCVD polydeposition is carried out at the upper temperature range of poly process in order to obtain reasonable growth rate. However, the achievable dopant concentration with in-situ doping process decreases with increasing deposition rate of polysilicon. At high process temperatures the poly deposition is limited by the mass transfer, that is, transfer of reactants into the via.

39.1.3 Metallic Vias Two major process steps for metallic vias are via etching/machining and via ﬁlling. Via ﬁlling includes lining of the deep vias with an inorganic or organic insulator, deposition of a diffusion barrier and/or adhesion layer and subsequent growth of the conductor material that is typically copper or tungsten. In some applications only lining of the etched via with metal is acceptable but in most cases complete via ﬁlling is required. An unﬁlled space or void is always a reliability risk especially during subsequent wet processing steps. The typical process ﬂows for metallic vias are depicted in Figure 39.6. The ﬁlling of the etched vias with metal is a time consuming and expensive process step. Therefore, wafer thinning is needed so that smaller vias can be prepared. When chips are stacked on top of each other, the wafer thinning is normally needed to reach the thickness speciﬁcations of the complete packaged device. In practice, the metallic vias can be machined either before or after the wafer thinning. For thick wafers, blind vias are generally employed, that is, the vias are not etched through the wafer but the etching is stopped at the desired depth. A conformal metallic seed layer for electroplating is required if blind vias are used. It is very important to have uniform and

Via Technologies for MEMS (a)

Blind vias

(b)

CHAPTER 39

Through vias

Hole patterning (a) or wafer thinning and patterning b) Blind via etching (a) or through wafer etching up to etch-stop layer (b) Insulation, diffusion barrier and seed metal deposition Cu plating (a) or opening of via bottom followed by plating (b) Removal of excess Cu by polishing

Fig 39.6 ● The simpliﬁed process ﬂows for metallic TSVs. The vias can be fabricated either before (a) or after (b) the wafer thinning. If the vias are fabricated prior to wafer thinning, blind vias are used (a). Blind vias call for the deposition of a conformal seed metal layer. If the vias are fabricated after wafer thinning, the vias can be etched through the wafer (b).

continuous seed metal layer inside the via before starting the electroplating. This is one of the challenges for the blind vias, because conventional thin ﬁlm sputtering techniques cannot be utilized for seed metal deposition into high aspect ratio vias. This process complication can be avoided if the vias are etched totally through the wafer. In this case, the seed metal layer can be sputtered by conventional means on top of the thin ﬁlm that was used as an etch-stop layer for the DRIE etching [10]. The other way to get a seed layer to the via bottom is to bond a wafer with through vias to another wafer with the seed metal ﬁlm [11]. The time required to fully ﬁll the via is normally shorter for blind vias than for through vias. However, the electroplating process is more challenging for blind vias than for through vias. The chosen via ﬁll approach inﬂuences the subsequent post-processing and process integration, because electroplating, wafer handling and metallization/interconnections schemes have to be adjusted accordingly. The excess copper (Cu overburden) has to be removed after the via ﬁlling. This is generally carried out using chemical-mechanical polishing [12]. Sometimes, copper is electroplated through a photoresist mask allowing the creation of a copper stud on top of the ﬁlled via. This reduces the Cu overburden on a wafer surface, but it may cause other process and integration difﬁculties. One has to master several challenging process techniques in order to economically fabricate metallic vias. The main problems are related to process integration issues because metallic vias, like copper vias, are normally fabricated on pre-processed wafers containing temperature sensitive structures and materials. Therefore, all via process steps have to be carried out at low temperatures. Also, special care is needed in order to block harmful diffusion of copper into the active

silicon crystal. There are also many problems related to wafer thinning and handling of thin processed wafers. One big challenge is the growth of conformal insulator, diffusion barrier and seed metal layers into high aspect ratio vias. The different methods for metal deposition that have been studied for through silicon deep vias are CVD, physical vapor deposition (PVD), electroless deposition and electrodeposition (electroplating). PVD does not provide acceptable ﬁll for high aspect ratio (7:1) vias and CVD is costly and better suited to small features rather than through wafer vias. Both CVD and PVD are more suitable for the lining of via walls with metals than for the complete hole ﬁlling. Tungsten metal CVD is suited for complete via ﬁll with lateral via width up to about 3 μm even at high aspect ratios. High stresses limit the use of W CVD layers for larger vias sizes. In the industry PVD and CVD are currently the methods of choice for the deposition of seed metal layer which acts as a base layer to grow copper by subsequent electroplating. Electroless deposition and electrodeposition are wet processes where metal ions in the wet solutions are converted to metallic form by providing electrons to the solution. In the electroless processes the electrons are provided by the reducing agent in the solution, whereas in the electroplating the electrons are provided by external power supply.

39.1.4 Laser Ablation of Via Holes TSV process begins conventionally with the machining of the via or hole into the silicon using deep silicon etching (DRIE). The details of DRIE etching of silicon are given in the other chapters of this book. The other 579

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common way to drill via holes or blind vias into silicon is laser drilling that is also known as laser ablation. Laser ablation is a process of removing solid material by irradiating it with a pulsed laser beam. The depth over which the laser energy is absorbed, and thus the amount of material removed by a single laser pulse, depends mainly on the optical properties of the material and the laser wavelength. Laser ablation processes for TSVs utilize focused and pulsed UV-light to drill holes into the wafers. Consecutive sequences of laser pulses are focused to the same point to drill a via of ﬁxed depth and diameter. Laser pulses can vary over a very wide range of duration (milliseconds to femtoseconds) and of ﬂux and can be precisely controlled. This makes laser ablation very valuable for both research and industrial applications. Tools use step and scan architecture where laser beam is typically moved by rapid optical galvanometer within the scanning ﬁeld. The movement between scanning ﬁelds is performed by linear stages. The drill rate (i.e., vias/ second) depends on via size (diameter, depth) and density. The die size also inﬂuences the throughput because the scanning ﬁeld may cover one or several dies. Laser drilling is a ﬂexible process and it can be employed for both front end and back end TSVs. With laser processing one can eliminate the need for various expensive lithographic steps, because the via positions are programmed by CAD on the tool. This enables rapid setup times and signiﬁcantly reduced the cost of the ownership. Laser process is also less selective than DRIE to various materials and is suitable even for patterned and structured wafers comprising oxide, nitride, metals and unpolished surfaces. Although laser techniques offer many beneﬁts there are some disadvantages compared to DRIE and other etching methods. One is thermal effect generated by a laser beam that is punched to substrate with high energy. This may inﬂuence active devices or structures. However, it has been demonstrated that UV laser prepared structures can be within 2 μm to an active device without producing device degradation [13]. A second disadvantage is the silicon debris that is splashed from the melted silicon. This Si debris is hard to remove with traditional silicon cleaning processes. The third limitation is that holes smaller than 5–10 μm in diameter cannot be obtained by current commercial laser machines. However, the natural sidewall angle for laser machined vias is about 85°, which makes them suitable for subsequent insulator, barrier and seed layer deposition by PVD methods. The surface ﬁnish of the sidewall of the via is strong function of the drilling rate. Rapid drilling typically produces rough sidewalls making complications for via ﬁlling. Memory and image sensor manufacturers have already reported the use of laser ablation for the fabrication of vertical 3D interconnects [14, 15]. 580

39.1.4.1 Insulation of Via Holes After hole drilling a conformal dielectric layer needs to be grown inside the via for hole insulation purposes. The best and most simple way to form reliable insulation would be thermal oxidation, and this is generally done if the wafers are non-processed and do not contain any temperature sensitive materials or structures. However, in many cases the TSVs are fabricated during or at the end of the back end processing. Thus, it is no longer possible to run processes above 400°C due to, for example, the presence of metallization layers on the substrates. CVD based SiOx ﬁlms grown at temperatures of 200–400°C are often used for TSVs. Films deposited with TEOS (tetraethylorthosilicate) as a source are more commonly used than silane based processes because TEOS yields better conformality. Plasma enhanced CVD (PECVD) TEOS and its varieties can be used for TSVs with modest aspect ratio and vertical via sidewalls. One technique that is suited to high aspect ratio TSVs is so called sub-atmospheric CVD (SACVD), which uses a mixture of TEOS and ozone (O3) gases in a pressure range of 100–600 mTorr. The process temperature for SACVD is 400°C, and good conformality can be achieved. Also, the use of organic insulators such as parylene, and spin or spray coated benzocyclobutene (BCB), polyimide and epoxy resins have been reported for TSVs. Parylene is the trade name for a family of vapor deposited conformal polymers. Being highly conformal and having deposition temperature near the room temperature, parylene ﬁlms can be used as a sidewall insulator for TSVs [16]. The problem with parylene ﬁlms is that the temperatures used in the subsequent process steps can create stress levels that are close to or above the yield strength of the parylene. This may result in delamination and cracking of the parylene insulation. In the case of spray or spin coated polymers, the machined vias are typically ﬁrst fully ﬁlled with the polymer material and next a route through the polymer is drilled with a laser [13]. It is important to fully ﬁll the hole with the polymer, no voids or bubbles are allowed. This means that the polymer has to have low viscosity and low shrinkage during the curing. Spray coating of conformal dielectrics into high aspect ratio TSVs is still unproven. Polymers are promising candidates for RF-applications because thick insulation layers could be achieved by ﬁlling of the etched via or the etched trench surrounding the via.

39.1.4.2 Diffusion Barrier, Adhesion Layer and Seed Layer for Electroplating It is important to prevent copper from entering silicon crystal and forming deep level traps or diffusing into the via insulator and decreasing the insulation strength.

Via Technologies for MEMS

There exist numerous good reviews and publications on copper electromigration, one example being [2]. The TSV metallization typically consists of multilayer stacks of a thin diffusion barrier layer, adhesion layer and seed layer. The nitrides of refractory metals (Ti, Ta, W) are commonly used as barrier layers. There is a contradiction between the barrier properties of a ﬁlm and the adhesion properties. In order to prevent diffusion, no reaction or mixing with copper and barrier ﬁlm is allowed. Nonetheless, copper is a relatively precious metal and, thus, it is not possible to obtain good adhesion with oxide bonding. An additional adhesion layer may be necessary between the diffusion barrier and the copper seed metal ﬁlm. In the case of TiN barrier layer, a process leading to a Ti-rich TiN layer has been developed to improve the adhesion between barrier and copper seed metal layer. Free Ti can react with Cu that strongly promotes the adhesion. Depending on the aspect ratio of the TSVs, the barrier and adhesion layers can be deposited by PVD, MOCVD or atomic layer deposition (ALD) techniques each having its advantages and disadvantages. PVD methods are limited to low aspect ratios (8:1), in terms of their ability to provide continuous barrier and seed layers with good step coverage and acceptable cost-of-ownership. MOCVD process is an established process for TSVs, but it is costly as compared to ALD. Also, electroless and other electrochemical processes, such as electrografting, for barrier and seed layer deposition have been reported [17]. These electrochemical processes are good economical candidates for TSVs.

39.1.4.3 Copper Electroplating Copper electroplating has been used in the production of semiconductor devices for over a decade [18]. Electroplating has played a major role as the IC industry changed from aluminum metallizations to copper metallizations. The electroplated copper has high conductivity and purity, and it is also compatible with multilayer interconnections and back end processes of modern ICs. All these make electroplated copper one of the preferred materials for through silicon via applications. Compared to electroless plating the electroplating has several advantages. For example electroless plating is slower, involves more complex and costly chemistry, and controls, and the bath requires frequent replacement. Basically, there are two types of plating equipment used for copper plating: wet bench type and fountain type of platers. Wet benches usually handle wafers that are loaded in a handling and electrical contact ﬁxture and move the ﬁxtures from cell to cell in a vertical direction. Fountain type platers typically handle one wafer at a time and the wafers are face down in a horizontal position during the processing. The electroplating process itself is reg-

CHAPTER 39

ulated by the electrical and mass transfer characteristics of the equipment. It is very important to control the ﬂuid motion at the surface of a wafer where it determines the hydrodynamic boundary layer thickness next to the deposition surface. The ﬂuid agitation conditions set up the length of the diffusion layer over which the transfer of the chemical species has to take place. In typical industrial wafer plating equipment the thickness of this hydrodynamic boundary layer is a few tens of 1 μm. In submicron copper damascene interconnect processes the depth of via structures on wafer surface are one or two orders of magnitude less than the length of the boundary layer. Whereas in TSV applications the via depth is easily one order of magnitude larger than the length of the boundary layer. This means that the same processes and plating electrolytes (or baths) that have been used for sub-micron metallizations cannot be used for TSV applications. The most common plating chemistry is acidic wet solution based on dissolved copper sulfate, sulfuric acid, chloride ions, water and various organic additives. Copper sulfate is the source of the Cu ions and the sulfuric acid increases the conductivity of the bath. If sulfuric acid is replaced by methane sulfonic acid, higher solubility of copper into the electrolyte can be obtained. The chloride ions are used because they reduce the anode polarization and increase the activity of certain additives. The purpose of the additives is to enhance the effectiveness and quality of the plating. The concentration of the additives is typically in the ppm range. Commercial via plating baths typically consist of three organic additives designated as suppressor (or carrier), leveler and accelerator (brightener) [19]. When these organic additives are used in proper concentrations, they can increase the growth rate of copper in vias relative to the planar surface. The resulting differential plating kinetics are known as superﬁlling or superconformal plating [20]. The principle of superﬁlling is illustrated in Figure 39.7.

Accelerator

Slow Deposition

Suppressor

Fast deposition

Fig 39.7 ● Schematics for superﬁlling mechanism illustrating the distribution of the additives near and within the via. Large and slow diffusing suppressor adsorbs at the wafer surface and along the via rim, while a fast diffusing accelerator goes down the via and increases the deposition rate at the bottom of the via.

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When conformal seed metal layer covers the sidewalls of the vias (Figure 39.6a), the conventional plating process cannot be used, since the top of the vias and especially the via corners are plated faster due to higher electric ﬁeld and enhanced transport of copper ions at the upper area of the via. Nor is it acceptable to plate conformally into the via, because it will lead to the formation of a seam inside the via. Voids and seams may cause serious reliability problems for the working devices. Conformal plating is acceptable if the purpose is only to form a metal lining layer inside the via. Lining process is feasible for large structures as is often the case in MEMS applications. Following the conformal growth of the copper, the remaining open portion of a via can be ﬁlled with other materials like polymer or ceramic paste [21]. The resistance of a via with thin lining layer may be too high for certain applications and also the contraction of the via ﬁlling material may produce problems during subsequent process steps. The advantages of a via lining process are decreased plating time and elimination of thermal mismatch issues between copper via and silicon substrate. The importance of minimization of thermal stresses is pronounced in the case of large via sizes and thin wafers because of reliability and robustness problems. The thermal expansion coefﬁcients for silicon and copper are about 2.3 ppm/°C and 16.7 ppm/°C, respectively [22]. Regarding thermal stresses, copper as a via ﬁlling material may represent a high reliability risk for certain MEMS applications, and copper may also inﬂuence the behavior of the device. For example, thermal stresses may affect resistivity of the pietzoresistive layers, modify the mechanical properties of free oscillating structures and stresses may also change the distance of the comb drive structures used for electrostatic actuation. As MEMS devices are interconnected, packaged and integrated with metallic vias, the thermal stress issues have to be taken into account. If the seed metal is only at the bottom of the via, more conventional plating electrolytes can be used because superﬁlling plating mechanism is not required. However, in this case the growth rate of copper is limited by the transfer of copper ions into plating interface. The same applies also to the case where the seed metal covers the via sidewalls, but for this case the required thickness of Cu to via ﬁll is smaller. For TSVs the maximum achievable plating rates are of the order of 1 μm/min. This limit is set by the fact that the current distribution inside the via is dominated by the diffusion of copper ions to the growth interface. When the aspect ratio of the via is small the ﬂow of copper ions is dominated by convection. In most TSV cases, however, the transfer of copper ions

582

is diffusion-controlled that means the ion transfer is not substantially improved by the increased forced convection. There can be a severe potential drop along the via because of the lack of copper ions along the via depth. The factors inﬂuencing the potential drop include the thickness, coverage and conductivity of the seed metal layer, feature dimensions and bath conductivity. Also, the proﬁle and smoothness of the etched via and the wetting of the via play major roles during the plating. The positively tapered via proﬁles are easier to ﬁll than straight or negatively tapered or barrel shaped proﬁles due to ease of ion transport into the sloped via. A feature must be wettable so that the electrolyte with Cu ions can easily move into the via. Wetting agents are typically added to plating baths to reduce the surface tension of the bath and to promote the good wetting of the via. It is also very important to eliminate the trapping of air bubbles inside the vias during the loading of a wafer to the plating electrolyte. Besides bath chemistry, the via ﬁlling can also be inﬂuenced by the current source of the plating cell. In electroplating the growth rate is proportional to the plating current (or current density). In DC plating cathodic current is continuously fed through the plating cell and the copper is continuously deposited. In pulsed or reverse pulse plating the cathodic current is applied in short pulses to give the plating chemicals (Cu ions) time to refresh concentrations at the surfaces of the via. The reverse pulses (i.e., anodic currents) remove copper from the thicker deposited regions. It has been shown that short high energy reverse pulses can improve the ﬁlling performance remarkably, since anodic current can selectively remove copper from the via mouth. Due to complexity of the electrochemical plating and the numerous variables that could inﬂuence the via ﬁlling, the plating mechanisms are still not completely understood. An important consideration for TSVs is the time required for a full, void-free and reliable via ﬁll. In order to maximize the throughput and to reduce the costs, the via sizes should be reduced as much as possible. However, the via dimensions should not exceed the process capability of the ﬁll, barrier, insulator and seed metal fabrication methods. It has been forecast that 3D vertical interconnects will revolutionize the whole 3D packaging and chip stacking. However, there still remains work to be done to achieve economically feasible and fast TSV processes. In MEMS, the challenges are related to process integration, stress control, and reliability. In RF-MEMS, the requirement for thick via insulation layer also poses challenges to the manufacturing.

Via Technologies for MEMS

CHAPTER 39

References 1. P. Garrou, C. Bower, P. Ramn, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, John Wiley and Sons, Inc., 1–2 2008. 2. E. Ogawa, K.-D. Lee, V. Blaschke, P. Ho, Electromigration reliability issues in dual damascene Cu interconnections, IEEE Transactions on Reliability 51 (2002) 403–419. 3. F. Laermer, A. Schilp, Method for anisotropic plasma etching of substrates. US patent 5,498,312 (March 12, 1996) and F. Laermer , A. Schilp, Method of anisotropically etching silicon. US Patent 5,501,893 (March 26, 1996). 4. E. Kälvesten, T. Ebefors, N. Svedin, P. Rangsten, T. Schönberg, Elektriska anslutningar i substrat/Electrical connections in substrates. Swedish Patent No. 0300784. 5. A. Lehto, Capacitive pressure detector structure and method for manufacturing same. US Patent 4,597,027 (June 24, 1986). 6. H. Kuisma. Pressure sensor construction and method for its fabrication. US Patent 4,875,134 (October 17, 1989). 7. H.-J. Quenzer, A. Schulz, B. Wagner, P. Merz, Method for structuring a ﬂat substrate consisting of a glass-type material, European Patent EP1371092, (December 17, 2003). 8. E. Chow, V. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. Quate, T. Kenny, Process compatible polysilicon based electrical throughwafer interconnects in silicon substrate, J. Microelectromech. Syst. 11 (2002) 631–640. 9. F. Ji, S. Leppävuori, I. Luusua, K. Henttinen, S. Eränen, I. Hietanen, M. Juntunen, Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging,

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Sens. Actuators A 142 (2008) 405–412. S. Savolainen-Pulli, H. Luoto, K. Henttinen, T. Suni, T. Riekkinen, A through wafer copper via in silicon for wafer level packaging. Book of Abstracts: Materials for Advanced Metallization MAM2006, Grenoble, Fr, 6–8 March (2006), pp. 221. N. Nguyen, E. Boellaard, N. Pham, V. Kutchoukov, G. Craciun, P. Sarro, Through-wafer copper electroplating for three-dimensional interconnects, J. Micromech. Microeng. 12 (2002) 395–399. Y. Ein-Eli, D. Starosvetsky, Review on copper chemical-mechanical polishing (CMP) and post-CMP cleaning in ultra large system integrated (ULSI)— An electrochemical perspective, Electrochimica Acta 52 (2005) 1825–1838. R. Toftness, A. Boyle, D. Gillen, Laser technology for wafer dicing and microvia drilling for next generation wafers, Proceedings of SPIE, 5713, 2005, pp. 54–66. M. Sekiguchi, H. Numata, N. Sato, T. Shirakawa, M. Matsuo, H. Yoshikawa, M. Yanagida, H. Nakayoshi, K. Takahashi, Novel low cost integration of through chip interconnection and application to CMOS image sensor, Proc. 56th Electron Components and Technology Conference, 2006, pp. 1367–1374. W.-C. Lo, Y.-H. Chen, J.-D. Ko, T.-Y. Kuo, Y.-C. Shih, S.-T. Lu, An innovative chip-to-wafer and wafer-to-wafer stacking. Proc 56th Electron Components and Technology Conference, 2006, pp. 409–414. J. Gobet, J. Thiebault, F. Crevoisier, J. Moret, IC compatible fabrication of through-wafer conductive vias. Proc. of SPIE, 3223, pp. 17–25. G. Druais, G. Dilliway, P. Fisher, E. Guidotti, O. Lühn, A. Radisic,

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S. Zahraoui, High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seek. Materials for Advanced Metallization MAM 2008, Dresden, Germany, 2–5 March 2008. D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper, T. McDevitt, W. Motsiff, A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, S. Luce, J. Slattery, Full copper wiring in a sub-0,25 μm CMOS ULSI technology, Proc. of IEEE IED, 1997, pp. 773–776. P. Vereecken, R. Binstead, H. Deligianni, P. Andricacos, The chemistry of additives in damascene copper plating, IBM J. R&D 49 (2005) 3–18. T. Moffat, D. Wheeler, M. Edelstein, D. Josell, Superconformal ﬁlm growth: Mechanism and quantiﬁcation, IBM J. R&D 49 (2005) 19–36. C. Patel, C. Tsang, C. Schuster, F. Doany, H. Nyikal, C. Baks, R. Budd, L. Buchwalter, P. Andry, D. Canaperi, D. Edelstein, R. Horton, J. Knickerbocker, T. Krywanczyk, Y. Kwark, K. Kwietniak, J. Magerlein, J. Rosner, E. Sprogis, Silicon carrier with deep through vias, ﬁne pitch wiring and through cavity for parallel optical transceiver, Proc. of 55th Electronic Components and Technology Conference, 2, 2005, pp. 1318–1324. C. Okoro, M. Gonzales, B. Vandevelde, B. Swinnen, G. Eneman, S. Stoukatch, E. Beyne, D. Vandepitte, Analysis of induced stresses in silicon during thermocompression Cu-Cu bonding of Cu-through-vias in 3D-SIC architecture, Proc. of 57th Electronic Components and Technology Conference, 2, 2007, pp. 249–255.

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40

Chapter Forty

Outgassing and Gettering Antonio Bonucci, Andrea Conte, Marco Moraja, Giorgio Longoni and Marco Amiotti SAES Getters S.p.A., Lainate, Italy

40.1 Introduction Conventional packaging of microelectronic and optoelectronic devices is usually stable and not affected by the external environment except for a few speciﬁc cases. The high power semiconductor lasers at 980 nm are affected by the presence of moisture inside their hermetic package causing optical damages of their laser emitting facets. Hydrogen can weaken the Pd metallization of GaAs microwave power ampliﬁers packaged inside hermetic metallic packages. In both cases, a dryer and a thin ﬁlm hydrogen getter respectively have been the practical way to guarantee a long lifetime and high reliability to these devices working under the oceans or on airplanes respectively. The evolution of microelectronic devices toward new functionalities as sensing and actuating as in the case of Micro Electro Mechanical Systems (MEMS) is posing new technical challenges for the packaging of these devices because the environment where the Si microstructure moves or electrons are emitted is becoming very sensitive to the total gas pressure as well as to the presence of speciﬁc gasses. In particular, Si or piezoelectric or quartz vibrating microstructures such as gyroscopes or frequency management devices are sensitive to the total pressure inside the package because of possible damping effects or mass loading effects of speciﬁc gasses. In fact, the quality factor Q of RF-MEMS is strongly reduced by operation in a non-vacuum environment due to gas damping [1]. Presence of moisture can cause stiction issues in MEMS sensors using electrostatic capacitive readout. In other MEMS devices where optical components are used to

manage light as in the case of Digital Light Processing (DLP), fogging and hazing of optical components due to moisture can degrade device performances. Finally, MEMS using free electrons as in the case of thermotunneling and data storage applications need a vacuum to be able to manage properly the electron free path and avoid thermal dissipation. The MEMS devices requiring a vacuum to operate properly are shown in Table 40.1 [2]. MEMS need to be protected from outside environmental stresses and also the package must provide an interior environment compatible with the device operation, increasing its performances, reliability and lifetime. The MEMS packaging technology moved from hermetic vacuum discrete packages to vacuum wafer-level packages. Vacuum wafer-level packaging is a very effective technique to produce low-cost, hermetically-sealed

Table 40.1 Internal vacuum environment requirements for particular MEMS Accelerometer

1–300 mbar

Absolute pressure sensor

104–1000 mbar

Gyroscope

101–104 mbar

RF switch

101–104 mbar

Microbolometer

104 mbar

Thermo-tunneling device

103 mbar 585

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packages for micromachined sensors and actuators. However, MEMS vacuum packaging at wafer level is really a challenging technology because of alignment issues as well as the surface-to-volume ratio increase; that is, increasing the effects of outgassing gasses from lateral walls of cavities. If we consider volume of 5 mm3, representing typical volumes for wafer-level packaged MEMS and a 45 mm2 of surface inside the MEMS package, the gas load after 5 years because of outgassing will be 2.25 101 mbar mm3 for O2, N2, CO, CO2 and 15 mbar mm3 for H2 [3]. These gas loads will represent a pressure increase of almost 3.75 mbar inside the MEMS package after 5 years. Moreover [4], a leak as small as 1014 mbar l/s represents a pressure increase of 0.06 mbar per year for a 5 mm3 volume. In a 10 year lifetime, the leak will increase the internal pressure by 0.45 mbar in a 5 mm3 MEMS volume. Similar situations where outgassing phenomena are increasing internal pressure of time management devices are present also when a quartz plate (1 in2 or more) containing many devices is used instead of a large wafer. A typical case of the inﬂuence of the environment on the MEMS performances are MEMS resonators where the Si resonator is closer to the proper resonating frequency when the merit factor or Q is higher. The damping of an Si vibrating system is mainly determined by the intrinsic dissipations in the mechanical spring (Si cantilever beams), by internal material losses (defects) and by the dissipations due to the interaction with the surrounding gas [5–7], as shown in Figure 40.1. The nature of the damping depends on the gas pressure: at low pressures (under about 10 mbar) the damping is of both a molecular and a viscous nature, whereas at high gas pressures, it is viscous. The viscous damping

is caused by the lateral displacement of the air surrounding the vibrating surface of the resonator, and it corresponds to the squeeze-ﬁlm damping, while the origin of molecular (acoustic) losses is the perpendicular displacement of the air surrounding the vibrating surface. However, the relationship between Q factor and gas pressure is not simple: the dependence of Q factor by both total pressure P and viscosity η can be summarized in the following formula: Q

α ⎛⎜ β ⎞ ⎜⎜1 1.159 ⎟⎟⎟ ⎝ ⎠ η P

(40.1)

where α and β are two parameters taking into account the resonance frequency, geometrical factors and physical constants. Several experimental and theoretical studies conﬁrm the Q factor of a silicon structure is an order of magnitude higher in vacuum than in the presence of a damping gas [5]. However, for pressures higher than about some tens of millibars, Q slightly depends on pressure P and is strongly inﬂuenced by gas viscosity. Instead for low pressures, Q is strongly inﬂuenced by both total pressure and gas viscosity. The gas viscosity is strongly dependent on gas species and temperature. Therefore, the Q factor is inﬂuenced by the cavity atmosphere composition and by the device operational temperature. For example, assuming a constant pressure P, H2, instead of N2, guarantees a higher Q factor, whilst, operating at a temperature of about 150°C, the Q factor is decreased by about 30–45%. In this paragraph, we will address ﬁrst the cause of gas generation due to outgassing and leakages inside MEMS packages in order to size the quantity of gas

Pressure (mbar) 8800 8850 8900 8950 9000 9050 9100 9150 9200

0.0027

1E-3

0.01

0.1

1 mbar

1

10

Q-Factor N2

0.0026 0.0025 0.0002 Anti-phase torsion mode

0.0015 0.0001 5 10–5

Q-factor

Photo detector output (V)

0.0028

1E-4 100000

10000

100 mbar 1000 mbar

0 8800 8850 8900 8950 9000 9050 9100 9150 9200

Frequency (Hz)

1000

0.01

0.1

1

10

100

Pressure (Pa)

Fig 40.1 ● (a) The width of frequency band in an Si MEMS resonator as a function of internal MEMS package pressure and (b) the dependence of the Q-factor of an Si MEMS resonator from the internal pressure.

586

1000

Outgassing and Gettering

and the correspondent pressure increase. Then, we will describe the gettering technology able to sorb gasses during the lifetime of MEMS devices working in vacuum or inert atmospheres in order to guarantee the stability of MEMS performances.

CHAPTER 40

device, the evolution of the pressure inside the device is exponential: p pext × (1 − e−( t / τ ) )

(40.3)

In Eq. 40.3, the characteristic time is given by,

40.2 Gas Sources into MEMS Devices

τ leak

The performances of particular MEMS devices shown in Table 40.1 are related to the internal pressure of the package: the internal pressure of these MEMS devices needs to be stable all through the device lifetime in order to avoid any shifts in device performances. However, the pressure inside MEMS packages continues to increase because gas sources continue to de-sorb gasses during the MEMS device lifetime. The main sources of the gas inside a MEMS device can be divided into two categories: A. the vapor and gas ﬂuxes during the lifetime that are classiﬁed in three classes: the gas which penetrates into the system as a result of leakage the gas coming from the outgassing of materials present in the system the gas entering the system by permeation through walls, windows, etc. B. the residual gasses: the gas molecules of the initial atmosphere enclosed in the system, just after the sealing ■

■

■

Because all MEMS devices we consider are manufactured out of silicon that is not permeable to gasses in a signiﬁcant way, from now on we will consider permeation negligible, considering, therefore, only leakages and outgassing phenomena inside vacuum-packaged MEMS.

40.2.1 Leakage A leak can be a hole or a defect in the bonding area of vacuum-packaged MEMS. In the case of MEMS devices, leak gas ﬂow is molecular and is given by Fmol K ×

1 M

( pext − pint )

(40.2)

where Fmol is the gas ﬂow; M the molar mass of the gas; pext and pint are the pressures at either side of the leak, internal and external with respect to the encapsulated volume; and K is a constant that takes into account channel geometry, temperature and gas density. Usually the internal pressure of MEMS device is negligible compared to atmospheric pressure. Therefore, if there is no sorption surface (e.g., a getter) inside the MEMS

V Qleak

(40.4)

where V is the MEMS free volume and Qleak is the leak ﬂux. After a time equal to τleak, the internal pressure is around 64% of the external one. Although the use of getters can limit this phenomenon, argon present in air cannot be sorbed in a sensitive way by any internal surface and this limits the maximum Qleak. Measurement techniques are available to check the quality of the sealing and the maximum Qleak. Helium leak detection is the most known and uses yielding leak rates below 1014 mbar l/s for vacuum packaged MEMS at wafer level [8].

40.2.2 Outgassing Outgassing remains the big issue to be contrasted inside MEMS devices during the lifetime. Desorption from surfaces is one of the complex phenomena of gas–solid interaction [9]. The general equation that can approximately describe the pressure evolution inside a hermetic device is [10] KV

dN dp

KSp

0 dt dt

(40.5)

where K is the number of molecules in a Torr liter (3.27 1019 molecules/l/Torr at 295 K), V is the internal volume of the device, S the pumping speed of the sorption surface or of a vacuum pump (in m3/s), p is the pressure, and N the total number of adsorbed and absorbed molecules onto the internal walls. In the case of irreversible desorption, the ﬂux of molecules is independent of the pressure and evolves in the time depending only on the initial state of the surface (represented by the initial number of molecules sorbed N0) and on the temperature.

40.2.3 Absorbed Species, Irreversible Desorption In the case of absorbed species for irreversible desorption, the gas ﬂows into the volume escaping from the surface, following Fick’s law [11]. Diffusivity of the gas in the solid system is the key parameter in the forecast of the outgassing rate evolution. 587

Encapsulation of MEMS Components

If the initial concentration of the gas in the wall thickness is uniform, the outgassing rate evolves as 2C1D ∞ dN ∑e dt d i0

t( 2i 1) tc

where tc

2DC1 πtc dN 16t dt d

(40.7)

40.2.4 Adsorbed Species, Irreversible Desorption In the case of adsorbed species, the rate of irreversible desorption can be evaluated as:

dN f ( N ) ( Ed / RT ) e dt τ0

(40.8)

where τ0 is the nominal period of an adsorbed molecule and Ed is the activation energy of desorption [12]. The function f(N) gives the probability of association before desorption for poliatomic molecules.

40.2.5 Adsorbed Species, Reversible Desorption The main contaminants on the silicon wafers are physisorbed on the surface, then the main desorption is related to the reversible adsorption phenomena [13]. In this case, the time in order to have thermodynamic equilibrium between the surface and the gas phase is smaller compared to the desorption phenomena. This is the so-called quasi-static solution. Reference [10] gives indication to check whether this condition is satisﬁed. The more relevant law that determines the pressure evolution in this case is the equilibrium isotherm (Henry’s law, Languimir, Freundlich, Temkin and extended Temkin). This can be represented by the relationship between the surface coverage, deﬁned as N θ f ( p, T ) Nm

⎛p ⎞ N ln ⎜⎜⎜ 0 ⎟⎟⎟ − m ⎝ p ⎟⎠ KV

4 d2 π2 D

(40.6) C1 is the initial concentration of the gas inside the solid, D the diffusivity of the gas through the mean, d is the solid thickness, e is Wapier’s constant, tc is the characteristic time of the phenomenon. The relationship can be approximated by the law, for t tc:

The pressure evolves following the solution of the non-linear equation:

(40.9)

p0

∫ p

1 dθ( p, T ) S t p dp V

(40.10)

where p0 is the pressure at time t 0, and S the total pumping speed inside the device (activated getter during the life or vacuum pump during evacuation). It is clear by Eq. 40.10 that high pumping speeds reduce the time of pumping down, but low volumes increase the absolute value of the pressure. The MEMS technology trend toward lower and lower volumes requires a higher and higher pumping speed as provided by a getter ﬁlm integrated inside the device. In the case of MEMS devices, moisture is the main contamination desorbed by Si and SiO2 surfaces. Exposure of a silicon wafer in air at 23°C and different relative atmospheric humidity causes adsorption of 3–4 monolayers of water whose thickness is estimated to be 0.31 nm [14], as shown in Figure 40.2. Exposure to standard dry atmosphere or a 100°C thermal treatment cannot eliminate the last two layers of residual adsorbed water molecules: one composed of Si-OH groups on the oxide surface and the other as a monolayer of water molecules directly hydrogen bonded to these surface groups. Thermal treatment at 300°C limits the adsorbed moisture to the Si-OH groups. Although MEMS process comprises a high-temperature thermal treatment, this is only partially done during the hermetic bonding and the “free” moisture layer in the gas phase cannot escape from the residual spaces into the vacuum chamber, remaining in the encapsulated system. After the process, going back to room temperature, the moisture can be adsorbed again in more than one layer. Furthermore, cleaning processes can nullify their beneﬁcial effect after 5 minutes of exposure in air [14]. 1.4

4

1.2 Thickness (nm)

PA R T V

1

3

Liquid-phase water

0.8

2

Hydrogen-bonded water to Si-OH

0.6 0.4

1

0.2

Surface Si-OH 0

0

Where N is the number of sites that have sorbed and Nm the available site for a monolayer coverage. As shown in relationship 40.9, the surface coverage is a thermodynamic function of external pressure and temperature. 588

0

10

20

50 60 70 30 40 Atmospheric humidity /%

80

90

Fig 40.2 ● Relationship between amount of adsorbed water on the silicon wafer surface and atmospheric humidity [14].

Outgassing and Gettering

Anyway, cleaning processes reduce the sorbed moisture at the surface. Figure 40.3 shows the amount of residual moisture physisorbed, after a cleaning in isopropanol (IPA) vapor dry process or N2-blow one. After an IPA cleaning at 400°C, the monolayer coverage is about 0.21; it must be considered that the surface had adsorbed IPA for a nonnegligible quantity that is 10 times lower with respect to moisture [15]. A getter can compensate moisture equilibrium as represented by Eq. 40.10. As explained, the equilibrium law θ( p,T) must be known. In the case of moisture multilayers sorption, a general equilibrium law can be used [10]: ⎛ 5ψ ⎞⎟1 3 ⎟ θ ⎜⎜ ⎜⎝1 ψ ⎟⎟⎠

where ψ

p ps ( T )

(40.11)

and pS is the saturated vapor pressure. The relationship 40.11 should be applicable to every adsorbent and has been validated for stainless steel or aluminum alloy, provided it is not porous, after about the ﬁrst monolayer, since it is known that physical adsorption isotherms are relatively insensitive to the nature of the solid surface. An experimental validation on nonporous crystalline anatase (TiO2) has been done [16]. The monolayer case depends too much on the state of surface that can be covered by special coating depending on the application. The only approach is the measurement of the outgassing rate by means of UHP nitrogen ﬂow and an APIMS detector [15] or standard RGA that uses a Quadrupole Mass Spectrometer [17, 18]. Although wafer-level hermetic bonding of MEMS includes a high-temperature process, the desorbed gasses from different layers inside MEMS devices cannot completely escape because of the small space available for gas ﬂow. For example, the outgassing behavior

CHAPTER 40

of different MEMS device parts has been analyzed by thermal desorption spectrometry (TDS) during a simulation of a standard MEMS wafer bonding temperature proﬁle. The TDS was focused on noble gasses because all other gasses can be absorbed by the getter ﬁlm. The composition of the released gas is dominated by Argon (Ar), which is typically used for sputtering and ion milling during the device preparation. Figure 40.4 summarizes the Ar content of the samples: both ion milling and sputtering processes are responsible for a signiﬁcant Ar outgassing. On the contrary, layer deposition by evaporation is completely Ar free [19]. For further analysis similar samples have been analyzed by secondary ion mass spectroscopy (SIMS) and electron probe micro analysis (EPMA). With both methods, a concentration of 1500–1700 ppm Ar has been found within the top Au layer of the sputtered plating base. The Ar content of all other layers is comparably small and can be neglected. The inﬂuence of ion milling was checked on a plain silicon sample. A high Ar concentration of 1000–1400 ppm was found within the ﬁrst 0.6 μm, followed by a decrease over several hundred nm. Both results are in very good agreement with the outgassing experiments. Another source of outgassing can be related to the carbon incorporated inside silicon wafers or as a result of the interaction between organic compounds and solvents used in processing [20]. Carbon can react during the MEMS high-temperature bonding processes with the moisture and oxygen trapped inside the solid, generating CO and CO2 by catalytic phenomena. A getter ﬁlm inside MEMS devices can avoid this phenomenon by reducing the level of oxidizing species before the catalysis phenomenon. Another kind of outgassing phenomenon in glass frit bonded MEMS is the presence of

0.01

400

Ar amount (cm3 mbar/cm2)

Integrated H2O degas (×106 liter)

450 Wafer D-SiO2

350 300 250

No wafer N2 blow IPA dry

200 150

1E-3

1E-4

1E-5

1E-6

100 1E-7

50 0 0

100

200 300 Temperature (°C)

400

500

Fig 40.3 ● Inﬂuence of drying methods on desorption amount of water from water surface.

Sensor wafer (Al-pads)

Ion milled reference

Evaporated plating base

Sputtered plating base

Fig 40.4 ● Outgassing of Ar from TDS experiments during a simulation of MEMS thermal wafer bond cycle for different samples.

589

PA R T V

Encapsulation of MEMS Components

gas voids inside the glass frit material [21]: these voids can be interconnected and can generate a pathway from the external MEMS environment in air to the internal MEMS environment, increasing N2 pressure inside the MEMS device with time.

40.2.6 Residual Gasses Inside WaferLevel Hermetically Sealed MEMS An accurate residual gas analysis (RGA) carried out on the hermetic package of a resonant MEMS structure packaged at wafer level could distinguish the gas species present inside the MEMS cavity [22]. RGA on MEMS samples is usually suggested to know the exact composition of the internal atmosphere. By using RGA data, it is possible also to make the correlation of the viscosity of different gasses and their partial pressure inside MEMS resonating devices. Current RGA equipment based on mass spectrometers is able to measure pressures down to 104 mbar in sealed cavities with internal volumes lower than 1 mm3. Table 40.2 shows the RGA results of MEMS devices without noble gas backﬁlling during bonding. By RGA data, it is also possible to establish a direct correlation between the merit factor (Q) and the total pressure inside the MEMS device. The sample showed a not high vacuum level, in the range of 1 mbar (viscous damping), mainly due to the outgassing of the internal surfaces (H2, CH4, and CO) during the heating of both the cap and sensor wafers for the wafer-bonding process. Many of the gasses inside the cavity are active gasses (like H2, CO, N2, and CO2) that can be eliminated by a gettering surface.

40.2.7 Conclusions So far, we have described that there are gasses remaining inside MEMS devices that need a vacuum or other stable pressure to operate properly. Moreover, the total as well as partial pressures inside MEMS are evolving during the lifetime of the device because of different sources of gasses such as permeation, outgassing and leakages. In the next paragraph, we will show that a technically viable solution to assure a long lifetime and high reliability to MEMS device is the possibility to integrate a getter ﬁlm.

40.3 Getter Films for MEMS Devices 40.3.1 Introduction to Getter Technology for Wafer-Level Packaged MEMS The use of Non Evaporable Getter (NEG) material (Zr-based alloy) is required to ensure suitable vacuum 590

Table 40.2 Results of RGA, measured and calculated Q-values and mean viscosities for the considered sample

Sample Q factor (measured)

3000

Q factor (calculated)

3220

Gas

Pressure (mbar)

Composition (%)

H2

7.92E-1

81.65

CH4

8.92E-2

9.20

H2O

9.7E-4

0.10

CO

5.53E-2

400

N2

1.55E-2

1.60

C2H6

5.82E-3

0.60

C3H8

7.76E-3

0.80

CO2

1.94E-3

0.20

Noble gasses (He, Ar, etc. …)

7.76E-4

0.08

Total

9.7E-1

100

Mean viscosity (105 Pa s) 0.984

(total pressure down to 104 mbar) and long-term stability in MEMS devices. NEG can chemically sorb all active gasses, including H2O, CO, CO2, O2, N2, and H2. An NEG captures gasses by means of a chemical reaction between a chemically active metal or alloy (the getter) and a chemically active gas thus forming a solid compound with low vapor pressure. The active gasses are therefore permanently removed from the sealed device. Hydrogen does not react to form a chemical compound but dissolves in the bulk of the getter forming a solid solution. A getter does not pump noble gasses as they do not chemically react. When an NEG is exposed to air, its surface is passivated by a layer of oxides, nitrides, etc. In these conditions, the getter is inert. Therefore, NEGs require a process called activation. Activation is obtained by heating the NEG under vacuum (ideally 102 Pa). During this heating, the passive layer diffuses into the getter bulk (the higher the temperature, the faster the diffusion) leaving a fresh, chemically active metal surface. Time and temperature depends on the speciﬁc NEG chosen.

Outgassing and Gettering

CHAPTER 40

ST122/NCF/50-400/4X40/D

Pumping speed (cc/s cm2)

10000

1000

100

10

1 0.001

According to ASTM F798-97 Activation: 10 min @ 500°C Test gas: CO Test pressure: 10−6 Torr 0.01

0.1

1

10

100

Sorbed quantity [cc Torr/cm2] Sorption temperature = 25°C

Sorption temperature = 300°C

Sorption temperature = 430°C

Fig 40.5 NEG sorption curves for CO at room temperature, 300°C and 430°C after an activation at 500°C for 10 minutes. ●

As the activated NEG is brought to room temperature, the active surface will start reacting with the active gasses until a passivated layer is formed again and the pumping for active gasses stops. The time required for this to happen is a function of the gas load to be pumped. It has to be remarked that the pumping action of a getter starts already during the activation. In fact, as soon as the passive layer starts to diffuse into the getter bulk, the remaining chemically active metal surface will already start pumping all the active gasses. Basically, the higher temperature results in pumping and, at the same time, diffusion into the bulk as sort of a continuous reactivation. Therefore the sorption capacity of a getter at moderate temperatures (e.g., 300–450°C) is (much) higher than that at room temperature. Pumping speeds and capacities for irreversibly sorbed gasses are typically displayed in a pumping speed vs. sorbed amount of gas (capacity) chart. In Figure 40.5, a classic example is reported showing CO sorption curves at different sorption temperatures of a sintered NEG (SAES HPTF, ST122/NCF/50-40/4X40/D). If the NEG is kept at room temperature, the initial active surface will be slowly reduced by the active gasses. Basically the number of available sorption sites will decrease as they are progressively occupied by the sorbed gas molecules. This explains why the curve of Figure 40.5 is decreasing as the sorbed amount of gasses increases. When a complete passivated layer is formed. the pumping for active gasses stops. A similar behavior can be seen also when the NEG is maintained at higher temperatures. The main difference is that the higher temperature promotes the diffusion of the sorbed species into the bulk as sort of a continuous reactivation. This explains why the curves at 300°C and

430°C of Figure 40.5 are still decreasing as the sorbed amount of gasses increase but at a lower rate. The ﬁrst generation of sealed devices, contained in large hermetic metallic or ceramic packages, uses NEGs in the form of sintered small pills made of a zirconiumor titanium-based alloys. The further miniaturization of hermetic packages required a different getter solution, based on a high-porosity getter thick ﬁlm deposited onto metallic substrates. However, the necessity of handling and welding a discrete getter component in a reduced space hindered the widespread use of this technology. Therefore, a thin getter ﬁlm technology fully compatible with MEMS was subsequently developed. Examples of this thin ﬁlm technology are PaGeLid® and PaGeWafer®1. These products are few-micron thick ﬁlm getter materials based on patented zirconium alloy, whose composition and morphology are optimized to maximize sorption performance and reduce activation temperature. PaGeLid is basically a lid where the getter is directly patterned (with different shapes according to the requirement) onto the available surface; hence, eliminating the need of any handling and welding of discrete getters. PaGeWafer is a silicon (or glass) wafer that acts as the cap wafer of wafer-level MEMS package. The getter ﬁlm is selectively placed and patterned with lateral dimensions down to hundreds of microns, inside the cavities of the cap wafer ensuring the device reliability throughout the engineered lifetime (5–20 years) and assuring at the same time that there are no loose particles, good adhesion, and thermal and mechanical stability. 1

Commercially available through the SAES Getters Group (http://www.saesgetters.com/).

591

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Encapsulation of MEMS Components

Fig 40.6 ● General conﬁguration of a vacuum-packaged MEMS device with integrated getter ﬁlm.

Table 40.3 Typical temperatures of various bonding techniques and corresponding Page ﬁlm performance

Bonding type

Typical bonding/activation temperature (°C)

Typical bonding time (minutes)

Page performance (a.u.)

Eutectic (AuSn)

300

15

1

Anodic

350

30

1.5

Eutectic (AuSi)

400

30

2

Glass frit

450–470

30

2.5

Low-temperature direct

450–500

30

2.5

The getter ﬁlm is supplied in a stable, nonactive form to protect the gettering surface and to ensure that it performs as speciﬁed. Therefore, the getter ﬁlm can be safely handled in clean room air before introducing the wafer with patterned getter ﬁlm inside the vacuum wafer bonding equipment. The geometrical layout of the MEMS design requires a patterned deposition of the getter material on the cap wafer as shown in Figure 40.6 for example. A key characteristic of a getter ﬁlm for wafer-level packaging MEMS is its capability of being activated at temperatures compatible with the sealing/bonding process. For example, PaGeWafer has been proven to be compatible with all the major wafer-to-wafer bonding techniques, such as glass frit, anodic, direct fusion and eutectic paste bonding processes, as shown in Table 40.3. The typical sorption characteristics of a thin ﬁlm getter (Page®) for hydrogen and carbon monoxide at room temperature are shown in Figure 40.7. The other active gasses, like CO2, O2, H2O, and N2, are sorbed by a thin-ﬁlm getter with comparable capacities. Table 40.4 reports the capacities for various gasses of Page ﬁlm. 592

The getter ﬁlm at wafer level for hermetic sealing of MEMS devices needs to be compatible with all the typical semiconductor processes before and during the wafer bonding. In particular, the getter ﬁlm needs to be stable and not chemically contaminated during typical wet cleaning processes of wafers before wafer bonding: the Page Film, for example, fully withstands standard wafer chemical cleaning processes, such as mega-sonic de-ionized water, RCA (SC1 and SC2) and HNO3 cleanings before any wafer bonding process [23]. The gas sorption performances of getter ﬁlm at wafer level are not affected as shown in Figure 40.8. The Page ﬁlm has also other mechanical and electrical characteristics compatible with MEMS applications as shown in Table 40.5: the mechanical stability of the getter ﬁlm even at high temperatures during typical thermal cycles assures that the getter ﬁlm is totally suitable for applications where Si moving parts are present. Moreover, the Page ﬁlm also successfully passed the most widely used aging tests, like pressure cooker test, highhumidity and high-temperature test, hot-temperature tests and thermal shock tests [24, 25].

Outgassing and Gettering

CHAPTER 40

100

Pumping speed (cc/s/cm2)

H2

10

1

CO

Getter thickness: 2 micron Activation: 15 min at 300°C Sorption temperature: 25°C According to ASTM F 798-82

0.1 0.001

0.01

0.1

1

Sorption capacity (cc mbar/cm2)

Fig 40.7 ● Typical hydrogen and carbon monoxide sorption curves at room temperature of a thin ﬁlm getter.

Table 40.4 Page ﬁlm relative sorption capacity for different gasses at room temperature Relative sorption capacity for different gasses at room temperature (a.u.) CO

1

CO2

1

O2

3

H2O

6

N2

0.5

H2

50

Noble gasses

N/A

40.3.2 Examples of Effects of Getter Film in Vacuum MEMS Devices Bonded at Wafer Level A getter ﬁlm at wafer level contributes to making pressure homogeneous along the entire wafer surface, especially in large-diameter wafers where conductance problems limit the lowest achievable pressure at the center of the wafer during the MEMS vacuum sealing. The getter technology allowed obtaining resonating angular rate MEMS sensor with controlled Q-factor all over the wafer surface, increasing production yield and

reproducibility of MEMS devices [24, 25], as shown in Figure 40.9. In order to better understand the effect of getter ﬁlm and of different backﬁlling and vacuum processes, three more samples have been prepared as follows: Sample 3 and 4: sample with getter and with backﬁlling at different pressure levels; Sample 5: sample with getter and without gas backﬁlling. Table 40.6 shows the results. The desired Q value for this MEMS sensor application lies in the range between 5000 and 10000 and it can be successfully achieved by a gas backﬁlling procedure using an inert or noble gas. The Q factor of sample 3 is the ﬁnal goal for the application of interest, being the atmosphere composing mainly or totally noble gasses (P 1.8 101 mbar). Traces of hydrocarbons can be found inside this MEMS device, mainly coming from some cleaning steps. The getter ﬁlm succeeded in maintaining a stable cavity atmosphere removing all the active gasses. Sample 4 is showing that a ﬁne tuning of the backﬁlling procedure allows reaching good vacuum level (P 7 102 mbar) and higher Q factor (27000) with lower contaminants’ concentrations. Finally, if no backﬁlling procedure was applied to the bonding process, a total pressure down to 104 mbar could be achieved corresponding to extremely high Q factors. This result is fundamental because for the ﬁrst time it was directly demonstrated that a pressure in the range of 104 mbar can be achieved by a wafer-level packaging of MEMS structures, using the combination of eutectic bonding and getter technologies. ■

■

593

Encapsulation of MEMS Components

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Sorption test after SC1 and SC2 treatment 1000

cc/s cm2

100

10

1

According to ASTM F798-97 Activation: 45 min @ 450°C Test gas: CO Test pressure: 10−6 Torr Sorption temperature: 25°C Reference SC1 + SC2

0.1 0.0001

0.001

0.01 cc torr/cm2

0.1

1

Fig 40.8 ● Evidence of no impact of SC1 SC2 (RCA) wet wafer cleaning process on the sorption performances of getter ﬁlm at wafer level.

Table 40.5 Typical mechanical characteristics of getter ﬁlm at wafer level Getter ﬁlm properties Getter ﬁlm density

6 103 kg/m3

CTE (bulk of getter ﬁlm)

6 106 m/m/°C

Young’s module (bulk of getter ﬁlm)

67 GPa

Stress value at rupture

120 MPa

Electrical conductivity

>20 kS/m

Another example of different internal environments of MEMS devices depending on process and materials conditions has been reported in [24, 25] where MEMS pressure sensors have been analyzed. Three samples have been prepared by eliminating the pumping well and by integrating a getter ﬁlm at wafer level. Figure 40.10 shows the different structures of the MEMS pressure sensor: Three types of MEMS pressure sensors (cavity volume 4.3 mm3) have been prepared: Type 1: standard MEMS pressure sensor with pumping well and without integrated getter ﬁlm; Type 2: modiﬁed MEMS pressure sensor without pumping well and without getter; Type 3: modiﬁed MEMS pressure sensor without pumping well and with getter. ■

■

■

594

Table 40.7 shows the results. The MEMS pressure sensor without getter (type 2) showed a low vacuum level, in the range of 2 102 mbar, mainly due to residual air (N2) and to the outgassing of the internal surfaces (H2, CH4, and CO) during the bonding process. On the other hand, the RGA on the sensor of Type 3 shows that the integrated getter ﬁlm is able to remove all the aforementioned gasses and the atmosphere composition is dominated by the noble gasses that are not removed by the integrated getter ﬁlm. In Type 3 MEMS pressure sensor, the vacuum level is in the high 104 mbar range. A similar vacuum level was found in the Type 1 MEMS pressure sensor (standard product), but in this case the gas composition is different: active gasses like N2 and CH4 are still present together with traces of water vapor. These gasses, compared to noble gasses, could lead to some performances drifts in the MEMS pressure sensor. MEMS yaw rate sensor, and in general MEMS microresonating sensors, requires a pressure of 101–102 mbar, corresponding to a Q factor comprised between 5000 and 10000. In some cases, ﬁlling these MEMS devices with noble gases is suitable for their proper operation. The getter ﬁlm at wafer level has been shown to stabilize the noble gas ﬁlling the atmosphere inside MEMS devices all over the wafer surface. The backﬁll operation is typically one step in the wafer bond cycle [26]. For a MEMS yaw rate sensor packaged at wafer level with AuSi eutectic bonding, Figure 40.11 shows that a yield of about 90% has been obtained onto 6 in. wafers (green dies are dies whose Q factor is within one σ of the mean value). Q factor appears now stable around about 6600 (Figure 40.11b)

Outgassing and Gettering

CHAPTER 40

Fig 40.9 ● The wafer distribution of the Q factor of MEMS resonant devices packaged at wafer level with integrated getter ﬁlm at wafer level.

Table 40.6 Results of RGA, measured and calculated Q-values and mean viscosities of samples 3, 4, and 5

Sample 3

Sample 4

Sample 5

Q factor (measured)

10000

Q factor (measured)

27000

Q factor (measured)

500000

Q factor (calculated)

10580

Q factor (calculated)

30920

Q factor (calculated)

1.4 107

Gas

Pressure (mbar)

Gas

Pressure (mbar)

Composition (%)

H2

Composition Gas (%)

H2

Pressure (mbar)

Composition (%)

H2

CH4

1.84E-02

10.20

CH4

3.12E-03

4.50

CH4

3.92E-05

9.80

H2O

3.60E-04

0.20

H 2O

6.94E-05

0.10

H 2O

2.28E-05

400

C2H6

1.52E-05

3.80

3.36E-05

8.40

CO

CO

CO

N2

N2

N2

C2H6

9.00E-04

0.50

C2H6

6.94E-05

0.10

C3H8

C3H8

C3H8

CO2

CO2

CO2

Noble gasses (He, Ar, etc.)

1.60E-01

89.10

Noble gasses 6.61E-02 (He, Ar, etc. …)

95.30

Noble gasses 2.89E-04 (He, Ar, etc. …)

72.30

Total

1.80E-01

100

Total

100

Total

100

6.94E-02

Mean viscosity (105 Pa s)

Mean viscosity (105 Pa s)

Mean viscosity (105 Pa s)

2.107

2.177

1.911

4.00E-04

595

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Encapsulation of MEMS Components

with a statistical variation of about 10%. More than 700 dies revealed a total internal pressure narrowed around 1.7 101 mbar (Figure 40.11c). The getter ﬁlm at wafer level can also shorten the encapsulation processes time of wafers since the ﬁlm getter is really a miniaturized and localized vacuum pump close to the MEMS device during the bonding process.

40.3.3 General Considerations on the Pressure Evolution Inside the Device: The Modeling Approach The pressure inside the device during the lifetime is determined by the source surfaces (outgassing) and sorption surface (getter). For example, we will consider three devices with typical volume, getter surface and thickness, as shown in Table 40.8. The parameter α is related to the pressure increase during the ﬁlling of the cavity in the event there is no getter. In fact, in those conditions, Eq. 40.5 is simpliﬁed and the pressure trend is the integral of the outgassing law multiplied for the constant α. The higher α is the higher the pressure at the same elapsed time. The parameter β is related to the partial pressure evolution inside the cavity when there is a getter and a quasistationary condition is the dominant regime. In the simulation, we will consider a baking process before the bonding. For example, we consider a baking at 350°C, with variable time (no baking, 30 minutes, 1 hour) and a bonding at 450°C for 30 minutes. For the simulation, we will also consider that The main contamination gas is CO, considering a number of sites available for physisorption of 1015 1/cm2, (measurable by the overall outgassed contaminants). The initial outgassing rate is 103 cc mbar/cm2 s at 450°C. ■

Fig 40.10 ● Structure of the MEMS pressure sensors with and without the pumping well and with and without the integrated getter ﬁlm.

■

Table 40.7 Results of RGA of three different samples of MEMS pressure sensors

Type 1 Pressure

%

Type 2 Pressure

%

Type 3 Pressure

%

H2

1.0 104

0

40 103

26.2

1.0 104

0

CO

1.0 104

0

2.1 103

9.5

1.0 104

0

N2

1.0 104

18.2

1.2 102

57.6

1.0 105

0

CH4

3.6 104

65.2

9.3 104

4.3

1.0 105

0

H2O

8.1 107

0.1

1.0 107

0

1.0 107

0

C2H6

1.0 106

0

1.0 106

0

1.0 106

0

C3H8

1.0 106

0

1.1 104

0.5

1.0 106

0

CO2

1.0 104

0

3.5 104

1.6

1.0 104

0

N.G.

9.2 105

16.5

7.6 105

0.3

8.3 104

100

Total

5.6 104

100

2.2 102

100

8.3 104

100

N.G. stands for Noble Gasses, Pressure in mbar.

596

Outgassing and Gettering

CHAPTER 40

Fig 40.11 ● (a) Q factor map of a 6 in. wafer realized with AuSi eutectic bonding and Page Wafer. (b) Q factor statistical evaluation: the mean value is 6600 with an uncertainty of 10%. (c) More than 70% of the dies have a total pressure around 1.7 101 mbar. Remark: the Q factor distribution is widened by two different sensor designs with individual resonance frequencies.

We will consider an outgassing law with f(θ)~θ2 that is more representative of the CO outgassing and conservatively slower2. The chemical and physical characteristics of the internal surfaces determine the activation energy for desorption. Typical values are in the range of 2–15 Kcal/mol. We will show that: In the case of lower activation energy (2 Kcal/mol), it is relevant to the increase of pressure during the lifetime.

■

■

In the simplest caseφ(θ) is proportional to (θ), basing on the Langmuir theory. The function could be θ2, if two surface atoms must associate to be desorbed [12].

2

■

Figure 40.12 shows the increase of the pressure during the lifetime in function of the baking time. The use of the getter makes the pressure practically negligible. Figure 40.13 shows the pressure trend of the CO partial pressure in 10 years, in a MEMS with getter, for different baking times. The usual geometrical area ratio between getter surface and the other outgassing surfaces is around 0.5/0.7. We consider also the case where the real outgassing surface is 10 times the geometrical one, because of the miniaturized 3D structure and the rugosity. Also in this case the advantage of the getter is clear. In the case of higher activation energy (12 Kcal/mol), it is relevant that the residual gas remains inside the 597

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Table 40.8 Example of typical devices considered

Volume (mm3) Cavity thickness Getter surface Outgassing surface (mm2) (mm) (mm2)

Total surface (cm2)

α surface/ β getter surface/ volume (mm1) outgassing surface

4.00

0.40

10.00

15.06

25.06

6.26

0.66

1.00

0.25

4.00

6.00

10.00

10.00

0.67

0.10

0.10

1.00

1.40

2.40

24.00

0.71

Fig 40.12 ● Pressure trend for the three examples of Table 40.8, without getter and low activation energy.

Fig 40.13 ● Pressure trend for the three examples of Table 40.8, with getter.

system. Figure 40.14 shows the partial pressure of CO, after the bonding process of a MEMs without any getter and with a baking process at 350°C for 1 hour. It is noticeable that big MEMS can have an acceptable pressure if a good cleaning process is done. This is not true for little MEMS. As the general trend of MEMS evolution is toward smaller and smaller sizes, for an obvious cost reduction, this will lead to higher and higher α S/V ratios making the getter more and more enabling. In fact, the residual quantity can be easily absorbed by the getter, affecting in a negligible way its total capacity. This positive feature of the getter is related to the life maintenance of the device. The location of the getter has another advantage also during the process, because is very near the sources. In fact, before bonding when the wafers are brought near to chamber vacuum conditions, 598

the temperature of the wafers themselves allow a baking process which cleans the surfaces. Unfortunately, the gap between the wafer surfaces is very narrow and makes the evacuation of the outgassed species difﬁcult. These residual gasses are trapped into the device when bonding is carried out. When the getter is activated, it can also sorb these little amounts of gas, working during the process as an in situ pump. Without a getter, these little amounts of residual gasses correspond to a not negligible pressure, because the volume of the MEMS is little.

40.4 Conclusions Pressure level is a key parameter for the quality of the MEMS devices. The main contamination source is the leakage in the bonding and outgassing phenomena.

Outgassing and Gettering

Fig 40.14 ● Pressure after 10 hours of life, in function of the ratio S/V that is increasing in the technological trend of the MEMS.

The leakage is mainly caused by defects in the bonding and can be solved by a suitable improvement of the

CHAPTER 40

technology or accepting a limited yield in the MEMS production. Outgassing is an unavoidable issue and although the cleaning process and long baking are carried out, the effect can be limited only by using the getter technology. This technology sorbs the residual gases trapped into the device during the process and maintains the pressure at very low level for the required lifetime, limiting the gas ﬂux. In particular, if the volume is very small and the required pressure is very low, the getter is an enabling solution that does not increase the tact time like deep and long cleaning and baking processes. The getter technology allowed obtaining resonating angular rate MEMS sensor with controlled Q factor, up to extremely high values (500000) and very good vacuum levels (104 mbar). Even the pressure sensor for avionics reached an internal vacuum level down to 104 mbar with high Q factors.

References 1. Patent US 6,924,582 (2005). 2. M. Madou, Fundamentals of Microfabrication, CRC Press, Boca Raton, 2002. 3. M. Moraja, M. Amiotti, Getters ﬁlms at wafer level for wafer to wafer bonded MEMS, in: Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’03), 2003, pp. 346–349. 4. S. Caplet, N. Sillon, M.T. Delaye, P. Berruyer, Vacuum wafer level packaging for MEMS applications, Proc. SPIE 4979 (2003) 271–278. 5. G. Stemme, Resonant silicon sensors, J. Micromech. Microeng. 1 (1991) 113–125. 6. P. Mohanty, et al., Intrinsic dissipation in high-frequency micromechanical resonators, Phys. Rev. B 66 (2002) 085416. 7. T. Veijola, H. Kuisma, J. Lahdenpera, T. Ryhanen, Equivalent-circuit model of the squeezed gas ﬁlm in a silicon accelerometer, Sens. Actuators, A 48 (1995) 239–248. 8. W. Reinert, G. Longoni, Assessment of vacuum lifetime in nL-packages, in: Electronic Packaging Technology Conference, 2005, EPTC 2005, Proceedings of 7th, vol. 1, December 7–9, 2005. 9. A. Roth, Vacuum Technology, second revised ed., North-Holland, 1982. 10. P.A. Redhead, Modeling the pumpdown of a reversibly adsorbed phase.

11.

12.

13.

14.

15.

16.

17.

18.

19.

I. Monolayer and submonolayer initial coverage, J. Vac. Sci. Technol. A 13 (2) (1995) 467–475. R.H. Doremus, Diffusion of Reactive Molecules in Solids and Melts, John Wiley & Sons, Inc., 2002. M. Lafferty, Foundations of Vacuum Science, John Wiley & Sons, Inc., New York, 1998. S.B. Zhu, Theoretical study of molecular contamination on silicon wafers, J. IEST (Sep/Oct) (1998). T. Takahagi, et al., Adsorbed water on a silicon wafer surface exposed to atmosphere, Jpn. J. Appl. Phys. 40 (2001) 6198–6201. H. Mishima, et al., Desorption characteristics of isopropanol (IPA) and moisture from IPA vapor dried silicon wafer, IEEE Trans. Semicond. Manuf. 2 (4) (1989) 121–129. P.A. Redhead, Modeling the pump down of a reversibly adsorbed phase. II. Multilayer coverage, J. Vac. Sci. Technol. A 13 (6) (1995) 2791–2796. H.F. Dylla, et al., Correlation of outgassing of stainless steel and aluminum with various surface treatments, J. Vac. Sci. Technol. A 11 (5) (1993) 2623–2636. M. Moraja, M. Amiotti, G. Longoni, Patterned getter ﬁlm wafers for wafer level packaging of MEMS, in: MST 2003, Munich, October 2003. G. Longoni, et al., Q-factor enhancement for MEMS devices: the

20.

21.

22.

23.

24.

25.

26.

role of the getter ﬁlm, in: Proceedings of IMAPS 2005, Philadelphia, September 2005, pp. 801–809. N. Rana, et al., Kinetic and mechanism of carbon incorporation in ultrathin silicon-based dielectric ﬁlms, J. Electrochem. Soc. 149 (5) (2002) F35–F42. M.A. Schmidt, Wafer-to-wafer bonding for microstructure formation, Proc. IEEE 86 (8) (1998) 1575–1585. A. Bonucci, S. Guadagnuolo, A. Caterino, A. Conte, M. Moraja, A new model for vacuum quality and lifetime prediction in hermetic vacuum bonded MEMS, Proc. SPIE 6884 (2008) 68840M-68840M-12. M. Moraja, et al., Chemical treatment on a getter ﬁlms on wafer prior to vacuum packaging, Proc. SPIE 53438 (2004) 7–93. A. Conte, et al., High and stable Q-factor in resonant MEMS with getter ﬁlm, Proc. SPIE Photo. West 2006 6111 (2006). G. Longoni, et al., Stable and reliable Q-factor in resonant MEMS with getter ﬁlm, Proc. IRPS (2006). W. Reinert, et al. Eutectic vacuum wafer bonding with patterned getter thin ﬁlms: the European VABOND project, in: 8th International Symposium on Semiconductor Wafer Bonding, Quebec, May 2005.

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41

Chapter Forty One

Dicing of MEMS Devices Scott Sullivan DISCO HI-TEC America, Inc. Santa Clara,CA, USA

41.1 Introduction Taking a silicon wafer and turning into hundreds or thousands of MEMS uses traditional semiconductor processes. Separating the wafer into die also uses traditional semiconductor processing. Over the past 30 years the dominant method has become blade dicing. Dicing is the process that joins the front-end fab process to the backend assembly process. A diamond-impregnated blade rotating at between 20000 and 60000 rpm cuts a channel in the wafer that can be as small as 15 μm wide or up to 180 μm wide. Over time the blades, cooling water ﬂow, dicing saw, and recipes have improved, resulting in higher yield, quality, and throughput while reducing cost.

broken as with the scribe-and-break process. In current practice the wafer is mounted on a low-cost plastic ﬁlm. This allows the wafer to be cut all the way through safely because the wafer is held securely. To full-cut blade-dice a wafer it is mounted on dicing tape which is attached to a stainless steel or plastic dicing frame. The blade cuts all the way through the wafer and continues 20–30 μm into the tape. As Figure 41.1 shows, the transitions from one method to the next have occurred gradually with a good deal of overlap. Full-cut dicing began to spread in the ﬁrst half of the 1980s and is currently the dominant method. At one time die size was a limiting factor. With improvements in dicing tapes, dicing small die become easier.

41.3 Process Flow 41.2 History of Dicing Starting with two-inch diameter wafers, the ﬁrst method in production was to scribe a line with a diamond and then break the wafer along the scribed line. Following that was laser scribe and break. About the same time as laser scribe was being evaluated thin-diamond saw blades started to be manufactured. The diamond and laser scribe lines were replaced by grooves in the wafer cut by thin-diamond saw blades and then broken. Diamond scribe, laser scribe, the recent laser method “stealth dicing” in which the scribed line is below the wafer surface, and blade half-cutting are still in use today. Blade dicing started as an extension of diamond scribe-and-break. The scribe line was changed to a groove cut partway into the wafer. The wafer was then

Regardless of which dicing process is used, the point at which dicing occurs in the process ﬂow is the same, as shown in Figure 41.2. After the die are separated they are mounted and wire bonded. Through technical innovation of the semiconductor manufacturing process and demand for thinner and higher quality die, the dicing process has changed.

41.4 Methods of Dicing There are a number of methods for converting wafers into die. The following are the predominant methods. Some variations of these methods exist. Those that never made the move to mass production are not discussed here. 601

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Sillicon wafer size ϕ2”

Encapsulation of MEMS Components

ϕ3”

ϕ4”

ϕ5”

ϕ6”

ϕ8”

ϕ12”

Diamond point scriber

Dual dicer

Dicer (blade)

DBG (Dicing before grinding) Laser

Laser scriber

Laser dicer

Figure 41.1 ● Evolution of silicon wafer singulation.

Fig 41.2 ● Process ﬂow from wafer to packaged die.

Fig 41.3 ● Diamond and laser scribe method.

41.4.1 Diamond and Laser Scribe Diamond scribe was the dominant process at one time. To eliminate the cost of frequent diamond tool exchanges, lasers were adopted. A scribed line parallel to the crystal plane acts as the crack initiation point during the breaking process. Die for the most part separate along crystal cleavage planes. Sometimes the break deviates from the scribed street and die breakage occurs, shown in Figure 41.3. Scribing the wafer surface with a diamond or laser and then breaking it into die has the advantage of being a dry process, but it is not as stable a process as blade dicing. In addition to die breakage, problems include die that do not separate, the force from the breaking process, and particles that are generated during scribing and breaking. 602

Particles can cause problems during assembly and interfere with the operation of the MEMS device itself. Particles stick to the back side of the die leading to die breakage during die bonding. Sometimes particles also stick to the wire bonding pad and create a bonding defect.

41.4.2 Half-Cut and Semifull-Cut Dicing An alternative breaking method that is sometimes used was devised using a blade dicer. Compared with diamond or laser scribing, half-cut and semifull-cut dicing improves die shape provides better process accuracy and quality. A groove is cut into the wafer halfway with a dicer (halfcut dicing) or deep enough so that only about 30 μm of silicon remains, as shown in Figure 41.4.

Dicing of MEMS Devices Half-cut dicing and breaking

Laser scribing and breaking

Point scribing and breaking

? 400

? 400

? 400

CHAPTER 41

Fig 41.4 ● Comparison of half-cut dicing, laser scribing, and diamond-point scribing. Point scribing: The machine makes a linear scribe line on the surface where we want to separate the workpiece with a diamond. Laser scribing: The machine grooves the surface of the workpiece with a laser.

Edge view

Photo of die surface

Photo of internal strains Sirtl-etched after heat treatment

Blade

Frame Blade

Wafer

Tape

Double ring

Roller

Tape

Wafer

Roller

Interconnect layer Tape

Tape

2/3

Half-cut dicing

Wafer

Wafer

Half-cut dicing

Breaking by roller

Wafer Expanding the wafer

Fig 41.5 ● Half-cut (semifull-cut) method.

Figure 41.5 shows how with MEMS the half-cut or semifull-cut is done from the back side of the wafer, unlike in dicing ICs. Protection tape is applied to the active side of the wafer which is then placed on the vacuum chuck table. A blade scores the wafer with grooves which go halfway, two-thirds, or almost completely through the wafer. Next, an expanding tape that can be stretched is applied to the wafer. Breaking is done using one of several methods and then the die are separated by expanding the tape.

41.5 Stealth Dicing Focusing a laser beam below the surface of the wafer, as in Figure 41.6, modiﬁes the silicon crystal structure.

As the laser beam is scanned across the wafer, a modiﬁed layer of silicon is scribed below the surface. The number of scans depends upon the thickness of the wafer and the ease of separation required. Few passes have higher throughput while additional passes ease separation and eliminate the need for breaking and the issue of particles. Performance of a resonator with a typical mass of less than 1010 kg depends greatly on the atmosphere inside the device as well as that surrounding it. Blade dicing is a wet process which can contaminate the resonator cavity with either water or water vapor, which will affect the performance of the resonator. Dry processes such as Stealth dicing eliminate concerns about water damage. 603

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41.5.1 Breaking Methods There are a number of breaking methods: • Static bending. This is the oldest and most common breaking method. A bending force is applied to the wafer, causing the wafer to crack along the scribed line. Roller breakers and hand breaking of wafers use this method. • Anvil: An anvil supports the wafer and restricts its vertical movement. An impulse bar strikes the bottom of the wafer under the scribe line. Both the wafer and anvil are covered with a material to cushion the blow and protect the die. • Noncontact or vacuum anvil method: Instead of an anvil holding the wafer in place vertically, a vacuum chuck is used. The vacuum is local and indexes from break to break. As with the anvil method, an impulse bar strikes the bottom of the wafer. The noncontact refers to the fact that there is no contact with the top surface of the wafer. This process is often applied to MEMS wafers.

make it easier to pick up the die from the tape during the die attach process. UV light hardens the adhesive, reducing the adhesive strength and making it easier to separate the die from the tape. Recently, the use of UV tape for dicing thin wafers has been increasing.

41.7 Effects of Dicing The typical IC wafer has a passivation layer protecting it from the environment. ICs also are for the most part unaffected by moderate vibration, heating, and electrostatic discharge (ESD). This is not the case for most MEMS. For many MEMS being affected by the environment is their function, and they need to be exposed to the atmosphere [1]. Mechanical components including the cantilevers, gears, hinges, bridges, and membranes of MEMS devices are often extremely fragile and have extremely ﬁne movements. For example, a resonator can have a peak-to-peak displacement of 10 nm. During dicing, contamination, vibration, heating, and ESD can reduce the performance or cause the device to catastrophically fail.

41.6 Full-Cut Dicing

41.7.1 Contamination

In Figure 41.7, a wafer is mounted on dicing tape which is attached to a stainless steel dicing frame. The blade cuts all the way through the wafer and continues 20–30 μm into the tape. This process began to spread in the ﬁrst half of the 1980s and is currently the dominant method of dicing for both MEMS and ICs. Most dicing tape has a base of polyvinyl chloride or polyoleﬁn to which about 10 μm of acrylic adhesive is applied. Ultraviolet (UV) tape is sometimes used to

Effects of contamination take two forms. A ﬁne ﬁlm of submicrometer particles can disrupt the function of a device. Larger particles can hinder or impede moveable parts, rendering devices useless. As the dicing blade cuts through the wafer, particles are created. Most of these particles are carried away by the water being showered on the wafer. The relatively smooth surface of ICs allows the particles to be carried away and in some cases surfactants are added to aid the sheeting action. The particles that remain on the wafer are easily washed away in a spin rinser dryer. In contrast, the structure of MEMS often traps the particles and surfactants that would normally be rinsed off the wafer. Dicing with a traditional method can limit the design of many MEMS devices. To allow the use of standard dicing saws, prior to dicing, the surface of the wafer can be covered with a

Modified layer

Fig 41.6 ● Stealth dicing.

604

Fig 41.7 ● Full-cut dicing.

Dicing of MEMS Devices

temporary protective ﬁlm or permanent cap. Another similar alternative is to coat the surface with an oxide or polymer layer that covers the devices and holds the structures in place. After dicing, the ﬁlm or coating is removed, releasing the MEMS. Modifying the spray nozzle can help to reduce the number of particles that adhere to the wafer, graphed in Figure 41.8. Once particles have adhered to a wafer or device it is difﬁcult to remove them. By changing the ﬂow of water the nozzle can keep the particles in suspension and not allow them to adhere to the wafer or device. Photos in Figure 41.9 are of two special test wafers. The wafers were coated with a resin that attracts and holds particles. This allows for a worst-case study on the effectiveness of the nozzle design. On the left is the wafer that was diced using a standard nozzle. On the right is the same type of wafer using a particle-reducing nozzle. The reduction in particles is signiﬁcant.

CHAPTER 41

41.7.2 Water Pressure Damage Due to the fragile nature of MEMS, limiting the amount of stress applied to the wafer is a primary consideration. This is in opposition to eliminating contamination with standard processing. Increasing water ﬂow and pressure is a common way to reduce contamination. Because MEMS are fragile there is a high likelihood of damage from the water. Figure 41.10 shows a wafer while it is being diced. Wheel coolant is supplied to the blade throughout the dicing process using a high-pressure nozzle as shown. Wheel coolant serves both to remove the heat of dicing and to slough off the material being cut. ICs for the most part are unaffected by this high-pressure ﬂow of water. Post dicing, there is a spin rinser dry step. Again the wafers are subjected to high-pressure water. Applying a temporary ﬁlm or capping the wafer will protect the devices from the damaging water. After dicing the ﬁlm is removed. Removing the ﬁlm from individual die is usually a time-consuming and costly manual process. Cap wafers are usually silicon or glass. The cap

80 5 μm or greater 70 Less than 5 μm 60 50 40 30 20 10 0

Fig 41.8 ● Particles adhering to the wafer, before and after spray nozzle modiﬁcation.

Fig 41.10 ● Wheel coolant.

Fig 41.9 ● Particle adhesion comparison.

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is an integral part of the device and remains after dicing. Both methods protect the devices from contamination and physical damage done by water spray but not from vibration [2]. Vibration during dicing and cleaning can damage the fragile and pressure-sensitive components of MEMS. During dicing, the blade rotates bringing abrasive particles in contact with the wafer. The blade’s rotation at roughly 30,000 rpm creates a vibration. Added to this is a spray of water that is directed at the cut area and the wash cycle. An atomizing nozzle is one way to reduce the force applied to MEMS devices during cleaning. Compressed air mixed with water produces an atomized liquid. This atomized liquid is sprayed onto the surface of the workpiece. The water particles travel at high speed impacting the wafer surface. The mass of the water particle is small compared with that of the device, so the total impulse energy is small. In comparison with the mass of the contamination particle the impulse energy is large so the contamination particle is dislodged and removed without damaging the MEMS structure. To reduce the force applied to the MEMS devices the wafer can be submerged in water during cutting, as in Figure 41.11. This method lowers the impact of the cutting water on the surface of the workpiece. Additionally the ﬂow rate is reduced. As a result, with the submerged cut the MEMS structures are undamaged (Figure 41.12).

41.7.3 ESD Damage A sudden discharge of electrostatic energy can damage the electronic components in MEMS devices. There are a number of stages where charges are built up. Wafer transfer between stations in the dicing saw leads to several situations in which an uncontrolled discharge can occur. For MEMS dicing it is essential that the dicing saw be equipped with ionizers. Typically the ionizers are ﬁxed and the wafer moves or passes by the ionizer. SEMI E78-1102 is a standard for electrostatic compatibility. Much of the standard can be applied to MEMS processing [3]. DI (deionized) water is often used when dicing MEMS. Ions are removed from the water in order to ensure the quality of the product. Some MEMS are susceptible to contamination by a number of ionic elements. The high resistivity of the water combined with

Fig 41.11 ● Submerged cut process.

Fig 41.12 ● Submerged cut diagram.

the high rotation speed of the blade causes charge build up. When the water is reionized with CO2 the resistivity of the water is decreased and the bicarbonate has no negative effects on the MEMS.

41.8 Conclusions Using traditional dicing methods on MEMS can limit the design of many MEMS devices. Traditional methods for dicing ICs are being modiﬁed to better address the unique needs of MEMS devices. A great number of the ﬁrst MEMS designs had to be abandoned because they could not be tested or diced. Over time that has changed. With changes to existing machines and ways to protect the MEMS structures, designers can have a freer hand. New processes such as stealth dicing may allow designers even more freedom to create our nanofuture.

References 1. K. Gilleo, MEMS and MOEMS packaging challenges, J. Mater. Proc. Manuf. Sci. 8 (4) (2001) 361–379.

606

2. H.W. Markstein, Designing electronics for high vibration and shock, Electronic Packag. Prod. (1987) 40–43.

3. E. Parton, H. Tilmans, Wafer-level MEMS packaging, Adv. Packag. 11 (4) (2002) 21–23.

42

Chapter Forty Two

Hermeticity Tests Dr. Wolfgang Reinert and Dr. Dirk Kähler Fraunhofer Institute for Silicon Technology ISIT, Itzehoe, Germany

42.1 Hermetic Sealing Technology Hermeticity testing is a technology that deals with the transfer of media (gasses) in and out of sealed enclosures based on vacuum science, physics, and chemistry [1]. A number of hermeticity tests with different speciﬁc properties are available to characterize the integrity of a package seal. As the enclosed volume in modern MEMS devices is in the nanoliter range (e.g., less than 0.1 mm³ 1000 μm 2000 μm 50 μm) with a demand for constant atmospheric conditions over 15 years, leak testing becomes a key technology for the package qualiﬁcation. The aim of this chapter is to establish an understanding of the different seal test methodologies for MEMS packages. A focus is set on the Neon Ultra-Fine Leak test newly established at Fraunhofer ISIT for nanoliter vacuum packages and the vacuum lifetime model to predict the vacuum degradation over device lifetime.

42.2 Hermeticity Requirements The speciﬁcations for the seal integrity vary depending on the package construction and the ﬁeld of application. Usually, the leak rate dimensions found in literature are mbar l/s, which are very speciﬁc to vacuum technology. The dimension for leak rate used in this description is Pa m³/s, which is based on international SI-units. The ratio between the dimensions is 1 mbar l/s 0.1 Pa m³/s. Still, the authors prefer the dimension mbar for describing the different test methods (1 mbar 100 Pa). Test methods can be grouped according to their measurement sensitivity; see Table 42.1.

The deﬁnition of hermeticity classes by the authors given in Table 42.1 is geared to the tightened demands of strongly miniaturized vacuum packages. The American standard ASTM F2391-05 “Standard Test Method for Measuring Package and Seal Integrity Using Helium as the Tracer Gas” deﬁnes and quantiﬁes these classes differently but uses the same wording. The most hermetic leak class, “Ultra-ﬁne leaks” in this standard, is deﬁned for helium leak rates 109–1011 Pa m³/s, which is by far inadequate to cover the demands of modern microresonator packages. The leak classes “extra-ﬁne” and “super-ﬁne” are missing and instead are added by the authors [3]. Based on the current knowledge of the authors, it does not make sense to elaborate the leak classes in the minimum leak range even further. Still, it may become necessary to extend the “ultra-ﬁne” leak class down to 1019 Pa m³/s as microresonators with thin ﬁlm sealing and very small evacuated cavity volumes, down to 0.1 nanoliter, reach production level. Δp q Δt V

(42.1)

Equation (42.1) indicates that even small leak rates q induce a fast change of the cavity atmospheric pressure Δp/Δt if the cavity volume V is reduced. Equation (42.1) is adequate to make a fast calculation of the hermeticity requirements of a sealed package for small pressure changes (linear approximation) in the molecular ﬂow regime. For a package with sealed cavity of 0.2 mm³ and an allowed vacuum degradation from initially 0.1 mbar to 0.3 mbar over 15 years, a measurement sensitivity of the hermeticity test of better than 8.4 1018 Pa m³/s is required. A very capable integrated getter may reduce this 607

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Table 42.1 Classiﬁcation of leaks [2]

Class

Leak rate [Pa·m³/s]

[std cc/s ≈ mbar·l /s]

[torr·l/s]

Gross

1 105

1 104

7.5 105

Moderate

107…105

106…104

7.5 107…7.5 108

Fine

109…107

108…106

7.5 109…7.5 1010

Extra-ﬁne*

1011…109

1010…108

7.5 1011…7.5 1012

Super-ﬁne*

1014…1011

1013…1010

7.5 1014…7.5 1011

Ultra-ﬁne*

1018…1014

1017…1013

7.5 1018…7.5 1014

hermeticity requirement for about a factor of 300 [2], down to an air leak rate of 2.4 1015 Pa m³/s. These leak rate requirements for modern microresonant devices are much more demanding than for hermetic hybrid packages, which were the basis to deﬁne the MIL-STD 883. At the moment, no appropriate standard is available to cover these new requirements, and only few hermeticity tests offer sufﬁcient measurement sensitivity.

42.3 Hermeticity Tests Table 42.2 lists the most known hermeticity tests with their integral characteristics. Only three nondestructive leak tests possess high enough measurement sensitivity for modern inertial sensors. Gross leak test, dye penetration, and pressure drop test are not relevant for the characterization of micro packages due to their macroscopic properties. In the following, the relevant hermeticity tests for MEMS packages are described.

42.3.1 Membrane Resonance The free bending of the sensor membrane in absolute pressure sensors may be used to measure the inner cavity pressure. For this, the devices to be tested are chucked on a vertical vibrating ﬁxture in an evacuated chamber to drive the membrane in resonant oscillation; see Figure 42.1. The membrane deﬂection is measured through an optical window by laser interferometry. As the chamber pressure equals the inner cavity pressure of the device, the membrane resonance amplitude will be maximum and the inner cavity pressure is thus known. From the differential measurement before and after a deﬁned exposure in a pressurized test gas, the leak rate for this test gas can be determined. This method is limited to membrane thicknesses below 20 μm, where the ratio of membrane area to membrane thickness affects 608

Table 42.2 Procedures to check the hermeticity of electronic packages

Test

Sensitivity limit/ Cavity volume

Gross leak test 1 106 Pa m³/s [4, 5] V 5 mm³

Characteristics Localization of gross leaks, veriﬁcation of ﬁne leaks detected by He/Kr85 test

Dye penetration [1, 4]

–

Inspection of weldseams, material ﬂaws

Pressure drop [4]

1 106 Pa m³/s

Inspection of pressure tanks and gas installations

Membrane resonance [2]

1 109 Pa m³/s V 0.5 mm³

Requires thin (~20 μm) membrane, may affect sensor structures

Optical 5 109 Pa m³/s deformation [6] V 0.5 mm³ Helium leak test [1, 7]

5 1013 Pa m³/s V 1 mm³

K85 radioactive 1 1013 Pa m³/s tracer [1, 8, 9] V 0.5 mm³

Inspection of metal housings, sensitivity affected by cap geometry Limited to sealed volumes 5 mm³ Handling of radioactive test gas

Q factor monitoring [2]

1 1018 Requires resonator in 2 mm³ V0.001 mm³ vacuum package

Internal pressure [10]

1 1016 Pa m³/s 2 mm³ V0.01 mm³

Integrated μ-Pirani pressure sensor

IR transmission 5 1017 [11, 12] 2 mm³ V0.01 mm³

Transmission of oxidized metal layer. No Getter integration possible.

Residual gas analysis [1]

Destructive test, laborious for small packages

gas volume: 1012 Pal

Hermeticity Tests

CHAPTER 42

streaming out from a leaky package is monitored by a mass spectrometer. The helium stream is measured only once and will be pumped out of the chamber. The measurement resolution changes over the day, as the helium background in the measurement environment increases with time. It is necessary to keep track of the transfer time after helium bombing for every device, as this time delay signiﬁcantly affects the measurement. The evacuation time of the vacuum chamber limits the test to larger cavity volumes, typically 5 mm³ and leak rates below 1 1013 Pa m³/s. It is necessary to perform a gross leak test (bubble test in solvent) after the helium leak test to identify devices with very large leaks.

Fig 42.1 ● Principle of measurement setup for the measurement of membrane resonance.

the measurement sensitivity. This ratio degrades the test performance for smaller devices. The measurement for each device on a wafer is time consuming, as the chamber pressure has to be regulated to ﬁnd the resonance for every individual device. For those devices with integrated resonant structures, the test poses a threat of mechanical overloading of these structures by the vertical vibration. The absolute calibration of the inner cavity pressure is problematic, as the effect of membrane tension and enclosed pressure by outgassing during the wafer bonding process may vary from wafer to wafer and on a wafer itself.

42.3.2 Optical Deformation The test developed by NorCom Systems is based on the high resolved measurement of cap deformation in macroscopic metal-can packages exposed to helium overpressure [13]. With the permanent, time-resolved measurement of the cap deﬂection curves of up to 10 packages at a time, the test can distinguish between ﬁne and gross leak. As a further help, a modulation of the test gas overpressure in the form of pressure impulses is applied to exploit the nonlinear characteristic between membrane deﬂection velocity and pressure impulse for better gross leak identiﬁcation. The measurement sensitivity is similar to the helium leak test when the package walls are not too thick and geometrical package construction does not limit the cap deformation.

42.3.3 Helium Leak Test During the helium leak test, several individual packages are exposed to a pressurized helium atmosphere for a deﬁned time (bombing). Each package is transferred thereafter into a vacuum chamber, where the helium

42.3.4 Kr85 Radioactive Tracer Gas Test The Krypton85 radioisotope emits a γ-radiation with 0.5 MeV during its radioactive decay. This radiation will penetrate typical package materials and can be monitored outside the package. After an exposure in Kr85–N2-mixed gas atmosphere, a certain amount of Krypton will remain in a leaky package. The packages are transferred from bombing to a scintillator counter chamber to register the gamma radiation. The very high detection sensitivity for penetrated Krypton, the independence from package cavity volume (in contrast to helium leak test), and the small effect of transfer delays due to the limited gas mobility of Krypton in comparison to Helium are the positive properties of this test. The radioactive gas demands special handling precautions and is used only diluted with Nitrogen due to legal regulations. The measurement equipment and all seals of the bombing chamber become radioactive with time. The test cannot be applied on the wafer level, as the allocation of measured gamma quanta to an individual device in dense device populations on wafers is not possible. The Kr85 test has to be performed together with a gross leak test to identify very leaky devices.

42.3.5 Internal Pressure Measurement (μPirani) The method of internal pressure measurement applies to miniaturized pressure sensors for the measurement of the pressure increase in a sealed package cavity. Most often, silicon-based resistance bridges are used as Pirani sensors. In operation, a current ﬂow is induced that heats up the resistor. The temperature of the structure can be determined by their resistivity change. A lowered ambient pressure reduces the heat losses over the gas to the substrate, and the temperature of the resistor increases, increasing the resistance. The pressure sensitivity is particularly good for higher pressures (up to 100 mbar), but can be optimized for low cavity pressures 609

PA R T V

Encapsulation of MEMS Components

below 1 mbar by a sensor construction with dominant thermal gas coupling and little suspension coupling. A reference plot has to be taken for a typical μPirani sensor, from which the pressure in every sealed device with integrated μPirani sensors can be determined before and after a test gas bombing. The precondition for a successful test is a very reproducible manufacturing process for the heater structures in respect to distance to substrate and a negligible aging drift of the electrical characteristics of the resistive heater.

42.3.6 IR Transmission Test A cumulative chemical reaction with penetrating test gas is a different methodology to identify leaky devices. One example is the oxidization of a thin copper ﬁlm with oxygen as test gas. It was shown that the degree of oxidization of selected metal ﬁlms can be determined by optical transmission measurements in the infrared spectrum. Pyrex as well as silicon-based packages can be examined by using long wavelength IR radiation (1 μm). The optical transmission of copper ﬁlms increases with the degree of oxidization. The oxygen bombing may be done in heated test gas under pressure (125–150°C) to stimulate oxidation. The measurement sensitivity is increased by decreasing the metal area and metal ﬁlm thickness inside the cavity. A typical area is a 25-μm-round pad with about 30 nm thickness. The test can be performed on the wafer level using a simple IR LED and IR-sensitive camera without IR ﬁlter. The area around the copper can be used to calibrate the picture for 100% transmission. This test prevents the integration of thin ﬁlm getter as this will considerably delay any copper oxidization and no cap metallization is allowed to ensure IR transparency.

42.3.7 Q factor Monitoring The very accurate measurement of the quality factor of a resonator can be exploited to determine the inner cavity pressure in a sealed device. Measuring the differential pressure before and after a test gas bombing allows one to calculate the leak rate of individual devices. The test can be performed with sensors (e.g. gyroscope sensors) or a microresonator integrated into the cavity for the hermeticity measurement only. The very high measurement sensitivity originates from a multitude of continual gas interactions of the resonator with the damping atmosphere inside the sealed cavity. Measurements can be repeated arbitrarily and can be averaged. The resonant measurement and additional electronic low pass ﬁltering suppresses noise. The application of this test method on wafer level is easily achieved, as standard wafer probes can be used. The absolute calibration of the Q factor vs. pressure reference plot (for a golden device) should be taken 610

for the damping atmosphere composition at a typical measurement temperature. Usually, frequency variations of individual resonators over a wafer are not considered when the cavity pressure is determined, but care has to be taken to limit any temperature excursions from the measurement temperature of the reference plot.

42.4 Neon Ultra-Fine Leak Test The Neon Ultra-Fine Leak Test is an elaborated hermeticity test environment with a dedicated vacuum prediction model (Vacuum Lifetime Model) based on quality factor monitoring of microresonating devices. There are some beneﬁts in using Neon as test gas instead of helium or any other noble gas. The test gas Neon is highly mobile to penetrate the ﬁnest leak channels but has a negligible permeation rate at room temperature in SiO2 interfaces often used in the construction of hermetically sealed MEMS devices. Neon is also compatible with integrated getter, as it will not be absorbed and pressure increases due to leaks can easily be monitored. The pressure increase for devices with getter is accelerated for a factor of around 500 when compared to air, as incoming air will be gettered and a pressure increase is achieved only by the Argon content of air. The Neon Ultra-Fine Leak Test procedure for a new device starts with measuring a calibration curve for Q factor over a relevant pressure range, using selected open devices. From this curve, a ﬁt function is derived that will be used to calculate the internal pressure of sealed devices from their measured quality factor; see Figure 42.2. The test procedure starts with a ﬁrst Q factor measurement, followed by Neon bombing in a highpressure chamber. The bombing parameters, exposure time, and pressure are derived from the Vacuum Lifetime Model, depending on the device seal speciﬁcations. To screen for very small leak rates, a longer exposure time is required. No gross leak test is necessary, as leaky devices will lose their vacuum, resulting in very low Q factors that indicate the leak. Devices to be tested can be bombed as full wafers, as diced wafers on tape, or as singulated and even packaged parts. The devices are then transferred to a second Q factor measurement. No negative effect has been observed, up to now at ISIT, with long delay times between bombing and measurement. This may be due to the high content of Argon in air (9.3 mbar), that is like a continual bombing at very low pressure. And also, the driving force for Neon to leave the leaky package is very low, keeping in mind that the gas exchange is driven by the partial pressures only, and the Neon partial pressure in air is comparatively high (1.9 102 mbar) [14]. From the two quality factors, the correlative cavity pressures can be calculated, which are the basis to calculate the Neon conductance of the leak, the Neon leak

Hermeticity Tests

0.02

0.04

Measured environmental pressure (mbar) 0.06 0.08 0.1 0.2

0.4

0.6

CHAPTER 42

0.8

1

Nitrogen Neon Linear fit

20000

10000

4 5 6 7 8 9 10

Q-factor

8000 6000

20

4000

30 Sensor: X2V5

40 50 60 70 80 90 100

2000

Calculated cavity pressure (Pa)

3

1000 2

4

6

8 10 20 Measured environmental pressure (Pa)

40

60

80 100

Fig 42.2 ● Calibration curve for gyroscope sensor X2V5 of Fraunhofer ISIT measured for nitrogen and neon damping gas with uncapped microsensor device. The ﬁt is the basis to determine the cavity pressure of sealed devices from measured Q factors.

Air leak rate (Pa· m3/s)

FHGM 650W22_V5_45° 1E–14 “open oxide process” Neon bombing: 93h @ 3 bar, RT

Leaky devices

1E–15

of yield losses due to surface contaminations or other defects. The test is also quite helpful to ﬁne-tune a sealing process for improved performance in moisture.

Critical air leak rate for device with getter

42.4.1 Basics of Thermodynamic and Vacuum Physics

1E–16 1E–17 1E–18 1E–19 –9|14

12|20

7|26

2|32

7|40

The interaction of gas molecules with each other depends strongly on the particle density n which is correlated to the gas pressure p and temperature T. Under normal conditions the molecules of air do not interact very much, resulting in a very simple relationship between the state variables called the ideal gas law.

Sensor ID

Ideal gas law: Fig 42.3 ● Identiﬁcation of two leaky gyroscope sensors on a wafer.

rate, and ﬁnally the air leak rate. The Vacuum Lifetime Model gives a critical air leak rate allowed for devices in a speciﬁc operating environment. All devices have to comply with this criterion to pass the leak test. As the Neon Ultra-Fine Leak test can be performed for every individual device on a wafer, it is a true 100% screen on wafer level to identify leaky devices; see Figure 42.3. Further packaging efforts like interconnection with ASIC, etc., will then only be performed on qualiﬁed hermetic devices. A side aspect of the test is also the very fast feedback to the encapsulation process in case

p ⋅ V NkBT ⇔ p nkBT nRT

(42.2)

p [Pa] V [m3] N [1] n n

T kB R

pressure inside the volume V cavity volume number of gas molecules inside the cavity [1/m3] particle density [mol/m3] particle density in Mol per m3 [K] temperature [J/K] Boltzmann constant (kB 1.380 6504(24) 10−23 Joule/Kelvin) [J/mol K ] molar gas constant (R NA · kB 8,314510 J/mol · K) 611

Encapsulation of MEMS Components

PA R T V

Even if the molecule interaction may be neglected in the equation of state, it has a dominant inﬂuence on the gas ﬂow behavior. First of all, we have to consider the mean distance between collisions of gas molecules, called the mean free path [15]:

Utilizing the ideal gas law, the equation becomes independent of the temperature: N kBT ni kBT nRT V d L ⇒ ⋅ ( n o ni ) ni dt V

pi

Mean free path: l

kBT 2πd p 1

2

V ⇔ l 2πd N 1

2

1 2πd

2

⋅

molecule

1 n

(42.3) 6, 8 ⋅ 10−5 m ⋅ mbar ⇒ lair at 20°C[m] p[mbar]

⇔

n i , n o

[m] [m]

(42.6b)

(42.4) ni, no

l dmolecule

d L ⋅ ( n o n i ) n i dt V

(42.6a)

mean free path molecule diameter

The gas ﬂow behavior depends not only on the mean free path l , but also on the diameter d of the gas ﬂow channel. The ratio of both dimensions is called the Knudsen number K = l/d. Depending on its value, different ﬂow regimes are distinguished (Table 42.3). The mass ﬂow between two regions with different pressure is typically described in analogy to Ohm’s law [17]:

[1/m3] [mol/m3]

particle density particle density

For a viscose gas ﬂow, the conductance L is proportional to the average pressure p divided by the viscosity η of the gas. In the case of a molecular gas ﬂow, conductance L is proportional to the average speed of the molecules c , but independent of the pressure and gas viscosity. viscose ﬂow: p ⋅ geometry factor η p pi p o with average pressure 2

Gas ﬂow:

L

d d pi : L ⋅ ( po pi ) ( pi ⋅ V ) V ⋅ dt dt L d pi ⇔ ⋅ ( po pi ) V dt

q :

(42.5)

q [Pa m3/s] gas ﬂow or, in our case, the leak rate L [m3/s] conductance po – pi [Pa] difference between outside and cavity pressure

Table 42.3 Dependency of the ﬂow regime from the Knudsen number K = l / d and Reynolds number Re ρ··d/η [16]

Pressure range in standard vacuum physics

(42.7)

For viscose gas ﬂow, the geometry factor typically is proportional to the square of the cross-sectional area divided by the length of the gas ﬂow channel. molecular ﬂow: L c ⋅ geometry factor 8 RT c with average particle velocity (42.8) πM For molecular gas ﬂow, the geometry factor typically is proportional to the cross-sectional area divided by the length of the gas ﬂow channel.

Knudsen number

Flow regime

K 102

Turbulent ﬂow

for Re 4000

high pressure, high gas velocity

42.5 Vacuum Lifetime Model

Viscose ﬂow

for Re 2300

low pressure or low vacuum

In a simple model a hermetic encapsulated device can be described as a cavity with vacuum inside and normal air pressure outside. First, let us assume a leak channel with a diameter of some microns, which is much larger than the mean free path l of the molecules at air pressure which is about 68 nm. Therefore, we can expect a viscose gas ﬂow at the entrance of the leak channel.

102 K 0.5

Knudsen ﬂow

medium vacuum

0.5 K

Molecular ﬂow

high vacuum

612

Hermeticity Tests

Assuming a vacuum of 1 mbar or better, the mean free path inside the cavity will be much larger than the channel diameter, resulting in a molecular ﬂow behavior. Under these conditions we have to assume a continuously changing gas ﬂow behavior from viscose at the outside to molecular ﬂow at the inside. The calculation will be much easier if we can assume molecular ﬂow in the hole leak channel. To verify this assumption, let us assume a cavity with a volume of 1 mm3 and a single leak which generates a pressure increase of 1 mbar per year. Since the outside pressure of 1000 mbar is much greater than the cavity pressure, we can derive the conductance directly from Eq. (42.5): d L L ⋅ ( po pi ) ≈ ⋅ po and pi dt V V 1mbar 100Pa d pi 1year 365 ⋅ 24 ⋅ 60 ⋅ 60 s dt ≈ 3 ⋅ 106 Pa s 3 ⋅ 106 Pa s ⋅ 109 m3 L ⇔ 105Pa 20 m3 3 ⋅ 10 s

Several academic groups recently have been investigating the ﬂow characteristic of ultra-ﬁne leaks. Roy et al. [18] proved that the gas ﬂow is proportional to the pressure difference; thus, the conductance is independent of the pressure. Holt et al. [19] investigated the inﬂuence of the molecular mass on the gas ﬂow. For the investigated air gases H2, He, Ne, N2, O2, Ar, CO2, and Xe, they validated the inverse square root dependency from the molecular mass, which is proportional to the particle velocity. The next step in our Lifetime Model is to solve the gas ﬂow Eq. (42.6) for a molecular ﬂow situation:

d L ⋅ ( n o n i ) ⇒ n i dt V

⎛ L ⎞ n i( t ) n o ( n o n i( t 0 )) ⋅ exp ⎜⎜ t⎟⎟⎟ with L ∝ ⎝⎜ V ⎠

2 r3 ⋅π⋅c ⋅ with 3 l 8 RT 463 m s cair at room temperature πM and l 100 μm 463 m 2 ⇒ Lmolecular, circular tube ⋅ π ⋅ 4 s ⋅ r 3 3 10 m 1 ⋅ 105 3 ! 3 ⋅ r 3 ⋅ 1020 m s s ⇒ r 1.5 nm In classical vacuum physics, molecular ﬂow is assumed if the mean free path l is larger than the typical diameter of the tube. For air, the mean free path is approximately 68 nm which is much larger than the estimated diameter of 3 nm. For this reason, we can assume molecular ﬂow for the whole leak channel. Even if parts of the leak channel are much wider, the ﬂow will be limited by the smallest region of the path. Furthermore, we don’t need any knowledge about the geometry of the leak channel for our lifetime calculation. The only assumptions we need are the proportionality of the conductance L to the particle velocity c and the independency of the pressure.

T M

To remove the implicit dependency of the conductance L from the temperature and molecular mass, we deﬁne a normalized conductance ˜L which is independent of the bombing conditions:

For this rough estimation, we assume the leak to be a long circular tube with a length l equal to the width of the sealing frame: Lmolecular, circular tube

CHAPTER 42

T ⇔ L L ⋅ M

L L ⋅

M T

(42.9)

With this deﬁnition the solution of the gas ﬂow equation becomes as follows: ⎛ L n i (t ) n o ( n o n i (t 0 )) ⋅ exp ⎜⎜⎜ ⋅ ⎜⎝ V

⎞⎟ T ⋅ t⎟⎟ M ⎟⎠ (42.10)

V ⇒ L t

n o n i ( t ) M ln T n o n i ( t 0 )

(42.11)

In case of the Neon Ultra-Fine Leak Test, Eq. (42.11) will be used to calculate the normalized conductance from the bombing conditions and the cavity pressure derived from the Q factor measurement. Utilizing the ideal gas law p nkBT, the equation can be written in a more convenient way: pbombing L

V

MNe

tbombing

Tbombing

ln

Tbombing pbombing Tbombing

pcavity after bombing TQ-measurement pcavity before bombing TQ-measurement (42.12) 613

PA R T V

Encapsulation of MEMS Components

Required bombing time in Neon 1000000

Ne bombing with 3.5 bar at 20°C Initial cavity pressure: 0.1 mbar Pressure increase: 0.01 mbar ‹ › 3σ

Bombing time (h)

100000 10000

Cavity volume 100 mm3 10 mm3 1 mm3 0.25 mm3

1000 100 10

~6h

1 0,1 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 Air leak rate (mbar · I/s)

Fig 42.4 ● Bombing conditions for different cavity volumes and critical air leak rates according to device hermeticity requirements.

If the Neon bombing and Q factor measurement are both done at room temperature, the temperature dependence can be canceled. Figure 42.4 shows the required bombing time in Neon for different maximum permissible leak rates in 4 different device cavity volumes as calculated by Eq. (42.12). By now we have used the Lifetime Model to derive a normalized conductance from the Q factor measurement before and after Neon bombing. With this knowledge we can predict the pressure increase inside of our cavity during lifetime. For an exact calculation we have to calculate Eq. (42.10) separately for any gas component of the air (Table 42.4). Unfortunately, the result depends on the exact temperature proﬁle. To perform these calculations, Eq. (42.10) has to be calculated iteratively for every temperature step in the device lifetime. Obviously a computer is needed to perform these calculations. In some special cases, however, the calculation can be done easily in an analytical way.

42.5.1 Cavity with Ideal Getter We assume that the cavity is equipped with an ideal getter which never saturates and absorbs any gas except noble gasses. Therefore, the atmosphere inside the cavity consists only of noble gasses. An initial gas load ni(t 0) will be incorporated during the wafer bonding and leak test. In the case of the Neon UltraFine Leak Test, this initial pressure is one parameter which is derived during the leak test. If the device is stored and operated during lifetime in normal air, Argon is the dominant noble gas which leaks into the cavity (Table 42.4). Under these conditions Eq. (42.10) can be used directly, with MAr 40 g/mol 614

Table 42.4 Partial pressure and molecular mass of different gasses usually found in the air

Gas

Molecular mass

Partial pressure at 1000 mbar

Nitrogen, N2

28 g/mol

780.9 mbar

Oxygen, O2

32 g/mol

209.5 mbar

Argon, Ar

40 g/mol

9.3 mbar

Carbon dioxide, CO2 76 g/mol

0.3 mbar

Neon, Ne

20 g/mol

1.8 102 mbar

Helium, He

4 g/mol

5.0 103 mbar

Krypton, Kr

84 g/mol

1.1 103 mbar

Hydrogen, H2

2 g/mol

5.0 104 mbar

Xenon, Xe

131 g/mol

8.8 105 mbar

Air

29 g/mol

1000 mbar

and n o,Ar po,Ar /RT 9.3mbar/RT . The result of this calculation for two arbitrarily chosen devices is shown in Figure 42.5.

42.5.2 Getter Saturation In real devices the getter capacity is quite limited due to the restricted volume which can be used. In the rare case that the saturation behavior of the getter material is known in detail, it can be used together with Eq. (42.10) to calculate the pressure increase of the air gases during lifetime. Typically, the necessary dependency of the getter rate from the getter saturation is unknown. In this case an estimated total getter capacity has to be used for the calculations. Assuming an ideal getter behavior until the saturation capacity is reached, the leak rate is independent of time. d L L ⋅ n o ⋅ n i dt V V

T ⋅ n o ⇒ M

⎛d ⎞ absorbed gas molecules [mol] V ⋅ ∫ ⎜⎜ n i ⎟⎟⎟ d t ⎜⎝ d t ⎠ T ⋅ n o ⋅ t L ⋅ n o ⋅ t L M

(42.13) The number of absorbed gas molecules is proportional to the particle density in the outside and the square root of the temperature. By calculating the particle density from the ideal gas law, we get the surprising

Hermeticity Tests

CHAPTER 42

Pressure increase over lifetime Cavity volume: 0.25 mm3 Initial cavity pressure: 0.1 mbar Getter capacity: 6 × 10–6 mbar l/s

/s

bar ·

r ba

4

–1

0 –14 m

1

·l

m

10

ir

=

1·

qa

qair = 2·1

Cavity pressure (mbar)

10

Ideal getter Real getter Real getter

0,1

0

5

10

15

20

25

Time (a)

Figure 42.5 ● Pressure increase before and after getter saturation compared to an ideal getter that does not saturate.

result that the number of absorbed gas molecules is proportional to the inverse square root of the temperature: po ⇒ absorbed gas molecules[mol] RT po L (42.14) ⋅ ⋅t R TM

With this simpliﬁcation we can calculate the saturation time of the getter from Eq. (42.14).

n o

tsaturation

R M ⋅ T ⋅ getter capacity[mol] L ⋅ po,air (42.16)

The reason for this curious behavior is the assumption that the air pressure po is kept constant independent of the temperature T, and thus the particle density in the air is reduced at higher temperatures! This behavior is the main reason for us to use the particle density instead of the cavity pressure for our calculations. With Eq. (42.14) we can only calculate the absorbed molecules of a single gas component. To achieve the full effect of the air bombing, we have to add the calculation results for all air components without the noble gases which are not gettered. Fortunately, we can simplify this calculation with the deﬁnition of a mean molecular mass. The partial pressures po,k and molecular masses Mk are taken from Table 42.4:

M air without noble gases

⎞⎟2 ⎟⎟ ⎟⎟ ⎟⎟ ⎟⎟ ⎟⎟ ⎟ ⎠⎟⎟ 28, 80 g/mol

⎛ ⎜⎜ ⎜⎜ ∑ pk ⎜⎜⎜ po,k ⎜⎜ ⎜⎜ ∑ Mk ⎜⎝

Again we see an increase of the getter lifetime with rising bomb temperature. A further increase of the saturation time can be expected due to the diffusion of absorbed gas molecules into the getter volume at elevated temperatures; thus, the getter capacity is enhanced. Since Eq. (42.14) is linear in time, we can easily accumulate over periods with different bombing temperatures: 1 L po,air dt ⋅ ⋅∫ R T M t L po,air ⋅∑ k ≈ ⋅ R Tk M k

absorbed gas molecules [mol]

(42.17)

(42.15)

Equation (42.17) can also be used to calculate a critical conductance L max , i.e., the maximum conductance

615

PA R T V

Encapsulation of MEMS Components

which is acceptable for a given getter capacity and temperature proﬁle: L max getter capacity[mol] ⋅

n i (t ) n air (Tmin )

R M po,air ⋅ ∑ k

Equation (42.10):

tk Tk (42.18)

42.5.3 Estimated Device Lifetime without Getter To calculate the pressure increase inside of a device which has no getter, Eq. (42.10) has to be calculated independently for each atmospheric gas (Table 42.4). In case of a non-constant temperature proﬁle, the calculation has to be performed iteratively. For a given maximum cavity pressure, the device lifetime can be derived by simple numeric calculations (Figure 42.5). An analytic solution is only possible if we assume a constant temperature and an atmosphere consisting of pure nitrogen. In this case the device lifetime can be estimated by Eq. (42.10), resulting in a save value which is a little bit smaller than the correct numerical value.

⎛ L ⎜ ⋅ ⎜⎝ V

[ n air (Tmin ) n i (t 0)] ⋅ exp ⎜⎜⎜

⎞⎟ Tmin ⋅ t⎟⎟⎟ ⎟⎠ MN2

Utilizing the ideal gas law p nkBT, the particle density can be replaced by the pressure at room temperature (RT) or bombing temperature Tmin: pi,RT

pair ⇒ R ⋅ Tmin ⎤ ⎡ T T pi,RT( t ) pair RT ⎢ pair RT pi,RT( t 0 )⎥ ⎥ ⎢ Tmin Tmin ⎦ ⎣ ⎛ L ⎞ ⎟ Tmin ⎜ ⋅ exp ⎜⎜ ⋅ ⋅ t⎟⎟⎟ ⎜⎜ V M ⎟⎠ N2 ⎝ T pair RT pi,RT( t ) MN2 V Tmin ⇒ device lifetime ⋅ ln T Tmin L pair RT pi,RT( t 0 ) Tmin n i

R ⋅ TRT

and n air(Tmin )

Tmin smallest temperature expected during lifetime.

References 1. H. Greenhouse, Hermeticity of Electronic Packages, Noyes Public, 1999. 2. W. Reinert, Neon Ultra-Feinlecktest zur Vorhersage der Vakuumerhaltung resonanter Mikrosensoren, in: Technische Fakultät, vol. PHD, Christian-Albrechts-Universität, Kiel, 2007, p. 131. 3. ASTM, Standard Test Method for Measuring Package and Seal Integrity Using Helium as the Tracer Gas, 2005. 4. D.R. Morrow and G. Baret, A package integrity primer, 2005. 5. G. Mil Std, MIL-STD-883G, METHOD 1014.12 SEAL, 2006. 6. S. Norcom, Optical leak testing, 1995. 7. D. Stroehle, On the penetration of gases and water vapour into packages with cavities and on maximum allowable leak rates, in: Reliability Physics Symposium, 1977, pp. 101–106. 8. Isovac, How the RADIFLOW process works, 2004. 9. S. Ruthberg, Graphical solution for the back pressurization method of hermetic test, Graphical solution

616

10.

11.

12.

13. 14.

for the helium leak detector and radioisotope methods of hermetic test, Master graphs and instructions, in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. CHMT-4, R. Stanley, Ed.: National Bureau of Standards special publication 400–473, 1981. S. Brian Hawks, Thin-ﬁlm technologies for hermetic and vacuum packaging of MEMS, 2004. C. Junseok, H. S. Brian, and N. Khalil, A micromachined Pirani gauge for vacuum package characterization, 2004. F. Gueissaz, Ultra low leak detection method for MEMS devices, in: International Conference on Micro Electro Mechanical Systems, 2005. S. Norcom, Optical leak testing, 2005. D. Baumer, E. Riedel, J. Bierhals, M. Eschwey, C. G. Okcek, J. Grefer, R. Hamm, D. Heeschen, H. Hiller, D. K. uster, H. Lugmayr, D. Schmicker, and W. Schreckenberg, Gase-Handbuch, in Messer Griesheim

15.

16.

17.

18.

19.

Gase Handbuch, E. R. D. Baumer, Ed., Messer Griesheim GmbH, 1990, pp. ff. Zengerle, MST Technologien & Prozesse, in IMTEK. Freiburg, WS 2006. M. Wutz, H. Adam, and W. Walcher, Theorie und Praxis der Vakuumtechnik. Braunschweig: VIEWEG, 1988. G. Ecke, Vorlesung Vakuumtechnologie in der Halbleiterindustrie, 1999. S. Roy, S.M. Cooper, M. Meyyappan, B.A. Cruden, Single component gas transport through 10 nm pores: experimental data and hydrodynamic prediction, J. Memb. Sci. 253 (2004) 209–215. J.H. Holt, H.G. Park, Y. Wang, M. Stadermann, A.B. Artyukhin, C.P. Grigoropoulos, A. Noy, O. Bakajin, Fast mass transport through sub-2-nanometer carbon nanotubes, Science 312 (2006) 1034–1037.

Appendix 1

Common Abbreviations and Acronyms

AAS

Atomic Absorption Spectroscopy, a tech nique to analyze impurities AFM Atomic Force Microscope, used in wafer surface nanotopography characterization ALD Atomic Layer Deposition ANSI American National Standards Institute AOG Axial Oxygen Gradient, oxygen distribution in crystal along the axis APCVD Atmospheric Pressure CVD ASIC Application-Speciﬁc Integrated Circuit ASTM American Society for Testing and Materials, developed standards formerly to silicon technology, SEMI has taken that role now BCB Benzocyclobutene, known also under the commercial name Cyclotene® BDD Bulk Defect Density BESOI Bonded and Etchback SOI BGA Ball Grid Array BMD Bulk Micro Defect, typically silicon dioxide precipitate, stacking fault or combination of both, typical density after thermal treat ments can be 107 to 1010/cm3 BOE Buffered Oxide Etch BOX Buried Oxide in SOI wafers BPSG Borophosphosilicate glass BSD Back Side Damage, a wafer back side get tering method BTAB Bumped Tape Automated Bonding CBGA Ceramic Ball Grid Array CC Chip Carrier CCC Ceramic Chip Carrier CER-DIP CERamic Dual In-line Package CFP Ceramic Flat Pack

CGBA CMOS CMP COB COP

CPGA Cpk CQFP CSP CZ

CVD D/B DBG DIL DIN DIP DPW DRIE DSP

Ceramic Ball Grid Array Complementary Metal Oxide Semi conductor ChemoMechanical Polishing or chemical mechanical polishing Chip-On-Board Crystal Originated Particle (or Pit), a vacancy agglomerate formed during crystal growth, also known as Flow Pattern (term related to a speciﬁc test method); seen on polished surface as a light scatterer in par ticle inspection, typical size 50–160 nm (size and density depends on crystal growth parameters). Degrades gate oxide integrity. Ceramic Pin Grid Array Process capability index Ceramic Quad Flat Pack Chip Scale Package A crystal growing technology named after its inventor Jan Czochralski; crystal is grown by pulling it from a silicon melt held in a crucible. A vast majority of silicon crys tals are grown with a CZ technology Chemical Vapor Deposition Die Bonding Dicing Before Grinding Dual InLine German industry standard (Deutsche Industrie Normen) Dual Inline Package Dies Per Wafer Deep Reactive Ion Etching Double Side Polished

617

Appendix 1

DZ

ED EDP

EMI ESF ESP

FC FEM

FDP

FDTD

FIB FPD FQA FTIR

FZ

GBIR GFA GOI Gr GTIR GUI HARM HZ IC ICP-MS IG IO 618

Denuded Zone, oxygen lean (and defect free) area near the wafer surface in annealed wafers Electro Deposition Ethylene Diamide Pyrocatechol, in water mixture used as anisotropic etchant of sili con, toxic ElectroMagnetic Interference Epitaxial Stacking Fault Electrostatic Potential, the potential energy of a test unit charge in a given charge dis tribution (Note that the test charge is assumed not to disturb the given charge distribution) Flip Chip Finite Element Method, a popular numeri cal method to solve various partial differen tial equations by dividing continuous space and time using a set of Focal Plane Deviation, a wafer ﬂatness spec iﬁcation, distance of the plane ﬁtted on the wafer surface to the parallel focus plane of the optical system Finite-Difference Time-Domain, a popular scheme to numerically solve time-depend ent Maxwell equations by discretization of continuous space and time elements com bined with appropriate basis functions Focused Ion Beam, commonly refers to a focused ion beam instrument Flow Pattern Defect, see COP Fixed Quality Area of a silicon wafer Fourier Transform Infrared Spectroscopy, e.g., to measure oxygen and carbon content in wafers and epi thickness A Float Zone crystal growing technology; a method where a crystal is grown from a small pool of silicon melt formed on a sili con feedrod A term to deﬁne global wafer ﬂatness, most commonly used, see SEMI M1 Gas Fusion Analysis, to measure oxygen content in heavily doped silicon Gate Oxide Integrity Grasshof number Global Total Indicated Reading, see SEMI M1 Graphical User Interface High Aspect Ratio Micromachining Hot Zone Integrated Circuit Inductively Coupled Plasma Mass Spectroscopy Internal Gettering Input Output

IR JEITA

JIS LCC LCCC LDV LED LIGA

LLCC LLPD LOCOS LPCVD LPD LPS LSE LST

LTCC LTO

LTV MBE MCM MCM-C MCM-D MCM-P MCP MCz

MEMS MD

MIT-IR MLB MLP MLPWB MOEMS MST

Infra Red light Formerly known as JEIDA; Japan Electronic and Information Technology Industries Association, develops Japanese standards for silicon materials and technology Japanese Industry Standard Leaded Chip Carrier Leadless Ceramic Chip Carrier Laser Doppler Vibrometer, an interferometer Light Emitting Diode Lithographie, Galvanoformung und Abformung (German), aka lithography, electroforming and molding Leadless Chip Carrier Large Light Point Defect Local OXidation Of Silicon Low Pressure Chemical Vapor Deposition Light Point Defects, same as LLS Lateral Photo Voltage Scanning Latex Sphere Equivalent, reference for particle size Light Scattering Tomography; an optical method for the characterization of defects in silicon, based on the scattering of laser light LLS (Localized Light Scatterer), a fea ture on silicon wafer surface scattering light in surface inspection Low Temperature Co-ﬁred Ceramic Low Temperature Oxide, used for example in back sealing of heavily doped wafers to minimize dopant outdiffusion Local Thickness Variation Molecular Beam Epitaxy MultiChip Module MCM-Ceramic MCM-Dielectric MCM-Plastic MultiChip Package A Magnetic Czochralski crystal growing technology, silicon melt is in magnetic ﬁeld during crystal growth Micro Electro Mechanical System Molecular Dynamics, a popular method to analyze materials properties by numerically solving atomic or molecular motions based on the Newton equations Multiple Internal Transmission InfraRed spectroscopy Multi Layer Board Micro Leadframe Package Multi Layer Printed Wiring Board Micro Electro-Optical Mechanical System Micro Systems Technology (Same deﬁnition as MEMS)

Appendix 1

NTD

NTV Oi OLB OPP

OSF

PACE PBGA PCAD PCB PCI PGA PLCC PMMA

PPGA PQFP PSD PSI

PUA PWA PWB P/V QFP QSOP Ra Ra RFID RGA RMS ROG RRG Rq RT RTA SAW SBIR SCP

Neutron Transmutation Doping, an intrinsic FZ crystal turned to high resistivity N-type crystal; a very uniform resistivity can be achieved Nonlinear Thickness Variation (old term, rarely used today) Interstitial oxygen in silicon Outer Lead Bond Optical Precipitate Proﬁling; an optical technique for characterizing bulk defects in silicon Oxidation induced Stacking Fault, a defect formed in oxidation, especially in wet oxi dation of a silicon wafer. OSF density can be minimized by engineered wafer speciﬁ cations and by tuning the oxidation process. Plasma Assisted Chemical Etching Plastic Ball Grid Array Packaging Computer-Aided Design Printed Circuit Board Peripheral Component Interconnect Pin Grid Array Plastic Leaded Chip Carrier Poly(methyl methacrylate) or poly(methyl 2-methylpropenoate), a transparent ther moplastic used as a resist in lithography Plastic Pin Grid Array Plastic Quad Flat Pack Power Spectral Density function Phase Shifting Interferometry, an inter ferometric method for measuring surface topography Percent Usable Area Printed Wiring Assembly Printed Wiring Board Peak to Valley, e.g., in roughness measurements Quad Flat Pack Quarter Size Outline Package Rayleigh number Average value of surface roughness Radio Frequency IDentiﬁcation Residual Gas Analysis Root Mean Square Radial Oxygen Gradient, radial variation of oxygen in silicon wafers Radial Resistivity Gradient, radial variation of resistivity in silicon wafers Root-mean-square value of surface roughness Room Temperature Rapid Thermal Anneal Surface Acoustic Wave Site ﬂatness, back side reference Single Chip Package

SD SEMI SFQR

SIMOX

SIMS

SIRM

SMC SMD SMT SO SOC SOI SOS SOT SPM SPV SRP SSIS

SSOP SSP STIR TIR TMAH

TO TPMS TQFP TSOP TSSOP TTV

TXRF

UBM

Small Dual in-line package Semiconductor Equipment and Materials International A term to deﬁne local ﬂatness of a silicon wafer, front reference, a most commonly used site ﬂatness deﬁnition, see SEMI M1 Separation by IMplantation of OXygen, SOI wafer produced by oxygen implanta tion and anneal Secondary Ion Mass Spectroscopy; a method for measuring impurities based on mass spectrometry of ions generated from the sample through ion bombardment Scanning InfraRed Microscope; a scanning optical microscope that uses an infrared laser as light source Surface-Mounted Component Surface Mount Device Surface Mount Technology Small Outline package System On Chip Silicon On Insulator, a silicon wafer with a sandwich structure Silicon On Sapphire Small Outline Transistor Scanning Probe Microscope Surface PhotoVoltage, one method to meas ure minority carrier recombination lifetime Spreading Resistance Proﬁling, a method to measure resistivity proﬁles in small scale Scanning Surface Inspection System; auto mated instruments for the optical inspec tion of the quality of polished surfaces Shrink Small Outline Package Single Side Polished Site TIR Total Indicator Reading, a term used to deﬁne silicon wafer global ﬂatness, see SEMI M1 TetraMethylAmmonium Hydroxide, in water mixture used as anisotropic etchant of silicon Transistor Outline package Tire Pressure Measurement System Thin Quad Flat Pack Thin Small Outline Package Thin Shrink Small Outline Package Total Thickness Variation, thickness vari ation of the wafer measured from several points, in MEMS applications typically 1 μm, see SEMI M1 Total reﬂection X-Ray Fluorescence Spectroscopy, a surface metal analysis tech nique capable of sensitivity down to 1010 at/cm2 (Cu) Under-Bump Metallurgy 619

Appendix 1

USOP UTQFP VPD

W/B WLP ZD

Ultra Small Outline Package Ultra-Thin Quad Flat-Pack Vapor Phase Decomposition, a technique where a surface oxide of silicon wafer is dissolved with HF-vapor. Subsequently the residue on the surface is collected with a small chemical droplet traversed over the wafer surface. This method enhances the detection limit of TXRF by factor 10 or more. It is used also together with AAS technique. Wire Bonding Wafer Level Packaging Zero Dislocation

Deﬁnitions Actuator A device performing mechanical work Anisotropic etch A selective etch that exhibits differ ent etch rate on different crystallographic planes Annealed wafer A silicon wafer, where a COP-free sur face area has been formed through annealing under hydrogen or neutral atmosphere Anodic bonding A technique to bond silicon to glass under electric ﬁeld and elevated temperature Aspect ratio The ratio of the long dimension to one other dimension in two- or three-dimensional structure Autodoping Appears in epi wafers, a phenomenon where dopant from substrate is incorporated into growing epi layer Backseal Silicon dioxide (typically LTO) ﬁlm, which is preventing dopant outgassing from the back surface, used in heavily doped wafers, reduces autodoping BioMEMS MEMS for biological, biomedical or analyti cal applications Bosch process A DRIE technology to achieve high aspect ratio etching, developed at Bosch Bow Shape error of silicon wafer; distance of the centerpoint of the unclamped wafer to the reference plane formed by three equally spaced support points near the periphery of the wafer. Typical values for the 150 and 200 mm wafers are below 30 μm Buckling Collapse of mechanical structure due to excessive compressive stresses Bulge test A method for determining material proper ties of thin ﬁlms based on the deﬂection of the ﬁlm caused by uniform pressure Compressive stress Axial stress producing a shortening of the body Crow’s foot Small shape crack on 100-wafers and Y-shape crack on 111-wafers, coming typically from hard contact between wafer and point-like object 620

Crystallographic orientations, conventions of notation In notation distinction is made between planes and directions with different types of bracket: Plane (100) Family of planes {100} Direction [100] Family of directions 100 Denuded zone A zone near the wafer surface, where oxygen is diffused out through thermal treatments and BMD concentration is close to zero Dimple A shallow round depression on a wafer surface, large dimples can be seen visually under suitable illumination Dislocation A linear crystal lattice defect; a moving dis location causes translation of the lattice parts, dislo cation content in a good silicon wafer should be zero Dislocation etch pit An etch pit is formed on the pref erentially etched wafer surface where dislocation is coming to the surface Dopant striation rings Circular features seen on heavily doped wafer surfaces coming from dopant variations along the axis of a silicon crystal. Especially in heavily boron doped wafers striation rings can be visible Eddy Current Gauge An instrument for measuring the resistivity of a bulk material Elastic deformation Reversible change in the shape of a body subject to stress Ellipsometry An optical technique for measuring opti cal and structural properties of thin ﬁlms Eltran SOI wafer produced using porous silicon for layer transfer, trade mark of Canon Epitaxial layer A single crystalline layer of element(s) grown on a single crystalline substrate; the orienta tion of the substrate is copied on the growing layer Etch stop A layer or interface in the structure stop ping etching (for instance P layer stopping alkaline etching) Eutectic bonding A technique to join materials with a metal alloy having lower melting temperature, e.g., silicon-to-silicon using a gold alloy melting at low temperature Fabry–Perot interferometer An optical interferometer consisting of two parallel, highly reﬂective mirrors; also called an etalon Flatness A deviation of the wafer front surface from the ideal reference plane; there are several ways to express the wafer ﬂatness, it can be local (site) or global ﬂatness and there are several ways to specify reference plane. SEMI M1, Appendix 1 discusses various speciﬁcations

Appendix 1

Flexular rigidity Force couple required to bend a rigid structure to a unit curvature Four point probe An instrument for measuring the resistivity of a material Fracture toughness A parameter describing the strength of bonding between wafers Gettering A method to immobilize impurities and make them inactive. In silicon technology, gettering can be done with BMD’s, with thin ﬁlms or mechani cal damage (polyback, BSD) or with heavily diffused areas (like phosphorus or boron diffusion) Glass frit bonding A technique to bond wafers using glass powder having low melting temperature Haze An area defect on a wafer surface causing light scattering, caused by impurity ﬁlm; small, dense pits or by microroughness Hillock A hill-like surface defect in wafers Interferometer A displacement measuring instrument based on the interference of coherent light beams Lineage A small angle grain boundary caused by array of dislocations Microroughness Small scale roughness of polished surface Mound A rounded protrusion on the wafer surface, seen especially on an epi wafer; can also have facets Nanoindentation A method of measuring mechanical properties by pressing into the sample a very small hard tip whose mechanical properties are known Orange peel Rough wafer surface seen under suit able illumination with unaided eye, typically results from too low material removal in polishing or from improper polishing conditions Phonon Quantum of lattice vibration in solid matter Pit A depression on a wafer surface. Sides of the pit are more steeply sloped compared to dimple, which has rounded sides Plastic deformation Irreversible change in the shape of a body subject to stress Poisson’s ratio A coefﬁcient giving the ratio of the transverse strain (normal to the applied load), to the axial strain (in the direction of the applied load) Polyimide Flexible polymer of imide monomers, used as an adhesive and photoresist Proﬁlometry Electromechanical or optical techniques for measuring surface topography Pull-in voltage Voltage that causes electrodes to move into contact in an electrostatically actuated capaci tive structure Raman spectroscopy An optical method used for meas uring phonon energies in solid materials

Residual stress Stress that remains in a material or structure after processing, in the absence of external forces or thermal gradients Resistivity A parameter describing a material’s ability to conduct electricity Sacriﬁcial layer A layer in a multilayer structure that is intentionally removed to release the layers above Saw mark Surface irregularity left on wafer surface after wafer slicing coming from ID-blade or from wires Secco etch A chemical etching method for characteriz ing defects in silicon Shallow etch pit Similar to pit, but seen only under micro scope with higher magniﬁcations, if density of shallow etch pits are high, they can be seen also as a haze Sheet Resistance For a thin ﬁlm, resistivity divided by layer thickness Sirtl etch A chemical etching method for characterizing defects in silicon Slip Dislocation movement causes plastic deformation in a crystal; in silicon wafers are normally arranged on distinct shear planes, which are visible under micro scope or with higher deformation with unaided eye SmartCut Trade mark of Soitec, SOI wafer produced by bonding and layer exfoliation Sori Originally Japanese deﬁnition of shape error, maximum distance above, plus the maximum dis tance below the front surface best-ﬁt plane of a free, unclamped substrate Stacking fault A 2-dimensional defect in the crystal, fault in the stacking sequence of the atoms in crys tal, in silicon their habit plane is {111}, which means that on (100) wafer surfaces stacking fault lines are in [110] directions Stiction Unwanted adhesion of moving part to sub strate or another moving part Stoney’s formula A formula linking wafer curva ture and stress in the thin ﬁlm deposited onto the wafer Strain The elongation or compression caused by stress Strain gauge A device used to measure the strain of an object Stress Force per unit area Supercritical drying Drying or cleaning the product with liqueﬁed gas (e.g., CO2) at a pressure above the triple point Swirl Small, shallow pits formed in concentric or heli cal formation of wafer surface, seen after preferential etching, seen visually under collimated light Taper Error in the wafer shape, thickness variation from edge to edge of a wafer 621

Appendix 1

Tensile stress Axial stress producing an elongation of the body Warp Error in the wafer shape in free-standing wafer (non-chucked), distance from the lowest point on wafer surface to the highest point μ-PCD Microwave Photoconductive Decay Wright etch A chemical etching method for character izing defects in silicon Young’s modulus Coefﬁcient of elasticity given by the ratio of stress to strain

List of Some Commonly Used MEMS Related Computational Programs IntelliSuite v8.5 Electrical, piezo-electrical, mechanical, electromagnetic, ﬂuidic and thermal analysis tools for executing linear or nonlinear static or transient analysis http://www.intellisensesoftware.com/

622

CoventorWare Integrated toolset for designing MEMS and microﬂuidic systems, evaluating their performance and optimizing them for manufacturability http://www.coventor.com/MEMS.html MEMS Pro v6.0 CAD tool suite for the design and analysis of MEMS in mechanical, thermal, magnetic, ﬂuidic, optical, and electrostatic domains including their associated elec tronics and packaging http://www.softmems.com/mems_pro.html Materials Explorer 4.0 Modeling and analytical capabilities for the full spec trum of molecular dynamics http://www.computers.us.fujitsu.com/www/products_ bioscience.shtml?products/bioscience/materials_ explorer

Appendix 2 Nanoindentation Characterization of Silicon and other MEMS Materials P. Zachariasz, K. Brudzin´ski, J. Gronicz, S. Nagao and R. Nowak The Nordic Hysitron Laboratory, Helsinki University of Technology, Espoo, Finland

Introduction

1 Nanoindentation Method

The very rapid and progressive process of miniaturiza tion of electromechanical devices, which is appreciable over the last few decades, simultaneously demand a high standard for both materials and base components used in prefabrication process. The potential of inte grating a MEMS (Micro Electro-Mechanical System) device together with a complete control of electric cir cuits implemented at individual chip, is nowadays one of the leading ideas in the ﬁeld of micro- and nanoscale systems. MEMS technology, which is commonly based on silicon material, either as fundamental constructive ele ment or as an excellent substrate for other products of microfabrication technology, supplies an excellent capa bility for that purpose. However, further miniaturization of MEMS involves multiple problems with regard to physical and mechani cal properties of these devices. Making a restriction only to the strictly mechanical parameters such as elasticity, hardness, as well as friction and adhesion coefﬁcients, those parameters are strongly size dependent and have a great inﬂuence on the quality and efﬁciency of the designed microstructures. In that way, further design engineering of MEMS devices has to be closely related to modern science based techniques adequately suited for new challenges coming from the IC industry.

Measurements of mechanical parameters involving reduced Young’s modulus and hardness of many types of materials can be carried out by conventional tech niques such as bending and scratching tests of investi gated specimens. However, large scale integration and miniaturization of MEMS devices, as well as a demand of exploration of new aspects of nature at increasingly growing scale, enforce employment of much more sophisticated experimental methods. Therefore, one of the powerful scientiﬁc tool to study nanostructured materials involving both imaging details of an investigation region, as well as determina tion of mechanical properties of a specimen is atomic force microscopy (AFM). The essential component of that method is a silicon or silicon nitride tip ﬁxed at the end of a cantilever, continuously kept in contact with sample surfaces during all imaging process. The deﬂec tion of the tip is recorded in a very precise manner by means of analysis of force-distance curves [1]. Another widely accepted technique useful for practical application of the standard tests for deter mining plastic and elastic properties of materials at micro- and nanometer scale is an indentation method [2, 3]. Many types of naniondentation device have recently been developed in response to an increas ing number of requirements for mechanical testing of crystalline thin ﬁlms and multilayer structures, which

623

Appendix 2

are utilized in optoelectronics and microfabrication of nanostructures. The nanoindentation technique, also named the depth-sensing indentation, is a method, where an indenter with a diamond tip goes deeply into the speci men after applying external force. The plastic-elastic behaviour of the test material is evaluated through the type and a shape of the P — h curve. A schematic loading-unloading diagram describing the response h of a specimen recorded as a function of load P is presented in Fig. 1, where hmax, Pmax indicate the maximum penetration depth at the maximum load, and the other parameters are described as follows: hr-residual indentation depth, hc at contact, S dP/dH -stiffness, deﬁned as the slope of the unloading curve at maximum load. Using Oliver-Pharr procedure [2], it is possi ble to determine from the P — h curve the effective Young’s modulus Eeff and a hardness H. The hardness H is a measure of the resistance of a material to plastic deformation, and is simply deﬁned as an applied force (“mean pressure” P) acting on the area Ac: H

Pmax , Ac

(1)

where Ac denotes a projected area of a contact between the probing tip and the specimen at the maximum load Pmax, and is estimated from the geometry of the tip during the procedure of the area function calibra tion (Ac f(dc)). This is the basis of the Oliver-Pharr method, where the momentary contact area between the tip and the specimen is simply related to the actual depth of the indenter.

=

On the other hand, with respect to the range of com pletely elastic behavior, the effective Young’s modulus is described as a measure of uniaxial strain under a given uniaxial stress. It was proved by Bulychev et al. [4] that the relation ship between the stiffness S, effective elastic modulus Eeff and the contact area Ac, deﬁned as: S

dP dH

h hmax

2 π

Eeff

Ac

(2)

is adequate for cylindrical and spherical indenter tips, as well as for conical ones, for which it was originally derived. Thus, for Oliver-Pharr analysis [2], the effec tive Young’s modulus is estimated according to the relation: Eeff

π S , 2β Ac

(3)

where the coefﬁcient β is the geometry correction factor of an indenter (β 1.034 for the standard Berkovich tip), and Eeff is deﬁned as: 1 ν12 1 ν 22 1

, Eeff E1 E2

(4)

where Et and νi are elastic moduli and the Poisson’s ratios of the sample and the indenter tip, respectively. A very important criterion determining the quality of indentation experiments is the type and shape of the probing tip (ε parameter on Fig. 1). A Berkovich threesided pyramidal tip, as well as other conical indent ers, are very useful for making deep indentations with comparatively small residual impressions, while the rel atively large spherical tips are generally used for crys talline materials revealing a big elastic-plastic anisotropy and for brittle materials. There are many scientiﬁc dissertations concerning interactions between a sharp tip and a small part of a specimen being found underneath a tip-sample contact [5]. All of them consider the size of residual impres sion, rather than a direct measurement of the contact area, since the dimensions of nanoindentations are inad equately suited for classical and optical techniques.

ε

2 Indentation in Silicon ε

Figure 1 ● Schematic diagram of the indentation method with a typical load-displacement curve and parameters used in the Oliver and Pharr analysis.

624

As was mentioned in previous chapters, silicon is a hard, brittle material containing many types of structural defects related to particular methods of crystal growing, and different foreign atoms being introduced into the silicon structure during the processes of silicon wafer

Appendix 2

fabrication. Therefore, there is a quite essential detail in experimental route, especially with respect to thin ﬁlms and extremely thin monolayers based on silicon and silica, since any defect on the surface may cause perma nent cracking of the investigation materials. Additionaly, very tenuous MEMS devices, which now adays are widely produced with the close cooperation of the IC industry, have challenged scientists to employ much more sophisticated methods and techniques to determine physical properties of these materials. In large scale production of MEMS devices, a typi cal 550 μm thick, p-type (100) oriented silicon wafer is commonly used as a prefabricated element for further steps of nanodevice manufacturing. Hence, the inden tation of silicon and related micro-structural systems based on silicon have been extensively carried out dur ing the last few decades. Many scientiﬁc papers deliver interesting information about the physical properties of that type of material, as well as reporting data involv ing phase transitions and creation of new phases during nanoindentation tests. Therefore in that meaning, nanoindentation method is a very fast and useful technique for the investigation of prefabricated silicon devices, nevertheless in compli ance with silicon structure modiﬁcations, one could be very careful, especially with the interpretation of the results arising from that method.

2.1 Structure Transition In general, material deformation under an indentation process might involve such competing mechanisms as brittle macro- and microfracture, plasticity disloca tion, defect formation and structural transitions. It was reported [6], that during nanoindentation, silicon shows small or almost no dislocation activity but highly dis turbed structures. In earlier work Pharr et al. [7] have shown, that dur ing an indenter loading into a silicon specimen, per manent pressure treated as a locally acting hydrostatic stress just beneath the tip can involve a tetragonal phase formation. A very similar phenomenon was also regis tered upon removing the applied force, where a phase transition to bcc structure was delivered [8]. Those observations prompted further investigations, hence numerous indentation experiments have been done, showing a great variety of different phase transi tions occuring in silicon structures with respect to vari ous pressure conditions. In 1997 Gogotsi et al. [9] methodically considered deformations in silicon wafers induced by indenta tion measurements. They adapted a hardness indenta tion technique and micro-Raman spectroscopy to show many interesting phenomena involving phase transitions and other microcracking processes.

The conclusion was that silicon undergoes a transition from the cubic-diamond structure (so called Si-I) into β-tin phase (Si-II) at the loading stage of indentation, between 9 and 16 GPa of hydrostatic pressure with a signiﬁcant decrease of the unit cell volume by about 22%. Further increase of pressure can induce consecu tive phase transitions into Si-V, Si-VI and Si-X struc tures, respectively. On the other hand, decreasing the hydrostatic pres sure transforming the silicon material into the rhombo hedral phase (Si-XII) starting at around 9 GPa of contact pressure and the Si-II to Si-XII transition results in about 9% volume expansion. This phase was found to be unstable at ambient pressure, although its existence was proved from postindentation analysis. However, Si-XII can transform to the bcc phase (SiIII), upon further unloading. It was shown that transi tion between the Si-XII and Si-III phases is martensitic, as well as reversible and occurs around 2 GPa of pres sure. The ﬁnal Si-III structure was found to be about 9% denser than the initial Si-I phase and 2% less dense than Si-XII. It is also possible to obtain an amorphous structure of silicon (a-Si), if the unloading rate is slow enough. The presented description of silicon deformations is only a simpliﬁcation of the structural changes aris ing from that system. Up to now, at least 12 different crystallographic structures of silicon have been distin guished. All recognized and well established silicon structures are collected in Table 1 with respect to their occurrence and the pressure conditions. A schematic diagram of hydrostatic stress as a function of volumetric strain is presented in Fig. 2. More detailed information including particular lattice parameters of development structures, and also a complete collection of publication references are included in Hull [10].

2.2 Size, Substrate and Other Effects in Silicon The miniaturization process of MEMS devices is bring ing to pass multiple problems regarding their mechani cal properties. As was introduced by Li et al. [11] the size effect cannot be neglected, especially when the technology goes into the scale of nanometers. The differences between the values of mechani cal properties of a single crystal of silicon obtained in macro- and nanoscale are deﬁnitely large. Many measurements carried out for bulk specimens could not be applied to microdevices due to the scale depend ence of the investigated material. Also, a plenty of physical results coming from different experiments are not so consistent with each other, which could be a very problematic question for designers of MEMS devices. 625

Appendix 2

Table 1 Structural data for crystalline phases of silicon [10].

Designation Space group Crystallographic Pressure structure range [GPa] Si-I

Fd3m

diamond cubic

0 – 12.5

Si-II

I41/amd

body centred tetragonal

8.8 – 16

Si-III

la 3

body centred cubic 2.1 – 0

Si-IV

P63/mmc

diamond hexagonal –

Si-V

P6/mmm

primitive hexagonal 14 – 35

Si-VI

–

unidentiﬁed

34 – 40

Si-VII

P63/mmc

hexagonal close packed

40 – 78.3

Si-VIII

P41212

tetragonal

14.8 – 0

Si-IX

P422

tetragonal

12 – 0

Si-X

Fm3m

face centred cubic

78.3 – 230

Si-XI

Imma

body centred orthorhombic

13/15

Si-XII

R3

rhombohedral

12 – 2

Other independent parameters could also inﬂuence values of mechanical properties of silicon structures. An excellent example of that relation is the variation of hardness as a function of temperature. As one can see in Fig. 3, the hardness H is not a constant value, but could be varied with respect to temperature conditions. For extremely small prefabricated elements one has to consider an effect coming from the substrate, of which mechanical parameters and time-dependent behaviour under speciﬁc conditions might play a dominant role. Nowadays, thin silicon microstructures are fabricated for e.g. on glass substrates by hot-wire chemical vapor depo sition, however the similar process of silicon microstruc tures spanning could also be maintained on Si substrate. Nevertheless, even in the case of full compatibility of com ponent materials, the above effects have to be taken into consideration during the MEMS project implementation.

Figure 2 ● Demonstrative diagram of hydrostatic stress P in function of volumetric strain εv for mono-crystalline silicon. Only phases appearing during loading stage are presented.

Figure 3 ● Temperature dependence of hardness H for mono crystalline silicon measured by means of Vickers indentation method [12, 13].

occuring in the specimen during indentation tests. Nanoindentation produces a very high contact pressure between the diamond tip and the specimen, and brings about deformations of the material due to dislocation gliding, twinning or phase transitions. The still growing importance of computers in science gives great opportunities for employing mathematical formalism through variety of computational techniques, which are very useful tools for modeling, making simu lations and predictions of many physical properties and phenomena occuring in different materials. 2.3 Analytical and Mathematical With molecular dynamic analysis, the phase tran sition from Si-I to Si-II structures was simulated by Modeling Aspects Cheong and Zhang [14]. The simulation results revealed that, at the maximum load, some atoms just beneath Alongside experimental efforts, many theoreti

cal approaches have been done in order to describe the indenter tip appear to have a different coordination structural changes, as well as the dynamic processes number than the initial structure. Investigations of the 626

Appendix 2

bond length between atoms showed that this coordi nation complied with β-tin structure, and after a very fast unloading, an amorphous structure was reproduced. Thus, the experimental results have been conﬁrmed by theoretical predictions. Interesting work was done by Vodenitcharova et al. [15], where a constitutive model for multi-phase tran sitions in mono-crystalline silicon was developed. The

background of that model was based on the combina tion of physical mechanisms observed experimentally, the ﬁnite element method and the theory of plasticity. The developed model was successfully applied to pre dict correct results involving the elastic-plastic response of silicon subjected to hydrostatic pressure and nanoin dentation tests, also including the phenomena of pop-in and pop-out events.

References 1. B. Cappella, G. Dieter, Surf. Sci Rep. 34 (1999) 1. 2. W.C. Oliver, G.M. Pharr, J. Mater. Res. 7 (1992) 1564. 3. M.F. Doerner, D.S. Gardner, W.D. Nix, J. Mater. Res. 1 (1986) 601. 4. S.I. Bulychev, V.P. Alekhin, M.Kh. Shorshorov, A.P. Ternovskii, G.D. Shnyrev, Industrial Lab. 41 (1975) 1409. 5. A.C. Fischer-Cripps, Nanoindentation, Springer, 2004. 6. T.F. Page, W.C. Oliver, C.J. McHargue, J. Mater. Res. 7 (1992) 450.

7. G.M. Pharr, W.C. Oliver, D.S.

Harding, J. Mater. Res. 6 (1991)

1129.

8. J.Z. Hu, L.D. Merkle, C.S. Menoni, I. L. Spain, Phys. Rev. B, 34 (1986) 4679. 9. A. Kailer, Y.G. Gogotsi, K.G. Nickel, J. Appl. Phys. 81 (1997) 3057. 10. A. George, “High pressure phases of c-Si”, In: R. Hull, ed. Properties of Crystalline Silicon, 20 ed. mspec, The Institution of Electrical Engineers, London, 1999 p.104–107.

11. X. Li, B. Bhushan, K. Takashima, C.W. Baek, Y.K. Kim, Ultramicroscopy 97 (2003) 481. 12. V.I. Treﬁlov, Y.V. Milman, Sov. Phys.-Dokl. 8 (1964) 1240. 13. I. Yonenaga, T. Hoshi, A. Usui, J. Phys.: Condens. Matter 12 (2000) 10319. 14. W.C.D. Cheong, L.C. Zhang, Nanotechnology 11 (2000) 173. 15. T. Vodenitcharova, L.C. Zhang, Int. J. Solids Struct. 41 (2004) 5411.

627

Index

0-9

3-dimensional integration, 575

4-point probe, 82, 98

μPCD (photoconductivity decay)

method, 81

A A-SiC:H, 420

AAS (atomic absorption spectroscopy),

81

Absorbance, 342

Absorbed species, 587

Absorbing boundary conditions, 255

Accelerometer, 476–7

Acceptance angle, 243

Acceptor, 37

Accuracy, 283

ACES, 172

Acidic etch, 77

Activation energy, 167, 398

Active electronic functions, 419

Active metal bonding, 533

Adhesion promoter, 536

Adhesion-promoting layer, 534

Adhesive bonding, 347, 549–50

Adhesive wafer bonding, 549

Adsorbed species, 588

Advanced Porous Silicon Membrane

(APSM) technology, 426

Advanced Silicon Etch, 481

AFM, 78

Airbag igniters, 424

Al–Au, 536

Alcohol additives, in wet etching, 387

Alcohols, addition to wet etching, 395

ALD, see Atomic layer deposition

Aligners, 338

Alignment, 337, 376

Alignment targets, 337

Alkali ions, 514

Alkaline etch, 77

Alkaline solutions, 375

Amorphous carbon, 450

Amorphous metallic Alloys, 479–80

Amorphous molecular glasses, 449

AnisE, 172, 174

Anisotropic etching, 375

Anisotropic silicon etching, 415

Anisotropic wet chemical etching, 375

Anisotropic wet etching, 49, 375, 376

Anisotropy of fracture toughness, 204

Anisotropy of fracture path, 204

Anodic bonding, 502, 513, 544, 545–7

Antimony, 27

Anti-reﬂection coatings, 251

Anti-sticking SOI, 485

Apparent activation energy, 397

Area-selective deposition, 440

Argon, 22

Argon backﬁll, 541

Argon working gas, 539

Arrhenius behavior, 397

Arrhenius diagram, 167

Arsenic, 27

AsH3, 92

Ashing, 342

ASIC, 543

integration, 427

Aspect ratio, 340

Atom coordination, 380

Atomic force microscopy (AFM), 623

Atomic layer deposition (ALD), 433

reactants in, 435

reaction cycle, 434

Atomic layer epitaxy (ALE), 433–4

Atomistic methods, 160

Atomistic removal rates, 167

Atomistic simulation method, 275

Atomistic simulators, 160, 162

AuGe, 536

Augmented Reynolds equation, 271

AuSi, 536

AuSn, 536

Autodoping, 92

Axial resistivity variations, 44

B B2H6, 92

Backward TC, 168

Band-bending, 412

Barometric air pressure, 426

Barrel reactor, 103

Barrier layers, 581

Base resin, 335

Basic cellular automaton (BCA), 163–4,

172, 381

Basic parameters of silicon, 4

Batch systems (EPI), 103–4

BCA, see Basic cellular automaton

BCl3, 92

Beam propagation method (BPM), 254

Bending fracture strength, 453

Berkovich tip, 624

BESOI (Bonding and etch-back SOI),

108, 128

Bevels, in wet etching, 390

Bias voltage, 226, 227, 228

Binary tree, 169

Binding energies, 199

Birefringence, 249

Bit-shift, 169

Blind vias, 578

Blister test method, 319–20

BMDs (bulk microdefects), 328, 451

applications of, 460

Body, 25

Boltzmann equation, 267

Bond alignment methods, 560

Bond strength, 120, 317

Bonded SOI wafers, 112

Bonding, 118

Bonding current, 515

Bonding temperature, 515

Bonding voltage, 515

Boron, 27

contamination, 506

etch stop, 377

Borosilicate glass, 513

Bortz–Kalos–Lebowitz (BKL), 169

Bosch DRIE process, 350

Bosch process, 351, 353–5, 356, 359,

360, 363, 368, 369

Bow, 290

Brittle, 201, 208, 210

fracture, 201

Bubble inclusions, 50

Buckling method, 308–9

Built-in potential, 230

Built-in voltage, 230

Bulge test, 307

Bulk metallic glasses, 451

Bulk micromachining, 71, 375

Bulk modulus, 181, 183

Burgers vector, 197

629

INDEX

C C-method, 256

CA, see Cellular Automata

Capacitance-voltage (CV), 98

measurement, 293

Capacitive coupling, 222, 225, 231

Capacitive nonlinearity, 227, 230, 232

Carbon, 38

Carbon concentration, 41, 81

Carbon-ﬁber-reinforced graphite, 21

Casting, 336

Cavities, 428, 539

CCA, see Continuous cellular automata

Cellular Automata (CA), 162–8, 171

Characteristic dimension, 265, 271

Charge biasing, 227

Charge effects, 546

Charging effects, 518

Chemical etching, 77, 375

Chevron test, 320

Chlorosilanes, 90

Cleaning techniques, 79

Cleavage, 207

Cluster methods, 190

CMOS compatibility, 543–5, 570

CMOS wafers, 543

CMP (chemical mechanical polish), 78

Cohesive surface energy, 318

Cold wall reactors, 442

Columnar structure (wet etching

morphology), 387

Comb drive, 482

Commercial crystal yield, 54

Compatibility, 466

Compensation method, 391

Compensation pattern, 391

Compressibility, 271

Computational cost, 172

Computational methods, 153–6

Concentration of impurities, 42

Conductive glass frit, 530–1

Conductivity type, 42

Conformality, 433, 434

Constant and variable time stepping, 167

Contact implantation, 412

Contact proﬁlometer, 296

Contact/proximity exposure, 333

Contamination, 604

Continuous cellular automata (CCA),

162, 164, 381, 171, 172

Convex corner, 390–1

Convex corner compensation method,

391

Convex corner compensation pattern,

391

Coordinate transformation method, 256

COP, see Crystal originated particles

Copper damascene, 576

Copper electroplating, 581

Core defects, 193

630

Core structures, 191

Core vacancies, 194–5

Corrosion resistance, 454

Couette ﬂow, 267

Coupling factor, 225

Crack, 205, 206, 208, 211, 214

Crack growth, 213

Crack length, 320

Crack propagation, 204, 207

Critical angle, 242

Critical energy release rate, 317

Critical size of nucleus, 61

Critical stress intensity factor, 317

Cropping, 73

Crown, 25

Crucible, 19–20

Crucible rotation, 31–2

Cryo-process, 356

Cryogenic process, 355

Crystal growth, 37

Crystal originated particles (COP), 9, 82

Crystal properties, 53

Crystal quality, 53

Crystal rotation, 32–3

Crystal yield, 49–50

Crystallographic planes, 414

Crystallography, 4

CTS KMC method, 168

Cumulative sum, 168

Curie temperature, 466

Current focusing, 416

Curvature measurement, 306

Curved steps, 170

Cusp ﬁeld, 34–5

Customer applications, 483

Cutoff frequency, 235

CVD oxides, 143–4

CVD reactor, 428

Cylindrical grinding, 73

Cylindrical perforation cell, 269

CZ furnace, 19

CZ silicon crystals, 37

Czochralski (CZ), 3, 19

D Damping atmosphere, 540

Damping coefﬁcient, 260

Damping force, 267

Dangling bonds, 413

Dashetch, 328

Dash neck, 24

DBT criterion, 209

DCA, see Discrete cellular automata DCB, see Double cantilever beam Deep cavity, 539

Deep marking, 75–6

Deep reactive ion etching (DRIE), 343,

349, 350, 351, 353, 357, 359, 360,

361, 365, 366, 367–8, 369, 370, 377

Defect–dislocation interaction, 198

Defects, 48–51

and dislocations, 199

in silicon lattice, 6–10

Dehydration bake, 335

Density functional theory, 190

Denuded zone, 67

Design rule, 482

Developers, 340

Development, 340

Device lifetime, 616

DFT calculations, 191, 196

Diameter control, 26–7

Dicing, 601

Dielectric layers, 420

Dielectric mirrors, 251

Differential scanning calorimetry, 452

Diffraction, 246

Diffusion, 378–9

Diffusion bonding, 535

Diffusion-controlled etching, 376

Direct alignment, 558–9

Direct bonding, 505

Direct deposition, 324

Direct milling, 469

Discrete cellular automata (DCA), 162,

171

Dislocation, 39, 49, 187, 189, 191, 194,

195, 197, 198, 200

Dislocation core, 199, 201

Dislocation–dislocation interactions, 197

Dislocation loops, 52

Dislocation mobility, 200

Dislocation motion, 197, 198

Dissolution of nuclei, 63

Distribution coefﬁcients, 40

DLP, 478

DLTS, 80

DMD, 478, 480

Donor, 37

Donor killing, 48, 78

Dopants, 37

Doping, 27

and defects, 184

proﬁles, 417

Double cantilever beam (DCB), 318

measurement, 120

Double-layer passivation, 421

Double-layer SOI, 485

Double-side alignment, 337

Doublecell, 411

DRIE, see Deep reactive ion etching

Dry etching, 377

Dry-ﬁlm resists, 336

Dry sacriﬁcial release, 476

DSMC method, 275

DSMC simulations, 266

DualBeamTM, 329

Ductile, 201

Ductile fracture, 201, 208

Ductile mechanism, 210

INDEX Ductility parameter, 209, 210

Dynamic crack propagation, 207–8

E EDA, 375

Edge bead, 36, 344

Edge crown, 101

Edge dislocation, 188, 193

Edge grinding, 76–7

EDP, Ethylene diamine pyrocatechol,

375

Effective index method (EIM), 252

Effective mass, 222

Effective stiffness, 305

Effective viscosity coefﬁcient, 261

Effective Young’s modulus, 318

Elastic constants, 180, 181, 184

Electrical equivalent circuit, 227

Electrical measurements, 283

Electrical properties, 11–16

Electrical spring constant, 227

Electrical vias, 501

Electrochemical cell, 412

Electrochemical etch stop, 377

Electrochemical etching, 573

Electrochemical passivation, 377

Electrochemistry, in wet etching, 382–4

Electrodeposited resists, 336

Electroless deposition, 579

Electrolytes, 411

Electromagnetic optics, 247

Electromechanical coupling factor, 224,

228

Electron beam lithography, 324

Electron probe micro analysis (EPMA),

589

Electroplating, 343, 535

Electrostatic bonding, 513

Electrostatic discharge (ESD), 604

Electrostatic pressure, 514

Ellipsometry, 295

ELTRAN, 108, 132

Encapsulation, 501, 569

Epi layer resistivity, 98–100

Epi-poly process, 94

Epi-polysilicon, 474

Epi-Seal process, 503

Epitaxial deposition, 572

Epitaxial ﬁlms, 424

Epitaxial growth, 427

Epitaxial layer overgrowth, 97

Epitaxial thickness measurements, 98

Epitaxy, 89

Epitaxy process, 89

Equilibrium isotherm, 588

Equivalent circuit, 224

Etch front propagation, 423

Etch pit (wet etching morphology),

385

Etch rate, 379

concentration dependence of,

399–402

temperature dependence of, 397–9

Etch-rate anisotropy, 375

Etch stop, 376

Etch3D, 174

Etchant inhomogeneities, 379, 386

Etch stop, 392–3

Ethylene diamine pyrocatechol, 375

Eutectic AuSi, 534

Eutectic bonding, 533, 535

Eutectic point, 536

Evaporated plating base, 539

Ex situ alignment, 558

Expansion coefﬁcient, 180

Explosive evaporation, 424

Exposure dose, 337

Exposure speed, 335

Exposure wavelength, 334

Extended defects, 187

Extinction coefﬁcient, 239

Extrinsic stacking faults, 7

F

Fracture anisotropy, 202

Fracture path, 202

Fracture tests, 516

Fracture toughness, 202, 317

Frank criterion, 189

Free convection, 30–1

Free-standing silicon structures, 419

Freestanding sensing elements, 474

Frequency dependency, 271

Frequency response, 229

Fresnel equations, 249

Freund’s criteria, 204

Front propagation, 159

Frontside processing, 427

FTIR technique, see Fourier transform infrared technique Functional layer, 474–5

G Gas compressibility, 271

Gas ﬂow, 22–3

Gas permeation, 534

Gas pressure, 22

Gas sensors, 426

Gas shear, 33–4

Gas sources, 587

Gaussian beam, 245

Geometrical method, 160

Geometrical optics, 242

Geometrical simulators, 160

Getter, 614

Getter activation, 540

Getter ﬁlms, 590

Getter saturation, 614–16

Gettering, 585

GFA, 328

Glass ﬂowing, 526

Glass frit bonding, 502, 521

Glass paste, 521

Glass transition temperature, 334,

340

Glassy/amorphous metal, 450

Glide set, 188

Graphite, 20

Graphite felt, 20

Grashof number, 30

Grating equation, 257

Gratings, 256

Grifﬁth criterion, 202, 204, 208

Grinding, 122

Ground state, 179

Growth modes, 438

Growth per cycle, 437

Growth rate, 51

Growth-related stress, 439

Gyroscopes, 477, 482

Fabry perot interferometer, 301

Face-speciﬁc etch rates, 172

Face-speciﬁc rates, 167

Facet, 45, 46

in wet etching, 390

Faceting, 375, 376

Failure mechanisms, 211

Fast etching planes, 390

Fatigue, 210, 211, 212, 213, 214

cracking, 449

mechanisms, 213, 214

FEM, see Finite element method

FEM simulations, 266

Fermi energy, 413

FIB, see Focused ion beam

Film-mode matching (FMM) method,

253

Finite difference time domain (FDTD)

method, 153, 255

Finite element method (FEM), 154,

223

Finite-size effects, 267

First-level packaging, 502

Flatness, 505

Floque–Bloch theorem, 256

Flow control, 533

Flow patterns, 268

Focused ion beam (FIB), 323, 458

Footings, 390

Four-point probe, 293

Fourier modal method, 256

Fourier transform infrared (FTIR)

spectroscopy, 98, 123, 327

Fourier transform infrared reﬂectometer, H 295

Half-cells, 411

Fracture, 201, 205, 206

Hard bake, 340

631

INDEX Hard contact, 338

Hardness, 305, 624

Hartree–Fock–Roothaan method, 154

Haze, 82

Heat transfer, 29–30

Heater, 21

Helium leak test, 609

Helmholtz equation, 244

Hermeticity, 484, 516, 570

requirements, 607–8

tests, 607

Hexagonal pits (wet etching

morphology), 170, 385

HF dip, 422

HF fume etching, 481

High-aspect-ratio, 434

High-pressure silicon structures, 185,

187

High-temperature annealing, 422

Hillocks, 170

HIPOX, 140

Horizontal vias, 503

Hot plate, 344

Hot recharging, 35–6

Hot wall reactors, 442

Hot-zone materials, 20–1

Hot-zone structure, 21–2

Hybrid integration, 477

Hydration shells, 401

Hydrogen bake, 90

Hydrogen bubble (wet etching

morphology), 387

Hydrogen prebake, 428

Hydrophilic, 397

Hydrophilic bonding, 505

Hydrophilic wafer bonding, 119

Hydrophobic, 397

Hydrophobic bonding, 507

HZ lifetime, 27–8

I

In situ alignment, 557, 558

ICP-MS, 81, 101

ID cutting, 73

Ignition process, 425

Illumination, 412

Image reversal, 340

Imprint lithography, 448

Improved thermal and gas ﬂow designs,

28–9

Impurities, 39

Impurity levels, 438

Indentation fracture, 306

Indirect alignment, 558, 559–60

Industrial products, 429

Infrared absorption, 40

Ingot cutting, 72–3

Inoue rules, 451

In-situ doped polysilicon, 578

Integrated circuit technology, 317

632

Integrated getter thin ﬁlms, 538

Integration, 570

IntelliEtch, 174, 175

Interference, 246

Interferometry, 300

Intermediate metal layer, 533

Intermetallic phase formation, 537

Intermodulation distortion, 231

Internal pressure measurement,

609–10

Interstitial atoms, 5

Interstitial oxygen, 327

concentration, 39

Interstitial solubility, 5

Interstitials, 194–5

Inverse Knudsen number, 261

Ion implantation, 417

IPA, see Isopropyl alcohol

IR alignment, 558–9

IR transmission test, 610

Irreversible desorption, 587, 588

Island growth, 438

Isopropyl alcohol (IPA), 385

Isotropic etchants, 397

Isotropic etching, 481

Isotropic silicon structuring, 481

Isotropic wet etching, 376

J JEDEC, 484

K K-Level Search (KLS), 169

Kinetic Monte Carlo (KMC), 162,

168–72, 171, 172

Kinetics-controlled etching, 376

Kink dissociation, 196

Kinks, 195–7

KMC, see Kinetic Monte Carlo

Knudsen number, 261

KOH, see Potassium hydroxide

KOH cascade, 422

L Lamella width, 416

Laminate resists, 336

Lapping/grinding, 77

Laser ablation, 579

Laser Doppler vibrometer, 303

Lattice parameter, 179, 180

Lattice trapping, 207

“Lattice-trapping” effect, 205

Lattice vibrations, 240

Layer-by-layer growth, 438

Lead dissolvings, 529

Lead free, 534

Leakage, 587

Level Set equation, 159

Level Set method, 159

Lifetime, 40, 47, 53, 534

Lift-off, 341, 440, 539

Lift-off resists, 334

LIGA, 346

Linear defects, 6

Linear Search, 168

Linearized (modiﬁed) Reynolds

equation, 271

Liquid phase, 538, 541

Lithography, 447–8

Lo–Hi treatment, 66

Local oxidation, 392–3

Local oxidation of silicon (LOCOS), 393

LOCOS, see Local oxidation of silicon

Low parasitic, 481

Low-temperature bonding, 508, 545

Low-temperature processes, 544

Lower contour, 160

Lower polygon, 161

LPCVD, 94

LST, 329

Lumped element model, 221

M M-test, 312

Macro-loading effect, 97

Macropores, 416

Macroporous silicon (MPS), 410

Magnetic anisotropy, 467

Magnetic ﬁelds, 34–5

Magnetic properties, 454

Maksym’s binning method, 169

Manifold absolute pressure, 426

Marangoni convection, 33–4

Marangoni drying method, 80

Marker method, 159

Mask design, 334

Maskless etching, 392

Mass percentage, 403

Mass–volume percentage, 403

Matrix optics, 243

Maxwell’s equations, 151, 243–4

Mean free path, 261

Measurement techniques, 283

Mechanical alignment, 557

Mechanical motion, 299

Mechanical properties, 283, 305

of silicon, 10–11

Mechanical strength, 516

Mechanical thinning, 115

Melt convection, 30–4

Melting, 23–4

Melting point, 425, 536

Membrane resonance, 608–9

MEMS, 305

MEMS devices, 473

MEMS-ﬁrst, 570

MEMS foundry, 485

MEMS-last, 570

MEMS structures, 306

Metal alloy bonding, 503

INDEX Metal concentration measurements, 81

Metal frames, 534

Metal melt, 533

Metal reactants, 435

Metal seal bonding, 533

Metal seal frame, 536

Metallic alloy bonding, 533

Metallic diffusion barrier, 536

Metallic glass, 447

Metallic glass thin ﬁlms, 463–8

Metallic MEMS, 477–80

Metallic vias, 578

Metropolis KMC, 168

Michelson interferometer, 300

MICROCAD, 174

Microcracks, 208

Microelectromechanical systems

(MEMS), 305

Microﬂuidic devices, 410

Microﬂuidics, 346

Microformability, 456–7

Microgeared motors, 461–2

Micro-loading effect, 97

Micromachining, 157

Micromasking, 378

Micromasking agents, 378

Micromechanical switch, 234

Microroughness, 297, 506

Microsystem, 317

Miller index, 5–6

Milling, 323

Minority carrier lifetime, 330

Mirror, 255

Mobile ion, 546

Mobility, 42, 197

Moduli, 180

Modulus, 305

MOEMS, 239

Molar concentration, 402

Molarity, 402

Mold master, 343

Monochromatic waves, 244

Monolithic integration, 477

Monte Carlo (MC), 168

Morphology, 421

Motional current, 228

Movable structures, 481

Multiphonon absorption, 240

Multiphoton absorption, 240

Multiple-step structure, 552

Multiscale approach, 191

Multiscale modeling, 151

Murnaghan equation, 183

N n crystals, 44

N-fold method, 169

N–S solver, 275

Naniondentation, 623

Nano laminates, 436

Nanocomposite materials, 454

Nano-electromechanical systems, 443

Nano-ﬂuidic devices, 324

Nanoformability, 457

Nanoindentation, 306

Nanolamination, 440

Nanoporous silicon (NPS), 409

Narrow-gap equations, 274

Narrow gaps, 259

Native oxide removal, 90

Navier–Stokes (N–S) equations, 259

Navier’s equation, 151

Necking, 24

Negative photoresist, 334

Neon Ultra-Fine Leak Test, 610–12

Nested masks, 341

Neutron deﬂection, 306

Next-nearest neighbors, 169

Nitrogen, 38

Nominal resistance, 263

Non-destructive bond strength testing,

551

Non Evaporable Getter (NEG), 590

Nonlinear optical effects, 241, 249

Normal freezing equation, 40, 43

Nucleation, 61, 64

Nucleation rate, 62, 63

Numerical aperture, 243

O OH-coverage, 402

Oi levels, 390

Oi precipitates, see Oxygen-induced

stacking faults (OISFs)

OISF ring, 51, 52, 53

Oliver-Pharr analysis, 624

Operating pressure, 92–4

OPP, see Optical precipitate proﬁling

Optical alignment, 557, 558

Optical components, 462–3

Optical deformation, 609

Optical metrology, 299

Optical path length, 242

Optical precipitate proﬁling (OPP),

329

Optical proﬁlometer, 296

Optical switch, 247

Optical waveguides, 243

Organic additives, 581

Organic surface contaminants, 538

Organometallic precursor, 324

Orientation, 73

Orientation dependence, 379, 382

of etch rate, 394

Orientation-dependent etch rate,

394

Outﬂow, 538

Outgass, 539

Outgassing, 536, 585, 587

Outgassing phase, 541

Overexposure, 340

Oxidation-induced defects, in Silicon,

142

Oxidation-induced stacking faults, 50–1,

127

Oxygen, 38, 81

Oxygen concentration, 41, 54

Oxygen content, 390, see also Oi

levels

Oxygen donors, 47

Oxygen gradient, 46

Oxygen precipitates, 51, 327

Oxygen solubility, 59

Oxygen-induced stacking faults, 390

P Package, 570

Package sealing, 537

Pancake reactor, 103

Parametric ampliﬁcation, 227, 230

Parasitic capacitance, 229–30

Paraxial approximation, 243, 245

Partial dislocations, 187, 188

Particles, 82, 602

Parylene, 580

Pattern shift, 93

Pd–Si, 536

Peak temperature, 541

PEB, see Post-exposure bake

Peeling masks, 341

Peierls barrier, 197

Peierls–Nabarro mechanism, 198

Peierls stress, 189, 197

Peierls valleys, 195

Percent weight per volume, 403

Perforated dampers, 268

Perforation cell, 269

Permeable material, 573

PH3, 92

Phase Field method, 159

Phase-noise, 233

Phase-shifting interferometry (PSI),

300–1

Phosphorus, 27

Photoacid generator, 342

Photo-acoustic microscopy, 306

Photoactive compound, 335

Photoinitiator molecule, 345

Photolithographic processing, 424

Photoluminescence, 409

Photomasks, 333

Photon, 249

Photonic crystals, 410

Photoresist thickness, 335

Photovoltaic processes, 417

Piezoresistive, 426

Pinhole-freeness, 434

Piranha, 146

Pit nucleation, 378

Pixel detector, 255

633

INDEX Planar defects, 6

Plane wave spectrum method, 246, 247

Plasma activation, 508–9, 565

Plasma-assisted chemical etching

(PACE), 123

Plasma-enhanced ALD (PEALD), 436

Plasma etching, 341, 349, 350, 356, 357

Plastic deformation, 10

Pockels effect, 241

Point defects, 6

Point-loaded samples, 320

Poiseuille ﬂow, 260

Poisson equation, 152

Poisson’s ratio, 305

Polarization, 248

Polishing, 78

Polycrystalline silicon-based

micromachining, 473–7

Polycrystalline silicon germanium, 474–5

Polygonal, 170

Polygonal steps (wet etching

morphology), 387

Polygons, 160

Polysilicon, 212–14

oxidation, 141, 421

Polysilicon vias, 577

Pore formation, 415

Porosity, 423

Porous silicon processing

np, 418

npn, 418

p+/p, 418

Position resolution, 303

Positive photoresist, 334

Post-bake, 340

Post-exposure bake (PEB), 340, 345

Post-treatment, 341

Potassium hydroxide (KOH), 375

Potentials, 191

Potentiostat, 411

Poynting vector, 247

Prebake, 336

Pre-bonding, 556

Precipitate growth, 63, 64

Precipitation of oxygen, 51

Precision, 283

Pre-existing nuclei, 63

Preferential etching, 328

Pressure, 570

boundary conditions, 262

distribution, 262

effect of, 182–3

Pressure sensors, 426, 460–1

Prestructured SOI, 485

Primary ﬂat orientation accuracy, 389

Process compatibility, 429

Process separation, 558

Process simulation tool, 482

Prototype, 325

Proximity, 338

634

PS (Porous Silicon) dissolution, 421

PS formation, 415

PS morphology, 423

PS removal, 422

PS sacriﬁcial layers, 429

PUA, 82

Pull-in voltage, 229, 312

Pyramidal hillocks (wet etching

morphology), 385

Q Q factor, 222, 223, 231, 586

monitoring, 610

Q-factures, 482

Qualiﬁcation, 484

Quantum conﬁnement, 416

Quantum optics, 249

Quartz crucible, 21

R Radial resistivity variation, 45

Radial variation of oxygen, 45

Radioactive tracer gas test, 609

Raman spectroscopy, 306, 310–11

Rareﬁed gas effects, 259

Ray optics, 242

Ray tracing method, 250

Rayleigh number, 31

RCA, 79

Reaction cycle, 440

Reaction kinetics, 534

Reaction-layer fatigue model, 213

Reaction-layer model, 212

Reactive sites, 434

Reconstruction defects, 194

Reconstruction energy, 192

Reconstruction modes, 193

Reconstruction of partials, 192

Rectangular squeeze-ﬁlm damper, 262

Reduce damping, 482

Reference oscillator, 233–4

Reﬂection, 242

Reﬂow, 535

Refraction, 242

Refractive index, 239, 242

Residual gas, 517

Residual gas analysis (RGA), 590

Residual stress, 305, 517

Resist polarity, 334

Resist removal, 342

Resistivity, 42–4, 82, 291

vs. dopant density, 43

speciﬁcation, 43, 44

Resistivity targets, 44

Resolution, 338

Retrograde proﬁles, 334

Reversible desorption, 588

Reynolds number, 271, 273

Reynolds solver, 266, 275

RF-MEMS, 479

Rigorous coupled wave analysis, 256

Room-temperature bond chambers, 560

Round pits, 170

S Sacriﬁcial layer, 341, 409, 476

Saturation, 540

SbH3, 92

Scalar wave equation, 244

Scalar wave model, 243–6

Scalloping, 363

Scanning acoustic microscopy (SAM), 119

Scanning infrared microscopy (SIRM),

329

Scattering tomography, 329

Schimmel, 101

Screen printing, 521, 522, 524

Screw dislocations, 188

Scribe, 601

SD, see Step dihydrides SEAES, 174

Seal Ring Design, 539

Seccoetch, 101, 328

Secondary ion mass spectroscopy

(SIMS), 328, 589

Seed layer, 427

Seed metal layer, 582

SEGS, 174–5

Selective epitaxial growth (SEG), 97

Selective epitaxy, 93

Selectivity, 376

Self-aligning, 524

Self-interstitials, 50

Self-terminating reactions, 434

Sellmeier-type dispersion formula, 240

SEMI (Semiconductor Equipment and Materials International) standard, 71, 74, 81–7 Semiempirical potentials, 190, 191, 196

Sensor module, 429

Series switch, 234

Shadow masks, 342

Shadow moiré system, 307

Shallow marking, 75–6

Shallow round pits (wet etching

morphology), 387

Shear stress, 318

Sheet resistance, 293

Shelf-life, 335

Shield electrode, 518

Shockley partials, 189

Shoulder, 25

Shufﬂe set, 188

Shunt switch, 234

Shut-off, 26

Si precursor, 90

Si3N4, 421

SiCl4, 91

Sidewall proﬁle, 344

SiGe, 95

INDEX SiH2 Cl2, 91

SiH4, 91

SiHCl3, 91

Silica crucible, 21

Silicon bridge, 425

Silicon carbide, 21

Silicon dioxide, 476

stress in, 141–2

structure and properties of, 144–5

Silicon direct bonding, 503

Silicon-electrolyte contact (Elymat), 81

Silicon monoxide, 22

Silicon nitride (Si3N4), 375

Silicon on insulator (SOI), 107, 409, 480

Silicon on sapphire (SOS), 97

Silicon oxide (SiO2), 375

Silicon structure, 179

Silicon wafer, 71, 289

SIMODE/QSimode, 175

SIMOX, 108

SIMS, see Secondary ion mass

spectroscopy

Simulation, 189, 205, 209

Single-crystal silicon, 211–12

Single crystal vias, 576–7

Single crystalline silicon, 481

Single-step structure, 552

Single wafer systems, 102–3

SIRM, see Scanning infrared

microscopy

Sirtl, 101

Site-speciﬁc, 380

Site-speciﬁc removal, 172

Size effects, 449

Slab waveguides, 251

Slip, 49–50, 101

Slip conditions, 273

Slowly varying envelope approximation

(SVEA), 245

Smart Cut, 108, 130

Snell’s law, 242

Sodium contamination, 518

Soft bake, 336, 344

Soft contact, 338

SOI, see Silicon-on-insulator

SOI wafer, 392

SOI-wafer-based surface

micromachining, 480

Solder bonding, 533, 535

Solder paste, 535

Solid diffusion bonding, 533

Solid state, 536

Solidiﬁcation techniques, 451, 541

Solids, 201

Solitons, 194

Solvent, 335

Spill tray, 22

Spin coating, 335

Spin reorientation transition, 468

Spray coating, 336

Spreading resistance proﬁling (SRP), 82,

98, 293

Spring force, 271

Spring softening effect, 227

Sputter-deposited ﬁlms, 479

Square diaphragms, 391

Squeeze-ﬁlm effect, 259

Stability, 421

Stacking faults, 7, 48, 65, 101, 188

Stages of growth process, 23–6

Standard time compensation, 168

Static fatigue, 212

Stealth dicing, 603–4

Stencil printing, 535

Stencils, 342

Step-and-repeat systems, 333

Step bunch (wet etching morphology),

388

Step coverage, 344

Step dihydrides, 380

Step ﬂow, 378

Step monohydrides, 380

Stereographic projection, 6

Stiffness, 624

Stochastic cellular automata, 171

Stochastic Cellular Automaton (SCA),

162, 168

Stokes damping, 259

Stokes equation, 273

Stoney’s formula, 307

Straight steps (wet etching morphology),

170, 387

Strains, 182, 183

Stress, 479

Striations, 45

Stripping, 342

Stroboscopic illumination, 301

Stroboscopic imaging, 300

Structural layers, 157

Structure delineation, 417

Stud pull test, 484

Subcritical crack, 212, 213

Substitutional lattice sites, 5

Substitutional solubility, 5

Supercell methods, 190

Superplasticity, 454

Surface-controlled material buildup, 440

Surface energy, 552

Surface extension, 265

Surface micromachining, 71, 157, 376,

473, 480

Surface morphologies, 384

Surface nanotopography, 113

Surface passivation, 419

Surface photovoltage (SPV), 81, 294

Surface potential, 98

Surface roughness, 114, 296, 389, 514

Surface tension, 397

Surfactants (wet etching morphology),

387

addition to wet etching, 394

surface active agent, 396

Susceptor, 21

Sutherland constant, 260

SUZANA, 174, 175

T Through silicon vias (TSV), 575

Tail, 25–6

Tailorable magnetic properties, 466

Tansition-metal impurities, 38

Taper, 74

TD, see Terrace dihydrides Temperature, effect of, 184

Tensile strain test, 318

Tensile strength, 452

Tensioactive additives (wet etching

morphology), 387

Tensioactive character, of alcohols

and surfactants in wet etching,

395

TEOS, 580

Terrace dihydrides, 380

Terrace monohydrides, 380

Tetramethylammonium hydroxide

(TMAH), 375

Thermal bond chambers, 560

Thermal conditioning, 524

Thermal conductivity, 241

Thermal desorption spectrometry

(TDS), 589

Thermal donors, 47–8, 60

Thermal expansion coefﬁcient, 515

Thermal history, 47

Thermal insulation, 425

Thermal oxidation, 138–42

Thermal stresses, 582

Thermo-compression, 503

Thermo-compression bonding, 533

Thermo-compressive bonding, 521

Thermodynamic MC (TMC) method,

168

Thermo-optical constant, 241

Thickness variation, 290

Thin ﬁlm, 259, 569

Thin ﬁlm stacks, 250

Thin-ﬁlm structures, 305, 424

Thin gas ﬁlm, 260

Three-dimensional growth, 438

Time compensation, 167–8

Time-dependent ﬁelds, 5

TLP bonding, 535

TMAH, see Tetramethylammonium hydroxide Total internal reﬂection, 243

Total thickness variation (TTV), 79, 82,

389

Trace impurities, 438

Transition metals, 39

Transparent alignment, 558

635

INDEX Wagon wheel, 402

Warp, 290

Warp/bow, 74

Waveguide, 252

Wavelength in gas, 274

Weak bonds, 413

Weight percentage, 403

Weight–volume percentage, 403

Weight–weight percentage, 403

Wet chemical cleaning, 116

Wet etching, 327, 375

Wet-etching quality, 341

Wire cutting, 74

Wright, 101, 328

Wulff net, 9

Wulff-Jaccodine method, 160

U-grooves, 391

Undercutting, 390–1, 418

Underetching, 390

Upper contour, 160

Vapor phase etching, 476

Variable optical attenuators, 247

Vector model, for anisotropic etching,

382

Vectorial wave optics, 247

Venting conditions, 263

Vernier gauges, 310

Vertical grooves, 391

Vertical vias, 503

Vibrating structure, 259

Vibration method, 311–12

Viscoacoustic wave propagation model,

274

Viscosity coefﬁcient, 260

VisualTAPAS, 174, 175

Voids, 52, 505, 525

Voigt’s notation, 181

Voltage effects, 546–7

Volume defects, 6

VPD-TXRF, 80

V

W

Y

V/G ratio, 52

V-groove pattern (wet etching

morphology), 387

V-grooves, 391

Vacancies, 50

Vacuum cavities, 428

in SOI wafer, 110

Vacuum contact, 338

Vacuum environment requirements, 585

Vacuum lifetime model, 612–16

Wafer bonding, 95, 317, 569

Wafer-bonding equipment, 555

Wafer cleaning, 115

Wafer ﬂatness, 289

Wafer geometry, 82

Wafer-level encapsulation, 502

Wafer marking, 74–6

Wafer-to-wafer alignment, 556, 557

Wafer topography, 533

Wafering, 73–4

Yield strength, 10

Young’s modulus, 305, 452, 623, 624

Transverse ﬁeld, 34 Trapezoidal hillocks (wet etching morphology), 387

Trenches, 481

Triangular pits, 170

Triangular pits (wet etching

morphology), 385

Triangular steps (wet etching

morphology), 387

Trichlorosilane, 3

TRITON X-100, 395

Twins, 50

Two-dimensional growth, 438

TXRF, 101

U

636

X

X-Ray Diffraction, 306

X-ray exposure, 346

Z Zero-level alignment, 337

Zigzag structure (wet etching

morphology), 387

Zr-based metallic glass, 464–6