Semiconductor Manufacturing Handbook (McGraw-Hill Handbooks)

Geng(SMH)_CH01.qxd

04/04/2005

19:31

Page 1.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

P

●

A

●

R

●

T

●

1

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:31

Page 1.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:31

Page 1.3

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 1

HOW SEMICONDUCTOR CHIPS ARE MADE Hwaiyu Geng Hewlett-Packard Company Palo Alto, California

Lin Zhou Intel Corporation Hillsboro, Oregon

1.1 INTRODUCTION Over the past decades, an information world that encompasses computers, the Internet, wireless communication, and global positioning systems has emerged. The center of this information world is enabled by many tiny integrated circuit (IC) chips embedded in the systems. ICs are used in many walks of life—in sectors including consumer products, home appliances, automobiles, information technology (IT), telecom, medical, military and aerospace applications. Continuous research and development coupled with nanotechnology will make ICs smaller and more powerful. In the foreseeable future, the size of a computer will shrink to the size of a fingernail and reach the practical limit of an IC that is smaller, faster, cheaper, and consumes low power. The semiconductor industry can help drive nanotechnology; thus, they are mutually beneficial.* The evolution from chip to Microelectromechanical Systems (MEMS) combines IC manufacturing and micromachining techniques to install motors, sensors, pumps, valves, or radio receivers and antennas on a chip. MEMS applications encompass IT, entertainment, biological, medical, and automotive sectors.† Similar IC technologies and manufacturing processes can be applied in manufacturing flat panel display.

1.2 WHAT IS A MICROCHIP? Microchips, or chips, are basically made of thousands to millions of transistors packed into a small piece of silicon. A transistor is an electronic switch that contains no moving parts but uses electricity to turn itself on and off. The transistors are wired together, using aluminum or copper, to perform

*

Stephen Marx, “Using Microtechnology to Get to Nanotechnology,” Machine Design, September 2004. Dave Thomas, “Key MEMS Building Blocks,” Solid State Technology, April 2004.

†

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

1.3

Geng(SMH)_CH01.qxd

04/04/2005

19:31

Page 1.4

HOW SEMICONDUCTOR CHIPS ARE MADE 1.4

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Integrated circuit complexity Transistors per Dle 4G 1965 actual data 1G 2G 512M MOS arrays MOS logic 1975 actual data 256M Pentium? 1975 projection 64M128M P e 16M ntium ? Memory Pen 4 1M 4M tium ? Microprocessor Pen III tium ? Pe 256K ntiu 1 II m? 138 488 TM 8 TM 64K ?028 4K 16K 8 8088 1K 8080 4004

1010 109 108 107 106 105 104 103 102 101 100 1960

FIGURE 1.1

1965

1970

1975

1980

1985

1990

1995

2000

2005

2010

Moore’s law.* (Image Courtesy of Intel Corporation.)

different functions. A transistor is turned on when a low-voltage electrical charge is applied to the gate. This change in the electrical charge on the transistor allows electrons to move from the source to the drain. There are several types of switch technologies—CMOS (complementary metal oxide semiconductor), RF CMOS, silicon germanium (SiGe), BiCMOS, and CMOS on silicon-oninsulator (SOI) technologies.

1.3 MOORE’S LAW Dr. Gordon Moore made his famous observation in 1965 and the press called it Moore’s law. Moore observed and predicted the doubling of transistors in the same size of an IC every two years (Fig. 1.1). Moore’s law has tremendous implications—it motivates and challenges all of us. With a global consumer’s need and an orchestrated and cooperative effort from all industry manufacturers, suppliers, government organizations, consortia, and collaborations between universities and semiconductor industries, we are marching and keeping pace with Moore’s law.1 Intel expects that it will continue at least through the end of this decade.

1.4 HOW CHIPS ARE DESIGNED Once the customer and chip design house agree on the purpose of a chip, the design process commences. A typical design process includes architecture, logics, circuit, verification, layout, test, approval of design, and release to fabrication.

* “No Exponential Is Forever ... but We Can Delay ‘Forever’,” Gordon Moore, International Solid State Circuits Conference, February 10, 2003.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

05/04/2005

18:01

Page 1.5

HOW SEMICONDUCTOR CHIPS ARE MADE HOW SEMICONDUCTOR CHIPS ARE MADE

1.5

1.5 WHERE CHIPS ARE MADE Chips are made in the most sophisticated manufacturing plants in the world, called wafer fabrication facilities or wafer fab. Typically 300-mm fabs cost $2 billion to build and equip. Today, there are over 1000 fabs around the world producing millions of chips everyday. The chip manufacturing process occurs in a cleanroom of a fab. A class-one cleanroom provides the world’s cleanest environment where air is continuously filtered to keep airborne contaminants to not more than one dust per cubic foot. Huge air filtration systems completely change the air in the cleanroom at the rate of about 10 times per minute. In addition to the cleanest air, stringent cleanliness requirements are also followed in the use of chip-making materials, chemicals, and processing equipment. Workers in fabs wear special clothing including gowns called “bunny suits,” hoods, facemasks, glasses, gloves, and shoe covers to avoid contaminating the chips. The temperature, barometric pressure, and humidity are controlled. All these efforts to avoid contamination in fabs are needed to ensure an accepted yield of chips that meet specifications.

1.6 HOW CHIPS ARE MADE Computer chips are built with pure silicon (99.9999999 percent pure) and metals. A silicon seed crystal is dipped in purified molten silicon and is rotated and pulled out as it revolves to grow into a silicon cylinder or ingot* (Fig. 1.2). Once the ingot reaches the desired size, it is prepared, inspected, and tested. The ingot is then sliced into many thin silicon wafers that are then polished. Hundreds of chips are made from each wafer. Chips are made in a precise manufacturing process that involves hundreds of operations being executed layer by layer onto a silicon wafer with constant testing. Chip making involves repeating processes using ultraviolet light, polymers, solvents, and gases. The processes include insulating (silicon dioxide), placing (deposition), patterning (with stencils known as masks), removing (etching), implanting (doping) and diffusion, and depositing interconnection metals (aluminum, copper). Each layer consists of thousands of microscopic components. In the process of building these layers, thousands FIGURE 1.2 Silicon ingot and silicon wafer. to millions of transistors are created and interconnected. (Courtesy of Dooson Company.) When completed, a single wafer will contain hundreds of identical dies (chips) that must pass rigorous testing and are then cut from the wafer. Each chip is then mounted onto a metal or plastic package. The mounted chip undergoes final testing and then is ready to be assembled into final products. Intel’s website illustrates how chips are made in detail.2 1.6.1 Oxidation Layering On a silicon-based wafer, the first thin layer of silicon dioxide (Fig. 1.3(a)) is formed over the complete wafer by exposing the wafer to a high temperature in a furnace. The oxidation temperature is generally in the range of 900–1200°C. The silicon dioxide layer is used to provide insulation to protect the silicon beneath it and to form transistor gates.

*

Doosoon company, www.dooson-inc.com.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:32

Page 1.6

HOW SEMICONDUCTOR CHIPS ARE MADE 1.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

SiO2

Si-substrate

(a) Add oxidation layer on silicon base material (the right illustration is the cross section from the front side)

Photoresist

SiO2

Si-substrate

(b) Add photoresist layer

(c) Mask for patterning

(d) Pass ultraviolet light through mask

Photoresist

Photoresist

SiO2 Si-substrate

(e) After revealing the mask pattern FIGURE 1.3 Process steps for patterning silicon dioxide: (a) add oxidation layer on silicon base, (b) add photoresist layer, (c) mask for patterning, (d) pass ultraviolet light through mask, (e) after removing photoresist and revealing the mask pattern, ( f ) after etching of silicon dioxide, (g) after removing photoresist.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:32

Page 1.7

HOW SEMICONDUCTOR CHIPS ARE MADE HOW SEMICONDUCTOR CHIPS ARE MADE

Photoresist

1.7

Photoresist

SiO2

SiO2 Si-substrate

(f) After etching of silicon dioxide

SiO2

SiO2 Si-substrate

(g) After removing photoresist FIGURE 1.3

(Continued)

1.6.2 Photoresist Coating The wafer is then uniformly coated with a substance called photoresist (Fig. 1.3(b)), a light-sensitive material that can be processed into a specific pattern after being exposed to ultraviolet light in the shape of the desired pattern. There are two main types of photoresists—negative and positive. When a negative resist is used, the unexposed portion of the photoresist becomes soluble, leaving a negative image. Alternatively when a positive resist is used, the exposed portion of the photoresist becomes soluble. Both positive and negative resists can sometimes be used on a single mask for two steps, making complementary regions available for processing, and therefore reducing the number of masks.3 1.6.3 Patterning Through the process called photolithography, ultraviolet light is then passed through a patterned glass mask, or stencil, onto the silicon wafer (Fig. 1.3(c)). The mask represents one color layer of the integrated circuit from mask blueprints and contains a specific pattern that is to be transferred to the silicon. Assuming a positive photoresist, the mask is transparent in the region that needs to be processed and opaque in the others. When the ultraviolet light exposes the photoresist through the combination of mask and wafer (Fig. 1.3(d)), the photoresist becomes soluble wherever the mask is transparent. After pattern generation, the exposed photoresist is dissolved by spraying the wafer with the developing solvent (Fig. 1.3(e)). This reveals a pattern of the photoresist made by the mask on the silicon dioxide. Then the wafer is hardened at a low temperature so that the remaining photoresist, which can resist the strong acid, is used to etch the exposed oxide layer. 1.6.4 Etching The revealed silicon dioxide is removed through a process called etching, which stops at the silicon surface (Fig. 1.3( f )). There are two main types of etching technologies—wet and dry etching.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:32

Page 1.8

HOW SEMICONDUCTOR CHIPS ARE MADE 1.8

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

(a) Add second silicon dioxide layer

(d) Pass ultraviolet light through mask

(b) Add polysilicon layer

(e) After etching of polysilicon and silicon dioxide layers

(c) Add photoresist layer

(f) After removing photoresist

FIGURE 1.4 Process steps for patterning a polygon layer: (a) add second silicon dioxide layer, (b) add polysilicon layer, (c) add photoresist layer, (d ) pass ultraviolet light through mask, (e) after etching of silicon dioxide, ( f ) after removing photoresist.

Wet etching removes the areas that are not covered by photoresist with liquids, including many different types of acids, bases, and caustic solutions, as a function of the material that is to be removed.3 In dry etching, or plasma etching, the reactive ionized gas is used in place of a wet-etching solution. Dry etching provides a higher resolution than wet etching, and therefore has emerged to replace wet chemistry approaches in modern semiconductor manufacturing.4 After silicon dioxide etching, the rest of the photoresist is removed (Fig. 1.3(g)) in a photoresist stripper by using either a solvent or plasma oxidation. This process leaves ridges of silicon dioxide on the silicon wafer base with the same pattern as the image on the mask. Figure 1.3 illustrates the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:32

Page 1.9

HOW SEMICONDUCTOR CHIPS ARE MADE HOW SEMICONDUCTOR CHIPS ARE MADE

1.9

process steps of how to transfer a pattern onto the silicon wafer. The sequence of the process steps patterns exactly one layer of the semiconductor material, and the same sequence patterns the layer of the complete surface of the wafer. Thus, hundreds of millions of patterns are transferred to semiconductor surface simultaneously. 1.6.5 Layering To introduce a polygon layer, a second and thinner layer of silicon dioxide is grown from thermal oxidation as before over the ridges and etched areas of the wafer base (Fig. 1.4(a)). Then a layer of polysilicon (Fig. 1.4(b)) and another layer of the photoresist (Fig. 1.4(c)) are evenly spread on the wafer. The photolithography process is applied to define the polygon region. Ultraviolet light exposes the photoresist through a second mask, leaving a new pattern for polysilicon on the photoresist (Fig. 1.4(d)). The photoresist is dissolved with a solvent to expose the polysilicon and silicon dioxide, which are then etched away with chemicals (Fig. 1.4(e)). After the remaining photoresist is removed (Fig. 1.4( f )), ridges of polysilicon and silicon dioxide are left on the polygon region. Figure 1.4 illustrates the process steps of how to transfer another polysilicon layer on the previous layer. A similar process will be repeated over and over again with each mask to pattern different layers of deposited materials. During this manufacturing process, conductive regions are formed and insulated from each other. Later they are selectively connected to each other to produce an integrated circuit. 1.6.6 Doping: Diffusion and Ion Implantation Many steps in the IC manufacturing process require a change in the dopant concentration of some areas to make them more conductive. Two approaches are used to introduce dopants—diffusion and ion implantation. Diffusion implantation is performed by either exposing the wafer to a high-temperature environment of dopant vapor (gaseous diffusion) or predepositing dopant ions on the surface and then thermally driving them in by high-temperature processing (nongaseous diffusion). The final concentration is greatest at the surface and decreases deeper in the material. Ion implantation is performed by bombarding the exposed areas of the silicon wafer with various chemical impurities called ions. With an implanter, ions are accelerated and implanted into the top layer of the silicon wafer just below the surface, altering conductivity in these areas. Figure 1.5 illustrates the exposed area before and after ion implantation. The acceleration of the ions determines how deep they will penetrate the material, while the exposure time determines the dosage. Therefore ion implantation provides a better controlled doping mechanism than diffusion. This is the reason doping technology has shifted from diffusion process to high-energy ion implantation in modern semiconductor manufacturing.4

(a) Before ion implantation FIGURE 1.5

(b) After ion implantation

Ion implantation: (a) before ion implantation, (b) after ion implantation.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:32

Page 1.10

HOW SEMICONDUCTOR CHIPS ARE MADE 1.10

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

(a) Add silicon dioxide layer

(d) After etching of silicon dioxide and creating contact holes

(b) Add photoresist layer

(e) After removing photoresist

(c) Pass ultraviolet light through mask

(f) Add metal layer to fill the contact holes

(g) After patterning and etching FIGURE 1.6 Process steps of depositing interconnect metal: (a) add silicon dioxide layer, (b) add photoresist layer, (c) pass ultraviolet light through mask, (d ) after etching of silicon dioxide and creating contact holes, (e) after removing photoresist, ( f ) add metal layer to fill the contact holes, (g) after patterning and etching.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:32

Page 1.11

HOW SEMICONDUCTOR CHIPS ARE MADE HOW SEMICONDUCTOR CHIPS ARE MADE

1.11

1.6.7 Depositing Interconnection Metals To connect different layers, similar layering and patterning processes are repeated (Fig. 1.6(a)–(c)). A mask is used to define contact holes allowing for the connections to be made between layers. After the etching of the silicon dioxide in the exposed area (Fig. 1.6(d)) and the removal of the remaining photoresist (Fig. 1.6(e)), the contact holes are created. A combination of tungsten and aluminum is then deposited onto the whole wafer to fill the contact holes under high-vacuum conditions (Fig. 1.6(f)). Another patterning and etching stage defines a contact pattern and leaves strips of the metal to make the electrical connections (Fig. 1.6(g)). In sophisticated circuits, the interconnect wiring is so complex that it is impossible to complete within a single layer. Approximately 20 layers are connected to form an IC in a three-dimensional structure. The exact number of layers on a wafer depends on the complexity of the design. After all the desired levels are in place, a final layer of insulation is deposited to protect the fragile aluminum wiring. In the last photolithograph step, small pads along the edge of the microchip are left exposed. These aluminum pads are the contact points between the microscopic wiring of the IC and the outside world. 1.6.8 Testing In the previous example a simplified process is completed to manufacture a tiny portion of a microchip. In reality, making a chip is much more complex. The complete run of the manufacturing process might involve hundreds of individual steps and take weeks to complete. Identical chips, or dies, are created in batches on a single wafer, and each finished wafer may contain hundreds of actual chips. A chip on a finished wafer is illustrated in Fig. 1.7. Despite the caretaken in the fabrication process, not all the chips on the wafer work. Automated methods are used to test the microscopic circuitry of each device on the wafer before it is cut into individual chips with a diamond saw, separating the chips on the wafer. 1.6.9 Packaging Each chip is then inserted into a protective package that provides mechanical support and an electrical connection interface with other external devices. The tiny chip is mounted on a metal frame, and thin gold wires connect the individual pin on the frame to the small aluminum pad on the chip. Thus, the pins on the metal frame are attached to the microscopic circuitry. To further protect the chip and its fragile wire bonds, the chip is encapsulated in hard plastic. Packaging also removes the heat generated by the circuit and protects the chip against environmental conditions such as humidity.3 The type of package depends on the type of microprocessor and its usage (Fig. 1.8).

FIGURE 1.7

Each square represents a chip on a finished wafer.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH01.qxd

04/04/2005

19:32

Page 1.12

HOW SEMICONDUCTOR CHIPS ARE MADE 1.12

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

FIGURE 1.8

Packaged microprocessors.

Each packaged chip is loaded on the testing board to test one more time, marking the last step in the chip-making process. The chips would be electrically stressed far beyond normal conditions, so weak chips are forced to fail before they are put into customers’ products. The chips are now ready for shipping to companies that will use them to make everyday items.

REFERENCES 1. Hammond, M. L., “Moore’s Law: The First 70 Years,” Semiconductor International, 2004. 2. Intel, Inc., http://www.intel.com/education/makingchips. 3. Rabaey, J. M., A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, pp. 33–55, 2d ed., Prentice-Hall, New Jersey, 2002. 4. Elliott, D., Microlithography Process Technology for IC Fabrication, pp. 311–350, McGraw-Hill, New York, 1986.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 2

IC DESIGN Ilsun Park Advanced Micro Devices Austin, Texas

2.1 INTRODUCTION In 1947, Drs. John Bardeen, Walter Brattain, and William Shockley discovered the transistor effect while working as researchers for Bell Labs. Prior to the invention of the transistor, bulky, unreliable vacuum tubes were used in electronic circuits. Eleven years later, Jack S. Kilby, an engineer at Texas Instruments, and Robert Noyce, cofounder of Fairchild Semiconductor, took the idea of miniaturizing circuits one step further and created the integrated circuit. The first commercially available integrated circuit was available in 1961, and comprised one transistor, one capacitor, and three resistors and was the size of a postage stamp. Forty years later, the AMD Opteron processor die had over 100 million transistors in an area smaller than a fingernail.

2.2 TYPES OF ICs The first integrated circuit (IC) was used in missile guidance systems and pocket calculators. Today, there are many different applications of integrated circuits. Dynamic random access memory (DRAM) is used in most personal computers due to low cost and small size. Each data bit is stored in a separate capacitor that leaks charge over time and thus needs to be refreshed periodically to keep its value. Unlike DRAM, a static random access memory (SRAM) cell will retain its value as long as power is applied. This is accomplished using transistors and is thus more expensive and harder to produce than DRAM. SRAM is generally faster than DRAM. An electrically erasable programmable read-only memory (EEPROM) is a nonvolatile memory that can be erased and reprogrammed electrically. The EEPROM can store data even when there is no power applied to it. An EEPROM can be rewritten a limited number of times, but can be read any number of times. The microprocessor is the largest and the most complex example of an IC. Often referred to as a central processing unit (CPU), the microprocessor is designed to perform many different functions. A microprocessor comprises many different units, including an arithmetic logic unit, a floating point calculation unit, and cache memory. An application specific integrated circuit (ASIC) is an IC that is designed for a specific task or purpose, unlike the microprocessor. Because custom ASICs can be very costly to design and produce, many designers will often substitute a field programmable gate array (FPGA) for smaller

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

2.1

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.2

IC DESIGN 2.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

designs. An FPGA is a reprogrammable logic device that uses gate arrays to implement the user’s design. A very common type of ASIC is a digital signal processor (DSP). This is a microprocessor that is usually designed to measure or manipulate a continuous real-world analog signal in a digital domain. The analog signal coming into the DSP is converted into a digital representation by the DSP. When leaving the IC, the digital signal can pass through a digital-to-analog converter and be output as an analog signal.

2.3 THE P-N JUNCTION Silicon itself is a semiconductive element and is not suitable for conducting current on its own. However, when impurities such as gallium, boron, or aluminum are added, thereby doping the silicon, a deficiency of electrons is created in the silicon, giving it a positive bias. The absence of an electron in the silicon molecule is commonly called a “hole.” This type of doped silicon is commonly referred to as p-type. Similarly, if silicon is doped with an impurity such as arsenic or antimony, then an excess of free electrons is created, thus creating a negative bias. This type of doped silicon is known as n-type. When p- and n-type silicon are placed in contact with each other, the junction of these two materials allows electric current to flow in one direction from p to n, but not in the other. This p-n junction is the basic building block of many types of electronic devices such as the diode and the transistor.

2.4 THE TRANSISTOR If three regions of doped silicon are placed in contact with each other (e.g., p-n-p or n-p-n), a small current applied to the center region (commonly called the base) that is doped opposite of the two other regions can be used to control a much larger current traveling between the two regions (commonly called the emitter and collector regions) that are doped opposite of the base of the npn or pnp junctions. This phenomenon is referred to as the transistor effect. With this effect, the base now acts as a current switch for turning the transistor’s emitter-collector junction on or off. In normal use, a small current differential between the base-emitter junction will cause an amplification at the collector terminal. This type of npn or pnp transistor is referred to as a bipolar junction transistor (BJT) (Fig. 2.1). The transistor that was invented at Bell Labs in 1948 was a BJT. BJTs are commonly used as current amplifiers, switches, and in analog circuits. They offer high gain and low output impedance, but dissipate a high amount of power. A schematic representation for BJTs—npn and pnp transistors— is shown in Fig. 2.2.

Base

Emitter

Collector

Metal

SiO2

n p Si

n FIGURE 2.1

npn BJT transistor.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.3

IC DESIGN IC DESIGN

Collector

Collector

p Base

2.3

n Base

n p

p n

Emitter

Emitter

C

C

B

B

E FIGURE 2.2

E

BJTs—npn and pnp—symbolic representation.

Another type of transistor, and one that is used in a majority of digital integrated circuits today, is called the metal-oxide-semiconductor-field-effect transistor (MOSFET). Instead of using the notation of base, collector, and emitter, the MOSFET uses the notation of gate, source, and drain (see Fig. 2.3). By adding a layer of SiO2 to provide insulation between the metal contacts, the gate input impedance is greatly increased over that of the base input impedance of the BJT, allowing for much lower power consumption than BJT transistors. A MOSFET that is configured in an n-p-n format similar to Fig. 2.3 is often referred to as an “n channel” MOSFET because a small channel of electrons will form between the two n substrates when an electrical stimulus is applied. Similarly, a MOSFET that has two p substrates embedded in an n substrate (p-n-p) is referred to as a “p channel” MOSFET, due to the creation of a small channel of holes. When MOSFETs are combined in certain configurations, the circuits can perform boolean logic functions. By using both n and p channel MOSFETs in the same circuit, there is almost no

Metal Drain

Gate

Source SiO2

n

n Si

p FIGURE 2.3

n-channel MOSFET.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.4

IC DESIGN 2.4

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

static power dissipation. Power is dissipated only when the circuit switches from 0 to 1 or vice versa. The combination of n- and p-channel MOSFETs in one device is referred to as complementary meta oxide semiconductor (CMOS) technology. s The combination of BJT and CMOS technologies is g referred to as BiCMOS technology. This technology is still pmos under active research, but shows much promise for amplifier and discrete logic component designs, due to the high input resistance of the MOSFET and the low output resistance of d the BJT. Using CMOS technology, low-power boolean logic gates Vin Vout can be created. An example of an inverter created using an N-channel metal oxide semiconductor (NMOS) and a P-channel s metal oxide semiconductor (PMOS) transistor is shown in g Fig. 2.4. When Vin = 0 (Gnd), the PMOS source to the drain nmos channel is switched on while the NMOS source to the drain channel switches off. This causes Vout = Vcc. d There are seven fundamental logic gates—NOT, AND, OR, NAND, NOR, XOR, and XNOR. These gates comprise the building blocks of the majority of ICs. Figure 2.5 shows each Gnd gate in its symbolic schematic representation. FIGURE 2.4 CMOS inverter. An IC that is designed from the gate level up is described as a bottom-up design. Conversely, a design can be modeled behaviorally at a high level and coded in a hardware description language (HDL). This is then converted into a register transfer level (RTL) code, from which gates are synthesized. This type of design methodology is described as top-down. Because modern designs are becoming increasingly complex with millions of gates, it is often impossible to use a bottom-up methodology for an IC design. Vcc

a

n

a b

NOT

n NAND

a b a b

n NOR

n AND a b

n XOR

a b

n OR

a b

n XNOR

FIGURE 2.5

Schematic representation of boolean logic gates.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.5

IC DESIGN IC DESIGN

2.5

2.5 DESIGNING AN IC A typical top-down IC design flow is shown in Fig. 2.6. The shaded steps are verification steps. The first step, and possibly the most important, is the creation of the device specification. The specification describes the architecture, functionality, and interfaces of the device. A typical device structure example is shown in Fig. 2.7. In this example, the device to be designed is an accelerated graphics Specification port (AGP) bus stimulator. It contains three different types of architectures—universal serial bus (USB) slaves, AGP master, and peripheral component interconnect (PCI) slave. The interfaces to Behavioral model the outside world are denoted by arrows. The specification must be detailed enough to follow when the HDL or RTL coding begins. Experienced engineers should be consulted during the specification process, as changes to the speciRTL model fication during the designing process can result in significant delays. If care is taken during the specification procedure, implementation mistakes in later phases of the design flow can be easily spotFunctional verification ted and rectified. When designing an IC, there are many things that have to be taken into consideration. What sort of architecture and interfaces are going to be used? Should the IC be designed to optimize for Synthesis speed, area, or power? Can parts of the IC use an existing design? And should the IC be designed for reuse in a later project? In addition to these issues, design testing methodologies (both simulation Logical verification and physical silicon), HDL, computer aided design (CAD), and layout tools that are to be used must be determined before HDL coding begins. The specification period is also when development costs, proPlace and route duction costs, and project schedule time should be determined. Once a device specification is created, a behavioral model of the IC can be designed. The behavioral model is used to simulate the funcLayout verification tionality and performance laid out by the device specification, before it is converted to RTL. A behavioral model is typically written in an HDL and cannot be synthesized into actual gates. Implementation However, there are certain behavioral synthesis tools that now aid in converting a behavioral model into RTL code. The behavioral model should be able to interface to any other blocks in the design. FIGURE 2.6 IC design flow. The behavioral model is then converted to RTL. This step is done manually by the designer, who must create a cycle accurate, fully clock drive, fully functional model. The RTL becomes the input for the synthesis tool that marks the point in the design flow in which CAD tools must then be used. Most of the manual design work is concentrated on optimizing the RTL for the synthesis tool. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.6

IC DESIGN 2.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

USB Interface to Host Controller

USB slave

AGP bus stimulator IC

AGP master

PCI slave

AGP interface to Target

PCI interface to Target

FIGURE 2.7

AGP bus stimulator block design example.

Synthesis is the process of converting the RTL design into a gate-level design. Due to the complexity of modern RTL designs, this step must be done with the aid of a computer. The synthesis tool creates a list of gates and nets from the RTL design. This “netlist” is then input into another tool, which will place the gates and route the nets according to constraints and optimizations specified by the designer. This output from the place and route tools becomes the physical layout of the integrated circuit. A modular design must be created in such a way that any type of model can be interfaced with any other type of model. For instance, a block in the RTL model phase must still be able to interface to a different block that is in the behavioral model phase. By doing this, simulation and testing can occur even when different portions of the IC are in different design phases. Verification of a design is done by means of a test bench. A test bench is generally coded using an HDL and should be able to interface to behavioral or RTL code or synthesized gates. The test bench usually encloses the device under test, and stimulates the behavioral, RTL, and gate-level designs with vectors. A successful set of vectors should verify the functionality of the design completely. The set of test vectors should also be able to detect common gate-level hardware faults. The test bench should not be coded by the same engineering team that designs the IC. More information about IC verification and test bench writing can be found in Ref. 1.

2.6 FUTURE TRENDS AND ISSUES IN IC DESIGN As IC technology progresses, the size of the transistor is decreasing, while the amount of logic in a design increases. Because HDLs, logic synthesis tools, and place and route CAD tools have become more sophisticated, it is now possible to create large, complex digital designs. However, as design Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.7

IC DESIGN IC DESIGN

2.7

complexity and gate count increase, power and heat dissipation begin to become a serious issue. As transistor features sizes shrink to submicron sizes, new and challenging electrical problems begin to emerge. Designers must keep these issues in mind when creating ICs. For the past 40 years, IC design has been steadily moving away from manual, gate-level schematic entry and continues to do so. CAD tools and HDLs are making it easier to develop complex ICs, and as these tools improve and become more sophisticated, are allowing for nearly optimal IC implementations.

BIBLIOGRAPHY Miczo, A., Digital Logic Testing and Simulation, 2d ed., New York: Wiley, July 2003, p. 696. Christiansen, J., IC Design Methodology, CERN, 2002, http://humanresources.web.cern.ch/humanresources/ external/training/tech/special/ELEC-2002/ELEC-2002_23Apr02_1_PDF.pdf. Keating, M., and P. Bricaud, Reuse Methodology Manual, New York: Kluwer Academic Publishers, 2002. Palnitkar, S., Verilog® HDL: A Guide to Digital Design and Synthesis, Mountain View, CA: Sunsoft Press, 1996. Sternheim, E., et al., Digital Design and Synthesis with Verilog® HDL, San Jose, CA: Automata Publishing, 1993. Streetman, B., Solid State Electronic Devices, Upper Saddle River, NJ: Prentice-Hall, 1999.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH02.qxd

04/04/2005

19:33

Page 2.8

IC DESIGN

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 3

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING K. V. Ravi Intel Corporation Santa Clara, California

3.1 INTRODUCTION The exponential growth of semiconductor electronics based on silicon technology is well known. A fundamental factor that has enabled this remarkable evolution of the technology and the inexorable progression of Moore’s law is a result of the unique properties of silicon. In this chapter an overview of silicon substrate technology will be presented. Following a brief discussion of the key properties of silicon, which make it the preeminent semiconductor material, the approaches for the manufacture of silicon wafers will be reviewed. A discussion of various semiconductor substrates, either currently in use or contemplated to be used to extend Moore’s law, will form the major portion of the chapter. Silicon wafers or substrates are most commonly used as active semiconductors in which electronic devices of various kinds are manufactured. An increasing trend is the use of silicon substrates as passive or semipassive materials, not participating electronically in the functioning of devices or circuits, but functioning as lowcost, high-volume substrates for either silicon films or other semiconducting, optical, mechanical, or magnetic materials. This is likely to be an increasing trend in the future where high-cost materials that are not easily manufactured as large area substrates are mated with silicon substrates using innovative wafer bonding or hetroepitaxial technologies. Such approaches may also be utilized in combining the electronic functions of silicon with, for example, optical functions of optoelectronic materials such as gallium arsenide or indium phosphide.

3.2 KEY ATTRIBUTES OF SILICON AS A SUBSTRATE MATERIAL Silicon enjoys a number of unequalled properties and characteristics that have made it the pervasive semiconductor material. While an exhaustive discussion of these characteristics would not be appropriate in this brief review, the major characteristics of silicon are briefly reviewed.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

3.1

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.2

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

TABLE 3.1 Electronic Function of Silicon Physical properties Band gap, eV Relative dielectricconstant Thermal conductivity, W/cm-K Lattice electron mobility, V/cm2 Lattice hole mobility, V/cm2 Breakdown electric field, V/cm

1.45 11.7 1.45 1350 480 3 X 5e10

3.2.1 Electronic and Thermal Properties Table 3.1 lists the relevant properties that determine the electronic function of silicon. 3.2.2 Availability Silicon is the second most abundant element in the Earth’s crust, most commonly occurring as its oxide with quartzite being the common ore of silicon from which elemental silicon is extracted. 3.2.3 Manufacturability Perhaps the most attractive aspect of silicon is the sophisticated manufacturing technology that has been developed for converting the naturally occurring ore of silicon (quartz or silicon dioxide) into very high-quality, large-area, single crystal substrates for the manufacture of current day advanced semiconductor products. Two major developments over the years have been a continuing reduction in the levels of heavy metals in the wafers and continuing advances in wafer flatness which in turn has facilitated advanced lithography for the printing of ever finer features on the wafers. 3.2.4 Wafer Diameter The need to enhance manufacturing productivity has motivated increases in the wafer diameter. As the wafer area is increased by more than two times, the cost of a new tool set for wafer fabrication is found to increase only by 30 to 40 percent and the total cost per area of a processed wafer is found to decrease by 30 to 50 percent. Since this is a major activity that has to address the growth—and conversion into wafers—of larger diameter ingots and the development of a full complement of wafer processing equipment, the transition in wafer diameters took approximately a decade. A transition to 200 mm wafers, from 150 mm diameter wafers, occurred at around 1990 and the initial conversion to 300 mm wafers began haltingly in 1999 and is currently accelerating. The International Technology Roadmap for Semiconductors (ITRS) projects the next transition to 450 mm in about 2011 to 2012,1 roughly 10 years from the 300-mm conversion. However, the transition to 450 mm ingots is a major step with new physical limitations for the cost-effective growth of such large ingots. This is discussed further later in this chapter. 3.2.5 Cost The cost per unit area of silicon has, roughly, remained the same with the transition from 150 to 200 mm diameter wafers. However, the transition to 300 mm has increased the unit cost relative to 200 mm wafers by roughly 50 to 75 percent. This increase in cost as a result of scaling is attributable to increased equipment costs, such as crystal growth equipment, as well as reduced productivity, particularly in crystal growth, due to fundamental limits to achievable growth rate as crystal diameter is increased. Despite the higher costs of larger diameter wafers, on a total cost basis, the transition to larger wafers makes excellent economical sense in integrated circuit manufacture. For example, a 300-mm wafer will enable

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.3

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

3.3

approximately 2.5 times the number of die to be fabricated as compared to a 200-mm wafer at a total increase in cost, including all materials and capital, of less than 1.5 times.

3.3 THE BASICS OF SILICON WAFER MANUFACTURE The literature is replete with information on the processes used for the manufacture of silicon wafers. Consequently, only a brief outline of the manufacturing process will be discussed here for the sake of completeness. The raw material for silicon wafer manufacture is high-quality, semiconductor-grade polysilicon. This is manufactured by reducing quartz of quartzite by carbon in arc furnaces. The resulting material, metallurgical-grade silicon, is purified to semiconductor-grade silicon by a series of halogenation and fractional distillation processes. Typically the silicon is converted into trichloro silane in a fluidized bed by reaction with anhydrous hydrogen chloride (HCl). When anhydrous HCl reacts with metallurgical-grade silicon, a number of reaction products result. These include SiHCl3, SiCl4, H2, and several metallic halides such as AlCl3, BCl3, and FeCl3. Trichloro silane is fractionally distilled from the impurity halides to result in a very high purity compound. Trichloro silane is thermally decomposed into silicon and HCl in the presence of hydrogen in a reactor in which a heated thin rod of silicon (and sometimes molybdenum) is utilized for the deposition of silicon. The resulting polysilicon rods are broken up into smaller pieces to load into a crucible for crystal growth. The most widely used process of crystal growth is the Czochralski or the ingot-growth process in which semiconductor-grade polysilicon is melted in a quartz crucible contained within a chamber with a controlled atmosphere. A seed crystal, typically less than 1 cm in diameter, is contacted with the silicon melt and slowly withdrawn vertically resulting in the melt in contact with the seed solidifying into a single crystal. In this process very careful temperature control is exercised such that the increase in the temperature of the solid-liquid interface, resulting from the latent heat of solidification, is compensated for by a reduction in the power input to the system and hence its temperature. Another important process for achieving dislocation free crystals is a process through which, after the initial growth of a short segment of the crystal, the crystal diameter is decreased followed by an increase in the ingot diameter. This local decrease in the diameter, called necking, causes thermal shock induced dislocations in the growing crystal to grow out of the crystal at the neck with the subsequently grown crystal being dislocation free. The final diameter of the ingot is achieved gradually to prevent stress introduction and to control the diameter. Following the growth of an ingot of a desired length, the pull rate is increased quickly to detach the crystal from the remaining melt in the crucible. Figure 3.1 shows an example of a contemporary 300-mm silicon ingot. Following ingot growth, the seed and tang ends—the ends of the ingot that do not meet the diameter requirements—are cut away, the ingot is centerless ground to the exact diameter, and an orientation notch (and sometimes a flat) is ground into the ingot using x-ray techniques for orientation determination and alignment. The ingot is now sliced into individual wafers using multiwire saws and is subsequently subjected to a series of grinding, lapping, and polishing operations to result in the final, very high quality wafers. Wafer fabrication operations are highly automated with an emphasis on quality with regard to particles and wafer flatness.

3.4 SILICON AS A SUBSTRATE MATERIAL Silicon wafers have evolved substantially over the past couple of decades. The evolution has proceeded along two directions—evolution in diameter with current state-of-the-art wafers being 300 mm in diameter and evolution in complexity in response to the increasing demand for more functionality of the material. Figure 3.2 is an illustration of the evolution of silicon substrates in both these attributes. In this section both these evolutionary paths will be discussed.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.4

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.4

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

FIGURE 3.1 An example of a 300-mm ingot. The seed crystal is shown at the right and the crystal diameter is gradually increased to the full diameter. On the left is shown the last portion of the ingot to solidify. The sections of the ingot, called the seed and the tang ends are cut off and the segment of the right circular cylinder is subsequently centerless ground to the exact diameter and sliced into wafers.

The evolution of silicon substrates 1990

2000

2011

200 mm

300 mm

450 mm Evolution in diameter (productivity)

Bulk substrates Epitaxial wafers Silicon-on-insulator (SOI) wafers Strained silicon wafers Strained silicon on insulator wafers

Evolution in functionality (complexity)

Germanium on silicon and on oxide on silicon Compound semiconductors on silicon Silicon on diamond wafers FIGURE 3.2 Schematic illustration of the evolutionary paths in silicon wafer development. Wafer diameter increases are motivated by economics of manufacturing and increasing functionality of the wafers enables new capabilities.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.5

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

3.5

3.4.1 Silicon as an Active Substrate Material A large class of devices is manufactured using polished silicon wafers as substrate materials. These include many discrete devices such as transistors, power and RF devices, and, very importantly, dynamic random access memories (DRAMs). As is well known, silicon wafers can be controllably doped during crystal growth and the wafers in turn can be selectively doped using gas phase diffusion or ion implantation processes for the manufacture of a large complement of complex devices and circuits. Polished silicon wafers represent the lowest cost version of this material for both discrete-device and integrated circuit manufacture. A key aspect of polished silicon wafers for the manufacture of advanced integrated circuits is the need for a preprocess step, prior to device fabrication, which modifies the surface and near surface characteristics of the wafer. Since silicon crystal growth is done by melting silicon in a quartz crucible, a necessary accompaniment to this process is the dissolution of the quartz in the molten silicon and the attendant incorporation of oxygen in the crystal. The subsequently sliced and polished wafers will have a distribution of oxygen throughout the bulk as well as at the surface. The key effects of oxygen are as follows: • Interstitial oxygen is a donor in silicon, altering the electrical characteristics of the material. Annealing the ingots can cause the oxygen to move from the interstitial, electrically active, locations in the crystal, thus eliminating the electrical effects. A donor anneal process is a frequent step following the production of the ingot. • Oxygen at the surface of the wafer can introduce adverse effects in shallow p-n junctions and at the silicon-silicon dioxide interface, causing excessive leakage, premature breakdown, a compromise in the integrity of gate oxides, and a variation of the electrical parameters across the wafer. • Oxygen, when converted into oxide precipitates (silicon dioxide) can function as internal gettering agents to attract and trap fast-diffusing heavy metals in wafers. However, this has to be achieved in such a way that oxide precipitates are not present at the surface as their presence would have severe negative electrical consequences in devices. In addition to oxygen another defect that has to be dealt with is commonly referred to as crystal originated particles or pits (COPS). COPS are aggregates of vacancies or vacancy clusters in the crystal formed as a consequence of the particular process attendant during solidification of the melt. Figure 3.3 shows a transmission electron micrograph of typical defects of this type. These tend to be micron-sized voids bounded by crystallographically defined surfaces. When such voids intersect the surface of a wafer, the result can be very small surface pits which in turn will disturb the planarity of an oxide used as the gate dielectric of metal-oxide-semiconductor-field-effect transistors (MOSFETs) that comprise the fundamental building blocks of integrated circuits such as DRAMs and logic products. (001) (111) 54.7° 35.3°

(110)

Observation

50 nm

FIGURE 3.3 Transmission electron micrograph of vacancy clusters (called COPS) in silicon wafer. The vacancy clusters or voids are frequently bound by crystallographically defined surfaces.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.6

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

To deal with the problems of COPS as well as oxygen, polished wafers are frequently annealed at elevated temperatures either in an atmosphere of argon or hydrogen. Annealing can have dual effects. Oxygen and COPS can be removed from the near surface regions of the wafer to depths of many microns, depending on the annealing conditions. Oxygen removal occurs by out diffusion and COP elimination can occur by the shrinking and the eventual disappearance of the vacancy clusters. These two processes are accelerated if hydrogen rather than argon is used as the process gas.2,3 A second effect of elevated temperature annealing is the precipitation of oxygen in the bulk of the wafer to form silicon oxide particles, which subsequently can function as internal gettering agents for heavy metals, as mentioned earlier. Thus a polished silicon wafer used for the fabrication of leading-edge integrated circuits is not a homogeneous material but an engineered structure with differing surface and bulk properties. The concept of defect engineering has been well developed to achieve high-quality, defect-free surfaces where the active devices reside and a two-phase material with a distribution of silicon dioxide particles in a silicon matrix in the bulk of the wafer. This is shown, schematically in Fig. 3.4. 3.4.2 Epitaxial Wafers With the advent and wide-scale use of CMOS circuitry and the aggressive scaling of the technology, attended by ever thinner gate oxides, lightly-doped, polished silicon wafers are no longer found to be sufficient for such products. As a consequence, epitaxial (epi) silicon wafers are now the mainstay for manufacturing advanced logic products such as microprocessors. Epitaxial wafers are polished silicon wafers with a thin layer of silicon, either of a different conductivity type, or more commonly, of a different resistivity deposited on the wafers (generally called the substrate wafer) using chemical vapor deposition (CVD) techniques. This is an extremely welldeveloped technology with high-quality epitaxial films ranging in thickness from about 1 µm to several microns for integrated circuit fabrication manufactured in highly automated equipment. Typically a mixture of hydrogen and silane is used as the process gases and silicon deposition on the single crystal substrate is achieved by thermal CVD, the cracking of the silane and the attendant deposition of silicon.

Dissolved oxygen, COPS in the wafer Surface depleted of defects and oxygen as a result of elevated temperature annealing

Bulk of the wafer has precipitates of silicon oxide FIGURE 3.4 Schematic illustration of defect engineering whereby a wafer containing dissolved oxygen and COPS (top figures) is converted into a wafer with a two-layer structure with a high-quality, defect- and oxygen-free device layer and an oxygen precipitate rich substrate that can function as a region into which unwanted heavy metals are gettered.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.7

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

3.7

The fundamental reasons for the use of epitaxial wafers are several fold. • A common failure mode of CMOS devices is a phenomenon called latch-up. This is a case where vertical pnp and lateral npn bipolar structures can switch on and draw excess current resulting in the destruction of the device. This is effectively prevented by having a high-conductivity (heavily doped) substrate under the lightly doped epitaxial layer in which the circuits reside. Heavy doping prevents the generation of stray charge carriers in the substrates. A further advantage of heavily doped substrates is conferring immunity from soft errors to the circuits. Soft errors are a result of stray a particles either from radioactive packaging materials or cosmic rays generating unwanted charge carriers (electron-hole pairs) that upset the state (on or off) of a transistor in the semiconductor. • A second reason for epitaxy is to achieve high bulk and surface quality silicon for device fabrication. Since modern day integrated circuits are, essentially devices very close to the surface of the wafer—within about a micron of the surface—the surface quality, in terms of impurities and defects, is critical for the high-yield manufacture of high-performance products. Vapor deposited epitaxial silicon on single crystal silicon wafers can display higher quality than melt grown crystals. Surface quality, the uniformity of dopants through the film, and control over the resistivity of the silicon are superior in epitaxial films. • A third reason for the attraction of epitaxial wafers is the opportunity to achieve vastly different resistivities between the substrate and the epitaxial layer. For example, typical epitaxial wafers have substrate resistivities as low as 0.005 Ω-cm while the overlying epitaxial film can have a resistivity approximately equal to 1 Ω-cm. The heavily doped substrate, which is doped with boron, performs several functions. Heavy doping in the substrate suppresses latch-up failure, as discussed earlier. The high concentration of boron can function as a gettering medium for metals, with particular reference to iron. A phenomenon known as solubility-enhanced gettering results in the attraction and trapping of iron by the heavily doped substrate, thus removing the metals from the top, lightly doped epitaxial layer in which the active devices reside. The gettering efficiency of the substrate is also enhanced by precipitated oxide particles that are formed as a combined consequence of the presence of a high concentration of oxygen in the substrate wafer and the heat treatments associated with epitaxial deposition and subsequent wafer processing. Since the top epitaxial layer is formed by vapor deposition it will be free of oxygen and consequently no precipitates form in this region. Heavily doped substrates also assist in suppressing the electrostatic discharge (ESD) failure of integrated circuits. ESD is a phenomenon whereby stray electric charges destroy devices and circuits. A heavily doped substrate effectively conducts away stray charges preventing ESD failure. Figure 3.5 shows schematically a cross section of a CMOS transistor in an epitaxial wafer with the various attributes of epitaxial wafers.

3.4.3 Silicon-on-Insulator Wafers The original concept of integrated circuits, as conceived by Noyce and Kilby, involved building multiple transistors in the same piece of silicon, electrically isolated from each other using reverse-biased p-n junctions, a process called junction isolation. With increasing shrinks and higher functionality of circuits, junction isolation was found to be inadequate for a number of reasons including the increased capacitance introduced by the junctions, which in turn adversely impacts the switching speed, the propensity for excessive junction leakage, and the increased space occupied by the isolating junctions. Consequently a transition has occurred to dielectric isolation with advanced products relying on shallow trench isolation where shallow, etched trenches filled with silicon dioxide surround the transistors. A further extension of this process is to provide a dielectric underneath the transistors as well as to, essentially, completely surround the transistor with an oxide on all sides. The use of a dielectric layer, underneath the transistors, resulted in the development of silicon-on-insulator (SOI) wafers wherein a thin, active device layer is separated from the bulk of the wafer by a thin, buried oxide. The thickness of the top layer, in which the devices are built, varies depending on device designs with the trend being in the direction of ever-thinner films on the top.4,5

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.8

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.8

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

N+ Thin epitaxial layer, lightly doped, free of oxygen with a high surface quality —good gate oxide integrity; low leakage junctions

N+

P+ N+

STI

P+

P-well

P+ N-well

Epitaxial layer

Substrate

Heavily doped with boron, silicon dioxide precipitates function as gettering agents for metals; heavy boron doping prevents latch-up failure, minimizes ESD sensitivity, and enhances heavy metal gettering. FIGURE 3.5

Schematic illustration of a CMOS circuit in an epitaxial wafer.

The presence of an insulating film between the active devices and the bulk of the wafer leads to several advantages as follows: • Feasibility of low-voltage ( less than 1 V) operation since stray currents from the substrate are suppressed • Higher speed capability due to lower junction capacitance since it is possible to dispense with well implants and have the bottom of the source/drain junctions terminate at the silicon-oxide interface • Higher operating temperatures due to reduced leakage currents • Lower power consumption because of lower operating voltages and reduced leakage currents • Decoupling the device area from the bulk of the wafer, due to the presence of the insulating layer, leads to reduced parasitic currents, immunity to a-particle effects (soft errors), and increased radiation hardness • For transistor gate lengths of approximately 25 nm and below the electric field in the channel induced by the gate has to compete with fields from the source and drain regions, resulting in degraded performance. These short channel effects are found to be reduced or eliminated by going to thin SOI structures. Ultrathin SOI is generally proposed to be the solution for short channel effects. • Designing devices for SOI can result in much simpler processing thereby reducing processing costs Figure 3.6 shows the comparison between traditional epi-based CMOS and SOI-based CMOS structures. Potential applications for SOI wafers have been expanding in recent times. These are shown in Fig. 3.7. The ability to electrically isolate the top device layer from the bulk of the wafer and the potential for making this top layer very thin (thicknesses equal to the depth of the junctions) lead to several advantages that enable proliferation of silicon into other product areas and into products with enhanced functionality.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.9

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

3.9

Conventional CMOS based on Epi wafers

Larger junction area leads to: -Higher leakage currents -Higher junction capacitance leading to limitations in device speed

P+

N+ N+

N+

P+

STI

P-well

P+

N-well

Conducting silicon beneath the transistors can result in stray currents leading to:

Epitaxial layer

• High off-stage leakage currents

Substrate

• Susceptibility to a-particle effects (soft errors) • Higher power consumption, greater heat generation CMOS using SOI wafers Smaller junction area can result in: • Low voltage (<1 V) operation • Higher speed due to lower capacitance • Higher temperature operation

N+ N+

P+ N+

P+

Buried oxide

FIGURE 3.6

Designing with SOI wafers can lead to: • Much simpler processing—lower cost

• Lower power consumption Decoupling the substrate from the active silicon volume enables elimination of parasitic currents— lower voltage operation, lower power consumption, immunity from a-particle events

P+

Substrate

• Low cost substrates can be used for wafer manufacture

Comparison of epi-based CMOS with an SOI-based CMOS structure.

SOI Wafer Manufacturing Processes. Over the years many approaches for manufacturing SOI wafers have been proposed. An exhaustive discussion of all these approaches would be beyond the scope of this review. Consequently the two most well-developed and commercial processes for manufacturing SOI wafers will be discussed. The literature cited should be consulted for delving into other approaches of SOI wafer fabrication. SOI wafers are manufactured by two methods nowadays:

Low-voltage (<1 V) applications • Portable systems • Cell phones • Notebooks • PDAs • Watches • Games

Memory products

Logic products • High-speed MPUs (20 to 30% speed improvement over epi) • Low-power logic (15 to 50% of the levels of epi-based products) • A particle immunity • Server applications • Three-dimensional structures

• Fast memory • A particle immunity

Automotive applications

Communications applications

• High-temperature applications • Smart sensors

• RF devices • Monolithic microwave ICs with cutoff frequencies of 20 to 30 GHz to replace GaAs devices • Optical applications–wave guides

FIGURE 3.7

Typical applications of SOI-based products.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.10

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.10

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

1. SIMOX Process.6 SIMOX, which stands for silicon separation by oxygen implantation, involves oxygen implantation into a silicon wafer using high-energy implanters to form a buried oxide film beneath the surface of the wafer (Fig. 3.8). This technique uses high-energy implanters to implant the oxygen followed by a thermal annealing process to promote oxygen-silicon reactions to form a buried oxide. Implant doses of 1017 to 1018 cm−2 are typically used to implant sufficient oxygen beneath the surface of the wafer. Following implantation the wafer is annealed at very high temperatures, of the order of 1350°C, to promote the formation of a buried silicondioxide film. There have been many developments in this process to improve the quality of the top silicon layer, which can be compromised as a consequence of the high-dose implantation process. Additional developments include implanting at elevated temperatures, to reduce defect densities, post-implantation in-diffusion of oxygen for improved oxide integrity, and interface properties.7,8 2. Wafer bonding and layer transfer.9 The second approach for SOI wafer manufacture involves bonding thin single crystal films of silicon to oxidized substrates as shown in Fig. 3.9. This approach is more flexible as compared to SIMOX as it allows a wider range of thicknesses for the top silicon and dielectric (oxide) layers and also makes possible the use of other dielectrics such as diamond and the potential for using lower-cost substrates besides single crystal silicon. The approach, called the layer transfer process, depends on two key technologies—the ability to bond silicon wafers to each other and the process whereby very thin layers of silicon are separated from a bulk of silicon wafers using a combination of hydrogen implantation to create a two-dimensional layer of microvoids beneath the silicon surface and the subsequent separation of the thin film of silicon (after bonding to a handle wafer) from the bulk of the wafer by thermal shocking or mechanical means. The fundamental problem with SOI wafers is the high manufacturing cost even at high volumes, resulting in very high prices (5X to 10X epitaxial wafers). If wafer prices can be brought down to parity with conventional epi wafers, SOI applications and their uses will proliferate. Manufacturing cost reduction requires new and innovative approaches. In addition, the bonding and layer transfer process lends itself to a large range of new materials combinations. One can combine dissimilar materials on a common silicon substrate to enable combining optical, optoelectronic, digital, analog, and memory functions on a common silicon substrate. Dissimilar materials such as silicon, gallium arsenide, silicon carbide, and indium phosphide can be combined on a common silicon substrate.

High-quality single crystal wafer

O ions Implantation of oxygen and annealing to form a buried oxide layer Silicon Silicon dioxide insulator Silicon FIGURE 3.8 process.

SOI wafer manufacturing based on the SIMOX

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.11

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

High-quality single crystal silicon wafer (oxidized)

H+ ions

3.11

Substrate (handle wafer)

Implantation of hydrogen

Bonding Anneal to delaminate top silicon layer leaving behind thin (~1 to 2µm) single crystal

Delaminated single crystal wafer reused

Single crystal silicon (device layer) bonded to oxidized substrate-SOI wafer

FIGURE 3.9 SOI wafer manufacturing using the layer transfer and wafer bonding approach.

3.4.4 Strained Silicon Performance enhancements, in terms of increased switching speed of transistors have been achieved, to date, by shrinks, i.e., reducing the dimension of the transistor gate so that the distance between the source and the drain of the transistor is made increasingly small. An accompaniment to reduced channel length is a reduction in the thickness of the gate oxide. For sub-100-nm MOSFETs, however, significant short channel effects (the electric field in the channel induced by the gate has to compete with electric fields from the nearby source and drain regions, degrading performance) make further channel length reduction very difficult. Additionally as the gate-oxide thickness is reduced, direct tunneling effects and inversion layer capacitance pose limitations for thinning oxides further. This is currently being addressed by developing high dielectric constant materials that can be used as gate dielectrics and can be thicker than silicon-oxide-based dielectrics. Another approach for achieving higher drive currents and lower operating voltages is to develop processes for enhancing electron and hole mobilities in the channels of the transistors. A technology that is receiving increasing attention is the use of strained silicon for mobility enhancement. It is found that inducing tensile strain along a direction parallel to the surface of the wafer increases both electron and hole mobilities beyond the universal mobility curves, with enhancements in hole mobilities requiring a larger degree of tensile strain in the channel. Hole mobilities may also be increased by introducing compressive strain in the channel.10 One of the approaches for introducing strain into silicon is the use of incommensurate heteroepitaxy of silicon-germanium (Si-Ge) alloys on silicon followed by the growth of thin silicon films on silicon-germanium. Si-Ge has a lattice mismatch with silicon with the result that when a Si-Ge film is grown on the silicon, the Si-Ge layer is strained.11 A graded layer of Si-Ge is grown such that the top region of the Si-Ge film is unstrained but has a different lattice parameter as compared with silicon. When a silicon layer is now grown on the unstrained Si-Ge layer, the resulting silicon is strained with tensile strain along the surface. Tensile strain modifies the band structure with the attendant increase in electron mobility. Electron mobility enhancements from 1.6 to 1.8 have been

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.12

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.12

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

n+ Poly SiO2 n+ drain

Strained Si

n+ source

Relaxed Si 0.7Ge0.3 Relaxed graded Si 1−yGe y layer Y = 0 to 0.3 Si substrate (a)

n+ source

n+ Poly SiO2 Strained Si

n+ drain

Relaxed Si 0.7Ge0.3 Relaxed graded Si 1−y Ge y layer Y = 0 to 0.3 Buried SiO2 Si substrate (b) FIGURE 3.10 Cross-sectional structures of MOSFETs in strained silicon and in strained silicon on oxide.

reported for a Ge content of about 20 percent. Figure. 3.10(a) schematically shows a cross section of a MOSFET with strained silicon channel based on using Si-Ge alloys to induce strain in the silicon. There is also a drive to combine strained silicon wafers with SOI wafers to achieve the advantages of both the technologies.12 Figure 3.10(b) shows strained silicon on SOI structure. Although the use of Si-Ge intermediate layers is one approach to introducing strain in silicon, this represents a wafer-level solution to strain introduction with the incoming wafer already having a strained layer on the surface. Another approach to strain introduction involves the local modification of the silicon surface during wafer processing to selectively introduce strain in the channels of the transistors. Approaches for doing this include the use of thermal-expansion-mismatched films, such as silicon nitride films, on the surface to introduce strain in the channel of the transistors, modification of the shallow trench isolation process as well as the use of silicide films on transistor source/ drain regions for strain introduction. This local strain introduction process, as distinct from the global Si-Ge based approach to strain introduction, has many potential advantages such as more control, during wafer processing, over the process and potentially lower costs. Based on the current state of the technology it is not clear which of these approaches will dominate in future.13,14,15 3.4.5 Novel Approaches for Using Silicon as a Substrate The major advantage of silicon is the availability of high-quality, large-area silicon wafers at reasonable prices. No other semiconductor material approaches the availability, affordability, and feasibility for scaling that silicon does. Consequently an emerging trend is to use silicon as a substrate for other, more-expensive or smaller-area wafers with differing electronic properties. This is not, as discussed in earlier sections, a new trend. Silicon epitaxy, with the top epitaxial layer having a

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.13

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

3.13

different resistivity, or conductivity type from the substrate was the first case of integrating two layers with differing properties. Extensions of this concept have been SOI wafers and strained silicon layers using Si-Ge heteroepitaxy, which involve integrating different materials (e.g., oxides, alloys such as Si-Ge) with silicon. The significant advances in wafer bonding technology have enabled the integration of materials that are not lattice matched with silicon, may exhibit different coefficients of thermal expansion and have no chemical or physical similarities or affinity with silicon. However, for good wafer bonding a few key requirements have to be borne in mind: • The material to be bonded to silicon has to be stable at the bonding temperatures and in subsequent wafer processing operations. • For good bond quality, excellent surface quality, flatness, planarity, and cleanliness of the two materials being bonded are essential. • Frequently the presence of a silicon oxide film between the silicon substrate and the material to be bonded aids in achieving good bonding. • Clearly, bonding is most viable when the two wafers being bonded are of the same diameter. However, with certain materials such as optoelectronic materials this is not currently possible. Materials such as gallium asenide, indium phosphide, indium antimonide cannot be produced as large area wafers since crystal growth technology for these materials is much less well developed as compared to silicon. Consequent attempts at bonding smaller wafers to larger silicon wafers to enable the processing of the composite wafer in conventional silicon wafer fabrication facilities are tentatively being explored. One material of interest, in the context of increased carrier mobility, is germanium. Compared with silicon, germanium has a smaller carrier transport mass and a smaller energy gap. Both these lead to a higher drive current Ion but also a higher off-stage leakage current Ioff. As a consequence of the increased off-stage leakage current, combining germanium with silicon would have to be in an SOI, or GeOI, configuration with an oxide between the top germanium layer and the silicon substrate.9,16 Thermal Issues. An increasing problem with higher density of transistors in advanced logic products is the higher power consumed by such circuits and the higher operating temperatures of such circuits. In particular, high-performance microprocessors have to deal with local hot spots, often called fire ball zones at the core of the circuits. The high local temperatures associated with these regions limit the performance of the products. Consequently means for spreading the heat from the local hot spots, such that the peak temperature approaches the average temperature of the die, are required. A technology that has been proposed to achieve this embeds diamond films, synthesized by CVD techniques, into silicon wafers to fabricate, the wafers called silicon-on-diamond (SOD) wafers. Diamond has the highest thermal conductivity of all known materials and placing a diamond film in close proximity to the transistors in a silicon film on the diamond layer is the most effective way of spreading heat from hot spots and thus enabling higher performance and better reliability. One scheme for fabrication of SOD wafers is described in Ref. 17. Combining diamond with silicon would represent another case of enhancing silicon with other materials.

3.5 KEY ISSUES AND CHALLENGES IN THE MANUFACTURE OF SILICON SUBSTRATES The primary issues and challenges in manufacturing silicon substrates can broadly be divided into the following: 1. In order to keep up with the needs of the technologies for the scaling of silicon, there is a continuing drive to improve wafer quality, with particular references to defects and improved wafer flatness. These are topics of intense interest to the user community, the manufacturers of semiconductor products.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.14

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.14

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

2. The drive toward larger wafer sizes as contemplated by the ITRS. 3. The combining of nonsilicon materials with silicon—SOI wafers being at the forefront of this trend and other technologies/materials such as strained silicon, germanium, and compound semiconductors on silicon—is forming topics of world-wide research. A brief discussion of silicon wafer quality and scaling issues are discussed in the following sections.

3.5.1 Wafer Quality Tremendous progress has been made over the last decade and half in reducing the size and density of particles on silicon wafers. Particles, which are generally foreign material of organic or inorganic origin or due to COPS in the ingots, have tracked with the technology generations. According to the ITRS, the particle size on the wafers is taken to be equal to the technology generation, i.e., the critical dimension of the transistor. For example, the particle size specification on wafers used for leading-edge products today (2004) would be 90 nm since current leading-edge products are manufactured using 90-nm technology. These sizes are expected to be dramatically reduced to keep up with the ITRS. Another wafer parameter of critical importance is wafer flatness. The one that has been emphasized over the years is site flatness. This is the flatness within a specified site, which is the area over which lithography is conducted in a step and repeat lithography tool, on the wafer. Typically a site size of 25 mm by 25 mm is prescribed with a 32-mm by 8-mm site size being specified when more contemporary scanning steppers are used. Site flatness variations on the wafer surface can lead to focus failures in lithography. This parameter addresses surface-height variations of the order of the depth of focus of the lithography tool over spatial wavelengths of tens of mm. A separate and more recent parameter of significance is called nanotopology or nanotopography, which are variations in the local-surface flatness in the tens of nanometers range over distances of 0.5 to 10 mm. These aberrations can cause process and yield issues as a result of two mechanisms. Local variations of flatness can lead to local variations in the thickness of nitride or oxide films after chemical-mechanical polishing. A second impact of small surface height excursions can create local variations in photoresist thickness and focus distance, both of which can lead to critical dimension (CD) variations and attendant shifts in device parameters. An example of nanotopology variation and its impact on post-CMP film thickness uniformity is shown in Fig. 3.11.18

Height (nm) Scale 100 50 0 −50 −100 FIGURE 3.11 Nanometer scale (nanotopology) flatness features on wafers have been shown to affect post-CMP uniformity of dielectrics and control of CD.18

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.15

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

3.15

3.5.2 Wafer Diameter As briefly discussed in the introduction there have been continuing increases in the diameter of silicon wafers and the relevant portion of the ITRS (Fig. 3.12) indicates further increase in diameter to 450 and 675 mm. Moving to a larger wafer size becomes important if the industry is unable to maintain Moore’s law, scaling transistors to half their size roughly every two to three years. In order to reduce costs, the shift to a larger wafer size has tended to make up for gradual slippages in the ability to move to a new process generation every two years. Depending on whether or not the two-year cycle can be maintained, it is claimed that the 450-mm diameter wafers may be needed in about 10 years. There are formidable problems in scaling silicon crystals from the current 300- to 450-mm diameter, to say nothing of 675 mm. The key challenges, briefly, are: • As the diameter of the crystal is increased, the achievable growth rate drops significantly. For example, 300 mm crystal growth rates are about half that of 200 mm crystals. This is a consequence of the increasing difficulty of extracting heat from the solid-liquid interface during crystal growth as diameter increases. The higher heat loads, as a result of the need to melt much higher volumes of silicon and the greater distance that heat has to travel from the center of the growing ingot to the surface reduces the rate of heat removal which, in turn, reduces growth or pull rate. This leads to much more expensive crystals and 450 mm ingots may not be cost effective from this perspective alone. • Large melt volumes are more difficult to manage with increased convection currents leading to instabilities. The large thermal budgets also lead to increased thermal time constants making process control more difficult. System response to changing power input slows down with larger melt volumes. • A formidable problem relates to the manufacture and cost of large quartz crucibles. Quartz or silica crucible diameters have been scaled from 22 to 24 in for 200 mm ingots to 32 to 36 in for 300 mm ingots. If this scaling continues for 450 mm ingots, crucible diameters can be as large as 54 in. in diameter. Whether such large crucibles can be manufactured and if so would they be cost effective are the questions that need to be addressed. • Crucible life is another parameter that has an important impact on affordability. As a result of the larger melt volumes, the higher energy inputs, increased convection currents, and radial temperature gradients crucible corrosion is expected to be much higher for 450 mm ingot growth as compared to the smaller ingots. Increased crucible corrosion will limit the length of ingot that can be grown. This coupled with the much higher expected costs of crucibles again impacts cost adversely. • The larger ingots will be considerably heavier. Consequently thin seed crystals cannot support the increased weight. New and innovative approaches for dealing with heavy crystals have to be developed.

First year of IC production

1999

Wafer diameter

200 mm 300 mm

2002

2005

2008

2011

2014

300 mm

450 mm

450 mm

450 mm 675 mm

Research required

FIGURE 3.12

Development underway

Qualification/production

ITRS projections for wafer diameter.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH03.qxd

04/04/2005

19:34

Page 3.16

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.16

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

3.6 CONCLUSIONS In this brief review on semiconductor substrates, a discussion of silicon substrates and the multitude of variations, which are being developed, based on silicon was presented. This is a very large subject and it has not been the intent of this chapter to exhaustively review all aspects of semiconductor substrates. With silicon and its variants being the preeminent materials for semiconductor manufacture the emphasis has been on this material. It is clear that the desirable properties of silicon, its ready availability in quantity and the existence of a mature manufacturing base make it the desirable substrate for other, less mature or more expensive substrates. Consequently the indirect use of silicon as a substrate is perhaps just as significant as the direct use of silicon for semiconductor devices and circuit manufacture. The opportunities for exploiting this material further are almost limitless.

REFERENCES 1. International Technology Roadmap for Semiconductors, http://public.itrs.net. 2. Y. Matsushita et al., “Semiconductor Silicon,” Proceedings of the Eight International Symposium on Silicon Materials Science and Technology, The Electrochemical Society, Pennington, NJ, 1998. 3. M. Aminzadeh et al., IEEE Trans. Semi. Manuf., Vol. 15, No. 4, p. 486, 2002. 4. G. K. Celler and S. Cristoloveanu, J. Appl. Phys., Vol. 93, No. 9, p. 1, 2003. 5. Proceedings of the International Symposium on Silicon on Insulator Technology and Devices XI, The Electrochemical Society, Pennington, NJ, Vol. 2003–2005, 2003. 6. K. Izumi, Vacuum, Vol. 42, p. 333, 1991. 7. S. Krause, M. Anc, and R. Roitman, MRS Bull., Vol. 23, No. 12, p. 25, 1998. 8. D. Hill, P. Fraundorf, and G. Fraundorf, J. Appl. Phys., Vol. 63, p. 4933, 1988. 9. C. Mazure, Proceedings of the International Symposium on Silicon on Insulator Technology and Devices XI, The Electrochemical Society, Pennington, NJ, Vol. 2003–2005. 10. G. E. Pikus and G. L. Bir, Symmetry and Strain-Induced Effects in Semiconductors, New York: Wiley, 1974. 11. H. R. Huff and P. M. Zeitzoff, “SOI Wafers: Fabrication Techniques and Trends, Solid State Technol.,” p. 63, Oct 2004. 12. T. A. Langdo et al., Appl. Phys. Lett, Vol. 82, p. 4256, 2003. 13. A. Shimizu et al., “Local Mechanical Stress Control: A New Technique for CMOS Performance Inhancement,” IEDM, Vol. 26, p. 433, 2001. 14. S. Itro et al., “Mechanical Stress Effect of Etch Stop Nitride and its Impact on Deep Submicron Transistor Design,” IEDM, Vol. 25, p. 247, 2000. 15. S. Thompson et al., IEEE Electr. Device L., Vol. 25, No. 4, p. 191, 2004. 16. A. Ritenour et al., The Electrochemical Society, PV 2004-01, Vol. 406, 2004. 17. K. V. Ravi and M. I. Landstrass, Proceedings of the First International Symposium on Diamond and Diamond-Like Films, The Electrochemical Society, Pennington, NJ, Vol. 89–12, p. 24, 1989. 18. K. V. Ravi, “Wafer Flatness Requirements for Future Technologies,” Future Fab Intl., Vol. 207, p. 7, 1999.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 4

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY Hazara S. Rathore Kaushik Chanda IBM Hopewell Junction, New York

4.1 INTRODUCTION Interconnects or wiring systems distribute clock and other signals and provide power/ground to various systems on a chip. One of the figures of merit for a high-performing interconnect system is its RC time delay. As geometries shrink in accordance with Moore’s law, this factor has become a bottleneck in achieving high-speed transmission for advanced microprocessors. Figure 4.1 shows the increasing dominance of wiring delay versus gate delay with scaling. The 1994 National Technology Roadmap for Semiconductors (NTRS) described the first needs for new conductor and dielectric materials that would be necessary to meet the projected overall technology requirements. A lower resistivity material in conjunction with a lower dielectric constant insulator was required to reduce the capacitive load of interconnects. Copper replaced aluminum as an interconnect material of choice due to its lower resistivity and capacitance reduction by scaling of 1x level heights.1 Copper integration required several modifications to the existing aluminum technology. New process steps like “damascene,” electrochemical deposition, and chemical mechanical polishing (CMP) were introduced. In addition, process elements like liners, hardmasks, seed layers, and caps were necessary for the integration scheme. Reliability concerns with copper and its interaction with the surrounding dielectric became an integral part of most technology qualifications. Section 4.2 briefly describes the copper interconnect technology. It discusses the advantages and limitations, along with the integration complexities. Several materials, both organic and inorganic based, are being evaluated to replace the traditional back end-of-line (BEOL) SiO2 as dielectric. This choice of the dielectric material depends on several factors. Electrical properties such as dielectric constant, intrinsic leakage, breakdown field, and physical properties like stability, moisture absorption, bulk modulus, and coefficient of thermal expansion are critical to making the choice. The material’s integration with copper and their reliability are vital to the success of such an advanced interconnect scheme. For example, mismatch in the mechanical properties of copper and low-k dielectrics can lead to reliability concerns like stress voiding, thermal fatigue, and chip package interactions. Poor thermal conductivity of the surrounding dielectric has become a factor in determining the allowable current densities through copper lines. Also, with the introduction of hardmasks and caps (higher dielectric constant materials), the effective dielectric constant of the whole stack instead of the bulk dielectric constant of the material

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

4.1

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.2

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY 4.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

2.5

Delay time (×10−9 sec)

2.0 Interconnect delay (RC) 1.5

1.0 Intrinsic gate delay 0.5

0

0

FIGURE 4.1

0.5

1.0

1.5 2.0 Feature size (µm)

2.5

3.0

3.5

Effect of interconnect scaling.

has become the metric of performance. Section 4.3 discusses low-κ dielectrics. It also addresses the issues concerning integration of copper with low-k dielectrics, which has been quite a challenge for the industry. Section 4.4 delves into the reliability of copper/low-k interconnects. Typical reliability stresses like time-dependent dielectric breakdown (TDDB), electromigration (EM), stress voiding, thermal fatigue, and chip package interactions (CPIs) are described. Factors affecting these reliability mechanisms are discussed.

4.2 COPPER INTERCONNECT TECHNOLOGY Continual scaling has led to the dominance of interconnect delay over gate delay. There have been efforts to reduce both the resistive and capacitive components of the RC time constant. Copper has been chosen as the interconnect material to replace aluminum because of its lower resistivity. It also brought about reduction in parasitic capacitance by allowing scaling of 1x level heights. Figure 4.2 shows the comparison of sheet resistivity of different metals. A new method was developed to deposit copper interconnects.3 Figure 4.3 shows a typical process flow used in this new method called damascene.2 The word originates from Damascus, a place in Syria, where ancient jewelers used a similar method to deposit precious metals for ornamental purposes. In this process, the dielectric instead of the metal is patterned first. This “mold” is coated with liner and seed layers, to protect copper and facilitate its deposition respectively. Copper is electrochemically deposited to fill up the trenches and holes. Excess metal is removed by a polishing step—CMP. Finally the surface is capped with a dielectric to protect the copper. There are two kinds of damascene processes—single and dual. In the single-damascene case, line processing begins after the vias have been completed. In the dual-damascene process, both the via and line are filled with copper in a single step. Copper damascene technology introduced new process elements in the integration scheme. Copper is known to diffuse into the surrounding dielectric under bias and high temperature.5 Figure 4.4 shows the diffusivity of various impurities in silicon as a function of temperature.6

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.3

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY COPPER, LOW-κ DIELECTRICS, AND THEIR RELIABILITY

4.3

Resistivity (µΩ-cm) 8

6

5.6

5.5

Mo

W

4 2.7

2.4

2

0

1.7

1.6

Al

FIGURE 4.2

Ag

Au

Cu

Resistivity of different metallizations.

Here one can see the higher diffusivity of copper compared to aluminum. It is also susceptible to corrosion. Hence interconnects have to be encapsulated by diffusion barriers on the base and side walls along with capping layers on top. Different materials have been researched as potential diffusion barriers for copper metallization.4,7,8,9 Typically refractory metal alloys have proven to be good barriers against copper diffusion. Materials like Ta/TaN, TiN, TiSiN, and TiW can be used for this purpose. Certain qualities are desired of a good liner material. Besides being a diffusion barrier, it should have

Elch slop (silicon nitride)

(a)

Via

Line Insulator Via

(b)

(c) Barrier

Seed layer (d)

Plated metal

(e)

FIGURE 4.3 Process steps for the fabrication of a via and line level by the dual-damascene approach.2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.4

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Temperature (°C) 1400 10−3

1300

1200

1100

1000

900

Cu 10−4

Li Au(I)

10−5 He 10−6

K

Au(I-S) H

Fe Na

S

10−7 Ni Diffusivity (cm2/s)

4.4

Au(I-S) +VI

Ag

10−8

Zn

O 10−9 C 10−10 10−11

Al Bi

Ga As

10−12

B Sn In.Ti

10−13

10−15

FIGURE 4.4

Ge

Sn

10−14

P

Sn 0.6

0.7 1000/ T (1/ K)

0.8

Diffusivity of various impurities in silicon as a function of temperature.4

physical and chemical stability. It should adhere well to both copper and the dielectric. Its deposition should be highly conformal so that adequate coverage is achieved in high aspect ratio structures. Figure 4.5 lists the attributes of a good liner and compares different materials as potential liner candidates.10 Missing liners is one of the major reliability concerns with copper metallization. It can lead to pinhole defects in via/line structures and thus potential electromigration and stress voiding problems. It can cause copper to leak out and short to adjacent metal structures during TDDB stress. High resistivity is one of the serious drawbacks of liners that add to the line resistance by usurping copper cross-section area. To keep the line resistivity low and maintain copper’s advantage, thickness should also be minimized without compromising the liner’s functionality. Electroplating is currently the preferred method of depositing thick copper films in dual-damascene architecture. This process requires the presence of a copper seed layer that serves as the cathode on

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.5

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY COPPER, LOW-κ DIELECTRICS, AND THEIR RELIABILITY

Attribute Cu barrier Adhesion to ILD Cu on liner adh. Liner on Cu adh. Low in-plane R Cu poisoning CMP Single chamber Via, contact R Contact-R Cu corrosion Thermal stability Stress, cracking Step coverage Final

Cr X

TiN

β-Ta TaN/Ta TaSiN WNx X

X ? X ?

X

X ? X X

X ? ?

X

X X

X ?

?/X ? X ?

X X

? ? X ? X

X

X


= CVD available, FIGURE 4.5

TiN/Ti Ti/TiN TiN/Ta TaN

4.5

X

?

X X

X X

X

X

? ? ?

X

X

= Ionized-PVD available,

X

X

X

? = not investigated

Attributes of an optimal liner and comparison of different potential candidates.

which copper ions from the electroplating bath are deposited. Like liners, conformality of this layer in high aspect ratio features is essential. A discontinuous layer results in pinholes and voids in the metals that cause yield and reliability problems. Physical vapor deposition (PVD) process is used for deposition. The ratio of seed copper and electroplated copper can influence electromigration performance of the interconnect. A capping layer is required to protect the copper surface post-CMP. This layer acts as an etchstop layer for the next damascene level. It also prevents interlevel copper diffusion. Typically silicon nitrides or nitrogen-doped silicon carbides are used for this purpose. One of the big disadvantages of this layer is its high dielectric constant. This adds to the overall dielectric constant of the stack and undermines the effect of low-k dielectric. The cap/copper interface is also critical from an electromigration viewpoint. Several deposition techniques have been investigated for filling up vias and trenches in copper dual damascene technology. The physical vapor deposition of copper has some limitations, especially lack of good step coverage in high aspect ratio features. Low throughput of the process makes it undesirable from manufacturing point of view. Chemical vapor deposition (CVD) is another technique used to deposit metals. Although several people have shown the feasibility of depositing copper using the CVD process, its reliability has been found to be inferior to the other processes.10 The semiconductor industry has adopted the electroplating process for depositing single or dual damascene copper films. When the electroplating process is well controlled, the deposited copper film fills high aspect ratio vias and trenches without voids or seams. Electroplating also produces copper films with greater electromigration resistance at a lower cost of ownership than can currently be produced with PVD or CVD. A seed layer is required to act as a cathode for the reduction of copper ions from the electroplating bath. Bath chemistry is critical in this procedure. There are different chemical agents called levelers, suppressors, and accelerators that are added to the electroplating bath to ensure a “bottom-up” filling of the trenches. This avoids the “pinch-off” problems and gets rid of seams in the metal that can later cause yield and reliability problems. There has been some focus on atomic layer deposition (ALD) of liners and seeds, especially for and beyond 65 nm nodes.11, 12 ALD is a surface-controlled layer-by-layer process for the deposition of thin films with atomic layer accuracy. Each atomic layer formed in the sequential process is a result of saturated surface-controlled chemical reactions. The self-controlled growth mode of

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.6

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY 4.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

ALCVD contributes several advantages. The thickness of the films can be controlled in a straightforward manner by controlling the number of reaction cycles, therefore enabling the controlled growth of ultrathin layers. New seedless techniques have also been developed. Metals like ruthenium and rhodium can be used both as a diffusion barrier and seed layer for copper metallization.13 Chemical mechanical polishing is done to remove the copper overburden post-electrochemical deposition and to achieve planarization. In this method the wafer is mechanically abraded in a slurry containing abrasives and etching agents. The process combines chemical reactions and mechanical forces to selectively remove unwanted material. In addition to copper, liners are also removed using this method. Tools have been developed to remove both copper and liners in the same process module, thus increasing the throughput. Across wafer uniformity, pattern factor sensitivity and chemical (corrosion, copper and liner residuals, particulates, moisture absorption) and mechanical (delaminating, peeling, and cracking) damage to the surface are some of the key issues associated with this methodology. They can impact both yield and reliability of the product. Advanced solutions like e-CMP (similar to electropolishing) with low down force have been introduced. Such solutions are required especially for technologies with finer line geometries and mechanically weak low-k dielectrics.14 Often integration routes use a permanent hardmask to protect the dielectric surface during CMP. It has been shown that the CMP slurry can damage the surface of the dielectric leading to high line to line leakage. This also adds to the effective dielectric constant and reduces the performance. Silicon nitride and oxide-based materials are typically used for this purpose.

4.3 LOW-k DIELECTRICS TECHNOLOGY The capacitive component of the RC delay can be reduced by incorporating lower dielectric constant (low-k) insulators in the back end. The ratio of the increased capacitance to the vacuum capacitance due to polarization of the dielectric is known as the dielectric constant. Polarization at the molecular level is made up of three components—electronic, atomic, and orientational. Electronic polarization is due to the displacement of the electron cloud with respect to the positive nucleus under an external electric field. It can react to very high frequencies and is responsible for the refraction of light. Atomic polarization is due to the distortion of the atomic nuclei arrangement in a molecule or a lattice. This movement of heavy nuclei is more sluggish than electrons so that atomic polarization cannot occur at as high frequencies as electronic polarization. Hence typically it is not observed above infrared frequencies. If the molecules of the material already possess a permanent dipole moment, there is a tendency for these to be aligned by the applied field to give a net polarization in that direction. This gives rise to orientational polarization. This component can make a large contribution to the total polarization in an applied field but may be slow to develop. Although copper containing chips were introduced in 1998 with silicon dioxide insulators, the lowering of insulator dielectric constant predicted by International Technology Roadmap for Semiconductors (ITRS) has been problematic. Several chemistries were evaluated to find the low-k solution for interconnect technology. Oxide-based dielectrics like fluorosilicate glass (FSG) and fluorine-doped tetra-ethyl-ortho silicate (FTEOS) were among the first set of materials studied for low-k solutions.15 The introduction of FSG (k = 3.7) at the 180-nm technology node in conjunction with the copper dual-damascene process represented the first major break in the historical extension of silicon dioxide (k = 4.1). Fluorine being the highest electronegative element reduces the electronic polarization and thus achieves lower dielectric constant. Issues like fluorine mobility, reactivity with refractory metal-based liners, and adhesion and moisture sensitivity had to be resolved before it could become a manufacturing process. Noguchi et al. have shown the degradation of TDDB life with increasing delay between CMP and cap deposition.16 FTEOS is another form of fluorine-doped oxide that is being used as the back-end dielectric. Materials like organosilicate glass (OSG) and carbon doped oxide (SiCOH) offer k values in the range of 2.9 to 3.2. Several polymers with k values between 2.5 and 2.9 can also be used as low-k dielectrics. SiLK,17 methyl silsesquioxane (MSQ) and hydrogen silsesquioxane (HSQ) are some polymer-based low-k dielectrics. Ultra-low-k dielectrics

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.7

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY COPPER, LOW-κ DIELECTRICS, AND THEIR RELIABILITY

Material

Undoped plasma SiO2 (PECVD SiO2, SiH4-based or TEOS-based HDP, BPSG, PPSG,...) Carbon doped PECVD SiO2 Flowable oxide Spin-on glass Porous SiO2 Polyimide Polyimide siloxane Polysilsesquioxane (Si polymer) Benzocyclobutene (BCB) Parylene N Fluorinated polyimide Poly (Olefins) Parylene F Polynaphthalene Amorphous teflon Polymer foams Aerogels Air

FIGURE 4.6

Dielectric Constant 3.9−4.5

Deposition Method PECVD

2.0−3.3 ~3.5 2.8−3.0 <2.0 3.0−3.7 2.6−2.7 2.7−3.0 2.5−2.7 2.6−2.7 ~2.5 2.4−2.6 2.3−2.4 ~2.3 1.9−2.1 <2.0−3.0 1.1−2.0 1.0

PECVD Spin-on Spin-on Spin-on Spin-on Spin-on Spin-on Spin-on PECVD Spin-on Spin-on PECVD PECVD Spin-on Spin-on Spin-on

4.7

Different low-κ materials for advanced metallization schemes.18

are materials with κ values below 2.2. One of the popular techniques to lower the dielectric constant is the introduction of pores. Integration of such porous dielectrics is a daunting task. Even air gaps (k around 1) are being studied to achieve the ultimate low-k solution. Figure 4.6 gives a list of low-k dielectrics along with their dielectric constants and methods of deposition.18 Besides a lower dielectric constant, a low-k dielectric has several other properties. It should have low leakage, low charge trapping, low dissipation, and high dielectric strength. High glass transition temperature, low thermal coefficient of expansion, high tensile strength and modulus, low stress, low shrinkage, and high crack resistance are also required. From integration point of view, it should have very low outgassing, high solvent resistance, low contamination, high etch selectivity, low gas permeability, and CMP process stability. There are mainly two methods of dielectric deposition—plasma-enhanced chemical vapor deposition (PECVD) and spin-on. Most of the organic-based dielectrics are deposited by the spin-on method. The dielectric solution is spun at a specified rate to form a coating. The wafer is then baked at high temperatures to remove the solvent and form a thin film. Ultrathin films are used to improve the adhesion between the lower metal level cap and the dielectric. This prevents delamination during subsequent process steps like CMP. The spin-on technique provides an important advantage of reduced topography. Glass transition temperature (Tg) is one of the most important parameters that define the properties and behavior of organic dielectrics. Below Tg the polymer is hard and glassy and above Tg the polymer has sufficient viscoelasticity. Questions like dependence of Tg on film thickness and its variation with topography (gap fill versus free standing film) are crucial to implementing polymers as back-end dielectric. Loke et al.20 have studied the interaction of copper with polymers. Most of the inorganic dielectrics are deposited by the PECVD method. The choice of the precursors for the PECVD reaction determines the chemistry of the final dielectric layer.21 Integration of copper and low-k dielectrics has been a significant challenge for the whole industry.19,22,23 Figure 4.7 shows SEM section of a 10 Cu level microprocessor. All 1x and 2x levels are Cu in low-k SiCOH. Dual 6x levels are Cu in FTEOS. W local interconnects (M0) and Al terminal metal levels are included. Decreasing the dielectric constant often leads to reduced mechanical strength of the dielectric, bringing in new planarization challenges. These bring new planarization

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.8

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY 4.8

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

(a)

(b)

FIGURE 4.7 SEM sections of a 10-Cu-level microprocessor. All 1x and 2x levels are Cu in low-κ SiCOH. Dual 6x levels are Cu in FTEOS. W local interconnects (M0) and Al terminal metal levels are included.19

challenges to the table. Among these is the need to reduce the mechanical forces applied to the wafer during CMP, to prevent adhesive or cohesive failures in the dielectric. Future tools are being designed for processing copper in low-k and ultra-low-k dielectrics in a low shear-force region of the CMP space. Dielectric surface damage is another area of concern during planarization. The damage can be both chemical and mechanical. Care should be taken to ensure that CMP slurry components do not attack the surface. Also, these materials tend to absorb a lot of moisture, but some are strongly hydrophobic. This is true especially for porous low-k dielectrics. Factors like pore size, pore shape, and degree of interconnectivity are being looked into to inhibit dielectric degradation. Defectfree hardmasks are typically used to isolate the dielectric surface during processing. This relatively higher dielectric constant film assists in patterning of the dual-damascene structure and acts as a highly selective CMP stop layer. In addition, this layer prevents detrimental interactions between low-k dielectrics and photoresists.

4.4 COPPER/LOW-k DIELECTRICS RELIABILITY The rapid changes in interconnect materials and structures have resulted in new challenges for the reliability community. The industry’s move to copper metallization allows improvements in interconnect current-carrying capacity and high-temperature operation, but has resulted in numerous new material integration and reliability issues. These problems are further exacerbated by increasing interconnect density. The integration of new low-k dielectrics needed for performance enhancement brings numerous reliability concerns that include thermally or mechanically induced cracking or adhesion loss, poor mechanical strength, moisture absorption, and poor thermal conductivity. Most development activities now incorporate detailed reliability evaluations to ensure long product life. Copper has been known to diffuse into dielectrics under the influence of bias and temperature. Hence it is encapsulated with refractory metal/metal alloys diffusion barriers to prevent electrical leakage between lines. The top surface is capped to prevent interlayer problems. TDDB stresses are designed to study this potential reliability concern. A set of fully integrated parallel metal lines makes up a typical test structure. These lines are put under bias and high temperature. Leakage current between the lines is monitored over a period of time. Usually the failure criterion is defined as a sudden jump in this leakage, indicating metallic short or the breakdown of the dielectric. Multiple structures from different wafers and lots can be put up on stress to generate a failure statistics.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:36

Page 4.9

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY COPPER, LOW-κ DIELECTRICS, AND THEIR RELIABILITY

4.9

Product lifetime can be estimated from this data. TDDB fails can also be induced by process defects. Missing liner at the bottom of the trench, CMP residuals between the lines, and chemically or mechanically damaged copper surface can lead to fails during stress. Thus TDDB helps in assessing process stability of the manufacturing line. Electromigration can lead to considerable material transport in metals. It is the migration of metal atoms in a high current density carrying line, due to momentum transfer from conducting electrons. A phenomenological description of the electromigration process is Black’s equation MTF = A J−n exp[−E/kT] where MTF = median time to failure J = current density n = current exponent E = activation energy A = a constant and E depends on the diffusivity of the metal atom. Multiple samples are stressed at high current densities and high temperatures. A structure is considered a fail if its resistance shifts by a predetermined amount. The fail times have been found to be lognormally distributed. Based on Black’s equation and lognormal statistics, the lifetime of an interconnect at typical use conditions can be calculated. Usually a target current density is desired by the designers. In that case, a failure rate is defined first before calculating the current density. Figure 4.8 shows the improvement in electromigration lifetime due to copper interconnects.1 Electromigration leads to increase in line resistance (or even opens) due to void formation during stress. These voids typically nucleate at regions of flux divergence. Two modes of electromigration— line depletion and via depletion—are studied for copper interconnects. The via depletion mode looks at dual-damascene structures. Here the electron flow goes from the via to the line. The bottom of the via can act as a flux divergence region and thus can cause void nucleation. In the line depletion mode, the electron flow occurs from the via at a higher level to the line in the adjacent lower level. Again, flux divergence occurs near the bottom of the via.

99.9 99 +

95 90 Percentile

Geng(SMH)_CH04.qxd

75 AI(Cu) t60 = 1.31 h

50 25

Cu t50 = 147.7 h

10 5 >110X 1 J = 2.5 E = 6 A/cm2 Temp = 295°C

0.1 0.01 0.1

FIGURE 4.8

1

10 100 Stress time (hours)

1000

10000

Electromigration lifetime improvement due to copper interconnects.1

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.10

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

T (°C) 441

352

282

227

181

103 103 102 n = −1.1 ± 0.2

102

t 50(h)

t 50(h)

4.10

101 100

n = −4.8

101

T = 314°C 2

10 1 (mA)

Cu (present work) Cu (Ref. 3) Al(Cu) (Ref. 3)

10−1

50

Log-log plot of lifetime (t 50) vs. current (I )

10−2 14

16

18

20

22

1/T (K−1104) Log t50vs. I /T for Cu and Al(Cu). The straight lines are least-squares fits

FIGURE 4.9 Electromigration kinetic parameters of copper interconnects.26

The diffusion of copper can occur through bulk, grain boundaries, or surface. The bulk diffusivity of copper is low compared to the other two interfaces. Narrow copper lines usually have bamboolike grain structures. Hence the major mode of copper transport is through the interfaces. Electromigration results have been found to be influenced by the nature of these interfaces. Lloyd et al.24 have shown the correlation between adhesion energy and electromigration activation energy. Copper/cap interface has been found to be the most critical interface.25 Most of the transport occurs at this place. Activation energies ranging from 0.9 to 1.2 eV have been observed for copper electromigration, depending on linewidth/integration an the like. Figure 4.9 shows the electromigration kinetic parameters for copper interconnects.26 Hu et al.27 have shown that the use of metallic cap like cobalt tungsten phosphide (CoWP) can significantly improve the electromigration life as it inhibits copper diffusion along the surface. Electromigration can also lead to extrusion fails. As the void grows, the diffusing atoms start accumulating at the other end. This leads to a stress gradient. If the compressive stress at the anode end is high, it can cause copper to extrude. Hence typical electromigration test structures have extrusion monitors built into them. The evolution of the stress gradient can counterbalance the depletion of atoms for short lines.28 This effect is known as the short length effect in which interconnects smaller than this critical length can have immortal life. Design manuals typically exploit this feature to increase the use of current densities for short lines. This model also includes the bulk modulus of the surrounding dielectric. With the advent of low-k dielectrics with lower bulk modulus, shortlength rules need to be revised for each technology node. Copper, unlike aluminum, lacks a self-passivating oxide. Reliability stresses are designed to evaluate the robustness of the interconnect scheme against oxidation. This is especially important in the case of low-k dielectrics due to their high moisture absorption. Edge seals are used around chips to prevent moisture ingress. The final passivation layer above low-k stack also provides this protection. Samples with compromised edge seals can be stressed under high temperature to determine the oxidation rate. Electromigration structures can be monitored for resistance shift to determine fails. The integrity of liners and caps plays a vital role in protecting the copper. Low-k dielectrics suffer from poor thermal conductivity. This can lead to local joule heating of interconnects due to high current densities. The effective thermal conductivity of an interconnect system should be taken into consideration before calculating the design limits for current densities.29

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:36

Page 4.11

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY COPPER, LOW-κ DIELECTRICS, AND THEIR RELIABILITY

4.11

Stress voiding is another reliability concern for copper/low-κ interconnect systems. Due to the mismatch in the thermal expansion coefficient, the interconnect’s final state is tensile. To relieve this stress, vacancies can migrate to lower stress regions (surface, grain boundaries) and coalesce to form voids. Over a period of time, this can lead to an increase in resistance. In case of wide lines a stress gradient causes vacancy flow to the via and subsequent voiding.30 Structures like isolated vias on large metal plates can be used to determine the reliability. Sullivan et al.31 have derived an expression of atomic flux by considering the effect of stress on the equilibrium vacancy concentration. The failure rate versus temperature curves exhibit maxima. At low temperatures, the stress is high but the diffusivity is low. At higher temperatures, the condition is reversed. Hence a range of temperatures is chosen to evaluate this mechanism. This phenomenon has also been found to depend on different process variables. Thermal cycling is done to simulate the stresses generated on interconnects during processing due to coefficient of thermal expansion (CTE) mismatch between metal and dielectric and assess reliability. Stacked via structures are vulnerable to this failure mechanism. Other structures like isolated vias and via chains are also investigated. A structure is flagged as fail if its resistance shifts by a predetermined amount. The stressing involves cycling from a low to a high temperature. Filippi et al.32 have showed that failure rates are dependent on both the temperature range and the maximum temperature (see Fig 4.10). Joint electron device engineering council (JEDEC) recommends no fails after 500 cycles ranging from −65 to 150°C or 1000 cycles from −55 to 125°C for reliability success. The stress is done at the wafer level. Organic low-k dielectrics have very high coefficient of thermal expansion. In case of stacked structures, the vias are pinned and the cycling induces stresses. This can lead to crack initiation and growth due to fatigue of copper. Design improvements can sometimes offset the effect of CTE mismatch. The lessened mechanical strength of low-k dielectric and higher temperature of operation of copper interconnects have driven the need for novel packaging techniques and structures. These combined with the move to higher packaging process temperatures needed to accommodate lead-free solders provides new reliability challenges. There are four major functions of a package—power distribution, signal distribution, heat dissipation, and circuit protection. Chip package interaction

99.99 99.9 99.5 99 98 95 90 Cumulative %

Geng(SMH)_CH04.qxd

80 70 60 50 40 30 20

∆T = 295°C

Tmax = 150°C

∆T = 255°C ∆T = 215°C ∆T = 185°C ∆T = 150°C Bimodal fits Linear fit

10 5 2 1 0.5 0.1 0.01 10 FIGURE 4.10

100

1000 Cycles to failure

10000

A lognormal CDF plot of failures during thermal cycle stress of copper/low-κ.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.12

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY 4.12

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

evaluates the effect of package on the reliability of the chip. The objective is to determine whether a particular packaging scheme has any adverse effect on the chip’s functionality. Several kinds of structures are monitored while modules (chips with their packages) are subjected to stress. JEDEC defines a set of standardized tests to determine this reliability for different kinds of packages like organic, C4, and ceramic. Test structures on the chip are monitored for resistance shifts and leakages. The stresses are similar to those done at the chip level. High-temperature storage, hermiticity of the package under temperature, humidity, bias, and thermal cycling are kinds of stresses done to evaluate the reliability. Landers et al.33 have discussed the CPI results of the 90-nm CVD low-k SiCOH technology. The introduction of copper and low-k dielectrics has been an incredible challenge to the semiconductor industry. New materials and integration schemes had to be devised to implement this novel technology. And with the industry trying to keep up with Moore’s law, more collaboration among design, development, and manufacturing teams is the need of the hour.

REFERENCES 1. D. Edelstein et al., “Full-Copper Wiring in Sub-0.25 um CMOS ULSI Technology,” Proceedings of the IEEE International Electron Devices Meeting, pp. 773–776, IEEE, Piscataway, NJ, 1997. 2. C. K. Hu et al., “Copper Interconnections and Reliability,” Mater. Chem. Phys., Vol. 52, p. 5, 1998. 3. C. W. Kaanta et al., “Dual damascene: A ULSI wiring technology,” Proceedings of 8th International IEEE VLSI Multilevel Interconnection Conference, pp. 144–152, IEEE, New York, 1991. 4. J. M. Harris et al., “Studies on the Al2O3–Ti–Mo–Au metallization system,” J. Vac. Sci. Technol., Vol. 12, No. 1, pp. 524–527, 1975. 5. J. D. McBrayer et al., “Diffusion of metals in silicon dioxide,” J. Electrocem. Soc., Vol. 133, No. 6, pp. 1242– 1246, June 1986. 6. J. Cho, “Process Integration Issues of Copper Interconnections for ULSI,” Doctoral Dissertation, Stanford University, 1994. 7. B. Arcot et al., “Interactions of copper with interlayer dielectrics and adhesion promoters/diffusion barriers,” MRS Proc., Vol. 203, p. 27, 1991. 8. M. A. Nicolet, “Diffusion barriers in thin films,” Thin Solid Films, Vol. 52, No. 3, pp. 415–443, August 1978. 9. D. Edelstein et al., “An optimal liner of copper damascene interconnects,” Proceedings of the Advanced Metallization Conference 2001,” Materials Research Society, pp. 541–547, October 2001. 10. H. Rathore et al., “Reliability of copper metallization for CMOS ULSI technologies,” Interconnect and Contact Metallization for ULSI, Proceedings of the International Symposium (Electrochemical Society Proceedings Vol. 99–131), pp. 190–197, Electrochemical Society, Pennington, NJ, 2000. 11. K. Higashi et al., “Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45 nm-node copper dualdamascene interconnects,” Proceedings of the 2004 International Interconnect Technology Conference, pp. 6–8, IEEE, Piscataway, NJ, 2004. 12. J. W. Hong et al., “Characteristics of PAALD-TaN thin films derived from TAIMATA precursor for copper metallization,” Proceedings of the 2004 International Interconnect Technology Conference, pp. 9–11, IEEE, Piscataway, NJ, 2004. 13. M. Lane et al., “Liner materials for direct electrodeposition of copper,” Appl. Phys. Lett., Vol. 83, No. 12, pp. 2330–2332, September 2003. 14. M. Tsujimura et al., “General principle of planarization governing CMP, ECP, ECMP & CE—low down force planarization technologies,” 2004 Proceedings of VLSI Multilevel Interconnection Conference, Institute for Microelectronics Interconnections, p. 267. See also www.imic.org, Institute for Microelectronics Interconnections on Chip. 15. E. Barth et al., “Integration of copper and fluorosilicate glass for 0.18 mu m interconnections,” Proceedings of the 2000 International Interconnect Technology Conference, pp. 219–221, IEEE, Piscatawy, NJ, 2000. 16. J. Noguchi et al., “Impact of low-κ dielectrics and barrier metals on TDDB lifetime of Cu interconnects,” International Reliability Physics Symposium Proceedings, p. 355, IEEE, Piscataway, NJ, 2001.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.13

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY COPPER, LOW-κ DIELECTRICS, AND THEIR RELIABILITY

4.13

17. Trademark of Dow Chemical. 18. S. P. Jeng et al., “Process integration and manufacturability issues for high performance multilevel interconnect,” Advanced Metallization for Devices and Circuits—Science, Technology and Manufacturability Symposium, pp. 25–31, 1994. 19. D. Edelstein et al., “Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology,” Proceedings of the 2004 International Interconnect Technology Conference, pp. 214–216, IEEE, Piscataway, NJ, 2004. 20. A. Loke et al., “Kinetics of copper drift in low-kappa polymer interlevel dielectrics,” IEEE Trans. of Elec. Dev., Vol. 46, No. 11, pp. 2178–2187, November 1999. 21. A. Grill et al., “SiCOH dielectrics: From low-kappa to ultralow-kappa by PECVD,” Proceedings of Advanced Metallization Conference 2001, Materials Research Society, pp. 253–259, 2001. 22. L. Clevenger et al., “90 nm SiCOH technology in 300 mm manufacturing,” Advanced Metallization Conference, Materials Research Society, 2004. 23. H. Rathore et al., “Reliability of Copper Interconnects with CVD Low-κ BEOL Dielectric,” 2004 Proceedings of VLSI Multilevel Interconnection Conference, Institute for Microelectronics Interconnections, p. 43. 24. J. Lloyd et al., “Relationship between interfacial adhesion and electromigration in Cu metallization,” 2002 IEEE International Integrated Reliability Workshop, pp. 32–35, IEEE, Piscataway, NJ, 2002. 25. C. K. Hu et al., “Electromigration path in Cu thin film lines,” Appl. Phys. Lett., Vol 74, No. 20, pp. 2945–2947, 1999. 26. C. K. Hu et al., “Electromigration in two-level interconnects of Cu and Al alloys,” Mater. Chem. Phys., Vol. 41, No. 1, pp. 1–7, June 1995. 27. C. K. Hu et al., “A study of electromigration lifetime for Cu interconnects coated with CoWP, Ta/TaN, or SiCxNyHz,” Proceedings of Advanced Metallization Conference 2003, Materials Research Society, pp. 253–257, 2004. 28. I. A. Blech, “Electromigration in thin aluminum films on titanium nitride,” J. Appl. Phys., Vol. 48, pp. 1203–1208, 1976. 29. F. Chen et al., “Measurements of effective thermal conductivity for advanced interconnect structures with various composite low-κ dielectrics,” International Reliability Physics Symposium Proceedings 2004, pp. 68–73, IEEE, Piscataway, NJ, 2004. 30. E. T. Ogawa et al., “Stress-induced voiding under vias connected to wide Cu metal leads,” International Reliability Physics Symposium Proceedings 2002, pp. 312–321, IEEE, Piscataway, NJ, 2002. 31. T. D. Sullivan, “Thermal dependence of voiding in narrow aluminum microelectronic interconnects,” Appl. Phys. Lett., Vol. 55, p. 2399, 1989. 32. R. G. Filippi et al., “Thermal cycle reliability of stacked via structures with copper metallization and an organic low-κ dielectric,” International Reliability Physics Symposium Proceedings 2004, pp. 61–67, IEEE, Piscataway, NJ, 2004. 33. W. Landers et al, “Chip to package interaction for 90 nm Cu/PECVD low-κ technology,” Proceedings of the 2004 International Interconnect Technology Conference, p. 108, IEEE, Piscataway, NJ, 2004.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH04.qxd

04/04/2005

19:36

Page 4.14

COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:36

Page 5.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 5

FUNDAMENTALS OF SILICIDE FORMATION ON Si L. P. Ren Global Nanosystems, Inc. Los Angeles, California

King N. Tu University of California at Los Angeles Los Angeles, California

5.1 INTRODUCTION 5.1.1 Why Is Silicide Essential in Very Large Scale Integration of Circuits on Si As microelectronics device dimensions scale down to the deep submicron level, reduction of parasitic resistance is a key issue for high-speed operations of ICs. Silicide is a metal-Si compound and has been used as electric contact to Si at the gate and source and drain regions for reducing both the sheet resistance of the gate and source/drain regions and the contact resistance to them. In the past the overall circuit performance has depended primarily on device properties. To enhance the circuit and system speed, the primary effort had been on improving the device speed. However, during the last decade the parasitic series resistance, capacitance, and inductance associated with interconnections and contacts have begun to influence circuit performance and will be one of the primary factors in the evolution of deep submicron very large scale integration (VLSI) technology. For the submicron feature size the impact of parasitic components adversely affects circuit and system performance. RC time delay, IR voltage drop, power consumption, and crosstalk noise due to these parasitics are becoming significant. Even with very fast devices the overall performance of a large circuit can be seriously affected by the limitations of interconnections and contacts. Thus application of silicides to modern microelectronics has become essential as the conventional metallization scheme yields intolerably high contact resistance. For a certain conductor to be used to form multiplayer interconnections, several requirements that are imposed by fabrication technology and circuit performance must be met. The main requirements include good conductivity, reliability, and manufacturability. In a multiplayer interconnection structure, the layers incorporated early in the process sequence might be subjected to several fabrication steps, to which layers incorporated later might not. Based on this, the most desired properties of the silicide for integrated circuits are: low resistivity, ease of formation of thin films, ability to withstand chemicals and high temperatures throughout processing, good adhesion to other layers and surface smoothness, stability of electrical contacts to other layers, ability to contact shallow junctions, good device characteristics, resistance to electromigration, and ability to be defined into fine patterns.1 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

5.1

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.2

FUNDAMENTALS OF SILICIDE FORMATION ON Si 5.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

5.1.2 MOS Device—RC Delay and Speed at the Gate and Interconnection Level In the last 40 years, the metal oxide semiconductor (MOS) field effect transistor (MOSFET) has played a dominant role in the silicon integrated-circuit industry. Figure 5.1 shows a cross section of a typical MOSFET. The central region is called the gate. In this region the substrate silicon is isolated from the metal electrode (generally a polysilicon layer) by an insulating layer (generally a thermal grown SiO2 layer). Gate The two neighboring regions, called the source and the drain, are interchangeable and formed by the controlled high-dose implant and post-implant anneal. For example, if the region under the gate is p-Si, the source and the drain will be n+-Si, so we have an n+/p/n+ type transistor called NMOSFET. The MOSFET is still the Source Drain building block of various complex circuits designed and Gate oxide manufactured today. The characteristics of a MOS device depend on several parameters, of which the RC time constant is the most important. R and C represent, respectively, Silicon substrate the effective total resistance and capacitance at the gate and interconnection level. The higher the RC FIGURE 5.1 A typical MOSFET. value, the slower is the speed of the operating device. Figure 5.2 shows the impact of complementary MOS (CMOS) gate conductor sheet resistance on the performance of a 51-stage CMOS ring oscillator with a 0.7 µm effective gate length.2 Without any silicide present, the delay time at 5 V is about 300 ps while with the titanium (Ti) silicide that lowers the sheet resistance at contacts and polygate, the signal delay time at 5 V can be reduced to 46 ps. Therefore, to exploit the nature of low-power and high-speed CMOS devices, it is important to keep the source/drain and polygate resistances low. 5.1.3 Advanced Silicide Technology for Deep Submicron CMOS Devices During the last few years, the use of metal silicide has been heavily investigated for many applications such as ohmic contact, MOS gate electrodes, and silicidation of diffusions, and the results have

Output waveform

L = 0.7 µm

5V

10−9 Delay/stage (s)

51 stage

6V Ti = 0 nm 2V 10−10

3V

4 V 5 V Ti = 20 nm

2V 3V

4V

5V Ti = 45 nm

10−11 −5 10

10−4

10−3

10−2

Power/stage (W) FIGURE 5.2 Measured delay time/stage of a 51-stage ring oscillator with a 0.7-µm gate length as a function of initial Ti thickness.2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.3

FUNDAMENTALS OF SILICIDE FORMATION ON Si FUNDAMENTALS OF SILICIDE FORMATION ON Si

5.3

been very exciting. Silicides of titanium, cobalt, nickel, platinum, tungsten, molybdenum, tantalum, and other metals have reasonable good compatibility with IC fabrication technology for one or more applications mentioned earlier. They have fairly high conductivity and resistance to electromigration, can make low resistance and reliable contacts to shallow p-n junctions, and can withstand the chemicals normally encountered during the fabrication process. However, to incorporate the silicides in a microelectronics structure, many problems must be understood for the proper functioning of the device. Important issues are that the silicides involve nonhomogeneous materials and often contain a secondary and metastable phase. Equally important is the presence of adjoining layers and the interfaces between them, and the role they play in the different processes and mechanisms. As the semiconductor structures get smaller, these adjoining layers and interfaces can dominate the various phenomena in interconnect processing. In addition, even the interfaces themselves can act as separate phases and greatly affect the film properties and processing. For the silicide process, low-resistivity silicide layers are obtained by depositing the silicide directly, or by depositing the metal on silicon and reacting the materials to form the silicide. In all of these cases a detailed knowledge of the formation techniques, properties of as-formed films, and changes during the subsequent processing is absolutely necessary.

5.2 WHAT ARE THE FUNDAMENTALS OF SILICIDATION ON Si? 5.2.1 Properties The resistivity of the silicide is the most important criterion for considering metallization in integrated circuits. Investigations of various metal-silicon systems have resulted in silicide resistivities that are routinely obtainable.3,4 Table 5.1 lists the resistivities of various silicides formed by reacting thin metal film with mono or polycrystalline silicon. The table also gives the sintering temperatures at which the lowest resistivities were obtained. Schottky barrier height is another important parameter that will affect contact resistance in deep submicron CMOS devices. For ohmic contact between metal and heavily doped silicon, current conduction is dominated by tunneling or field emission. The contact resistivity rc depends exponentially on the barrier height ΦB and the surface doping concentration Nd:10 rc  exp[4pΦB /qh (m*esi/Nd)1/2], where h is Planck’s constant and m* is the electron effective mass. The best known value of Schottky barrier heights of silicide on n-silicon has been included in Table 5.1. In general, four apparent variables control the barrier heights of various silicides on silicon—(a) the work function fM of the metal, (b) the crystalline or amorphous structure at the metal-silicon interface, (c) the ability of the metal

TABLE 5.1 Resistivity of Various Silicides and Schottky Barrier Value of Silicide on n-Silicon Silicide

Self-aligned reaction temp. (°C)

Resistivity (µΩ-cm)

NiSi Pd2Si PtSi

625–675a 850–900b 400–540a 700–800b 400–650 175–450 400–600

18–20 ~50 30–35 28–35

WSi2 MoSi2

690–740 850

~70 90~100

TiSi2 CoSi2

ΦB (eV)

Useful temperature (°C) <950

0.605

<900

0.645

<700

0.656 0.717 0.888 0.21 for p+-type 0.655 0.559

13–16

<800

a

First anneal followed by the selective metal etch. Second anneal to form the low-resistivity silicide.

b

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.4

FUNDAMENTALS OF SILICIDE FORMATION ON Si 5.4

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

TABLE 5.2 Crystal Parameters of Various Metal Silicides12–20 Lattice constant Metal

Compounds

Structure

Prototype

a

b

c

Density

Ti Co Ni Pd Pt W Mo

TiSi2 CoSi2 NiSi Pd2Si PtSi WSi2 MoSi2

Orthorhombic Cubic Cubic Hexagonal Orthorhombic Tetragonal Tetragonal

Si2Zr CaF2 FeSi Fe2P MnP MoSi2 MoSi2

8.253 5.365 4.446 13.055 5.590 3.211 3.203

4.783

8.554

4.043 4.950 5.920 9.589 12.394 9.857 6.240

3.603

27.49 5.932 7.868 7.855

atoms, which may have diffused (across the interface) into the silicon, to act as traps for electrons or holes and thus participate in the current-carrying process, and (d) the outermost electronic configuration of the metal atoms. Forming good contacts is essential to the operation of the device.11 Table 5.2 presents the crystallographic structures, lattice parameters, and densities of the most commonly used metal silicides. Silicide structures vary in complexity. Usually the number of atoms per unit cell is large; TiSi2 has 24 atoms per unit cell and Pd2Si has 288 atoms per unit cell. During the formation of transition metal silicide by solid-phase reaction, there is always a net volumetric change resulting in net volume shrinkage as shown in Table 5.3. This shrinkage can cause a large tensile stress in the silicide films, thereby threatening the structure’s mechanical stability at siliciding temperatures or during further processing. By using this table, the amount of silicon required for the formation of a silicide per angstrom of the metal and amount of the resulting silicide also can be calculated.1 The stress can arise from lattice mismatch between the substrate and film, the intrinsic stress related to the mechanical structure and properties of the film, and the difference between the thermal expansion coefficients of the film and the substrate. Table 5.4 lists the thermal expansion coefficients of various silicides, together with those of the constituent metal and silicon. The thermal expansion coefficients of the silicides are considerably larger than those of the metals and silicon, and the difference can be responsible for the observed stress. The melting point of the transition metal silicides has also been listed in the table. Wet chemical etching has been used in the silicide process to selectively remove unreacted metal from the oxide surface. Table 5.5 presents the chemical reactivity of various silicides of interest. As shown in the table, silicides in general, are hard to etch in aqueous alkalis or in mineral acids, except for hydrofluoric acid.11

TABLE 5.3 Volumetric change during silicide formation. The metal thickness tM is normalized to 1 and the silicon and silicide thickness tSi and Tsil are in the units of tM

Metal

Atomic volume °3) (Α

Ti Co Ni Pd Pt W Mo

10.60 6.62 6.60 8.87 9.12 9.53 9.41

Silicide

tSi (Consumed silicon thickness)

tsil (Thickness of the resulting silicide)

C54TiSi2 CoSi2 NiSi Pd2Si PtSi WSi2 MoSi2

2.22 3.61 1.83 0.68 1.32 2.52 0.43

2.44 3.49 2.01 1.42 1.98 2.48 2.60

Tsil/tM

Tsil/tSi

Tsil/tM+tSi

Ratio of thickness of silicide formed to that of the metal 2.44 3.49 2.01 1.42 1.98 2.48 2.60

1.10 0.97 1.10 2.09 1.50 0.98 1.01

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

0.76 0.76 0.71 0.84 0.85 0.70 0.73

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.5

FUNDAMENTALS OF SILICIDE FORMATION ON Si FUNDAMENTALS OF SILICIDE FORMATION ON Si

5.5

TABLE 5.4 Thermal Properties

Silicide

M Pt (°C)

TiSi2 CoSi2 NiSi Pd2Si PtSi WSi2

150017,21,22 132617,21,22 992 901 122917,22 216017,21,22

MoSi2

200717,21,22

a (ppm/°C) Thermal expansion 12.5 (200–1200°C)17 10.14 (20–800°C)17

6.25 (20–420°C)17 7.90 (420–1070°C)17 8.25 (20–1070°C)17

Element

M Pt11 (°C)

a (ppm/°C) Thermal expansion

Si Ti Co Ni Pd Pt W

1661 1495 1453 1553 1773 3411

3.0 8.5 12.0 13.0 13.0 8.0 4.5

Mo

2617

5.0

5.2.2 Formation The formation of a low-resistivity silicide is of great importance for deep submicron devices. The simplest method to form a silicide thin film is to deposit a film of metal on a silicon substrate and to induce the formation by annealing. It is thus of prime importance to understand and control the kinetics of reaction between metal and silicon. For a metal film deposited on silicon or polysilicon substrate and annealed at low temperatures, metal-rich silicides form first. There are two fundamental issues in silicide formation. The first is how to break the covalent bonds in Si at a low reaction temperature, say the formation of Ni2Si at around 200°C.23 The second is the single-phase formation of the silicide in the reaction between a metal thin film and Si. Noble and near-noble metals diffuse interstitially in Si and react with Si at relatively low temperatures. The interstitial metal atoms in Si convert the covalent bonds to metallic bonds and lower the reaction temperature of silicide formation. On the other hand, transition and refractory metals do not diffuse interstitially in Si and need a higher reaction temperature in silicide formation. The single-phase formation behavior is due to kinetic reasons and it benefits us to have a single-phase contact or gate formed uniformly on millions of source-and-drain contacts and gates on a Si device. For suitable kinetic conditions, the formation of metal-rich silicide continues until all the metal is consumed. At that point the next silicon-rich phase starts to form. It is a sequential formation of silicides, one phase followed by another phase. Numerous studies have been devoted to this subject.24–27 For Ti silicide formation, a high resistivity phase called C49 is formed at a low temperature

TABLE 5.5 Chemical Reaction of Silicide Silicide

Insoluble in

Soluble in

TiSi2 CoSi2

Aqueous alkali, all mineral acids Nitric, sulfuric, or phosphoric acids; H2SO4 + H2O2 mixture Nitric, sulfuric, or phosphoric acids; H2SO4 + H2O2 mixture Aqua regia, HCI, H2SO4, HF, H2SO4 + H2O2 Aqua regia, HCI, HNO3, H2SO4, HF, H2SO4 + H2O2 Aqua regia, mineral acids Aqueous alkali, aqua regia, mineral acids

HF—containing solutions HF—containing solutions; boiling conc. HCI; conc. aqueous alkali HF—containing solutions

NiSi Pd2Si PtSi WSi2 MoSi2

HNO3, HF + HNO3 Slightly soluble in HF + HNO3 HF + HNO3 HF + HNO3

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.6

FUNDAMENTALS OF SILICIDE FORMATION ON Si 5.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

TABLE 5.6 Results of the Growth Kinetics of Silicide Thin Films: Silicide Formed, Range of Formation, Activation Energy, Dominant Diffusing Species (DDS), and Kinetics Time dependence

Silicide

Tf (°C)

Q (eV)1

DDS

TiSi2

550–650 575–750 350–500 400–550 405–500 250–400 175–450 300–540 850–1100 474–550 850–1100

2.5 2.5 1.5 1.75 2.3 1.4 1.4 1.5 3, 2.2 3.2, 2.4 2.2

Si

t1/2

Co Si Co Ni Pd-Si Pt-Si? Si

t1/2 t1/2

Co2Si CoSi CoSi2 NiSi Pd2Si PtSi WSi2 MoSi2

t t1/2 t1/2 t, t1/2 t, t1/2

Si

first, then a second high-temperature anneal is needed to convert C49 to low resistivity phase C54. Similar information has been obtained for cobalt silicide. Table 5.6 summarizes the results of the growth and transformation of various silicides at different temperatures. In most cases a t1/2 dependence of the phase growth has been found, indicating a diffusion-limited growth, where the thickness of the silicide layer formed in time t is given by X2 = Dt. In some cases a linear dependence on time was found, suggesting an interface rate-controlled interaction and the thickness is given by X = Dt, where D represents interface diffusivities during silicide formation. These data are quite useful for practical applications—reacted silicide thickness at the specific temperature and time can be calculated by using these data. 5.2.3 Integrated-Circuit Fabrication The standard silicide process for MOSFETs on Si substrates is well developed. A two-step rapid thermal annealing (RTA) method is used to minimize lateral overgrowth of silicide onto the oxide sidewall. Among the choices of metal silicides, titanium and cobalt silicides are widely used in industry due to their low resistivity, high thermal stability, and ability to remove from oxide on Si. Figure 5.3 and Table 5.7 represent the detailed fabrication procedures with standard CMOS process flow—as a part of the overall CMOS process, the silicide formation follows the spacer definition. The starting metal was sputter deposited as a bilayer stack, with the bottom layer being the reacting species and the top layer being the stabilizing material for suppressing unwanted

Gate Drain

Source

Substrate

Silicide

Gate

Substrate FIGURE 5.3

Silicide

♣ Active area definition and LOCOS ♣ Threshold voltage adjustment ♣ Gate oxidation and polydeposition ♣ E-beam polygate lithography and polyetch ♣ Source/drain extension implant ♣ Spacer formation and deep S/D implant ♣ RTA dopant activation ♣ Two step Ti silicidation

Silicide process flow with CMOS technology.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.7

FUNDAMENTALS OF SILICIDE FORMATION ON Si FUNDAMENTALS OF SILICIDE FORMATION ON Si

5.7

TABLE 5.7 Fabrication Procedure for Titanium and Cobalt Silicide Films in the CMOS Process Process flow

TiSi2

CoSi2

Starting Metal/Thickness Capping Layer/Thickness Metal Deposition Method First RTA Select Wet Etch

Ti/35 nm TiN/15 nm Sputter or evaporation 675°C/120 s 4:1, 120°C/10 min H2SO4:H2O2 850°C/1 min

Co/32 nm Ti/20 nm Sputter or evaporation 475°C/3 min 1:1:1, 65°C/1 min NH4OH:H2O2:H2O 700°C/1 min

Second RTA

agglomeration and surface reactions. The metal stacks were deposited without breaking the vacuum. Prior to metal deposition, the wafers were sputter cleaned with Ar ions to remove any residual native oxides. For cobalt silicide, the Ar sputter clean eliminates the need for a Ti interlayer between Co and Si, thus allowing it to process at a lower temperature and results in films with greater uniformity and less agglomeration. Capping layers such as Ti or TiN have been shown to be effective in giving more uniform and lower-resistivity silicide films.28 They also lead to greater thermal stability and greatly suppressed line-width degradation effects. These advantages due to the capping films were speculated to result from reduced surface and interface diffusion of the reacting metal species during the nitrogen anneal. Following the metal deposition, the wafers were annealed by the RTA system in a 100 percent N2 ambient. After the initial RTA, the unreacted material on the field oxide and spacer regions was wet etched in a heated H2SO4:H2O2 for titanium silicide and NH4OH:H2O2:H2O mixture for cobalt silicide. This is a critical part of the self-aligned silicide process, which has been found to be adequate in preventing bridging between the source/drain region and the gate. After the etch, only the polysilicon gate and the source/drain region have silicides. The final step is to convert the remaining active silicide into a low-resistivity material without agglomeration. This was accomplished with another RTA annealing cycle. For Co, this was done at 700°C for 1 min and for Ti, it was done at 850°C for 1 min. After this, the wafers are ready for the contact dielectric deposition and the subsequent first-level metal-interconnect processing.

5.3 FUTURE TRENDS AND NANOSILICIDE FORMATION 5.3.1 General Trends It has been observed that the sheet resistance of a Ti-silicided polysilicon-gate electrode or source/drain region increases significantly as the dimension reaches the lower submicron range. Thus alternative silicide choices like cobalt and nickel silicides have been investigated and chosen as the promising silicides for deep submicron MOS technologies.29,30 They have the advantages of having the lowest resistivities (~20 µΩ-cm), good thermal stability (up to 700 ~ 900°C), low forming temperature (~400–600°C) and little or no resistivity degradation on narrow gate lines. Moreover, NiSi can be formed at as low as 450°C, and has a large processing temperature window. It is stable up to 650°C, where the phase transition to high resistive NiSi2 takes place. In addition to achieving low silicide resistivity, nickel consumes less amount of silicon to form monosilicide than Ti or Co does in forming disilicide. Also, there is no reaction with N2 and no resistivity degradation on gate lines. When the scaling of traditional bulk devices becomes deep submicro regime, there are several challenges for silicide process development—well-controlled thin film silicide is essential due to shallow junctions; and large contact resistance induced by conventional silicide with barrier height ~0.6 eV needs to be decreased by using an alternative silicide. Based on this, low-barrier silicides of ErSi2 for n-channel MOS (NMOS) and PtSi for p-channel MOS (PMOS) have been suggested, which attract a lot of interest for ultrathin devices.31,32 Selective deposition of the silicide on bulk Si

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.8

FUNDAMENTALS OF SILICIDE FORMATION ON Si 5.8

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

wafers by low-pressure chemical vapor deposition (LPCVD) has been investigated as an alternative choice for small dimensional devices. In the CVD process, the silicide thickness is no longer limited by the shallow source/drain junction, and substrate doping does not have a strong effect on silicide growth. More important, the sheet resistance is not affected by polysilicon line-width because the formation of the C54 phase occurs during deposition. One remaining issue of this technology is the silicide/Si-specific contact resistivity. 5.3.2 Nanosilicide Formation In Fig. 5.4(a), several nanosize Pd2Si particles on a (100) surface of Si are shown.33 The formation of these nano-Pd2Si particles was obtained by annealing a thin film of 75Pd25Er alloy on (100) Si surface at 347°C for 1 h. The misfit between the diffraction patterns of the Pd2Si and Si is shown in Fig. 5.4(b)—the misfit between the (220) spot of Si and (3030) spot of Pd2Si is 0.03 or 3 percent. Most of the nanoparticles of Pd2Si have a rectangular shape with its edge of [0110] parallel to the [110] direction of Si. One of the potential applications of these rectangular and nanosize Pd2Si particles is to serve as the seeds for solid-phase epitaxial growth of Si nanowires on (100) Si surface. We postulate that if we deposit amorphous Si over these particles, we will embed these nano-Pd2Si particles between the amorphous Si and the (100) Si substrates, in other words we have a sandwiched structure of amorphous Si/ nano-Pd2Si/ (100) Si substrate. Then, if we anneal the embedded structure at around 400°C, we may achieve solid-phase epitaxial growth of nano-Si wires on (100) Si via the nano-Pd2Si particles. We recall that solid-phase epitaxial growth of a blanket-type thin film structure of amorphous Si/ Pd2Si/ (100) Si has been performed, and the amorphous Si reacts with the Pd2Si and grows on the (100) Si.34 However, solid-phase epitaxial growth of Si on nano-Pd2Si has not been done. If it does occur, we may etch away the unreacted amorphous Si surrounding the nanocrystalline Si wires to reveal the wires. These nano Si wires may have the (100) growth direction and with (110) surfaces as the sidewalls. In addition to the use of amorphous Si as the source of Si for the growth of the nano-Si wires, we can use gas phase of Si as the source. Indeed, nanoscale C49-TiSi2 particles have been used to grow Si nanowires in gas ambient.35–37 However, the misfit between C49 TiSi2 and (100) Si is much larger than that between Pd2Si and (100) Si. The Si wires grown under the C49 TiSi2 are bent and not

0002− 220−×

×

000 50 nm ( a)

220 Pd2Si

– 303 0

× Si

(b)

FIGURE 5.4 (a) Bright-field plan-view image showing the two habits of the Pd2Si crystals. (b) The misfit between the (220) spot of Si and (3030) spot of Pd2Si is 3 percent. Most of the nanoparticles of Pd2Si have a rectangular shape with its edge of [0110] parallel to the [110] direction of Si.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.9

FUNDAMENTALS OF SILICIDE FORMATION ON Si FUNDAMENTALS OF SILICIDE FORMATION ON Si

5.9

straight at all. It is possible that we may be able to grow straight nano-Si wires via the nano-Pd2Si particles. It is known that NiSi2 and CoSi2 have the CaF2 cubic crystal structure and they have a very small lattice misfit to Si. Superlattice of CoSi2/Si/ CoSi2/Si with nanoscale period has been grown. On the other hand, nanoscale NiSi2 particles on (111) Si have been observed.38 Nevertheless, superlattice or epitaxial growth of CoSi2 and NiSi2 thin films on (100) Si is much more difficult; furthermore, the growth in nanoscale has not been studied.

5.4 CONCLUSIONS The application of silicides is essential for modern microelectronics. The main requirements for silicides are good conductivity, reliability, and manufacturability. In order to form good silicides with low resistivity and low contact resistance, a detailed knowledge of their thermodynamic, electrical, and mechanical properties, and their stability at high temperature is needed. Based on the criteria mentioned in this chapter, the RTA silicide process has been introduced in detail with standard CMOS integrated-circuit fabrication. Due to a more complicated demand for submicron CMOS technology, novel silicide development has received much attention for next generation VLSI.

REFERENCES 1. Maex, K., and M. V. Rossum, Properties of Metal Silicides, United Kingdom: INSPEC, the Institution of Electrical Engineers, 1995. 2. Yamaguchi, Y., et al., “Self-aligned silicide technology for ultra-thin SIMOX MOSFETs,” IEEE Trans. Electron Dev., Vol. 39, p. 1179, 1992. 3. Murarka, S. P., et al., “Resistivities of thin film transition metal silicides,” J. Electrochem. Soc., Vol. 129, p. 293, 1982. 4. Nava, F., et al., “Electrical and optical properties of silicide single crystals and thin films,” Mater. Sci. Rep., Vol. 9, pp. 141–200, 1993. 5. Sze, S. M., Physics of Semiconductor Devices, 2d ed., New York: Wiley, 1981. 6. Liehr, M., et al., “Correlation of Schottky-barrier height and microstructure in the epitaxial Ni silicide on Si(111),” Phys. Rev. Lett., Vol. 54, p. 2139, 1985. 7. Ho, P. S., “Chemical bonding and Schottky barrier formation at transition metal-silicon interfaces,” J. Vac. Sci. Technol. A, Vol. 1, p. 745, 1983. 8. Ottaviani, G., K. N. Tu, and J. W. Mayer, “Barrier heights and silicide formation for Ni, Pd, and Pt on silicon,” Phys. Rev. B, Vol. 34, p. 3354, 1981. 9. Thompson, R. D., and K. N. Tu, “Comparison of the three classes (rare earth, refractory and near-noble) of silicide contacts,” Thin Solid Film, Vol. 93, p. 265, 1982. 10. Taur, Y., and T. H. Ning, Fundamentals of Modern VLSI Devices, p. 243, United Kingdom: Cambridge University Press, 1998. 11. Murarka, S. P., Silicides for VLSI Applications, Orlando: Academic Press, 1983. 12. NBS Monograph 25 (USA) No. 21, p. 126, 1984. 13. Wong-Ng, W., et al., NBS Grant-in-Aid Report, 1987. 14. Ishida, K., T. Nishizawa, and M. E. Schlesinger, “The Co-Si (Cobalt-Silicon) System,” J. Phase Equilibria, Vol. 12, p. 578, 1991. 15. d’Heurle, F., et al., “Formation of thin films of NiSi: Metastable structure, diffusion mechanisms in intermetallic compounds,” J. Appl. Phys.,Vol. 55, p. 4208, 1984. 16. Nash, P., and A. Nash, Bull. Alloy Phase Diagrams, Vol. 8, p. 6, 1987. 17. Samsonov, G. V., and I. M. Vinitskii, Handbook of Refractory Compounds, New York: IFI/Plenum, 1980.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH05.qxd

04/04/2005

19:37

Page 5.10

FUNDAMENTALS OF SILICIDE FORMATION ON Si 5.10

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

18. Pearson, W. B., A Handbook of Lattice Spacings and Structures of Metals and Alloys, Vol. 2, London: Pergamon, 1967. 19. Tanner, L. E., and H. Okamoto, Z. Metallkd., Vol. 55, p. 503, 1964. 20. d’Heurle, F. M., C. S. Petersson, and M. Y. Tsai, “Observations on the hexagonal form of MoSi/sub 2/ and WSi/sub 2/ films produced by ion implantation and on related snowplow effects,” J. Appl. Phys., Vol. 51, p. 5976, 1980. 21. Kosolapva, T. Y., Handbook of High Temperature Compounds: Properties, Production, Applications, New York: Hemisphere Publishing, 1990. 22. Massalski, T. B., Binary Alloy Phase Diagrams, 2d ed., Vol. 1–3, ASM, 1990. 23. Tu, K. N., W. K. Chu, and J. W. Mayer, “Structure and growth kinetics of Ni/sub 2/Si on silicon,” Thin Solid Films, Vol. 25, p. 403, 1975. 24. Gosele, U., and K. N. Tu, “Growth kinetics of planar binary diffusion couples: ‘Thin-film case’ versus ‘bulk cases’,” J. Appl. Phys., Vol. 53, p. 3252, 1982. 25. Pico C. A., and M. G. Lagally, “Kinetics of titanium silicide formation on single-crystal Si: Experiment and modeling,” J. Appl. Phys., Vol. 64, p. 4957, 1988. 26. Lien, C. -D., M. -A. Nicolet, and S. S. Lau, “Kinetics of CoSi/sub 2/ from evaporated silicon,” Appl. Phys. A, Vol. 34, p. 249, 1984. 27. Ren, L. P., B. Chen, and J. Woo, “Advanced silicide for sub-0.18 µm CMOS on ultra-thin (35 nm) SOI,” IEEE International SOI Conference, pp. 88 and 89, 1999. 28. Liu, H. I., et al., “Thin silicide development for fully-depleted SOI CMOS technology,” IEEE Trans. Electron Dev., Vol. 45, pp. 1099–1104, 1998. 29. Liang, J. M., et al., “Crystallization of amorphous CoSi/sub 2/thin films. I. Kinetics of nucleation and growth,” Mater. Chem. Phys., Vol. 38, pp. 250–257, 1994. 30. Pan, G. Z., E. W. Chang, and Y. Rahmat-Samii, “Effect of a Ti-capped and Ti-mediated layer on Co silicide formation,” Mat. Res. Soc. Symp. Proc., Vol., No. 716, pp. 451–456, 2002. 31. Kedzierski, J., et al., “Design analysis of thin-body silicide source/drain devices,” IEEE International SOI Conference, pp. 21 and 22, 2001. 32. Kedzierski, J., et al., “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” IEDM Tech. Dig., pp. 247–250, 2002. 33. Boothroyd, C. B., W. M. Stobbs, and K. N. Tu, “Formation of submicron epitaxial islands of Pd/sub 2/Si on silicon,” Appl. Phys. Lett., Vol. 50, p. 577, 1987. 34. Poate, J. M., K. N. Tu, and J. W Mayer, Thin Films—Interdiffusion and Reactions, chap. 12, New York: Wiley-Science, 1978. 35. Kamins, T. I., et al., “Chemical vapor deposition of Si nanowires nucleated by TiSi/sub 2/ islands on Si,” Appl. Phys. Lett., Vol. 76, p. 562, 2000. 36. Tang, Q., et al., “Twinning in TiSi/sub 2/-island catalyzed Si nanowires grown by gas-source molecular-beam epitaxy,” Appl. Phys. Lett., Vol. 81, p. 2451, 2002. 37. Kamins, T. I., X. Li, and R. S. Williams, “Thermal stability of Ti-catalyzed Si nanowires,” Appl. Phys. Lett., Vol. 82, p. 263, 2003. 38. Hess, D., P. Werner, R. Matttheis, and J. Heydenreich, “Interfacial reaction barriers during thin-film solid-state reactions: the crystallographic origin of kinetic barriers at the NiS/sub 2//Si(111) interface,” Appl. Phys. A, Vol. 57, pp. 415–425, 1993.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 6

PLASMA PROCESS CONTROL David J. Coumou MKS Instruments, Inc. Rochester, New York

6.1 INTRODUCTION Plasma processing is an intricate and integral part of the manufacturing of semiconductor devices. Plasma chambers are used in the manufacturing of semiconductor devices to etch or deposit thin films of material on a substrate. For etch, the objective is to create a high-density plasma that generates ions that travel from the plasma discharge and strike a target to remove atoms of material. For deposition, the process is similar to etch with the exception that the objective is to coat the target with material. The control of the plasma process is analogous to other manufacturing processes and respective control systems. It is a process where physics that is described by mathematics meets a form of control methodology. In the case of high-density plasma chambers, the plant model is a consortium of chemistry and physics. The pursuit of an optimal control scheme for this manufacturing process faces endless and daunting degrees of challenge. As the size of features, often referred to as critical dimensions or CD, decreases and the surface area of targets increases, a higher level of integration on semiconductor devices is produced. Increasing the process rate is highly advantageous because the cost of semiconductor manufacturing is directly proportional to the time required for fabrication. These are just some of the vexing issues that challenge the control of the manufacturing process of this industry. It is paramount that the control methodology is repeatable and targeted manufacturing yields are maintained. This chapter serves to present the basis of plasma physics and a survey of control schemes and metrology. The chapter will not focus on vacuum or flow control and chemistry. To meet this objective, this chapter presents a survey of a great body of work in these areas. For this reason, an acknowledgment is warranted to a number of exceptional contributors to this field. The attempt at the provision of precise references and direction to additional information has been a rigorous task. It is hoped that none of the work of the great contributors to this field has been omitted.

6.2 FUNDAMENTALS OF PLASMA GENERATION AND PROCESS CONTROL In this section the development of a physical model of high-density plasma reactors is described. The first model will be developed for an inductively coupled source. This is then followed by a capacitive-coupled parallel plate. In each subsection, models, theories, and practices will be explored.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

6.1

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.2

PLASMA PROCESS CONTROL 6.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Primary coil

Tube RF source

FIGURE 6.1

Physical model of an inductively coupled plasma source.

6.2.1 Inductively Coupled Plasma Sources The simplest form of an inductively coupled plasma source is shown in Fig. 6.1. The radio frequency (RF) source produces the current to flow through the coil. The coil surrounds the cylindrical chamber formed by the tube. The tube is a dielectric material, traditionally in the form of a ceramic type of material. The genesis of inductively coupled plasma sources dates as far back as 1884.1 Over time, this plasma source has proven to be attractive for applications requiring a clean and stable source of plasma, due to the absence of an electrode and its contamination. The inductively coupled discharge is either maintained by the axial electrostatic field or by an azimuthally electromagnetic field of the primary coil.2 The electrostatic mode of operation appears at low RF power while the electromagnetic mode of operation appears when the coil current is large enough to induce an azimuthal electric field that can maintain the ionization process. In this inductive mode, the gas discharge is sustained by induction from a time-varying Ro R2 VRF Lo L2 Le magnetic field.3 The physical model of an inductively coupled discharge can be described in terms of an electrical circuit. An air core FIGURE 6.2 Electrical model of an inductransformer model is the traditional method used to describe tively coupled plasma source. an inductively coupled discharge.4–6 Figure 6.2 depicts the transformer circuit to describe an inductively coupled discharge. The proceeding mathematical derivation for the air transformer model of an inductively coupled discharge is transcribed from Ref. 3. An air transformer consists of two windings. These windings are interlinked by a mutual magnetic field. The magnetic field produced by a current flowing in the primary coil interacts with the secondary coil. In the case of the inductively coupled discharge, the primary of the transformer is the coil that is wound about the tube. This coil is composed of N turns with inductance Lo and resistance Ro. The discharge is electrically conductive and can be considered a one-turn secondary winding with inductance L2. The discharge comprises an inductance Le and a series resistance R2 for the plasma. The two components of the discharge are the magnetic inductance and the electron inertia inductance. The magnetic inductance is due to the discharge current path and Le results from the conductivity of the plasma.7

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.3

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

6.3

In mathematical terms, the change in plasma resistance is given by r=

w 2 M 2 R2 R + (w Le + w L2 )2 2 2

where M represents the mutual inductance of the primary and secondary. The change of the plasma reactance is c=

w 2 M 2 (w Le + w L2 ) R22 + (w Le + w L2 )2

These components are used to define the secondary impedance as Zs = Ro + r + jw ( Lo + c ) The RF voltage is the product of the RF current and Zs. The power absorbed by the plasma is the product of the plasma resistance r and the square of the RF current. The reader is directed to Ref. 3 for a comprehensive development of the parameters described by the real r and imaginary c components of the discharge impedance. There are a number of advantages to using inductively coupled plasma sources—flexibility, density, low transverse energy, no magnetic field, low gate damage, high efficiency and plasma confinement.8 There are various chambers that have been deployed that use inductively coupled plasma sources for semiconductor manufacturing. An example of this form of a plasma tool used in industry is the TCP 9600 tool from Lam Research. This chamber design employs a planar inductor and is used for metal etch processing. Applied Materials has the Omega Tool that utilizes a solenoid RF coil and is used for oxide etch processing. Readers who are interested in obtaining additional information about inductively coupled discharges should see Refs. 9 to 15 at the end of the chapter. 6.2.2 Electron Cyclotron Resonance Plasma Sources An alternative form of inductively coupled reactors is electron cyclotron resonance (ECR). Reference 16 provides a review of the principles of ECR plasma sources. In summary, a brief explanation of an ECR discharge is described. An ECR discharge is created from a microwave radiation source and a magnetic field. Electrons transverse in a circular motion in the direction of the magnetic field. The frequency of this circular motion is the cyclotron frequency. With the application of an electromagnetic field, energy is transferred to the electrons. Resonance occurs when the electron undergoes one circular orbit in one period of the applied electromagnetic field. The microwave frequency is typically 2.45 GHz. This is primarily because the hardware costs and availability are realizable for the production of commercial reactors and the necessary electromagnets and permanent magnets are reasonable in cost and size. Commercial uses of this technology in the production of semiconductor manufacturing are evident in both etch and deposition tools. 6.2.3 Capacitively Coupled Plasma Sources Capacitively coupled plasma sources have been the most widely used source for low-pressure material processing.17 Not shown in this figure is the vacuum control system that is used to maintain a stable pressure in the chamber and the gas inlet where the flow of chemistry into the chamber is controlled. Capacitively coupled plasma sources are used for reactive ion etch (RIE), plasma etch, physical vapor deposition (PVD), and plasma-enhanced chemical vapor deposition (PECVD). Interestingly, the RIE chamber is a misnomer since the etching is a chemical process that is ameliorated by energetic ion bombardment of the substrate, rather than a removal process due to reactive ions alone.17 The typical configuration for capacitively coupled plasma sources is a parallel plate

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.4

PLASMA PROCESS CONTROL 6.4

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Sheath

RF source Electrodes

Plasma Sheath

Chamber under vacuum

FIGURE 6.3

Physical model of a parallel plate plasma source.17

arrangement of electrodes and is illustrated in Fig. 6.3. With the application of RF energy, the plasma is developed between the upper and lower electrodes. For simplification, the upper electrode is powered in this model and the lower electrode is grounded. Some industrial applications for capacitively coupled discharges employ a second RF source at the lower electrode. A sheath is generated between the electrodes and the plasma. The sheath is a positively charged layer that confines electrons. The electrons are confined because the electric field in the sheath is directed from the plasma.17 The industry standardized the parallel plate configuration and referred to this chamber design as the Gaseous Electronics Conference (GEC) RF reference cell.18 It is also commonly referred to as the GEC cell. Figure 6.4 illustrates the circuit model for this parallel plate chamber design. Reference 19 is utilized to describe the circuit model and Ref. 17 to correspond the circuit model to the plasma parameters. The shunt circuit elements (Ls, Cs, and Rs) will be addressed in the matching network discussion of this chapter. The circuit model includes the parasitic elements that are present in the powered and ground electrodes and in the chamber wall. Note that sometimes the powered electrode is referred to as the anode and the grounded electrode is referred to as the cathode. CPE is the parasitic capacitance for the powered electrode and is attributed to the insulator between the powered electrode and the ground shield. The transmission line that powers the electrode is represented by the series elements LPE and RPE. Typical chamber designs will have RF metrology installed in situ before the electrode. CM represents the shunt capacitance that is introduced by the RF metrology. LPE and RPE may also address the effects of the RF metrology. Analogous to the powered electrode, elements

LPE RPE LS VRF

CS

CM

IPE

RGE CPE

CGE

L GE

RS LW FIGURE 6.4

Electrical model of a capacitively coupled plasma source.19

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.5

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

6.5

CGE, LGE, and RGE represent the parasitic elements of the ground electrode. LW is the self-inductance of the cavity between the chamber wall and the outer surface. The inherent stray capacitance Cchuck between the lower and upper electrodes and chamber side wall is not included in the circuit model in Fig. 6.4. The electrical properties of the chamber (LW and Cchuck) and the transmission line that powers the electrode do not change with respect to the input RF power and plasma parameters. Specifically, Cchuck and the inductance of the rod Lrod can be measured with no plasma present. Obtaining a base pressure in the chamber and with an RF source set to a power that is insufficient to ignite plasma but drives the chamber with a voltage, the electrical characteristics of the chamber can be calculated from the measured voltage and current obtained from the RF metrology. jw Lrod + 1/ jw Cchuck = Vm / Im Vm and Im are the voltage and current measured by the RF metrology. Ve and Ie are the true voltage and current at the powered electrode. Vm, Im, Ve, and Ie are all time-varying complex numbers. Ve and Ie are related to Vm and Im by Ve = Vm − jw Lrod Im Ie = (1 − w 2 Lrod Cchuck ) Im − jw Cchuck Vm The electrical properties of the chamber (LW and Cchuck) and the transmission line have an insignificant role in the analysis of plasma for parallel plate systems and are often omitted. Cs is used to define the equivalent capacitance of the plasma sheaths on the powered and grounded electrodes and Rs to define the equivalent resistance of the two sheathes. Since the plasma is typically operated at a frequency of 13.56 MHz, the dominant current-transport species in the plasma are the highly mobile electrons. This is represented as a resistive component Rb that is defined by Rb =

mνdb Ane2

where A = electrode area db = bulk thickness e, m = electron charge and mass n = bulk plasma density n = electron-atom collision frequency The bulk resistance is inversely proportional to the mobility and density of electrons, and proportional to the thickness of the bulk region. The sheath capacitance determines the effective sheath thickness S0 as Cs = Ae 0 /2 S0 where e0 is the vacuum dielectric constant and 2S0 + db = L the gap distance between the two electrodes. The parallel sheath resistance represents the ion acceleration power (Pi) in the sheath in terms of the RF voltage drop (Vsh) across the sheath as Rs = Vsh2 /2 Pi = Vsh2 /4 Ii Vdc where Ii is the ion current to the electrode, and Vdc is the dc voltage across each sheath. Another way to account for ion power loss is through an equivalent series resistance in terms of the discharge current (I) Rs = 2 Pi / I 2 = 4 Ii Vdc / I 2 =

Rs 1 + (w Cs Rs )2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.6

PLASMA PROCESS CONTROL 6.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

The plasma resistance and capacitance are obtained from R = Rs + Rb C=

[

Cs 1 + (w Cs Rs )2 (w Cs Rs )2

]

Capacitively coupled plasmas have the disadvantage of high sheath voltages with low ion density and high ion bombarding energy. The ion bombarding energy cannot be controlled independent of the ion energy.17 The addition of a magnetron to the capacitively coupled plasma system is an attempt to achieve these goals. The magnetically enhanced reactive ion etcher (MERIE) is described in the section that follows. 6.2.4 Magnetic Plasma Sources Magnetrons are also used to ameliorate plasma or ion density and uniformity for the production of semiconductor devices. Typically, they are found in sputtering systems that deposit metal (aluminum or copper) onto a target. Reference 20 is explicitly used here as a source to describe the physical utilization and features of using a magnetron. The efficacy of using a magnetron is related to the efficiency between power density and etch rate. Only the ion energy across the surface of the wafer is useable for etching. This results in a volume of unusable ion energy. Increasing the power density is generally not a viable solution because with the increase in power, there is a proportional increase in heat and loss. A magnetron is used to generate a magnetic field in parallel with the wafer to confine the ion energy of the discharge. This magElectric Electron netic field is orthogonal to the electric field that is generated by field path the plasma. Figure 6.5 illustrates the path of the electron. Although the magnetic field is not shown due to the 3D visualization challenges posed by the interaction of these fields, the magnetic field for a dipole magnet can be imagined to travel into r the paper at the solid point in this figure. The electric and magnetic fields create an electron drift velocity component that traverses with a closed path radius in a direction orthogonal to both the electric and magnetic fields. This is shown with the arrow pointing to the right. The drifting electrons impinge on neutral molecules and cause additional dissociation of electrons. The closed-loop path of the electron results in an electron storage ring FIGURE 6.5 Electron path. that produces a high plasma density and limits electron mobility. The radius of the path r is proportional to the square root of the energy. The electron path is typically referred to as cycloidal. There are several commercial methods that have been employed for the previously described magnetron applications. Tokyo Electron Limited uses a dipole ring magnet assembly constructed with a plurality of magnetic segments.21 The dipole ring has a nonmagnetic material between each magnetic segment. The magnet assembly uses a circular rotation on a track around the center axis about the outer periphery of the chamber. Tylan Corporation accomplished a similar effect that uses a linear motion in place of a circular rotation for the magnets.20 Applied Materials obtained similar results with a novel approach of using electromagnets spaced around the periphery of the chamber to generate and control the magnetic field.22 Pulsing the magnets in a periodic fashion controls the magnitude and direction of the instantaneous magnetic field. Reference 23 provides an elegant description of a recent magnetron sputter reactor design from Applied Materials. For this reactor design, Ref. 24 elaborates on the three magnetrons contained in this sputter reactor design. There are two circular ring magnet assemblies that are located on the roof and inner wall of the chamber vessel. These magnets rotate about the chamber axis. The third ringshaped magnet assembly is located at the outer sidewall. The inner and outer magnet assemblies are parallel to the chamber axis and the roof magnet assembly is orthogonal to the chamber axis.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.7

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

6.7

The magnetic field components that are generated in this configuration yield the following advantageous effects—the electron losses are reduced and the plasma density increased; and metal ions are extracted from the source and their trajectories are guided toward the target. Similarly in Ref. 25, a magnetron that uses a coaxial electromagnetic coil to create a magnetic field component from the target to the wafer is described. This magnet assembly rotates around the chamber axis. The magnetron was improved in Ref. 26 with the addition of auxiliary magnets that were added to the outer periphery of the chamber. The auxiliary magnets—permanent or electromagnets— proved to draw a portion of the unbalanced magnetic field toward the wafer. This design guided more of the ionized sputter particles. Reference 27 discloses a recent magnetron design for an inductively coupled source from Tokyo Electron Limited. i The use of a stationary, axially symmetric permanent magnet assembly is described. This magnetron design was found to enhance the concentration of a high-density inductively coupled plasma by containing the plasma. 6.2.5 Inductively Coupled Plasma Versus Capacitively Coupled Plasma Reference 8 provides the following delineation between an inductively coupled discharge and a capacitively coupled discharge. The density of a capacitively coupled discharge is controlled by the amount of RF current that can pass through the sheath. It has been shown that when the plasma sheath impedance dominates, the plasma density is proportional to the square root of the plasma power for electropositive gases.17 In conclusion, the plasma efficiency decreases as the power and the sheath voltage increase. It is for this reason that an inductively coupled discharge has an advantage over capacitively coupled discharges. An inductively coupled discharge tends to be more efficient because the plasma discharge can be generated and controlled in the proximity of its use.

6.3 PROCESS CONTROL AND METROLOGY Based on the derivations for inductively and capacitively coupled sources, it becomes evident that the control of the RF source is a principal control point of the plasma source. The significant physical component of the discharge is the delivery of RF power into the plasma. For the inductively coupled source, the power absorbed by the plasma was through the induced RF current. Conversely, the power absorbed by the capacitively coupled discharge was through the induced RF voltage. It is through these interactions that the RF source controls the stability of the plasma and the processing conditions. Typically, etch rate is a parameter that is controlled for a particular process. The block diagram in Fig. 6.6 illustrates a typical architecture for a plasma chamber. The RF source is contained in the RF generator. The RF generator’s frequency must be compliant with Code of

RF metrology

RF generator Host interface

Matching network

Analysis module

Plasma chamber

Plasma metrology FIGURE 6.6

Typical plasma chamber block diagram.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.8

PLASMA PROCESS CONTROL 6.8

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

C L

L

L

L

L

C

T network FIGURE 6.7

C

L networks

C

C

PI network

Matching network circuit topology.

Federal Regulation 47, Part 18. The RF generator is typically designed for a 50-Ω load impedance. Since the impedance of the plasma and the transmission line to the chamber is not 50-Ω or matched to the impedance of the RF source, a matching network is located between the RF generator and the plasma chamber. Iin The circuit topology of the matching network A B ZG is generally a T, Π, or L network as illustrated in x = −1 x=0 Fig. 6.7. The purpose of the matching network is to maximize the power transfer from the RF VRF ZM ZL source to the plasma by matching the impedance Vin of the plasma to the impedance of the RF source. Figure 6.8 illustrates the electrical circuit of the RF source, the matching network, and the plasma. FIGURE 6.8 Plasma processing RF circuit model. ZG represents the source impedance, ZM represents the matching network impedance at a distance l from the source, and ZL represents the impedance of the plasma. Transmission line theory describes the voltage and current at a particular position in the transmission line as V ( −l ) = Ve jΒl [1 + Γ ( −l )] V jΒl I ( −l ) = e [1 − Γ ( −l )] Zo where β is the phase constant and Γ is the reflection coefficient. If Zin is defined as Zin = Z M + Z L then the voltage on the transmission line can also be described as V ( −l ) = Zin I ( −l ) = Zin

Vrf Zin + Zg

Substituting Zin = Zo

1 + Γ ( −l ) 1 − Γ ( −l )

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.9

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

6.9

reduces the voltage on the transmission line to V ( −l ) = Vrf

1 V = rf [1 + Γ ( −l )] 1 + 11+− ΓΓ (( −− ll )) 2

Accordingly the current on the transmission line to I ( −l ) =

Vrf [1 − Γ ( −l )] 2 Zo

The time-averaged power at the input is then described by 1 1 ℜ{Vin Iin} = ℜ{Zin Iin Iin} 2 2 1 1 = ℜ{V ( −l ) I ( −l )} = | V |2 [1− | Γ ( −l ) |2 ] 2 2 Zo

Pav,in = Pav,in

The reflection coefficient is zero when the load (in this case Zin) is equal to the characteristic impedance of the transmission line, Zo. When this occurs the time-averaged power at the input achieves a maximum Pav,in = Pmax =

| V |2 2 Zo

The matching network usually has at least one tunable element since the impedance range of the plasma can vary based on power, pressure conditions, and chemistry of the discharge. The tunable element(s), usually a capacitor, of the matching network adjusts the impedance of the matching network to a load impedance that is within the operating specification of the RF generator. In mathematical terms, the matching network arrives to an impedance value that is a near equivalent to the complex conjugate of the plasma impedance. This cancels the phase component difference and requires a scaling of the impedance magnitude. When the matching network is tuned to the optimal load impedance of the RF generator, the transfer of power into the discharge is maximized. The tuning operation of the matching network is accomplished by circuitry that is internal to the matching network. The circuitry of the matching network has an RF detector and associated electronics that measure the impedance magnitude and phase. These measurements are used as feedback elements to command the tunable element(s) of the matching network. Traditionally, this has been accomplished with analog and mixed signal circuitries.28 This has some limitations due to the nonlinear equations that describe the transfer of power based on impedance. A more novel approach uses a digital controller with fuzzy logic to command the tunable element.29 Today, the industry is experiencing the advent of solid-state matching networks to replace the passive elements of the traditional matching network. A matching network using a pin-diode configuration is one such example.30 Another alternative to matching the impedance of the plasma to the RF source impedance is to use a fixed match with an RF generator that has an agile frequency.31 Auto frequency tuning has the major benefits of speed, cost, and reliability by eliminating the movable tuning elements found in traditional matching networks. To use auto frequency tuning, it is necessary to incorporate a matching network with a fixed impedance between the generator and chamber. This matching network must be designed so that the process window of impedance can be tuned within a reasonable frequency range (typically ±10 percent for mid frequency and +5 percent for high frequency). The operation of auto frequency tuning generators is analogous to the operation of a tunable matching network. The tunable matching network adjusts the real and imaginary components of the impedance to a tune range within the operating specification of the RF generator. In the case of auto frequency tuning generators, the fixed match converts the real component of the impedance and the auto

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.10

PLASMA PROCESS CONTROL 6.10

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

frequency tuning generator controls the trajectory of the imaginary component of the impedance. To ensure that auto frequency tuning generators do not interfere with emergency safety, search, and rescue radio transmissions, the following frequency bands are blocked—490 to 510 kHz, 2170 to 2194 kHz, and 8354 to 8374 kHz. 6.3.1 Improvements in RF Control of Plasma The RF configuration has seen some recent modifications that have ameliorated semiconductor processing conditions and manufacturing yields. The objective of both approaches was to improve the plasma density and ion energy. The changes include the use of multiple RF frequency sources and increasing the frequency of the RF source. G. Béïque, S. Marks, J. Almerico, and P. Werbaneth from Tegal explained the benefits of dual RF frequency sources during the Plasma Etch Users Group’s monthly meeting in September 2003. Figure 6.9 was taken from their presentation and depicts the configuration of the plasma chamber. This is an inductively coupled discharge that is excited by the 13.56-MHz RF generator. The bottom electrode is biased with 450 kHz. Tegal reported that using 13.56 MHz and 450 kHz simultaneously achieved maximum ion bombardment and plasma generation efficiency. The ion energy is controlled by the low-frequency RF source. The plasma density is controlled by the high-frequency RF source. Reference 32 summarizes the work of exploring ion energy distribution for high-density plasma for three different ion masses. The experiments used a setup that replicated an actual etching configuration and focused on the effect of varying the bias frequency for inductively coupled plasma from a low frequency of 678 kHz to a high frequency of 60 MHz. For a low-frequency RF bias, the ions cross the sheath in a small fraction of the RF cycle and respond to the instantaneous sheath voltage. For higher frequencies, the sheath voltage oscillates during the period when the ions cross the sheath and respond to the average sheath voltage. The higher frequency resulted in a narrow ion energy distribution. The work concluded that ions with higher mass have narrower ion energy distribution than ions with lower mass and this relationship follows a square root of the mass of the ion. For a given ion mass, the ion energy distribution becomes narrower and increases the mean of the ion energy with the increase of the frequency of the RF bias. Pulsing the RF source has been another area of focus on improving plasma condition for semiconductor manufacturing. Pulsing typically entails the modulating of the RF power using square wave pulses.33 This provides the process engineer with two additional control variables—the pulse period and duty cycle (ratio of the on time to the off time)—over the conventional continuous-wave

Matching network

MHz supply

Wafer

Matching network

FIGURE 6.9

kHz supply

Tegal’s dual frequency chamber.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.11

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

6.11

RF source. In Ref. 34, it was discovered that higher plasma densities were achieved by selecting the appropriate modulation period. Pulsing the RF source for capacitively coupled plasma has shown to alter the ion energy of the plasma.35 Improved etch rate and control has been obtained using pulsed plasmas.36 Pulsing the plasma has also demonstrated the manufacturing capability of reducing lateral etching.37 Plasma dynamics for inductively coupled sources are described in Refs. 38–40 and for electron cyclotron resonance plasma sources in Ref. 41. The work to date for a control methodology of pulsing is based on either power or plasma impedance monitoring. Monitoring of the plasma dynamics has been achieved through a variety of instruments that include Langmuir probes, RF metrology, radiometry, inferometers, and optical emission spectroscopy.35,38–42 Reference 42 provides a summary that highlights the advantages of controlling the pulsed RF based on impedance measurements. In pulsed RF plasma, a variety of processes occur at the first stages of RF turn-on and turn-off, as illustrated in Fig. 6.10. During the transient RF turnon, the electron energy elevates above the steady state; electron and ion densities increase; and the thickness of the sheaths on the electrodes varies. At the transient power turn-off, electron energy decreases rapidly, electron and ion densities decrease, and the plasma sheaths disintegrate with the decay of electron density. These dynamics affect the plasma impedance through the changes of the bulk plasma resistance and the sheath capacitance and resistance. This infers that pulsed plasmas can be characterized by an impedance measurement. 6.3.2 RF Metrology for Plasma Chambers The following excerpt from Ref. 43 summarizes the advantages of RF metrology to control plasma processing chambers for the manufacturing of semiconductor devices. RF sensors are important because they are not intrusive, and they collect and report data in real time. This enables a fast response time to any changes that occur during processing. Radio-frequency monitors also give information about the discharge, which can be used to develop a physical understanding of the internal electrical characteristics of the plasma. At the very least, this information can be used to establish trends between the input settings and the electrical characteristics of the plasma source. A number of sensors have been employed as RF metrology in plasma processing tools. These include voltage probes, current loops, diplexers and directional couplers.19,44–49 Directional couplers typically do not have adequate directivity for effective measurement in the typical operating impedance regimes of plasma chambers.50 References 51 and 52 describe a robust voltage/current sensor design. This sensor can be configured in a coaxial line system with a fixed-characteristic impedance or a noncoaxial line system. When configured in the noncoaxial line system, the sensor is calibrated in a system that is a close replication of the final configuration. The construction of the probe is in the form of a coaxial line segment. The probe is designed with an aluminum-body outer conductor

Power

Turn-on

Turn-off

Steady state

Late afterglow

Charge density

Electron energy

Time

FIGURE 6.10

On period (ton)

+ ions electrons

Off period (toff)

− ions?

Dynamics of pulsed RF plasma.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.12

PLASMA PROCESS CONTROL SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

and a silver-plated copper inner conductor. The geometry of the inner conductor is square with chamfered corners. The material of the dielectric spacer is boron nitride. The boron-nitride dielectric and the silver-plated inner conductor are designed specifically to permit the higher operating current at higher frequencies. The square shaft of the conductor has demonstrated improved coupling for increased signal-to-noise ratio. The square shaft also increases the surface area for optimal heat transfer from the inner conductor to the body of the probe. These design features have enhanced the absolute and unitto-unit repeatability accuracy. They also permit the use of the probe in high frequencies (greater than 13.56 MHz), high-current applications without performance degradation at low frequencies, and power applications. The sensor comprises voltage and current pick-up assemblies. The voltage pick-up assembly converts the time-varying electric field created on the inner conductor to a small voltage signal representative of the line voltage(s). The current pick-up assembly converts the time-varying magnetic field created on the inner conductor to a small voltage signal representative of the line current(s). These voltage and current signals are connected to an associated analysis module. A feature-rich signal processing architecture of an analysis module for an RF impedance/power sensor is described.50 One of the significant advantages of this signal-processing architecture is its ability to autonomously track multiple RF sources. This is accomplished through a high-speed sampling and digital processing unit. The signal-processing architecture is analogous to phase lock loop; however in this case the implementation is in the form of analog and digital electronics. Figure 6.11 is evidence of the robust ability of autonomous frequency tracking in an experimental environment during severe plasma transients. In this experiment, the plasma chamber was configured with two frequency-agile RF sources. Each RF source was programmed to sweep the entire bandwidth of the respective RF source. In this case the RF sources were 2 and 27 MHz. The pressure setting of

2113173 27101470

2056665 27073700

Frequency (Hz)

6.12

2000156 27045920

1943648 27018140

1887139 26990360 20.00 FIGURE 6.11

25.00

30.00 Time (s)

35.00

Frequency tracking during plasma transients.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

40.00

04/04/2005

19:37

Page 6.13

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

Before

Cp Co

Resist Oxide

Plasma sheath

Silicon

Plasma

Cp Resist Silicon

Probe

FIGURE 6.12

6.13

After

Plasma

Plasma sheath

Probe

Oxide etch.

the chamber and power level of each source was established such that arc transients were intentionally created. The trace with more cycles for the given time period in Fig. 6.11 is the measured frequency for the 2-MHz RF source and the trace with three complete cycles is the measured frequency of the 27-MHz RF source. The discontinuities in the traces with three complete periods are correlated to the occurrence of arcs in the plasma. This demonstrates the rigid ability to maintain lock to the frequency of multiple RF sources in a worse-case environment. Also apparent is the ability to detect plasma arc transients. Extensions of arc detection include arc classification and suppression controls. Figure 6.12 illustrates before and after effects of an oxide etch. The illustration on the left in this figure shows the presence of oxide in a trench prior to initiating an etch. The circuit diagram of the capacitor-divider circuit is a simplification of the resulting change in the impedance measured by the voltage/current sensor and analysis module. As the ion bombardment penetrates the trench and removes the oxide, the impedance of the plasma varies. Monitoring the harmonics generated from the plasma has proven to be an effective method of monitoring the etch process.49,53,54 Real-time feedback control and monitoring of the impedance during the etch process has been demonstrated to yield an etch rate and endpoint.55 Figure 6.13 yields an example of polysilicon etch when monitoring the sixth harmonic of 13.56 MHz. The T1 and T2 labels on the plot indicate the etch start and Etch Trend on 6th Harmonics 1.15 1.13

BARC Etch

Mask Etch

Polyetch #1

Polyetch #2

T2

1.11 1.09 Noimalized

Geng(SMH)_CH06.qxd

1.07

T2

T1

1.05

T1

1.03 1.01 0.99 0.97 0.95 0.00

FIGURE 6.13

50.00

100.00

150.00 200.00 Time (s)

250.00

300.00

Endpoint detection.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

I V Phase Z-mag

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.14

PLASMA PROCESS CONTROL 6.14

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

etch endpoint respectively from an optical emission spectroscopy sensor. The RF signals have been normalized to illustrate that measuring multiple RF parameters can achieve a robust method of measuring the etch rate and endpoint. Analogous to controlling etch, a voltage/current sensor and the associated analysis module have proven to be an effective means of chamber excursion detection and clean optimization.48,56 Recall from Sec. 2.4 the utilization of a magnetic field to improve the density of the plasma, the magnetic field is rotated in the plane of the wafer. Figure 6.14 provides an impedance measurement from the voltage/current sensor and analysis module as evident from the characteristic change of the impedance phase. The period of the change in phase is the frequency of the rotation of the magnet system. Control of this type of measurement has been employed to control uniformity and density. These are just some applications that exemplify the inherent ability of an RF-impedance measuring system. In addition to these traditional applications, the high-speed sampling and digital processing unit has the ability to perform in more advanced applications. Some of these include the plasma stability and impedance measurements for RF-pulsing applications. These real-time measurements and analyses of process power and impedance contribute to advance process control (APC). This type of metrology has been recommended as a necessary component of an APC system.57,58 The efficacy of using a multivariate analysis method of principal components on harmonic data from an RF sensor has been proven to be a resilient approach to APC.59 6.3.3 Langmuir Probe The description that follows on how the Langmuir probe operates and how it is utilized is taken from Refs. 17 and 60. For a thorough review of this plasma sensor, the reader should consult these references. The Langmuir probe is a small-diameter cylindrical collector that is similar to a piece of wire and is inserted into the plasma. When a negative potential (with respect to the plasma potential) is applied to the probe, the probe repels negative ions and electrons and attracts positive ions. This creates a cylindrical sheath around the probe surface. The total positive charge of the sheath is equal to the negative potential applied to the probe. The induced current into the probe is restricted to the rate at which the ions arrive at the sheath edge. Decreasing the negative potentials beyond this point, the probe current is predominantly ion current. When the probe is biased to a potential that is equal to the plasma potential, the probe current is induced from the mobile electrons in the plasma. For probe

87.7 87.6

Phase (degree)

87.5 87.4 87.3 87.2 87.1 87 86.9

0

FIGURE 6.14

1

2

3

4

5 Time (s)

6

7

8

9

Phase impedance measurement for an MERIE plasma system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

10

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.15

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

6.15

bias voltages greater than the plasma potential, the probe current saturates at the electron saturation current. Traditionally used by researchers, the Langmuir probe is a valuable instrument to understand plasma physics. One example utilizing the Langmuir probe to study transformer-coupled plasma is given in Ref. 61. Reliable-process endpoint has also been achieved using the Langmuir probe.62 Surface contamination on the Langmuir probe adversely affecting its measurements has been published.63,64 6.3.4 Optical Emission Spectroscopy Optical emission spectroscopy (OES) utilizes an optical sensor to detect and measure the spectral emission from the plasma. Typically the sensors comprise a CCD image sensor and an optical filter. It has become the most widely used method for detecting oxide-etch endpoint in semiconductor manufacturing environments.65 Patent applications and grants that employ this technology for etch endpoint and rate are numerous. Though they have proven to be a viable technology; limitations of OES have been cited and justify alternative endpoint detection methods.66 The case is made that current dual damascene via etch requires exposed areas in the ranges of 2 to .5 percent and with the demands of shrinking critical dimensions, the exposed area may decrease to .2 percent. Presently the limitations encountered with OES are approximately 1 percent of the exposed oxide area.

6.4 PROPERTIES OF DRY ETCH PROCESS There are two types of methods of etching—chemical and physical. These combine to form four basic plasma processes—sputtering or physical, chemical, ion-energy-driven, and ion-enhancedinhibitor etching. Chemical etch is performed by free radicals that bombard the target with a nearuniform angular distribution. This process is characterized by high etch rates and occurs in high-pressure conditions. Physical etch is performed by the sputtering of ions and is an anisotropic process. Anisotropy is defined as the ratio of the vertical etch to the horizontal etch. With this process only a marginal amount of sidewall removal occurs. This is the only etch process that can remove nonvolatile material from the target. As compared to chemical etch, the selectivity for physical etch is low. Selectivity is the ratio of the etch rate of the insulator to the etch rate of the semiconductor.17

6.5 FUTURE TRENDS AND CONCLUSIONS To look to the future, we need to reflect on the past. In the 1980s the semiconductor industry relied on single-frequency, capacitively coupled plasmas for manufacturing. The 1990s provided an array of technology choices. Variants of ECR and inductively coupled plasma chambers were offered. During this time all major etch companies were moving toward high-density plasma chambers. Presently, the capacitively coupled chamber appears to be the mainstay. Today a large manufacturing base of plasma chambers for semiconductor manufacturing comprise the AMAT P5000 PECVD tool, LAM Rainbow and TCP series etch platforms and TEL Unity II DRM etch tool. Novellus Concept 1 & 2 PECVD tools also share a significant part of the market. There have been tremendous advances in etch capability of feature-size, selectivity, and criticaldimension control that have been accomplished by continuing to refine the chamber and its inputs. The industry will continue to be challenged with shrinking feature sizes. The present manufacturing capability of height-to-depth ratios ranges from 20:1 to as much as 60:1. The industry trend today is to increase the number and frequency of RF sources. Time will tell if this evolution of science will yield better control of the plasma and achieve the expected manufacturing objectives.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.16

PLASMA PROCESS CONTROL 6.16

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

REFERENCES 1. Hittorf, W., “Wiedemannus Ann Physics,” Vol. 21, pp. 90–139, 1884. 2. MacKinnon, K. A., The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science, Vol. 8, pp. 605–616, 1929. 3. Gudmundsson, J. T., and M. A. Lieberman, “Magnetic induction and plasma impedance in a cylindrical inductive discharge,” Plasma Sources Science Technology, Vol. 6, pp. 540–550, 1997. 4. Thomson, J. J., Philosophical Magazine, Vol. 32, pp. 321–336, 1891. 5. Thomson, J. J., Philosophical Magazine, Vol. 32, pp. 445–464, 1891. 6. Tykocinski-Tykociner, J., Philosophical Magazine, Vol. 13, pp. 953–963, 1932. 7. Piejak, R. B., V. A. Godyak, and B. M. Alexandrovich, “A simple analysis of an inductive RF discharge,” Plasma Sources Science Technology, Vol. 1, pp. 179–186, 1992. 8. Keller, J. H., “Inductive plasmas for plasma processing,” Plasma Sources Science Technology, Vol. 5, pp. 166–172, 1996. 9. Keller, J. H., J. C. Forster, and M. S. Barnes, “Novel radio-frequency induction plasma processing techniques,” Journal Vacuum Science Technology A, Vol. 11, No. 5, pp. 2487–2491, 1993. 10. El-Fayoumi, I. M., and I. R. Jones, “The electromagnetic basis of the transformer model for an inductively coupled RF plasma source,” Plasma Sources Science Technology, Vol. 7, pp. 179–185, 1998. 11. Colpo, P., R. Ernst, and F. Rossi, “Determination of the equivalent circuit of inductively coupled plasma sources,” Journal of Applied Physics, Vol. 85, No. 3, pp. 1366–1371, 1999. 12. Godyak, V. A., R. B. Piejak, and B. M. Alexandrovich, “Electrical characteristics and electron heating mechanism of an inductively coupled argon discharge,” Plasma Sources Science Technology, Vol. 3, pp. 169–176, 1994. 13. Turner, M. M., and M. A. Lieberman, “Hysteresis and the E to H transition in radio frequency inductive discharge,” Plasma Sources Science Technology, Vol. 8, pp. 313–324, 1999. 14. Piejak, R. B., V. A. Godyak, and B. M. Alexandrovich, “The electric field and current density in a low pressure inductive discharge measure with different B-dot probes,” Journal of Applied Physics, Vol. 81, No. 8, pp. 3416–3421, 1997. 15. El-Fayoumi, I. M., and I. R. Jones, “Measurement of the induced plasma current in a planar coil, low frequency, RF induction plasma source,” Plasma Sources Science Technology, Vol. 6, pp. 201–211, 1997. 16. Holber, W. M., Handbook of Ion Beam Technology: Principles, Deposition, Film Modification and Synthesis, Park Ridge, NJ: Noyes, 1989, p. 21. 17. Lieberman, M. A., and A. J. Lichtenberg, Principles of Plasma Discharges and Materials Processing, New York: Wiley, 1994. 18. Hargis, Jr., P. J., et al., “The gaseous electronics conference radio frequency reference cell: A defined parallel plate radio system for experimental and theoretical studies of plasma processing,” “The Review of Scientific Instruments,” Vol. 65, No. 1, pp. 140–154, 1994. 19. Sobolewski, M. A., “Current and voltage measurements in the gaseous electronics conference RF reference cell,” Journal of Research of the National Institute of Standards and Technology, Vol. 100, No. 4, pp. 341–351, 1995. 20. Bobbio, S. M., “A review of magnetron etch technology,” Proceedings of SPIE Int. Society of Optical Engineering, Vol. 1185, pp. 262–277, 1989. 21. Arami, J., et al., Plasma Process Device, US Patent 6014943, 2000. 22. Shan, H., et al., Magnetically Enhanced Plasma Chamber with Non-uniform Magnetic Field, US Patent 6113731, 2000. 23. Wang W. D., et al., Auxiliary Electromagnets in a Magnetron Sputter Reactor, US Patent 6730196, 2004. 24. Subramani, A., et al., Magnetron with a Rotating Center Magnet for a Vault Shaped Sputtering Target, US Patent 6406599, 2002. 25. Wang, W. D., Coaxial Electromagnet in a Magnetron Sputtering Reactor, US Patent 6352629, 2002. 26. Ding, P., Magnet Array in Conjunction with Rotating Magnetron for Plasma Sputtering, US Patent 6610184, 2003.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.17

PLASMA PROCESS CONTROL PLASMA PROCESS CONTROL

6.17

27. Brcka, J., Ring-shaped High-density Plasma Source and Method, US Patent 6523493, 2003. 28. Keane, A. R., and S. E. Hauer, Automatic Impedance Matching Apparatus and Method, US Patent 5,195,045, 1993. 29. Harnett, S., Fuzzy Logic Tuning of RF Matching Network, US Patent 5842154, 1997. 30. Brounley, R. W., Solid State Plasma Chamber Tuner, US Patent 5473291, 1995. 31. Wilbur, J., Ratiometric Autotuning Algorithm for RF Plasma Generator, US Patent 6020794, 2000. 32. Abraham, I. C., et al., “Ion energy distributions versus frequency and ion mass at the RF-biased electrode in an inductively driven discharge,” Journal Vacuum Science Technology A, Vol. 20, No. 5, pp. 1759–1768, 2002. 33. Vincent, T. L., and R. L. Laxminarayan, “Approach for control of high-density plasma reactors through optimal pulse shaping,” Journal Vacuum Science Technology A, Vol. 20, No. 5, pp. 1722–1732, 2002. 34. Ashida, S., C. Lee, and M. A. Lieberman, “Spatially averaged (global) model of time modulated high density argon plasmas,” Journal Vacuum Science Technology A, Vol. 13, No. 5, pp. 2498–2507, 1995. 35. Booth, J. P., G. Cunge, and N. Sadeghi, “The transition from symmetric to asymmetric discharges in pulsed 13.56 MHz capacitively coupled plasmas,” Journal of Applied Physics, Vol. 82, No. 2, pp. 552–560, 1997. 36. Boswell, R. W., and R. K. Porteous, “Etching in a pulsed plasma,” Journal of Applied Physics, Vol. 62, No. 8, pp. 3123–3129, 1987. 37. Jung, C. O., et al., “Advanced plasma technology in microelectronics,” Thin Solid Films, 341, pp. 112–119, 1999. 38. Hebner, G. A., and C. B. Fleddermann, “Characterization of pulse-modulated inducively coupled plasmas in argon and chlorine,” Journal of Applied Physics, Vol. 82, No. 6, pp. 2814–2821, 1997. 39. Malyshev, M. V., et al., “Dynamics of pulsed-power chlorine plasmas,” Journal of Applied Physics, Vol. 86, No. 9, pp. 4813–4820, 1999. 40. Cunge, G., et al., “Characterization of the E to H transition in a pulsed inductively coupled plasma discharge with coil geometry: Bi-stability and hysteresis,” Plasma Sources Science Technology, Vol. 8, pp. 576–586, 1999. 41. Samukawa, S., and H. Ohtake, “Pulse-time modulated electron cyclotron resonance plasma discharge for highly anisotropic and charge-free etching,” Journal Vacuum Science Technology A, Vol. 14, No. 6, pp. 3049–3058, 1996. 42. Overzet, L. J., and F. Y. Leong-Rousey, “Time resolved power and impedance measurement of pulsed radio frequency discharge,” Plasma Sources Science Technology, Vol. 4, pp. 432–443, 1995. 43. Miranda, A. J., and C. J. Spanos, “Impedance modeling of a Cl2/He plasma discharge for a very large scale integrated circuit production monitoring,” Journal Vacuum Science Technology A, Vol. 14, No. 3, pp. 1888–1893, 1996. 44. Andries, B., G. Ravel, and L. Peccoud, “Electrical characterization of radio-frequency parallel-plate capacitively coupled discharges,” Journal Vacuum Science Technology A, Vol. 7, No. 4, pp. 2774–2783, 1989. 45. Godyak, V. A., and R. B. Piejak, “In situ simultaneous radio frequency discharge power measurements,” Journal Vacuum Science Technology A, Vol. 8. No. 5, pp. 3833–3837, 1990. 46. Braithwaite, N. St. J., “Internal and external electrical diagnostics of RF plasmas,” Plasma Sources Science Technology, Vol. 6, pp. 133–139, 1997. 47. Kawata, H., et al., “Power measurements for radio-frequency discharges with a parallel-plate-type reactor,” Journal of the Electrochemical Society, Vol. 145, No. 5, pp. 1701–1707, 1998. 48. Steffens, K. L., and M. A. Sobolewski, “Planar laser-induced fluorescence of CF2 in O2/CF4 and O2/C2F6 chamber cleaning plasmas: Spatial uniformity and comparison to electrical measurements,” Journal Vacuum Science Technology A, Vol. 17, No. 2, pp. 517–527, 1999. 49. Law, V. J., et al., “Remote-coupled sensing of plasma harmonics and process end point detection,” Surface Engineering, Surface Instrumentation and Vacuum Technology, Vol. 57, pp. 351–364, 2000. 50. Coumou, D. J., “Advanced RF metrology for plasma process control,” Semiconductor International, 2003. 51. Gerrish, K. S., and D. F., Vona, Jr., Baseband V-I Probe, US Patent 5770922, 1998. 52. Coumou, D. J., RF Power Probe Head with a Thermally Conductive Bushing, US Patent 6559650, 2003. 53. Ukai, K., and K. Hanazawa, “End-point determination of aluminum reactive ion etching by discharge impedance monitoring,” Journal Vacuum Science Technology, Vol. 16, No. 2, pp. 385–387, 1979.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH06.qxd

04/04/2005

19:37

Page 6.18

PLASMA PROCESS CONTROL 6.18

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

54. Kanoh, M., M. Yamage, and H. Takada, “End-point detection of reactive ion etching by plasma impedance monitoring,” Japan Journal of Applied Physics, Vol. 40, No. 3a, pp. 1457–1462, 2001. 55. Bushman, S., T. F. Edgar, and I. Trachtenberg, “Radio frequency diagnostics for plasma etch systems,” Journal of the Electrochemical Society, Vol. 144, No. 2, pp. 721–731, 1997. 56. Hanson, E., H. Benson-Woodward, and M. Bonner, “Optimising CVD through RF metrology,” Plasma Monitoring, pp. 25–28, 1999. 57. Zhao, D. W., and C. Spanos, “Towards a complete plasma diagnostic system,” IEEE Conference Proceedings for the International Symposium on Semiconductor Manufacturing, pp. 137–140, 2001. 58. Schneider, C., L. Pfitzner, and H. Ryssel, “Integrated metrology: An enabler for advanced process control (APC),” Proceeding of SPIE, Vol. 4406, pp. 118–130, 2001. 59. Koh, A. T. -C., N. F. Thornhill, and V. J. Law, “Principal component analysis of plasma harmonics in endpoint detection of photoresist stripping,” IEEE Electronic Letters, Vol. 35, No. 16, pp. 1383–1385, 1999. 60. Mott-Smith, H. M., and I. Langmuir, “The theory of collectors in gaseous discharges,” Physical Review, Vol. 28, pp. 727–763, 1926. 61. Malyshev, M. V., et al., “Langmuir probe studies of a transformer coupled plasma, aluminum etcher,” Journal Vacuum Science Technology A, Vol. 17, No. 2, pp. 480–492, 1999. 62. Murete de Castro, R., et al., “End-point detection of polymer etching using langmuir probes,” IEEE Transactions on Plasma Science, Vol. 28, No. 3, pp. 1043–1049, 2000. 63. Thomas, T. L., and E. L. Battle, “Effects of contamination on langmuir probe measurements in Glow discharge plasmas,” Journal of Applied Physics, Vol. 41, No. 8, pp. 3428–3432. 64. Szuszczewicz, E. P., and J. C. Holmes, “Surface contamination of active electrodes in plasmas: Distortion of conventional langmuir probe measurements,” Journal of Applied Physics, Vol. 46, No. 12, pp. 5134–5139, 1975. 65. Biolsi, P., et al., “An advanced endpoint detection solution for <1% open areas,” Solid State Technology, Vol. 39, No. 12, p. 59, 1996. 66. Hudson, E. A., and F. C. Dassapa, “Sensitive end-point detection for dielectric etch,” Journal of the Electrochemical Society, Vol. 148, No. 3, pp. C236–C239, 2001.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 7

VACUUM TECHNOLOGY Peter Biltoft Lawrence Livermore National Laboratory Livermore, California

7.1 VACUUM TECHNOLOGY OVERVIEW 7.1.1 What Is Vacuum The environmental condition called vacuum is created when the pressure of a gas is reduced compared to atmospheric pressure. On earth we typically create a vacuum by connecting a pump capable of moving gas to a relatively leak-free vessel. Through operation of the gas pump, the number of gas molecules per unit volume is decreased within the vessel. As soon as one creates a vacuum, natural forces (in this case entropy) work to restore equilibrium pressure. The practical effect of this is that gas molecules attempt to enter the evacuated space by any means possible. It is useful to think of vacuum in terms of a gas at a pressure below atmospheric pressure. In even the best vacuum vessels ever created, there are approximately 3,500,000 molecules of gas per cubic meter of volume remaining inside the vessel. The lowest pressure environment known is in interstellar space where there are approximately four molecules of gas per cubic meter. 7.1.2 A Very Brief History of Vacuum Technology The recorded history of vacuum dates back to 150 B.C. Hero of Alexandria wrote Pneumatias* in which the function of siphons and pumps were discussed. Advances in the basic understanding of the behavior of gases took place in Europe between A.D. 1500 and 1800. Notably, Galileo Galilei studied the function of pumps, Evangelista Torricelli studied both pressure gauges (the barometer) and gas pumps, and Otto von Guericke produced pumps specifically designed for creating vacuum. The Englishman Robert Boyle published his scientific findings on the behavior of gases as a function of pressure. Devices invented in the nineteenth century such as the light bulb, x-ray tube, and cathode ray tube required reliable methods for producing, measuring, and maintaining vacuum and provided the motivation for the development of better vacuum equipment. As early as 1936 vacuumtube integrated circuits were built. The growing electronics industry, the Manhattan Project, and exploration of outer space provided the drive for many of the advancements in vacuum technology made between the 1930s and today, including the development of the turbomolecular pump, the ion pump, and the partial-pressure analyzer.

*

Source: www.avs.org/information/timeline.pdf

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

7.1

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.2

VACUUM TECHNOLOGY 7.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

TABLE 7.1 Atmospheric Pressure Expressed in a Set of Units Psi

torr

mBar

Pa

Kg/cm3

inches of Hg

14.7

760

1013

101,300

1.033

29.92

7.1.3 The Composition of Atmospheric Gases The air we breathe is composed of approximately 78 percent nitrogen and 20.1 percent oxygen, the balance being argon, carbon dioxide, water vapor, and other trace gases. Dalton’s law of partial pressure describes the relationship between the total pressure and the partial pressures of gases in a gaseous mixture. i

Ptot = ∑ Pi 1

where Ptot = total pressure of all gases in the mixture Pi = partial pressure of gas i At sea level the approximate pressure the atmosphere exerts on all surfaces it contacts is 14.7 pounds per square inch (psi). Other units of measurement used include the torr, mBar, and pascal (Pa). Unit conversion calculators for pressure are available on the following website: http://www.avs.org/ and in Table 7.1. 7.1.4 Typical Applications of Vacuum Technology Vacuum technology is essential to the microelectronics industry as many of the processes involved in the fabrication of microcircuits require a controlled environment in which thin films can be deposited with minimal interference from atmospheric gas molecules. Other industries that rely on vacuum technology include the food processing and pharmaceutical industries (products are freeze dried under vacuum).

7.2 METHODS FOR MEASURING SUBATMOSPHERIC PRESSURE 7.2.1 Force Displacement Gauges These pressure gauges rely on the physical displacement of a solid or liquid surface by an applied pressure as a means to measure the magnitude of the applied pressure. This family of pressure gauges will give an accurate reading of pressure within their range of operation for all gases independent of the composition of the gas. As such these gauges are referred to as being gas species insensitive. Liquid Level Barometer. One of the earliest pressure gauges developed, the water barometer and later the mercury barometer were used to measure the pressure of the earth’s atmosphere. Early barometers were made by filling a long glass tube open at only one end (the tube being approximately 33 ft long if water was the fluid being used and approximately 30 in long for mercury), capping the open end of the tube, inverting the tube and placing the capped end under the surface of the same liquid used to fill the tube in a secondary container, and then removing the cap. The column of liquid inside the inverted tube would drop under the force of gravity until the pressure on the top surface of the liquid in the secondary container was equal to the gravitational load of the column of liquid in the inverted tube. As the external atmospheric pressure changed, the height of the supported

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.3

VACUUM TECHNOLOGY VACUUM TECHNOLOGY

7.3

column of liquid in the barometer would be observed to change. A reproduction of the barometers made in the 1600s is shown on the following website: http://www.barometers.com/torricel.htm. The measurement of pressure by this method is accurate only to approximately +/− 1 torr. U-Tube Manometer. Developed following the liquid barometer, the U-tube manometer allows one to measure pressure in two vessels or between a vessel and atmospheric pressure. The difference in the heights of liquid in the U tube’s two columns provides a direct reading of the pressure difference in the two sides of the U tube. Measurement of pressure by this method is accurate only to approximately +/− 1 torr. McLeod Gauge. The McLeod gauge was developed to extend the range of pressures that could be measured using liquid-displacement gauges. In this device, a known volume of gas is isolated from the vacuum vessel under study by tipping the McLeod gauge such that liquid mercury traps the gas in a bulb of known volume. As the McLeod gauge is turned upright, the trapped gas is compressed to a known amount and the pressure of the compressed gas is measured by comparing the levels of mercury in the tubes of the device and applying Boyle’s law (P1 × V1 = P2 × V2). Pressure readings using a McLeod gauge can be accurate to pressures as low as 10−7 torr. Bourdon-Tube Gauge. This gauge design uses the elastic deformation of a thin-walled metal tube to sense pressure and display on a circular dial. The sensing element is not unlike a popular party favor that unravels as one exhales into the mouthpiece. The interior of the Bourdon tube is connected to the interior volume of a vacuum vessel. As the pressure in the vessel increases, the Bourdon tube responds by elastically deforming. This motion is translated into the rotation of a dial indicator on the gauge face. Diaphragm Gauge. This gauge design utilizes the elastic deformation of a diaphragm to measure pressure. As the pressure inside the gauge tube is reduced, the diaphragm is elastically deformed and this deformation is translated via an electrical signal or mechanical mechanism to a pressure reading. Gauges of this type can typically read pressure from atmospheric down to 1 torr. 7.2.2 Capacitance Manometers The capacitance manometer gauge contains a diaphragm that is elastically deformed as pressure in the gauge tube changes. This diaphragm is one electrode of a capacitor, and as the diaphragm is displaced relative to a fixed electrode, the capacitance of the assembly changes, yielding an electrical signal that can be used to infer pressure. These gauges are referred to as being gas species insensitive. Capacitance manometers are typically manufactured to accurately measure pressure across a span of three to four decades below the rated pressure. For example, a 1000-torr capacitance manometer can typically read pressures as low as 0.5 torr with an accuracy of +/− 0.25 percent. Additional accuracy can be obtained if the gauge is equipped for temperature stabilization. 7.2.3 Thermal Transfer Gauges The property of thermal conductivity of a gas is utilized in this family of gauges to infer the pressure of the gas being measured. The thermal conductivity of a gas is a function of its molecular weight and other characteristics, therefore pressure gauges based on thermal conductivity must be calibrated for the gas of interest. These gauges are referred to as being gas species sensitive. Thermocouple Gauge. This gauge uses a thermocouple junction to measure the temperature of a wire heated by an applied constant electric current that is exposed to the environment of the vacuum vessel interior. As pressure is reduced in the thermocouple gauge tube interior, fewer gas molecules per unit time are available to remove heat from the thermocouple gauge heated filament. The temperature rise in the filament of the gauge tube is sensed by the thermocouple. This signal is sent to the gauge controller that computes the corresponding pressure based on an algorithm in the controller for a specified gas.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.4

VACUUM TECHNOLOGY 7.4

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Pirani Gauge. The Pirani gauge uses two heated electrodes, each made from platinum, to sense the pressure inside the gauge tube. One of the electrodes is the reference and is encapsulated in an evacuated glass tube, and the other is the sensor enclosed in a similar glass envelope that is open to the interior of the Pirani-gauge tube volume. These two electrodes are connected to a Wheatstone bridge circuit. As the pressure in the Pirani gauge tube decreases, the temperature of the sensor filament increases due to fewer collisions with gas molecules. The electrometer in the Wheatstone bridge circuit senses the change in resistance of the sensor filament and increases the current to that leg of the circuit to maintain the current balance in the Wheatstone bridge. The current applied to the sensor filament is used to infer pressure. The typical operating range for a Pirani gauge is from approximately 1 torr down to 10−5 torr. Convection-Enhanced Pirani Gauge. In this gauge technology, the range of a typical Pirani gauge is extended by adding a resistively heated coil that creates an environment in which induced convection occurs in the viscous flow regime. Under these conditions the range of operations of the gauge is from atmospheric pressure down to approximately 1 mtorr. 7.2.4 Ionization Gauges Gauges that infer pressure from ionization events are gas species sensitive. Hot Cathode Ionization Gauge. The basic hot cathode ionization gauge has three electrodes—an electron emitter (often referred to as the filament), an electron collector (referred to as the grid), and the ion collector (referred to as the cathode). Following the evacuation of the internal volume of the hot cathode ionization gauge tube to a pressure of less than 10−4 torr, current is provided by the gauge controller to the filament that becomes heated to a temperature of approximately 2000°C. At this operating temperature the tungsten or thoria coated iridium filament glows white hot and emits electrons. These electrons are electrostatically attracted to the electron collector that has a positive bias of approximately 150 to 180 V dc. En route to the electron collector, these electrons are likely to collide with neutral gas molecules inside the gauge tube body. These collisions often result in the ejection of an electron (or two) from the gas molecules, resulting in the creation of ionized gas molecules. These ionized gas molecules are electrostatically attracted to the ion collector by a bias applied to it by the gauge controller. As ionized molecules impinge upon the ion collector, they extract an electron to become neutral once again. This extracted current (ion current) is used to infer pressure. Two factors that influence the observed reading for a specific gas species are the physical size of the gas molecule (cross section) and its ionization potential. Cold Cathode Ionization Gauge. As with the hot cathode ionization gauge, the cold cathode gauge must be internally evacuated to a pressure of less than 10−4 torr prior to operation. In the cold cathode gauge, a high voltage (up to approximately +6 kV) is applied to the anode inside the gauge. This bias causes spontaneous electron emission from the cathode inside the cold cathode gauge tube body. These electrons traversing the space between the anode and cathode can strike neutral gas molecules and may create gas-phase ions. These ions will move under the applied bias toward the cathode. Once the ions impact the cathode, they will extract an electron and result in a net ion current that may be used to infer pressure inside the gauge tube. Often a strong permanent magnet is placed outside the cold cathode gauge tube body to cause the electrons to travel in a helical path, thus increasing the probability of an impact with a gas-phase molecule. A variety of designs for cold cathode gauge tubes are commercially available including an inverted magnetron design. 7.2.5 Partial Pressure Measurement It is often useful to know not only the total pressure of gases remaining in a vacuum vessel after evacuation, but also the composition of the gas mixture and the relative amounts of each gas species in the mixture. Partial pressure analysis (PPA), also known as residual gas analysis (RGA), is the method used

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.5

VACUUM TECHNOLOGY VACUUM TECHNOLOGY

7.5

to obtain this kind of information. Most commercial PPAs have three functional components—an ionizer, a mass selector, and a detector. In the ionizer, neutral gas molecules that randomly enter the detector inlet are bombarded with energetic electrons that have sufficient energy to ionize the gas molecules. In addition to ionizing, the energetic electrons may break the gas molecules into fragments consisting of one or more of the atoms in the original molecule. These fragments are often also ionized. All the gasphase ions created in the ionizer are electrostatically attracted to the mass selector by an applied electric field. Based on the mass and charge (single or multiple) of the ion, its trajectory through the magnetic field of the mass selector will determine if the ion completes its journey all the way to the charged particle detector to be counted. Ions that reach the detector extract one or more electrons at the detector thus creating a current that is a function of the number and charge (single or multiple) of the ions impacting the detector. In practice, the control system for the PPA creates a set of operating conditions (accelerating voltage for the ions entering the mass selector and magnetic field strength of the mass selector) such that at any one time only one mass-to-charge ratio (M/z) is allowed to pass through the mass selector and continue to the detector to be counted. Ions having an M/z other than the value prescribed by the mass selector are neutralized or otherwise prevented from being counted by the detector. After a signal for a specified M/z has been collected, the controller will adjust the operating parameters of the PPA for another M/z and will collect data for ions having this new M/z. In this manner the PPA scans through a range of M/z and records data for each ionized gas species. Data from the PPA are typically plotted as detector current as a function M/z.

7.3 METHODS FOR CREATING A VACUUM 7.3.1 Primary Vacuum Pumps These pumps are used for reducing pressure in a vacuum vessel from an initial state of atmospheric pressure (760 torr) to a reduced pressure (typically in the range of 10 mtorr). The principles of operation and operating ranges for a variety of commercially available pumps are covered in the following subsections. Oil Sealed Rotary Vane Mechanical Pumps. These pumps move gases by isolating a small volume of gas from the vacuum system, compressing this isolated volume to atmospheric pressure, and then exhausting this gas to the atmosphere. The mechanisms of the oil sealed rotary vane pump include a rotor with sliding vanes, a stator, inlet and exhaust ports, a means for rotating the stator, and the pump oil. In operation, the rotor, which is smaller in diameter than the bore of the stator and offsets concentrically from the stator bore, is caused to rotate by the drive mechanism. As the rotor spins within the stator, the sliding vanes maintain intimate contact with the inside surface of the rotor. As a sliding vane passes by the pump’s inlet orifice that connects to the bore of the stator, a crescent-shaped volume of increasing size is created by the surfaces of the rotor, stator, and sliding vane. The oil helps to create a seal between the rotor, stator, and sliding vane. As the rotor continues to rotate, the next sliding vane passes by the pump’s inlet port. As this happens, the gas, which has expanded into the crescent-shaped volume, is isolated from the vacuum system. Continued rotation of the rotor causes the crescent-shaped volume to reduce in size, thus compressing the isolated gas. Compression continues until the pressure is just above atmospheric pressure, and the compressed gas is released to the atmosphere through an exhaust valve and port. Each rotation of the rotor continues to isolate, compress and exhaust gas in this manner to reduce pressure at the inlet of the pump. The oil in pumps of this type, in addition to forming a tight seal, serves to remove the heat generated by compression of gas to lubricate the sliding surfaces of the pump and to help remove wear particles and other debris during maintenance cycles. Dry Pumps Diaphragm Pumps. In these pumps, a diaphragm (usually made from thin stainless steel or polymer sheet) is flexed by the rocking motion of an eccentric connecting rod and rotating shaft.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.6

VACUUM TECHNOLOGY 7.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

The motion of the diaphragm opens an inlet port, isolates a volume of gas, compresses the gas, and then expels this gas to the atmosphere. These pumps are available as multiple stage units that can attain pressures as low as 1 torr. Diaphragm pumps are well suited for intermittent-use applications and can be oil-free. Scroll Pumps. In this pump design there are two interleaved helical scrolls—one that is stationary and one that moves in a circular oscillation relative to the stationary scroll. During each oscillation of the moving scroll, a crescent-shaped volume is created at a port connected to the pump inlet. As oscillation of the moving scroll continues, the crescent-shaped volume increases in size, thus locally reducing pressure and gas flows into this volume from the pump inlet. With further travel of the oscillating scroll, the volume of gas drawn into the crescent-shaped volume is isolated from the pump inlet and is compressed. In the last stage of the pump cycle, the size of the crescent-shaped volume is reduced, compressing the gas to slightly above atmospheric pressure and the gas is exhausted through a spring-loaded valve. Scroll pumps use no lubricants in the swept volume and are well suited for use in primary evacuation of vacuum vessels and load vacuum locks. Screw Pumps. The concept of moving fluids using a screw mechanism dates back over 2000 years and is attributed to Archimedes. In the modern implementation of this design for vacuum applications, two parallel counter-rotating close-tolerance screws are fitted within a stator housing. As the screws rotate at approximately 6000 rpm, gas is drawn into the pump inlet and forced along the axis of the pump by the screw threads. Most of the compression occurs at the exhaust end of the pump and gas temperatures can rise to 300°C. The screws of these pumps are often coated with Teflon (PTFE) to reduce friction and to protect the base metal of the pumps’ internal components from chemical attack by the gases being pumped. Screw pumps are used for primary evacuation of a vessel from atmospheric pressure to a base pressure of approximately 10 mtorr. Sorption Pumps. Sorption pumps remove gases from a vacuum vessel by cryosorption and cryocondensation. These pumps typically consist of an aluminum cylinder internally filled with a sorbent such as zeolite. The exterior of the pump body is cooled to below room temperature often through immersion in a cryogenic fluid such as liquid nitrogen. The cooled sorbent material will cryocondense gases that have a boiling point above that of liquid nitrogen; other gases are cryosorbed onto the very fine pore structure of the zeolite. In either case, the gas molecules entering the cryosorption pump are effectively removed from the vacuum vessel thus reducing pressure in the vessel. Gases not efficiently pumped using a cryosorption pump are helium, hydrogen, and neon. Sorption pumps are used for primary evacuation of a vessel from atmospheric pressure to a base pressure of approximately 100 mtorr. 7.3.2 Secondary Vacuum Pumps Secondary vacuum pumps are used to further reduce pressure in a vacuum vessel following the primary evacuation from 760 torr to approximately 10 mtorr. Secondary vacuum pumps if operated correctly can routinely achieve pressures in the range of 10−8 torr and with extra care and good vessel design, pressures as low as 10−11 torr. Momentum Transfer Pumps. Momentum transfer vacuum pumps reduce pressure in a vacuum vessel by compressing gas and expelling it to the inlet of a primary vacuum pump that further compresses the gas and expels it to the atmosphere. During operation, momentum transfer pumps require the pressure at their exhaust port (also called the foreline) to be maintained at a pressure below their critical foreline pressure. The value of the critical foreline pressure is a function of pump design; manufacturers clearly state the value of the critical foreline pressure for each pump in the published specifications. Oil-Vapor Diffusion Pumps. In the oil-vapor diffusion pump, a supersonic-speed jet of vapor is created by controlled boiling of the pump fluid inside the pump body. The oil vapor rising up the internal stack of the diffusion pump body is forced out of jets that are directed downward and toward

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.7

VACUUM TECHNOLOGY VACUUM TECHNOLOGY

7.7

the inner surface of the water-cooled pump body. Gas molecules that randomly enter the diffusion pump inlet are intercepted by the high-speed oil vapor jet. This collision with a high-speed and relatively high-molecular-weight oil vapor molecule produces a net downward trajectory for the affected gas molecule. Through the use of multiple stages of jets, gas molecules are compressed and forced to the foreline port of the diffusion pump. At the foreline, sufficient pumping speed applied by the primary roughing pump (in this case functioning as the foreline pump) causes the gas ejected from the diffusion pump foreline to be compressed and expelled to the atmosphere. Often, a liquid nitrogen cold trap is installed at the inlet of the diffusion pump to reduce the amount of pump oil that can migrate from the diffusion pump into the vacuum vessel. The operating range of most commercial diffusion pumps is from 10−4 to 10−10 torr. Turbomolecular Pumps. In turbomolecular vacuum pumps, the random trajectory of gas molecules entering the pump inlet is influenced by the high-velocity surfaces of the rotating turbine blades. Gas molecules impacted by the blades stay on the surface of the blades for a brief period called the residence time. During this period, gas molecules lose any directional identity they had and assume the trajectory of the blade (not unlike a bug interacting with the windshield of a car traveling at 60 mi/h!). At the end of the residence time, gas molecules leave the surface of the turbine blade following the Cosine Law. According to this law, gas molecules are most likely to leave a surface in a direction normal to the plane of the surface and are least likely to follow a trajectory parallel to the surface. The combination of these two effects cause gas molecules to be forced from the inlet of the turbomolecular pump to the exhaust. Most modern turbomolecular pumps are of the axial flow design, which bears similarity to the engines on commercial jet aircraft. The rotors of most turbomolecular vacuum pumps are precision machined and carefully balanced for operation at rotational velocities ranging from 30,000 to 90,000 RPM depending on the pump size and model. Rotors of turbo pumps often are designed with several “stages.” At the inlet of the pump, the rotor blades are wide, have a steep pitch, and form a relatively open blade structure. This design is optimized for high pumping speed at the pump inlet with relatively modest compression. At the middle of the rotor, blades are often more closely spaced, and the pitch of the blades is reduced compared to blades at the inlet. At the output or exhaust of the turbo pump, the blades are very closely spaced and the pitch of the blades is optimized to achieve high compression of gas and relatively modest pumping speed. The critical foreline pressure of many turbomolecular pumps is approximately 100 mtorr. A suitable foreline pump is required for proper operation of a turbo pump. Some turbo pumps have an integrated molecular drag stage that further compresses the gas before exhausting it to the foreline of the pump. These hybrid pumps are often called turbo-drag pumps. The critical foreline pressure of many commercial turbo-drag pumps can be as high as 1 torr, allowing for evacuation of the foreline by a diaphragm pump. In either design, care should be taken to prevent objects from entering the inlet of a turbo pump during operation. Were this to occur, almost certainly the pump would be damaged, and in some cases a hazard to personnel would be created. Gas Capture Pumps. Unlike the momentum transfer pumps discussed previously, gas capture pumps reduce pressure in a vacuum vessel by removing gas molecules from the gas phase. In cryogenic pumps, gas molecules are cryocondensed or cryosorbed, while in sputter-ion pumps, gas molecules are chemically reacted to form solid by-products or are otherwise immobilized. Cryogenic Vacuum Pumps. There are generally two types of mechanisms used in cryogenic vacuum pumps—direct cooling via the use of cryogenic liquids or cooling by a mechanical compressor. One of the oldest cryogenic pump designs is the Meissner coil. In this design a helical coiled tube (usually copper) is placed inside the vacuum vessel, both ends of the helical coil pass through and are tightly sealed to a flange attached to the vacuum vessel. After primary evacuation of the vacuum vessel to a pressure of approximately 100 mtorr, liquid nitrogen is flowed through the inside of the copper coil. Gas molecules randomly striking the cooled surface of the Meissner coil will be cryocondensed if the gas species has a boiling point above that of liquid nitrogen. Gas species with boiling points below that of liquid nitrogen will be removed from the gas phase for a residence time that is a function of the temperature of the Meissner coil and the molecular weight of the gas species.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.8

VACUUM TECHNOLOGY 7.8

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Sputter-Ion Pumps. These pumps reduce the pressure inside a vacuum vessel by removing molecules from the gas phase. There are three methods by which sputter-ion pumps remove gas molecules from a vacuum vessel—gettering, ion burial, and physical burial. Gettering is a chemical process in which a gas molecule reacts with an active metal to form a solid product. In most sputterion pumps, the active metal that is utilized is titanium. During operation of the sputter-ion pump, a thin film of titanium is deposited onto the internal surfaces of the pump. Titanium is a chemically reactive metal that will readily react with atmospheric gases to form stable solid compounds such as titanium dioxide, titanium hydride, and titanium nitride. In addition to gettering, sputter-ion pumps can also remove noble gases such as helium, neon, argon, krypton, xenon and radon. These gases tend not to form chemical compounds with reactive metals. During operation of the sputter-ion pump, all gases including the noble gases may be ionized by the electrons traversing the space between the cathode and anode. If a collision between an electron and a gas molecule occurs, the gas molecule may become ionized. This ionized gas molecule will then move under the applied electric field of the pump toward the cathode. Upon impact with the cathode, the ion will lose its electric charge and may have sufficient kinetic energy to become implanted within the bulk of the cathode. This process is called ion implantation. It should be noted that as pump operation continues, the exposed surface of the cathode will continue to be eroded and some of the implanted gas molecules may be liberated. The last process by which sputter-ion pumps can remove molecules from the gas phase is called physical burial. In this process gas molecules that land on the internal surfaces of the sputter-ion pump body and remain on that surface for a residence time may be overcoated with titanium.

7.4 VACUUM SYSTEM COMPONENTS 7.4.1 Flanges with Demountable Seals Components such as vacuum pumps, pressure gauges, and virtually every component of a vacuum system are typically connected to a vacuum vessel using a flange system incorporating some type of demountable seal. These joints are made up using mechanical devices such as threaded fasteners or clamps and form a relatively leak-tight seal that allows the vacuum system to achieve its design base pressure. The seals used may be polymeric (O-rings) or metallic. 7.4.2 Valves Valves serve to control the flow of gas into or out of a vacuum vessel. While some vacuum systems are constructed without valves for simplicity, robustness, or cost savings, most vacuum systems employ several types of valves. Isolation valves are generally placed between the primary roughing pump inlet and the vacuum vessel as well as between the inlet of a secondary vacuum pump and the vacuum vessel. If a process gas is injected into a vacuum system, a metering valve is often used to control either the flow rate or the pressure, based on feedback from a pressure gauge and flow controller. 7.4.3 Feedthroughs Feedthroughs allow for the transmission of mechanical motion, radiation, or fluids into or out of vacuum vessels. Mechanical feedthroughs allow us to manipulate objects inside a vacuum system under vacuum; examples of this are the multiple axis stages of electron microscopes that allow simultaneous tip, tilt translation, and rotation of a sample under study. Viewports on a vacuum system are a type of optical feedthrough. Viewports permit us to observe the vacuum environment inside a vessel or to transmit radiation such as a beam of laser light generated outside the vessel to the vessel interior while the vessel is evacuated. Electrical feedthroughs permit the transmission of electrical power into an evacuated vessel for the operation of devices such as deposition sources and

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.9

VACUUM TECHNOLOGY VACUUM TECHNOLOGY

7.9

detectors. Electrical feedthroughs also are used for transmission of data such as the signal from a thermocouple located inside an evacuated vessel to an electronics package located outside the vacuum vessel.

7.5 LEAK DETECTION 7.5.1 Techniques for Locating and Quantifying Large Leaks Rate of Rise Test. This test measures the combined effects of gas loads to a vacuum system from outgassing sources internal to the vacuum system, gas loads due to permeation through vacuum seals, and leaks in the vacuum system. To measure the rate of rise, one typically evacuates a vacuum vessel to its base pressure, isolates the vacuum pump from the vessel, and records the pressure as a function of time. If a leak is present, the rate of change in pressure is linear with time. If outgassing is the major source of gas load to the system, the pressure will rise and eventually stabilize at the equilibrium vapor pressure for the materials internal to the vacuum system.

7.5.2 Techniques for Locating and Quantifying Small Leaks Ultrasonic Leak Detection. In this technique, a microphone sensitive to the sound in the ultrasonic range is used to survey the external surfaces of an evacuated vacuum vessel. Leaks present may generate sound in the ultrasonic range that the microphone can detect. Helium Mass Spectrometer Leak Detector (HMSLD). A mass spectrometer tuned to detect only helium gas is used to precisely locate leak paths in vacuum vessels. Helium is used as the tracer gas as it is in low abundance in the atmosphere, relatively inexpensive, nontoxic, nonflammable, and has a high average velocity relative to other gas molecules in the atmosphere. There are two modes of operation of HMSLD—tracer and sniffer probes. In the tracer probe method, the HMSLD is connected to an evacuated vessel at a pressure of less than 10−4 torr. The point of connection of the HMSLD to the vessel may be at a port of the vessel or the foreline of a secondary vacuum pump. Helium gas is carefully applied using a wand to locations on the external surface of the vessel, where leaks are suspected. Helium gas entering the vacuum vessel through a leak will likely be detected in the HMSLD, which will give a visual or auditory signal to the operator. As an alternative to using a probe to search for leaks as described, one may enclose the vessel in a plastic bag and flood the bag with helium. This method will test all of the vacuum system that is enclosed in the plastic bag at once.

7.6 DESIGN OF A VACUUM SYSTEM 7.6.1 Flow Modes for Gases For the following discussion it is assumed the gas being pumped is atmospheric in composition (approximately 79 percent nitrogen and 19 percent oxygen, the balance being trace gases), the conductance elements through which the gases flow is circular in cross section, and the internal surfaces of these conductance elements are relatively smooth. Gases move under the influence of pressure differentials. As a vacuum pump operates, it creates a reduced pressure environment at its orifice. Gas molecules in a vacuum vessel connected to the pump by a conductance element move almost instantaneously to equilibrate pressure within their confined environment. Some resistance to the flow of

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.10

VACUUM TECHNOLOGY 7.10

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

the gas molecules is provided by the conductance element(s). At near atmospheric pressure, the flow of gases is well described by viscous flow. Viscous flow may be further broken down into turbulent and laminar flows. In turbulent flow, the motion of gas molecules is characterized by disorganized eddies and currents not unlike a raging river rapid. Once pressure is further reduced, the gas flow shifts to laminar, which is like that seen in wind tunnels—an orderly flow of gases in sheets. Further reduction in pressure results in a transition between the viscous and molecular flows. Once the mean free path of molecules is approximately the same length as the inside diameter of the conductance element, the trajectory of molecules is more strongly influenced by the inner walls of the vacuum vessel than by other gas molecules. The mean free path is the average length a gas molecule travels between collisions with other gas molecules. For air, the mean free path is a function of pressure and is given by l=

5 × 10 −3 P

where l = mean free path, cm P = pressure, torr In molecular flow, gas molecules travel in straight lines between collisions and their motion tends not to be influenced by pressure differentials. 7.6.2 Conductance of Gases Through Tubes and Orifices In the viscous flow regime, conductance of gases is a function of the length and diameter of the conductance element as well as the average pressure of the gas in the element. C=

3000 PD4 L

where C = conductance, 1/s P = average pressure, torr D = inside diameter of conductance element, in L = length of conductance element, in In the transition flow regime the conductance of gases is given by C=

3000 PD4 + 80 D3 L

and in the molecular flow regime the conductance of a straight tube is given by C=

80 D3 L

Often conductance elements of different diameters are connected in series. The total conductance of a series connection of conductance elements is given by n

Ctot = ∑ 1

1 Cn

where Ctot = total conductance, 1/s Cn = conductance of element n, 1/s n = number of conductance elements

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.11

VACUUM TECHNOLOGY VACUUM TECHNOLOGY

7.11

7.6.3 Delivered Pumping Speed Conductance elements impede the flow of gas from a vessel to a pump and therefore reduce the effective (delivered) pumping speed. The delivered pumping speed is a function of the speed at the pump inlet and the total conductance of the conductance elements connecting the vacuum pump to the vessel. 1 1 1 = + St Sp Ctot where St = delivered pumping speed, 1/s Sp = speed at vacuum pump inlet, 1/s 7.6.4 Time Required for Primary Evacuation of a Vacuum Vessel The elapsed time required to evacuate a vacuum vessel from an initial pressure (generally 740 torr) to a lower pressure (usually near the base pressure of a primary vacuum pump, approximately 10 mtorr) is given by t=

V  P1  ln St  P2 

where t = time, s V = vessel volume, 1 P1 = initial pressure, torr P2 = final pressure, torr 7.6.5 Calculation of Base Pressure for a Vacuum System Following the primary evacuation of a vacuum vessel, the primary pump is isolated from the vessel and the secondary pump is used to further reduce pressure in the vessel. The time required to reach the base pressure of the vessel by the secondary vacuum pump is a strong function of the internal environment of the vessel. Outgassing from components internal to the vacuum vessel, permeation of gases through the vessel walls, and leaks all contribute significantly to the gas load the secondary pump works to remove from the vacuum vessel. At the base pressure an equilibrium is established between the delivered pumping speed of the secondary vacuum pump and the total gas loads as described earlier. Q = St × P where Q = total gas load, torr ⋅ l/s Outgassing. Outgassing is the spontaneous vaporization of materials, which is commonly observed in a vacuum vessel. The rate at which materials outgas tends to be a strong function of the material composition and the temperature of the material. Tables of outgassing rates for a wide variety of materials used in vacuum are available in the books listed in the references. Materials to avoid placing inside vacuum vessels intended to achieve pressures below 10−5 torr include high vapor pressure fluids (water, common hydrocarbon oils) and any solid materials that have a detectable smell (you can smell these materials because they have a high vapor pressure!). To achieve pressures below 10−7 torr, the following additional materials should be excluded from the internal volume of a vacuum vessel, if possible—polymers such as polyvinyl chloride (PVC) and high vapor pressure metals such as zinc, cadmium, mercury, and lead.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.12

VACUUM TECHNOLOGY 7.12

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

To calculate the outgassing load for a given material one must know the outgassing rate (at the temperature it will experience inside the vacuum vessel) and the amount of surface area of the material inside the vacuum vessel. Qx = qx × Ax where Qx = outgassing load for material x, torr ⋅ 1/s qx = outgassing rate for material x, torr ⋅ 1/s ⋅ cm2 A = area of material x exposed to the interior of the vacuum vessel, cm2 Note: Many reference books provide values for outgassing rates (q) in W/m2. To convert from W/m2 to torr ⋅ l/s ⋅ cm2 divide by 1333.2. The total outgassing load for all materials inside the vacuum vessel is given by y

outgas Qtot = ∑ Qy 1

outgas where Qtot = total outgassing load, torr ⋅ 1/s Qy = outgassing load for material y

It should be noted that for a vacuum system at equilibrium, the relationship between pressure, volume temperature, and amount of gaseous material inside the vacuum vessel is given by the Ideal Gas law. PV = nRT where P = total pressure, atm V = volume, 1 n = amount of material, mol R = Ideal Gas law constant, atm ⋅1/k ⋅ mol T = temperature, K The numeric value of the ideal gas law constant R is 0.08206 l ⋅ atm/K ⋅ mole. One mole of material contains approximately 6.023 × 1023 molecules of the material and weighs 1 g atomic weight. For example, 1 mol diatomic nitrogen gas weighs approximately 28 g and 1 mol of helium gas weighs 4 g. Permeation. Permeation is the transport of a fluid (in this case gas) through a contiguous solid. In order for gases to permeate through a solid material, gas molecules must land on the outer surface of a solid material, become adsorbed, diffuse through the bulk of the solid and, desorb from the inner surface. The driving force for permeation of gases through materials is the pressure differential for each gas species. Tables of permeation rates (Kp) for a wide variety of materials used in vacuum are available in the books listed in the references. To calculate the permeation gas load, one must specify the gas permeating through a solid, know the area the gas is permeating through, and the thickness of the permeable solid. The equation for calculating permeation rate is qx =

K px ∆Px d

where qx = permeation rate for a specified gas through a specified solid, W/m2 Kpx = permeation coefficient for a specified gas through a specified solid, m2/s ∆Px = pressure differential across solid interface for the specified gas, Pa d = distance the gas must permeate through, m

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.13

VACUUM TECHNOLOGY VACUUM TECHNOLOGY

7.13

Permeation gas load is calculated in the same manner as the outgassing gas load. Qx = qx × Ax where Qx = permeation load for material x, torr ⋅ 1/s qx = permeation rate for material x, torr ⋅ 1/s ⋅ cm2 A = area of material gas is permeating through, cm2 Leaks. Leaks are accounted for by measuring the leak rate by the rate of rise method or using a helium mass spectrometer leak detector. It should be noted that if one measures the leak rate using helium as a tracer gas, a conversion factor must be applied to relate that value to the leakage rate for the higher molecular weight atmospheric gases nitrogen and oxygen.

7.7 FUTURE TRENDS AND CONCLUSIONS Researchers are currently developing vacuum technology components (such as pumps, gauges, and valves) using microelectromechanical systems (MEMS) technology.† Miniature vacuum components and systems will open the possibility for significant savings in energy costs and will open the doors to advances in electronics, manufacturing, and semiconductor fabrication. In conclusion, an understanding of the basic principles of vacuum technology, as presented in this summary, is essential for the successful execution of all projects that involve vacuum technology. Using the principles described in the chapter, a practitioner of vacuum technology can design a vacuum system that will achieve the project requirements.

FURTHER READING Hoffman, D. M., B. Singh, and J. H. Thomas, Handbook of Vacuum Science and Technology, San Diego: Academic Press, 1998. Lafferty, J. M., Foundations of Vacuum Science and Technology, New York: Wiley, 1998. O’Hanlon, J., A User’s Guide to Vacuum Technology, 2d ed., New York: Wiley, 1987. Harris, N. S., Modern Vacuum Practice, 3d ed., London: BOC Edwards, 2004.

INFORMATION RESOURCES The American Vacuum Society: www.avs.org The Association of Vacuum Equipment Manufacturers International: www.avem.org Safety on Vacuum and Pressure Systems: http://www.llnl.gov/es_and_h/esh-manual.html American Society of Mechanical Engineers: http://www.asme.org/ The University of Alberta Vacuum: http://www.ee.ualberta.ca/~schmaus/vacf/ The Bell Jar: http://www.belljar.net/ International Vacuum Societies: http://www.sansalone.de/engl/LK_vacuum_associations.htm Vacuum Industry Associations: http://www.sansalone.de/engl/LK_vacuum_industry_associations.htm Journals of Vacuum Science and Technology: http://www.sansalone.de/engl/lk_vacuum_journals.htm Physics on the Web: http://physicsweb.org/

†

http://www.darpa.mil/mto/mems/index.html

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH07.qxd

04/04/2005

19:40

Page 7.14

VACUUM TECHNOLOGY

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH08.qxd

04/04/2005

19:41

Page 8.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 8

PHOTOMASK Charles Howard DuPont Photomasks Dresden, Germany

8.1 INTRODUCTION Photomasks are the intermediate steps between the design of an integrated circuit and the actual wafer itself. They are the stencils used to print images on the semiconductor material. The lithographic principles at play in producing wafers are the same in photomask manufacture. During the early years of semiconductor manufacturing, photomask production was rather straightforward. The layout of the mask was identical to that of the wafer. The image was transferred 1:1 from mask to wafer. The number of product dice on the chip was equal to the number of master dice on the photomask. In the late seventies, so-called step and repeat systems were introduced into semiconductor manufacturing. Such systems utilized reduction lens systems and would expose a mask image stepped many times across the wafer plane. Initially the reduction was 10×, though in later years 5× and 4× reductions became the norm. This innovation resulted in larger image field sizes on the photomask (or more precisely, the reticle since the magnification is no longer 1:1 but rather 5:1 or 4:1). The result was a relaxation of various critical specifications such as minimum feature and defect sizes. Photomask production during this period was free of many of the resolution issues paramount to the wafer lithographer. The photomask business could properly be described as a commodity-driven market during that time. This technical landscape was not to last, however. As demand for faster and more powerful ICs grew, the ever-shrinking feature sizes on the wafer put greater pressure on photomask lithographers to push engineering boundaries. The photomask business today has evolved from a commodity to a critical enabling technology.

8.2 PHOTOMASK FUNDAMENTALS Figure 8.1 is a flowchart outlining the manufacture of photomasks. A brief description of each step is provided. 8.2.1 Data Preparation Design data are received from the customer design center. Data must be conditioned prior to manufacture. Generally, this includes generating a set of instructions for the pattern generator to use to print the mask features. The pattern data also need to be sized to compensate for process bias and converted to a file format acceptable to the pattern generation tool. Computing resources for

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

8.1

Geng(SMH)_CH08.qxd

04/04/2005

19:41

Page 8.2

PHOTOMASK 8.2

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

FIGURE 8.1

Basic photomask manufacturing flow. (Courtesy of ETEC Systems, Applied Materials, Inc.)

this step can be prodigious. Shrinking feature sizes lead to exponentially larger pattern files. Operations on the data are processor intensive, and transferring data files from the design center to the photomask vendor and subsequently to the pattern generation tools presents challenges to network resources. 8.2.2 Pattern Generation The converted design data are printed on the resist-coated photoblank using a pattern generation tool. Two basic systems have evolved for imaging patterns on photomasks. One system uses an electron beam (ebeam) to expose the photo resist. In general, these ebeam systems are noted for very good resolution and pattern fidelity. They require a high vacuum to operate properly. Print times can be lengthy, with 10 to 18 h not outside the norm. Pattern placement can suffer from beam deflections due to localized charging on the photoblank. The other pattern generation alternative is a laser-based system. Such systems utilize I-line or deep ultraviolet (DUV) lasers to expose the resist. Laser systems can operate at standard atmospheric pressure and thus do not require maintenance of high vacuum subsystems. Print times are generally half, or less, those of the ebeam systems, and pattern placement is generally superior as well. Where the laser system is not as capable as ebeam systems, it is in the realm of resolution and pattern uniformity. 8.2.3 Postexposure Bake This step occurs after patterning for any of several reasons. For laser-based lithography, it removes standing waves formed in the resist due to reflections from the substrate surface. Standing waves can degrade the resist image, which in turn leads to poor uniformity. Additionally, this step is required after patterning on chemically amplified resists regardless of the pattern generation tool. The bake step drives the chemical amplification to completion by inducing the diffusion of photoactive compounds through the resist. Resist line widths are very sensitive to postexposure bake temperatures. Bake tools must have excellent uniformity across the photomask. Temperature uniformities of 0.5°C or less are required.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH08.qxd

04/04/2005

19:41

Page 8.3

PHOTOMASK PHOTOMASK

8.3

8.2.4 Develop Process The exposed resist is removed by dissolution in an appropriate solvent. The solvent most frequently used is tetramethylammonium hydroxide (TMAH) in an aqueous solution. Surfactants are also added to improve the wetting of the resist. Develop tools have typically utilized one of two approaches to dispensing developer onto the resist surface. Puddle processes dispense a fixed amount of developer. The developer is left on the surface for some period of time and then rinsed off. The second approach is to spray developer on the resist for a fixed period of time. Either method has drawbacks. Evaporation rates across the surface cause temperature gradients that affect develop rates. The hoses, tubes, or nozzles used to deliver the developer to the resist are potential defect sources. Surface tension will induce forces that can impact some line width geometries. 8.2.5 Etch Process Once the exposed resist is removed, the underlying chrome is etched using the unexposed photo resist as a masking agent. Both wet and dry etch processes are in common use. Wet processes involve the use of powerful acids. Dry etch processes utilize etchant gases such as chlorine in a plasma induced by radio frequency energy. 8.2.6 Resist Removal and Cleaning After the pattern is etched into the chrome, or other opaque layer, of the photomask, the unexposed resist needs to be removed. Typically this is accomplished in a wet process involving the use of strong acids and/or acid cocktails. 8.2.7 Inspections At this point, the photomask has completed the manufacturing process and is ready for quality assurance. Critical dimensions are measured to ensure that the mask features are printed at the proper size. In addition, the critical dimensions must meet range criteria to achieve a given uniformity across the printed field. Since semiconductor devices are built layer by layer, the image fields of the photomasks used for each layer must “stack” upon each other within some tolerance. Typically, there is a design grid against which the placement of the field is measured. This measurement step is called registration. A defect inspection must be performed. This inspection must ensure there are no reticle defects larger than a given size. If defects are found, they must be repaired or determined to be within the specification required for printing. In some cases, optical measurements subjected to simulations may show a given defect to fall outside the print window of the wafer stepper/scanner. When the photomask is a phase shifting mask (PSM), measurements of the optical transmission and phase are required. 8.2.8 Final Cleaning and Pellicle Mounting After all inspections are complete, the photomask must receive a final cleaning. While this involves the use of strong acids, it is not typically as vigorous as the resist strip/clean process. Since the photomask has passed through the inspection steps at this point, the primary goal is not to damage it. Also, excessive cleaning can alter the phase and transmission characteristics of phase shift masks. Once cleaned, a pellicle is installed over the printable field to protect it from contamination at the wafer fab. The pellicle is a rectangular anodized metal frame with an optically transparent film on it. The frame height is such that any airborne or other contaminant that should fall on the film will lie outside the focus plane of the reticle image when printing the wafer. 8.2.9 Final Shipment The photomask is now ready for shipment to the wafer fab.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH08.qxd

04/04/2005

19:41

Page 8.4

PHOTOMASK 8.4

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

8.3 PHOTOMASK EQUIPMENT The principal tool, and consequently one of the most expensive, in the photomask manufacturing facility is the pattern generator. As mentioned previously, there exist two broad categories of tools— those that utilize beams of energetic electrons and those that use energetic photons. Electron beam tools were among the first to come into the marketplace and the design aesthetic of these machines influenced succeeding generations. One of the original ebeam tools was the electron beam exposure system (EBES) developed by Bell Labs in Murray Hill, New Jersey. This system utilized a raster-scanning system similar in principle to the television picture tube. The electron optics scanned a beam in one direction, while a mechanical stage moved the resist-coated mask in the perpendicular direction. The photomask image was constructed of “stripes” of variable lengths in the direction of stage travel and a fixed height that depended on the scan length of the electron beam. This simple raster scan approach exposed pixels on the resist by turning the beam on or off at the appropriate times. The photomask design was laid out on a square grid structure and the writing grid of the ebeam system, as well as the spot size of the beam, matched this grid. Simple raster scanning suffers a fundamental throughput flaw. As the smallest feature on the mask decreases in a linear fashion, the spot size of the beam must decrease in a quadratic fashion. One way to tackle the problem was to develop faster electronics and speed up the exposure rate. The MEBES system developed by ETEC Systems (an Applied Materials company) evolved through several models with exposure rates increasing from 40 MHz for the original MEBES tool up to 320 MHz for the MEBES 5500. Even an eightfold increase in speed could not keep pace with the reduction in feature sizes and writing time quickly drove production costs higher and higher. To remedy this problem, alternative writing strategies were developed. Mask lithographers recognized that the important parameter was not so much the minimum feature size, as the placement of the edges of a given feature. Schemes using writing grids and spot sizes larger than the design grid, which patterned the mask with multiple passes, were developed. Rather than simply exposing a pixel once, developers found that feature edges could be controlled very precisely by exposing them in several print passes. Exposures could be averaged and this averaging reduced printing errors. Optical pattern generators are also widely used in the photomask industry. The Altas family of optical pattern generators from ETEC Systems is a very common production tool. These tools are raster-scanning systems that utilize multipass printing. The Altas are laser-based systems that split the laser into 32 separate beams. The beams are then raster scanned across the mask using a 24-faceted rotating cylindrical mirror called a polygon. These systems are capable of very high throughput.

8.4 OPERATIONS, ECONOMICS, SAFETY, AND MAINTENANCE CONSIDERATIONS Operations and economics issues in photomask manufacture tend to be driven by the mask yield at a given technology node. An industry survey conducted by International SEMATECH in 2003 produced the following summary observations:4 • Logic designs account for 61 percent of the mask volume. • While technologies for 130 nm node and below capture the attention of the technical community, they only account for 3 percent of the mask volume. Nearly half of all masks are built to a 500 nm, or larger design node. • Binary masks account for 95 percent of the total volume. • Six-inch photoblank usage exceeds that of 5 in by a factor of 3.4 to 1. All other glass sizes account for 7 percent of the total volume.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH08.qxd

04/04/2005

19:41

Page 8.5

PHOTOMASK PHOTOMASK

8.5

• The 5× magnification accounts for just under half the total mask volume, with 4× at a 38-percent share and 1× at 12 percent. • File sizes for design data averaged 1.5 GB with a maximum observed of 76 GB. • Data preparation times averaged 6.5 h of CPU time with a maximum of 360 h reported. • Mask yields for binary masks were in the low 90s percent for all respondents. Phase shift average yields ranged between 40 percent and 90 percent, with attenuated phase shifting masks averaging 65 percent and alternating aperture phase shifting masks averaging 58 percent. • The major process related yield loss mechanism is defects, accounting for about 60 percent of yield loss. Administrative and manufacturing errors accounted for 18 percent. CD control accounted for 16 percent. • Delivery times average 5 days for a simple binary mask to 7 days for a binary mask with aggressive optical proximity correction (OPC) applied. Attenuated phase shift masks delivery times averaged 11 days. Alternating aperture phase shift masks (PSMs) average 23 days. • Mask returns represent about 0.2 percent of production volume. The largest return reason is data preparation errors of 19.5 percent with soft defects, “other reasons,” and “administrative errors” accounting for roughly 17 percent each. • Mask maintenance service is dominated by damaged pellicle replacement at 63 percent and particles under the pellicle accounting for 17 percent of service volume.

8.5 FUTURE TRENDS AND CONCLUSIONS Each new generation of lithographic technology requires advances in photomask equipment and materials. Mask making capability and cost escalation continue to be critical to future progress in lithography and will require continued focus. As a consequence of prior aggressive roadmap acceleration—particularly the microprocessor chips (MPU) gate linewidth (postetch), and increased mask error factors (MEFs) associated with low k1 lithography—mask linewidth control appears to be a particularly significant challenge for the future.3 Mask equipment and process capabilities are in place for manufacturing masks with complex OPC and PSM, while mask processes for post-193-nm technologies are in research and development. Mask damage from electrostatic discharge (ESD) has long been a concern, and it is expected to be even more problematic as mask features shrink. Furthermore, masks for 157-nm lithography will be kept in ambient atmospheres nearly free of water, so the risk of ESD damage in masks will increase. A cost-effective pellicle solution has not yet been fully developed for 157 nm masks, further complicating mask handling for lithography at that wavelength.3 Because of the particular challenges associated with imaging contact holes, the contact hole size after etch will be smaller than the lithographically imaged hole, similar to the differences between imaged and final MPU gates. This is important to comprehend in the roadmap (Fig. 8.2) because contacts have very small process windows and large mask error factors, and minor changes in the contact hole size have large implications for the mask CD control requirements.3 In fact, the most critical aspect of the roadmap to photomask manufacturers is probably the CD uniformity specifications. Figure 8.3 shows a plot of the roadmap requirements for three categories of CD types. Over the next five years, the 3-sigma uniformity of all feature types mentioned in the roadmap will be halved. Meeting this demand will be a major endeavor requiring coordination between the mask house and its suppliers. Both the litho tool and process equipment vendors will need to collaborate with their photomask customers to reach these goals. The 2003 Mask Industry Assessment conducted by SEMATECH noted that almost 20 percent of all photomask returns were for data preparation errors. The authors rightly noted that this indicates a need for better and more sophisticated software tools for photomask vendors. The International

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH08.qxd

04/04/2005

19:41

Page 8.6

PHOTOMASK 8.6

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

Year of production

2003

2004

2005

2006

hp90

Technology Node

2007

2008

2009

hp65

DRAM 1/2 Pitch

100

90

80

70

65

57

50

MPU/ASIC 1/2 Pitch

107

90

80

70

65

57

50

MPU Printed Gate Length

65

53

45

40

35

32

28

MPU Physical Gate Length

45

37

32

28

25

22

20

Wafer Minimum 1/2 Pitch

100

90

80

70

65

57

50

Wafer Minimum 1/2 Line (nm, in resist) [A]

65

53

45

40

35

32

30

Wafer Minimum 1/2 Line (nm, post etch)

45

37

32

28

25

22

20

Overlay

35

32

28

25

23

21

19

Wafer Minimum Contact Hole (nm, post etch)

115

100

90

80

70

65

55

4

4

4

4

4

4

4

Mask nominal image size (nm) [C]

260

212

180

160

140

128

112

Mask Minimum primary feature size [D]

182

148.4

126

112

98

89.6

78.4

Mask OPC feature siye (nm) clear

200

180

160

140

130

114

100

Mask sub-resolution feature size (nm) opaque [E]

130

106

90

80

70

64

56

Image placement (nm, multi-point) [F]

21

19

17

15

14

13

12

CD uniformity allocation to mask (assumption)

0.4

0.4

0.4

0.4

0.4

0.4

0.4

MEF isolated lines, binary [G]

1.4

1.4

1.4

1.4

1.6

1.6

1.6

CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary [H]

4.6

3.8

3.3

2.9

2.2

2.0

1.8

1

1

1

1

1

1

1

6.4

5.3

4.6

4.0

3.6

3.1

2.9

2

2

2

2

2.5

3

3

CD uniformity (nm, 3 sigma) contact/vias [K]

5.0

4.4

3.9

3.5

2.6

2.1

1.8

Linearity (nm) [L]

15.2

13.7

12.2

10.6

9.9

8.7

7.6

CD mean to target (nm) [M]

8.0

7.2

6.4

5.6

5.2

4.6

4.0

Defect size (nm) [N]

80

72

64

56

52

45.6

40

298

252

192

Magnification [B]

MEF isolated lines, alternating phase shift [G] CD uniformity (nm, 3 sigma) isolated lines (MPU gates), alternating phase shift mask [H] MEF dense lines [G]

152 × 152 × 6.35

Substrate form factor (mm) Blank flatness (nm, peak to valley) [O] Transmission uniformity to mask (pellicle and clear feature) (+/−% 3 sigma) Data volume (GB) [P] Mask design grid (nm) [Q]

480

410

365

320

1

1

1

1

1

1

1

144

216

324

486

729

1094

1640

4

4

4

2

2

2

2

Attenuated PSM transmission mean deviation from target (+/−% of target) [R]

5

5

5

4

4

4

4

Attenuated PSM transmission uniformity (+/−% of target) [R]

4

4

4

4

4

4

4

3 2

3 2

3 2

3 1

3 1

3 1

3 1

20%

20%

15%

15%

15%

10%

10%

Attenuated PSM phase mean deviation from nominal phase angle target 180 degrees *+/− degree) [S] Attenuated PSM phase uniformity (+/−degree) [T] Normal Reflectivity (%) [U] Mask materials and substrates

Strategy for protecting mask from defects (Exposure tool dependent)

FIGURE 8.2

Absorber on fused silica, except for 157 nm optical that will be absorber on fluorine doped, lo OH fused silica substrate. Modified fused silica pellicles have demonstrated feasibility for 157 nm scanners, and removable Pellicle for optical masks down to 193 nm pellicles might be useful for small lot productionl. Research continues on organic membrane pellicles materials in a search for viable solutions Primary PSM choices are attenuated shifter and alternating aperture

ITRS roadmap.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:41

Page 8.7

PHOTOMASK PHOTOMASK

8.7

ITRS roadmap-mask CD uniformity (3σ) 6.0

Nanometers

5.0 4.0 3.0 2.0 1.0 0.0 2004

2005

2006

2007

2008

2009

Year of production Binary isolated lines

FIGURE 8.3

Alternating phase shift isolated lines

Contacts/vias

Photomask CD uniformity chart.

Technology Roadmap for Semiconductors (ITRS) roadmap indicates that over the next 5 years, data file sizes will grow eightfold (Fig. 8.4). This puts additional pressure on the industry to place the development of these software tools on a fast track. The potential for even greater data preparation errors will be a risk few semiconductor firms will wish to take.

Data volume 1800 1600 1400 1200 Gigabytes

Geng(SMH)_CH08.qxd

1000 800 600 400 200 0 2004

2005

2006 2007 Year of production

2008

2009

Data volume FIGURE 8.4

Photomask data volume expansion.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH08.qxd

04/04/2005

19:41

Page 8.8

PHOTOMASK 8.8

SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

BIBLIOGRAPHY 1. Levinson, H. J., Principles of Lithography, Bellingham, WA: SPIE Press, 2001, pp. 229–253. 2. Cha, B. C., et al., Proceedings of the 17th Annual Symposium on Photomask Technology and Management, J. A. Reynolds, and B. J. Grenon, (eds.), Vol. 3236, pp. 34–37, Bellingham, Washington: SPIE, 1992. 3. International Technology Roadmap for Semiconductors, 2003. 4. Kimmel, K., Proceedings of the 23rd Annual Symposium on Photomask Technology and Management, K. Kimmel and W. Staud (eds.), Vol. 5256, pp. 331–343, Bellingham, WA: SPIE, 1992.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

P

●

A

●

R

●

T

●

2

WAFER PROCESSING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.2

WAFER PROCESSING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.3

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 9

MICROLITHOGRAPHY Chris A. Mack KLA-Tencor Austin, Texas

The fabrication of an integrated circuit (IC) requires a variety of physical and chemical processes performed on a semiconductor (e.g., silicon) substrate. In general, the various processes used to make an IC fall into three categories—film deposition, patterning, and semiconductor doping. Films of both conductors (such as polysilicon, aluminum, and more recently copper) and insulators (various forms of silicon dioxide, silicon nitride, and others) are used to connect and isolate transistors and their components. Selective doping of various regions of silicon allows the conductivity of the silicon to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Fundamental to all of these processes is lithography, the formation of three-dimensional relief images on the substrate for subsequent transfer of the pattern to the substrate. The word “lithography” comes from the Greek lithos, meaning stones, and graphia, meaning to write. It means quite literally writing on stones. In the case of semiconductor lithography our stones are silicon wafers and our patterns are written with a light sensitive polymer called a photoresist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated at least 10 times, but more typically are done 20 to 30 times to make one circuit. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators, and selectively doped regions are built up to form the final device. The importance of lithography can be appreciated in two ways. First, due to the large number of lithography steps needed in IC manufacturing, lithography typically accounts for about 30 percent of the cost of manufacturing. Second, lithography tends to be the technical limiter for further advances in feature size reduction and thus transistor speed and silicon area. Obviously, one must carefully understand the trade-offs between cost and capability when developing a lithography process. Although lithography is certainly not the only technically important and challenging process in the IC manufacturing flow, historically, advances in lithography have gated advances in IC cost and performance.

9.1 THE LITHOGRAPHIC PROCESS Optical microlithography is basically a photographic process by which a light sensitive polymer, called a photoresist, is exposed and developed to form three-dimensional relief images on the substrate. The general sequence of processing steps for a typical optical lithography process is as follows— substrate preparation, photoresist spin coat, prebake, exposure, postexposure bake, development, and postbake. A resist strip is the final operation in the lithographic process, after the resist pattern has

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

9.3

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.4

MICROLITHOGRAPHY 9.4

WAFER PROCESSING

been transferred into the underlying layer. This sequence is shown diagrammatically in Fig. 9.1, and most of these steps are generally performed on several tools linked together into a contiguous unit called a lithographic cluster. 9.1.1 Substrate Preparation Substrate preparation is intended to improve the adhesion of the photoresist material to the substrate. This is accomplished by one or more of the following processes—substrate cleaning to remove contamination, dehydration bake to remove water, and addition of an adhesion promoter. One common type of contaminant—adsorbed water—is removed most readily by a high temperature process called a dehydration bake. A typical dehydration bake, however, does not completely remove water from the surface of silica substrates (including silicon, polysilicon, silicon oxide, and silicon nitride). Surface silicon atoms bond strongly with a monolayer of water forming silanol groups (SiOH). Bake temperatures in excess of 600°C are required to remove this final layer of water. Since this approach is impractical, the preferred method of removing this silanol is by chemical means. Adhesion promoters are used to react chemically with surface silanol and replace the -OH group with an organic functional group that, unlike the hydroxyl group, offers good adhesion to photoresist. Silanes are often used for this purpose, the most common being hexamethyldisilizane (HMDS). 9.1.2 Photoresist Coating A thin, uniform coating of photoresist at a specific, well-controlled thickness is accomplished by the seemingly simple process of spin coating. The photoresist, rendered into a liquid form by dissolving the solid components in a solvent, is poured onto the wafer, which is then spun on a turntable at a high speed, producing the desired film. Stringent requirements for thickness control and uniformity and low-defect density call for particular attention to be paid to this process where a large number

Prepare wafer

Coat with photoresist

Prebake

Align and expose

Develop

Etch, implant, etc.

Strip resist FIGURE 9.1 Example of a typical sequence of lithographic processing steps (with no postexposure bake in this case), illustrated for a positive resist.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.5

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.5

of parameters can have significant impact on photoresist thickness uniformity and control. There is a choice among static dispense (wafer stationary while resist is dispensed) or dynamic dispense (wafer spinning while resist is dispensed), spin speeds and times, and accelerations to each of the spin speeds. Also, the volume of the resist dispensed and properties of the resist (such as viscosity, percent solids, and solvent composition) and the substrate (substrate material and topography) play an important role in the resist thickness uniformity. At the end of this cycle a thick, solvent-rich film of photoresist covers the wafer, ready for postapply bake. Although theory exists to describe the spin coat process rheologically, in practical terms the variation of photoresist thickness and uniformity with the process parameters must be determined experimentally. The photoresist spin speed curve is an essential tool for setting the spin speed to obtain the desired resist thickness. The final resist thickness varies as one over the square root of the spin speed and is roughly proportional to the liquid photoresist viscosity. 9.1.3 Postapply Bake After coating, the resulting resist film will contain between 20 to 40 percent of weight solvent. The postapply bake process, also called a softbake or a prebake, involves drying the photoresist after the spin coat process by removing this excess solvent. There are four major effects of removing solvent from a photoresist film—(1) film thickness is reduced, (2) postexposure bake and development properties are changed, (3) adhesion is improved, and (4) the film becomes less tacky and thus less susceptible to particulate contamination. Typical prebake processes leave between 3 and 8 percent residual solvent in the resist film, sufficiently small to keep the film stable during subsequent lithographic processing. Unfortunately, there are other consequences of baking some photoresists. At temperatures greater than about 70°C, the photosensitive component of a typical conventional resist mixture, called the photoactive compound (PAC), may begin to decompose. Thus, one must search for the optimum prebake conditions that will maximize the benefits of solvent evaporation and minimize the detriments of resist decomposition. For chemically amplified resists, residual solvent can significantly influence diffusion and reaction properties during the postexposure bake, necessitating careful control over the postapply bake process. Fortunately, these modern resists do not suffer from significant decomposition of the light-sensitive components during prebake. Although the use of convection ovens for the prebaking of the photoresist was once quite common, currently, the most popular bake method is the hot plate. The wafer is brought either into intimate vacuum contact with or close proximity to a hot, high-mass metal plate. Due to the high thermal conductivity of silicon, the photoresist is heated to near the hot plate temperature quickly (about 5 s for hard contact, or about 20 s for proximity baking). The greatest advantage of this method is an order of magnitude decrease in the required bake time over convection ovens, to about 1 min, and the improved uniformity of the bake. In general, proximity baking is preferred to reduce the possibility of particle generation caused by contact with the backside of the wafer. 9.1.4 Alignment and Exposure The basic principle behind the operation of a photoresist is the change in the solubility of the resist in a developer on exposure to light (or other types of exposing radiation). In the case of the standard diazonaphthoquinone positive photoresist, PAC, which is not soluble in the aqueous base developer, is converted to a carboxylic acid on exposure to UV light in the range of 350 to 450 nm. The carboxylic acid product is very soluble in the basic developer. Thus, a spatial variation in the light energy incident on the photoresist will cause a spatial variation in the solubility of the resist in the developer. Contact and proximity lithography are the simplest methods of exposing a photoresist through a master pattern called a photomask (Fig. 9.2). Contact lithography offers high resolution (down to about the wavelength of the radiation), but practical problems such as mask damage and resulting low yield make this process unusable in most production environments. Proximity printing reduces mask damage by keeping the mask a set distance above the wafer (e.g., 20 µm). Unfortunately,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.6

MICROLITHOGRAPHY 9.6

WAFER PROCESSING

Mask Resist Wafer Contact printing

Proximity printing

Projection printing

FIGURE 9.2 Lithographic printing in semiconductor manufacturing has evolved from contact printing (in the early 1960s) to projection printing (from the mid-1970s to today).

the resolution limit is increased to greater than 2 to 4 µm, making proximity printing insufficient for today’s technology. By far the most common method of exposure is projection printing. Projection lithography derives its name from the fact that an image of the mask is projected onto the wafer. Projection lithography became a viable alternative to contact and proximity printing in the mid-1970s when the advent of computer-aided lens design and improved optical materials allowed the production of lens elements of sufficient quality to meet the requirements of the semiconductor industry. In fact, these lenses have become so perfect that lens defects, called aberrations, play only a small role in determining the quality of the image. Such an optical system is said to be diffraction limited, since it is diffraction effects and not lens aberrations, which, for the most part, determine the shape of the image. There are two major classes of projection lithography tools—scanning and step-and-repeat systems. Scanning projection printing, pioneered by the Perkin-Elmer company, employs reflective optics (i.e., mirrors rather than lenses) to project a slit of light from the mask onto the wafer as the mask and wafer are moved simultaneously by the slit. The exposure dose is determined by the intensity of the light, the slit width, and the speed at which the wafer is scanned. These early scanning systems, which use polychromatic light from a mercury arc lamp, are in the ratio 1:1, that is, the mask and image sizes are equal. Step-and-repeat cameras (called steppers for short) expose the wafer, one rectangular section (called the image field) at a time, and can be 1:1 or reduction. These systems employ refractive optics (i.e., lenses) and are usually quasi-monochromatic. Both types of systems (Fig. 9.3) are capable of high-resolution imaging, although reduction imaging is required for the highest resolutions.

Mask

Wafer

Scanner

Reduction stepper

FIGURE 9.3 Scanners and steppers use different techniques for exposing a large wafer with a small image field.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.7

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.7

Scanners replaced proximity printing by the mid-seventies for device geometries below 4 to 5 µm. By the early 1980s, steppers began to dominate as device designs pushed to 2 µm and below. Steppers have continued to dominate lithographic patterning throughout the 1990s as minimum feature sizes reached the 250-nm levels. However, by the early 1990s, a hybrid step-and-scan approach was introduced. The step-and-scan approach uses a fraction of a normal stepper field (e.g., 25 mm × 8 mm), then scans this field in one direction to expose the entire 4 × reduction mask. The wafer is then stepped to a new location and the scan is repeated. The smaller imaging field simplifies the design and manufacture of the lens, but at the expense of a more complicated reticle and wafer stage. Step-and-scan technology is the technology of choice today for below 250 nm manufacturing. Resolution, the smallest feature that can be printed with adequate control, has two basic limits— the smallest image that can be projected onto the wafer and the resolving capability of the photoresist to make use of that image. From the projection imaging side, resolution is determined by the wavelength of the imaging light (l) and the numerical aperture (NA) of the projection lens, according to the Rayleigh criterion R∝

l NA

(9.1)

Lithography systems have progressed from blue wavelengths (436 nm) to UV (365 nm) to deep UV (248 nm) to today’s mainstream high-resolution wavelength of 193 nm. In the meantime, projection tool numerical apertures have risen from 0.16 for the first scanners, to amazingly high 0.93 NA systems today, producing features well under 100 nm in size. Before the exposure of the photoresist with an image of the mask can begin, this image must be aligned with the previously defined patterns on the wafer. This alignment, and the resulting overlay of the two or more lithographic patterns, is critical since tighter overlay control means circuit features can be packed closer together. Closer packing of devices through better alignment and overlay is nearly as critical as smaller devices through higher resolution in the drive toward more functionality per chip. Another important aspect of photoresist exposure is the standing wave effect. Monochromatic light, when projected onto a wafer, strikes the photoresist surface over a range of angles, approximating plane waves. This light travels down through the photoresist, and, if the substrate is reflective, is reflected back up through the resist. The incoming and reflected lights interfere to form a standing wave pattern of high and low light intensity at different depths in the photoresist. This pattern is replicated in the photoresist, causing ridges in the sidewalls of the resist feature as seen in Fig. 9.4. As pattern dimensions become smaller, these ridges can significantly affect the quality of

FIGURE 9.4 Photoresist pattern on a silicon substrate showing prominent standing waves.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.8

MICROLITHOGRAPHY 9.8

WAFER PROCESSING

the feature. The interference that causes standing waves also results in a phenomenon called swing curves, the sinusoidal variation in linewidth with changing resist thickness. These detrimental effects are best cured by coating the substrate with a thin absorbing layer called a bottom antireflective coating (BARC) that can reduce the reflectivity seen by the photoresist to less than 1 percent. 9.1.5 Postexposure Bake One method of reducing the standing wave effect is called the postexposure bake (PEB). Although there is still some debate as to the mechanism, it is believed that the high temperatures used (100 to 130°C) cause diffusion of the exposed photosensitive material, thus smoothing out the standing wave ridges. It has also been observed that the rate of diffusion is dependent on the prebake conditions since the presence of solvent enhances diffusion during a PEB. Thus, a low temperature prebake results in greater diffusion for a given PEB temperature. For a conventional resist, the main importance of the PEB is diffusion to remove standing waves. For another class of photoresists, called chemically amplified resists, the PEB is an essential part of the chemical reactions that create a solubility differential between exposed and unexposed parts of the resist. For these resists, exposure generates a small amount of a strong acid that does not itself change the solubility of the resist. During the postexposure bake, this photogenerated acid catalyzes a reaction that changes the solubility of the polymer resin in the resist. Since the photogenerated acid is not consumed in this reaction, it continues to cause more solubility changing events and thus “amplifies” the effects of exposure. Control of the PEB is extremely critical for chemically amplified resists. 9.1.6 Development Once exposed, the photoresist must be developed. Most commonly used photoresists use aqueous bases as developers. In particular, tetramethyl ammonium hydroxide (TMAH) is used almost universally at a concentration of 0.26 N. Development is undoubtedly one of the most critical steps in the photoresist process. The characteristics of the resist-developer interactions determine to a large extent the shape of the photoresist profile and, more importantly, the control of the sizes of the features being printed. The method of applying a developer to the photoresist is important in controlling the development uniformity and process latitude. During spin development, wafers are spun using equipment similar to that used for spin coating, and the developer is poured onto the rotating wafer. The wafer is also rinsed and dried while still spinning. Spray development has been shown to have good results using developers specifically formulated for this dispense method. Using a process identical to spin development, the developer is sprayed, rather than poured, on the wafer by using a nozzle that produces a fine mist of the developer over the wafer (Fig. 9.5). This technique reduces developer usage

Nozzle

Spray

Puddle

FIGURE 9.5 Different developer application techniques are commonly used.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.9

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.9

and gives more uniform developer coverage. Another in-line development strategy is called puddle development. Again using developers specifically formulated for this process, the developer is poured onto a stationary wafer that is then allowed to sit motionless for the duration of the development time. The wafer is then spin rinsed and dried. Note that all three in-line processes can be performed in the same piece of equipment with only minor modifications, and combinations of these techniques are frequently used.

9.2 IMAGE FORMATION IN OPTICAL LITHOGRAPHY Projection imaging tools are sophisticated reduction cameras with stages that allow, through a combination of stepping or stepping and scanning motions, the exposure of many copies of a mask pattern onto a large wafer. The image of the mask that is projected into the photoresist defines the information content used by the photoresist to form the final resist image. Understanding the limits and capabilities of projection imaging is the first step in understanding the limits and capabilities of lithography. Consider the generic projection system shown in Fig. 9.6. It consists of a light source, a condenser lens, the mask, the objective lens, and finally the resist-coated wafer. The combination of the light source and the condenser lens is called the illumination system. In optical design terms a lens is a system of (possibly many) lens elements. Each lens element is an individual piece of glass (refractive element) or a mirror (reflective element). The purpose of the illumination system is to deliver light to the mask (and eventually into the objective lens) with sufficient intensity, the proper directionality and spectral characteristics, and adequate uniformity across the field. The light then passes through the clear areas of the mask and diffracts on its way to the objective lens. The purpose of the objective lens is to pick up a portion of the diffraction pattern and project an image onto the wafer, which, one hopes, will resemble the mask pattern. 9.2.1 Diffraction The first and most basic phenomenon occurring in projection imaging is the diffraction of light. Diffraction is usually thought of as the bending of light as it passes through an aperture, which is certainly an appropriate description for diffraction by a lithographic mask. More correctly, diffraction theory simply describes how light propagates. This propagation includes the effects of the surroundings (boundaries). Maxwell’s equations describe how electromagnetic waves propagate, but result in partial differential equations of vector quantities, which, for general boundary conditions, are extremely

Mask

Light source

Condenser lens

Objective lens Wafer

FIGURE 9.6

Block diagram of a generic projection imaging system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.10

MICROLITHOGRAPHY 9.10

WAFER PROCESSING

difficult to solve without the aid of a powerful computer. A simpler approach is to artificially decouple the electric and magnetic field vector components and describe light as a scalar quantity, and then to use simplified (assumed) boundary conditions. Under most conditions scalar diffraction theory is surprisingly accurate. In lithography, the distance from the mask to the objective lens is very large, so that the scalar diffraction theory is at its simplest, called Fraunhofer diffraction. In order to establish a mathematical description of diffraction by a mask, let us describe the electric field transmittance of a mask pattern as tm(x, y), where the mask is in the x − y plane and tm(x, y) has in general both magnitude and phase. For a simple chrome-glass mask, the mask transmittance is assumed to be binary—tm (x, y) is 1 under the glass and 0 under the chrome. Let the x′ − y′ plane be the diffraction plane, that is, the entrance to the objective lens, and let z be the distance from the mask to the objective lens. Finally, we will assume a monochromatic light of wavelength l and that the entire system is in air (so that its index of refraction can be dropped). Then, the electric field of our diffraction pattern Tm(x′, y′) is given by the Fraunhofer diffraction integral Tm ( x ′, y ′ ) = ∫

∞

∫

∞

−∞ −∞

tm ( x, y ) e

−2pi ( f x x + f y y )

dxdy

(9.2)

where fx = x′/(zl) and fy = y′/(zl) and are called the spatial frequencies of the diffraction pattern. For many scientists and engineers, this equation should be quite familiar—it is simply a Fourier transform. Thus, the diffraction pattern (i.e., the electric field distribution as it enters the objective lens) is just the Fourier transform of the mask pattern. This is the principle behind an extremely useful approach to imaging called Fourier optics. Figure 9.7 shows two mask patterns—one an isolated space and the other a series of equal lines and spaces—both infinitely long in the y direction (the direction out of the page). The resulting mask transmittance functions tm(x) look like a square pulse and a square wave, respectively. The Fourier transforms are easily found in tables or directly calculated and are also shown in Fig. 9.7. The isolated space gives rise to a sinc function diffraction pattern, and the equal lines and spaces yield discrete diffraction orders. Isolated space: Tm ( x ′ ) = Dense space: Tm ( x ′ ) =

sin(p wfx ) p fx n 1 ∞ sin(p wfx )  d  fx −  ∑ p n =−∞ p fx p 

(9.3)

Mask

tm (x)

1 0

Tm(x ′) 0

(a)

0

fx

(b)

FIGURE 9.7 Two typical mask patterns—an isolated space and an array of equal lines and spaces—and the resulting Fraunhofer diffraction patterns assuming normally incident plane wave illumination.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.11

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.11

where δ = Dirac delta function w = space width p = pitch (the linewidth plus the space width) Let’s take a closer look at the diffraction pattern for equal lines and spaces. Note that the graphs of the diffraction patterns in Fig. 9.7 use spatial frequency as its x-axis. Since z and l are fixed for a given optical system, the spatial frequency is simply a scaled x′ coordinate. At the center of the objective lens entrance ( fx = 0), the diffraction pattern has a bright spot called the zero order. The zero order is the light that passes through the mask and is not bent. The zero order can be thought of as “DC” light, providing power but no information as to the size of the features on the mask. To either side of the zero order are two peaks called the first diffraction orders. These peaks occur at spatial frequencies of ±1/p, where p is the pitch of the mask pattern (linewidth plus spacewidth). Since the position of these diffraction orders depends on the mask pitch, their position contains information about the pitch. It is this information that the objective lens will use to reproduce the image of the mask. In fact, in order for the objective lens to form a true image of the mask it must have the zero order and at least one of the first orders. In addition to the first order, there can be many higher orders, with the nth order occurring at a spatial frequency of n/p. 9.2.2 Image Formation We are now ready to describe what happens next and follow the diffracted light as it enters the objective lens. In general, the diffraction pattern extends throughout the x′ − y′ plane. However, the objective lens, being only of finite size, cannot collect all of the light in the diffraction pattern. Typically, lenses used in microlithography are circularly symmetric and the entrance to the objective lens can be thought of as a circular aperture. Only those portions of the mask diffraction pattern that fall inside the aperture of the objective lens go on to form the image. Of course we can describe the size of the lens aperture by its radius, but a more common and useful description is to define the maximum angle of diffracted light that can enter the lens. Consider the geometry shown in Fig. 9.8. Light passing through the mask is diffracted at various angles. Given a lens of a certain size placed at a certain distance from the mask, there is some maximum angle of diffraction a for which the diffracted light just makes it into the lens. Light emerging from the mask at larger angles misses the lens and is not used in forming the image. The most convenient way to describe the size of the lens aperture is by its numerical aperture, defined as the sine of the maximum half-angle of diffracted light that can enter the lens times the index of refraction of the surrounding medium. In most cases, all lenses are in air and the numerical aperture is given by NA = sina. (Note that the spatial frequency is the sine of the diffracted angle divided by the wavelength of light. Thus, the maximum spatial frequency that can enter the objective lens is given by NA/l.)

Objective lens

α

Mask

Aperture

FIGURE 9.8 The numerical aperture is defined as NA = sinα, where α is the maximum halfangle of the diffracted light that can enter the objective lens (the lens and mask are in air).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.12

MICROLITHOGRAPHY 9.12

WAFER PROCESSING

Clearly, the numerical aperture is going to be quite important. A large numerical aperture means that a larger portion of the diffraction pattern is captured by the objective lens. For a small numerical aperture, much more of the diffracted light is lost. In fact, we can use this viewpoint to define resolution, at least from the limited perspective of image formation. Consider the simple case of a mask pattern of equal lines and spaces. As we have seen, the resulting diffraction pattern is a series of discrete diffraction orders. In order to produce an image that even remotely resembles the original mask pattern, it is necessary for the objective lens to capture the zero order and at least one higher diffraction order. If the light illuminating the mask is a normally incident plane wave, the diffraction pattern will be centered in the objective lens. Since the position of the ±1 diffraction orders are given by ±1/p, the requirement that a lens of a finite size must capture these diffraction orders to form an image puts a lower limit on the pitch that can be imaged. Thus, the smallest pitch ( pmin) that still produces an image will put the first diffraction order at the outer edge of the objective lens. 1 NA = pmin λ

(9.4)

To proceed further, we must now describe how the lens affects the light entering it. Obviously, we would like the image to resemble the mask pattern. Since diffraction gives the Fourier transform of the mask, if the lens could give the inverse Fourier transform of the diffraction pattern, the resulting image would resemble the mask pattern. In fact, lenses are designed to behave precisely in this way. We can define an ideal imaging lens as one that produces an image that is identically equal to the inverse Fourier transform of the light distribution entering the lens. It is the goal of lens designers and manufacturers to create lenses as close as possible to this ideal. Does an ideal lens produce a perfect image? No. Because of the finite size of the numerical aperture, only a portion of the diffraction pattern enters the lens. Thus, even an ideal lens cannot produce a perfect image unless the lens is infinitely big. Since in the case of an ideal lens the image is limited only by the diffracted light that does not make it through the lens, we call such an ideal system diffraction limited. In order to write our final equation for the formation of an image, let us define the objective lens’ pupil function P (a pupil is just another name for an aperture). The pupil function of an ideal lens simply describes what portion of light passes through the lens— it is one inside the aperture and zero outside: 1,  P( f x , f y ) =  0,

fx 2 + fy 2 < NA/l

(9.5)

fx 2 + fy 2 > NA/l

Thus, the product of the pupil function and the diffraction pattern describes the light entering the objective lens. Combining this with our description of how a lens behaves gives us our final expression for the electric field at the image plane (i.e., at the wafer): E(x,y) = F −1{Tm( fx, fy)P( fx, fy)}

(9.6)

where the symbol F−1 represents the inverse Fourier transform. The aerial image is defined as the intensity distribution at the wafer and is simply the square of the magnitude of the electric field. Consider the full imaging process. First, light passing through the mask is diffracted. The diffraction pattern can be described as the Fourier transform of the mask pattern. Since the objective lens is of finite size, only a portion of the diffraction pattern actually enters the lens. The numerical aperture defines the maximum angle of diffracted light that enters the lens and the pupil function is used to mathematically describe this behavior. Finally, the effect of the lens is to take the inverse Fourier transform of the light entering the lens to give an image that resembles the mask pattern. If the lens is ideal, the quality of the resulting image is only limited by the amount of the diffraction pattern collected.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.13

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.13

9.2.3 Partial Coherence Although we have completely described the behavior of a simple ideal imaging system, we must add one more complication before describing the operation of a projection system for lithography. So far, we have assumed that the mask is illuminated by spatially coherent light. Coherent illumination means simply that the light striking the mask arrives from only one direction. We have further assumed that the coherent illumination on the mask is normally incident. The result was a diffraction pattern that was centered at the entrance to the objective lens. What would happen if we changed the direction of the illumination so that the light struck the mask at some angle q′? The effect is simply to shift the position of the diffraction pattern with respect to the lens aperture (in terms of spatial frequency, the amount shifted is sinq′/l). Recalling that only the portion of the diffraction pattern passing through the lens aperture is used to form the image, it is quite apparent that this shift in the position of the diffraction pattern can have a profound effect on the resulting image. If the illumination of the mask is composed of light coming from a range of angles rather than just one angle, the illumination is called partially coherent. If one angle of illumination causes a shift in the diffraction pattern, a range of angles will cause a range of shifts, resulting in broadened diffraction orders. One can characterize the range of angles used for the illumination in several ways, but the most common is the partial coherence factor s (also called the degree of partial coherence, the pupil filling function, or just the partial coherence). The partial coherence is defined as the sine of the half-angle of the illumination cone divided by the objective lens numerical aperture. It is thus a measure of the angular range of the illumination relative to the angular acceptance of the lens. Finally, if the range of angles striking the mask extends from −90 to 90° (i.e., all possible angles), the illumination is said to be incoherent. The extended source method can be used to calculate partially coherent images. In this method, the full source is divided into individual point sources. Each point source is coherent and results in an aerial image calculated using the diffraction pattern appropriately shifted in the pupil for that source point. Two point sources from the extended source, however, do not interact coherently with each other. Thus, the contributions of these two sources must be added to each other incoherently (i.e., the intensities of the resulting images are added together). The full aerial image is determined by calculating the coherent aerial image from each point on the source, and then integrating the image intensity over the source. 9.2.4 Aberrations and Defocus Aberrations can be defined as the deviation of the real behavior of an imaging system from its ideal behavior (the ideal behavior was described earlier using Fourier optics as diffraction limited imaging). Aberrations are inherent in the behavior of all lens systems and come from three basic sources—defects of construction, defects of use, and defects of design. Defects of construction include rough or inaccurate lens surfaces, inhomogeneous glass, incorrect lens thicknesses or spacings, and tilted or decentered lens elements. Defects of use include use of the wrong illumination or tilt of the lens system with respect to the optical axis of the imaging system. Also, changes in the environmental conditions during use, such as the temperature of the lens or the barometric pressure of the air, result in defects of use. Defects of design may be a bit of a misnomer, since the aberrations of a lens design are not mistakenly designed into the lens, but rather were not designed out of the lens. All lenses have aberrated behavior since the Fourier optics behavior of a single lens element is only approximately true. It is the job of a lens designer to combine elements of different shapes and properties so that the aberrations of each individual lens element tend to cancel in the sum of all of the elements, giving a lens system with only a small residual amount of aberrations. It is impossible to design a lens system with absolutely no aberrations. Mathematically, aberrations are described as wavefront deviations, the difference in phase (or path length) of the actual wavefront emerging from the lens compared to the ideal wavefront as predicted from Fourier optics. This phase difference is a function of the position within the lens pupil, most conveniently described in polar coordinates. This wavefront deviation is, in general, quite complicated, so the mathematical form used to describe it is also quite complicated. The most common

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.14

MICROLITHOGRAPHY 9.14

WAFER PROCESSING

model for describing the phase error across the pupil is the Zernike polynomial, an infinite orthonormal polynomial series, usually cutoff at 36 terms, with powers of the radial pupil position and trigonometric functions of the polar angle. The Zernike polynomial can be arranged in many ways, but most lens design software and lens measuring equipment in use today employ a form called the fringe or circle Zernike polynomial. Terms of this polynomial describe common aberrations such as coma and astigmatism. The impact of these phase errors described by the Zernike polynomial is to modify the pupil function of Eq. (9.5) to include this phase change on transmission through the pupil. Previous expressions for calculating the aerial image (such as Eqs. (9.2), (9.5), and (9.6)) apply only to the image at the focal plane. What happens when the imaging system is out of focus? What is the image intensity distribution some small distance away from the plane of best focus? The impact of focus errors on the resulting aerial image can be described as an aberration of a sort. Consider a perfect spherical wave converging (i.e., focusing) down to a point. An ideal projection system will create such a wave coming out of the lens aperture (called the exit pupil), as shown in Fig. 9.9a. If the wafer to be printed were placed in the same plane as the focal point of this wave, we would say that the wafer was in focus. What happens if the wafer were removed from this plane by some distance d, called the defocus distance? Figure 9.9b shows such a situation. The spherical wave with the solid line represents the actual wave focused to a point a distance d away from the wafer. If, however, the wave had a different shape, as given by the dotted curve, then the wafer would be in focus. Note that the only difference between these two different waves is the radius of curvature. Since the dotted curve is the wavefront we want for the given wafer position, we can say that the actual wavefront is in error because it does not focus where the wafer is located. (This is just a variation of “the customer is always right” attitude—the wafer is always right, it is the optical wavefront that is out of focus.) By viewing the actual wavefront as having an error in curvature relative to the desired wavefront (i.e., the one that focuses on the wafer), we can quantify the effect of defocus. Looking at Fig. 9.9b, it is apparent that the distance from the desired to the defocused wavefront goes from zero at the center of the exit pupil and increases as we approach the edge of the pupil. This distance between wavefronts is called the optical path difference (OPD). The OPD is a function of the defocus distance and the position within the pupil and can be obtained from the geometry of the situation. Describing the

Exit pupil

Wafer

Wafer

d

( a)

(b)

FIGURE 9.9 Focusing of light can be thought of as a converging spherical wave: (a) in focus, and (b) out of focus by a distance d.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.15

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.15

position within the exit pupil by an angle θ, the optical path difference is given by OPD = δ (1 − cosθ)

(9.7)

As we have seen before, the spatial frequency and the numerical aperture define positions within the pupil as the sine of an angle. Thus, Eq. (9.7) will be more useful if expressed as a function of sinq:   sin 4 q sin 6 q OPD = (1 − cosq ) = 12 d  sin 2 q + + + K ≈ 12 d sin 2 q 4 8  

(9.8)

where the final approximation is accurate only for relatively small angles. So how does this optical path difference affect the formation of an image? The OPD acts just like an aberration, modifying the pupil function of the lens. For light, this path length traveled (the OPD) is equivalent to a change in phase. Thus, the OPD can be expressed as a phase error ∆f due to defocus: ∆f = k OPD = 2pd (1 − cosq )/l ≈ pd sin 2 q /l

(9.9)

where k is equal to 2p/l, the propagation constant in air and, again, the final approximation is only valid for small angles. We are now ready to see how defocus affects the diffraction pattern and the resulting image. Our interpretation of defocus is that it causes a phase error as a function of the radial position within the aperture. Light in the center of the aperture has no error; light at the edge of the aperture has the greatest phase error. Recall that diffraction by periodic patterns results in discrete diffraction orders—the zero order is the undiffracted light passing through the center of the lens, higher orders contain information necessary to reconstruct the image. Thus, the effect of defocus is to add a phase error to the higher-order diffracted light relative to the zero order. When the lens recombines these orders to form an image, this phase error will result in a degraded image. 9.2.5 Image in Resist and Standing Waves The energy that exposes a photoresist is not the energy incident on the top surface of the resist, but rather the energy that has propagated into the photoresist. Of course, exposure leads to chemical changes that modify the solubility of the resist in a developer and so a knowledge of the exact exposure inside the resist is essential. The propagation of light through a thin film of partially absorbing material coated on a substrate, which is somewhat reflective, is a fairly well-known problem and results in various thin film interference effects including standing waves. Let us begin with the simple geometry shown in Fig. 9.10a. A thin photoresist (layer 2) rests on a thick substrate (layer 3) in air (layer 1). Each material has optical properties governed by its complex index of refraction n = n − ik, where n is the real index of refraction and k is the imaginary part,

EI Air Resist

n1 D

Substrate (a) FIGURE 9.10

Air z=0

n2

Resist

n3

Substrate

E0

E1

(b)

Film stack showing the geometry used for the standing wave derivation.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.16

MICROLITHOGRAPHY 9.16

WAFER PROCESSING

called the extinction coefficient. This latter name comes from the relationship between the imaginary part of the refractive index and the absorption coefficient of the material a=

4pk l

(9.10)

where a is the absorption coefficient and l is the vacuum wavelength. Consider now the propagation of light through this simple film stack. We will begin with simple illumination of the stack by a monochromatic plane wave normally incident on the resist. When this plane wave strikes the resist surface, some of the light will be transmitted and some will be reflected. The amount of each is determined by the transmission and reflection coefficients. Defined as the ratio of the transmitted to incident electric field, the transmission coefficient tij for a normally incident plane wave transmitting from layer i to j is given by r ij =

2 ni ni + n j

(9.11)

In general, the transmission coefficient will be complex, indicating that when light is transmitted from one material to another, both the magnitude and the phase of the electric field will change. Similarly, the light reflected off layer j back into layer i is given by the reflection coefficient rij r ij =

ni − n j ni + n j

(9.12)

If an electric field EI is incident on the photoresist, the transmitted electric field will be given by t12EI. The transmitted plane wave will now travel down through the photoresist. As it travels, the wave will change phase sinusoidally with distance and undergo absorption. Eventually, the wave will travel through the resist thickness D and strike the substrate, where it will be partially reflected. So far, our incident wave (EI) has been transmitted in the photoresist (E0) and then reflected off the substrate (E1), as pictured in Fig. 9.10b. The total electric field in the photoresist (so far) will be the sum of E0 and E1. Before evaluating mathematically what this sum will be, consider the physical result. When two waves are added together, we say that the waves interfere with each other. If the waves are traveling in opposite directions, the result is a classical standing wave, a wave whose phase is fixed in space (as opposed to a traveling wave whose phase changes). Of course, we would expect the mathematics to confirm this result. Allowing the light to reflect off the top surface of the resist, it again propagates down. If all the reflections and propagations inside the resist are accounted for, the resulting intensity in the thin photoresist film becomes I ( z ) ≈ (e −az + | r 23 |2 e −a ( 2 D − z ) ) − 2 | r 23 | e −aD cos( 4p n2 ( D − z )/l )

(9.13)

This equation is graphed in Fig. 9.11 for a photoresist with typical properties on a silicon substrate. By comparing the equation to the graph, many important aspects of the standing wave effect become apparent. The most striking feature of the standing wave plot is its sinusoidal variation. The cosine term in Eq. (9.13) shows that the period of the standing wave is given by Period = λ /2n2 The amplitude of the standing waves is given by the multiplier of the cosine in Eq. (9.13). It is quite apparent that there are two ways to reduce the amplitude of the standing wave intensity. The first is to reduce the reflectivity of the substrate (reduce r23). As such, the use of an antireflection coating (ARC) is one of the most common methods of reducing standing waves. The second method

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.17

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.17

1.6 1.4

Relative intensity

1.2 1 0.8 0.6 0.4 0.2 0 0

200

400 600 Depth into resist (nm)

800

1000

FIGURE 9.11 Standing wave intensity in 1 µm of photoresist on a silicon substrate for a normally incident plane wave of 365 nm wavelength.

for reducing the standing wave intensity that Eq. (9.13) suggests is to increase absorption in the resist (reduce the e−aD term). This is accomplished by adding a dye to the photoresist (increasing a).

9.3 PHOTORESIST CHEMISTRY The formation of an aerial image is only the first step in the transfer of information from a photomask into a resist pattern. The aerial image must propagate into the resist and cause a chemical change, forming a latent image of exposed and unexposed material. This latent image, either directly or indirectly, will affect the solubility of the resist, allowing the latent image to be turned into a profile image through the process of development. 9.3.1 Exposure Kinetics All photoresists have a light sensitive compound called a sensitizer that reacts when exposed to light of a certain wavelength. For conventional resists used at near UV wavelengths, this molecule is called a PAC. The chemistry of exposure for diazonaphthoquinone (a popular PAC) is given below O N2

C

UV

COOH

O + N2

H2O

SO2

SO2

SO2

R

R

R

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

(9.14)

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.18

MICROLITHOGRAPHY 9.18

WAFER PROCESSING

The diazonaphthoquinone absorbs a photon and a water molecule, releases nitrogen gas and produces a carboxylic acid (that will exhibit high solubility in a developer made of water and base). The kinetics of the chemical reaction represented by Eq. (9.14) are first order: dm = − CIm dt

(9.15)

where the relative PAC concentration m (the actual concentration divided by the initial preexposed concentration) has been used and C is the exposure rate constant. A solution to the exposure rate equation (Eq. (9.15)) is simple if the intensity within the resist is constant throughout the exposure. m = e−CIt

(9.16)

This result illustrates an important property of first-order exposure kinetics called reciprocity. The amount of chemical change is controlled by the product of light intensity and exposure time. Doubling the intensity and cutting the exposure time in half will result in the exact same amount of chemical change. This product of intensity and exposure time is called the exposure dose. 9.3.2 Chemically Amplified Resists Unlike conventional resists, such as the diazonaphthoquinone system discussed earlier, chemically amplified resists require two separate chemical reactions to change the solubility of the resist. First, exposure turns an aerial image into a latent image of exposure reaction products. Although very similar to conventional resists, the reaction products of exposure for a chemically amplified resist do not change the solubility of the resist. Instead, a second reaction during a postexposure bake is catalyzed by the exposure reaction products. The result of the postexposure bake reaction is a change in the solubility of the resist. This two-step sensitization process has some interesting characteristics and challenges. For chemically amplified photoresists, the sensitizer is called a photoacid generator (PAG). As the name implies, the PAG forms a strong acid when exposed to deep-UV light. The reaction of a common (though simplified) PAG is shown in Eq. (9.17): Ph Ph

S+ CF3COO−

hν

CF3COOH + others

(9.17)

Ph The acid generated in this case (trifluoroacetic acid) is a derivative of acetic acid where the electron-drawing properties of the fluorines are used to greatly increase the acidity of the molecule. The PAG is mixed with the polymer resin at a concentration of typically 5 to 15 percent by weight for 248 nm resists, with 10 percent as a typical formulation. For 193 nm resists, PAG loading is kept lower at 1 to 5 percent by weight to keep the optical absorbance of the resist within desired levels. The kinetics of the exposure reaction are presumed to be standard first order. Exposure of the resist with an aerial image I(x) results in an acid latent image H(x). A postexposure bake (PEB) is then used to thermally induce a chemical reaction. This may be the activation of a cross-linking agent for a negative resist or the deblocking of the polymer resin for a positive resist. The defining characteristic of a chemically amplified resist is that this reaction is catalyzed by the acid so that the acid is not consumed by the reaction and, to first order, H remains constant. A base polymer such as polyhydroxystyrene (PHS) is used, which is very soluble in an aqueous base developer. It is the hydroxyl groups that give the PHS its high solubility, so by “blocking” these sites (by reacting the hydroxyl group with some longer chain molecule) the solubility can be reduced. Early chemically amplified resists employed a t-butoxycarbonyl group (t-BOC), resulting in a very

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.19

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.19

slowly dissolving polymer. In the presence of acid and heat, the t-BOC blocked polymer will undergo acidolysis to generate the soluble hydroxyl group, as shown in Eq. (9.18): CH2 CH

CH2 CH

CH3

H+ ∆ O C

+

CH2

C

+

CO2

CH3 OH

(9.18)

O

O CH3

C

CH3

CH3 One drawback of this scheme is that the cleaved t-BOC is volatile and will evaporate, causing film shrinkage in the exposed areas. Larger molecular weight blocking groups can be used to reduce this film shrinkage to acceptable levels (below 10 percent). Also, the blocking group is such an effective inhibitor of dissolution that nearly every blocked site on the polymer must be deblocked to obtain significant dissolution. Thus, the photoresist can be made more “sensitive” by only partially blocking the PHS. Additionally, fully blocked polymers tend to have poor coating and adhesion properties. Typical photoresists use 10 to 30 percent of the hydroxyl groups blocked, with 20 percent as the typical value. Molecular weights for the PHS run in the range of 3000 to 5000 giving about 20 to 35 hydroxyl groups per polymer molecule, about 4 to 7 of which are initially blocked. While the previously mentioned two-step dissolution enhancement mechanism is an innovative way of making the PHS polymer photosensitive using the conventional base developer, the real innovation lies in the products of the deblocking reaction. The deblocking reaction was designed to regenerate the acid as one of the products of the reaction. Thus, the acid serves as a catalyst (defined as a chemical that must be present for a reaction to occur, but which is not consumed in the reaction). This reaction has been dubbed “chemical amplification” since the impact of an absorbed photon is chemically amplified by the catalytic nature of the deblocking reaction. While catalytic reactions are not at all uncommon in chemistry, a photo-generated catalyst opens up numerous interesting implications. What is the role of acid diffusion in determining the rate of reaction? How does this diffusion affect feature size control? What stops the reaction from continuing indefinitely? How does the average number of deblocking reactions per acid (called the catalytic chain length) influence resist performance? The answers to these questions make up the critical aspects of the design of a chemically amplified photoresist. Through a variety of mechanisms, the acid formed by exposure of the resist film can be lost and thus not contribute to the catalyzed reaction to change the resist solubility. There are two basic types of acid loss—loss that occurs between exposure and postexposure bake and loss that occurs during the postexposure bake. The first type of loss leads to delay time effects—the resulting lithography is affected by the delay time between exposure and postexposure bake. Delay time effects can be very severe and, of course, are very detrimental to the use of such a resist in a manufacturing environment. The typical mechanism for delay time acid loss is the diffusion of atmospheric base contaminants into the top surface of the resist. The result is a neutralization of the acid near the top of the resist and a corresponding reduced amplification. For a negative resist, the result is that the top portion of a line is not insolublized and the resist is lost from the top of the line. For a positive resist, the effects are more devastating. Sufficient base contamination can make the top of the resist insoluble, blocking dissolution into the bulk of the resist (Fig. 9.12). In extreme cases, no patterns can be observed after development. Another possible delay time acid loss mechanism is base contamination from the substrate, as has been observed on TiN substrates.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.20

MICROLITHOGRAPHY 9.20

WAFER PROCESSING

(a)

(b)

FIGURE 9.12 Atmospheric base contamination leads to T-top formation. Shown are line/space features printed in APEX-E for (a) 0.275 µm features with no delay and (b) 0.325 µm features with 10 min delay between exposure and postexposure bake. (Courtesy of SEMATECH.)

Another mechanism for acid loss is intentional rather than accidental. Most modern formulations of chemically amplified resists include the addition of a base quencher. Loaded at concentrations of 5 to 15 percent of the initial PAG loading, this base quencher is designed to neutralize any photogenerated acid that comes in contact with it. For low exposure doses, the small amount of photoacid generated will be neutralized by the base quencher and amplification will not take place. Only when the exposure rises above a certain threshold will the amount of acid be sufficient to completely neutralize all of the base quencher as well as cause deblocking during PEB. The main purpose of the base quencher is to neutralize the low levels of acid that might diffuse into the nominally unexposed regions of the wafer, thus making the final resist linewidth less sensitive to acid diffusion. The simple description of base quenching behavior mentioned previously, is made more complicated by the fact that the quencher will, in general, diffuse during the postexposure bake. The difference in diffusivity between the acid and the base becomes an important descriptor of lithographic behavior for these types of resists. 9.3.3 Dissolution Dissolution involves some of the most critical chemistry of the resist. The goal is to create a highly nonlinear response of the resist dissolution rate to the exposure dose, with the ideal response being a threshold “switch” of high and low development rates at some exposure level. Our discussion will focus on the development of a diazo-type positive photoresist, but can be easily generalized to negative working and chemically amplified resists. Photoresist dissolution involves three processes—diffusion of a developer from the bulk solution to the surface of the resist, reaction of the developer with the resist, and diffusion of the product back into the solution. Generally, we can assume that the last step, diffusion of the dissolved resist into the solution, occurs very quickly so that this step may be ignored. Let us now look at the first two steps in the proposed mechanism. The diffusion of the developer to the resist surface can be described with the simple diffusion rate equation, given approximately by rD = kD(D − DS)

(9.19)

where rD = rate of diffusion of the developer to the resist surface D = bulk developer concentration DS = developer concentration at the resist surface kD = rate constant We shall now propose a mechanism for the reaction of the developer with the resist. It is quite likely that this step is in fact a series of more detailed steps, including the diffusion of the developer cation into the resist to form a thin gel layer. However, we will assume a simple surface-limited reaction here. The resist is composed of large macromolecules of resin along with a photoactive

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.21

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.21

compound M, which converts to product P on exposure to UV light. The resin is somewhat soluble in the developer solution, but the presence of the PAC acts as an inhibitor to dissolution, making the development rate very slow. The product P, however, is highly soluble in the developer, enhancing the dissolution rate of the resin. Let us assume that n molecules of product P react with the developer to dissolve a resin molecule. The rate of the reaction is rR = kR DS Pn

(9.20)

where rR is the rate of reaction of the developer with the resist and kR is the rate constant. From the stoichiometry of the exposure reaction: P = Mo − M

(9.21)

where Mo is the initial PAC concentration (i.e., before exposure). The two steps outlined earlier are in series, that is, one reaction follows the other. Thus, the two steps will come to a steady state such that their rates are equal. Equating the rate equations (Eqs. (9.19) and (9.20)), one can solve for DS and eliminate it from the overall rate equation. After some algebra and letting m = M/Mo r = Rmax

( a + 1)(1 − m)n + Rmin a + (1 − m)n

(9.22)

where Rmax =

kD D kD /kR Mon + 1

a = kD /kR Mon =

(n + 1) (1 − mTH )n (n − 1)

where mTH is the value of m at the inflection point of the development rate function, called the threshold inhibitor concentration. Note that the simplifying constant a describes the rate constant of diffusion relative to the surface reaction rate constant. A large value of a will mean that diffusion is very fast, and thus less important, compared to the fastest surface reaction (for the completely exposed resist). The addition of Rmin to equation (9.22) assumes that the mechanism of development of the unexposed resist is independent of the above-proposed development mechanism. In other words, there is a finite dissolution of resist that occurs by a mechanism that is independent of the presence of exposed PAC. Note that the addition of the Rmin term means that the true maximum development rate is actually Rmax + Rmin. In most cases Rmax >> Rmin and the difference is negligible. Figure 9.13 shows some plots of this model for different values of n. The behavior of the dissolution rate with increasing n values is to make the rate function more “selective” between resist exposed above mTH and resist exposed below mTH. For this reason, n is called the dissolution selectivity parameter. Also from this behavior, the interpretation of mTH as a “threshold” concentration becomes quite evident. Note that as the developer selectivity parameter n goes to infinity, the resist approaches the ideal step function response that is desired. Thus, the goal of resist design is to create higher values of n, which is directly related to the number of blocked polymer sites in the resist.

9.4 LINEWIDTH CONTROL Historically, lithography engineering has focused on two key, complimentary aspects of lithographic quality—overlay performance and linewidth control. Linewidth (or critical dimension (CD)) control generally means ensuring that the widths of certain critical features, measured at specific points on those features, fall within acceptable bounds. Overlay describes the positional errors in placing

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.22

MICROLITHOGRAPHY WAFER PROCESSING 100.

n = 16 Development rate (nm/s)

9.22

80.

n=2

60.

40.

20.

0. .00

.20

.40

.60

.80

1.00

Relative PAC concentration m FIGURE 9.13 Development rate as a function of the dissolution selectivity parameter (Rmax = 100 nm/s, Rmin = 0.1 nm/s, mTH = 0.5, and n = 2, 4, 8, and 16).

one mask layer pattern over an existing pattern on the wafer. The two types of errors are not independent in their effects on the device. Since the packing density (the closest allowed spacing between devices in a chip) is determined by the accuracy of feature edge placements, both CD control and overlay capability contribute to the design rules that determine packing density. However, by and large, the sources of errors that affect feature size and feature placement act independently so that efforts to improve overlay capability tend to have little effect on CD control, and vice versa. As a result, CD and overlay controls tend to be independent operations in most wafer fabs today. Other than the impact of CD control on design rules, are there any other ways in which CD control affects device performance? The answer is, of course, yes, but the specific manner of influence is completely dependent on the specific device layer being printed. One of the classic examples of the influence of CD control is at the polysilicon gate level of standard complementary metal oxide semiconductor (CMOS) logic devices. Physically, the polysilicon gate linewidth (paradoxically called the gate length by device engineers rather than gate width) controls the electrically important effective gate length (Leff). In turn, Leff is directly proportional to the switching time of the transistor. Narrower gates tend to make transistors that can switch on and off at higher clock speeds. Obviously, faster chips are more valuable than slower ones, as anyone who has priced a personal computer lately, knows. But smaller is not always better. Transistors are designed (especially the doping levels and profiles) for a specific gate length. As the gate length gets smaller than this designed value, the transistor begins to “leak” current when it should be off. The result is increased power consumption. If this leakage current becomes too high, the transistor is judged a failure. When printing a chip with millions of transistor gates, the gate widths take on a distribution of values across the chip (Fig. 9.14). This across chip linewidth variation (ACLV) produces a range of transistor behaviors that affect the overall performance of the chip. Although the specific details can be quite complicated and device specific, there are some very basic principles that apply. As a signal propagates through the transistors of a chip to perform an operation, there will be several paths— connected chains of transistors—that operate in parallel and interconnect with each other. At each clock cycle, transistors are turned on and off with the results passed to other interconnected transistors. The overall speed with which the operation can be performed (i.e., the fastest clock speed) is limited by the slowest (largest gate CD) transistor in the critical path for that operation. On the other hand, the power consumption of the chip is limited by the smallest gate CDs on the chip due to the leakage current. The distribution of linewidths across the chip produces a range of switching times for the transistors, which can result in timing errors. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:42

Page 9.23

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.23

1

Frequency

0.8

High leakage current, device fails

Devices are too slow, poor bin sort

0.6

0.4 Range affects timing, which affects max clock speed possible

0.2

0 150

160

170

180

190

200

210

Gate CD (nm) FIGURE 9.14 A distribution of polysilicon gate linewidths across a chip can lead to different performance failures.

So how does improved CD control impact device performance? From the previous discussion, a tighter distribution of polysilicon gate CDs will result in reduced timing errors. This smaller range of linewidths also means that the average linewidth can be reduced without running into the leakage current limit (Fig. 9.15). As a result, the overall speed of the chip can be increased without impacting reliability. The resulting improved “bin sort,” the fraction of chips that can be put into

1

0.8

Frequency

Geng(SMH)_CH09.qxd

Leakage current limit

Bin sort limit

0.6

0.4

0.2

0 150

160

170 180 Gate CD (nm)

190

200

210

FIGURE 9.15 Tightening up the distribution of polysilicon gate linewidths across a chip allows for a smaller average CD and faster device performance.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.24

MICROLITHOGRAPHY 9.24

WAFER PROCESSING

the high clockspeed bins on the final test of the device, can provide significant revenue improvements for the fab. The preceding discussion describes why CD control is important, using the gate layer of a CMOS process as an example. But how can CD control be improved? What are the root causes of CD errors? What is the best approach to attacking the problem? Fundamentally, errors in the final dimension of a feature are the result of errors in the tools, processes, and materials that affect the final CD. An error in a process variable (the temperature of a hotplate, for example) propagates through to become an error in the final CD based on the various physical mechanisms by which the variable influences the lithographic result. In such a situation, a propagation of errors analysis can be used to help understand the effects. Suppose the influence of each input variable on the final CD were expressed in a mathematical form, such as CD = f(v1, v2, v3, . . .)

(9.23)

where vi are the input (process) variables. Given an error in each process variable ∆vi, the resulting CD error can be computed from a Taylor expansion of the function in Eq. (9.23) n

∞  ∂ ∂ . . . ∆CD = ∑  ∆v1 + ∆v2 +  f (v1 , v2 , . . .) ∂v1 ∂v2  n =1 

(9.24)

This imposing looking summation of powers of derivatives can be simplified if the function is reasonably well behaved (and of course we hope that our critical features will be so) and the errors in the process variables are small (we hope this is true as well). In such a case, it may be possible to ignore the higher-order terms (n > 1), as well as the cross terms of Eq. (9.24), to leave a simple, linear error equation ∆CD = ∆v1

∂CD ∂CD . . . + ∆v2 + ∂v1 ∂v2

(9.25)

Each ∆vi represents the magnitude of a process error. Each partial derivative ∂CD/∂vi represents the process response, the response of CD to an incremental change in the variable. This process response can be expressed in many forms; for example, the inverse of the process response is called process latitude. The linear error equation (Eq. (9.25)) can be modified to account for the nature of the errors at hand. In general, CD errors are specified as a percentage of the nominal CD. For such a case, the goal is usually to minimize the relative CD error ∆CD/CD. Equation (9.25) can be put in this form as ∆CD ∂ ln CD ∂ ln CD . . . = ∆v1 + ∆v2 + CD ∂v1 ∂v2

(9.26)

Also, many sources of process errors result in errors that are a fraction of the nominal value of that variable (e.g., illumination nonuniformity in a stepper produces a dose error that is a fixed percentage of the nominal dose). For such error types, it is best to modify Eq. (9.26) to use a relative process error ∆vi /vi ∆CD ∆v1 ∂ ln CD ∆v2 ∂ ln CD . . . = + + CD v1 ∂ ln v1 v2 ∂ ln v2

(9.27)

Although Eqs. (25) to (27) may seem obvious, even trivial, in their form, they reveal a very important truth about error propagation and the control of CD. There are two distinct ways to reduce

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.25

MICROLITHOGRAPHY MICROLITHOGRAPHY

9.25

∆CD—reduce the magnitude of the individual process errors (∆vi), or reduce the response of CD to that error (∂CD/∂vi). The separation of CD errors into these two source components identifies the two important tasks that face the photo engineer. Reducing the magnitude of process errors is generally considered a process control activity and involves picking the right material and equipment for the job and ensuring that all equipment is working in proper order and all materials are meeting their specifications. Reducing the process response is a process optimization activity and involves picking the right process settings, as well as the right equipment and materials. Often, these two activities are reasonably independent of each other. A note of caution—the derivation of Eq. (9.25) assumed that the process errors were small enough to be linear and independent in their influence on CD. This will not always be the case in a real lithographic process. One needs only to consider the two variables of focus and exposure to see that the response of CD is certainly nonlinear (it is approximately quadratic with focus) and the two variables are highly dependent on each other. Usually, a linear expansion such as that of Eq. (9.25) is most useful as a guide to understanding rather than as a computational tool.

9.5 THE LIMITS OF OPTICAL MICROLITHOGRAPHY To date, optical lithography has been the technology of choice of IC manufacturing. What are the limits of this lithographic approach? The resolution limit as described in Eq. (9.1) outlines obvious challenges. Lower wavelengths require expensive, unproven materials (superpure fused silica and fluoride salts, for example, are required if the wavelength is reduced to 157 nm). Higher numerical apertures result in increasing aberrations, which can only be reduced by more complicated designs and more exacting lens manufacturing processes. To make the situation worse, any improvement in resolution is always accompanied by a decrease in depth of focus (DOF). According to the Rayleigh criterion, the DOF for small features should decrease as the feature size squares. In reality, empirical results have shown the DOF to decrease, as about the feature size, to the first power (due to improvements in photoresists and other factors). Today’s 100 nm features typically have a DOF of a few tenths of a micron. An important requirement of any improvement in the “practical” resolution of an imaging system is the ability to live within the confines of this reduced DOF. Improvements in wafer and mask flatness, autofocusing and autoleveling systems, and wafer planarization by chemical-mechanical polishing of the wafer are examples of how the industry is coping with reduced DOF. Attempts to simultaneously improve the resolution and DOF by optical means—sometimes called optical “tricks”—include (Fig. 9.16) • Optimization of the mask pattern shape, called optical proximity correction (OPC) • Optimization of the angles of light illuminating the mask, called off-axis illumination (OAI) • Adding phase information to the mask in addition to intensity information, called phase shifting masks (PSM) • Control of the polarization of the illumination Collectively, these optical approaches are known as resolution enhancement technologies (RETs). The limits of optical lithography may be further pushed with immersion lithography. By replacing the air between the lens and the substrate with a higher index fluid, it is possible to design and build a lens with a numerical aperture greater than 1.0. At 193 nm, water has very low absorption and an index of refraction of 1.44, thus increasing the maximum theoretical NA from 1.0 to 1.44. It seems likely that numerical apertures up to 1.3 will one day be available. These hyper NAs in conjunction with aggressive RETs should enable 193 nm lithography to extend to resolutions of 45 nm and below.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH09.qxd

04/04/2005

19:42

Page 9.26

MICROLITHOGRAPHY 9.26

WAFER PROCESSING

Optical proximity correction (OPC)

Off-axis illumination (OAI) Lens

1000 780 560 340 120 −100 −320 −540 −760

Profile Y position (nm)

Y position (nm)

Mask

1000 780 560 340 120 −100 −320 −540 −760

Profile

Wafer

Conventional

Annular

Quadrupole

Phase shifting mask (PSM) Quartz

Phase shifted space FIGURE 9.16

Examples of several types of resolution enhancement technologies (RETs).

FURTHER READING Rai-Choudhury, P. (ed.), Handbook of Microlithography, Micromaching, and Microfabrication, Vol. 1: Microlithography, Bellingham, WA: SPIE Press, 1997, pp. 597–680. Sheats, J. R., and B. W., Smith (eds.), Microlithography Science and Technology, New York: Marcel Dekker, 1998, pp. 109–70. Dammel, R., “Diazonaphthoquinone-based Resists,” SPIE Tutorial Texts, Vol. TT 11, Bellingham, WA: SPIE, 1993.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 10

ION IMPLANTATION AND RAPID THERMAL PROCESSING Michael Graf Axcelis Technologies Inc. Beverly, Massachusetts

10.1 OVERVIEW Modern ion implantation forms a cornerstone of advanced complementary metal oxide semiconductor (CMOS) processing. By providing significant flexibility in the selection of dopant species and precision in the amount and spatial placement of these dopants, ion implanters help enable the aggressive scaling of advanced CMOS devices from one generation to the next. The manufacture of modern integrated devices can require up to dozens of individual ion implantation steps covering a wide range of doses and subsurface profile depths. The tools to enable these demands have evolved over a number of decades, but still retain surprising commonality with their original embodiments.

10.1.1 Basic Principles Ion implantation has historically been divided into several distinct types of processes, each serviced by a distinct type of tool engineered to provide a solution for a specific segment of the application space. Traditionally, these segments have been referred to as high current, high energy, and medium current, and can be characterized mainly by the dose and the energy of implanted ions used for applications in each segment. Shown in Fig. 10.1 is a typical dose-energy map that roughly highlights these major segments. High-current implantation primarily delivers doses in the range of 1013 to 1016 cm−2 at energies no higher than about 100 keV but as low as 0.2 keV. The most common applications for which highcurrent implanters are used include: • • • • •

Source/drain contact formation Source/drain extension formation Polysilicon doping Preamorphization Bonded wafer splitting

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

10.1

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.2

ION IMPLANTATION AND RAPID THERMAL PROCESSING WAFER PROCESSING

1017

Bonded wafer splitting for SOI (H,He) Polysilicon doping (As,B)

1016

Bipolar buried subcollector (P,As)

Dose (atoms/cm2)

10.2

1015

1014

Source/drain contact (As,BF2,B)

Latchup/ESD protection (B)

Source/drain extension (As,BF2,B)

h chthroug Anti-pun ,Sb) (As,B,In

ering l engine Channe ,B,In,Sb) ,P (As,BF2

1013

1012

Preamorphization (Ge,Si)

CMOS retrograde wells (P,B,As) Noise isolation wells (P,B)

Threshold voltage adjust (As,BF2,B,P,In)

CCD wells (B)

1011 0.1

1

10 100 Energy (keV)

1000

10000

FIGURE 10.1 Dose-energy map of common ion implantation processes performed by three basic types of tools (high current, high energy, and medium current), showing typical ranges of application as well as common dopant species for each.

High-energy implantation primarily delivers doses in the range of 1011 to 1013 cm−2 at energies up to as high as several MeV. The most common applications for which high-energy implanters are used include • Retrograde and triple well formation • Buried layer formation Medium-current implantation covers a similar dose range as high-energy implantation, but at maximum energies of only several hundred keV. The most common applications for which mediumcurrent implanters are used include: • Threshold voltage adjustment • Anti-punchthrough implants • Channel engineering/retrograde channel doping All segments make use of the same basic set of primary dopant species. The dominant p-type dopant in use today is boron, usually delivered by the implanter in the form of B+ of BF 2+ ions. These ions are typically generated from BF3 (boron trifluoride) ion source feed gas. The dominant n-type dopants in use are phosphorus and arsenic, usually delivered in the form of P+ and As+ ions from PH3 (phosphine) and AsH3 (arsine) ion source feed gases, respectively. For some higher-energy applications in both the medium-current and high-energy segments, multiple charged ions, including doubly and triply charged n-type dopants (P++, P+++, As++) and doubly charged p-type dopants (B++) are not uncommon. Other dopant species that are important but typically used less frequently include indium and antimony from In Cl3 (indium trichloride) and Sb2O3 (antimony oxide). When diffusion migration of dopants during the postimplant anneal is of concern, germanium and silicon from GeF4

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.3

ION IMPLANTATION AND RAPID THERMAL PROCESSING ION IMPLANTATION AND RAPID THERMAL PROCESSING

10.3

(germanium tetrafluoride) and SiF4 (silicon tetrafluoride) are used for preamorphization of the crystal lattice prior to ultralow energy implantation for shallow junction formation. Nitrogen and carbon are occasionally used for material property modification in some applications as well.

10.2 COMPONENTS OF AN ION IMPLANTATION SYSTEM 10.2.1 Ion Source The productivity demands of commercially viable ion implantation tools are perhaps most evident in the development of ion source technologies for this industry. Beam current requirements that can be as high as tens of milliamperes have led to the adoption of hot cathode ion sources almost exclusively for mainstream production needs. The earliest versions of these ion sources were derived directly from the Freeman1 and Bernas2 style sources that had been developed for use in isotope separation. The basic operating principle of these sources relies on thermionic emission from a filament to support a dc plasma discharge between a cathode and anode separated by a potential difference of the order of 100 V. The electrons in the discharge are confined by an externally applied magnetic field of the order of 100 G. Plasma ion densities in these sources can be as high as 1012 cm−3. Relatively simple triode extraction systems are typically used to extract and shape ion beams from these sources and inject them into beamlines of various designs for delivery to the wafers being processed. Beginning in the mid-nineties and driven largely by the desire to increase the operating lifetime of the ion source, a migration from a hot filament that was immersed in the plasma discharge to an indirectly heated cathode (IHC) where the filament was shielded from the discharge, took place.3 Today, the majority of new implant systems make use of this IHC technology and generally realize source operating lifetimes that are improved by factors of two to five.4 10.2.2 Beamline Architectures There are elements of implanter beamlines that are generally common among the three major types of tools. All beamlines begin with an ion source and extraction optics, which are responsible for injecting an appropriately shaped beam of ions into the subsequent elements of the beamline. Virtually all implanter beamlines also require a mass analysis device, which is almost universally a dipole electromagnet that provides momentum dispersion and transverse focusing of the ion beam.5 The force applied to an ion passing through this dipole field is described by F = qv × B

(10.1)

where q = ion charge v = ion velocity B = magnetic field strength The direction of this force is perpendicular to both the velocity of the ion and the magnetic field. In a uniform magnetic field, the ions follow circular trajectories and can be described by balancing the Lorentz force above with the centrifugal force as qvB =

mv 2 R

(10.2)

where m is the ion mass and R is the radius of the circular trajectory. Typically, the velocity of the ion can be determined from the electrostatic potential V, through which it was accelerated when leaving the ion source and being injected into the rest of the beamline as qV =

1 2 mv 2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

(10.3)

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.4

ION IMPLANTATION AND RAPID THERMAL PROCESSING 10.4

WAFER PROCESSING

Combining Eqs. (10.1), (10.2), and (10.3) gives BR =

2 mV q

(10.4)

as a fundamental equation describing mass analysis (actually a misnomer, since it is really momentum analysis) in every beamline ion implanter. What follows the ion source, extraction, and mass analysis is more clearly differentiated among the three major tool segments.

10.2.3 High-Current Beamlines The primary objective of high-current implanters is to deliver multimilliampere beams at specific energies, typically below 200 keV, and more common recently, below 80 keV. The lower energy requirements of high-current implanters grow ever lower, with production needs now reaching the sub-keV level, with active process development down to energies below 0.2 keV. Various estimates of whether a practical production lower limit for minimum energy exists (based on concerns of implanted dose retention due to an equilibrium between surface deposition and sputtering, for example) have placed this limit in the vicinity of 0.2 to 0.5 keV.6 All of these constraints drive the design of high-current beamlines in a particular direction in which they tend to be relatively short and have large cross sections. Each of these attributes is favorable for delivering the highest possible usable beam current to the wafer. The primary challenges to delivering high beam currents at lower energies center around the effects of space charge forces on these beams. Given that the ions in an ion beam experience a repulsive force exerted by all neighboring ions, there is a tendency for the beam to expand in size as it propagates through the beamline. This beam size expansion typically gets worse as the beam current or ion mass is increased, or as the energy of the beam is decreased (as a result of a lower energy beam moving more slowly, thereby allowing more time for the expansion forces to act on the beam between points A and B). A typical parameter for understanding the scaling of space charge forces acting on an ion beam is known as the beam perveance and is usually written as7 Pi = m

I E 3/2

(10.5)

where m = ion mass E = energy of the beam I = net nonneutralized ion current in the beam This net nonneutralized ion current can be thought of as only the fraction of the ion beam population which is in excess of any electron population that may also be present in the beam and the surrounding beam plasma. In regions where the beam plasma is excluded (such as regions of high electric field), the net nonneutralized beam current is equal to the total beam current. In field-free regions where there is a beam plasma, the net nonneutralized beam current can be as little as 1 percent of the beam current. Beam size expansion due to space charge is a problem primarily due to the loss of ion current (and hence productivity) whenever the beam passes through an aperture in the beamline that is smaller than the beam. Most common high-current beamlines are as simple from an optics standpoint as having only one ion source, an analyzer magnet, and a resolving aperture, and allow the beam to travel through the entire beamline without any externally imposed electrostatic fields present. This mode of operation is referred to as drift mode since the ions are given their final energy via the ion source and extraction optics alone, and are left to “drift” through the remainder of the beamline at that energy. It is advantageous to operate high-current tools in drift mode, since the presence of any electrostatic fields in the beamline creates regions of very high space charge, by virtue of the fact that any electrons that

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.5

ION IMPLANTATION AND RAPID THERMAL PROCESSING ION IMPLANTATION AND RAPID THERMAL PROCESSING

10.5

might help to neutralize that space charge are excluded from any region with finite electrostatic fields. The analyzer magnet in high-current tools typically bends the beam through approximately 90° with a radius of approximately 300 mm. The distance from the ion source to the entrance of the analyzer magnet is typically no more than 200 to 300 mm, with a similar distance from the exit of the analyzer magnet to the resolving aperture. The distance from the resolving aperture to the wafer is in the range of 400 to 700 mm, producing a total beamline length in the range of 1.5 to 2 m. Emerging from the ion source and extraction optics, the beam is approximately 50 mm tall and converging slightly (in the nondispersive plane), and approximately 5 mm wide and diverging (in the dispersive plane). In the dispersive plane, the beam is focused by the analyzer magnet to a waist at the resolving aperture. The beam size passing through the resolving aperture is approximately 5 to 25 mm, depending largely on the energy. The beam arrives at the wafer with a dispersive plant size in the range of 30 to 100 mm. In the nondispersive plane, there is typically much less focusing applied to the beam and the size of the beam is similar (approximately 50 mm) from the source to the wafer. Most ion implanters with the simple fixed-spot beamlines described previously also make use of multi-wafer process chamber geometries (see the following section) to improve overall tool productivity. A rendered drawing of a typical high-current tool is shown in Fig. 10.2. Some high-current beamlines make use of a fixed ribbon beam architecture and a single-wafer process chamber.8 The fixed ribbon beam is intended to have a uniform spatial extent that covers at least the entire diameter of the wafer and enables a single direction of mechanical wafer scanning. In order to deliver the fixed ribbon beam with a sufficiently uniform ion flux and beam angle uniformity across the wafer, a significantly more complicated beamline is required. In addition to the ion source, analyzer magnet, and resolving aperture, this architecture requires an additional parallelizing magnet and multiple independent tuning elements (typically also small electromagnets)

Wafer process chamber

Analyzer magnet and beamguide Gas delivery and ion source

Wafer delivery and handling

FIGURE 10.2 A 300-mm high-current implanter showing the gas delivery system and ion source on the left, analyzer magnet in the center, and process chamber and wafer handling system on the right.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.6

ION IMPLANTATION AND RAPID THERMAL PROCESSING 10.6

WAFER PROCESSING

along the width of the ribbon. While this architecture has gained some acceptance, it is generally accepted that fundamental limitations to low-energy beam transport exist in this configuration that make the low-to-sub-keV energy ranges impractical for production operation. In addition to the drift mode of operation that is most common for high-current tools in the energy ranges of production interest today, most high-current tools can also be operated in a deceleration mode (sometimes also referred to as a decel or differential mode) wherein the ion beam is transported through the majority of the beamline at an energy much higher than the final desired energy, and then decelerated by means of an electrostatic field to the final energy just before the beam is incident on the wafer.9,10 The deceleration mode is typically used only when the ion beam transport through the beamline is at an energy that is so low as to make beam current losses due to space charge beam expansion very problematic from a productivity standpoint. By allowing the beam to propagate through the beamline at a higher energy, the space charge beam expansion and losses are mitigated. The decel mode of operation can be employed on both fixed-spot and fixedribbon beam beamlines. The deceleration typically occurs in a single stage at or just following the resolving aperture on the fixed-spot beam tools. On fixed-ribbon beam tools, the deceleration can occur in a single stage in the vicinity of the resolving aperture, or in multiple stages, the first of which is in the vicinity of the resolving aperture and the second following the parallelizing magnet, immediately before the wafer. Most concerns related to the deceleration mode have to do with the possibility of some beam flux reaching the wafer at energies other than the intended final energy. This so-called energy contamination is usually a result of charge exchange reactions that take place between fast beam ions and slow background gas neutral atoms or molecules. The charge exchange reaction results in a fast neutral beam atom and a slow background gas ion. The fast neutral beam can no longer be influenced by the decelerating electrostatic field that is necessary in the deceleration mode. Because of this, any fast neutral beam created before deceleration and within the line of sight of the wafer will arrive at the wafer with an energy that is higher than the intended energy.11 The typical amount of energy contamination in high-current tools making use of the deceleration mode in production today is of the order of 1 percent of the intended total dopant dose. Depending on the sensitivity of the processing step to this amount of energy contamination, or to day-to-day variations in this amount of energy contamination, this may be a serious problem.

10.2.4 High-Energy Beamlines The primary objective of high-energy implanters is to deliver up to hundreds of microampere beams at energies up to several MeV. There are two fundamental beamline approaches to achieving this objective. Most commercial high-energy systems today make use of a radio frequency (RF) linear accelerator (referred to as a linac) to deliver the MeV range of energies.12 The commercial RF linac relies on a conventional ion source and analyzer magnet, not unlike those found in a high-current beamline, to produce a dc beam of up to several milliamperes at approximately 90 keV. This dc beam is then injected into a series of 8 to 12 electrodes connected to RF resonators operating at 13.56 MHz that further accelerate the beam. The resonators serve to provide accelerating voltages of up to approximately 80 kV on each electrode. The first two RF electrodes bunch the beam into discrete packets and provide some acceleration, thereby forming a pulsed ion beam. Each beam packet is then further accelerated by the subsequent RF electrodes, each of which provides the opportunity to accelerate the beam both as it enters and leaves the electrode (by virtue of the fact that the electric field changes polarity at the RF while the beam packet is transiting the length of the electrode—a so-called push-pull technique). Each electrode in the series has a length that is chosen to provide an optimum transit time for each beam packet (which moves faster after each subsequent acceleration stage). A pair of electrostatic quadrupole lenses is placed between each RF stage to provide additional control over the beam size and shape. Following the acceleration to the final energy in the linac stage of the beamline, the beam passes through an electromagnet (typically referred to as the final energy magnet, or FEM) that deflects, disperses, and focuses the beam through an angle of approximately 40° (again according to Eq. (10.4)) and ensures that only ions of the desired momentum are allowed to pass

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.7

ION IMPLANTATION AND RAPID THERMAL PROCESSING ION IMPLANTATION AND RAPID THERMAL PROCESSING

10.7

through to the wafer. This magnet is typically tuned to a known deflecting field, based on some calibration with dc drift beams, to pass only those ions in the beam packet that are of the desired momentum (typically synonymous with saying that those ions are at the desired energy, since the mass is known). Emerging from the ion source and extraction optics, the dc beam is typically smaller than in highcurrent tools, both in the dispersive and nondispersive planes, by approximately a factor of two. The typical beam diameter passing through the linac and exiting the FEM is no larger than about 20 mm and this beam arrives at the wafer typically no larger than approximately 30 mm in diameter. The overall beamline length in the linac-based high-energy implanter is approximately 2.5 m. A rendered drawing of the beamline is shown in Fig. 10.3. The fixed-spot beam produced by this type of beamline is typically used in conjunction with a multi-wafer process chamber to improve the overall productivity. As an alternative to the linac-based implanter, a fundamentally different technology is used in some commercial high-energy implanters. A dc-tandem accelerator may also be used to generate beams in the range of energies required for the high-energy segment.13,14 The basic concept of a tandem accelerator relies on charge exchange to effectively double the accelerating capability of any given potential placed on the high-voltage terminal of the beamline. Following the extraction of positive ions from the ion source at approximately 60 keV, a fraction of these positive ions is converted to negative ions in a gas charge exchange cell. The negative ions produced in this cell pass through an analyzer magnet and some additional quadrupole focusing elements and are injected into the main accelerating terminal that is held at a fixed positive potential. The negative ions are first accelerated toward the positive terminal potential, gain energy, and then are passed through another gas cell, this one designed to strip electrons from the negative ions and convert them back to positive ions. Once this occurs, the resulting positive ion beam is then accelerated away from the positive terminal, gaining its final energy before passing through a deflecting magnet to select only ions of the desired charge and energy (since a range of charge states typically emerges from the various gas cells). Typical beam sizes and overall beamline length are comparable to the linac-based beamline. This architecture is also typically used with multi-wafer process chambers, although a variation of this architecture also scans the beam and makes use of a singlewafer process chamber geometry.

FIGURE 10.3 A high-energy beamline featuring an RF linac with 12 resonators. The ion source and analyzer magnet are on the left; the final energy magnet is on the right.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.8

ION IMPLANTATION AND RAPID THERMAL PROCESSING 10.8

WAFER PROCESSING

10.2.5 Medium-Current Beamlines The primary objective of medium-current implanters is to deliver a wide range of beam currents, from a few microamperes to several milliamperes at energies in the range of a few keV to a few hundred keV. This broad set of expectations for medium-current tools make them among the most versatile for at least having the capability to perform almost any implant required in typical processing, albeit at the expense of optimum productivity. There is also a significant variety in the architecture of the medium-current beamline, but fundamentally, most implementations involve the use of a scanned ion beam. The formation of the ion beam again takes place in a manner similar to high-current tools, typically at energies in the range of 40 to 80 keV. Following the analyzer magnet and resolving aperture, the beam is typically scanned in the dispersive plane via either an electric or a magnetic scanning element.15,16 The scanning takes place at frequencies in the range of 100 to 1000 Hz (slower for magnetic scanning where the inductance of the electromagnet poses a limitation) and over an angular extent of 10 to 20°. Following scanning, the beam must then be made parallel once again before it is incident on the wafer. This is typically achieved again with either an electrostatic or a magnetic optical element. Following this parallelizing element, the beam may also be electrostatically deflected once more to provide energy filtering to remove ions of unwanted energy that may have had coincidental paths through the beamline. Acceleration of the beam to its final energy (which may be as high as several hundred keV for multiply charged ions) typically occurs following the scanning and parallelizing stages. Schematically, a typical medium-current beamline with electric scanning and electrostatic parallelizing is shown in Fig. 10.4. The ion source, analyzer magnet, and resolving aperture serve to inject the unscanned beam from the left. The parallel scanned ribbon beam on the right is passed through a postacceleration column and electrostatic deflector before reaching the wafer.

Vlens Insulator

Fan scanned beam Unscanned beam

Ribbon scanned beam Electrostatic X-scanner

Curved electrode

FIGURE 10.4 lelizing lens.

Second curved electrode Electrostatic angle corrector lens

A medium-current beamline showing an electric scanner and electrostatic paral-

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.9

ION IMPLANTATION AND RAPID THERMAL PROCESSING ION IMPLANTATION AND RAPID THERMAL PROCESSING

10.9

Given that the beam is scanned in one dimension, mechanical wafer scanning of only one dimension is required. For this reason, medium-current beamline architectures are almost exclusively coupled with single-wafer processing chambers.

10.3 ENDSTATION ARCHITECTURES 10.3.1 Multi-Wafer High-current and high-energy architectures predominantly make use of a multi-wafer batch processing chamber in which a large number of (typically 13 to 17) wafers can be implanted simultaneously in any processing step. This type of processing is typically implemented with a spinning disk that provides two-dimensional mechanical scanning (one rotation and one linear translation) of the wafers across the fixed-spot beam. Wafers are automatically loaded onto individual pads on the disk through a vacuum loadlock. Each pad typically sits at an angle (typically about 5°) relative to the plane of the disk itself and is coated with a compliant elastomer material (such as specially formulated room temperature vulcanizing polymers, or RTVs) to allow for adequate heat transfer from the wafer to the cooled disk and pad.17 Disk rotation typically occurs at a speed of approximately 1000 revolutions per minute (rpm) at a nominal radius of approximately 650 mm, which is sufficient to maintain wafer temperatures below about 80°C with beam powers of up to 2 to 3 kW. Liner disk translation speeds can be up to approximately 100 mm/s over a travel of up to 400 mm (enough to allow a beam of order 100 mm in size to be scanned completely off of a 300-mm diameter wafer).5 Multi-wafer batch disks also typically allow implantation at incident angles that can be varied over approximately 10° about two orthogonal axes. When operating at maximum throughput, a multi-wafer architecture can process up to approximately 230 wafers per hour (Fig. 10.5). 10.3.2 Single-Wafer Medium-current architectures have exclusively made use of a single-wafer processing chamber in which only one wafer is implanted in any one processing step. This architecture is typically implemented with a single scanning arm capable of linear motion at up to 150 to 200 mm/s over a range

FIGURE 10.5 A multi-wafer batch processing chamber, showing a 13-wafer process disk and multiaxis tilt capability.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.10

ION IMPLANTATION AND RAPID THERMAL PROCESSING 10.10

WAFER PROCESSING

of up to 400 mm. The wafer is typically held on an electrostatic chuck that may be gas cooled to maintain adequate wafer temperature.17 The wafer can usually be tilted at angles of up to 60° and rotated through a full 360° either while on the chuck or prior to being placed there. When operating at maximum throughput, a typical single-wafer architecture can process up to 300 wafers per hour.

10.4 KEY PROCESS AND MANUFACTURING ISSUES There are several critical process parameters, in addition to the implant species, which describe and differentiate various ion implantation processes. These parameters include implant energy, dose, and angle. In addition, demands in the area of wafer contamination and charge control each present unique process control challenges that are also dependent on the beamline and process chamber architecture. 10.4.1 Dose Uniformity and Repeatability The delivery of a uniform dose of ions across the entire surface of the wafer is one of the key metrics in any ion implant tool. How this delivered dose is controlled during the implantation process varies depending on the particular architecture of the implant tool and the range of the dose being delivered. Both multi-wafer and single-wafer implant tools typically control the speed with which the wafers are scanned across the ion beam in one direction based on a feedback signal that is related to the flux of atoms and ions arriving at the wafer. In most cases, this signal comes from a Faraday cup sampling the electrical charge, arriving during a known period of time when the beam is not incident on the wafers. Changes in the flux of atoms and ions incident on the wafer (as a result of changes in the ion source output, or beamline transport, for example) lead to changes in the wafer scan speed to maintain constant flux over the entire surface of the wafer. In multi-wafer tools with a spinning process disk and a fixed position ion beam, the ion flux can be measured either in real time during each revolution of the process disk through a slot of known dimension in the disk itself and/or during the period of time when the disk has scanned completely out of the path of the beam.5 In single-wafer tools with a scanned ion beam, the ion flux can be measured at the end points of each scan of the beam. In single-wafer tools with a fixed ribbon ion beam, the ion flux can be estimated from the edges of the ribbon beam, which are not incident on the wafer, or can be measured during the period when the wafer has scanned completely out of the path of the beam.18 How the delivered dose is measured in the wafer following implantation depends on the species, energy, and range of dose being delivered. Common measurement techniques include modulated reflectance (commonly known as Therma-wave) and four-point probe sheet resistance.19 Therma-wave is an optical technique that measures damage to the crystal structure of the silicon following implantation and can be used to infer a delivered ion dose, if the sensitivity of the damage measurement at the particular energy and dose range is known. Therma-wave measurements have the highest sensitivity at energies above a few tens of keV and for doses in the range of 1011 to 1013. The sensitivity in this range can be as high as approaching unity (i.e., fractional changes in Therma-wave units of measurement correspond to the same fractional changes in the ion dose). Below these highsensitivity energies and/or above these high-sensitivity doses, Therma-wave sensitivity is usually no better than approximately 0.1 and is generally not used. Therma-wave measurements have the advantage of being performed on wafers as they are implanted, and require no interim annealing or other postimplant processing step. Therma-wave measurements can also be made for implant species that are not electrically active (common examples of nonelectrically active implant species are Ge+ and N+). Sheet resistance measurements with a four-point probe are contact electrical measurements requiring the presence of a p-n junction. Because of this, they can only be performed for implant species that can be electrically activated and then only following such activation (typically via a thermal annealing process as described in the next section).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:46

Page 10.11

ION IMPLANTATION AND RAPID THERMAL PROCESSING ION IMPLANTATION AND RAPID THERMAL PROCESSING

10.11

The uniformity of delivered ion dose across a wafer in modern ion implantation tools is typically expected to have a standard deviation no greater than approximately 0.5 percent, as measured with the most sensitive means available. Thermal Annealing and Junction Formation. Postimplant thermal annealing is required to repair the crystalline structure of the wafer from the damage created during implantation and to provide for some level of electrical activation of the newly introduced dopant ions. Various techniques for performing the annealing step are available, but can be broadly grouped according to whether they are more isothermal or adiabatic in nature. Adiabatic processes must take place on time scales of the order of microseconds or shorter, and are not common in mainstream high-volume manufacturing today. Isothermal annealing, with time scales ranging from hundreds of milliseconds to minutes is dominant and can be achieved with a variety of types of equipment.20 Most common for isothermal advanced anneal processing today are still lamp-based or hot-walled furnaces. The former typically uses arrays of high-power filament lamps arranged and controlled to provide uniform radiation over one or both surfaces of the wafer. The latter establishes a controlled spatial temperature profile within a volume and then positions the wafer within that volume to achieve the desired temperature and time profile for the process. Both can be used in regimes that range from more conventional long anneal times to rapid thermal anneals (RTA). As trends toward ultrashallow junction formation call for ever-decreasing thermal budgets for the wafer to minimize dopant diffusion, their abilities to serve as robust RTA tools is increasingly challenged. Typical RTA thermal budgets (generally a time integral of the temperature profile of the anneal, for temperatures where significant diffusion is occurring) for the formation of the most aggressive ultrashallow junctions must balance the need for reduced diffusion (as typically characterized by a junction depth Xj measured at a given dopant concentration) with the requirement for sufficient activation (typically characterized by the sheet resistance Rs). Ideally, minimum Xj and Rs are desirable. From a practical standpoint, while decreasing the temperature during the RTA will reduce the junction depth significantly, it will also reduce the electrical activation and lead to high sheet resistances. Increasing the temperature, on the other hand, will improve the activation and the resistance, but at the expense of a deeper junction. A typical best-case performance over a range of thermal budget conditions is shown in Fig. 10.6.6

1000 -

Rd (Ohm/sq)

Geng(SMH)_CH10.qxd

100

0

10

20

30

40

50

60

70

80

90 100 110 120

xj at 1 × 1018 cm−3 (nm) FIGURE 10.6 Comparison of sheet resistance and junction depth for various rapid thermal anneals from various sources, showing that all results fall within a narrow band and with a predicted 1/x dependence.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.12

ION IMPLANTATION AND RAPID THERMAL PROCESSING 10.12

WAFER PROCESSING

10.4.2 Implant Angle Control The angle between the incident ion beam and the surface of the wafer is an important parameter in determining the final distribution of dopant in the wafer.21 The primary factors related to the implant angle which determine this distribution are channeling in the crystalline silicon and shadowing of areas of the wafer by the edges of various masks. Channeling occurs as implanted ions migrate along and between the crystallographic planes and rows of the silicon lattice. Significant variations in the depth a given ion will travel can occur depending on whether or not it is aligned with a particular channel. A critical angle can be defined to describe how close to a particular channel an incident ion needs to be before it can travel in that channel. The critical angle is a function of the energy (E) of the incident ion and, for both axial and planar channeling, is proportional to 1 E Shadowing can occur in implants that have masks of heights that are large compared to some critical device dimensions, such as channel lengths. Whenever such an implant is performed at angles other than zero degree, either by design or due to some variation, parts of the wafer surface will be shadowed and not receive any implant dose. Control over the implant angle is achieved via control over the angle at which the wafer is positioned during implantation, both in multi-wafer and single-wafer architectures. Sources of variation in the implant angle during an implant, or from run-to-run, occur as a result of a number of possible factors, including • Variation in beam tuning causing the incident ion beam to not be parallel to the axis of the beamline. Up to several degrees of variation as a result of beam steering have been reported for various high-current architectures.22 Typical variations for medium-current and high-energy architectures tend to be significantly lower, of the order of a few tenths of a degree. • Variation in wafer crystal-cut error as a result of the bulk wafer manufacturing process. These variations typically do not exceed 0.5°, and can be controlled from batch to batch to better than 0.1°. • Variation in wafer positioning as a result of scanning architecture. Some multi-wafer spinning disk geometries introduce a systematic variation in the incident angle across the wafer as they scan and rotate in front of the beam. This across-wafer variation can be of the order of 1°,23 and can be mitigated by reductions in the wafer pad angle offset (that is used to improve cooling) to be no more than a few tenths of a degree. Further mitigations for variations in the implant angle may be achieved through the use of “quadmode” segmented implants in which the wafer is deliberately rotated by 90° during each of four equal dose segments of the overall implant. These rotations of the wafer serve to average out any angle variation that might exist in one or more planes and have been shown to effectively reduce the device sensitivity to these variations.24 Newer developments in angle control for all types of tools involve active correction for certain types of detectable angle variation prior to implant. Automated changes to beam tuning are capable of correcting beam steering variations. Repositioning of the wafer at a tilt angle to compensate for other known sources of variation is also now possible.22 As devices continue to shrink and generally become more sensitive to variations in the implant angle, this area of implanter control will remain a fertile one for new developments. 10.4.3 Contamination Several types of contaminations are of critical concern during the implantation process. Surface contaminants, both elemental and particulate, can result from the sputtering processes occurring as the ion beam strikes surfaces in close proximity to the wafer. Deposition and resputtering of material (both dopants and bulk beamline structural materials) over time puts the in-process wafers at some

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.13

ION IMPLANTATION AND RAPID THERMAL PROCESSING ION IMPLANTATION AND RAPID THERMAL PROCESSING

10.13

risk of collecting this foreign material. Surface elemental contamination of the order of 1 percent of the implanted dose can be problematic for processes. Measures to reduce elemental surface contamination include general reduction of surface area struck by the beam in the vicinity of the wafer and ensuring that the remaining surface area is coated with more benign materials such as silicon.25 The highly spoked process disks in the multi-wafer batch architecture are examples of this approach, as shown in Fig 10.7. In general, surface elemental contamination levels of the order of 1 percent or better are routinely achievable. Particle contamination can originate both locally from sputtering in the vicinity of the wafer and can also be carried by the ion beam itself, in the form of massive charged particles entrained in the electrostatic potential of the beam. The primary concerns with high levels of particle contamination include local shadowing of the dopant dose and possible bridging and shorting of device structures. A more recently emerging concern involving particles causing ballistic damage to fine device structures is more prevalent in systems with high-velocity wafer scanning via a spinning disk and during high-current implants performed when tall device structures such as the transistor gate stacks are unsupported by sidewall spacers and are in their most fragile state. Mitigations for these effects include a reduction of the kinetic energy in the scanning wafers by a reduction of the disk rotation speed up to the limits allowed by wafer cooling.26 Since the high-current implants most sensitive to this effect occur at low energies where the beam power is low, significant reductions in the disk rotation speed (a factor of ten or more) are easily implemented. Energetic elemental contaminants are typically of more serious concern, since they are more likely to find their way into the active areas of the device. Sources of energetic contamination generally originate at the ion source, either from residual dopant material left over from previous implant steps or from the structural materials of the ion source and extraction optics. Any material in the ion source that is ionized and extracted will pass through some portion of the beam guide. Since the mass (really momentum) analysis magnet has only a finite resolving power, any unwanted extracted ions with momentum similar to the desired species may still pass through to the wafer.27 Classic examples of

FIGURE 10.7 A multi-wafer process disk with significant material between wafer pads removed to reduce surface contamination.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.14

ION IMPLANTATION AND RAPID THERMAL PROCESSING 10.14

WAFER PROCESSING

these “mass coincidences” include Mo++ and BF2 (both have an apparent mass of 49 amu). Molybdenum is a common ion source arc chamber material that ionizes relatively easily; it is not uncommon for this energetic contaminant to have levels as high as several tenths of a percent. Manufacturers who rely on BF2 implants often turn to more expensive tungsten arc chambers specifically to avoid this issue. Other common energetic contaminants include PF+ in BF 2+ (masses 50 and 49, respectively) but are only present following long periods of P+ operation and can be easily mitigated with simple in situ plasma cleaning steps during process recipe transitions from one species to another. 10.4.4 Wafer Charge Control Delivering a large number of ions to the wafer can lead to very high electrostatic potentials if there is not a sufficient supply of electrons to neutralize the positive charge as it arrives.28 Beam potentials (and hence wafer potentials) of tens or even hundreds of volts would be commonplace without such a supply of electrons. Of greatest concern in the face of such potentials is the integrity of the dielectric gate oxide. Despite the fact that high-quality gate oxides can have breakdown fields as high as 10 to 15 MV/cm, the gate oxides in modern devices are now no more than a few atoms thick and are susceptible to breakdown with applied voltages of no more than a few volts. Luckily, significant neutralization of these high potentials is achieved using electrons from a number of sources. Secondary electrons generated by ion beam impact with the wafer itself and its supporting structures play a role in helping to control wafer charging. All modern high-current tools also have active plasma sources in the vicinity of the wafer to provide an additional supply of electrons to aid in this neutralization. A typical design for such plasma electron floods (PEFs) or plasma flood guns (PFGs) is shown in Fig. 10.8.29 High-energy and medium-current tools have either active electron or plasma sources or a means of locally increasing the pressure in the vicinity of the wafer to assist in the generation of a significant enough plasma beam to ensure adequate wafer charge control.

FIGURE 10.8 A typical plasma electron flood gun design for highcurrent architectures. The PEF sits just before the wafer. The ion beam is incident from right to left in this drawing.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.15

ION IMPLANTATION AND RAPID THERMAL PROCESSING ION IMPLANTATION AND RAPID THERMAL PROCESSING

10.15

10.5 RESOURCES IN ION IMPLANTATION Leading-edge developments and trends in ion implantation equipment and process development are given a biannual forum at the International Conference on Ion Implantation Technology (IIT) whose proceedings are published by IEEE (many of the references in this chapter are taken from previous IIT conferences). As part of that conference, a School of Ion Implantation is held immediately preceding, and has developed a textbook of ion implantation fundamentals that is without equal.5

REFERENCES 1. Freeman, J., “A New Ion Source for Electromagnetic Isotope Separators,” Nucl. Instr. Meth., 22 (1963), p. 306. 2. White, N., “Ion Sources for Use in Ion Implantation,” Nucl. Instr. Meth. Phys. Res., B37/38 (1989), p. 78. 3. Horsky, T. N., “Indirectly Heated Cathode Arch Discharge Source for Ion Implantation of Semiconductors,” Rev. Sci. Instrum., 69, 2, (1998), pp. 840–842. 4. Horsky, T. N., “Current Status of the Extended Life Source: Lifetime Performance and Improvements,” IEEE Proceedings of the 12th International Conference on Ion Implantation Technology, 1998, pp. 416–419. 5. Glawischnig, H., et al., “Modern Implanter Concepts,” Chap. 10 in J. F. Ziegler, ed., Ion Implantation Science and Technology, Yorktown, NY: Ion Implantation Technology, 2000. 6. Agarwal, A., “Ultra-shallow Junction Formation Using Conventional Ion Implantation and Rapid Thermal Annealing,” IEEE Proceedings of the 13th International Conference on Ion Implantation Technology, Piscataway, NJ, 2000, pp. 293–299. 7. Graf, M., et al., “Low Energy Ion Beam Transport,” IEEE Proceedings of the 14th International Conference on Ion Implantation Technology, Piscataway, NJ, 2002, pp. 359–363. 8. Angel, G., et al., “Enhanced Low Energy Drift-mode Beam Currents in a High Current Ion Implanter,” IEEE Proceedings of the 12th International Conference on Ion Implantation Technology, Piscataway, NJ, 1998, pp. 219–222. 9. Angel, G., et al., “A Novel Beam Line for Sub-keV Implants with Reduced Energy Contamination,” IEEE Proceedings of the 12th International Conference on Ion Implantation Technology, Piscataway, NJ, 1998, pp. 188–191. 10. Tsukihara, M., et al., “Introducing the LEX/LEX3, New Low Energy High Current Implanters,” IEEE Proceedings of the 14th International Conference on Ion Implantation Technology, Piscataway, NJ, 2002, pp. 373–376. 11. Al-Bayati, A., et al., “Junction Profiles of Sub-keV Ion Implantation for Deep Sub-quarter Micron Devices,” IEEE Proceedings of the 13th International Conference on Ion Implantation Technology, Piscataway, NJ, 2000, pp. 87–90. 12. Sugitani, M., et al., “Introducing the NV-GSD-HE3, a New High Energy Implanter,” IEEE Proceedings of the 12th International Conference on Ion Implantation Technology, Piscataway, NJ, 1998, pp. 192–195. 13. O’Connor, J., et al., “Performance Characteristics of the Genus Inc. Tandetron 1520 Ion Implantation System,” IEEE Proceedings of the 11th International Conference on Ion Implantation Technology, Piscataway, NJ, 1996, pp. 17–20. 14. LaFontaine, M., et al., “Beam Optics of the VIIsta 3000 Ion Implanter,” IEEE Proceedings of the 13th International Conference on Ion Implantation Technology, Piscataway, NJ, 2000, pp. 403–406. 15. Harlan, J., and K. Petry, “Overview of the Eaton 8250 Medium Current Implanter,” IEEE Proceedings of the 12th International Conference on Ion Implant. Technology, Piscataway, NJ, 1998, pp. 266–269. 16. Renau, A., and D. Hacker, “The VIISta 810 300 mm Medium Current Ion Implanter,” IEEE Proceedings of the 12th International Conference on Ion Implantation. Technology, Piscataway, NJ, 1998, pp. 158–161. 17. Mack, M., and M. Ameen, “Wafer Cooling and Wafer Charging in Ion Implantation” in J. F. Ziegler, ed., Ion Implantation Science and Technology, Yorktown, NY: Ion Implantation Technology, 2000, pp. 524–537.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH10.qxd

04/04/2005

19:46

Page 10.16

ION IMPLANTATION AND RAPID THERMAL PROCESSING 10.16

WAFER PROCESSING

18. Mezack, G., et al., “Advantages of the Varian Single Wafer High Current Ion Implanter for Advanced Device Fabrication,” IEEE Proceedings of the 13th International Conference on Ion Implantation Technology, Piscataway, NJ, 2000, pp. 431–434. 19. Keenan, W., et al., “Advances in Sheet Resistance Measurements for Ion Implant Monitoring,” Solid State Technol., 28, 6 (1985), p. 155. 20. Gyulai, J., et al., “Radiation Damage and Annealing in Silicon after Ion Implantation,” Chap. 4 in J. F. Ziegler, ed., Ion Implantation Science and Technology, Yorktown, NY: Ion Implantation Technology, 2000. 21. Simonton, R., and L. Rubin, “Channeling Effects in Ion Implantation into Silicon” in J. F. Ziegler, ed., Ion Implantation Science and Technology, Yorktown, NY: Ion Implantation Technology, 2000, p. 303. 22. Campbell, C., et al., “Beam Angle Control on the VIISta 80 Ion Implanter,” IEEE Proceedings of the 14th International Conference on Ion Implantation Technology, Piscataway, NJ, 2002, pp. 193–196. 23. Jones, M., and F. Sinclair, “IEEE Proceedings of the 11th International Conference on Ion Implantation Technology,” Piscataway, NJ, 1996, pp. 264–267. 24. Rubin, L., et al., “Process Control Issues for Retrograde Well Implants for Narrow n+/p+ Isolation in CMOS,” IEEE Proceedings of the 14th International Conference on Ion Implantation Technology, Piscataway, NJ, 2002, pp. 17–20. 25. Stone, L., et al., “Performance of a New Silicon-coated Disk Material: Disk Manufacture Control & Device Production Experience,” IEEE Proceedings of the 12th International Conference on Ion Implantation Technology, Piscataway, NJ, 1998, pp. 574–577. 26. Kawasaki, Y., et al., “The Collapse of Gate Electrode in High Current Implanter of Batch Type,” IEEE Proceedings of the 4th International Workshop on Junction Technology, Piscataway, NJ, 2004, pp. 39–41. 27. Ryssel, H., et al., “Contamination Control for Ion Implantation,” Chap. 11 in J. F. Ziegler, ed., Ion Implantation Science and Technology, Yorktown, NY: Ion Implantation Technology, 2000. 28. Mack, M., and M. Ameen, “Wafer Cooling and Wafer Charging in Ion Implantation” in J. F. Ziegler, ed., Ion Implantation Science and Technology, Yorktown, NY: Ion Implantation Technology, 2000, pp. 537–563. 29. Mack, M., et al., “Optimized Charge Control for High Current Ion Implantation,” IEEE Proceedings of the 12th International Conference on Ion Implantation Technology, Piscataway, NJ, 1998, pp. 486–489.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH11.qxd

04/04/2005

19:47

Page 11.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 11

WET ETCHING Peng Zhang Air Products and Chemicals, Inc. Allentown, Pennsylvania

11.1 INTRODUCTION In semiconductor manufacturing, the etch process is responsible for transferring a pattern from a mask layer to the underlying layer. A part of the underlying film is removed by chemical reaction with a reagent material called etchant, while the other part remains intact, protected underneath the mask layer (Fig. 11.1). The basic requirement for an effective etch process is the high selectivity between the mask and the etched layers. In other words, there should be minimal etching on the mask layer. One of the most common mask layers is the photoresist. There are mainly two methods of etching—wet chemical and dry plasma etching. During wet etching, the etchants are liquid chemical mixtures that react with the substrate to produce soluble products to be dissolved away. Dry etching employs plasma gas to etch the substrate both chemically and physically. Dry etching has started replacing wet etching in many applications, particularly in advanced microelectronics. When the semiconductor industry was getting started, wet etching was the only etching method. Nowadays, it is still quite common in the semiconductor manufacturing including compound semiconductor and microelectromechanical systems (MEMS) applications. There are several factors contributing to the popularity of wet etching. First, wet etching technology is mature and well established. It is simple to implement and there is no additional cleaning step needed. In addition, the etch selectivity is usually very high with no damage to the underlying substrate. Probably the most important factor is that wet etching is much cheaper than dry etching, which relies on expensive etching gases and chambers. Except when etching crystalline materials, the wet etching process is isotropic, i.e., the etch rate is equal in all directions. This limits the use of wet etching in advanced microelectronic manufacturing. As shown in Fig. 11.2a, with isotropic etching, undercutting occurs underneath the mask layer. As the geometries of transistors are being pushed to smaller and smaller sizes, the thickness of the film being etched becomes comparable to the lateral pattern dimension. The undercutting of the etched film becomes intolerable and the etch process difficult to control. Therefore wet etching is not a viable method to etch features in the µm and sub-µm ranges. As an alternative, dry etching or reactive ion etching (RIE) is an anisotropic etching process where energetic ions hit the substrate surface along paths perpendicular to the surface by directional bombardment while secondary reactions form protective residues on sidewalls to reduce lateral etching. As a result, high-aspect-ratio vias or contacts can be achieved. Nowadays, dry etching is the main etching process in advanced microelectronics manufacturing.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

11.1

Geng(SMH)_CH11.qxd

04/04/2005

19:47

Page 11.2

WET ETCHING 11.2

WAFER PROCESSING

Mask layer Layer to be etched FIGURE 11.1

Etch

Illustration of the pattern transfer process through etch.

11.2 HF-BASED ETCHING CHEMISTRY Hydrofluoric acid (HF)-based etching solutions are the most commonly used wet etchants in semiconductor manufacturing. Mixtures of concentrated HF (49 wt percent HF) with or without the addition of ammonium fluoride (NH4F) and deionized (DI) water can be used to etch silicon oxide (SiO2) films and silicate glasses (such as phosphosilicates and borophosphosilicates) that are grown or vapor deposited on semiconductor substrate wafers. Water is added to concentrated HF in the range of 10:1 to 100:1 and the resulting diluted HF (DHF) has a more controlled etch rate and better compatibility with the photoresist. The addition of NH4F creates a buffered HF (BHF) solution, also called buffered oxide etch (BOE). The addition of NH4F lowers the pH value and replenishes the depletion of the fluoride ions, thus maintaining a stable etch rate. The dissolution of SiO2 by HF can be depicted in the following reaction SiO2 + 4HF → SiF4 + 2H2O HF is a weak acid that does not readily dissociate into H+ and F− species. With high fluoride concentration, the fluoride-rich species such as HF2− and (HF)2 are dominant in SiO2 etching. Low pH favors the neutral species HF and (HF)2. The etch rate of SiO2 can be suppressed with lower pH and dilute solutions.1 With concentrated HF solution (49 wt percent), the removal rate of SiO2 is very fast (more than 10 µm/min) and the photoresist can be lifted off. Dilute HF has a much slower etch rate and is compatible with the photoresist. It can also be used in the removal of native oxide, cleaning, and surface treatment processes. The etch rate of SiO2 with BHF increases as the NH4F:HF ratio decreases (Fig. 11.3). For a 7:1 NH4F:HF ratio, BHF etches SiO2 at the rate of 1000 Å/min at room temperature. Higher temperatures would also increase the etch rate (Fig. 11.3). The addition of surface active agents to HF-based chemicals such as etchants and cleaning solutions may offer many potential benefits such as enhanced wetting, reduced particulate contamination, and lowering of surface roughness. For example, nonionic surfactants based on alkylphenol ethoxylate or alkylphenol polyglycidol are used in HF-based solutions to penetrate into narrow hydrophobic trenches. Ideally, the surfactant should absorb quickly onto the substrate surface during etching but completely desorb from the surface without leaving any residues when rinsed with DI water. This is difficult to achieve since many surfactants absorb strongly on hydrophobic surfaces. The effectiveness of the surfactant in HF-based solutions is usually demonstrated by a decreased contact angle on the substrate surface. The removal of the surfactant by DI water rinsing is then characterized by the increase in the contact angle of water from a low to a high value during rinsing.

Mask layer Etched layer (a)

(b)

FIGURE 11.2 (a) Isotropic etching leads to undercutting underneath the mask layer; (b) Anisotropic etching leads to minimal undercutting and is useful in etching highaspect-ratio vias or contacts.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:48

Page 11.3

WET ETCHING WET ETCHING

11.3

6000 Etch rate (Å/min)

Geng(SMH)_CH11.qxd

5000 4000

5:1 BHF

3000

7:1 BHF

2000

10:1 BHF

1000 0 20

40 Temperature (°C)

60

FIGURE 11.3 BHF etch rate of SiO2 as a function of etch temperature and NH4F:HF ratios.

However, this methodology is macroscopic in nature and cannot be used to detect the monolayer level of surfactant residues. Raghavan et al. used the attenuated total reflection (ATR) Fourier transform infra red (FTIR) technique to quantitatively analyze the absorption and desorption behavior of various nonionic surfactants such as polyglycidol and alkyl phenol ethoxylates on silicon substrates in a BHF solution.2 During the adsorption experiment, various surfactant-containing BHF solutions were flown over the hydrophobic surface of a Si internal reflection element (IRE) with the controlled flow rate (Fig. 11.4). Afterward, DI water was flown through the cell to desorb surfactants. The density of absorbed surfactants were calculated from infrared (IR) spectra and plotted as a function of adsorption and desorption time. Later, follow-up work by Zhang et al. employing the same technique, explored the absorption and desorption behavior of acetylenic diol type surfactants on a hydrophobic silicon surface.3 Figure 11.5 illustrates the increase of IR absorbance contributed by surfactant surface adsorption as a function of the adsorption time, along with the decrease in signal over the desorption process. It was found that certain types of surfactants exhibit superior dynamic performance by desorbing much more quickly from the surface (Fig. 11.6). In some cases, the isotropic nature of wet etching can be utilized to achieve the desired etch profile. It can be used in conjunction with dry etching, usually removing the bulk of the material followed by a dry etch step to take care of the pattern profile. For example, high-aspect-ratio vias and contacts can be difficult to fill with metal. One way to solve this problem is to purposely taper their profiles (Fig. 11.7). The tapered profile is created by carrying out an isotropic etch before the anisotropic dry etching. The isotropic etch, commonly called a slope or round etch, is used to etch only a part of the interlevel dielectric (ILD) thickness. The anisotropic dry etch then clears ILD and

Solution flow IR beam

Solution flow Flow cell FIGURE 11.4 ATR FTIR flow cell setup where solutions flow over the surface of a Si IRE.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH11.qxd

04/04/2005

19:48

Page 11.4

WET ETCHING WAFER PROCESSING 0.030

0.030

Absorbance

0.020 0.015 0.010

0 min 1 min 5 min 10 min 30 min 60 min

0.025 Absorbance

60 min 30 min 20 min 10 min 5 min 1 min

0.025

0.020 0.015 0.010

0.005

0.005

0.000

0.000 3050 3000 2950 2900 2850 2800 2750

3050 3000 2950 2900 2850 2800 2750 Wavenumber (cm−1)

Wavenumber (cm−1)

(a)

(b)

FIGURE 11.5 (a) IR absorbance increases with adsorption time; (b) IR absorbance decreases with desorption time.

opens the contacts to silicon. The combination of these two steps gives the contacts a characteristic wineglass shape. Wet enchants such as DHF (50:1 or 100:1 dilute HF) or BHF are commonly used to accomplish the slope etch. Another area of intense research where wet etching may find some use is the etching of high-κ gate oxide. The semiconductor industry is searching for a suitable high-κ material that can be deposited to form a very thin layer to reduce leakage of electric current.4 This is motivated by the urgency to rein in power consumption for battery-driven high-performance devices. The materials of interest are the oxides, nitrides, and silicates of Al, Zr, and Hf. An Hf oxide-based material is the current frontrunner. Etching is among the many integration challenges for these new materials. Dry etching may be used to define the gate electrode, but it may damage the underlying silicon if the etching goes any further. So far, despite some promising developments, no acceptable plasma etch with sufficient selectivity has been reported. Wet etching has to be used to remove the gate dielectrics from the source and drain regions to open up the contacts. Wet etching is also facing new challenges, since the traditional HF-based etchants have very slow etch rates for the new high-κ materials. It was reported that hot, acidic (pH = 1), dilute HF (more than 1000:1) has been effective in removing

2.5E−10 Adsorption density (mole/cm2)

11.4

2E−10 Alkyl phenol ethoxylate

1.5E−10

Acetylenic diol type

1E−10

Alkyl ethoxylate 5E−11

0 0

10

20

30

40

50

60

Desorption time (min) FIGURE 11.6

Surfactant adsorption density decreases as a function of desorption time.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH11.qxd

04/04/2005

19:48

Page 11.5

WET ETCHING WET ETCHING

disordered high-κ films including Hf and Zr silicates.5 Other new HF-based solvent chemistries have also shown promise.6 Work is underway to etch the crystalline form of these high-κ materials and improve the etch selectivity over SiO2. In the end, the final solution to the etch challenge will be dependent on the nature of the selected high-κ material, film deposition method, and optimization of electrical parameters.

11.5

1. Isotropic etch 2. Anisotropic etch

FIGURE 11.7 A wineglass-shaped contact formed by slope etch followed by straight etch.

11.3 METAL ETCHING The etching solution for Al is usually a mixture of phosphoric acid (H3PO4), acetic acid, and nitric acid (HNO3). It is often necessary to conduct the etch at elevated temperatures (approximately 50°C) to dissolve residues. Persulphates, various ammonia mixtures, and dilute sulfuric-acid-peroxide mixtures can be used to etch copper. For gold etching, cyanide-based chemistries have been used. Various other etchant solutions can be used to etch gold, nickel, platinum, chromium, and titanium (Ti). Even though the isotropic nature of wet etching limits its use in approximately µm level structures, it still finds use where the feature size is large enough that the undercutting is not a major concern. One such area is in back-end wafer-level packaging to chemically etch under-bump metallurgy (UBM). In wafer-level packaging, solder bumps are typically placed on conventional peripheral Al bonding pads or on landing pads that have been redistributed to new locations above the chip circuitry. The UBM is a layer, or stack of layers, that provides an important foundation for the solder-bumping process. The purpose of a UBM etch is to remove all metal from the area between the solder bumps, isolating them on top of UBM islands. When the solder is subsequently reflowed, it does not wet the dielectric and is limited to the UBM underneath the as-plated bump. The surface tension of the molten solder pulls it into the desired shape of a truncated sphere (Fig. 11.8). Although UBM layers may be etched using the dry etch technique, wet etching is generally used because of the following advantages: (1) the wet etching process etches more efficiently from beneath the caps of mushroom-plated bumps, (2) no additional cleaning of etch residue is required, and (3) there is significant cost saving using the wet etching process. It is critical to control the undercut to less than 2 to 5 µm to maintain the adhesion of the bump. As a result, the etch time has to be tightly controlled.

11.4 WET ETCHING FOR COMPOUND SEMICONDUCTOR Due to the undercutting under the mask caused by the isotropic wet etching, wet etching of dielectric films on group III-V materials is being gradually replaced by plasma dry etching, since all the common dielectrics (SiO2, SiNx, phosphosilicate glass, TiN) can be dry etched using fluorine-based gas mixtures (CF4, SF6, NF3). However, wet etching is still widely used in etching group III-V materials in compound semiconductor manufacturing.7

Solder UBM Landing pad FIGURE 11.8

UBM etch

Solder reflow

UBM etch and solder reflow steps in solder-bumping process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH11.qxd

04/04/2005

19:48

Page 11.6

WET ETCHING 11.6

WAFER PROCESSING

The basic chemistry in wet chemical etching of group III-V materials involves oxidation of the substrate surface and subsequent removal of the soluble reaction product. The etch rate can be limited either by the diffusion process, i.e., diffusion of active etchant to the substrate surface, or the diffusion of soluble product away from the surface, or the chemical reaction at the substrate surface. The diffusionlimited etching process can be highly anisotropic, but difficult to control in a reproducible fashion. The reaction-limited etch is preferred in the device fabrication. It is generally insensitive to agitation, but shows a marked temperature dependency illustrated by the Arrhenius equation. Depending on the etch mixtures and actual application, the solution can either be heated or cooled to obtain controlled etch rates. For group III-V materials with at least two different sublattices, a wet etch can produce a degree of anisotropy during pattern transfer, because the solution usually etches different crystal orientations with different rates. For example, the As faces in GaAs typically etch faster than the Ga faces. Table 11.1 summarizes the most common etchant mixtures for GaAs, InP, InGaP, and other group III-V semiconductor materials. These solutions usually contain strong acids such as phosphoric acid (H3PO4), sulfuric acid (H2SO4), nitric acid (HNO3), HCl, HF, acetic acid, and citric acid. They sometimes also contain hydrogen peroxide (H2O2), which is used to oxidize the substrate surface and dissolve the oxidized products. For a GaAs substrate, both acidic and basic etchant mixtures can be used since Ga and As oxides can be dissolved in both media.8 An ammonium hydroxide (NH4OH)-H2O2-water mixture with 1:700 v/v ratio of NH4OH:H2O2 affords a very controlled etch rate of approximately 3000 Å/min. For H2SO4-H2O2-water mixtures, the concentrations of sulfuric acid and peroxide have a major impact on the etch process. A mirror-smooth after-etch surface can be obtained over a wide range of temperatures using mixtures with either high sulfuric acid or peroxide concentration. When both concentrations are high, the etch rate is extremely rapid, resulting in a rough surface. A 4:1 H2SO4:H2O2 ratio has an etch rate of approximately 5000 Å/min. The mixture of H3PO4-H2O2-water can be used to etch GaAs at slow, controlled rates. For mixtures with high phosphoric acid content, the etching process becomes diffusion-limited due to the high viscosity of H3PO4. Bromine-methanol solutions have very rapid etch rates for GaAs and GaSb (typically more than 5 µm/min at 25°C) and are used for polish etching. A photoresist is not a suitable mask due to the attack by bromine, but patterned etching using SiO2 leads to grooves that have rounded bottoms. Therefore they are often used for V-groove formation.

TABLE 11.1

Summary of Wet Etchant Solutions for Various Group III-V Materials

Group III-V materials GaAs

InP

InGaP AlInP GaSb GaN GaP InSb InAs

Etchant mixtures

Comment

Acid-H2O2-H2O Base-H2O2-H2O HNO3-HF-H2O KI-I2-H2O Br2-methanol HCl or HCl acid mixture-H2O HCl or HCl acid mixture-H2O2-H2O HBr/HCl H3PO4-HCl-H2O HCl-H2O HCl-H2O, HCl-H2O2-H2O HF-HNO3 NaOH-H2O2-H2O Acid-H2O2-H2O HF-HNO3-H2O Acid-H2O2-H2O HF-HNO3-H2O HCl or HCl acid mixture-H2O

Acid: H2SO4, HNO3, H3PO4, acetic acid with HNO3 Base: NH4OH Selective for AlGaAs at low pH Chemical polishing Acid mixture: mixtures of HCl with HNO3, H3PO4, acetic acid Selective for InP over InGaAsP Highly selective over GaAs for low H3PO4 Selective over GaAs Must be heated (80°C) Etched in a similar mixture as GaAs

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH11.qxd

04/04/2005

19:48

Page 11.7

WET ETCHING WET ETCHING

11.7

Wet etchants for InP are mainly based on HCl, which is combined with H2O, H3PO4, HNO3, H2O2, or HBr.9 The etch rate depends on HCl concentration with etch rates as high as 5 µm/min. Dilution with water is used to provide etch rates in the hundreds of Å/min range for device fabrication. Etch rates with HCl-H3PO4-water are in the range of 900 to 10000 Å/min for a 1:4 acid to water ratio. For other group III-V materials, they are generally etched with the combination of acids and water or acids, peroxide, and water. For example, InGaP is etched with HCl-H3PO4-water. AlInP can be selectively etched from an underlying GaAs layer with an HCl-H2O mixture. GaSb and GaP can be etched in HNO3-HF, HNO3-HCl, H2SO4-H2O, or bromine-methanol. InAs is typically etched in HCl based mixtures, HNO3-HF, or HNO3-HCl-H2O. For selective etching, the H3PO4-H2O2-water and H2SO4-H2O2-water mixtures will etch GaAs or InGaAsP, but stop on InP, whereas HCl/H2O will etch InP, not InGaAs or InGaAsP. For nonselective etching, an HCl-HNO3-H2O mixture will remove both GaAs and InP with equal rates.

11.5 EQUIPMENT FOR WET ETCH Immersion processors, or wet benches, are typically used for wet etching. A cassette of wafers is immersed in the etching solution for a specific period of time, after which it is rinsed in DI water. Immersion baths can be heated to achieve the desired temperature. Physical agitation can be used to flush away contaminants and provide fresh solutions to the surface, particularly with viscous etching solutions. The agitation is accomplished in various ways including ultrasonic agitation, nitrogen bubbling through the solution, or mechanical agitation. Filtered recirculation of chemicals can be used to improve chemical cleanliness and reduce chemical consumption. Rinse tanks and dryers can be major sources of particulate contamination. The proper design of the rinse and dry steps is especially critical in HF-type wet etching where hydrophobic surfaces are produced. There are three types of rinse systems—quick-dump rinse, cascade overflow rinse, and spin rinse dry (SRD). The quick-dump rinse tanks with top spray rapidly remove chemicals from the wafer surfaces and periodically drain the chemical solution. The disadvantage of this method is bacterial growth in parts of the system, especially the nozzle, and the inherent turbulence that can move particles through the solution. The cascade overflow system is less susceptible to particle contamination. Hot water is often used for cascade rinses when viscous chemicals such as phosphoric acids need to be removed. For SRD process, water is sprayed on the wafers as they rotate in a chamber. After the rinse, the wafers are spun dry, often with nitrogen flowing through the chamber. The chamber needs to be designed such that the water remaining on the walls after the rinse is not deposited on the wafer. Several other techniques for drying have been used, such as hot nitrogen drying, vacuum drying, slow pull drying, and the popular isopropyl alcohol (IPA) vapor drying.

11.6 ENVIRONMENTAL, HEALTH, AND SAFETY ISSUES There are a lot of environmental, health and safety (EH&S) issues associated with the wet etching process, which uses some of the most directly hazardous materials. Strong oxidizers such as hydrogen peroxides are highly reactive and cause damage similar to acid burns. HF is a particularly corrosive hazard. Dilute HF causes delayed damage undetected till hours after exposure. Strong acids and oxidizers are often mixed together and heated to elevated temperatures. Fume generation can occur and spread highly corrosive droplets. Some metal etching solutions are particularly hazardous. For example, cyanide solutions used for gold etching can react with acid, generating the deadly gas HCN. Proper ventilation and personal protective equipment (PPE) such as face shields, aprons, and safety goggles are required while working with these solutions. Disposal of large quantities of these hazardous solutions can also be very costly.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH11.qxd

04/04/2005

19:48

Page 11.8

WET ETCHING 11.8

WAFER PROCESSING

REFERENCES 1. Knotter, D. M., “Etching Mechanism of Vitreous Silicon Dioxide in HF-Based Solutions,” J. Amer. Chem. Soc., 122(18), 4345–4351, 2000. 2. Almanza-Workman, A. M., S. Raghavan, and R. P. Sperline, “In Situ ATR-FTIR Analysis of Surfactant Adsorption onto Silicon from Buffered Hydrofluoric Acid Solutions,” Langmuir, 16, 3636–3640, 2000. 3. Zhang, P., et al., “Fundamental Studies of Surfactant Interactions with Silicon Surface Using ATR-FTIR Technique,” at SEMACH Cleaning Workshop, 2003. 4. Iwai, H., et al., “Advanced Gate Dielectric Materials for Sub-100 nm CMOS,” 2002 IEDM Conf., IEDM Digest, 625–628, 2002. 5. Christenson, K., et al., “Selective Wet Etching of High-κ Dielectrics,” 2002 UCPSS Conference. 6. Watanabe, D., et al., “Selective Wet Etching for High-κ Material by Organic Solvent Containing Hydrofluoric Acid,” 2003 Semiconductor Pure Water and Chemicals Conference, p. 117. 7. Pearton, S. J., “Wet and Dry Etching of Compound Semiconductors,” In Handbook of Compound Semiconductors—Growth, Processing and Devices, Hollaway, P. H., McGuire, G. E. (eds.) William Andrew Publishing, Park Ridge, NJ, 1995. 8. Ashby, C. I. H., “Etching of GaAs in Properties of GaAs,” 2d ed., EMIS Data Review Series, INSPEC, London, 1990. 9. Adachi, S., “Properties of InP,” EMIS Data Review 6, INSPEC, London, 1990. 10. Kovacs, G. T. A., Maluf, N. I., and Petersen, K. E., “Bulk Micromachining of Silicon,” Proc. IEEE, 86, pp. 1536–1551, 1998.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 12

PLASMA ETCHING Shouliang Lai Unaxis USA, Inc. St. Petersburg, Florida

12.1 INTRODUCTION Plasma is an assembly of ions, electrons, and neutrals in which the motion of particles is dominated by electromagnetic interaction. Plasma as a whole is electrically neutral.1 Since the 1960s plasma has been employed in etching processes to replace wet chemical etching in semiconductor manufacturing.2,3 The driving force is that modern semiconductor manufacturing depends on mass replication of tightly controlled micron-sized features, and plasma etching is the only technology capable of doing the job efficiently and effectively. Advanced plasma etching technology is capable of faithfully transferring submicron patterns, satisfactorily controlling process uniformity, readily adapting to wide varieties of materials, and effectively reducing chemical wastes and pollution to the environment. In the last decades, plasma etching was stimulated by and greatly contributed to the progress of semiconductor technology. 12.1.1 Plasma Fundamentals Plasma can be described by various parameters including plasma density, temperature, pressure, frequency, sheath thickness, Debye length, skin depth, and so forth. A number of excellent books discuss plasma physics at great length and in rigorous detail.4–6 Also, some books cover specific plasma topics related to plasma processing.7–9 Here, only a simplified picture is provided to illustrate the aspects of plasma relevant to etching processes. Plasma can be started by supplying external dc or radio frequency (RF) power to pairing electrodes in an evacuated chamber. Gas ionization is initiated and amplified by electron/molecule collisions. With the ongoing input of RF energy and gases into the chamber, the electron/molecule collisions continue to generate ions, electrons, and neutrals. Exposed surfaces within the chamber absorb and neutralize these species. After a transient period, a steady state is reached so that the generation and loss processes are balanced. At this point, the discharge is characterized by a bulk glow region and dark sheath regions, as illustrated in Fig. 12.1a. The bulk region is semineutral, with nearly equal number of negative and positive particles. The sheath region is depleted with charged particles. Particles drift to the boundary of the bulk region in a random thermal motion and sweep across the sheath region. Due to the difference in mobility, more electrons than ions move toward the chamber wall initially until a steady state is reached, at which equal fluxes of ions and electrons are swept across the plasma sheath. As such, the chamber wall has a negative potential Vf relative to the floating potential of the plasma Vp. Hence, there is an electrical field across the sheath, as illustrated in Fig. 12.1b. This electrical field exerts a dc bias to accelerate

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

12.1

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.2

PLASMA ETCHING 12.2

WAFER PROCESSING

positive ions toward the substrate placed on the cathode, facilitating sputtering etching. The dc bias can also be influenced by a separate external power supply. Plasma also facilitates etching by means of reactive etchant species. For example, free fluorine (F) atoms can be generated in SF6 plasma through dissociation, ionization, and attachment reactions as described next. The F atoms react with silicon atoms spontaneously to form a volatile product SiF4 that desorbs from the substrate surface and is pumped away.

Plasma Ions, electrons, neutrals Sheath

Substrate

Dissociation reactions Cathode

(a)

+

e− + SF6 = SF5 + F + e− e− + SF5 = SF4 + F + e− e− + SF4 = SF3 + F + e− Ionization reactions e− + SF6 = SF5+ + F + 2e− e− + SF6 = SF3+ + F2 + F + 2e− e− + SF4 = SF3+ + F + 2e−

Vp

Attachment reactions −

Vf (b)

FIGURE 12.1 (a) Conceptual illustration of plasma (the lower electrode is powered). The discharge is characterized by a bulk region and a sheath region. (b) Potential across the plasma. At the steady state, the electron and ion fluxes to chamber wall are equal. The chamber wall has a floating potential Vf that is negative relative to the plasma potential Vp.

e− + SF6 = SF5− + F e− + SF4 = SF3− + F Plasma has several properties important to etching. First, the high electron temperature (104 to 105 K) in plasma allows and enhances reactions that are otherwise not possible under normal conditions. Second, ions are drawn out of the plasma surface and accelerated to energies of tens to hundreds of electronvolts with a direction normal to the electrode surface, thus facilitating anisotropic etching. Third, plasma density and ion influx can be controlled effectively, allowing for process flexibility.

12.1.2 Plasma Etching Mechanisms Generally, plasma etching mechanisms can be grouped into four functional categories—sputtering, chemical etching, ion-enhanced etching, and sidewall inhibitor etching. In sputtering (Fig. 12.2a), positive ions are accelerated across the sheath, which is just above the substrate, and strike the substrate surface with high kinetic energy (>100 eV). Some of the energy is transferred to surface atoms that are then ejected and removed from the substrate at low pressure. The resulted etch profile is typically tapered, has low etch selectivity, a rough etch surface, and can result in significant damage. In chemical etching (Fig. 12.2b), active etchant species generated in the plasma are transported to the substrate surface and chemical reactions take place to form volatile products. Since etching is nondirectional in the absence of ion bombardment, significant undercutting of mask and loss of critical dimensions can result. But etch selectivity is high, depending on the difference in the etchant’s chemical affinity for various substrate materials. In ion-enhanced etching (Fig. 12.2c), ions accelerated across the sheath disrupt the surface being etched, enhance the chemical reactivity, and improve desorption of volatile etch products formed at the surface. An anisotropic profile is obtained due to directional ion bombardment.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.3

PLASMA ETCHING PLASMA ETCHING

Ion +

Volatile product

(a) Sputtering

Neutral

Neutral

Ion +

12.3

Volatile product

(c) Ion-enhanced etching

Volatile product

(b) Chemical etching

Neutral

Ion +

Volatile product

(d ) Sidewall inhibitor

FIGURE 12.2 The four basic mechanisms of plasma etching: (a) sputtering in which ions strike the substrate surface and eject substrate materials at low pressure, (b) chemical etching in which neutrals in the plasma react with substrate materials to form volatile products, (c) ionenhanced etching in which ions strike the substrate surface, enhance chemical reactivity at the surface, and improve desorption of volatile products, and (d) sidewall inhibitor etching in which an inhibitor is formed on the sidewall and disrupted on the horizontal surface.

In sidewall inhibitor etching (Fig. 12.2d), a polymer-forming gas is added to the plasma to facilitate the formation of a thin film on feature sidewalls. If ion scattering is low, chemical attacks on the sidewall are inhibited. The horizontal surfaces intercept most of the normal-going ion flux and the inhibitor does not form on the surfaces. As such, an anisotropic etch profile is obtained. 12.1.3 Plasma Etching Systems Plasma etching equipment has evolved significantly since the first “barrel” etcher appeared in the late 1960s.2 The barrel etchers were used to remove residuals after photoresist processing with oxygen gas. Later, they were used to etch silicon using fluorine-containing gases such as CF4. In the 1970s, capacitively coupled planar diode systems were developed for the benefit of energetic bombardment in improving etch rates.10,11 However, a diode system was unable to control ion energy and ion flux independently. Triode systems were developed in the mid-1980s to circumvent such limitations. Dual frequency systems were developed to mitigate ion bombardment to the top electrode in capacitively coupled systems. The inductively coupled plasma (ICP) and other wave sources were developed for high-density plasmas. A more detailed history of plasma etching equipment can be found elsewhere.8,12 To classify plasma etchers, several criteria including frequency, pressure, external power source, load size, and vicinity of the substrate to the plasma source can be used. Often, selection of a plasma etching system in hardware and chemistry has to be based on experience. Nevertheless, many available variations in equipment, gases, operating conditions, and desired results require that limits be put on the range of process parameters that can be reasonably explored. Table 12.1 summarizes plasma etcher classifications using a few selected criteria.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.4

PLASMA ETCHING 12.4

WAFER PROCESSING

TABLE 12.1 Plasma Etcher Classifications Criteria Frequency

Pressure

External source

Categories

Descriptions

Low frequencies High frequencies Microwave Ultralow (≤0.1 mTorr) Low (≤100 mTorr) High (> 100 mTorr) Capacitively coupled

↑ <1 MHz. Matching network is needed to adapt impedance. ↑ <40 MHz. 13.56 MHz is the most widely used. ↑ Usual frequency is 2.45 GHz. Stub tuner is often used for matching. Diffusion pumps, cryopumps, and turbo pumps are required. Turbo pumps and blowers are required. Mechanical pumps and blowers are required. ↑ With one or more electrodes, and “L” matching network. ↑ Plasma density limited to <1016 m−3. ↑ Preferred pressure range of 100–1000 mTorr. ↑ No independent control of plasma density and bias in diode systems. ↑ RF coils separated by dielectric wall. L-C matching network. ↑ Frequencies in the range of 1–40 MHz, pressure 1–100 mtorr. ↑ High-density plasma, ne ≥ 1017 m−3. ↑ Independent control of plasma source power and bias power. ↑ External DC magnetic field required. ↑ ECR: Typical freq 2.45 GHz; Helicon: typical 13.56 MHz. ↑ ECR: matching usually with a three-stub tuner. ↑ Most in ion beam etching20. ↑ Bias applied to conducting materials in high-frequency discharge21. Substrate to be etched is placed directly in the plasma. ↑ Wafers placed away from plasma region. ↑ Used to minimize plasma charging damage22. ↑ Each wafer is etched in identical environment. ↑ Multiple wafers are processed simultaneously.

Inductively coupled (ICP)13–16

Wave (ECR,17 Helicon18,19) DC bias Substrate vicinity

Closely coupled Downstream

Load size

Single wafer etcher Batch systems

12.2 PLASMA ETCHING IN SILICON-BASED IC DEVICES Plasma etching has the advantage of faithful pattern transfer in the manufacturing of modern integrated circuit (IC) devices as the critical dimensions of the devices have shrunk to the submicron regime. Over the last two decades, there have been widespread applications of the plasma etching technology in making IC devices, along with tremendous progress in the plasma etching technology itself. This section surveys some of the prevalent aspects, among which are etch rate, etch directionality, selectivity, uniformity and damage, and contamination, in plasma etching of materials involved in mainstream IC devices. 12.2.1 Silicon Etching Anisotropy of Etching. Etching of silicon can be accomplished using F-, Cl-, and Br-based chemistries as the etch products are volatile SiF4, SiCl4, and SiBr4, respectively. For Cl- and Br-based chemistries, anisotropic plasma etching is caused by the action of neutral gas-solid reactions, which is stimulated by directional ion bombardment. In other words, ion-enhanced etching is responsible for anisotropic etching results. For F-based chemistries, however, an inhibitor-assisted mechanism needs to be involved to achieve anisotropy. Ion-driven anisotropy. The plasma sheath bias propels positive ions onto the substrate at normal incidence. Under appropriate conditions, this kind of ion bombardment stimulates anisotropic etching. It is also important to realize that ions play yet another critical role in Si etching—the reactions between the substrate and neutral species are significantly accelerated by ion bombardment. For example, at room temperature chlorine alone does not etch silicon, and the sputtering etch rate by Ar+ too is very small. However, in a plasma where both energetic Ar+ ions and free Cl atoms are present,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:49

Page 12.5

PLASMA ETCHING PLASMA ETCHING

the Si etch rate is dramatically higher, as shown in Fig. 12.3.23 Inhibitor-Assisted Anisotropy. In inhibitorassisted anisotropy, a layer of inhibitor forms on the vertical sidewalls of features and protects the sidewalls from reactive neutrals, while ion bombardment suppresses inhibitor formation on the horizontal surfaces being etched. When F-based chemistries are used to etch silicon, the reaction between F and Si is spontaneous and isotropic in nature. Thus an inhibitor on the sidewall is required to achieve anisotropy. Inhibitor films are usually formed from a feed gas additive such as C2F6 and CHF3. Unsaturated species, for example, CF2 radicals and other derivatives, polymerize to form thin films on surfaces. In other situations, a resist mask facilitates the growth of an inhibitor film by serving as a catalyst or a source of inhibitor.24,25

12.5

Ar+ + Cl2 gas

Ar+ only

Si etch rate (Å/min)

Geng(SMH)_CH12.qxd

10

5

0

200

400 Time (s)

600

FIGURE 12.3 At room temperature, Cl2 does not etch undoped Si without ion bombardment. At 450 V bias, Ar+ sputters Si slowly. But the etch rate of Cl2 combined with Ar+ bombardment is dramatically faster.

Etch Rate Doping effects. Free chlorine and bromine atoms do not etch single-crystal silicon spontaneously. Studies have shown that chlorine atoms on a silicon surface, for example, have to overcome an energy barrier of approximately 10 eV to attack Si-Si bonds and form SiCl4.26 Cl and Cl2 etch undoped Si very slowly (approximately 100 Å/min at less than100°C and 100 mtorr) or not at all, depending on the crystallographic orientations. However, Cl will etch undoped Si in the presence of energetic ion bombardment. The chemical etching of silicon is strongly affected by the type and concentration of electrically active dopants. In chlorine plasma, heavily doped (approximately 1020 cm−3) n-type (100) and (111) silicon and polysilicon are rapidly and spontaneously etched by free Cl atoms, and the etch rate can be as much as 15 to 25 times faster than that of undoped substrate.27,28,30–32 However, heavily doped p-type (B-doped) silicon is etched slower than undoped silicon.33 In fluorine plasma, a similar effect is observed—high concentrations of n-type dopants (approximately 1019 cm−3) enhance the etch rate by a factor of 1.5 to 2, while p-type dopants slightly suppress silicon etch rates by as much as a factor of 2.34–37 The enhancement in etch rate is related to the concentration of active carriers (i.e., the Fermi level) rather than the chemical identity of the dopant. Unannealed or electrically inactive dopant implants have a minimal influence on the etch rate.29,38,39 Gas addition effects. Halocarbons and their mixtures with oxidants such as O2, Cl2, and NF3 are used for practically all plasma processing. Unsaturated halocarbon radicals and oligomers usually are the precursors to inhibitor formation on silicon sidewalls. If excessive concentrations of unsaturated species are present in the plasma, they may produce gross amounts of polymers and stop etching. The addition of small amounts of O2 to CF4 plasma is known to increase F atom concentration in the plasma dramatically.40,41 This is due to the reaction of O2 with CFx radicals to form CO, CO2, and COF2 and liberate more fluorine. Thus, polymer formation will be suppressed and etching will be enhanced. However, with increased addition of O2 beyond approximately 20 percent in concentration, fluorine atom concentration decreases due to dilution. Similar effects of oxygen addition may occur for chloro- and bromocarbon plasmas (such as CF3Cl, CCl4, and CF3Br) in which an increase in Cl or Br concentration and a decrease in the formation of a polymer may result.42 The addition of small amounts of H2 to CF4 plasma reduces F atom concentration because of HF formation. A lower F atom concentration decreases the importance of recombination of F with CF3 radicals and results in a discharge rich in unsaturated fluorocarbons such as CF2. Thus polymer formation Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.6

PLASMA ETCHING 12.6

WAFER PROCESSING

is enhanced and etching is suppressed. The addition of H2 to mixed halocarbon-based plasma such as CClF3 has similar effects as observed with CF4 plasma.43 Such effects can also be achieved by adding CH4, C2H4, CHF3 or alternatively C2F6, C3F8, and so forth to CF4 discharge. The underlying principle of manipulating the balance (or imbalance) between polymer formation and etching is to influence the F/C ratio in the plasma.44 Noble gases such as Ar and He are often added to stabilize plasma. Ar addition is known to cause inert ion bombardment of surfaces, and results in anisotropic etching in reactive ion etching (RIE) of silicon in Cl2 plasma. Some believe that the addition of the chemically inert gas may significantly change the electron energy distribution in plasma and alter the reactive species population. For example, the addition of He, Ar, and Kr in BCl3 plasma was found to enhance the dissociation of BCl3.45 The addition of inert gas also dilutes etchant concentration in plasma. Etch Selectivity. Etch selectivity defines the relative etch rates of materials in a plasma. Etch selectivity of Si is required with respect to the etch mask, due to the implications in the choice of mask materials and pattern transfer fidelity, or to the underlayer materials if overetch needs to involved. Three mechanisms can be responsible for the attainment of etch selectivity: 1. Selective formation of etch inhibitor layer on one material. Take fluorocarbon-based plasma etching of Si and SiO2, for example. Both F-induced etching and film deposition take place in CHF3 plasma. If the process conditions are chosen so that etching and deposition are nearly balanced on SiO2, this balance may be tilted to deposition on Si. This is possible because the gasphase precursor for passivating film has higher sticking coefficients and different reactivity with the Si surface. 2. Nonreactivity of a material in plasma. Ashing of photoresist on a SiO2 film in O2 plasma is an example. The photoresist layer volatizes by forming C-O, H-O, and other related species, but the SiO2 layer is not attacked by the O2 plasma. 3. Nonvolatility of reaction product. An example is ashing of photoresist on the Si surface in O2 plasma. Involatile silicon dioxide will be formed on the Si surface but the photoresist layer volatizes by forming C-O, H-O, and other related species. The most often used mask materials on silicon are photoresists and SiO2. A photoresist is attacked in O2 plasma and chlorine plasma, so selectivity is low. The presence of energetic ions in the plasma also reduces the selectivity of resist masks. The oxide mask is frequently used in etching Si trenches, patterning of polysilicon gate contacts over gate oxide, and a great number of other steps. Normally, high Si/SiO2 etch selectivity of ≥30:1 is possible using F- and Cl-based plasmas. But due to high Si/SiO2 etch selectivity, a thin native oxide layer on Si can completely prevent etching of Si or, if nonuniformly etched, cause grass formation on the Si surface. When etching SiO2 with Si as an underlayer, it is usually difficult to obtain good etch selectivity in CF4 or C4F8 plasma. However, adding 30 to 60 percent of H2 to the CF4 plasma makes it possible to minimize the etching of Si as compared to the etching of SiO2.46 Si etch rate monotonically decreases as the percentage of H2 is raised and eventually Si etch stops, while only a small decrease in SiO2 etch rate is observed. Addition of CHF3 to CF4 plasma can also achieve similar results.47 Etch Uniformity. Etch uniformity refers to two things—the evenness of etch rate across a wafer and the degree to which etch rates are maintained from wafer to wafer in the same etcher. Uniformity is more dependent on hardware configurations. So this is the area where plasma etch equipment makers have invested great efforts in innovation, as evident by the presence of vast amounts of patents. Nevertheless, there are several common factors that influence etch uniformity: • Uniformity of etchant species, which is controlled by gas flow, chamber configuration (for example, spacer and confinement ring), and plasma parameters such as pressure. • Uniformity of ion density in plasma. The nonuniformity of ion density can be affected by chamber configuration such as spacer and confinement ring. Figure 12.4 gives an example in an ICP chamber. The nonuniformity affects ion-enhanced etch processes prominently.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.7

PLASMA ETCHING PLASMA ETCHING

12.7

1.6E+17 Ar plasma P = 5 mT

No focus ring

Ion density (m−3)

1.2E+17

8.0E+16 With focus ring

4.0E+16

0.0E+00 0

5

10

15

20

25

30

35

Position (cm) FIGURE 12.4 Nonuniformity in ion density in an ICP plasma chamber measured by a Langmuir probe.48 Ion density is higher toward the center of the chamber. The focus ring inside the plasma chamber reduces ion density but increases nonuniformity in ion density.

• Macroloading effects. Such effects are related to localized depletion of etchant and mass-transport limitation. • Microloading effects. High concentrations of materials in a localized area of a fine pattern would induce etchant depletion and etch variation. • Condition of plasma chamber. Variations in process conditions such as temperature over time also cause nonuniformity from wafer to wafer. Damage and Contamination. Wafers are exposed to bombardment by energetic particles (ions, electrons), photons, and soft x-rays in plasma. Most ions bombard wafer surfaces with energies below a few tens of electron volts, yet some ions may have energies more than 1000 eV in the energy distribution and cause atomic displacement in layers up to 150 Å deep. The average electron energy in plasma ranges from a few to 10 eV or more. Electron-hole pairs can be created by the primary ionization from UV and x-ray photons, and defect centers can be generated by secondary ionization. Polymeric products during etch processes are often the source for contamination on etched surfaces. Damage and contamination can be detected as a change in the capacitance versus voltage (C-V) characteristics of metal-oxide-semiconductor (MOS) capacitors, contact resistance, breakdown voltage, leakage current, flatband voltage, lifetime, and other parameters.49 Table 12.2 provides a brief summary of damage types, sources, and recoverability. 12.2.2 Dielectric Materials and Metal Etching Besides silicon, a variety of materials need to be etched in the manufacturing of IC devices. The most prominent materials are silicon dioxide, silicon nitride, photoresist, silicides, and metals. Many plasma etching principles discussed so far are still valid in etching these materials. When choosing chemistries, for example, the volatility of reaction products is a cause of concern. Often, ion-enhanced etching has to be involved to increase etch rates and control anisotropy. And in some cases, gas additions play critical roles in etching materials. Table 12.3 briefly summarizes plasma chemistries for selected dielectric, metallic, and silicide materials.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.8

PLASMA ETCHING 12.8

WAFER PROCESSING

TABLE 12.2 Damage and Contamination in SI Etch Processes Reversible damages Atomic displacements

↑ Include lattice damage, impurity penetration, defect center, etc. ↑ UV photon damage can be removed by thermal anneal at 350°C. ↑ High-energy ion damage is removed by annealing at 650°C. It can be reduced by lowering RF bias and/or independent control over plasma density and bias. ↑ X-ray damage may require annealing at temperature up to 950°C. X-ray damage can be minimized by using insulating materials in reactor parts. Irreversible damages

Surface residues Heavy metal contamination Loss of dopant or its activity Surface roughness Gate-oxide breakdown

↑ Intrinsic, such as excessive polymer or involatile etch product formation. ↑ Extrinsic, such as impurities from chamber configuration. ↑ Transition metal (Fe, Ni, Cr) contamination from sputtering of stainless steel parts of a chamber. It can be reduced by lowering plasma potential.50 ↑ For example, etching Si in CHF3 and CF4/H2 plasmas causes the loss of dopant activity in the near-surface region through hydrogen-boron interaction.51 ↑ Micromasking due to sputtering and redeposition of Al. ↑ Replication of the surface roughness from overlayer. ↑ Caused by transient surge current as RF power is turned off and coupling capacitor discharge and charge buildup during etch.52,53 ↑ Charging or discharging during photoresist ashing processes.

12.3 PLASMA ETCHING IN Si-BASED MEMS DEVICES MEMS (Microelectromechanical systems) device manufacturing presents a different set of challenges to plasma etching technology. For example, unlike IC devices that have transistors as the basic building blocks, MEMS devices do not have relatively uniform and standardized architectures across different devices. Nevertheless, there are some common requirements often encountered. For example, many MEMS structures frequently have depths ranging from tens to hundreds of micrometers, and high etch rates are thus needed to maintain good throughputs and ensure productivity. Other critical requirements include high etch selectivity to mask materials, good anisotropy control, smooth sidewall, and other satisfactory etch performances.

TABLE 12.3 Selected Materials and Etchant Chemistries Used in IC Device Manufacturing Materials

Chemistry

Additive

Remarks

Oxide Nitride Polymers Al W Al(Cu) Cr Au TiSi2 Wsi2 MoSi2

CF4, C4F8, CHF3, NF3 CF4, NF3, CHF3, SF6 O2 Cl2 CF4, SF6 Cl2 Cl2, CHCl3 Cl2 CCl2F2 CF4, SF6 Cl2, SF6, CF4

H2, O2, CO2 H2, CO2 CF4, C2F6 BCl3, SiCl4 O2 BCl3, SiCl4 O2

Etch selectivity to Si Characteristics intermediate to Si, SiO2 Addition of fluorinated increase rate Removal of native aluminum oxide

H2, CO2 O2 O2

Cu removal, ion bombardment Addition of O2 near 1:4 typical Temperature and ion energy Control of oxygen impurities

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.9

PLASMA ETCHING 12.9

PLASMA ETCHING

12.3.1 Time Division Multiplex Etch Process Conventionally, single-step plasma etch processes cannot simultaneously meet the requirements described previously. So for silicon-based MEMS device manufacturing, time division multiplex (TDM) etch processes have been developed.54,55 TDM etch processes employ alternating plasma deposition and etching steps. In deposition steps, octofluorocyclobutane (C4F8) is used and in etching steps sulfurhexafluoride (SF6) is used. As shown schematically in Fig. 12.5a–d, during an etching step, free F atoms promote isotropic and spontaneous reaction with silicon. During a deposition step, C4F8 plasma promotes Teflonlike polymer passivation on all surfaces. In the subsequent etching step, on directional energetic ion bombardment, the polymer film formed at the bottom of the etched structures will be preferentially removed to expose the silicon surface for further etching, while passivation on the sidewalls remains to inhibit lateral etching. A TDM etch process employs the alternating deposition and etching steps in a repetitive fashion. This approach allows highaspect-ratio features to be defined into silicon substrates at high etch rates. Figure 12.5e exhibits a cross-sectional scanning electron microscope (SEM) image of etched Si trenches. A simplified physical model can be used to describe a TDM process. As shown in Fig. 12.6, for a complete deposition/etch cycle, the deposition step lasts for time t1 and the etch step for t2. In the deposition step, a thin layer of polymer with a thickness of a1⋅t1 is deposited, where the deposition rate is denoted as a1. In the etch step, however, the first portion of time is spent in removing this layer of deposited polymer from the bottom of the feature. If the polymer removal rate is a2, the time left for further etching of silicon in the etch step is then t = t2 −

(a)

(b)

(c)

(d )

Mask

Si

(e)

FIGURE 12.5 Schematic illustration of TDM etch processes: (a) A Si wafer with patterned mask, (b) an etching step in which F radicals facilitate isotropic etching, (c) a deposition step in which polymer forms on all surfaces, (d ) a subsequent etching step in which the polymer at the horizontal surface is preferentially removed subject to direct ion bombardment, and (e) a cross-sectional SEM image of Si trenches etched in a TDM process.

a1 ⋅ t1 a2

(12.1)

Given the isotropic silicon etch rate a3, the etch depth achieved during this complete deposition/etch cycle is expressed as a ⋅t   L = a3 ⋅ t = a3 ⋅  t2 − 1 1  a2  

(12.2)

Assuming the three rates are independent of the depth of etch features, the overall TDM etch rate in a TDM process is then expressed as R = a3 ⋅ t ⋅

a ⋅t  1 1  = a3 ⋅  t2 − 1 1  ⋅ a2  t1 + t2  t1 + t2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

(12.3)

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.10

PLASMA ETCHING WAFER PROCESSING

t1

Isotropic etch

12.3.2 Etch Rate Removal

Deposition

12.10

t2

a1: Passivation rate a2: Passivation removal rate a3: Si Isotropic etch rate FIGURE 12.6 A simplified model for TDM etch processes. In a complete deposition/etch cycle, the deposition step lasts for a period of time t1 and the etch step for t2. a1, a2, and a3 are the deposition rate, polymer removal rate and isotropic silicon etch rate, respectively.

Insights in the overall etch rate R of a TDM etch process can be gained from the TDM model. First, increasing the isotropic silicon etch rate a3 could increase the TDM etch rate. In this regard, increases in ICP source power, SF6 gas flow rate, and chamber pressure play dominant roles. Figure 12.7 schematically shows that the isotropic Si etch rate increases with the ICP source power and SF6 gas flow rates. Improving the etch rate by increasing the ICP power and etch gas flow rate is essentially a “brute force” approach in a sense in that it generates more F radicals in plasma. Another way to increase F concentration is to use magnetic confinement to minimize radical loss to chamber walls. Second, if step times are fixed, etch rate R can be improved by increasing the polymer removal rate a2, which can be realized at a higher bias voltage. Of course, one could reduce the polymer deposition rate a1, but this would lead to insufficient polymer protection on the sidewalls. Third, if plasma conditions are fixed, increasing the ratio of t2 /t1 will result in a higher TDM etch rate. In this case, the verticality of etch features could be affected.

12.3.3 Sidewall Smoothness One limitation of TDM etch processes is the roughened sidewalls known as sidewall “scalloping.”56,57 A cross-sectional SEM image of an etched Si trench sidewall in Fig. 12.5e demonstrates the scallop formation. Equation (12.2) provides some insights into the scallop formation. The scallop length, i.e., peak-to-peak dimension, is the etch depth achieved during a deposition/etch cycle. If one improves the TDM etch rate R by making the etch step more aggressive, the etch process will form larger scallops and hence rougher sidewalls. So scallop length is often directly linked to the TDM Si etch rate, meaning that high etch rates are often achieved at the expense of rougher sidewalls in TDM etch processes. One can minimize scallop formation by replacing the isotropic etching steps with anisotropic etching steps. For example, the addition of oxygen (O2) or nitrogen (N2) gas to the SF6 gas in the etch steps would induce oxide or nitride formation on the silicon sidewall thus slowing down the lateral etching

Si etch rate (µm/min)

SF6 flow

ICP power FIGURE 12.7 Isotropic silicon etch rates in SF6 plasma. Increasing ICP power and SF6 flow rate leads to increase in the isotropic etch rate.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.11

PLASMA ETCHING PLASMA ETCHING

12.11

at sidewall. Although this approach reduces scalloping, it is at the expense of the overall feature profile. Oxide or nitride passivation layers are typically very thin, leading to difficulties in controlling the profile. Also, oxygen-scavenger gases (such as CHF3, C4F8, and CF4) need to be added to the plasma to minimize oxide formation on the etch front to obtain the desired overall etch rate. An alternative approach to minimize scallop formation is to use shorter etch steps.56,58 Keep in mind, however, that in TDM etch processes, different gases are introduced into a reactor at different flow rates and chamber pressures are maintained at different levels as required. For example, in etch steps, etchant gas SF6 is introduced into the reactor and C4F8 gas is excluded from it; in deposition steps, C4F8 gas is introduced into the reactor and SF6 gas should be excluded. Such abrupt gas changes are often not smooth and cause plasma instability. A fast gas switching technique has been developed to alleviate this problem.59 The gas switching technique, in combination with a technique controlling pressure alternations, eliminates the destabilizing pressure “burst” even when very short process cycles, that is, <1 s, are used. The challenge here is to minimize scallop dimensions while maintaining TDM etch rates. Again, insights can be gained through the TDM model. Rearrange Eqs. (12.2) and (12.3) as following: a t   L = a3 ⋅ 1 − 1 ⋅ 1  ⋅ t2  a2 t2 

(12.2b)

a t  1  R = a3 ⋅ 1 − 1 ⋅ 1  ⋅  a2 t2  1 + t1/t2

(12.3b)

According to Eq. (12.3b), the etch rate does not change if the etch/deposition duty cycle remains constant. Yet in Eq. (12.2b), the scallop length can be made smaller if the etch step is shorter. In a series of experiments shown in Fig. 12.8, the step duty cycles were fixed at 50 percent—equal time for etching and deposition steps, while process step times were varied from 1.0 to 1.5 s. As a result, large scallops resulted on the Si sidewall in longer process steps. But when the process steps became shorter, scallop dimension was progressively reduced. Figure 12.9 summarizes the TDM etch rate and scallop length in the experiments. The etch rate remains almost constantly at 3 µm/min as the scallop length decreases from 0.87 to 0.26 µm, for process step time ≥2.5 s. The TDM etch rate drops when the process step time is shorter than 2.5 s, probably due to gas residence time limitation that causes mixed gases in a plasma reactor and lowered process efficiencies. 12.3.4 ARDE Lag Reduction MEMS devices almost ubiquitously have structures with different dimensions and aspect ratios (ARs) that coexist on a single microchip, and plasma etching is needed to generate the structures at once. There is a well-documented aspect ratio dependent etching (ARDE) effect in silicon etching processes.60 The ARDE effect can be manifested in two ways—first, for a specific feature, the etch rate decreases as the aspect ratio increases over time; second, for features of different dimensions coexisting on the same substrate and etched simultaneously, wider features are etched at faster rates than narrower features. ARDE is a highly complex phenomenon and many mechanisms are proposed to explain it. In general, many factors contribute prominently to ARDE lag—ion flux loss at the bottom of the etched structure, reactive neutral species depletions due to neutral shadowing, and Knudsen transport.60–67 In addition, the interaction between passivation and etch process steps may also contribute to the ARDE effects observed in a TDM etch process. One of the approaches to cope with ARDE is to employ an etch stop layer, such as an oxide layer, to compensate the lag. However, disadvantages emerge sometimes when an insulating etch stop layer is used, which will be discussed in the next section. In TDM etch processes, the aspect ratio dependent effects can be exhibited in all the three fundamental processes—deposition, polymer removal, and isotropic etching. For example, in Fig. 12.10 the measured deposition rate and polymer removal rate as a function of AR are presented. However,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.12

PLASMA ETCHING 12.12

WAFER PROCESSING

(a) 10 sec/ 10 sec

(b) 5 sec/ 5 sec

(c) 2.5 sec/ 2.5 sec

(d ) 1.5 sec/ 1.5 sec

FIGURE 12.8 SEM images showing the scallop dimension is progressively reduced as process steps shorten. Times along the images are etch and deposition times.

it can be noted that the polymer removal is more weakly AR dependent, relative to the deposition process. One should also expect a similar AR dependence of the isotropic Si etch rate in F-based plasma. Given these facts, the question is—Can ARDE lag be reduced or eliminated? Once again, insights can be gained from the TDM model by recalling Eq. (12.2). Take two trenches A and B, for example. Trench A has a higher AR than trench B. At the bottom of trench A, a thinner layer Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:49

Page 12.13

4

1

3

0.75

2

0.5

Fixed duty cycle = 50% 1

Scallop length (µm)

Etch rate (µm/min)

PLASMA ETCHING

0.25

0

0 0

2

4

6 8 Cycle time (sec)

10

12

FIGURE 12.9 The overall TDM etch rate (left axis) and scallop length (right axis) when the duty cycle of etch/deposition steps is fixed at 50 percent. Scallop dimension is reduced with the retaining of a high etch rate.

120%

D0: Polymer thickness on trench top

100%

D1: Polymer thickness at trench bottom Polymer Mask

80%

D1/D0

Silicon

60% 40%

22.5 mT 18.0 mT

20%

15.4 mT

0% 0.00

1.00

2.00

3.00 Aspect ratio

4.00

5.00

6.00

(a) 15 Passivation removal rate (nm/s)

Geng(SMH)_CH12.qxd

RIE bias = 500 V

12 9 6 3 0 0.00

1.00

2.00

3.00

4.00

5.00

Trench width (µm)

(b )

FIGURE 12.10 Measurements on polymer deposition and removal rates as functions of aspect ratio: (a) polymer thickness in the trench bottom is normalized to that on the resist mask surface, and (b) polymer removal rate at the trench bottom is measured.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

12.13

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.14

PLASMA ETCHING 12.14

WAFER PROCESSING

of polymer is deposited during a deposition step. However, if the polymer removal rate is controlled so that it is relatively independent of AR, the time required to clear the polymer at the bottom of trench A will be shorter. So trench A will have an early start in the isotropic etching process. Despite a slower isotropic etch rate in trench A, the resulting etch depth in it could be the same as that in trench B by the time a deposition/etch cycle finishes. Indeed, plasma parameters can be controlled to achieve the elimination and even the reversing of ARDE lag.68 This is demonstrated in Fig. 12.11. In Fig. 12.11b, the ARDE lag is reduced to below 2 percent in trenches with widths ranging from 2.5 to 10 µm. In Fig. 12.11c, the ARDE lag is reversed, meaning the 2.5-µm-wide trench is etched 5 percent faster than the 10-µm-wide trench.

12.3.5 Notch Reduction in Silicon-on-Insulator (SOI) Etching

(a)

(b)

Certain MEMS applications require that a silicon substrate be etched down to an insulating layer that serves as an etch stop or a device function layer. In such instances, SOI wafers are often used as substrates. In more complex designs, an insulating layer can be “buried” between silicon layers. When an SOI wafer is etched in a TDM process, the so-called “notching” often occurs.69,70 This is evidenced as a localized undercutting of silicon at the silicon/insulator interface, as shown in Fig. 12.12a. It should be pointed out (c) that notching occurs in etching polysilicon too. In fact, the first discoveries of the notching phenomenon were made in FIGURE 12.11 Tailoring ARDE lag for polysilicon-on-oxide structures. trenches with widths ranging from 2.5 to 10 µm It is generally understood that electrical charging under different process conditions: (a) normal effects are responsible for notching.71,72 The charging lag (10 percent), (b) nearly zero lag (less than 2 effects are not present during bulk etch because the silicon percent), and (c) reversed lag (−5 percent). substrate is sufficiently conductive to ensure charge dissipation (see Fig. 12.13b). However, when the etch front reaches the silicon/insulator interface, the conductive current path is broken, allowing charge separation to occur. The resultant electric field is strong enough to bend the trajectories of arriving ions into the feature sidewall where lateral etching (notching) occurs, as shown in Fig. 12.13c. Thus notching occurs when overetch of a structure is involved. Also, notching can be affected by other factors including aspect ratio, RF bias voltage and frequencies, plasma density and electron temperature, and the thickness of the insulating layer. Approaches that can be adopted to reduce notching are strong sidewall passivation,73 charging reduction in low-density plasma, and charging relaxation.74 The charging relaxation approaches, which involve a time-modulated (pulsed) plasma source or RF bias, have found many applications in practice.75–77 The concept of using a pulsed ICP source to reduce notch formation is related to bias reduction in the after-glow plasma during the “off” state. However, if the source power does not completely extinguish, extremely high self bias voltages could result. In other words, this approach works better for low-pressure plasma in which the source can be switched off completely. On the other hand, the pulsed RF bias approach offers the opportunity for charge relaxation and subsequent charge neutralization at the trench bottom during the bias off periods. Typically, RF bias frequency, pulse length and duty cycle are among the dominant factors in determining the performance in notch reduction. Figure 12.13 demonstrates a successful example of reducing notch formation in

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.15

PLASMA ETCHING PLASMA ETCHING

+

+

Mask − − − Si

+ − − −

12.15

+ Mask − − −

− − − Si

Si Notch

SiO2 (a)

+ + + +

+ + + +

Insulator

Insulator

(b)

(c)

FIGURE 12.12 (a) Notching at the Si/oxide interface in a conventional TDM etch process, (b) current flow within the Si substrate prevents charge separation during bulk etch, and (c) charging effects cause notching to occur in the overetch period.

high-aspect-ratio structures. At an aspect ratio of 18:1, the notch size is <100 nm for 25 percent overetch; at aspect ratios exceeding 8:1, no notch is observed for significant overetch up to 50 percent.

12.4 PLASMA ETCHING IN III-V COMPOUND SEMICONDUCTORS III-V semiconductors are composed of an element from Column III of the periodic chart and an element from Column V of the chart. Indeed, III-V compound semiconductors encompass a variety of materials. Perhaps the best studied compound semiconductor is GaAs. Compared with Si, compound semiconductors have some technical advantages. For example, the higher mobility and saturated

FIGURE 12.13 Notch reductions using a time-modulated RF bias method. At an aspect ratio of 18:1, the notch size is less than 100 nm for 25 percent overetch; at aspect ratios exceeding 8:1, no notch is observed for significant overetch up to 50 percent.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.16

PLASMA ETCHING 12.16

WAFER PROCESSING

drift velocity for electrons in GaAs than in Si allow GaAs devices to operate at higher frequencies. Unlike Si, GaAs is a direct band-gap semiconductor and thus useful for fabricating optical devices. In etching III-V compound semiconductors, the same set of principles in silicon etching still hold true. Yet beyond the requirements of etch rate, selectivity, uniformity, and damage control, care must be taken to maintain chemical stoichiometry at the etched surface while etching III-V materials.78,79 Here the strategy is again to control the ion-driven and chemical-driven components to achieve the required balance. Thus, many plasma etching processes require independent controls of plasma density and bias to make such controls possible. This chapter will only focus on plasma etching of generic GaAs, InP, and GaN materials. III-V compound semiconductors are typically etched using halogen-based chemistries. Since the group III fluorides (i.e., GaF3) are involatile, most III-V etching is performed using chlorine-, bromine-, or iodine-based chemistries. Other chemistries, such as CH4, are also used to etch III-V materials. Table 12.4 provides some common gases used for plasma etching of III-V materials. 12.4.1 Etching of GaAs and Related Materials Front Etch of GaAs and Related Materials. Front etch of GaAs-based materials (including GaAs, AlGaAs, and GaSb) is used in making high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs). To etch GaAs, chlorine-based chemistry is often employed following an ion-enhanced chemical etching mechanism. The addition of oxygen scavengers, such as BCl3 or SiCl4, to the process gas mixture is often necessitated by the difficulty in initiating the GaAs etching process in Cl2 plasma.80 BCl3 and PCl3 gases are often added to Cl2 when etching AlGaAs materials. BCl3 and PCl3 have the ability to getter water vapor in the process chamber as well as attack aluminum oxide as it forms. The chemical reaction taking place is described as GaAs + 3 Cl2 ↑ = GaCl3 ↑ + AsCl3 ↑ However, the group V etch products (AsCl3) have a higher vapor pressure than the group III etch products (GaCl3). This volatility difference makes the removal of the group III (Ga) component in the material rate-limiting, and often results in rough post-etch morphologies and changed chemical stoichiometry. However, the volatility difference between AsCl3 and GaCl3 can be compensated by shifting the etch process from a chemical to a more physical regime and controlling substrate temperature. High-energy ion bombardments during etching helps equalize the removal rates in the different crystallographic planes thus resulting in smooth post-etch surface morphologies. Along the same line, when equirate and step-free etching is required in etching GaAs/AlGaAs device heterostructures, adjusting the chemical etching and ion-driven etching components, a balance can be reached so that the equirate is achieved. The other prominent issues are related to selectivity and damage control. For example, etching of GaAs over an AlGaAs etch stop is a key process in the fabrication of high-speed devices. In capacitively coupled 13.56 MHz RIE plasma processes, selectivity to the underlying AlGaAs etch stop was achieved through the addition of oxygen or fluorine to form nonvolatile AlF3.81 However, the high ion energies associated with the self-induced dc bias at 13.56 MHz results in device damage and compromises device performance. An alternative option is to use high-density plasma processes in inductively

TABLE 12.4 Common Gases Used for Plasma Etching of III-V Semiconductors Cl-based Br-based I-based CH4-based

Cl2, HCl, BCl3, CCl4, SiCl4, PCl3, ICl, CCl2F Br2, HBr, CF3Br, IBr, HBr/N2 HI, I2, CH3I, ICl CH4/H2, CH4/He, C2H6/H2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.17

PLASMA ETCHING PLASMA ETCHING

12.17

TABLE 12.5 Etch Rates and Selectivity coupled plasma and electron cyclotron resonance (ECR) in the Pulsed 40 MHz Plasma reactor configurations,82,83 to take advantage of the capability of independent control of the ion density and energy. The conEtch rates figurations allow for lower ion energies (dc bias <50 V) at higher ion densities. While the lower ion energies facilitate low GaAs etch rate 618.6 Å/min damage etching, the GaAs etch rates in high-density plasma AlGaAs etch rate 1.6 Å/min Si3N4 etch rate 14.2 Å/min are high, i.e., >1000 Å/min, making it difficult to control the Resist Etch rate 30.9 Å/min etch process for thin film (<1000 Å) applications. An improved approach is to use a parallel plate configuraSelectivity tion powered at 40.68 MHz in a time-modulated fashion.84 GaAs : AlGaAs 399:1 The high-frequency RF excitation results in lower dc bias GaAs : Si3N4 44:1 voltages, <30 V, compared to the 13.56-MHz RIE. In order to GaAs : resist 20:1 reduce the GaAs etch rate to controllable levels for thin film applications, the high-frequency RF power is pulsed. The etch rate during the “on” period remains unchanged (~1000 Å/min), while the etch rate during the off period is essentially zero. The average etch rate is thus a function of the pulse duty cycle and can be lowered. Table 12.5 summarizes the etch performance achieved using this approach.

Backside Etch of GaAs and Related Materials. GaAs is a relatively poor thermal conductor, making it difficult to remove heat efficiently from power devices. A solution is to form vias from the wafer backside to the frontside circuitry and metallize the vias.85 For a via etch process, since it is necessary to etch approximately 100 µm deep into the GaAs substrates, a high etch rate is essential to ensure a reasonable wafer throughput. Also, selectivity to a photoresist mask of at least 10:1 is desirable for photoresist processing. For good metallization, the via wall should have a sloped profile, with some control over the slope to accommodate the conflicting requirements of the wall slope and reduced via dimensions. As illustrated in Fig. 12.14, a combination of high GaAs etch rate, controlled selectivity to the resist mask, and a sloped resist profile facilitates sloped via etching.85 The high etch rate is achieved using an ICP source. Control over selectivity is through independent control of the bias voltage. The resist profile can be manipulated through hard bake. One of the issues in via etching is that pillar formation is sometimes observed.86 Pillar formation can arise from a number of causes including residues from upstream operations, material effects, and the plasma etching process. It is potentially harmful to the reliable metallization of the vias. It has been demonstrated that pillar formation can be reduced through the use of higher Cl2 flows, lower process pressures, and higher ICP powers.87 Lower RF bias powers during the etch initiation step also significantly reduce pillar formation. 12.4.2 Etching of InP Materials Indium-containing multilayer structures (including InP, InGaAs, and InGaAsP) are now prevalently used for long wavelength optical devices. Due to the difficulties associated with dry etching In-based materials, manufacturing has traditionally been low volume at high cost. In recent years, the demand for high etch rate for improved throughput is on the rise. For example, plasma etching of InP materials now involve processes in ICP sources using hydrocarbon-(CH4/H2-) and halogen (Cl-, Br-, and I-)-based chemistries.79,88 • CH4 /H2 chemistry results in a smooth surface due to near equal removal rates of volatile In(CH3)3 and PH3 products. The etching rate is considered slow at approximately 500 Å/min and polymer deposition causes contamination of both the etching module and the samples.89,90 • Cl2 chemistry is an alternative to etching In-based materials. Elevated temperatures are typically required to obtain high etching rates and acceptably smooth surfaces. The use of Cl2-based chemistries at substrate temperatures of 225°C to etch InP/InGaAsP with smooth surfaces and high etching rates has been reported.91,92 • HBr chemistries are also used to etch InP.93 The etch rate is approximately 1000 Å/min, along with a smooth surface and a positively sloped profile, at room temperature. As the substrate temperature

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.18

PLASMA ETCHING 12.18

WAFER PROCESSING

GaAs via wall slope versus photoresist slope (at various GaAs: PR selectivities)

GaAs via wall angle (degrees)

90 32

75

16

8 4

60 Selectivity (GaAs: PR)

45

2

Resist

1

30 15

GaAs

0 0

15

30

45

60

75

90

PR wall angle (degrees)

(a )

(b ) FIGURE 12.14 (a) Expected GaAs via wall angle as a function of resist slope and etch selectivity, and (b) a SEM image showing a sloped GaAs via.

increases, the etch rate and selectivity to hard mask increase. Generally, at temperatures more than 150°C, a high etching rate, selectivity, and smooth morphology can be achieved. The HBr/CH4 chemistry is used to minimize mask undercut and maintain a vertical profile. And out of concerns over chamber contamination, the HBr/N2 chemistry can be used. The etch performance includes a high etch rate (2.0 µm/min), good anisotropy (90 ± 1°), high selectivity (30:1), and excellent surface smoothness (RMS <2.0 nm). 12.4.3 Etching of GaN Materials Gallium nitride (GaN) is an important material used in an array of devices including light emitting diodes (LEDs), transistors, and laser devices. Bulk GaN is not commercially available, it is epitaxially

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:49

Page 12.19

PLASMA ETCHING PLASMA ETCHING

12.19

RF bias power (ion energy)

Geng(SMH)_CH12.qxd

ICP power (plasma density) FIGURE 12.15 Pit/pillar formation and elimination in GaN etching using Cl2 chemistry in an ICP system. Smooth surface morphology is obtained by balancing the chemical-driven and ion-driven etching components.

grown on an appropriate lattice matched substrate material such as sapphire or SiC. RIE, ECR, and ICP systems have been employed to etch GaN materials in different chemistries such as SiCl4, HBr, BCl3, CH4, and Cl2.94–99 The Ga-N bonds have high bond energies −8.9 eV versus 6.5 eV for Ga-As bonds. When GaN is etched in Cl-based chemistry, for example, GaCl3 production is kinetically slow in the absence of energetic ion bombardment so etching will not proceed. Also, defects in GaN appear to be particularly sensitive to etching conditions and respond by etching faster or slower, ultimately forming pits or pillars. Once again, the balancing effects with the ion-driven and chemical-driven components can be applied to control etch performance. An example of etching GaN with Cl2 chemistry in an ICP system is given in Fig. 12.15.100 When ICP power is increased, GaN etching is driven into a more chemical regime, resulting in pit formation. When the ion energy is increased by increasing RF bias power, etching is more ion driven resulting in pillar formation. But balancing the chemical- and ion-driven components leads to smooth etched surface. The small wafer sizes, coupled with cost pressures for GaN based devices, promote demands on high throughput capability in dry etching systems. One solution is to use an RIE process and run large batches of wafers. However, there is reduction in etch rate associated with increased loading, as can be understood from chemical mass balance. On the other hand, high-density ICP systems offer a capacity for high etch rates, and thus high throughput. A comparison of RIE and ICP performance is shown in Table 12.6.

TABLE 12.6 GaN Etching Comparison Process metric Etching rate (Å/min) Selectivity (GaN:hardmask) Nonuniformity percent Etched surfaces

Typical performance RIE 750 ≥ 5:1 ≤ ± 5 – 10 Smooth

ICP 5000 ≥ 10:1 ≤±3 Smooth

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.20

PLASMA ETCHING 12.20

WAFER PROCESSING

12.5 ENDPOINT DETECTION IN PLASMA ETCHING In many instances, overetch is mandatory primarily thanks to surface topography and etching uniformity implications. Yet overetch must be done with great care. For example, in modern MOS devices the gate oxide is extremely thin—less than 150 Å—rendering excessive overetch undesirable. Though high selectivity can be used to mitigate the situation, some requirements in anisotropy often compromise the high selectivity. Therefore, endpoint detection plays an important role in plasma etching processes. The sequence of events in a typical plasma etching process provides many possibilities for detecting the endpoint. When RF power is turned on, gases are ionized and etchant species are produced. These species react with substrate materials to produce the primary volatile products. Toward the end of the etch cycle, the underlying materials begin to be exposed and react with the etchant species to produce the secondary volatile products. Meanwhile, the concentration of the primary volatile products decreases. In the overetching period, the primary and secondary productions reach steady states. A variety of techniques can be constructed in principle: • Pressure change: Pressure increases initially when gas starts to dissociate. During etching, reactions consume gas molecules and thus cause a decrease in system pressure. After etching reaches the endpoint, pressure rises again. This technique was used in early batch etchers. Yet in modern dry etchers that maintain constant pressures, it is no longer used. • Bias change: During an etch cycle, the impedance and sheath characteristics change. This usually causes changes in the self-bias voltage in asymmetrical reactor geometries. In photoresist stripping, this is an effective technique for endpoint detection. • Mass spectrometry: Different chemical species are associated with the start and end of an etch cycle, and they can be monitored by mass spectrometry. In high vacuum—less than 1 × 10−5 torr— the process gas is sampled and specific etch products are detected. • Laser interferometry and reflectance: When monochromatic light rays are reflected from the front and underlying interface of a transparent film, constructive and destructive interference takes place. At normal incidence, interference maxima and minima occur when twice the thickness of film (d ) is the multiple of the wavelength (l) divided by the refractive index (n), as expressed in the following: d=

l ⋅n 2

(12.4)

In an etch cycle, the intensity of a monitoring laser beam varies sinusoidally when the film thickness changes. On the other hand, metal films are opaque but usually have high reflectance. So etching through a metal-semiconductor or metal-insulator interface is marked by a sharp change in the reflected laser intensity. • Optical emission spectroscopy (OES): Many chemical species from etchant and etch products are present in plasma and optical emissions can emanate at different wavelengths. An optical spectrometer can be set to the line of interest and follow its intensity during an etch cycle. This technique is capable of endpoint detection with great sensitivity. In practice, laser interferometry and OES are the two most commonly used techniques in plasma etching. They require only a suitably located optical window on the chamber and can be easily implemented. More elaborate data processing is often required to sort through collected spectra. One example is illustrated in a HEMT fabrication process.101 In this case a gate was defined in 2500 Å of GaAs on 500 Å of Al0.25Ga0.75As using a nitride mask. Figure 12.16a shows the optical emission spectra collected from main etch and overetch periods in the process. It is apparent that the “straight” OES endpoint strategy is not obvious in detecting the endpoint. However, the OES spectra can be processed to elucidate the difference between the main etch and overetch spectra with a focus on the 403-and 417-nm Ga lines. Figure 12.16b shows the derivative of the Ga signal. A clear and distinct endpoint was determined.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:49

Page 12.21

PLASMA ETCHING

Intensity (arbitrary units)

PLASMA ETCHING

12.21

Main etch

Overetch

300

400

500

600

700

800

Wavelength (nm) (a) 0.5

2.5 Ignition

Selective etch

2

0.25 Endpoint detected

1.5

0 1 −0.25

0.5

0

Ga signal slope

Normalized signal intensity (Ga)

Geng(SMH)_CH12.qxd

0

30

60

90

−0.5

Time (sec) (b) FIGURE 12.16 (a) Optical emission spectra from the GaAs/Al0.25Ga0.75As etch process during the main etch and overetch segments of the process, and (b) the derivative OES trace using the 417-nm Ga line for endpoint detection.

Another example is in the OES endpoint detection in the TDM etch processes in MEMS applications.102 Applying conventional OES methods to a TDM etch process in SOI wafers results in an end point trace that is periodic, as shown in Fig. 12.17 (thin solid lines). The 440-nm wavelength of SiF emission is assigned for OES monitoring. The majority of the etch endpoint information is contained within the etch segments of the process. But it is difficult to use the periodic trace for endpoint detection in automation. For this reason, a special algorithm is applied to convert and distil the raw spectra. An “envelop” trace of the OES spectra is then obtained to indicate the endpoint of Si etch process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.22

PLASMA ETCHING 12.22

WAFER PROCESSING

1.5

Intensity (arb. units)

Endpoint 1.4 1.3 1.2

Raw OES input data

1.1 1 0

100

200

300 400 Time (sec)

500

600

700

FIGURE 12.17 An example of OES traces in a TDM silicon etch process. The converted “envelop” trace (thick solid line) through a special algorithm is better in detecting the endpoint than the raw periodic trace (thin line).

12.6 CONCLUSIONS The materials that have been and will be etched in semiconductor manufacturing are vastly diverse, from mainstream to exotic. And the etch requirements, from etch rate, selectivity, anisotropy, uniformity to damage control, are always case-specific. Yet there are common principles that can be applied to formulate and tailor etch processes. This chapter outlines some of the processing principles in this regard, but only with a limited scope. Though discussions on the principles are illustrated separately in specific classes of etching application, it does not mean that these principles can only be applied to a certain type of material. For example, mechanisms underlying etch rate, selectivity, and anisotropy in etching silicon are equally applicable to etching compound semiconductors; mechanisms related to plasma chemistry and surface morphology and damage control in etching IIIV semiconductor can be applied to other compound materials such as II-VI semiconductors. There exists a wealth of publications discussing topics not addressed in this chapter. For example, plasma etching of photomask materials and magnetic materials can be found elsewhere.103,104 With respect to plasma technology itself, plasma reactor modeling,105 plasma diagnostics,106 and plasma safety have also been well covered.107 These topics are indeed inseparable aspects of plasma etching in semiconductor manufacturing.

ACKNOWLEDGMENTS I gratefully acknowledge the encouragement and support from my close colleagues—Russell J. Westerman and Dr. Dave Johnson. Mr. Westerman also helped enormously in furnishing some of the critical data, which made this chapter possible.

REFERENCES 1. CRC Handbook of Chemistry and Physics (CRC Press, Boca Raton, FL, 1979), p. F-121. 2. Irving, S. M., Solid State Technol., 14(6), 47 (1971). 3. Irving, S. M., K. E. Lemons, and G. E. Bobos, U.S. Patent No. 3, 615, 596.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.23

PLASMA ETCHING PLASMA ETCHING

12.23

4. Chen, F., Introduction to Plasma Physics (Plenum Press, New York, 1974). 5. Krall, N. A., and A. W. Trivelpiece, Principles of Plasma Physics (McGraw Hill, New York, 1973). 6. Golant, V. E., A. P. Zhilinski, and I. E. Sakharov, Fundamentals of Plasma Physics (John Wiley & Sons, New York, 1977). 7. Manos, D., and D. Flamm (eds.), Plasma Etching (Academic Press, San Diego, 1979). 8. Lieberman, M. A., and A. J. Lichtenberg, Principles of Plasma Discharges and Materials Processing (John Wiley & Sons, New York, 1994). 9. Shul, R. J., and S. J. Pearton (eds.), Handbook of Advanced Plasma Processing Techniques (SpringerVerlag, Berlin, 2000). 10. Hosokawa, N., N. Matsuzaki, and T. Asamaki, Jpn. J. Appl. Phys. Suppl. 2(1), 435 (1974). 11. H. N. Yu, et al., J. Vac. Sci. Technol. 12, 1297 (1975). 12. Popov, O. A. (ed.), High Density Plasma Sources (Noyes Publications, Park Ridge, NJ, 1995). 13. Lieberman, M. A., and R. A. Gottscho, Design of High Density Plasma Sources for Materials Processing in: M. H. Francombe and J. L. Vossen (eds.), Physics of Thin Films, Vol 18, pp. 1–119 (Academic Press, San Diego, 1994). 14. Holland, J. P., et al., Proc. SPIE 1803, 258 (1992). 15. Keller, J., J. Forster, and M. Barnes, J. Vac. Sci. Technol. A11, 2487 (1993). 16. Marks, J., et al., Proc. SPIE 1803, 235 (1992). 17. Suzuki, K. et al., Jpn. J. Appl. Phys. 16, 1979 (1977). 18. Boswell, R. W., and E. F. Chen, IEEE Trans. Plasma Sci. 25, 1229 (1997). 19. Stevens, J. E., M. J. Sowa, and J. L. Cecchi, J. Vac. Sci. Technol. A 13, 2476 (1995). 20. Harper, J. M. E., Ion Beam Etching, in: D. M. Manos and D. L. Flamm (eds.), Plasma Etching (Academic Press, San Diego, 1979). 21. Bruce, R., and A. Reinberg, J. Electrochem. Soc. 129, 393 (1982). 22. Cook, J. M., Solid State Technol. 30(4), 147 (1987). 23. Coburn, J. W., and H. F. Winters, J. Appl. Phys. 50, 3189 (1979). 24. Bernacki, S. E., and B. B. Kosicki, J. Electrochem. Soc. 131, 1926 (1984). 25. Oda, M., and K. Hirara, Jpn. J. Appl. Phys. 19, L405 (1980). 26. Seel, M., and P. S. Bagus, Phys. Rev. B23, 5464 (1981). 27. Schwartz, G. C., and P. M. Schaible, J. Vac. Sci. Technol. 16, 410 (1979). 28. Schwartz, G. C., and P. M. Schaible, J. Electrochem. Soc. 130, 1898 (1983). 29. Mogab, C. J., and H. J. Levenstein, J. Vac. Sci. Technol. 17, 721 (1980). 30. Leahy, M. F. Proceedings of the 3rd Symposium on Plasma Processing, Electrochemical Society, Pennington, New Jersey, 82–6, 176 (1982). 31. Cabral, S. M., D. D. Rathman, and N. P. Economou, Extended Abstracts, Electrochemical Society, Pennington, New Jersey, 83–1, 246 (1983). 32. Shibagaki, M., et al., Proceedings of the 3rd Symposium on Dry Processes, IEEE, Tokyo, 39 (1985). 33. Lee, Y. H., and M. M. Chen, J. Vac. Sci. Technol. B4, 468 (1986). 34. Lee, Y. H., M. M. Chen, and A. A. Bright, Appl. Phys. Lett. 46, 260 (1985). 35. Makino, T., H. Nakamura, and M. Asano, J. Electrochem. Soc. 128, 103 (1981). 36. Baldi, L., and D. Beardo, J. Appl. Phys. 57, 2221 (1985). 37. Borghesani, A. F., and F. Mori, Jpn. J. Appl. Phys. 22, 712 (1983). 38. Berg, S., et al., J. Vac. Sci. Technol. A5, 1600 (1987). 39. Okano, H., Y. Horiike, and M. Sekine, Jpn. J. Appl. Phys. 24, 68 (1985). 40. Mogab, C. J., A. C. Adams, and D. L. Flamm, J. Appl. Phys. 49, 3796 (1978). 41. Donnelley, V. M., et al., J. Appl. Phys. 55, 242 (1984). 42. Flamm, D. L., and V. M. Donnelley, Plasma Chem. Plasma Process 1, 317 (1981).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.24

PLASMA ETCHING 12.24

WAFER PROCESSING

43. Oehrlein, G. S., et al., Appl. Phys. Lett. 46, 686 (1985). 44. Coburn, J. W., and H. F. Winters, J. Vac. Sci. Technol. 16, 391 (1979). 45. Gottscho, R. A., and G. R. Scheller, Proceedings of the 6th Symposium. on Plasma Processing, Electrochemical Society, Pennington, New Jersey, 201 (1987). 46. Ephrath, L. M., and E. J. Petrillo, J. Electrochem. Soc. 126, 1419 (1979). 47. Lehmann, H. W., and R. Widmer, J. Vac. Sci. Technol. 15, 319 (1978). 48. Johnson, D., private information exchange. 49. Pang, S. W., “Surface Damage Induced by Dry Etching,” in: R. J. Shul and S. J. Pearton (eds.), Handbook of Advanced Plasma Processing Techniques (Springer-Verlag, Berlin, 2000). 50. Ephrath, L. M., and R. S. Bennett, J. Electrochem. Soc. 129, 1822 (1982). 51. Mickkelsen, J. C., Jr., and I. W. Wu, Appl. Phys. Lett. 49, 103 (1986). 52. Watanabe, T., and Y. Yoshida, Solid State Technol. 27-4, 263 (1984). 53. Giapis, K. P., “Fundamentals of Plasma Process-Induced Charging and Damage,” in: R. J. Shul and S. J. Pearton (eds.), Handbook of Advanced Plasma Processing Techniques (Springer-Verlag, Berlin, 2000). 54. Suzuki, K., et al., U.S. Patent No. 4, 579, 623. 55. Laermer, F., and A. Schilp, U.S. Patent No. 5, 498, 312; F. Laermer and A. Schilp, U.S. Patent No. 5, 501, 893. 56. Lai, S. L., et al., Proc. of SPIE 4979, 43 (2003). 57. Ayón, A. A., J. Electrochem. Soc. 146, 339 (1999). 58. Blauw, M., T. Zijlstra, and E. van der Drift, J. Vac. Sci. Technol. B 19, 2930 (2001). 59. Lai, S. L., et al., Proc. of SPIE 5342, 94 (2003). 60. Gottscho, R. A., C. W. Jurgensen, and D. J. Vitkavage, J. Vac. Sci. Technol. B 10, 2133 (1992). 61. Jurgensen, C. W., A. E. Novembre, and E. S. G. Shaqfeh, Proc. SPIE 94, 1262 (1990). 62. Blauw, M. A., and E. van der Drift, J. Vac. Sci. Technol. B 18, 3453 (2000). 63. Ingram, S. G., J. Appl. Phys. 68, 500 (1990). 64. Arnold, J. C., and H. H. Sawin, J. Appl. Phys. 70, 5314 (1991). 65. Giapis, K. P., et al., Appl. Phys. Lett. 57, 983 (1990). 66. Dushman, S., and J. M. Lafferty, Scientific Foundations of Vacuum Technology (Wiley, New York, 1962), p. 94. 67. Coburn, W., and H. F. Winter, Appl. Phys. Lett. 55, 2730 (1989). 68. Lai, S. L., D. Johnson, and R. J. Westerman, to be published. 69. Nozawa, T., et al., Jpn. J. Appl. Phys. 34, 2107 (1995). 70. Fujiwara, N., T. Maruyama, and M. Yoneda, Jpn. J. Appl. Phys. 34, 2095 (1996). 71. Arnold, J. C., and H. H. Sawin, J. Appl. Phys. 70, 5314 (1991). 72. Hwang, G. S., and K. P. Giapis, J. Vac. Sci. Technol. B 15, 70 (1997). 73. Sato, M., and Y. Arita, J. Vac. Sci. Technol. B 16, 1038 (1998). 74. Donohue, J., et al., U.S. Patent No. 6, 071, 822. 75. Samukawa, S., and T. Mieno, Plasma Sources Sci. Technol. 5, 132 (1996). 76. Hopkins, J., et al., U.S. Patent No. 6, 187, 685. 77. Srinivasan, S., et al., Proceedings of the 9th International Conference on Commercialization of Micro and Nano Systems, 2004, to be printed. 78. William, R., Modern GaAs Processing Methods (Artech House, Norwood, MA, 1990). 79. Youtesy, C., and I. Adesida, “Plasma Processing of III-V Materials,” in: R. J. Shul and S. J. Pearton (eds.), Handbook of Advanced Plasma Processing Techniques (Springer-Verlag, Berlin, 2000). 80. Hu, E. L., and R. E. Howard, J. Vac. Sci. Technol. B 2, 85 (1984). 81. Seaward, K. L., et al., J. Appl. Phys. 61, 2358 (1987). 82. Ren, F., et al., J. Vac. Sci. Technol. B 15, 983 (1997). 83. Lee, J., et al., GaAs MANTECH; International Conf. on GaAs Manufacturing Technology, 2000, pp. 13–16.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.25

PLASMA ETCHING PLASMA ETCHING

12.25

84. Westerman, R. J., D. Johnson, and Y. Lee, Proc. CS-MAX, (San Jose, CA, 2002), pp. 91–94. 85. Clayton, F., R. J. Westerman, and D. Johnson, GaAs MANTECH; International Conf. on GaAs Manufacturing Technology (2002), pp. 121–124. 86. Nam, P. S., et al., J. Vac. Sci. Technol. B 18, 2780 (2000). 87. Westerman, R. J., D. Johnson, and F. Clayton, GaAs MANTECH; International Conf. On GaAs Manufacturing Technology (2003), pp. 273–276. 88. Thomas, S., and J. J. Brown, Dry Etching of InP Vias, in: R. J. Shul and S. J. Pearton (eds.), Handbook of Advanced Plasma Processing Techniques (Springer-Verlag, Berlin, 2000). 89. Niggebrügge, U., M. Klug, and G. Garus, Inst. Phys. Conf. Ser. 79, 367 (1985). 90. Whelan, C. S., T. E. Kazior, and K. Y. Hur, J. Vac. Sci. Technol. B 15, 1728 (1997). 91. Youtsey, C., et al., J. Vac. Sci. Technol. B 20, 3317 (1994). 92. Rommel, S., et al., J. Vac. Sci. Technol. B, 1327 (2002). 93. Lee, Y. S., et al., IEEE 2003 International Conference on Indium Phosphide Related Materials Proceedings, pp. 78–79. 94. Adesida, I., et al., Appl. Phys. Lett. 63, 2777 (1993). 95. Karouta, F., et al., Electrochem. Solid State Lett. 2, 240 (1999). 96. Ping, A. T., I. Adesida, M. A. Khan, and J. N. Kuznia, Electron. Lett. 30, 1895 (1994). 97. Lin, M. E., et al., Appl. Phys. Lett. 64, 887 (1994). 98. Shul, R. J., et al., Appl. Phys. Lett. 66, 1761 (1995). 99. Smith, S. A., et al., Appl. Phys. Lett. 71, 3631 (1997). 100. Devre, M., et al., Unaxis Chip 8, 26 (2003). 101. Johnson, D., et al., Comp. Semi., 2001. 102. Westerman, R. J., and D. Johnson, pending patent, 2004. 103. Resnick, D. J., “Photomask Etching,” in: R. J. Shul and S. J. Pearton (eds.), Handbook of Advanced Plasma Processing Techniques (Springer-Verlag, Berlin, 2000). 104. Jung, K. B., H. Cho, and S. J. Pearton, “Dry Etching of Magnetic Materials,” in: R. J. Shul and S. J. Pearton (eds.), Handbook of Advanced Plasma Processing Techniques (Springer-Verlag, Berlin, 2000). 105. Meyyappan, M., “Plasma Modeling,” in: M. Meyyappan (eds.), Computational Modeling in Semiconductor Processing (Artech House, 1995). 106. Hutchinson, I. H., Principles of Plasma Diagnostics (Cambridge University Press, 2002). 107. Herb, G. K., “Safety, Health, and Engineering Considerations for Plasma Processing,” in: D. M. Manos, D. L. Flamm (eds.), Plasma Etching (Academic Press, San Diego, 1979).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH12.qxd

04/04/2005

19:49

Page 12.26

PLASMA ETCHING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:50

Page 13.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 13

PHYSICAL VAPOR DEPOSITION Florian Solzbacher University of Utah Salt Lake City, Utah

13.1 INTRODUCTION TO PHYSICAL VAPOR DEPOSITION Physical vapor deposition (PVD) is a high-vacuum deposition process for metals, metal alloys, or other solid chemical compounds using thermal energy (evaporation) or kinetic energy of ions (sputtering) to remove material from a source (sputter target or crucible) and deposit it onto a substrate. 13.1.1 Motivation and Key Properties PVD is the most commonly used process for the deposition of metals and metal oxides in semiconductor processing. The motivation for using PVD processes lies in the specific properties of the process and the deposited layers: • A wide range of layer thicknesses ranging from tens of nanometers to tens of micrometers is possible. • The layer uniformity and reproducibility is high. • Essentially, there is no limitation in the choice of source materials (such as metals, semiconductors, glass, ceramics, and plastics) that can be deposited. • Multilayer systems can be deposited in one vacuum process. • The substrate temperature can be kept low (down to room temperature) and seldom exceeds 350°C during deposition. Thus, no damage is being done to underlying layers. • The layer properties (specific resistance, temperature coefficient of resistance (TCR), adhesion, structure, composition, density, refractive index) can be modified by changing the process parameters (substrate temperature, residual gas pressure, process pressure, particle energy, deposition rate, and gas atmosphere).

13.2 FUNDAMENTALS OF PVD PROCESSES PVD processes are vacuum processes. In order to understand their specifics, it is necessary to briefly introduce some of the main concepts of vacuum physics like pressure and mean free path. As discussed in Chap. 7, pressure p can be described as gas molecules with concentration n per unit

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

13.1

Geng(SMH)_CH13.qxd

04/04/2005

19:50

Page 13.2

PHYSICAL VAPOR DEPOSITION 13.2

WAFER PROCESSING

NV

– v (b)

(a)

v

FIGURE 13.1 (a) Scattering and random walk of particles between collisions, and (b) Boltzmann distribution of mean particle velocities.

volume, mass m, and mean velocity v colliding with container walls: p=

nmv 2 3

The gas molecule mean velocity v depends on the temperature and molecular mass. Assuming the particle velocity distribution follows the Boltzmann distribution (Fig. 13.1), we obtain 1/2

 8kT  v2 =   pm 

k , Boltzmann constant

The mean free path λ of molecules between collisions is therefore l=

kT pps 2 2

which approximates to l=

6.3 p

in air. In order to obtain high-purity layers, it is imperative that the mean free path must be much larger than the distance between the source and the substrate. The degree of contamination depends on the purity of the source material as well as the reaction with the residual gas in the vacuum chamber. The smaller the mean free path, the higher is the possibility of vapor particles colliding on their path between the source and the substrate. In the case of reactively sputtered layers, like metal oxides and nitrides, one makes use of this fact by initiating reactions of the vapor particles with the ambient gas (Fig. 13.2).

13.3 VACUUM EVAPORATION Vacuum evaporation works on the principle of heating a source material in vacuum until a sufficient vapor pressure for net evaporation of the source material is reached. The deposition process (Fig. 13.3) includes three stages: 1. Evaporation of target material (evaporation phase) 2. Transport of particles through the vacuum to the substrate (transport phase) 3. Condensation on the substrate (condensation phase)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:50

Page 13.3

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

100

0

80

20

r 60

40

40

60

20

80

%

%

0 100 50

10

5

− l

1

0.5

0.1

100

13.3

Percentage of vapor particles experiencing collisions while passing the distance r

Percentage of vapor particles passing the distance r without collision

Geng(SMH)_CH13.qxd

r

FIGURE 13.2 Collision probability of vapor particles as the function of mean free path over the distance r traveled.1

Key characteristics of this process are that the source material is heated to very high temperatures, whereas the substrate temperature can be freely chosen to influence the layer parameters. A large mean free path for vapor particles is required to prevent reaction of the source vapor particles with the residual gas or collision with other vapor particles. Thus, normally, vacuum pumps for evaporator equipment are connected directly to the main vacuum chamber with large crosssection tubing. At equilibrium pressure or saturation vapor pressure, evaporation and condensation rates of the source material are equal. The saturation vapor pressure is given by ps = Ae( − B/T ) where A is the integration constant and B is the constant depending on heat of evaporation, i.e., target material. Small temperature changes thus lead to large changes in the condensation rate (Fig. 13.4). The degree of freedom in process parameters is limited. Low evaporation rates lead to chemical reactions with residual gas particles, and high evaporation rates lead to collisions and subsequent

Substrate

Vapor particles Source with crucible and heater To vacuum pump FIGURE 13.3

Schematic of vacuum evaporation PVD.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:50

Page 13.4

PHYSICAL VAPOR DEPOSITION WAFER PROCESSING

Pb

Cd

Al

Cr Ti

10+3 Pressure/Pa

13.4

Ta 10−1

W

10−5 0

1000

2000

3000

Temperature/K FIGURE 13.4 evaporation.2

Equilibrium vapor pressures of selected metals for vacuum

backscattering of source vapor particles. In practice, process pressures are set between 10−2 and 10−4 Pa. The evaporation rate R can be described as M R = 4.43 ⋅ 10 −4   T

1/2

ps [g/cm 2 ]

where M is the molecular weight and T is the absolute temperature. Examples of evaporation rates for common source materials can be found in Fig. 13.5. During the transport phase, the mean kinetic energy of the particles is Ee =

m 2 3 n = kTn 2 2

where m is the particle mass, k is the Boltzmann constant, Tv is the source temperature, and v is the particle velocity. Ee typically amounts to about 0.2 eV at 1500 K (0.26 eV at 2000 K), i.e., the energy of the particles is small compared to sputtering, as we will see later. Also, variation in evaporation temperature allows for little variation in particle energy. The condensation stage consists of three steps: 1. Vapor particles deposit on the substrate surface, thereby transferring kinetic energy to the substrate (adsorbtion). 2. Surface diffusion of the particles occurs with subsequent exchange of energy with the lattice atoms until the particle (atom) settles in a spot of low energy (nucleation/seed). Surface defects are preferred locations for nucleation; the growth of domains leads to continuous layers and the layer growth depends highly on the substrate surface and deposition conditions. 3. Volume diffusion of atoms within the lattice. The surface structure resulting from the evaporation deposition is typically distinguished into three types or zones depending on the ratio of the substrate temperature Ts to the target melting temperature Tm (Fig. 13.6).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:51

Page 13.5

100

Evaporation rates of selected metals as functions of temperature [1]. FIGURE 13.5

10−7 10−8 10−9 10−10 10−11 10−12 0

500

2000

2500

10−16

10−15

10−14

10−13

Melting point 3000

3500

Evaporation rate/g cm−2s−1

10−6

10−5

10−4

W

10−3

Ta

10−2

Nb

10−1

Zn

Ca 1000

Li Mg

Ag

Al

1500

Au Be Cu

Fe Ni

Ti

Zr

Rh Pt

Mo

101

PHYSICAL VAPOR DEPOSITION

Temperature/K

Geng(SMH)_CH13.qxd

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

13.5

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.6

PHYSICAL VAPOR DEPOSITION 13.6

WAFER PROCESSING

Zone 1

Zone 2

Zone 3

T 2 /T m T 1/T m e

eratur

Temp

FIGURE 13.6 Zone model of layer surface structure for vacuum evaporation deposited layers.3

Zone 1 (Ts/Tm < 0.25): Dendrite structure, porous, lower density than bulk material, dendrites grow with Ts Zone 2 (0.26 < Ts/Tm < 0.45): Columnar structure, surface mobility is large enough, high packing density, low surface Ra, crystal diameter grows with T Zone 3 (Ts/Tm > 0.45): Volume diffusion in dominant layers with high density and flat surface

13.4 EVAPORATOR EQUIPMENT For evaporation, the source material is heated using either a resistive heater or an electron beam (e-beam evaporation). The drawback of resistive heating of the vapor source is the evaporation of the heater itself leading to contamination of the layer and the limited layer thickness. Furthermore, this process does not allow the deposition of high melting temperature materials such as W, Mo, and Ta. The source material is heated either in a ceramic crucible and evaporator boat, or using an evaporator spiral with twisted tungsten wire. The heat produces an upward vapor column above which the substrate material is moved in concentric circles to ensure constant layer thickness across the substrate. In e-beam evaporation, a highly efficient local heating is accomplished by using an electron beam directed at the source material. The 270° deflection of the e-beam prevents contamination of the layer from the glowing e-beam cathode (Fig. 13.7). Key process parameters are the residual gas pressure, the substrate temperature, the evaporation phase, and the time. In situ layer thickness is measured using quartz micro balances or resonators. Typical deposition rates can vary between 100 nm/min and 5 µm/min. The core parameters for good layer quality are a sufficient thickness uniformity and good step coverage. The residual gas pressure must not exceed approximately 10−2 Pa to prevent collisions of vapor molecules with residual gas molecules and contamination (adsorbed gas molecules on the substrate surface). Typical operating pressures are therefore 10−3 to 10−5 Pa. Important process parameters are residual pressure, substrate temperature, evaporation phase, and time. The evaporation rate can be controlled using the current density or the e-energy of the e-beam. Quartz thickness gauges are used for the measurement and control of the deposition rate. The core drawback of this method is the generation of x-rays at acceleration voltages >10 kV, which can damage MOS-integrated circuitry during deposition by causing trapped charges in the gate oxide. The trapped charges have to be removed using an annealing process. Turning this drawback into an advantage, the x-rays can however be used for in situ layer analysis (XRD). High e-beam

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.7

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

Electrons

13.7

Metal vapor particles Target/crucible

Electron flight path +

+ +

Shutter

Magnet + Cooling water

S

Aperture FIGURE 13.7

E-source

Schematic of an electron-beam evaporator.

energies lead to bubbling of the target material and consequently the danger of splattering the substrate. For a sufficient layer quality, the following criteria have to be taken into account: • In situ control of layer thickness • Sufficient thickness uniformity across the wafer • Good step coverage = ts/tn × 100 percent; ts—minimum layer thickness at the step edge, tn—layer thickness in the flat part 13.4.1 Cosine Law For good thickness uniformity across the wafer, the wafer transport follows a specific movement under the e-beam vapor. The particle flow from a small source theoretically follows the cosine law. The evaporated mass per unit area is RD =

Me cosf cosq p r2

where Me is the total mass of evaporated material and R, f, and q are according to Fig. 13.8. Since in practice the vapor source is not a point source, the evaporation is not isotropic. In practice, a planetary motion of the substrate holder is used for most applications.

13.5 LAYERS DEPOSITED USING EVAPORATION AND THEIR PROPERTIES Evaporation is primarily used for the deposition of metals. Principally, it allows the nonreactive and reactive deposition of metals, alloys, chemical compounds, and ceramics as single and sandwich layers.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.8

PHYSICAL VAPOR DEPOSITION 13.8

WAFER PROCESSING

dAr θ

ϕ

θ

°

dAr

90

r

dω

ϕ

r0

dAe FIGURE 13.8

dAe Cosine law of evaporated mass per unit area for a point source.1

Metals: Examples of metal layers deposited are Al, Au, Ag, Cr, Ni/Cr, Ti, Ni, Pt, and Pd. Primarily, e-beam evaporation is used. Alloys: The evaporation of alloys is significantly more difficult than that of metals since the components of alloys seldom have the same vapor pressure at the same temperature. Therefore, sputtering is normally used for alloy deposition. Multilayer: Multiple crucible evaporators with one or more e-beams are used to deposit multilayer structures in one deposition run. Chemical compounds: The evaporation of chemical compounds is usually combined with dissociation. Since small changes in stoichiometry already lead to drastic changes in layer properties, chemical compounds are usually deposited using CVD or sputtering. Reactive evaporation: The use of a reaction gas (e.g., O2, N2) during evaporation leads to a chemical reaction between the evaporated material and the gas and can be used, for example, to deposit oxides or nitrides of metals while using a pure metal target. CVD and sputtering allow much better process control, and are therefore primarily being used.

13.6 SPUTTERING 13.6.1 Definition Sputtering is a plasma process, during which noble gas ions (typically Argon (Ar+)) are accelerated toward a target (cathode) from which they remove material particles. These particles build a vapor column that condenses on the substrate. Sputtering is the primary method for the deposition of metallization layers in microelectronics and MEMS. Sputtering is a four-stage process: Stage 1: Creation of ions through collision of inert gas atoms (Ar) with electrons and acceleration of ions toward a target Stage 2: Removing of target atoms by impact of ions with the target Stage 3: Transport of free target atoms to the substrate Stage 4: Condensation of target atoms on the substrate Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.9

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

13.9

The distance between the substrate and the target is typically 5–10 cm (up to 35 cm for some sputtering equipment) to allow maximum condensation rate of removed target atoms on the substrate. Seed and cluster building occurs in an identical fashion as evaporation. Atoms reaching the substrate have higher energy (3–10 eV) than in evaporation (0.2 eV). Collisions between the target and the gas atoms result in atoms reaching the substrate from various directions. The deposition process is therefore, to a large extent, isotropic and the step coverage of sputtered layers is better than that of evaporated layers. Sputtering exhibits a higher particle bombardment of the substrate surface than evaporation. This can on the one hand lead to crystal damage, but on the other hand also be used for in situ annealing of deposited layers. The layer properties can be influenced using a bias voltage. The key differences between sputtering and evaporation (Fig. 13.9) are as follows: • Sputtered atoms and molecules have a higher impact energy (3 to 10 eV, compared to 0.2 to 0.26 eV for evaporation). • Due to collisions with gas particles (Ar), the free target atoms reach the substrate surface from various directions leading to good step coverage. • The substrate has a higher exposure to gas than in evaporation. • Applying a bias voltage can influence the layer parameters (e.g., planarisation of surface). • Changing the polarity of the substrate and the target, the substrate can be exposed to backsputtering. Backsputtering can be used for  cleaning of the substrate surface prior to deposition  in situ annealing of layers in sandwich layer structures (i.e., layers are successively deposited and partially backsputtered thereby annealing the layer through physical impact and heat)  sputter etching of layers that are otherwise difficult or impossible to pattern

Evaporation Substrate

Vapor particles Source with crucible and heater To vacuum pump

Sputtering Cathode Target

e− Ar+

Substrate Substrate holder

FIGURE 13.9

−

Ar

Plasma

Anode

Metal, e.g., Al

Al

+

Comparison of evaporation and sputtering (schematic layout).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.10

PHYSICAL VAPOR DEPOSITION 13.10

WAFER PROCESSING

13.6.2 Mechanism Ions are created through plasma discharge between two electrodes. Ionization occurs through inelastic collisions between free electrons and gas molecules (in most cases Ar). The required ionization energy (15.7 eV for Ar) stems from the electron kinetic energy. The kinetic energy of the Ar ions after the acceleration by the electric field between the cathode and anode is between 10 eV and several 1000 eV. On collision with the substrate, the Ar ions transfer a part of their kinetic energy to a confined volume (ca. 1000 atoms) of the lattice atoms through a series of quasi-elastic collisions. Some target atoms are diffracted toward the surface. If their energy is larger than the surface binding energy, they leave the lattice. The removed target atoms typically have 3 to 10 eV of energy. The mean quantity of removed atoms or sputtering yield S is given by S=

number of removed target atoms number of colliding ions

The sputter yield depends strongly on the angle of impact or Ar ions hitting the target (Figs. 13.10, 13.11). At 0°, the ions fly parallel to the surface thus having a low probability of knocking atoms out of the target. At a 90° impact angle, the momentum translates into the bulk of the target material rather than knocking atoms out of the target. The maximum sputter yield can typically be found around 60°. S also depends on the mass relation of ion (Ar) versus the target atom as well as the binding energy between the atoms (Fig.13.12). 13.6.3 Film Microstructure and Mechanical Properties Depending on the deposition and annealing process parameters, PVD thin film properties can be modified to some extent. The most relevant properties are the film microstructure, crystallinity, grain size, its surface texture, layer stress and hardness, and the electrical and mechanical properties (e.g., E-modulus). The layer structure, just like in evaporation, depends on the inert gas pressure and the ratio of the substrate temperature to the target melting temperature (Fig. 13.13). Typically, annealing does improve the layer crystallinity, but leaves the surface texture unaffected. Increasing sputtering power can decrease the layer crystallinity. The introduction of reactive gases can disrupt the crystallization process leading to smaller grain size. The most common surface analysis tools used for layer

Yield

2

1

0

0

FIGURE 13.10

30

60 Angle of impact a/degree

90

Sputter yield as a function of particle impact angle.4

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

19:51

Page 13.11

PHYSICAL VAPOR DEPOSITION

Target atoms

Target surface Angle of impact a

+ Removed target atom

O Removed target atom

Ar-ion Backscattered neutral Ar atom

FIGURE 13.11 Schematic of propagation of momentum and particle movements of Ar ions hitting a sputter target surface.

3 Ag

Ar+ 2.5

Au

2 Sputter yield

Geng(SMH)_CH13.qxd

Pd

Cu 1.5 Co

Cr

1

0.5

0

Ge

Fe

Al

Pt

Ni Ru

Zr Be

Si

Ti

V

14

22

24

Mo

Ir

Re Hf

Nb

U

Os Ta W

Th

C 6

FIGURE 13.12

27

29 40 42 46 Atomic number

72

74

76

78

90

Sputter yield as a function of target atomic number.4

Zone T

Zone 1

one 3 Zone 2 Z

Ine

rt g

as

pre

ss

FIGURE 13.13 layers.3

ure

T /T m

Zone model of a layer surface structure for sputtered

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

13.11

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.12

PHYSICAL VAPOR DEPOSITION 13.12

WAFER PROCESSING

characterization are x-ray diffraction (XRD), electron dispersive x-ray spectroscopy/wavelength dispersive x-ray spectroscopy (EDX/WDX), Auger electron spectroscopy (AES), scanning electron microscope (SEM), and transmission electron microscope (TEM). XRD is used to determine the crystallinity and texture of the layers. A broader peak signifies smaller grain size. EDX/WDX is used to determine the composition of the layers, to detect contamination, stoichiometry of compound layers and reaction of donors, and dopant materials with underlying base layers. Zones 1–3 as in evaporation Zone T—fiber-type closely packed layer with smooth surface

13.7 SPUTTER EQUIPMENT Sputtering equipment is available for a variety of different sputtering processes. Ion beam sputtering uses an ion beam to ablate material from a target which condenses on a substrate. Plasma sputtering constitutes the largest and most common group of sputtering processes and systems. It uses ionized gas atoms that are being accelerated toward the target to remove material that condenses on a substrate. Depending on the type of assembly, a triode or diode system is used. The more common diode systems are operated either in DC sputtering with a DC voltage being applied across the plasma or in HF/RF sputtering mode. In RF sputtering, one can choose between inert gas sputtering and reactive sputtering (Fig. 13.14). 13.7.1 Methods 1. DC-sputtering 2. HF/RF sputtering 13.7.2 DC Sputtering DC sputtering is suitable only for the deposition of conducting materials. Nonconducting materials lead to charging of the target material by the Ar ions, resulting in a reduction of the negative potential. Thus, the acceleration potential for Ar ions breaks down (self-stopping process). (Fig. 13.15)

Sputtering

Ion beam sputtering

Plasma sputtering

Diode system

DC-sputtering

HF-sputtering

Inertgas (Ar) sputtering FIGURE 13.14

Triode system

Reactive sputtering

Common types of sputter processes and equipment.2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.13

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

13.13

Cooling water Shield Cathode Target Gas inlet Plasma

−

e−

Metal, e.g., Al

Positive column

Ar

UDC

Ar + Substrate Substrate holder

Cathode dark field

Al +

Anode To vacuum system FIGURE 13.15

Schematic of DC-sputtering equipment.

13.7.3 HF Sputtering HF or RF sputtering prevents charging of the target material, since due to the changing field, no ions can accumulate in front of the target. Hence, the target material does not have to be conductive to allow a working sputtering process. HF sputtering allows an almost entirely free choice of target materials (such as metals and dielectric materials). The schematic layout is depicted in Fig. 13.16. The HF generator frequency is typically 13.56 MHz. 13.7.4 Self-Bias Effect During the positive half wave of the HF voltage, more electrons than ions reach the target because of their higher mobility. Therefore, the target electrode charges negatively (self-bias) until equal

Cooling water Shield Cathode Target

Matching network Metal, e.g., Al

Gas inlet Plasma

HF/RF generator

Substrate Substrate holder

Aperture/ shutter

To vacuum system FIGURE 13.16

Schematic of HF/RF sputter process and equipment.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.14

PHYSICAL VAPOR DEPOSITION 13.14

WAFER PROCESSING

numbers of ions and electrons reach the target. If the potential difference between the discharge and the self-bias is large enough, particles will be removed from the target. The significantly different sizes of the two electrodes prevent a sputtering of the substrate and susceptor (the substrate carrier is much larger than the target) during a normal sputtering operation (Fig. 13.17). 13.7.5 Bias Sputtering In bias sputtering (not to be confused with self-bias!) a negative bias voltage (50 to 500 V) is used for continuous bombardment of the substrate with Ar ions during sputtering. The basic mechanism is that Ar ions transfer energy to the surface atoms thereby increasing their surface mobility and reaction rate. Bias sputtering (Fig. 13.18) is used in DC and HF sputtering. This process is used for the following: • Backsputtering (Eion >100 eV), which is used for sputter etching to clean the substrate surface prior to metal deposition by removing native oxide over contacts or organic residues. It can also be used as a physical etching process to remove material that is otherwise difficult or impossible to pattern using wet chemical etching processes. • In situ annealing processes to modify the layer properties during deposition due to the constant bombardment of the layer with ions leading to heating of the wafer as well as a potential layer surface damage due the impacting Ar ions. These mechanisms influence • • • • • • •

Implantation of Ar ions into the layer Step coverage of the layer Layer stress Grain size Electrical properties like specific resistance and temperature coefficient of resistance (TCR) Surface roughness Ra Layer adhesion

Current I

Plasma

Current I

UDC

P

P Voltage U

Voltage U

Time t (a)

Time t (b)

FIGURE 13.17 Self-bias effect in HF/RF sputtering: (a) initial state of current versus voltage (I-V) curve on switching on the HF voltage (excess electrons), (b) shift of I-V curve due to UDC bias voltage (charging of the target, until the number of electrons and ions hitting the target is equal).1

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.15

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

200

Au

13.15

Cu

Sn Ag Pt

Relative sputter rate

150

Ni Al Vacuum molten Cr V2A target

100

Cr Ti Ta W

50

0

FIGURE 13.18 power.10

• • • •

500

Hot pressed target

1000 1500 Power/W

Relative sputtering rate as function of sputter

Layer density Layer hardness Pinhole density and Layer composition

13.7.6 Reactive Sputtering In reactive sputtering a chemical reaction between target atoms and a reactive gas occurs. The resulting layer is a compound of the target and the reactive gas material (e.g., Ti + O2 → TiO2). The reaction (Fig. 13.19) can take place (a) at the target, (b) in the gas-phase, or (c) on the substrate. Reactive sputtering is frequently used for oxides, carbides, and nitrides. 13.7.7 Magnetron Sputtering In conventional sputtering, only a few secondary atoms contribute to further ionization of Ar atoms. Most electrons are collected at the anode leading to heating of the substrate. Magnetron sputtering increases the number of electrons contributing to ionization of Ar atoms by using an electromagnetic field. The E and B fields cause a cycloid motion of the charge carriers in the plasma. The deflection radii of the electrons are much smaller than that of the ions. Therefore, the electrons concentrate r close r to the target leading to a larger probability of ionization and thus, a higher sputter rate. The (E × B) drift causes electrons to flow to a special anode rather than to the substrate, therefore reducing heating of the substrate. Magnetron sputtering, naturally, has a larger impact in dc sputtering, but is used in HF/RF sputtering as well. The drawback of magnetron sputtering is the inhomogeneous use and ablation of the target (Fig. 13.20) leading to early need for replacement. New methods with more complex electromagnetic field geometries allow for a more efficient use of the target material. Normally, a target supplier will reclaim the remaining material on the base plate and

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

05/04/2005

18:03

Page 13.16

PHYSICAL VAPOR DEPOSITION 13.16

WAFER PROCESSING

Cathode (a)

Target

M O

(b)

M O

(c)

Substrate

M O Anode FIGURE 13.19 tering.1

Schematic and reaction sites for reactive sput-

charge the customer only for the extra material as well as the sintering and bonding of the new target material (Figs. 13.21 and 13.22). 13.7.8 Sputtering Equipment Sputtering equipment have been built in a multitude of different ways. The schematic layout of the most common systems today is given in Fig. 13.23. The core components of such a system are the vacuum system, the RF/DC power supply, and matching network. The key components are described below. Vacuum System. A vacuum system consists of two chambers—the main processing chamber and an airlock (pre-vacuum chamber). The airlock is used to accelerate processing and reduce contamination

Magnet N

S

N

Cathode −

Target e−

Plasma

Ar

Ar +

Metal, e.g., Al

Substrate Substrate holder

Al

Anode

+

To vacuum FIGURE 13.20

Schematic of magnetron sputter process and equipment.12

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

05/04/2005

18:03

Page 13.17

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

of the main chamber, since venting of the main chamber is not required for substrate loading. The vacuum system is usually a two-stage system with a mechanical coarse vacuum pump and a turbo high vacuum pump. Ion current gauges are used to determine the process chamber pressure at high vacuum. A residual gas analyzer is used to determine the concentration and composition of the residual gas.

-

13.17

-

-

-

Cooling Water. For chamber temperature control, a cooling water system (dual-walled chamber or welded steel tubing) and a radiation heater is used. A good chamber design eliminates the possibility of cooling water entering the chamber and getting in contact with electronics and current-carrying or high-voltage parts in case of a leakage or system breakdown.

-

N S

N

FIGURE 13.21

Schematic of mag-

sputter target, electromagnetic Cathodes and Targets. Most systems have multiple cathodes netron field, and subsequent cycloid path of that allow the sputtering of two to four different materials in one electrons.5 run either simultaneously or sequentially. In addition to the electrical switching network, a mechanical aperture/shutter system is used to select between targets. That is, not only will an “off” target not receive a sputtering voltage, it will also be mechanically sealed to prevent exposure to accelerated Ar ions, reaction with the other sputtered material particles or simply mechanical chipping of the target that leads to deposition of macroscale contamination particles on and in the deposited layer. Two standard configurations exist for the substrate holder and targets—horizontal and vertical sputtering (Fig. 13.24). In both cases the distance between target and substrate is typically between 15 and 35 cm, depending on the target and palette sizes and geometries as well as the sputtering parameters. Horizontal sputtering allows for a simple substrate holder (e.g., rotating disc) that passes underneath the targets. Most horizontal sputter targets have a circular shape with diameters between 4 and 12 in. Targets usually consist of a base plate with integrated water cooling and magnets (magnetron sputtering) and the bonded target material (typical thickness 3 to 5 mm). The target base plate is reusable. In use, operators have to monitor the target use. Traces of the base plate material in the deposited layer composition indicate that the target has been ablated down to the base plate and requires replacement. Normally quality and process control will lead to replacement of a target prior to sputtering of the base plate material. The substrates are placed on the disc without any fixture holding them in place. The disc rotation is off center of the target to create a homogeneous layer thickness. More complex systems feature a planetary motion. An advantage of the horizontal system is its flexibility—experimental setups (e.g., fixtures holding a shadow mask aligned above a substrate)

Backing plate

Target (bonded or clamped)

Magnet assembly Cathode body Insulator Shield Bolt/screw FIGURE 13.22

Cooling water lines

Schematic of magnetron sputter target including cooling water system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.18

PHYSICAL VAPOR DEPOSITION WAFER PROCESSING

HF/RF power supply

HF/RF matching network

Pre-vacuum/ loading chamber

Base plate

Cooling water Shield

Target

Conveyor transport system

Aperture Residual gas analyzer Gas inlet

Cooling water

Palette Vacuum pumps

Load lock

Load lock

Substrates FIGURE 13.23 Schematic of a horizontal RF magnetron sputter machine with a loading chamber, multiple targets, and a rotating substrate pallet.

and devices with complex geometries can easily be placed on the horizontal plate without need for a special fixture. The key drawback is that bulk material that falls off the targets as well as flakes of deposited material on the chamber walls can fall onto the substrates, contaminating them. Vertical sputtering systems eliminate this drawback. They do however require a complex substrate fixture to keep wafers or samples secured to the base plate without falling off and to ensure a good thermal and electrical contact to the substrate holder. Bad electrical or thermal contact will lead to variations in layer thickness and structure across the sample. Vertical sputtering systems exist as simple linear designs where the substrate passes parallel along one or more targets and as rotary systems where substrates are mounted on a barrel-type holder. Vertical sputtering allows sequential multilayer deposition, but in most cases not simultaneous deposition, since the substrates can only face one target at any given time.

Anode/palette

Cathode

Substrate

Target

Substrate

+

+

Target Cathode

Anode/palette

+

+

+

+

13.18

FIGURE 13.24

Schematic of a horizontal and vertical sputter setup.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.19

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

13.19

13.8 LAYERS DEPOSITED USING SPUTTERING As previously mentioned, sputtering allows the deposition of almost any kind of material. It allows the deposition of a free choice of metals, including those with high melting temperature. Depending on the target size and material, target prices can vary a lot (e.g., Al1Si target 10 in × 5 mm: $1,000; Pt target 10 in × 5 mm: $18,000). All alloys can be deposited using sputtering, depending on the availability of targets for the specific sputtering system. Multilayer structures can be deposited using multiple target sputter equipment with apertures to prevent cross contamination of targets. Chemical compounds (dielectric materials, insulators, metal oxides) can be deposited either using specific compound targets (mostly sintered material) and/or using reactive sputtering. A typical configuration is using a metal or semiconductor material target and a reactive ambient gas atmosphere (O2, N2) to build oxide or nitride layers. A selection of materials and physical properties (Table 13.1) is given below: Metals: Au, Pt, Pd, Ni, Ti, Al, Cr, Mo Alloys: NiCr, CrSi, TiW Multilayers: Cr-Al, Ti-Au, Ti-Pd-Au, Ti-TiN-Au, Ti-TiWN-Au, NiCr-Ni-Au, SnO2, Cr-Al Chemical compounds: Al2O3, SnO2, SiO2, ZnO, Ga2O3, HfB2, NiO, V2O5, Mo2O3, In2O3, glass (Pyrex) 13.8.1 Step Coverage An important issue in all coating processes is step coverage of textured and patterned substrate surfaces. Poor step coverage can lead to microcracks and interruption or breaking of a layer coating. Vacuum evaporation deposition follows the cosine law with the vapor particles coming straight from a point vapor source in high vacuum with little collisions and scattering. The subsequent coating process is almost anisotropic, i.e., surfaces facing the vapor source are coated whereas the ones perpendicular to those remain almost uncoated, leading to poor step coverage. This characteristic, however, favors lithographic lift-off processes as patterning processes. Sputter deposition exhibits a large area vapor source and higher process pressures leading to higher frequency of collisions between vapor particles. In consequence, the vapor particles approach the substrate surface from more random directions leading to higher deposition isotropy and better step coverage. In comparison, chemical vapor deposition (CVD) layers almost always feature better step coverage than PVD layers. Process pressures in CVD are typically higher than in PVD. Furthermore, the source is a strong constant gas flow of process gases, needed as precursors for the layer (e.g., 3 sccm methylsilane in 200 sccm hydrogen at 3.5 l/min total flow for LPCVD silicon carbide deposition). This leads to high particle

TABLE 13.1 Examples of Metallization Systems Used in Semiconductor Devices and Selected Physical Properties6 Material Density [kg/m3] Thermal conductivity l [W/mK] Melting point Tm/°C Specific heat capacity [J/KgK] Specific resistance/µΩcm Passivation layer Contact layer/diffusion barrier required on Si and SOI substrates

Al

Au

Pt

Mo

HfB2

19300 237 660 897 2.4 Si3N4/ SiO2 Ti/ TiWN

2700 317 1000 129 2.2 –

21500 71.6 1768.4 133 9.6 –

10200 138 2623 251 4.85 Si3N4/ SiO2

11200 41.8 3250 25.1 253 ±5 Si3N4/ SiO2/TaN

Ti/ TiWN

Ti

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.20

PHYSICAL VAPOR DEPOSITION 13.20

WAFER PROCESSING Vacuum evaporation

Sputtering

CVD

Direction of vapor particles Coating layer

Coating layer

Patterned layer, e.g., SiO2

Patterned layer, e.g., SiO2

Coating layer

Substrate, e.g., silicon

FIGURE 13.25

Coating layer

Coating layer

Patterned layer, e.g., SiO2

Coating layer

Substrate, e.g., silicon

Substrate, e.g., silicon

Step coverage of vacuum evaporation, sputtering, and CVD in comparison.4

collision frequency and partially turbulent gas flow causing a completely isotropic coating process and excellent step coverage. Only in deep high aspect ratio cavities, as caused, e.g., by deep reactive ion etching (DRIE), diffusion governs the coating characteristics in CVD (Figs. 13.25 and 13.26).

13.9 ATOMIC LAYER DEPOSITION––NEW PERSPECTIVES FOR THIN FILM DEPOSITION TECHNIQUES Shrinking feature size, thinner layers, as well as the requirement of high dielectric constant layers have led to the development of atomic layer deposition (ALD), also known as atomic layer epitaxy or atomic layer CVD .7–10 ALD is essentially a CVD process that first emerged in the 1970s and that is based on self-limiting surface reactions of precursors on a heated substrate. ALD allows outstanding thickness control and layer uniformity across large areas, which makes it likely to become the most suitable process for the fabrication of ever thinner and more accurate layers and device geometries in electronics. ALD layers tend to have very low defect density and contamination as well as good step coverage. The schematic principle of an ALD process and reactor is displayed in Fig. 13.27. ALD research and process technology has originally focused on the deposition of high-k dielectrics, oxides, and nitrides. In recent years, deposition processes for metal thin films (primarily Cu) and diffusion barriers (e.g., TiN) have been developed.11,12 Deposition temperatures have over the past years been decreased to typically 350 to 450°C at pressures 1 to 20 mbar. The gases are pulsed leading to the sequential deposition of layers. Growth typically starts randomly on the surface leading to the building of small islands. Islands grow until they close the layer. Growth rates are in the range

Bad step coverage (sharp edge, anisotropic coating)

Ideal step coverage (soft edge, isotropic coating)

Micro crack Coating layer Patterned layer, e.g., SiO2

Coating layer a

Coating layer

Substrate, e.g., silicon

FIGURE 13.26

Patterned layer, e.g., SiO2

a

Coating layer

Substrate, e.g., silicon

Impact of step coverage on layer coherence.4

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.21

PHYSICAL VAPOR DEPOSITION PHYSICAL VAPOR DEPOSITION

Fast valves

Fast valves

Reactor

13.21

Deposited layer

X X Vapor pulses Substrate

Heater

Pump/exhaust Vapor source 1 FIGURE 13.27

Vapor source 2 Schematic of ALD reactor and process.

of 0.2 to 0.8 Å per cycle. Typical layer thicknesses are in the 10 nm range with thickness standard deviation of only 3 to 5 percent. Layer properties (just as in most CVD processes) depend on the precursors, their partial pressures, the deposition temperature, and certainly the surface properties (e.g., roughness and possible nucleation sites). Deposition of more complex layer structures, for example, diffusion barrier layers must be compatible with the surrounding layers (e.g., metals and oxides). As an example, contamination problems can occur when depositing TiN on Cu layers because of the interaction of the precursor gases with the Cu. It is expected that the start of 65 nm technology in semiconductor processing will initiate the industrial use of ALD layers in commercial electronics.12 The core requirements are layer thicknesses of around 5 to 7 nm and aspect ratios of more than 1:100 for good step coverage on vertical walls and compatibility to porous low dielectric materials. Current research also studies lateral selectivity of ALD processes.

13.10 SUMMARY AND OUTLOOK PVD is used primarily for metallization layers, but also for metal oxides and some dielectric materials. It is essentially a “cold” process that does not require substrate heating per se. Substrate heating can, however, be used to influence the layer properties. Evaporation yields higher purity material, but the material choice is limited and the isotropic nature of the deposition process causes poor step coverage. Sputtering allows deposition of a huge choice of materials with good reproducibility and exhibits better step coverage. Most standard metallization layers are deposited using sputtering. The dividing line between PVD and CVD processes appears to vanish. PVD and CVD processes are frequently combined in one piece of equipment. Evaporation is on a decline due to high competition from sputtering and CVD, with sputtering remaining the dominant PVD coating process in semiconductor processing. Key engineering challenges in sputtering lie in better equipment reliability (down times less than 10 percent), increased throughput and automation, higher layer uniformity, and more complex multilayer deposition techniques that will require more complex sputter etching or in situ cleaning and annealing techniques. This will also lead to further consolidation of the equipment manufacturer market. From a scientific point of view, little understanding exists today of the fundamental principles underlying the impact of the process parameters on layer properties, in particular with multilayer coatings as well as the material’s electrical, mechanical, and chemical properties in harsh environments (i.e., high temperatures, aggressive gas, and fluid media). This will become a focal point of future research on PVD coating processes and layers.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH13.qxd

04/04/2005

19:51

Page 13.22

PHYSICAL VAPOR DEPOSITION 13.22

WAFER PROCESSING

REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

12.

Obermeier, E., Technologien der Mikrosysteme I, Lecture scriptum, Berlin, Germany, 2002. Wehl, W., Mikrotechnische Fertigung, Lecture Scriptum, Heilbronn, Germany, 2002. Menz, W. , Mikrosystemtechnik für Ingenieure, VCH Verlag, Weinhein, Germany, 1997. Schade, K., Mikroelektroniktechnologie, Verlag Technik, Berlin, Munich, Germany, 1991. Pupp, W., Vakuumtechnik, Hanser Verlag, Munich, Germany, 1991. West, R. C., et al. (eds.), CRC Handbook of Chemistry and Physics, CRC Press, Boca Raton, Florida, 1987. Suntola, T., Thin Solid Films, 216, 1992, p. 84. Ritala, M., M. Leskelä, and In: Nalwa, H. S., (eds.), Handbook of Thin Film Materials, Vol. 1, Chap. 2, Academic Press, San Diego, 2001. Ritala, M., and M. Leskelä, M. Nanotechnology, 10, 1999, p. 19. Leskelä, M., et al. (eds.), Atomic Layer Epitaxy, Chap. 1, Blackie and Son, Glasgow, Scotland, 1990. Juppo, M., “Atomic Layer Deposition of Metal and Transition Metal Nitride Thin Films and In Situ Mass Spectrometry Studies,” Academic Dissertation, University of Helsinki, Laboratory of Inorganic Chemistry, Helsinki, Finland, 2001. Beyer, G., and M. Van Bavel, “Using Atomic Layer Deposition to Prepare Future-Generation Copper Diffusion Barriers,” Micromagazine, 2002.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 14

CHEMICAL VAPOR DEPOSITION Edward J. McInerney Novellus Systems, Inc. San Jose, California

14.1 INTRODUCTION Chemical vapor deposition (CVD) is widely used in microelectronics fabrication to deposit thin films. It is a versatile technique used for producing both conductors and dielectrics. CVD films typically have excellent feature-filling capabilities, enabling them to fill high aspect ratio vias and trenches found in modern integrated circuits. 14.1.1 CVD Fundamentals In CVD, reactive gases pass over the silicon wafer. These gases adsorb onto the wafer surface and react there, forming a film. By-products of the reaction leave the surface, as gases, and are pumped away. The reactions are activated either by thermal energy through heating the wafer or radio frequency (RF) energy through plasma (less commonly, other means such as laser light are used). In the latter case, RF energy is used to strike plasma in the reaction chamber, creating energetic electrons that propel the reaction forward. A typical CVD reactor is shown schematically in Fig. 14.1. The gases enter the chamber through an inlet. They pass over the heated wafer, then flow out of the chamber to the pumps. 14.1.2 Some History Few CVD processes operate at atmospheric pressure due to the formation of gas-phase particles. As a result, chemical vapor deposition wasn’t developed until the advent of reliable vacuum equipment in the late nineteenth century. Pyroltyic carbon was deposited by Sawyer and Man in 1880 and various metals were deposited by hydrogen reduction of their chlorides in 1896 by Aylesworth.1 Modern CVD reactors were developed in the mid-twentieth century. It was the invention of planar processing in 1959 by Noyce and Hourni that made integrated circuit fabrication possible. This process relies on thin film deposition, followed by patterning and etching to define the metal and insulating layers that wire together the transistors. The first CVD film used in semiconductor fabrication was Vapox, an SiO2 film deposited from silane and oxygen at atmospheric pressure. It was used as an intermetal dielectric and passivation. 14.1.3 CVD Versus Other Methods There are many methods of depositing thin films, several of which are used in integrated circuit fabrication. When aluminum was the primary conductor used in interconnects, a nice division of labor

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

14.1

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.2

CHEMICAL VAPOR DEPOSITION 14.2

WAFER PROCESSING

Showerhead (inlet) Wafer

Platen (heater)

Exhaust

FIGURE 14.1

A typical CVD reactor.

existed between CVD and PVD—PVD was used to deposit aluminum. The purity of this process provided low resistivity with precise control over the Si and Cu dopants. The insulating layers between the films were deposited by CVD, typically plasma enhanced. The vias connecting different metal layers were tungsten, deposited by CVD. In recent years, there has been a switch to copper as the interconnect metal of choice. Its low resistivity, combined with improved barriers for preventing Cu diffusion, has made it the conductor of choice in high performance applications. While Cu can be deposited by CVD methods, it is more economical to use electroplating. Table 14.1 lists some of the common deposition techniques used in semiconductor fabrication. 14.1.4 Typical Applications CVD films are used throughout the manufacture of integrated circuits, from the formation of the transistors to the interconnect layers that wire the transistors and in the final passivation that protects the device. Early in the device fabrication, epitaxial (single crystal) silicon is grown on the wafer to improve transistor isolation and prevent latchup of CMOS devices. CVD silicon nitride is used as a mask in defining the transistor areas. After the gate oxide is grown, the gate is formed with CVD polysilicon and possibly CVD tungsten silicide or similar material. Once the transistors are

TABLE 14.1 Deposition Techniques Weaknesses

Applications

Chemical vapor deposition

Method

Excellent conformality, economical

Residual contaminants, grain size

Physical vapor deposition Electroplating

Precise control of purity and dopants Excellent conformality, low resistivity, economical Nearly perfect step coverage

Poor conformity

Intermetal dielectrics, shallow trench isolation, passivation layers, diffusion barriers Aluminum, diffusion barriers, seed layers

ALD

Strengths

Limited to conductors, purity Slow

Copper deposition Barriers

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.3

CHEMICAL VAPOR DEPOSITION CHEMICAL VAPOR DEPOSITION

14.3

formed, layers of metal lines separated by dielectric are laid down, forming the interconnect structure. When aluminum is used as the primary conductor, CVD tungsten provides the conductive medium between metal layers. CVD is also used for the dielectric separating metal layers. This could be CVD SiO2, fluorinated SiO2, or carbon-doped SiO2 (the latter two low-k films being used to reduce the capacitance of the circuit). For copper metalization, the diffusion barrier between copper and oxide may be deposited by CVD. Once complete, the wafer is given a scratch protection or passivation layer, typically silicon nitride or oxynitride, deposited by plasma-enhanced CVD.

14.2 THEORY The theoretical study of CVD focuses on two areas—the transport of gases to and from the wafer, and the chemical reactions that take place both on the wafer and in transit. 14.2.1 Mass Transfer In order to deposit a CVD film, the reactants must be transported from the inlet to the wafer surface. For many processes, the deposition rate is limited by how fast this takes place. Additionally, film uniformity can be strongly dependent on mass-transfer rates. Mass Transfer Versus Kinetic Control. Consider a tungsten CVD process in which hydrogen and tungsten hexafluoride flow into a chamber and react to form tungsten: 3H2 + WF6 → W + 6HF

Mass transfer

Kinetic

1/ T FIGURE 14.2

Kinetic

Rate

Ln (rate)

The volatile HF is pumped away. If the wafer were maintained at room temperature, the reaction would proceed at near zero rate. As the temperature is increased, the deposition rate would increase exponentially. At sufficiently high temperature, the rate would slow down and level off, as illustrated in Fig. 14.2. What is going on? At low temperatures, the reactants are being consumed at a very slow rate, much slower than they are entering the chamber. Thus the deposition rate is completely governed by the reaction rate on the wafer surface. This reaction rate is very temperature sensitive, and so increases rapidly with temperature. Under these conditions, the process is said to be kinetically controlled. That is, the deposition rate is governed by the chemical kinetics or the reaction rate. As the temperature is increased further, the reaction rate eventually reaches and then exceeds the rate at which WF6 or H2 arrive at the wafer surface. Once that happens, the process is no longer kinetically controlled; it is now mass-transfer controlled or mass-transfer limited. At this point, further increases to the temperature cannot increase the deposition rate because there is not enough material to react. The only way to increase the rate at this point is to turn up the flow.

Mass transfer

Reactant flow

Mass transfer versus kinetic control.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.4

CHEMICAL VAPOR DEPOSITION 14.4

WAFER PROCESSING

Does it matter if the process is kinetically controlled or mass-transfer limited? Yes. When masstransfer limited, the surface is starved for at least one of the reactants. That means the sticking coefficient for that reactant will be high. As we will see later in the chapter, high sticking coefficients result in poor step coverage. On the other hand, in the kinetic regime, the surface is saturated with reactants. Under these conditions, by-products can become trapped in the film, reducing its purity. In the case of the tungsten reaction, the level of fluorine incorporated into the film is much higher when the process is kinetically controlled. Gas Utilization. For many CVD processes, reactants are expensive and so we want to use them most efficiently. Unfortunately, the most efficient operating conditions are those that produce the lowest deposition rate, i.e., flow the gases into the chamber very slowly, to allow lots of time for the reactants to diffuse to the wafer. Mass-transfer limited processes will be more efficient than kinetically controlled ones. The low sticking probabilities of kinetically controlled processes mean that some molecules will hit the wafer, bounce off, and be pumped out. The utilization can be easily calculated if you know the flow and deposition rates. Transport Mechanisms: Diffusion, Convection, Thermal Diffusion, E Fields, Pe Number. Reactants are transported from the inlet to the wafer primarily by convection and diffusion. Several secondary mechanisms may also be present. In convection, the reactants are transported by the gas velocity. In diffusive transport, the reactants migrate from areas of high concentration to low. The rate of convective transport is given by j = Yi ρu where Yi is the mass fraction of species i, r is the density of the gas, and u is the velocity. The diffusive flux is given by j = − Dρ∇Yi where D is the diffusion coefficient of species i in the mixture. The relative importance of convection and diffusion is determined by the dimensionless Peclet number Pe =

ud D

where d is the characteristic length of the chamber (typically the distance from showerhead to wafer). If Pe << 1, the transport is primarily by diffusion. If Pe >> 1, it is by convection. For most CVD reactors, Pe is between 1 and 10, indicating that convection is somewhat stronger, but both mechanisms are important. This can have implications for process development. For instance, if a process engineer changes a carrier gas from helium to argon, as a cost-saving measure, there will likely be the unintended consequence of lowering the deposition rate because of the lower diffusivity of argon. Diffusive transport can also lead to nonuniformities when there are purge flows near the wafer surface. The reactants diffuse out of the reaction zone, following the concentration gradient, leading to a thin deposition at the wafer edge. The Pe number can be used to estimate the gas utilization of a process, at least for the rate-limiting reactant. Figure 14.3 shows the gas utilization versus Pe number for a mass transfer limited reaction in a showerhead reactor like Fig. 14.1. In the typical range of 1 to 10, the efficiency is between 25 and 68 percent. Additional transport mechanisms may also be important. In plasma processes, electron and ion transport are governed by the electric fields in the chamber. The chamber surfaces are typically somewhat negative due to higher electron mobilities. This leads to ion bombardment of those surfaces, including the wafer. Thermal diffusion is a weak transport phenomenon that only becomes important where there is a large difference in the molecular weights of the gases and large temperature gradients. For instance,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.5

CHEMICAL VAPOR DEPOSITION CHEMICAL VAPOR DEPOSITION

14.5

0.9 0.8

Reactor efficiency

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0

10

20

30

40

50

60

70

Peclet number FIGURE 14.3

Reactor efficiency as a function of peclet number.

in CVD tungsten—where H2 and WF6 are the reactants—there is a difference of 298/2 = 149 in the molecular weight. Under these conditions, thermal diffusion causes the heavier molecule to move toward the colder surface and the lighter one to move to the hotter surface. In tungsten this can reduce the deposition rate by 20 percent. Even for smaller mass differences, the effect can be important. In polysilicon deposition when H2 or He is the carrier gas and silane is the reactant thermal, diffusion has a noticeable effect.2 14.2.2 Kinetics While the laws of mass transfer are universal, the kinetics of a reaction is specific to the process under consideration. Thus the reaction mechanisms must be worked out for each chemistry. Surface Chemistry. Often there are many reactions occurring on the substrate surface during CVD film growth. Broadly speaking, these can be broken down into three sets of reactions—adsorption, reactions, and desorption. The first step in the surface chemistry is adsorption of the reacting species onto the substrate. The simplest form of chemisorption is where the adsorbing molecule attaches to an open site on the substrate surface. This is the Langmuir-Hinshelwood mechanism. Some molecules decompose during adsorption, requiring multiple open sites for adsorption (Eley-Ridel mechanism).16 The adsorbed species react with one another, often through multiple pathways, to produce the desired film and by-products. The by-products must desorb off the wafer surface and reenter the gas phase, where they are pumped away. The surface chemistry of most CVD reactions is extremely complex and unfortunately theoretical methods are not as advanced as for gas-phase reactions. Nevertheless, computational chemistry has made great strides in recent years and surface reaction pathways are being worked out. For instance, the effect of germane on Si deposition has been analyzed by Hierlemann et. al.3 Computers will probably have to advance by another couple of orders of magnitude before surface kinetics can be routinely determined by these methods. Until then, a semiempirical approach is often used. This consists of using chemical intuition to postulate some chemical pathways. One then looks at the thermodynamics of the system and rejects the paths that are not energetically favorable. Careful experiments

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.6

CHEMICAL VAPOR DEPOSITION 14.6

WAFER PROCESSING

can then be used to estimate the rate coefficients for the rest. For CVD tungsten, this has been done to varying levels of detail.4,5,6 Gas-Phase Chemistry. Up until now we have discussed reactions occurring on the wafer surface. However, in many CVD processes, reactions occur in the gas prior to the reactants reaching the wafer. This is particularly true for high-pressure processes (for instance, those operating at 1 atm) and for plasma processes. A classic example of a thermal gas-phase reaction is SiH4 → SiH2 + H2 in polysilicon deposition. Coltrin, Kee, and Miller found that this reaction plays a key role in the deposition of Si on the wafer surface.2 Deposition comes from both SiH4 directly and from SiH2. As the temperature increases, the gas-phase reaction becomes increasingly important and a larger fraction of the deposition is from SiH2. Interestingly, adding H2 to the mixture suppresses, to some degree, the formation of SiH2, making SiH4 the dominant surface reactant. Thermodynamics Versus Kinetics. For a thermal CVD process to move forward, it must be energetically favorable. That is, the energy level of the final state must be lower than the initial state. This is a problem in thermodynamics and is solved by minimizing Gibbs’ free energy. However, just because a reaction is thermodynamically favorable, it doesn’t mean it is useful for CVD. Thermodynamics doesn’t consider the rate of reaction. It only says that eventually the reaction will occur. It is kinetics that deals with the rates of reactions. In order to be useful for CVD applications, a reaction must be both thermodynamically and kinetically favorable (i.e., occur at a fast rate). When investigating a new chemistry, it is common to begin with a thermodynamics study to confirm its viability. Middleman and Hochberg7 provide a detailed example of this type of calculation.

14.2.3 Plasma Plasma processing is widely used in semiconductor processing, particularly in deposition, etching, and photoresist stripping. In CVD, the energy in the plasma supplements the thermal energy present, allowing a much wider range of chemistries to be used while maintaining moderate wafer temperatures. Plasma can also produce ion bombardment of the wafer, which can be beneficial for improving feature filling. E-energy Instead of Thermal. To prevent excessive diffusion of dopants and other problems, CVD processes generally cannot be run at temperatures over 400°C. Yet, some very useful chemistries don’t have practical deposition rates in this temperature range. For instance, thermal deposition of SiO2 from TEOS and N2O requires temperatures of 700°C or higher. So how can one take advantage of the excellent step coverage of this film without damaging the device being fabricated? The answer is plasma processing. In typical plasma, the electrons have temperatures of 10,000 K or higher, while the wafer remains cool. Allows Lower Temperatures. The energy required to break chemical bonds is typically a few electron volts (eV). The average electron energy in plasma is typically in this range, and at the high energy tail of the electron distribution, the energies are much higher (more than 10 eV). These electrons collide with neutral gas molecules and either excite or ionize them. Their tremendous energy allows reactions that would normally require hundreds of degrees to occur at room temperature. In the TEOS case mentioned previously, the addition of plasma allows the process to be operated in the range of 300 to 400°C. This process can take place at room temperature, but it is found that the film quality is greatly improved by heating the wafer. Ion Bombardment. If the wafer platen is negative biased, positive ions will be drawn out of the plasma and will bombard the wafer surface. For low-density plasma, such as typical capacitively coupled systems, ion fluxes are not high enough to provide significant etching. However, they can

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.7

CHEMICAL VAPOR DEPOSITION CHEMICAL VAPOR DEPOSITION

14.7

Inductive coils

RFin FIGURE 14.4 excited.

Left: inductively excited plasma, right: capacitively

densify the film and improve the quality of the film. Ion bombardment can also be used to adjust the stress of a film. For instance, plasma-enhanced, chemical-vapor-deposited (PECVD) silicon nitride films are typically very tensile. Under ion bombardment, this high stress can be reduced or even made compressive. In high-density plasma, the high ion flux causes sputter etching of the deposited film. The sputter yield is highest at about 45° to the incoming ion direction. Over time, this preferential etching can produce 45° facets at feature corners. When the deposition and etch rates are well balanced this can be used to prevent trenches from pinching off, resulting in improved feature fill. Methods of Plasma Coupling. The plasma energy is brought into the chamber by one of two methods—capacitive coupling or inductive coupling. This is shown schematically in Fig. 14.4. In capacitive discharges, two surfaces in the chamber form the two plates of a capacitor. These are typically the showerhead and platen. One is grounded and the RF is applied to the other. The electric fields between the two plates create plasma. In inductively coupled plasma, electrical energy is applied to a coil outside of the chamber. Electromagnetic fields propagate from this coil into the chamber where they cause the plasma to form.

14.2.4 Step Coverage The greatest strength of CVD is the ability to deposit deep into trenches and vias. This allows uniform or near uniform film thickness on the side walls and bottom of features. This is important for depositing barrier layers or for films designed to fill features, such as tungsten plugs. The step coverage of a process is determined by the sticking probability, or sticking coefficient of the reactants. As the reactants enter a trench or via, they bounce off the walls on their way down to the bottom. If the sticking probability is high, all the reactants stick in the first few bounces at the top of the feature. This is why PVD, with its near unity sticking coefficient, has such poor step coverage. In CVD the sticking coefficients are typically in the range of 10−1 to 10−4. At the lower end of this range, it takes 10,000 wall collisions before a molecule sticks. So it is easy to imagine that under these conditions, the reactants can get down into the deepest trenches. Figure 14.5 shows the step coverage in a 4:1 aspect ratio trench at four sticking coefficients. Sticking probability is defined as S=

reaction rate arrival rate

To reduce the sticking coefficient, and improve the step coverage, one must either slow down the reaction rate or speed up the arrival rate. Lowering the temperature will often improve step coverage because it reduces the reaction rate with minimal effect on arrival rate. Increasing pressure can improve or degrade step coverage depending on the rate kinetics. For instance in CVD tungsten, increasing the pressure initially improves step coverage, then degrades it.8,9

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.8

1.4

1.4

1.2

1.2

1

1

0.8

0.8

0.6

0.6

0.4

0.4

0.2

0.2

0 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 X (µm)

Sticking coefficient = 1, Bottom coverage = 8% (a)

Sticking coefficient = 0.1, Bottom coverage = 25% (b)

1.4

1.4

1.2

1.2

1

1

0.8

0.8

FIGURE 14.5

Y (µm)

Y (µm)

0 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 X (µm)

0.6

0.6

0.4

0.4

0.2

0.2

0 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 X (µm) Sticking coefficient = 0.01, Bottom coverage = 58% (c)

14.8

Y (µm)

Y (µm)

CHEMICAL VAPOR DEPOSITION

0 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 X (µm) Sticking coefficient = 0.001, Bottom coverage = 100% (d )

Effect of sticking coefficient on step coverage in a 4:1 aspect ratio trench.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.9

CHEMICAL VAPOR DEPOSITION CHEMICAL VAPOR DEPOSITION

14.9

14.2.5 Particles Like any piece of semiconductor equipment, CVD systems can suffer from particle contamination. In addition to the typical sources, like flaking or friction, CVD systems can create particles from the chemistry itself. To get a handle on the particles, it is important to understand both how they are created and how they are transported to the wafer. Creation Mechanisms. Particles can be generated in a chamber volume through gas-phase reactions, or they can form at surfaces through flaking and abrasion. In addition, moisture droplets can nucleate on particles in the load lock during pumpdown. Of these mechanisms, only gas-phase nucleation (GPN) is unique to CVD. In the ideal CVD process, the gaseous precursors don’t react in the gasphase, or do so very slowly. However, at high pressures—where there are many gas collisions—and high temperatures, many processes will proceed in the gas phase. The chemistry of GPN is complex and has only been studied in depth for silicon deposition.10,11 Once created, particles can be transported to the wafer surface, resulting in a defect. Transport Mechanisms.

There are five mechanisms for transporting particles in CVD reactors.

Gravitational setting. Large particles can fall onto the wafer surface. The settling time is a function of particle size and density, as well as the chamber pressure. Figure 14.6 shows settling times for various size particles of density 1 g/cm3. Convection. Like species transport, the gas flows can carry the particles to the wafer surface. Brownian diffusion. Small particles (less than 1 µm) can be moved around by collisions with the gas molecules in the chamber. This motion is random and results in a diffusive-type behavior where the particles tend to diffuse from regions of high concentration to low. Thermophoresis. Just as with thermal diffusion, temperature gradients can move particles away from hot surfaces toward cold. This is beneficial in cold-wall reactors where the wafer is much hotter than its surroundings. Interestingly, even very small temperature differences, like a few degrees, can push particles away from the wafer surface.7 Electric fields. In a plasma environment, particles tend to pick up charge. They are then transported by the local electric fields. These fields can form regions that serve as particle collection areas or traps. Once the plasma is shut off, these clouds of particles can migrate to the wafer surface.12

1000

Terminal velocity (cm/s)

100 10 1 0.01 torr 0.1 0.1 torr 0.01 1 torr 0.001 10 torr 0.0001

100 torr

0.00001 0.01 0.000001

760 torr 0.1

1

10

Particle diameter (µm) FIGURE 14.6

Particle settling time at different pressures.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.10

CHEMICAL VAPOR DEPOSITION 14.10

WAFER PROCESSING

14.2.6 Wafer Temperature Rarely is it practical to measure the wafer temperature directly. However a uniform, well-controlled temperature is often essential for achieving a uniform, high-quality deposition. The two most common ways of achieving temperature uniformity are to maintain the entire chamber at a single temperature (hot-wall reactor) or to place the wafer on a large thermal mass. As will be mentioned later, hot-wall reactors deposit on all surfaces, hurting gas utilization and increasing particle risk. Thus they are not as commonly used these days. However, they are hard to beat for achieving excellent wafer temperature uniformity. In cold-wall reactors, the wafer is placed on a heated platen and absorbs thermal energy both from conductive and radiative heat transfer. It also loses heat to its surroundings by the same mechanisms. As a result its equilibrium temperature will be less than the platen temperature. How much less depends on a number of factors—wafer platen gap, gas type and pressure, and wafer emissivity. An excellent description of these effects is provided by Hasper et. al.13 The heat conduction across the platen wafer gap depends on the “effective gap” between the two. This is the physical gap, plus a function of the mean free path of the gas. At low pressures, the mean free path is long and the effective gap is large. This slows heat transfer to the wafer. Because of this, at very low pressures (millitorr range) the heat transfer is primarily by radiation and the wafer can be 100°C cooler than the platen. As the pressure is increased, the mean free path shrinks as does the effective gap, leading to better heat transfer. Above 10 or 20 torr, the effective gap is essentially the same as the physical gap and very little additional heat transfer occurs with increased pressure. Figure 14.7 shows wafer temperature versus pressure. For this case, even at 100 torr, the wafer temperature is 13°C cooler than the platen. At typical CVD gas flows, convective heat transfer is not important, however, at pressures above 100 torr, natural convection can occur in the CVD chamber. This buoyancy-driven flow can greatly increase the heat losses off the wafer, lowering its temperature. It can also affect the transport of species to the wafer surface.4

410

Wafer temperature (C)

390 370

Platen temperature Conduction dominates

350 330 310 290 270 250 0.001

Radiation dominates 0.01

0.1

1

10

100

Pressure (torr) FIGURE 14.7 Wafer temperature versus pressure in N2 ambient with platen at 400°C, chamber at 50°C and wafer to platen gap of 0.1 mm.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.11

CHEMICAL VAPOR DEPOSITION CHEMICAL VAPOR DEPOSITION

14.11

14.3 COMPONENTS OF A CVD SYSTEM Up until now, our focus has been on a process chamber where reactions occur and films are deposited on silicon wafers. The chamber is a key component of a CVD system, but it is not the only one. Gases must be delivered to the chamber precisely and uniformly, then efficiently removed. RF energy must be coupled to the chamber. Wafers must be moved to the loadlock, pumped down, and then transferred to the process chamber. Figure 14.8 schematically shows the components of a CVD system. 14.3.1 Chamber There are a wide range of CVD process chambers in use. For kinetically controlled processes, it is important to maintain a uniform wafer temperature. The easiest way to do this is to keep the entire chamber at a single temperature. These chambers, referred to as hot-wall reactors, can provide excellent thickness uniformity. Unfortunately, the deposition occurs on all chamber surfaces, in addition to the wafer. As a result, the gas utilization can be poor. Also, frequent cleaning may be required. For these reasons, commercial reactors are more often of the cold-wall variety. The chamber walls are usually water cooled, while the wafer is heated by the platen it rests on. If the platen is carefully designed, wafer temperature variations of less than 1°C can be achieved. Another important characteristic of the chamber is the number of wafers it processes at a time. When wafer sizes were smaller, and the value of processed wafers was less, it was common to process 8 to 25 or even more wafers simultaneously. There is an obvious throughput advantage in doing so. However, in recent years single wafer and small batch reactors have come to dominate. There are several reasons for this. Very large batch reactors generally require hot walls to achieve temperature uniformity, and it can be difficult to uniformly deliver the reactants to all wafers. Also, as wafer sizes have increased, it becomes more difficult to make a chamber with a small footprint and a large batch size. Lastly, the value of wafers has increased with their size. Should a problem occur during the processing of a large batch, a substantial amount of revenue can be at risk. Gas delivery methods also distinguish chamber designs. Large batch tube reactors flow the gas in one end and exhaust it out the other. The gas must diffuse between wafers to reach the wafer center. This design results in poor uniformity when mass transfer effects are important. Most commercial reactors today use a showerhead-type inlet to deliver the gas. The face plate of the showerhead is perforated with anywhere from a few hundred to thousands of holes (typically about 1 mm in diameter).

Process gases Gas box RF energy FOUP

Vent Loadlock

CVD

Match network

RF generator

Robot

Wafers Vacuum pumps FIGURE 14.8

Vacuum pumps

Schematic of a CVD system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.12

CHEMICAL VAPOR DEPOSITION 14.12

WAFER PROCESSING

With good design, showerheads can deliver species with 1 percent uniformity. This allows processes that are mass transfer limited to be deposited uniformly. A system combining such a showerhead with a uniform platen heater can successfully deposit films over the full range from mass transfer limited to kinetically limited. This versatility has made this design very popular. 14.3.2 Pumps CVD processes send large volumes of reactive and potentially corrosive gases to the pumps. Because of this, capture pumps like cyropumps are not practical. Typically mechanical pumps such as a roots blower with a rotary vane pump would be used. Concern over pump oil diffusing into the process chamber has led to the replacement of vane pumps with oil free or dry pumps. In applications requiring process pressures of less than 100 mtorr, a turbo pump is generally used. Pumping technology is discussed in more detail in books on vacuum systems such as Roth14 and O’Hanlon,15 and Lafferty.16 14.3.3 Wafer Handling To automate the CVD process tool and reduce the possibility of particle contamination, all wafer movement in a production tool is done by robot arms. The cassette or front opening unified pod (FOUP) of wafers is placed in the tool by the operator. From there, the wafers pass through a load lock in which the pressure is reduced from atmospheric pressure to the process pressure. The robot then moves the wafer into the CVD process chamber where the film is deposited. Once complete, the robot arms move the wafer back to the load lock and then to the FOUP. 14.3.4 Gas Delivery System The flow control components of a CVD system are generally clustered in a single module—the gas box. All the process gases enter the gas box from the fab facilities typically through 1/4 in diameter electropolished stainless steel tubing. Pneumatic values control the flow of gases. The magnitude of the flow is regulated by mass flow controllers. The valves and mass flow controllers (MFCs) are controlled by the system computer, which executes the process recipes. These recipes instruct various valves to open and set the MFCs to the proper set points. Many CVD processes use precursors that are liquids at room temperature. In order to get this material into the process chamber, it must be vaporized, then delivered in a controlled manner. There are two common methods used for this depending on the vapor pressure of the precursor and its sensitivity to decomposition. The simplest method is to bubble an inert gas through the liquid, allowing the bubbles to pick up some of the vapor. This method is easy to implement and inexpensive, but is not suitable for fragile materials that will decompose after extended time at elevated temperatures. Alternatively, the liquid can be sprayed onto a heated surface and evaporated there. Then the flow can be precisely controlled with a liquid flow controller, and the thermal exposure is limited. Often the gas lines downstream of the evaporator must be heated to prevent the precursor from recondensing. 14.3.5 RF System For plasma-enhanced CVD systems or those using a plasma clean, an additional set of components is required to generate the plasma. An RF generator is used to produce the high-frequency energy needed by the plasma. This is typically at 13.56 MHz, but other frequencies are also used. Commercial generators are usually designed to send the electrical energy into a 50-Ω load. Since the load presented by the CVD chamber can vary widely depending on the chamber geometry, gases used, pressure, and the like, a matching network must be inserted between the generator and the chamber. Matching networks designed for 13.56 MHz operation are usually adaptive. They will vary their capacitance or inductance to match changes in the chamber impedance, so the RF generator always sees a 50-Ω load. If the match is unable to do this, much of the energy will be reflected back to the generator. Its protective circuitry will then shut it down.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.13

CHEMICAL VAPOR DEPOSITION CHEMICAL VAPOR DEPOSITION

14.13

A commercial CVD tool is a complex piece of equipment capable of processing up to 100 wafers per hour (or more) and costing millions of dollars. It may consist of multiple CVD modules or CVD modules combined with other processes like etch or PVD. In addition to the components discussed here, there will be control systems to run the machine and sensors to monitor its state, as well as a computer for interacting with the operator. There may also be metrology equipment for measuring the thickness and uniformity of the film just deposited and reporting any issues back to a central computer in the fab.

14.4 PRECOATING AND CLEANING Why Precoat. After a CVD chamber has been opened for maintenance or cleaning, it must be run for some time before the deposition rate, thickness uniformity, and other film properties stabilize. The time required varies with the process, but is typically in the range of one to ten wafers worth of deposition. It is difficult to determine why CVD processes exhibit this transient behavior upon startup. It is likely that the maintenance or cleaning leave residual chemicals behind that poison the reaction. Once these are consumed, or buried, the process then runs at its normal rate. Methods of Cleaning. CVD chambers are cleaned with plasma processes. Frequently fluorine containing molecules such at NF3, CF4, and C2F6 are used. The resulting F and F2 species react with the CVD film that has deposited on the chamber walls and platen and form volatile compounds that are then pumped away. For films that don’t contain a volatile fluorine containing compound other clean gases must be used. For instance, chlorine is effective at removing Al films whereas F is not. Unfortunately, some materials don’t readily form volatile compounds. Copper, for instance, is very difficult to remove by plasma cleaning. In situ plasma cleaning can, over time, wear chamber components out leading to frequent maintenance and additional expense. The ion bombardment that accompanies the plasma process roughens surfaces. Additionally AlF3 layers can grow on aluminum parts. These changes can lead to drift of uniformity or deposition rate. Because of this, CVD tools frequently use remote plasma for cleaning. Inductively coupled or microwave high-density plasma is generated upstream of the chamber and the F radicals are fed into the chamber. The very short-lived ions are lost to wall recombination before the gas reaches the chamber. The result is a purely chemical clean with no ion bombardment.

14.5 TROUBLESHOOTING CVD processes are complex and it is not uncommon for things to go wrong. Once a process goes out of spec, a good understanding of CVD fundamentals, combined with a systematic approach, will help identify and resolve the problem. Unfortunately it is human instinct to draw hasty (and poor) conclusions from incomplete data. (See Dorner for a fascinating discussion of this trait).17 Some common problems along with possible causes are listed next. 14.5.1 Particles A well-designed CVD system will have excellent particle performance. However, particle problems do crop up from time to time. Gas-Phase Nucleation. Gas-phase nucleation occurs when the process gases react in the gas phase and begin growing particles. This will typically occur when there has been a process change that promotes gas-phase reactions. These changes include increasing the process pressure, reactant concentrations, and temperature. Another possible cause is changing from a light carrier gas

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.14

CHEMICAL VAPOR DEPOSITION 14.14

WAFER PROCESSING

(e.g., He) to a heavy one (Ar) that supports the three-body collisions needed for gas-phase reactions.18 In extreme cases, GPN can be seen during processing by shining a bright light into the chamber and observing a gray or black smoke. Another sign—SEM photos show the particles to be spherical in shape and uniform in size. They may also be agglomerations of spheres. That is a strong evidence of GPN. Gas-phase reactions can also occur upstream in the gas box. For instance, an air leak in a silane line will cause “dusting” of the line. Flaking. Flaking occurs when the CVD film has become too thick on the walls of the chamber. CVD films often have high stresses and at sufficient thickness will crack and shed particles. These particles tend to be irregular in shape with a wide size distribution. Their composition is similar to the film being deposited. Both thermal and pressure cycling can make the problem worse. More frequent or effective cleans will generally fix the problem. Abrasion. Misadjustment of moving parts can cause components to scrape in the process chamber. At the point of contact, particles are shed, and they may end up on the wafer. Like flakes, these particles are irregular in shape and of varied size. However, their composition is that of the scraping components, not the film. Also the particle pattern on the wafer may be nonuniform, with higher particle densities near the point of contact. Condensation. In moving from the fab environment to the CVD process chamber, the wafers are pumped down to vacuum in a load lock. Before pump down, this load lock is filled with air or perhaps N2 with a residual of air. During a fast pump down the air temperature drops rapidly, and the moisture present in the air can condense. Such condensation occurs preferentially at nucleation sites, such as dust particles in the air. The result is a small water droplet, surrounding a particle that can fall onto the wafer. The water then evaporates leaving behind a contaminant. If this is the case, partitioning experiments will point to the load lock as the particle source rather than the process chamber. Condensation can be eliminated by slowing the pump down or reducing the temperature drop. The latter can be done by shrinking the load-lock volume so all of the gas is in close proximity to a warm wall.19 14.5.2 Deposition Rate and Uniformity Fundamentally, the deposition rate depends on just two things—the local magnitude of reactive species and energy (either thermal or RF). Armed with this information, plus an understanding of the process parameters affecting the rate, one can design experiments to identify the source of the drifting deposition rate or poor uniformity. Some typical problem areas are as follows: Gas delivery. If the rate is dropping, it may be due to a clog in the gas delivery system or a problem with an MFC. Rate of rise tests can determine if you are getting the flow you desire. Sinks. When the reactant concentration at the wafer drops, it can be due to a delivery problem, or it can be that the reactants are being consumed elsewhere. For instance, if a powder builds up on the showerhead over time, it will present an increased surface area in which more material will deposit, reducing the deposition rate on the wafer. Poisons. After chamber maintenance, the chamber walls can be left contaminated. Materials in the chamber can oxidize on air exposure, moisture can adsorb onto the walls, skin oils can be transferred, and so forth. These compounds can poison the CVD reaction, reducing the deposition rate or adversely affecting uniformity. Wafer temperature. The platen temperature can drift due to problems with the temperature controller or measurement. The coupling to the wafer can also fluctuate. For instance, if wafers are heated up too quickly, especially 300 mm wafers, they can bow, taking on a bowl shape. It can take a minute or more for them to relax. Or the emissivity of the wafer or platen may change, altering the radiative heat transfer. Changes in showerhead emissivity or temperature can also

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.15

CHEMICAL VAPOR DEPOSITION CHEMICAL VAPOR DEPOSITION

14.15

affect the wafer temperature. For unclamped wafers, changes in pressure, especially in the 1 to 10-torr range, can have a large effect on the wafer temperature. If the platen roughens over time, it can reduce heat transfer.

14.5.3 Film Properties Diagnosing problems with film properties such as film stress, refractive index, or dielectric constant is difficult because of our weak theoretical understanding of these things. The most effective way to treat these problems is to use design of experiments (DOE) methodology to empirically determine the relationships between the film properties of interest and the process parameters (e.g., flows, RF power, pressure, and temperature.20 Once this mapping is complete, the cause of a property drift can be assigned to the parameters that affect it. For instance, if refractive index has been found, through a DOE study, to increase with increasing RF power and decreasing pressure, one can then look for problems in these two areas. Perhaps the matching network is not working properly, leading to high reflected power levels. Or perhaps some reactant by-products have found their way into the pressure sensor, leading to stray readings.

14.6 FUTURE TRENDS The transition from aluminum metalization to copper, combined with the ongoing need to reduce feature sizes, is continuing to drive CVD development. In addition, there is a strong economic push to keep each layer of the device economical. Atomic layer deposition has attracted a lot of interest for its ability to deposit extremely conformal films. In this method, a reactant (gas A) is first flowed, causing a single monolayer to adsorb onto the wafer. This is followed by gas B that reacts with the monolayer to form an atomic layer of film. This is repeated until the desired thickness is achieved. ALD produces highly conformal films, even into deep features. However, its one layer at a time approach results in a slow deposition rate. Thus its applications have tended to be in thinner films, like nucleation and barrier layers. A review of ALD is found in Ref. 21. Recently, a hybrid ALD-CVD method has been developed by Hausmann et al., which promises CVD-like deposition rates combined with the perfect conformity of ALD.22 It relies on balancing two competing reactions to produce a self-limiting layer tens of atomic layers thick per cycle. This may extend ALD processing to thicker film applications. Another approach to filling device features is superconformal filling in which the feature bottom has a higher deposition rate than the top. This superfilling technique, originally developed for electroplating, has been applied to CVD copper, using an iodine catalyst. See Josell et al. for details.23 Another method of achieving excellent film conformality is to operate the process chamber under extremely high process conditions. At pressures of typically 200 atm, the CO2 ambient becomes a supercritical fluid. It then has a density similar to a liquid while maintaining a diffusion coefficient similar to a gas. This allows reactants to be very efficiently transported into vias and trenches. Watkins et al. have shown excellent film conformity using this technique.24

REFERENCES 1. Mattox, D. M., “The History of Vacuum Coating Technology: Part V,” Vac. Technol. Coat, 2002, pp. 32–37. 2. Coltrin, M. E., R. J. Kee, and J. A. Miller, “A Mathematical Model of Silicon Chemical Vapor Deposition,” J Electrochem Soc., Vol. 131, pp. 1206–1213, 1986. 3. Hierlemann, M., C. Werner, and A. Spizer, “Equipment Simulation of SiGe Heteroepitaxy: Model Validation by Ab Initio Calculations of Surface Diffusion Processes,” J. Vac. Sci. Technol. B, Vol. 15, pp. 945–941, 1997.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH14.qxd

04/04/2005

19:52

Page 14.16

CHEMICAL VAPOR DEPOSITION 14.16

WAFER PROCESSING

4. Kleijn, C. R., “Chemical Vapor Deposition Processes,” in M. Meyyappan (ed.), Computational Modeling in Semiconductor Processing. Artech House, Boston, MA, 1995, pp. 97–229. 5. Arora, R., and R. Pollard, “A Mathematical Model for Chemical Vapor Deposition Processes Influenced by Surface Reaction Kinetics: Application to Low Pressure Deposition of Tungsten,” J. Electrochem. Soc., Vol. 138, pp. 1523–1537, 1991. 6. Wang, Y. F., and R. Pollard, “An Approach for Modeling Surface Reaction Kinetics in Chemical Vapor Deposition Processes,” J. Electrochem. Soc., Vol. 142, pp. 1712–1725, 1995. 7. Middleman, S., and A. K. Hochberg, Process Engineering Analysis in Semiconductor Device Fabrication, McGraw-Hill, New York, 1993. 8. Schmitz, J. E. J., Chemical Vapor Deposition of Tungsten and Tungsten Silicides, Noyce Publications, Park Ridge, NJ, 1992. 9. McInerney, E. J., E. Srinivasan, D. C. Smith, and G. Ramanath, “Kinetic Rate Expression for Tungsten Chemical Vapor Deposition in Different WF6 Flow Regimes from Step Coverage Measurements,” Zeitschrift fur Metallkunde, Vol. 91, pp. 573–580, 2000. 10. Han, P., and T. Yoshida, “Growth and Transport of Clusters in Thermal Plasma Vapor Deposition of Silicon,” J. Appl. Phys., Vol. 92, pp. 4772–4778, 2002. 11. Kremer, D. M., R. W. Davis, E. F. Moore, J. E. Maslar, D. R. Burgess, and S. H. Ehrman, “An Investigation of Particle Dynamics in a Rotating Disk Chemical Vapor Deposition Reactor,” J. Electrochem. Soc., Vol. 150, pp. G127–G139, 2003. 12. Hwang, H. H., E. R. Keiter, and M. J. Kushner, “Consequences of 3-Dimensional Physical and Electromagnetic Structures on Dust Particle Trapping in High Plasma Density Material Processing Discharges,” J. Vac. Sci. Technol. A, Vol. 16, p. 2454, 1998. 13. Hasper, A., J. E. J. Schmitz, J. Holleman, and J. F. Verwey, “Heat Transport in Cold Wall Single Wafer Low Pressure Chemical Vapor Deposition Reactors,” J. Vac. Sci. Technol. A, Vol. 10, pp. 3193–3202, 1992. 14. Roth, A., Vacuum Technology, North-Holland, Amsterdam, 1989. 15. O’Hanlon, J., A Users Guide to Vacuum Technology, 3rd ed., John Wiley & Sons, New York, 2003. 16. Lafferty, J. M. (ed.), Foundations of Vacuum Science and Technology, John Wiley & Sons, New York, 1998. 17. Dorner, D., The Logic of Failure. Perseus Books, Cambridge, MA, 1996. 18. McInerney, E. J., T. W. Mountsier, E. K. Broadbent, and B. L. Chin, “Silane Reduced Chemical Vapor Deposition Tungsten as a Nucleating Step in Blanket W,” J. Vac. Sci. Technol. B, Vol. 11, pp. 734–743, 1993. 19. O’Hanion, J. F., and J. J. Shieh, “Reduction of Water Aerosol Contamination During Pumping of a Vacuum Chamber from Atmospheric Pressure,” J. Vac. Sci. Technol. A, Vol. 9, pp. 2802–2807, 1991. 20. Box, G. E. P., W. G. Hunter, and J. S. Hunter, Statistics for Experimenters, John Wiley & Sons, New York, 1978. 21. Ritala, M., and M. Leskela, “Deposition and Processing,” in H. S. Nalwa (ed.), Handbook of Thin Film Materials, Vol. 1, Academic Press, San Diego, CA, 2002, pp. 103–159. 22. Hausmann, D., J. Becker, S. Wang, and R. G. Gordon, “Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates,” Science, Vol. 298, pp. 402–406, 2002. 23. Josell, D., S. Kim, D. Wheeler, T. P. Moffat, and S. G. Pyo, “Interconnect Fabrication by Superconformal Iodine-Catalyzed Chemical Vapor Deposition,” J. Electrochem. Soc., Vol. 150, pp. C368–C373, 2003. 24. Blackburn, J. M., D. L. Long, A. Cabanas, and J. J. Watkins, “Deposition of Conformal Copper and Nickel Films from Supercritical Carbon Dioxide,” Science, Vol. 294, pp. 141–145, 2001.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 15

EPITAXY Jamal Ramdani MEMC Electronic Materials Inc. St. Peter, Missouri

Giovanni Vaccari MEMC Electronic Materials Inc. Novara, Italy

15.1 INTRODUCTION The last three decades have witnessed a remarkable growth in the electronic and optoelectronic industry. The growth and preparation of semiconductor materials have played a major role in this success. The ability to prepare high-purity semiconductor materials, control interfaces and the doping profile and type, and engineer new material combinations has opened the door to new and higher performance electronic and photonic devices. Quantum-wells-based laser diodes and photodetectors, high-mobility two-dimensional electron gas transistors, heterojunction bipolar transistors, highbrightness GaN light emitting diodes, and strained silicon are a few examples of the devices that have emerged from material growth processes. Hand in hand with material engineering progress, equipment and chemical manufacturers have shown similar aggressiveness in developing state-of-the-art deposition tools and high-purity source materials to meet the ever-challenging demands for higher quality materials, lower costs, and safer operations. At the speed at which information technology is evolving, we look forward to meeting the market demand and the challenge of next generation electronic and photonic devices.

15.1.1 Basics of Epitaxy Royer1 first introduced the word epitaxy in 1928 from Greek meaning “ordered upon.” Epitaxy refers to the growth of a crystal (epitaxial layer or epilayer) upon a host crystal (substrate) in an ordered fashion. In other words, the symmetry between the contacting crystal planes must be respected. The growth mode depends on lattice mismatch or the difference between the parallel lattice constant of the epilayer and that of the substrate and their chemical compatibility. Thermodynamically, the equilibrium morphology or the growth mode is governed by the relationship of the sum of epilayer surface free energy (Eep) and epilayer-substrate interface free energy (Ei) with respect to substrate surface free energy (Es), also known as wetting conditions. Three main growth regimes have been identified and are illustrated in Fig. 15.1.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

15.1

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.2

EPITAXY 15.2

WAFER PROCESSING

Epilayer thickness 3-D island

Substrate

Substrate

Substrate

Layer by layer growth

Nucleation growth

S-K growth

FIGURE 15.1

Different growth modes in epitaxy.

1. Layer-by-layer growth Eep + Ei ≤ Es

(wetting)

2. Nucleation growth Eep + Ei >> Es

(no wetting)

3. Layer by layer followed by nucleation growth (S-K growth mode) Eep + Ei ≥ Es

(intermediate phase)

The Layer-by-Layer Growth or the “Frank-Van-Der-Merwe Growth Mode.” In this regime the system is thermodynamically stable and atoms aggregate on the surface of the substrate to form monolayer islands that enlarge with deposit time in order to complete a full monolayer. Then a new monolayer island starts and the sequence continues until the desired total thickness is attained. In practice, full monolayer coverage is hardly accomplished since subsequent monolayer islands begin before the completion of the first monolayer coverage, but overall the growth process stays twodimensional. This is the case in homoepitaxy such as Si/Si and GaAs/GaAs or heteroepitaxy of lattice matched materials such as AlGaAs/GaAs, InGaP/GaAs, and InGaAsP/InP under normal growth conditions. Extensive work has been done in various laboratories to achieve true layer-by-layer growth. Migration enhanced epitaxy (MEE) and atomic layer epitaxy or deposition (ALE, ALD) are two processes that were developed to achieve true layer-by-layer growth.2,3 In MEE atoms are given time to diffuse across the surface to the next available nucleation site through a cycle of source flux interruption and full surface reconstruction. In ALE or ALD the deposition is self-limiting to one monolayer per process cycle through a combination of flux exposure and purge cycles. These two techniques are extremely useful when thickness control is required at the atomic level, but are generally limited to very thin epilayers due to the long growth rate (1 monolayer/s). ALD, for instance, is now the technique of choice for high-k gate dielectric deposition on silicon.4 Nucleation Growth. In nucleation growth or the Wolmer-Weber growth mechanism, the system is thermodynamically unstable and growth proceeds in a three-dimensional (3-D) fashion in order to lower the total surface free energy. The three-dimensional islands increase in size as the deposition time increases until they touch and intergrow to form a continuous film. This is the case in highly mismatched materials or chemically incompatible systems. Heteroepitaxy of dissimilar materials is increasingly sought and techniques have been developed to remedy issues of lattice mismatch such as compliant substrates and interface template engineering to overcome chemical incompatibilities.5,6 Layer by Layer Followed by Nucleation Growth (S-K Growth Mode). The third growth mode or the Stranski-Krastanov (S-K) growth mode deals with intermediate cases such as low lattice mismatched materials. Initially, the system is stable for the first several monolayers and the wetting is Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.3

EPITAXY EPITAXY

15.3

complete. As the thickness increases, the total surface free energy increases, and a breakdown occurs followed by a three-dimensional growth. Pseudomorphic structures such as GaInAs/GaAs and SiGe/Si are a few examples where the S-K mode growth process is applied. 15.1.2 Growth Techniques and Equipment Varieties of methods are used to grow crystalline materials on crystalline substrates. In the semiconductor industry two major techniques are well established—chemical vapor deposition (CVD) and molecular beam epitaxy (MBE). Both techniques are of nonequilibrium character. Variants of these techniques—metal-organic chemical vapor deposition (MOCVD)—are associated with the epitaxy of compound semiconductors arsenides-, phosphides-, and nitrides-based materials, and chemical beam epitaxy (CBE) or gas source MBE (GSMBE) where the elemental sources are gaseous instead of solid sources. A combination of CVD and ultrahigh vacuum deposition system (UHV-CVD) is generating acceptance in some applications such as the SiGe/Si materials system.7 15.1.3 Molecular Beam Epitaxy In molecular beam epitaxy (MBE),8 epitaxy is induced by the flux of atoms/molecules onto a heated substrate in a high vacuum environment. The mean free path is large enough so that the impinging atomic or molecular fluxes are ballistic in nature and with no gas-phase interactions. The growth conditions are such that the sticking coefficient of low vapor pressure elements is near unity and high vapor pressure elements are used in excess to compensate for their lower sticking coefficient. Surface kinetics and diffusion suffice to achieve two-dimensional growth. As illustrated in Fig. 15.2 atomic or molecular species impinging the surface undergo the following steps: 1. 2. 3. 4. 5.

Migration on the surface Reevaporation Formation of isolated two-dimensional clusters Incorporation at step edges Migration along step edges and incorporation at kinks

The energetic of each step depends on the growth conditions (atomic/molecular species, fluxes, and growth temperature) and substrate surface reconstruction and orientation. The MBE system (Fig. 15.3) is based on the evaporation/sublimation of elemental sources such as Si, Ge , Al, Ga, In, As, and P in an ultrahigh vacuum (UHV) environment using effusion or Knudsen cells. In some instances, the e-beam evaporation method is used. These cells are the key elements of the MBE system; they must provide excellent flux stability and uniformity. This stability should be in the order of 1 percent during a working day and a daily variation of less than 5 percent. This means that the temperature control must be in the order of ±1 percent at 1000°C. Mechanical shutters are provided to switch the fluxes on and off. Since the fluxes from various cells come from different directions,

In coming flux 2 5

3 1 4

FIGURE 15.2

Kink

Surface 1 Step edge

Elemental steps in the MBE process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.4

EPITAXY 15.4

WAFER PROCESSING

LN2

Vacuum system

LN2 cryopanel BFM Mass spectrometer

RHEED screen

Substrate

RHEED gun

Effusion cells

FIGURE 15.3

Schematic drawing of a generic MBE system.

the distribution across the substrate is different leading to non-uniform thickness and composition. Substrate rotation is then used to ensure high thickness and composition uniformity. The MBE system is made up of stainless steel and consists of a loading chamber, a transfer and analytical/treatment chamber, and a growth chamber. The MBE system is maintained in UHV using a combination of diffusion pumps, turbo pumps, cryopumps, or ion pumps with auxiliary titanium sublimation pumps. Liquid nitrogen (LN2) cryopanels surround the interior of the growth chamber and effusion cell flanges to prevent reevaporation from the internal walls and maintain thermal isolation between them. The base pressure is in the 10−11 Torr range with H2 being the main residual gas. MBE systems have evolved in the last 10 years from small production and R&D tools to large systems with multiwafer capability and wafer sizes as large as 12 in. An example of this system is shown in Fig. 15.4. The main advantage of this technique is the ability to use high vacuum in situ characterization systems. The most valuable analysis tool available in MBE is reflection of high energy electron diffraction (RHEED). This technique employs a high-energy (20 keV) electron beam, directed on the substrate surface at a grazing incidence (1 to 3 degrees). The diffraction pattern is imaged on a fluorescent screen placed opposite the e-beam gun. Due to the small incidence angle, the diffraction pattern corresponds to the first atomic layers thus giving information on the surface reconstruction during epitaxy. A detailed discussion on the principles of electron diffraction is beyond the scope of this chapter. Qualitatively, a perfectly flat surface results in a streaky diffraction pattern indicative of two-dimensional growth, while a three-dimensional surface will result in a spotty pattern. Figure 15.5 shows an example of a RHEED pattern of single crystal strontium titanate (SrTiO3) thin epilayer film grown on silicon using MBE.6 RHEED is also useful to monitor native oxide desorption from the substrate before deposition and to calibrate the ratio of the elements to maintain the optimum growth process. The growth rates and alloy mole fractions are monitored during the growth process using the RHEED oscillations of the specular beam. To complement the ion gauges, a quadruple residual gas analyzer (RGA) is essential to monitor the integrity of the UHV. The RGA provides spectra of all residual gases present in the chamber, thus providing indications on possible leaks, system cleanness, insufficient bake, or inefficient pumping capability. An ion gauge placed behind the substrate manipulator is used as a beam flux monitor (BFM) for Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.5

EPITAXY EPITAXY

15.5

FIGURE 15.4 Picture of modern MBE production system from groupV semiconductors for III-V compound semiconductors (http://www. vgsemicon.com/products/v150.html).

daily atomic/molecular flux calibration and monitoring. This technique requires skilled technicians and operators. MBE production systems are expensive and require high maintenance, the downtime being larger than any other epitaxy system. However, the cost of ownership of MBE has been in steady decline in the last decade due to the improvement in operation, automated handling, and simplification of operation. Because of the superior quality of the AlGaAs/GaAs materials system, this technique has captured the GaAs-based electronics niche market. Moreover, because of low hazards involved in the MBE process, most GaAs epitaxy foundries have shifted their operations to MBE.

FIGURE 15.5 RHEED patterns of epitaxial SrTiO3 on a silicon substrate: (a) along the [110] azimuth and (b) along the [010] azimuth.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.6

EPITAXY 15.6

WAFER PROCESSING

15.1.4 Chemical Vapor Deposition Chemical vapor deposition occurs at or near atmospheric pressure depending on the application. The sources are gaseous and generally carried by high-purity hydrogen. The CVD growth process is much more complex and usually carried out at higher temperatures than MBE. It involves gas-phase and surface mechanisms. Only recently, a full understanding of these two processes through simulation and experimental works has emerged. For example, in Si epitaxy using trichlorosilane (SiHCl3 or TCS), up to eleven species of SixHyClz and nine reactions have been identified in the gas-phase reactions.9 A first-order approximation of the TCS and H2 reaction for silicon epitaxy is SiHCl3 + H2 → Si + 3HCl MOCVD is very similar to CVD in most aspects.10 The difference is in the precursors; metalorganic sources such as trimethyl gallium (TMG), indium (TMI), and aluminum (TMA) are used with hydride group five elements such as AsH3, PH3, and NH3. The growth conditions are slightly different from those of silicon. The growth rate can be described by the same equations (see next section) with multiple chemical species. However, for III-V compound semiconductor epitaxy an additional parameter, the V/III ratio (mole fraction ratio of group V elements over group III elements) must be taken into account. The V/III ratio needs to be high enough to compensate for the low decomposition rates of hydrides and to drive carbon and oxygen from group V lattice sites. For GaAs grown at a typical temperature of 700°C, a V/III of about 100 is sufficient, for GaN using ammonia for group V, a V/III of about 1000 at 1050°C is needed for high-quality materials. For GaAs, the simplified reaction using TMGa and AsH3 is given by Ga(CH3)3 + AsH3 → GaAs + 3CH4 CVD epitaxial systems consist of a gas manifold, a reaction chamber, and an exhaust system. The gas manifold is made of semiconductor-grade stainless steel tubing with pneumatic valves, mass flow controllers, and pressure regulators and transducers. The growth chamber is made of either quartz or stainless steel and consists of a susceptor and elements of heating (resistive, induction heating, and lamp heating) and finally the exhaust system. Two reactor designs are available in the market—vertical reactors in which the gas flow is perpendicular to the substrate surface and horizontal reactors in which the gas flow is parallel to the substrate. In addition, for batch or multiwafer processes, two types of susceptor designs exist—the barrel type and the pancake type. These reactors are suitable for small diameter substrates (less than 200 mm) standard complementary metal oxide semiconductors (CMOS) and for discrete device applications where the requirements in thickness and resistivity uniformity are not tight. Advanced CMOS epitaxy systems for 200 and 300 mm diameter wafers are of the horizontal type equipped with cassette load locks, a transfer chamber, and a cool-down chamber.

15.2 SILICON EPITAXY FOR ADVANCED CMOS TECHNOLOGY Silicon epitaxy of 200 and 300 mm is still the technique of choice for virtually defect-free epilayers with thickness and resistivity that can be tuned to customer specifications. Recently, Czochalski (CZ)prepared Si substrates combined with processes such as Ar/H2 anneal produced top silicon with characteristics similar to epilayers. These techniques are very cost effective and will compete with epitaxial layers in terms of device performances. However, epilayer characteristics such as the absence of oxygen and tight control of resistivity cannot be obtained so easily with CZ bulk crystal growth and annealing. 15.2.1 Silicon Epitaxy Process: An Overview In general, the CVD process includes:11 1. Transport of bulk gases to the growth region 2. Transport of reactants to the substrate surface through a “stagnant layer” or boundary layer Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.7

EPITAXY EPITAXY

15.7

This step can described by the following equation: dh1 = hg(Cg − Cs ) dt where hg is the mass transport factor of the gas in the chamber, and Cg and Cs are the concentration of the elements in the gas and on the surface. 3. Adsorption of reactants on the surface 4. Surface reactions, which include chemical decomposition, surface migration to nucleation sites, and incorporation in the lattice 5. Desorption of by-products and transport to the exhaust Steps 3 through 5 are described by the “over-simplified” equation dh2 = ks Cs dt with ks being the surface reaction rate. In steady state dh1 dh2 = =H dt dt

or

 k  Cs = Cg 1 + s   kg 

−1

The growth rate is then given by Gr =

k h Cg k h CT H = s g = s g M N ks + hg N ks + hg N

where N = number of atoms incorporated per unit volume CT = total number of molecules per unit volume in the gas M = mole fraction of the reaction species in the gas Figure 15.6 shows the boundary-layer model for silicon epitaxy using SiHCl3 (TCS) and H2. From the growth rate equation, we see that this simple model predicts a linear relationship of growth rate and the mole fraction M. Experimentally this relationship holds for low values of M (M < 0.1). We also distinguish two growth regimes:

Gas steam Inlet

Exhaust

SiHCl3 + H2 Diffusion Substrate

FIGURE 15.6.

HCl Boundary layer db

Boundary layer model schematic for Si epitaxy using SiHCl3.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.8

EPITAXY WAFER PROCESSING

1. ks << hg: The growth mode is reaction limited and since the reactions are thermally activated or of the Arrhenius type, the growth rate is given by Gr ≈

CT M ks N

with ks = k0 e − ( Ea /kT )

where Ea = reaction activation energy (Ea ≈ 1.6 for silicon) k = Boltzman constant T = temperature k0 = constant independent of temperature In this regime, the growth rate is highly temperature dependent and will increase until the mass flow limits the process. 2. hg < ks: The growth process is mass transport or gas-phase diffusion controlled and the growth rate equation is reduced to Gr ≈

Cg N

hg

with hg =

Dg db

where Dg is the diffusion coefficient through the boundary layer δb. In practice, the mass-transport-limited regime is preferred since it is practically independent of the growth temperature and primarily driven by a square root dependence on the bulk flow, thus allowing for high growth temperature for high-quality epilayers. Figure 15.7 shows the growth regime as a function of the deposition temperature. However, the mass transport regime depends strongly on the boundary layer thickness, which in turn depends on the reactor geometry leading to restrictions on the reactor chamber design. Horizontaltype reactors provide the ability to control the boundary layer structure by maintaining the lowest possible height-to-width aspect ratio of the reaction chamber. According to the boundary layer theory,11 δb is given by 1/2

 Dx  db =   Re 

with Re =

Dvp m

where D = reaction tube diameter x = distance along the reactor Re = Reynolds numbers

Growth rate (log scale)

15.8

ks = k0exp(−Ea/kT) hg = constant

Mass transfer Mixed controlled

Reaction controlled I/T

FIGURE 15.7 temperature.

Growth regimes as a function of deposition

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.9

EPITAXY EPITAXY

Laminar flow

15.9

Boundary layer db

0 FIGURE 15.8

x

Susceptor

Boundary layer structure.

The Reynolds number depends on the gas density (ρ), the gas velocity (ν) and gas viscosity (µ). The boundary layer structure is depicted in Fig. 15.8. This configuration will retain the flow in the laminar mode, that is, the gas flows in a regular, continuous, and nonturbulent mode. Yet, the boundary layer thickness is not constant as the gas flow across the heated wafer surface leading to a nonuniform deposition rate along the flow direction and in the transverse direction. Therefore, wafer rotation in the azimuthal direction along with a special injector design for flow distribution control is added to achieve high thickness uniformity. Thorough treatment of the horizontal reactor process using computational fluid dynamics can be found in Ref.12 and Ref. 13. Large diameter 200 and 300 mm epi-systems are single-wafer horizontal type reactors. Figure 15.9 shows a photograph of a commercial system for a 300-mm Si epitaxy and Fig. 15.10 a cross-section schematic of the growth chamber. As mentioned earlier, epitaxy provides the ability to control the film doping level and thus the electrical characteristics of the thin film (resistivity). Dopants such as boron for p-type and arsenic and phosphorous for n-type are introduced with reaction precursors in their hydride forms, usually heavily diluted in hydrogen to prevent decomposition:

FIGURE 15.9 A 300-mm Centura epitaxy system. (Courtesy of Applied Material Inc., http://www.amat.com/products/epi_centura.html.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.10

EPITAXY 15.10

WAFER PROCESSING

Pyrometer

Upper lamps

Upper dome

Susceptor Gas inlet Exhaust Wafer lift shaft

Lower dome

Lower IR lamps Pyrometer

FIGURE 15.10

Cross section of an Applied Material Centura deposition chamber.

Boron (B) Diborane (B2H6) Arsenic (As) Arsine (AsH3) Phosphorous (P) Phosphine (PH3) Dopant incorporation is a surface kinetic process and consequently extremely sensitive to deposition temperature. Due to the complexity of the gas-phase reaction, it is practically impossible to accurately model the dopant incorporation in the epilayer from the gas-phase ratio and growth conditions. However, empirical solutions for each set of deposition parameters are established. With current epitaxy systems, the repeatability of epilayer doping concentration is excellent for typical target levels and process settings.

15.2.2 Epitaxy Parametric Thickness. The film thickness is controlled by the overall flow of precursors and growth conditions. Under normal growth conditions and using TCS and H2 as precursors, a growth rate in the range of 3 to 4 µm/min can be achieved. Thickness uniformity of less that 1 percent is easily obtained at 3 mm edge exclusion for 200 and 300 mm wafers. Resistivity. Resistivity or doping level depends on the flow of dopant gas, the growth temperature, and the growth rate. The films can be grown intrinsic (no doping) or doped to a level as high as 1019 /cm3. The resistivity uniformity strongly depends on the flow pattern and on the temperature uniformity across the wafer. Most CMOS products call for a lightly doped epilayer on a heavily doped substrate. In this case, two effects need to be taken into account. First, solid state diffusion of substrate dopants into the epilayer tends to create a wide transition layer. This effect varies with the deposition temperature and epilayer thickness. Second, autodoping from the vapor phase. This mechanism results from substrate dopants evaporating from the backside and edge of the substrate into the vapor phase and incorporating into the epilayer. This effect also depends on the growth temperature and greatly affects resistivity uniformity across the wafer. A tight control on the process generally leads to resistivity uniformity in the range of 2 to 4 percent and a transition region less than 1 µm.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.11

EPITAXY EPITAXY

(a) FIGURE 15.11

(b)

15.11

(c)

SPV maps: (a) Fe concentration, (b) diffusion length, and (c) lifetime.

Surface Defects. Surface defects are one of the major concerns in epitaxy. These defects directly affect device operation and thus die yield. They are measured using automated laser surface scanning tools and usually referred to as laser light scattering (LLS) or light point defects (LPD). This inspection technique provides details on the density of these surface defects and allows for their identification and classification (size and shape). Each wafer measured generates a file containing the size and coordinate for each light-scattering event detected that can be converted into wafer map. Stacking all the maps of the production series will allow for information on the process evolution and for monitoring the reactor and incoming substrate characteristics. As the device geometry shrinks, the specifications on LPDs become rigid. According to the 2003 International Technology Roadmap for Semiconductors (ITRS),14 the 65-nm technology node predicted for 2005 will necessitate a maximum of 100 LPDs larger than 45 nm per wafer. This specification will require extreme care in the preparation and control of substrate and epi processes. Bulk Metals. Metals with high diffusivity and low solubility such as Fe, Cu, Ni, Cr, and Mo are detrimental to device operation. In the epitaxy process, system components and the environment should be free of metal contaminants. The typical level of metals is very low in single-wafer reactors (in the range of 109 to 1010 cm−3). Techniques such as surface photovoltage (SPV) and deep-level transient spectroscopy (DLTS) are used for metal detection. Typically, iron is periodically measured on test wafers in order to monitor the integrity of the reactor and gas delivery systems. Figure 15.11 shows typical SPV maps of a 300-mm epi-wafer under normal epi operation with iron concentration in the mid-109 cm3 a diffusion length of 360 µm and a lifetime of 700 µs. Flatness and Nanotopography. Flatness and nanotopography are critical in wafer parametric. They directly affect the focusing performance of photolithography tools during device processing. Flatness and nanotopography depend strongly on the substrate preparation (lapping and/or grinding and polishing). Epitaxy could affect these two elements if the thickness profile of the epilayer is not well optimized. In practice, the epilayer profile is tuned to avoid any degradation of the original flatness and nanotopography of incoming substrates. As an example, advanced CMOS specifications according the ITRS roadmap for flatness and nanotopography for 300 mm are shown in Table 15.1.

TABLE 15.1 2003 ITRS Roadmap for Flatness and Nanotopography Year of Production

2004

2005

2006

Wafer diameter (mm) Edge exclusion (mm) Site flatness (nm), SFQR 26 mm × 8 mm site size Nanotopography, p-v, 2 mm diameter area

300 2 ≤90 ≤23

300 2 ≤80 ≤20

300 2 ≤71 ≤18

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.12

EPITAXY 15.12

WAFER PROCESSING

However, customer requirements are often one to two generations ahead of the general trend and pressurize the epitaxial wafer producers to develop products at a greater pace than the customer requirements. R&D epitaxy laboratories have already produced epitaxial wafers with state-of-the-art flatness, nanotopography, and LPDs. Figure 15.12 shows an example of site flatness of a 300-mm epitaxial wafer where the maximum site is less than 35 nm, half of the expected specification for the 2006 design rule. The factors that directly influence wafer parametric discussed earlier are as follows: • Substrate: In general any imperfection on the substrate is copied and magnified by epitaxy. • Environment: It is critical to maintain the environment free of particulate and contamination sources for high-quality epitaxial layers. • Reactor: The reactor system can be a source of particulate and other types of contamination. It should be properly maintained and under tight control. • Facilities: Gas delivery, water and air-cooling and the exhaust systems including scrubbers play a major role in the proper operation of the epi-reactor. Failures in these parts could lead to not only poor quality epitaxial films but also to environmental and safety issues. Table. 15.2 shows a link matrix between parameters and the characteristics of epilayers. The quality of incoming substrates affects drastically the epilayer quality and may hinder the production reactor control resulting in unnecessary downtime and consequently higher operation cost. In the next section, we will focus mainly on the effect of incoming substrate imperfections on the surface defects. These imperfections are classified as follows: a. Crystal defects: Usually generated during bulk crystal growth. Slip lines, twin lines, and oxygen precipitates are the most common defects. They affect epitaxial layers through the generation of crystal originated hillocks or linear defects visible with laser inspection.

18.83 17.89 16.41 18.8 16.69 18.11 10.69 14.35 15.43 14.52

25.33 23.56 18.69 16.66 18.07 18.34 14.42 13.01 12.04 6.14 9.03 7.95 11.07 11.24 12.72 21.02 11.25 10.76 9.67 17.17 18.66 18.55

FIGURE 15.12

22.96 22.47 11.07 11.78 10.71 14.81 14.76 19.58 23.76 20.28 21.97 17.69 15.59 15.83 10.97 11.79 10.75 9.56 10.09 8.82 10.09 12.5 12.42 9.49 7.2 10.66 10.4 12.3 24.46 23.41

23.6 19.49 13.08 11.2 9.75 9.67 10.69 12.32 11.31 10.45 11.51 11.12 14.94 10.76 14.04 11.12 5.72 8.07 7.17 8.54 8.07 8.19 10.74 12.34 11.31 9.3 12.11 13.26 11.21 9.98 12.49 11.25 23.39 22.2

26.12 14.2 11.53 6.84 9.52 14.02 14.63 10.68 11.8 13.72 14.1 12.2 9.49 13.99 14.8 7.37 8.31 8.54 8.47 7.1 5.54 11.04 10.88 6.65 7.77 10.11 9.17 7.97 9.69 8.89 11.41 10.57 9.16 10.12 13.27 22.29

17.85 10.32 11.33 13.15 8.93 10.6 11.57 7.3 8.29 8.06 12.71 9 8.96 12.16 10.06 8.82 7.92 15.82 13.94 11.64 7.1 7.35 9.95 8.6 10.1 6.21 8.1 7.97 9.77 14 11.75 9.45 15.72 15.45 14.49 16.38

10.48 11.44 11.26 9.92 6.88 7.52 9.72 9.69 8.07 15.58 15.12 10.71 15.51 14.2 14.61 14.86 13.74 16.48 13.94 19.45 15.75 16.27 15.61 11.49 8.16 7.54 11.04 10.48 7.94 11.6 13.13 9.52 9.08 12.73 12.2 10.63

31.78 9.66 7.46 8.07 10.85 8.35 9.02 13.07 11.2 9.88 17.02 19.49 11.83 10.93 10.04 13.02 11.19 9.76 9.68 8.42 12.95 12.06 10.81 16.02 13.36 10.35 13.36 12.45 14.13 11.99 14.47 12.64 10.13 9.92 10.62 24.61

28.14 22.67 17.82 15.95 15.47 14.42 17.83 17.24 15.16 11.7 10.49 7.78 13.43 12.97 11.91 7.53 11.79 15.79 14.27 9.72 11.68 16.38 14.93 13.75 10.53 8.04 8.9 12.55 11.32 13.93 9.43 15.6 18.65 22.24

26.6 34.16 28.16 27.66 26.56 21.17 9.23 13.69 14.01 17.72 22.27 20.87 20.07 23.24 15.07 16.03 19.65 22.4 22.31 22.27 17.55 15.77 20.89 15.32 10.57 8.16 16.6 26.73 29.75 24.22

17.75 25.18 24.11 21.03 11.86 11.43 13.31 11.33 14.36 10.95 10.12 6.85 8.21 6.85 5.69 6.04 12.61 19.09 21.37 18.85 29.69 23.33

26 × 8 mm2 site flatness map of a 300-mm epi; 3 µm P− epi on a P++ substrate.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

24.77 22.56 28.5 31.18 23.03 29.44 33.99 36.69 28.74 30.84

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.13

EPITAXY EPITAXY

15.13

TABLE 15.2 A Link Matrix Between the Operation Parameters and the Characteristics of Epilayers Thickness

Resisitivity

Surface defects

Bulk metals

Flatness

Average

1 1 5 3

3 1 5 2

5 5 5 3

3 2 5 4

5 1 4 1

3.4 2 4.8 2.6

Substrate Environment Reactor Facilities 1 Low impact

2

3

4

5 High impact

b. Slip lines from thermal processes: Occasionally, epitaxy is performed after substrate thermal treatment. This treatment can leave residual stress on the substrate before epitaxy deposition. The additional stress during epi could generate slip lines. c. Surface events: The presence of “events” on the substrate and their effect on the epilayer quality depends strongly on their nature. For example, crystal originated particles (COPs) are easily eliminated through epi process optimization. Scratches and work damage on the other hand, can subsist after epi deposition, and could lead to Epi Staking Faults (ESF), hillocks, or pits. Environment-related particles on the substrate could lead to epi defects such as buried particles depending on their chemical nature and size.

15.3 MANUFACTURING The correct balance between quality and cost is a challenge in modern epitaxial production that needs to deliver high-volume state-of-the-art epitaxial wafers with very high yield at target cost. This in turn requires tight control of the epitaxy operation and a high level of quality management.

15.3.1 Control Procedure Figure 15.13 shows a typical process flow in advanced CMOS epitaxy. It is clear that quality is strongly related to the complex system of characterization and metrology. Advanced inspection systems are costly and add substantially to the overall fixed cost. The metrology allows for process development, process control, and troubleshooting and sorting. Statistical process control (SPC) is the most common approach used in process control. The SPC chart for each parameter is recorded and used to monitor process evolution and potential upsets that occur during the process. The sampling frequency depends on the inspection tool throughput and the nature of the parameter monitored. For example, LPDs are 100 percent sampled, whereas thickness and resistivity have a much lower sampling frequency. Figure 15.14 shows a typical example of LPDs SPC chart evolution against the reactor loadlock’s performance. In this example the load-lock, B shows a higher LPD count and thus was disengaged and placed in maintenance. The SPC chart in Fig. 15.15 clearly identifies the lot change as being the main contributor to the SPC chart deviation. In this case the epitaxy reactor was behaving according to its specifications. A thorough evaluation of the previous lot should reveal the root cause of the excursion points.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.14

EPITAXY 15.14

WAFER PROCESSING

Substrate cleaning

Particles inspection Maintenance

Process tuning

Epi reactor

Reactor monitoring; Metals, particles and intrinsic resistivity

Sampling

Process control: Thickness and resistivity monitoring

Sampling

Particles inspection Slip Nanotopography Flatness Post-epi cleaning Visual inspection

FIGURE 15.13

Particles inspection

Shipping

Process flow in advanced CMOS Si epitaxy.

B B B A B

A A

FIGURE 15.14

B

B

B

B

A

A

FIGURE 15.15

A

Example of SPC charts showing poor performance from load-lock B.

A

B

A

Lot change

B

B B

B

A

A A

A B

A

A

A

B

Example of an SPC chart showing the effect of lot change.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.15

EPITAXY EPITAXY

15.15

15.3.2 Control Procedure and Methodologies for Thickness and Resistivity Thickness and resistivity are also controlled; these two parameters on the other hand exhibit tight runto-run control (<1 percent) with uniformity in the range of 1 to 2 percent for thickness and run-to-run reproducibility in the 2 to 3 percent range for resistivity. Because of the high stability of the epitaxy process, the capabilities often exceed the 1.33 Cpk value allowing for a looser control plan. Current epitaxial reactors are stable for a large number of epitaxial wafers without any intervention for reactor tuning. In addition, integrated supervision systems in modern epitaxy reactors allow for monitoring and flagging any anomaly that occurs during the process, giving the operator the ability to abort the process and identify the source, thus minimizing the losses.

15.3.3 Environmental Needs for Epitaxial Growth As discussed previously, it is critical to maintain the incoming substrates under tight surface defects control. This is accomplished by maintaining an environment free of particulate and contamination around the epitaxy operation. State-of-the-art epitaxy facilities usually include a class-1 cleanrooms environment, and a mini-environment around certain inspection tools with additional features such as: 1. Through the wall mounting: All reactors are installed using the “through the wall” approach where the reactor service area (gray area) is separated from the loading area (class-1). 2. Front opening unified pod: In order to minimize the environment effect, wafers handling in the pre-epi and post-epi process sequence is usually carried out using automatic loading and unloading, completely eliminating the operator factor in manual load/unload processes that have shown to contribute to wafer contamination. This procedure though costly is very effective in producing a low particle count that will meet next generation products. Figure 15.16 shows a photograph of a FOUP cassette and opener.

15.4 SAFETY AND ENVIRONMENTAL HEALTH The main concern in the operation of CVD epitaxy systems is safety. A substantial part of the cost associated with setting up a CVD operation is in the toxic/flammable gas monitoring and alarms systems along with emergency trained personnel, usually as part of the facility department. In addition, since only a fraction of the inlet gases is consumed in deposition, the un-reacted gases along with the gas-phase reaction by-products are run through the exhaust system. Abatement systems are installed down stream of the CVD system to reduce the emission to the atmosphere. Epi-foundries must comply with OSHA (Occupational Safety and Health Act) codes, Toxic Gas Ordinance, Uniform Fire Code and Clean Air Act and city/state regulations.

15.5 FUTURE EPITAXY TRENDS It is obvious that epitaxy will evolve at the same pace as the electronic and photonic industry. Next generation devices will require tighter epilayers specifications and complex structures with abrupt transition layers and doping profiles. Heterogeneous epitaxy with low thermal budgets on patterned substrates will see more acceptance. Epitaxy systems also need to evolve in the same direction with new reactor designs to meet the flatness, nanotopography, and LPDs required for small geometry devices. In addition, in situ real-time process control of thickness, doping, and composition will be sought for potential elimination of post-epi inspection, thus increasing the throughput and reducing the overall cost.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.16

EPITAXY 15.16

WAFER PROCESSING

FIGURE 15.16 Automation.)

FOUP cassette and opener. (Courtesy of Brooks

15.6 CONCLUSIONS This chapter gives a bird-eye view of the fundamentals of epitaxy, the most common epitaxy processes and equipment and a condensed version of manufacturing environment and process control. These topics are vast and require the combined knowledge of various disciplines from material science to facility management to quality control and management. A team of experts in all these areas makes a successful epitaxy foundry.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.17

EPITAXY EPITAXY

15.17

REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

Royer, L., Bull. Soc. Franc. Miner. 51, 7 (1928). Horikoshi, Y., et al., Jpn. J. Appl. Phys. 27, 169 (1988). Tishler, M. A., and S. M. Bedair., Appl. Phys. Lett. 48, 1681 (1986). Gusev,. E. P., et al., Microlectron. Eng. 69, 2–4 (2003). Bourret, A., Appl. Surf. Sci. 164, 3 (2000). Ramdani, J., et al., Appl. Surf. Sci. 159/160, 127 (2000). Curie, M. T., et al., Appl. Phys. Lett. 72, 14 (1998). Foxon, C. T., Principles of Molecular Beam Epitaxy, Handbook of Crystal Growth, Vol. 3. Elsevier, Amsterdam, 1994, p. 157. Ho, P., et al., Proc. 194th Mtg. Electrochem. Soc. PV 98-23, 117 (1999). Stringfellow, G. B., Organomettalic Vapor-Phase Epitaxy. Theory and Practice. Academic Press, New York, 1989. Wolf, S., and R. N. Tauber, Silicon Processing for VLSI Era. Process Technology, Vol. 1., Lattice Press, Sunset Beach, CA, 1986. Hakuba, H., et al., J. Cryst. Growth, 207, 77 (1999). Kommu, S., et al., J. Electro Chem. Soc. 147, 1538 (2000). http://public.itrs.net/Files/2003ITRS/Home2003.htm.

FURTHER READING Baliga, B. J., Epitaxial Silicon Technology. Academic Press, New York, 1986. Crippa. D., D. L. Rode, and M. Masi, Silicon Epitaxy, Semiconductors and Semimetals, Vol. 72, Academic Press, New York, 2001. Parker. E. H. C., The Technology and Physics of Molecular Beam Epitaxy, Kluwer Academic Publishers, Dordrecht, 1985.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH15.qxd

04/04/2005

19:53

Page 15.18

EPITAXY

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 16

ECD FUNDAMENTALS Tom Ritzdorf John Klocke Semitool, Inc. Kalispell, Montana

16.1 INTRODUCTION In the early years of semiconductor processing, transistor gate delays determined chip speed. However, as devices shrank, the RC delay in the metallization (interconnect) levels became an important factor determining the chip speed. Copper, which has the second lowest resistivity of all metals, has now replaced aluminum in interconnect metallization for high-performance chips because of its low resistivity and improved electromigration lifetime. This required significant changes in the fabrication process such as switching to a damascene process flow and implementing electrolytic copper deposition and copper chemical mechanical polishing (CMP) in the semiconductor industry. Although electroplating had been used in the manufacturing of printed circuit boards for many years, it was a new process for chip manufacturing. This new application has spawned a wealth of research and development. The “art” of electroplating has now been refined to a fully characterized scientific process. Additionally, other electrochemical processes are now being considered as potential production solutions.

16.1.1 Basic Process Flow for Copper Damascene Processing Traditional aluminum interconnects were formed through a subtractive metallization process, with dry etching used to pattern blanket films of aluminum alloys. However, in dry etching, copper isn’t feasible because the temperature required to volatilize copper compounds is too high to be compatible with semiconductor processing, so a new metallization scheme (damascene process) has been implemented.1–3 In damascene processing, a dielectric material is deposited and patterned first and then metal is filled into the features. Finally, the excess material is removed, leaving an embedded metal line or via. In dual damascene processing, a lower via level and upper metal line layer are patterned in the dielectric material prior to metallization. Both layers can then be filled in a single metallization process, which reduces the overall number of process steps and manufacturing costs. The standard process flow for damascene copper metallization is shown in Fig. 16.1. After the dielectric layer has been patterned, barrier and seed layers are deposited using a physical vapor deposition (PVD) process. Typically the barrier layer is either Ta or a TaNx/Ta bilayer and the seed layer is pure copper. Electrochemical deposition (ECD) is then used to fill the features with copper. The wafers are annealed to stabilize the film and finally, the excess copper is removed with CMP.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

16.1

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.2

ECD FUNDAMENTALS 16.2

WAFER PROCESSING

A.

B.

C.

D.

FIGURE 16.1 Dual damascene process flow: (a) patterned dielectric, (b) PVD seed and barrier, (c) ECD fill, and (d ) post-CMP.

16.2 FUNDAMENTAL ECD TECHNOLOGY (HOW PLATING WORKS) 16.2.1 Basic Electrochemistry Electrochemical deposition is the reduction of ions from a solution to deposit metal on a surface (cathode). It occurs because ions, not electrons, carry current in a solution. Electrochemical reactions (oxidation and reduction) provide the mechanism for the transfer between electrons and ions as the charge carriers in an electrical circuit involving an ionic solution, or electrolyte. Electrochemical reactions can be driven either by an external power supply (electrolytic deposition) or a difference in chemical potential (electroless deposition). In the electrolytic deposition of copper with a soluble copper anode the main electrochemical reactions are Cathode (reduction) Cu2+ + 2e− → Cu0

(16.1a)

Anode (oxidation) Cu0 → Cu2+ + 2e−

(16.1b)

The driving force for electrochemical reactions is the electrochemical potential. The electrochemical potential (relative to the standard hydrogen electrode) at an electrode determines what reactions can occur at that electrode. There must be sufficient overpotential available to drive the reaction. The surface on which the reaction takes place (initially) also strongly influences the deposit nucleation and growth, which affects the mechanical and adhesive properties of the deposit.4 Any reaction that occurs at a less cathodic (anodic) potential can also take place in parallel with the main reduction (oxidation) reaction. The voltage of a particular metal deposition reaction can be determined by adjusting for the actual conditions using the Nernst equation and the standard reduction (or oxidation) potential for standard conditions.4,5 The current is related to the reaction rate through the chemical reactions, as in Eqs. (16.1a) and (16.2b). Essentially, the current is related to the number of atoms, ions, or molecules reduced (or oxidized) per unit time through Faraday’s second law.6 Q = It =

mzF M

or

dm IM = dt zF

where Q = charge passed I = electrical current m = mass of the deposit z = charge number of the ion F = Faraday’s constant M = molecular weight of the element deposited dm dt = mass rate of deposition

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

(16.2)

04/04/2005

19:54

Page 16.3

ECD FUNDAMENTALS ECD FUNDAMENTALS

16.3

Industrial processes are typically operated in current-control mode that is analogous to controlling the deposition rate. In such a case, the voltage increases to the point necessary to drive the chemical reaction(s) necessary to support the current in the system. The electrochemical reactions at the electrodes in an electrodeposition system consume reactants and create reaction products. This leads to the importance of mass transfer to carry these reactants and products to the surface of the electrode within the electrolyte. Typically, mass transfer effects are explained relative to the metal being deposited at the cathode. It is important to remember, however, that mass transfer is also critical for the other bath components and at the anode, as well as the cathode. In a typical ECD cell, the source of the metal being deposited is considered to be the electrolyte very near the electrode (cathode). This is in contrast to a vacuum deposition process such as sputtering, in which the mean free path is very large and the source of the deposited material is the counter-electrode, or target. The metal ions are consumed by the reduction reaction at the cathode (Eq. (16.1a)) and the concentration of these ions is reduced in a region very near the electrode surface. As the reaction proceeds, this leads to the formation of a region of reduced concentration called the diffusion boundary layer. The concentration gradient in this diffusion boundary layer is the driving force for the transport of the ionic reactant to the cathode surface. The balance of the diffusion rate to the reaction rate is a critical parameter in electrolytic systems. If the current is increased to the point at which every metal ion is consumed as soon as it reaches the cathode surface, the diffusion rate across the diffusion boundary layer is at a maximum because the concentration gradient cannot be increased. This is called the limiting current density (Fig. 16.2). If the voltage is increased slightly, the current will typically not change, as a higher reaction rate cannot be supported. If the current is driven higher, the voltage will increase to the point of driving another reaction in the system, at which point the current will again increase. In an aqueous system, this can happen until the reduction potential of H+ or water is reached at the cathode, or the oxidation potential of OH− or water is reached at the anode. The water in the system will essentially provide an infinite source of the reactants for these reactions, so the potential will never increase beyond these values. Therefore, metals with reduction potentials cathodic to the reduction of water (such as aluminum and titanium) cannot be electrochemically deposited from aqueous solutions. If a deposition reaction is operated near the limiting current density, the deposit will tend to be nodular or dendritic. Typically, industrial processes are operated at 30 to 50 percent of the limiting

Draft Dendritic/powdery

iL Current density

Geng(SMH)_CH16.qxd

Nodular Mixed control (activation and mass transport)

Smooth and compact

Lamellar Potential FIGURE 16.2 Generic polarization curve for metal deposition showing regions of different deposit morphology (adapted from Ref. 4).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.4

ECD FUNDAMENTALS 16.4

WAFER PROCESSING

current density (Fig. 16.2) in order to produce smooth deposits with consistent morphology. Limiting current density is a reasonable measure of the relative deposition speed capability of different systems. The factors that increase the diffusion rate of metal ions to the cathode surface have the most impact on increasing the limiting current density of an ECD system. These factors are agitation (such as flow and spin speed), temperature, and metal ion concentration. Superconformal deposition is the deposition property that enabled electrolytic deposition processes to be utilized for copper deposition in a damascene metallization scheme.7–10 This is the ability of the process to provide a higher deposition rate, or coverage, at the bottom of an etched feature than in the field region on top. This property, which results from the combination of suppressors and accelerators in the bath,11,12 enables the process to be used to fill high-aspect-ratio features with subconformal PVD seed layers. Extensive references are available on the two theories that explain this behavior—consumption of diffusion-limited suppressing agents and curvature-enhanced catalytic enhancement.7–9,13,14 Copper can be electrolytically deposited from several types of solutions—acidic copper sulfate, methane sulfonic acid, basic cyanide complexed chemistries, pyrophosphate baths, and many other specialized chemistries; some of which contain complexing agents. Most copper deposition for semiconductor processing, however, is done using relatively simple acidic copper sulfate chemistry. These baths typically consist of three inorganic components—sulfuric acid, copper sulfate, and hydrochloric acid—with some organic compounds to modify the deposition and film properties. These organic additives are usually named after their functions, with names such as suppressors, accelerators, and levelers. Copper sulfate provides the source of copper ions that are electrolytically deposited during the plating operation. The higher the concentration of copper ions in solution, the better the featurefilling performance of the chemistry. Sulfuric acid is used to maintain an acid environment to keep copper in solution and to provide the ionic conductivity of the solution. The H+ ions, or protons, are the preferred charge carriers in the solution and provide high solution conductivity. The pH of the solution also affects the activity of the organic additives. The concentrations of copper sulfate and sulfuric acid are not completely independent since the common ion effect limits the total solution concentration of sulfate ion.15 This sets the upper limit on the total concentration of these two chemicals. Hydrochloric acid is added to these solutions to assist the effectiveness of some organic additives and to aid in anode erosion.13,16 Table 16.1 lists examples of acid copper plating baths with varying characteristics. The organic additives most commonly used in acid copper sulfate plating baths consist of suppressors, accelerators, and levelers. Suppressors typically consist of polymers or copolymers of glycol ether compounds.16,17 These organic materials tend to adsorb on the copper surface and inhibit deposition, although they usually require the presence of a small amount of chloride ion to be effective. They are called suppressors because of their effect on reducing the deposition rate (current density) at a given deposition potential. They also have the effect of increasing the overpotential required for maintaining a specific deposition rate. Conversely, there are classes of materials which, when added to a bath containing suppressors, increase the deposition rate or decrease the overpotential to maintain a specific deposition rate. These accelerators are typically compounds such as 3-mercapto1-propanesulfonate (MPS) and bis (3-sulfopropyl) disulfide (SPS), or similar thiol compounds.16,17 These materials usually provide a catalytic effect and remain adsorbed at the deposition surface as the deposition proceeds. The geometric concentration of these materials on the surface within cavities

TABLE 16.1 Copper Plating Bath Compositions

CuSO4 H2SO4 HCl Organic additives

High throwing power

High deposition rate

60 g/L 170 g/L 50 ppm As recommended

250 g/L 60 g/L 50 ppm As recommended

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.5

ECD FUNDAMENTALS ECD FUNDAMENTALS

16.5

is one mechanism thought to promote superconformal deposition.9 The third type of additive that is commonly added to these baths is called a leveler. Levelers are polar (negatively charged) molecules that perform a suppressing function. They are typically high-molecular-weight compounds with sulfonic or sulfamic acid or other nitrogen-containing functional groups.16 Their function is to attach to the areas of the surface with higher current densities and decrease the local deposition rate. They also tend to reduce the deposition rate over small features. The concentrations of all these organic additives are typically very low, ranging from ppb to 0.1 percent of the bath composition. The low concentrations make these compounds very susceptible to changes in the diffusion boundary conditions, as noted earlier. Other organic components are sometimes added to copper plating baths, including surfactants, ductility modifying agents, and bactericides. Other parameters that affect the electrodeposition process include temperature, flow rate, agitation, and substrate motion. Temperature can increase the diffusion rates of the bath components and change the adsorption characteristics and usage rates of some of the organic additives. The flow rate, agitation, and substrate motion parameters typically impact the process by changing the hydrodynamic boundary layer thickness (which sets the diffusion boundary layer thickness) and the distribution of chemical constituents across the surface. It is sometimes difficult to predict all the changes associated with modifying the process conditions, but the results can usually be explained by examining the basics noted earlier. It is also important to pay attention to the anode in electrolytic deposition systems. There are two classes of anodes available for copper deposition—consumable (copper) and inert (nonconsumable, dimensionally stable, noble). The main differences between the types of anodes are in the anodic reactions they support. Consumable anodes promote copper dissolution at the anode (Eq. (16.1b)), while inert anodes usually involve the anodic generation of oxygen gas. Oxygen gas can lead to film defects if not managed properly.18 Most industrial systems utilize consumable anodes for copper deposition on semiconductor wafers. In this case, the anode reaction is the reverse of the cathode reaction, leading to a stable copper concentration. Any contaminants in the anode will also be dissolved and will lead to chemical or particulate contamination of the chemistry. There is a large amount of information published on ECD that is beyond the scope of this short chapter. For instance, alloys can be deposited if the reduction potentials of the metals involved are close enough to each other. In some cases, the reduction potential must be adjusted by utilizing complexing agents or other chemistry changes that affect the deposition overpotential. Similar techniques can be used to affect the ability to deposit metals on certain surfaces. In addition, there are nonaqueous systems, such as solvents or molten salts, available for the deposition of certain materials.19,20

16.3 BENEFITS OF COPPER DAMASCENE ECD PROCESSING Electrochemical deposition of copper provides all the material property benefits of copper interconnections at a low cost. Copper is second only to silver in elemental resistivity at 1.67 µΩ-cm and provides high electromigration resistance when compared to aluminum alloys. Electroplating is well known as a purification method for copper (electrorefining). This same effect can be seen in ECD films. Impurity levels in the final deposit typically range from 0 to 50 ppm (see Fig. 16.3). However, sulfur concentrations tend to be an order of magnitude higher in concentration due to organic additives incorporated into the deposit. The electrical resistivity of ECD copper films is approximately 2.1 µΩ-cm, as deposited, because of the small grain size.21 After a low-temperature anneal (200 to 400°C), the increased grain size reduces the resistivity to about 1.8 µΩ-cm. This is far below the resistivity of the aluminum alloys that are used to provide reasonable electromigration resistance (approximately 4 µΩ-cm). Copper inherently provides an electromigration advantage over aluminum. Additionally, ECD copper films are predominantly (111) in crystal orientation.11 Copper interconnects typically offer an order of magnitude increase in electromigration lifetime over traditional aluminum copper alloys.22 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.6

ECD FUNDAMENTALS 16.6

WAFER PROCESSING

Evolution of contaminants concentrations in the copper film versus bath aging 25

Concentration (ppm)

20

O F

15

S (×10 ppm) Cl

10

C N

5

0 0 FIGURE 16.3

20 40 60 80 Number of wafers per liter of bath

100

Contaminants in electroplated copper films.

16.4 INTEGRATION OF COPPER ECD INTO THE PRODUCTION LINE Damascene features must be completely filled with copper to achieve high production yields with good reliability. This depends on the integration of upstream and downstream processes, from dielectric etch to post-CMP passivation. The seed layer profile, in particular, has a very strong influence on the fill capability of copper ECD processes. The subsequent anneal process is required to stabilize grain size for CMP and minimize line resistance. However, improper annealing can result in either incomplete grain growth or the formation of voids, even after successful feature fill. The uniformity of the ECD copper film also affects the ability of the CMP process to remove excess copper without leaving either residual metals or creating excess dishing and erosion due to overpolishing. The PVD copper seed layer provides a current path into the features and an active surface for ECD deposition. Therefore, having a continuous layer is a critical factor affecting gap fill. Bottom voids are likely to occur if the seed layer is too thin or discontinuous at the bottom of the feature (see Fig. 16.4) and seam voids are likely to occur if the seed layer is too thick or substantially overhangs at the top of the feature. Of course, if the feature shape itself is reentrant this will aggravate the issue. PVD processes are also susceptible to center-to-edge differences due to their line-of-sight nature. At the edge of the wafer, the centermost sidewall is sometimes shadowed and receives insufficient seed layer coverage. This leads to side-wall voids (see Fig. 16.5). In general, the ECD process can also be tuned to be either less sensitive to bottom voids or seam voids. By optimizing the PVD seed and ECD copper processes together it is possible to fill features below 100 nm in size.23,24

FIGURE 16.4 FIB cross-sectional SEM images showing the effect on fill of seed layer coverage from insufficient, to optimal, and finally overhanging.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.7

ECD FUNDAMENTALS ECD FUNDAMENTALS

16.7

The copper ECD process typically deposits films with very small grains (0.03 µm to 0.1 µm).25 After processing, this film undergoes self-annealing, in which grain sizes grow significantly.25–33 The resistivity of an electrolytically deposited blanket copper film will fall from 2.1 to about 1.8 µΩ-cm.34 This process can take from several days to months to occur, depending on the deposition conditions and film thickness. In the confinement of submicron features, FIGURE 16.5 Side-wall voids self-annealing occurs much more slowly. Grain size affects the resulting from PVD shadowing at resistivity of copper and the removal rate of CMP. Therefore, the wafer edge. wafers must be annealed after plating to provide minimal line resistance and a stable film for CMP. Smaller lines require more aggressive annealing conditions to achieve complete grain growth. Small grains can be seen in the bottom of 0.18 µm trenches after a 3 min anneal at 250°C (Fig. 16.6). Complete grain growth is observed in the same features after 30 s at 400°C. If adhesion between the barrier and the seed layer is poor, hightemperature annealing can cause copper to delaminate (de wet, agglomerate), leaving voids at the bottom of features.35,36 The annealing process must be integrated in conjunction with the barrier and the seed deposition process to prevent void formation. Uniformity of ECD copper films must be examined both locally (feature scale) and globally (wafer scale). Global uniformity of the film across the wafer is critical to ensure that all portions of the wafer are cleared of the excess copper material during the CMP process at the same time. If a portion of the wafer clears before the rest, the excessive polishing in that area can lead to dishing and erosion problems. For optimum performance, the final profile of the deposited film should match the removal rate profile of the CMP system. The bottom-up fill process leads to excess plating above features.13 In extreme cases, the bump can be more than twice the thickness of blanket areas. This is very difficult to planarize and leads to residual copper after CMP (see Fig. 16.7). Bump formation can be significantly reduced with leveler chemistries or pulse plating.

16.5 ADDITIONAL CONSIDERATIONS FOR COPPER ECD PROCESSING In addition to process integration, there are several other factors that must be considered when using copper in chip production. The plating chemistry must be maintained within specification at all times to ensure consistent yield. Chemical waste must be classified and treated appropriately. In addition to this, measures must be taken to ensure that copper contamination does not affect other areas of the fabrication facility.

FIGURE 16.6 400°C.

FIB images of 0.18 trenches (cut lengthwise) that have been annealed at 250°C and

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.8

ECD FUNDAMENTALS 16.8

WAFER PROCESSING

FIGURE 16.7 Bump formation over dense features and the resulting copper residual versus planar deposition.

The plating bath composition used in copper ECD processes is critical to ensure complete fill, low surface roughness, and good local planarity. However, the organic additives decompose over time and with plating. In addition to this, liquid loss from evaporation, drag out, and sampling must be compensated for. Therefore, it is necessary to periodically analyze and replenish the plating bath. Inorganic components such as sulfuric acid, copper, and chlorides are typically measured with titration techniques. The copper and acid concentrations can also be measured with photometry. The organic additives are typically measured with electroanalytical techniques such as pulsed cyclic galvanostatic analysis (PCGA) and cyclic voltametric stripping (CVS) or with high purity liquid chromotography (HPLC). All these methods can be integrated together in automated systems that utilize feed-forward dosing, based on time and wafers plated, and feedback dosing, based on analytical results.18,37 The components of copper plating baths are generally nonvolatile and evaporative losses can be compensated for by periodically adding deionized (DI) water to the bath. With the introduction of ECD processing comes copper-contaminated acid waste—a waste stream not traditionally found in semiconductor fabrication. Most copper production facilities have separate waste streams for copper-containing waste. To minimize the cost of treatment, the volume of copper-containing waste is minimized by extending the usable life of plating baths and minimizing the required liquid volume needed for subsequent rinsing and cleaning steps. Generally, the amount of copper-containing waste generated by the deposition process is significantly lower than that generated by the CMP process, and they are treated together. Copper contamination is also a concern within the processing facility. Copper is a mobile ion capable of poisoning semiconductor devices. At the interconnect levels, copper is contained within the barrier and capping layers. To prevent cross contamination at the device level, processing facilities utilize strict protocols. Persons working in and around copper processing areas are prohibited from entering other areas, and individuals working with copper ECD and CMP are frequently required to wear specific cleanroom gowns for identification. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.9

ECD FUNDAMENTALS ECD FUNDAMENTALS

16.9

16.6 FUTURE TRENDS With each technology node, interconnect size decreases and the current density in interconnects increases. (According to the International Technology Roadmap for Semiconductors, the current density will approximately double from the 130-nm to the 45-nm node technology.38) This translates to higher line resistance and increased susceptibility to electromigration. Semiconductor companies are actively pursuing techniques to manage both of these factors. As feature sizes become smaller, the percentage of the interconnect filled by the barrier layer becomes more significant. In addition to this, the size of the interconnect feature is approaching the electron mean-free path in copper, causing the resistivity to increase due to surface scattering of electrons. To minimize line resistance, barrier layers must become thinner, smoother, and more conductive, while continuing to prevent diffusion of copper atoms into the dielectric material. The minimal barrier thickness is determined by the conformality of the deposit. For this reason, atomic layer deposition (ALD)—a derivative of CVD technology—looks very promising. ALD processes deposit barrier materials with nearly 100 percent conformality. Chip manufacturers are also investigating higher-conductivity barrier materials including ruthenium and tungsten. Current process technology utilizes either a blanket layer of silicon nitride or silicon carbide (or a combination) to cap the copper lines after CMP. This insulating layer provides sufficient protection against copper diffusion and serves as an etch stop. However, electromigration occurs primarily along this interface, reducing the device lifetime.39 This layer also has a relatively high dielectric constant, which increases the effective dielectric constant of the dielectric stack. To achieve effective dielectric constants significantly below 3.0, the blanket-capping layer must be either changed or eliminated.40 Metal capping layers reduce the mobility of copper along the top interface of interconnect lines. This extends the electromigration lifetime by more than ten-fold.41 To prevent shorts or leakage, the layer must be selectively deposited only on top of the copper. This selectivity can be achieved either through electroless deposition or CVD. Electroless deposition of CoWP or CoWB is a leading candidate for this process. The material can be selectively deposited in very thin layers to minimize the change in via resistance while increasing electromigration lifetimes (see Fig. 16.8).

16.7 SUMMARY Semiconductor manufacturers continually strive to make smaller, faster chips by minimizing line resistance, feature sizes, and dielectric constants. As features shrink, the local current densities increase, creating issues with electromigration. Copper interconnects provide lower resistance and improved electromigration lifetimes relative to aluminum. To implement copper in production, manufacturers have switched to a damascene processing sequence that uses copper electroplating to fill

CoWP Cu Cu

FIGURE 16.8 ping layer.

TEM image of electroless selective CoWP cap-

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.10

ECD FUNDAMENTALS 16.10

WAFER PROCESSING

submicron features. ECD prevents void formation in the deposition process by combining organic additives and electrolytic deposition parameters to produce high-yielding, reliable interconnects. To maintain consistent performance, the plating bath is periodically analyzed and replenished with automated chemical management systems. Semiconductor manufacturers are now researching methods to further reduce line resistance as features continue to shrink. These include switching to thinner and more conductive ALD barrier materials. Electromigration lifetimes and dielectric constants may be further improved with selectively deposited electroless capping layers.

REFERENCES 1. Murarka, S., I. Verner, and R. Gutmann, Copper—Fundamental Mechanisms for Microelectronic Applications. John Wiley & Sons, New York, 2000. 2. Edelstein, D., et al., “Full Copper Wiring in a Sub-0.25 µm CMOS ULSI Technology,” Proc. IEEE IEDM, pp. 773–776, 1997. 3. Andricacos, P. C., et al., “Damascene Copper Electroplating for Chip Interconnections,” IBM J. Res. Develop., Vol. 42, No. 5, pp. 567–574, 1998. 4. Paunovic, M., and M. Schlesinger, Fundamentals of Electrochemical Deposition. John Wiley & Sons, New York, 126–127, 1998, pp. 55, 91. 5. Lyons, E. H., in F. A. Lowenheim (ed.), Modern Electroplating, 3rd ed. Wiley Interscience, New York, 1974, p. 7. 6. Weast, E. H. (ed.), CRC Handbook of Chemistry and Physics, 58th ed. CRC Press, West Palm Beach, 1978, p. F104. 7. Deligianni, H., et al., in P. C. Andricacos, P. C. Searson, C. Reidsema-Simpson, P. Allongue, J. L. Stickney, and G. M. Oleszek (eds.), Electrochemical Processing in ULSI Fabrication and Semiconductor/Metal Deposition II, ECS, Pennington, NJ, 1999, pp. 52–60. 8. Takahashi, K., and M. Gross, “Transport Phenomena That Control Electroplated Copper Filling of Submicron Vias and Trenches,” J. ECS, Vol. 146, No. 12, pp. 4499–4503, 1999. 9. Moffat, T. P., et al., “Superconformal Electrodeposition of Copper,” ECS Electrochem. Solid-State Lett., Vol. 4, No. 4, pp. C26–C29, 2001. 10. Andricacos, P. C., et al., in P. C. Andricacos, J. O. Dukovic, G. S. Mathad, G. M. Oleszek, H. S. Rathore, and C. R. Simpson (eds.), Electrochemical Processing in ULSI Fabrication I and Interconnnect and Contact Metallization: Materials, Processes, and Reliability. ECS, Pennington, NJ, 1999, pp. 48–58. 11. Gross, M. E., et al., “The Role of Additives in Electroplating of Void-Free Cu in Sub-micron Damascene Features,” AMC 1998, p. 51, 1999. 12. Vereecken, P., et al., “Effect of Differential Additive Concentrations in Damascene Copper Electroplating,” Meeting Abstracts of the 203rd Meeting of the Electrochemical Society, Abstract, Vol. 606, 2003. 13. Ritzdorf, T., D. Fulton, and L. Chen, “Pattern-Dependent Surface Profile Evolution of Electrochemically Deposited Copper,” AMC 1999, p. 101, 2000. 14. Andricacos, P. C., et al., “Damascene Copper Electroplating for Chip Interconnections,” IBM J. Res. Develop., Vol. 42, No. 5, pp. 567–574, 1998. 15. Murmann, R. K., Inorganic Complex Compounds. Reinhold, New York, 1964. 16. Safranek, W. H., in F. A. Lowenheim (ed.), Acid Copper, 4th ed. Wiley Interscience, New York, 1974, pp. 66–71. 17. Frank, A., and A. J. Bard, “The Decomposition of the Sulfonate Additive Sulfopropyl Sulfonate in Acid Copper Electroplating Chemistries,” J. ECS, Vol. 150, No. 4, pp. C244–C250, 2003. 18. Ritzdorf, T., and D. Fulton, “Electrochemical Deposition Equipment,” in M. Datta, T. Osaka, and J. W. Schultze (eds.), New Trends in Electrochemical Technology, Microelectronic Packaging, Vol. 3. Francis & Taylor, London, in press. 19. Jordan, M., in F. A. Lowenheim (ed.), Electrodeposition of Lead and Lead Alloys, 4th ed. Wiley Interscience, New York, 1974, pp. 380–381. 20. Mentone, P., “Filling Vias With Electroplated Aluminum,” Peaks in Plating, Semitool, 2004.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.11

ECD FUNDAMENTALS ECD FUNDAMENTALS

16.11

21. Ritzdorf, T., et al., “Self-Annealing of Electrochemically Deposited Copper Films in Advanced Interconnect Applications,” Proceedings of the International Interconnect Technology Conference, Burlingame, CA, pp. 106–108, 1998. 22. Tsai, M. H., et al., “Reliability of Dual Damascene Cu Metallization,” Proceedings of the International Interconnect Technology Conference, p. 214, 2000. 23. Steinlesberger, G., et al., “Microstructure of Cu Damascene Nano-Interconnects,” Advanced Metallization Conference, p. 345, 2002. 24. Wu, W., et al., “Resistivity of Ultra-narrow Cu Interconnects Fabricated with Electron Beam Lithography,” Advanced Metallization Conference, p. 345, 2002. 25. Brongersma, S. H., et al., “Non-Correlated Behavior of Sheet Resistance and Stress During Self-Annealing of Electroplated Copper,” Proceedings of the International Interconnect Technology Conference, p. 290, 1999. 26. Brongersma, S. H., et al., “A Grain Size Limitation Inherent to Electroplated Copper Films,” Proceedings of the International Interconnect Technology Conference, p. 31, 2000. 27. Hogan, B. M., “Microstructural Stability of Copper Electroplate,” AESF Conference—SUR/FIN ’84. 28. Stoychev, D. S., and M. S. Aroyo, “The Influence of Pulse Frequency on the Hardness of Bright Copper Electrodeposits,” Plating and Surface Finishing, pp. 26–28, 1997. 29. Tomov, I. V., D. S. Stoychev, and I. B. Vitanova, “Recovery and Recrystallization of Electrodeposited Bright Copper Coatings at Room Temperature. II. X-ray Investigation of Primary Recrystallization,” J. Appl. Electrochem., Vol. 15, pp. 887–894, 1985. 30. Harper, J. M. E., et al., in D. Edelstein, T. Kikkawa, M. Ozturk, K. Tu, and E. J. Weitzman (eds.), MRS Symposium Proceedings: Advanced Interconnects and Contacts, San Francisco, CA, Vol. 564, pp. 387–392, 1999. 31. Ritzdorf, T., et al., “Comparative Investigation of Plating Conditions on Self-Annealing of Electrochemically Deposited Copper Films,” Proceedings of the International Interconnect Technology Conference, p. 287, 1999. 32. Stoychev, D. S., et al., “Influence of the Inclusions in Thick Copper Coatings on their Physico-Mechanical Properties,” Polygrafia Russ., Vol. 9, p. 37, 1984. 33. Stoychev, D. S., I. V. Tomov, and I. B. Vitanova, “Recovery and Recrystallization of Electrodeposited Bright Copper Coatings at Room Temperature. I. Microhardness in Relation to Coating Structure,” J. Appl. Electrochem., Vol. 15, No. 6, pp. 879–886, 1985. 34. Jiang, Q., R. Mikkola, and B. Carpenter, “Room Temperature Film Property Changes in Electro-Deposited Cu Thin Films,” AMC 1998, p. 177, 1999. 35. Maitani, T., et al., “Mechanism of Defect Formation in the Micro Cu Wiring,” Peaks in Plating, Semitool, 2004. 36. Nogami, T., et al., “Characterization of the Cu/Barrier Metal Interface for Copper Interconnects,” Proceedings of the International Interconnect Technology Conference, pp. 298–300, 1998. 37. Ritzdorf et al., “Design and Modeling of Equipment Used in Electrochemical Processes for Microelectronics,” IBM J. R&D, submitted for publication. 38. Int’l Tech. Roadmap for Semiconductors, 2003. Available at: http://public.itrs.net/. 39. Zschech et al., “Reliability of Copper Inlaid Structures—Geometry and Microstructure Effects,” AMC, pp. 305–311, 2002. 40. Kastenmeier, B., K. Pfeifer, and A. Knorr, “Porous Low-k Materials and Effective k,” Semicond. Int., p. 87, 2004. 41. Bill, L., “Electroless CoWP Boosts Copper Reliability, Device Performance,” Semicond. Int., pp. 95–100, 2004.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH16.qxd

04/04/2005

19:54

Page 16.12

ECD FUNDAMENTALS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 17

CHEMICAL MECHANICAL POLISHING Timothy S. Dyer Carpenter Advanced Ceramics Auburn, California

17.1 INTRODUCTION TO CMP Chemical mechanical polishing or planarization (CMP) has enabled the production of advanced semiconductor devices by producing a globally planar wafer surface. The optical depth-of-focus issues of photolithography drives the near-atomic-level flatness achieved by CMP, which is a highly sophisticated process. Photolithography requires a flat surface to image dense, multilayer integrated circuits. In general, the smaller the device features, the flatter the substrate must be. At the current device technology node, global wafer planarization and CMP are necessary for building reliable next-generation multilevel interconnects. 17.1.1 Advantages of CMP CMP offers many advantages over standard reactive ion etching (RIE) processes. For one, RIE processes cannot readily etch copper. CMP does a very good job removing copper for the semiconductor wafer surface while at the same time producing a surface that is both very smooth and flat. CMP is mainly used for silicon dioxide, polysilicon, copper, low-k dielectrics, and tungsten removal and planarization. CMP is an elegant process and can be completed in a semiclean environment in the wafer fab. CMP tools tend to be massive and large. Though CMP processes require chemicals, they do not require the use of dangerous pyrophoric or highly toxic gases like most RIE or chemical vapor deposition (CVD) systems. 17.1.2 The Science of CMP CMP is a straightforward process to understand. A thin film on a wafer surface is abraded by a simultaneously using a chemically active slurry, moving polishing pad, and an applied polishing down force (See Fig. 17.1). Fundamentally, its roots lie in the science of friction and wear called tribology. In brief, the science of tribology characterizes both friction and wear of substances. Some folks believe that high friction during polishing suggest high-stock material removal rates, however, this is generally not true. Polishing friction is system related and therefore is a unique behavior of the materials, surfaces, linear velocity, and chemistry involved in the polishing process. Material removal rates are generally proportional to the work done to the film being polished.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

17.1

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.2

CHEMICAL MECHANICAL POLISHING 17.2

WAFER PROCESSING

Slurry supply Carrier pad Slurry

Chuck

Polishing pad

Wafer

Carrier

FIGURE 17.1

Polishing table

The basic CMP process.

17.1.3 Preston’s Law For the CMP process, this relationship is characterized by Preston’s equation† that linearly relates film removal rates to polishing velocity and down force. R = K*PV where R = material removal rate K = Preston’s coefficient P = applied pressure V = linear velocity For a true prestonian system, the exponents M and N are equal to one. Preston’s equation is a simple tool for characterizing the wafer/slurry/polishing pad interaction and is a fairly good approximation of relatively mechanical processes such as shallow trench isolation (STI) and interlevel dielectric (ILD) CMP. Some CMP processes like Cu and STI do not necessarily follow Preston’s law. In general, it is safe to estimate material removal rates by Preston’s law most of the time. However, if the abrasive chemistry or abraded materials change during the process, the system will not follow Preston’s law. 17.1.4 Other CMP Terminology Along with material removal, the objective of CMP is to flatten the wafer surface both globally (within the wafer) and locally (within a die). Planarization efficiency is defined by the amount of material removed in comparison to the step height reduction of a nonplanar feature on a wafer. In general, larger features require more material removal to planarize. Smaller features can actually planarize too quickly, resulting in feature erosion. In metal CMP processes such as tungsten and copper, overpolishing can also manifest itself in feature dishing. Dishing occurs when a large metallic feature is over polished in the center, resulting in a dish-shaped profile when viewed from the film cross section. Lastly, control in CMP requires stopping the polishing process at the right time. Much like RIE systems, CMP processes require good selectivity and process endpoint control. The best CMP processes produce a planar surface with minimal material removal. This is the most difficult part of CMP process optimization. In general, processes that generate globally uniform polishing uniformity yield poor local planarization. This is one of the true engineering tradeoffs of the CMP process.

†

Preston F., Journal of the Society of Glass Technology 11, no. 214 (1927).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.3

CHEMICAL MECHANICAL POLISHING CHEMICAL MECHANICAL POLISHING

17.3

17.2 MOST COMMON CMP PROCESSES There are many polishing systems in CMP. For illustrative purposes, we will discuss two different but very common polishing systems. These systems are silicon dioxide (Oxide) CMP and tungsten CMP. Additional common CMP process will also be briefly discussed. 17.2.1 Oxide/Poly Si CMP The most basic and common CMP process is called ILD CMP. This process is relatively mechanical in nature and follows Preston’s law quite well. ILD CMP processes typically use silica-based abrasives in KOH-based solution to polish silicon dioxide films. During ILD CMP, KOH chemically softens the silica film on the wafer in the presence of a mechanically applied pressure. Silica abrasives in the polishing solution, carried by the polyurethane pad (Rodel IC1000), abrade away the softened film layer on the wafer surface. This process is quite elegant since during polishing the fine abrasives particles also dissolve by the same softening mechanism, therefore reducing scratching defects. Planarization during oxide ILD CMP is fairly easy to explain. Since mechanical forces are required to soften the silica films in alkaline chemistries, die level features that protrude from the wafer surface are preferentially removed by high localized pressures. Using a more rigid polishing pad or pad stack further enhances this dimensional selectivity and can improve the planarization efficiency. As features flatten, the local surface area being polished actually increases due to the erosion of protruding elements. As local die level features flatten, polishing pressures that generate dimensional selectivity are reduced. Due to topography changes, the polishing rates of high features slowly reduce to that of blanket films (See Fig. 17.2). In general, oxide CMP processes are very sensitive to the amount of solids contained in the CMP slurry. Common industrial ILD slurries, such as Rodel Klebesol 1501 and Cabot SS12, contain approximately 12 to 22 percent silica solids by volume. For most CMP processes, slurry flows range from 50 to 125 mL/min. In general, too little slurry flow results in removal rate instability. Too much slurry flow just increases the process cost of ownership with little or no productivity benefits. 17.2.2 Metal CMP Processes Tungsten CMP (WCMP) is different from ILD CMP in many ways. It is a far more chemical process than ILD CMP, and special care must be taken not to overpolish tungsten plugs or vias. A good tungsten polishing process can planarize a via with less than 100 Å of dishing. Slurries for WCMP, such as Cabot

No planarization

Smoothing

Local planarization

Global planarization FIGURE 17.2 Die level ILD planarization. (Source: Rockwell, J., and Li, Y. “Chemical Mechanical Polishing,” Proceedings, Spring CONFCHEM, April 2000.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.4

CHEMICAL MECHANICAL POLISHING WAFER PROCESSING

2.2 −6

1.8

0

WO52−

1.4 1.0 Electric potential V

17.4

Select

WO4

WO3

0.6

Refs

2−

E(V) W2O5

0.2 −0.2

−0.45 pH 7.18 pO2 (bar) 0.0 E−89 pH2 (bar) 9.1 E+0

WO2

−0.6 −1.0 W

−1.4 −1.8

−2

0

2

4

6

8

10

12

14

16

pH FIGURE 17.3 Tungsten and Water Pourbaix diagram. (Source: Pourbaix, M., Atlas of Electrochemical Equilibria in Aqueous Solutions, NACE, Houston, TX, 1974.)

W2000, are typically acidic. If one refers to a Pourbaix diagram* for tungsten and water (Fig. 17.3), one will observe that tungsten will grow a WO3 oxide film on its surface when exposed to an acid. The key to WCMP is the formation, rate of formation, and rate of ablation of this metal oxide layer. Hydrogen peroxide or ferric nitrate oxidizers are often added to WCMP slurries to increase the oxidation rates of tungsten. Since tungsten oxides are very hard, aluminum-oxide-based abrasives are used to remove the oxide layer grown by the slurry chemistry. WCMP processes are generally exothermic and occasionally subject to high friction. If the oxidation process is overrun by abrasion from alumina, very high friction can result. Tungsten CMP processes are often plagued by vibration for this very reason (mechanically abrading faster than the oxidizing mechanism at the tungsten surface). Care must be taken to properly titrate hydrogen peroxide slurry systems since hydrogen peroxide decomposes into water, thus reducing the ability of the slurry to grow the oxide layer quickly. Since WCMP is for more chemical than ILD CMP, process consumables are very different. Fluid transport both to and from the wafer surface can dramatically impact WCMP process results due to its chemical nature. Not all CMP processes follow Preston’s equation. Advanced CMP processes used to planarize Cu (damascene) and undoped silicon dioxide films used for shallow trench isolation (STI) do not follow Preston’s law. The most unique of these systems is abrasive free polishing (AFP) of copper (Hitachi Chemical Company, 430 slurries). AFP slurries are very non-prestonian and use carefully balanced acidic, oxidizing, and complexing chemistries to modify the Cu surface to actually become softer than the polyurethane (IC1000) pad. Basically, these slurries allow the polyurethane pad itself to become the abrasive, allowing for excellent planarization when using a relatively stiff pad. AFP slurries are clear and do not contain any abrasives that can erode oxide/barrier layers during damascene integration (less than 40 Å erosion and dishing). When polishing using AFP slurries, removal rate increases nonlinearly with pressure on rotational CMP tools. *

Pourbaix, M., Atlas of Electrochemical Equilibria in Aqueous Solutions, NACE, Houston, TX, 1974.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.5

CHEMICAL MECHANICAL POLISHING CHEMICAL MECHANICAL POLISHING

17.5

17.2.3 Shallow Trench Isolation Lastly, Ibarra and 3M have developed fixed abrasive polishing pads. These ceria-based pads generate abrasives as they are worn during CMP. The process of generating abrasives as a pad wears is called friability. Process lubrication is provided by basic KOH solutions, while the cerium oxide particles abrade higher spots within the wafer die. Ceria slurries are also non-prestonian in behavior (pressure), offering high removal rates for rough wafer surfaces and almost none for a smooth film or die. Friablefixed abrasive pads and self-planarizing ceria-based polishing abrasives work very well for STI applications, since erosion through the thin nitride layers applied directly to the silicon wafer surface will result in contamination of the substrate (typical within a die range of less than 100 Å). When the feature surface becomes smooth, these systems stop polishing quickly, almost like magic. Polishing friction increases dramatically with some ceria-based systems as the wafer surface planarizes.

17.3 REVIEW OF CMP PROCESS CONTROL CMP processes are conceptually simple, but can be rather difficult to control. The most common process issues faced in the wafer fab are within wafer polishing uniformity degradation, feature planarity changes, and bulk material removal rate drift. With today’s more sophisticated equipment, process control has become a bit easier due to the use of closed-loop systems. In addition, over the past few years the quality of CMP process consumables has improved dramatically. Still to this day, slight changes in CMP polishing pads and/or slurries will have a dramatic impact on CMP process stability. The key to CMP process control is to make sure that each wafer processed is subject to the exact same conditions, both chemically and mechanically. This is the challenge of CMP in a production environment. 17.3.1 Removal Rate Control Basic process tuning for CMP involves adjusting the table or platen speed, carrier angular velocity, and applied polishing pressure (downforce). It is typical for the carrier rotation rate to be similar to the platen rotation rate (in the same direction) for most rotational CMP processes. When the carrier and platen angular velocities are the same, the entire wafer surface will be subjected to globally uniform linear velocity. By increasing the carrier angular velocity relative to the platen speed, the wafer will polish the edge fast, since linear velocities at the wafer edge will be relatively higher than the center. Conversely, as one reduces the carrier angular velocity the wafer will polish the center fast. To increase blanket film removal rates, one just has to increase the polishing pressure and/or platen angular velocities (remember to keep the angular velocity of the carrier about the same as the platen for the most uniform polish). This relationship holds well for lower linear velocities and prestonian systems. At very high linear velocities or platen speeds, the wafer can hydroplane when the polishing downforce is inadequate to overcome hydrodynamic pressures. During hydroplaning the wafer will polish with a poor polishing removal rate and uniformity control. If the polishing downforce is increased too much, the platen drive system may not be able to overcome the polishing friction forces required to rotate the platen. In addition, within the die, the planarity will be negatively impacted as one increases the polishing downforce. This is due to more die level pad/film interaction between features, reducing geometric selectivity and therefore planarization efficiency. Typical platen speeds for 24 in rotational polishing tools are 25 to 90 rpm. Polishing pressures for oxide CMP range from 3 to 8 psi. WCMP and Cu CMP processes use similar polishing pressures and speeds (tool dependent). 17.3.2 Within Wafer Uniformity Control Process tuning can also be influenced by the construction of the wafer carrier. Older CMP systems use back referencing carriers. These carriers comprise a steel or ceramic plate with an applied carrier

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.6

CHEMICAL MECHANICAL POLISHING 17.6

WAFER PROCESSING

film (i.e., Rodel DF200). The shape of the plate and film at the back of the wafer determines the wafer curvature during CMP. Hence the term, back-referencing carrier. For example, a backing plate with a center bow outward of about 2 µm over 200 mm will result in a center fast polishing process. Temperature changes during CMP can influence back-referencing carrier profiles and subsequently the polishing nonuniformity by thermally changing backing plate shape. In addition to the backing plate curvature, the position of the CMP retaining ring on the backreferencing carrier can influence edge-polishing rates. These consumable wear rings are typically made out of polymers or ceramics. By increasing the wear ring pressure to the pad, polishing at the edge of the wafer can be reduced. For some systems this is completed pneumatically, and with others it is determined by the distance the wafer protrudes from the carrier wear ring. For typical backreferencing carriers using a fixed wear ring, this wafer protrusion above the wear ring should be set from 75 to 150 µm. This protrusion is normally set via shims and needs to be completed with a dry carrier film. Care must be taken to keep the wafer protrusion even around the carrier wear ring. A total range of less than 50 µm is suggested for optimum polishing uniformity. Tuning polishing nonuniformity on newer CMP systems requires an understanding of frontreferencing carriers. These carriers are typically pneumatic diaphragms made out of industrial rubbers. The wear ring position relative to the wafer surface is less important for tuning the polishing process. These systems typically have independent wear ring and polish diagram pressure settings. These carriers are called front-referencing carriers since the flexible diaphragm allows the wafer to fully conform to the polishing pad surface during processing. Basically, the ideal wafer shape for optimum polishing uniformity is that of the polishing pad profile. One can reduce the polish rates at the wafer edge by increasing the wear ring pressure relative to the bladder pressure. Care must be taken not to reduce wear ring pressure to less than 1 psi than the polishing pressure to prevent wafer loss during CMP. More advanced carriers may have up to seven or eight unique pressure zones behind the diagram to tune polish nonuniformity. For these advanced carriers, one will need to use software supplied by the CMP tool manufacturer to optimize polishing nonuniformity. In general, pneumatic carriers use polishing pressures from 2 to 10 psi for CMP processes. 17.3.3 Process Consumables Process engineers can ensure that the CMP process remains consistent by properly managing both the slurry and the polishing pad. Slurry management is often left to the facilities people in the wafer fab to maintain and control. Using proper slurry mixing, filtering, titrating, and fluid system rinsing processes can mitigate slurry-related issues. Slight changes in the solid contents of slurries, pH, and/or particle shape and size will change material removal rates. In addition, defective polishing often results from slurry housekeeping-related issues. Dried slurry is very difficult to remove from wafer surfaces and will scratch silica films if entrained in a slurry distribution system from dirty CMP tool components. 17.3.4 Pad Conditioning In general, slurry-related CMP process issues are less common than pad-related issues. The polishing pad is the most critical process consumable in CMP. This is because the CMP polishing pad is important for both transporting fresh chemicals to the wafer surface and removing process by-products. In addition, the polishing pad has a dramatic influence on both within wafer and within die polishing nonuniformity. For the best process control, the pad must be properly managed. A dried pad will scratch wafers, while an old pad will planarize differently than a new pad. To get the best results for one’s CMP process, one must properly take care of the pad. CMP pads for ILD processes are stacked or two-layer pads. A typical stacked ILD polishing pad is a Rodel IC1000 pad backed with a SUBA IV subpad of similar thickness. A good ILD pad stack is a 0.080-in thick IC1000 with a 0.050-in thick SUBA IV subpad. Metal CMP processes typically use fibrous single-layer pads like those supplied by Thomas West Inc. Overall, pad management of oxide and metal CMP pads are similar, and slightly process dependent. In general, polishing pad management for optimum process stability includes, at a minimum, the following: Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.7

CHEMICAL MECHANICAL POLISHING CHEMICAL MECHANICAL POLISHING

17.7

• Regular pad replacement after wafer breakage is critical for defects • Optimum subpad selection for best within wafer and within die uniformity and planarity (stacked pads or two layers are suggested) • Pad temperature control using an integrated, closed loop, cooling system • Pad grooving (Rodel K-Groove), surface texturing, perforations, and/or slurry channeling to improve mass transport • Proper “break in” and contouring or flattening of the polishing pad prior to CMP • Regular conditioning of the pad (in situ or ex situ) using a brush or diamond abrasive conditioner • Periodic pad rinsing and cleaning, which may also include chemical washing of the pad • Maintaining the pad wetness at all times will lower defects and improve process control • Replacing the pad when it wears more than 50 percent of its original thickness is also suggested for best results • Storing pads dry and flat can also help improve polishing results Diamond abrasive pad conditioners are typically used For ILD CMP. These conditioners consist of diamond particles sintered, glued, or brazed to rigid or flexible surfaces. The purpose of the pad conditioner is to periodically mechanically roughen the pad surface in between polishing runs. This is called ex situ pad conditioning. Conditioning during the CMP process is also possible on some platforms, and is known as in situ pad conditioning. Companies such as 3M, Kinik, ATI, and TBW make diamond abrasive pad conditioners. When the pad conditioner scrapes the pad, it opens up small closed bubbles or cells in the polyurethane polishing pad. These bubbles help aid fluid transport both to and from the wafer surface. In addition, rigid diamond abrasive pad conditioners planarize defects or bumps on the pad surface, reducing defects and improving polish uniformity. Channeling occurs as diamonds rake across the pad surface, also improving fluid transport. The downforce one uses to condition the polishing pad will directly influence bulk material rates during oxide CMP. Increasing pad conditioning downforce can increase film removal rates. However, at higher conditioning loads, pad consumption and therefore the process cost of ownership, will be higher. Inadequate pad conditioning will likely result in both unstable polishing uniformity and film removal rate control. This is called polishing pad “glazing.” One can trade off process stability for throughput with pad conditioning. Removal rates can also be maintained by conditioning during the CMP process. This is called in situ pad conditioning. The good news is that grid-based sintered diamond pad conditioners like those offered by 3M/Rodel provide both a long pad life and relatively high polishing rates.* It is too bad that not all CMP tools can be adapted to use these types of pad conditioners. 17.3.5 Endpoint Systems Ensuring wafer-to-wafer process repeatability for CMP is very important to reduce over polishing. It is common for more advanced CMP tools to use endpoint systems. There are a few types of common endpoint systems. Endpoint systems can be classified as either friction-based or optical metrology systems. These two endpoint technologies will be discussed next. Friction-based CMP endpoint systems are the most simple, and typically use platen motor drive current to measure changes in polishing friction. When a wafer film planarizes, the polishing friction slowly reduces and the wafer becomes smoother. In addition, when the film being polished clears, polishing of the underlayer film commences. Since polishing friction is highly material dependent, a strong surge or decrease in the platen drive motor can be observed. Friction-based endpoint systems work well for polishing larger features since they may not be sensitive enough to determine clearing on smaller die features. They also assume that polishing uniformity is nearly perfect. If global

*

Dyer, T., and J. Schlueter, “Characterizing CMP Pad Conditioning Using Diamond Abrasives.” Micro Magazine, January 2002.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.8

CHEMICAL MECHANICAL POLISHING 17.8

WAFER PROCESSING

wafer polishing uniformity is poor, one will significantly over polish regions of the wafer to clear the entire film. This issue is especially critical for metal CMP processes, since residual metal films on a device wafer result in short circuits. Overpolishing of metal wafer features reduces vertical line dimensions and subsequently increases local current densities in circuits. Optical endpoint systems are used as an alternative to friction-based endpoint systems. In general, optical-based systems are far more complicated and expensive than friction-based systems; however, they provide better process control. Optical endpoint systems can use monochromatic or white light depending on the detection system. They can also use interference or reflectivity to determine the film condition at the wafer surface. Ideal optical endpoint systems should view as much of the wafer surface as possible, and be immune to the optical impact slurry and polishing debris. Most optical endpoint systems require placing sensors or holes in the polishing pad (Rodel). As the wafer moves across the polishing pad, these optical sensors look for changes in material reflectivity, color, or spectral interference patterns. For multipressure zone polishing heads, optical endpoint systems can be used to reduce local pressures in regions where the endpoint is achieved to reduce overpolishing. More advanced CMP tools such as the Novellus Momentum platform can use the systems to optimize polishing uniformity and hold consistent stock material removal rates on a run-to-run basis. 17.3.6 In Situ Metrology The ultimate in process control metrology for oxide CMP is an embedded metrology tool like a Nova Inc. or Filmetrics Inc. system. These metrology tools are embedded into a CMP platform to measure within die features and film stack thickness in critical areas immediately after polishing. These tools often require that the wafer be placed die side down over the measuring head. The measurements are performed under deionized (DI) water to prevent slurry particles from drying to the wafer surface. In general, these embedded metrology tools are slow to take measurements and are relatively expensive. As optical endpoint systems mature, within wafer nonuniformity polishing improvements should allow for improved process tuning to reduce overpolishing and provide a planar wafer without extensive in situ metrology verification.

17.4 POST-CMP WAFER CLEANING Originally, CMP tools were used just to polish wafers. After the polishing process was complete, wafers were delivered to a submerged wafer cassette. After a process lot was completed, wafers were placed in a spin rinse dryer (SRD) and continued on their way through manufacturing. These older CMP tools are know as “dry in, wet out” (DIWO) tools. Today’s advanced CMP tools regularly deliver dry wafers to the production line. These “dry in, dry out” (DIDO) CMP tools eliminate the need for a local spin rinse drier for the tool. The following section discusses the advantages of dry in, dry out CMP tools with regard to wafer cleaning and defect levels. 17.4.1 Dry in-Wet out CMP Tools DIWO CMP tools were state-of-the-art for many years. Older single and dual platen CMP tools often fed wafers into cassettes via water tracks and slides. The main issues with these tools in the wafer production line are wet wafers. When CMP wafers are allowed to dry, slurry particles can chemisorb onto the wafer surface. They become nearly impossible to remove after the wafer dries off. In addition, a wafer fab environment is typically dry; therefore the logistics of managing with wet wafers complicates the manufacturing process flow. Older CMP tools are often flanked by a spin rinse-drier system used to dry wafers immediately after polishing. This local drying system is used to reduce slurry-related surface defects. As these DIWO tools evolved, a second polishing platen or buffing system was added to post scrub the wafer after polishing. The buffing process removes larger, say more than 0.5 µm, slurry particles quite effectively. These systems typically use textured polytex pads (Rodel) at high linear velocities using very low polishing downforces (less than 2 psi). DI water or a Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.9

CHEMICAL MECHANICAL POLISHING CHEMICAL MECHANICAL POLISHING

17.9

solution of KOH, with pH more than 10, is typically used to lubricate the wafer during the buffing process. The addition of a second platen adds another process step and therefore additional time to polish wafers. To prevent dried slurry-related defects, one is still required to spin rinse-dry wafers out of a two platen DIWO CMP tool. 17.4.2 Dry in-Dry out CMP Tool As critical wafer dimensions decreased in size, so did allowable defect sizes and surface concentration levels. DIWO CMP tools were no longer able to buff wafers and meet increasingly more stringent defect criteria. Therefore, the DIDO CMP tool was developed. A DIDO CMP tools looks much like a DIWO CMP tool; however, there is a dry wafer cassette placed on the “unload” or completed process station. These tools also use a robot to load the dry wafers in to the completed cassette since water slides or tracks can no longer be used. DIDO CMP tools also contain a wafer cleaning system that typically uses a spin rinse or Marangoni drier. After buffing wafers with a second platen, wafers are then cued in a wet-storage elevator or compartment for post-CMP cleaning and drying. 17.4.3 CMP Wafer Cleaners CMP cleaning systems originally evolved separately from CMP tools. Their function is to chemically and mechanically remove defects and particles from wafers prior to spin rinse drying. Standalone CMP cleaners for ILD and STI CMP typically use ammonia, dilute hydrofluoric acid, and PVA-type brushes (Texwipe Inc., Rippey Inc.) to clean wafers. Hydrofluoric acid helps the cleaning system to chemically dissolve particles, while ammonia reduces zeta potential (electrostatic-type forces) that attracts particles to surfaces. More advanced cleaners use noncontact ultrasonic or megasonic sound energy to remove particles. Megasonic cleaning systems use immersion baths or spray jets backed with transducers to create high-frequency pressure waves in water. These pressure waves can help break zeta potential and van der Waals attraction forces of particles attached to the wafer. For very small particles, van der Waals attraction forces per unit area can be extremely high; therefore a lot of energy is required to remove small particles. 17.4.4 Internal CMP Cleaning Systems CMP cleaners are now commonly found residing inside CMP tools. Increasing productivity requirements have made stand-alone cleaners obsolete except for process development. The trick to placing a cleaning system into a CMP tool is floor and tool space. Even with strict space limitations, integrated CMP cleaners nowadays are extremely effective and convenient. The productivity of cleaning modules is also improving as systems evolve. By using Marangoni or other solvent-type drying processes, the need for extensive spin rinse drying of wafers is quickly going away. In addition, porous low-k films are very delicate and can be damaged by the use of water-based clean chemistries. Therefore, solvent-type CMP cleaning and drying systems will become more common in the future.

17.5 COMMON CMP PLATFORMS AND TOOLS CMP systems have been in use for over 30 years. The first of these tools were based on the more traditional rotational CMP process. However, as time went on, process and productivity requirements changed and the tools had to evolve. This section will discuss typical production of CMP tools and architectures. In addition to tool configurations, this section will discuss some of the special features of the different types of CMP tool sets. 17.5.1 Single Head Rotational Systems Rotational tools for CMP are roughly based on lapping and polishing tools for glass, ceramic, or metal components. These tools consist of a single polishing platen and a single polishing head known Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.10

CHEMICAL MECHANICAL POLISHING 17.10

WAFER PROCESSING

as a carrier. Carriers for these systems are, in general, back referencing. A classic rotational CMP tool is the IPEC (Integrated Process Equipment Corporation)-Westech 372. This single-head system consisted of a single carrier on a gantry, a 22- to 26-in polishing pad, and a wand holding a 75- to 100-mm diameter TBW Inc. type pad conditioning disk. These tools also look much like first CMP systems, first offered by Struassbaugh Inc. For basic low-volume CMP work, these tools are quite effective. They are all “wet in, wet out” (WIWO) in configuration and process a single wafer at a time. Loading and unloading of wafers is completed with a water jet and track system, and the wafers remain submerged in the unload station. For basic WCMP and Oxide CMP, these reliable tools work well and can typically be found in the used equipment market or in R&D labs. 17.5.2 Multihead Rotational CMP Systems As productivity and defectivity requirements increased, multihead rotational CMP tools were born. This classification of tools has a wide variety of variants. In general, multihead rotational CMP systems are developed for high throughput production applications. High productivity multihead CMP systems can achieve productivities of greater than 40 wafers per hour (ILD or WCMP). The benchmark multihead, twin platen CMP tool is the Speedfam-IPEC Auriga system. Evolving from the Speedfam Inc. CMP-V platform, the Auriga is a five-head CMP tool that uses one main 32 in diameter platen and a secondary smaller platen for post-CMP buffing. The pad conditioner is a large diamond ring or brush that conditions the pad in between each fivewafer run. At full bore, the Auriga can process more than forty 200 mm wafers per hour (1 min polish at 3000 Å/min) in a production environment. Each head is individually controlled to allow for better process control. Initially a WIWO system, the Auriga evolved into the Auriga C, being the first multihead tool to offer an integrated wafer cleaning system. The Auriga was the throughput king for many years, and was mimicked by the three-head Straussbagh Symphony platform. Other two-and three-head CMP tools, like those offered by Ibarra hit the market later using up the three polishing platens to increase process flexibility. 17.5.3 Multiplaten CMP Systems The lack of process flexibility, for example, polishing a lot of 22 wafers versus 25, limited the Auriga and Symphony platforms to simple high-volume CMP processes. Though fast, the Auriga also had reliability problems and could not be extended to multistep, multichemistry CMP processes like Cu CMP. This weakness of multihead single-platen tools allowed multiplaten rotational systems, like those offered by Peter Wolters, Ibarra of Japan, and Applied Materials Inc., to capture the CMP equipment market. The best example of a multiplaten CMP carousel tool is the Applied Materials, Inc. Mirra CMP system (see Fig. 17.4). Initially a WIWO system, the Mirra quickly evolved into a DIDO system. Using three polishing platens, the Mirra can polish up the three wafers simultaneously

FIGURE 17.4 Applied Materials Mirra CMP tool. (Courtesy of Applied Materials, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.11

CHEMICAL MECHANICAL POLISHING CHEMICAL MECHANICAL POLISHING

17.11

using three different chemistries. Each approximately 20 in diameter polishing platen utilizes just one carrier for polishing. Carriers on the Mirra platform are front referencing “Titan Head” pneumatic bladder carriers and offer better polishing performance than the dated back referencing carriers offered by many competitors. Since the platens are relatively small in diameter, the multiplaten Mirra is also a compact CMP tool. The Mirra is called a “carousel” tool. After each process step is completed, the cross- shaped gantry that holds the polishing heads, rotates clockwise to the next polishing platen. This allows the Mirra to complete a two chemistry polishing process and post-CMP buffing operation on each wafer. Though slower than the Auriga, the Mirra can process odd number CMP lots without suffering from process variability. Due to the simplicity and process flexibility of multiplaten CMP tools, they now dominate the world’s CMP market. 17.5.4 Orbital CMP Systems Due to increasing process flexibility and productivity requirements, IPEC Inc. developed the 676 orbital CMP. This system was developed from an orbital CMP concept originally patented by Intel. Instead of moving the polishing platen in a rotation motion, the IPEC 676 orbits the 16 to 18 in flexible polishing platen (pad backer) in a 5/8 in circular pattern at high angular velocities. Instead of the typical 24 to 90 rpm rotational speeds of the IPEC 372/472, the 676 typically uses orbit speeds of 150 to 400 rpm to generate the required linear velocities to polish wafers with a reasonable throughput. Polishing pressure loads are similar to rotational CMP tools. In contrast to rotational CMP tools, carrier rotational speeds for the 676 are relatively low. In addition, to improve polishing nonuniformities, the polishing pad is also dithered up to 270° back and forth at very slow rate. This dithering is called advanced pad motion (APM). The 676 and 776 orbital CMP tools use a perforated flexible polishing platen called the pad backer to provide polishing loads. The pad backer provides some improvement in the polishing uniformity since the system uses only a simple back referencing carrier with a pneumatically controlled wear ring for edge polish rate control. In addition, since the pad backer is perforated, slurry can be delivered directly to the wafer surface during polishing. Fluid transport to and from the wafer for this tool is very unique, and advantageous for abrasive-free Cu CMP. Pad conditioning on the 676 and 776 platforms is completed with a long foam-backed flexible diamond abrasive strip attached to a rigid arm. These polishing tools had up to four individual polishing modules known as microplanarizers, or “MPs.” Wafer buffing, post-CMP, is completed on a smaller orbital buffing unit attached to the back of the tool. The 676 tool is of a WIWO configuration, and the 776 has an embedded wafer cleaner allowing for DIDO operation. SpeedFAM and IPEC merged in the late 1990s to create Speedfam-IPEC. The combined companies revolutionized the performance of the orbital platform. The main changes made to the 776 were stiffening the pad backer, improving the control system, and replacing the back referencing carrier with a multizone front referencing carrier. This new hardware combination dramatically improved the process performance of the 776 platform. This new platform is known as the Momentum tool, and offers true 1 mm edge exclusion polishing control, dynamic polishing uniformity adjustment, and DIDO operation. Speedfam-IPEC is now a part of Novellus Inc., who offers the tool to this day. During the late 90s, Obsidian Inc. introduced a competitor orbital polishing tool to the 776. This tool uses an orbiting carrier head, unlike the Momentum’s orbiting platen, to generate linear velocities required for reasonable productivity. The Obsidian tool was a web-based tool, using a flexible fixed abrasive pad for oxide CMP. Made by 3M Inc., this “web” pad offers a superior planarization performance to standard IC1000/SUBA IV pad polishing processes that utilize silica-based slurries. Process development is tricky using the ceria-based 3M pad, since wafer patterns can change material removal rates. Blanket PETEOS or steam oxide silica films are poorly polished by the 3M fixed abrasive pad. Applied Materials purchased and absorbed Obsidian in the early 2000s. 17.5.5 Linear Drive CMP Tools Lastly, linear CMP tools were developed to provide very high and uniform linear velocities for CMP. These tools work analogous to a belt sander where the polishing pad is mounted to a track Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:57

Page 17.12

CHEMICAL MECHANICAL POLISHING 17.12

WAFER PROCESSING

driven by motors. The wafer carrier is stationary and centered on the track. It can be rotated slowly to “smooth” and further polishing uniformity. These systems produce an ideally uniform velocity field across the wafer surface. Slurry distribution consists of an array of sprayers pointed at the pad. A linear diamond-coated bar placed against the pad completes the pad conditioning. This allows for in situ pad conditioning. The most famous of these linear CMP tools is the Teres platform developed by LAM Research Corporation. The Teres platform has a horizontal pad configuration. The second linear drive tool, and less well known, was the twin head APLEX tool. The APLEX system is unique in that it uses a vertical pad configuration to reduce the tool footprint. Linear CMP tools were fairly successful for oxide CMP, but lacked the multiplaten flexibility for Cu CMP. Both linear tools used front referencing carriers at one time or the other, and fluid bearing systems to improve polishing uniformity. Unlike the Aplex CMP tool, the LAM Teres platform was actually used in a production environment. Due to poor process flexibility, reliability problems, and adverse business conditions, these tools did not survive long in the industry.

17.6 CMP PROCESS WASTE MANAGEMENT CMP tools use both benign and hazardous chemicals. For the most part, CMP tools use copious amounts of DI water for wafer processing. By volume, DI water is the most predominant effluent from CMP tools. In addition to DI water, CMP process effluents can contain a multitude of constituents such as ammonia, dilute hydrofluoric acid, KOH, hydrogen peroxide, ferric nitrite oxidizers, metallic residues, and possibly silica, alumina, and/or ceria particulates. Strategies for elimination of CMP process wastes depend on meeting local laws and environmental regulations. CMP tool waste streams are normally separated by process modules. Mixing process effluents from a CMP tool is not a good idea, since CMP cleaning chemistries can be very reactive with polishing chemistries. In addition, some oxidizers such as ferric nitrate can discolor CMP tool plastic components and attack steels used to frame the tool. In general, CMP tool components are very corrosion resistant. Therefore, improper management of CMP tool waste can impact tool reliability due to corrosion or reactivity issues. 17.6.1 Oxide CMP Process Waste Oxide CMP slurry systems are KOH-based and contain solids like silica and ceria. An array of fibrous and ceramic filters can remove solids from the process effluent of the CMP tool. Additions of weak acids to KOH will generate potassium salts while neutralizing the solution to a pH of about 6 to 7. Oxide CMP waste streams are also free of metallic contamination; therefore they are typically environmentally benign after filtering and neutralization. Typical HF neutralization systems used for processing acid wastes can handle CMP cleaning system effluents from ILD or STI CMP tools. Though dangerous or aromatic in their diluted state, CMP cleaning chemistries can be neutralized and processed much like wet etch station effluents. 17.6.2 Metal CMP Process Waste Metallic CMP effluents are far more of a concern in the fab. Cu CMP is the most toxic of the CMP processes since ionic Cu is a common process effluent along with a variety of oxidizers and acids. WCMP, using acidic chemistries and a hydrogen-peroxide-based oxidizer (Cabot W2000), forms stable tungsten oxide particles in the process effluent. These particles can be captured in ceramic filters along with the alumina abrasive used for polishing. After filtering, WCMP effluents can be diluted and neutralized much like other chemicals used for etching in a wafer fab. Hydrogen peroxide can be reacted away using activated carbon filters. Oxidation of tungsten makes WCMP process effluents less of a problem than Cu effluents. Cu CMP effluents require more advanced techniques for management. Currently, Cu CMP effluents are filtered using ceramic systems (US Filter Corporation, Kinetico Inc.) and post-processed. Ceramic Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:58

Page 17.13

CHEMICAL MECHANICAL POLISHING CHEMICAL MECHANICAL POLISHING

Pressure gauge P Flow meter

17.13

Pressure gauge P Flow valve Filtration element Permeate

Heat exchanger Flow valve

P Flow valve

Pressure gauge

Valve Feed tank

Drain

Centrifugal pump The pH of the sample was adjusted manually prior to solids removal with the ceramic membranes. FIGURE 17.5 Modern Cu CMP Effluent Cleaning system. (Source: R. Woodling, www.semi.org.)

filters, like those made by US Filter for Cu CMP effluents,* can usually filter down to 0.02 µm. Postprocessing of Cu CMP residues after filtering is typically completed using precipitation, ion exchange, and electrochemistry to eliminate Cu. In general, these techniques will generate solid toxic wastes that will have to be stored and removed for the facility. Both academic and industrial research continue to improve Cu CMP effluent management. An advanced Cu CMP effluent management system by US Filter is illustrated in Fig. 17.5.

17.7 FUTURE TRENDS AND CONCLUSIONS CMP is an elegant way of etching films while simultaneously flattening them to atomic levels. The process also works for a wide variety of films and applications. Newer CMP tools are now very reliable. CMP tools and consumables industries have both made many improvements over the last 20 years. The process is DI water intensive and can generate some manageable toxic wastes. Overall, CMP is a good way to help resolve depth-of-focus issues with lithography while also bringing Cu into advanced microelectronics. As CMP tools advance into the 70 nm and smaller process nodes, they will encounter softer, porous, low-k dielectric (constant) materials and fluoro-silicate glasses (FSGs). These films are so delicate that they can actually be crushed by the capillary forces resulting from drying water. Polishing-generated friction and chemicals can easily damage low-dielectric constant films. In order to reduce polishing-related shear forces, applied polishing downforce is reduced and the table (pad) speed is increased to bring up material removal rates. Polishing near the hydroplaning regime is helpful for improving planarization efficiency and reducing polishing shear friction forces. In these “gentle” CMP tools, efficient fluid transport of slurry to and from the wafer and gentle downforce control *

Woodling, R., “Treatment of Copper CMP Wastewater Without Hazardous Waste Generation,” SEMI.ORG Web Site, 2003.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH17.qxd

04/04/2005

19:58

Page 17.14

CHEMICAL MECHANICAL POLISHING 17.14

WAFER PROCESSING

will be critical for process stability. Wafer cleaning systems are becoming solvent based to reduce CMP cleaning damage on low-k films. In addition, these new tools must offer increasing pad life, reduced water consumption, and lower slurry utilization rates. Cost of ownership is increasingly a bigger driver in CMP tool selection. For advanced Cu CMP, some companies have reported depositing Cu and planarizing it on the same platform. This would potentially allow for a deposit-etchback-deposit damascene-based trench fill process. Integrating CMP tools with Cu deposition tools will likely occur in the future. Surprisingly, the Cu CMP and Cu deposition processes are chemically very similar. In summary, advanced CMP tools will likely consume less water and recycle some chemicals. Toxic wastes will be better managed. They will be highly automated tools that offer good reliability and low process cost of ownership. In addition, solvent or low-pressure based drying systems will likely replace spin rinse driers in newer CMP tools as critical defect criteria keep reducing in size and allowable surface density.

FURTHER READING 1. Lee, S. H., and R. Miller, Chemical Mechanical Polishing in Silicon Processing, Academic Press, Burlington, MA, October 15, 1999. 2. Borst, C. L., W. N. Gill, and R. J. Gutmann, Chemical-Mechanical Polishing of Low Dielectric Constant Polymers and Organosilicate Glasses: Fundamental Mechanisms and Application to IC Interconnect Technology, Kluwer Academic Publishers, Boston, 2002.

INFORMATION RESOURCES Novellus: http://www.novellus.com/damascus/tec/tec.asp. CREOL in Florida: http://www.creol.ucf.edu/. Clarkson University (CAMP): http://www.clarkson.edu/camp/. The American Vacuum Society: http://www.avs.org/. The Materials Research Society: http://www.mrs.org/.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 18

WET CLEANING Andrew Machamer SEZ America, Inc. Phoenix, Arizona

18.1 OVERVIEW AND BACKGROUND OF WET CLEANING Wafer cleaning and surface preparation are key areas of technology and development in the semiconductor manufacturing industry. Researchers are recognizing that this area of manufacturing, once thought of as a non-value-added process step, is now an enabling process sequence that is becoming increasingly more important in wafer processing technology. Some key trends in cleaning that are critical to future complimentary metal oxide semiconductor (CMOS) technology generations are toward the use of single-wafer wet cleans, post-damascene copperporous low-k etch clean, post-Cu CMP cleaning, new material cross-contamination control, and consideration of environmental, safety, and health factors in development.1 18.1.1

Contaminants Wet cleaning and etching are processes that expose a semiconductor wafer to liquid phase chemistries in order to remove unwanted materials (films and defects) from the surface. Films can be described as contiguous layers of material across a surface having a thickness of at least one monolayer of atoms. Defects describe both particle contaminants and physical damage characteristics such as surface scratches and gouges. All defects are generated both inherently as part of the production process and also inadvertently due to the manufacturing environment. Particles are bodies with finite mass and structure, but negligible dimensions. Films may be organic or inorganic in nature. Even with the scrupulously clean manufacturing environments found in the semiconductor industry, particles are nonetheless generated. These particle sources include equipment, personnel, and other wafers. Control of wafer contamination in general requires control of these defect sources. Furthermore, an effective method of defect removal also needs to exist and wet clean processing provides solutions for these problems.

18.1.2

Theory of Particle Adhesion There are a number of different interactions that account for the adhesion of a particle to a wafer surface. Understanding these interactions is critical in the development of cleaning processes that adequately remove particles. In this section some of the primary interaction mechanisms are discussed including molecular and charged particle interactions. Molecular Interaction. Molecular interaction is attributed to the van der Waals force of adhesion between the particle and the wafer surface. The strength of adhesion force is a function of (a) the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

18.1

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.2

WET CLEANING 18.2

WAFER PROCESSING

Hamaker constant (defined as a function of the Hamaker constants of the particle, the wafer surface, and the interlaying medium), (b) the geometries of the interacting bodies, and (c) the distance between the particle and the wafer surface. There are two major theories for the calculation of the Hamaker constant, known as the London and the Lifshitz theories. Both are based on the molecular properties of matter. The London theory takes into account the pairwise addition of interactions between neighboring matter and the Lifshitz theory is based on quantum electrodynamics. Most often, both theories yield equivalent values for the Hamaker constant. The Hamaker constant (A12) between different matter is expressed as the geometric mean of the individual Hamaker constants (AXX) for matter “1” and “2” is expressed as A12 = A11 ⋅ A22 When two materials are separated by a third medium “3” then the Hamaker constant for the system (A123) is calculated by A123 = A12 + A33 − A13 − A23 Using A123, it is possible to calculate the force of adhesion (FAd) for a system. The calculation of FAd varies depending on the geometry of the matter involved. A typical example used in wet cleaning as a theoretical model is that of a flat plane (wafer surface) and a sphere (particle). The equation for the van der Waals force of adhesion is described as FAs =

A123d p 12 Z02

where dp is the diameter of the particle and Z0 is the distance between the edge of the particle and the surface of the wafer. This is consistent for a smooth particle on a smooth surface. If either the surface, the particle, or both are rough, this equation becomes more complex to account for a distributed adhesion rather than a single point.2 Therefore, by the aforementioned equation, the force of adhesion for any system is directly proportional to the media to which the wafer is exposed. The Hamaker constant for a system in water is calculated to be an order of magnitude smaller than that for the same particle and wafer combination in air. Due to this difference in the Hamaker constant, the van der Waals force of adhesion is an order of magnitude smaller in a system containing a liquid as the interlaying medium, thus implying that a wet cleaning technique will require less force to remove particles on a wafer surface than a dry cleaning technique. It is important to note that the force of adhesion for a real system is highly dependent on particle shape, wafer topography, film on wafer, and purity of interlaying media.3 Charged Particle Interaction. Charged particle interaction is another important method of particle adhesion. The forces are due to coulombic attractions, electrostatic contact potentials, and ionic double layer interactions. For coulombic attractions, the particle and/or the surface must be charged. They are best described as the force between a particle and its “image” within the planar surface, also known as an electronic double layer force. The magnitude of the force is inversely proportional to the dielectric constant of the media between the particle and the surface and therefore this force is very weak when the system includes an aqueous solution.4 Greater forces are developed by electrostatic contact potentials than coulombic interactions. For very small particles, electrostatic contact potentials induce electronic double layer forces that result from the differences in local energy states and electronic work functions of the particle and the surface. This force develops from the transfer of electrons between the particle and the surface in order to achieve a common charge. It is directly proportional to the diameter of the particle and can achieve magnitudes equal to the van der Waals force.5 Still greater forces are developed when the particle and wafer are present in a liquid solution, due to the presence of ions that create an ionic double layer interaction. This interaction results from the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.3

WET CLEANING WET CLEANING

18.3

ionic distribution in the liquid and can act as a repulsive or an attractive force. If the particle and the wafer surface have like charges, the force is repulsive and therefore aids in particle removal. The forces developed from these interactions can be quite large when compared to van der Waals forces and also act over greater distances.6 This phenomenon is described by the DLVO theory (developed by Derjaguin and Landau, Verwey, and Overbeek, independently) that characterized the interactions between two of the same colloidal particles. The DLVO theory is further extended by Hogg, Healy, and Fuersteanu (HHF) among others to describe the interaction between a colloidal particle and a plane. The HHF equations assume that either the zeta potential Ψ(ζ ) or the charge σ remain constant. The ionic double layer force FelΨ is given as

(

FelΨ = pe r e 0 R Ψ012 + Ψ022

−kH

) 1k−ee

−2kH

  2 Ψ01Ψ02 − e −kH   2 2 + Ψ Ψ 02   01

where Ψ01 = zeta potential of the particle with radius R Ψ02 = zeta potential of the substrate er = dielectric constant of the medium e0 = dielectric permittivity of a vacuum k = Debye-Huckel parameter of the electrolyte solution. The zeta potential is directly related to the electrolyte concentration and the pH. High zeta potentials are seen for the following particles in high pH solutions—SiO2, Al2O3, W, polyvinyl alcohol (PVA), and polystyrene latex (PSL). The removal of these particles is aided by using a strong basic cleaning solution such as ammonium peroxide mixture (APM).7 Other Interactions. There are additional forces such as capillary condensation and hydrophobic/ hydrophilic interactions that bind particles to wafer surfaces. Capillary condensation creates an adhesion force when a particle is present on the wafer surface after removal from a liquid bath. The liquid between the particle and the wafer binds the particle to the surface due to the surface tension of the liquid. If the particles are not removed prior to a baking process and the liquid has a tendency to crystallize, then a solid connection can be formed between the particle and the wafer surface with an increased binding energy between the particle and the surface. This attractive force is not observed on hydrophobic wafers. The wetability of the wafer and particles (hydrophobic or hydrophilic) has an effect on their interaction. Hydrophobic particles group together because of their tendency to resist contact with water molecules. This also applies to the interactions of hydrophobic particles and a hydrophobic wafer surface. In contrast, a system that contains both hydrophilic particles and a hydrophilic wafer will typically repel each other in order to ensure that the surfaces are surrounded by water molecules. The aforementioned interactions are those that are described in literature. However, as particle removal becomes more important in the semiconductor manufacturing process, there is a need for a better understanding of the forces that hold particles to wafer surfaces. The best method to minimize particle adhesion is to limit the number of particles generated and the number that come into contact with the wafer. This is accomplished by minimizing particle generation and transport in the equipment design, using ultrapure fluids for wafer processing and minimizing attraction by controlling the electrical charge on the wafer and in the processing environment. 18.1.3

Overiew of Wet Processing Techniques Wet processing is the common approach for removal of particles and films on a wafer surface. The most common techniques include wet chemical cleaning via immersion, liquid dispense, or physical surface scrubbing. Wet chemical cleaning may also include the use of pressurized fluid jet or sonic cleaning. Liquid Chemical Cleaning. Liquid chemical cleaning involves subjecting the wafer surface to various liquid chemicals to remove the contaminants. Historically liquid chemicals are used for the removal

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.4

WET CLEANING 18.4

WAFER PROCESSING

TABLE 18.1

Typical Wet Cleaning Chemistries

Chemistry

Common name

Purpose or removal of

NH4OH/H2O2/H2O HCl/H2O2/H2O

RCA-1, SC-1, APM RCA-2, SC-2, HPM

H2SO4/H2O2 HF/H2O HF/NH4/H2O HNO3 (CH3)3N+CH2CH2OH⋅OH

Piranha, SPM, “Caros acid” HF, DHF (dilute HF) BOE (buffered oxide etch), BHF Nitric Choline, Trimethyl (2-hydroxy-ethyl) ammonium hydroxide Choline/peroxide

(CH3)3N+CH2CH2OH⋅OH/ H2O2/H2O (NH4)2SO4/H2SO4 H2S2O8/H2SO4 O3/H2O H2SO4/O3/H2O HF/HNO3 HF/H2O2

SA-80 PDSA, “Caros acid,” Piranha Ozonized water SOM (sulfuricozone mix) Hydrofluoric acid/nitric acid Hydrofluoric acid/hydrogen peroxide

Light organics, particles, and metals Heavy metals, alkalis, and metal hydroxides Heavy organics Silicon oxide Silicon oxide Organics and heavy metals Metals and organics Heavy metals, organics, particles Organics Organics Protective oxide regrowth, organics Organics Slight Si etch; metals Slight Si etch; metals

Source: Burkman D., D. Deal, D. Grant, C. Peterson, Handbook of Semiconductor Wafer Cleaning Technology, W. Kern (ed.), p. 121, Noyes Publications, New Jersey (1993).

of organics, alkali ions, and metals. The choice of chemicals is based on their ability to selectively react with contaminants to either dissolve them (or solubilize) or to cause them to be dispersed in the liquid.8 The most common chemicals used in wet chemical cleaning are listed in Table 18.1. In the front end-of-line the most commonly used wet clean approach to remove particles and metals from the wafer surface is the Radio Corporation of America (RCA) method via immersion of a batch of wafers in a tank. This approach is well characterized and has thus far proved successful for the existing technology requirements of the industry. Some advantages of batch wet chemical cleaning are the removal of metal ions and soluble impurities and the cost of the process. Disadvantages include the requirement of additional process steps such as deionized (DI) rinsing and wafer drying. Furthermore, in the case of immersion, there is the potential for redistribution of particles within the wafer batch, from a wafer backside to a front side surface. Scrubbing. Scrubbing involves the use of rotating brushes that move across the surface of a wet wafer as shown in Fig. 18.1. The brushes are typically made of nylon or polypropylene or some other organic polymer. In theory, these brushes never touch the surface of the wafer because the materials are hydrophilic and therefore have a boundary layer of liquid that is always between the brush and the wafer surface. A mathematical model of this interaction utilizes the critical particle Reynolds

Rotating brush

Brush motion

Fluid Wafer FIGURE 18.1

Typical scrubbing system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.5

WET CLEANING WET CLEANING

18.5

number for the determination of the effect of the hydrodynamic removal force on the cleaning and a moment balance approach to determine the affect of the direct moment transfer from the brush to the particle. The flow particle Reynolds number is defined as Re p =

drVp m

where d = particle diameter r = fluid viscosity Vp = relative velocity between the fluid and the particle at the center of the particle m = fluid viscosity The critical particle Reynolds number (Repc) is the Reynolds number at which the particle will begin to roll on the surface. In order for the particle to be removed, Rep must be greater than Repc. Typically in a scrubbing system, the distance between the brush and the wafer surface is such that brush-particle interaction occurs that has the effect of either lowering Repc due to adhesion to the brush or a momentum transfer between the brush and the particle.9 Recent work has concluded that the brush must come into contact with the particle for complete removal and that the particle shape has a great effect on the efficiency of the scrubbing system.10 The optimum wafer surface for this type of clean is a hydrophobic wafer (particles are transferred to the brush) without patterning (the bristles cannot penetrate into small line widths because of their size). The benefit of scrubbing is its highly efficient removal of particles. The problems associated with scrubbing are maintenance intensiveness as brushes must be changed or cleaned frequently, the poor cleaning ability on patterned wafers, and the potential to damage the wafer surface. Pressurized Jet Cleaning. Pressurized jet cleaning is the application of a liquid, usually water, by a high pressure nozzle. Air or nitrogen has been used for many years to remove particles from a surface. A more refined approach is a pressurized liquid jet to remove small particles from the wafer surface. The phenomenon that governs this type of cleaning is that the kinetic energy of the moving fluid imparted to the particle is greater than the force of adhesion of the particle on the surface thereby removing the particle from the wafer surface. The use of a liquid instead of gas for the jet has some fundamental benefits. The force imparted from one body to another body is based on the momentum of the moving object. Therefore, at comparable velocities, a liquid will have a much greater momentum than a gas due to its higher density. Another benefit of using a liquid instead of a gas is that a liquid develops a smaller boundary layer than a gas thereby allowing the jet stream to interact with much smaller particles. Furthermore, a pressurized jet has the ability to remove small particles from a patterned wafer. Disadvantages of this cleaning method are the potential for damage of the wafer surface and the propensity for the moving fluid to create a static charge that can lead to device damage. Sonic Cleaning. Sonic cleaning can be divided into two categories—ultrasonics and megasonics. The principle for sonic cleaning is to use the energy of sound waves to initiate cavitation, in the case of ultrasonics, or acoustic streaming (high-velocity pressure waves), in the case of megasonics, in a liquid system. Sonic energy is used to overcome the particle adhesion force and dislodge the particle from the wafer surface. The ultrasonic frequency range is from 20 to 800 kHz, while the megasonic frequencies are greater than 800 kHz. Megasonic cleaning is dependent on the reduction of the boundary layer and on acoustic streaming. The acoustic boundary layer is very small when compared to the hydrodynamic boundary layer. The acoustic boundary layer is given as 2n d ac =   w

1/2

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

18.6 Heater

Return pump

Filter

Flowmeter

Generic design for wet cleaning equipment.

Pump

Chemical storage tank

Recirc. valve

Chemical valve Wafer handling robot

Drain to chemical waste

Drain valve

Process vessel

Wafer handling module

Loadport

Foup

19:58

FIGURE 18.2

Deionized water

Deionized water valve

Exhaust

04/04/2005

Chemical handling module

Wet cleaning system boundary

To chemical exhaust scrubber

Geng(SMH)_CH18.qxd Page 18.6

WET CLEANING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.7

WET CLEANING WET CLEANING

18.7

where ω is the acoustic frequency (2πf ) and ν is the viscosity of the liquid, while the hydrodynamic boundary layer is given by 1/7

n d H = 0.16  x  Ux  where x is the distance from the leading edge of the wafer and U is the fluid velocity. For a typical 8 in wafer in water with a velocity of approximately 4 m/s the hydrodynamic boundary layer is approximately 1000 µm at the wafer’s center. For the same wafer with a megasonic frequency of 850 kHz, the acoustic boundary layer is 0.61 µm. Therefore, the acoustic field allows for much smaller particles to be exposed on the wafer surface and higher cleaning efficiencies.11 18.1.4 Overview of Wet Cleaning Equipment Specialized equipment are used for the implementation of the aforementioned technologies. The three major classes of equipment typically used for wet cleaning are—immersion, placing the wafers in a tank filled with a chemical; spray, using a nozzle to spray the wafer(s) with a chemical; and dispense, directing a stream of an appropriate chemical to the wafer. These can be further categorized by the number of wafers treated at a time—batch or single wafer. Figure 18.2 shows a generic diagram that is the basis of a wet cleaning system. All wet cleaning equipment have a means of getting the chemical to the wafer(s) to be treated in a specialized area (process vessel) and a method of transferring the wafer(s) to the process vessel. General Requirements of Wet Cleaning Systems. Since the majority of wet cleans utilize hazardous liquid chemicals, the equipment must incorporate the following general design considerations: • • • •

Ensure separation of chemicals to eliminate cross contamination. Rinse chemicals from the wafer surface. Dry wafers after chemical treatment. Use materials of construction that are compatible with the chemicals used, and do not add contamination to the wafer. • Provide laminar flow (to minimize particle transport from the equipment to the wafer) in wafer handling and process areas (if open). • Control static charge. In addition, the systems need to ensure that their use does not create a hazardous condition for manufacturing personnel, other equipment, or the general public. Equipment design guidelines to minimize exposure to manufacturing personnel and to contain chemicals within the system are listed in Table 18.2. Protection of the general public is accomplished by monitoring and treatment of liquid waste streams to ensure that effluents are within applicable limits for contaminants. Equipment should be interlocked to ensure that an appropriate exhaust is present prior to dispense of chemicals, and manufacturing exhaust systems need to incorporate scrubbers to ensure neutralization of airborne contaminants prior to release in the atmosphere.

18.2 TYPICAL SEMICONDUCTOR MANUFACTURING WET CLEANING PROCESSES Wet cleaning processes can be divided into two major categories—front end-of-line (FEOL) and back end-of-line (BEOL). The division between these two categories is generally accepted to be at the metallization of the wafer. The following sections are organized according to a typical semiconductor

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.8

WET CLEANING 18.8

WAFER PROCESSING

TABLE 18.2

Design Guidelines for Equipment Using Liquid Chemicals

Hazard

Design considerations

Chemical exposure to operator

Secondary containment able to hold a minimum of 110 percent of the stored chemical volume Exhausting of chemicals Leak sensors that are part of a hard-wired safety system Interlocks on access points to ensure depressurization and shutdown of moving equipment Barriers or electronic monitoring for point of operation hazards

Chemical exposure to maintenance personnel

Depressurization of chemical systems upon failure, interlock activation, or normal shutdown Transparent doors and view ports that allow visual inspection of the area before opening access panels Systems that allow automated purging and/or flushing of chemicals Locate system components that are accessible and easy to service

Equipment and component failure

Materials of construction that are compatible with chemicals present in system Design pressurized systems that are able to withstand 150 percent of the maximum foreseeable pressure or provide appropriately sized relief valves

Chemical leak

Use appropriate chemical storage containers Incorporate visual pressure indicators Design and build pressurized vessels and piping to recognized standards Verification system pressure prior to dispense of chemicals Incorporate normally closed valves on distribution lines Overfill sensors on tanks and baths Monitor for excessive flow on filling systems

Source: “SEMI S2-0703,” Appendix 3 (2003).

fabrication process. The material will be presented as moving from one wet clean to the next disregarding the intermediate process steps. In addition, multiple repetitions of the same wet clean will not be represented although this is often the case with today’s complex wafer fabrication techniques. 18.2.1

Front End-of-Line Processes Wafer Cleans. The pre-gate wafer clean, used before a wafer is subjected to the furnace, was the first wafer clean developed. The most common process used for pre-gate is the RCA clean developed by Kern and Puotinen.12 Since the 1970s when the RCA clean was developed, there have been a number of variants of the RCA clean as well cleans that completely depart from the RCA chemistries. The RCA clean process utilizes the chemical mixtures of Standard Clean 1 (SC1) and Standard Clean 2 (SC2). The original RCA process steps are—SC1, ultrapure water, SC2, ultrapure water, and dry. SC1 is a mixture of NH4OH/H2O2/H2O in a ratio of 1:1:5 at 70 to 80°C. It primarily removes organic residues and particles by forming and dissolving hydrous oxide films. SC2 is a mixture of HCl/H2O2/H2O in a ratio of 1:1:6 at 70°C. It removes alkali metal and hydroxides with the exception of Cl residues.13 Modified RCA processes have been developed to deal with specific problems that have been encountered as the importance of removing smaller particles increases. These modifications typically add additional process steps. One additional step that is often added after SC2 is dilute HF (DHF) in FEOL because the thin oxide left on the wafer surface after the traditional clean cannot be tolerated. This “HF last” process removes the thin oxide and leaves the wafer with a hydrophobic surface that requires special attention in the subsequent rinse and dry steps. A DHF step is also utilized before SC1 when the process is modified to include sulfuric peroxide (SPM) as the initial step. SPM is used to remove bulk organic material and consists of H2SO4/H2O2 in a ratio of 4:1.14 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.9

WET CLEANING WET CLEANING

18.9

Other modifications involve the dilution of RCA chemistries that result in lower costs by a combination of reduced chemical consumption, decreased effluent treatment, and less environmental impact. Dilute RCA chemistries have been tested at numerous concentrations including a ratio of 1:20:100 (NH4OH/H2O2/H2O) for SC1 with comparable particle removal capabilities.15 This mixture is optimal because experimental studies have shown that the high pH (less than 9) is required for particle removal as well as minimizing the silicon etch rate.16 A diluted SC1 chemistry with a ratio of 1:1:20 can also be used. This is done to reduce the hydrogen peroxide concentration that is considered a potential source of metallic contamination because of its propensity to deposit metals on a wafer surface in high alkali solutions. It maintains the thermal stability of the standard solution and therefore maintains a similar bath life. A modified and dilute version SC2 can also be used. This version is a mixture of HF/HCl/H2O in a ratio of 1:1:200. This solution is quite effective in removing metallics and eliminates the need for an HF last step. Typically this modified and dilute SC2 treatment is followed by a step of H2O/O3 to provide a passivated oxide surface to inhibit particle attraction.17 A modified approach to the “full” RCA clean (SPM -> HF -> SC1 -> SC2) is the IMEC∗ clean.2 This replaces SPM with a mixture of H2SO4, O3, and H2O. This mixture has a longer bathlife than SPM. The three remaining chemical steps are replaced with a single chemical step of HF/HCl/H2O followed by an ozonated water (H2O/O3) step. Post-Dry Etch or Ash Residue Removal. FEOL post-dry etch ash residue removal is accomplished using standard cleaning techniques. This process step comes after the bulk of the photoresist has been removed by exposure to a plasma etch. There are two types of photoresist—positive and negative. A positive photoresist is most widely used today and is easy to remove using chemicals such as SPM and/or APM. A negative photoresist is seldom used in current semiconductor manufacturing given its inherent difficulty to remove. Metal Removal. Wet cleaning is also traditionally required after metal silicide barrier formation due to the presence of unreacted metal. In the case of cobalt or nickel silicide, the unreacted cobalt (or nickel) and titanium nitride (TiN) must be selectively removed from the silicide surface. These materials are typically removed with a mixture of H2SO4 and H2O2 (SPM) in a ratio of 6:1. This is followed by a rinse and then by APM and then a final rinse. The complete removal of these materials is critical in order to reduce yield loss due to open contacts from Ti or Co contamination.18 Post-CMP Clean. FEOL post-chemical mechanical planarization (CMP) cleaning is a very challenging cleaning process that needs to be independent of the polish used in CMP and does not react with the materials on the wafer. Two common ways to perform post-CMP cleaning of thermal oxide wafers are using a scrubbing system or a megasonic system. The scrubbing system typically uses DI water to clean the wafer but brushes have been found in some cases to induce defects on the wafer. A megasonic system using SC1 produces the same cleaning efficiency as the scrubbing system without the induced defects. From a cleaning standpoint, the megasonic system is superior to the scrubbing system. However, concerns with damaging sensitive device structures make the use of megasonics challenging. Although the scrubbing system does induce defects, it does not use any chemicals. If the induced defects can be tolerated, that is, if they do not have a significant effect on yield, the scrubbing system is also a viable solution.19 Backside Cleans. After certain steps in FEOL processing it is necessary to remove contamination from the backside of the wafer. The contamination typically comes in two forms. The first involves the presence of ionic contamination that can be considered as potential killer defects. The second involves concerns over “litho hot spots” (addressed later in the chapter). In cases where there is a possibility of transference of these defects to the front side wafer surface, it is necessary to clean the wafer backside. This is typically completed with an HF-based chemistry to remove newer materials such as high-k dielectrics (e.g., HfO2, ZrO2, and Ta2O5). * IMEC (Interuniversity MicroElectronics Center) is Europe’s leading independent research center in the field of microelectronics, nanotechnology, enabling design methods, and technologies for ICT systems.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.10

WET CLEANING 18.10

WAFER PROCESSING

18.2.2 Back End-of-Line Cleaning BEOL wafer cleans pose additional complexity issues because of the addition of interconnect metal. Special chemistries have been developed for wet cleaning in order to minimize the negative effects that the FEOL clean chemicals have on the metal layers. Post-CMP (Cu). Post-copper chemical mechanical polish (CuCMP) clean is an important step to remove the CMP slurry from the wafer prior to further processing the semiconductor device. The most common method to remove the slurry from the wafer is with a brush cleaning system. Sonic removal systems are gaining in acceptance and have shown to have a similar or better removal efficiency than brush systems and work with very dilute chemistries.20,21 The primary adhesion force in post-CuCMP are electrostatic forces. HF-based chemistries are typically used in post-CuCMP but have been found to create issues with corrosion in the copper and also promote the reattachment of certain types of slurry particles.22 Post-Etch Residue Removal. BEOL post-dry etch or ash residue removal is accomplished using a wide range of chemicals depending on the type of resist used and how the bulk of it is etched away. Some typical chemistries used for this are given in Table 18.3. The current trends are moving toward dilute acid chemistries because of the cheaper cost for both the initial chemical and subsequent waste processing. They also have a significant impact on environmental and health issues. Researches are investigating the use of chemistries with ozone gas diffused into water and some inorganic chemicals as a method of removing resist residues.23 The aforementioned chemistries are typically applied using a spray or chemical dispense system. Backside and Bevel Cleans. BEOL backside and bevel cleans (see Fig. 18.3) are used to remove particles and films that can either diffuse into the wafer substrate or cause handling equipment contamination issues. TABLE 18.3

Typical Polymer Removal Chemistries

Family of chemistry Quaternary based

Manufacturer Dupont-EKC Air Products JT Baker Nonproprietary ATMI

Fluoride based

Air Products

Dupont-EKC

ATMI Mitsubishi Gas Chemicals Amine based

Dupont-EKC Air Products

Inorganic

Nonproprietary

Name EKC-525 EKC-505 ACT-K101 REZI-28 TMAH ESC-775 CE-15 NE-12 NE-14 NE-88 NE-89 EKC-630 EKC-640 EKC-650 N.O.E. ST-200 series ELM-C30 series EKC-265 EKC-270 ACT-935 ACT-970 DHF DSP (dilute sulfuric peroxide)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.11

WET CLEANING WET CLEANING

18.11

Film 2 Film 1 Si

The second film extends beyond the edge of the underlying film. That is to say it goes further over the edge of the wafer than the underlying film. During subsequential thermal stress, film 2 cracks and forms flakes. The mechanism may be related to a slight thermal mismatch between films with the underlying film shrinking more than the upper film and becoming brittle. The resulting cracked film forms flakes that become a major defect issue or can also cause liftoff of later deposited films. FIGURE 18.3

Bevel clean.

Sacrificial barriers are removed from the backside with specific chemicals that remove the film and any particles without attacking the underlying material. Bevel cleans remove particles and films from the bevel and a small amount from the front side of the wafer to ensure that the handling equipment is not contaminated and the films on the front side of wafer have a symmetric transition to the wafer substrate. The root cause of the problems is related to a mismatch in the deposition of different films in the film stack. Many times the films are not deposited across the wafer to the same distance from the wafer center. The result is that some films overlap the bevel edge of the wafer and consequently can break off later in the process integration flow, causing defects. The previous discussion of cleans is by no means an exhaustive list of all wet cleans and as new materials are integrated into the manufacturing process and new design rules are adopted, additional cleans will be introduced to the production cycle. A key point that has be left out of this discussion on wet cleans is drying. This is a separate technology from the removal of the particles, which is a crucial step in the manufacturing process. However, it should be noted that drying technology is becoming a key concern for engineers engaged in cleaning and integration of effective drying is a challenge for wet cleaning equipment vendors.

18.3 WET CLEANING EQUIPMENT TECHNOLOGY The machines used to apply the wet chemicals to the semiconductor wafer can be divided into three major groups—batch tank, batch spray, and single wafer. Each provides a unique way of applying the chemistries discussed in the previous chapter to the wafer surface. In this section, each group will be addressed by the technology applied along with the benefits. 18.3.1

Batch Tank A batch tank machine is typically referred to as a wet bench. It exposes one or two cassettes of wafers to a single chemistry at one time. A wet bench will have a number of tanks linearly arranged for use with different chemicals. The tanks can be used just for chemical application or for chemical application and rinsing. Usually only one chemical may be used in each tank. Chemicals are either recirculated, typically with filtration, or used once. Specialized modules are also used such as a tank equipped with a sonic cleaning device or specialized wafer dryers. The benefits of a batch tank system are its ability to Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.12

WET CLEANING 18.12

WAFER PROCESSING

process a large number of wafers at a time, to ensure consistent process chemicals for all wafers in a lot, and flexibility in the number of process steps and diversity of chemicals. 18.3.2

Batch Spray A batch spray typically exposes one to four cassettes of wafers to a specific chemistry at a time. The cassettes are rotated with fixed nozzles applying the chemicals. The chemicals can be recirculated or used once. These systems have the benefit of high throughput, consistent wafer-to-wafer results, and flexibility in mixing chemistries at the nozzle.

18.3.3

Single Wafer Single wafer is a wide classification that includes immersion, spray, scrub, sonic, and dispense cleaning systems. The continuing improvement to smaller and smaller line widths creates the need for better process uniformity across the wafer surface and lower defect density. Single wafer offers faster cycle times than traditional batch processes and incorporates process monitoring that is recorded on a per wafer level (a vast improvement over per batch).24 Single-wafer immersion systems are based on the concept of larger wet benches. Single-wafer spray systems utilize a moving or static spray nozzle(s) and a rotating or static wafer. The scrubbing system can be implemented into a spray machine or can utilize a chemical dispense on the cleaning brushes. Sonic devices are used with rotating wafers and a chemical dispense system. Chemical dispense systems are used on rotating wafers. A novel dispense system utilizes a “Bernoulli chuck” that ensures that only one side of the wafer is treated with a chemical at a time.

18.4 FUTURE TRENDS AND CONCLUSIONS In addition to the standard processes and technologies discussed previously, there are some emerging technologies that are being more accepted in wafer manufacturing. Supercritical fluids are being evaluated for such diverse areas as FEOL critical cleans and BEOL photoresist removal. Pre-lithography backside cleans along with silicon stress relief and silicon thinning are being added to the manufacturing flow to address specific technological issues that have arisen. 18.4.1

Supercritical Fluids Supercritical fluids are compounds at a temperature and pressure above their critical point. They have long been used as solvents in commercial applications such as the extraction of caffeine from coffee and essential oils from plants. Their unique properties resemble both gas and liquid phases specifically in the area of viscosity (gas) and density (liquid). A promising supercritical fluid is propylene carbonate (referred to as PCO3) that is mixed at 5 vol. percent with CO2. This has shown to have no negative effect on the metallization present on wafers.25 A hypothesis to describe the mechanism of removal is a combination of photoresist swelling by diffusion of the supercritical fluid into the polymer matrix followed by a debonding of the film caused by rapid depressurization then followed by a fluid flow that clears away the removed film. This method of removal offers an environmentally benign process for the complete removal of a photoresist.26

18.4.2

Pre-lithography Backside Clean Pre-lithography backside cleans are becoming important as linewidths are decreased. The smaller linewidth creates a smaller focus window that can be impacted by wafer bow due to film stresses on the backside of the wafer, also known as “litho hot spots” (see Fig. 18.4). This clean also reduces the likelihood of cross contamination from the lithography chuck by removing the contamination from the backside of the wafer prior to placement on the chuck. The process uses

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.13

WET CLEANING WET CLEANING

18.13

Silicon Oxide Poly Oxide Nitride

Warped wafer

Particle ∆ DOF

FIGURE 18.4

Lithography hot spots.

a two-step chemical treatment. The first chemistry is HNO3/H2O. It is used to oxidize the metals found on the backside of the wafer. The second step is a chemical mixture of HF/H2O at a ratio of 1:10 that attacks the oxidized elements and provides for uniform removal of a thin layer of SiO2 from the backside of the wafer.27 18.4.3 Backside Silicon Removal As the device complexity increases, the stresses on the wafer also increase making the silicon stress relief process an important part of the wafer manufacturing flow. Wet chemical etching of silicon to remove stress involves the removal of 8 µm of silicon from the backside of the wafer. This leads to stronger wafers for post-grind processing, defect-free backsides, stronger die, easier handling and packaging, and an improved backside adhesion surface. This process is typically accomplished using a single-wafer chemical dispense system with a Bernoulli chuck.28 Wet cleaning processes are complex and essential steps in semiconductor manufacturing. As the feature size decreases, the effect of contamination on device yield increases.29 In order to maintain or increase yield, wet cleaning processes need to be continually improved and new technology must be integrated into the processing equipment.

REFERENCES 1. Bowling, A., B. Kirkpatrick, T. Hurd, L. Losey, and P. Matz, Solid State Phenomena, Vol. 92, pp. 1–6 (2003). 2. Burdick, G., N. Berman, and S. Beaudoin, Journal of The Electrochemical Society, Vol. 150 (10), p. G659 (2003). 3. Menon, V., “Particle Adhesion to Surfaces: Theory of Cleaning” in Particle Control for Semiconductor Manufacturing, R. P. Donovan (ed.), Marcel Dekker, New York (1990), pp. 362–365. 4. Ibid., pp. 365–366. 5. Ibid., p. 366. 6. Ibid., pp. 368–369. 7. Busnaina, A., H. Lin, N. Moumen, J. Feng, and J. Taylor, IEEE Transactions on Semiconductor Manufacturing, Vol. 15 (4), pp. 376–377, (2002). 8. Menon, V., “Particle Adhesion to Surfaces: Theory of Cleaning” in Particle Control for Semiconductor Manufacturing, R. P. Donovan (ed.), Marcel Dekker, New York (1990), p. 360.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH18.qxd

04/04/2005

19:58

Page 18.14

WET CLEANING 18.14

WAFER PROCESSING

9. Burdick, G., N. Berman, and S. Beaudoin, Journal of The Electrochemical Society, Vol. 150 (10), pp. G659–G664 (2003). 10. Burdick, G., S. Eichenlaub, N. Berman, and S. Beaudoin, Solid State Phenomena, Vol. 92, pp. 135–138 (2003). 11. Busnaina, A., H. Lin, and N. Moumen, Advanced Semiconductor Manufacturing Conference and Workshop, IEEE/SEMI, pp. 328–329 (2000). 12. Wolf, S., and R. Tauber, Silicon Processing for the VLSI Era: Process Technology, Vol. 1, Beach, CA, p. 516, (1986). 13. Jones, S., Integrated Circuit Technology Introductory Material, Process Integration and Unit Step Processes, ICKnowledge.com, pp. 126–127 (2003). 14. Jones, S., Integrated Circuit Technology Introductory Material, Process Integration and Unit Step Processes, ICKnowledge.com, p. 127. 15. Lin, F., S. Ajuria, P. Schay, M. Masquelier, R. Sanders, and J. Smith, Proceedings of the Third International Symposium on Ultra Clean Processing of Silicon Surfaces, Acco Leuven, Amersfoort, p. 180 (1996). 16. Itano, M., F. Kern Jr., M. Miyashita, and T. Ohmi, IEEE Transactions on Semiconductor Manufacturing, Vol. 6 (3), pp. 262–266 (1993). 17. Ridley, R., Sr., T. Grebs, J. Trost, R. Webb, M. Schuler, R. Longenberger, T. Fenstemacher, and M. Caravaggio, 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 235–242 (1998). 18. El-Sayed, A., S. Collins, D. Frystak, and L. Loewenstein, Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEE/SEMI, pp. 148–153 (2003). 19. Maumen, N., M. Guarrera, C. Piboontum, and A. Busnaina, 1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 250–253 (1999). 20. Busnaina, A., H. Lin, N. Moumen, J. Feng, and J. Taylor, IEEE Transactions on Semiconductor Manufacturing, Vol. 15 (4), p. 381 (2002). 21. Fyen, W., R. Vos, I. Teerlinck, S. Lagrange, J. Lauerhaas, M. Meuris, P. Mertens, and M. Heyns, Proceedings of ISSM 2000, The Ninth International Symposium on Semiconductor Manufacturing, p. 418 (2000). 22. Fyen, W., R. Vos, I. Teerlinck, S. Lagrange, J. Lauerhaas, M. Meuris, P. Mertens, and M. Heyns, Proceedings of ISSM 2000, The Ninth International Symposium on Semiconductor Manufacturing, pp. 415–418 (2000). 23. Ma, S., R. Parker, R. Kavari, I. Leal, D. Boyers, and J. Cremer, Jr., Proceedings of the IEEE International Interconnect Technology Conference, pp. 46–48 (2000). 24. Singh, R., M. Fekhruddin, and K. Poole, IEEE Transactions on Semiconductor Manufacturing, Vol. 16(2), pp. 96–101 (2003). 25. Rubin, J., L. Davenhall, J. Barton, C. Taylor, and K. Tiefert, Electronics Manufacturing Technology Symposium, 1998, pp. 308–314 (1998). 26. Rothman, L., R. Robey, M. Ali, and D. Mount, Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop, pp. 372–375 (2002). 27. Lysaght, P., I. Ybarra, T. Doros, J. Beach, J. Mello, G. Gupta, M. West, and D. DeBear, 1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (1999). 28. Hendix, M., S. Drews, and T. Hurd, 26th IEMT Symposium—PackCon 2000, pp. A1–A7 (2000). 29. Hattori, T. (ed.), “Ultraclean Surface Processing of Silicon Wafers,” pp. 5–7 (1995).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

P

●

A

●

R

●

T

●

3

FINAL MANUFACTURING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.2

FINAL MANUFACTURING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.3

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 19

INSPECTION, MEASUREMENT, AND TEST Donald W. Blair Agilent Technologies San Diego, California

19.1 INTRODUCTION—OVERVIEW ON TESTING EQUIPMENT 19.1.1 The Need for Tests Why test at all? The simple answer to this question is to increase the confidence of the IC manufacturer that the device-under-test (DUT) will meet its specifications listed in the device data sheet and will perform as designed in its end application. Semiconductor manufacturing processes are not perfect, therefore the good parts need to be sorted from the bad and testing assures customer quality. Test also plays another, equally important role—that of quantifying and identifying the manufacturing defects so they can be reduced and the yield increased. Not only do manufacturers want to ship only good chips, they want to maximize the yield of good chips rather than scrap. By increasing yield, defects are decreased and the probability of a bad part escaping the test is reduced. Yield is crucial to the profitability of a fab since it determines how much revenue in the form of good chips, can be obtained for the cost of producing a wafer. Furthermore, yield, along with cycle time, sets the capacity of the fab. Thus products, manufacturing processes, and wafer fabrication facilities all go through yield improvement cycles where designs, procedures, and equipment settings are adjusted to decrease the rate of defects. The rate of this yield learning determines the return on the investment in equipping the fab and developing the manufacturing process since it determines the rate at which capacity can be ramped to match the peak demand before the demand inevitably falls. That is, the rate of yield learning determines a fab’s ability to hit its product’s market window. Fast yield learning depends on the ready availability of yield and defect information, and semiconductor manufacturing tests are one of the prime sources. Semiconductor manufacturing has been advancing rapidly for many years as exemplified by the steady reduction in the minimum feature size with each process generation or node. This advance also means that the defect density, and yield, of any given node is also improving rapidly. By the time a node has been obsoleted by newer nodes its yield can be so high that its manufacturing process can be very well understood and controlled. Why does the electronics industry keep using newer, smaller dimension processes that consequently are less understood, less in control, and have higher defect densities? The first answer obviously is performance—smaller devices and denser circuits operate faster. Therefore, manufacturing tests increase product performance by allowing the product to use a higher performance and lower quality process while maintaining acceptable customer quality. The second answer is cost. A denser

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

19.3

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.4

INSPECTION, MEASUREMENT, AND TEST 19.4

FINAL MANUFACTURING

process enables a smaller chip to perform the same function thus enabling more chips to be built on a wafer and partially offsetting the effect of the higher defect density on yield. The economics usually work out such that the difference between the higher price commanded by the higher performance chip and the lower wafer cost per chip more than makes up for the cost of the test and reduction in yield. Therefore, manufacturing tests decrease product cost again by allowing the product to use a higher density and lower quality process while maintaining acceptable customer quality. An IC design-to-manufacturing process is shown in Fig. 19.1. Since in this sequence, the later a defect is found after it is created, the more the wasted effort and material, it is advisable to perform tests at each level of assembly. However, each test instance needs only test for defects that were introduced by the immediately preceding assembly operation or those that escaped the previous test instances, for example, due to accessibility or environmental restrictions. The first opportunity in the manufacturing flow to test the product chip is when the wafer exits the fab. Usually, as much as can be tested with the limited signal and power integrity provided by the probe contacts, is tested at a probe, also called a wafer test. These are usually low-frequency and low-sensitivity catastrophic, functional, and structural measurements. After the chip has been assembled in its package it can be connected to the tester as it is in its end use so that its functional performance can be fully verified and assembly defects can be detected as well. This is called a final or package test. When an extra level of reliability is required, the packaged chips may also be stressed by voltage and temperature in an operation called burn-in prior to the final test. Finally, the customer may perform an incoming inspection before inserting the IC into its end application. As with processes, products and their tests go through learning cycles. As tests and user data are accumulated, product design problems—often process margin problems—will be discovered and addressed requiring changes to the tests. The tests themselves will be examined for effectiveness and efficiency, resulting in ineffective test steps being deleted and other ones being added in an effort to reduce the time and instruments required to achieve the target level of quality. Such efforts may continue to reduce the cost of tests or increase the product quality as the product is redesigned and the wafer fabrication process matures. Clearly, the common criticism of manufacturing managers that tests add no value, because it does not build product functions, is false. Tests add performance and increase quality, both of which increase prices and decrease costs. These are certainly value additions. 19.1.2 Errors That Tests Can Find A defect is a physical anomaly within the IC, which can be caused by impurities such as dust or improper manufacturing processes. Defects cause electrical failures on the IC and logical failures or faults. A fault is a model of a defect’s effect on the circuit. Fault models are the basis of fault coverage. Fault coverage is a methodology used by IC manufacturers to determine the likelihood of finding a particular fault with a given set of patterns. Academic and industrial researchers struggle with

Final assembly and test

Wafer sort

Burn-in

Wafer PS

Final PS

PS

• Chip design and characterization Wafer prober interface to test FIGURE 19.1

Burn-in oven

IC package handler interface to test

Incoming PS

• Ship to customer

IC concept to customer.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.5

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.5

the very real distinction between these because, though defects are the reality, circuit model-based electronic design automation (EDA) tools can only deal with faults, and good fault coverage can still result in poor defect coverage. The stuck-at fault is the most widely used fault model in digital designs because it is the easiest to use but often not the most relevant. Other digital fault models are used as well—bridging, transition time, and path delay. The “stuck-at fault” term means a node or logic gate is stuck at either a “0” or “1” level. This stuck-at condition must now be propagated to the output of the device for observation. If it can be observed it is called a detected fault. The goal is to cover the stuck-at detectable faults to 95 percent or higher. This in combination with other forms of tests that will be explored later, will provide coverage close to 100 percent. There are many reasons that a fault may not be detectable. Untestable faults are faults that will not propagate to the device’s output because of the device’s design. Undetected faults are those that cannot be detected in a reasonable amount of time, usually due to a massive fan in or fan out in the circuit design. The untested fault is one that the fault analysis tool did not evaluate. Understanding and using all these IC fault types along with a high-performance analysis tool, IC manufacturers can design and build high-quality circuits. There are also other indirect methods of testing, such as IDDQ, which can catch these kinds of errors without direct logic analysis. IDDQ will be described more in the section “Functional, Structural, and Defect-Based Tests.” The fault coverage model relies on testing to realize its potential to catch these physical imperfections. Other error types that can be detected by testing are design errors or package errors. Design errors can result from the merging of designs from different people or tools. Package errors may occur in assembling the die into the package or connections to the IC pins. There is also a trend to package multiple die in one package, usually to save cost. There is a process called known-good die (KGD) in which all the die are fully tested to the level that would normally be done at the final test before assembly, saving the cost of scrapping, packaging, and other potentially good die in the event of a bad die being assembled in the multichip package. 19.1.3 The Importance of Tests Throughout the Product Lifecycle In today’s semiconductor market, product lifecycles are shrinking as new products are introduced and obsoleted at an unprecedented rate. The product lifecycle can be characterized by three major phases, each with its own challenges and goals—time-to-market, time-to-volume, and time-to-profit as seen in Fig. 19.2. Throughout the lifecycle and in each phase, testing plays a key role by ensuring the performance, functionality, and quality of the devices. Time-to-Market. To be successful, a product must meet its market window, which is open for only a limited time. A delay in market entry means the product will have a shorter lifetime, resulting in a loss of revenue or even complete loss of business to competitors who already have products in the market. From a test perspective, this means the test plan for a new device must be developed as quickly as possible, yet still must meet the fundamental goal of characterizing the device’s performance and verifying its functionality. Time-to-Volume. After rushing the device to market, the next step is to ramp up production, bringing the device into high-volume manufacturing. During this phase, the manufacturing process is automated and refined to meet the volume expectations of the market. The test results in manufacturing must correlate to the testing done during the design validation and device characterization stages. It is also important for test results to be repeatable over time and across different test cells. The Automated Test Cell. SEMI* standards provide a helpful framework for defining the need for an automated test cell as opposed to simply a stand-alone automated test system. SEMI Standard E40-0703 defines a process agent as “an intelligent system within a factory which is independently

*

SEMI, http://www.semi.org/.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.6

INSPECTION, MEASUREMENT, AND TEST FINAL MANUFACTURING

Evaluation and purchase




Volume

19.6






Needs assessment Requirement defined Test system strategy Solution definition Planning Development

Time-tomarket




Be ahead of market window Characterize device Win design-ins to application

Time-tovolume

Time-to-profit




Ramp production







Automated test cell Correlation to standard Improve repeatability Reduce guardband













Maturity in the market

Maximize profitability Minimize COT Overall equipment efficiency Best business model

Test system delivery Time

FIGURE 19.2

Test adding value in all product phases.

capable of providing manufacturing value added to material.”* A stand-alone test system alone is not capable of meeting this requirement, as the test system alone is not capable of handling and moving the devices through test process steps. In order to do that, the test system needs to be integrated with a materials handling system. The combination of a test system and a materials handling system meets the SEMI definition of a processing agent, and is commonly called a test cell. Accomplishing the integration of a test system with a materials handling system requires consideration of several important software, electrical, and mechanical interfaces internal to the cell. The device electromechanical interface provides a connection between the device and the tester measurement resources. This includes a DUT board, plus a device contactor for a package test or a probe tower and a probe card for the wafer level test. The tester/materials handler mechanical interface provides a solid physical docking connection between the tester and the materials handler. The tester/ materials handler software interface provides a software communications path to synchronize the movement and presentation of a device and the tester program execution. There are also major interfaces outside of the cell. The human interface provides a way for the human to operate the test cell. Lastly, the factory host interface provides a software connection to the factory host. This allows program and processing of data information to be provided from a factory controller. Correlation and Repeatability. In order to verify a manufacturing test process, the results must be repeatable, statistically significant, and able to correlate to other systems performing the same test functions. Repeatability verifies the results will be the same to within a margin. The statistical significance of the results allows the use of a common process control statistical analysis to prove the manufacturing test process is stable. A stable system can then be correlated with other stable systems to allow material to be processed across several systems, or even across different factories. Correlation allows comparison and verification of the results across test processes and has two major components.

*

SEMI E40-0703, Standard for Processing Management.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.7

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.7

First, the raw stimulus and measurement performance of two or more test systems need to be comparable. In this case a stimulus/measurement standard is run on each system and the raw performance of the systems is compared. The second component of correlation is the device performance. The measured performance of the actual device should have a consistent result on two or more platforms. Variations in either of these measures identify if the system or the device is drifting or is erratic with respect to the last sample. Time-to-Profit. As the device continues to ship in volume and approaches maturity and obsolescence, profitability is the key concern. The goal during this phase of the product lifecycle is to minimize manufacturing costs, including test costs, while maintaining reliable quality and product delivery to customers. Defining Cost-of-Test (COT). Since COT can make up 3 to 10 percent of the total cost of manufacturing, driving down COT is key to reducing manufacturing costs and ultimately to growing profitability. A simple definition of COT is the “test cost per good part.” To determine this metric, the yearly test costs associated with a test cell are divided by the number of good devices processed by the test cell during the year. The major cost factors include acquisition costs, cost of the test equipment, floor space, and yearly recurring costs such as labor, utilities, maintenance, support contracts, spare parts, and consumables. The number of good devices per year will depend on the test yield, throughput of the test cell and utilization of the test cell. SEMI Standard E35* provides a comprehensive look at the costs associated with testing. Overall Equipment Efficiency (OEE). SEMI Standard E58† provides a good basis for understanding the OEE metric and defines the availability and utilization that are important components of OEE. Availability is a straightforward measure of the percentage of the total manufacturing time, typically some part of a 168-h week, that a test system is able to perform its intended function. A number less than 168 h is used since in a typical manufacturing operation, the system is assumed to be unavailable for maintenance and other nonproduction use for some portion of the week. Utilization takes availability a step further; it is a measure of the percentage of the total manufacturing time that the system actually performs its intended function. Finally, OEE takes another step forward and measures how efficiently the system is performing when it is being utilized. For example, if a test system is scheduled for 150 of 168 h in a week, and is actually available for 100 h, its availability is 100/150 = 67 percent. If it is actually used to test devices for 75 h, the system is 75/150 = 50 percent utilized. If the test system is expected to produce 10,000 good parts while it is utilized, but due to system problems can only produce 8000 good parts, then the system OEE is 50 percent × 8000/10,000 = 40 percent. From this analysis it can been seen that OEE actually accounts for device yield performance by looking at the expected good parts produced and not the total parts tested. 19.1.4 Business Models In the past, semiconductor manufacturers or integrated device manufacturers (IDMs) used a business model where they owned and controlled all the processes and equipment in the vertical market segment required to design, develop, produce, test, package, and ship devices to their customers. This model requires a large amount of capital and human resources and tends to favor large, well-established companies. A new model has emerged, for a number of reasons, which segments all these different operations among many companies. This model is called the subcontract manufacturing (SCM) model. In this new model, there are two main subdivisions—the design house that implements the IC design part and the foundry that does the fabrication, packaging, and testing of the silicon. This model has a significant shift in expenses, the design house having a significantly lower capital outlay expense than the foundry. This lower capital expenditure model also fueled a number of startup IC design houses. * †

SEMI E35-0701, Cost of Ownership. SEMI E58-0703, Automated Reliability.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.8

INSPECTION, MEASUREMENT, AND TEST 19.8

FINAL MANUFACTURING

Both are viable business models; however the SCM model has been growing at a faster rate than the IDM model. The value that test vendors can add to the design house is expertise on testing in general and their tester platforms, more specifically, so that a test program can be developed in parallel with foundry services. The value that the test vendor can add to the foundry is having a diverse geographic network for equipment maintenance and support. Foundries can also supply test development services.

19.2 FUNDAMENTALS OF TEST EQUIPMENT AND MANUFACTURING AUTOMATION SYSTEMS 19.2.1 Linking Test to the IC Manufacturing Process IC manufacturing processes are achieving smaller geometries, faster speeds, and lower operational voltages, and this additional complexity has the potential to lower yields and make yields less consistent. By taking electrical measurements of specific test structures, the physical properties of the manufacturing process can be extracted independent of the products it produces. These measurement results can then be used to determine if the test devices are physically as they were designed and how the process parameters compare to target values. It is much simpler to extract the physical parameters from electrical measurements than to make actual physical measurements at the small geometries of a modern IC process. DC parametric tests are commonly used in the design and manufacture of semiconductor wafers as shown in Fig. 19.3. This figure shows various steps in the design and production of new ICs, and the dashed line boxes show how the parametric test data are used. In the lab, trial wafers will be made to evaluate new processes and device structures. These test wafers typically do not contain any product die, but consist exclusively of parametric test modules (PTMs) or test element groups (TEGs). These wafers contain many basic components such as transistors, diodes, resistors, capacitors, conductive traces, and other test structures. At first, there are a large number of these devices that have different device geometries and process parameters. The dc parametric measurement data are used to understand, target, and characterize the process by calculating the physical characteristics

New device design

New process design Feedback

Lab

Trial wafer-process/device/reliability evaluation Transfer new process/device to production line

Production line

Trial wafer-process/device evaluation

Change process for yield enhancement

Function evaluation Data correlation Production wafer-process/reliability monitor Wafer test Package and final test

FIGURE 19.3

What are dc parametric tests used for?

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

20:00

Page 19.9

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.9

from the electrical data. Once the process has been developed to the point where its performance, reliability, and yield targets have been achieved as verified by using parametric test data, the product die can be added and the process can move into the pre-production phase. The PTM areas are then significantly reduced or removed, with the product die taking their place. For a well-established process in full production, it is frequently possible to eliminate the PTMs altogether and to have the parametric test structures reside in the scribe lines between the die. The number of measurements is also usually reduced since these impact the manufacturing time, but some dc parametric measurements are still done to ensure that major process parameters are on track. Five basic measurements and their impact on IC manufacturing processes are shown in Fig. 19.4. Five Basic Parametric Tests Resistivity tests monitor the doping, diffusion, and deposition processes that form conductive layers. A van der Pauw structure is typically used to separate the effects of resistance in the measurement instrument from the actual resistance of the layer under testing. Current is passed between two corners of the van der Pauw and voltage is measured at the opposite two corners. The corners can also be switched around to compare uniformity. Continuity/bridging tests monitor the lithography, deposition, etching, and metallization processes. These tests utilize serpentine or finger pattern structures where bridging and continuity are tested on the conductive lines (metal line/polysilicon layers). Leakage current/breakdown voltage tests monitor the oxide/diffusion and ion implant processes. When leakage currents are large, usually implying a process problem, this can be investigated by comparing the rectangular structure to the multiple-edge structure; both of which have the same area. Capacitance-voltage (C-V) tests monitor the oxide/diffusion and ion implant processes. For example, on a metal oxide semiconductor (MOS) capacitor on a p-type wafer, as the gate bias is made less negative, the MOS capacitance will be a certain value, C (oxide). At a point where Vgate is zero, a depletion region forms in the gate area and grows, adding C (diffusion). At a certain point, adding more voltage to Vgate will not add any more capacitance and it stays at a fixed level. C-V measurements yield valuable information on the quality of the gate dielectric for MOS transistors.

Resistivity SMU1

Continuity/bridging

I-V measurement

VM1 + V −

I

SMU2

MOSFET subthreshold test

Id

VM2

Van Der Pauw

Serpent pattern

Ileak 1pA

Finger pattern

V′gS

Vth Vgs

Measurement circuit Source

Gate

L W

0V

Substrate (<0.1 V)

Var1 Drain

Geng(SMH)_CH19.qxd

+V−

4-point resistor

Leakage/breakdown

Interlayer continuity contact strings

A/V

C-V measurement

A/V Accumulation Vg<0

Area

FIGURE 19.4

Vd

0V

Interlayer bridging

Isolation edge effects

A

Edge

Cox

Depletion Vg~0 Cox Cd

Inversion Vg>0 Cox Cd

The five basic parametric tests.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.10

INSPECTION, MEASUREMENT, AND TEST 19.10

FINAL MANUFACTURING

Only C-V measurements can supply electrical oxide thickness, flat-band voltage, and substrate impurity concentration information. Current-voltage (I-V) tests monitor the lithography, oxide/diffusion, etching, ion implant, and metallization processes. This is the most common parametric test. For example, a typical I-V measurement on a metal-oxide-semiconductor-field-effect transistor (MOSFET) would be to measure the subthreshold (turn off region), where typically the current measured should be a few femtoamperes (10−15 A). If the gate oxide were damaged, it would measure in the pico-to nano-amperes range. These kinds of current measurements need to be made with very high resolution and accurate resources while the fixturing and path routing are also challenges to keeping leakage paths low. A triaxial Kelvin connection is required to make these types of low-current measurements, where a center (actively driven guard) always matches the potential of the inner signal. This ensures that there is no leakage path between the measured signal and the outer ground shield. Combinations of these tests can provide feedback to all different IC manufacturing processes. Wafer-Level Reliability. As devices become smaller and new materials and structures are introduced into manufacturing, new reliability problems come into play. DC parametric testing of waferlevel reliability structures is an essential tool in characterizing the reliability of a fabrication process and verifying its compliance to its specifications. As an example, in deep submicron processes three common areas of concern areelectromigration, hot carrier induced degradation, and oxide integrity. Electromigration is a process in which current flow causes metal atoms in the interconnect layers to move, which over time causes voids, even gaps, in metal lines and extrusions that can short to adjacent lines. This can be evaluated with large currents applied at a certain temperature while measuring the resistance of the line over time. Hot-carrier-induced degradation is the degradation of Si-SiO2 interface due to hot electrons or hot holes generated by the highly intensified electric field along the channel. Testing for stability includes applying ac and dc stress while making parametric measurements and then comparing the shift of the measurements to nominal conditions over time. Thin oxide integrity—Over time, insulating oxides subjected to an electric field can break down due to a process known as time-dependent dielectric breakdown (TDDB) and cause catastrophic circuit failure. Measuring oxide integrity typically involves applying a constant voltage or current stress to an oxide and then checking the oxide leakage current over time to determine how much the oxide has degraded. Other oxide integrity tests include voltage ramp (VRAMP) and current ramp (JRAMP), where voltage and current are swept (respectively) until breakdown. From these measurements, charge to breakdown (Qbd) can be calculated. Factory Automation. DC parametric testing is used as feedback to the IC process during manufacturing. Measurements are made and semiconductor parameters are extracted and fed back to a computer monitoring the line. This is known as statistical process control (SPC) and a typical example is shown in Fig 19.5. SPC is a key to maintaining process control and improving yields and is one of the driving forces behind computer integrated manufacturing (CIM). Automation is important to SPC because SPC requires a vast number of measurement results to make the statistical analysis meaningful. This data can be collected over time and used to draw a trend chart. • Another important aspect of making this process control methodology work is setting standards so that the different pieces of equipment on the manufacturing floor can communicate with each other. The SEMI organization has set many industry standards* to define the message protocol and contents exchanged between the process host and tester controller workstation. These include: • • • •

SECS (SEMI Equipment Communication Standard) HSMS (high-speed message service) GEM (generic equipment model; equipment automation software) TSEM (testing specific equipment model)

*

SEMI E40-0304, Standard for Processing Management.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.11

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.11

LAN

RS-232C

PC

Process equipment

Host computer

PC WS

PC WS

WS

Data analysis LAN

DC parametric tester

Workstation

DC parametric tester

Process monitoring

FIGURE 19.5

Workstation

Functional testers CIM standards SECS I/II HSMS GEM TSEM

Statistical process control.

19.2.2 Common Concepts of Tests Some common test concepts for validating a design and detecting manufacturing defects will now be discussed. These concepts are independent of the particular test solution. Basic Overview. Initially, continuity from the silicon die to the outside pad or pin needs to be established, as well as short circuit checks. The part must have power and ground applied for it to function. Then certain static conditions need to be applied to prepare the device to perform its function; these are commonly called static or dc tests. A transient stimulus may be applied after which time a transient response is to be measured. This may simulate a transient condition in the end application or may be a quick test of its normal function. These are commonly called dynamic or ac tests. Once this response is measured, it needs to be quantified against a limit, a decision made as to whether it passed or failed the test and then the decision whether to go on testing or stop. In a production environment, when the device is judged good or bad, a physical disposition needs to be made. This is called “binning” the device because the device is physically put into a good or bad bin (device tubes are connected to the bins). There can also be the need to log the data that were measured and to perform statistical analysis on the data. Functional testing uses the device as it would be used in its end application and the device either works or doesn’t according to its designed function. A good example of this is digital logic that has logic “0” or logic “1” inputs and predefined outputs. If the outputs are not correct for the given inputs, the device is not functioning. Performance-based testing will test not only whether a part functions, but how well above the baseline limit it operates. An example of this is an amplifier that has a linear range of operation within which it works. Comparing two amplifiers, both may work but one may have a larger range of operation. Using Statistical Analysis. Manufacturing and measurement variations are both described by statistical distributions. The parameter that is commonly used to quantify the width of a distribution is the standard deviation, also known as sigma. It is common to set the high and low limits on a test

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.12

INSPECTION, MEASUREMENT, AND TEST FINAL MANUFACTURING

True test spec. without guardband New test spec. with guardband Measurement uncertainty

Probability

19.12

−5

Fail

−4

Pass

Fail

0 1 3 2 −3 −2 −1 Measurement standard distribution s

4

5

True distribution FIGURE 19.6

The concept of guardbanding.

parameter at the mean plus or minus respectively, three times the sigma measured on a sample of good parts. There will then only be a 0.27 percent probability of a part falling outside of these limits when the manufacturing process is behaving as it should. The variation of a process over time can be monitored and controlled by the concepts of SPC. The fundamental measure of process control is the coefficient of process variation (Cp) that equals (upper passing limit—lower passing limit)/ (6 × sigma). This parameter will represent how tight the distribution is compared to the limits. A large number is desirable, while it is generally accepted that a number less than two exposes a stability problem. Often more useful, because it measures how well the distribution is centered between the limits, is the coefficient of process capability, Cpk. For symmetrical limits Cpk = Cp × (1 − k) where k=

(specification target − mean) 0.5* (upper limit − lower limit)

For a six sigma quality program, Cpk should be greater than 1.5.* Measurement Variation, Limits, and Guardbanding. Often the value will vary from measurement to measurement due to a variety of reasons. This variation needs to be quantified in order to understand the stability of the test and where the test limits should be set. At the different phases in the IC concept to customer process, the test limits vary for many reasons. For example, at the wafer level, it is best to comb out as many failures as possible to improve profits, considering the 10X rule of cost. The 10X rule generally states that detecting and correcting faults costs an additional 10X at each successive step in manufacturing. It should also be taken into account that the packaging may alter some of the electrical characteristics and the limits have to be adjusted to take this into account. In addition, many companies do a random sampling of the lot for a process known as quality assurance (QA) where more testing may be done and the limits are made much tighter than in normal production. *

An Introduction to Mixed Signal IC Test and Measurement, Burns and Roberts, Oxford University Press, 2001, p. 630.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.13

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.13

Guardbanding is a process shown in Fig. 19.6, which adjusts the test limits to take the setup and measurement uncertainty into account. The SEMI organization has quantified this in the E35 * document. The goal is to eliminate the possibility of falsely passing a bad part, but it also has the undesirable effect of potentially failing a good part. High accuracy and low uncertainty are desirable so that the guardband can be reduced as much as possible thereby maximizing yield. Defining the Project. Developing a test program can be a complicated process and must be treated as a project. Formal project management rules should be used including developing a project definition with a timeline. 1. Defining the application development phases: a. The proposal phase defines the deliverables such as the hardware delivered, the test parameter list, software coding and debugging, production integration (wafer prober or IC handler integration, special operator interface, or data log needs), solution diagnostics, and project wrap up definition (items 2 to 6 in this section). The proposal phase requires an agreement from the IC design group. b. The design phase defines the test strategy and the design of the DUT board hardware. c. The implementation phase executes the design phase plans. d. The release phase is when the project is completed and released. 2. Acceptance criteria. The acceptance criteria defines how the list of deliverables will be demonstrated to be complete and within the specifications of the agreement. The mean, sigma, and correlation limits of the data need to be defined as well as the conditions under which they are taken. 3. Documentation of the project deliverables. A written explanation of the test including schematics of the circuit used on the DUT board for each test including test data, limits, and the statistical variations. This documentation will be used for future modifications and maintenance, and for new engineers to learn the test solution. 4. Training for the deliverables of the project. The training on how to run the program and correctly set up the hardware. The training could vary depending on the job function of the person operating the program. 5. Roles and responsibilities of the different parties. A roles and responsibilities definition makes it clear who is responsible for which deliverables and what specific knowledge is required. 6. Change management definition to this proposal. Since changes will inevitably happen, it is important to define up front how these changes will be handled. Each of the project deliverables should be put on a timeline with dependencies to the previous items noted. This plan incorporates the common elements of developing a test program—defining the DUT pins, configuring what test system resources are needed based on the DUT functionality, designing a DUT interface from the DUT to the tester resources, transferring and translating any EDA data that are applicable, writing and debugging the test program, data logging the results, further analyzing the data to look at the mean, sigma, and correlation to known good devices, developing a binning strategy, developing a diagnostic for the test solution, and documenting the project including training on the use of the solution. Common Test Parameters. Usually test parameters are as diverse as the end applications for which parts are designed. However there are some types of test parameters that are common to all devices. Continuity: Device pins are ESD-protected by a diode to ground and/or power. A current sink (−) is placed on the DUT pin while the ground or Vcc substrate is grounded. The resulting current turns the diode on and a diode drop voltage is measured on the DUT pin. A short circuit would read as 0 V and an open would go above the preprogrammed voltage clamp value placed on the DUT pin current force function. *

SEMI E35-0701, Cost of Ownership.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.14

INSPECTION, MEASUREMENT, AND TEST 19.14

FINAL MANUFACTURING

Supply currents (Icc, Idd): Each supply draws a predetermined amount of current when set to the correct voltage. This can be tested with the device in a static condition or while running in a typical operation. Input voltage/currents (Iih, Iil, Vih, Vil): Each input pin has a valid range of voltage and current that will be judged correctly by the DUT. This applies to digital pins at two levels, logic “0” and “1”. Output voltage/current (Voh, Vol, Ioh, Iol): Each output pin has a specified voltage and current specification representing logic “0” and “1” levels. Common Test Challenges. Noise in a test setup can cause failure and erode performance. Proper grounding techniques—decoupling capacitors at the power supplies and DUT and if a certain resource is noisy, isolating it and coupling the resource to other quieter ones through a radio frequency (RF) ferrite bead or inductor—are important. Also the overall noise floor (in dB or volts per root hertz) needs to be compared against the device requirements. It is difficult and time consuming to improve an overall test solution’s noise floor if it is worse than the device requirements. The DUT interface can be a challenge in several ways. The pin count of an IC may be in thousands with very small pitch distances between pins. This increases the complexity because of the physical limitations of trace routing and typically will increase the number of layers required on the load board to isolate the signal traces going to these types of devices. Typically the test source and measure resources go through a pogo pin to a DUT printed circuit board that has a special socket called a contactor to physically interface with the actual device. Another challenge is noise transference and the inductive coupling of ac waveforms on top of each other. A wafer probe card interface has much the same problems as the DUT board. Some options are blade or needle-type connections or membrane probes. Other new technologies are being developed to accommodate more complex pad geometries. 19.2.3 Testing Linear Devices Linear Device Market Segments. Linear markets could have a very wide definition. For this handbook, linear devices will be defined as power products such as power supplies, voltage regulators, and power switches; communications products such as signal amplifiers, switches, filters; and other categories such as light emitting diodes (LEDs) for brake lights, stop lights, and optical mouse devices. Definition of a Linear Device. A linear device is one in which the output is linearly proportional to the input, within a given range. Linear devices are sometimes also called analog devices. As opposed to digital devices, linear devices have a continuously variable output that is theoretically capable of taking on an infinite number of states. Some common linear devices include operational amplifiers (OP AMPs), filters, voltage regulators, analog switches, diodes/LEDs, transistors, triacs/ silicon controlled rectifiers (SCRs), and optical couplers. Linear devices are the building blocks or the “analog glue” that manufacturers of higher-level products use to complete their product. For instance, a cell phone will combine a microcontroller, Flash memory, static random access memory (SRAM), digital signal processing (DSP), and many linear components such as RF amplifiers, filters and switches, and LEDs. Architecture of a Linear Device Tester. The architecture of a linear device test system is very dependent on the type and variety of linear device that will be tested. Often the first choice to be made in selecting a tester for linear devices is between automated test equipment (ATE) and “rack and stack,” i.e., a combination of individual instruments. This is discussed more in Sec. 19.3. Since the architecture of a test system for linear devices is highly dependent on device functionality and these devices require a very low COT, many times the architecture is custom tailored to a specific family of devices and is not a general purpose one. However some of the typical tester building blocks that are needed include the following: A switching matrix provides a method of connecting the source and measurement devices to the different pins of the DUT. The number of pins, their function, and parameter specifications must be considered when specifying (or designing) the switching matrix requirements. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.15

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.15

Power supplies will be required to provide power to the device for testing. Power supply considerations include the number of supplies and their voltage and current specifications. All traces, wires, and fixtures must withstand the maximum expected voltage and current. Some tests can be dangerous to humans or even the test equipment. For example, testing the breakdown voltage of the DUT exposes it to a very high voltage (hundreds of volts) to ensure compliance to specification. Safety considerations must be adhered to as defined in Sec. 19.4. Often a pulsed high-current source will be used to keep the test equipment to a reasonable size and to prevent destroying the DUT, particularly in wafer form when no heat sinks can be attached to the device. Even at a package test, any kind of heat sinking capability would be minimal. Digital logic input and output pins may be used as digital control pins needed to access the DUT or configure it for certain test modes. Control, signal lines, or identification pins may be used to control relays or switches on the DUT fixturing. Different devices require different fixturing and often the test program will electronically check the identification information of the fixture to ensure it is the correct one. The prober/handler interface will allow indexing to the next die or package as well as sending category or binning information that allows the sorting of devices into different grades. Often the interface will also integrate equipment for temperature testing. The integration of a prober or handler into a tester is often more time consuming than expected due to the mixing of mechanical and electrical issues. There is a standard set of signals expected for this interface that can be provided with simple transistor-transistor logic (TTL) logic or via a standard interface like the general purpose instrument bus (GPIB). System controllers are required to run and coordinate all the operations for the test cell. Considerations for the system controller include the operating system used, networking capabilities, processing power or speed, upgradeability, the testing language(s) supported, and whether the operating system language is an industry standard or a proprietary. A final factor to be considered is that often test systems are installed in clean areas or areas with limited access. Since it is inconvenient to carry out test development in these limited-access areas, it is important to find a way to do remote development. Basic Test Setup for Linear Devices. The test setup for a linear device is dependent on its function and the level of testing required. For instance, testing a simple diode will require a programmable voltage and a current source, in addition to a voltage and current measuring device (typically called a parametric measurement unit, or PMU). An oscilloscope or programmable threshold counter will also be required to measure its ac switching characteristics. The architectural decisions on the tester will depend upon how much automation is needed and what level of accuracy is desired. For example, to test a small batch of diodes, a human operator can manually test with a power supply, a voltmeter, a pulse generator, an analog oscilloscope, a pencil and notepad. For a large quantity of diodes, with the requirements of data logging and temperature testing, one would need to add an automation—comprising a system controller, computer controllable PMU, signal generator, scope/counter, a temperature controllable device handler, and some form of device-marking system to allow the data log to track the device. Future Trends in Linear Devices. In the future, more and more of these linear devices will be integrated into the higher-level assemblies of the final product as manufacturers strive to add value and reduce cost. 19.2.4 Testing Digital Devices Digital Market Segments. Digital devices provide logic and computing capabilities for low-end gadgets all the way up to the most complex systems. Some examples of this are appliances, printers, calculators, cars, and computers. The major types of digital logic devices include processors, application specific integrated circuits (ASICs), and programmable logic. Processors can be programmed to do multiple tasks. ASICs are designed and optimized with only one application in mind, for example, controlling a printer, or monitoring an automobile’s performance. Because of this, ASICs are much simpler and cheaper to design. The cost and time to market are the major reasons why Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.16

INSPECTION, MEASUREMENT, AND TEST 19.16

FINAL MANUFACTURING

designers develop so many different ASICs. Lastly, programmable logic gives the end user flexibility to make changes in what the device does to meet its end application needs. Definition of a Digital Device. Digital data has two states—on/off, high/low, or logic “1” or “0.” A stimulus on one or more of the inputs to the device causes a result on one or more of the outputs of the device. It is made of transistors, or more specifically field effect transistors (FETs), configured together to build gates. A gate is the simplest of all digital building blocks. Gates include AND, OR, XOR, and NOT among others and can be combined to build logic for specific functions or blocks. A device may have several blocks that, together, form a digital device. These individual bits of data can be combined to form a byte or a word of digital data, and one bit has two possible states (0, 1). Binary words on a digital device are also called a bus. They can be used to address memory, as the data that go into some memory location, or as control lines. Many companies sell digital building blocks as their intellectual property (IP). This gives the designer access to the highest performance design and allows a designer to build a device using proprietary digital blocks along with a microprocessor block from one company and an interface block from another company to create a new device that fills a specific need. Digital signals are received or transmitted to a device based on the device clock. The rising or falling edge or both edges of a clock signal are used to latch data into flip-flops in the device. The faster the clock can run, the faster the device can use data, and the faster the device can complete a given task. Processors and ASICs may have several clocks. The device may be able to do computations internally with a clock of one frequency, yet transmit and receive data at much different speeds. In this case, the device may generate its own clock, using a phase-lock loop, and transmit data to other devices according to that clock. The highest clock frequencies are generally used inside a device to do computations; other clock speeds are used to reduce the risk of bit errors in communicating to other components. Functional, Structural, and Defect-Based Tests. A common way to test a digital device is by using functional tests that exercise the digital inputs the same way as they would be used in the end application. For instance, with an “AND” gate, the following sequence of inputs—00, 01, 10, 11— would produce these outputs—0, 0, 0, 1. IC designers simulate device operation to make sure their design is correct. Test vectors are then generated from this simulation data. As the number of gates on a digital device grows, the time it takes to simulate the device and the number of vectors required to test it grow exponentially. Devices with millions of transistors cannot feasibly be simulated completely because of time-to-market (TTM) pressures and the costs of added simulation and test equipment (such as larger memory and more processing power required). Therefore, engineers can design test circuitry into the device and use a combination of functional and structural tests to verify the device’s operation. Simple functional tests are written to test the interconnects between different blocks within a device and structural tests are written to test the individual gates. A design-for-testability review can determine which of these methods are needed for a particular device. Structural tests seek to verify that all the pieces of the product circuit are present and working. Alternatively, a structural test verifies that the DUT is free of faults but does not attempt to verify that it performs to all its specifications. The most common digital structural test is scan. With scan tests, the designer must use scan flip-flops and when the chip is placed in scan mode, special input pins on the device can shift data serially through chains of these registers and into particular flip-flops. Data that are required to test for a specific fault can be easily applied to the gate inputs. After the correct data are placed in the flip-flops, the device is clocked once and data are captured by scan flip-flops at the output of these gates. That data are shifted out serially and compared against the data predicted by simulation. Multiple “chains” of scan registers can be tested in parallel for added throughput. Any data can be placed into any gate so the fault coverage is very high. The down side is that the data for all these different serial scan chains require lots of vector memory and, since the scan lines have typically lower speed than the rest of the device, the test time can be long. A third test strategy is known as defect-based testing (DBT). DBT attempts to detect defects in a circuit by measuring any of its outputs while looking for unusual behavior, even if it is within

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.17

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.17

specification. The most widely used class of DBT methods is based on measuring the circuit’s quiescent power supply current. Called IDDQ, these methods are most useful in complementary metal oxide semiconductor (CMOS) circuits. Ideally, in a CMOS device no current should flow from the supply when the device is powered on but not running. Any current that flows is the result of leaky FETs or defects, usually bridges between interconnect lines that bias gates of the series connected n-channel MOS (NMOS) and p-channel MOS (PMOS) FETs away from the supply rails such that both FETs are weakly turned on and current can flow from VDD to Gnd. Once a device is characterized to have a certain IDDQ value, any part with IDDQ above that can be considered a bad part. The device is usually put into its quiescent state(s) by scanning in patterns so IDDQ tests are built on top of structural scan tests. As FETs get smaller, their natural leakage increases rapidly, which makes it harder to distinguish the defect current from the defect-free current. More advanced IDDQ tests have been developed for small geometry devices including Delta IDDQ and IDDQ current signatures. These tests make multiple IDDQ measurements with the device programmed to be in various “quiet” states. Extreme changes indicate a failure. These more advanced methods require considerable characterization. A common alternative to the accessibility, resources, and time required to read patterns into a device from an external tester is built-in self-test (BIST) that can execute either functional or structural tests. A very high-speed or very dense digital block may not be able to be tested with scan. BIST is implemented as a small state-machine circuit built into the device itself. This circuit generates inputs and compares outputs of a particular block in a device. Programming the device to drive random data can test a high-speed circuit using the device’s own input pin to receive that data and compare it to an expected result. BIST can be implemented as part of the device or off the device employing so-called built-out self-test (BOST) as a small circuit on the wafer that is physically cut off when the device is packaged. Deterministic Versus Nondeterministic Behavior. Traditional functional testing has been done using deterministic patterns that can be defined prior to testing. These patterns typically came from simulations of the device and contain stimulus and response data. The stimulus signals are intended to exercise the DUT and the response signals are the results of the simulations based on the stimulus. The part being tested is exercised to validate that it matches the simulated responses; for a given input there is only one correct output. Nondeterministic behavior has multiple forms, but the basic definition is that an algorithm or protocol has to be used to determine the correctness of the outputs and cannot be predicted prior to execution, thus there can be no previously generated “expect data.” This can take the form of either the data or the execution timing being the variable. For data, this means with a given input, there is a range of valid outputs for a good device. For timing, this means that timing of the comparator strobe is set by finding the timing placement of some pin and measuring additional pins relative to this timing location. Basic Setup for Digital Test. The basics of setting up and running a digital test include defining the pin configuration, or DUT pin to tester resource mapping, the voltage levels, the timing of the pin edges, and bringing the definitions of the correct drive and receive states, or vectors into a framework to develop a program. Most of this data can be leveraged from EDA. The dc tests are explained in the common test section. Additional ac tests include functional tests where vector inputs are given and outputs compared to, timing tests to find out where the edges produce a passing result and where they do not, level tests to dynamically find input and output sensitivity, propagation delay that determines the amount of time taken to get through a circuit, and setup and hold measurements that determine how long an input needs to be set up before a clock and how long it needs to be held after a clock cycle occurs. Other tests include frequency measurements, jitter measurements, and sweep tests. A sweep test moves either a voltage, timing edge, or frequency through a range of values, and then determines where the device passed and where it failed. Usually this is a characterization test since it is time consuming. Often in production a single test functional pattern will be run with critical timing and/or levels and a pass or fail status is determined.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.18

INSPECTION, MEASUREMENT, AND TEST 19.18

FINAL MANUFACTURING

Shmoo plots depict two or three of these sweep parameters tested across a range for each, and the pass/fail results plotted in an XY(Z) plot. This not only shows the limits of the parameters, but also indicates how the parameters interact with one another. Architecture of a Digital Tester. Digital tester architectures can vary widely, depending on the target market of devices to cover. Some digital testers are aimed at specific test market segments, such as DFT or low-end production; other digital testers have a scalable platform, allowing changes in speed and memory depth to enable the end-user to expand the system as needs arise or to reconfigure systems for a particular job without having to invest in different platforms, DUT boards or test program translations. A high-end digital tester architecture is shown in Fig. 19.7 and will be described in this section. The heart of any digital tester is where the device input and output (I/O) pins connect to the tester I/O called the pin electronics (PE). The PE contains many functions that will be described here. The driver sets the logic “1” and logic “0” voltage levels that will be driven into the device and sets the pin to a high impedance or “tri-state” function in case the DUT needs to drive the pin. The comparator sets the logic “1” and logic “0” voltage levels that will be measured from the device. If the level is between these two logic levels it is called a “mid-band” level. DC sourcing and measuring are also accomplished for level setting and biasing statically with a parametric measurement unit (PMU). Since the DUT will expect ac dynamic signals, the timing edges have to be generated by a timing generator to meet the DUT needs. There are common formats for both the driver and the comparator that are a combination of levels and timing within a device period or cycle. Usually the device cycle is 1/clock rate at which the device is running and represents a period of time to take 1 bit of data, process it and send out 1 bit of data. These formats are explained in the glossary section. The more edges available per device cycle, the more flexible and potentially faster the signal can be. The vector memory contains the logical “1” or “0” data for each device cycle input from the tester.

Clock domain

Clock domain Per pin architecture resources

Test processor Drive edges Sequencer Vectors

Driver

Active load

0 0 00 0 0 0 00 0 010 00 10 0 011 0 1 10 0 0 10

Tri-state formatterr

Digital compare

APG SCAN

Optical link to workstation

FIGURE 19.7

Ioh Iol

Window formatter Error map

I/Os to DUT

Drive formatter

Waveforms

Comparator

Data sampler

Compare edges

Workstation

DUT

PPMU

TIA

SPMU

DPS

Architecture of a digital tester.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.19

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.19

The compare memory is a table of what the tester expects to see from the DUT for each cycle and the error memory logs the pins and locations that fail. These all interact so that a logic “1” drive coming from the vector memory has the correct timing and level so that the DUT recognizes it as a valid input, and the DUT can send the appropriate response that the comparator decodes to a logic “1” or “0,” which is then compared against the compare memory to judge if it is the correct response. The test may or may not run through the memory addresses in a linear fashion. A sequencer is a vector address generator that will allow the memories to be accessed in structured ways like subroutines or randomly move with jump operations. Also, the flexibility of being able to change from one format or setting of edges to another in the next device cycle is desirable; this is called changing on-the-fly (OTF). All these operations need to be orchestrated to put the DUT into its end application environment, and a test processor accomplishes this task on an individual pin-by-pin basis. All the functionality described under pin electronics needs to be available on every pin, or per-pin to be able to meet the flexibility and complexity demands of many different digital devices. Scan has become popular with digital devices. Very large lengths, for example, over 100 Mbytes, of Scan memory need to be available in the configuration to accommodate this need. Other specialty functions such as capture memory and digital source memory will be covered in the mixed-signal test section, and algorithmic pattern generator will be covered in the memory section. Some other critical parts of the architecture include clocks and timing. Clocks are what drive the DUT and it may need more than one domain. A different domain may use a frequency unrelated to others used by the DUT, or be nonphase related. Overall timing accuracy (OTA) and edge-placement accuracy (EPA) are widely considered to be the most important and fundamental specifications of a digital tester. These specifications indicate how accurately an edge can be launched and measured from the test system. Edge timing resolution is also critical to DUT performance as well as the jitter, or the undesirable movement of edges from one device cycle to the next. Other functions required in the architecture include power supplies, a higher precision dc parametric measurement unit to make more exacting measurements than the per-pin PMU can make, a system controller or CPU to run the program, and a time interval analyzer that is used to making timing measurements on edges. The software environment needs to be interactive and graphical user interface (GUI) based. Since the increasing speeds and number of pins make it difficult to move enough air through a system to maintain the proper temperature, liquid cooling is a state-of-the-art trend. High-Speed Digital Testing. Advances in silicon, such as smaller gate widths and superior materials, and fabrication techniques have enabled extremely fast on-chip communication. In many cases, the bottleneck of the ICs has become transporting data between chips and other system building blocks. The need to create faster chip-to-chip interfacing has resulted in many different standards for data transportation. Unlike sub-gigabit-per-second (Gbit/s) testing, high-speed testing involves no tristating—as mentioned in an earlier section—because tristating causes additional capacitance. Termination is always used to avoid reflections, and the data bus effectively becomes a high-speed transmission line. Understanding the particular high-speed device and its challenges is an important first step to outlining a test plan and determining the fit to a particular piece of ATE. For example, some standards utilize embedded clocks, whereas others, such as HyperTransport, provide a clock synchronized with the data and the internal phase locked loop (PLL). The latter may require an interface with sourcesynchronous capabilities, whereas the former may require a clock-recovery circuit. Many cases exist where the digital tester is asked to synchronize to a bit stream that is not deterministic or contains seemingly random data packets. Many high-speed bus protocols are differential based. Differential swings are typically extremely small and require a digital tester with the ability to provide a linear signal with a well-defined, controlled slew rate at low swings. Some applications require a dual-transmission line implementation to enable fast write-to-read transitions or to enable dedicated drive-only or receive-only ATE to interface with a bidirectional device interface. An example is double data rate (DDR) devices that must use a driver and a receiver to interface bidirectional DDR data pins (single ended) with ATE.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.20

INSPECTION, MEASUREMENT, AND TEST 19.20

FINAL MANUFACTURING

Setup and hold and skew measurements are typically important in the world of high-speed tests and the ATE hardware must be able to accurately measure skews and setup and hold times. One of the most important high-speed parameters is jitter. The impact jitter has, as it is introduced to a device, is to cause a connected receiver to detect an incorrect bit transition, causing a fault. Generally, the tester needs to be able to inject and measure jitter. A jitter tolerance measurement requires that the tester inject a known amount of jitter while the device’s outputs are monitored for an effect on the bit error rate as a functional test. Jitter transfer, on the other hand, is a measure of how a device amplifies or transfers jittery input to its outputs. The ability of the device’s PLL to filter out the jitter is of key importance. For this test, the tester provides a jittery source and the device’s transfer of the jitter is characterized. Eye diagrams are another commonly used, graphical way to view the total jitter present on a device, as measured by the test system. An eye diagram is a composite view of all the bit periods of a captured waveform superimposed on each other. To create an eye diagram with a digital tester, the pattern is typically executed multiple times; each time the edge position and/or strobe levels are modified. The horizontal size and overall shape of the eye indicates the jitter present on the device. The shapes of the eye crossings indicate whether or not deterministic jitter is present in addition to random jitter. Devices with source-synchronous outputs can require a different approach to tests than traditional techniques. The main difference in testing these outputs is the nondeterministic placements of the transitions of output signals. Traditional devices have specifications that define the timing relationship of the inputs to the outputs. Source synchronous devices do not have such a specification; instead, the data output is also accompanied with a clock signal that is coupled to the data. For ATE, this means that the output clock of the device has to be used to sample the data. Today, many of the source synchronous parts can tolerate huge shifts in output placement, two to four data bit times in the system, and are able to be tested without the use of source synchronous capability. In this case, searching for the best place to capture the data is one way of using testers without source-synchronous capability.

19.2.5 Testing Memory Devices Market Segments. Memory densities and speeds are continually driven by market demands. Memory is prevalent in almost all applications that use semiconductors. Typical memory markets include personal computers, workstations, game consoles, personal digital assistants (PDAs), and mobile phones. Architecture of a Memory Device. Semiconductor memories can be categorized into two general types—volatile and nonvolatile. A volatile memory loses its data contents when its power is switched off while a nonvolatile memory retains its data without power. The most common nonvolatile memory is also known as Flash memory and is discussed in Sec. 10.2.6. Volatile memory cells can be further classified as SRAM or dynamic random access memory (DRAM). To retain data, a DRAM cell requires a data refresh operation at regular intervals and if power is removed, all data are lost. An SRAM cell will retain data as long as a power source is applied. The reason for this behavior, in both cases, can be found in the design. In order to maximize memory density, high-density DRAM memory arrays are designed with a single transistor with a capacitor load to hold the data. The charge stored in a DRAM cell would eventually leak off if not for the refresh operation. A refresh reads the current data and writes it back to the DRAM which renews the stored charge in the DRAM cell, hence, the term dynamic memory. An SRAM cell is implemented with multiple transistors to latch the data and eliminates the need for a refresh operation. Semiconductor memories are typically organized as an array of cells, each one containing a logic bit “1” or “0,” of information. These arrays are typically very regular. The dimensions of the array are denoted by X and Y, or rows and columns. Through row and column select lines; each cell may be individually enabled for reading and writing. The X dimension address corresponds to the row enables and the Y dimension address to the column enables, although for some manufacturers these X and Y definitions are reversed. An address is placed on the address pins of the device, which is then internally decoded to enable the required cells. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.21

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.21

More than one cell may be enabled by an address so that multiple bits of data may be manipulated at the same time. For instance, a memory device with a 1 Mbit capacity has 1048576 cells in its array. These cells may be organized as 131072 addresses that enable eight cells at a time. This would commonly be known as a 128K × 8 memory device. Likewise, the same memory might instead be organized as a 64K × 16 device. Basic Memory Test Setups. Similar to other types of digital semiconductor devices, the test setup includes pin configurations, voltage levels, timing conditions, and test patterns determined by the design of the device. Different logic designs require different timing and level setups. For example, a device with high speed transistor logic (HSTL) outputs would require one set of voltage and timing conditions while a device using stub series terminated logic (SSTL) 1.8 compliant off chip drivers would require a completely different set of conditions. In general, there are three steps involved in the testing process—determining the fault coverage requirement, planning and implementing the test setup, and finally analyzing the test results. A good understanding of the fabrication process, such as historical data and a good understanding of the design determine the fault coverage requirements. This was discussed in Sec. 19.1. Early in the design process, decisions must be made about the level of BIST. In one extreme, designers could implement BIST engines to accomplish most of the functional memory tests, leaving the standard dc parametric test to ATE. Or, the design might not provide enough extra space for the BIST circuitry on the silicon die, in which case all the testing, including functional dc and ac, would be performed with ATE. The functional testing of a memory device can be viewed as three parts—the memory core consisting of memory cells, the address decoders consisting of logic used to select a particular section of the memory array, and finally the logic used to control device operations such as read, write, and refresh. Each section of the memory requires different patterns to test for proper functionality. Some of the fault models are the same as any other logic device such as stuck-at faults or stuck-at logic “0” or “1.” Because of the way a memory design is laid out, other faults also apply. These are called neighborhood sensitive faults that have to do with the proximity of one element to another. Some examples of this are coupling faults defined as cross talk between data lines or electrical shorts between data lines, and address decoder faults defined as inaccessible address lines or multiple cell access faults. Architecture of a Memory Tester. Stand-alone memory devices are typically tested with algorithmic pattern generators (APGs). An APG generates tester cycles that contain a pattern to execute a series of write and read operations of data to a predetermined sequence of addresses. The tester will capture results from the read operations and compare them to the expected data. There are two memory tester architectures to consider—per-pin and centralized. The centralized architecture implements the APG using hardware architected as a collection of programmable hardware registers. The contents of the registers are gated to dedicated tester buses for address pins, data pins, and control pins. In contrast, a tester with a per-pin architecture provides identical functionality using a software APG that programs each tester channel to execute a memory test. The centralized APG architecture is a traditional tester implementation that does a good job of testing standard memory devices. The per-pin architecture provides a flexible memory test solution that does not use dedicated tester buses and can generate APG patterns as well as logic patterns. This allows the per-pin architecture to be used to test standard memory devices as well as new memory architectures that also contain logic. This capability is also very useful in testing embedded memories. Test Result Analysis. A requirement when characterizing memories is to represent the pass/fail results in a graphical format. The graphical display, known as a bitmap display, shows a two-dimensional depiction of the memory array and the passing and failing bit represented by different characters or colors. 19.2.6 Testing Flash Memory Devices Flash Market Segments. Flash memory is a huge market and very pervasive in our day-to-day lives. Any device that needs to remember something without power is a good candidate for Flash memory. This includes cell phones, digital cameras, PDAs, MP3 players, computer BIOS, and memory used as small external drives for a PC. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.22

INSPECTION, MEASUREMENT, AND TEST 19.22

FINAL MANUFACTURING

Definition of Flash Memory. Flash memory allows users to electrically program and erase information and is a nonvolatile memory; that is, power can be removed from the circuit, and it will retain the information. Flash memory is similar to erasable programmable read-only memory (EPROM), but with a much thinner oxide layer between the gate and the source/drain. Each individual Flash memory cell is a FET with a modified gate structure. The gate structure has a floating gate where electrons are trapped or stored. By trapping or storing these electrons, the threshold voltage of the FET is raised and it is considered programmed. When the electrons are removed from the floating gate of the FET, it is considered erased. The process of storing and removing charge is complicated. It requires that certain voltages be placed on the contacts of the FET for controlled periods of time. It is possible to over-program or over-erase the FETs causing the memory device to cease functioning. Users typically want to deal with bytes or words instead of individual bits. Because of this, the Flash memory device contains a state machine that is a microcontroller that acts as a user interface. The user issues predetermined commands to the Flash memory device, such as “program this word,” or erases some portion of the Flash memory, and the microcontroller does the low-level work of moving the charge onto or off the floating gate of each affected FET. Different Flash memory manufacturers have various features and gate structures that enhance this basic behavior. One approach is to store different levels of charge to allow multiple bits of information per cell. Another is to modify the FET structure by allowing the floating gate to store different charges at each end of the gate thus allowing multiple bits per FET. In any case, the trend is to store more bits in less space thus reducing the cost per bit. There are two different types of Flash memory technologies—NOR and NAND. NOR: The data words can be accessed in any order (random access). This type of Flash memory is typically used for code or code and data storage. Codes can be executed directly from the Flash memory because the random access allows looping and branching to different locations in the device. Typical end applications are for cell phones, PDAs (internal storage—not the Flash memory storage cards), and PC BIOS. NAND: The data words are accessed a page at a time, with the data clocked out of a buffer. This type of Flash memory is typically used for data storage. Since the access is somewhat serial, the data are usually buffered to some other memory (SRAM/DRAM) if the code is to be accessed. Digital cameras and MP3 players typically use this type of memory since the data access is usually in order. This is the memory in all the Flash memory storage cards—Compact Flash (CF), SmartMedia, Secure Digital (SD), eXtreme Digital (XD), and memory stick. Architecture of Flash Memory Tester. The typical Flash memory tester architecture is shown in Fig. 19.8 and will be described in this section. Since Flash memory consists of millions of similar FETs that require a similar algorithm to test, the APG allows the manufacturer to create an algorithm for one FET and then simply set up ranges for the amount of rows, columns, and blocks (X, Y, and Z address generators) to test. Crossover or scrambling circuitry is needed to map the address generators to the correct address pins since Flash memory devices have different numbers of rows, columns and blocks, circuitry. Parametric measurement units (PMUs) are used to measure voltage or current parameters on each FET. This architecture also allows “trimming” the device, where the reference cells and comparators are programmed to differentiate between a logic “1” and a “0” state. Since there are so many FETs and either 8-, 16-, or 32-bit wide data buses, multiple PMUs, or even per-pin measurement units (PPMUs) are configured into the architecture to speed the testing. Parallelism. Testing a Flash memory device takes a large amount of time because of the relatively low speed and large size. To reduce cost, Flash memory manufacturers typically test multiple devices at the same time. This requires that the resources to test each device be duplicated and that the system must support multiple APGs and have enough pins for all the address, data, and control pins of the DUTs. The individual test site controller is where the test program runs. It is responsible for quickly controlling the APG and the other test resources. It saves the data and is also responsible for displaying the test results.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.23

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.23

PC workstation controls all sites PPS PMU PPMU Vector memory

Test site controller

Algorithmic pattern generator Buffer memory

M U X

DUT DUT Site x DUT DUT Site 1

M U X

Error catch RAM

Site x

Site 1

FIGURE 19.8

Architecture of a Flash memory tester.

The overall system controller is where the tester control software runs and coordinates all the test sites. This is where the test program is developed and downloaded to each individual test site controller for parallel execution. Often the distinction between the test site controller and the system controller is blurred with different test systems having these resources responsible for different roles. Typically the system controller has access to the manufacturer’s network and production floor control systems so test jobs can be automatically dispatched and the test results can be saved. The prober/handler interface will be used in the equipment to handle either a wafer or a package. A prober/handler interface will allow control to index to the next die or IC package, as well as send category or binning information to signify a good DUT or a bad DUT. This allows sorting devices into different grades. If temperature testing is required, there is a standard set of signals expected for this interface, which can be provided with simple TTL logic or via a standard interface like GPIB. Basic Test Setup for a Flash Memory Device (Typical Tests). The basic test setup for a Flash (memory) device includes common test parameters, for example, opens, shorts, leakage, static/ dynamic Icc current, and voltage reference. Functional tests include program/erase tests and can be done in two ways, either customer or test mode. Customer mode uses the built-in microcontroller to do the programming or erasing. This is not usually the most efficient method, but is one that is guaranteed to function in the end application. Test mode is the manual method where the test program controls all the DUT voltages directly. This method of programming and erasing can be optimized for the current temperature and other conditions. Test mode is usually used for sort testing because it can save time and allows the test program to determine the appropriate settings for the DUT’s resources that are then saved into the DUT memory itself for use by the customer mode algorithms. In this way, the test defines the parameters for its end application functionality. The margin test will allow the manufacturer to check all the FETs by reading the whole DUT to assure that they can properly detect a logic “0” and a “1.” Conceptually, this is a pass or fail (go/nogo) voltage threshold (Vt) test. Since there are millions of FETs, to do an individual Vt test on each FET is not cost-effective. The margin test will allow the manufacturer to determine the distribution of the Vts across the DUT without actually measuring each Vt individually.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.24

INSPECTION, MEASUREMENT, AND TEST 19.24

FINAL MANUFACTURING

There are many other tests that can be done on Flash memory devices. They include the program/ erase suspend to see if the program or erase steps can be suspended and resumed, testing block locking that checks the ability to prevent overwriting certain data when the part is locked, and other data security feature functions. These tests are usually specific to the feature set of the Flash memory device. Typical Production Test Flows. Sort 1 is the first time a Flash (memory) device is checked on a wafer after the IC fabrication steps. This is where the DUT’s voltage reference cells are trimmed. This allows the DUT to determine the difference between a logic “0” and a “1” state. After setting up these thresholds, the DUT is checked for basic program and erase functionality as well as checking for slow or fast programming bits. Any FETs that do not stay within predetermined limits for Vt and other characteristics are marked for potential repair with redundant elements. Other tests may or may not be done depending on the feature set. High fallout tests are done at Sort 1 to weed out the bad DUTs early. Devices that pass Sort 1 are programmed with a pattern and sent to the burn-in ovens shown in Fig. 19.1; this step is called the retention bake. Since the oxide layers are so thin, any anomalies that prevent the proper storage of the charge on the floating gates are judged defective. The retention bake step is a form of accelerated aging to determine if the DUT will be able to retain data for its specified lifespan. Sort 2 is a wafer level test that quantifies the amount of charge loss or gain to see if it falls within the allowed limits. Retrimming of the reference cells is done and the Vt distributions are again checked with margin tests. Any bits that do not pass this step are repaired with redundant elements. A custom pattern is then programmed into the part, and it is sent to packaging. Sort 3 or package test runs a simple functional test to make sure that the packaging step did not damage the DUT. For KGD sales, the package step is not done, but the equivalent is done on the wafer prior to die separation. The last step is to program any of the custom features of the DUT and program any data desired by the end customer. What Makes Testing Flash Memory Difficult? Flash memory testing is difficult because the program and erase execution times are long. In order to get the electrons onto or off of the floating gate, the three terminals of the FET need to be held at certain voltage levels. This allows electrons to migrate across the barrier oxide and get trapped or released. Since program/erase time and data retention are both affected by the thickness of the barrier oxides, a tradeoff between the two characteristics must be made. To achieve the goal of 20 years of data storage, the program and erase times end up being much longer than equivalent times for SRAM or DRAM, for example, µS or mS instead of nS. This means that total test time for Flash memory is much longer than that of other volatile memory technologies. Testing all the characteristics of a Flash memory device can take on the order of minutes. Because of this, Flash algorithms are designed to make the best use of several test patterns that overlay to minimize unnecessary erases. For this reason, patterns common with SRAM and DRAM testing such as walking 1s and 0s are not used in Flash testing. With Flash densities ever increasing and the number of individual FETs in a device growing, the number of memory cells is large. Densities of several gigabytes are available today, meaning that several billion FETs per device must be checked. Combining long program and erase times with billions of FETs results in even longer test times. This is why most manufacturers resort to as much parallelism as the latest tester and probe card technologies will allow. Higher parallelism increases complexity since more resources must be coordinated and more data must be managed. There is a need for redundant memory cells because with billions of FETs, it is virtually impossible to guarantee that each one will be fully functional after all the complex fabrication steps. One speck of dust can damage an entire device. For this reason, each Flash memory device is made with redundant rows and/or columns to allow the device to be repaired during a test. This means the redundant elements must also be checked for proper functionality and the test program must manage the swapping and tracking of errors in the main array as well as the redundant elements. The redundancy analysis and repair routines are arguably the most difficult portion of the test process. Some devices even allow repairing of the repair elements, which further increases this complexity.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.25

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.25

Future Trends in Flash Memory. As mentioned previously, Flash memory is an offshoot of EPROM. It has virtually replaced EPROM and EEPROM due to its better capability and lower cost. Inevitably, this will also happen with Flash memory. Several technologies are being investigated that could replace Flash memory, such as ferroelectric RAM (FRAM), magnetic RAM (MRAM), ovonic unified memory (OUM), and polymer memory and spin memory. There is also a desire to combine the capabilities of SRAM, DRAM, and Flash memory into one unified memory type that does what all three can do, but is cheaper to manufacture. Future Trends in Flash Memory Testing. Since Flash memory is very time consuming to test, the IC manufacturers are looking at how to reduce or eliminate the testing needs. One area that is being pursued is BIST. By adding circuitry that can diagnose the device and log the memory array’s errors, the job of the test system becomes greatly simplified. The addition to the device real estate must be weighed against the cost reduction in test time and tester capital expense. This will be discussed further in Sec. 19.5. 19.2.7 Testing Mixed-Signal Devices Mixed-Signal Market Segments. Mixed-signal devices are very prevalent in our everyday lives. Some of the most common include devices that allow such products as cellular telephones, hard disk drives, Internet devices that access Internet service providers (ISPs), multimedia audio and video, optical disk storage, games, and medical equipment to work properly in a convenient form factor. Definition of a Mixed-Signal Device. A mixed-signal device consists of both analog and digital components combined or integrated into a single device to meet a function or application need. The analog section is one that deals with signals that are varying in time as well as amplitude and have similar functionality to linear devices such as amplifiers and filters. The digital section can use logic, state machines and processors to accomplish its tasks. The Basic Building Blocks of a Mixed-Signal Device. The digital section functionality and organization are similar to that described in the digital section of this chapter. A more specialized digital function includes DSP, which is a mathematical technique used to process a signal according to a specific need. A typical use of DSP is to convert the time domain data into data more suited to CPU math operations; for example, converting time domain data into the frequency domain ( fast Fourier transform) and then performing the math to arrive at an actual test parameter number such as total harmonic distortion. Other uses included complex signal processing such as signal modulation or demodulation or digital filtering. Other digital blocks include CPUs, digital logic, and embedded memory. The analog is the section of the device that deals with signals that vary in time as well as amplitude. These signals are usually considered real-world type signals, because all signals of this nature usually are not related to a fixed timed event but can occur randomly and are nonperiodic. The most common analog building blocks are amplifiers and filters. The converters section of the device can convert an analog signal, or one that is varying in time and amplitude into a digital representation of the applied signal (A to D converter) or can take a digital signal and convert it into an analog or time and amplitude-varying signal (D to A converter). The converters provide the interface between the analog domain and the digital domain. The digital domain data can be modified or transferred without any deterioration and are more suited to digital logic and computation while the analog representations are more suited for human use, such as audio and video signals and are vulnerable to noise and distortion. The filtering section uses techniques to remove or limit unwanted signals from the signal of interest. This filtering can be in the form of analog filtering, usually occurring in the time domain, using active components such as op amps or passive components such as resistors, inductors, and capacitors. Digital filtering is a math process using either a convolution operation in the time domain or FFT-based operation in the frequency domain and will either subtract unwanted or enhance desired components. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.26

INSPECTION, MEASUREMENT, AND TEST FINAL MANUFACTURING

Most system-on-chip (SOC) devices include PLL sections to generate appropriate clock signals to be distributed to various functional blocks. An external oscillator may supply a basic clock signal to the device and it may be multiplied or divided into suitable frequencies for each functional block. In a serial data transmission SOC, an incoming receiver signal may contain its own clock that is extracted by a PLL. The power section is one of the most critical sections of the device that is frequently overlooked. Optimum power supply, distribution, and bypass filtering are key to keeping noise and ripple to a minimum to allow the device to function properly. Architecture of a Mixed-Signal Tester. The architecture of a tester that can test all the diverse functionality of the basic building blocks has to match the stimulus expected and has to be capable of measuring the expected outcome. Fundamental digital tester requirements for mixed-signal tests are similar to that of digital tests as shown in Fig. 19.7. However, there are two added digital capabilities that are necessary to provide the digital stimulus waveform data and to capture the results of the analog-to-digital conversion. These two capabilities are digital source memory and digital capture memory. The added digital functionality and added analog subsection are shown in Fig. 19.9. Digital capture memory is the ability of the ATE system to store the results of the vector compare action into DSP accessible memory as data rather than a pass/fail condition. Analog-to-digital converters (ADCs) require that the sample data be stored into tester memory because their outputs are nondeterministic in nature; further DSP is necessary to determine a pass or fail condition. This can require a large capture memory for high-resolution devices. Additionally, in order to minimize the tester resources, the tester requires the capability to selectively store sample data on a per vector address basis. This capability is referred to as selective capture. This requirement is demonstrated by audio coder/decoders (CODECs) that are used frequently in the telephony and multimedia audio industries. These devices require a 256-bit frame, while only 20 bits of this frame

Multiple master clocks

Inter resource communication and sychronization

19.26

Digital subsystem additions to Figure 7

Digital master sequencer

Test vector generator

Digital capture memory

AWG function AWG sequencer Digitizer function Digitizer sequencer

Pin electronics

Digital source memory

Analog subsystem High speed and Waveform MUX source memory high resolution DSP processor Ultra high speed optional distributed Waveform High speed and MUX capture memory high resolution

DC subsystem not in the per pin architecture DC sequencer

DC front end supplying V and I

Time measurement subsystem TIA data memory

FIGURE 19.9

DC data memory

Time measurement unit

Time interval analyzer

MUX

Architecture of a mixed-signal tester.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.27

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.27

represent the results of one channel. Digital capture functionality requires the ability to capture only the relevant sample bits within this frame to reduce the unnecessary overhead of capturing and postprocessing the unnecessary 236 bits per sample. For adequate dynamic test coverage, the digital capture rate must be able to operate at the maximum frequency at which the device under test samples. As in digital and memory devices, there is a requirement of digital vector drive/compare, digital capture, and PMU capability on the same DUT pin depending on which mode it is in for a specific test in the flow. Therefore, the trend in the ATE industry has been toward a solution that provides this capability on a per-pin basis to reduce the necessity of multiplexed tester resources. By providing advanced per-pin architectures with these capabilities native to each pin, cost and performance are optimized. Digital source memory (DSM) is the ability to segment a portion of digital vector memory as a contiguous block of data that can be called from standard test vectors. In most cases this memory is utilized in frame-based, serial device interfaces. This capability simplifies the effective management of source waveforms for DAC testing. Similar to capture memory, the necessary size is relative to the resolution and number of waveforms to be sourced. As this capability is used primarily in frame-based interfaces, the speed requirements are not stringent. In the current market, devices that require speeds of over 50 MHz do not have frame-based interfaces and as such do not require DSM capability. Analog subsection. There are two analog module requirements for mixed-signal tests— waveform generators and digitizers. Both are usually specified by their resolution and sample rate. An arbitrary waveform generator (AWG) provides a sample memory that the user programs to allow the generation of any type of waveform that can be defined mathematically. Output frequency changes can be accomplished by either modifying the sampling clock or waveform data. The sampling clock of the AWG can be derived from a common master clock with digital vectors to ensure coherency, or from another master clock. Usually in mixed-signal testers at least two master clocks are provided for supporting multiple frequency combinations in tests. Waveform digitizers sample the device-generated analog output and store the discrete voltage values in the local memory. A local DSP within the digitizer will then calculate the performance relative to the specifications and return the results to the user’s computer. For cases of sampling a waveform whose frequency is over the maximum available Nyquist frequency of the digitizer, undersampling can be utilized. This methodology takes advantage of a high input bandwidth of the measure unit to alias the signal of interest into the spectrum. A digitizer that utilizes this sampling methodology is referred to as a sampler and is usually specified by bit resolution and bandwidth at the −3 dB cutoff point. Many mixed-signal implementations have multiple functional blocks. As such, ATE test resources must provide an autonomous test capability within each tester module to enable parallel testing with minimal overhead. This capability within each module, as shown in Fig. 19.9, includes: Analog sequencer: Similar to the digital pin sequencer, the analog sequencer steps through a series of instructions to control the operation of the module. It is in effect an address generator for access to the AWG or digitizer memory locations. This allows an AWG to repeat a block of waveform or switch waveforms from one cycle to the next (OTF), and a digitizer/sampler to do multiple measurements sequentially without any interruption from the system. Memory: These comprise AWG source or digitizer capture waveform memory within the module. For complex mixed-signal devices such as multimedia, cellular phones, and hard disk drives, test signal waveforms can be long and require many different stimuli and measurement segments requiring deep memory. Digital signal processor: A local DSP provides the ability to calculate results without requiring the transfer of the capture results to the tester controller workstation for processing. FFTs and filtering are the most common operations. Parallelism: There is an architectural advantage to having multiple autonomous units to provide multisite and parallel IP block testing capability. Other necessary pieces to the architecture include highly accurate dc source and measure capability to be used for voltage and current setup and measures. A per-pin architecture is the most flexible and contributes to parallelism that is necessary to satisfy COT economics.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.28

INSPECTION, MEASUREMENT, AND TEST 19.28

FINAL MANUFACTURING

Clock distribution in a system is necessary because different resources running concurrently will often run at different frequencies, so they must be capable of dividing a master clock rate down as needed. In fact, sometimes frequencies are not multiples of each other and it may be necessary to support multiple unrelated (frequency) clocks within the system. This is also desirable when implementing the undersampling technique mentioned previously. Power supplies deliver the necessary voltage and current to power up the device and keep it running. Usually, some relays are used on the DUT board to facilitate signal multiplexing and other uses; these require drivers to turn on the relay coils. Basic Test Setup for a Mixed-Signal Device. Load board layout is often overlooked, yet is a critical factor in overall test performance. Poor design or layout can lead to significant noise and cross talk and undesired attenuation issues. These issues can be compounded when dealing with multisite designs. Digital, analog and utility signals and their associated return paths should be as isolated as possible. Utility supplies, such as those used for relay control, are generally the noisiest supplies on the tester. There are two basic parameters in the selection of the analog instrument—resolution and bandwidth. Resolution is the number of discrete values the module can source and measure, usually specified in bits. For example, a 16-bit digitizer can resolve 2^16 discrete values. With a 2-Vpp input range, the resolution would be the full scale of the range/ the total number of discrete values, 2V/2^16 or 30.52 µV. A parameter that quantifies the impact of nonlinearity and noise within the bandwidth of interest is the effective number of bits (ENOB). The ENOB calculation is ENOB =

SNR meas − 1.76 6.02

It is critical that this value be associated with a specified frequency range. Another method that is often used to specify the performance of an analog instrument is the noise power or spectral density. In this case the noise power is spread out over the frequency spectrum and the units are expressed as volts per root hertz. It is a useful way to express the noise floor of a resource in a standard terminology. The basic test setup includes powering up the device, setting up the logic pins to achieve the testing mode desired, and then sourcing a stimulus and measuring a response. The test list will be defined according to the test specifications found in the data sheet. Since a converter is a very common mixed-signal device to test, it will be briefly examined. There are two fundamental tests that are used to characterize the performance of the devices—transfer curve and distortion tests. Transfer Curve Tests. DAC transfer curve testing is accomplished by measuring the discrete analog output voltage for each code and comparing these measured values with the ideal. This comparison derives the fundamental measurements of differential nonlinearity (DNL), integral nonlinearity (INL), offset error, and gain error. DNL measures the least significant bit (LSB) step size of the device relative to an ideal step size. INL measures the deviation of each point, in LSBs, relative to an ideal curve. Offset error is the offset of the output, at code “0,” relative to the ideal curve and the gain error is the difference from the ideal at full scale. Although the same parameters are used to measure ADC accuracy, the calculation methodology is different due to the inherent differences between DAC and ADC transfer curves. While there is a one to one correlation of input code to output voltage for a DAC, an ADC has a range of input values that correspond to a single output code. Therefore, a histogram method is utilized in the calculation of the transfer curve characteristics. The histogram plots the number of occurrences of each of the converter codes and through some statistical mathematics the transfer curve for each code can be plotted. This would be the deviation from an ideal transfer curve for each code. Distortion Tests. Distortion testing is a method of dynamically testing a converter and the approach is the same for both ADCs and DACs. The primary goal is to generate (or stimulate) a single frequency to the DUT input and then measure or sample the output, convert the time sampled values to the frequency domain, utilizing DSP with a Fourier transform, and quantify the undesired, distortion,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.29

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.29

and noise elements in the spectrum. Some common parameters that are results of this test include— total harmonic distortion (THD), signal-to-noise ratio (SNR) and signal-to-noise + distortion ratio (SNDR). All these are indicative of the performance of the device. 19.2.8 Testing RF Devices Market Segments. The types of devices that will be included in this consumer market segment are at a high integration level and include RF reception or transmission, or both. This includes devices that go into cellular telephones, TV tuners, WLAN Internet, Bluetooth, and Ultra Wide Band applications. Definition of an RF Device. The term RF refers to an analog signal, called a carrier, typically above 100MHz, that is modulated to contain information. This signal is propagated through the airways and then the carrier signal is removed and the modulated data are decoded. There are many devices manufactured today which can be considered RF devices. RF techniques are used in both the wireless and wired, or wireline industries. The wireless RF industry comprises cellular phones, wireless LAN or WLAN, Bluetooth, Ultra Wide Band, and other standards of sending information from point a to point b without wires. In contrast, the wireline RF industry comprises cable TV tuners and other appliances used to send information through cables. Building Blocks of RF. There are all kinds of devices that use RF signals, but a “pure” RF device is one that has only RF in, RF out, and a power supply. This kind of device requires a traditional RF test approach and therefore a specific type of test system that has sufficient RF source and measure capabilities to meet the device specification. As devices evolve, more and more functionality is being placed on a single substrate, thus the emergence of RF SOC devices. RF SOC devices have RF in, RF out along with digital and analog controls. These kinds of devices will have functions such as registers, digital interfaces, memories, mixed-signal blocks, as well as RF inputs and outputs. This kind of device requires a much more flexible test system that can handle the variety of signal types mentioned. All RF tests start with understanding the basic building blocks of RF SOCs. These basic building blocks are amplifiers that take an input signal and increase its power, mixers that take an input signal and translate it from one frequency into another, filters that take an input spectrum and modify certain frequency components, and voltage controlled oscillators (VCOs) that convert a voltage into a frequency. System-Level Tests. System-level tests, for example, testing the IC as a radio rather than a series of blocks, provides true performance verification since the device is tested under conditions similar to its end-use environment. Examples of these types of measurements include adjacent channel power (ACPR), error vector magnitude (EVM), and bit error rate (BER). Bit error rate. BER is the number of error bits divided by the number of transmitted bits. The bit sequence to be sent to the DUT is coded into an RF modulated signal. The DUT then demodulates the signal to the in-phase and quadrature (I and Q) signals. The I and Q signals are decoded to get the digital data (bit sequence) that were originally sent to the DUT. The digital data from the DUT are then compared to the original bit sequence to determine the BER. Error vector magnitude. EVM is a measure of modulation or demodulation accuracy. The ideal modulation vector is compared to the resulting vector coming from the DUT. Error vector magnitude is the root mean square value of the error vector over time at the instant of the symbol clock transitions. EVM =

rms error vector ×100% outermost most magnitude

Or, expressed in decibels: EVM = 20 × log

EVM% dB 100%

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.30

INSPECTION, MEASUREMENT, AND TEST FINAL MANUFACTURING

Using orthogonal frequency division multiplexing (OFDM) as an example, these calculations are made for each burst and data vector, resulting in an individual EVM (the error vector for a particular instant in time relative to the symbol clock). Adjacent channel power. When two or more signals (f1 and f2) at different frequencies are applied to an amplifier, nonlinearities in the amplifier cause the output to contain additional mixing frequencies called intermodulation (IM) products. These occur at frequencies (mf1 ± nf2) and at (mf2 ± nf1), where m + n is the order of the IM product. For example, the second order IM products would be at f1 + f2, f1 − f2 and f2 − f1. Even-order products are located near the baseband, while odd-order products are located on either side of the input signals. As an example, if two input tones are applied to the input of the amplifier, the output consists of amplified versions of the two input tones, plus odd-order intermodulation products caused by amplifier nonlinearity. If the frequency spectrum is divided into channels of equal bandwidth located next to each other, and the two input tones are applied, distortion in the amplifier causes signals to appear in the output adjacent channels. In the digital-modulation world, the two tones at the input are really replaced by an infinite number of tones (or noise) within the defined channel bandwidth. The energy generated by amplifier nonlinearity in adjacent channels is called spectral regrowth and is measured as adjacent channel leakage. The actual specifications take the measured spectral regrowth within a specified bandwidth and ratio it as a relative quantity to the desired power in the main channel. This is done for each of the two adjacent channels above and below the desired transmit channel, expressed in dB and is called adjacent channel leakage ratio (ACLR). Architecture of an RF System. The RF SOC device will need the same class of analog and digital test capability as outlined in these sections respectively. Additionally, the RF part of the test system will have to be able to source and measure RF signals. The capability required will need to match the needs of the device under test in terms of specifications, for example, frequency, bandwidth, power, purity, and dynamic range. The number of resources and how many are active at the same time will also need to match the device requirements. A suitable architecture is shown in Fig. 19.10. These can be simple, single-frequency sources or more complicated ones such as multifrequency sources that modulate data onto a carrier or even frequency-hopping sources that instantaneously change frequency a certain number of times per second. The standards for the modulation schemes, which are numerous, need to match the device requirements as well as the

RF interface 8 GHz source

6 GHz source

PA

Source MUX and 3-tone combiner

6 GHz source (optional)

8 GHz source

LO distribution assembly

M RF bridge U X RF bridge

RF to IF down conversion

19.30

LNA

PA PA RF bridge

Narrow BW RF receiver IF mux Wide BW RF receiver/ analog inst. (optional)

Analog signal conditioning module

M U X

M U X

-A -B -C -D -A -B -C -D

-A -B -C -D Baseband IQ

Pogo interface

FIGURE 19.10

Architecture of an RF SOC tester.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.31

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.31

number of frequency hops per second. The amount of noise present on the system is always a consideration. RF, because of the frequency involved, has special fixturing considerations, not only for the DUT board, but also for the construction and location of system resources. Also with today’s COT pressures, the architecture needs to support multisite configurations both in performance and resource availability as mentioned in this section. Basic RF SOC Test Setups. The basic test setup for an RF SOC is similar to mixed-signal testing. Briefly, this includes bringing any EDA data into the test environment and consulting with the specification sheet for the test list and basic setup conditions, including stimulus signal and where and when to measure outputs. The parameters that are measured could include traditional tests such as gain, linearity, and distortion tests or tests very specific to its RF functionality, which could include the system-level tests explained previously. 19.2.9 System-Level Integration Today higher integration and lower cost requirements are driving some markets toward system-level integration. The consumer market typically drives smaller application form factors and cheaper prices; some examples of this are—cell phones, CD and DVD players, and PDAs. An SOC refers to the complexity level where any of the previously mentioned tests and IC disciplines can be included, such that the entire system is included on a single chip. This has many COT and performance benefits. Typically, the functions for these are stand-alone IP blocks that can be readily glued into designs that are on the same die, enabling complex SOC designs to be completed rapidly. These could also come complete with test vectors and a program as will be discussed later. A system-in-a-package (SiP) is a device that combines multiple individual semiconductor die into a single package. The partitioning of the functions of the different die is determined by optimizing technologies to achieve the end result—improved performance, minimizing cost, improving TTM, or a combination of these. There are many test ramifications of system-level testing, including increased functional and performance complexities, increased pin (package) and pad (wafer die) counts, faster time-to-market, and even the potential to require multiple pass testing because one tester may not have all the necessary functionality. This trend has driven test vendors who wish to test SOCs and SiPs to integrate all these technologies into a single platform from single “niche” market tester backgrounds. Multiple pass testing with single technology niche testers is not usually economically feasible, especially in the consumer marketplace. An exception to this, where multiinsertion testing can be more economical than single-insertion testing, is in cases where resource utilization is grossly mismatched. For example, if a large DRAM is one of the die in the package, it may be more economical to test this in a separate insertion on a lower-cost memory tester. Another good solution to this requirement would be to resort to a KGD strategy that did not require full memory testing in the SIP package. The SOC tester of today incorporates architecture from all the market segments outlined in this section, although digital, mixed signal, memory and RF are the dominant features. With this increase in capability, there needs to be a focus on COT, because of consumer market demands. Test vendors are responding with more parallelism to meet these needs. They are also working on ways to speed up TTM including concurrent engineering, automatic development, and test emulation, all of which will be explored in Sec. 19.5.

19.3 HOW TO PREPARE, PLAN, SPECIFY, SELECT VENDOR, AND PURCHASE TEST EQUIPMENT This section will discuss a methodical approach of how to prepare, plan, specify, select vendor, and purchase test equipment. Some of these steps may be skipped for a variety of reasons, such as time, cost, and available resources. Also purchase decisions may not be made only on new technologies or Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.32

INSPECTION, MEASUREMENT, AND TEST 19.32

FINAL MANUFACTURING

devices; they may be made for a variety of reasons including lowering COT, obsolescence, or seeking partnerships advantageous to both parties. 19.3.1 Understand the Test Need The first thing to do is to understand the end application focus for the IC. Based on that, IC designers will design a chip that will function in that application. The IC designers will know what kind of source (stimulus) and measure (response) each circuit and pin will require. A device data sheet is a description of how the IC operates, its end application, and every parameter critical to its operation. These parameters and the functionality of the part will dictate what kind of resources will be required in the tester. The market segments of the various common types of devices were described in Sec. 19.2. The device data sheet specifications are design guidelines for designing the IC into its end application. Some of these rules are more critical than others and will be dependent on the design of the IC and the end application itself. The limits are the not-to-exceed low and high numbers that define the performance. Characterization was described in Sec. 19.1, and a decision may be made to characterize the part using bench equipment where an application mock-up is used, or test equipment can be used for the application’s stimulus and response. Once a proper characterization is done, then the production decision of rack and stack versus ATE needs to made. ATE Versus Rack and Stack. ATE refers to a fully integrated test solution supplied usually by one manufacturer. The advantage to selecting an integrated test solution is that a single vendor is accountable for all the engineering, manufacturing, and support of integrated hardware and software, documentation, spare parts, calibration, and diagnostics. Rack and stack refers to the practice of building a test solution from stand-alone components. This would encompass all the responsibilities applied to building the tester architectures and software to control them, outlined in Sec. 19.2. When comparing the costs of an integrated solution versus rack and stack, it is important to factor into this decision the engineering time required and also assume a certain amount of time-to-market to a rack-and-stack solution—not just the “hardware costs” of each. The IC manufacturer must weigh all of these factors when making the rack and stack versus ATE decision. Different markets have different requirements, but for most manufacturers, cost-of-test and timeto-market are the two biggest factors determining the success and profitability of an IC product, as explained in Sec. 19.1. Guaranteed Versus Typical Limits. On a device data sheet, most parameter limits are tested in production and can be guaranteed to be between the minimum and maximum specification. Other test parameters are not tested in production, but have been characterized to “typically” be at the nominal specification. There are various reasons that a limit may be typical instead of tested. For example, it may be difficult to test a particular parameter in production because of fixturing, long test times, or simply the lack of failure over a large number of devices. Typical limits lower the COT and perhaps even reduce the requirements that the test solution needs for production. However, in some market segments, preferences and potential price premiums may be given to manufacturers with guaranteed limits. The IC manufacturer needs to determine these tradeoffs. If the decision is to go with guaranteed limits, then the correlation and repeatability requirements need to be determined. The role that repeatability plays was described in the six sigma discussion in Sec. 19.2. The end application will also determine how close the correlation of known good devices and production units needs to be. Typically the closer the correlation required, the more resolution and accuracy the production solution needs. The ultimate judgment of how well a test is screening bad parts is from the customer and the rate of device returns. Sometimes manufacturers even do production correlation by comparing the tally of good and bad devices. Test Philosophies. There are different philosophies regarding what IC manufacturers want to achieve with testing. Largely this is determined by the market norms and the manufacturer’s desired

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.33

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.33

perception within that market. A manufacturer with the highest quality philosophy wants to test every parameter possible in the best possible way. Examples of this would be high-end, expensive, mission-critical and leading-edge technology markets. Other manufacturers want to be perceived as technology market leaders. They have a dedication to quality and lead in technology but in less “mission critical” markets. Others promise a fast turnaround, taking proven technology and being a second source or improving on it in other ways. Lastly, there are those who deal in largely commodity chip markets where the profit margins are thin and COT is a key consideration. An example of this is devices used in the consumer market, such as DVD players. What Is the IC Manufacturing Company’s Product Line Emphasis? The emphasis of an IC manufacturer’s product line usually aligns with the test philosophy as a rule of thumb. If the product line focuses on R&D technology, either through the IC process or design functionality and performancepushing technology, then rigorous testing will be required. If a product line is market focused and has a goal of delivering the right device at the right time then a mixture of performance innovation and COT is required. If manufacturing cost management is a product line’s focus, then COT is the largest concern. In reality, many companies run their different product lines as a portfolio mixture of all of these. Also, some product lines exhibit portions of each of these traits throughout their product life cycle. General Purpose Platform Versus a Focused Solution. Another decision to be made is a generalpurpose platform versus a more focused solution to test very specific devices. Some factors to consider on picking a general-purpose platform include: Is the number of different products (product mix) high enough that there is a benefit to a one-or two-platform strategy? The general-purpose platform lifecycle may justify the investment in equipment and training, if it is long and can maintain excellent OEE past its depreciated timeframe. Also, many vendors will field upgrade new capabilities into their existing platform base and even may have features that allow “pay as needed” system capabilities that keep the platform technology ahead of requirements. Other factors to consider on picking a focused platform include: Will specific devices keep the utilization high enough to justify a focused platform? A focused platform can be a good choice if the number of products is low, but the volume of product sold is high. Linear and Flash memory market segments are some good candidates for this. 19.3.2 Use Industry Contacts to Determine Vendors in the Specific Market Segment of Interest Once the needs for tests have been decided, vendor identification is next. Using industry/trade publications, professional sources, and the web to identify the leaders in the desired market segment is a good start. Another source can be to examine what one’s competitors are using for a test solution, or stated another way, what are the market leaders using for an IC test solution? All the normal business checks into the history and reputation of the company should be done when considering a test supplier. 19.3.3 Planning and Justifying the Selection Process The decisions made as a result of understanding the need to test will determine what kind of equipment is needed. Using industry contacts will determine which test vendors or equipment providers are in that market segment. These decisions can involve large capital expenditures and significant time for many resources within a company. This selection must be approached methodically and professionally with a plan to justify to the management and investors that a tester is required, or that a new tester is needed if the current platform no longer meets the needs. Technology gaps or disconnects, when the current solution can no longer meet the device requirements, are typically the easiest to justify. However, there may also be cost drivers that can justify a new test platform, such as the need to lower COT or to retire old equipment that is no longer cost-effective. The latter may be Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.34

INSPECTION, MEASUREMENT, AND TEST 19.34

FINAL MANUFACTURING

due to excessive downtime and/or maintenance costs, or poor yields caused by tester inaccuracy. There can also be time-to-market drivers that require faster test development and production release. For business reasons, it may also be desirable to have a dual vendor strategy for testing, which requires that a second test platform be selected. This approach has a lot of advantages including the lowered risk of an automatic fallback plan. However, it is difficult to have a close strategic partnership with two vendors. If the SCM model is used, the availability of time on equipment at the test house must also be considered. The analysis should include various tradeoffs in test methodologies against capital cost. This includes such things as engineering characterization versus high-volume production testing, test coverage at wafer probe versus a final package test, and at-speed performance testing versus functional verification testing with structural (scan and BIST) testing. There should be a target COT based on the average selling price (ASP) of the device and the overall manufacturing costs. This, along with other factors, such as throughput, yield, and utilization, will determine the target tester capital cost required to meet COT goals. For more information on cost-of-test, see Sec. 19.1. The justification should also include alternatives to purchasing capital equipment. Some alternatives include leasing or renting the tester, renting time on a tester at an external engineering test center (ETC) for test development and characterization, or outsourcing high-volume production to a subcontract manufacturer. Refer to Sec. 19.1 for more information on the subcontract manufacturing outsourcing model. A Purchase Proposal Outline Should Include the Following Segments: 1. 2. 3. 4. 5. 6.

Definition of problem statement or gap that currently exists Company philosophy of how to solve the problem citing company core competencies Analysis of the test philosophy chosen and the resources needed Alternatives and their impact on the company and the initial problem statement Request for approval of purchase proposal Post-approval implementation plan including an initial vendor market survey and a decision as to which vendors to invite to participate 7. “Paper evaluation” to narrow down vendors to a “short-list” of two to four vendors (see Sec. 19.3.4). Note that the more vendors selected, the more support will be required a. Benchmark with two to four short-listed vendors including estimated costs for this process b. Roadmap presentation from vendors that successfully complete the benchmark c. Selection of primary and secondary vendors 8. Negotiation of contract on final pricing, terms and conditions (T&Cs), and acceptance criteria 9. Placing of a conditional purchase order with the primary vendor for initial system(s) with a probation period for the vendor to deliver on commitments and meet acceptance criteria a. Final acceptance and initiation of purchase contract for additional systems, as appropriate There should be a well-defined, unbiased evaluation process that is clearly documented and well understood by the evaluation team and the vendors that are invited to participate. The support of upper management for the evaluation process and their commitment to endorse the decision that is the outcome of the process is critical.

19.3.4 Building the Evaluation Criteria to Compare Vendors and Get to a “Short List” A “paper evaluation” using a list of criteria or “evaluation matrix” is an effective means for comparing various vendors and narrowing them down to a “short list.” An evaluation matrix is seldom used to make the final decision, but rather, to remove unqualified vendors and select the top tier Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.35

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.35

suppliers to proceed to the next phase. This next phase is typically the benchmark phase, where the “paper performance” is physically verified. Benchmarking is discussed in the following section. A good evaluation matrix can provide a basis for an impartial decision and should evaluate business as well as technical criteria. Although the personal experiences of team members, both positive and negative, should be considered in the evaluation process, personal biases should not overly influence the decision. The various categories should be weighted with a higher scaling number given to the areas of more importance. The graded number multiplied by the scaling factor provides the subtotal and then these are all added together for a total scoring for a vendor. A sample list of evaluation criteria includes the following: Tester Evaluation Criteria: Technical Criteria Specifications and performance. This is based on the vendor’s published specifications— determine whether “guaranteed” or “typical” specifications Guaranteed: warranted performance that is verified by calibration, diagnostics Typical: performance expected under normal operating conditions Hardware Digital: number of pins, data rate, number of timing edges, formats, EPA, OTA, vector capabilities, capture memory, sequencer capabilities, driver and comparator pin electronics Clocks: number of pins, frequency, accuracy, jitter Device power supplies: number of supplies available, voltage and current force/measure ranges, accuracy and speed, IDDQ capability PMU: types—whether system, per board, or per pin; number of pins, voltage and current force/measure ranges, accuracy and speed SCAN: number of pins, vector depth, ac timing capabilities Memory test: number of pins address and data, HW or SW APG, APG rate, scrambling, pattern library, pattern language, redundancy repair capabilities Analog: number of pins of source and measure, BW, sample rates, number of bits of resolution, spurious free dynamic range (SFDR), and accuracy RF: number of pins of source and measure, frequency range, power levels, accuracy, modulation formats Software Workstation, Operating System, and Networking Environment Software usability (development environment, SW languages, and/or GUIs and debug tools) Reliability (system running and bug issues) Revision control Design-to-test links and ATPG tools from EDA/simulation tools Support for STIL, CTL, other industry standards Data logging, data collection, and analysis tools (STDF, statistical management of data) Ease of integration into the IC manufacturer’s design and production processes Scalability—flexibility to cover a broad set of applications Useful life of the tester Future upgradeability: “head room” and flexibility of architecture Committed sales and support life of platform Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.36

INSPECTION, MEASUREMENT, AND TEST 19.36

FINAL MANUFACTURING

Special needs for design verification/characterization Production needs See Sec. 19.4. Tester Evaluation Criteria: Business Criteria History of the ATE vendor in the industry Financial performance of the company References Past performance and recent trends Cost of ownership Capital expense Request official quotes (list price) for various typical configurations for range of target devices, product families for engineering, wafer sort, final package test. off-line workstation HW and SW Software license costs and terms Terms—duration, global, node-locked, or floating Warranty Cost of Application Support and Test Development/Program Conversion Services Maintenance costs (HW and SW support contracts, spares, training) Training costs (test development, maintenance, operator) Facility costs (power, floor support, special cooling, air) Volume Purchase Agreements and Discount Rates (for testers, maintenance, and training) SCM availability of platform (for IC manufacturers subscribing to the SCM model) and loading Contract terms and conditions (T&C’s that include payment terms, cancellation penalties, guaranteed deliveries) COT per good device (see the COT section in this chapter) Track record of system in the industry Length of time on the market and maturity of system Installed base SCM installed base Production capacity Number of systems that can be shipped each month Standard delivery/supplier response time Ability to quickly respond to upside requests Existence of and access to technical expertise Number of resources, expertise, and experience level (application and maintenance) Location of resources relative to the IC Manufacturer’s business sites

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.37

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.37

Third-party support Test development services Load board design and fabrication services SW tools (DFT, statistical analysis) Documentation—on-line or context sensitive Training—courses, locations, and frequency Consumables There is some level of subjectivity to this process because there will be different tester architectures and different terminology used by vendors, as well as different ways to specify accuracy. There may be a meeting where the vendors present their answers, along with any additional factors they think are relevant, and answer open questions. Sufficient time should be allowed in the process to complete each step in the process and to allow a decision to be made and implemented before a critical need develops. 19.3.5 Benchmark Evaluation Process Benchmarking is a process where the test vendor(s) develop a test program in order to compete for business. This is a great chance for the IC manufacturer to compare results from different vendors. In this comparison, the winner can be selected and backup strategies can be defined. The first step is to develop a matrix of selection criteria, prioritize these criteria, and come up with a fair, objective way to judge results across all vendors. This is similar to the evaluation criteria in processing but the factors are different. For example, some typical factors would be—completeness of the project, speed of completion, ability of the vendor to develop the program with minimal help from the IC manufacturer, test execution time, analysis of data including correlation to passing and failing units and repeatability, COT (implying potential parallelism in the tests), software tools, and reports to display the data easily and clearly point out problems. There are also more abstract factors such as software usability of the program generation, debug and production environments, and the availability of tools to translate data from the EDA environment. Another decision to be made is which device to select for the benchmark. This could be an advanced technology part or possibly a high volume part, in order to reduce the COT and improve the profit margin. The use of stable, known devices will add consistency to the process whereas choosing new unproven parts can add uncertainty. The more parts selected, the more support investment required by the vendors and the IC manufacturer as well. If there are multiple parts from different product families with different requirements, consider a subset of tests for each part to show unique capabilities needed for each. The decision must not put risk into the revenue stream of the IC manufacturer. A common test list that all vendors must complete should be made. A deadline for completion then needs to be established. Once all criteria are established, the IC manufacturer supplies data logged ICs with repeatability data to the test vendor. The vendors then complete the project as described in Sec. 19.2, “Common Strategies of Implementation.” When the deadline occurs, the IC manufacturer evaluates the results according to the criteria and makes a decision on the relative success of each vendor. 19.3.6 Test Vendor Support Different IC manufacturers need different kinds of support. The type of support required depends on many factors including the company’s core competencies, available labor pool, and company philosophies. Test knowledge is one type of support that requires basic and advanced test theory and proven implementation. Device knowledge is an understanding of the DUT needs and application environment. Tester-specific knowledge is the knowledge of a specific vendor’s hardware and software. Lastly, a company may simply need a larger labor pool than they currently have or simply want to outsource for a variety of reasons. Typically an IC manufacturer will want a combination of all of

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.38

INSPECTION, MEASUREMENT, AND TEST 19.38

FINAL MANUFACTURING

the above. Another variable in the support model is the degree to which the IC manufacturer wants to depend on the test vendor for support. A tradeoff decision must be made between having the revenue stream (production) and technology advances in the form of characterization in the hands of a vendor or maintaining control of those factors within the IC manufacturer. 19.3.7 Roadmap Alignment Process Purpose of Roadmap Alignment. Adding or changing a test platform is a large investment, not only in capital outlay, but also in infrastructure costs including engineering and manufacturing software environment and tools, training, interface fixturing hardware, and maintenance. To ensure maximum returns on this investment, when selecting a tester, consider how the platform will meet long-term requirements, in addition to how it satisfies the immediate needs. The way to accomplish this is to compare the test vendor’s roadmap for planned future enhancements and the capabilities and features of their platform, to the IC’s features and capabilities and test requirement roadmap for future devices. Comparing roadmaps for a two-to-three-year timeframe is typical. The information should include device applications and functionality (digital, linear, mixed signal, RF, memory, or highspeed interfaces), pin counts and package types, performance (digital data rates, clock frequencies, analog frequencies and bits of resolution, RF frequencies and signal levels, and the required accuracy), design-for-test (DFT) methodologies, and any special test challenges or requirements, as well as the device life cycle, and ASP and COT targets. In fact, COT road mapping is becoming a necessity in cost-driven markets such as the consumer market. Similarly the IC manufacturer can expect test vendors to share their test platform roadmap for a two-to three-year timeframe. The information they disclose should include targeted device applications and functionality, tester resource pin counts, performance, DFT methodologies supported, software tools and enhancements, time-to-market enablers, as well as any cost or COT reduction targets. It is critical to determine whether these roadmap enhancements will be incorporated in the current platform being evaluated, or in a planned next generation platform” that may or may not be compatible with the current generation platform. Roadmap components that are not specific to the current platform can carry the same penalties as switching platforms in the first place if a future generation model is not compatible. Analyzing the overall synergy, identifying gaps, and developing resolutions or workarounds are all part of the alignment process and are critical to ensuring that once a business relationship with a vendor is started, it will not end abruptly with negative consequences. Alignment is not always complete, and it is common for the vendor and IC manufacturer to revise roadmaps on a continual basis. It is important that the test vendor has the credibility of meeting roadmap plans and commitments and has a track record for doing so. Nondisclosure Agreement. Sharing roadmap information requires both companies to execute a nondisclosure agreement (NDA), confidential disclosure agreement (CDA), or some other similar document. It is necessary to share information about future products and capabilities that is not publicly available during the roadmap process, and the NDA is a legal document to protect that information from being widely distributed, especially to competitors. Specifics in the NDA include the type and purpose of the information to be disclosed by each party, the duration of the NDA under which information will be disclosed, and the timeframe this information must be kept confidential. An NDA should also include the process for documenting what information has been disclosed, to whom and when.

19.4 WHAT ARE OPERATION, SAFETY, CALIBRATION, AND MAINTENANCE CONSIDERATIONS? Once a test solution has been selected, it is now time to plan for the successful site installation, operation, calibration, and maintenance of the system. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.39

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.39

19.4.1 Site Planning Two months before installation, the planning process should begin and be treated as a formal project. This includes defining the vendor and IC manufacturer roles and responsibilities, timeframes, and a list of deliverables. The vendor should have site planning and preparation guidelines that identify any unique requirements for a particular system. Typical Requirements.

Some of the most typical requirements include:

1. Shipping dock requirements: Height of the unloading dock and door size requirements for all access points leading to the install site. 2. Footprint: Space requirements for system and periphery items, including proper access room. 3. Floor: A raised floor is a cleaner and a safer environment because most of the cables and hoses are below the floor; however, it is more expensive. If used, make sure the raised floor can meet the total weight and pounds-per-square-inch requirements of the system and all other equipment to be located within the test cell. 4. Power: Number and recommended placement of system power connections. Voltage, number of phases and current requirements for each system connection including peripherals and other planned equipment for the test cell. Any special grounding requirements of the system or other equipment to be placed in the test cell must be identified. 5. Power conditioner: The site needs to be monitored for noise and power stability and a decision must be made about whether a power conditioner is needed. 6. House chilled water availability or chiller unit: Used for liquid-cooled systems. 7. Air temperature/relative humidity: Must meet both ambient and stability requirements. 8. Altitude: Maximum altitude specifications must be adhered to. 9. Airborne contaminants: There may be both system as well as industry requirements (for example, cleanrooms). 10. Electrostatic discharge damage prevention: There must be ESD prevention equipment and procedures in place to prevent the ESD into sensitive system areas, especially for the DUT printed circuit board. 11. Vibration requirements: Some systems testing IC wafers may have requirements in this area. 12. Compressed air and/or vacuum: Needs to meet pressure and consumption-per-time unit requirements. 13. Radiated signal immunity: Some systems may require the absence of any type of equipment generating signals that could interfere with the system, such as cell phones and pagers. In rare cases, even local radio stations or other communication equipment could be a problem. Site Preparation. Four to six weeks before the installation date, the implementation of all the plans made in the previous step should be completed. For all work to conform to the installation requirements, the responsible party must ensure that all the proper permits are obtained and all the implementers have proper credentials and authorization. Site Verification. Two weeks before the installation date, all the items to be implemented and the entire plan should be verified. Enough time should be allotted to allow for potential rework of any item not passing verification. Receiving the System. The week before the actual installation, the system should arrive at the destination. A system component inventory is done, as well as any other third-party components that might be required. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.40

INSPECTION, MEASUREMENT, AND TEST 19.40

FINAL MANUFACTURING

Installation. The test vendor will usually complete all the operations in this phase except for the final power and plumbing connections that require a certified electrician and plumber respectively. If additional third parties are involved in the overall solution, some of the integration may need to be performed by several vendors or involve the IC manufacturer in the process. Briefly, the basic steps in this phase include the physical assembly of the system, testing power, wiring up the power, connecting all other environmental needs (water, air, vacuum), powering up the system, running diagnostics, and running calibration. Often there are documents certifying that the system meets certain calibration standards, such as the National Institute of Standards and Technology (NIST).* These should be archived for potential industry compliance (medical, military, and aerospace) and to record the condition of the system at the time of installation. Once the previous steps are completed the system is ready for normal operation. 19.4.2 Operation of the System There are many different operating environments and personnel that will use the system. The operational knowledge requirements for engineers who develop test programs, or perform yield or failure analysis are very different from the ones that system operators will need while running production. Another aspect of operation is the system administration that will be required to maintain the software. The test vendor will specify all of these requirements. The basic operational knowledge requirements include powering the system up and down, exchanging DUT boards on the test head or other fixturing, emergency shutdown procedures, logging into the system software, starting up the software environment to use the system, basic window and mouse operation, and basic usage of the software tools and help screens that will be needed to accomplish the desired task and monitor the test results. Many times a test vendor will further simplify the production operation by providing a simpler interface that will bypass the need to know many of the software operations described earlier. This could either be a much simpler operator interface available within the software environment or another piece of hardware, the operator console that is typically a smaller dedicated LCD display with simple switches to control the software environment. In the production environment, other third party equipment such as probers, handlers, and manipulators that are part of the overall test cell will need to be understood as well. More advanced operations include • • • •

Running the software tools to develop a test program Digital vector or other EDA tool translation Running the test program debugger Using the software tools to get statistical data including the mean and standard deviations to understand stability • Getting the final data log test limits • Producing Standard Test Data Format (STDF) or ASCII format data for additional analysis The system administration tasks include understanding operating system basics such as file systems, backup and recovery, managing user accounts, system printers, and other peripheral devices, as well as network and system security. Additional duties include understanding the system networking, the company network environment, and interfacing the two together. Often system administrators will automate these normal tasks with software programs called scripts that may do the task on command or even set up an automated time chronology to do the tasks without intervention. Another aspect of operation is the requirement for consumable items such as printer paper and cartridges, as well as tapes or other digital media for backup and recovery. Usually the system itself will require consumables, for example, pogo pins for the test head or DUT board fixtures. *

NIST website at http://www.nist.gov.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.41

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.41

19.4.3 Safety Some countries have government standards for safety. For example, in the United States, the Occupational Safety and Heath Administration (OSHA)* has set workplace safety standards. In other cases, industry organizations, for example, the International Special Committee on Radio Interference (CISPR)† have set standards. Radiated emissions (Electromotive Force/RF emissions): Standards have been established by the CISPR organization. If these are exceeded, a shielding mechanism must be developed. Acoustic noise emissions: There are standards for this, but the long-term potential hearing damage of engineers working around medium levels of noise for extended periods of time should also be considered. A low-cost solution is earplugs. Earthquake: Some special securing mechanisms to resist damage and injury in the event of an earthquake should be used if the installation is in an impacted area. Fire prevention: It is possible to reduce fire risk by putting fire sprinklers in the installation room. Open exposure to voltage/current: Many of the standards agencies have limits on the amount of voltage and current that can be exposed to a potential user in a normal operating environment. If these limits are exceeded on a DUT board, the requirement would be to add nonconductive insulation or compounds on these areas. Nonconductive epoxy glues are effective and easy to use for this purpose. In some cases a more elaborate approach may be needed, such as adding insulated covers incorporating an interlock switch to disable hazardous voltages when opened. External cable routing: An area with excessive cabling or hoses can be a hazard. One possible solution is to tie these cables together. Routing cables and hoses under a raised floor is another potential solution. If cables are tied together, care needs to be taken not to degrade signal performance caused by possible inductive coupling of signals. Lifting of weight: Care should be taken not to require excessive lifting of weight in normal daily operations. If this condition exists, either a different procedure should be developed or multiple people should be used for the lifting.

19.4.4 Calibration The tester hardware, and occasionally other equipment within the test cell, requires periodic adjustments and/or verifications to maintain its performance and to ensure that it stays within its published specifications. The passage of time and temperature changes will determine the required calibration interval. During calibration the tester hardware is occupied, so engineering and production cannot continue. Depending on the system and type of calibration requirement, external fixturing may be required for the calibration to be successful. Different systems have different needs for calibration and the test vendor will have a time interval specification and often a temperature fluctuation recommendation for calibration. A more advanced aspect of calibration is using the calibration data to predict future failures as the data diverges more from the nominal values. 19.4.5 Maintenance Diagnostics isolate and specify equipment failures. Spare parts may be procured as needed from the vendor or stored at the actual installation site for an even faster response. Also, many test vendors

*

OSHA website at http://www.osha.gov/. CISPR website at http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=dirdet.p&committee=SC &number=cispr. †

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.42

INSPECTION, MEASUREMENT, AND TEST 19.42

FINAL MANUFACTURING

supply cooperative agreements that can include even remote diagnosis of system failures. Two figures of merit in this area are Mean time between failures (MTBF): A figure measuring how often the tester is unavailable for productive use Mean time to repair (MTTR): A figure measuring how long it takes to make a repair

19.5 FUTURE TRENDS AND CONCLUSIONS 19.5.1 General Trends Economic growth and strong competition followed by a downturn is the cyclical nature of the semiconductor business. However, over time, this has led to a new business model. This model includes a new way of operating in a cost competitive environment with a strong focus on core competencies. It calls for outsourcing of nonessential operations, demands open communication, and removal of barriers that inhibit improvements in TTM, and it addresses the need for effective collaboration and operation in a global setting through virtual teams and agile business networks. The main result is market expansion of the different microelectronics-related industries to new and uncovered areas. This expansion has led to the metamorphosis of the previously heavy and weakly-linked supply chain to a new one that offers flexibility with various options of operations and is integrated in a way that surpasses the strength of the old one. This new model is well suited to the SCM model outlined in Sec. 19.1. The new business model allows a plethora of information to be shared among all the links of the supply chain related to technical and business needs. It allows companies to expand into new areas in their own market space for the purpose of strengthening their position in the market. As a result, EDA, ATE, and test houses link their operation into their customers’ needs with a focus on cost reduction and competitive strength for design houses and semiconductor companies. The focus is on aggressive schedules for faster TTM at the least possible market cost. 19.5.2 Cost of Test—Expansion of the Basic Equation One of the main shifts is the change from a static target cost to a competitive market cost. The cost equation is extended from research and development into design, manufacturing, test, and production. Each of the individual units has a cost equation with preassigned factors and as the environment changes, the equations change as well. In particular, the cost equation for testing used to be impacted mainly by the capital cost of the test equipment, utilization, and frequency of maintenance directly related to the test equipment. Test yield used to be the main and often the only factor related to device testing. In a typical setting, one device was tested at a time and the overall yield provided the information on the test cost across a number of quality devices versus the whole production run. In the new environment, this changes to include the testing of multiple devices in parallel with the objective of reducing the cost of testing by sharing the test equipment overhead time across multiple devices and by increasing the utilization of tester resources—the definition of multisite testing. The cost reduction of multisite testing is possible only when the test equipment is capable of handling multiple devices in a parallel setting. The factors to be considered include the number of available driving and receiving points, the variety of test capabilities, including digital, analog, and RF functionalities, and software that can address tests and reporting of multiple devices at the same time. For an IDM company, a cost analysis is required to justify the cost of multisite testing based on the number of increased resources. The IDM company also needs to consider the product mix in this equation. If other products are run that do not require all the resources a multisite program uses, it may not be an effective utilization of resources. On the other hand, using the SCM model, a design house often does not own its own test equipment for production tests, so multisite testing is a very attractive way to increase the number of devices tested within a specified time interval.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.43

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.43

Multisite testing is proven as a factor for better management of test equipment requirements and may reduce the requirement for additional capital purchases. However, since Multisite test program development can have an impact on TTM, this must be understood and appropriately planned for. The next step is maximizing the effect of parallel testing by implementing its capability in an individual device. Concurrent test (CCT) is the parallel test methodology that allows the simultaneous testing of multiple IP cores within a device. Concurrent test requires a good understanding of the test equipment capabilities and also the way the test program generation is done. Successful CCT is based on careful planning and implementation discipline. It calls for a cross-functional team of design and test engineers to work up front, planning the solution, then it requires more test program integration on completion of the individual core test programs. The trend is toward test program reuse, which requires that the software related to test programs be capable of merging test programs of previously tested cores with new ones. Combining this parallel test solution with the multisite model described previously allows even more efficiency. The benefits include reduction of test time, greater usage of test resources, and a more effective utilization of them, improving the return on invested capital. Other benefits include improvement on the quality of parts by running the device closer to its end application environment and the reduction of the hidden cost of returns, as well as improved customer satisfaction with the delivery of products with a reduced statistical factor of defects measured in parts per million. Because CCT applies to single device execution, the individual cores within the device need to be properly designed for parallelism and isolated so that the testing of one IP core minimally impacts others. Core isolation for any form of parallel test application is a new test methodology linked to DFT tools offered by EDA companies. This expands the linkage between design and testing. EDA companies that traditionally provide design tools are currently expanding their product offering to include design methodologies that assist design for testability. In addition, there is movement in the design for manufacturing (DFM) area where new design methodologies interact with ATE for fast diagnosis of failures. This shows the strength of the new supply chain’s links with feedback loops between EDA and ATE for faster TTM and time-to-volume (TTV).

19.5.3 Time-To-Market—DFT as a TTM Accelerator With the increasing complexity and high gate counts enabled by deep submicron SOC manufacturing processes, designers face a formidable challenge in keeping design cycles and manufacturing ramps to manageable timelines. There are two major trends working against shorter timelines that will be discussed. The first trend is IC process roadmaps, which are roughly doubling the gate density of silicon every 18 months and allowing integration of different circuit types on the same piece of silicon. For example, integration of CPUs, digital logic, memory, analog circuits, and high speed I/O buses onto a single device is typical. This complexity drives an exponential growth in the number of connections in an IC and also creates new failure mechanisms with different failure modes. The second trend is the increased reliance on third-party IP core licensing and IP core reuse that creates situations where the designer is not familiar with the design or the test requirements of the embedded core in an SOC device. Increasingly, cores are delivered with synthesizable code. These “soft cores” may be easily and automatically integrated into the target technology and design database. Less often, IP cores are delivered in artwork from as “hard cores” that are more difficult to port into the target technology. Hard cores cannot be logically integrated into the design database of the device and thus create unique issues in testing. DFT adoption, coupled with robust IP reuse processes and industry standards can go a long way toward compensating for these trends. The two major stages in the development cycle of an SOC where testing impacts the TTM are— the test development phase and the diagnostic/debug phase (prior to release to manufacturing) as illustrated in Fig. 19.11. Industry standards and reuse also can lower COT along the entire process by speeding it up and improving efficiency and accuracy.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.44

INSPECTION, MEASUREMENT, AND TEST 19.44

FINAL MANUFACTURING

IP core database IC designs

Test development

MPEG

MPEG

1394

1394

ADC

DAC

FIGURE 19.11

Turn-on and characterization

High-volume manufacturing

Customer ship

ADC

DAC

Standards can help TTM and improve COT along the entire test development process

SOC development flow.

DFT During Test Development. If the design methodology and EDA tools support DFT standards, then third-party core test data can be integrated into the design database using IEEE standards such as Standard Test Interface Language (STIL) and Core Test Language (CTL), which is part of STIL. Therefore, the test engineer only has to generate new protocol corresponding to the new logic that has been developed. The tests for the whole device do not have to be regenerated. This reduces the possibility of errors in the test program and also shortens the test development time. DFT During Diagnostics. Robust DFT and standards also allow fast diagnosis and isolation of faults. The test failure data can be transferred back into the design environment and then compared with the netlist to isolate the fault location if the EDA environment supports standards. One of the major barriers to widespread DFT and standards adoption has been the legacy infrastructure of ATE systems and the legacy toolsets still in use by many IC chip design groups. The linkage between the ATE and EDA environments depends heavily on the ability of reliable, fast, and seamless communication. Distributed Test Development. Distributed test development refers to the practice of having multiple test development engineers working on a single device, often in different global geographies. If the device has been designed with this practice in mind, the test development can be partitioned so that each engineer can focus on a block (or blocks) for which they are responsible. Parallelized test development can significantly reduce test development time for the device. 19.5.4 The Impact of Advances in Silicon Technology on Test Methodology How to Use Additional Die Space: Redundant Circuits and BIST. With logic gate densities doubling from approximately 40 million transistors per cm2 in the 130 nm process to about 80 million transistors per cm2 with the 90 nm process, chip designers have increasing freedom to add test-related circuitry to the device and in some cases redundant copies of a circuit, cell or core on the same die. This is a technique that has been in use in memory design for many years. Also, with this extra space, BIST and design configuration circuitry can be employed on silicon for self-diagnosis. If the BIST and design circuitry can do all the testing, and the circuitry is working as designed, there is no need to test the rest of the circuit with ATE. This is especially useful in large die since making the die tolerate a defect under certain conditions can materially increase yields as well as lower the test time by allowing only the BIST and configuration circuitry to be tested by ATE. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

20:00

Page 19.45

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.45

DFT Techniques for Analog Circuits. Designing analog circuits for testing is intrinsically more difficult than for digital circuits because analog circuits are less regular and analog signal paths are more difficult to isolate than their digital counterparts. Most analog DFT is done to isolate analog blocks so that they can be characterized individually and to enable the application of the test stimulus and the measurement of the test response at the internal nodes of these blocks. This test access is provided by inserting analog multiplexors or configuring the analog switches that are already part of the design. Such switches can also be used in some cases to reconfigure the circuit blocks to test each other. For example, an ADC can be connected to test a DAC. Particularly useful in testing radio transceivers and digital serializer/deserializers (SerDes), which are really analog circuits, is the concept of loop-back where an on-chip receiver tests an on-chip transmitter and vice versa. The loop-back connection can be made by switches internal to the DUT or through the test fixturing. Sometimes it is even possible to add feedback around an analog circuit in test mode to cause it to oscillate. In this “oscillation BIST” the health of the DUT is indicated first by the presence of an oscillation and, second, by this oscillation being at the correct frequency. Finally, there are often opportunities to alleviate the difficulties of transmitting high-frequency and high-quality signals between the DUT and the tester’s pin electronics by generating the stimulus and measuring the response with additional test circuits on the chip or on the DUT interface, i.e. the probe card or load board. Often these test circuits serve to convert signals, rather than to generate or measure them, by mixing frequencies up or down, amplification, or converting to dc. Emergence of DFT Testers. Recently, several tester vendors have brought to the market test systems that have been classified as DFT testers. These testers are distinguished by having a capital cost below $500K, digital frequencies of 100 MHz or less and large amounts of vector memory. These can either be designed as low-cost testers with this functionality or a cost-optimized scaled down version of a functional performance-based tester. Figure 19.12 shows the generally

Test techniques

Analog specs

Analog/Mixed signal functional

Pin specs

AC pin specs

Binning

At speed functional

Logic

Static functional

Analog circuit

Analog DFT-DAC, ADC, PLL, VCO, BIST

Memory

Memory BIST

Logic

Logic BIST

Bridges, opens

IDDQ

AC logic delay

AC logic delay (scan)

AC logic freq.

AC transition (scan)

Stuck at logic

DC scan and retention

Test access

Test logic verify

Connectivity, voltage, current

DC parametrics

FIGURE 19.12

Coverage

Functional tester

Test purpose

DFT tester

Geng(SMH)_CH19.qxd

Typical tester/DFT tester capability.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.46

INSPECTION, MEASUREMENT, AND TEST 19.46

FINAL MANUFACTURING

accepted view of the difference between a DFT tester and a functional tester. A DFT tester will generally not have the speed and accuracy to do functional tests and will also not have analog instruments that allow it to do SOC level testing. DFT testers require a sophisticated IC design environment and a design methodology that supports DFT. One of the goals of using a DFT tester is reducing the capital cost, but test times are generally longer due to the need to load and unload test stimulus and response data through serial scan ports. These ports generally run at a maximum frequency of 40 MHz. COT and TTM requirements are expected to drive significant changes in the approach to test over the next few years. With circuit densities exceeding 150 million transistors per cm2 with the implementation of the 65 nm processes, it will become difficult to continue to use current test approaches in the future. The performance gap between the ATE and the DUT will continue to grow and will make it increasingly difficult to do functional or at-speed testing for semiconductor devices. As a result, alternate approaches to functional testing may become the workhorses for SOC testing, with functional testing focused on testing the device’s internal test circuitry. The majority of SOC devices in the future will have integrated hard or soft cores from third parties. It is expected that IP reuse productivity will become a major challenge in meeting COT and TTM goals as designers work increasingly at the system level instead of at the gate or circuit level. Standards that allow designers to work at higher levels of the design hierarchy while being confident that the circuit level data have integrity are needed and are being developed, as in the case of the IEEE CTL standard. 19.5.5 Automatic Test Program Generators An automatic test program generator (ATPG) is a series of software steps to automate the development of a test program. It leverages data from the EDA process and adds to it code where either assumptions are made about device setups, or the end user can input data into variables to customize the program according to the device requirements. The advantages to ATPG over manual test program generation are shorter development time, higher fault coverage, fewer redundant patterns, and fewer errors. This technique tends to work well with devices of similar design or devices that are completely defined by their EDA data. Some examples of the market segments where ATPG is highly effective are—digital application specific standard product (ASSP), digital ASIC, and all types of memory. Analog and RF circuits are fundamentally different in the nature of fault models and there is difficulty simulating them efficiently. The EDA tools available in the mixed-signal market space are not as advanced as their digital counterparts and this makes complete ATPG for complex devices such as mixed signal, SOC, and SiP devices impossible with today’s tools. It is difficult to simulate noise and harmonic sources and since this is performance-based testing, many parameters are out of the scope of ATPG software, such as DUT board fixturing are unaccounted for. A hybrid model, using ATPG on some IP blocks and a more manual process on others, is the best case scenario. 19.5.6 Test Environment Emulation Test environment emulation is another concept where software emulates the DUT, tester source and measure resources, and the hardware fixturing. One such implementation of this used cdsSpice macromodels to model the IC, tester resources, and DUT board. This methodology used the same simulation environment as the IC design one, allowing interaction between the design and test environments. Once the user gets the simulated test working the way it should, further enhancements to this model could include automatic DUT board design and routing, automatic test program code generation, compiler code syntax checking, and even run-time error checks. The advantages are concurrent engineering of design and test, faster time to market, and the significant capital cost reduction of using a computer versus a complete online ATE system. The disadvantages include potentially long simulation execution times (dependent on the complexity of the modeling of the previously mentioned elements and CPU speed) and that the correlation of the simulation with the actual test setup is highly dependent on the accuracy of the modeling for all elements.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.47

INSPECTION, MEASUREMENT, AND TEST INSPECTION, MEASUREMENT, AND TEST

19.47

If the previous two concepts were executed well and with reasonable cost, the job of the test engineer could change to focus more on final real-world debug, correlation and repeatability studies. 19.5.7 Future Trends in Semiconductors The International Technology Roadmap for Semiconductors (ITRS)* is an organization dedicated to tracking and reporting future technology requirements in the semiconductor segment and test. The ITRS enjoys wide sponsorship and contacts including the Semiconductor Industry Association (SIA), the European Electronic Component Association (EECA), the Japan Electronics & Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), Taiwan Semiconductor Industry Association (TSIA), and the International SEMATECH. 19.5.8 Conclusion The continuing rapid advances in wafer fabrication and circuit technologies, as well as the changing nature of the electronics market create big challenges for semiconductor testing. As long as there are new circuit (product) designs, there will be a need for design validation testing. More important to test volume, as long as fabrication processes continue to advance such that they introduce new materials and structures and continue to push the limits of manufacturability in order to achieve higher performance and density, manufacturing test will be necessary. As the ITRS shows, there is no sign of these process advances letting up. But as these denser processes enable more functions to be integrated into a chip, the effort to test them, for example, number of vectors, instruments, and time, also increases. Since increasing the number of circuits on a chip can bury the potential faults farther from the chip’s external pins, this may cause the test effort to grow even faster than the chip’s functionality. Furthermore, increasing integration levels enables and requires the integration of a greater variety of circuit and function types thus requiring a greater variety of tester resources. New processes and device structures also add new defect mechanisms that may require additional tests to detect. All these developments threaten to increase the cost of testing a chip and decrease the chip’s quality. At the same time the increasing consumer orientation of the semiconductor market is forcing chip prices to decrease as functions are added. Since it is commonly expected that the test cost should remain a small fraction of the packaged chip cost, the test cost must also scale as dramatically as the fabrication cost. The challenge in doing so, as just described, is that the economics of traditional test strategies run opposite to the economics of fabricating chips as fabrication technology advances. The solution lies in new test strategies that are under active development in the industry. One of these new strategies is to get the DUT to perform more of its test itself through BIST. BIST has been proven to be most effective for memories. While not being completely effective for other circuit types, BIST can still reduce the burden on the ATE. Of course BIST also has the drawbacks of adding chip area and needing to be tested itself. But as soft errors, i.e., errors due to radiation from which the circuit always can recover become more common, some degree of BIST will increasingly become necessary for online test and repair. Structural test methods are coming into much more frequent use to address the test accessibility issue and are slowly being developed to work in analog. Various other kinds of DFT are being developed to improve test access especially at probe. Structural tests are being extended into various kinds of indirect testing that can reduce the number and variety of test instruments required, while increasing the sensitivity to defects. The most promising indirect methods rely on identifying statistical outliers. In such methods, analog measurements of any device parameter that differ significantly from some established pattern, e.g., parameter versus parameter, or comparison to values of neighboring die, indicate defects. The testers themselves are changing to facilitate these changing methods. For instance low-cost DFT testers have been introduced to inexpensively perform structural, and perhaps defect-based, *

ITRS website at http://public.itrs.net/.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH19.qxd

04/04/2005

20:00

Page 19.48

INSPECTION, MEASUREMENT, AND TEST 19.48

FINAL MANUFACTURING

tests. Testers are also being designed to increase their resource utilization by testing more chip functions concurrently and to test more chips in parallel. Finally, economic modeling is being used more commonly to optimize test flows and resource deployment. Sometimes this results in more tests being moved from final to wafer in order to reduce yield learning times and to produce better quality die for multi-chip packages.

ACKNOWLEDGMENT TO AUTHORS Donald Blair, Robert J. Smith, Jeff Brenner, George Redford, Neils Poulsen, Edwin Lowery, Hans Verleur, Asad Aziz, Ariana Salagianis, Shawn Klabunde, Michael Kozma, Gary G. Raines, Peter O’Neill, Gina Bonini, and William T. O’Grady.

FURTHER READING Agrawal, V., ATT Bell Labs, general reference papers website: http://www.informatik.unitrier.de/~ley/db/indices/ atree/a/Agrawal:Vishwani_=.html. Burns, M., and G. W. Roberts, An Introduction to Mixed Signal IC Test and Measurement, Oxford University Press, New York, 2001. Bushnell, M. L., D. Vishwani, and V. Agrawal, Essentials of Electronic Testing for Digital, Memory & MixedSignal VLSI Circuits, Kluwer Academic Publishers, New York, 2000. Chang, L. L., “Systematic Methodology with DFT Rules Reduces Fault-Coverage Analysis,” EE Design, August 2001, available at http://www.eedesign.com/isd/features/OEG20010803S0032. Kao, W., and K. Hasebe, “Simulation of Tester Environment Improves Design to Test Link for Mixed Signal ICs.” Proceedings of the ATE Instrument Conference, Anaheim, California, Jan. 14–17, 1991. Mahoney, M., “DSP Based Testing of Analog and Mixed Signal Circuits,” The Computer Society of IEEE, 1987. Goor, A., “MaLT: Memory and Logic Testing, Testing of Digital Systems, Introduction,” available at http://ce.et. tudelft.nl/~linden/testing/. Parker, K., The Boundary-Scan Handbook, Analog and Digital, 2d ed., Kluwer Academic Publishers, Boston, 1998. Tocci, R. J., Fundamentals of Electronic Devices, Charles E. Merrill Publishing Company, Columbus Ohio, 1975. Goor, A., Testing Semiconductor Memories, Theory and Practice, 1991. Maxfiled, C., Boolean Boogie, HighText Publications, Solana Beach, CA, 1995, http:/www.Harrington-institute/ downloads/whitepapers/UnderstandingSix-Sigma.pdf.

INFORMATION RESOURCES http://www.evaluationengineering.com/ http://www.testandmeasurement.com/content/homepage/default.asp?VNETCOOKIE=NO http://www.reedelectronics.com/tmworld/index.asp?layout=Community&industry=Semiconductor+Test& industryid=19033&rid=0&rme=0&cfd=1 http://www.semi.org/wps/portal http://www.ieee.org/portal/index.jsp http://www.itctestweek.org/error404.shtml http://www.semitest.org/site/Membership/index_html http://www.fabtech.org/industry.news/9907/05.04.shtml

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 20

GRINDING, STRESS RELIEF, AND DICING Kazuhisa Arai Yoshikazu Kobayashi Hideaki Otani Disco Corporation Tokyo, Japan

20.1 INTRODUCTION Traditionally, semiconductor wafers have been diced and ground separately. As new applications in sophisticated cell phones and personal digital assistants (PDAs) demand much thinner semiconductors, however, we are seeing the order of grinding and dicing reversed (dicing before grinding, or DBG). In this chapter, we will take a brief look at the basic technologies of grinding and dicing before moving on to manufacturing technology for ultrathin semiconductor chips, a high volume application.

20.2 GRINDING TECHNOLOGY OVERVIEW Grinding, also known as BG, more specifically is backgrinding. After the wafer fabrication process, the back of the device wafer is ground to thin the wafer enough for it to be assembled into a package. The overall package thickness is determined by global standards; the overall thickness has to be sufficient to accommodate the lead frame, chip, molded plastic, and epoxy paste or die attach film (DAF). Figures 20.1 and 20.2 show the two grinding methods, creep-feed, and in-feed. • Creep-feed: The wafer is ground by passing it under a cup wheel. The wafer does not rotate. From a finished thickness of 300 µm, an 8-in wafer with a starting thickness of 725 µm will need 425 µm ground away. With this much material to remove, the grinding is not done in a single pass. Most grinders have three spindles (Z1, Z2, and Z3-axis) for a rough grind, a medium grind, and a fine grind. As wafers have grown in size, so too have grinders. Creep-feed grinding was still used with 6 in wafers, but with the 8-in generation, it was almost entirely phased out in favor of in-feed grinders. • In-feed: In this method, the wafer rotates on a chuck table, as shown in Fig. 20.2, and is ground as the cup wheel is lowered. The thickness of the wafer is measured during grinding by a contact probe called an in-process gauge. When the desired thickness is achieved, the spindle descent stops and dwells (spark out) for few seconds and then moves onto escape cut, ending the grind. This setup allows grinding to be completed in two stages—rough grinding (Z1-axis) and fine grinding

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

20.1

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.2

GRINDING, STRESS RELIEF, AND DICING 20.2

FINAL MANUFACTURING

Wheel travel Wafer travel Grinding wheel

Grinding wheel

Wafer Spindle axis

FIGURE. 20.1

Creep-feed.

Spindle axis

Wafer

FIGURE 20.2

In-feed.

(Z2-axis)—meaning that the equipment can be smaller than a comparable creep-feed grinder. This is currently the mainstream grinder. Naturally, it is used for 300 mm wafers as well. Hereafter, our discussion assumes the grinder uses the in-feed method.

20.3 A GENERAL LOOK AT GRINDERS Figure 20.3 shows a typical grinder composed of several structures with various functions. 20.3.1 Grinding Section Figure 20.4 illustrates the workflow. Many in-feed grinders follow this pattern. There are three wafer chuck tables, which are placed on a rotary table. The rotating spindle descends. Figure 20.5 shows the grinding point. 20.3.2 Self-grinding

FIGURE 20.3 Grinder. (Courtesy of Disco Corporation.)

The wafer chuck table is made of porous ceramic. First, in a process called self-grinding, a cup wheel for ceramic grinding is mounted on a spindle and the chuck table is ground flat. This is to correct any error in the mounting of the chuck table. Then, the chuck table or spindle (depending on the mechanism) is oriented at a slight angle so that the chuck table is ground convex. This adjusts the wafer to the contours of the chuck table during grinding, through vacuum suction. A cup wheel like that shown in Fig. 20.6 comes in contact with only half the diameter of the wafer during grinding while the other half is never touched. This prevents the grind marks creating an irregular criss-crossing pattern, resulting in a uniform surface finish.

20.3.3 Grinding Wafer thickness is measured during grinding in real time using an in-process gauge like that shown in Fig. 20.7. In-process gauges may have either one or two probes. The two-probe type has recently become more common because it is more responsive to temperature changes and is more reliable. Figure 20.8 shows how to set up the feed rate. In-feed grinding feed rate on the first spindle (Z1-axis) is normally Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.3

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

20.3

Z1 spindle

Z2 spindle

Chuck table Rotary table

Centering

Cleaning

Cassette A

Cassette B

Operation panel FIGURE 20.4

Grinding work flow.

set in two or three levels, gradually decelerating. This is because layers of hard-to-grind materials such as oxides or nitrides are normally coated to the back of finished semiconductor wafers, so if grinding begins at the fastest feed rate, the cup wheel may cause “wafer burning,”a darkened discoloration of the wafer. Once rough grinding on the Z1-axis is done, the wafer moves to fine grinding on the second spindle (Z2-axis). By the time the wafer reaches the second spindle, the oxide, nitride, and

Spindle

Grinding wheel

Grinding point FIGURE 20.5

Chuck table

Grinding point.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.4

GRINDING, STRESS RELIEF, AND DICING FINAL MANUFACTURING

Cup wheel

20 µm

Si wafer Chuck table

FIGURE 20.6

Inclination of a chuck table.

Probe

Gauge

FIGURE 20.7

Height

20.4

In-process gauge.

Air cut

Original thickness of wafer

1st cut

2nd cut

Escape cut Sparkout Final wafer thickness Wafer (cross sectional) Time

FIGURE 20.8

In-feed grinding speed.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.5

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

20.5

similar layers will have already been removed. The key on the Z2-axis is the dwell or “spark out” just prior to finishing. Spark out refers to dwelling the cup wheel from the wafer after releasing the compression on the cup wheel, which elastically deforms during grinding. In other words, once we know when the processing will end (from the readings of the in-process gauge), the spindle descent stops and the chuck table rotates a few times in that state. Since the spindle is no longer descending, the compression of the cup wheel is gradually released. Just before it separates from the wafer, it becomes fully disengaged. If the cup wheel is not sparked out, the wafer will have striations like those shown in Fig. 20.9. These are caused by a sudden release of cup wheel compression just before separation from the wafer.

20.3.4 Cleaning Cleaning is very important for maintaining the quality of grinding. • Chuck table cleaning: Grinding produces a great deal of particles. These fine contaminants dry, and once dry, are difficult to remove from the chuck table. When the wafer is held by vacuum to the chuck table, these particles cause “dimples” (slight, localized indentations) and “crow’s feet” (localized cracks) that can lead to wafer breakage. • Wafer cleaning (after grinding): Figure 20.10 shows the ground surface of the wafer being brush cleaned after leaving the grinding chamber. Relatively large particles are removed at this stage. It also prevents contamination from the robot transport arm and makes spinner cleaning easier. • Spinner cleaning/drying: Finally, the ground wafer is cleaned with deionized water and spin dried before being returned to the wafer cassette.

20.3.5 Wafer Cassette The most commonly used type of cassette used in wafer transport is like that shown in Fig. 20.11. For transporting ground wafers to another factory (sometimes overseas), however, a “coin stack” cassette like that shown in Fig. 20.12 is often used. This type of cassette places dust-free separators between wafers, alternating wafers, and separators in the stack.

FIGURE 20.9

Striations.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.6

GRINDING, STRESS RELIEF, AND DICING 20.6

FINAL MANUFACTURING

FIGURE 20.10

Brush cleaning the wafer (under vacuum pad) after grinding.

20.3.6 Processing Capacity The grinding point is generally the bottleneck in the grinder throughput. For 8 in silicon wafers (original thickness 725 µm) being finished to about 200 µm thick, the processing capacity is about 28 wafers/h. When finished to less than 200 µm thick, the Z1-axis, which does the rough grinding, needs to increase the removal amount. This makes processing time dependent on the Z1-axis (Fig. 20.13).

20.3.7 Maintenance Grinder maintenance consists chiefly of the aforementioned self-grinding, replacing wheels, and dressing wheels. FIGURE 20.11

Wafer cassette.

• Self-grinding: As was described earlier, the chuck table is shaped on the machine to ensure that grinding produces a more precise level of flatness in the wafer. • Wheel exchange: When the grinding abrasive reaches the end of its service life, the wheel must be replaced. This task is sequential and interactive, which greatly reduces the difficulty for the operator. It can be performed using readily available tools and requires no special skills. • Dressing the wheel: Self-sharpening diamond abrasive wheels are normally used to eliminate the task of dressing, but the diamond abrasive can clog or “load” the wheel, impairing grinding. When this happens, the wheel is dressed.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

20:01

Page 20.7

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

FIGURE 20.12

Coin stack cassette.

Processing time (sec) Final wafer thickness (µm) Wafer size

Grinding axis Z1 Z2

50 121 91

100 112 91

200 96 91

f 8 inch

Z1 Z2

172 133

162 133

142 133

f 300 mm

Z1 Z2

216 159

203 159

178 159

f 6 inch

Z1: Rough grinding Z2: Fine grinding Grinding TACT time TACT time (wafers per hour)

Geng(SMH)_CH20.qxd

35 30 25 20 15 10 5 0

f f 6 inch f 8 inch f 300 mm

50

100 Final thickness (µm)

200

TACT = Total average cycle time FIGURE 20.13

Processing capacity of grinder.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

20.7

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.8

GRINDING, STRESS RELIEF, AND DICING 20.8

FINAL MANUFACTURING

20.3.8 Installation Environment • Footprint: A grinder for 300 mm wafers is about 1500 mm wide and 3500 mm deep. The total minimum space requirement is 3300 mm wide and 5200 mm deep, once the vacuum pump (ancillary equipment) and maintenance area are factored in. • Floor load bearing: A grinder for 300 mm wafers weighs 4000 kg, so floors require reinforcement. • Cleanroom: Grinders are usually set up in class 1000 to 10000 cleanrooms. • Temperature: To ensure precision, the room temperature should be 20 to 25°C with temperature fluctuations kept to ±1°C. 20.3.9 Data Transfer Data transfer specifications for grinders are stipulated in terms of bar codes that are placed on transport cassettes for each lot. The bar codes are read before grinding begins and sent to the host to get the recipe. GEM-compliant SECS-I/-II or HSMS are the standard options. (GEM stands for Generic Equipment Model, SECS stands for SEMI Equipment Communications Standard, SEMI stands for Semiconductor Equipment and Materials International, and HSMS stands for High Speed Message Services.)

20.4 DICING OVERVIEW Dicing is a process in which a wafer that has been thinned by grinding is cut into individual die. Although dicing may come before grinding (in DBG, which will be described later), for our purposes here we will be discussing the more traditional process of die separation. Figure 20.14 illustrates some of the basic terminology. 20.4.1 Blades Dicing is predicated on use of an ultrathin diamond blade. Dicing really could not be done until such blades were invented. In the early days of blade development, the blades were annular or “washer” types, with a ring-shaped blade clasped between flanges, as shown in Fig. 20.15. These were

Particles

Chipping

Kerf Street

FIGURE 20.14 Basic terms for dicing process (“particles” stands for “particle contaminates”).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.9

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

FIGURE 20.15

Washer blade.

FIGURE 20.16

20.9

Hub blade.

succeeded by hub blades, as shown in Fig. 20.16, which were unitized with an aluminum hub for ease of handling. These days, most users employ hub blades. The blades themselves are manufactured by electroplating an alloy composed primarily of nickel that contains fine diamond powder (the most commonly used grain size covers a range of 4 to 6 µm). Most blade thicknesses fall in the range of 25 to 35 µm. Since discrete devices have smaller die sizes than ICs, they increasingly use finer grain-size blades to boost die yields. Blades in the range of 15 to 20 µm are used in the general discrete market, while the thinnest blade used in mass production is about 12 µm. 20.4.2 Dicing Points A wafer is diced by placing the diamond blade on an air spindle, spinning it at high speed (30,000 to 60,000 rpm), and cutting through the wafer and about 20 µm into the dicing tape. Dicing is a wet process, with wheel coolant supplied to the blade throughout using a high-pressure nozzle as shown in Fig. 20.17. The wheel coolant serves both to remove the heat of dicing and to slough off contaminants. It is particularly important to remove contaminants on the bonding pad. This will have a direct

Coolant nozzle

Dicing point

FIGURE 20.17

Dicing point.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.10

GRINDING, STRESS RELIEF, AND DICING 20.10

FINAL MANUFACTURING

Half-cut dicing FIGURE 20.18

Breaking by roller

Expand the wafer

Scribe and break process.

impact on the junction strength in the wire bonding later. Three dicing methods—half-cut, tape cut, and semifull cut—are discussed as follows. • Half-cut: To give a bit of history, dicing initially involved holding a wafer directly to a chuck table using vacuum suction as shown in Fig. 20.18 and then scoring the wafer with grooves going two-thirds of the way through the wafer. Next, a special expanding tape was applied to the wafer, which expanded when the wafer passed under a roller and was broken up before going into die attachment. The risk of damage with this method is too high these days because wafers are much thinner and much largFIGURE 20.19 Wafer attached to dicing frame. er in diameter. Its use has become rare. • Tape cut: Tape cutting has become the most popular dicing method. As shown in Fig. 20.19, the wafer is attached with dicing tape to a stainless steel dicing frame and the wafer is cut all the way through, extending 20 to 30 µm into the tape. Most dicing tape starts with a base of polyvinyl chloride or polyolefin to which about 10 µm of acrylic adhesive is applied. Ultraviolet (UV) tape is sometimes used to make it easier to pick up the die in the die attach process when the die are larger. With UV tape, ultraviolet light hardens the adhesive, making the die separate from the tape more easily. Increasingly, this method is used for all thin die, regardless of size. • Semifull cut: This method cuts until only 10 to 20 µm is left of the wafer and then lets the die separate during the die attach process with an ejector needle. When both the blade (100 µm or more) and the die (300 µm or more) are relatively thicker, keeping the die from fully detaching provides better alignment during die attachment, and thus better throughput. This method is still sometimes used. 20.4.3 Dual Dicing Saws Dual dicing saws have two spindles, which opens up a wide range of dicing possibilities. Figure 20.20 illustrates some of the applications in which dual dicing saws are used. • Dual cut: With this system, the two spindles dice two lines simultaneously. Depending on the die size, throughput is up to 1.5 times higher than on a single-spindle dicer. • Step cut: Most dual dicing saws currently use a step-cut system. Increasing levels of integration on semiconductor wafers means that multiple aluminum, oxide, nitride, and copper interconnect

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.11

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

Dual cut

Step cut

20.11

Bevel cut

Interconnect layer Si wafer Tape FIGURE 20.20

Dual spindle application.

layers are laid down on the street (the part that is cut into). Dicing now commonly involves not just silicon but these other materials as well. As Fig. 20.21 shows, first, wiring layers on the surface are removed using a wide blade, and then the silicon substrate is diced with a narrower blade. Optimizing blades for each task helps with yield and throughput. Figure 20.22 shows a metal layer on the back of the wafer (backside metallization), as happens with discrete and bipolar ICs. In contrast with Fig. 20.21, here the silicon is cut first, and then the wafer is cut all the way through with a blade suited to the metallization on the backside of the wafer. • Bevel cut: Although basically similar to step cuts, in bevel cutting a V-shaped blade is used for the initial dicing to chamfer the upper edges of the die. This greatly reduces the incidence of chipping. 20.4.4 Selecting a Dicing Saw (Fig. 20.23) The first choice is whether to use a semiauto dicer or a full-auto dicer. • Semiauto dicers: Semiauto dicers are often used for small die (which many discretes are) that require a long time for dicing each wafer. For diodes, which have die dimensions as small as 0.30 mm, dicing often takes 20 min for a single wafer. If a 25-piece wafer cassette were used, as is the case with a full-auto dicer, the wafers would remain in the dicing stage for a very long time. In such cases, the cycle time is faster when the operator is managing between 7 and 10 small semiauto dicers because wafers spend less time in the dicing process. • Full-auto dicers: Facing dual dicers are currently the most commonly used type. They can be used for high-throughput dual cuts, high-quality step cuts, or products that use bevel cuts, and they can be programmed readily. They are used for almost all devices other than the small die devices discussed earlier, including CPUs, memory, and logic. • Half-cut dicers: DBG is being used more frequently for thin die (particularly 100 µm or under). DBG requires half-cut dicers. They provide greater precision in cut depth than previous half-cut dicers and can also be switched over to tape cut specification by exchanging certain parts of the machine.

First cut First cut FIGURE 20.21

Second cut

Second cut Step cut 1.

Metal layer FIGURE 20.22

Step cut 2.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.12

GRINDING, STRESS RELIEF, AND DICING 20.12

FINAL MANUFACTURING

Application comparison* Single spindle Device/category

Wafer thickness Single cut (µm)

Dual spindle dicing saw Dual cut

Bevel cut

Step cut

DBG Half cut

Common device (CPU, memory, general microcomputer)

Mobile products (mobile phone, PDA, etc.; memory, logic, etc.)

400−300 150−75 (100−50 for next generation)

Device for IC card (memory, logic, microcomputer, etc.)

150−80

Discrete device

200−120

(transistor, diode, LED, etc.)

(100−30 in the future)

= Better = Not as good = Not suitable * Currently used by customer, or is recommended by DISCO corporation FIGURE 20.23

How to select dicing saw.

20.5 DICING SAW OVERVIEW Dicing saws have several important structural features and functions. 20.5.1 Alignment Before a wafer can be diced, the cut position must be aligned. This process consists of automatically or manually detecting the cut position (the street), then adjusting the street to the blade position. The standard image processing method is the pattern recognition process, which is shown in Fig. 20.24. 20.5.2 Optional Functions Dicing saws have several important ancillary functions. • Blade breakage detector: The biggest problem encountered in dicing is blade damage. An undamageable blade is ideal, but it is impossible to completely prevent die in the area of 20 to 30 µm in size from flying off and damaging the blade due to insufficient tape adhesion. A completely broken blade may not be able to dice and will not damage the wafer. A partially damaged blade, however, may reduce cut quality or increase chipping. A sensor warns the operator to shut down the saw and change the blade when it is damaged. A blade breakage detector is shown in Fig. 20.25. It is mounted as a unit with the nozzle cover. • Noncontact setup: This function is surprisingly important. Knowing where the blade and chuck table are relative to one another is key information for controlling the dicing saw. Dicing saws have to control the depth of the cut down to a few microns, so due to blade wear, they repeatedly

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.13

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

20.13

Street

Alignment target

Kerf Hair line

• Recognize the target that has been memorized by the machine beforehand • From where the target pattern is positioned, hair line and cutting street are calculated • Machine recognizes the distance between the target pattern and cutting street FIGURE 20.24

Rotate

Cut direction Before After Difference adjustment adjustment Axis alignment

Alignment process.

go through an operation called “setup” to ascertain the blade peripheral edge reference accurately to the top surface of the chuck table. This function lowers the conductive blade slowly toward the chuck table. A slight current flows at the instant the blade and chuck table come into contact. That point is considered the zero point. If this process were repeated frequently, the blade would cut slightly into the chuck table each time, damaging itself. Instead, this process is only run when a blade is exchanged for the initial referencing. Thereafter, an optical position detection unit (noncontact setup, or NCS) installed off the chuck table is employed to control the blade tip position. • Kerf inspection: Kerf is the actual amount of material, usually the blade width, which is removed from the street during the dicing process. Kerf inspection checks the dicing quality while dicing is

FIGURE 20.25

Blade breakage detector.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.14

GRINDING, STRESS RELIEF, AND DICING 20.14

FINAL MANUFACTURING

underway. The Kerf position changes as the spindle extends or contracts under the influences of the wheel coolant, spindle coolant, and room temperature. Changes in the blade’s cutting ability can suddenly produce major chipping. The dicing saw can be programmed in the frequency that stops during the dicing process to look at the kerf width on the machine, chipping size, and misalignments of the kerf position using image processing, and either corrects it or sounds an alarm. • CO2 bubbler: Deionizied water is used as the wheel coolant for dicing silicon. Although its resistivity is only 17 to 18 MΩ-cm, if no other measures are taken, friction with the wafer will produce static electricity, possibly causing device damage. To prevent this, CO2 can be dissolved into the deionized water, making a weak carbonic acid, to lower its resistance to about 1 MΩ-cm. Although more expensive than CO2, deionized water is sometimes diluted with a cutting lubricant. This lowers the surface tension of the wheel coolant and removes particle contamination, lengthening the blade service life. • Spinner cleaning (spin rinser dryer, or SRD): This unit cleans and dries the wafer after dicing. Cleaning effectiveness has recently greatly improved with the adoption of two-stream cleaning nozzles. • UV irradiation unit: When UV tape is used in dicing, this unit irradiates diced wafers with UV to reduce tape adhesion just before they go into the frame cassette, so they can go right to die attachment after dicing ends. 20.5.3 Processing Capacity (Fig. 20.26) Dicing saw processing capacity varies tremendously with differences in the diameter of the wafers diced, dicing speed, chip size, and the cut method used by the dual dicing saw. Figure 20.15 depicts an example in which the per-hour capacity is calculated for 8-in wafers. The biggest factors affecting processing capacity are alignment time and dicing time. 20.5.4 Installation Environment • Footprint: The DFD6361 dual dicing saw for 300 mm wafers is about 1200 mm wide and 1550 mm deep, so it requires 1.8 m2. The total minimum space requirement including the maintenance space is about 2420 mm wide and 1850 mm deep.

Example of dicing saw processing ability per hour (8-in round wafer) 60

50 mm/s single

50

50 mm/s step

No. of wafer

50 mm/s dual

40

100 mm/s single 100 mm/s step

30

100 mm/s dual

20

150 mm/s single

10 20 × 20

18 × 18

16 × 16

14 × 14

12 × 12

10 × 10

8×8

6×6

4×4

150 mm/s dual

2×2

0

150 mm/s step

Alignment time; 30 s clean and dry time; 60 s cut mode; A mode

Die size (mm) FIGURE 20.26

Processing capacity of dicing saw.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.15

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

20.15

• Cleanroom: Dicing saws are usually set up in class 1000 to 10,000 cleanrooms. • Temperature: The room temperature should be 20 to 25°C with temperature fluctuations kept to ±1°C.

20.6 FABRICATION EQUIPMENT REQUIREMENTS Fabrication equipment must meet other requirements besides improving processing quality. 20.6.1 Ease of Operation Most fabrication equipment is operated through liquid crystal display (LCD) touch screens. These generally employ a user-friendly, interactive graphical user interfaces (GUIs) that use graphics and images rather than just text, making them easier to operate. 20.6.2 Safety Inherently hazardous areas such as dicing, grinding, transport, and other moving parts are behind panels with safety interlock to minimize hazards. These safe designs earn the machine structure the CE mark* (representing compliance with the Electronic Commerce regulations, “EC machinery directives”) and are compliant with EMC directives and SEMI’s S2 requirements (Environmental, Health, and Safety Guidelines for Semiconductor Manufacturing Equipment).

20.7 THINNING This chapter has so far covered basic dicing and grinding. From here on, we explore the process of thinning, which employs many recent innovations and numerous constituent technologies that did not exist even a few years ago. A slimmer size is a selling point for many end products such as cell phones and notebook computers. This has meant ever thinner semiconductor packages as well. One way to increase density without an increase in surface area is stacked packages that place die on top of each other. In the same package thickness, three to five die can be stacked if they are made thinner. Some die are even stacked on both sides with interposers. Recent innovations have seen up to nine die placed in a package 1 mm thick. How far can this go? As things stand now, it looks as though the thinnest stack packages might reach 50 µm, IC cards the same 50 µm, and power devices around 20 µm. One special design foresees building an silicon-on-insulator (SOI) device and then removing all the silicon wafer substrate to produce an ultrathin 2 to 3 µm film. 20.7.1 The Processes Leading to a Die We have discussed dicing and grinding in isolation. Now we will consider them together with the peripheral processes that precede and follow them. There are, broadly speaking, five approaches used, depending on the finished thickness. 1. Conventional processes (down to 200 µm in thickness) End of wafer fabrication → Tape mounting → Grinding → Tape removal → Wafer test → Frame mounting → Dicing → Next process (die attach) *

CE mark: “CE” is the abbreviation of French phrase “conformité Européenes,” which means “European conformity” in English.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.16

GRINDING, STRESS RELIEF, AND DICING 20.16

FINAL MANUFACTURING

2. Thinning (200 to 50 µm in thickness) End of wafer fabrication → Wafer test → Tape mounting → Grinding → Stress relief (etch, polish) → DAF mounting → Frame mounting → Dicing → Next process (die attach) 3. DBG (no DAF, about 50 µm in thickness) End of wafer fabrication → Wafer test → Half-cut dicing → Tape mounting → Grinding → Reverse transfer → Next process (die attach) 4. DBG for Smart and IC cards (no DAF; about 50 µm in thickness) End of wafer fabrication → Wafer test → Half-cut dicing → Tape mounting → Grinding → Plasma stress relief → Reverse transfer → Next process (die attach) 5. Ultrathin power devices End of wafer fabrication (circuit side) → Tape mounting → Grinding → Stress relief (spin etcher) → Backside metallization process → Wafer test → Frame mounting → Dicing → Next process (die attach) 20.7.2 Stress Relief One new technology developed for making wafers into thin die is stress relief. This process uses chemical and mechanical means to eliminate warpage caused by grinding. There are four main types of stress relief (Fig. 20.27). 1. Spin etching: The silicon is etched in a mixture of boric and nitric acids, as shown in Fig. 20.28. The wafer is spun and sprayed with the acid mixture from above to etch it to uniform thickness. The etching rate is about 0.5 to 2.0 µm/s. Although this is both a wide and high-speed range, most etching is done at 0.5 µm/s and etches about 20 µm in total. This has been used for quite some time for IC cards. This method is also well suited to ultrathin power devices that have a lot of removal after grinding, where it results in good electrical characteristics. 2. Chemical mechanical polishing (CMP): CMP polishes about 2 to 3 µm off the ground surface using an alkali slurry and polishing pad. The maximum polishing rate is about 1 µm/min, so this is slower than spin etching. It has come to be more widely used, however, because it produces a

Device

Common device (CPU, microcomputer)

Wafer • 400−380 thickness (µm)

Required features

• Low cost • High yield

Back-grinding process only

Recommended stress relief

Grinding wheel

Wafer

FIGURE 20.27

Device for mobile products (memory, logics, etc.)

Device for IC card (memory, logic, microcomputer, etc.)

• 150−75

• 150−80

• Low cost • High yield • Thin die

• • • •

Dry polishing process (CMP process as well)

• 200−120

• Low cost Low cost • High yield High yield • Thin die Thin die • Improved device Greater die strength properties DBG + plasma etching process

Dry polishing wheel

Wafer

Discrete device (transistor, diode, LED, etc.)

Fluorine gas

Wafer

Plasma

Spin etching process Exhaust gas system HF + HNO3

Wafer

Stress relief selection.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.17

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

20.17

smoother surface, and because dedicated assembly plants that do not process wafers are not set up to handle the NOx gas and liquid waste that spin etching generates. The development of three-spindle grinders (described later in this chapter) has been another factor in its spread. 3. Dry polishing: Dry polishing is as effective as CMP. A metal oxide that reacts with silicon in its solid state is impregnated into a bonded material as a polishing agent and used as a polishing pad held in place by FIGURE 20.28 Spin etcher. resin. The maximum polishing rate is about 1 µm/min, and like CMP, it polishes about 2 to 3 µm off the grinding surface. Since, unlike CMP, it does not use an alkali slurry, it requires no disposal of waste liquid. After polishing, all it needs is a cleaning with deionized water. This process has the lowest total cost. 4. Plasma etching: This method currently finds use in combination with DBG. One reason is the difficulty in using other stress relief methods with DBG. In DBG, die separation is achieved during the grinding (thinning) process. This means the die are attached to the surface protection tape. Plasma etching done in this state thus etches both the back and the sides of the die, increasing die strength and flexibility If CMP or dry polishing were used after DBG, the polishing agent would get stuck to the sides of the die and to the tape exposed between the chips, making cleaning very difficult. The difficulty in spin etching is controlling the flow of the etchant, which varies with each die size. It also readily makes its way between the die and the tape, leading to considerable die damage. This makes plasma etching the only process that can currently be used with DBG. 20.7.3 The Importance of Tape A surface protection tape and DAF are the most important tools in thinning wafers. The following discussion makes reference to examples 1 and 2 in Sec. 20.7.1. 1. Conventional process (down to 200 µm in thickness) End of wafer fabrication → Tape mounting → Grinding → Tape removal → Wafer test → Frame mounting → Dicing → Next process (die attach) → The only tape used here is the surface protection tape to protect the circuit surface for back grinding and the dicing tape for dicing. 2. Thinning (200 to 50 µm in thickness) End of wafer fabrication → Wafer test → Tape mounting → Grinding → Stress relief → DAF mounting → Frame mounting → Dicing → Next process (die attach) → In addition to the tape used in the conventional processes, here DAF is also used. • How surface protection tape disperses stress: The first thing we need to determine is how thin we can grind based on the performance of the surface protection tape alone. Figure 20.29 shows an example of grinding to a thickness of 20 µm. The surface conditions of the device wafer used—unevenness of the circuit surface, presence of bonding bumps, bump height, and presence of reject ink marks from the prober—will vary greatly. The surface protection tape must be able to absorb such unevenness and disperse the force generated during grinding to protect the wafer from breaking. • Thermal resistance: When a DAF is also used, it may require thermal resistance that has not been needed in the past. If paste were used as it has been in the past for die attaching of thin die, the paste would climb up onto the sides of the thin die, as shown in Fig. 20.30. For this reason, DAF (which is double-sided tape) is stuck to the back of the die to attach the die. This allows the die to be attached without the paste going up onto the die sides or spreading out laterally. Die that are first attached to a substrate, however, must be able to cover irregularities Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.18

GRINDING, STRESS RELIEF, AND DICING 20.18

FINAL MANUFACTURING

FIGURE 20.29

25 µm thick wafer.

on the interposer surface, so they use a relatively flexible thermoplastic resin tape. When heated to 180°C, this tape pressure-bonds to the wafer. This is not a problem if the DAF can be pressure-bonded after removing the surface protection tape, but such handling can lead to damage in wafers that are already very thin. The DAF thus needs to be pressure-bonded while the surface protection tape is in place. • One side of the wafer is always tape protected, supported, and held in place by vacuum: To give more details, the process is as follows. • Attach heat-resistant surface protection tape → Grinding → Stress relief → DAF pressurebonding (with surface protection tape still attached) → Attach dicing tape to dicing frame (with surface protection tape and DAF attached) → Remove surface protection tape → Dicing → Next process (die attachment) → To prevent damage to the thinned wafer, the wafer backside must supported by tape before going into dicing. Ring frame

Si wafer Adhesive layer Release film

130−180°C Adhesive layer Tape mounting

Ring frame Adhesive layer

No heating Tape mounting

UV irradiation

Dicing tape Dicing

Picking Up

Substrate

Dicing

Picking up

Substrate Die mount (heating-200°C)

FIGURE 20.30

Base film

Si wafer

Die mount (heating −100−150°C)

DAF process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.19

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

20.19

• Stress relief requirements: As we mentioned, there are four type of stress relief currently in use. Each makes its own demands on the tape (here, surface protection tape). • Spin etching: → Chemical and temperature resistance. Most spin etching conditions should not result in acid creeping around the tape, which is opposite the etched side, but just in case, the tape should be acid resistant. • CMP: → Caution must be exercised with some types of devices, particularly memory devices. Memory devices often have circuits formed out to the outermost edge of the wafer. Streets and active areas are generally at different levels, with the streets generally creating a channel. In memory devices, the lowest streets will extend to the periphery of the wafer. If the tape does not neatly fill in this channel, the alkali slurry may seep from the periphery into the interior of the device, causing damage. CMP thus requires surface protection tape with a high ability to cover two different modalities of unevenness—active area variations and the difference in levels with streets. • Dry polishing: → Thermal resistance is desirable for dry polishing, but recent advances in chuck table cooling technology have enabled the use of ordinary surface protection tape. • Plasma etching: → Plasma etching requires tape that uses an adhesive with good thermal conductivity rather than good thermal resistance. 20.7.4 Dicing DAF DAF will become a necessary structural material in the future for thin device packages; it should also make the overall process easier. Dicing DAF unites dicing tape and DAF and can be attached at room temperature, so it does not require a special device for DAF attachment. Both dicing tape and the DAF are designed to be removable, so that die can be readily picked up in the die attach process after dicing. Several firms currently make such products, but unfortunately none meet the requirement of attaching the die first to an interposer. In other words, they are deficient in terms of filling in irregularities on the interposer surface but are good enough to be used for the second stage and beyond of die attach (i.e., die on die, or attaching one die to the next). They are likely to develop further in the future. 20.7.5 DAF Dicing Process Simultaneous dicing of a thinned wafer and a DAF is a tricky process, regardless of whether the DAF is a thermoplastic or dicing type. When the wafer has been thinned down to about 50 µm, the DAF layer under the wafer is 25 to 40 µm and the dicing tape adhesive layer under that is to be cut into to a depth of 20 µm, the silicon and the resin regions are about equal in thickness. Resistance to dicing becomes quite high, making it easy for the blade to clog. When a burr is produced on the corner of the DAF as shown in Fig. 20.31, it is easy for defects to crop up when the die are stacked. Special processing methods that prevent burrs by slowing down dicing are currently used, despite the lower throughput (Fig. 20.32). DAF dicing will be a goal in the development of DAF materials in the future.

FIGURE 20.31

Burr of DAF tape.

FIGURE 20.32

DAF tape without burr.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.20

GRINDING, STRESS RELIEF, AND DICING 20.20

FINAL MANUFACTURING

20.8 ALL IN ONE SYSTEM A few manufacturers have recently developed all-in-one in-line systems for stacked packages, utilizing the latest technology. 20.8.1 Integration of Grinder and Stress Relief The latest equipment has integrated rough grinding, finish grinding, and final polishing. Wafers moving from rough to finish grinding stay mounted in the chuck table. This specification significantly decreases the risk of wafer damage during transfer to the next step (stress relief, dry polish). 20.8.2 Mounter/Remover Robotic transfer brings a wafer that has been thinned and undergone stress relief in the grinder to a newly developed mounter/remover. This equipment is an all-in-one mounter/remover that can do all the processes considered necessary at this stage, including UV irradiation of the surface protection tape, mounting of the DAF (thermal pressure-bonding specification), mounting the dicing frame, removing the surface protection tape, and irradiating the dicing tape and or DAF with optional UV irradiation. It can also, of course, skip any unnecessary steps and is compatible with DBG. A grinder/stress relief/mounter/remover in-line system thus encompasses all required functions at this time. As materials are developed (such as an improved dicing DAF), it is designed with enough flexibility to be able to add extra functions or remove those that are no longer needed.

20.9 FUTURE TECHNOLOGY TRENDS To conclude this chapter, three possible breakthroughs that stand out in the area of wafer thinning should be considered. 20.9.1 Wafer Support Systems Thinned wafers both tend to sag under their own weight as shown in Fig. 20.33, and exhibit minor complex torsion deformation from stress on the active side. The wafer support system (WSS) uses a polyethylene terephthalate (PET) film as the basis for its surface protection tape and is able to correct

FIGURE 20.33

Thin wafer.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.21

GRINDING, STRESS RELIEF, AND DICING GRINDING, STRESS RELIEF, AND DICING

FIGURE 20.34

20.21

PET film WSS.

sagging and bending as the wafer is thinned, as shown in Fig. 20.34. This allows a wafer to be moved from the grinder to the next process using a tool such as a double slot cassette (DSC), allowing the production of thinned wafers on systems that are not in-line. Although the WSS has not achieved thermal resistance at this time, a PET film WSS should prove to be fully up to production as soon as a dicing DAF that can be attached at room temperature is developed. 20.9.2 Hard-Wafer Support Systems Two systems have been proposed for hard-wafer support systems (H-WSS): double-sided tape that uses a special removal material on a glass plate and spin coating resins in two stages—one for removal and one for wafer adhesion. The system is able to prevent almost 100 percent of wafer damage. The spincoated type excels at thermal resistance and allows thinned discrete devices to go through the process of forming films on the back of the wafer and be transferred to the dicing tape with the H-WSS still attached. While the performance is virtually perfect, the materials are expensive. It is not yet possible to use them in thinning for stacked packaged used in cell phones. Double-sided tape is also still expensive. Both systems require dedicated machines, so progress will have to be made before they find widespread use. 20.9.3 Edge Trimming The periphery of the wafer is always chamfered. As the wafer is thinned, it takes a knife-edge shape as shown in Fig. 20.35. In this state, it is extremely susceptible to damage. A knife-edge can be prevented

Grinding wheel

Substrate

FIGURE 20.35

Knife-edge-shaped wafer edge.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH20.qxd

04/04/2005

20:01

Page 20.22

GRINDING, STRESS RELIEF, AND DICING 20.22

FINAL MANUFACTURING

Blade

Final thickness + a

Wafer

FIGURE 20.36

Edge trimming.

by trimming the outer periphery as shown in Fig. 20.36 and turning it over before thinning the wafer. This dramatically reduces the incidence of damage after the wafer is thinned. It thus becomes safe to move wafers even when thinned wafers have to go overseas in coin stack cassettes to package assembly plants. This reduces risk during processing in in-line systems as well. The problem is that dedicated processing devices are currently required. WSS, H-WSS, and edge trimming are thus considered landmark technologies in wafer thinning. The drawbacks are that they are expensive, since they are not yet widely used, and they require additional capital investment. These technologies may change with progress in other package materials. With the modern prominence of thin products, dicing and grinding are already ceasing to be separate processes.

FURTHER READING Tummala, R., Fundamentals of Microsystems Packaging, 1st ed., McGraw-Hill, New York, 2001. Van Zant, P., Microchip Fabrication, 5th ed., McGraw-Hill, New York, 2004. Wolf, S., and R. N. Tauber, Silicon Processing for the VLSI Era Volume 1: Process Technology, 2d ed., Lattice Press, Sunset Beach, CA, 2000.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 21

PACKAGING Dietrich Tönnies Suss MicroTec Garching, Germany

Michael Töpper Fraunhofer IZM Berlin, Germany

21.1 INTRODUCTION Electronic packaging and assembly are needed to link the small dimensions of the integrated circuit (IC) to an interconnecting substrate—usually the printed circuit board (PCB). The PCB combines a multitude of ICs and passive components to build a microelectronic system. New device technologies and applications with their ever-increasing performance and functionality are driving the requirements and innovation for assembly and packaging. The technology boundaries between semiconductor technology, packaging, and system design are becoming blurred. As a result, chip, package, and system designers will have to work closer together than ever before in order to drive the performance for future microelectronic systems. Flip chip in package (FCIP), flip chip on board (FCOB), wafer level packaging (WLP), and system in package (SiP) are among those new packaging technologies that will enable the industry to meet future system requirements. Generally, economic and technical considerations are driving packaging toward adopting wafer level processes such as wafer bumping and rerouting. The focus of this chapter will therefore be on these new technologies, keeping the description of the more conventional die level packaging deliberately short. Standard textbooks on electronic packaging are cited at the end of this chapter for more details on conventional package types. 21.1.1 Basics of Electronic Packaging and Assembly The Role of Electronic Packaging. The packaging technology determines the size, weight, ease of use, durability, reliability, performance, and cost of electronic products. The package has to protect the IC, support the IC performance (such as operating speed, power, and signal integrity), handle the thermal management, and has to compensate for stress between the IC and PCB by providing a mechanically and electrically reliable interconnect. For the assembly of complex microelectronic systems, it is important that individual ICs can be tested and burned-in. The majority of ICs are packaged in so-called single chip packages (SCPs) where the IC is electrically, mechanically, and most often thermally linked to a carrier (lead frame, interposer) that spreads the IC contacts to the outside world such that they can be assembled to the PCB. Additional plastic materials often protect the IC from mechanical damage. The increasing speed of modern IC generations calls for improved electrical performance and heat dissipation of packaging. The growing semiconductor Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

21.1

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.2

PACKAGING 21.2

FINAL MANUFACTURING

content in electronic equipment as well as the growing demand for mobile equipment both require a reduction of the package form factor. A further reduction in size and weight together with a performance increase can be reached by multichip packaging. An early, but commercially not very successful, adoption of this idea was the multichip module (MCM). In an MCM, bare dice are assembled on a substrate, and the entire assembly is packaged. Today, the packaging industry focuses on the SiP technology as an alternative multichip packaging approach. In SiP ICs, active and passive components are combined and packaged as a whole. The result is a complex microelectronic system with high functionality and better performance and smaller form factor than conventionally assembled systems. The challenge, on the other hand, is to set up a manufacturing process that provides SiP at comparable or even lower prices. Interconnect Technologies. Bare die is assembled to a substrate or a carrier/lead frame either with its face up or its face down. Today, the majority of packages require a face-up assembly to lead frames or organic or ceramic interposers that are then assembled to the PCB. Flip-chip bonding, on the other hand, is by definition a face-down assembly technique and can be used to connect the die to a lead frame or interposer or directly to the PCB. Direct bonding of a die to a PCB (flip chip, TAB, or wire bonding) is called chip on board (COB) or direct chip attach (DCA). The metal-metal interconnect can be made by soldering, welding, or gluing. Three major technologies (Fig. 21.1) have been used over the past 40 years—wire bonding (WB), flip chip (FC), and tape automated bonding (TAB). Wire bonding is the most common bonding technique. The chip is glued or soldered face up onto a substrate or a carrier and the interconnection is made by thin gold or aluminum wires using ultrasonic or thermosonic techniques. Wire bonding is capable of fine-pitch bonding and is in principle applicable to all peripheral pad pitches required by the International Technology Roadmap for Semiconductors (ITRS) roadmap (see the section, “The ITRS Packaging Technology Roadmap,” and Table 21.4). Deformation forces are spread over the whole bottom side of the die and hardly affect the active chip area. A high degree of automation with image recognition systems has reduced the bonding time to less than one-tenth of a second per wire. Although a sequential process where each bond is made after the other, wire bonding is cost competitive to flip chip and TAB where all the interconnects are made at once. A thermosonic Au wire ball bond between a lead frame and the chip pads is the interconnection technology for the most popular IC package—the molded plastic package. The flip-chip assembly is a face-down assembly technique originally developed by IBM and known as C4 (controlled collapse chip connection). Flip chip provides excellent performance and represents a cost-effective interconnect technique for dice with high input/output (I/O) counts. An overview of the different kinds of FC assemblies is given in Fig. 21.2.1 A major requirement for most of the flip-chip interconnections is modified pads on the IC. The so-called under bump metallization (UBM) or ball limiting metallurgy (BLM) are the basis for a lowohmic electrical, mechanical, and thermal contact between a chip and a substrate. Two solutions were developed by IBM to prevent the collapse of the interconnect during soldering—embedding of a nonmelting Cu ball or a nonwettable surface around the pads of the IC and the substrate. Depending on the interconnect pitch, a flip-chip bonder or a highly accurate surface mount technology (SMT) assembly unit is used. A camera system or a split-field optic is used for the alignment of the chip to the substrate. The major advantage of the flip-chip assembly is the self-alignment function. Chips can be misregistered by as much as 50 percent off the pad center, and the surface tension of the molten solder will align the pads of the chip to the substrate metallization. The disadvantage of flipchip assembled ICs is that the bumps are the only mechanical links between the chip and the substrate. As a consequence the stress caused by the coefficient of thermal expansion (CTE) mismatch of the semiconductor die and the substrate acts only on the bump interconnects. Therefore, underfillers

FIGURE 21.1

Wire bonding, flip chip, and TAB are the main interconnection technologies.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.3

PACKAGING PACKAGING

21.3

Flip chip

Welding

TC TC thermothermocompression sonic

Au, In

Au studs

Adhesive joining

ICA isotrop conductive adhesive

Ni/Au, Au +ICA

Soldering

NCA ACA nonanisotrop conductive conductive adhesive adhesive

Ni/Au, Au +ACA

Thermode Reflow soldering soldering Pull Compression

Au studs

PbSn

PbSn, SnAg, AuSn

Au+Cu/Sn

FIGURE 21.2

Overview of the different kinds of FC interconnection technologies.1

(epoxy resins with filler particles) have to be filled in between the flip chip and the substrate, which translates into extra costs in the assembly process. TAB uses polymeric tape with copper beam leads on a strip for the interconnect. These copper beams with an electroplated Sn or NiAu layer are aligned to Au-bumped dice (see the section, “Wafer Bumping Overview”) and all interconnects are made in one step using thermocompression bonding (gang bonding). TAB is a very common assembly technique for LCD drivers where a minimum pitch of 45 to 50 µm is currently in leading-edge production. The minimum achievable pitch of TAB is limited by the mechanical strength of the Cu leads and is considered to be around 30 to 35 µm. Another limiting factor of TAB is the cost of the high-density beams. Assembly. Soldering is the standard interconnect technique for assembling packaged semiconductor ICs to a PCB. Soldering allows easy repair of defective boards by desoldering defective components and replacing them with functional ones. The layout of the PCB depends heavily on the interconnection technology as described in Table 21.1.2 Through-hole technology (THT) was common until the late 1980s. With THT, the PCB consists of a board with mechanically drilled and copper plated holes. The packaged IC has long connector pins along two sides of its periphery. The IC is assembled to the PCB by putting the pins through the holes TABLE 21.1

Overview of PCB Layout Rules

Technology Through hole Standard SMT Standard fine pitch SMT High-end fine pitch SMT Extreme fine pitch SMT Flip chip

Interconnection pitch [mm] 2.54 1.27 0.5–0.635 0.4 0.3 0.2

linewidth and spacing [µm] 300 150 60–75 50 35 25

Via hole diameter [µm] 600 300 130–150 100 80 50

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.4

PACKAGING 21.4

FINAL MANUFACTURING

PCB Through-hole package FIGURE 21.3

Surface mount package Ball grid array (area array)

Through-hole versus surface mount technology.

of the PCB and soldering them at the bottom side of the board. Throughout the 1990s the higher complexity and miniaturization of electronic products had nearly totally replaced THT by SMT due to the higher routing capacity of SMT boards, higher assembly throughput, and the possibility of double-side assembly. The first step for the assembly of an electronic system using SMT is to print solder onto the PCB for the surface mount devices (SMDs). With an automatic pick-and-place machine, the SMDs are placed into position on the substrate. Reflow in a convection and IR-heating oven completes the assembly process. Unlike THT devices, high pin count SMDs often have an area array pin layout (Fig. 21.3). This allows designing packages with small form factors. PCB roadmaps describe minimum linewidth and spacing and are driven by increasing IC pin counts and miniaturization requirements. Table 21.2 summarizes the ITRS roadmap for ball grid array (BGA) (see Sec. 21.2.1) and chip scale package (CSP) (see Sec. 21.2.2) boards. For the flip-chip assembly even higher density substrates are needed. Depending on the application, the geometric structures on the FC board (that means the patterns) can vary strongly (low cost versus high-density boards for high frequency), and it is difficult to predict the routing density trends. In addition, new materials will be needed for the above-GHz range. In the future lowcost PCBs for high-density applications will be a major bottleneck. Possible solutions are few-chip-BGAs/SiPs where high-density wiring is only needed for some parts of the system. With this kind of modular system, standard boards can be used as the interconnection substrate of SiPs in order to save cost. Green manufacturing has an important impact on chip packaging and assembly. As an example, the European Union has issued the “Restriction of Hazardous Substances in Electrical and Electronic Equipment” (RoHS) directive in 2003. This directive bans the use of lead, mercury, cadmium, hexavalent chromium, and polybrominated diphenyl ether from new electrical and electronic equipment starting from July 1, 2006. Other countries have similar programs. In particular the ban of lead has important consequences for packaging and assembly because of the common use of PbSn solders. Figure 21.4 shows other areas of interest for green manufacturing in chip assembly, such as the availability of halogen-free substrates and underfills. Some soldering processes, in particular high-lead flip chip for microprocessors, have received exemptions from the ban until 2010. For system assembly several lead-free solders are in use already. SnAgCu, SnCu, SnAgBiIn, and SnZnBi are a few examples. All these lead-free solders are rich in tin and most of them have a higher melting point than eutectic PbSn. Therefore, packages are exposed to higher temperatures during soldering, which has consequences for the selection of packaging materials and the reflow process.

TABLE 21.2 Year 2003 2004 2005 2009 2015

ITRS Roadmap for BGA and CSP Boards

Ball size [µm] 400 400 300 80 60

Pad size [µm] 160 160 120 80 60

Lines [µm]

Space [µm]

48 48 36 24 18

48 48 36 24 18

Number of rows accessed 3 3 3 3 3

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.5

PACKAGING PACKAGING

Halogen-free underfills withstand 260°C

Lead-free solder bump

Lead-free per-solder

21.5

Lead-free finish

Die

Halogen-free substrates withstand 260°C FIGURE 21.4

Lead-free per-solder

Lead-free solder ball

Green product legislation impact on packaging materials.3

Lead-free solders don’t have as good a wetting behavior as PbSn and show different electromigration characteristics than PbSn. All this creates risks in the transition from lead to lead-free electronics. 21.1.2 Packaging Forecast The ITRS Packaging Technology Roadmap. As the complexity of devices and systems is rapidly increasing, new packaging technologies play a major role for the electronic industry. Packaging roadmaps are caught between the IC roadmaps and the trends in the PCB industry. In the last few years through-hole mounting packages (such as the dual in-line package (DIP) and pin-grid array package (PGA)) were displaced by surface mount packages (such as the TSOP and PQFP, or plastic quad flat package). The steady progress in the IC technology increases the density, speed, power, and number of I/Os. For example, gate density on a chip for high-end applications is increasing by about 75 percent per year resulting in the growth of the IC chip I/O terminals by 40 percent per year. Along with the national roadmaps published by organizations such as the Semiconductor Industry Association (SIA) in the United States and the Electronic Industries Association of Japan (EIAJ), many IC companies have their own roadmaps describing the evolution of the physical parameters of ICs and electronic packaging. These roadmaps are top-down approaches anticipating changes in the IC technology guiding as well the requirements for packaging. Several reasons could lead to significant changes in such roadmaps, for example, completely new IC technologies, and adoption of new packages or new products changing the electronic marketplace. The following statements are based on the ITRS, 2003 edition: Electronic products are grouped together by standardized categories. These groups are: • Low-cost/hand-held: <$500—consumer products, wireless products, disk drives, and displays • Cost performance: <$3,000—notebooks, desktop personal computers, telecommunications • High performance: >$3,000—high-end workstations, servers, avionics, supercomputers, most demanding requirements • Harsh: under-the-hood and other hostile environments The package pin count forecast for the different electronic applications as proposed by the ITRS is given in Table 21.3. Since 2003, the packaging requirements have been grouped by only four product categories. These application areas cover the majority of the product development of the semiconductor industry. The technology addressed in the roadmap provides at least 80 percent of the revenue in each application area. The low-cost and hand-held segments have been combined into a single category

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.6

PACKAGING 21.6

FINAL MANUFACTURING

TABLE 21.3

ITRS Forecast of Pin Counts for Different Applications

Year/application

Low-cost/hand-held

2005 2010 2015 2018

134–550 208–777 325–1213 421–1576

Cost performance

High performance

Harsh

550–1760 780–2782 1216–4339 1581–5642

3400 4009 6402 8450

550 642 933 1235

based on the realization that there will not be a significant difference in the cost or major performance requirements in these segments any longer. The interconnection pitch becomes smaller in response to the increasing number of I/Os (Table 21.4). The wire bond pitch includes only in-line configurations. Staggered pads will relax these constraints. In addition, larger pitches could be required for extremely high-current applications. Conductive adhesive flip chip is not addressed separately but may have smaller pitches for small die applications, provided high-density substrates with competitive cost are available. Flip chip will require fan-out routing on the package substrate. Signal lines will be on the outer rows of area array to minimize package inductance. Inner balls will be used for voltage and ground to minimize voltage drop across the IC. The design will benefit from smaller bumps and reduced pitch. But higher substrate costs, substrate warpages, assembly issues, tests, and electromigration have to be considered. An example of a 50-µm pitch (area array) FC assembly is given in Fig. 21.5. The ITRS identifies the following topics as the difficult future challenges: • • • • • • • • • •

Improved organic substrates Improved underfillers for flip chip on organic substrates Coordinated design tools and simulators to address chip, package, and substrate codesign Impact of Cu/low k on packaging High current density packages Package cost does not follow the die cost reduction curve Small die with high pad count and/or high power density High frequency in general System-level design capability to integrated chips, passives, and substrates New device types (organic, nanostructures, biological) that require new packaging technologies

Although the assembly and packaging cost is expected to decrease over time on a cost-per-pin basis, the chip and package pin count is increasing more rapidly than the cost-per-pin is decreasing. This high increase in the pin count raises not only the absolute cost of assembly and packaging on a

TABLE 21.4

Forecast of Interconnect Pitch (on the Die) for Different Interconnect Technologies

Year/ interconnect

Wire bond ball [µm]

Wire bond wedge [µm]

TAB [µm]

Flip-chip area array [µm]

Flip-chip peripheral [µm]

2003 2004 2005 2010 2015

40 35 25 20 20

30 25 20 20 20

35 35 30 20 15

150 150 130 100 80

60 60 40 20 15

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.7

PACKAGING PACKAGING

21.7

FIGURE 21.5 A 50-µm FC pitch (area array).4 For this sensor application a silicon-to-silicon approach was used. The MCM consists of 16 chips (7.4 mm × 11 mm) on a silicon sensor (18.6 mm × 63 mm). No PCBs are available up to now for such fine-pitch FC applications.

per-chip basis, but also the substrate and system-level packaging cost. The pin count will continue to increase in all segments while the die size is expected to remain constant. Forecast by Package Type. Figure 21.6 shows the evolution of the different package types over the years with a forecast until 2020. Until the early 1990s through-hole packages accounted for the majority of IC packages. Through the 1990s, SMT packages largely replaced through-hole packages. Low pin count peripheral packages such as small outline (SO) packages, leadless chip carrier (LCC) packages, and quad flat packages (QFP)

Percent of total ICs

M13.088bp-waves

100% Bare die (COB) 90% 80% 70% 60%

Through -hole (TO & DIP) Surface mount (SO, LCC, QFP, TAB)

50%

Modified leadframe (QFN, MLF, MLP)

40% 30%

Array package (BGA, CSP) age pack ip in h c p Fli Flip chip (DCA, WLP)

20% 10% 0% 1980

FIGURE 21.6

1985

1990

1995

2000

2005

2010

2015

Forecast by package type. (Courtesy Prismark Partners LLC.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

2020

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.8

PACKAGING 21.8

FINAL MANUFACTURING

dominate. Especially peripheral packages with near CSP size, such as the quad flat no-lead (QFN) package are rapidly gaining importance. But the share of area array packages such as BGAs and CSPs is growing. The adoption of flip chip in the form of direct chip attach, wafer level packaging, or flip chip in package will continue at a rapid pace. Forecast by Product Type. Figure 21.7 shows a breakdown of FCIP by product category. FCIP represents high-end packages in terms of lead count and performance and is among the fastest growing packaging technologies. Unsurprisingly, microprocessors (MPUs) account for the majority of FCIP products in 2003 followed by chipset and graphic ICs. In this forecast, however, it is expected that other products such as microcontrollers (MCUs), digital signal processors (DSPs), or analog devices will quickly adopt FCIP as well and will outnumber MPUs by 2008. 21.1.3 The Electronic Packaging Industry Semiconductor front-end manufacturing is strongly driven by the need to advance to each next technology node. Processing die at the wafer level and increasing the wafer diameter over the years (up to 300 mm to date) have been key to increasing productivity and meeting the cost targets of the industry. Packaging, on the other hand, used to be rather cost driven. In consequence, packaging is still mostly done at the die level, and IC manufacturers have cut costs by moving many of their packaging operations to countries with low-cost labor or by outsourcing packaging to specialized subcontractors. But with ever-increasing semiconductor performance the electronic packaging industry is changing. Conventional (wire bond based) packaging is starting to reach its limits when it comes to fulfilling all the functions described under the section, “The Role of Electronic Packaging,” for high-performance dice. Area array packaging in particular increases the complexity of package design, at the same time adding significantly more value to the chip than most other packages. The technological challenges in packaging are growing, and the packaging industry has to look for means to advance in technology and to increase productivity at the same time. It is therefore expected that, similar to the front end, wafer level processes will be increasingly adopted in the back end to benefit from the same productivity advances. Today, outsourcing represents an important share of the worldwide packaging, assembly, and test revenue. Among the largest packaging subcontractors are Amkor Technology, Advanced Semiconductor Engineering (ASE), Siliconware Precision Industries (SPIL), and STATS-ChipPAC. Production facilities are predominantly in East Asian countries and in Taiwan in particular. Packaging foundries have been a reality long before the first silicon foundries were established (Amkor Technology was founded in 1968, TSMC was founded in 1987). Expectations in the industry are that

2003

2008

Memory Logic/ASIC 15 M 3.5% Analog 5 M 1.2% 55 M 12.9%

Chipset/graphics 112 M 26.2% MCU/DSP 40 M 9.4%

MPU 200 M 46.8%

Total: 427 M units

FIGURE 21.7 Partners LLC.)

Logic/ASIC 350 M 15.4%

Memory 120 M 5.3%

Chipset/MPR 293 M 12.9%

Graphics 137 M 6.0%

Analog 435 M 19.2%

MPU 310 M 13.7% MCU/DSP 625 M 27.5% Total: 2270 M units

Flip chip in package by the product type for 2003 and 2008. (Courtesy of Prismark

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.9

PACKAGING PACKAGING

21.9

the share of outsourcing will increase steadily to about 50 percent in the next few years. With more complex packages emerging, subcontractors see the opportunity for growth and are strengthening their endeavors to become technology leaders. Standards are important for the packaging industry because new package types have to comply with existing standards for testing, assembly, and board technology. There are three packaging engineering standards organizations—JEDEC in the United States, Japan Electronics and Information Technology Industries Association (JEITA) in Japan, and International Electrotechnical Commission (IEC) in Switzerland. 5 In addition, there are two international semiconductor equipment consortia for advanced packaging—Semiconductor Equipment Consortium for Advanced Packaging (SECAP) and Advanced Packaging and Interconnect Alliance (APiA). Both groups are promoting new packaging technologies in seminars and workshops. In addition, SECAP has set up a 300-mm wafer bumping line in Taiwan to demonstrate the need of combined developing efforts in automation.

21.2 PACKAGING EVOLUTION The evolution of SCPs has started from metal encapsulations and developed over the DIP for throughhole assembly and SMT packages such as the PQFP and the BGA to the CSP (see Fig. 21.6). DIPs and PQFPs represent packages with peripheral I/Os while BGAs and CSPs are area array packages where a CSP is defined as a package that is only marginally larger than the chip itself. The highest level of electrical performance is achieved by DCA where a bare die is attached onto the printed circuit board. This method has been used long before the introduction of CSPs, but the absence of any package for the die has limited the implementation of DCA into volume production. In most area array packages, the packaged die has a peripheral pad layout while the interposer/substrate provides the rerouting metallization from the peripheral pads to the area array pads. Flip chip, in contrast to TAB and wire bonding, has been proven as a reliable interconnection technology over the active IC area. The FC assembly, therefore, can be used to assemble rerouted die. This is already common for microprocessors. A wafer level package provides a rerouted die with a ball grid array and combines the advantages of FC and standard area array packaging. 21.2.1 Peripheral and Area Array Packages The packaging industry is confronted with a wide range of pin counts and form factor requirements. Memory chips, for example, have less than 120 I/Os in contrast to logic chips like microprocessors or ASICs with often several thousand I/Os. Peripheral packages can accommodate smaller pin count devices but area array packages are necessary for large I/O numbers if the package size needs to be small. Using area array interconnection enables a much larger interconnection pitch for the same amount of I/Os. If x and y are the die lengths and pp and pa are the peripheral and area array pad pitch, the maximum number of I/Os is n = 2(x/pp − 1) + 2(y/pp − 1) for a peripheral layout and n = (x/pa − 1)(y/pa − 1) for an area array layout. A 5-mm × 5-mm large die, for example, could have a maximum of 9 × 9 = 81 I/Os in an area array design with a pitch of 0.5 mm. This can be assembled with standard SMT equipment. In a peripheral package, the pitch would have to be 0.23 mm, which would be difficult to assemble with the standard SMT and board technology and would lead to a cost increase. The majority of all peripheral and area array packages are plastic packages. Three common packages with peripheral pins are shown in Fig. 21.8. The DIP is a typical through-hole package, while the small outline package (SOP) is designed for SMT. The PQFP is a SMD package with pins at all four sides of the chip to maximize the possible pin count. All these packages use lead frames. A lead frame is a sheet metal frame on which a die is attached, wire bonded, and molded with plastic (Fig. 21.9, left). The lead frame serves as a holding fixture in the assembly process and as an electrical and thermal conductor from the die to the PCB. In most cases the die is mounted onto the lead frame by gluing or soldering and is electrically

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.10

PACKAGING 21.10

FINAL MANUFACTURING

Dual In-line Package (DIP) FIGURE 21.8

Small Outline Package (SOP)

Plastic Quad Flat Package (PQFP)

Standard molded plastic packages.

interconnected to the leads by wire bonding. After die attach the lead frame is overmolded with plastic to form the final package body. Most lead frames are stamped. Replacing the stamping process with an etching process makes lead frames with finer structures possible. Leadless packages where leads are only exposed at the bottom side of the chip (see Fig. 21.9, right) use such etched lead frames.6 An important representative of leadless packages is the QFN package. A common area array package is the BGA package. In most BGAs, the rigid or flexible interposer provides the redistribution from the peripheral pads to the area array. Figure 21.10 shows the design of a flex-BGA (FBGA) with wire bond interconnects. The die is attached to the substrate and then encapsulated. Mechanical stiffness is provided by a metal frame, and a radiation plate is added for further protection and serves as a heat spreader. Today, in most BGAs, the die is wire bonded to the interposer. The growing number of I/Os, however, is driving flip-chip interconnects, and the number of flip-chip BGAs (FC-BGAs) is currently growing rapidly. The FC-BGA represents a typical FCIP technology. 21.2.2 Chip Scale Packages A chip scale (or chip size) package is defined as a package with an outline not more than 1.2 times the size of the die. CSPs are typically BGAs with a grid pitch between 1 and 0.5 mm (with a trend down to 0.3 mm). Therefore, full compatibility to SMT is given, and no additional processes or extra equipment is necessary for the assembly of CSPs. CSPs are suited for low and medium pin-count devices. Products that are packaged in a CSP include flash and other memory chips, DSPs, and analog

Leadframe package Molding compounds

Leadless package Wire bond

Molding compounds

Wire bond

Die Die

Leadframe Leads

Die paddle Leads (Only exposed at bottom side of the package)

FIGURE 21.9

Principles of molded plastic packages with lead frames.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.11

PACKAGING PACKAGING

21.11

Wire bonds

Radiation plate

Die Metal frame Encapsulant

Adhesive

BGA substrate (flex) Solder balls FIGURE 21.10

Design of a BGA with a flexible interposer (FBGA).

devices. It is believed that CSP will become the standard package solution in the future because they can be tested like other packaged devices. Today, a large variety of CSP designs exist. An important requirement in all CSP designs is that the CTE mismatch between the PCB and the die needs to be compensated with either interposers, lead frames, or polymer layers. Most CSPs are currently packaged using the standard die level packaging technology based on lead frames and flexible or rigid interposers (Fig. 21.11). All common interconnect techniques (wire bonding, TAB, and flip chip) are used in CSPs. The rigid interposer concept, for example, uses wire or flip-chip bonding on an FR-4 board. Wafer level packaging represents an entirely new concept and allows true chip size packages. The adoption of the CSP technology was initially difficult because of the unavailability of PCBs for these small packages with their narrow ball grid arrays. High-density substrates such as microvia boards are now available. The packaging industry owes the commercial success of the CSP to the efforts of mostly Japanese companies that demonstrated the first commercialized products using CSPs.7 21.2.3 Wafer Level Packaging Economic considerations are driving the packaging industry toward adopting WLP. The idea of WLP is to finalize as much of the packaging sequence at the wafer level as possible. WLPs are by definition true chip size packages. Wafer level processes are independent of the number of dice and the number of bond pads per die and wafer. With WLP the back end will benefit from

Wafer level redistribution

Flexible interposer

Rigid interposer

Leadframe FIGURE 21.11

An overview of principal CSP designs.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.12

PACKAGING 21.12

FINAL MANUFACTURING

productivity advances in the front end such as larger wafer diameters and die shrink. This is not the case with all the other types of CSPs where each die has to be individually mounted on a carrier or an interposer.8,9,10 Like other CSPs, WLPs come with area array pads. If the dice on the wafer have a peripheral pad layout, a redistribution process becomes necessary to reroute the peripheral pads to the area array pads (Fig. 21.12). These area array pads need to be solderable pads and are usually built up using thin-film technology. Normally a redistribution layer is a combination of polymer and metal layers. Polyimide (PI) or benzocyclobutene (BCB) is used for dielectric isolation. If the process is done at the back end of a front-end line, inorganic interlayers like silicon nitride are used as well. Aluminum or copper are the metals of choice for the rerouting metallization. The first redistribution technology was published in 1994 by Sandia. In 1995, Fraunhofer IZM and Technical University of Berlin (TUB) initiated several German and European projects to explore this technology for different applications. Over the years more and more companies started to offer WLP services in large volumes. Flip Chip International (formerly Flip Chip Technology) in Phoenix, Arizona, and Unitive (starting out of MCNC) at the Research Triangle Park, North Carolina (and since 1999, also in Taiwan) created standards in this technology under the trade names UltraCSP (FCI) and Xtreme (Unitive) and are now shipping WLPs in million pieces per week. Pure Redistribution Technologies. Today, most commercially available WLPs have redistribution layers without special resilient interconnect elements. If no underfiller is used, the thermomechanical board-level reliability of these WLPs is limited, given by the chip size, number of I/Os, and distance to neutral point. This type of WLP has therefore been adopted mostly for small die for mobile consumer products. A selection and the status of commercial sources for these WLPs is given in Table 21.5. Redistribution with Resilient Interconnect Elements. Fraunhofer IZM and TUB together with Motorola started a program in 1996 to develop new concepts of highly reliable WLPs. A modified Mitsubishi package that could be manufactured totally at the wafer level showed promising results of finite element method simulations. The technology consists of a stacked solder ball

FIGURE 21.12 Wafer level package—the peripheral pads are redistributed into an area array. Solder balls are attached to the pads of the redistribution. In this example the dielectric polymer is benzocylobutene (BCB).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.13

PACKAGING PACKAGING

TABLE 21.5

21.13

Commercially Available Pure Redistribution Technologies/Services Commercial

ACE-Tek ASE Amkor Atmel California Micro Dev. Chipbond Dallas Semiconductor/Maxim FC International MicroFab Microscale National Semiconductor PacTech Sanyo Shellcase SPIL STATS Unitive Unitive Taiwan Xintec

UltraCSP UltraCSP dBGA UltraCSP chipBGA OneWire UltraCSP

microSMD ShellBGA ShellOP ShellBGA ShellOP UltraCSP UltraCSP Xtreme CSP Xtreme CSP ShellBGA ShellOP

Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Qualifying Commercial Qualifying Commercial Commercial Commercial Qualifying Commercial Commercial Commercial

array with a stress compensation layer in between. The result was an increase in the board-level reliability of at least 10 times without using underfillers. A survey of WLP for high reliability is given in Table 21.6. In addition, these resilient package designs offer the possibility of wafer level test and burn-in. Despite the fact that some of the technologies are based on high cost processes, one should not neglect their potential for high-volume production. 21.2.4 Packaging with Higher Integration Multichip Packaging and Three-dimensional (3D) Integration. MCMs combine multiple bare dice on a substrate that are packaged as a whole. MCMs are similar to hybrid microelectronic systems but achieve higher performance. The first work was done in the middle of the 1970s for mainframe

TABLE 21.6 A Survey of WLP Technologies for High Board-level Reliability Without Underfillers Super CSP from Fujitsu, Oki, and Casio (Japan) using a ball on copper pillar Polymer Collar as a modified UltraCSP from FC International of K&S (USA) Compliant WLP by Georgia Tech (USA) using a 25-µm thick polymeric layer as a stress compensation layer Omega CSP from Hynix (Korea) using a bump on stress buffer layer Wafer Process Package by Hitachi (Japan) using a stress relaxation layer Flexible Pin by Ibiden (Japan) Sea of Leads (SoL) by GeorgiaTech (USA) using a bump on air gap structure Metal Covered Pin by Fujikura (Japan) Wafer Level Floating Pad Technology by General Electric Corporate R & D center (USA) MicroSpring on Silicon Technology (MOST) by Formfactor (USA) using metallized wire bonds on redistributed pads ELASTec by Infineon (Germany) providing compliant interconnects between memory dice and printed circuits or test boards using a redistribution onto silicone bumps

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.14

PACKAGING 21.14

FINAL MANUFACTURING

FIGURE 21.13

3D packaging using wire bonding. (Courtesy of Sharp, left; ASE, right.)

computers at IBM, where the main drivers were electrical performance and circuit density. The different MCM technologies are based on thick-film ceramics, thin-film, and PCB techniques. MCMs are classified accordingly as MCM-C (ceramic), MCM-L (laminated), MCM-D (deposited = thinfilm based), and MCM-E (embedding types using chip-first technologies originally developed by General Electric).11,12 Mainly flip-chip and wire bonding are used to interconnect the bare dice to the substrate. In an MCM-E, the chip is directly linked by thin-film metallization to the substrate circuitry, which guarantees an impedance-controlled interconnection. The major challenge that hindered MCM for mass production was cost and chip yield. Test and burn-in of bare dice is much more complicated than full functional testing of packaged dice using test sockets. Known good die became the synonym of the barrier for the commercialization of MCMs. The main applications of MCMs have been in military, aerospace, and mainframe computer applications. The situation changes, however, if tested WLPs or even CSPs are used instead of bare dice. Such an assembly is not an MCM according to the original classification but a promising packaging concept included in the different SiP approaches, which will be discussed later in more detail. Stacking of chips can be done using wiring bonding, flip chip, or vertical integration by wafer stacking or chip-to-wafer stacking. The main advantage of wire bonding is the existing infrastructure. In addition, there is no need of modification of chip pads. The final aluminum metallization of the IC can be used directly for the bonding process. For example, Amkor, ASE, Hitachi, and Sharp use this approach mainly for memory dice (Fig. 21.13). The disadvantages are the limited electrical performance and the lack of additional integration of passive components. Figure 21.14 shows a stacked FC-BGA with a flip-chip mounted microcontroller

FIGURE 21.14 Chip-on-chip integration using FC bonding. (Courtesy of Fraunhofer IZM and Infineon.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.15

PACKAGING PACKAGING

21.15

on a silicon chip with redistributed IC pads. The interconnection from the interposer to the board is done using wire bonding. In this approach a base chip on wafer level is used as an active substrate for FC bonding of a second die. The electrical and mechanical interconnection is done using eutectic solder balls that are deposited by electroplating. The base chip is redistributed to an area array of UBM pads. A low electrical resistivity of the redistribution is achieved by electroplating copper. The dielectric isolation is achieved using the low-k photo-BCB. Infineon Technologies has developed a stacking technology for face-to-face interconnection using very thin metallizations. The technology is called SOLID, which is an acronym for diffusion soldering—solid-liquid interdiffusion.13 In contrast to the preceding generation where chips were attached with adhesive in a cost-intensive and technically unsatisfactory process, two chips are simply placed on top of each other face to face, as in a “sandwich.” The next step is the soldering. Both contact surfaces are coated with thin copper (3 µm) before being permanently bonded at temperatures of around 270°C. To avoid the FC bonding process the thin chip integration (TCI) concept can be used. The key element of this approach is the use of extremely thin ICs (down to 20-µm thickness) that are incorporated into the redistribution. This technology offers excellent electrical properties of the whole microelectronic system.14 Integration of Passives. Resistors, capacitors, and inductors are generally referred to as passive components. Compared to the developments in IC technology passive components at the circuit board level have made only marginal advances in decreasing size.15 Therefore, they are a major hurdle for further miniaturization of electronic products. For example, decoupling capacitors play a major role in reducing the switching noise for high-speed digital electronic systems. As the switching speed is well above 1GHz and the power supply voltage is decreasing at the same time the power supply noise is not negligible. Large capacitance density and small leakage current are required. They should have very thin capacitor dielectric thickness and should be mounted as close to the chips as possible to minimize parasitic inductance. The smallest passive SMT component today is 0.5 mm × 0.25 mm (generally referred to as 0201). Over a trillion passives were used in 2000 that cost about 0.5 cent per SMT piece. But 1.3 cent has to be paid for the assembly, inspection, test, and rework. Analog and mixed signal systems especially require lots of passives. The ratio of passives to ICs is in the range of 12:1 to 25:1 in cellular phones. This can increase to over 30:1 for camcorders or pagers. The number of passives has increased from 369 for early Pentium designs to 2195 for the Pentium III. Ulrich and Schaper classify the different integration levels as follows:15 • Discrete passive component: As a single passive element which is packaged for THT or SMT. • Integrated passive component: Which consists of multiple passives sharing a package or a substrate. • Embedded passive component: Which is inside a substrate for active components. • Passive array: Which consists of passives of like functions in one package or one chip. • Integrated passive network: Consists of multiple passive components of more than one function formed on the surface of a separated substrate and packaged as a single SMD. Simple functions like filters or terminators are formed. • Integrated passives subsystems: Are similar to passive networks but are more complex and could include active devices packaged together in a single SMD. These subsystems are close to SiP concepts. The potential of integrated passives is obvious if one compares it with the revolutionary change in electronics going from single transistors to integrated circuits. Moore’s law was the result of the constant development in on-wafer technologies. The main difference is that passives cannot be scaled down to submicrons due to physical limits. In addition, the possible reduction in footprints is limited for integrated passives. For example, discrete ceramic SMT capacitors are using multilayer

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.16

PACKAGING 21.16

FINAL MANUFACTURING

structures (10 to 20 layers) that are unacceptable for integrated passives. Therefore, SMT capacitors can achieve higher capacitance values at a given board space. System in Package. The definition of SiP has not been well established across the literature. Basically, SiP requires breaking up the boundaries between the system design, and the semiconductor front end and back end in order to have more flexibility for the overall product design and thus enhance the product performance and reduce cost. A paradigm shift in product design and manufacturing is necessary because Moore’s law is now more and more restricted by packaging and substrate technology than by nanotechnology. A close cooperation among semiconductor, interconnection, integrated passives, substrate, and system designers will be necessary.16 Stacked memory dice should not fall into the class of SiP; a minimum combination of logic and memory is required.17 The increasing role of packaging for microelectronic systems is schematically shown in Fig. 21.15. Even though the SMT and area array technology were major developments in the electronic industry, the gap between the semiconductor technology and packaging has been increasing. System in package will be the packaging wave for the next 10 years to keep Moore’s law alive. SiP bears many similarities with MCMs. The possibility to use tested CSPs or WLPs instead of bare dice without compromising form factor and performance considerations compared to the bare die assembly is a new aspect of SiP. Chip stacking and integration of passives are also included in the SiP concept. Tummala from Packaging Research Center (PRC), Atlanta, is postulating system on package (SoP) as an extension of SiP including optical interconnects to substrates.18 An alternative approach to SiP that has been discussed in the last few years is the system on chip (SoC) technology where the system functionality is fully integrated into a single chip. The industry, however, now commonly agrees that SiP has many advantages over SoC which include: • • • • • • •

Combination of different semiconductor technologies Integration of MEMS, MOEMS, Biosensors, and the like Faster design Faster prototype cycles Higher flexibility Reduced mask costs Higher yield due to KGD concepts

System volume a.u. 1000000

Through-hole wave Surface-mount wave

100000 Se

mi

10000

Area array wave

co

nd

uc

1000

tor

HDI-wave

s—

Mo

ore

’s l

aw

Packaging gap

100 SIP wave 10 1

1970

FIGURE 21.15

1980

1990

2000

2010

2020

The increasing role of packaging for microelectronic systems.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.17

PACKAGING PACKAGING

21.17

The ever decreasing size of electronic packages has brought the technology from simple plastic housing to material and equipment challenges soon to be touching the nanoworld. The simulation of electrical, thermal, and thermomechanical nature will gain higher importance to identify the interaction of packaging material. The concept of SiP will not only be the key to further miniaturization but also to higher reliability due to fewer interfaces and interconnects.

21.3 WAFER BUMPING AND REDISTRIBUTION TECHNOLOGY 21.3.1 Process Technology Wafer Bumping Overview. A bump is defined as a usually conducting 3D interconnect element between a die and a substrate. In most cases the bump is formed on the wafer prior to wafer dicing and die attach. This process is called wafer bumping. Interconnect methods are soldering, thermocompression bonding, and adhesive bonding (Fig. 21.2). Depending on the application, many different bump metallurgies are used ranging from pure Au, Cu, Sn, or In to alloys such as PbSn, AuSn, AgSn, and AgSnCu. Various parameters need to be looked at when choosing the best bump metallurgy. These parameters include the melting point, bump hardness and shear strength, the conductivity, the resistance to electromigration, the tendency to form oxides, the bond pad metallization of substrate and wafer, and finally the cost of depositing the metal. Common bumping technologies include gold bumping, solder bumping, and copper posts. Gold bumping. Gold interconnects don’t oxidize or corrode and have excellent electrical and thermal conductivity. Because of their high melting point, gold bumps are not reflowed. Gold bumped dice are typically attached to flexible substrates or tapes (tape carrier packaging, or TCP) by thermocompression bonding (TAB) or adhesively bonded to glass substrates (chip on glass, or COG) using conductive films. Gold bumping allows very tight bump pitches. Today, LCD driver ICs with their high I/O count and peripheral bump layout account for the majority of gold bumped dice. Figure 21.16 shows a typical gold bumping process. A TiW-Au UBM is sputtered onto the wafer and a liquid photoresist film (approximately 20-µm thick) is spin coated, exposed, and developed. The gold is deposited by electroplating followed by resist strip and UBM etch. Finally, the gold bumps are softened by an annealing step. Devices are tested after die attach to the tape. Rework of TAB, COF, or COG interconnects is difficult. Today, the minimum gold bump pitch for LCD drivers in mass production is around 35 µm with a 10-µm gap between bumps (COG applications allow finer pitches than TAB). These are the tightest pitches of any bumping process in mass production.

Gold bumping 20 µm 1. Passivation layer

4. Resist development FIGURE 21.16

2. Sputter UBM and coat resist

5. Electroplating

3. Exposure

6. Resist stripping and etching of plating base

Gold bumping process flow.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.18

PACKAGING 21.18

FINAL MANUFACTURING

Solder bumping. Soldering is the most common SMT assembly technology and allows the formation of reliable interconnects between a die and rigid substrates that often are uneven by a few 10 µm. Soldering, therefore, largely avoids any stress buildup between a die and a substrate during assembly. In addition, solder joints allow for easy repair of defective devices. On the other hand, electrical and thermal conductivity of solder is not as good as that of gold or copper interconnects. Soldering a bare die to a substrate is known in the industry as the C4 process, an acronym and technology introduced by IBM in the early 1960s. Solder bumps are the common interconnect elements of high-end flip-chip assembly (Table 21.7). Today, the flip-chip technology is used in mass production for high-end dice such as microprocessors and graphic chips. Solder bumping requires a wettable surface on the IC pad and on the substrate. Often nonwettable solder stop layers are added to the wafer (polyimide or BCB) and to the board (epoxy). To reduce thermally induced stress on the solder interconnects, the gaps between the interconnects are underfilled by a filled epoxy. The maximum solder bump height is limited by ball pitch while the minimum solder bump height must not compromise the interconnect reliability and has to allow reliable flux cleaning and underfilling. Flip-chip dice have typical solder bump heights of approximately 100 µm. Solder interconnects are formed during a reflow process with a reflow temperature of about 220°C if eutectic PbSn (Pb: 37 percent, Sn: 63 percent, melting point: 183°C) is used. This temperature range is acceptable for all common substrate types. High-lead PbSn bumps, on the other hand, are more stable against electromigration and are commonly used for applications requiring high current densities as is the case for microprocessors. Flip-chip bonding with high-lead PbSn (Pb: approximately 95 percent) solder joints with a reflow temperature of about 350°C is possible on ceramic substrates or high temperature polymeric board materials but not on many others. High-lead PbSn bumps can be soldered to substrates by providing eutectic PbSn on the substrate and reflowing the eutectic solder only. This allows the removal of the flip chip by melting the eutectic solder joint maintaining the integrity of the high-lead PbSn bumps on the die. Another advantage is that such a flip-chip interconnect has a very defined standoff height because the high-lead bump does not melt. Legislations by the European Union and other countries demand the ban of lead from electronic products by 2006 with the exception of high-lead solders for microprocessor applications. However, the industry faces certain technological barriers replacing PbSn flip-chip interconnects with lead-free solders. This is explained in more detail under the section “Solder Deposition.” TABLE 21.7

Selection of Solders for Flip-chip Interconnects

Solder

Melting point

Remark

63Pb37Sn

183°C

Eutectic PbSn, low melting point, compatible with organic PCBs, commonly used for most SMDs High lead, good electromigration behavior, highly reliable thermomechanical interconnect, flip chip on ceramic substrate; no reflow of high-lead bumps during chip attach on PCB (eutectic PbSn on PCB side), flux-free reflow in H2 atmosphere

95Pb5Sn (or similar)

315°C

96.5Sn3.5Ag (or similar)

221°C

Currently most common binary lead-free solder for flip chip, typically used in conjunction with electroplating

97Sn/3Cu 95.5Sn3.9Ag0.6Cu

227°C 218°C

Difficult to electroplate, short bath lifetime. Common lead-free solder paste, Cu content reduces Cu consumption from UBM

80Au20Sn

280°C

Common for flux-free optoelectronic assembly on gold finishes, controlled standoff height

In Sn

157°C 232°C

Allows very low reflow temperatures Tin whisker formation

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.19

PACKAGING PACKAGING

Processed wafer passivated

ICP soft etch C4: Mask appl.

Bump process: Pb/Sn 95/5 Pb/Sn 40/60 Au/Sn, Sn/Ag, various Pb free.

21.19

RF sputter etch

Evaporation (masked/unmasked)

Ion etch/mill

Sputtering (masked/unmasked)

Back-side coating

Chem. etch of Al/Zincate

Pretreatment

Native oxide removal

Photoresist patterning

PR patterning, etchback UBM Patterning Stripping of back-side coating

UBM process: Cr-Cr:Cu-Cu-(Au), Ti-(Ti:W)-Cu, Ti-Ni, Al-Ni:V-Cu, e-less Ni

E-less Ni UBM deposition

Evaporation

Mask removal

Electroplating,

Resist stripping/ etchback UBM

Screen/stencil printing Flux cleaning

Solder sphere deposition

Wafer reflow

Bump deposition

FIGURE 21.17 The basic process flow of solder bumping technologies. (Courtesy of Unaxis and Fraunhofer IZM.)

Various techniques to deposit solders exist. Their basic process steps are shown in Fig. 21.17. It is important to control the bump volume across the wafer as well as the solder composition in order to achieve a uniform bump height distribution and to avoid an incomplete reflow process. The most important deposition techniques for solder bumping are evaporation, electroplating, and solder paste printing. Figures 21.18 and 21.19 depict the typical wafer bumping process flows for electroplated and solder paste bumps. The process flow shown in Fig. 21.18 uses electroplating to deposit the solder. In this case the UBM that provides a wettable surface is sputtered, and a thick liquid or dry film resist is coated onto the wafer. The resist is then exposed and developed. Electroplating allows the solder to be plated over the top of the resist layer to form mushroom-like structures. Then the resist is stripped, and the UBM is etched between the bumps. The reflow process nearly transforms the solder into a ball shape and leads to the formation of intermetallic compounds at the UBM/solder interface, which is important for a reliable adhesion of the bump to the UBM (see the section “Under Bump Metallization”). The advantage of mushroom plating is that the photoresist layer can

Solder bumping (mushroom) 25 µm 1. Passivation layer

4. Electroplating (PbSn)

FIGURE 21.18

2. Sputter UBM and coat resist 3. Exposure + development

5. Resist stripping

6. Plating base etch and reflow

Solder bumping process flow (electroplating).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.20

PACKAGING 21.20

FINAL MANUFACTURING Solder bumping (photo stencil)

5 µm 1. Passivation layer

2. Sputter UBM and coat resist

3. UBM etch and resist stripping

70 µm

4. Laminate dry film resist, expose and spray develop

FIGURE 21.19

5. Solder paste screening

6. Resist stripping and reflow

Solder bumping process flow (photo stencil).

be significantly thinner than the final solder ball height and the solder deposition is fast because the solder surface is growing when being plated over the resist edge. A disadvantage is that with mushroom bumping, plating control becomes more demanding. The photoresist thickness in mushroom plating typically is between 25 and 60 µm. On the other hand, mushroom plating becomes a problem for finer bump pitches. A thicker resist layer (approximately 100 µm) is used for fine-pitch bumping where the solder is completely plated in the bump mold. The process shown in Fig. 21.19 uses solder printing. Either metal or resist stencils are used where resist stencils are required for finer pitches and are the most common solution for flip-chip bumping. With stencil printing, the UBM is patterned and etched before solder deposition. Next, a thick photoresist (approximately 70 µm and larger) is coated onto the wafer. After exposure and development solder paste is screened into the molds. As the UBM pad defines the final bump base, the molds for the stencil process can have a larger footprint than the final bump in order to have more solder paste being screened into the mold to achieve a larger bump height. Before resist stripping the

70−100 µm

Copper posts

1. Passivation layer

2. Sputter UBM and coat resist

Solder

Solder

Cu

Cu

4. Electroplating (Cu + solder)

FIGURE 21.20

5. Resist stripping

3. Exposure + development

6. Plating base etch and reflow

A copper post process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.21

PACKAGING PACKAGING

21.21

solder paste has to be heated to be transformed into a solid solder. After the resist strip the solder is reflowed to take on a ball shape. Copper posts. Copper has approximately 10 times better electrical and thermal conductivity than PbSn solders. Copper posts are therefore attractive whenever high currents pass through the interconnect as is the case with power devices. This is particularly important for fine-pitch bumping that reduces the size of the bump base and increases the resistance of the bump. Copper posts are not reflowed and therefore can be used to provide high-aspect-ratio structures for fine-pitch bumping without reducing the bump standoff height. For the interconnect to the substrate a solder tip is added on top of the post. Copper posts are plated and a typical process flow is shown in Fig. 21.20. Unlike solder plating copper posts require in-via plating with very thick resist layers of typically 70 µm and more. Copper posts are discussed as future bump interconnects for microprocessors. Other bumping technologies. All the bumping techniques described previously use either solder printing or electroplating. Alternative bump technologies include stud bumping, solder jetting, and evaporation. Electroless bumping is actually an under bump metallization technique and is described under the sections “Under Bump Metallization” and “Electroless Plating Tools.” Stud bumps are made with wire bonders by cutting off the wire right after bonding it to the IC pad. The bump can be either left with a spike or can be coined creating a flat surface or can be sheared off across the top directly after bonding. This technique is fairly flexible with regard to the desired bump metallurgy and can be used for example, for gold bumping and even for solder bumping. Since stud bumping is a serial process it has little importance for mass production but is an important technique for flip-chip prototyping and low-volume manufacturing. Stud bumping is the major technology applicable to singulated dice. Solder jetting is a serial and maskless solder deposition technique where solder droplets are ejected from a print head onto the wafer. High ejection frequencies are possible. However, overall process control is difficult and solder jetting has not yet been adopted by the industry. Evaporation is the deposition method of the classic IBM C4 process. In terms of quality evaporated solder bumps are excellent but the overall cost of the evaporation process is very high. The industrial importance of evaporation therefore currently decreases quickly especially with the transition from 150-mm to 200-mm and from 200-mm to 300-mm wafers. Under Bump Metallization. UBM is the direct interface between the interconnecting solder and the final chip metallization. The UBM has to provide a low-contact resistivity to the chip pad and the solder, good adhesion to the chip metallization and the chip passivation, and a hermetic seal between the UBM and an IC pad. It has to be a reliable diffusion barrier between the IC pad and a bump with low film stress, and it needs to be sufficiently resistant to stress caused by thermal mismatch or during die assembly. In case of PbSn bumping common UBM stacks are Cr-Cr:Cu-Cu-Au (original C4 from IBM); Ti-Cu; Ti:W-Cu; Ti-Ni:V; Cr-Cr:CuCu; Al-Ni:V-Cu; and Ti:W(N)-Au. Usually, these UBM stacks are subsequently deposited by sputtering. A schematic drawing of Ti:W-Cu for PbSn is given in Fig. 21.21. In the case of PbSn bumps deposited onto a copper-based UBM, intermetallic compounds (IMCs) between Sn and Cu are formed by the reflow process FIGURE 21.21 An example of a UBM stack providing the required adhesion of the bump to the (Ti:W-Cu) for PbSn bumps.19 chip pad. IMCs are brittle in nature due to the ordered crystal structure, which is in contrast to solid solutions like PbSn. The metals that are mostly used in packaging—Cu, Ni, Au, and Pd—form binary intermetallics with Sn-based solders of the Hume-Rothery type.20 These compounds are based on electron valence bonding. The crystal structure is controlled by the number of electrons in the bonding.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.22

PACKAGING 21.22

FINAL MANUFACTURING

The composition of each phase can be calculated based on the concentration of the valence electrons. For example, Cu3Sn and Cu6Sn5 phases are found for intermetallics of Cu and Sn, and Ni3Sn4 and Ni3Sn phases are formed between Ni and Sn. The growth rate depends on the temperature, the different activation energies of compound forming, and diffusion processes. In general, the intermetallic growth rate is much higher for Cu compared to Ni. This is becoming more important for the lead-free solder due to its higher Sn content. Several methods have been developed for the UBM deposition. As described earlier the UBM deposition can be part of the sputtering/plating process (see the sections “Vacuum Metallization Systems” and “Solder Deposition”). All bumping processes shown in Figs. 21.16 to 21.24 include a UBM etch process. Some devices have sensitive surface areas and do not allow such an etching process. A vacuum-based technology for the depositions of UBM avoiding the metal etch process is the so-called liftoff process. This technology is not restricted to UBM deposition but can also be used for other thin-film metallization. A general process flow is given in Fig. 21.22. The liftoff photoresist is deposited by spin coating on the wafer. Only negative-type resists can be used because an undercut in the opening has to be created that acts as an aperture for the vacuum metallization. The key step is the separated metal deposition on the resist and inside the opening. By stripping the resist, the metal is lifted leaving a well-defined metallization. Mostly evaporation is used for this metallization because the sputtering processes usually have a temperature budget above the glass transition temperature of the resist. Electroless Ni is a complete wet deposition process avoiding lithography and vacuum-based processes. The process is based on autocatalytic deposition, which is necessary to plate more than monolayers without any current. The energy is supplied internally inside the plating bath by the oxidization of adsorbed hypophosphite. The released electrons are able to reduce Ni2+. Phosphorus converted from hypophosphite is built into the Ni layer. This can change the mechanical and electrical properties of the Ni. To start the electroless Ni deposition, the Al surface of the bond pad has to be zincated. The Al is therefore cleaned and microetched to remove the oxide and improve the adhesion to the Ni. Due to the active electrical nature of circuits, the bottom side of the wafers has to be protected by a resist that needs a cure to withstand the wet chemicals. The deposited Ni has a standard height for solder bumping of typically 5 µm. The plating uniformity is better than 5 percent on the wafer and batch to batch. The phosphorus content should be around 10 percent. A flash of Au (less than 100 nm) is deposited onto the Ni to prevent the formation of oxides, which would decrease the wettability for solder deposition. The Au content should be as low as possible to avoid brittle Au intermetallics at the solder interface. The Ni UBM has been extensively tested. No failures were detected even after 10,000 h thermal storage at 300°C; 10,000 cycles AATC (−55/ + 125°C); and 10,000 h humidity storage (85°C/85 percent RH).21 Solder Deposition. The three most important solder deposition techniques in wafer bumping are electroplating, solder paste printing, and preformed solder ball attach. Table 21.8 compares the

Wafer

Deposition of resist

Exposure

Development

Vacuum metallization

Resist lifting

FIGURE 21.22

The process flow of Liftoff.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.23

PACKAGING PACKAGING

TABLE 21.8

Electroplating Solder pasting Ball attach

21.23

Comparison of Different Solder Deposition Techniques Flexibility of use with different solder types

Cost of solder deposition

Fine pitch capability

Typical application

Limited Good Very good

Medium Low Low

Very good Medium Poor

Fine-pitch flip chip, high-end die Low to medium pin-count flip chip BGAs of wafer level packages

advantages and disadvantages of all three technologies. Please note that the industry tries to push the limits of each technology and that this table does not necessarily represent a common consensus in the industry. Plating. An electroplating process as a low-cost alternative to evaporation was introduced by Hitachi in 198122 and is now widely used for fine-pitch bumping. Electroplating is a relative slow deposition technique with typical plating speeds ranging from 0.2 µm to only a few micrometers per minute depending on the deposited material. The setup of a plating system is described under the section “Electroplating Systems.” An important challenge in the plating process is the design and maintenance of the composition and purity of the electrolyte. In the case of PbSn plating tin and lead salts (see Table 21.13) are dissolved in the electrolyte and dissociate into their anions and cations. Due to the applied voltage, the positively charged Sn2+ and Pb2+ cations migrate to the cathode (wafer) and are deposited by a discharge reaction on its surface. For this to occur, the cations need to be reduced to the metallic state by accepting electrons from the cathode. The plating time can be described by Faraday’s law t=

r ⋅T JEa

where T = plating thickness r = density of the metal deposit E = electrochemical equivalent a = current efficiency ratio of actual/theoretical weight deposited J = current density In fact the electroplating process is a much more complex process. For example, the mechanism of the metal deposition consists of several steps—the hydrated metal ions have to diffuse to the wafer surface covered by a Helmholtz double layer. In addition the metal ions can be chemically attached to complexing molecules. Additives control the metal growth to achieve fine-grained solders. Obviously, the plating time can be shortened by increasing the plating current density. However, the maximum current density is limited because high plating speeds translate into higher challenges in plating bath maintenance. For the deposition of solders the plating speed of the individual constituents must be balanced according to the desired final solder composition. The electrochemical equivalent is a material dependent constant and a function of the atomic mass and the number of valence electrons of the individual metal. Therefore, the only parameter that allows the balancing of the partial plating speeds is the plating current density J or in other words the resistivity of the electrolyte. With a given voltage the current density of each individual metal is obviously a function of the density of the corresponding cations in the plating bath. Another important factor that strongly influences the current density is the electrochemical potential of the cations. This electrochemical potential describes the energy required to reduce a cation to its metallic state. It is standardized to the normal hydrogen electrode that has 0.00 V by definition. In the case of PbSn these standard electrochemical potentials are: Pb2+ + 2e− → Pb0 (−0.13eV) Sn2+ + 2e− → Sn0 (−0.14eV) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.24

PACKAGING 21.24

FINAL MANUFACTURING

The probability for each of these reactions is a function of the energy it takes to reduce the cation. In the case of PbSn the natural tendency to reduce Pb2+ is slightly higher than the natural tendency to reduce Sn2+. For other solders the electrochemical potential of each constituent can be significantly different, which can lead to difficulties in designing the electrolyte. Furthermore, the equilibrium between the metal and its ions is controlled by the activity (or approximated by concentration) of the products and reactants, which is described by the Nernst equation. The actual cell potential departs from the equilibrium value by the overpotential or cell polarization that includes all concentration, diffusion, and other effects. These can be minimized by bath agitation, high ion content, and lower current density. In addition, the seed layer must be thick enough to avoid voltage drops below a few millivolts. A deposition rate of over 4 µm/min with a uniformity of less than 3 percent (1 sigma) over 300 mm can be achieved with optimized conditions using automatic plating systems. The electrolyte composition has to take all these factors into account. This can be done by optimizing the cation concentration ratio or by organic additives that modify the electrochemical potential of the individual cation types. Designing proper electrolytes for alloys, however, is difficult and becomes more difficult and expensive when more elements are involved. Another difficulty is that the constituents of the electrolyte can react with each other thereby modifying the electrolyte performance. Therefore, binary alloy compositions like PbSn and SnAg are common while ternary alloys are difficult and expensive to plate. This is a certain limitation of the plating technology for lead-free manufacturing because ternary or even quaternary alloys might become the preferred lead-free solution in the industry. Plating techniques can use constant voltage (potentiostatic), constant current (galvanostatic), or pulse plating. Pulse plating is the method of choice for fine-pitch application providing a more uniform, smooth deposit with less porosity. Solder printing. Solder printing is a standard process technology in the manufacturing of PCBs. The typical setup of a stencil printer is shown in Fig. 21.40. Typical solder pastes that are screened into the apertures of the stencil consist of solder particles of 15 to 45 µm diameter in binders and flux. Small grain size is important for fine-pitch bumping. The grain size, however, should not be too small in order to minimize the active solder surface to avoid excessive oxidation and to prevent the solder being taken away with the flux. The reflow process forms the solder ball from solder particles. But at the same time it significantly reduces the volume of the originally deposited solder bump. Especially for fine-pitch area array designs this limits the total solder volume that is deposited by solder printing. Another difficulty of stencil printing for fine-pitch bumping is the formation of voids during reflow processes. On the other hand, solder printing is a fairly simple and inexpensive process step when compared to electroplating. An important advantage of stencil printing is the large variety of available solder pastes. This offers flexibility and is of particular importance for selecting leadfree solders. Ball attach. Direct ball attach is only used for large solder balls of typical diameters of 300 µm or above. In some cases a vacuum head serves as a template for the ball layout on the wafer and picks up preformed solder spheres from a reservoir. The spheres are dipped into flux and are placed on the wafer and are reflowed. The advantage of ball attach is that it is an inexpensive way to provide large solder volumes and that it is easily applicable to any solder type. Ball attach is often used to provide solder balls on redistributed dice where the pitch of the area array pad layout is larger or equal to 500 µm. Equipment makers are trying to push the limits to finer geometries. Process Technology for Pad Redistribution Layers (RDL). Several different redistribution processes have been developed but the main process steps are similar to each other. Differences exist mainly in the material selection. As an example the redistribution technology of Fraunhofer IZM/TU Berlin will be described in more detail (Fig. 21.23). First a dielectric layer is deposited on the wafer to enhance the passivation layer of the die. Pinholes in an inorganic passivation would give shorts in the rewiring metallization. The polymer layer underneath the rewiring metallization acts also as a stress buffer layer for the bumping and assembly processes. Using photosensitive polymers requires fewer processing steps for thin-film wiring than nonphotosensitive materials that have to be dry etched. Fraunhofer IZM/TU Berlin uses photo-BCB

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.25

PACKAGING PACKAGING

21.25

Redistribution Perimeter pad

Dielectric (Polyimide or BCB)

Resist

1. Passivation layer

2. Coat dielectric and open pads by photolithography

3. Sputter plating base and coat resist

Area array pad

Dielectric (Polyimide or BCB)

5. Electroplating and resist stripping

6. Etch plating base, coat dielectric and open pad

4. Print redistribution (photolithography)

FIGURE 21.23

The process flow of an RDL process. (Courtesy of Fraunhofer IZM.)

(Cyclotene). Compared to other polymers BCB has a low dielectric constant and dielectric loss, minimal moisture uptake during and after processing, very good planarization, and a low curing temperature. The rewiring metallization consists of electroplated copper traces to achieve a low electrical resistivity. A sputtered layer of Ti:W-Cu (200/300 nm) serves as a diffusion barrier to Al and a plating base. A positive acting photoresist is used to create the plating mask. After metal deposition, the plating base is removed by a combination of wet and dry etching. The copper process is shown in Fig. 21.24. A second photo-BCB layer is deposited to protect the copper and to serve as a solder mask. BCB can be deposited directly over the copper metallization without any additional diffusion barriers. Electroplated Ni/Au is used for the final metallization. Solder balls (high melting or eutectic PbSn) are deposited by solder printing directly on the redistributed wafers. Then the solder paste is reflowed in a convection oven under nitrogen atmosphere, and flux residues are removed in a solvent adapted to the used solder paste (Figs. 21.25 and 21.26). The mean value of the solder ball diameter can be adapted to the assembly and board requirements between approximately 100 and 250 µm depending on the ball pitch. Shear testing is the method of choice for a first quality check. Values for these ball diameters should be higher than 130 cN per bump. Dicing the wafer with a standard wafer saw completes the WL-CSP buildup. The reliability of

Sputter plating base (Ti: W/Cu)

Photoresist stripping Etching plating base

Photoresist processing (AZ)

Electroplating (Cu)

FIGURE 21.24

The thin-film copper process at Fraunhofer IZM/TUB.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.26

PACKAGING 21.26

FINAL MANUFACTURING

the redistribution layer is evaluated for consumer, medical, automotive, and space applications. RDL Design. There are two major different designs for redistribution—the bump and the UBM are separated to the chip surface by an additional polymer layer or the UBM is deposited directly on top of the inorganic chip passivation (Fig. 21.27, left and right). The company FCI (former FCT) came up with the classification of bump on polymer (BOP) (Fig. 21.27, left) and bump on nitride (BON) (Fig. 21.27, right) for the different built-up structures. It is still under discussion whether the type of polymer under the bump plays a critical role in the reliability. The BOP type is preferred if an FIGURE 21.25 Solder printed PbSn on redistributed underfiller is used. Different geometric values are wafer. (Photo-BCB/Cu.) possible for the design. The opening in the first polymeric passivation (a in Fig. 21.27, left) should be similar but not of the same size as for the peripheral pad passivation. The UBM and the ball size (b and c in Fig. 21.27, left) can be adjusted to the pitch of the area array. The maximization of the ball size is limited by the pitch. Today minimum ball pitches of 500 µm and even 400 µm are in production. Layer Adhesion. The reliability of a multilayer thin-film structure strongly depends on the adhesion between the different layers.23 In Fig. 21.28, the different interfaces in a photo-BCB/TiW/Cu/PbSn technology based WLP are shown. 1. Photo-BCB to the inorganic chip passivation (silicon oxide, nitride, and the like) and to metal (chip pad (Al) or redistribution metallization (Cu)) 2. Metal (i.e., redistribution metallization or UBM) to photo-BCB 3. Photo-BCB to photo-BCB 4. Solder to UBM

FIGURE 21.26 A cross section of screen printed PbSn on redistributed wafer. (Photo-BCB/Cu.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.27

PACKAGING PACKAGING

21.27

Solder ball

b Photo-BCB Electroplated Cu Electroplated Ni

UBM and RDL layer

BCB2 layer

Al pad

Si-wafer Solder-ball

a

No BCB in the streets

c

Wafer

SiN passivation

BCBI layer

FIGURE 21.27 Two different RDL layouts—polymer between a chip and a bump (left, Courtesy of Fraunhofer IZM) and UBM directly on top of the inorganic passivation (right, Courtesy of FCI).

The adhesion in these thin-film structures can be described with three mechanisms—roughness, chemical bonding using adhesion promoters, and chemical interlocking/diffusion. Important for a reliable package is the integrity of the interfaces during the lifetime of the microelectronic product. For interface (1) organosilane-based adhesion promoters are used to create essential layers to couple the organic dielectric to the inorganic surfaces. The theoretically ideal structure would be a monomolecular layer, coupling on one side to the inorganic surface and the other to the polymer. Different adhesion promoters for photo-BCB have been evaluated. High adhesion strengths on several inorganic surfaces were obtained using a vinylsilane that is spun directly on the wafer before BCB deposition. There is a strong indication that chemical bonding through Si-O bonds is responsible for the adhesion. The thickness of the adhesion promoter layer is in a range of 0.5 to 5 nm. This adhesion promoter layer improves the adhesion to values over 60 MPa on Al, Cu, and different inorganic chip passivations. The metal to BCB interface (2) depends strongly on the metallization technique.24 Electroless deposited metals have no adhesion on untreated BCB films with its very smooth surfaces (roughness in the Å range). Sputtering is used as a reliable metallization process for the redistribution of the WLP because the metal atoms have a penetration depth of around 100 nm. This guarantees the strong adhesion of over 80 MPa between the sputtered metal on the photo-BCB. Paik et al.25 described the stable interface between Cu and BCB. In addition, there is nearly no influence of the descum process (RIE) using a flourine gas/oxygen mixture, which is necessary to achieve a 100-percent electrical yield in via holes. Pure O2-plasma reduces the adhesion due to an oxidization of the BCB surface.26,27 For the photo-BCB to photo-BCB interface (3), high adhesion is obtained by performing a partial cure of the underlying BCB layers followed by a final full cure of the whole stack. A correlation between the adhesion strength and the degree of cure was found. The roughness and the surface chemistry of the photo-BCB layer modified by RIE had no significant effect on the adhesion. The mechanisms of chemical interlocking and interdiffusion are the driving forces for the adhesion between BCB layers. Therefore, the degree of cure is the key to high adhesion.

Metal (solder)

Metal (UBM)

Metal (Cu) BCB Chip surface

FIGURE 21.28

Structure of the WLP for the adhesion study.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.28

PACKAGING 21.28

FINAL MANUFACTURING

The solder to UBM interface is based on the formation of intermetallics (see the section “Under Bump Metallization”). Due to the brittle nature of those intermetallics, there should be minimum growth of these layers during the operation lifetime. Ni is preferred over Cu in the case of Sn-based solders because of the slower growth rates of NiSn phase compared to CuSn intermetallics. In conclusion the surface chemistry and physics should be carefully analyzed for the reliable build up of thin-film structure. Special emphasize has to be made to all modification processes such as sputtering and plasma. Integrated Passives. As described under the section “Integration of Passives” the integration of passive components at the board or wafer level will be an important step toward further performance enhancement and system miniaturization. Three basic material classes are needed for the realization of integrated passives elements—conductors, resistors, and dielectrics.15 These can be made out of metals, polymers, or ceramics. The main difference between polymer and ceramic technologies is the maximum process temperature that can be up to 300°C for polymers but can reach 700°C and above for the firing of ceramics. Metals like Cu, Au, Al, or metal-filled polymer thick films with a resistivity of less than 0.1 Ω/square are used for the conductors to avoid high parasitic resistance. Alloys like NiCr, CrSi, TaN, cermets (ceramic-metal composites), or carbon-filled polymers are the materials of choice for resistors having values of 100 to 10,000 Ω/square. Polymers with a dielectric constant k of 2 to 5, amorphous metal oxides (k = 9 to 50) or crystallographic ordered mixed oxides with k > 1000 are the central building blocks for capacitors. A wide variety of deposition technologies are used for integrated passives depending on the material types and the structuring process (additive versus subtractive)—sputtering, evaporation, spin-on, lamination, sol-gel, and chemical conversion such as oxidization. The different processes can be classified according to the MCM types—thin film (MCM-D), polymer thick film (MCM-L), and ceramic thick film (MCM-C). The highest performance is achieved using thin-film technology. Although this technology is still struggling with costs, the use of 300 mm substrates (glass, metal sheets, or silicon) will allow the reduction of the cost in the future. Polymer thick film is closely linked to the PCB infrastructure. Large substrate size or even roll-to-roll processing enables lowest cost processing. In addition, there is a well established PCB infrastructure that has no principal barrier for the integration of passive elements. The main hurdles, on the other hand, are the less controllable tolerances and the limited material spectrum for very high frequency applications. A tradeoff has to be made whether the additional cost and complexity to the manufacturing process, that add extra internal layers for passives, are worth free board space. Ceramic thick film is cost-wise in-between. Further cost reduction is achieved by photosensitive materials and improvements in printing but the substrate size is generally limited to 6 in. The high-temperature compatibility is an interesting feature for automotive and other applications under extreme conditions. An integrated passive filter based on thin-film technology is given as an example. The built-up process is similar to the redistribution for WLP, therefore the same production line can be used. The copper/BCB technology in conjunction with NiCr sputtering is the core process step. In Fig. 21.29, the built-up process for inductors, resistors, and capacitors are shown.

FIGURE 21.29

Thin-film built-up for integrated passive components. (Courtesy of Fraunhofer IZM.)28

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.29

PACKAGING PACKAGING

TABLE 21.9

21.29

Thin-film Passive Components. (Courtesy of Fraunhofer IZM.) Inductors

Capacitors

Resistors

BCB/Cu/BCB/Cu

BCB/NiCr/BCB/Cu

Structure

Values

BCB/Cu/BCB/Cu/BCB 0.7−80 nH Q-factor up to 35

0.2−2.5 pF

100 Ω−150 kΩ

The electrical characterization of the different elements is given in Table 21.9. The low capacitance values of 0.2 to 2.5 pF are due to the use of BCB with its low dielectric constant of 2.6. Sputtered high k materials have to be used for the nF range. A combination of these passive elements can be used for the realization of filter components. An example for Bluetooth band (2.4 GHz) is given in Fig. 21.30. One filter consists of three inductors of 3.9 nH and 2 capacitors of 1.8 nF. Microstrip lines with 50-Ω impedance are used for the interconnect of the single elements resulting in two low-pass filters of second order and one single inductor within an area of 1.3 mm × 2.6 mm. PbSn or lead-free solder balls are used for the board assembly. A similar technology using BCB/Cu as the core process has been developed by IMEC.29,30 The joint venture Intarsia (Dow Chemical and Flextronics) had installed a manufacturing line for integrated passives using BCB/Cu/sputtered TaN on 350 mm × 400 mm glass panels. It was closed in 2001. At that time the SiP concept was not yet at the horizon and Intarsia was therefore far ahead of the needs in the electronics industry. SyChip (USA) and Telephus (Korea) are recently founded companies for the commercialization of these promising technologies. 21.3.2 Equipment for Wafer Bumping Many of the wafer level processes described under Sec. 3.1 appear to be similar to front-end processes. But process requirements are very different. Therefore, standard front-end equipment is often not

FIGURE 21.30 An FC mountable integrated filter for Bluetooth band.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.30

PACKAGING 21.30

FINAL MANUFACTURING

a good choice for wafer bumping or WLP because it leads to overinvestment and overengineering. This has to be kept in mind when setting up a WLP line. Today, merchant bump services offer wafer bumping at a price depending on production volume, wafer size, and technology ranging from approximately $50 to $200 per wafer. On average, a typical bumping line processes about 3000 wafers a week. If one assumes $100 per wafer to be the cost target for a wafer bumping line, the total annual revenue of that line would be $15.6 million. If one-third of this revenue is used for equipment depreciation and the equipment has to be depreciated within five years, the total equipment cost should not exceed $26 million. Obviously this budget is small compared to a front-end line. Therefore, dedicated wafer bumping equipment are necessary. Vacuum Metallization Systems. Since the introduction of wafer bumping and WLP, thin-film metallization has gained a strong momentum for packaging. Sputtering and evaporation are the key thinfilm metallization technologies for the fabrication of ICs. The main difference between sputtering and evaporation is the kinetic energy of the deposited atoms that is in the range of 0.1 to 0.5 eV for evaporation and 1 to 100 eV for sputtering, which guarantees a much higher adhesion. In addition, the uniformity of the deposited metals is much higher. For 200-mm and 300-mm wafers, the evaporation distance has increased to a nearly unacceptable level that further decreases the deposition efficiency, being proportional to the square of the distance. Therefore only sputtering will be discussed in detail. Sputter systems are used to deposit UBM stacks and wiring metallization (typically Al and Cu) for rerouting layers. Sputter systems are vacuum tools (10−3 to 10−5 torr) that generate plasma of argon ions. Accelerated by an electrical field these ions bombard a target leading to the sputtering of the target atoms. These atoms are deposited on the wafer. Sputter systems used for UBM deposition often use magnetrons to efficiently maintain the plasma. Figure 21.31 shows a dedicated sputter system for wafer bumping applications. It consists of a deposition chamber with five sputter targets, an etch chamber to remove oxides or other contaminants from the wafer surface, and a load lock chamber. The five different sputter targets are of interest for bumping applications as different technologies (gold bumping, PbSn bumping, lead-free bumping, rerouting) require different UBMs. Batch processing usually leads to sufficient results in packaging applications. A combination of batch processing with single wafer handling (not shown) is therefore an interesting option to reduce the cost of the sputtering process. An important aspect for the cost of sputtering is the efficient utilization of sputter targets. In addition, a process has to run in each chamber at the same time. Important parameters that have influence on the properties of the deposited film and need to be controlled by the equipment are the sputter pressure and the substrate bias. Resist Processing Equipment. A photoresist process consists of the following process steps— resist coat (including resist bake), UV exposure, and develop. Resist coat. Laminators are used to coat dry film resists. The lamination process typically applies heated rolls. The control of film adhesion is particularly important when a dry film resist is used in conjunction with electroplating. For reliable further processing of the wafer, it is important

Load lock with lamp heater

Etch chamber with elevator

Deposition chamber

FIGURE 21.31 Design of a dedicated sputter system for wafer bumping. (Courtesy of NEXX Systems.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:44

Page 21.31

PACKAGING PACKAGING

21.31

to precisely cut the laminated dry film at the wafer edge and to avoid any delamination. Fully automated lamination processes often use laser cutters. The coating process with a liquid resist is more complex. Figure 21.32 shows the schematics of a spin coating process. First, a photoresist is dispensed onto the wafer. The dispense pattern can be important for the final film uniformity and for the material consumption. In most cases a spiral dispense from the edge to the center is the method of choice. Then the spin coater rotates the wafer at a speed of several hundred to thousand rotations per minute to uniformly spread the resist film across the entire wafer surface. During this step most of the solvent in the resist evaporates. The thickness of the final resist film is controlled by the resist viscosity, spin speed, and surface tension. The resist thickness of, for examples, a 50 µm thick layer can vary less than 1 percent over 300-mm wafers by optimized processing conditions. For a given resist formulation, the centrifugal force adjustable by the spin speed is the main parameter for adjusting the resist height. A complete mathematical model for describing the spinning process is still not available. For practical use the so-called spin curves (i.e., resist thickness versus rotation speed) are given by the material suppliers for adjusting a spin coater. The polymer thickness h is a function of the angular velocity ω and two parameters K and m h = K ⋅ ω −m where K describes the coater design and the solid content in the resist while the interaction of the polymer and the solvent is given by m.31 Solvents that evaporate during the spinning process, which are, for example, typical for positivetone AZ4620 resists from AZ Electronic Materials, lead to m = 0.5. Higher values are typical for polyimides that are dissolved in solvents with lower vapor pressure. The evaporation of solvents can be suppressed by a rotating lid over the spinning chuck (Gyrset coating, trademark of Suss MicroTec). This leads to a wider thickness range for a given resist formulation. Spin coating always leads to the formation of a resist edge bead due to surface tension. Depending on the subsequent process steps, this edge bead remains on the wafer or has to be removed (full or partial edge bead removal is, for example, necessary for electroplating). The edge bead is often removed chemically from the wafer by solvent dispense or by UV exposure and development where the latter is the more accurate method. The coating process has to be optimized for film thickness and uniformity, minimum edge bead, best exposure results, and minimum resist consumption. After spin coating the resist is baked in order to remove the remaining solvent from the resist. The baking temperature depends on the resist type but is typically between 80 and 150°C. The baking process has a big influence on the exposure result observed after resist development. Even if the production volume is low, it is advantageous to use a full automatic coating system for good process control and to obtain repeatable results. An automatic system at the least, has to consist of a handling module, a spin coater with a dispense unit, and a hotplate/coolplate. Often cluster tools are used that combine several of these process modules in order to increase throughput and in order to be able to run different chemistries in one system. In particular, multiple hotplates are important since baking is often the most time-consuming step when processing a thick resist. A special challenge is the resist coating of 3D structures such as trenches, via holes, or resilient bump elements. Electrophoretic resist plating is a common technology to coat severe topography

Homogeneous resist layer

Dispensed resist

Wafer FIGURE 21.32

Coating

Edge bead

Spin coating process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.32

PACKAGING 21.32

FINAL MANUFACTURING

whenever a metal surface is available. An emulsion of photoresist is used for electophoretic resists. These are commercially available from Rohm and Haas (formerly Shipley) as Intervia 3D-N and Intervia 3D-P. The organic phase consists of small micelles (50 to 150 µm). Each charged micelle contains the resist. The negative-tone Intervia 3D-N has 1 to 15 percent solvent and is cathodic. The anodic Intervia 3D-P is positive tone and has 1 percent solvent. The deposition can be done in conventional electroplaters. The deposition is very fast. Within less than a minute a 5 to 10 µm resist is deposited uniformly over a plating base. The process is self-limiting. The disadvantages are the high voltage (100 to 300 V) that has to be applied and the leveling bake after resist plating that limits the application for 3D structures. In addition, thin copper plating bases may be strongly attacked by the chemicals that are corrosive. Another deposition technology for severe topography uses spray technology and can be used for metal and nonmetal surfaces. The resist or polymer is modified by dilution and sprayed by a special nozzle across the wafer. Even nearly vertical sidewalls can be coated. An example is given in Fig. 21.33. A further advantage of spray coating is the reduction of material consumption. In spin coating most of the resist is spun over the edge of the wafer. Using spray coating only the wafer surface is covered with the resist. For thicker layers multiple spraying steps have to be performed. The film quality (uniformity, flatness) of sprayed resists is not as good as with spin coating because there are no centrifugal forces leveling the film. But for most of the packaging applications resists are used for etching or as plating molds and polymers are used for electrical isolation where only a given thickness has to be reached. UV exposure. The most common exposure tools for wafer bumping/wafer level packaging are mask aligners and 1X steppers (as opposed to reduction steppers that are used in the front end). Figure 21.34 shows the characteristic difference between the two exposure techniques. Mask aligners are proximity printing tools where masks and wafers are separated by an exposure gap of approximately 50 µm. Proximity printing allows even 300-mm wafers to be exposed in one shot. A mask for mask aligners is larger than the wafer and contains the full wafer layout. Typical exposure intensity ranges between 20 and 100 mW/cm2 (350 to 450 nm wavelength range). Proximity aligners offer a low-cost lithography solution for high volume production. Care has to be taken that the exposure process is optimized in a way that minimizes mask contamination such that mask cleaning is required only every few wafer lots. The full field mask layout requires a careful mask design in order to avoid run out on large wafers. 1X steppers are projection systems that image a 1:1 projection of the reticle onto the wafer. Steppers expose the wafer with multiple shots. The maximum field size is about 20 mm × 40 mm.

FIGURE 21.33 30, 35, and 40 µm line and space patterns across a 100-µm deep trench. The dark lines are photoresists. (Courtesy of Suss MicroTec.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.33

PACKAGING PACKAGING

21.33

Reticle

Projection optics

Full field mask

Exposure gap

Step-and-repeat (1X projection) Proximity printing (mask aligner)

FIGURE 21.34 Proximity printers (mask aligners) and 1X steppers are the most common exposure tools in wafer bumping.

Therefore more than 30 shots may be necessary to expose a full 200-mm wafer depending on the wafer layout. This translates into a throughput disadvantage compared to the mask aligner especially for large wafer sizes. Because of the small field size the typical exposure intensity per shot is about 1500 to 3000 mW/cm2. Mask aligners and 1X steppers use mercury short arc lamps. In order to achieve short exposure times for thick resist applications, the use of the full spectrum between approximately 350 and 450 nm is desirable. This spectral range includes the g-line (436 nm), h-line (405 nm), and i-line (365 nm) of the mercury spectrum. Depending on the process, the overlay accuracy in advanced packaging has to be between 1 and 5 µm. Mask aligners and steppers are capable of achieving this overlay accuracy. Mask designs have to be made carefully to provide the required accuracy. Most often only the layout of one chip of the wafer is available. The step-and-repeat data from the front-end manufacturing have to be taken into account. A small variation can result in run-out. GDSII is the preferred data format in packaging with the benefit of small files and hierarchal data format. Circles are reproduced by segments. The DXF is used in lots of other applications. True circles are possible but there are no standard design rules. Gerber, which is common in the PCB industry should not be used for mask designs due to the low data integrity and the resulting extremely large files. Resist develop. Most thick photoresists today use aqueous developers that translate into lower material costs than solvent-based developers (see the section “Photoresists”). The developer has to be applied at elevated temperatures to show the best efficiency and to allow short process times. Photoresists can be either developed by puddle or spray development where spray development allows better process control especially when very thick resist layers have to be developed. With spraying the mechanical pressure of the developer allows the development of structures with higher aspect ratios. Puddle develop, on the other hand, is faster and lower cost and is therefore used for thinner resists below approximately 20 µm. Plasma Processing Equipment. Plasma treatment is used for a wide range of process steps—surface preparation to enhance the adhesion, preplate resist wettability enhancement, descumming (removal of resists or polymer residues in vias or openings), resist strip, metal etch, rework, and the like. Only ceramics and copper cannot be etched in practice. In general, plasma processes modify the surface by etching or depositing materials. Therefore, this process has to be used carefully to avoid unwanted reactions. But the surface activation results are often a must for some of the process steps. Mostly RF-reactive ion etching (RIE) and microwave downstream technologies are in use for this dry etching process. The inert gas sputtering etching is used in sputtering tools for the pretreatment of surfaces prior to metal deposition. The advantage of dry etching compared to wet etching is the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.34

PACKAGING 21.34

FINAL MANUFACTURING

Cooling water channel

Gas inlet above plasma Gas region distribution

RF powered chuck with cooling loop

Chamber wafer opening

Vacuum distribution manifold

Cooling water

Typical parallel plate RIE

Wafer lift assy

Vacuum exhaust

FIGURE 21.35 Schematic drawing of RIE chamber (left) and production plasma etcher for 300-mm Panther 300 (right). (Courtesy of Matrix, Inc.)

clean nature of the process. No residual ions are left on the surface. Process control is excellent because the etching process is started and stopped by switching power. In general the material consumption is low compared to wet etching processes. RIE is based on parallel plates that are capacitively coupled. This gives a highly directional etching process with a medium power of up to 600 W. No charged ions are at the wafer surface in the case of downstream plasma. Much higher power can be achieved for isotropic etch profiles with a high etching rate. Single wafer processing is preferred for both technologies especially for wafer sizes larger than 150 mm due to uniformity issues in batch processing. In addition, wafer temperature control cannot be given in batch processing tools. An example of a machine layout is shown in Fig. 21.35. Highly reactive radicals and ions are created in the plasma. As the electron energy of the plasma used in the microelectronic industry is in the range of 2 to 10 eV, mostly dissociation reactions occur because ionization typically only starts above 10 eV. The total etching/cleaning process is controlled by the absorption of the etchant on the surface, the reaction rate at the surface, and the desorption of the products. An example of the importance of plasma processing is given for the photo-BCB process in Fig. 21.36.

FIGURE 21.36 Effect of RIE on the photo-BCB process—no descum (left), RIE with O2/CF4 (right). (Courtesy of the Dow Chemical Company.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.35

PACKAGING 21.35

PACKAGING

µm 0.29 0.15 0.00

µm 0.29 0.15 0.00

4 4 µm

µm

0

0

2 µm

4

2 µm

2

4

µm 0.29 0.15 0.00

2 0

4 2 µm

4 µm 2

0

0

0

FIGURE 21.37 Effects of RIE to photo-BCB surface (AFM)—no descum (left), RIE with 10 Vol percent SF6 (middle), RIE with 25 Vol percent SF6 (right).

A short plasma descum is necessary for the photo-BCB after cure (final polymerization) to guarantee a yield close to 100 percent. Small residues on the bottom of the vias (Fig. 21.36, left) can be easily removed by a 30-s descum (Fig. 21.36, right). A fluorine gas (CF4, SF6, or NF3) has to be added to oxygen because a pure oxygen plasma oxidizes the BCB to a SiO2-like surface due to the silicon inside the BCB backbone. This etching characteristic is also responsible for the different etching rates and the resulting surface roughness of BCB as shown in Fig. 21.37. BCB has a very smooth surface with a roughness of less than 0.8 nm. If the surface is etched by RIE with only 10 Vol percent SF6, the roughness is increased to over 20 nm. Increasing the SF6 content to 25 Vol percent reduces the roughness to less than 3 nm. Therefore, the plasma process has to be optimized not only with regard to the etching rate. The surface roughness and the resulting surface chemistry have to be monitored for a reliable build up of thin-film structures. Electroplating Systems. The basic electroplating cell consists of an anode, a cathode, a power supply, and the electrolyte. The wafer serves as the cathode and the seed layer (as part of the UBM) acts as the plating base. Two common types of plating cells are rack platers and fountain platers (Fig. 21.38). In a rack plater the wafer is vertically mounted in the electrolyte whereas in a fountain plater the wafer is horizontally mounted with the seed layer facing down. The plating speed and plating control critically depends on several factors including electrolyte composition, impurity levels, and plating current uniformity. Equipment and electrolyte maintenance are therefore important and add to the cost of plating. It is very important to constantly refresh the electrolyte near the wafer surface in order to prevent local variations of electrolyte efficiency. In a rack plater bath agitation by spray tubes is necessary. In a fountain plater it is important to constantly provide the same amount of electrolyte on each location of the wafer. This is controlled by a diffusion plate.

G C

A

B

G

D A D

E

H J

F

K

F

FIGURE 21.38 Construction schemes of the electrolytic cell of a rack plater (left) and a fountain plater (right).32 A: Anode, B: Spray Tubes, C: Shielding, D: Wafer, E: Overflow F: Immersion Heater, G: Level Switch, H: Diffusion Plate, J: Cylinder, K: Riser.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.36

PACKAGING 21.36

FINAL MANUFACTURING

Seal

Electrode

PR

Seed layer Wafer FIGURE 21.39 In a cup plating system the resist at the wafer edge needs to be removed and the electrode makes contact with the seed layer along the entire wafer perimeter. A sealing ring is attached to the resist surface to prevent the electrolyte from touching the electrode.

Among the most important parameters that influence the uniformity of plating height and solder composition as well as bump morphology is the electrical field distribution across the wafer as it defines the plating current. Simple platers often only inject the current through a few points on the wafer. This, however, does not allow good plating control especially for large wafer sizes. The alternative is to apply the voltage over many points along the wafer parameter (Fig. 21.39). In this case the photoresist is completely removed along the perimeter of the wafer (edge bead removal) and the electrode in the form of a ring is attached to the wafer. A sealing ring is put on top of the resist surface to prevent the electrode from being contaminated by the electrolyte. The current distribution has an approximately rotational symmetry but can show a radial variation. In this case the anode design in fountain platers offers another means to control the plating current uniformity by compensating for radial field variations. In addition, the ratio of open area (this is the total plated area) versus the full wafer area influences the plating current uniformity. It is important to have a uniform distribution of bumps across the wafer surface that may require the placement of bumps in some areas on the wafer without any die underneath (dummy bumps). Likewise, the precision of edge bead removal has an important influence on the plating result. Stencil Printers. Figure 21.40 shows the principal setup of a stencil or screen printer. These printers are commonly used to deposit solders onto PCBs. The technology was further developed for wafer bumping. A rigid support pallet should be used to protect the wafer. The screens are typically made by laser drilling of metal sheets or by electroforming. The printer aligns the stencil to the substrate or wafer. The printer’s alignment system should be able to recognize small fiducials on the

Squeegee

Stencil frame

Solder paste

Stencil

Filled aperture

IC metallization FIGURE 21.40

Stencil aperture

Wafer

A principal setup of stencil printing apparatus. (Courtesy of EKRA GmbH.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.37

PACKAGING PACKAGING

21.37

wafer, which can be pad corners, emblems, or other metallized features that have a good contrast to the rest of the wafer.33 Then solder paste is dispensed and a squeegee screens the paste across the stencil and into the apertures. Within seconds the paste is distributed through the stencil and thousands of pads are bumped at a time. One of the key issues is the requirement that all the paste has to be transferred from the stencil to the wafer. Any solder paste residues in the screen will reduce the final bump height uniformity. For wafer bumping photoresist stencils are often used instead of metal stencils (see Fig. 21.19) because of the fine-pitch flip-chip interconnects. Photoresist stencils take advantage of the high resolution capabilities and high overlay accuracy of thin-film technology. Then the stencil is removed followed by a reflow to form the final solder ball. The metal stencils have to be cleaned by solvents. Mostly water-soluble solder pastes are used in production. If a photoresist is used for the stencil process, the paste is partly reflowed before stripping the resist. A second reflow has to be done afterward, which requires an additional fluxing step. The stencil or screen bumping, process is limited by the layout of the chip pads that are designed mostly for wire bonding. Therefore the pads are rowed at the periphery of the die. Rectangular openings have to be designed for the stencil to maximize the amount of solder paste transferred to the solder. To calculate the size of the reflowed bump as a function of pad size and geometry, the following equation is used for a reflowed bump as a truncated sphere: p 1 V =   A ⋅ H +   ⋅ H3  2  6 where V is the solder volume, A is the pad area, and H is the bump height. The advantage of stencil printing is the wide variety of solder paste materials. It is possible to adjust the solder composition for the requirements of lead-free solders. Electroless Plating Tools. A process line for electroless Ni/Au consists of a set of wet benches. Typically, 14 tanks are necessary for full production (25 wafers at a time for a wafer size up to 200 mm and 12 wafers for the 300-mm technology). The total size is roughly 6.0 m × 1.5 m. Extra space has to be reserved at the back of the line for services like refilling or cleaning. A typical example for a manual process line is given in Fig. 21.41. Only deionized-water supply, compressed air, nitrogen, electricity, and exhaust have to be added. A robot cassette handler can be added for full automation. Monitoring of the chemical composition of the baths is a critical task for high quality. It has to be done by a manual chemical analysis or by an automatic analyzing unit. The Ni content and additives have to be added by the time of operation.

FIGURE 21.41

Plating line for e-less Ni/Au. (Courtesy of Fraunhofer IZM.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.38

PACKAGING 21.38

FINAL MANUFACTURING

TABLE 21.10

Specification of the E-less Ni/Au Process

Property Wafer material Bond pad material Pad metal thickness Passivation Residues on bond pads nonorganic organic Wafer size Wafer thickness Bond pad geometry Passivation opening Bond pad spacing Passivation overlap Wafer fabrication process Ink dots Probe marks Scribe lines Laser fuses AL fuses Poly-Si fuses

Specification Si AlSi 1%, AlSi 1%, Cu 0.5%, AlCu 2% ≥1 µm Defect-free nitride, oxide, oxinitride, polyimide, BCB <5 nm Not acceptable 100–300 mm >200 µm (>150 µm) Any (square, rectangular, round, octagonal) >40 µm >20 µm 5 µm CMOS, BiCMOS, bipolar Acceptable Stability depends on ink Acceptable Must be passivated (thermal oxide) Test structures acceptable Not acceptable Acceptable (with limitations)

Source: Courtesy of Fraunhofer IZM.

The tanks have to be cleaned by strong acids according to the utilization of the equipment. Specification of the Fraunhofer IZM process is given in Table 21.10. Control of the UBM quality is monitored by shear strength that has to be around 150 MPa (minimum 100 MPa). The Al etching process has to be restricted to less than 0.5 µm to avoid damage of the silicon devices. UBM Etch Equipment. The UBM etch process removes the UBM metallization between the bumps. For cost and technology reasons wet chemical etching is common. For a UBM stack consisting of different metal layers different etch chemistries are required for each layer. Among the requirements for the etching step are a uniform etching result, a minimum bump undercut, and the monitoring of the remaining metallization thickness in order to stop the etching process or the switching of the etch chemistry in case a layer of a UBM stack is fully removed. For the best process control, spray etchers are used either in a single wafer or batch configuration (Fig. 21.42).

FIGURE 21.42 UBM etch equipment can either be single wafer processing (left) or batch tools (middle). Spray etch equipment allow the best process control. An interface of PbSn solder bump to TiW/CrCu/Cu UBM with 1.2-µm UBM undercut (right). (Courtesy of Semitool, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.39

PACKAGING PACKAGING

21.39

It is important to design the etching process in such a way that the bump surface is not oxidized or modified in any other way. In addition, the design of the UBM stack has to take the UBM etch process into account in order to achieve reliable and good process results. Reflow Ovens. In the reflow process the deposited solder is melted and a mechanically stable interface between the solder and the terminal metal surface on the wafer (reflow after wafer bumping) and the substrate (reflow during the flip-chip assembly) is generated. Reflow after wafer bumping transforms the solder into a sphere-like shape. Like in any other soldering process, oxidation of the solder leads to an insufficient flow behavior of the liquid solder, the formation of voids, and a mechanically and electrically poor solder joint quality. The solder is therefore cleaned from oxides by either reflowing in nitrogen atmosphere and providing flux or by reflowing in a reducing atmosphere (e.g., H2 or formic acid) without flux. A new technology uses plasma-assisted reflow. The use of flux can have a detrimental effect on the formation of the solder joint or, in the case of MEMS or optoelectronic devices, can even contaminate the product. Flux-free reflow is therefore a desired option. In the case of PbSn flux-free reflow with hydrogen is only applicable to high-lead PbSn with its high reflow peak temperatures around 350°C since the reaction with hydrogen requires a certain activation energy. For eutectic PbSn solders or lead-free solders with lower melting points, flux-free reflow in reducing hydrogen atmosphere is not possible and the application of flux is required. Various furnace designs and reflow techniques exist—convection ovens with heated process gas, hotplates, or IR heaters. The oven design and heating process influence the reflow process and flux activation. A certain disadvantage of hotplates is that a controlled and reliable heating and melting of the solder can become difficult if a wafer is contaminated on its bottom side (for example, by flux) or if wafers are warped. In convection furnaces, on the other hand, the solder is heated directly by a wellcontrolled heated gas stream. With the introduction of lead-free solders with their usually higher melting temperatures compared to eutectic PbSn, it can become desirable to have means to only expose the solders to these higher temperatures while wafers or boards are exposed to lower temperatures. A combination of convection oven and IR heating might become the best solution for this requirement. The maximum reflow temperature is typically a few 10 K above the melting point of the solder, and it is important that an optimized temperature profile is maintained during the reflow process. Figure 21.43 shows a reflow furnace where a single wafer handling unit loads the wafer onto a belt that transports the wafer through the convection oven. Different sections of the furnace have different temperatures and the wafer—depending on the speed of the belt—is exposed to a certain temperature profile over time. For fine-pitch bumping, flux management and cleaning is important to avoid particle generation and to maintain a good yield. A flux management system allows the processing atmosphere to be evacuated from the process chamber with the flux still in the gaseous state. This allows the process chamber to stay clean. The remaining flux on the wafer has to be cleaned after reflow.

FIGURE 21.43 International.)

A reflow furnace with single wafer handling modules. (Courtesy of BTU

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.40

PACKAGING 21.40

FINAL MANUFACTURING

21.3.3 Materials Photoresists. Photoresists are photosensitive materials that are applied temporarily on the wafer. In most cases they serve as etch masks or plating molds. Table 21.11 summarizes the different types of photoresist materials used in wafer bumping and WLP. The base resin of positive-tone photoresists is typically Novolak whereas negative-tone resists are based on acrylate or an epoxy resin. Positivetone resists have photoactive compounds that make exposed areas soluble in a diluted alkali (base) solution such as sodium hydroxide (NaOH) or metal ion-free TMAH. A negative dry film resist is developed with an aqueous carbonate developer. These are about the lowest cost and the most environmentally friendly developer chemistries possible since most of the developer consists of water. For a negative liquid resist, aqueous-based developers as well as more expensive organic developers are used. The base chemistry of a resist, solvent, and developer is important for the configuration of coat/develop clusters as different chemistries should not be used in the same process module. Liquid photoresists—positive- and negative-tone—require a prebake step to drive the solvent out of the resist layer. The baking step can be very time consuming especially for very thick layers. Insufficient baking leads to trapped solvent in the middle of the resist layer. Especially with positivetone resists, this is detrimental to sidewall control as belly shaped resist profiles appear because the developer becomes more efficient when solvent is still present. In addition, the trapped solvent can contaminate a plating bath over time, which will deteriorate plating control. With positive-tone resists in particular it is important to carefully ramp up the baking temperature in order to avoid the induction of stress into the long cross-linked polymer molecules. Proximity hot plates are usually required to process thick positive resists. An important difference between positive- and negative-tone resists is that a positive-tone resist requires a rehydration step after baking to allow water to penetrate into the resist layer again. This is necessary because the resist will not work without sufficient water being present in the resist layer. This rehydration step can take hours for very thick layers. Most common thick photoresists are exposed by broadband (combined g, h, and i-line of the mercury spectrum). The strong absorption of the i-line in positive resists makes it difficult to achieve vertical sidewalls. The sidewall angle therefore strongly depends on the resist thickness and typically ranges from 65° to 85°, where steep angles are easier to achieve in thicker layers than in thinner ones. However, new chemically amplified positive-tone resists show near 90° sidewalls with broadband exposure as well. An important parameter to look at with regard to tool productivity is the exposure dose as it determines the exposure time and thus the throughput of the exposure tool. Here the different resist classes show very different characteristics—a dry film resist requires very low doses even for very

TABLE 21.11

Classification of Photoresists and Their Characteristics

Class

Resin/dev. chem

Pos. liquid

Exposure spectrum

Prebake

Rehydr.

Sidewall

Resol.

Novolak/ aqueous

Yes

Yes

Broadband High (chemically amplified)

Dose

65°–85° (~90°)

+

Easy

Stripping

Gold bump, mushroom solder bump, UBM

Application

Neg. liquid

Acrylate, epoxy/ aqueous, organic

Yes

No

Broadband

Medium

~90°

+

More difficult

Gold bump, in-via plated solder bump

Neg. dry film

Acrylate, epoxy/ aqueous

No

No

Broadband

Low

~90°

−

More difficult

In-via plated solder bump, photo stencil

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.41

PACKAGING PACKAGING

21.41

thick layers, while the exposure dose for a very thick positive resist is often very high. This results in very long exposure times making it difficult to use this resist class for layers thicker than 50 µm. Negative liquid resists have acceptable dose requirement even for layers thicker than 50 µm and are a good alternative to dry film resists whenever the film thickness exceeds approximately 50 µm. An advantage of positive photoresists is in the stripping of this material. Positive resists can be easily stripped using standard solvents such as NMP. Negative resists have a stronger resistance to organic solvents and require more aggressive stripping chemicals that increase costs. This requires a more careful treatment to guarantee, for instance, a good wetting behavior of the UBM during plating. Different examples of openings in photoresists with a thickness of 50 µm are shown in Fig. 21.44. From an application point of view the following trends can be observed—positive tone resists are still very popular because of their ease of use. They are often selected whenever the resist thickness is typically less than 50 µm and a near 90° sidewall angle is not a requirement. Usually positive resists are used for mushroom solder bump plating, gold bumping, rerouting, and UBM patterning (in cases where the solder is applied by stencil printing). However, since straight sidewalls are important in gold bumping, negative tone resists are increasingly used in this application. Resist layers thicker than 50 µm are necessary for in-via solder plating and photostencil printing. In most cases negative resists are used. Thick dry film resists dominate as they have been commercially available for many years. However, their limited resolution capabilities are driving the interest toward negative liquid resists for fine-pitch solder bumping. Spin-on Dielectrics (Photosensitive). Thin-film polymers have proven to be an integral material basis for many different types of advanced electronic applications. First used as IC stress buffer layers, then established for MCMs, they are now used in various new packages, especially in the field of WLP, SiP, and MEMS. The requirements for the selection of a given polymer are quite broad— high decomposition or glass temperature for the high temperature processes in packaging like solder reflow, high adhesion, high mechanical and chemical strength, excellent electrical properties, low water uptake, photosensitivity, and high yield manufacturability. Only thermosets are therefore the polymer class for packaging applications. An important process difficulty is due to the fact that these high-end thermosets are nearly insoluble in organic solvents. Therefore, prepolymers are manufactured, which have a molecular weight in the 100 thousands and are dissolved in organic solvents. These solutions are commonly called precursors and are ready for the spin-on process. The final polymerization is done on the wafer by thermal curing after photoprocessing. In addition, the selection of the optimal polymer for a given application depends not only on its physical and chemical properties and processability, but also on its intrinsic interfacial characteristics. Table 21.12 gives a selection of common types of photosensitive spin-on dielectric materials. Unlike photoresists these materials remain permanently on the wafer and act as a repassivation (buffer coat) or insulation layer for redistribution traces. Repassivation is used as additional protection of the active chip area wherever required (mechanical damages, a particles, and flux media) in order to increase the chip reliability. In the case of flip chip it also reduces the influence of underfill stress on the die surface. PI, BCB, and polybenzoxazole (PBO) are common repassivation materials

FIGURE 21.44 Examples of 50-µm thick resists—Novolak-based AZ 4620 (left), negative-type JSR THB151N (middle), dry film Dupont WPR 2000 (right).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Positive Negative Negative

HD 8000 Cardo VPA Intervia 8000

Aqueous Organic Organic Aqueous Aqueous

Positive Negative Negative Positive Positive

Aqueous

Aqueous Aqueous

Organic Organic Organic Aqueous

Negative Negative Negative Negative

PBO Photoneece BG 2400 Photoneece UR 5480 Photoneece PW 1000 Photoneece PN 1000

Sumitomo Toray

Nippon Steel Rohm and Haas

JSR

HDM

Aqueous

Positive

Organic Organic Organic Organic

Developer

Photoneece PWDC 1000 WL 5150 PI 2730 HD 4000 WLP 1200

Negative Negative Negative Negative

Photosensitivity

PI

PI

PI

Silicone PI PI Nanofilled Novolac PI Modified acrylic resin Chemical amplified resist PBO PI

PI

PI PI PI BCB

Base chemistry

2.9–3.5 3.2 3.2 2.9 2.9

320 >350 >350 >350 180–200

2.9 (1 GHz)

3.4 3.4

>350 200 175

3.2 2.9 3.2 3.8

[1 kHz– 1 MHz] 3.3 3.2 3.3 2.65 2.55 (1 GHz) 2.9

Diel. const

250 >350 >350 170

320

>350 >350 >350 210–250

[°C]

Curing T (for 1–2 h)

0.002

0.002

0.026 (1 GHz)

0.0097 0.03

0.0070 0.003 0.006 0.036

[1 kHz– 1 MHz] 0.007 0.004 0.003 0.0008 0.002 (1 GHz)

Loss factor

280

36

36

16

>350 290

55 25

58

47 80

236 16 35 51

36

27 23 40–50 45

[ppm/K]

CTE

380 255

150–200

300 180

>350 350 >210

290

>350 >350 355 >350

[°C]

Tg/decompostion T

110

130

150

100 180

122 7.5

6 170 200 75

130

170 123 150 87

[MPa]

Tensile strength

10

40

40

18 40

11 11.5

37 ? 45 7.5

40

73 8 30 8

[percent]

Elongation to break

29 14–30

2.6 18 35–37

28

40–50 28

30

[MPa]

Residual stress

3.2

3

4.2

2.5 3.9

4.5

2.5 2.5

0.16 4.7 3.5 1.6

3

2.9

2.9 3.2

[GPa]

Youngs modulus

1.5

0.3

<0.38

1.6

>1.0

1.3 1.8 0.8 <0.2

[percent]

Water uptake

20:45

Dow Corning

Asahi Dow Chemical

Probimide 7000 348 Pimel G7621 Cyclotene 4000

Trade name

Classification of Dielectrics and Their Characteristics

04/04/2005

Arch

TABLE 21.12

Geng(SMH)_CH21.qxd Page 21.42

PACKAGING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.43

PACKAGING PACKAGING

TABLE 21.13

21.43

Overview of Selected Electrolytes19 Cu electrolyte

Ni electrolyte

Contents

CuSO4, sulfonic acids, chloric acid, grain refiner and leveler, wetting agent

Ni(NH2SO3)2, boric acid, grain refiner, and wetting agent (if necessary)

Metal concentration Temperature PH value Current density Current efficiency Anode material

20g/l Cu

PbSn electrolyte

Au electrolyte

Sn electrolyte

45g/l Ni

Sn(CH3SO3)2, Pb(CH3SO3)2, methane sulfonic acid, grain refiner, wetting agent, oxidation inhibitor Total of 28g/l

(NH4)3[Au(SO3)], Sn(CH3SO3)2, ammonium sulfite, methane ammonia, organic sulfonic acid, grain refiner and grain refiner, leveler, complexing wetting agent, agents and stabilizers oxidation inhibitor 12g/l Au

20g/l Sn

25°C <1 10....30 mA/cm2

50°C 4.0 10....30 mA/cm2

25°C <1 20 mA/cm2

55°C 7.0 5....10 mA/cm2

25°C <1 7....15 mA/cm2

Nearly 100 percent

>95 percent

Nearly 100 percent

>95 percent

Nearly 100 percent

Phosphorus alloyed copper

S-activated nickel pellets

Appropriate Pb/Sn alloys

Platinumcovered titanium

Pure tin

and are used as insulation for redistribution layers or integrated passives (copper coils) as well. However, BCB has gained a certain dominance in the market for these applications. BCB and polyimides (with only a few exceptions) are negative acting materials requiring organic developers while PBOs are positive acting materials. All materials require a bake to remove solvents but no rehydration step. In some cases a post exposure bake is necessary to enhance the photoinitiated polymerization. All materials are exposed by the broadband spectrum and achieve a sidewall angle of approximately 40 to 60°. Resolution is usually not an important requirement because only vias of 20 µm or larger in diameter have to be opened over larger I/O pads.

21.3.4 Metals Sputter equipment uses sputter targets of high-purity metals. The geometrical shape of the targets has to be optimized by the equipment manufacturer and is adjusted to the electrical field of the sputter equipment. For cost-saving reasons it is important to achieve the maximum target utilization. Magnetic targets such as Ni need special tool designs. Electrolytes are aqueous solutions with dissolved metal salts and additives as shown in Table 21.13. The electrolytes are shipped as ready to use or as a set of concentrates that will be mixed and diluted on-site. Depending on the electrolyte different kinds of analyses have to be made during the operation time to monitor the composition of the electrolyte. The chemical suppliers offer application specific solutions to maintain a long lifetime of the electrolyte. Solder pastes are a mixture of small solder spheres (<150 µm), flux, and binders. They are classified according to the particle size of the solder (Table 21.14).

TABLE 21.14

Solder Paste Classes

Class

1

2

3

4

5

6

7

Solder sphere size [µm]

75–150

45–75

20–45

20–38

15–25

5–15

2–11

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.44

PACKAGING 21.44

FINAL MANUFACTURING

An additional function of the paste is the prefixing of the placed components on the substrate before reflow. The viscosity of the pastes should be between 250 and 550 Pa ⋅ s for screen printing and between 400 and 800 Pa ⋅ s for stencil printing. Underfiller. The reliability of flip chips assembled on carriers is limited mostly by the thermal fatigue lifetime of the solder joints. The CTE mismatch of the different materials generates stress at the interfaces and the solder joints. This has been getting worse by the introduction of the FC assembly on organic substrates due to the higher CTE of the PCB compared to ceramic substrates. In 1987 Nakano et al.34 published the highly positive influence of epoxy resins filled with silica dispensed between flip chips and boards. This use of underfillers opened the introduction of the FCOB concept to consumer products without the need of a first level package. The challenge for these filled polymeric materials is the combination of a fast process (i.e., enhanced capillary flow) and the final thermomechanical property mechanically interlocking a chip and a substrate. The CTE of underfillers should be close to the CTE of the solder (i.e., 23 ppm/K for eutectic PbSn) and an elastic modulus of about 10 GPa to provide an optimum solder joint creep strain relief.35 The decreasing area array pitch will reduce the gap that has to be filled. For a 100-µm pitch, the gap will be less than 50 µm. The addition of volatile additives is less favorable because this would lead to voiding and shrinkage. Most of the underfillers are based on epoxy, hardeners, and 60 to 70 percent inorganic fillers that adjust the modulus and the CTE to the required performance. Adhesion to the chip and board surface is essential to maintain the interlocking mechanism during life time. The underfiller fillet height should be at least 50 percent of the die thickness to minimize stresses. The underfiller is dispensed along the chip in L or U shape (Fig. 21.45). One side of the die has to be open during the dispensing process otherwise air would be trapped under the chip. This can be monitored by acoustic microscopy. New technologies like the deposition of underfillers before the FC assembly are under development. In this case the chip has to be held for around 100 ms in place to avoid the rebounding from the board. Unfortunately, the self-alignment feature is suppressed by these no-flow underfillers. In general the main issues for the use of underfillers is the extra process step and the time after reflow which is not needed for the assembly of other SMT components. In addition, the rework of thermoset-based underfillers is still not a practical manufacturing method. Fluxes. Fluxes are needed to remove oxides during the assembly and soldering process. In addition, the tackiness allows the placed components to be held in place before the reflow and the final joining process is completed. Fluxes can be inorganic acids, organic acids, rosins, and no-clean resins. The J-STD classification describes both flux activity and flux residues activity as follows— L = Low or no flux/flux residue activity; M = Moderate flux/flux residue activity; and H = High flux/flux residue activity. These classes are further labeled for activity or corrosiveness.

Straight line

L shape

FIGURE 21.45

U shape

Underfill dispense and crosscut of an underfilled flip chip (SEM).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.45

PACKAGING PACKAGING

21.45

21.4 CASE STUDIES 21.4.1 Pure Redistribution for WLP (BioTronik, Micro System Engineering, Fraunhofer IZM) In a joint project, Biotronik, known as one of the world’s leading companies of medical implantable devices, together with Fraunhofer IZM and TU-Berlin has proofed the application of WLP for pacemakers. Especially for medical implantable devices, the size reduction of electronic packaging is coupled with a high functionality and high reliability. Biotronik and Fraunhofer IZM jointly developed a new packaging technology for an implantable microelectronic system where all the single chip packages are WL-CSPs mounted on a 3D rigid-flex substrate.36,37 The WLPs were assembled on a two-layer rigidflex board with an automatic SMT assembly line. The fully assembled board for the pacemaker is shown in Fig. 21.46. Implantable microelectronic devices have to pass reliability tests which are comparable to automotive and space applications. In Table 21.15, the test conditions and the results are FIGURE 21.46 A fully assembled board summarized. for a pacemaker (WLP are marked with a The challenge of adapting WLP for a next generation dot). pacemaker was successfully demonstrated.

21.4.2 High-Density Multichip Module for a Pixel Detector System (ATLAS Consortium) The multichip module, which is described here, is a prototype for a pixel detector system for the large hadron collider (LHC) at CERN, Geneva. The project is part of the ATLAS experiment.38 It will study proton-proton interactions. For the pixel detector a modular system is needed that can be put together to build the large detector system. These modules are excellent examples showing the highest wiring capacity together with the FC assembly with a 50-µm pitch. A module consists of a sensor tile with an active area of 16.4 mm × 60.4 mm, 16 readout chips, each serving 24 × 160 pixel unit cells, a module controller chip, an optical transceiver, and the local signal interconnection and power distribution busses. The sensor wafer is 4 in with a thickness of 250 µm. There are 288 electronic chips on a 200-mm wafer. This extremely high wiring density that is necessary to interconnect the readout chips was achieved using a thin-film copper/photo-BCB process above the pixel array.39 The silicon diode array is used as the substrate, that is, the basic building block for the detector system. The bumping of the readout chips was done using electroplating PbSn. The bump pitch is 50 µm. All dice are then attached by flip-chip assembly to the sensor diodes and the local busses (Fig. 21.47).

TABLE 21.15

Test Conditions and Results for Implantable Medical Electronic Devices

1000 h HTOL 1000 h high temp Autoclave Temp. humidity bias AATC 1000 cycles Mechanical shock Centrifuge

at 125°C, 100 mA at 150°C 121°C, 2 atm, 168 h (1000 h 85/85 RH) (−55°C/ + 125°C) (1500 G, 0.5 ms, 6 axis) (10,000 G)

Passed Passed Passed Passed Passed Passed Passed

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.46

PACKAGING FINAL MANUFACTURING

Power/DSC flex cable with optical fibers

Active detector area with feed through elements (not shown here)

Optical package Module controller chip Front-end chips

8

9

10 11 12 13 14 15

7

6

5

MCC 4

3

2

1

0

FIGURE 21. 47 MCM-D concept for the particle detector.

Two pixel detector substrates were on each 4-in wafer. A four-layer thin-film metallization is necessary for routing the power, ground, and signal layers. Signal lines were designed in microstrip line configuration. Signal layers are bus lines for the interconnection of the readout chips. The link between silicon pixel cells and flip-chip contact pads were realized using vias of staggered and staircase type. This was only achievable by a high-density multilayer metallization. A maximum via diameter of 25 µm was allowed by the design rules (Fig. 21.48). A minimum isolation layer of 3-µm thickness between the metal layers was demanded. PhotoBCB was chosen as a dielectric because of matching physical parameters and because of its process properties. A 3-µm copper layer was electroplated for the metallization. For copper lines of width w = 20 µm, thickness t = 2.2 µm with a line spacing s = 30 µm, and a BCB dielectric thickness h = 8 µm, one computes for a microstrip line configuration a typical line capacitance of 1.2 pF/cm with a time of flight of about 55 ps/cm. The characteristic impedance is around 50 Ω and the voltage coupling to the neighbored line is estimated to be -20 dB. For a 7-cm long line, the signal attenuation is about 30 percent. The process flow of the bumping technology for electronic wafers consists of incoming inspection, sputtering/plating process including lithography and etching, bump inspection, thinning (180-µm final thickness), dicing, cleaning, flip-chip bonding, x-ray inspection, module test, and rework (in case of defective dice a rework of chips is possible). The flip-chip assembly can only be done using a bonder with a placing accuracy of close to 1 µm. A crosscut of a final module is given in Fig. 21.49. The results prove that it is possible to build high-density MCM-Ds with more than 6000 I/Os per cm2 as a multilayer BCB/Cu silicon substrate. Four via layers are needed for the feed-through connections from the sensor pad to a pad in the uppermost Cu layer (to be used for the bump connection

135 µm 50 µm

35 µm 30 µm

15 10 12

35 µm 25 µm

21.46

Bump pad Cu BCB Cu BCB Cu BCB Cu BCB Detector

FIGURE 21.48 Design of feed-through elements (left) and realization (right). (BCB was etched for visualization of the metal.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.47

PACKAGING PACKAGING

FIGURE 21.49

21.47

Crosscut of a final assembled module.

to the readout chips). As there are more than 61,000 interconnection structures with nearly 250,000 vias in a single module, a test program has been set up to determine experimentally the via yield of the thin-film multilayer and to study the procedure of flip-chip assembly onto the MCM layers. Here four 2-µm thick Cu layers separated by 5-µm thick photo-BCB layers have been deposited onto monitor sensor substrates. The vias in the uppermost BCB layer (component layer) are opened to allow the solder joining of the readout chips. Full scale modules with 16 readout chips bump bonded to the substrate have been built. From more than 1.1 million monitored vias a defect rate of less than 10−5 has been found. An important factor for such a complex module is the importance of KGD and the possibility of repair. In Fig. 21.50 the yield of modules is calculated versus the chip yield. A total module yield of only 44 percent can be achieved if the chip yield is 95 percent for this 16 chip module. 21.4.3 ELASTec Wafer Level Package (Infineon Technologies) Memory products are often considered as ideal candidates for wafer level packaging—the typical chip size and pin counts allow the use of standard low cost boards with board pitches of 0.65 mm and above. At the same time the transition to 300 mm wafers more than doubles the number of chips per wafer, which significantly reduces the cost per die of WLP. However, the demand for high second level reliability of memory die imposes challenges on WLP. WLPs as described under Sec. 21.4.1 have been mainly adopted for small die because in this case stress is low and an underfiller is

Module yield

100 80 60 40 20 0 100

65

95 90 % of good di

85

e

FIGURE 21.50

80

7 8 9 10 r 11 12 be 1413 m 15 u 16

43

of

21

e

di

N

Module yield as a function of KGD and the number of dice.5

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.48

PACKAGING 21.48

FINAL MANUFACTURING

not needed. Memory die, on the other hand, are relatively large and the small distance between chips and boards leads to increasing stress during the thermal treatment if rigid interconnect elements such as solder balls are used without underfillers. A solution for large die WLP without underfillers would not only improve product reliability but also allow another path to significantly reduce the cost of memory production—wafer level burn-in and test. Since die level burn-in and test at speed is an expensive step in memory production, the transfer to wafer level burn-in and test can reduce the overall back-end cost by approximately 50 percent. Infineon Technologies has developed a new WLP packaging platform to address these testing and second-level reliability issues.40 This Elastic Bump on Silicon Technology (ELASTec) is based on resilient interconnect elements on the wafer. These interconnect elements consist of printed silicone bumps with redistribution traces routed from the I/O pads onto the top of the silicone bumps (Fig. 21.51). The traces on the silicone bumps form a spiral pattern where the inductance increase caused by this spiral design turns out to be negligible for frequencies up to approximately 1 GHz. The redistribution traces on top of the resilient bumps have a gold finish and serve as the contact surface for tests and burn-ins and as the solder pad in the second-level assembly. The traces of the redistribution are electroplated where the geometry of the traces is defined by photolithography on a sputtered seed layer. The bump height of the ELASTec package is 170 µm to realize packages of smaller height down to 500 µm. This is a factor of two in height reduction compared to conventional interposer-based packages. Compared to conventional solder bumped WLP with ball diameters larger than 300 µm, the ELASTec package reaches a smaller package form factor at high reliability. The design of the ELASTec package has various advantages—the bumps are flexible in the z direction for reliable test contact and in the x, y direction for the compensation of thermal mismatch to the printed circuit board after the board assembly. The elasticity in the z-direction dramatically simplifies test and burn-in equipment as conventional contacts like needles, springs, and the like are not required (Fig. 21.52). Instead the wafer with the resilient bumps is pressed by a low force against a flat contactor board. Due to the Au/Au contact surfaces, these contact forces still guarantee low contact resistance and allows the use at very high frequencies (up to 10 GHz) with high reliability. Thermal and mechanical reliability tests were done on the component as well as module level. For module assembly a standard SMT process was used consisting of solder printing, pick and place for passives, and package followed by solder reflow. For good thermal behavior and as an additional mechanical protection, heat spreaders were used at component or module level. No special adaptation of the line for ELASTec was needed. The proof of the first- and second-level reliability was done under Infineon Technologies’ standard test conditions. All tests have been performed first on daisy

FIGURE 21.51 The ELASTec WLP package consists of metal traces routed on top of resilient silicone bumps. (Courtesy of Infineon Technologies.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.49

PACKAGING PACKAGING

ELASTec® WLP

Conventional WLP Pad

RDL

Chip

Solder stop

21.49

WLP built up

Pad

Chip Elastic bump

RDL

Solder ball

Low force pressing Test and burn-in contact

Only top soldering Module assembly

FIGURE 21.52 Comparison of conventional and ELASTec WLP. (Courtesy of Infineon Technologies.)

chain test vehicles to investigate the interconnection and package reliability. In a second step live components were used to proof functionality of the ELASTec package and memory module (128Mbit-based 256 MB SODIMM). All tests at the component as well as module level showed comparable or better behavior than FBGAs without failures. Tables 21.16 and 21.17 give a summary of the performed reliability tests at the component and module level, respectively. Of particular interest is the reliability at the module level during thermal cycling as this test proves the flexibility of the ELASTec bump in x,y direction. As shown in Table 21.2, the package survived the 1000 thermal cycles test with temperatures between −40 and +125°C. 21.4.4 Schott Opto-WLP A new packaging technology with a strong focus on optical applications, which is a smart combination of WLP and MEMS processing technology, has been introduced by Schott Electronic

TABLE 21.16 Summary of Reliability Tests at Component Level (Courtesy of Infineon Technologies) Test Preconditioning Pressure cooker test HAST w/o bias Thermal humidity storage High temperature storage Temperature cycling Solderability ESD ELT

Condition

Result

Shipping simulation 121°C, 2 atm, 100 percent RH, 240 h 125°C, 85 percent RH, 240°C 85°C, 85 percent RH 125°C, 1000 h −65°C/150°C, 1000 c JESD22-B102-C JESD22-A114-A

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.50

PACKAGING 21.50

FINAL MANUFACTURING

TABLE 21.17

Summary of Reliability Tests at Module Level

Test

Condition

Application test (hot/cold) Temperature cycling Temperature cycling Thermal humidity bias High temperature storage Bend test Shock test Vibration test Pinch test

Correlation 0°C/100°C, 1000 c −40°C/125°C, 1000 c 85°C, 85 percent RH, Vmax, 500 h 125°C, 1000 h JESD22-B110-(B)

Result ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

Source: Courtesy of Infineon Technologies.

Packaging. Optical packaging and most MEMS packages have to solve a very basic problem, when advanced assembly techniques should be applied to the device—the sensor surface has to interact with the environment without any restrictions caused by packaging, which at the same time is protecting the sensor device against the environment. WLP is possible if the active area of the sensor is on one side of the device, and the grid array contacts for the interconnection are placed on the bottom side of, for example, an image sensor chip. Silicon-via-contacts are the key to this approach. Standard silicon device wafers are the starting point of SCHOTT opto-WLP,41 which is schematically shown in Fig. 21.53. Those device wafers, i.e., image sensors—both CCD or CMOS—as well as surface-MEMS devices, typically have an active sensor surface on one side of a silicon substrate. In between the silicon and/or comprising this active surface, an interdielectric layer may be found, which may consist of a wide range of dielectric materials, like silicon oxide and/or silicon nitride. Standard contact pads typically made out of metals are on top of the same insulating layer. These given contact pads are directly connected by the silicon-via-contacts later in the process. That means the same pads that are used for testing or wire bonding are used for packaging as well. The first step in the SCHOTT optoWLP process is the protection of sensitive active structures by a high-quality cover glass. A specialized adhesive wafer bonding process was developed, which either performs a full area bond or enables a selective coverage of the adhesive within that bond layer. In the next step the bonded siliconglass sandwich is thinned from the silicon side (bottom side). The thickness of the silicon is reduced to about 100 µm enabling low-profile, chip-size optical packages for the devices. The actual thickness of the silicon can be adjusted according to the application of the devices—stress sensitive devices may need a very different residual silicon thickness compared to more robust sensors where a 50-µm residual silicon thickness might be preferred. A highly specialized plasma etching process is used to structure silicon. Preferably tapered sidewalls for all structures are used. The deposition of dielectric layers over silicon guarantees the electrical isolation to the subsequent redistribution process that is based on BCB/Cu or Al. After UBM deposition the wafer is ready for the balling and dicing process (Fig. 21.54).

FIGURE 21.53 Principle of opto-WLP. (Courtesy of Schott Electronic Packaging.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.51

PACKAGING PACKAGING

21.51

FIGURE 21.54 Video print of bumped CCD-WLP. (Courtesy of Schott Electronic Packaging.)

A further improvement of this packaging concept will be achieved by the use of microstructured glass. This new deposition technology will add hermetic sealant to MEMS WLP.42

21.5 OPTOELECTRONICS AND MEMS PACKAGING Optoelectronics and MEMS impose new challenges on the packaging, test, and assembly of microdevices. Typical MEMS devices include ink-jet printer heads, magnetic read/write heads, micromirror arrays, pressure and acceleration sensors, and gyroscopes. Optoelectronic systems range from discrete components such as LEDs and semiconductor laser diodes to complex modules combining active and passive optical and electronic components on one board (Fig. 21.55). Optical and mechanical functions have to be maintained by package and assembly. Chemical or biological sensors need packages that allow chemical and biological reactions of the device with the environment. All this has a big influence on the package design, material selection, and—consequently—on the manufacturing process. The existing infrastructure is used to package these devices wherever possible. However, packaging often represents a barrier that prevents new devices from being commercialized. Placement accuracy is often more critical than for pure electronic devices. Semiconductor lasers, for example, often have to be aligned to a fiber with a precision better than 1 µm in order to get

FIGURE 21.55 Optoelectronic device with active and passive optical components assembled on a silicon substrate. (Courtesy of Axun Technologies.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.52

PACKAGING 21.52

FINAL MANUFACTURING

sufficient optical coupling between both components. This can be accomplished by either passive or high-accuracy active alignment that requires different tool sets than the standard SMT assembly. The high-precision assembly of a laser diode, for example, can be accomplished by measuring the light coupling into the fiber and feeding this information back to the alignment system. Another important aspect of optoelectronic and MEMS packaging is that standard pick and place equipment can damage delicate devices with the functioning parts at its surface. For the assembly of complex modules, the possibility of bare die assembly and the self-alignment capability of flip-chip bonding make this interconnect technique attractive for optoelectronics and MEMS. Many components, however, do not allow flux reflow as flux residues can deteriorate the device performance. In addition, the metal coating of the board is often different from pure electronic products. Optoelectronics, for example, often use boards with gold pads in order to avoid corrosion and to have good electrical and thermal conductivity. Gold coatings are ideal for flux-free soldering because no oxides form on the gold surface. The different board metallization and the requirement for flux-free reflow lead the use of different bump metallurgies than in standard flip chip. When reflowing high-Sn solders on Au films, the brittle AuSn4 phase is formed during reflow as soon as sufficient Au is dissolved by the solder. An alternative is solders with low Sn content, such as Au80Sn20. AuSn bumps are extensively used in the assembly of optoelectronics since AuSn bumps are relatively hard and don’t tend to deform allowing the maintenance of a high alignment accuracy over time. The fluxfree assembly of AuSn bumps is accomplished by reflowing the solder in a reducing atmosphere. Hermetic packaging is a key requirement for most MEMS packages. Therefore the cost of packages based on expensive sealing techniques sometimes exceeds the cost of the bare MEMS device. Besides hermeticity, the controllability of the cavity ambient can be an important issue for sensors.43 For example, the time response of a microrelay depends on the ambient pressure. Wafer bonding of structured glass wafers offers the opportunity of combining low-cost WLP with a hermetic seal. Different techniques have been developed over the past few years.

REFERENCES 1. Oppermann, H., “Vorlesung: Aufbau- und Verbindungstechnik für Mikrosysteme,” TU Cottbus, 2003. 2. Jillek, L., and G. Keller, Handbuch der Leiterplattentechnik, Eugen Leuze Verlag, Germany, 2003. 3. Lau, J., and K. Liu, “Global Trends in Lead-free Soldering,” Advanced Packaging Magazine, February 2004. p. 25. 4. Grah, C., “Das Atlas Experiment und Fraunhofer IZM,” AVT Workshop TU, Berlin, April 2004. 5. Advanced IC Packaging Markets and Trends, 7th ed., Electronic Trend Publication, 2003. 6. Combs, E., “Leadless Plastic Packages, Such As the DFN and QFN, Have Inspired a Renaissance in a Mature Technology,” Chip Scale Review, Vol. 7, pp. 75–77, March 2003. 7. Iwabuchi, K., “CSP Mounting Technology,” Proceedings of SEMI Technology Symposium 1996, Chiba, Japan, 1996; Kosuga, K., “CSP Technology for Mobile Apparatuses,” Proceedings of International Symposium on Microelectronics 1997, Philadelphia, October 1997. 8. Garrou, P., “Wafer Level Packaging Has Arrived,” Semiconductor International, October 2000, p. 119. 9. Garrou, P., “Wafer Level Chip Scale Packaging (WL-CSP): An Overview,” IEEE Transactions on Advanced Packaging, p. 17, 2000. 10. Töpper, M., J. Simon, and H. Reichl, “Redistribution Technology for CSP Using Photo-BCB,” Future Fab International, p. 363, 1996. 11. Fillion, R., R. Wojnarowski, and W. Daum, “Bare Chip Test Techniques for MCM,” Proceedings of EIA/IEEE Electronic Computer Technology Conference, p. 554, Las Vegas, 1989. 12. Töpper, M., et al., “Embedding Technology—A Chip First Approach Using BCB,” Advancing Microelectronics, Vol. 24 (4), July/August 1997. 13. http://www.infineon.com/cgi/ecrm.dll/jsp/showfrontend.do?lang=EN&channel_oid=-10550.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.53

PACKAGING PACKAGING

21.53

14. Töpper, M., et al., “Thin Chip Integration (TCI-Modules)—A Novel Technique for Manufacturing Three Dimensional IC-Packages,” Proceedings of IMAPS 2000, Boston, MA, September 2000. 15. Ulrich, R., and L. Schaper, Integrated Passive Component Technology, Wiley Interscience/IEEE Press, 2003. 16. Roosmalen, A., “There Is More Than Moore,” 5th International Conference on Mechanical Simulations and Experiments in Microelectronics and MST, EuroSim, 2004. 17. Levine, B., “System-in-Package: Growing Markets, Ongoing Uncertainty,” Semiconductor International, pp. 47–61, March 2004. 18. Tummala, R., “System-on-Package Integrates Multiple Tasks,” Chip Scale Review, pp. 53–56, January/February 2004. 19. Dietrich, L., J. Wolf, O. Ehrmann, and H. Reichl, “Wafer Bumping Technologies Using Electroplating for High-Dense Chip Packaging,” Proceedings of Third International Symposium on Electronic Packaging Technology (ISPT ’98), Beijing (China), August 17–20, 1998. 20. Müller, U., Anorganische Strukturchemie, Teubner Verlag, 3, Auflage, 1996. 21. Anhöck, S., et al., “Reliability of Electroless Nickel for High Temperature Applications, International Symposium of Advanced Packaging Materials Conference, Braselton, USA, March 1999. 22. Kawanobe, T., K. Miyamoto, and Y. Inaba, “Solder Bump Fabrication by Electrochemical Method for FC Interconnection,” Proceedings of IEEE Electronics Components Conference, S. 149, May 1981. 23. Töpper, M., A. Achen, and H. Reichl, “Interfacial Adhesion Analysis of BCB/TiW/Cu/PbSn Technology in Wafer Level Packaging, Proceedings of ECTC, 2003. 24. Töpper, M., T. Stolle, and H. Reichl, “Low Cost Electroless Copper Metallization of BCB for High-Density Wiring Systems, Proceedings of the 5th International Symposium on Advanced Packaging Materials, Braselton, USA, March 1999. 25. Paik, K., R. J. Saia, and J. J. Chera, “Studies on the Surface Modification of BCB Film, Proceedings of MRS, Boston, November 1990. 26. Krause, F., et al., “Surface Modification Due to Technological Treatment Evaluated by SPM and XPS Techniques, Proceedings of MicroMat, Berlin, April 2000. 27. Chinoy, P., “Reactive Ion Etching of Benzocyclobutene Polymer Films, IEEE Transactions on Computer Packaging and Manufacturing Technology, Part C, Vol. 20 (3), pp. 199–206, 1997. 28. Zoschke, K., et al., “Thin Film Integration of Passives—Single Components, Filters, Integrated Passive Devices” Proceedings of the 2004th ECTC Conference, Las Vegas. 29. Carchon, G., et al., “Accurate Measurement and Characterization of MCM-D Integrated Passives up to 50 GHz,” Proceedings of International Conference and Exhibition on HDI and System Packaging, Denver, CO, pp. 307–312, 2000. 30. Carchon, G., et al., “Multilayer Thin Film MCM-D for the Integration of High-Performance Wireless FrontEnd Systems,” Microwave Journal, Vol. 44, pp. 96–110, 2001. 31. Daughton, W., “An Investigation of the Thickness Variation of Spun-On Thin Films Commonly Associated with the Semiconductor Industry,” Journal of Electrochemical Society, Vol. 129 (1), pp. 173–179, 1982. 32. Dietrich, L., J. Wolf, O. Ehrmann, and H. Reichl, “Wafer Bumping Technologies Using Electroplating for High-Dense Chip Packaging,” Proceedings of Third International Symposium on Electronic Packaging Technology (ISPT ’98), Beijing, China, August 17–20, 1998. 33. Schake, J., “Stencil Printing for Wafer Bumping, Semiconductor International, October 2000. 34. Nakano, F., T. Soga, and S. Amagi, “Resin Insertion Effect on Thermal Cycle Resistivity of FC Mounted LSI Devices,” Proceedings of ISHM Conference 1987, pp. 536–541, September 1987. 35. Schubert, A., et al., “Thermo-Mechanical Reliability of FC Structures Used in DCA and CSP, Proceedings of the International Symposium on Advanced Packaging Materials, Braselton, Atlanta, 1998, pp. 153–160. 36. Töpper, M., et al., “Chip Size Package—The Option of Choice for Miniaturized Medical Devices, Proceedings of IMAPS Conference, San Diego, CA, 1998. 37. Schaldach, M., et al., “State-of-the-Art Technology Development for Medical Implantable Systems, Proceedings of IMAPS’ 98, San Diego, CA, October 1998.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH21.qxd

04/04/2005

20:45

Page 21.54

PACKAGING 21.54

FINAL MANUFACTURING

38. Becks, K., et al, “A Multi-Chip Module, the Basic Building Block for Large Area Pixel Detectors, Proceedings of IEEE MCM Conference, 1996. 39. Töpper, M., et al., “Fabrication of a High-Density MCM-D for a Pixel Detector System Using a BCB/Cu/PbSn Technology,” The International Journal of Microcircuits and Electronic Packaging, Vol. 22 (4), pp. 305–311, 1999. 40. Meyer, T., and H. Hedler, “A New Approach to Wafer-Level Packaging Employs Spin-On and Printable Silicones,” Chip Scale Review, Vol. 8, pp. 65–71, July 2004. 41. Leib, J., and M. Töpper, “New Wafer-Level-Packaging Technology Using Silicon-Via-Contacts for Optical and Other Sensor Applications, Proceedings of 54th Electronic Components and Technology Conference, Las Vegas, June 2004, pp. 843–847. 42. Mund, D., and J. Leib, “Novel Microstructuring Technology for Glass on Silicon and Glass-Substrates, Proceedings of 54th Electronic Components and Technology Conference, Las Vegas, June 2004, pp. 939–942. 43. Parton, E., and H. Tilmans, “Wafer-level MEMS Packaging, Advanced Packaging Magazine, pp. 21–23, April 2004.

FURTHER READING Elshabini-Riad, A., and F. D. Barlow (eds.), Thin Film Technology Handbook, McGraw Hill, New York, 1997. Garrou, P., and I. Turlik, Multichip Module Technology Handbook, McGraw-Hill, New York, 1998. Harman, G., Wire Bonding in Microelectronics: Materials, Processes, Reliability and Yield, McGraw-Hill, New York, 1997. Hwang, J., Modern Solder Technology for Competitive Electronic Manufacturing, McGraw-Hill, New York,1996. Lau, J., Ball Grid Array Technology, McGraw-Hill, New York, 1995. Lau, J., and S. W. Ricky Lee, Chip Scale Package, McGraw-Hill, New York,1999. Messner, G., I. Turlik, J. W. Balde, and P. Garrou, Thin Film Multichip Modules, ISHM Publications, Reston, Virginia, 1992. Puttlitz, K., and P. Totta, Area Array Interconnection Handbook, Kluwer Academic Publishers, Dordrecht, Netherlands, 2001. Reichl, H., Hybridintegration, Verlag Hüthig, Heidelberg, Germany, 1988. Reichl, H., Direktmontage, Springer-Verlag, Berlin, Germany, 1998. Seraphim, D. P., R. Lasky, and Che-Yu Li, Principles of Electronic Packaging, McGraw-Hill, New York, 1989. Tummala, R., E. Rymaszewski, and A. Klopfenstein, Microelectronic Packaging Handbook, Parts 1–3, Chapman & Hall, Boca Raton, Florida, 1997.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

P

●

A

●

R

●

T

●

4

NANOTECHNOLOGY, MEMS, AND FPD

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.2

NANOTECHNOLOGY, MEMS, AND FPD

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.3

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 22

NANOTECHNOLOGY AND NANOMANUFACTURING Zhong L. Wang Georgia Institute of Technology Atlanta, Georgia

22.1 WHAT IS NANOTECHNOLOGY? In the history of industrial engineering, it is only in microelectronics that technology is characterized by size. The semiconductor industry over the last few decades has followed Moore’s law. The projections extend to the year 2012, at which time the smallest component of a device would have a linear dimension of 50 nm. However, for years beyond 2006 and device features 100 nm or smaller, the roadmap is filled with the notation “no known solution.” The semiconductor roadmap ends just short of true nanostructure devices because the principles, fabrication methods, and way of integrating devices into systems are unknown. The transition from microelectronics to nanoelectronics results in changes in fundamental physics. Nanotechnology is the second example of technology being characterized by size. How small is one nanometer? A typical width of a human hair is 50 µm; one nanometer is 50,000th of a hair width. If a golf ball is 1 nm in size, the size of the earth would be approximately 1 ft. Nanotechnology is the construction and utilization of functional structures designed from an atomic or molecular scale and with at least one characteristic dimension measured in nanometers. Such materials and systems can be rationally designed to exhibit novel and significantly improved physical, chemical, and biological properties, phenomena, and processes because of their size. When characteristic structural features are intermediate in extent between isolated atoms and bulk materials, in the range of about 1 to 100 nm, the objects often display physical attributes substantially different from those displayed by either atoms or bulk materials. Small is different! But small is not necessarily nanotechnology! We define nanomaterials by their sizes as per the aforesaid definition, but nanotechnology requires size induced unique, and/or largely improved properties. The nanoparticles suspended in a plume of smoke, for example, are nanoparticles in a size range of 50 nm, but these particles offer no beneficial properties. Therefore, the smoke particles are nanoparticles, but they are not nanotechnology. Phenomena at the nanometer scale are likely to be a completely new world. Philosophically, changing in quantity results in changing in quality. Shrinkage in the device size may lead to a fundamental change in the operation principle due to the quantum effect. In the nanoscale, many of the phenomena and properties are unscalable. The electrical conductance of a fine atom wire or a carbon nanotube,1 for example, is quantized even at room temperature, and the conductance is a constant Q = 2e2/h = 1/(12.9 kΩ), which is independent of the cross section of the nanowire and its length, provided the length is smaller than the electron mean free path for inelastic collisions. This number is the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

22.3

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.4

NANOTECHNOLOGY AND NANOMANUFACTURING 22.4

NANOTECHNOLOGY, MEMS, AND FPD

same regardless of whether the nanowire is gold, plantium, or silver. We know that metals have melting points. Bulk platinum, for example, has a melting point of 1772°C. But for 20-nm Pt nanoparticles, surface melting starts as low as 500°C. Small gold nanoparticles of 3 nm in size melt at 200°C. The properties of matter at the nanoscale may not be predictable from those observed at larger scales. Important changes in behavior are caused not only by the continuous modification of characteristics with diminishing size, but also by the emergence of totally new phenomena such as quantum size confinement, wave-like ballistic transport, and predominance of surface/interface and contact phenomena. The designed and controlled fabrication and integration of nanomaterials and nanodevices is likely to be a revolution for science and technology. Nanotechnology can provide unprecedented understanding about materials and devices, and is likely to impact many fields. By using structure at the nanoscale as a tunable physical variable, it is possible to greatly expand the range of performance of existing chemicals and materials. Patterned monolayers of molecules can function as a new generation of chemical and biological sensors. Switching devices and functional units at the nanoscale can improve computer storage and operation capacity by a factor of a million. The entirely new biological sensors are for early diagnostics and disease prevention. Nanostructured ceramics and metals have greatly improved mechanical properties. From the fundamental units of materials, all natural materials and systems establish their foundations at the nanoscale; the control of matter at atomic or molecular levels means tailoring the fundamental properties, phenomena, and processes exactly at the scale where the basic properties are initiated. Nanotechnology could impact the production of virtually every human-made object— everything from automobiles, electronics, advanced diagnostics, and surgery to advanced medicines and tissue/bone replacements. Nanotechnology will fundamentally restructure the technologies currently used for manufacturing, medicine, defense, energy production, environmental management, transportation, communication, computation, and education.

22.2 NANOTECHNOLOGY AND BIOTECHNOLOGY The development of nanotechnology is closely related to biotechnology. Nanotechnology provides the technical foundation for developing biotechnology, especially in biosensing, biodetection, drug delivery, bioimaging, and biointerfacing. Biotechnology will inspire the development of nanotechnology. Many biosystems are the most profound and intriguing nanoscale processes and phenomena, understanding which will provide the most outstanding examples and routes for developing nanotechnology. The future will be the joint exploration of nanotechnology and biotechnology.

22.3 NANOMANUFACTURING: APPROACHES AND CHALLENGES Nanomanufacturing technologies will support tailor-made products having functionally critical nanometer-scale dimensions produced using massively parallel systems or self-assembly. The current research mainly focuses on nanoscience for discovering new materials, novel phenomena, new characterization tools, and fabricating nanodevices. The future impact of nanotechnology to human civilization is manufacturing. Due to the small feature size in the nanotechnology, which limits the application of the well-established optical lithography and manipulation techniques, industrial nanomanufacturing remains a serious challenge to our technological advances. 22.3.1 Manufacturing of Nanomaterials The synthesis of nanomaterials is one of the most active fields in nanotechnology.2 There are numerous methods for synthesizing nanomaterials of various characteristics. An essential challenge in synthesis is controlling the structures at a high yield for industrial applications. Techniques are

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.5

NANOTECHNOLOGY AND NANOMANUFACTURING NANOTECHNOLOGY AND NANOMANUFACTURING

22.5

needed for atomic and molecular control of material building blocks that can be assembled, utilized, and tailored for fabricating devices of multifunctionality in a wide variety of applications. The oxide nanobelt that Zhong Lin Wang discovered can be taken as an example (Fig. 22.1). Ultralong nanobelts have been successfully synthesized for ZnO, SnO2, In2O3, CdO, Ga2O3, and PbO2, by simply evaporating the desired commercial metal oxide powders at high temperatures.3 These materials are semiconductors, with important applications in sensors and transducers. The assynthesized oxide nanobelts are pure, structurally uniform, single crystalline, and most of them are free from defects and dislocations; they have a rectangular-like cross section. The semiconducting oxide nanobelts could be doped with different elements and be used for fabricating nanosize sensors based on the characteristics of individual nanobelts, which could be potentially useful for in situ, realtime and remote detection of molecules, cancel cells or proteins based on electronic signals. The nanobelts could also be used for the fabrication of nanoscale electronic and optoelectronic devices because they are semiconductors. Recently, helical nanostructures and nanorings have been grown by rolling up single-crystal ZnO nanobelts whose flat surfaces are dominated by the c-plane polar planes (Fig. 22.2).4,5 This spiral structure is only possible when the thickness of the nanobelt is extremely small, and the helical phenomenon is attributed to a consequence of minimizing the total energy contributed by spontaneous polarization and elasticity. The polar-surface dominated ZnO nanobelts are likely to be an ideal system for understanding piezoelectricity and polarization induced ferroelectricity at nanoscale; and they could have applications as one-dimensional nanoscale sensors, transducers, and resonators. Nanowires and nanobelts have been synthesized for a wide range of materials, and they are the forefront research topics in nanotechnology today.6,7 Field effect transistors (FETs) have been fabricated using individual nanobelts (Fig. 22.3).8 The principle of this device is that controlling the gate voltage would control the current flowing from the source to the drain. The conductivity of a nanobelt can be tuned by controlling its surface and volume oxygen deficiency. Before electrical measurement, SnO2 nanobelts are annealed in a 1-atm oxygen environment at 800°C for 2 h. Without this treatment, the as-produced nanobelts exhibit no measurable conductivity for source-drain biases from −10 to 10 V and for gate biases from −20 to 20 V, while after this treatment the SnO2 nanobelts exhibit considerable conductivity. By further annealing of the devices at lower temperatures in vacuum, oxygen, or ambient, the electrical properties of the nanobelts can be tuned. After annealing of the SnO2 devices in vacuum at 200°C, the nanobelt conductivity is observed to increase along with an associated negative shift in the gate-threshold voltage. Smaller, additional

FIGURE 22.1 Transmission electron microscopy image of semiconducting zinc oxide nanobelts of width 100 to 200 nm, thickness approximately 50 nm, and lengths up to a few hundreds of micrometers for applications in sensors, piezoelectric transducers, and optoelectronic devices.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.6

NANOTECHNOLOGY AND NANOMANUFACTURING NANOTECHNOLOGY, MEMS, AND FPD

FIGURE 22.2 Scanning electron microscopy images of piezoelectric single-crystal zinc oxide (a) nanosprings and nanohelicals, (b) seamless perfect nanorings. These structures have potential applications as sensors, resonators, and transducers in biosensing and nanoelectronics.

increases in conductivity are observed after additional vacuum anneals. Eventually, the nanobelt behaves like a metal with the gate field being unable to affect the current flowing through the device. The strong dependence of the conductance on the oxygen deficiency in nanobelts is an important characteristic of the functional oxide, using which one is capable of tuning and controlling the electrical properties of the nanodevice. 10−6

10−7 Source-drain current A

22.6

10−8

10−9 250°C anneal in vacuum 200°C anneal in vacuum vacuum air 200°C anneal in air Vds = 50, 100, 150, 200 mV

10−10 10−11 −20

−15

−10

−5 0 5 Backgate potential V

10

15

FIGURE 22.3 FET device made using a single nanobelt, as shown in the inset. Source-drain current versus gate bias for an SnO2 FET after various treatments measured in this order—air, vacuum, 200°C vacuum anneal, 250°C vacuum anneal, 200°C air anneal.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.7

NANOTECHNOLOGY AND NANOMANUFACTURING NANOTECHNOLOGY AND NANOMANUFACTURING

22.7

22.3.2 New Tools for Characterizing the Performance and Properties of Nanostructures The property characterization of nanomaterials is challenged by the small size of the structure because of the difficulties in manipulation. New tools and approaches must be developed to meet new challenges. Due to the highly size and structure selectivity of nanomaterials, their physical properties could be quite diverse, depending on their atomic-scale structure, size, and chemistry. Characterizing the mechanical properties of individual nanotubes, for example, is a challenge to many existing testing and measuring techniques because of the following constraints. First, the size (diameter and length) is rather small, prohibiting the application of well-established testing techniques. Tensile and creep testing require that the size of the sample be sufficiently large to be clamped rigidly by the sample holder without sliding. This is impossible for one-dimensional nanomaterials using conventional means. Secondly, the small size of the nanostructure makes their manipulation rather difficult, and specialized techniques are needed for picking up and installing individual nanostructures. Therefore, new methods and methodologies must be developed to quantify the properties of individual nanostructures. In situ transmission electron microscopy (TEM) technique has been developed for measuring the modulus of individual carbon nanotubes. The technique is powerful in a way that it can directly correlate the atomic-scale microstructure of the carbon nanotube with its physical properties, providing a one-to-one correspondence in structure-property characterization. To carry out the property measurement of a nanotube, a specimen holder for a TEM was built for applying a voltage across a nanotube and its counter electrode .9 Static and dynamic properties of the nanotubes can be obtained by applying controllable static and alternating electric fields. To measure the bending modulus of a carbon nanotube, an oscillating voltage is applied on the nanotube with the ability to tune the frequency of the applied voltage. Resonance can be induced in carbon nanotubes by tuning the frequency (Fig. 22.4), from which the bending modulus can be derived.

FIGURE 22.4 Nanoscale measurement of the mechanical property of individual carbon nanotubes. (a) A carbon nanotube at stationary, (b) the first resonance mode of the carbon nanotube (frequency f = 1.21 MHz), (c) the second resonance mode of the nanotube ( f = 5.06 MHz). The bending modulus of the nanotube is derived from the experimentally measured resonance frequency.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.8

NANOTECHNOLOGY AND NANOMANUFACTURING 22.8

NANOTECHNOLOGY, MEMS, AND FPD

22.3.3 Large-Scale Manipulation and Self-Assembly Manipulation of nanostructures relies on scanning probe microscopy. Using a fine tip, atoms, nanoparticles, or nanowires can be manipulated for a variety of applications. This type of approach is outstanding for scientific research. For manufacturing, an array of scanning tips, if synchronized, may be used for achieving the “atom-by-atom” engineering. But the building rate is rather slow. If a device has a feature size of 5 nm and the frequency with which a scanning tip can move atoms is 109 atom/s, it will take about 6 months to build 1012 devices on an 8-in wafer. The ultimate solution is self-assembly. Like many biological systems, self-assembly is the most fundamental process for forming a functional and living structure. The genetic codes and sequence built in a biosystem guide and control the self-assembling process. To meet the need of future manufacturing needs, designed and controlled selfassembly is a possible solution. Here we use the self-assembly of magnetic nanoparticles for achieving ultrahigh memory density as an example (Fig. 22.5).10 Size and shape selected nanocrystals behave like molecular matter that can be used as fundamental building blocks for constructing nanocrystal assembled superlattices. Self-assembled arrays involve self-organization into monolayers, thin films, and superlattices of size-selected nanocrystals encapsulated in a protective compact organic coating .11 Nanocrystals are the hard cores that preserve the ordering at the atomic scale; the organic molecules adsorbed on their surfaces serve as the interparticle molecular bonds and as protection for the particles in order to avoid direct core contact with a consequence of coalescing. The interparticle interaction can be changed via control over the length of the molecular chains. Quantum transitions and insulator to conductor transition could be introduced, resulting in tunable electronic, optical, FIGURE 22.5 Self-assembly of cobalt and transport properties. nanoparticles into ordered arrays. The The growth of patterned and aligned one-dimensional cobalt particles are passivated by surfactants and they are aligned due to the internanostructures has immense possibilities for applications in action between the surfactants. The size of sensing, optoelectronics, and field emission. Using a vaporthe particle is 11 nm. This type of structure liquid-solid (VLS) process and the epitaxial orientation relahas applications for ultrahigh density data tionship between the nanostructure and the substrate, aligned storage. and patterned ZnO rods have been grown on a solid substrate12 (Fig. 22.6a). The growth combines the self-assemblybased mask technique using photonic crystal with the surface epitaxial approach. Patterned growth of carbon nanotubes has been accomplished by using a patterned substrate with designed distribution of metallic particles such as Fe or Ni (Fig. 22.6b). These approaches combine lithiographic techniques with self-assembled nanomaterials growth, opening the possibility of creating patterned one-dimensional nanostructures for applications as sensor arrays, piezoelectric antenna arrays, optoelectronic devices, and interconnects. 22.3.4 Large-scale Parallel Device Fabrication and System Integration System integration involves at least an integration of numerous functional materials and components for achieving a complex, preprogrammed action. This involves patterned materials growth on a designed substrate, large-scale, parallel integration of nanowires, nanoparticles, and functional groups, interconnection among the components, and defect tolerated path design following neuron networks. A wide range of novel approaches has been developed for the fabrication of single nanodevices. Nanomanufacturing requires a simultaneous, parallel fabrication of a large amount of nanodevices under precisely controlled conditions and repeatability. This remains a major challenge to the development of nanotechnology, especially for nanoelectronics. A possible solution is to

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.9

NANOTECHNOLOGY AND NANOMANUFACTURING NANOTECHNOLOGY AND NANOMANUFACTURING

Polar molecular patterns

22.9

Nonpolar region

Substrate

Surface functionalization SWCNT suspension

SWCNT self-assembly

0 FIGURE 22.6 Growth of patterned and aligned (a) ZnO nanorods, (b) carbon nanotubes, showing the potential of building hierarchical structures using nanowires and nanotubes. (Courtesy of Dr. Liming Dai, University of Akron.)

µm

30

FIGURE 22.7 Large-scale integration of singlewalled carbon nanotubes (SWNT) with patterns designed by mask technology through substrate patterning, surface functionalization, and solution-based manipulation. (Courtesy of Dr. S. Hong, Florida State University.)

integrate patterns produced by a lithographic technique with a self-assembly process. Self-assembly of single-walled carbon nanotubes is an example.13 By functionalizing the substrate produced by the lithographic technique, so that individual carbon nanotubes selectively recognize the locations for self-assemble on the substrate following specific patterns, it is possible to mass-produce carbon nanotube-based circuit structures (Fig. 22.7). To achieve the process, the substrate is coated with patterns of organic molecules using techniques such as dip-pen nanolithography and microcontact stamping. Two surface regions are produced—one patterned with polar chemical groups such as amino or carboxyl and the second coated with nonpolar groups such as methyl. A suspension of single-walled carbon nanotubes is then added—the nanotubes are attracted to the polar regions and self-assembled to form predesigned structures. Millions of individual nanotubes have been patterned on stamp-generated microscale patterns, covering areas of about 1 cm2, on gold. 22.3.5 Integrating Nano-to-millimeter Multilength-scale Manufacturing Technologies Over the next decade, major industrial and scientific trends that emerged during the 1990s will influence not only how manufacturing will be done, but also what is manufactured. The size of many manufactured goods continues to decrease, resulting in ultraminiature electronic devices and new hybrid technologies. For example, microelectromechanical system (MEMS) devices integrate physical, chemical, and even biological processes in micro- and millimeter-scale technology packages. MEMS devices now are used in many sectors—information technology, medicine and health, aerospace, automotive, environment, and energy to name a few.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.10

NANOTECHNOLOGY AND NANOMANUFACTURING 22.10

NANOTECHNOLOGY, MEMS, AND FPD

To p

do wn

: sy

100

ste

m

en

Device size (nm)

gin

ee

rin

g

Nanotechnology Self-assembly genetic engineered manufacturing

50

eer

r

ula

lec

o ic/m

in eng

ing

tom

p: a

u ttom

Bo

Time

FIGURE 22.8 Nanotechnology is an integration of top down engineering systems with bottom up atom-by-atom engineering, resulting in a complex, multifunctional, intelligent and robust system.

The future relies on the integration of nanotechnology with the current existing technology. The challenge remains in integrating nanotechnology with microelectronics-based technology. The nanometer scale components have to be connected with micrometer and millimeter scale components to communicate with the real world. This requires an integration of not only the technologies covering nano-to-millimeter multilength-scales, but also the physics and chemistry covering the entire length scale. We are facing the merging of quantum mechanics and classical mechanics. Any ultrasmall components have to be connected with the real world. The goals should be on how to use nanotechnology to make microtechnology more efficient, multifunctional, much improved, faster, smaller, more intelligent, and achieve the impossible. Nanotechnology can come to life if we can achieve the integration of nanoscale building blocks or materials with lithographically produced structures through self-assembly and genetic-engineered growth (Fig. 22.8). The true revolution of nanotechnology starts once this integration is implemented. 22.3.6 Bioinspired Manufacturing As for atomic and molecular control and self-assembly, biological systems are the most extraordinary examples, which have been most precise, most efficient, and most complex in assembling life species for billions of years. The biological system is an ideal and perfect model for humans to learn how to make a system. Biological engineering is an emerging technology paradigm capable of enabling revolutionary advances in the fabrication of micro- or nanostructured materials and devices. Interface with bionanostructures and bioinspired structures to produce multifunctional and adaptive nanostructures is a future direction of nanomanufacturing. Biological organisms exhibit unprecedented control at the micro- and nanoscales, including: • Direct three-dimensional self-assembly of micro- or nanostructures (e.g., fibers, tubes, and capsules) • Precise genetic control over micro- or nanoscale shapes and features • Highly selective chemical separation or precipitation (e.g., biomolecular agents can localize the precipitation of solids with tailored functionalities—optical, chemical, mechanical, and the like) • Massively parallel replication at ambient conditions (low-cost, environment-friendly processing) Figure 22.9a shows silica-based nanowires grown by Zhong Lin Wang using a solid-vapor phase process.14 In nature, silica-based diatoms can exhibit unique and beautiful shapes, as shown Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.11

NANOTECHNOLOGY AND NANOMANUFACTURING NANOTECHNOLOGY AND NANOMANUFACTURING

22.11

FIGURE 22.9 (a) Silica nanowire arrays synthesized by a solid-vapor process, (b) silica-based diatom structures formed in nature through genetic engineering.

in Fig. 22.9b.15 The difference between the two cases is that the man-made nanomaterial has relatively poorer reproducibility and controllability, but the genetic-engineered natural material has precise reproducibility and has been produced in huge amounts. Nature is the best example of nanomaterials manufacturing. The design and manufacturing of bioinspired materials are being realized in a number of ways. The controlled shapes and fine features of lignocellulosic structures may be utilized to generate new, high-value-added ceramic-, metal-, or polymer-based products.16 Natural or genetically modified ligno-cellulosic structures may be cultured, and the structures can be chemically converted into new materials without a loss of shape or fine features. 22.3.7 Building Nanomanufacturing Standards Nanomanufacturing needs the measurements and standards required to achieve effective and validated nanoscale product and process performance. This challenge is mainly in the following three directions: Atomic-scale manufacturing: Developing and assembling the technologies required to fabricate standards that are atomically precise. This will include work directed at solving artifact integrity, precision placement, dimensional metrology, and manufacturing issues. Molecular-scale manipulation and assembly: Identifying and addressing the fundamental measurement, control, and standard issues related to the manipulation and assembly of micro- or nanoscale devices using optical, physical, and/or chemical methods. This entails building the manipulation technology and using it to understand and address the measurement issues that arise when assembling devices at the micro- or nanoscale level. Micro-to-millimeter scale manufacturing technologies: Developing the technologies required to position, manipulate, assemble, and manufacture across nm-to-mm multilength scales.

22.4 NANOMANUFACTURING—GOING BEYOND THE ENGINEERING PROCESS Traditionally, manufacturing is attributed to the engineering field. For nanomanufacturing, we must go beyond engineering. Once we approach the atomic-scale precision and control, fundamental physics and chemistry have to be enrolled and correctly understood. Nanoscale manufacturing is Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.12

NANOTECHNOLOGY AND NANOMANUFACTURING 22.12

NANOTECHNOLOGY, MEMS, AND FPD

multidisciplinary and cross field, involving but not limited to mechanics, electrical engineering, physics, chemistry, biology, and biomedical engineering. The future view of nanomanufacturing is the integration of engineering, science, and biology. This complex task requires not only innovative research and development themes, but also a new education system for training future scientists and engineers. To many people, nanotechnology may be understood as a process of ultraminiaturization. In fact, the trend in product miniaturization will require new process measurement and control systems that can span across millimeter-, micrometer-, and nanometer-size scales while accounting for the associated physics that govern the device and environment interaction at each specific size scale. This will require new standardized architecture definitions that support multiple physics-based models and new computational representations that allow for seamless transition and traversing through these various models. Nanotechnology is much more than a miniaturization. The future advance from microelectronics to nanoelectronics is not just in making the line thinner and thinner and approaching 10 nm, but possibly a change in materials system and approach. Steel was the most important material in the first industrial revolution, silicon is the most important material for the second industrial revolution, the question for us now is what will be the material for the third industrial revolution?

ACKNOWLEDGMENT The results reviewed in this paper were partially contributed from my group members and collaborators: Xiang Yang Kong, Ph. Avouris, and Shouheng Sun. Research supported by NSF, NASA, and DARPA.

REFERENCES 1. Frank, S., P. Poncharal, Z .L. Wang, and W. A. De Heer, “Carbon Nanotube Quantum Resistors,” Science, Vol. 280: pp. 1744–1746 (1998). 2. Wang, Z. L., Y. Liu, and Z. Zhang (eds.), Handbook of Nanophase and Nanostructured Materials, Vol. I–IV, Kluwer Academic Publishers–Tsinghua Univ. Press, New York (2002). 3. Pan, Z., Z. R. Dai, and Z. L. Wang, “Nanobelts of Semiconducting Oxides,” Science, Vol. 291: pp. 1947–1949 (2001). 4. Kong, X. Y., and Z. L. Wang, “Spontaneous Polarization and Helical Nanosprings of Piezoelectric Nanobelts,” Nano Letters, Vol. 3: pp. 1625–1631 (2003). 5. Kong, X., Y. Ding, R. S. Yang, and Z. L. Wang “Single-Crystal Nanorings Formed by Epitaxial Self-Coiling of Polar-Nanobelts,” Science, Vol. 303: pp. 1348–1351 (2004). 6. Wang, Z. L. (ed.), Nanowires and Nanobelts—Materials, Properties and Devices; Vol. I: Metal and Semiconductor Nanowires, Kluwer Academic Publishers, New York (2003). 7. Wang, Z. L. (ed.), Nanowires and Nanobelts—Materials, Properties and Devices; Vol. II: Nanowires and Nanobelts of Functional Materials, Kluwer Academic Publishers, New York (2003). 8. Arnold, M., P. Avouris, Z. W. Pan, and Z. L. Wang, “Field-Effect Transistors Based on Single Semiconducting Oxides Nanobelts,” J. Phys. Chem. B, Vol. 107: pp. 659–663 (2003). 9. Wang, Z. L., “New Developments in Transmission Electron Microscopy for Nanotechnology,” Adv. Mater., Vol. 15: pp. 1497–1514 (2003). 10. Sun, S., C. B. Murray, D. Weller, L. Folks, and A. Moser, “Monodisperse FePt Nanoparticles and Ferromagnetic FePt Nanocrystal Superlattices,” Science, Vol. 287: pp. 1989–1992 (2000). 11. Zhang, J., Z. L. Wang, J. Liu, S. W. Chen, and G. Y. Liu, Self-Assembled Nanostructures, Kluwer Academic Publishers, New York (2002). 12. Wang, X. D., C., J. Summers, and Z. L. Wang, “Large-Scale Hexagonal-Patterned Growth of Aligned ZnO Nanorods for Nano-Optoelectronics and Nanosensor Arrays,” Nano Letters, Vol. 3: pp. 423–426 (2004).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.13

NANOTECHNOLOGY AND NANOMANUFACTURING NANOTECHNOLOGY AND NANOMANUFACTURING

22.13

13. Rao, S., L. Huang, W. Setyawan, and S. H. Hong, “Large-Scale Assembly of Carbon Nanotubes,” Nature, Vol. 425: pp. 36–37 (2003). 14. Pan, Z. W., Z. R. Dai, C. Ma, and Z. L. Wang, “Molten Gallium as A Catalyst for the Large-Scale Growth of Highly Aligned Silica Nanowires,” J. Am. Chem. Soc., Vol. 124 (8): pp. 1817–1822 (2002). 15. Round, F., R. M. Crawford, and D. G. Mann, The Diatoms: Biology and Morphology of the Genera, Cambridge University Press, Cambridge (1990). 16. Sandhage, K. H., M. B. Dickerson, P. M. Huseman, M. A. Caranna, J. D. Clifton, T. A. Bull, T. J. Heibel, W. R. Overton, and M. E. A. Schoenwaelder, “Novel, Bioclastic Route to Self-Assembled, 3D, Chemically Tailored Meso/Nanostructures: Shape-Preserving Reactive Conversion of Biosilica (Diatom) Microshells,” Advanced Materials, Vol. 14: p. 429 (2002).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH22.qxd

04/04/2005

20:47

Page 22.14

NANOTECHNOLOGY AND NANOMANUFACTURING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 23

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS Michael A. Huff MEMS and Nanotechnology Exchange Reston, Virginia

23.1 INTRODUCTION 23.1.1 The Definition of MEMS, Microsystems Technology, and Micromachining Microelectromechanical systems (MEMS) is a technology that in its most general form can be defined as miniaturized mechanical structures and devices that are made using the techniques of micro- and nanofabrication. The critical physical dimensions of MEMS devices can vary from well below 1 µm at the lower end of the dimensional spectrum all the way to several millimeters for larger components. Likewise, the types of devices encompassed by MEMS can vary from relatively simple structures wherein there are no mechanically moving elements to extremely complex electromechanical systems with multiple moving elements under the control of microelectronics integrated into the same silicon substrate. Obviously, the one main criterion of MEMS is that there are at least some elements on the substrate having some sort of mechanical functionality whether or not these elements can move. The term used to define MEMS even varies in different parts of the world. While in the United States they are predominantly called MEMS, Europe tends to call them microsystems technology (MST) and Japan mostly uses the term micromachined devices. For the sake of simplicity, we will limit ourselves to MEMS, which will be used exclusively throughout this chapter. Common elements of MEMS are miniaturized sensors and actuators that are frequently called microsensors and microactuators. Both these elements are properly categorized as transducers that are devices that convert energy from one form to another. In the case of microsensors, the device typically converts a measured mechanical signal into an electrical signal. Over the past several decades MEMS researchers and developers have demonstrated an extremely large number of microsensors for almost every possible sensing modality including temperature, pressure, inertial forces, chemical species, magnetic fields, radiation, and the like. Remarkably many of these micromachined sensors have demonstrated performances exceeding those of their macroscale counterparts. That is, the micromachined version of, for example, a pressure transducer, usually outperforms a pressure sensor made using the most precise macroscale level machining techniques. Not only is the performance of MEMS devices exceptional, but their method of production leverages the same batch fabrication techniques used in the integrated circuit (IC) industry—which can of course translate

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

23.1

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.2

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.2

NANOTECHNOLOGY, MEMS, AND FPD

into low per-device production costs, as well as many other benefits. Consequently, silicon-based discrete microsensors were quickly commercially exploited and the market for these devices continues to grow at a rapid rate. More recently, the MEMS research and development community has demonstrated a number of microactuators including microvalves for the control of gas and liquid flows, optical switches and mirrors to redirect or modulate light beams, independently controlled micromirror arrays for displays, microresonators for a number of different applications, micropumps to develop positive fluid pressures, microflaps to modulate airstreams on airfoils, as well as many others. Surprisingly, even though these microactuators are extremely small, they frequently can cause effects at the macroscale level, that is, these tiny actuators can perform mechanical feats far larger than their size would imply. For example, researchers have located small microactuators on the leading edge of airfoils of an aircraft and have been able to steer this aircraft using only these microminiaturized devices.1 Furthermore, the flight capabilities of this MEMS-instrumented aircraft frequently far exceeded any expectations— the MEMS-equipped aircraft at a high velocity was able to completely reverse its direction in a turning radius of nearly one wing radius! The real potential of MEMS starts to become realized when these miniaturized sensors, actuators, and structures are all merged onto a common silicon substrate along with integrated circuits. While this is the future trend of MEMS technology, the present state-of-the-art is more modest and usually involves a single discrete microsensor, a single discrete microactuator, a single microsensor integrated with electronics, a multiplicity of essential identical microsensors integrated with electronics, a single microactuator integrated with electronics, or a multiplicity of essential identical microactuators integrated with electronics. However, in the future as MEMS fabrication methods advance, the promise is enormous design freedom wherein any type of microsensor and microactuator can be merged with microelectronics onto a single substrate. 23.1.2 The Importance of MEMS There are many beneficial attributes of MEMS technology. First, MEMS are made using integrated circuit-like processes and this enables the ability to integrate multiple functionalities onto a single microchip. The ability to integrate miniaturized sensors, actuators, and structures along with microelectronics has far-reaching implications in countless products and applications. Second, MEMS borrows many of the production techniques of batch fabrication from the integrated circuit industry and therefore, the per-unit device or microchip cost of complex miniaturized electromechanical systems can be radically reduced—similar to the per-die cost reductions commonly seen in the IC industry. Although the cost of the production equipment and each wafer can be relatively high, the fact that this cost can be spread over many die in batch fabrication production can drastically lower the per-part cost. Third, integrated circuit fabrication techniques coupled with the tremendous advantages of silicon and many other thin-film materials in mechanical applications allow the reliability of miniaturized electromechanical systems to be radically improved. It is well known that the most expensive and unreliable components of a conventional macroscale control system are the sensors and actuators. It is expected that as these miniaturized sensors and actuators are integrated onto a single microchip with electronics, we will see similar improvements in system reliability such as we have experienced in the transition from discrete electronics on printed circuit boards to integrated circuits. The lower cost of these miniaturized electromechanical systems also allows them to be easily and massively deployed and more easily and inexpensively maintained and replaced as needed. Fourth, miniaturization of microsystems enables many benefits including increased portability, lower power consumption, and the ability to place radically more functionality in a small amount of space and without any increase in weight. Fifth, the ability to make the signal paths smaller and place radically more functionality in a small amount of space allows the overall performance of electromechanical systems to be enormously improved. In short, MEMS as a technology translates into products that have lower cost, higher functionality, improved reliability, and increased performance. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.3

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.3

23.1.3 MEMS Markets Presently, the largest market drivers for the MEMS industry include silicon-based pressure sensors, crash air-bag sensors, digital light processors (DLP) for projectors, optomechanical switches for alloptical networks, and ink-jet cartridges for printers. Because of these success stories and the applicability of this technology in so many other products, the market potential for MEMS is very promising. Since MEMS technology leverages off the enormous capital investment of IC technology, its growth is expected to continue to be rapid for the foreseeable future. Already in the industrial sector MEMS devices are emerging as product performance differentiators in numerous markets. Recent market research by In-Stat/MDR has projected that the MEMS device industry will continue to grow from a world-wide component market size 1.1-billion units in 2003, to 2-billion units market in 2008. Likewise, revenues are predicted to increase from $5.3 billion in 2003 to $9.9 billion in 2008.2 Several other market research studies have projected even higher growth. In addition to the sales of MEMS components themselves, equally important is the fact that these MEMS devices enable an additional $100 billion annual market in new or improved industrial and medical systems. The application areas considered in these studies have been typically restricted to pressure sensors, inertial sensors, fluid regulation and control, optical switching, analytical instruments, and mass data storage. Since MEMS is a nascent and highly synergistic technology, one can expect many new applications to emerge, expanding the markets beyond that which are currently identified. MEMS is an extremely important technology that has a very promising future.3,4

23.2 TECHNOLOGY FUNDAMENTALS OF MEMS 23.2.1 Microsensors Technology Many different types of sensors have been demonstrated using micromachined devices including pressure, acoustic, temperature (including infrared focal plane arrays), inertia (including acceleration and rate rotation sensors), magnetic field (Hall, magnetoresistive, and magnetotransistors), force (including tactile), strain, optical, radiation, and chemical and biological sensors.5 Sensors are transducers that convert one form of energy, such as mechanical force, to another, usually an electrical signal. There are several basic physical principles by which sensors function including resistive, magnetic, photoconductive, piezoresistive, piezoelectric, thermocouples and thermopiles, diodes, and capacitive. All of these sensing principles have been successfully demonstrated in MEMS devices. There are far too many variations of MEMS sensors to review even a fraction of those reported in the literature and therefore we will review only a few of the more important examples. The reader is referred to Refs. 5, 6, and 7 for more information. A piezoresistive material is one in which the resistance is influenced by applied mechanical strains. This phenomenon is most prominent in semiconductors where the strain induces changes in the electronic band structure of the material thereby making the carrier scattering rates dependent on the direction of transport. This effect can be used to make a variety of sensors by placing the piezoresistive elements at a position where the strain is maximized. A useful quality factor of peizoresistive materials is the gauge factor that is given by the normalized change in resistance divided by the strain. Silicon has a very high gauge factor approaching 200 in some special configurations. In comparison, metal resistors typically have gauge factors of 2 to 5. Piezoresistors are used primarily as strain measurement sensors wherein the resistor (strain sensing element) is placed on a compliant surface or structure such as illustrated in Fig. 23.1. Note that micromachining allows the substrate to be selectively removed to reduce the stiffness in the sensing region of the device. Capacitive sensing is very commonly utilized in MEMS sensors due to its inherent simplicity. In general the capacitance of a two-terminal device is given by C=

( e o e r A) d

(Farads)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.4

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.4

NANOTECHNOLOGY, MEMS, AND FPD

Diffused resistors

Diffused resistor Proof mass

Pressure sensor

Accelerometer

FIGURE 23.1 Two types of MEMS silicon sensors made using the piezoresistive effect in semiconductors.

where eo = dielectric constant of free space er = relative dielectric constant of any material between the electrodes A = area of the capacitor d = separation of the electrodes In general, capacitors can be used as sensors in five different ways as shown in Fig. 23.2—varying the distance between electrodes (a), varying the position of the center electrode relative to two outer electrodes giving a differential measurement (b), varying the overlap between electrodes (c), varying the differential overlap between electrodes (d), and varying the position of the dielectric in the space between electrodes. As an example of how a capacitive structure can be used to implement an accelerometer, see Fig. 23.3 wherein a pair of electrodes are separated by a distance that can change as the compliant cantilever is deflected under acceleration loading in the normal direction to the device. Another widely used physical phenomenon for making sensors in MEMS is the piezoelectric property of some materials. Piezoelectricity is when a mechanical strain produces an electrical polarization (i.e., voltage potential) in the material. Likewise an applied electrical field will also induce a mechanical strain in the material. The first effect is primarily used for sensors while the second is usually employed for actuators. Silicon and germanium are centrosymmetric crystals and therefore display no piezoelectric effect (unless strain induced). Other materials that lack a center of symmetry, such as quartz, lead zirconate titanate (PZT), or zinc oxide (ZnO) are commonly used in MEMS. The latter two can be deposited in thin-film form on silicon. 23.2.2 Microactuator Technology A variety of different basic principles are used to implement MEMS actuators including electrostatic, piezoelectric, magnetic, magnetostrictive, bimetallic, and shape-memory alloy. Each of these has its respective advantages and disadvantages and therefore careful consideration to the specific application requirements must be part of the selection process. We shall review a few of the more popular methods for MEMS microactuators herein. The reader is referred to Ref. 5 for a more comprehensive review. Electrostatic actuation is based on the mutual attraction of two oppositely charged plates. The force F generated between the plates under the application of a voltage potential V is given by F=

1 V (e o e r A)  d 2

2

d

(a)

d

d

d

FIGURE 23.2 element.

d

(b)

(c)

(d )

(e)

Different configuration to use a capacitor as a sensing

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.5

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.5

Direction of acceleration

Proof mass

FIGURE 23.3 accelerometer.

Illustration of an MEMS capacitive-based

where eo = permittivity of free space er = relative permittivity of a dielectric A = area of the plates V = applied voltage potential on the plates d = separation between the plates There are some inherent advantages of electrostatic microactuators that make them attractive and popular for MEMS devices including—they are easy to fabricate and integrate with electronics, they have very low power consumption during operation, and they can exhibit very high mechanical bandwidths. Some of the disadvantages of electrostatic actuators is that the force is nonlinear with displacement and applied voltage, the resultant force is relatively small, and the operating voltages can be relatively high. Another popular method of implementing microactuators for MEMS is based on the bimetallic effect. The bimetallic effect uses the differing thermal expansion coefficients of two different materials to realize a thermal-based microactuator. When these two materials are made into a composite structure and heated, a thermally induced stress is generated that can result in the structure if it is sufficiently compliant. The thermal strain is given by

ε = (αfilma − αfilmb) (Tele − Tamb) where afilma and afilmb are the thermal expansion coefficients of the top and bottom films, respectively, and Tele and Tamb are the temperature of the bimetallic element and ambient, respectively. Some of the attributes of a bimetallic microactuator for MEMS are high power consumption for heating, low mechanical bandwidth, relatively complex design and fabrication, reasonable deflections, a linear deflection versus power relationship, and sensitivity to environmental conditions. A simple bimetallic microactuator can be made by depositing a thin film of aluminum onto a thin compliant silicon cantilever (see Fig. 23.4), and passing current through the aluminum layer. As the aluminum layer heats up through Joule heating, the cantilever will bend due to the different expansion coefficients of the two materials.

Aluminum thin film

Silicon FIGURE 23.4 Illustration of a bimetallic microactuator made from a thin-film aluminum layer on a silicon cantilever. When heated, aluminum has a higher thermal expansion coefficient than silicon and causes the cantilever to deflect downward.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.6

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.6

NANOTECHNOLOGY, MEMS, AND FPD

Yet another popular material for implementing microactuators in MEMS is shape-memory alloys (SMAs). A SMA is a material that undergoes a martensite to austensite phase change on heating. During this phase change, the material will return to its unstrained shape (i.e., the material has memory). Figure 23.5 is an illustration demonstrating the shape-memory effect. SMAs can be sputter deposited in thin-film form on silicon wafers. Heating of the film is usually achieved by Joule heating. The shape-memory effect is a reversible effect and can be repeated many times. Some attributes of SMAs are used in MEMS actuators—they exhibit very high energy densities, they have enormous recoverable strain levels (strains of over 8 percent have been demonstrated), since they are thermally activated, the power consumption can be high and the mechanical bandwidth low, the processing is somewhat complicated, and the material can fatigue if repeatedly cycled at high strain levels. 23.2.3 Integrated MEMS There are several commercial products in the market, that integrate a MEMS device or an array of MEMS devices onto a silicon substrate with integrated circuits including the Analog Devices accelerometer device for crash air-bag applications, the Texas Instruments DLP chip for optical projection systems, the Honeywell microbolometer uncooled infrared focal plane array (UCFPA), and a few others. While at first it may seem that it would be preferable to always integrate MEMS with electronics, in practice there should be a significant rationale for integration before this is done. For example, the Analog Devices accelerometer required on-chip bipolar complementary metal oxide semiconductor (BiCMOS) circuitry to provide for signal pickup of the capacitive acceleration sensor. This sensor is a surface micromachined device with a very low total device capacitance and even smaller changes in capacitance as the proof mass deflects under loading. It was necessary to integrate the sensor with electronics since the parasitic capacitances of connecting off-chip electronics would have been too large for the sensor to work properly. In the case of both the TI DLP device and the Honeywell UCFPA, the density of actuators and sensors necessitated that the MEMS be built on top of the electronics. In both these examples of integrated MEMS, the cost of development of the process technology was high but was required for the devices to function properly and apparently was also economically justifiable. 23.2.4 The Materials Used in MEMS There is an enormous diversity of materials used to fabricate MEMS devices including semiconductors, metals, glasses, ceramics, and polymers. Furthermore, since the functionality of MEMS devices is not only electrical, but mechanical, chemical, thermal, and the like, the choice of a material or a set of materials for a given application frequently depends on its electrical as well as nonelectrical material

Matensite phase ∆L

F

F

Matensite phase with applied force and resultant strain

∆T Heated in austensite phase with strain recovered FIGURE 23.5 Illustration of the shape-memory effect. The SMA sample is in the martensite phase at the top and is at room temperature and unstrained. In the middle, the sample is subsequently strained and kept at room temperature. At the bottom, the SMA sample is heated and the sample undergoes a phase change from the martensite to the austensite phase and the strain is completely recovered. This cycle can be repeated over and over.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.7

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.7

properties. Silicon is the most popular material used in MEMS. This is partly due to the established infrastructure and extensive knowledge base of silicon as a material. Remarkably, silicon is an extremely good mechanical material and has a yield strength nearly equal to that of stainless steel, and its strength-to-weight ratio is one of the highest of all engineered materials. Nevertheless, if silicon is strained beyond its limit, it will catastrophically fail. This is unlike most metals that plastically deform if loaded beyond their yield points. Another issue with silicon is that it is an anisotropic material and therefore its material properties will vary quite significantly depending on the orientation of the crystal axes with respect to the load. In addition to single crystal silicon, a variety of thin films are also used in MEMS fabrication with the more popular ones being polysilicon, silicon nitride, deposited glasses, and aluminum. These thin films frequently are deposited using either a low-pressure chemical vapor deposition (LPCVD), plasmaenhanced chemical vapor deposition (PECVD), or sputtering, among others, and can have a large residual (or built-in) stress. The residual stresses in thin films are dependent on the material type, temperature of deposition, and method of deposition and can vary from highly compressive to highly tensile. It is extremely desirable that the mechanical properties of the materials used in a MEMS device are accurately determined before initiating the design. Unfortunately, this can be difficult to achieve in practice since the material properties, especially many of the mechanical material properties, are highly dependent on the exact processing conditions and sequence used in the fabrication of the MEMS device. Furthermore, since, each MEMS device frequently has a customized process sequence, the development of a MEMS device and the fabrication sequence must be done in conjunction with the materials properties measurements. The measured material property data can then be fed back into models in order to improve or optimize the design. The measurement of the properties of thin film materials can be challenging. For example, the film cannot be removed from the substrate and have a load-deflection measurement done on it without changing the stress state of the film. Fortunately, the MEMS community has devised a number of different test structures that can be used to measure the most important of material properties (Fig. 23.6). The reader is referred to Ref. 8 for more information.

FIGURE 23.6 SEM (Scanning electron microscope) photograph of an array of thin-film polysilicon beams that are clamped at both ends and have a compressive residual stress. As can be seen, the beams are buckled due to the compressive residual stress in the polysilicon layer. Fortunately, the residual stress can be reduced or eliminated by a high-temperature anneal. For example, it is very common to perform a high-temperature anneal on polysilicon thin films that have been deposited using LPCVD to reduce the high-compressive residual stress in these layers in a surface micromachining process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.8

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.8

NANOTECHNOLOGY, MEMS, AND FPD

23.2.5 MEMS Design Tools MEMS design is frequently more demanding than the design of integrated circuits. In the integrated circuit domain, a process technology and the associated design rules usually already exist. The designer merely needs to build these into their computer-aided design tool that usually only considers the electrical effects, and come up with a design. In MEMS technology, the situation is much more complicated. As previously mentioned, a customized process sequence must frequently be developed for each device type as part of the product development effort, and design rules are not known until the process sequence is finalized. Furthermore, as discussed in the preceding section, the material properties are usually not fully known and are highly dependent on the process sequence and conditions that also are not known beforehand. Also, many MEMS devices have many physical phenomena (such as electrical, mechanical, thermal, and chemical) occurring simultaneously, which leads to many strongly coupled fields and thereby making the design effort much harder. Another key difference between MEMS and integrated circuit designs is that in IC design the designer usually does not need to know much about the fabrication. In MEMS design, the designer must be an expert in MEMS fabrication. Fortunately, there are some design tool capabilities that are now available to the MEMS community, which are suitable for process, physical, device, and systems modeling. The process modeling tools are essentially the same as used by the integrated circuit industry and enable the designer to create process models and mask artwork. Numerical techniques are available to simulate the processing steps. Although these tools are quite good at predicting electrical behavior, they are not very good for predicting mechanical material properties. One important feature of MEMS process design tools is the ability to create representative three-dimensional (3D) renderings of the devices. The physical-level design tools are used to model the behavior of components in the real 3D continuum using partial differential equations. These tools can be analytical or numeric, and the numeric techniques include finite-element, boundary-element, and finite-difference methods. These tools are mostly modified versions of numeric modeling tools used in macroscale design. The devicelevel models are macro or reduced-order models that capture the physical behavior of a component (over a limited range) and are compatible with the system-level models. Care must be exercised to ensure that the dynamic range of the model is not overextended. System-level models are high-level block diagrams and lumped-parameter models that describe the system as a coupled set of ordinary differential equations.

23.3 HOW ARE MEMS MADE? 23.3.1 Overview of Front-end Micromachining Processes MEMS fabrication is an extremely exciting endeavor due to the customized nature of process technologies and the diversity of processing capabilities. MEMS fabrication uses many of the same techniques that are used in the integrated circuit domain, such as oxidation, diffusion, ion implantation, LPCVD, and sputtering, and combines these capabilities with highly specialized micromachining processes. Some of the most widely used micromachining processes are discussed in the following sections. Bulk Micromachining. The oldest micromachining technology is bulk micromachining. This technique involves the selective removal of the substrate material in order to realize miniaturized mechanical components. Bulk micromachining can be accomplished using chemical or physical means, with chemical means being far more widely used in the MEMS industry. A widely used bulk micromachining technique is chemical wet etching that involves the immersion of a substrate into a solution of reactive chemical that will etch exposed regions of the substrate at measurable rates. Chemical wet etching is popular in MEMS because it can provide a very high etch rate and selectivity. Furthermore, the etch rates and selectivity can be modified by altering the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.9

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.9

chemical composition of the etch solution, adjusting the etch solution temperature, modifying the dopant concentration of the substrate, and even the selection of the crystallographic planes of the substrate to be exposed to the etchant solution. The basic mechanism of chemical wet etching involves the following—reactant transport to the surface of the substrate, followed by the reaction at the substrate surface between the etchant solution and the substrate material, and transport of the reaction products from the substrate. If the transport of reactants to the surface of the substrate or transport of reaction products away from the substrate surface are the rate-determining steps, then etching is defined as diffusion limited and the etch rate can be increased by stirring the solution. If the surface reaction is the rate-determining step, then etching is reaction rate limited, and the etch rate is very dependent on the etch solution temperature and composition and the substrate material. In practice, it is usually preferred that the process is reaction-rate limited since this gives more repeatability and a higher etch rate. There are two general types of chemical wet etching in bulk micromachining—isotropic and anisotropic wet etching.9 In isotropic wet etching, the etch rate is not dependent on the crystallographic orientation of the substrate and the etching proceeds in all directions at equal rates. The most common isotropic etchant for silicon is a solution of HNO3, HF, and HC2H3O2. The reaction is given by HNO2 + HNO3 + H2O −−> 2HNO2 + 2OH− + 2H+ Holes and (OH)− ions are supplied by HNO3 when it combines with H2O and trace concentrations of HNO2. Note that the reaction is autocatalytic because of the regeneration of HNO2. Increasing the concentration moves the reaction toward diffusion-limited etch rate dependence, and etching can be controlled by stirring. Increasing the HF concentration or temperature increases the surface reaction rate. In theory, lateral etching under the masking layer etches at the same rate as the etch rate in a normal direction. However, in practice lateral etching is usually much slower without stirring and consequently isotropic wet etching is almost always performed with vigorous stirring of the etchant solution. Figure 23.7 illustrates the profile of the etch using an isotropic wet etchant with and without stirring of the etchant solution. Any etching process requires a masking material to be used with preferably a high selectivity relative to the substrate material. Common masking materials for isotropic wet silicon etching include silicon dioxide and silicon nitride. Silicon nitride has a much lower etch rate compared to silicon dioxide and therefore is more frequently used. The etch rate of some isotropic wet etchant solution mixtures are dependent on the dopant concentration of the substrate material. For example, the commonly used mixture of HC2H3O2:HNO3:HF in the ratio of 8:3:1 will etch highly doped silicon (>5 × 1018 atoms/cm3) at a rate of 50 to 200 µm/h, but will etch lightly doped silicon material at a rate 150 times less. Nevertheless, the etch rate selectivity with respect to dopant concentration is highly dependent on the solution mixture. The much more widely used wet etchants for silicon micromachining are anisotropic wet etchants. Anisotropic wet etching involves the immersion of the substrate into a chemical solution

Without stirring

With stirring FIGURE 23.7 Illustration of the etch profile, with and without stirring, using an isotropic wet chemical etchant.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.10

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.10

NANOTECHNOLOGY, MEMS, AND FPD

wherein the etch rate is dependent on the crystallographic orientation of the substrate. The mechanism by which the etching varies according to silicon crystal planes is attributed to the different bond configurations and atomic density that the different planes are exposed to in the etchant solution. Wet anisotropic chemical etching is typically described in terms of etch rates according to different normal crystallographic places, usually <100>, <110>, and <111>. In general, silicon anisotropic etching etches more slowly along the <111> planes than all the other planes in the lattice and the difference in etch rate between the different lattice directions can be as high as 1000 to 1. It is thought that the reason for the slower etch rate of the <111> planes is that these planes have the highest density of exposed silicon atoms in the etchant solution, as well as three silicon bonds below the plane, thereby leading to some amount of chemical shielding of the surface. The ability to delineate the different crystal planes of the silicon lattice in anisotropic wet chemical etching provides a high-resolution etch capability with reasonably tight dimensional control. It also provides the ability for two-sided processing to embody self-isolated structures wherein only one side is exposed to the environment. This assists in the packaging of the device and is very useful for MEMS devices exposed to harsh environments such as in pressure sensors. Anisotropic etching techniques have been around for over 25 years and are commonly used in the manufacturing of silicon pressure sensors as well as bulk micromachined accelerometers. Figure 23.8 is an illustration of some of the shapes that are possible using anisotropic wet etching of a <100>-oriented silicon substrate including an inverted pyramidal and a flat-bottomed trapezoidal etch pit. Note that the shape of the etch pattern is primarily determined by the slower etching <111> planes. Figures 23.9(a) and (b) are scanning electron microscope (SEM) photographs of a silicon substrate after anisotropic wet etching and show in Fig. 23.9a, a trapezoidal etch pit that has been subsequently diced across the etch pit and in Fig. 23.9b, the backside of a thin membrane that could be used to make a pressure sensor. It is important to note that the etch profiles shown in the figures are only for a <100>-oriented silicon wafer, and substrates with other crystallographic orientations will exhibit different shapes. Occasionally, substrates with other orientations are used in

(100) (111)

Frontside mask

Boron-doped Si membrane

54.74° (111) Backside mask <100> (111)

Self-limiting etches

FIGURE 23.8 Illustration of the shape of the etch profiles of a <100>oriented silicon substrate after immersion in an anisotropic wet etchant solution.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.11

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

(a) FIGURE 23.9 etchant.

23.11

(b)

SEMS of a <100> oriented silicon substrate after immersion in an anisotropic wet

MEMS fabrication, but given the cost, lead times, and availability, the vast majority of substrates used in bulk micromachining have <100> orientation. There are three basic types of anisotropic wet etchants that are commonly used. The first and by far the most popular anisotropic etchants are aqueous alkaline solutions such as KOH, NH4OH, NaOH, CsOH, and TMAH.13 These etchants have high etch rates and a relatively high etch-rate ratio between <100> and <111> planes. Also, TMAH is sometimes preferred for use on preprocessed microelectronic wafers, since this etchant does not etch aluminum appreciably under certain conditions. The drawbacks of these etchants are that they have a relatively high etch rate of silicon dioxide that is frequently used as a masking material. There is the potential for alkali contamination of the wafer using these etchants, although there are cleaning procedures that can be employed to minimize these risks. Another popular anisotropic wet etchant is ethylene diamine and pyrocatechol (EDP). This etchant has a higher etch rate ratio of the <100> and <111> planes and has a larger variety of masking materials that can be used compared to aqueous alkaline solutions. The drawbacks of EDP are that it is a carcinogenic material, and when using this solution it can be difficult to see the wafer etching. Also, EDP is a thick orange-yellow material and can be hard to clean. The last type of anisotropic etchant is hydrazine and water (N2H2:H2O). One advantage of this etchant is that it has a very low silicon dioxide etching rate, but on the other hand it has a relatively poor etch-rate ratio of the <100> and <111> planes. The biggest disadvantage of hydrazine etching is that it is a very hazardous material. Although it was used in the early days of micromachining, given that its disadvantages outweigh its advantages, it is now rarely used. Useful anisotropic wet etching requires the ability to successfully mask certain areas of the substrate and consequently an important criterion for selecting an etchant is the availability of good masking materials. Silicon nitride is a commonly used masking material for anisotropic wet etchants since it has a very low etch rate in most etchant solutions. Some care must be exercised in the type of silicon nitride used, since any pin-hole defects will result in the attack of the underlying silicon. Also, some low-stress silicon-rich nitrides can etch at much higher rates compared to stoichiometric silicon nitride formulations. Thermally grown SiO2 is frequently used as a masking material, but some care must be exercised to ensure a sufficiently thick masking layer when using KOH etchants since the etch rates of oxides can be high. Photoresists are unusable in any anisotropic etchant. Many metals including Ta, Au, Cr, Ag, and Cu hold up well in EDP and Al holds up in TMAH under certain conditions. In general, etch rates, etch-rate ratios <100>/<111>, and etch selectivities of anisotropic etchants are strongly dependent on the chemical composition and temperature of the etchant solution. The etch rate [R] obeys the Arrhenius law given by [R] = Ro exp(−Ea/kT) µm/h

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.12

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.12

NANOTECHNOLOGY, MEMS, AND FPD

where Ro = constant Ea = activation energy k = Boltzmann’s constant T = temperature in degrees Kelvin Both Ro and Ea will vary on the type of etchant, etchant composition, and crystallographic orientation of the material being etched. Fortunately, there is a wealth of published literature characterizing many of the commonly used anisotropic etchants and the reader is referred to Ref. 13 for more information. Frequently, when using bulk micromachining it is desirable to make thin membranes of silicon or control the etch depths very precisely. As with any chemical process, the uniformity of the etching can vary across the substrate, making this difficult. Timed etches whereby the etch depth is determined by multiplying the etch rate by the etch time are difficult to control, and the etch depth is very dependent on the sample thickness uniformity, etchant species diffusion effects, loading effects, etchant aging, surface preparation, and the like. To allow a higher level of precision in anisotropic etching, the MEMS field has developed solutions to this problem, namely etch stops. Etch stops are very useful to control the etching process and provide uniform etch depths across the wafer, from wafer to wafer, and from wafer lot to wafer lot. There are two basic types of etch stop methods that are used in micromachining—dopant and electrochemical etch stops. Etch stops in silicon are commonly made by the introduction of dopants into the silicon material. The most popular etch stop is heavy p-type doping of silicon with boron (more than 5 × 1019 cm−3) to create an etch stop. The lightly doped region of the wafer will etch at the normal rate and the highly doped region of the silicon will have a very slow etch rate. The dopant is introduced into the silicon using the standard technique of thermal diffusion and provides for a controlled depth and reasonable uniformity of the dopants in the substrate. Figure 23.10 is a graph of the normalized etch rate of a <100>-oriented silicon wafer in KOH at different concentrations as a function of the boron dopant concentration.10,11 As can be seen, the etch rate falls off very quickly at dopant concentrations above 1019 boron atoms/cm3. One of the problems with boron etch stops is that the surface of the silicon will be so highly doped that it may not be useful. For example, the material at the concentrations required for a good etch stop would not be useful for making a piezoresistive device. The other etch stop method used in silicon bulk micromachining is the electrochemical etch stop.12–16 Figure 23.11 is an illustration of a three-terminal electrochemical etch setup. Electrochemical etching of silicon using an anisotropic etchant is useful since it provides very good dimensional control (e.g., the diaphragm thickness is reproducible) and can make diaphragms with lightly doped material, which is required for high-quality piezoresistive devices. The disadvantage of electrochemical etch stops is that they require special fixturing to each wafer in order to make electrical contacts, and an electronic control system is needed to control and apply the correct voltage potential to the wafer during the etch. Surface Micromachining. Surface micromachining is another very popular technology for the fabrication of MEMS devices. There is a very large number of variations of how surface micromachining is performed depending on the materials and etchant combinations that are used.17,18 However, the common theme involves a sequence of steps starting with the deposition of some thinfilm material to act as a temporary mechanical layer onto which the actual device layers are built, followed by the deposition and patterning of the thin-film device layer of the material, which is referred to as the structural layer, and followed by the removal of the temporary layer to release the mechanical structure layer from the constraint of the underlying layer thereby allowing the structural layer to move. An illustration of a surface micromachining process is given in Figure 23.12, wherein an oxide layer is deposited and patterned. This oxide layer is temporary and is commonly referred to as the sacrificial layer. Subsequently, a thin-film layer of polysilicon is deposited and patterned, and this layer is the structural mechanical layer. Lastly, the temporary sacrificial layer is removed and the polysilicon layer is now free to move as a cantilever. Some of the reasons why surface micromachining is so popular is that it provides for precise dimensional control in the vertical direction due to the fact that the structural and sacrificial layer Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

20:48

Page 23.13

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

101

100

Relative etch rate

Geng(SMH)_CH23.qxd

10−1 KOH concentration 10% 24% 42% 57%

10−2

<100> silicon 60°C

10−3 1017

1018

1019 Boron concentration

cm−3

1020

FIGURE 23.10 Etch rate plotted versus boron concentration for a <100>-oriented silicon wafer at different etchant concentrations.

Potentiostat

Reference electrode

Working electrode

Counter electrode

FIGURE 23.11 Illustration of the setup for a three-terminal electrochemical etch of silicon.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

23.13

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.14

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.14

NANOTECHNOLOGY, MEMS, AND FPD

10 µm

Oxide

Si substrate FIGURE 23.12

Poly-Si

Si substrate

Cantilever Anchor

Si substrate

Illustration of a surface micromachining process.

thicknesses are defined by deposited film thicknesses that can be accurately controlled. Also, surface micromachining provides for precise dimensional control in the horizontal direction since the structural layer tolerance is defined by the fidelity of the photolithography and etch processes used. Other benefits of surface micromachining are that a large variety of structure, sacrificial, and etchant combinations can be used, and some are compatible with microelectronics devices to enable integrated MEMS devices. Surface micromachining frequently exploits the deposition characteristics of thin films, such as conformal coverage using LPCVD. Lastly, surface micromachining uses single-sided wafer processing and is relatively simple. This allows a higher integration density and lower resultant per-die cost compared to bulk micromachining. One of the disadvantages of surface micromachining is that the mechanical properties of LPCVD structural thin films are usually unknown and must be measured. Also it is common for these types of films to have a high state of residual stress frequently necessitating a high-temperature anneal to reduce residual stress in the structural layer. Also, the reproducibility of the mechanical properties in these films can be difficult to achieve. Additionally, the release of the structural layer can be difficult due to stiction—an effect whereby the structural layer is pulled down and stuck to the underlying substrate due to capillary forces during release. Stiction can also occur in use and an antistiction coating material may be needed. The most commonly used surface micromachining process and material combination is a phosphosilicate glass (PSG) sacrificial layer, a doped polysilicon structural layer, and the use of hydrofluoric acid as the etchant to remove the PSG sacrificial layer and release the device. This type of surface micromachining process is used to fabricate the Analog Devices integrated MEMS accelerometer device used for crash air-bag deployment. Figures 23.13 and 23.14 are SEMs of two surface micromachined polysilicon MEMS devices.

FIGURE 23.13 A polysilicon micromotor fabricated using a surface micromachining process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.15

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.15

FIGURE 23.14 A polysilicon resonator structure fabricated using a surface micromachining process.

Another variation of the surface micromachining process is the use of a metal structural layer, a polymer layer as the sacrificial layer, and an O2 plasma as the etchant. The advantage of this process is that the temperature of the sacrificial and structural layer depositions are sufficiently low so as to not degrade any microelectronics in the underlying silicon substrate, thereby enabling MEMS to be integrated with electronics. Also, since the sacrificial layer is removed without immersion in a liquid, problems associated with stiction during release are avoided. A process similar to this is used to produce the TI DLP device used in projection systems. Wafer Bonding. Wafer bonding is a micromachining method that is analogous to welding in the macroscale world and involves the joining of two (or more) wafers together to create a multiwafer stack. There are three basic types of wafer bonding, including direct or fusion bonding, field-assisted or anodic bonding, and bonding using an intermediate layer. In general, all bonding methods require substrates that are very flat, smooth, and clean in order for the wafer bonding to be successful and free of voids. Direct or fusion bonding is typically used to mate two silicon wafers together or alternatively to mate one silicon wafer to another silicon wafer that has been oxidized. Direct wafer bonding can be performed on other combinations such as bare silicon to a silicon wafer with a thin film of silicon nitride on the surface as well. The basic wafer bonding process has five steps:19 1. Hydration and cleaning (such as RCA clean and piranha immersion) of wafer surfaces 2. Physical contacting and pressing together of wafers (must be done quickly and in a clean environment since silicon will be charged and attract particles) 3. Infrared inspection of pre-anneal bond quality 4. High-temperature anneal, typically 1000°C 5. Infrared inspection of post-anneal bond quality Figure 23.15 illustrates some of the steps involved in the direct wafer bonding process. The wafers are initially held together after physical contacting due to the hydrogen bonds created by the hydration of the surfaces. The two wafers to be bonded can be preprocessed and then aligned during the bonding procedure so as to register features on the top wafer to features on the bottom wafer. After the hightemperature anneal, the bond strength between the two wafers is similar to that of single crystal silicon. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.16

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.16

NANOTECHNOLOGY, MEMS, AND FPD

Hydrated surfaces Wafer 2 Step 1 - Clean and hydration

Wafer 1 Wafer 2 Step 2 - Physical contacting

Wafer 1 Wafer 2 Step 4 - High temperature anneal FIGURE 23.15

Direct or fusion wafer bonding.

There is relatively low residual stress in the bonded layers after anneal. It is imperative that the wafers are flat, smooth, and clean prior to bonding and the bonding process is performed in a very clean environment. The hydration of the surfaces makes them highly charged and attractive to particles in the environment. Any particles attached to the wafer surfaces prior to bonding will result in voids between the two wafers or the inability of the wafers to bond. Although the high-temperature anneal can be performed at a lower temperature than 1000°C in direct silica wafer bonding, the bond strengths tend to be weak when the anneals are performed below 800°C. As mentioned, wafer bonding is analogous to welding in the macroscale world. Wafer bonding is used to attach a thick layer of single crystal silicon onto another wafer. This can be extremely useful when it is desired to have a thick layer of material for applications requiring appreciable mass or in applications where the material properties of single crystal silicon are advantageous over those of thin-film LPCVD materials. Direct wafer bonding is also used to fabricate silicon-on-insulator (SOI) wafers having device layers several microns or more in thickness. Another popular wafer bonding technique is anodic bonding, which is illustrated in Figure 23.16. In anodic bonding a silicon wafer is bonded to a Pyrex 7740 wafer using an electric field and elevated temperature.20,21,22 The two wafers can be preprocessed prior to bonding and can be aligned during the bonding procedure. The mechanism by which anodic bonding works is based on the fact that Pyrex 7740 has a high concentration of Na+ ions and a positive voltage applied to the silicon wafer drives the Na+ ions from the Pyrex glass surface, thereby creating a negative charge at the glass surface. The elevated temperature during the bonding process allows the Na+ ions to migrate in the

500 to 1000 V −

Pyrex 7740 Silicon

+

Hot plate - 500°C FIGURE 23.16

Illustration of the setup for anodic wafer bonding.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.17

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.17

glass with relative ease. The realigned charge distribution in the glass results in a high-field between the silicon and the glass, and this combined with the elevated temperatures fuses the two wafers together. As with direct wafer bonding, it is imperative that the wafers are flat, smooth, and clean and that the anodic bonding process is performed in a very clean environment. Any particles on the wafer surfaces will result in voids between the two wafers. One advantage of this process is that Pyrex 7740 has a thermal expansion coefficient nearly equal to silicon and therefore there is a low value of residual stress in the layers. Anodic bonding is a widely used technique for MEMS packaging. In addition to direct and anodic bonding there are other wafer bonding techniques that are used in MEMS fabrication. One method is eutectic bonding and involves the bonding of a silicon substrate to another silicon substrate at an elevated temperature using an intermediate layer of gold on the surface of one of the wafers.23 Eutectic bonding works because the diffusion of gold into silicon is extremely rapid at elevated temperatures. In fact, this is a preferred method of wafer bonding at relatively low temperatures. Another wafer bonding technique used in MEMS is glass-frit bonding.24 In this process glass is spun or screen printed onto one substrate surface. Subsequently this wafer is physically contacted to another wafer and the composite is annealed to flow the glass intermediate layer and bond the two wafers. Lastly, various polymers can be used as intermediate layers to bond wafers, including epoxy resins, photoresists, polyimides, silicones, and the like.25 This technique is commonly used during various fabrication steps in MEMS, such as when the device wafer becomes too fragile to handle without mechanical support. High-aspect-ratio MEMS Fabrication Technologies Deep reactive ion etching of silicon. Deep reactive ion etching (DRIE) is a relatively new fabrication technology that has been widely adopted by the MEMS community.26,27 This technology enables very high-aspect-ratio etches to be performed into silicon substrates. The sidewalls of the etched holes are nearly vertical and the depth of the etch can be hundreds or even thousands of microns into the silicon substrate. Figure 23.17 illustrates how DRIE is accomplished. The etch is a dry plasma etch and uses a highdensity plasma to alternatively etch silicon and deposit an etch-resistant polymer layer on the sidewalls. The etching of silicon is performed using an SF6 chemistry whereas the deposition of the etch-resistant polymer layer on the sidewalls uses a C4F8 chemistry. Mass-flow controllers alternate back and forth between these two chemistries during the etch. The protective polymer layer is deposited on the sidewalls as well as the bottom of the etch pit, but the anisotropy of the etch removes the polymer at the bottom of the etch pit faster than the polymer is removed from the sidewalls. The sidewalls are not perfect or optically smooth and if the sidewall is magnified under SEM inspection, a characteristic washboard or scalloping pattern is seen in the sidewalls. The etch rates on most commercial DRIE systems varies from 1 to 4 µm/min. DRIE systems are single wafer tools. A photoresist can be used as a masking layer for DRIE etching. The selectivity with photoresist and oxide is about 75 to 1 and 150 to 1, respectively. For a through-wafer etch a relatively thick photoesist masking layer will be required. The aspect ratio of the etch can be as high as 30 to 1, but in practice tends to be 15 to 1. The process recipe depends on the amount of exposed silicon due to loading effects in the system, with larger exposed areas etching at a much faster rate compared to smaller exposed areas. Consequently, the etch must frequently be characterized for the exact mask feature and depth to obtain desirable results. Figure 23.18 is a SEM of an MEMS component fabricated using DRIE and wafer bonding. This device was made using an SOI wafer wherein a backside etch was performed through the handle wafer and stopping on the buried oxide layer and a frontside DRIE was performed on the SOI device layer and then the buried oxide was removed to release the microstructure allowing it to freely move. Figure 23.19 is a cross-section SEM of a silicon microstructure fabricated using DRIE technology. As can be seen, the etch is very deep into the silicon substrate and the sidewalls are nearly vertical. Deep reactive ion etching of glass. Glass substrates can also be etched deep into the material with high aspect ratios and this technology has been gaining in popularity in MEMS fabrication.28 Figures 23.20 and 23.21 show various structures fabricated into glass using this technology. Figure 23.20 shows some deep, high-aspect-ratio trenches etched into glass and Fig. 23.21 is a SEM of a Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.18

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.18

NANOTECHNOLOGY, MEMS, AND FPD

SFx+ +

F Mask

Silicon Etch nCFx+

Polymer (nCF2) Deposit polymer

F SFx+

Etch FIGURE 23.17

Illustration of how DRIE works.

FIGURE 23.18 SEM of an MEMS device fabricated using two-sided DRIE etching technology on an SOI wafer.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.19

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.19

microlens array made in glass. The typical etch rates for high-aspect-ratio glass etching range between 250 and 500 nm/min. Depending on the depth a photoresist, metal, or a polysilicon can be used as a mask. LIGA. Another popular high-aspect-ratio micromachining technology is called LIGA, which is a German acronym for “LIthographie Galvanoformung Adformung.”29 This is primarily a nonsilicon-based technology and requires the use of a synchrotron generated x-ray radiation. The basic process is outlined in Fig. 23.22 and starts with the cast of an x-ray radiation sensitive Poly(methyl methacrylate) (PMMA) onto a suitable substrate. A special x-ray mask is used for the selective exposure of the PMMA layer using x-rays. The PMMA is then developed and defined with extremely smooth and nearly perfectly vertical sidewalls. Also, the penetration depth of the x-ray radiation into the PMMA layer is quite deep and allows exposure through very thick PMMA layers, up to and exceeding 1 mm. After the development, the patterned PMMA acts as a polymer mold and is FIGURE 23.19 SEM of the cross section of a silwafer demonstrating a high aspect ratio and placed into an electroplating bath and nickel is plated icon deep trenches that can be fabricated using DRIE into the open areas of the PMMA. The PMMA is technology. then removed, thereby leaving the metallic microstructure (Fig. 23.23). Because LIGA requires a special mask and a synchrotron (x-ray) radiation source for the exposure, the cost of this process is relatively expensive. A variation of the process which reduces the cost of the micromachined parts made with this process is the reuse of the fabricated metal part (step 5) as a tool insert to imprint the shape of the tool into a polymer layer (step 3), followed by the electroplating of metal into the polymer mold (step 4) and the removal of the polymer mold (step 5).30 Obviously this sequence of steps avoids the need of a synchrotron radiation source each time a part is made and thereby significantly lowers the cost of the process. The dimensional control of this process is quite good and the tool insert can be used many times before it is worn out.

22 µm

22 µm depth trench (SiO2) FIGURE 23.20 SEM of high-aspect-ratio structures etched into a glass substrate. (Courtesy of ULVAC Technologies, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.20

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.20

NANOTECHNOLOGY, MEMS, AND FPD

3 µm

10 µm

FIGURE 23.21 SEM of a microlens array etched into a glass substrate. (Courtesy of ULVAC Technologies, Inc.)

Hot embossing. Another variation of this process is to fabricate the metal tool insert using LIGA or a comparable technology and then to emboss the tool insert pattern into a polymer substrate, which is then used as the part. Figure 23.24 is a photograph of a nickel mold insert (the part in the right side of the photo) and a polymer substrate embossed (the part in the left side of the photo) with the metal mold insert. This process can make imprints into a polymer of over 200 µm deep with very good dimensional control. The advantage of this process is that the cost of the individual polymer parts can be very low compared to the same structures made using other technologies. Because of the overwhelming cost advantages combined with very good performance, this polymer molding process is very popular for producing microfluidic components.

Cast PMMA on metal base

X-ray radiation

Separate metal from PMMA

1

2

5

Develop PMMA

Electroplate through PMMA

4

3

FIGURE 23.22 An illustration of the steps involved in the LIGA process to fabricate highaspect-ratio MEMS devices.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:48

Page 23.21

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.21

FIGURE 23.23 A tall high-aspect-ratio gear made using LIGA technology. (Courtesy of Louisiana State University CAMD.)

Other Micromachining Technologies. In addition to bulk micromachining, surface micromachining, wafer bonding, and high-aspect-ratio micromachining technologies, there are a number of other techniques used to fabricate MEMS devices. We shall review a few of the more popular methods in this section, but the reader is referred to Ref. 13 for an exhaustive catalog of MEMS processes. Xenon difluoride (XeF2) dry phase etching. XeF2 in a vapor state is an isotropic etchant for silicon.31 This etchant is highly selective with respect to other materials commonly used in microelectronics fabrication including LPCVD silicon nitride, thermal SiO2, aluminum, titanium, and others. Since the etching process with this etchant is a completely dry release process, it does not suffer from the stiction problems of wet release processes. Figure 23.25 is a cross-sectional SEM of a cantilever beam made by isotropic etching the silicon substrate using XeF2 to partially undercut the metal material of the cantilever. This etchant is popular with micromachining of microstructures in preprocessed CMOS wafers where openings in the passivation layers on the surface of the substrate are made to expose the silicon for etching. Electrodischarge micromachining (EDM). Electro-discharge micromachining or micro-EDM is a process used to machine a conductive material using electrical breakdown discharges to remove material. A working electrode is made from a metal material onto which high-voltage pulses are applied. The working electrode is brought into close proximity to the material to be machined, which has been

FIGURE 23.24 A photograph of a tool insert and a polymer substrate hot embossed with the tool insert to fabricate a microfluidic device. (Courtesy of Louisiana State University CAMD.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:49

Page 23.22

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.22

NANOTECHNOLOGY, MEMS, AND FPD

FIGURE 23.25 SEM of a beam undercut using XeF2 isotropic etching of silicon.

immersed in a dielectric fluid. The minimum-sized features that can be made with micro-EDM are dependent on the size of the working electrode and how it is fixtured, but holes as small as tens of microns have been made using this method. One issue with micro-EDM is that it is a slow serial process. Laser micromachining. Lasers can generate an intense amount of energy in very short pulses of light and direct that energy onto a selected region of material for micromachining. Among the many types of lasers now in use for micromachining include CO2, YAG, and excimer, among others. Each has its own unique properties and capabilities suited to particular applications. Factors that determine the type of laser to use for a particular application include the laser wavelength, energy, power, and temporal and spatial modes, material type, feature sizes and tolerances, processing speed, and cost. The action of CO2 and Nd:YAG lasers is essentially a thermal process, whereby focusing optics are used to direct a predetermined energy/power density to a well-defined location on the work piece to melt or vaporize the material. Another mechanism, which is nonthermal and referred to as photoablation, occurs when organic materials are exposed to ultraviolet radiation generated from excimer, harmonic YAG, or other UV sources. Similar to micro-EDM, laser micromachining can produce features in the order of tens of microns, but it is a serial process and is therefore slow. Figure 23.26 is a photo of some holes made in a medical catheter using laser micromachining. Focused ion beam micromachining. Another versatile tool for performing micromachining is the FIB. The accelerating voltages are adjustable from a few to several hundred keV. The spot sizes can be

FIGURE 23.26 0.008 in, 0.004 in, and 0.001 in holes made in a medical catheter using laser micromachining. (Courtesy of Resonetics, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:49

Page 23.23

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.23

focused down to 50 nm, making it capable of making extremely small structures. The user can input a 3D CAD solid model of desired etching topology and the computer controlled stage with submicron positional accuracy allows a very precise registration of the sample. In addition to material removal, the FIB can also be used to perform ion-induced deposition, lithography, implantation doping, mask repair, device repair, and device diagnostics. Many of these tools can also be outfitted with a secondary column for the mass analysis of particles removed from the substrate using uSIMS. Electrochemical fabrication (EFAB). EFAB is a micromachining process technology that is in many ways similar to stereolithography. Using this technology, three-dimensional microstructures are created through a sequential series of depositions of thin layers of the structural material. Each thin layer can be independently patterned so as to provide flexibility of the resultant device shape. The process easily allows overhanging components and components that bridge across supports. Individual layer thicknesses range between about 1 µm to over 10 µm, and the minimum lateral feature size is a few microns. 23.3.2 MEMS Process Integration Process integration for our purposes is defined as understanding, characterizing, and optimizing to the extent possible, the interrelationship of the individual processing steps in a process sequence. Given the customization of MEMS process sequences, it should not be surprising that process integration is of critical importance. Also, given that MEMS developers must not only have good data on the electrical material properties, but also on the mechanical material properties, coupled with the enormous diversity of materials and processing techniques used in MEMS fabrication, means that this can be a major part of a product development effort. Consequently, it is not uncommon to see that the product development costs of complex process technologies, such as integrated MEMS devices, can exceed the costs of developing typical microelectronics process technologies. Fortunately, the MEMS community has been working on this problem and one of the most promising solutions is to modularize the processes so as to simultaneously provide the flexibility in the process sequence, which is needed in MEMS, while also affording a good level of reproducibility.32,33 Although the process sequences for most MEMS devices are quite different, it is illustrative to provide the example of a process sequence for a typical MEMS device—a silicon-based pressure sensor. The process is shown in Fig. 23.27. The process starts with an SOI wafer having a device layer thickness tailored to the desired mechanical behavior of the diaphragm onto which piezoresistors will be made (see Fig. 23.27a). Subsequently, the piezoresistors are formed in the device layer using either diffusion or implantation and followed by a high temperature as shown in Fig. 23.27b. Typically, the silicon substrate (in this case, the device layer of the SOI wafer) is n-type and the dopant for forming the piezoresistors is boron, or p-type. Next, a layer of passivation material (commonly oxide or nitride) is deposited and patterned, followed by the deposition and patterning of a metal layer, and then followed by the deposition and patterning of

(a)

(b)

(c)

(d ) FIGURE 23.27 Process sequence for a piezoresistive silicon pressure sensor using SOI wafer and bulk micromachining.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:49

Page 23.24

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.24

NANOTECHNOLOGY, MEMS, AND FPD

another passivation layer (Fig. 23.27c). This is to make electrical contacts to the piezoresistor devices and wire the devices into a Wheatstone bridge configuration. Lastly, the handle wafer is anisotropically etched, the silicon material is removed immediately under the piezoresistors and the buried oxide is removed (Fig. 23.27d), thereby creating a thin mechanically compliant diaphragm. 23.3.3 Backend MEMS Processes: Device Release and Die Separation Backend processes for MEMS are usually more challenging than those found in integrated circuits. One reason is that many MEMS products have movable elements that are made from silicon or other thin film materials and these elements can be easily broken. The backend processes for MEMS frequently involve the releasing of the movable elements and die separation. Releasing of the movable elements prior to die separation means that the fragile MEMS devices must survive the cutting and separation processes, which frequently requires special fixturing. Likewise, if the die separation is performed first, a means to perform the release of the MEMS device in a batch mode rather than individually, it will require a special fixturing. Another issue is the release process itself. Many times the release is performed using an immersion into a strong chemical solution, such as hydrofluoric acid, for the removal of a sacrificial oxide layer. The wafer must then be rinsed and dried, and the retracting liquid can cause the movable element to be brought into contact with the underlying substrate and remain stuck. This is commonly referred to as release stiction and a widely used solution to this problem is CO2 supercritical point drying.34 While supercritical drying may solve the problem of stiction during release, it is not uncommon for compliant MEMS devices to come into contact with the underlying substrate during use as well. This can also result in stiction that results in the MEMS device becoming inoperable. Self-assembled monolayers and environmental control of the MEMS device in the package are frequently used to overcome the stiction effects during use.35 23.3.4 Assembly, Testing, and Packaging of MEMS MEMS assembly, testing, and packaging are other demanding areas of the technology. There are very few MEMS wafer-level functional test systems available and the availability of test equipment is very application specific. MEMS testers must usually apply a suitable stimulus to the device under test (e.g., pressure, or inertia). Consequently, a test system for a pressure sensor will invariably be very different from a tester for an inertial sensor. Assembly in MEMS is demanding because many MEMS devices are very fragile and standard pick-and-place equipment may not be appropriate. Also, many standard die attach adhesives are often not appropriate and the effect of stress on the die due to the use of an adhesive and as a function of time must be considered. MEMS packages often must allow controlled access of the die to the environment (e.g., a pressure sensor requires a port allowing the pressure to be applied to the strain-sensitive membrane) and simultaneously protect die from all other environmental effects. Furthermore, there are no MEMS packaging standards and existing packaging solutions tend to be highly proprietary. Even for mature MEMS markets, packaging solutions are frequently fragmented due to the use of different package types to accommodate different customer needs. Consequently, the cost of the packaged MEMS device is frequently dominated by the cost of the assembly, testing and packaging of the component. It is not uncommon for this cost to be 50 percent to 90 percent of the total packaged device cost.

23.4 WHAT ARE THE APPLICATIONS OF MEMS? 23.4.1 Overview MEMS is a new technology with an enormous number of potential applications. As the technology matures, it is expected that more and more of these opportunities will continue to be exploited. In this section, we will discuss some of the more widely known applications and then quickly review Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:49

Page 23.25

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.25

some expected future applications. The reader is referred to Ref. 36 for a more in-depth review of MEMS applications. 23.4.2 Applications Automotive. The automotive market is one of the largest for MEMS devices and exclusively composed of sensors. Currently, MEMS automotive applications include pressure transducers, accelerometers, gyroscopes, and carbon monoxide and mass flow sensors. The largest single application for MEMS pressure sensors in the auto market is for manifold air pressure monitoring. This may change in the future with the expected introduction of in-dwelling tire pressure monitoring using MEMS devices. Inertial measuring MEMS devices are primarily accelerometers that are currently used for front and side airbag deployment, but new markets for electrically controlled suspension and traction control systems are expected. MEMS gyroscopes are starting to be used for vehicle stability and roll-over control applications as well. MEMS flow sensors are starting to be used for engine-control applications. Some of the companies dominating the auto MEMS market are Bosch, Delphi, Motorola, and Analog Devices. The quantity and diversity of MEMS sensors is expected to increase in the future. This coupled with the fact that MEMS sensors will continually displace other sensor technologies means that the automotive market for MEMS is expected to steadily increase for the foreseeable future. Industrial Control. The industrial control market is a significant market for MEMS devices and is also mostly composed of sensors such as pressure sensors, accelerometers, gyroscopes, vibration sensors, shock and impact sensors, security devices, and a few others. Industrial control applications tend to have a very large spectrum of dynamic ranges. For example, pressure sensors may be expected to measure relatively small pressures (e.g., 1 to 5 psi gauge) for a fluidic system to enormously high pressures for an extruder (e.g., over several thousand psi). Each of these individual markets will frequently require a specific design and the resultant individual markets may not be very large. Honeywell and Endevco are two of the leading companies in this area. Office Equipment. Ink-jet nozzles for printers are by far the largest market for MEMS in office equipment. These are usually sold as disposable cartridges that plug into the printer and contain a supply of ink. The companies dominating this space are HP, Lexmark, and Canon. Another large and rapidly growing office equipment application is MEMS displays for projectors. Texas Instruments dominates this segment with its DLP technology. Some of the other applications of MEMS include joysticks and head-mounted displays. Aerospace. MEMS markets in aerospace applications include pressure sensors, rate sensors, navigation sensors, accelerometers, shear and shear rate sensors, strain sensors, temperature sensors, flow sensors, and conformable surfaces for the aerodynamic control of aircraft. Many of these applications involve very harsh conditions and require special materials and packaging. For example, researchers are working on MEMS pressure sensors fabricated from silicon carbide that can be placed inside a gas turbine engine. This market is still relatively small, but is expected to grow significantly in the future. Medical. There are a wide variety of applications for MEMS in medicine. MEMS have been used for medical in-dwelling pressure sensors for over a decade. More recently, very tiny MEMS pressure sensors have been placed on catheters to measure effects such as the differential pressure across a patient’s heart valves. MEMS accelerometers and rate sensors are used in implantation pacemakers. MEMS devices are also starting to be employed in drug delivery devices for both ambulatory and implantable applications. MEMS electrodes are being used in neurostimulation applications. A variety of biological and chemical MEMS sensors for invasive and noninvasive uses are beginning to be marketed. Lab-on-a-chip and miniaturized biochemical analytical instruments are nearing the market as well. Most of the medical markets are being pursued by smaller companies with some involvement by larger companies such as Medtronic, Abbott Labs, Johnson and Johnson, and Baxter Healthcare. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:49

Page 23.26

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.26

NANOTECHNOLOGY, MEMS, AND FPD

Communications. The applications for MEMS in communications basically fall into two categories—optical telecom and radio frequency (RF). Frequency selective filters using MEMS for cell phones are starting to be marketed and MEMS RF switches for reconfigurable transceivers are expected to hit the market soon. MEMS phase shifters are being explored for low-cost phased-array antennas and show great promise. In optical telecom, a variety of MEMS cross-connect switches, modulators, and attenuators are on the market and many more applications are expected in the future.

23.5 FUTURE TRENDS The future of MEMS comprises higher levels of integration, more functionality for each device, and smaller dimensional scales. As the fabrication capabilities continue to improve, it is expected that it will be possible in the future to easily integrate a multiplicity of different sensor and actuator types on a single slab of silicon with state-of-the-art electronics. This will enable enormous amounts of functionality to be squeezed into a very tiny amount of space and with a very low relative cost. Additionally, we are currently seeing the blending of MEMS and nanotechnolgy, and this will only continue into the future. The size scale of many MEMS devices are continuously reducing due to advancements in fabrication technologies and this fact coupled with the benefits derived from making some things smaller due to the scaling laws (as well as economic forces) will provide a relentless driving force to continuous size reductions. Also, it is becoming evident that the progress of nanotechnology will be very dependent on the developments in MEMS technology, primarily since MEMS offers the only possible interface with the nano world.

23.6 CONCLUSIONS MEMS is revolutionizing the design of mechanical systems through miniaturization, batch fabrication, and integration with electronics. MEMS technology is not about a specific application or device, nor a single fabrication process. Rather, this technology provides new and unique capabilities for the development of smart products for all industrial, commercial, and military applications. While MEMS devices may be a fraction of the cost, size, and weight of the products that incorporate them, they will be critical to their performance, reliability, and affordability. This chapter has reviewed MEMS technology and attempted to present this material from the perspective of the integrated circuit industry. The MEMS industry shares a common ancestry with the integrated circuit (IC) industry but is a much broader and more diverse technology. The diversity, economic importance, and extent of potential applications of MEMS make it the hallmark technology of the future.

REFERENCES 1. Huang, P. H., et al., “Applications of MEMS Devices to Delta Wing Aircraft: From Concept Development to Transonic Flight Test,” AIAA Paper No. 2001-0124, Reno, Nevada, January 8–11, 2001. 2. Bourne, M., “MEMS Update: 2004 Likely to be a Banner Year,” Small Times, July 16, 2004. 3. “Implications of Emerging Micro- and Nanotechnologies,” National Research Council, National Academies Press, 2002. 4. Fishbine, G., The Investor’s Guide to Nanotechnology and Micromachines, Wiley, New York, 2002. 5. Kovac, G. T. A., Micromachined Transducers Sourcebook, McGraw-Hill, New York, 1998. 6. Elwenspoek, M., and R. Wiegerink, Mechanical Microsensors, Springer, Berlin, Germany, 2001. 7. Madou, M., Fundamentals of Microfabrication, CRC Press, Boca Raton, FL, 1997. 8. Gad-el-Hak, M., The MEMS Handbook, CRC Press, Boca Raton, FL, 2002.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:49

Page 23.27

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS

23.27

9. Sze, S., Semiconductor Sensors, Wiley, New York, 1995. 10. Seidel, H., et al. “Anisotropic Etching of Crystalline Silicon in Alkaline Solutions: II, Influence of Dopants,” J. Electrochem. Soc., Vol. 137: p. 3626, 1990. 11. Raley, N. F., Y. Sugiyami, and T. van Duzer, “(100) Silicon Etch-Rate Dependence on Boron Concentration in Ethylenediamine-Pyrocatechol-Water Solutions,” Jo. Electrochem. Soc., Vol. 131: p. 161, 1984. 12. Zwicker, W. K., and S. K. Kurtz, “Anisotropic Etching of Silicon Using Electrochemical Displacement Reactions,” in H. R. Huff and R. R. Burgess (eds.), Semiconductor Silicon, 1973, p. 315. 13. Jackson, T. N., M. A. Tischler, and K. D. Wise, “An Electrochemical p-n Junction Etch Stop for the Formation of Silicon Microstructures,” IEEE Electron Device Letters, EDLM-2: p. 44, 1981. 14. Glembocki, O. J., R. E. Stanlbush, and Tomkiewicz, “Bias-dependent Etching of Silicon in Aqueous KOH,” J. Electrochem. Soc., Vol. 132: p. 145, 1985. 15. Kloech, B., et al., “Study of Electrochemical Etch-Stop for High Precision Thickness Control of Silicon Membranes,” IEEE Trans. Electron Devices, ED-36: p. 663, 1989. 16. McNeil, V. M., et al., “An Investigation of the Electrochemical Etching of (100) Silicon in CsOH and KOH,” Tech. Dig. IEEE Solid-State Sensor and Actuator Workshop, Hilton Head, SC, 1990, p. 92. 17. Howe, R. T., and R. S. Muller, “Polycrystalline and Amorphous Silicon Micromechanical Beams: Annealing and Mechanical Properties,” Sensors and Actuators, Vol. 4: p. 447, 1983. 18. Fan, L. S., Y. C. Tai, and R. S. Muller, “IC-Processed Electrostatic Micromotors,” Presented at the Int. Electron Devices Meeting (IEDM), Washington, DC, 1991, p. 666. 19. Huff, M. A., and M.A. Schmidt, “Fabrication, Packaging, and Testing of a Wafer-Bonded Microvalve,” IEEE Solid-State Sensor and Actuator Meeting, Hilton Head, SC, June 22–25, 1992. 20. Wallis, G., and D. L. Pomerantz, “Field Assisted Glass-Metal Sealing,” J. Appl. Phys., Vol. 40: p. 3946, 1969. 21. Johansson, S., K. Gustafsson, and J. A. Schweitz, “Strength Evaluation of the Field Assisted Bond Seals Between Silicon and Pyrex Glass,” Sens. Mater., Vol. 3: p. 143, 1988. 22. Johansson, S., K. Gustafsson, and J. A. Schweitz, “Influence of Bond Area Ration on the Strength on FAB Seals Between Silicon Microstructures and Glass,” Sens. Mater., Vol. 4: p. 209, 1988. 23. Tiensuu, A. L., J. A. Schweitz, and S. Johansson, “In Situ Investigation of Precise High Strength Micro Assembly Using Au-Si Eutectic Bonding,” 8th International Conference on Solid-State Sensors and Actuators, Transducers, Stockholm, Sweden, June, 1995, p. 236. 24. Editorial, Sealing Glass, Corning Technical Publication, Corning Glass Works, 1981. 25. Besten, C., R. E. G. Hal, J. Munoz, and P. Bergveld, “Polymer Bonding of Micromachined Silicon Structures,” Proceedings of the IEEE Micro Electro Mechanical Systems, MEMS, Travemunde, Germany, 1992, p. 104. 26. Larmar, F., and P. Schilp, “Method of Anisotropically Etching of Silicon,” German Patent DE 4,241,045, 1994. 27. Bhardwaj, J., and H. Ashraf, “Advanced Silicon Etching Using High Density Plasmas,” Proceedings of SPIE, Micromachining and Microfabrication Process Technology Symp., Austin, TX, October 23–24, Vol. 2639: p. 224, 1995. 28. ULVAC, Inc., Technical Data, 2004. 29. Ehrfeld, W., et al., “Fabrication of Microstructures Using the LIGA process,” Proceedings of IEEE Micro Robots and Teleoperators Workshop, Hyannis, MA, November 1987. 30. Menz, W., W. Bacher, M. Harmening, and A. Michel, “The LIGA Technique–A Novel Concept for Microstructures and the Combination with Si-Technologies by Injection Molding,” IEEE Workshop on Micro Electro Mechanical Systems, MEMS, Nara, Japan, 1991, p. 69. 31. Chu, P. B., et al., “Controlled Pulse-Etching with Xenon Diflouride,” Proceedings of Inter. Conf. Solid-State Sensors and Actuators, Transducers, Chicago, IL, June 1997, p. 665. 32. Sedky, S., R. T. Howe, and T. J. King, “Pulsed-Laser Annealing, a Low-Thermal-Budget Technique for Eliminating Stress Gradient in Poly-SiGe MEMS Structures,” J. of Microelectromechanical Systems, Vol. 13 (4): p. 669, August 2004. 33. Xie, H., and G. Fedder, “A CMOS-MEMS Lateral-Axis Gyroscope,” Proceedings of The 14th IEEE International Conference on Micro Electro Mechanical Systems (MEMS ’01), Interlaken, Switzerland, January 2001, pp. 162–165.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH23.qxd

04/04/2005

20:49

Page 23.28

FUNDAMENTALS OF MICROELECTROMECHANICAL SYSTEMS 23.28

NANOTECHNOLOGY, MEMS, AND FPD

34. Mulhern, G. T., D. S. Soane, and R. T. Howe, “Supercritical Carbon Dioxide Drying of Microstructures,” Proceedings of 7th Int. Conf. Solid-State Sensors and Actuators, Transducers, Yokohama, Japan, June 1993, p. 296. 35. Ashurst, R., et al., “Improved Vapor-Phase Deposition Technique for AntiStiction Monolayers,” Proceedings of SPIE—the International Society for Optical Engineering, Vol. 5342 (1): pp. 204–211, Santa Clara, CA, 2004. 36. Maluf, N., and K. Williams, An Introduction to Microelectromechanical Systems Engineering, 2d ed., Artech House, Norwood, MA, 2004, p. 89.

OTHER INFORMATION The reader is referred to three very popular additional sources of information concerning MEMS technology. The first source is a web site called the MEMS and Nanotechnology Clearinghouse, which is located at http://www.memsnet.org and is a general informational portal about MEMS technology and includes events, news announcements, directories of MEMS organizations, and a MEMS material database. The second source is the MEMS Exchange located at http://www.memsexchange.org. This web site represents a large MEMS foundry network and offers MEMS designs, fabrication, packaging, product development, and related services as well as considerable information about MEMS and nanotechnologies. Lastly, the reader is referred to several electronic discussion groups concerning MEMS technology that have very active participation from several thousand MEMS developers and researchers from around the world. These sites can be accessed through the following URL: http://www.memsnet.org/lists/.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 24

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING David N. Liu Electronics Research & Service Organization/Industrial Technology Research Institute Hsinchu, Taiwan, People’s Republic of China

24.1 INTRODUCTION Display has been used in various applications in different industries such as computer, communication, and consumer. It is an interface between human eyes and information. Without display, information is not visible. In addition, display is preferred flat since display space can be limited. Therefore, flat-panel display has become a very important and popular electronic device in the world. The various types of flat-panel displays are classified in Fig. 24.1. Flat-panel displays are classified into two major groups—direct view and projection. The direct view group is typically further classified into emissive and nonemissive subgroups. Plasma display panel (PDP), light-emitted display (LED), flat CRT, and electroluminance display (ELD) are common in the emissive subgroup while liquid crystal display (LCD) and electrophoresis display (EPD) are common in the nonemissive subgroup. The projection group consists of liquid crystal on silicon (LCoS), digital mirror display (DMD), LCD, and cathode ray tube (CRT).

24.2 DEFINITIONS This section defines some of the terminology that is commonly used in various types of flat-panel display. The terminology, structure, and characteristics of various displays will be discussed in this chapter. Alternating current (ac): AC is an approach to operating the display panel. When this approach is used, a dielectric layer is usually needed as part of the panel. Brightness: Brightness is the intensity of the light or image. The unit is nit (or cd/m2) or footlambert (English unit). Candela (Cd): This is a unit of light flux. Cd/m2: This is a unit of brightness.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

24.1

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.2

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING 24.2

NANOTECHNOLOGY, MEMS, AND FPD Display

Direct view

Emissive

Light-emitting display (LE display)

LE diode Polymer light-emitting diode (PLED) Organic light-emitting display (OLED)

Flat CRT

Field emission display (FED)

Spindt FED Carbon nanotube FED (CNT-FED)

Vacuum fluorescent display (VFD) Plasma display panel (PDP)

AC type DC type

Electro luminescent display (ELD)

Thin film Thick film

Nonemissive

Liquid crystal display (LCD) Electrophoresis display (EPD) Others

Projection

Liquid crystal on silicon (LCoS) Liquid crystal display (LCD) Digital micromirror device (DMD) Cathode ray tube (CRT)

FIGURE 24.1

Classification of flat-panel display.

Color filter: A color filter is typically composed of red, green, and blue sections that are able to pass red, green and blue light, respectively. The color filter is popularly used in color LCD displays. Color temperature: Color temperature is used to indicate the position of the curve of a black body for a white color. High color temperature indicates a blue color tendency in the Commission International d’Eclairage (CIE) chromaticity diagram while low temperature indicates a red color tendency in the CIE chromaticity diagram. Contrast ratio: Contrast ratio indicates the ratio of the strongest and the weakest light intensity of a display. The weakest light intensity of a display is very small for a dark room environment. Direct current (dc): The dc mode is an approach for operating a display panel. Direct addressing: This is a technique in which each pixel is directly connected to a driver. Therefore, each pixel needs independent wiring. It is not a practical technique when the pixel numbers are large. Direct view: This mode indicates that a display image is viewed directly without changing the display size. This mode is the opposite of the projection mode. Foot-lambert (fL): A foot-lambert is an English unit of brightness and is defined as lumen per square foot. Full color: Full color is defined as a display with 8 bits (or 256 gray levels) for each red, green, and blue color. Gray level: Gray level is a mechanism of leveling the image intensity between the strongest and the weakest emission for each pixel. Lumen (lm): The lumen is a unit of luminous flux. Lux: Lux is defined as one lumen per square meter. Matrix addressing: Matrix addressing is a technique that uses a row and a column lead to select a pixel. The lead is shared with other pixels. Therefore, this technique is the most commonly applied method for displays using large pixel numbers. Monochrome color: Monochrome color is defined as only one color, which can be green, or red, and so on.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.3

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING

24.3

Multiple color: Multiple color is more than two colors in display. Optical efficiency: Optical efficiency indicates the efficiency of the conversion of electric power to the light output. The typical unit is lm/w. Pixel: A pixel is a picture element that is typically composed of three subpixels—red, green, and blue. Projection: This mode indicates that the image is not directly viewed by the display itself but by a change (usually enlargement) of the display size. This mode is the opposite of the direct view mode. Resolution: This term indicates how display is resolved. The typical unit is ppi (pixel per inch). A high value of ppi indicates that the display has a higher resolution. Thin film transistor (TFT): This is a transistor made on a glass substrate using thin-film technology. It is used in TFT LCD as a pixel switching component so that the display performance can be increased and a higher video content display is possible. Video format: This is used to indicate how many pixels are in a display. Larger pixel numbers for a fixed size of display show a higher capacity of video content. The typical format is VGA (640 × 480), SVGA (800 × 600), and so on.

24.3 WHAT ARE THE FUNDAMENTALS AND PRINCIPLES OF FPD? The major factors for defining the qualities of a display, such as pixel size/resolution, brightness/optical efficiency, contrast ratio, color/gray level, and speed, will be dealt with in this section. The basic structures, characteristics, and benchmarks of various displays will be also discussed later in this section. 24.3.1 What Are Display Qualities? The purpose of this subsection is to discuss the important factors of display qualities. Pixel Size/Resolution. In flat-panel display, a pixel is a picture element that is typically composed of three subpixels—red, green, and blue. The subpixel is typically called a dot. In other words, each pixel usually has three dots. The pixel size is important since it is the smallest picture element. A display composed of many smaller pixels indicates that it is able to generate a relatively fine image. There is a relevant term of display quality related to pixels—display panel resolution. A display panel resolution indicates the number of pixels per inch. For example, a typical display panel resolution of 100 ppi indicates 100 pixels per inch. The pixel size is around 250 µm. Another term associated with pixels is display video format. Display video format indicates the amount of pixels in the display that can be used. For a 15-in display with VGA resolution, the display has 640 × 480 pixels. For the same size of display, more pixel numbers indicate that a more detailed image can be displayed. Brightness/Optical Efficiency. Brightness is the intensity of the image. The unit of brightness generally used is a nit (or cd/m2) or foot-lambert. The typical brightness value of flat-panel display is 500 cd/m2 for TV and 250 cd/m2 for monitor applications. Optical efficiency (OE) is defined as OE =

brightness or luminance power

A higher value of OE is needed because it indicates a higher brightness with less power. The typical optical OE value of flat-panel display is 5 lm/w.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.4

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING 24.4

NANOTECHNOLOGY, MEMS, AND FPD

Contrast Ratio. There are two major contrast ratios—one is the dark-room contrast ratio and the other is the bright-room contrast ratio. The dark-room contrast ratio (DCR) is defined as DCR =

on-pixel brightness off-pixel brightness

On-pixel and off-pixel brightness are defined as the brightness due to pixel turning on and off, respectively. The brightness must be (and usually is) very small so that the DCR can be large. A large value of DCR indicates a good contrast ratio of a display. The typical DCR value is 1000:1. However, ambient brightness is an additional important factor that affects the contrast ratio in practical use. This contrast ratio is called the bright-room contrast ratio (BCR). BCR is defined as BCR =

on-pixel brightness + ambient brightness off-pixel brightness + ambient brightness

The value of DCR is usually higher than BCR because the ambient brightness in BCR is usually higher than the off-pixel brightness. The typical BCR value is 30:1. Color/Gray Level. All flat-panel displays are able to display either monochrome or multiple colors. Chroma indicates the saturation degree of a color either from monochrome or multiple colors. A typical color display is composed of three basic colors (red, green, and blue). In other words, the display is able to display various colors using these three basic colors. It is also important to know the chroma values of these red, green, and blue colors since the maximum of color capacities is determined by these values. This indicates that a higher saturation of basic colors has a higher capacity of image colors to display. A white color is composed of three colors—red, green, and blue. A different color temperature occurs due to the different color intensities of the red, green, and blue colors. The color temperature is higher when the color blue is rich, and it is lower when the color red is rich. However, the white color should be used to follow the curve of the white balance (black-body curve) in the chromaticity diagram. The color temperature is typically designed in the range of 6500 to 11000°C. Gray level is a mechanism of leveling the image intensity between the strongest and the weakest emission for each pixel. More gray levels generate more levels of image intensity. For a typical flatpanel display, 256 gray levels (full color) are usually applied. Speed. A typical display image is designed with less than 60 frames per second (16 ms per frame) so that most human eyes can observe the image properly. Therefore, each frame must be completed within 16 ms. For a display with a large video content, the time sharing of each pixel will be very limited. Therefore, the response time of each pixel to turn on or off is very important for a display. If the pixel needs a long response time, it will not be possible to display a large video content. The response time is particularly important for the application of motion picture display. The response time of LCD is relatively slow—around 1 to 10 ms. Other displays of response time, such as PDP, organic LED (OLED), and field emission display (FED), are around the microsecond scale or less. Addressing. Direct and matrix are two common types of addressing techniques in flat-panel displays. Direct addressing is a technique in which each pixel is directly connected to a driver. A pixel is selected by an independent lead that is not shared with other pixels. Therefore, this technique is limited for displays with small pixel numbers, such as a display of a few alphanumeric characters. Matrix addressing is a technique that uses a row and a column lead to select a pixel. The lead is shared with other pixels. As a certain row is selected via electronic scanning, a bench of display data is sent to all columns. The pixels are therefore displayed. Compared with direct addressing, the number of leads is reduced. Therefore, the matrix addressing technique is the most commonly used method for displays with large numbers of pixels, such as graphic display. Passive matrix and active matrix are two major types of matrix addressing techniques. The passive matrix type applies passive components while the active matrix type applies active components for pixel switching. By using the active component, the active matrix technique is able to

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.5

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING

24.5

increase the pixel performance. Higher quality or higher video contents of display are used in this addressing technique. 24.3.2 Basic Structures and Characteristics of Various Displays Many different flat-panel displays are emerging, and we will discuss as many displays as possible in this subsection. The displays that will be discussed are LCD, PDP, OLED, FED, LCoS, and DMD. The main direction of the discussion will be the basic structure and characteristics of these displays. LCD. LCD is the most commonly used flat-panel display currently. The operational principle of LCD is the use of an electric field to control the liquid crystal (LC) molecular arrangement. The pass percentage of light to the viewer is determined by different LC molecular arrangements. Some LCs need polarizers to control the light output properly. Since LCD is a nonemissive display, a backlight source is needed for the transmissive type. For color LCD, a color filter is typically needed for most types of LCs. The most popular LC in flat-panel display is the nematic-type LC. When a higher image quality or larger video content is applied, transistors in pixels become necessary. An LCD with a transistor in each pixel is called a TFT LCD and is popularly used in most commercial personal computers. The cross section of a typical transmissive type of TFT LCD is shown in Fig. 24.2. In the figure, a spacer is needed to keep the distance between the upper plate (color-filter substrate) and lower plate (TFT-array substrate) so that there is space for LC molecules to be arranged. The space is typically 2 to 4 µm. Alignment layers are used to align the LC molecules in a certain orientation. A storage capacitor helps to store voltage so that the LC has enough voltage to be arranged properly. A black matrix is used to cut off some of the ambient light so that the contrast ratio is increased. The pixel electrode connects the TFT and LC parts and the common electrode connects the LC part to ground via a “short.” The reflective type of LCD is used commonly in portable devices because it consumes less power than the transmissive type of LCD. For this type of LCD, a backlight is not needed and ambient light is the light source for display. A reflective layer is usually additionally needed and implemented in the lower plate (TFT-array substrate). In addition, there are two common types of transistors that are used in each pixel of TFT LCD. One is amorphous silicon (a-Si) TFT. The other is low temperature polysilicon (LTPS) TFT. Since LTPS TFT has naturally higher mobility than a-Si TFT, the TFT size is smaller for LTPS TFT. Therefore, LTPS TFT LCD has a higher aperture ratio and brightness. In addition, LTPS is able to integrate discrete integrated circuits (ICs) such as digital analog converter (DAC), memory, timing circuit, and so on into the panel. The time stability of LTPS TFT is also superior to a-Si TFT. However, LTPS TFT has relatively poor uniformity compared with a-Si TFT, particularly in large displays.

Spacer

Black matrix

Polarizer Color filter substrate ITO Seal Short

Color filter TFT

L /C

Alignment layer ITO

TFT-array substrate Polarizer Backlight FIGURE 24.2

A typical structure of transmissive type of LCD display panel.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.6

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING 24.6

NANOTECHNOLOGY, MEMS, AND FPD

PDP. The PDP operational principle is similar to that of a fluorescent lamp. They both use a gas discharge mechanism. The gas discharge generates ultraviolet (UV) light. The gases most commonly used in fluorescent lamps are mercury and argon while those most commonly used in PDPs are neon and xenon. The UV wavelength is typically 254 nm for fluorescent lamps and 147 nm/173 nm for PDPs. The wavelengths of 147 nm /173 nm are called vacuum UV (VUV) and do not exit in air. RGB phosphors in PDP are excited by UV. There are two types of PDPs. One is the dc-type PDP and the other is the ac-type PDP. Since ACPDP has a longer life and higher performance, it is the most popular PDP used in the market. The typical structure of ACPDP is shown in Fig. 24.3. In the figure, the rib is very important since it serves not only as the spacer between the upper and lower plates but also as crosstalk isolation among R, G, and B. The rib height is typically hundreds of micrometers. MgO is most commonly used for the protection layer because it is a good material for ion bombardment and has a higher secondary electron emission. These characteristics of MgO help the PDP to have a longer life and lower the operation voltage. The dielectric layers used in both the upper and lower plates serve as capacitance as ac power is applied. A surface discharge mechanism in PDP is commonly used and successfully keeps the plasma on the surface of the upper plate so that the plasma will not damage the phosphor that is located in the lower plate. Therefore, the display life can be extended. However, for the surface discharge type of PDP, the arrangement of electrodes is critical. The electrode in the upper plate should preferably be as transparent as possible because most of the area of the upper plate is occupied by electrodes. Therefore, indium tin oxide (ITO), being a transparent conductive material, is commonly used. However, the conductivity of ITO is not as high as that of a typical metal. A conductive metal with an electrode of relatively small linewidth is applied to the ITO electrode so that the electrode conductance is increased. The metal electrode on the ITO electrode is called the auxiliary electrode or bus electrode. PDP has a high quality of picture and simple manufacturing process steps. The need for highvoltage driving (typically 200 V) is the main drawback affecting the cost and the application. OLED. The operational principle of OLED is the use of electron and hole injections into the luminance layer to generate light. Since the luminance layer is an organic material, the display is called OLED. OLED is a solid state display and does not comprise vacuum, liquid, or gas. Therefore, the structure is relatively simple compared with other displays. There are two types of OLED—small molecular OLED and polymer OLED (PLED). Small molecular OLED uses small molecules of luminance material that are typically deposited by vacuum evaporation. PLED uses polymers of luminance materials that are typically deposited by spin coating or ink-jet printing. The most commonly used approach to form a pattern of color OLED is the shadow mask approach. Another approach is ink-jet printing. In order to have a higher performance of OLED, TFT is additionally used. The typical structure of TFT OLED is shown in Fig. 24.4.

Auxiliary electrode

Transparent electrode Upper plate Dielectric layer Protective layer Plasma UV

Barrier rib Phosphor Dielectric layer Lower plate

Address electrode FIGURE 24.3

A typical structure of ACPDP display panel.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.7

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING

24.7

Cathode (Al)

Emitting layer

Anode (ITO)

Passivation layer

Bus line

Inter-layer Light output Dielectric TFT

FIGURE 24.4

Glass substrate

A typical structure of TFT OLED display panel.

In the figure, aluminum (Al) is used as the cathode and ITO as the anode. The emission is bottom emission (downward emission) since Al (topmost) is reflective and nontransmitting. The typical material of the emitting layer is Alq3 for the small molecular type of OLED and polyphenylene vinylene (PPV) for the polymer type of OLED. Top emission is another approach of emission in which the anode serves as a reflective layer and the cathode should be as transparent as possible. The material selection of electrodes in the top emission approach is critical. However, the aperture ratio for top emission is higher than for bottom emission. The pixel arrangement for the top emission approach is more flexible than for bottom emission. Although OLED has all the good characteristics of display technology, such as high optical efficiency, simple manufacturing process steps, and low voltage drive, the major drawback of OLED is a short lifetime that is typically less than 5000 h for color OLED applications. FED. FED is a display using electrons of field emission to excite phosphors and generate luminance. Field emission uses a high electric field rather than the thermionic approach to extract electrons in vacuum. There are many types of FEDs. Spindt-type (sharp-cone-type) FED was intensively studied several years ago. As the evaporation needed to form the sharp-cone emitter is difficult in displays with large areas and the uniformity of the sharp-cone emitter is also poor, most researchers of Spindt-type FED have shifted to research of carbon nanotube (CNT) FED and other approaches of FED. The typical structure of CNTFED is shown in Fig. 24.5. In the figure, electrons are emitted from the CNT material and excite RGB phosphors. The space between the upper and lower plates is typically from hundreds to thousands µm. CNT as an emitter is the most promising approach to FED display in the last few years.

Upper plate Anode (ITO) Phosphor e− Gate (Ag) Dielectric CNT emitter Cathode (Ag) FIGURE. 24.5

Lower plate A typical structure of CNTFED display panel.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.8

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING 24.8

NANOTECHNOLOGY, MEMS, AND FPD

Glass substrate ITO electrode Alignment layer

Liquid crystal

Reflective electrode Wiring Capacitor Silicone substrate Source Gate Drain FIGURE 24.6

A typical structure of LCoS display panel.

Although FED has CRT-like picture quality and high optical efficiency, one of the major drawbacks of FED is the poor emission uniformity. LCoS. LCoS is a projection display combining LC and semiconductor technologies. The lower plate including the TFT is made on silicon wafer. Therefore the TFT can be made as small as typical semiconductor devices, and the resolution of the display can be as high as possible. In addition, the TFT mobility is the same as a single crystal since the TFT is made on a silicon wafer. The typical structure of LCoS is shown in Fig. 24.6. As the figure shows, the upper part is a typical LCD structure that is made on a glass substrate. The lower part is a typical TFT structure but is made on silicon wafer. The reflective electrode is needed to reflect light. The pixel size can be made as small as 10 µm. The die size of the lower plate is designed as 1 in. Therefore, an HDTV format (1920 × 1080) is easy to implement. LCoS displays can be of the single panel or three panel type. The panel size is typically 1 in. The cost of singlepanel type LCoS is lower. However, the technology barrier is higher. DMD. DMD is another popular type of projection display. This kind of display uses many digital mirrors to reflect light. By using proper voltage, every single mirror can be tilted so that the light hitting each mirror can be deflected individually. The typical structure of DMD is shown in Fig. 24.7.

Mirror

Mirror (a) Top view FIGURE 24.7

Substrate with various electrodes (b) Side view

A typical structure of DMD display panel.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.9

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING

24.9

The DMD panel is made of silicon wafer. Using a proper silicon machining approach, many mirrors and certain electronics are formed inside the silicon wafer. After these components are formed, a silicon wafer cover is used as a seal so that a DMD panel is completed. The major challenge of the DMD device is to manufacture it with high yield since the device includes complex electronics with lots of mirrors. 24.3.3 Benchmarks of Various Displays In this subsection, various displays will be discussed. Although there are many different advantages of different displays, certain disadvantages are common. Table 24.1 shows the benchmarks of various displays. Although LCD needs many components, such as backlight, color filter, polarizer, and so on compared with other displays, the manufacturing cost has been significantly reduced due to mature technology and large scale mass production. In addition, other traditional disadvantages, such as low view angle and long response time, are improving gradually. PDP has two fundamental drawbacks: large pixel size and high voltage driving. However, as PDP is applied in large-sized displays, the drawback of large pixel size is significantly reduced. OLED is a kind of solid state display that has no need of vacuum, liquid, or gas inside the device. It also has the advantage of high optical luminance and self-emission. However, OLED at present has a short lifetime. FED is generally believed to have a CRT-like quality with flat characteristics. However, the emission uniformity has not significantly improved during the last few years. Besides, its color lifetime is not long enough. Single panel LCoS will be very competitive in terms of cost. Single panel DMD has been cost and space effective. For a projection application using either LCoS or DMD, the projection size can be conveniently adjustable based on the user needs. For flexible display, various types of displays such as cholesteric LCD, polymer-dispersed microencapsulated liquid crystal display (PDMLCD), electrophoretic display (EPD), are emerging. Cholesteric LCD uses cholesteric material as the display medium, which has good characteristics in bistable and color but it is poor in contrast ratio. PDMLCD uses an LC droplet surrounded by a TABLE 24.1 Benchmarks of Various Displays Advantage

Disadvantage

Application size

Technology status

LCD

• Technology mature and low cost • Low voltage drive • Low power consumption • Long life time

• Needs many components (backlight color filter polarizer, and so on) • Limited view angle and operation temperature • Relatively long response time

• < 80 in

• Large scale mass production

PDP

• Easy to scale-up size • High picture quality • Fewer process steps (thick-film process)

• High voltage driving • Pixel size

• < 40–80 in

• Mass production

OLED

• High optical efficiency • Relatively simple process • Low voltage drive

• Short life time • Not easy to scale-up size

• < 20 in

• Production

FED

• CRT-like picture quality • High optical efficiency

• Poor emission uniformity • Short color FED lifetime

• < 40–80 in

• R/D

LCoS

• High resolution • Low cost of one panel type • Projection size adjustable

• High cost of three-panel type • Low yield

• > 100 in

• Production

DMD

• High response time • High resolution • Projection size adjustable

• High cost • Complex device process

• > 100 in

• Production

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.10

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING 24.10

NANOTECHNOLOGY, MEMS, AND FPD

polymer film. The microencapsulated liquid-crystal droplets improve the contrast ratio. The mechanism of EPD uses the transport of charged pigment particles in a colloidal suspension to form a display. The response time of EPD is one of the major challenges for the future. The mechanism of Gyricon display uses bichromal balls to display. The major drawback of Gyricon display is the poor contrast ratio.

24.4 WHAT IS THE MANUFACTURING PROCESS? FPD manufacturing needs two plates (the upper and lower plates) at the beginning of the process. These two plates are aligned and sealed followed by electronic board/film bonding and mechanical assembly. Before shipping, aging and a series of tests are also performed in order to make sure that the display is sound and reliable. Among the various displays, TFT LCD is the most popular information display. The process flow of typical TFT LCD manufacturing is shown in Fig. 24.8. The process starts with TFT array and color filter glasses. The structures of the TFT array and color filter glasses are shown in Fig. 24.2. The TFT array glass is processed not only by the transistor process but also by the LC alignment layer process and spacer spray. The color filter glass is not only processed by the color filter process but also the LC alignment layer process. The two plates are then aligned and sealed. LC is injected and the end seal is performed. After that, a polarizer is attached and the tape carrier package (TCP) is bonded. The next steps performed are electronics, backlight, and chassis assembly. Aging and various tests are performed in between so that display panel performance and reliability are confirmed. Since different displays have different processes, we are not able to discuss the detailed process for each display in this chapter. However, most processes of displays use thin- film, thick-film, and cell-formation processes, aging, and tests. Therefore, in the following sections we will discuss these processes separately. 24.4.1 Thin-film Processes Thin-film processes normally consist of deposition, photolithography, and etching techniques. Sputter, evaporation, and chemical vapor deposition (CVD) are the common techniques for deposition. The photolithography system includes a PR coater, exposure system, developer, and stripper while the etching system includes dry and wet etchers. TFT processes of TFT LCD and TFT OLED use thin-film processes. The backplanes (lower plates) processes of LCoS and DMD, and part processes of OLED use thin-film processes too. 24.4.2 Thick-film Processes Deposit and cure systems are two common types used in thick-film processes. Screen printing and ink-jet printing to deposit a paste or slurry are very common techniques for the deposit system, while a furnace is the equipment typically used to cure the paste or slurry. Most processes of PDP and FED, and part processes of OLED, use thick-film processes. 24.4.3 Cell Formation Processes At the beginning of cell formation processes, sealing material is dispensed on the plates. Alignment between the two plates follows. With proper curing of the sealing material, the cell is formed. Most of various displays use these processes for cell formation. 24.4.4 Aging and Testing Processes Aging is very important. Using this process, the device can be stabilized and its reliability can be assured. Testing is performed to sort out not a good (NG) panel so that it will not leak NG panel to next steps. Most of the various displays need these processes to control their quality and reliability. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.11

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING

TFT array glass

Color filter glass

LC alignment layer and spacer spray

LC alignment layer

Cell alignment and sealing

LC injection

End seal

Polarizer attachment

TCP bonding

TEST

Repair

NG

YES Repair

Electronics assembly

TEST

NG

YES Backlight /chassis assembly

TEST

Repair

NG

YES Aging

Final test

NG

YES Shipping FIGURE 24.8

Process flow of typical TFT LCD manufacturing.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

24.11

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.12

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING 24.12

NANOTECHNOLOGY, MEMS, AND FPD

24.5 FUTURE TRENDS AND CONCLUSIONS In this section, we will discuss future trends in two aspects of flat-panel display (FPD): technology and applications, and make concluding remarks. 24.5.1 Technology Trends Although there are many technologies emerging, we will list the most common trends in this subsection. Table 24.2 shows the technology trends of flat-panel display. There are two approaches for reaching large display sizes. One is by direct view and the other is by projection. The direct view approach typically provides a higher contrast ratio than the projection approach. However, in the projection approach, it is easy to scale up the display size compared with the direct view approach. Undoubtedly, high image quality is the continuous goal for the development of flat-panel display. The factors affecting image quality are pixel size/resolution, brightness/optical efficiency, contrast ratio, color/gray level, and speed, which we have discussed in a previous section. Driver number reduction and production scale up are two major ways to reduce cost. LTPS is one of the approaches for reducing the driver cost. This is because the high mobility of LTPS enables the integration of drivers and most discrete integrated circuits (ICs) into the display panel. The cost is therefore reduced. One of the most exciting future trends is the need for light and flexible displays. Flexible displays will be needed because this kind of display can be applied on nonflat backgrounds. In addition, flexible display can be manufactured using a roll-to-roll process so that a large scale of mass production is easy and possible. The manufacturing cost is therefore significantly reduced. 24.5.2 Application Trends It is obvious that FPD has various applications since each kind of FPD has features that are suitable for different applications. Table 24.3 shows the application trend of flat-panel display, which is classified according to the display size. TABLE 24.2 Technology Trends of Flat-Panel Display Item

Specification Front

100" ~ 200"

Rear

40" ~ 80"

Direct view

40" ~ 80"

PDP

10.4" ~ 50"

a-TFT LCD, CNT FED

Large

Display quality

Cost-effective

Relevant tech.

Projection

LCoS, DMD

Pixel size/resolution

SVGA → UXGA/HDTV

LTPS, LCoS

Brightness/optical efficiency

150cd/m →  500cd/m

LTPS, Super-IPS (In Plane Switch), VA (Vertical Alignment)

Contrast ratio

100:1 →  500:1

Super-IPS, VA

Color/gray level

260 K → 16700 K gray level

Driving

Speed

40 ms → 25 ms →  8 ms

LC material, driving

2

2

Driver reduction

LTPS

Production scale

Mass production

Light/flexible

Semi/reflective, plastic substrate, flexible substrate, COG, SOP

OLED/reflective LCD

Ecology

Power consumption, production waste reduction

Design/process improvement

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.13

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING

24.13

TABLE 24.3 The Application Trend of Flat-Panel Display Size

Major technologies

Application

Large size (30~300 in)

• a-Si TFT LCD • PDP • Micro Display (LCoS, DMP)

• Wall-mounted TV (direct view) • Desktop TV (direct view) • Front projection • Rear projection

Medium size (8~30 in)

• a-Si TFT LCD

• Monitor • NBPC • E-book • Flexible display

Small size (below 8 in)

• a-Si TFT LCD • LTPS • STN/TN • OLED • VFD • FED

• Mobile phone • View finder • PDA • Virtual reality • Flexible display

The display size is an important factor in deciding the applications of the display technology. LCD is the most popular flat-panel display in the existing market. The display size of LCD ranges from less than 1 in to more than 30 in. Therefore, the application of LCD is wide and sophisticated. At present, OLED is available only in small display sizes due to its technical limitations. The application is used in mobile phone display. PDP is for display sizes of 40 to 80 in. Its major applications are TV and small meeting room display. Projection display is generally used in screen sizes above 100 in. Its applications include large meeting room display.

24.5.3 Conclusions Among the various display technologies, LCD apparently has become the main stream of flat-panel display technology in the past years. One of the reasons is that LCD has no fatal drawback although it has many weaknesses. In addition, these weaknesses, such as view angle limitation, high cost, and low response time have been solved or improved in the past few years. OLED certainly has a reasonable chance to become popular in the near future due to its better performance in many aspects compared to other displays. However, the OLED lift time needs to be significantly improved first. PDP is practically positioned for display sizes larger than 40 in because of its relatively large pixel size. However, the cost and performance advantages of PDP today compared with LCD may challenge LCD in the future. We believe no display can exist in the market forever. Therefore, display performance and low cost will continue to be very important in the future.

FURTHER READING Castellano, J. A., Handbook of Display Technology, Academic Press, CA, 1992. Hatalis, M. K., et al., “Flat Panel Display Materials II,” Material Research Society, PA, 1997. Jensen, K. L., “Electron-Emissive Materials, Vacuum Microelectronics and Flat-Panel Displays,” Material Research Society, PA, 2000. Keller, P. A., Electronic Display Measurement: Concepts, Techniques, and Instrumentation, Wiley, New York, 1997. MacDonald, L. W., and A. C. Lowe, Display Systems: Design and Applications, Wiley-SID, New York, 1997. Matsumoto, S., Electronic Display Devices, Wiley, New York, 1991. Nelson, T. J., and J. R. Wullert, “Electronic Information Display Technologies,” World Scientific, 1997. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH24.qxd

04/04/2005

20:50

Page 24.14

FLAT-PANEL DISPLAY TECHNOLOGY AND MANUFACTURING 24.14

NANOTECHNOLOGY, MEMS, AND FPD

O’Mara, W., Liquid Crystal Flat Panel Displays: Manufacturing Science and Technology, Van Nostrand Reinhold, New York, 1993. Refioglu, H. I., Electronic Displays, IEEE Press, New York, 1983. Sasaki, A., and C. J. Gerritsma, Optoelectronics, Vol. 7 (2), Mita, Tokyo, 1992. Sherr, S., Electronic Displays, 2d ed., Wiley, New York, 1993. Stokes, A., “Display Technology: Human Factors Concepts,” Society of Automotive Engineers, 1998. Tannas, L. E., Flat-Panel Displays and CRTs, Van Nostrand Reinhold, New York, 1985. Weston, G. F., and R. Bittleston, Alphanumeric Displays, McGraw-Hill, New York, 1982. Whitaker, J. C., Electronic Display: Technology, Design and Applications, McGraw-Hill, New York, 1994. Wu, S. T., and D. K. Yang, Reflective Liquid Crystal Displays, Wiley-SID, New York, 2001.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

P

●

A

●

R

●

T

●

5

GASES AND CHEMICALS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.2

GASES AND CHEMICALS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.3

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 25

SPECIALTY GAS AND CDA SYSTEMS Wayne D. Curcie Infineon Technologies Sandston, Virginia

25.1 INTRODUCTION Specialty gases are commonly defined as the process gases supplied from cylinders. This is in contrast to bulk gases such as nitrogen, oxygen, argon, and hydrogen that are provided via pipeline, generated on-site, or delivered in bulk and supplied from cryogenic storage tanks. As is the case with many critical process support systems, the purpose of specialty gas systems is the safe, reliable, consistent, and cost-effective supply of the required quality product to the manufacturing processes. Implementation of a successful specialty gas supply involves the understanding and execution of several interdependent activities. Figure 25.1 illustrates some of the basic implementation elements. While it may be obvious that the process needs (e.g., moisture, particles) directly influence the cylinder gas specifications, other decisions will also influence the product purity (e.g., gas cabinet design—filtration and purification, cylinder change procedures, tubing specification, system commissioning process). The specialty gas supply design will also be impacted by the interactions and trade-offs among the project budget, distribution concepts (e.g., coaxial versus single-walled tubing), code requirements, industry practices, and site preferences. This chapter looks at the elements shown in Fig. 25.1, beginning with the identification of the process requirements and cylinder gases specifications. The following sections provide an overview of code requirements and industry practices, describe the specialty gas equipment and distribution design considerations, explain the execution aspects including strategic planning, design, commissioning, operations, and maintenance, and conclude with future trends.

25.2 SEMICONDUCTOR MANUFACTURING PROCESS REQUIREMENTS Definition of the manufacturing process and equipment needs is essential to the design of the specialty gas systems. The initial information required to design specialty gas systems is similar to other process support systems; however, the ever-changing nature of semiconductor processes makes this more dynamic and challenging. The following information is necessary to begin the development of a specialty gas system:

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

25.3

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.4

SPECIALTY GAS AND CDA SYSTEMS 25.4

GASES AND CHEMICALS

Process needs

Gas characteristics

Cylinder gas product specifications

Equipment and distribution design

- Codes - Risk assessment - Local considerations - Industry practice

Budget and schedule Installation and comissioning

Operation and maintenance

FIGURE 25.1

• • • • • • •

Specialty gas supply execution process.

Tool name and process(es) Number of tools Process area Gases Gas purity Flow range (minimum, maximum, and average consumption) Pressure

This information provides an impression of the gas usage by the process area and total gas cylinders required. In conjunction with a building code assessment (see Sec. 25.3), it provides insight into the location and sizing of the gas rooms. This process information also provides insight into the initial gas equipment and distribution requirements (see Sec. 25.4), and the feasibility of bulk specialty gases. A wide variety of specialty gases are used in the manufacture of semiconductor devices. Table 25.1 includes a sampling of common gases with their basic properties and typical applications. The characteristics of these gases vary dramatically from inerts to corrosive liquefied gases and pyrophorics (spontaneously flammable and may form explosive mixtures with air). An understanding of the specific characteristics of each gas is essential to the design and operation of specialty gas systems.1–3 Process information is also used to make operational decisions such as: • Cylinder gas purity specifications • Cylinder material, preparation, and cleaning requirements • Gas cylinder sizes

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.5

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.5

TABLE 25.1 Typical Semiconductor Process Gases Hazardous properties Gas Description

Formula

HPM (per NFPA 704)

Ammonia

NH3

Yes

Freon 14

CF4

Freon 23 Krypton/neon Hydrogen bromide Nitrogen triflouride Nitrous oxide

Silane Tungsten hexafluoride *

Classification

Physical properties Cylinder state at 70°F Liquid

No

Flammable, corrosive, low toxicity Inert

CH3F Kr/Ne HBr NF3 N2O

Yes No Yes No Yes

SiH4 WF6

Yes Yes

Cylinder pressure* at 70°F

Applications

114

Diffusion LPCVD, PECVD

Gaseous

2000

Flammable Inert Corrosive, toxic Oxidizer, low toxicity Oxidizer

Liquid Gaseous Liquid Gaseous Gaseous

611 2000 301 1450 766

Pyrophoric, flammable Corrosive, toxic

Gaseous Liquid

1260 2.44

Etch, films, dry plasma etching Etch Litho, laser gas Etch Etch, films Diffusion, films, silicon nitride layer formation LPCVD, PECVD LPCVD tungsten

Gaseous cylinders pressures are based on standard fill volume.

Cylinder gas purity specifications should take into consideration the concentrations of specific contaminants of concern. Cylinder specifications should include the maximum allowable concentration of these substances (e.g., moisture in HBr) with certificates of analysis. Restrictive flow-orifice sizing will need to consider the equipment demands as well as the cost and feasibility of release abatement. Gas cylinder size selections often represent trade-offs between anticipated usage, shelf life, code storage limitations, and cost. Additional information will be required for subsequent project phases, including: • Tool layout • Tool gas connection type and size • Tool configuration (e.g., number of connections and external gas box needs) Typically the challenges in defining the process gas requirements are not due to a lack of information, but rather the quality and management of the information as the process evolves. Actual gas consumption rates and peak flows can be significantly less than the vendor stated requirements that may simply be the maximum rated flow of the mass-flow controller. For critical applications, a more detailed analysis of the process recipes, throughput, and utilization may be necessary. The nature of device manufacturing is such that the process needs will continually change. Therefore, process needs must be regularly verified, particularly at critical project phases (e.g., equipment purchase, installation). Changes must be assessed and reflected throughout the specialty gas systems (e.g., the potential impact to cylinder gas purity specifications, codes, gas equipment, distribution, and gas room layouts).

25.3 CODE REQUIREMENTS AND OTHER GENERAL DESIGN CONSIDERATIONS With an understanding of the process gases required, their specific properties, and a code analysis, a general outline of the gas systems is possible. Layouts and designs of specialty gas systems must involve a thorough and careful examination of the applicable national and local codes (e.g., BOCA, UFC, NFPA, IBC, TGO),4–9 in addition to such other considerations as accepted guidelines (e.g., FM),10,11 industry practices, site risk assessment, and site specific issues.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.6

SPECIALTY GAS AND CDA SYSTEMS 25.6

GASES AND CHEMICALS

It may be helpful to understand the mission of the various codes and guidelines. For instance, the primary objective of most codes (e.g., BOCA, UFC, and IBC) is to protect personnel. Guidelines such as Factory Mutual Global are directed more toward fire prevention and property preservation. This section is not intended to provide a comprehensive summary of the code requirements as these vary geographically, tend to change, and are subject to interpretation based on the specific site conditions and risk assessment. The purpose of this section will be to provide an overview of a typical US fab specialty gas system with focus on industry codes and guidelines. Most manufacturing facilities (fabs) are arranged with the production equipment or tools in a class M100 to M1 (Federal Standard 209E or ISO 14644-1) cleanroom (see Fig. 25.2,). Directly underneath (or beside in the case of some older fabs) this production area is a return air space and/or production support space (subfab). The production support space contains chillers, vacuum pumps, abatement units, power panels, and other equipment. It may also serve as a return air path for the recirculating cleanroom air. Additional support space may be located beneath or beside the subfab level. Site specific conditions and code requirements will influence the arrangement of the production, support, and return air spaces. This in turn will influence the location of the specialty gas rooms, cabinets, and valve manifolds. An important first step is to classify and quantify the process gases required. Semiconductor gases are typically classified and separated into several categories: 1. 2. 3. 4. 5. 6.

Pyrophorics Toxics and highly toxics Flammables Corrosives Oxidizers Inerts Recirculating air ULPA filters (fan tower units not shown)

Fan filter units FAB level

FAB level production equipment VMBs, VMPs, liq. gas cabinets

Raised floor Waffle deck

Raised floor Subfab level

Concrete deck

Production support equipment Concrete deck Gas rooms

Subfab support rooms support equipment

Support level support equipment

Gas rooms

Building section view Toxic & Corrosive & flammable oxidizer gas room gas room

Inert gas room

Support areas

Production cleanroom area (Subfab level beneath with VMBs, VMPs, liq. gas cabinets)

Support areas

Bulk specialty gases pyrophorics

Support areas Building plan view

FIGURE 25.2

Fab general arrangement.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.7

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.7

Within these categories it is important to identify the hazardous gases (otherwise referred to as hazardous production materials (HPM), and defined per BOCA 416.2 as a solid, liquid, or gas that has a degree of hazard rating in health, flammability, or reactivity of class 3 or 4 per NFPA 704). In the case of high-volume fabs, an additional category or subcategory for bulk specialty gases may be useful. Specialty gases will be located based on their hazard levels, quantity, and classification of the space. Most production areas are classified as HPM fabrication areas. The codes specify the allowable quantities of hazardous gases within an HPM (or H6) classified area (that is the fab cleanroom and often subfab area). Certain conditions must be met to achieve this classification (such as automatic sprinkler systems, sufficient protected egress, fire rated construction, minimum ventilation rates, smoke detection, and continuous gas detection). Typically, the limited quantity allowed in the HPM production area is dedicated to liquefied, low vapor pressure gases that are more easily supplied close to their point(s) of use. Separate HPM gas rooms enable the storage of larger quantities of HPM gases. Separate rooms are typically provided for toxic and flammable, and corrosive and oxidizing gases. These rooms are referred to as HPM cutoff rooms by code and are generally located along an exterior wall and separated from the HPM fabrication area (fab cleanroom and subfab) by fire rated construction (e.g., walls, doors, and sealed penetrations). The placement of these rooms also involves the consideration of logistics such as material delivery and transport. HPM gas rooms are typically provided with: • Automatic sprinklers • Two means of egress, one to the outside • Minimum ventilation rate (one cubic foot per minute per square foot of room area (cfm/sf), or six air changes per hour (ac/h)) • Smoke detection • Continuous gas detection • Treatment of exhaust to 1/2 IDLH (immediately dangerous to life and health) and catastrophic release • Standby power for exhaust ventilation, abatement, gas detection, and emergency alarm systems. Flammable gas rooms are generally designed with explosion venting along an exterior wall and may be rated class 1 division 2 (per NFPA 70). Inert gas supplies may be located in the subfab, a separate inert room, or combined with other gases in an HPM cutoff room. Pyrophoric gases may be stored in cabinets or racks and located in a separate remote structure (FM 7-7)10 or a separate HPM cutoff room. Bulk specialty gases may be placed in their respective HPM gas rooms, or a remote location (refer to Fig. 25.2). Their location will generally be a function of the gas type, size, and space and access constraints. HPM gas cabinets typically include the following features: • A 12-gauge metal exhausted enclosure with self-closing and latching door and exhaust monitoring • Continuous gas detection interlocked with a gas isolation valve to automatically shut down gas flow and alarm to a central, continuously manned location • Internal class 1 division 2 rating • Excess flow and over pressure protection • Seismic restraint (depending on location) • Internal fire sprinkler for toxics and flammables • Purge gas from a cylinder source • Connection to a standby power source HPM gas distribution panels (e.g., valve manifold boxes) are not specifically addressed in the codes. The codes do specify several operational items such as leak testing, signage, cylinder transport, material safety data sheets, emergency response capabilities, and other requirements. It is important to recognize that while the features described here are “typical,” actual practices can vary dramatically, particularly outside the United States. Consider for instance the use of coaxial

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.8

SPECIALTY GAS AND CDA SYSTEMS 25.8

GASES AND CHEMICALS

tubing, which though not required by the national code, is recommended for pyrophoric, flammable, and toxic gases (FM 7-7) and widely used in the United States. Its use is less common outside the United States. Even within the United States, some HPM gases are not double contained based on a risk assessment and other factors. For instance, gases such as hydrogen and methane may not always be distributed in coaxial tubing as long as the piping is metallic with all welded connections and any mechanical connections are in exhausted enclosures with exhaust monitoring and gas detection. Further guidance regarding the use of coaxial tubing is available in the Toxic Gas Ordinance (TGO) and SEMI F6-92, which classify gases based on their material hazard index.12 Codes are necessarily complex, but the following two ideas may simplify their use. First, the approach to codes should be a holistic one taken by experienced, licensed professionals and coordinated with local building officials. Second, while codes once understood, interpreted, and agreed upon specify what is required, there are many other factors that will influence the system design. The factors that have been mentioned, such as guidelines, local considerations, site specific issues, and others such as stakeholder (tool owner, production, environmental, safety, operators, suppliers) perceptions and preferences.

25.4 SPECIALTY GAS DISPENSE AND DISTRIBUTION The designs of specialty gas dispense and distribution systems are based on factors such as gas characteristics, code requirements, desired flow and purity, tool designs, risk assessment, and cost. Due to the diverse nature of the gases used and process requirements, unique design solutions may be required for the same gas used in different applications (e.g., standard versus high flow ammonia process). Clearly, hazardous gas system configurations are inherently more complex and costly than inert gas systems. 25.4.1 Inert Gas Distribution Inert and nonhazardous gases are typically supplied from dual-cylinder, automatic crossover (AXO) racks. A rack being a floor, or wall mounted frame configured to accommodate cylinders, cylinder straps and pigtails, panel mounted valves, piping and components, and possibly a controller.

To scrubbed exhaust 1"- Purge gas vent header - CFOS 316L SS 1/

2" - CDA - CFOS

316L SS (pnuematics) From other NH racks

To other NH racks 3/8" - NH gas - EP 316L SS

3/8" - purge N2 - EP 316L SS 120 V 60 Hz 2A

Controller

Purge gas rack Purified N2/He purge gas cylinders with controller

FIGURE 25.3

120 V 60 Hz 2A

Controller

3/8" - NH gas - EP 316L SS

To other NH racks

Non-hazardous (NH) gas rack Dual process gas cylinders with controller

NH gas MVP

Inert specialty cylinder gas distribution diagram.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.9

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.9

The nonhazardous gas (NH) racks may have capabilities such as semiautomatic purge and automated controls. Nonhazardous gases may be distributed to tools in several ways: • • • •

Direct feed from the NH rack to a single tool An AVMP to several tools Manual valve manifold panel to several tools (MVP, see Fig. 25.3 and Ref.13) Distribution to multiple tools via laterals similar to bulk gases

Automated valve manifold panels (AVMPs) include such features as a pressure monitoring (gauge or transmitters), pressure regulation, filtration, pneumatic valves, and a controller (see Fig. 25.4). Automated panels can also be capable of semiautomatic purging with a vacuum venturi. A manual valve panel is simply a back panel with a common supply to several (four to eight) manual valves (see Fig. 25.5). Manual valve panels (MVPs) while less expensive, require close coordination with tool personnel to enable proper commissioning, operation, and decommissioning.

25.4.2 Hazardous Gas Distribution Hazardous gases are supplied from dual-cylinder gas cabinets with automatic cylinder switchover, semiautomatic purge, gas detection, automated gas shutoff, and remote monitoring. Distribution is via coaxial tubing either directly to a single tool or through an automated valve manifold box (VMB) to multiple tools (typically four to eight). VMBs are exhausted enclosures with capabilities similar to a cabinet (see Fig. 25.6). HPM cabinets and VMBs are provided with programmable logic controllers (PLC) that monitor the operation of the equipment (e.g., pressure, exhaust flow, coaxial annular space pressure, status— on/off/purge) and provide alarms and source isolation. If any condition exceeds its set point, the controller will set off an alarm or shut down the gas flow as required. Controllers often include an LCD display of equipment schematic, valve positions, alarms, and operator prompts for routine sequences (e.g., cylinder change, gas stick purge).The controller can also take inputs from other systems (e.g., hazardous gas detection to shutdown gas flow) and provide outputs or information to remote monitoring and control systems (Sec. 25.4.5). Controllers may have several levels of security access.

FIGURE 25.4 A nonhazardous rack (purge) and automated valve manifold panel.

FIGURE 25.5

A manual valve panel.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.10

SPECIALTY GAS AND CDA SYSTEMS 25.10

GASES AND CHEMICALS Scrubbed exhaust Notes:

Purge gas vent to scrubbed exhaust or tool abatement

1. Gas detection report to hazardous gas detection system Utilities not shown Fire protection CDA N2

3/8 × 5/8"-Hgas

3/8"-Purge N2 - EP 316L SS Note 1 Controller

Controller

To other gas cabinets 1"-Purge gas vent-CFOS 316L SS

To other VMBs

To tools (typical of up to 8)

Note 1 Controller

Controller VMB

120 V 60 Hz 2A

Hazardous gas valve manifold box

Purge gas cabinet

Hazardous gas cabinet

Abatement unit

Purified N2/He purge gas cylinders with controller, each feed multiple cabinets of compatible gases

Dual process gas cylinders with controller

Thermal oxidation

FIGURE 25.6

1/4 × 1/2"-Hgas

Purge gas cabinet Located in subfab Purified N2/He purge gas cylinders with controller

Hazardous specialty cylinder gas distribution diagram.

25.4.3 General Distribution and Tool HookUp Considerations It is important to recognize that the preceding distribution approaches represent an overview of common configurations. There are many factors to consider in addition to the issues discussed, such as the gas characteristics, code requirements, desired flow and purity, and cost. Distribution concepts are also influenced by factors such as tool design and risk assessment. Many tools can be purchased with single points of connections for process gases. These tools will generally have a gas box where the gases are manifolded to several chambers. In cases where multiple connections of a single gas are required at the tool, several options are possible depending on the tool configuration. The service can be routed to several points of connection without isolation (valves independent of the tool). Where the isolation of hazardous gases is required, a gas box can be provided at the tool (some sites refer to this as a GIB—gas interface box). This would typically be an exhausted enclosure with exhaust monitoring and hazardous gas detection. Another method is to provide multiple lines from a distribution panel (e.g.,VMB, AVP, and MVP). Distribution concepts are highly influenced by the perceived risk to the process. That is, the more tools that are supplied from a single source, the greater the production impact of an interruption in supply. Some sites supply a single tool from a cabinet, while others provide 8 to 12 tools from a cabinet (based on the flow capacity). Some sites attempt to minimize costs and risks by maximizing the number of tools supplied from a single source and connecting the sources and tools such that only a portion of the same process tools are connected to the same source. In this way, a supply failure may bottleneck but not preclude production (for instance if two of the four tools performing a required process step are idled). The gas system design must consider the entire scope from sources to tools and include a detailed understanding of the tool (connection points, as well as flow and pressure) and the manufacturing process. 25.4.4 Gas Equipment Considerations Many of the design considerations discussed in the preceding paragraphs are summarized in Table 25.2. Specialty gas equipment should be designed to minimize the internal purge volumes and the number of mechanical connections to reduce the potential for contamination. The proper specification of gas equipment involves the consideration of numerous general and gas-specific details. The general requirements and basic operation of a gas cabinet or NH rack are available from most equipment suppliers and SEMI F13-93.14 Table 25.3 illustrates some of the many considerations and features of specialty gas supply equipment. A matrix of this sort would also include component Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

AXO cabinet Dual outlet inert rack AXO inert rack AXO bulk rack

F2/Kr/ Ne Kr/Ne

Dual outlet cabinet

WF6

Corrosive gas room Corrosive gas room Corrosive gas room Corrosive gas room Flammable purifier room Subfab AVMB

AVMB

AVMB

AVMB

AVMB

AVMB

N N

Y

3/8" 1/4" × 1/2" 3/8" × 5/8"

3/8" 3/8" × 5/8"

N

N

1/4" × 1/2"

3/8" × 5/8" 3/8"

N

1/4" × 1/2"

3/8" × 5/8"

3/8"

N

3/8" × 5/8"

N

N

3/8"

N

3/8"

3/8"

1/2"

3/8"

N

CDO

CDO

PEA

PES

PES

PES

CDO

CDO

PES

PES

PES

PES

Purge gas vent (PGV)*

PES

PES

PEA

PES

PES

PES

PES

PES

N

N

N

PES

Exhaust†

Notes: 1. Gas cabinets, AVMBs, AVMPs, and racks require seismic restraint, 120V 20A UPS and network connections. 2. Gas cabinets, AVMBs, AVMPs, and racks require CDA for pneumatics. 3. Gas cabinets, AVMBs, and AVMPs require utility N2 for venturi. 4. MVPs may optionally use a purge header, with a valved VCR connection for purge cart hookup for their purge gas source. * Gas equipment with purge gas vent to abatement units (CDO or thermal decomposition) require interlock wiring. † Exhaust systems include PES—process exhaust to an acid scrubber and PEA—process exhaust to an ammonia (caustic) scrubber. ‡ Exhausts shall be set to obtain 200-fpm face velocity—this typically equates to 150 scfm. § Ductwork materials include TFE/SS—Teflon- or Halar-lined stainless steel and SS—welded stainless steel. ¶ Fire protection (FP) sprinklers in toxic and flammable cabinets.

SiH4

NH3

NF3

HCl

HBr

DCS

AXO cabinet Dual outlet cabinet AXO cabinet AXO cabinet AXO cabinet AXO cabinet Bulk

CH3F

AVMP

3/8"

3/8"

1/4" × 1/2"

3/8" × 5/8" 3/8"

N

Hookup line

Fit-up line

150

150

150

150

150

150

150

150

150

Exhaust flow (cfm)‡

TFE/SS

SS

TFE/SS

TFE/SS

TFE/SS

TFE/SS

TFE/SS

TFE/SS

TFE/SS

Exhaust duct§

N

N

Y

N

N

N

Y

Y

N

N

N

N

FP¶

Y

Y

N

Y

Y

Y

Y

Y

N

N

N

Y

Toxic gas monitoring

20:52

CF4 (bulk)

AVMP

MVP

Subfab Inert gas room Subfab support room Flammable gas room Subfab

AVMB

Subfab

Location

AVMB/ AVMP/ MVP

Heat trace and insulate (hookup line)

04/04/2005

CF4

Cabinet type

Gas type

Max cabinet flow rate (slpm)

TABLE 25.2 Specialty Gas Systems Design Matrix

Geng(SMH)_CH25.qxd Page 25.11

SPECIALTY GAS AND CDA SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

25.11

Panel excess flow switch

Regulator

Cylinder scale

Cylinder size Cylinder shelf

Cylinder press monitor

Proc outlet size

Purifier

Safety relief

Process filter

Vent press monitor

Delivery press monitor

2 Cyl auto Yes 1/4" B No No crossover MVCR rack

CF 4

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. No Yes No

Gauge Gauge 0-3000 0-200

No

Xducer Xducer No 0-3000 0-251

Xducer Xducer No 0-3000 0-250

Xducer Xducer No 0-1000 0-250

Vent switch

Toxic gas sensor port

He leak test port

Weld gas port

Coax pressure switch Proc out dual ISO

UVIR

No None

Yes Yes

No Class Yes Yes 1 div 2

Yes Yes

Z purge

Yes Yes No Yes 1/8 Yes 1/4 Yes Yes Yes No Class comp. 1 div 2 comp. union

No Yes 1/8 Yes 1/4 Yes Yes No comp. comp. union

Elec class No Class 1 div 2

Network

No Yes 3/8

No No 3/8

No No 3/8

No Yes No

No No No

No Yes No

No Yes No

Yes No

Yes No

Yes No

Yes No

No No

No No

No No

No No

No

No

No

No

No None

No None

No None

No None

No No

No Yes

No Yes

No Yes

No No 3/8 Yes Yes No Yes 1/8 Yes 1/4 Yes Yes Yes No Class COMP comp. 1 div 2 comp. COAX union

Yes Yes No 1/4

No

No

No

Xducer Xducer No 0-250

Xducer: pressure transducer COMP COAX: welded carrier line connection in coaxial compression connection COMP: compression MVCR: male VCR face seal connection UVIR: ultraviolet, infrared flame detector

B No No

No Yes No

No Yes No

2 Cyl auto Yes DISS crossover rack

Kr/Ne B No No

B No Yes No Yes No

2 Cyl auto Yes DISS crossover 716 rack

Xducer 0-250

Xducer Xducer Yes No No 3/8 0-250

No Yes Yes Xducer Xducer Xducer Yes No No 3/8 0-3000 0-250

A No Yes No Yes Yes Xducer 0-250

A No No

CHF 3

10% 2 Cyl auto Yes DISS crossover He/N 2 718 cabinet

Sprinkler head

A No Yes No Yes Yes Xducer Xducer Xducer Yes No No 3/8 No Yes 1/8 Yes 1/4 Yes Yes No 0-1000 0-250 COMP comp. comp. COAX union

A No Yes No Yes No

2 Cyl auto Yes DISS crossover 720 cabinet

NF 3

TEMP switch

B No Yes No Yes Yes Xducer Xducer Xducer Yes No No 3/8 Yes Yes No No Yes 1/8 Yes 1/4 0-1000 0-250 COMP comp. comp. COAX union

20:52

SiH 2 Cl 2 2 Cyl auto Yes DISS crossover 636 cabinet

2 Cyl auto Yes DISS crossover 640 cabinet

Gas

NF 3

System type 2 Cyl auto Yes DISS crossover 634 cabinet

Controller

HCl

Cylinder connection

2 Cyl auto Yes DISS crossover 634 cabinet

04/04/2005

HBr

Pneumatic cylinder valve

TABLE 25.3 Specialty Gas Equipment Consideration

Geng(SMH)_CH25.qxd Page 25.12

SPECIALTY GAS AND CDA SYSTEMS

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.13

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.13

pressure and flow ranges and manufacturers and model numbers. Special considerations may include the use of Hastalloy trim on regulators in corrosive gas service, solid stainless steel gaskets rather than nickel gaskets for face seal fittings in carbon monoxide service, and Vespel seats for components in nitrous oxide service. 25.4.5 Remote Monitoring, Control, and Management Remote monitoring and management systems are common, especially in large fabs. The gas management system is a human machine interface that allows monitoring, trending, and control of the gas equipment and cylinders. It is generally a PC-based system that is connected to the local UPS and emergency power. The gas management system monitors all of the information from the individual cabinets and valve panels via serial or Ethernet communications. It provides the operating status of the gas equipment, paging capabilities, equipment alarm status and history, and trending of gas usage. As shown in Fig. 25.7, the gas management system may share information with the facility monitoring and control system. The hazardous gas detection system can comprise several types of detectors. This system can provide outputs (e.g., gas shutdown, purge not available) to the gas equipment. The fire alarm system also interacts with the gas systems to monitor and alarm smoke and ultraviolet/infrared light detectors in the gas rooms. 25.4.6 High-Purity Tubing The distribution piping for specialty gases is generally 316L SS (stainless steel) electropolished tubing.15,16 This material is available in several grades and forms. Ten (10) microinch maximum Ra (arithmetic average roughness) surface finish tubing with automatic tube welded connections is commonly used. Final connections (to the tool and specialty gas equipment) are made with face seal connections. In the case of the coaxial tubing used for HPMs, the outer containment is cleaned for oxygen service 316L SS.17 Tubing is available in 20-ft lengths and coils of several hundred feet. Tubing sections are more commonly used in high-purity systems as the quality is more easily verified. Offsets LEGEND Control wiring (serial, analog, or discrete) Discrete wiring Facility monitoring and control system

Serial wiring TFE tubing

Hazardous gas detection system

FAS

Purge not available

Gas shutdown

Gas management system

Horn/strobe Ambient

In situ detectors

EGO UV/IR Smoke detectors Pull stations

FIGURE 25.7

Purge cabinet

Gas cabinet

VMB

Abatement unit

Ambient Tool

Tool Extractive gas detection analyzer

Gas management interface network diagram.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.14

SPECIALTY GAS AND CDA SYSTEMS 25.14

GASES AND CHEMICALS

are made with welded fittings or by bending the tubing. Bends for high-purity gas tubing are typically required to have a minimum radius of 10 times the tubing diameter. Some sites do not allow bending due to the potential for changes to the surface morphology, which could result in particle generation or corrosion. Coaxial tubing is monitored for integrity by one of several means: • Developing a vacuum in the annular space: The negative pressure is then monitored to ensure line integrity. This can be costly and complicated to develop and maintain. • Pressurization of the annular space: This can be done with nitrogen or a mixture of helium and nitrogen. The pressure in the annular space is set to below the process gas pressure (approximately 30 psi) and monitored to ensure line integrity. The use of a helium mix can facilitate leak checking. In some cases, such as with pyrophorics the annular space may be pressurized above the process gas pressure to ensure that the highly reactive process gas does not enter the annular space. • Gas detection: Monitoring for the specific process gas in the annular space is the easiest to do; however, the response time to a leak is the slowest and leak identification can take longer. The response time can be improved by using nitrogen to provide trickle flow purge toward the gas detector. These methods may not be appropriate for highly toxic and pyrophoric gases. Hastalloy C-22 tubing is sometimes considered for corrosive service. However, due to its higher cost, longer lead time, limited availability of components (e.g., valves), and surface finishes limited to 20 to 25 microinch Ra mechanical polish, it is rarely used. Electropolished 316L SS is used in fabs with special measures to prevent the introduction of moisture into the system. These measures include the specification of high purity, low moisture cylinder gas, the use of purified nitrogen purge gas, careful commissioning and desorption, and cylinder change and purge procedures.18

25.4.7 Purge Gas Supply Purge gas is used to evacuate hazardous gases for the protection of personnel prior to maintenance activities and to prevent the intrusion of atmospheric contaminants when the integrity of the gas system is broken (e.g., cylinder changes and component replacements). Purge gas can be provided to NH racks by several means. An NH rack with purge gas cylinders can be provided with piping to NH racks of the same, or compatible gases (refer to Fig. 25.3). House nitrogen may also be used for purging. Caution must be used in the design of such a system to prevent backflow or diffusion of the high pressure cylinder gas into the nitrogen system. Purge nitrogen systems can be separate, dedicated distribution networks with multiple backflow protection devices such as a pressure regulator, pressure relief valve, and/or a purifier. Purge gas for HPM gases is generally provided from purge gas cylinders in cabinets (refer to Fig. 25.6). In some cases, three cylinder cabinets are used, which include two process cylinders and one purge cylinder in a single cabinet. In the case of AVMBs, AVMPs, and MVPs, where purging is done less frequently, purge carts may be an economical choice (Fig. 25.8). A purge cart is simply a movable cart with a gas valve panel and a purge cylinder which can be connected to the distribution panel for tool commissioning, tool purging, and component replacements. The filtration and purification of purge gas sources should be considered relative to the source purity, process purity needs, gas characteristics, and cost. The type of gas used for purging should also be considered. For FIGURE 25.8 A purge cart. instance, cylinder purge gas allows the use of a helium/nitrogen mix,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.15

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.15

which is more costly than nitrogen, but can be useful for leak checking final connections. Many laser gases require the use of helium for purging to preserve the laser optics. 25.4.8 Exhaust Abatement Abatement of the enclosure exhausts and purge vent gases to 1/2 IDLH can be provided by several means depending on the gas and volume. Exhausts from the gas rooms can be directed to a facility exhaust scrubber, or to a dedicated scrubber. In some cases, restrictive flow orifices may be specified with the gas cylinder to limit a potential release to manageable levels. Purge vent gases may be handled in several ways depending on the specific gas. Inerts and readily water-soluble gases may be directed to the scrubbed exhaust, toxic gas cabinet purge gases may vent to a separate dedicated abatement unit such as a thermal decomposition unit (CDO), while toxic and pyrophoric VMB purges may be integrated into the tool abatement units. 25.4.9 Special Considerations One of the challenges of specialty gas systems are the many special considerations based on gas properties, chemistry, and thermodynamics. For instance, fluorine passivation of tubing is often used for fluorinated services such as tungsten hexafluoride (WF6) and fluorine laser gas mixtures. Fluorine passivation provides a protective barrier that impedes the reaction of fluorine with stainless steel.19 In untreated tubing, fluorine will react with stainless steel to deplete the chromium enriched surface layer via the formation of chromium fluorides and oxyfluorides. The heat tracing and insulation shown in the matrix (Table 25.2) for these services are used for bake out (moisture desorption) prior to passivation. The delivery of liquefied, low vapor pressure gases such as WF6, C4F6, and dichlorosilane (DCS) involve unique approaches to prevent the condensation of gas in the delivery lines. The objective with gases of this type is to keep the gas conditions in the process tubing below the saturation point of the gas.18 This can be accomplished by one of three means: • Heat the distribution tubing: Providing uniform heating throughout the distribution system is difficult and expensive. The small coaxial lines and fittings are difficult to heat trace and insulate especially inside cabinets and valve boxes. Ensuring uniform temperature control is difficult (especially with coaxial tubing) and expensive even with the newer heat tracing and insulation products. • Cool the cylinder: Special cylinder cooling units are available. Heat tracing and insulation of the distribution lines are often included with this solution to provide a positive temperature gradient toward the tool. However, cooling the cylinder reduces the pressure and flow capacity of the supply source. • Reduce the delivery pressure to below the saturated vapor pressure: With the use of absolute pressure regulators and absolute mass-flow controllers from the cabinet to the tool, the condensation of gas in the lines can be prevented. Heat tracing and insulation may also be required with this solution depending on the gas line route. Gas flow from a cylinder can be limited by evaporative cooling, especially in the case of moderately low pressure gases (e.g., NH3, Cl2, and C4F8) used at high flows. As the gas flows out of the cylinder, the remaining gas expands (or liquid evaporates). In order to maintain a high flow, heat must be transferred through the cylinder walls into the gas. This heat transfer is limited by the convective transfer between the cylinder and its surroundings. If this heat transfer is not satisfied then the gas cools and flow is limited. This can be overcome by insulating and heating the cylinder to maintain the required gas temperature at the demand flow rate. Joule-Thomson (J-T) cooling can also occur at high flows. This effect, discovered in 1852 by William Thomson (later Lord Kelvin) and James Prescott Joule, describes the change in temperature that occurs when a gas expands into a region of lower pressure.20 The gas-specific J-T coefficient (uJT) determines the size of the effect. Generally the result is cooling on expansion (positive uJT). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.16

SPECIALTY GAS AND CDA SYSTEMS 25.16

GASES AND CHEMICALS

The J-T coefficient is dependent on the temperature and molecular parameters, which account for energetic interactions and the size of the molecules. These parameters are predicted by the van der Waals equation of state. Molecules having stronger attractive interactions should show the larger temperature decrease. The amount of cooling also increases in proportion to the pressure difference at the throttle, and increases substantially when the starting temperature of the gas is decreased. In practice, this effect is mainly of concern at the regulator in the gas cabinet (or rack). The use of gas-specific thermodynamic data such as saturated vapor pressure versus temperature, cylinder pressure versus time at various flows, and pressure versus enthalpy are required to address these issues. This data is often available from the gas supplier or can be found in reference sources.1,2,21 One of the major challenges in the design of specialty gas equipment and systems is the diversity of gases and applications. This situation becomes even more challenging given the time constraints of a typical fab project.

25.5 IMPLEMENTATION 25.5.1 Strategic Planning The successful implementation of specialty gas systems involves the development of an overall strategic plan to include the integration and execution of several interdependent phases including: 1. 2. 3. 4. 5. 6. 7.

Design Equipment supply Cylinder gas supply Installation Test and commissioning Tool hookup Operation

It is in the fab owner’s interest to develop a strategic plan that encompasses all the project requirements. For instance, the trend in the semiconductor industry seems to be toward outsourcing of the specialty gas systems operation and maintenance. A likely party for this scope would be the gas equipment vendor. For cost reasons, this scope should be negotiated along with the gas equipment and gas cylinder supply contracts. Some gas vendors will also perform design/build scope, in which case all or major portions of the above seven phases would be performed by the gas vendor. Partnering with a gas vendor to perform multiple portions of work and provide a point of use guarantee has also become much more common. The decision as to how to execute the necessary work is very company and project specific. Many different approaches can yield the desired results. What’s important is to define the desired results and develop an overall strategic plan to accomplish them. Table 25.4 lists many elements of a specialty gas systems project and some of the options to achieve them. This table is designed with large projects in mind. In many cases, new equipment additions and small projects are handled almost entirely by the owner. The remainder of this section looks at specific implementation elements in greater detail. 25.5.2 Design The project design is generally the first step and is usually broken into several phases—programming or conceptual design, preliminary or initial design, detailed or final design, and construction services or support. These phases are not discrete and generally overlap. The conceptual design phase would have the following deliverables: • Definition of applicable codes, local requirements, and other considerations • Initial list of gases by area and possibly tool Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.17

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.17

TABLE 25.4 Execution Scope and Alternative Execution Alternatives Design/Build Construction Local ThirdArchitectural Specialty Gas Specialty Specialty Engineering Management Supply Party Owner and Vendor Contractor(s) Fabricator Firm Firm Firm QA/QC Engineering Firm

Scope Design Project cost, schedule, and coordination Building and gas room construction Furnish equipment Cylinder gas supply Local cylinder storage delivery Installation of specialty gas systems Quality assurance and quality control POU guarantee Monitoring and control systems Gas detection Commissioning Acceptance testing Tool hookup design Tool hookup installation Tool hookup QA/QC Operation and maintenance Sustaining engineering

• • • •

Descriptions of equipment and distribution system configurations Initial gas room locations and sizing Initial feasibility assessment of bulk specialty gas supply Potential evacuation strategies

Preliminary design would finalize the above items and develop: • The proposed distribution concept including pipe routing and location of valve manifold boxes and panels • Purge and abatement solutions with space allocation • Initial process and instrumentation diagrams (P& IDs) for each type of gas system configuration • Preliminary specifications for: • • • • •

Gas equipment Abatement equipment Tubing materials Monitoring and control systems Gas detection systems

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.18

SPECIALTY GAS AND CDA SYSTEMS 25.18

GASES AND CHEMICALS

• Coordination of required interfaces and system needs (e.g., power, and exhaust) • List of qualified vendors, installation contractors, and equipment and material lead times • Tool hookup concepts based on specific tool configurations Detailed design would involve the production of early material and equipment purchase documents, and construction drawings and specifications. Construction services may involve such activities as bid analysis, submittal review, construction observation, and commissioning support. The owner’s role in the design process is crucial to the success of the project. Providing appropriate, accurate, and timely information and decisions during this phase sets the stage for the remainder of the project. Another important aspect for owners is a process for change management. The need or desire for changes will arise. A process must be in place to assess the benefits and impacts, and then decide, track, and communicate changes. The later stages of the design activities will overlap with equipment supply and installation. 25.5.3 Installation Some of the critical aspects of the installation or construction phase are selecting qualified contractors, field issues, and field quality assurance. The availability of key resources is critical to successful implementation. The availability of qualified and experienced detailed designers, high-purity welders, field superintendents, project engineers, and managers will significantly influence the project. In addition to assessing and attracting qualified firms and personnel, it is important for the owner to ensure the accurate and timely resolution of field issues. Field productivity and quality are both important to a successful project. 25.5.4 Quality Assurance and Control A quality assurance program integrated into the execution strategy can help to achieve the project goals. In addition to ensuring conformance to the construction documents, a quality assurance program should strive to improve field execution by optimizing work methods and providing effective communication between the engineering staff and skilled trades in the field. A quality assurance program may involve several parties including a quality representative from the installing contractor known as the quality control representative (QCR), a third-party specialist, or owner’s personnel known as the quality assurance representative (QAR), and a quality manager (QM) who is the owner or owner’s representative (e.g., construction manager). Two key considerations are the qualifications of the quality assurance personnel and the extent of owner control over the performance of critical tasks. Quality assurance personnel, particularly the QARs, should have a technical background, several years of field experience, and be certified welding inspectors. Quality assurance tasks critical to the performance of the system should be executed by a firm whose only obligation is to the owner. Table 25.5—Quality Assurance/Quality Control Program Responsibilities Matrix—outlines many of the program activities and responsibilities. Again there are many different ways to successfully structure this scope depending upon the desired results, project size, and execution strategy. 25.5.5 Start-up, Commissioning, and System Acceptance Start-up, commissioning, and system acceptance activities occur at the end of the installation and before normal operation. The criteria for system acceptance must be included in the design specifications and will define the expectations for such items as: • Training • Operation and maintenance manuals • Checklist of prerequisites for operation including utilities, safety systems, signage, calibration records, Quality assurance/quality control (QA/QC) documents, sequences of operation, as built P & IDs • Purity testing

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.19

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.19

TABLE 25.5 QA/QC Program Responsibilities Matrix Activity Specification generation Vendor qualification Material and component testing prior to shipment Material and component inspection on receipt Equipment testing prior to shipment Equipment inspection on receipt Storage and handling areas and methods Contractor submittals Weld and test gas certification Weld qualification Weld QA Cleanroom protocol Cleanroom monitoring DI water quality monitoring Piping fab areas and operation Installation—inspection and testing Pressure test Acceptance testing Performance testing Out-of-spec action

Contractor (QCR)

Gas vendor

R R R P

R P

P P P P P S

S P P

S

M P W R V V V V

V V W V

QAR

Owner

R R V V V V W V W W P W P P V W W P W W

R P M M M M M R M M M M M M M M M M W M

Key: P—Perform, provide labor and material; S—supervise, coordinate, direct, and oversee activity; M—monitor, oversee, and review on periodic basis; W—witness, be present, and sign-off; V—verify, perform independent random testing; R—review and approve.

• Functional testing of equipment, components, instruments, control loops, alarm set points, and monitoring and control systems • Operational testing generally in fully automatic mode for a specified period of time Acceptance purity testing of specialty gas systems involves integrity and purity testing of the equipment prior to shipment, testing of the installed specialty gas system (source cabinet or rack to the VMB or MVP) at the outlet of the valve manifold, and testing of the gas lines to the final connection at the tool. This often includes pressure hold (process line and coaxial annular space), inboard helium leak to 1 × 10−9 cc/s, moisture, oxygen, and particle testing with acceptable contaminant levels and specifications for test equipment and procedures to be used. 25.5.6 Tool Hookup Tool hookup must be considered in the initial strategic plan and throughout the implementation phases, especially system design, installation, QA/QC, and commissioning. Considerations such as tool configuration (e.g., single drops per tool versus multiple) and the level of acceptable risk (e.g., number of tools per source) must be addressed in the system design in order for the hookup phase to be successful. The use of the same construction and QA/QC forces for system installation and hookup can be an important consideration in terms of expertise, resources, and schedule. Commissioning requirements should take the entire scope (source to tool) into consideration to avoid duplications or omissions. With appropriate planning the inherent challenges of an initial factory tool ramp can be limited. 25.5.7 Operations, Maintenance, and Sustaining Engineering Properly trained operations personnel are crucial to a successful specialty gas system. Operations and maintenance functions may be outsourced to a gas vendor, or other qualified firms. These services

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.20

SPECIALTY GAS AND CDA SYSTEMS 25.20

GASES AND CHEMICALS

may also be performed by in-house personnel. In either case, training and sufficient staffing is crucial, especially during the start-up, and hookup of the initial tool sets. Consideration should be given to such issues as: • Necessary equipment and supplies (helium leak detectors, portable gas detectors, tools, carts, cleanroom garments, personal protective equipment) • Emergency response activities and supplies • Interface with gas detection systems • Parts and consumables inventory (e.g., gaskets, filters, regulators, and gas sticks) • Certifications (ISO 9000) • Regular reports, safety, and performance metrics (e.g., uptime, MTBF, and MTTR) • Documentation and coordination of procedures for the commissioning, energizing, and decommissioning of gases to tools • Cylinder inventory levels and shelf life22 • Incoming product quality monitoring The careful monitoring and planning of gases to tools is required to ensure the availability (connection points) and capacity (flow rate) of gases. This information is likely to change frequently and therefore should be regularly verified. Table 25.6 shows a simple example of such a tracking tool. This could be a spreadsheet or relational database depending on the needs of the users and customers and could also include such information as product specifications and links to process recipes. TABLE 25.6 Gas to Tool Management Area: Diffusion Building: FAB X Gas name Ammonia

Gas NH3 NH3 NH3 NH3 NH3 NH3 NH3 NH3 Total flow NH3 NH3 NH3 NH3 Total flow NH3 NH3

Max. source flow (slpm)

Stick flow (slpm)

Cabinet

Manifold

Stick

SGNHCRF2 SGNHCRF2 SGNHCRF2 SGNHCRF2 SGNHCRF2 SGNHCRF2 SGNHCRF2 SGNHCRF2

SGNHF10B SGNHF10B SGNHF10B SGNHF10B SGNHF10B SGNHF10B SGNHF10B SGNHF10B

A B C D E F G H

Tool

SGNHCRF3 SGNHCRF3 SGNHCRF3 SGNHCRF3

SGNHF10A SGNHF10A SGNHF10A SGNHF10A

A B C D

ABCD02B ABCD01DB

Available Available Inactive Active

SGNHG11B

A

RSTX02DA

Inactive

SGNHG11B

B

RSTX01DA

Inactive

XYZZ01DB

Revised

Status

12/4/03

Available Available Available Available Available Available Available Active

Notes

Was NZDZ01DB

Locked out at tool Locked out at tool

Total flow

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.21

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.21

Frequent communication with the equipment and process engineers and equipment planners will help to ensure equipment and product readiness by helping to forecast gas usage and anticipate potential changes (new gases or tools). The implementation of specialty gas systems will always be challenging given the semiconductor industry’s critical time to market. However a comprehensive implementation strategy can make this process better, faster, and cheaper provided the approach has the support of key stakeholders and management. 25.5.8 Sustaining Engineering While much of this chapter is devoted to developing and designing specialty gas systems for a new factory, these same principles and guidelines can be applied to smaller scale projects from retrofitting areas to adding a new gas system. In addition, this section highlights some of the opportunities to optimize specialty gas systems. The potential to reduce the cost and cycle time exists in every fab. Opportunities may exist in one or more areas including • Equipment and distribution: Configurations can be simplified, and the number of tool connections per unit of equipment can be increased to reduce costs. • Product: Synchronization of process requirements with product specifications, optimization of cylinder change criteria, shelf life, and inventory, and consideration of alternate suppliers and container sizes, and possibly bulk supply. • Inventory: Reduction of product as well as spare parts. • Manpower and processes: Streamlining of processes and reduction of the cycle time for new installations, commissioning, and decommissioning. In the case of these systems, there are technical and other obstacles to change, which must be overcome. The technical challenges are addressed throughout this chapter and include code and risk assessment, understanding the process requirements, and the specific gas properties and behavior. Other challenges involve the perceptions and preferences of various internal and external customers and stakeholders including suppliers (gas, gas equipment, and tool suppliers), equipment engineers, process engineers, operations, and environmental health and safety.

25.6 FUTURE TRENDS ON SPECIALTY GAS SYSTEMS Several noticeable trends in specialty gas systems include: • • • • •

The increasing use of bulk specialty gas systems for high-volume fabs A continued need for reduced cost and increased uptime The emergence of new gases as the manufacturing process evolves 300 mm wafer processing Integrated gas systems

Bulk specialty gas supply (BSGS) systems are standard vendor-supplied packaged systems to supply inert or hazardous specialty gases from bulk containers to valve manifolds (e.g., MVMBs, AVMPs, MVPs). Bulk containers can be “Y cylinders” (24-in diameter horizontal cylinders), isotainers, hydril tube trailers, or bulk tanks. The systems may be located in the fab building, remote from the fab at a back pad, or both. BSGS systems are typically easier to apply to new factories, unless provisions were made for future bulk systems. These systems can significantly reduce the capital and operating costs. Product cost savings based on bulk containers can range from 5 to 50 percent ($/lb basis). The use of bulk containers also significantly reduces the number of cylinder changes (one Y cylinder ~ eight A or B cylinders). Since

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.22

SPECIALTY GAS AND CDA SYSTEMS 25.22

GASES AND CHEMICALS

most incidents occur during cylinder changes, bulk systems can be safer.23 An assessment of costs involves comparing the BSGS costs and savings from purchasing bulk material to the cost of gas cabinets. BSGS can be justified based on high volume usage (material savings) and/or a large number of points of use (driven by installed cabinet costs). Table 25.7 serves a foundation to evaluate the cost of BSGS for a new factory. Prior to performing this cost comparison it may be useful to develop a short list of likely gases by determining which have: • • • •

The highest usage per month The highest cost per month The highest number of points of use The largest product cost delta (cylinders versus bulk containers)

Typically, several gases will appear in more than one of these categories. These will have the highest potential for a favorable payback and should be evaluated first. The values for items A, B, and C in Table 25.7 should be readily available. The costs for BSGS systems (items D, E, and F) may require some additional investigation. The installation costs for a BSGS system can be especially difficult to define for an existing facility. In the case of an existing facility, it is also unlikely that the material savings will offset the total BSGS costs (except perhaps inerts). Once a solid design concept is developed, the cost assessment can be straightforward. However, the design must be carefully and thoroughly thought through to address issues such as weatherproofing of systems located outdoors and environmental and regulatory considerations with locating large HPM containers.24 In addition to the usual considerations of specialty gas system design, bulk systems have additional unique issues. For instance, some standard BSGS are designed strictly to replace the gas cabinet as the supply source and do not always address the distribution issues inherent to bulk supply. Usually a gas cabinet supplies a single VMB that is installed with the gas cabinet. With a bulk supply system, one or several VMBs may be installed with the BSGS and several more may be added in the future. Some consideration must be given to future expansion and modifications without service interruptions (e.g., standard VMBs, or custom engineered main valve boxes that can be used as “primary VMBs,” which supply other secondary VMBs). The number, location(s), and control functionality of these units require careful consideration, as they can be crucial to the performance of the system. Consider the inert BSGS system depicted in Fig. 25.9. With inert gases it is relatively easy to plan future build-out valves for back-up sources and future tools. With hazardous gases it is much more difficult to achieve these capabilities due to the need for exhausted enclosures, toxic gas monitoring, and automatic isolation of the supply. A bulk silane system is depicted in Fig. 25.10. This is a fully redundant system with future expansion capabilities from spare gas sticks in the primary VMBs. The operation of this system was revised, from its original design, to prevent interruption of service due to high process pressure, or leak detection in a single primary VMB. While BSGS can have significant cost advantages, they also involve a higher level of risk because a larger number of tools are dependent on a single system.25 The cost of an unplanned interruption could exceed several years of BSGS cost savings. This is especially important when considering the use of BSGS for multiple wafer processing tools. In the case of hazardous BSGS systems a formal analysis (e.g., failure mode and effect analysis, and fault tree analysis) of failure modes is warranted.

TABLE 25.7 Standard Cylinder Versus Bulk Container Gas Supply Assessment Summary

Gas

Points of connection

Number of cabinets required

X

YY

A

Cabinet unit cost

Cabinet install cost

BSGS unit cost

BSGS install cost

Annual bulk product savings

Cabinet total

BSGS total

First year BSGS cost delta

B

C

D

E

F

A(B + C) = G

D+E–F=H

H–G

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

20:52

Page 25.23

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.23

Gas room subfab Keyed notes 2 Purge requirements of inert gas trees to be satisfied by local purge header or mobile purge cart. 4 Regulator 5 Filter 7 Flex hose 8 Diss connector

1/2−dair Pes header gas header Purge vent

3/8−PN2

From other non-hazardous racks (typ) as required 1/4 To other Future non-hazardous racks (typ) as required 1/2−XXX

From purge cart

3/8−PN2 PN2 to other inert racks (typ) as required

3/8−PGV

1/4 1/4−PN2

1 × 3/8

1/4−dair 1/4−PN2

N2 purge vent

From dair

3/8−PGV

Geng(SMH)_CH25.qxd

Future

To IGT #2 as required 3/8−XXX

To tool typical up to 8 sticks

2 IGT Inert gas tree

Purge gas rack Purified N2 purge gas PT from cylinders 7 8 1/2−XXX PT PT 7 8 1/2−XXX

FIGURE 25.9

120 VAC 60Hz 2A 4

4

5

5

Inert BSGS system schematic.

Although not strictly a part of BSGS systems the use of bulk helium has become more common in recent years. The material cost of bulk helium is orders of magnitude less than cylinders. Helium can be supplied from a hydril tube trailer, “Y” cylinders, or a manifolded rack of cylinders (6 pak) and distributed similar to traditional process bulk gases (e.g., argon and oxygen). The purification of helium may be required depending on the application requirements. These examples highlight just a few of the many issues and opportunities that must be carefully considered with bulk specialty gas systems.

Fab building

Silane back pad

Secondary VMBs

Tube trailer B

Tube trailer A Side B controller

Primary VMB 1

Primary VMB 2

Side B process panel Side A controller

Crossover panel

FIGURE 25.10

Side A process panel

Bulk silane schematic.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.24

SPECIALTY GAS AND CDA SYSTEMS 25.24

GASES AND CHEMICALS

As the industry continues to mature, the trend toward reduced cost and increased uptime will continue. This is evident in the continued movement toward outsourcing through such means as expanding the role and scope of supply (partnering) with major gas suppliers and reducing initial capital investments (by simplifying specialty gas systems, supplying more tools from a single supply, using bulk specialty gas systems, and leasing of supply systems, among other measures.). Developments in the semiconductor industry have resulted in several new gases and delivery methods. Safety concerns with the use of highly toxic implantation materials have led to the use of low-pressure cylinder packages for gases such as BF3, AsH3, PH3, and others. This approach allows the delivery of the implant gas to the tool under vacuum from a cylinder package that is at a very low pressure (e.g., less than 30 psig to −4.7 psig26). This minimizes the potential for accidental releases. New gases and applications will continue to emerge for a variety of reasons. The highly reactive chlorine trifluoride has been proposed for more efficient chamber cleans. The substitution of gases such as C2F6 for CF4 and NF3 has been used to increase the chamber clean efficiency and decrease the environmental impact of fluorinated carbons (in terms of tons of carbon equivalents).27 Process requirements have led to the use of new reactive gases such as C3F8, C5F8, and C4F6. The drive toward smaller devices has also led to shorter wavelength lasers (248 to 193 and 157 nm) using argon rather than krypton-based reactive (Kr/F2/Ne, Ar/F2/Ne) and fill (Kr/Ne, Ar/Xe/Ne) gases. While these new gases and applications offer advantages, their characteristics must be carefully considered before designing the supply and distribution systems as they can be more toxic and difficult to distribute. Future developments may include the use of integrated gas system components in gas cabinets and particularly valve manifolds. Integrated gas systems (Fig. 25.11) involve the modular assembly of compact surface mount components (e.g., valves, regulators, and filters). They take up 30 to 60 percent less space, have 50 percent less wetted area, and can be faster and less costly to repair and replace (20 to 50 percent improvement in MTTR) than conventional welded assemblies.28 In some applications, flow and pressure drop may currently be a limitation. The initial cost of integrated gas systems is higher; however, this is expected to decrease as production volumes increase. These components are currently used in some of the new tools, especially 300 mm etch platforms. The industry’s move to 300 mm is unlikely to significantly change specialty gas systems, other than to perhaps expand the usage of bulk systems. This is due more to the fact that 300 mm fabs tend to be high-volume factories than to dramatically increased gas consumptions. 300 mm processes use higher volumes of gas, but it is no where near the 2 to 3× increase once predicted.

FIGURE 25.11

Integrated gas systems.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.25

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.25

25.7 CLEAN DRY AIR 25.7.1 Introduction—CDA Semiconductor fab clean dry air (CDA) system designs have received increasing attention because of the requirements of photolithography tools. Technology developments in the integrated circuit (IC) industry have led to the use of lithography tools with higher purity, flow, and pressure requirements, placing new demands on CDA system design. This section discusses traditional CDA system design, the role of vendors in supplying CDA to fabs, and lithography tool requirements. It presents measures that existing and future fabs can take to meet their CDA needs and discusses the potential impact of those measures on the manufacturing process. 25.7.2 CDA System CDA is used in many applications throughout the fab and support areas, including in pneumatic controls and tools, purging equipment, air cylinders for machine actuation, product cleaners and blowoff devices, and air-driven pumps. A fab’s CDA system is typically located in the central utility plant and is configured along the lines of the simplified schematic in Fig. 25.12. The system is normally designed to provide –80 to –100°F dew-point air with 0.01-to -0.003-µm filtration. The delivered pressure to the point of use is generally 100 psig. Generally, multiple compressors are needed to generate CDA, and an additional unit (n + 1) serves as a standby. Design data from many fabs indicate that CDA consumption can vary significantly from 25 to 50 std cu ft/min per 1000 sq ft of production cleanroom area. CDA consumption in newer fabs seems to be closer to a nominal 40 std cu ft/min per 1000 sq ft of cleanroom area. Typically, more than 80 percent of the CDA system is used to support manufacturing equipment, while the remaining 20 percent is used for instrument air and utility applications (Fig. 25.13). In the manufacturing area, wet and lithography applications are the largest consumers of CDA, each using 15 percent of the facility’s total supply. Empirical data from one factory indicate that the actual nominal CDA consumption is 55 percent of the manufacturer’s design-flow requirements. Surprisingly, the correlation between wafer starts and CDA use is higher than that for many bulk process gases. 25.7.3 Requirements of Modern Photolithography Tools Photolithography is the most demanding of all fab processes. Depending on the specific model, a lithography tool can require low-parts-per-billion concentrations of organic and inorganic species, a high air-pressure supply, and high airflow.

Instrument air Receiver

CDA

Compressors (n + 1)

Dryers (n + 1)

After filters (n + 1)

Final filters (n + 1)

FIGURE 25.12 Schematic diagram of a typical central plant CDA system located inside the central utility building.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.26

SPECIALTY GAS AND CDA SYSTEMS 25.26

GASES AND CHEMICALS

Other fab areas 30%

Probe, assembly, and test 20%

Facilities 20%

Fab wets 15% FIGURE 25.13

Fab lithography 15% Breakdown of CDA used by fab area.

Some lithography steppers have high-purity requirements in order to prevent lens contamination caused by photochemical reactions. While lenses can be cleaned, the cleaning process is difficult, time-consuming, and disruptive to the production process. Moreover, lenses can be cleaned only a limited number of times before their coating is damaged and replacement becomes necessary. Lens replacement can cost several million dollars. As device geometries shrink, the potential for lens contamination increases. The shorter wavelengths and higher light intensities used to manufacture devices with small linewidths increase the incidence of photochemical reactions. While specific organic and inorganic species of concern differ from one manufacturer’s tool to another and from one technology generation to another, less than 1-ppm levels of total organic carbon or total hydrocarbons, low parts-per-billion levels of organic gases, and moderate parts-per-billion levels of specific volatile inorganic species can contaminate lenses. Species of concern include ammonia compounds, amines, sulfates, and phosphates. In many cases, finding a lab capable of performing contamination analyses can be challenging. Typically, CDA systems produce air at 100 psig. However, scanner tools require a higher CDA pressure of 125 psig for optimal performance. Furthermore, scanners require twice as much airflow as steppers because they use active air mounts for vibration isolation and air bearings for stage positioning. New-generation track tools, on the other hand, require five times more CDA than tools installed five years ago because they incorporate hot plates where CDA is used to remove heat rapidly. These data are based on the total design flow specifications rather than the actual tool data; preliminary data indicate that actual scanner-tool CDA use is approximately half of the tool’s rated airflow. Clearly, new fabs must consider the requirements of critical lithography tools when they set out to design a CDA supply system. However, even new fabs may be forced to procure such a system before they have detailed information on the process equipment they will be installing. When new tools are to be used in an existing facility, the CDA system may have to be upgraded or otherwise modified. The demand for increased CDA pressure and flow can be particularly challenging for systems that may already be highly utilized. 25.7.4 Supplying CDA to the Fab and the Tool CDA Distribution Systems. CDA piping distribution systems are commonly arranged in a centerspline configuration. Some older fabs use a perimeter-loop design, while some very large new fabs may use a double-spline design. Tubing is typically constructed of cleaned-for-oxygen-service (CFOS) copper, although CFOS stainless-steel tubing has become more common. While copper tubing is sufficient for the quality of air required, it is prone to quality problems (in part because of oxidation). Copper also requires brazing, but brazing should not be performed in clean areas. Although more expensive than copper tubing, stainless steel may be preferable because it is easier to install,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.27

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

2

25.27

N2

Dryer

N2

Air compressor for N2 production

LN2 source 3 CDA compressor

1 CDA

FIGURE 25.14 A leased vendor CDA system located on a gas pad outside the facility. (The numbered boxes indicate the sequence of backup steps in the event of system failure.)

requiring orbital welding instead of brazing. Because stainless steel is easier to work with than copper, it is particularly advantageous for large-diameter tubing. The total installed cost of stainless steel can be similar to that of copper. The labor time and costs of installation seem to vary regionally depending on the experience of the local workforce. Leasing Vendor CDA Systems. Presumably because of the need to focus capital and personnel resources on the production of devices, fabs have increasingly leased CDA systems from gas vendors in recent years. While some fabs purchase CDA or N2 to back up an existing central plant CDA system, others receive all their CDA from outside suppliers (Fig. 25.14). In general, leased systems should be considered carefully to ensure that they meet all site requirements, such as noise levels, energy efficiency (particularly when an extended factory rampup is planned), and flexibility. In particular, leased systems can complicate the use of lithography tools. They tend to be less flexible than on-site systems, and because they are typically procured as a complete package of services, they have longer lead times than the traditional central plant system. Hence, fabs considering a vendor-supplied CDA system must define the required use and purity requirements ahead of time. Often, leased gas systems are not procured as part of the capital building and site construction project and therefore do not meet site construction requirements.

25.8 CONCLUSIONS In conclusion, specialty gas system design is somewhat complex due to the diverse character of gases used, difficulties in comprehending the many code requirements, and the interdependencies of the various execution phases. These issues become even more challenging given the perceptions of various stakeholders, and the ever changing nature of the manufacturing processes. Hopefully, a better understanding of the execution elements, considerations, options, and overall process will help to provide a more reliable, safe, consistent, timely, and cost-effective supply of specialty gases. The competitive DRAM semiconductor market manufactures small, high-capacity devices at a low cost per bit, leading the industry to develop lithography tools with high throughput and fine resolution. Such tools, in turn, require supplies of CDA at a higher flow, pressure, and purity than in the recent past. These requirements have driven and will continue to drive CDA system design. Many system design options exist. Leased vendor-supplied systems should be carefully considered, specified, and procured. Current and potential lithography tool requirements should be thoroughly

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.28

SPECIALTY GAS AND CDA SYSTEMS 25.28

GASES AND CHEMICALS

documented. Ultimately, the most appropriate systems depend on specific site conditions and preferences, such as the products manufactured, whether the fab is a new or existing one, the availability and cost of capital, tool suppliers, internal lens-purge methods, the anticipated number of tools to be used, and energy costs.

ACKNOWLEDGMENTS I appreciate the contributions of many individuals, especially Ken Duffy and Pat Gibson (Air Products and Chemicals), Mike Baron (FST Consulting), Tom Stagg (Alliance Engineering), Mike Bridges (Swagelok Company) and Jeff Connelly, Clayton Forehand, Eric Holterman, Jim Toussaint, Will Morden, and Kirt Sederstrom of Infineon Technologies, Richmond.

REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.

20. 21. 22. 23.

Braker, W., and A. Mossman, Matheson Gas Data Book, 6th ed., 1980. Compressed Gas Association, Handbook of Compressed Gases, 3rd ed., 1990. Air Products, Specialty Gases and Equipment Catalog, 1998. Building Officials and Code Administrators International, Inc. (BOCA), National Building Code and National Fire Prevention Code, 1996. International Conference of Building Officials, Uniform Fire Code (UFC), International Fire Code Institute, 1996. International Building Code (IBC), 2003. “Toxic Gas Ordinance” (TGO), Santa Clara County, 1990. NFPA 704, Standard for the Identification of the Fire Hazards of Materials, National Fire Protection Association, 1990. NFPA 318, Standard System for the Protection of Cleanrooms, National Fire Protection Association, 1992. Factory Mutual Engineering Corp, “Loss Prevention Data 7-7,” Semiconductor Fabrication Facilities, 1991. Factory Mutual Engineering Corp, “Loss Prevention Data 1-56,” Cleanrooms, February 1988. SEMI F6-92, Guide for Secondary Containment of Hazardous Gas Piping Systems, 1996. Curcie, W., “Designing a Specialty Gas System,” Semicond. Int., November 2003. SEMI F13-93, Guide for Gas Source Control Equipment, 1996. SEMI F16, Specification for 316L SS Tubing Which Is to Be Finished and Electropolished for High Purity Semiconductor Manufacturing Applications. ASTM A269, Specification for Seamless and Welded Austenitic Stainless Steel Tubing for General Service. ASTM B280, Standard Practice for Cleaning Methods for Material and Equipment Used in OxygenEnriched Environments. George, M., D. Bohling, W. Bailey, T. DelPrato, K. Harlan, and C. Magnella, “Minimizing System Contamination Potential from Gas Handling,” Semicond. Int., July 1993. George, M., B. Felker, and D. Bohling, “Controlling Surface Interactions of WF6 with 316L SS through Fluorine Passivation and Selection of Alternate Materials,” Conference Proceedings ULSI, Materials Research Society, 1994. Magnin, E., “Joule-Thomson Effect Module,” www.nd.edu, July 10, 2001. Hui, H., D. Ruppert, and G. Hoban, “Streamlining Gas Delivery Systems Design and Management,” SEMI Technical Symposium, SEMICON West, 2002. SEMI C52-0301, Specification for the Shelf Life of a Specialty Gas, 2001. Frausto, J., and D. Quadrini, “Bulk Silane Systems for Semiconductor Manufacturing,” Future Fab Int., Vol. 1, No. 3, pp. 309–313, 2000.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.29

SPECIALTY GAS AND CDA SYSTEMS SPECIALTY GAS AND CDA SYSTEMS

25.29

24. Ford, R., and B. Hertzler, “300 mm Fabs and the Role of Bulk Specialty Gas Supply,” Solid State Technol., October 2001. 25. Ruppert, D., W. Preller, and M. Marmaro, “Principles and Design Issues of Bulk Specialty-Gas Systems,” Solid State Technol., May 2003. 26. Hart, J., J. Irven, R. Parise, R. Pearlstein, and J. Van Ommeren, “Incorporating More Gas Control Within Cylinders,” Solid State Technol., 2003. 27. Johnson, A., R. Pearce, M. Sistern, M. Kencel, R. Sward, and H. Winzig, “C2F6—Based Chamber Clean for Silane PECVD,” Semicond. Int., March 2004. 28. Culwell, B., ”Modular Gas System Solutions,” Future Fab Int., No. 5, pp. 299–305.

FURTHER READING Baxter, J., “Gas Systems Undergo Radical Design Modifications, Resulting in Significant Serviceability Improvements,” Cleanrooms, Nashua, New Hampshire, 2003.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH25.qxd

04/04/2005

20:52

Page 25.30

SPECIALTY GAS AND CDA SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 26

WASTE GAS ABATEMENT SYSTEMS Joseph D. Sweeney ATMI Danbury, Connecticut

26.1 INTRODUCTION During the manufacture of semiconductor devices, significant concentrations of toxic and hazardous gases can be present in the effluent streams of the various process tools. These gases are by-products of reactions occurring within the tool or are feed gases that make it through the tool unreacted. Abatement systems are necessary in order to remove these compounds from the exhaust streams. Although many liquid chemicals are also used in semiconductor device manufacturing, this chapter focuses primarily on the abatement of gas species. Abatement systems generally fall into three categories—(1) point of use (POU) systems, (2) house systems, and (3) emergency release scrubbers (ERS). Point of use abatement units are usually dedicated to one process tool and sometimes to a single process chamber (a tool may have anywhere from one to six chambers). These scrubbers are relatively small and are almost always installed in the subfab within proximity to the process tool. In contrast to these units, house abatement systems are much larger and handle high flow rates of effluents (usually low in concentration) from a wide range of sources such as fume hoods, wet benches, and the general fab exhaust. Due to their size, house units are often placed outside the fab. The third type of abatement system—ERS—is needed to handle a large, sudden release of a toxic species. For example, these units are often dedicated to the exhaust ventilation of gas cylinder storage areas. The three types of abatement systems are usually not in competition with each other. That is, a POU system could not be used as a house scrubber nor would a house scrubber be used at the POU. In addition, the use of one type of scrubber system usually does not greatly impact the use of another type. For example, the presence of a house scrubber will not eliminate the need for POU systems or vice versa. The various advantages of each abatement type are described next.

26.1.1 Point of Use Scrubbers Increased Tool Productivity. POU scrubbers help keep semiconductor process tools running. For example, POU systems remove reactive gas species before they can form solids within the ductwork. In the case of metal etch, POU water scrubbers effectively remove BCl3 and AlCl3. Both materials are reactive with air and water, while AlCl3 is also condensable. In the absence of a POU scrubber, these compounds will react with water vapor and/or air at the location where the tool exhaust combines with the house exhaust system (note that the house exhaust mostly comprises air

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

26.1

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.2

WASTE GAS ABATEMENT SYSTEMS 26.2

GASES AND CHEMICALS

from the fab). Over time, the solid by-products will tend to accumulate and corrode the duct. In the case when a house exhaust duct becomes clogged or forms a leak, not only is expensive maintenance required, many production tools within the fab are likely to be affected. One option to avoid clogging is to run a dedicated process exhaust line all the way from the tool to the house scrubber. The disadvantage of this method is primarily cost due to the long lengths of tubing often required—a process tool might be a couple of hundred feet or more away from an available house scrubber. Also, for processes with condensable species, the entire line length must be heated. This is expensive from both a capital and operating expense standpoint. Additionally, using a house scrubber as the primary method of abatement for many process tools may be risky. Not only must the house scrubber be appropriately sized, it also must run 100 percent of the time. Any required maintenance of the house scrubber would cause many process tools to be shut down (as opposed to only one tool for a POU scrubber). For these reasons, it is often found that POU scrubbers are the least expensive method of abatement and provide the highest level of process tool utilization. Improved Safety. POU scrubbers remove toxic and hazardous compounds at or near the location of their use. This reduces the chance of incompatible compounds (e.g., SiH4 and NF3, H2 and O2) mixing within the house exhaust system, avoiding the possibility of an explosion or fire. Additionally, the removal of these compounds at the POU contains these species to specific locations within the fab, reducing the risk of exposure to workers. Environmental Compliance. Because POU systems are usually tailored to specific semiconductor manufacturing processes, they commonly remove between 99 and 99.99 percent of effluent gases, allowing the fab to meet regulatory requirements. For example, water scrubbers are often used for metal etch where the effluent gases are water reactive or soluble. In the case of plasma-enhanced chemical vapor deposition (PECVD), an integrated system containing a burner chamber and water scrubbing tower is common. For ion implant, dry adsorption scrubbers are usually best suited. A second reason for the high efficiency is that the total effluent flow is relatively small at the point of use, and is not highly diluted by ventilation air unlike the house exhaust ducts that lead to the house scrubber. One specific area where POU scrubbers are used primarily for environmental compliance is for PFC (perfluorinated compound) abatement. PFCs are known to be very strong infrared absorbers making them suspected agents of global warming. Due to the semiconductor industry’s strong stance against the emission of potential global warming compounds, many fabs are using scrubbers specifically designed to treat PFCs. Note that many PFCs are inert from a health and safety perspective. 26.1.2 House Scrubbers Environmental Compliance. The primary purpose of house scrubbers is to ensure that regulatory requirements associated with the emission of toxic and hazardous air pollutants are met. House scrubbers are often used in applications where the exhaust flow is relatively high (greater than 10 to 100 SCFM, depending on the process). Typically, the ventilation from fume hoods, wet benches, gas cabinets, and process tools goes to a house scrubber. The exhaust stream usually has a relatively small concentration of toxic species, and there is minimal chance of clogging or corrosion. In these applications, exhausts from multiple tools/hoods can be manifolded to a single scrubber with only a small risk of downtime. Additionally, (with a few exceptions) the exhaust of POU scrubbers is plumbed into the house exhaust system, eventually making its way to the house scrubber. If any small concentrations of toxic species are present in the POU exhaust, the house scrubber can be designed to further remove these compounds. 26.1.3 Emergency Release Scrubbers Safety. ERS units are often placed in locations where the potential exists for a large release of a toxic or hazardous gas. The most common application is in the exhaust ventilation of cylinder storage bunkers.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.3

WASTE GAS ABATEMENT SYSTEMS WASTE GAS ABATEMENT SYSTEMS

26.3

ERS units are also sometimes installed on gas cabinet exhausts. In the event of a leak, the ERS units are typically sized to remove the full contents of a given cylinder. For highly toxic compounds such as arsine, phosphine, and diborane (among others), a significant release to the environment could pose a serious health and safety hazard to employees and residents in the vicinity. Emergency release scrubbers dramatically reduce this risk. Environmental Compliance. Although safety is probably the primary purpose of the ERS, complying with environmental regulations in the event of a leak or release is also a critical reason for installing these scrubbers.

26.2 FUNDAMENTALS AND PRINCIPLES In the semiconductor industry, there are generally five types of chemical or physical unit operations utilized in the abatement or removal of toxic and hazardous gases from waste streams. A given abatement system may utilize one unit operation or may integrate two or more. The unit operations are described next. 26.2.1 Thermal Oxidation and/or Decomposition These units rely on high temperatures to chemically oxidize or reduce semiconductor exhaust gases to less toxic or more manageable by-products. For example, to abate silane gas, air or oxygen is flowed into the abatement unit to create an oxygen-rich environment that oxidizes silane to silicon dioxide and water vapor. The silicon dioxide particulate is later removed by a filter, cyclone separator, or gas absorption tower. In another example, fluorine gas is reacted with hydrogen fuel to yield hydrogen fluoride (HF), which is easier to remove in a subsequent gas absorption scrubber. In the case of PFCs, water vapor is often added to produce HF and CO2 by-products. The thermal abatement scrubber operates on the premise that chemical reaction rates increase with temperature. For a given reaction between species X and Y, the rate can be expressed as1 r = k[X]x[Y]y

(26.1)

k = AT bexp(−Ea/RT)

(26.2)

where r = chemical reaction rate k = rate constant [X] = concentration of species X [Y] = concentration of species Y x = empirical factor y = empirical factor A = preexponential factor T = temperature (K) b = empirical parameter Ea = activation energy R = universal gas constant In most semiconductor processes, the concentration of effluent species is largely dictated by the process recipe and cannot be changed to suit the abatement device. Therefore, the only way to controllably increase a reaction rate is to increase the reaction rate constant (see Eqs. (26.1) and (26.2)). For a given chemistry, the only way to do this is by increasing the temperature. As shown in Eq. (26.2), the reaction rate constant increases exponentially with temperature. Of course, some species will react or decompose faster at a given temperature than others. Approximate temperatures required for four compounds are shown in Table 26.1.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.4

WASTE GAS ABATEMENT SYSTEMS 26.4

GASES AND CHEMICALS

TABLE 26.1 Approximate Decomposition Temperatures for Four Perfluorinated Compounds2 Gas species

Decomposition temperature (°C)

CF4 C2F6 SF6 NF3

~1120 842 ~800 300

It is important to note that thermal scrubbers are only useful for reactions in which the thermodynamics favor the products. For example, one could not use a thermal scrubber to create hydrogen and oxygen from water. 26.2.2 Gas Absorption Also known as water scrubbing, gas absorption is the process of removing gaseous species from an effluent stream by contacting the effluent stream with a liquid—usually water or an aqueous solution. This can be achieved by using a structured or random bed of packing media to provide the contact surface area, or the abatement device can simply be a spray tower or a bubble column (where the gas is dispersed directly into a liquid bath). The process of y absorption works best for cases where the effluent gas species is either water soluble or water reactive. yi Additives can also be metered into the liquid solution to react with the effluent gas species. xi x The mechanism of gas absorption is described in Refs. 3, 4, and 5 and will only be summarized Gas Liquid here. To get from the gas phase to the liquid phase, the effluent species must travel through an interfacial region composed of gas and liquid films as Gas Liq. shown in Fig. 26.1. The concentration of the gas film film species, y in the bulk fluid, decreases across the gas FIGURE 26.1 A simplified concentration profile of a film until it reaches a value of yi at the interface. given effluent species between liquid and gas phases. This concentration is in thermodynamic equilibrium with the concentration of the effluent species in the liquid film, xi. The expression relating the two values is that of the vapor liquid equilibrium. For low concentrations, the curve is usually linear and is termed Henry’s law. yi = Hxi

(26.3)

where H is Henry’s law constant. The effluent concentration continues to decrease until it reaches the bulk concentration in the liquid phase, x. Note that the actual values of y, yi, xi, and x, as well as the film profiles, are functions of the effluent gas, liquid composition, and the fluid dynamics of the system. The rate at which effluent gases transfer from the gas phase to the liquid phase can be shown to be equal to the following:3 NA = KG (y − y*) = KL(x* − x) where NA = rate of mass transfer (per unit area of interfacial surface) KG = overall gas phase mass transfer coefficient KL = overall liquid phase mass transfer coefficient y* = Hx = theoretical equilibrium vapor concentration over bulk liquid phase x* = y/H = theoretical equilibrium liquid concentration under bulk gas phase

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

(26.4)

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.5

WASTE GAS ABATEMENT SYSTEMS WASTE GAS ABATEMENT SYSTEMS

26.5

Therefore, to improve the rate of absorption, it is necessary to have one or more of the following—(i) a large concentration gradient, (ii) a large mass transfer coefficient, or (iii) a large amount of interfacial surface area. A large concentration gradient is often obtained with highly soluble gases. This is because high solubility is synonymous with a low Henry’s law constant, yielding a low value of y*. One example is hydrogen chloride (HCl). At room temperature, a 2-wt percent solution of HCl (equivalent to a pH near zero), only has an HCl vapor pressure of 8.4E-5 torr, which is equivalent to approximately 0.1 ppm in air. The Henry’s law constant is 1E-5. Contrary to this, chlorine gas has a Henry’s law constant of about 60 for dilute streams, and is therefore much more difficult to remove in a water scrubber unless a reactive agent is added to the liquid. The reactive agent works by effectively reducing the Henry’s law constant to zero. Alternatively, a larger makeup water flow rate can be employed in order to keep the liquid phase concentration of chlorine low enough such that a driving force is still present in the gas-phase film. An interesting aside is that gas solubility generally increases as the temperature decreases. Therefore, heat exchangers in small absorbers or evaporative cooling in larger units can actually improve scrubbing efficiency. The overall mass transfer coefficients are functions of the fluid properties (e.g., viscosity and density of the liquid and gas phases), the liquid and gas flux rates, the gas species diffusivity, and the packing or water droplet diameter among other things. For example, because the diffusivity of a gas increases with decreasing molecular weight, compounds such as HCl and HF will tend to yield higher mass transfer coefficients than WF6 or BF3. Another example is that scrubbers with larger liquid flux rates will tend to be more effective. Good correlations for gas and liquid phase mass transfer coefficients have been determined by Onda et al.6 The third method to improve the overall rate of mass transfer is to increase the amount of interfacial area between the gas and liquid phases. This can be accomplished through the use of smaller packing media or, in the case of a spray tower, can be done by reducing the droplet size without reducing the liquid flow rate. So far, only the rate of mass transfer has been discussed (NA). The total amount of effluent mass transfer (removal) will also depend on the depth of the absorber unit. The simplified expressions are shown below: Z = NTU × HTU HTU a

1 K

NTU = ln(yin/yout)

(26.5) (26.6) (26.7)

where Z = bed depth of absorber NTU = number of transfer units HTU = height of a transfer unit K = overall mass transfer coefficient yin = inlet gas phase effluent concentration yout = outlet gas phase concentration desired From Eqs. (26.5) to (26.7), the following observations can be made: 1. The outlet concentration from the absorber decreases exponentially with increasing bed depth. 2. The outlet concentration from the absorber decreases exponentially with increasing overall mass transfer coefficient. 3. The outlet concentration from the absorber decreases linearly with decreasing inlet concentration. It is important to note that the expression shown in Eq. (26.7) is only valid for the case of highly soluble or reactive gases, where the Henry’s law constant approaches zero. When this condition is not satisfied (e.g., chlorine or ammonia scrubbing with water), Eq. (26.7) is modified3 to account for the Henry’s law constant as well as the liquid and gas flow rates. In this regime, the makeup water flow rate to the absorber unit can become the critical performance parameter.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.6

WASTE GAS ABATEMENT SYSTEMS 26.6

GASES AND CHEMICALS

26.2.3 Gas Adsorption Adsorption-based scrubbers, sometimes referred to as “dry scrubbers,” utilize a solid, high-surfacearea adsorbent medium to capture effluent species. The process can either be physisorption in which the effluent species reversibly adsorbs onto the adsorbent surfaces, or, more commonly, it is chemisorption in which the effluent not only adsorbs but also chemically reacts (irreversibly) with the adsorbent Gas path (Fig. 26.2). There are a number of transport processes that an effluent molecule must undergo during the process of adsorption. These include Reaction zone

i. Transport from the bulk effluent stream to the adsorbent particle outer surface ii. Diffusion from the surface to within the interior of the highly porous adsorbent particles iii. Transport from the gas phase to the surface (adsorption) iv. Reaction with the surface

Additionally, any product gases must desorb from the surface and make their way to the bulk flow stream. Processes (i) and (ii) can generally be improved by decreasing the particle size of the adsorbent, although FIGURE 26.2 A view into an adsorbent parthis leads to a higher pressure drop across the bed. ticle. Process (iii) is usually not rate limiting, while the speed of process (iv) is dictated by the chemistry of the adsorbent and of the adsorbate (effluent species). Also, because process (iv) is a chemical reaction, temperature can be used to increase the rate as is done in thermal scrubbers. The performance of a given adsorbent is often characterized by the amount of adsorbate removed per unit volume of adsorbent. An arbitrary adsorbate concentration at the outlet of the adsorbent scrubber must be chosen as the endpoint condition. In the semiconductor industry, this is commonly chosen to be the OSHA permissible exposure limit (PEL),7 the NIOSH recommended exposure limit (REL),8 or the ACGIH threshold limit value (TLV)9 of the particular species of interest—see Table 26.2 for a list of PELs and RELs. Figure 26.3 shows the progression of the reaction zone through the adsorbent bed as a function of time. Although much work has been performed in the field of adsorption, it is difficult to estimate the absolute performance of a given adsorbent for a given effluent gas—although the trends described previously relating to processes (i) through (iv) are valid. Therefore, the performance is often characterized experimentally as a function of the inlet species concentration and the total gas-space velocity through the adsorbent bed.

26.2.4 Plasma-Enhanced Reaction A relatively new technique for abating PFCs, plasma units create electrically excited ions and electrons to bombard the PFC molecules, creating unstable intermediates and radicals. These intermediates and radicals then react with additive gases such as H2, O2, or H2O to form CO2 and HF. Whereas all other types of abatement systems are commonly operated at atmospheric pressure, many plasma scrubbers operate at pressures close to that of the semiconductor processing tool (less than 10 torr). In these units, the effluent gas is in nonthermal equilibrium with the electrons. That is, the electrons have energies equivalent to temperatures nearing 10,000°C, while the effluent gas temperature remains relatively low (room temperature to approximately 100°C). Because the plasma scrubber does not heat the effluent gas significantly, the energy used to abate the PFC molecule can be an order of magnitude less than that associated with a thermal scrubber.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Si2H6 F2 CH3F GeH4 GeF4 He H2 HBr

Disilane

Fluorine Fluoromethane

Germane

Germanium tetrafluoridek Helium Hydrogen Hydrogen bromide

N.E. S.A. S.A. 3

N.E.

0.1 N.E.

N.E.

N.E. N.E. N.E.

N.E. S.A. S.A. 3j

0.2

0.1 N.E.

N.E.

N.E. S.A. S.A. N.E.

N.E.

N.E. N.E.

N.E.

N.E. S.A. S.A. 30

N.E.

25 N.E.

N.E.

N.E. N.E. N.E.

SiH2Cl2 CH2F2 SiH2(CH3)2

Dichlorosilanek Difluoromethane Dimethylsilane

N.E. N.E. N.E.

15

N.E.

0.1

B2H6

Diborane

3.9-78 percent N.A. N.A. N.A. N.A. N.A. N.A. 12.5-74 percent N.A. N.A. N.A. N.A. Unknown; flashpoint is 80°C11 0.8-98 percent; pryophoric 2.5-98.8 percent 14–31 percent LEL = 1.3 percent; unknown UEL LEL = 0.2 percent; unknown UEL; pyrophoric N.A. UEL = 22.2 percent; unknown LEL UEL = 100 percent; unknown LEL pyrophoric N.A. N.A. 4-75 percent N.A.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

(Continued)

B, C Not abated A B, C

A, C

A, B, C A, C*, D

A, C

A, B, C A,C*, D A, C

A, C

A, B, C B, C B, C B, C B, C B, C Not abated A, C B, C B, C B, C B, C C, E

Not abated Varies

A, B, C Varies

Abatement methodsg

20:53

N.E. N.E. N.E.

3 N.E. N.E. 25 3 N.E. 40,000 1200 2 N.E. 10 20 15 mg/m3

0.002i mg/m3 N.E. N.E. N.E. 0.3 N.E. 30,000 200 0.2i 5 0.5i N.E. 0.15

N.E. 1j N.E. 1j 0.1 0.1 5000 35 0.1 2 N.E. 0.1j 0.05

0.05 N.E. N.E 1j 0.1 N.E. 5000 50 0.1 N.E. N.E. 0.1j 0.05

AsH3 BBr3 BCl3 BF3 Br2 BrF5 CO2 CO COCl2 COF2 Cl2 ClF3 B10H14

N.A. N.A.

15–30 percent N.A.

Flammable limitsf

04/04/2005

0.1

S.A. 5 mg/m3

S.A. 0.002i mg/m3

S.A. N.E.

S.A. 0.01 mg/m3

Ar As

300 50 mg/m3

IDLHe (ppm)h

35 N.E.

STELd (ppm)h

25 0.5 mg/m3

RELc (ppm)h

50 0.5 mg/m3

PELb (ppm)h

NH3 Sb

Formula

Ammonia Antimony and compounds as Sb, except stibine Argon Arsenic (inorganic compounds as As, except arsine) Arsine Boron tribromide Boron trichloridek Boron trifluoride Bromine Bromine pentafluoride Carbon dioxide Carbon monoxide Carbonyl chloride Carbonyl fluoride Chlorine Chlorine trifluoride Decaborane

Compound

TABLE 26.2 Exposure Limits, Flammability Ranges, and Abatement Methods for Commonly Used Chemicals in the Semiconductor Industrya

Geng(SMH)_CH26.qxd Page 26.7

WASTE GAS ABATEMENT SYSTEMS

26.7

26.8 SiCl4 SiF4

Silicon tetrachloridek Silicon tetrafluoridek

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. N.E. N.E.

N.E. N.E.

N.E. N.E.

3 mg/m3 0.5 N.E. 0.5 N.E. N.E. N.E.

1 mg/m3 0.1 1 mg/m3 0.2 N.E. N.E. 5

1 mg/m3 N.E. 1 mg/m3 0.5 N.E. N.E. N.E.

H3PO4 POCl3 PCl5 PCl3 PF5 PF3 SiH4

Phosphoric acid Phosphorus oxychloride Phosphorus pentachloride Phosphorus trichloride Phosphorus pentafluoridek Phosphorus trifluoridek Silane

N.E. N.E. N.E. N.E. N.E. 1

0.05j 0.1j N.E. N.E. N.E. 0.3

0.05 0.1 N.E. N.E. N.E. 0.3

OF2 O3 CF4 C2F6 C3F8 PH3

N.E. N.E.

1000 mg/m3 N.E. 70 mg/m3 25 N.E. N.E. N.E.

0.5 5 N.E. N.E. N.E. 50

25 100 S.A. 20 1000 N.E. N.E N.E N.E.

100 S.A. N.E. S.A. 2

50 50 30 1

IDLHe (ppm)h N.A. 5.6-41 percent N.A. Unknown, but flammable 4-46 percent N.A. 1.3-88.9 percent N.A. LEL = 2 percent; unknown UEL N.A. N.A. N.A. N.A. N.A. N.A. N.A. N.A. Unknown, but flammable N.A. N.A. N.A. N.A. N.A. LEL = 1 percent; unknown UEL N.A. N.A. N.A. N.A. N.A. N.A. 0.8-98 percent; pyrophoric N.A. N.A.

Flammable limitsf

B, C B, C

B B, C B, C B, C B, C B, C A, C

B, C A, C A, C*, D A, C*, D A, C*, D A, B, C

B B, C Not abated B, C A, C* A A, C*, D A, C*, D A

A, B, C Not abated A, C Not abated A, C

B, C A, B, C B, C A, C

Abatement methodsg

20:53

4 N.E. S.A. 1 N.E. N.E N.E. N.E. N.E

10m S.A. N.E. S.A. N.E.

N.E. 4.7 6i N.E.

STELd (ppm)h

04/04/2005

2 25 S.A. N.E. 10 25n N.E. N.E. N.E

2 25 S.A. 5j 10 N.E N.E. N.E. N.E

HNO3 NO N2 NO2 NF3 N 2O C4F8 C5F8 C8H24O4Si4

Nitric acid Nitric oxide Nitrogen Nitrogen dioxide Nitrogen trifluoride Nitrous oxide Octafluorocyclobutane Octafluorocyclopenteneo Octamethylcyclotetrasiloxanep Oxygen difluoride Ozone Perfluoromethane Perfluoroethane Perfluoropropane Phosphine

N.E. S.A. N.E. S.A. 0.001

20 j, 50l S.A. N.E. S.A. 0.001

H 2S Kr SiH3CH3 Ne Ni(CO)4

Hydrogen sulfide Krypton Methylsilane Neon Nickel carbonyl

5j N.E. 3 0.05

RELc (ppm)h

5j 10 3 0.05

PELb (ppm)h

HCl HCN HF H2Se

Formula

Hydrogen chloride Hydrogen cyanide Hydrogen fluoride Hydrogen selenide

Compound

TABLE 26.2 Exposure Limits, Flammability Ranges, and Abatement Methods for Commonly Used Chemicals in the Semiconductor Industrya (Continued )

Geng(SMH)_CH26.qxd Page 26.8

WASTE GAS ABATEMENT SYSTEMS

SO2 SF6 SF4 H2SO4 Si(OC2H5)4 C4H16Si4O4 Si(CH3)4 TiCl4 SiHCl3 CHF3 SiH(CH3)3 WF6 Xe

Sulfur dioxide Sulfur hexafluoride Sulfur tetrafluoride Sulfuric acid Tetraethylorthosilicate Tetramethylcyclotetrasiloxane

Tetramethylsilane Titanium tetrachloridek Trichlorosilanek Triflouromethane Trimethylsilane Tungsten hexafluoridek Xenon N.E. N.E. N.E. N.E. N.E. N.E. S.A.

5 1000 N.E 1 100 N.E.

0.1

N.E. N.E. N.E. N.E. N.E. N.E. S.A.

2 1000 0.1j 1 10 N.E.

0.1

N.E. N.E. N.E. N.E. N.E. N.E. S.A.

5 N.E. N.E. N.E. N.E. N.E.

N.E.

N.E. N.E. N.E. N.E. N.E. N.E. S.A.

100 N.E. N.E. 15 mg/m3 700 N.E.

5

Unknown, but flammable N.A. N.A. N.A. N.A. 1.4-23 percent Unknown, but flammable 0.9-37.9 percent N.A. 1.2–90.5 percent N.A. 1.3-44 percent N.A. N.A. A, C B, C A, B, C A, C*, D A, C B, C Not abated

B, C A, C*, D B, C B A, B, C A

A, C

04/04/2005 20:53

a Table notes are dictated by lettered superscripts. Source references for the data are shown as bracketed numbers. Abbreviations: “N.E.” means not established (but the compound could still be highly toxic); “N.A.” means not applicable; and “S.A.” means that the compound is a simple asphyxiant. b PEL stands for permissible exposure limit. These values are generated by the Occupational Safety & Health Administration (OSHA)7 and correspond to time-weighted-average (TWA) exposure limit concentrations for an 8-h workday of a 40-h workweek. c REL stands for recommended exposure limit. These values are generated by the National Institute for Occupational Safety and Health (NIOSH)8 and correspond to TWA exposure limit concentrations for up to a 10-h workday of a 40-h workweek. d STEL stands for short-term exposure limit. These values are generated by NIOSH and correspond to TWA exposure limit concentrations in a 15-min period that are not to be exceeded any time during the workday. e IDLH stands for immediately dangerous to life and health. These values are generated by NIOSH and correspond to concentrations that could cause permanent injury or death if the exposure duration is 30 min. NIOSH recommends that every effort be made to immediately leave an IDLH environment if proper respiratory and other necessary protective equipment is not being used. f Flammability limits are given as volume percents. “N.A.” means not applicable and infers that the compound will not propagate a flame in air. However, the compound could still be highly reactive with air (e.g., BCl3). Data represent the most conservative values found for the lower and upper explosion limits (LEL and UEL, respectively). g Abatement methods are as follows—A = thermal oxidation or decomposition; B = gas absorption (water scrubbing); C = gas adsorption (dry scrubbing); C* = heated gas adsorption (e.g., hot catalyst bed); D = plasma; E = condensation/cold trap; F = filtration. The table shows what abatement method types have been used for successful treatment of the particular compounds, and does not necessarily mean that other types would not work as well. Conversely, just because a given abatement system has been successfully used in the past does not guarantee that it will work for all applications. It is important that for each application of interest the abatement system be designed or specified by someone trained and experienced in the art. For example, water scrubbers can be used to abate arsine gas, but they must be properly sized and be outfitted with a means for injection of specific oxidizing agents (e.g., KMnO4 or NaOCl). h Units are in parts per million (ppm) by volume unless specified otherwise. i This is a 15-min ceiling value. j This is a ceiling value that should not be exceeded at any time. k Although no exposure limits are provided, it is important to note that this compound will tend to react with moisture in air. Therefore, it will be at least as toxic as its hydrolysis by-products. For example, BCl3 + 3H2O → H3BO3 + 3HCl. In this case, one should be aware of the exposure limits for HCl and H3BO3 and take care to consider the reaction stoichiometry. l This is a 10-min max peak. m This is a 10-min ceiling value. n This is a TWA over the time exposed. o One manufacturer recommended an 8-h TWA of 2 ppm. p One manufacturer recommended an 8-h TWA of 5 ppm.

SbH3

Stibine

Geng(SMH)_CH26.qxd Page 26.9

WASTE GAS ABATEMENT SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

26.9

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.10

WASTE GAS ABATEMENT SYSTEMS 26.10

GASES AND CHEMICALS

Outlet Inlet

Sensor tube

Mass transfer zone

Breakthrough detection

Fully reacted zone

Increasing time FIGURE 26.3

Adsorbent bed usage.

Certain types of plasma can be operated at atmospheric pressure. The effluent gas temperature in these units can be relatively low (100°C) to very high (10,000°C). Plasma can be created in various ways. One method is to use RF or microwaves to induce the plasma (frequencies in the range of MHz to GHz). Other methods include various types of discharge plasma in which a high voltage source is brought into proximity with ground. Usually, a dielectric material can be used to distribute the electrical discharges uniformly throughout the reactor. Alternatively, the plasma can be designed in the shape of a nozzle to create a plasma gun. To further enhance chemical reaction rates, a catalyst or adsorbent can be placed within the plasma reactor. 26.2.5 Condensation Although not strictly an abatement method, condensation techniques have been used to remove condensable, low vapor pressure species from gas streams. Examples include AlCl3, WOF4, and elemental phosphorus. Typically, devices promoting condensation are referred to as cold traps. These units almost always utilize an active cooling agent such as cooling water in order to reduce the temperature of the effluent gas stream. As the effluent temperature is reduced, the equilibrium vapor pressure of condensable species also decreases. If the concentration of the condensable species entering the trap is higher than the vapor pressure within the trap, a phase change from gas to solid (or liquid) will occur. Removing condensable species from the effluent stream helps to reduce or eliminate clogging at the inlet of the primary abatement system, downstream from the cold trap. The theoretical maximum rate of effluent removed by a cold trap is equal to mc =

mt ( Pin − Pc ) Ptot

where mc = rate of condensation mt = total mass flow rate of effluent gas (including diluents) Pin = partial pressure of condensable species at inlet to cold trap Pc = equilibrium vapor pressure of condensable species within cold trap Ptot = total pressure of effluent stream The vapor pressure of the condensable species increases with temperature. Therefore, the rate of condensation will improve for colder cooling agents. Additionally, depending on the emission rate of condensable species from the tool, the inlet tubing to the condenser may have to be heated to avoid unwanted condensation prior to the cold trap.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.11

WASTE GAS ABATEMENT SYSTEMS WASTE GAS ABATEMENT SYSTEMS

26.11

26.3 MAJOR COMPONENTS Table 26.3 lists many of the components and features available within each of the five gas abatement technologies. A description of these components and features for each technology follows. 26.3.1 Thermal Oxidation and/or Decomposition The following is a list of components usually associated with thermal scrubbing systems. 1. Multiple entries: Allows the effluent from more than one chamber to be processed. 2. Smart entry design: Reduces the frequency of solids clogging the entry structures, which would result in tool downtime. 3. Inlet pressure switch: Indicates clogging anywhere within the abatement system. 4. Fuel and/or additive gas inlets: Necessary to promote the reaction and/or decomposition of effluent species. 5. Flow indicators or controllers on fuel and additive inlet lines: Ensures that the proper fuel and additive flow is being delivered to the abatement system. 6. Reaction zone: Location where the effluent species are reacted or decomposed. The zone could be electrically heated or might use fuel. Generally, electrically heated units require between 1 to 10 kW of power, while fuel units may require 10 to 50 slpm (standard liters per minute) of hydrogen or natural gas. 7. Temperature controller: A thermocouple or other temperature measurement device is used to monitor the reaction zone temperature. Many units have feedback control to adjust the electrical or fuel input flow rate accordingly.

TABLE 26.3 Typical Components and Features of Five Gas Abatement Technologies Component or feature

Thermal

Absorption

Adsorption

Multiple inlets Low clogging inlets Inlet self-cleaning mechanism Inlet pressure switch or gauge Gas-phase reaction zone Gas-liquid contact zone Gas-solid contact zone Adsorbent media Temperature monitor/controller Pressure control Liquid sump with level control Pump Thermal quench section Particulate removal device Interface and control system Toxic gas sensor Scrubbed bypass Fuel and/or oxidizer injection Liquid chemical injection Cooling water Makeup water

X X X X X

X X X X

X

*

Plasma

Condensation

X X

X

X

X* X* X X X

X X X X

X X X*

X X X

X X X X

X X X X

X

X

X X X

Present for the case of an integrated thermal-gas absorber abatement system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

X

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.12

WASTE GAS ABATEMENT SYSTEMS 26.12

GASES AND CHEMICALS

8. Self-cleaning mechanism: Some thermal abatement units have a device that automatically cleans the entries and reaction zone when oxide deposits form. Note that many oxidation by-products are solids. Examples include silicon and tungsten oxides. 9. Quench section: Just downstream of the reaction zone, this is a section in which by-product gases are mixed with air or water to reduce the temperature. 10. Particulate removal device: As previously mentioned many by-products of oxidation or decomposition are solids. One or more devices to remove much of this particulate are often located after the quench section. Examples include cyclone separators, gas absorption towers, filter elements, electrostatic precipitators, and spray towers. 11. Acid gas removal: Acids such as HF and HCl are common by-products formed in the reaction zone. A gas absorption tower (water scrubber) is often integrated with the thermal scrubber to remove these gases. In fact, the most prolific POU abatement systems on the market comprise a thermal unit followed by a gas absorption tower. 12. Human machine interface (HMI) and programmable logic controller (PLC): Allows for operation of the scrubber. Ensures that the unit is shut down or sends alarms under the appropriate circumstances. May also allow for automated logging of critical data.

26.3.2 Gas Absorption Common components found in water scrubbers are listed below. 1. Multiple entries: Allow the effluent from more than one chamber to be processed. 2. Smart entry design: Reduces the frequency of solids clogging the entry structures, which would result in tool downtime. Some entries are designed to automatically clean themselves. 3. Inlet pressure switch: Indicates clogging anywhere within the abatement system. 4. Gas/liquid contacting chamber: May contain a high-surface-area packing material, or may simply be a spray tower. Usually, multiple spray nozzles distribute the water into the chamber. The nozzles may be part of a rotating hub or may individually move in order to cover the full cross section of the chamber. The chamber is normally constructed of acid resistant plastics, although some chambers are made from stainless steel. 5. Liquid collection sump: Below the gas/liquid contact chamber, a sump is present to collect the liquid. The gas outlet is located above the liquid level to avoid liquid entrainment. 6. Recirculation pump: A pump is located below the sump. It recirculates the scrubbing liquid back to the spray nozzle assembly at the top of the gas/liquid contacting chamber. 7. Sump level switches: If the sump is not drained via gravity, level switches are necessary to control the sump liquid level. The switches send signals to a PLC, which then controls a wastewater valve. 8. Chemical injection: For the abatement of certain species, chemical additives must be used. These may be aqueous acid or base solutions or might be defoaming agents. A control system is necessary to inject the appropriate quantity of chemical. 9. Secondary gas/liquid contacting chamber/s: Additional scrubbing chambers further reduce the effluent species concentration levels. These chambers are outfitted with spray nozzles or liquid injection devices and will often times contain high-surface-area packing materials, although this is not always the case. 10. Makeup water flow meter or controller: Controls the flow rate of freshwater to the scrubber. 11. Demister: Located near the scrubber outlet, this device helps remove small droplets of entrained water. 12. HMI and PLC: Allows for the operation of the scrubber. Ensures that the unit is shut down or sends alarms under the appropriate circumstances. May also allow for automated logging of critical data.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.13

WASTE GAS ABATEMENT SYSTEMS WASTE GAS ABATEMENT SYSTEMS

26.13

26.3.3 Gas Adsorption Figures 26.4 and 26.5 show schematics of POU adsorption scrubber units. Typical components are: 1. Adsorbent-containing vessels: One or more canisters containing the adsorbent material/s are usually placed within a cabinet containing a tubing manifold that directs the flow of effluent gases. Within the vessels themselves are sometimes found flow distributors, subcompartments for different adsorbents, and a sensing tube to sample the concentration of toxic species in the outlet of the vessel. It is important to note that different adsorbents are usually required for different gas types. For example, an acid gas (e.g., HCl) adsorbent will usually not work well on hydride gases (e.g., AsH3) and vice versa. 2. Pressure control: Due to the possibility of solids accumulating within the adsorbent bed, a venturi or small blower is sometimes installed downstream of the adsorbent vessels in order to maintain a given pressure at the inlet of the vessels. 3. Gas sensor: Determines the concentration of the toxic species in the adsorbent vessel outlet. Determines when the adsorbent requires replacement. 4. Temperature sensor: Measures the temperature within the adsorbent bed for safety purposes. 5. Temperature control: Some adsorption units are heated to enhance the decomposition rates of effluent gases. This is particularly true in the abatement of PFC gases with adsorption scrubbers. 6. Flow meters or controllers: Allow the flow control of nitrogen purge gas and in some cases for clean dry air, which is used for regenerating adsorbent materials. 7. Bypass: Used when canisters are off-line. Sometimes a small additional canister is installed within the bypass line to ensure a 100 percent scrubbing efficiency. 8. HMI and PLC: Allows for the operation of the scrubber. Ensures that the unit is shut down or sends alarms under the appropriate circumstances. May also allow for automated logging of critical data. 26.3.4 Plasma Reactor 1. Reaction chamber: Due to the fast reaction rates in a plasma device, this section is usually rather small and is often composed of a ceramic, nonelectrically conductive, corrosion resistant material. 2. Additive injection: To decompose many PFC materials, both an oxidizer and a reducer are often utilized. The oxidizer reacts with carbon to yield CO2, while the reducer reacts with fluoride to form HF. Some units use O2 and H2 gases as the oxidizer and reducer respectively, while others use water vapor. 3. Plasma control system: Many units have specific electronics to ensure the plasma is optimized. There may also be a visual indicator confirming when the plasma is on and off.

House exhaust 1 Inlet pressure transducer Process

Pressure controller 2

Eductor (Venturi pump)

Effluent Process pump

3

FIGURE 26.4 Effluent path from a vacuum pump through a POU adsorbent scrubber unit.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.14

WASTE GAS ABATEMENT SYSTEMS 26.14

GASES AND CHEMICALS

FIGURE 26.5

A look inside a POU adsorbent scrubber cabinet.

26.3.5 Condensation 1. Contact chamber: Condensers try to maximize the area of contact between the effluent gas and the cooling surfaces. The cooling surfaces may be in the form of coils, fins, plates, and the like. The chamber must be large enough to collect sufficient solids, yet not too large to avoid difficulty in handling. 2. Cooling fluid: Often this is house cooling water. 26.3.6 General Comments 1. Most abatement systems require power. This is most often 110 or 120 to 240 VAC single phase (50 or 60 Hz). Some units will use 208 VAC or higher three-phase power. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.15

WASTE GAS ABATEMENT SYSTEMS WASTE GAS ABATEMENT SYSTEMS

26.15

2. The design and operational compliance is often in accordance with SEMI and CE standards. 3. Inlet connections to POU abatement systems are usually common NW25, NW40, or NW50 vacuum flanges. Outlet connections may be any of these but may also be 4 in (100 mm) or 6 in (150 mm) in diameter.

26.4 IMPORTANT CONSIDERATIONS A number of issues should be reviewed and analyzed when choosing and operating abatement equipment. These are separated into the following categories—efficiency and waste streams, reliability, cost of ownership, installation requirements, and operational factors. 26.4.1 Efficiency and Waste Streams 1. What is the effluent removal efficiency of the abatement equipment? Is it enough to meet regulations and fab safety guidelines? One example is the abatement of arsine. Due to its very high level of toxicity, many fabs require that POU abatement systems remove arsine to less than 50 ppb (OSHA PEL). 2. Usually POU abatement system vendors will require general process information in order to quote an appropriate scrubber and efficiency. The typical information required includes the flow rate of each process gas, the amount of time the gas is flowed per day or week, the concentration of the gas in the source bottle, as well as the total nitrogen gas flow rate coming to the abatement system. Note that the nitrogen flow predominately comes from the vacuum pumps. The house scrubber vendors will likely require information detailing the typical hazardous gas concentration at the scrubber inlet as well as the total air flow rate. 3. If the abatement unit incorporates an absorption tower, it is important to avoid local minima points in the exhaust ducting after the scrubber. Even if the absorption unit is 99 percent efficient, the concentration of acid gases and water vapor in the scrubber exhaust may be sufficient to cause corrosion problems in the house ducting. 4. Does the abatement system produce any waste? For example, the adsorbent media from dry scrubbers must be disposed of when it has become spent. If the adsorbent media contains certain compounds (e.g., arsenic, selenium, chromium, lead, or other regulated materials), the adsorbent may be considered hazardous waste. For water scrubbers, or a thermal unit with a gas absorption tower, the wastewater will likely need some type of treatment. This could range from pH treatment to fluoride treatment to arsenic treatment depending on the application. 5. Plasma-based scrubbers produce F2, HF, and/or COF2 depending on the additives used. It may be important to use a POU wet scrubber after a plasma unit or at the minimum one should be aware of the added load the acid gases place on the house scrubber. 6. Thermal scrubbers may produce solid particulate through the combustion of certain effluent gases. Does the scrubber have a means for removing these particles? Are these compounds toxic and will they require special protective equipment to be worn by the employees during maintenance? Additionally, thermal scrubbers may produce NOx and/or CO as by-products, depending on the application. 26.4.2 Reliability 1. Components historically requiring the most maintenance include the inlet of water scrubbers due to clogging, the reaction chambers of thermal units and plasma scrubbers due to clogging or corrosion, and the recirculation pumps used in gas absorption systems (as well as integrated units containing wet sections) due to corrosion. In addition, dry scrubbers require the replacement of the adsorbent beds with a frequency in proportion to the effluent gas load to the scrubber. Condensation units must be cleaned on a regular basis. Most vendors of abatement equipment can provide the mean time between failure (MTBF) data for their equipment. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.16

WASTE GAS ABATEMENT SYSTEMS 26.16

GASES AND CHEMICALS

2. How long does it take to repair a unit that requires maintenance? This is known as mean time to repair (MTTR). Often times it is possible to install a spare component in order to get the abatement system up and running as soon as possible. The damaged or clogged component can then be repaired or cleaned off-line. 3. The reliability of abatement units is one of the most important factors when making a procurement decision. Any time a scrubber undergoes maintenance, the process tool that it serves must be shut down. Because process tools are the most expensive investment for a fab, any length of time they are not operating is very costly. 4. One option to reduce the cost of scrubber downtime is to install a small bypass system to be used during the maintenance of the primary scrubber. 26.4.3 Cost of Ownership 1. What consumables does the scrubber require? Examples include fuel, nitrogen, air, oxygen, electricity, cooling water, makeup water, ventilation, adsorbent media, and chemical injection agents. A good source that provides a list of some of these consumables with their associated costs is Sematech.10 2. How much fab space does the scrubber take up? 3. How much will it cost to install the abatement equipment? 4. How much will it cost to maintain the equipment? 26.4.4 Installation Requirements 1. What facilities are required by the abatement unit (e.g., air, N2, fuel, electricity, water)? Does the fab have access to all of these? 2. What is the size of the abatement system and how much clearance space is required around the unit for maintenance? 3. Most abatement units are installed downstream of the vacuum pump. However, some of the newer plasma systems need to operate upstream. It can be a very costly mistake to install a low-pressure plasma abatement unit downstream of the vacuum pump. 4. For POU units installed downstream of the pump, will the tubing connecting the pump to the abatement device need to be heated or require a cold trap? Processes that may require such action are metal etch, tungsten CVD, MOCVD, and LPCVD nitride because they produce condensable species as by-products. 5. What is the exhaust draw requirement of the abatement system and can the fab supply this? Most abatement equipment operates at slightly negative pressure (−0.5 in wc to −5 in wc). 6. How many chambers or tools will be plumbed to one POU scrubber unit? More chambers or tools per scrubber can save on scrubber expenditures, but could have serious consequences on tool downtime in the future. 26.4.5 Operational Factors 1. What type of control system and interface does the scrubber utilize? Is it straightforward to operate? Many POU scrubbers have PLCs and HMIs that offer a large number of capabilities. 2. Will the abatement system need to be controlled or accessed remotely? If so, does the system have these capabilities? 3. Sometimes fabs require that if the abatement unit fails, it sends a signal to automatically shut down the semiconductor process tool. To do this, the abatement system must be capable of sending an output signal.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.17

WASTE GAS ABATEMENT SYSTEMS WASTE GAS ABATEMENT SYSTEMS

26.17

4. For many systems it is critical that noncompatible gases are not mixed together before or within the unit. An example is a water scrubber treating the effluent from a silicon EPI process. Byproducts consist predominantly of H2, HCl, N2, and chlorosilanes. If more than one tool or chamber is connected to a given scrubber, there is the real chance that during maintenance of one of the tools, air could get into the system and create an explosive mixture in the scrubber. Although still needing an ignition source to create an explosion, it is highly desirable to always avoid creating explosive mixtures.

26.5 FUTURE TRENDS Three items have the focus of most abatement vendors. First, a large amount of effort is currently being expended to make abatement systems more reliable, while at the same time increasing their capacity for effluent gases. Significant progress has been made in this endeavor in the past few years and we are likely to see additional improvements. A second focused effort is in the area of PFC abatement. Many companies have developed plasma scrubbers specifically for this purpose since they use less energy to effect the same removal efficiency. A third focus is in the area of new product concepts. For example, some work is being done on ways to concentrate the hazardous components of the effluent streams and then abate or recycle the materials. Abating a concentrated stream almost always requires less energy for a POU unit. Additionally, there is some interest in ways to catalytically crack ammonia into N2 and H2 and then to use H2 as a fuel or source to generate electricity.

REFERENCES 1. Turns, S. R., “Chemical Rinetics,” (chap. 4), in An Introduction to Combustion—Concepts and Applications, McGraw-Hill, New York, 2000, p. 117. 2. Getty, J. D., “Oral Presentation,” Semicon Korea, 1998. 3. Perry, R. H., D. W. Green, and J. O. Maloney, “Mass Transfer and Gas Absorption,” (sec. 14), “Liquid-Gas Systems” (sec. 18), in Perry’s Chemical Engineers’ Handbook, 6th ed., McGraw-Hill, New York, 1984. 4. Treybal, R. E., “Equipment of Gas-Liquid Operations,” (chap. 6), “Gas Absorption,” (chap. 8), in Mass Transfer Operations, 3rd ed. McGraw-Hill, New York, 1980. 5. Bird, R. B., W. E. Stewart, and E. L. Lightfoot, Transport Phenomena. John Wiley & Sons, New York, 1960. 6. Onda, K., H. Takeuchi, and Y. Okumoto, “Mass Transfer Coefficients Between Gas and Liquid Phases in Packed Columns,” J. Chem. Eng. Jpn. Vol. 1, pp. 56–62, 1968. 7. Occupational Safety & Health Administration, 1910.1000 Table Z-1, “Limits for Air Contaminants.” Available at: www.osha.gov. 8. National Institute for Occupational Safety and Health, “Pocket Guide to Chemical Hazards,” 1997. Available at: www.cdc.gov. 9. American Conference of Governmental Industrial Hygienists, “Guide to Occupational Exposure Values,” 2004. Available at: www.acgih.org. 10. O’Halloran, M., “Fab Utility Cost Values for Cost of Ownership (COO) Calculations,” International Sematech Technology Transfer #02034260A-TR, March 29, 2002. 11. United Stated Environmental Protection Agency (EPA), Chemical Profiles. Available at: www.epa.gov.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH26.qxd

04/04/2005

20:53

Page 26.18

WASTE GAS ABATEMENT SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 27

PFC ABATEMENT James C. Cox Hitachi High Technologies America Dallas, Texas

27.1 PERFLUOROCARBON COMPOUNDS 27.1.1

What Are PFCs? Perfluorocompounds (PFCs) are a class of compounds with all the bonding sites of the primary atom or atom chain occupied by fluorine atoms. Perfluorocarbon compounds are a subclass of perfluorocompounds with carbon as the primary atom or atom chain. Hydrofluorocompounds are not being completely fluorinated but instead have a mixture of hydrogen and fluorine in the bonding sites. Because of their useful properties, these classes of compounds have found wide acceptance in a range of industrial applications. In this chapter we will primarily concern ourselves with the use of and issues surrounding the applications of these compounds within the semiconductor (SC) industry. The acronym, PFC, is often loosely used in practice in the semiconductor industry to identify a class of chemical compounds utilized in chemical vapor deposition (CVD) and/or in etch processes. The problem within the SC industry is that there are examples of these chemical compounds that technically do not adhere to either the perfluorocompound or perfluorocarbon definition. The perfluorocompound definition is the broadest and encompasses an entire range of completely fluorinated chemicals. However, in the SC industry CHF3 (trifluoromethane) is often considered to be a PFC gas though it is technically a hydrofluorocompound. The perfluorocarbon definition is more specific in that it defines a completely fluorinated carbon or carbon chain molecule. However, just as trifluoromethane would not fit this definition either, the SC industry typically categorizes SF6 (sulfur hexafluoride) as a PFC gas. The reader must recognize that the PFC definition is far from perfect and that daily practices tend to override technical correctness. In this chapter the acronym PFC will be used in terms of the SC manufacturing environment to indicate any “highly” fluorinated compound typically used in CVD and/or etch processes to manufacture SC integrated circuits (ICs) unless specifically written as either perfluorocarbon or perfluorocompound.

27.1.2

Chemical and Physical Properties Chemicals in the PFC family are uniquely distinguished by their stability and inertness. The most commonly used PFCs for the SC industry (CF4, C3F8, C4F8, CHF3, and SF6) are gaseous in nature. They are colorless, odorless gases that are nonflammable and practically nontoxic. In addition, they are thermally stable and very chemically inert. In an industrial manufacturing environment that is filled with a myriad of acids, bases, and solvents that are quite harmful to people and the environment, Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

27.1

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.2

PFC ABATEMENT 27.2

GASES AND CHEMICALS

PFCs were viewed very favorably. PFCs meet the stringent process performance requirements while having almost minimum regulations. This was an extraordinary and quite uncommon position for SC manufacturing facilities. It meant that the PFC gas vendors could sell PFC gases cheaply to wafer fabs that used them to manufacture products but yet would incur little or no disposal costs.

27.1.3

Industrial PFC Usage Obviously, the major industrial benefit for using PFC gases is the absence of safety-related issues where people are involved in processes utilizing these gases. Due to such nonvolatility and nontoxicity, these compounds have, in the past, been much less restricted in usage than some of their counterparts used in other fab process applications. In fact, only since the mid-1990s have issues regarding the usage of these gases come to light. PFC gases are suspected of contributing to global warming. Prior to that, PFCs were the perfect industrial gases. PFCs do not attack the ozone layer, they are not at risk of exploding or reacting violently when mixed with other chemicals, and other than asphyxiation, these chemicals were not a threat coming into contact with operators or equipment technicians. All safety issues aside, PFC gases also offered the process performance and stability necessary for wafer fabs to build functional integrated circuits (ICs) and continually optimize processes for smaller and smaller geometries thus fueling the SC industry growth. Usage in the SC Industry. PFCs find two primary uses within the SC industry. The first is as a carbon and/or fluorine source in plasma etching and the second as a cleaning gas in CVD systems. In a typical SC wafer fab, the CVD clean operation is the larger consumer of PFCs compared to etch. In CVD clean processes, PFC gases are injected into a CVD chamber with no production wafers present. Radicals are created from the PFC clean gases in the presence of the plasma. The radicalized gases combine with solid residues coating the CVD chamber parts to form by-products that are gaseous in phase. These gaseous by-products are pumped from the chamber thus reducing or eliminating any remaining solid residue within the chamber. Solid residue is unwanted because it may pose a yield loss potential if particles from the residue get onto the wafer surface. Etch process usage of PFC gases is somewhat different in that the actual production wafers are created through the use of PFC gases that become etchants for a given material on the wafer. In the etch process fluorine radicals are generated in the plasma. The fluorine radicals attack the sacrificial layer on the wafer to remove unwanted areas that define the desired pattern on the wafer. At the same time the etch process may be designed so that liberated carbon will coat some wafer features creating a passivation layer that reduces the etch rate of features that are not desired to be etched. This is common in the case of defining very vertical structures. The carbon passivation layer is formed on the feature sidewalls as the etch progresses thus keeping the reactive species from continuing to erode the already etched features. Etch processes are very carefully designed to optimize the amount of radical etch compared to passivation so that well-controlled patterns are created. The choice of PFC is very often determined by the amount of available fluorine to carbon ratio in the etchant gas mixture to optimize the etch results to meet the criteria necessary for high-yielding functional IC devices. Emissions. The current amount of PFC gases emitted by the semiconductor industry is actually a very minute amount when compared to all PFC emission sources. The amount of PFC emissions attributed to the semiconductor industry is well under 10 percent and only approximately 0.1 percent of the United States total greenhouse gas emissions.1 The need to address SC manufacturing PFC emissions really did not stem from the amount already being emitted. One of the primary factors that drove the consideration was a review of SC industry growth rates as a whole. Through the late 1990s the semiconductor industry maintained a high growth rate and with it PFC emissions have tracked that growth. There was a concern that as the industry continued to grow the emissions levels of PFC gases would continue to swell with that growth. From this extrapolation began the idea that PFC emissions should be investigated for reduction in the SC industry.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.3

PFC ABATEMENT PFC ABATEMENT

27.1.4

27.3

Environmental Issues—Global Warming Potential The major disadvantage to the usage of PFCs is their influence in global warming potential (GWP). Though emissions are expected to increase over time, the amount of PFCs emitted into the atmosphere are almost minuscule when compared to other global warming gas emissions. In fact, carbon dioxide (CO2) by far makes up the largest global warming gas emission.2 So, why should we be concerned with the smallest volumetric greenhouse gas contribution? The trouble with PFCs are their extremely efficient infrared radiation (IR) absorption property and their extremely long atmospheric lifetime owed to chemical stability. PFCs have a unique property in the infrared spectrum for gases in the atmosphere. PFC gases have an absorption band in the 800 to 1200 cm−1 range where thermal energy would normally not be absorbed by atmospheric gases. By absorbing within this region PFC gases actually trap the heat energy that would normally leave the atmosphere into space.1 Essentially the greenhouse gases form an unintentional insulating layer above the earth trapping more warmth than would be considered normal. The entire greenhouse gas problem is further compounded for PFC gases because of properties so respected by the SC industry. The inertness of these chemical compounds makes them unlikely to decompose once emitted into the atmosphere. PFC gases are proven to have extremely long atmospheric lifetime values. Hence, a PFC gas in the atmosphere creating an insulating layer may last for hundreds or even thousands of years.2 Therefore, PFC gas emissions today are additive to those in the past and what will occur in the future. It’s this runaway potential that is garnering environmental concern. To understand the real significance of the global warming capacity of PFC gases, they are often compared in terms of carbon dioxide to indicate GWP. By definition CO2 is given a GWP of unity. Refer to Table 27.1 for a comparison of GWP and atmospheric lifetime for common PFC gases used in the SC industry. GWP is often provided in a 100-year integrated value. This value relates a given volume of a gas against the same volume of carbon dioxide. Thus, the GWP provides a multiplier for a PFC gas against carbon dioxide indicating how much more IR energy that gas will absorb within 100 years. To get the total global warming capacity of a given PFC gas the atmospheric lifetime must also be considered since most of the PFC gases have lifetime values much larger than 100 years. Refer to Table 27.1 for a comparison of lifetimes. By a quick review of these gases, the reader can easily surmise that PFC gases pose a significant greenhouse gas potential that will last forever, in terms of human time on earth. SC and EPA Endorse MOU. Recognizing the potential contribution that PFCs make to global warming, 160 nations agreed to the Kyoto Protocol in December 1997. This protocol was to become to PFC gases what the Montreal Protocol is to ozone depleting substances. Essentially, the Kyoto TABLE 27.1 Atmospheric Lifetime Values and Global Warming Potential for Selected PFC and HFC Gases3,4 Gas

Atmospheric lifetime (years)

GWP

Carbon Dioxide CHF3 CF4 C2F6 C3F8 C4F8 C5F8 NF3 SF6

50 – 200 264 50,000 10,000 2,600 3,200 1 740 3,200

1∗ 11,700 6,500 9,200 7,000 8,700 90 11,700 23,900

∗

By definition carbon dioxide is given a GWP of one.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.4

PFC ABATEMENT 27.4

GASES AND CHEMICALS

Protocol requires an average 5.2 percent reduction in emissions of six key greenhouse gases by the 38 participating industrialized countries. The six gases specified by the Kyoto Protocol are:5 Carbon dioxide (CO2) Nitrous oxide (N2O) Methane (CH4) Perfluorocarbons (PFCs) Sulfur hexafluoride (SF6) Hydrofluorocarbons (HFCs) The Kyoto Protocol directly impacts the SC industry because half of the targeted compounds are typical emissions from an SC fab, these being PFCs, HFCs, and SF6. In 1999 the World Semiconductor Council (WSC), with members from the United States, Europe, Japan, Taiwan, and South Korea met and agreed to reduce PFC emissions by at least 10 percent below 1995 levels (1997 for Korea) by 2010. Members of the WSC produce over 90 percent of the world’s semiconductors.6 In the United States, the Semiconductor Industry Association (SIA), partially in order to preempt any government enforced regulations, entered into a Memorandum of Understanding (MOU) with the United States Environmental Protection Agency (US-EPA) to reduce PFC emissions. On March 13, 2001 the SIA signed this new voluntary partnership with the US-EPA with the intention of reducing emissions of perfluorocompounds by 10 percent of 1995 emissions levels by the year 2010. The agreement sets reductions to occur for all perfluorocompounds, including perfluorocarbons, hydrofluorocarbons, and sulfur hexafluoride. These gases were specifically targeted for reduction due to their GWP and their extremely long atmospheric lifetimes derived from their chemically stable nature. The partnership agreement further complemented efforts by the WSC/SC trade organizations to reduce emission levels of PFC gases.7

27.2 PFC EMISSION REDUCTION STRATEGIES In an effort to meet the MOU goals agreed to by the major SC companies in the United States, investigations to Pareto PFC emissions began. This step simply determined which processes utilized PFCs and at what volumes in order to locate the largest emission processes within the SC industry. From there research got underway to review reduction options that would allow a given company to meet their emission goals relative to the 1995 baseline. Several different strategies for PFC reduction will be discussed in this section. Strategies being considered or in place, at least to some degree, by SC manufacturers include process optimization, chemical substitution, capture and recycle, and abatement. In many cases, companies will need more than a single strategy to meet their reduction goals. It may take a combination of strategies applied to a single emission process or multiple strategies that are process dependent. 27.2.1 Process Optimization The first PFC reduction strategy to consider is process optimization. This strategy simply targets a particular process to determine if emissions can be reduced with minimal or no adverse performance impact. Essentially, this strategy reviews emissions looking for ways to reduce the volume through either reduced PFC flow rates and/or reduced PFC gas flow times. Although this strategy will not eliminate PFC emissions, if successful, it will reduce the overall volume of PFC emissions from a given process or at least reduce the global warming impact. It is theoretically possible that process optimization could reduce emissions levels below the target threshold of today, but as the SC industry continues to grow even those optimized emissions would eventually exceed the allowable levels.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.5

PFC ABATEMENT PFC ABATEMENT

27.5

Process optimization had its greatest success on the CVD side due to less stringent requirements of the CVD cleaning process and prior lack of concern for the large quantities of PFC gases consumed. During initial investigations, SC companies found that CVD cleaning processes emitted large quantities of PFC gases (typically 60 to 70 percent of a fab’s overall PFC emissions) that are flowed into the chamber but do not react in the plasma cleaning process. These unreacted PFCs once removed from the chamber simply became an emission to the atmosphere. Through process investigation and optimization, engineers found that it was possible to reduce the amounts of PFC gases flowing into the chamber and/or reduce the total cleaning time while still achieving the desired chamber cleaning result. This provided a simple and often cost-effective method of reducing overall PFC emissions. Unfortunately, process optimization could not be as effective for etch processes. In etch processes PFC gases are used during actual production wafer processing, and thus play a critical role in the final chip performance and company profit. Any changes in gas flows, pressures, and the like have the potential to cause process shifts that can lead to low yield or even process-related scrap material. Since yield is of utmost importance in a SC fabrication facility, process engineers are extremely hesitant to consider such far-reaching process changes. Other PFC emissions reduction techniques are necessary for etch processes. 27.2.2 Chemical Substitution Chemical substitution is another seemingly simple strategy to reduce or eliminate PFC emissions from wafer fabs. This strategy proposes different gases that have either no adverse or lesser environmental impact. In theory the ideal alternative process gas would have an atmospheric lifetime and global warming potential of approaching zero while still being nontoxic and nonflammable. Obviously such an ideal gas must also possess properties that will allow it to be reactive with silicon compounds in a plasma environment while being cost-effective for the manufacturing process. To date, no ideal alternative gases are available. Although no ideal gas is currently available, the chemical substitution strategy is responsible for some major successes in the reduction of overall global warming potential through the exchange of larger GWP PFC gases with ones with much lower GWPs. Again, the greatest strides occurred in the CVD clean application for PFC reduction through the use of alternative chemistries. The most common CVD clean alternative chemistry is NF3. At first glance in Table 27.1 it would appear that NF3 is not at all a good candidate for an alternative chemistry aimed at reducing GWP emissions. Compared with the CVD cleaning gas reference standard of C2F6, nitrogen trifluoride does have a much shorter atmospheric lifetime. However, NF3 actually has a larger GWP than the C2F6 standard. The benefit comes in the mechanics of the CVD chamber clean and not in the alternative chemistry itself. One of the most successful NF3 chamber cleans is the remote chamber clean implemented by Applied Materials, Inc. The benefit for PFC gas emissions is that a remote chamber utilizing a microwave plasma source dissociates the cleaning gas into neutral and charged species. These species are injected into the CVD deposition chamber where the fluorine radicals react with siliconbased deposition residue (typically SiO2 or SiN4) to form volatile silicon tetrafluoride by-products that have no global warming potential. The SiF4 by-products are pumped out of the CVD chamber and are removed from the exhaust using conventional scrubbing technologies. Since the utilization efficiency of NF3 in these systems approaches 100 percent, there is zero or at least minimal global warming gas emission from this CVD chamber clean process. As a side benefit, the NF3 clean process is more gentle on internal CVD chamber materials than the standard C2F6 clean process.8,9 The NF3 chamber clean provides a major reduction in overall PFC emissions by essentially eliminating emissions from wafer fab processes that account for 60 to 70 percent of facilities’ PFC emissions. The only practical drawback to this new clean process is the fact that older wafer fabs would have to make significant capital outlays in order to purchase new equipment or equipment modifications to take advantage of the NF3 clean. Each wafer fab has to weight the return on investment (ROI) of such a project in order to determine if this is the most cost-effective solution to their PFC emissions.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.6

PFC ABATEMENT 27.6

GASES AND CHEMICALS

27.2.3 Capture and Reuse Capture and reuse is another strategy being considered to help wafer fabs reduce or eliminate their PFC emissions. This strategy is often called the environmental friendly option since it seeks to capture unreacted PFC gases from an exhaust stream. The unreacted gases would be purified and reused creating, in theory, a closed-loop process where no PFC gases are emitted and smaller volumes of new stock is necessary.10 There are several technical and economical issues that make the wide acceptance of the capture and reuse strategy unfavorable. The capture portion is relatively straight forward. The difficulty lies in handling the waste gas once it is collected. Several companies pursued methods to reclaim the PFC gas, C2F6 in most cases because of its large volumetric usage in CVD chamber cleans. Unfortunately, the required measures necessary to get reclaimed PFC waste gas purified for reuse are not trivial. In the end, the economics of the strategy are such that under current regulations it is cost prohibitive for a typical SC fab to consider this option. The purification step also provides a great technical challenge. If done on-site, it requires equipment to store and purify the gas(es). After purification most SC fabs would then require extensive testing to ensure that a high level of purity is obtained before they would allow a reclaimed batch of gas to reenter the manufacturing process. Outsourced reclamation also does not offer significant improvements in technical or commercial solutions due to the need to purify waste gas batches from multiple facilities that may have significantly different chemical component makeups. The added cost of transportation must also be considered. Essentially, under the current level of regulations a PFC gas such as C2F6 is much cheaper to purchase as new stock than to attempt to capture and reuse waste gas. However, only the future will tell if the economic balance shifts to make the capture and recovery technique more accepted. 27.2.4 Abatement Finally, abatement is a final option to the issue of PFC emissions. Abatement is a strategy that seeks to decompose the PFC molecules by breaking them down into by-products that are allowable as emissions or that can be further treated by common fab treatment facilities. Abatement schemes add energy to the waste gas exhaust containing PFC gases in the attempt to dissociate the molecules into non-PFC by-products. There are several different techniques utilized in abatement that differ mainly in the way energy is provided. Some abatement methods, called point of use (POU) abatement, simply add heat to burn the PFC gas components. These may use ignition gases such as methane or even hydrogen to provide the necessary heat energy. A second approach also utilizes heating but requires lower temperatures, achievable through electrical heating, in the presence of a catalyst. The catalyst aids in reducing the activation energy required to dissociate PFC molecules into easily treatable by-products. Finally, a third approach utilizes a plasma source to provide the necessary energy of dissociation. Although abatement is effective at reducing or even eliminating PFC emissions, the SC industry may approach abatement as a last option because it requires capital dollars that do not go directly into the production of profit or wafers. Processes of this nature that have an associated cost but provide no profit benefit are said to be nonvalue-added costs. This being said, abatement for some companies is a necessary step toward reducing their PFC emissions to their goal levels.

27.3 PFC ABATEMENT THEORY 27.3.1 Chemistry As discussed earlier, PFC gases are extremely stable substances. Much of this stability is owed to the carbon-fluorine bond that is one of the strongest single bonds encountered in organic chemistry and by far the strongest of the alkyl halide family. Bond dissociation energies for the carbon-fluorine bond indicate that significant energy must be imparted to the PFC molecule in order to abate the PFC gas molecules from the process waste stream. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.7

PFC ABATEMENT PFC ABATEMENT

Potential energy

CF4 + 2H2O

27.7

CO2 + 4HF ∆E

Reactants Products Reaction coordinate

FIGURE 27.1

Reaction energy diagram.11,12

Figure 27.1 illustrates how the reaction takes place for the dissociation of CF4 into carbon dioxide and hydrofluoric acid. This diagram is the typical kinetic pathway for reactants to products found in most general chemistry texts. The reactants begin at an elevated energy level relative to the products. There is, however, a significant energy hill (represented by the activation energy ∆E) to climb before the reaction is carried to completion. This energy hill necessitates the use of an energy source in order to abate PFC gases. 27.3.2 Abatement Methods Combustion. A combustion abatement system for PFC emissions reduction typically involves using a flammable gas injected into a reaction chamber with an ignition source. PFC gases for abatement flow into the reaction chamber and are essentially burned to facilitate PFC abatement. Water scrubbers are normally employed in a combustion system to remove the HF by-product from the exhaust gas where it can be easily treated as an aqueous solution. Combustion is not necessarily the perfect PFC emission reduction solution because CO2 is a by-product and also a global warming gas. The benefit comes in the fact that abatement with CO2 by-products trades high GWPs of PFC gases for much lower GWPs of CO2. Finally, combustion abatement is also not considered the ideal solution to PFC emissions reduction because combustion may produce NOx compounds that are considered hazardous air pollutants (HAP). When the combustion reaction takes place in the nitrogen rich gas stream many SC process tools use large amounts of nitrogen in their dry pumps. However, companies that specialize in building combustion abatement systems have optimized their reactor designs to generate the lowest NOx emissions possible. Overall, the combustion technique has been well accepted by the SC industry for PFC abatement due to the familiarity of these systems. SC facilities have long relied on combustion systems for abating emissions of other process wastes. Combustion abatement systems are normally capable of handling the PFC exhausts from several process tools and only limited by a maximum exhaust gas flow rate. The combustion technique is particularly suited for the high flow rates of PFC gases from a CVD process but has been viewed as overkill for the much smaller volumes generated by etch processes. Catalytic Decomposition. A new twist to the combustion technique is catalytic PFC abatement. Instead of simply adding raw energy to overcome the bond dissociate energies required to break down the PFC molecules, a catalytic system utilizes a catalyst that reduces the amount of energy required to drive the reaction from reactants (PFC) to products (normally CO2 and HF). A catalyst is a substance that initiates or accelerates a chemical reaction without itself changing chemically or physically (i.e., reacting). Companies that specialize in building catalytic abatement systems have developed proprietary catalysts that reduce the activation energy necessary for the PFC dissociation reaction thereby accelerating the reaction and helping to drive the reaction to completion so that PFC destruction rates (destruction removal efficiencies, or DRE) approach 100 percent. Figure 27.2 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.8

PFC ABATEMENT GASES AND CHEMICALS

CF4 + 2H2O Potential energy

27.8

CO2 + 4HF ∆E

Reactants

∆E catalyst Products Reaction coordinate

FIGURE 27.2 Reaction energy diagram with reduced activation energy requirement for a catalytic reaction.11,12

illustrates how the activation energy hill is reduced for the catalytic-aided reaction compared to the standard reaction pathway. Typical catalytic abatement systems for PFC destruction in SC facilities utilize electrical heating to accomplish the reaction since lower energy is required and in most cases SC facilities prefer to utilize electricity over flammable gases whenever possible. Catalytic abatement systems normally have a water scrubber similar to combustion systems to remove HF from the exhaust gas stream and make it an aqueous solution that is easily treated by the SC facility. Catalytic systems also have the downside of producing CO2 as a by-product; however, NOx emissions are negligible at the lower operating temperature of catalytic systems. Again, although CO2 is a global warming gas, it is considered more desirable for emissions when compared to the extremely efficient GWP PFC gases. Catalytic PFC abatement systems are also widely accepted for PFC abatement needs in SC manufacture. A typical catalytic PFC abatement system will treat exhausts from several chambers and/or several process tools and like combustion systems is only limited by a maximum flow rate of exhaust gas. Plasma Abatement. Plasma PFC abatement systems are considerably different compared to combustion or catalytic abatement techniques. A plasma abatement system utilizes energy from plasma source to dissociate the PFC molecules. These plasma systems are also different because they are installed in the process tool’s foreline between an etch chamber’s turbo molecular pump (TMP) and the roughing or dry pump whereas combustion and catalytic abatement tools are installed downstream from the roughing pumps. For this reason, a separate plasma abatement unit is necessary for each chamber on a process tool platform and there must be a separate facilities scrubbing system to remove any HAPs from the abated exhaust. Etch platforms may have anywhere from one up to four process chambers and each chamber would require a separate plasma abatement system. However, plasma abatement units are much less expensive than a single combustion or catalytic abatement systems and because combustion and catalytic systems depend on maximum exhaust flows, each application can be different as to which is the most cost-effective. Plasma abatement units are targeted only for etch process PFC abatement since CVD PFC flow rates are much too high to achieve acceptable PFC DRE values.13 As with combustion and catalytic abatement, plasma systems also emit CO2, a global warming gas, but with a much lower GWP than the PFC gases being abated. Plasma abatement systems like catalytic systems generate negligible NOx emissions. Plasma systems typically use a gas or water injection system to ensure that the PFC abatement by-products do not recombine back to PFC gases downstream in the exhaust. Essentially, the PFC gas molecules enter the plasma area and are dissociated but continue to flow toward the dry pump. At some point without a countermeasure there is a potential for recombination back to a PFC molecule. To overcome this effect, plasma abatement system makers incorporate a water or oxygen injection system just prior to the plasma area. This injection

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.9

PFC ABATEMENT PFC ABATEMENT

27.9

provides a source of hydrogen and oxygen (in the water case) or simply oxygen for the dissociated PFC by-products to combine with forming stable species such as HF, CO, and CO2 in the case of injected water and HF, CO2, COF2, and F2 in the case of injected oxygen. Due to the related hazards of COF2 and F2, the water injection method is preferred. Plasma abatement systems are also accepted in SC fabs for abatement of PFCs from etch tools because they are efficient and inexpensive. However, some SC fabs are hesitant to place any constrictive devices into the process tool foreline due to specter of unknown process drifts or backflows that always have the potential to occur.

27.4 CATALYTIC ABATEMENT 27.4.1 System Description The following sections will provide much greater detail about a catalytic abatement system for SC PFC abatement manufactured by Hitachi, Ltd., Japan (see Fig. 27.3). This family of abatement systems is the super catalytic decomposition system (SCDS) and can be installed in four sizes depending on the total flow treatment necessary. The smallest POU unit will handle 60 Lpm of the total flow while the largest will handle 3000 Lpm and is meant as an entire SC fab abatement system instead of a POU strategy. Other POU models available handle 120 and 200 Lpm. Pre-Treatment. In the Hitachi SCDS catalytic abatement system, the first stage is a water scrubber designed to remove any particulate matter that would potentially clog the catalyst bed and ensures the removal of any acidic and/or water soluble gases. The pretreatment consists of a packed tower where water cascades down while exhaust gases flow up the tower. The packing provides the necessary contact surface area of water and gas to create an efficient scrub. Since at this point the gas stream entering the system is the dirtiest that it will be, the water utilized in the pretreatment stage is recycled from other stages to reduce the total system water consumption. The remaining gases after leaving the prepacked tower go through a prespray section as a last water contact for further acid removal. The fresh facilities water in the prespray removes any acidic gases and flows down into the prepacked tower as the prespray is located overhead of the prepacked tower. The water leaving the prepacked tower is collected in a wastewater tank where at steady state a given amount continues to be recycled and some exits the system to the facility drain. After the pretreatment stage the gas stream should only contain nonwater soluble gases and the PFC gases of interest as they enter the reactor stage.

Fresh H2O Waste H2O

Ejector

Air

PFC gas Air Pre-spray

Post-packed tower Cyclone Heater Exhaust gas

From etcher

Pre-packed tower

Catalyst Water tank Cooling room

Pump

DI H2O Waste H2O

H2O

FIGURE 27.3

Hitachi SCDS catalytic abatement system diagram.11,12

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.10

PFC ABATEMENT 27.10

GASES AND CHEMICALS

Reactor. The reactor stage is where PFC decomposition occurs. In this stage the PFC gas stream enters through the top along with a small trickle of high purity (1 MΩ) water. The first stage of the reactor is a preheater where the water trickle is converted to steam and the PFC gas stream is heated prior to entering the heated catalyst bed. The reactor temperature is normally set at 750°C since experimental data shows that all common PFC gases used in SC manufacturing are decomposed to nearly 100 percent at that temperature.11,12 The next stage of the reactor is the catalyst bed. Here the gas stream enters the packed catalyst bed along with the steam generated in the prereactor. The Hitachi catalyst is a proprietary mixture designed to effectively decompose PFC gases. The addition of the steam ensures that the decomposed PFC molecules do not recombine after exiting the catalyst bed. Finally the Hitachi catalyst contains a specialized catalyst that ensures that carbon monoxide (CO) is converted to carbon dioxide (CO2) due to health considerations of carbon monoxide. The final section of the reactor stage is the cooling room. Here the hot decomposed gases exiting the reactor are contacted with recycled water in order to cool the gases back to a manageable temperature. The cooling room consists of multiple water spray curtains that the gases contact on their way to the next section. Posttreatment and Separation. The final stage of the Hitachi SCDS catalytic abatement system is the posttreatment and separation section. After the decomposed gases are cooled by water spray in the cooling room they enter another packed tower called the postpacked tower where the gases contact water for separation. In this stage the gases of concern are the PFC abatement by-products, HF, and CO2. The desire is to remove 100 percent of the HF from the gas stream so that it does not become a HAP emission in the facility exhaust system. Fresh facilities water in the postpacked tower provides the water contact to create an aqueous HF solution that is collected in the wastewater tank. The CO2 gas continues on into a cyclone apparatus that ensures complete drying of the gas before it leaves the system. All the gases are pulled through the system by an ejector, essentially a venturi pump that discharges the CO2 into the facilities exhaust along with all the other atmospheric makeup gases (e.g., N2, O2, and Ar). The aqueous HF solution is collected in the wastewater tank that is below the postpacked tower. This solution is recycled through the system into the prepacked tower for particle removal and into the cooling room. At steady state the SCDS pump siphons off an amount of the wastewater to keep the proper wastewater level in the tank. The siphoned wastewater goes to the facility HF treatment plant for subsequent treatment. Facilities Requirements. Table 27.2 indicates the facilities requirements for the Hitachi SCDS by model.

TABLE 27.2 Utilities Requirements for the Hitachi SCDS Catalytic Abatement System11,12

Abatement volume Water usage Particles Calcium (Ca) Temperature Process water Power Footprint Reactor temperature Cabinet exhaust Catalyst lifetime Warranty period

CD-60

CD-120

CD-200

60 L/min 0.4 gpm <50 µm <30 mg <25°C 10 cc/min >1 MΩ-cm 4 kW 5.8 ft2 300–800°C 106 cfm 12 months (…) 24 months

120 L/min 0.6 gpm <50 µm <30 mg <25°C 15 cc/min >1 MΩ-cm 8 kW 7.8 ft2 300–800°C 141 cfm 12 months (minimum) 24 months

200 L/min 0.9 gpm <50 µm <30 mg <25°C 20 cc/min >1 MΩ-cm 11 kW 7.8 ft2 300–800°C 177 cfm 12 months (minimum) 24 months

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.11

PFC ABATEMENT PFC ABATEMENT

PFC (CHF3, C4F8, C5F8) Dry pump

Etcher exhaust sampling point

27.11

SCDS SCDS exhaust sampling point

Etcher Exhaust

10 m cell

N2 purge 10 cm cell

MIDAC FT-IR

FIGURE 27.4 Experimental setup for PFC decomposition testing on the Hitachi SCDS catalytic abatement system.11,12

27.4.2 Performance Decomposition data for the Hitachi SCDS will be shown and discussed in the next sections. Experimental. Hitachi engineers ran multiple experiments to validate the capability of the SCDS in decomposing PFC gases generated in a real 300-mm oxide etch environment. Processes were examined with several different gas types and varying flow rates. PFC data were collected utilizing Fourier transform infrared (FTIR) methods. Gas compositions and concentrations were measured by the FTIR while there was no etching occurring (a no plasma condition), once plasma etching began, and after the SCDS decomposition of the PFC gases. Figure 27.4 illustrates the experimental setup used to collect PFC decomposition data that will be discussed in the next section. Application Data for PFCs. Figure 27.5 illustrates the capability of the first stage of abatement by the Hitachi SCDS. The FTIR was used to collect chemical species and concentrations just after the Pre-packed tower efficiency 800

C2F4

700 Concentration (ppm)

500

C2F6

Pre-packed tower emission plasma-on

Etcher exhaust plasma-off

600

C5F8 CF4

COF2

400

COF2

SIF4

CHF3

300

CO

200 100 0

COF2

SIF4 0

FIGURE 27.5

10

20

30 40 50 Arbitrary time

HF 60

70

80

90

SiF4

Prepacked tower removal efficiency.11,12

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.12

PFC ABATEMENT 27.12

GASES AND CHEMICALS

water scrubbing in the prepacked tower and prespray but before the gases enter the reaction stage. This data represent the scrubber’s efficiency at removing water soluble components from the exhaust stream before entry into the catalytic bed. The next four figures show the Hitachi SCDS capability to decompose PFC gases. Each figure has a table indicating the starting amounts of gases used in the oxide etch process. The left-most graph in each figure indicates the concentration by the species of gas without any plasma in the etch reactor. Essentially, this is measuring the gas input to the system as shown in the chart since no breakdown of the incoming PFC gases is occurring yet. This sample is taken after the etcher but prior to entry into the Hitachi SCDS catalytic reactor stage. The middle graph in each figure is quite similar to the left-most graph with the exception that the etch process has begun and thus there is a plasma condition within the etch chamber of the etch tool. In this case the injected PFC gases begin to breakdown into smaller component gases within the etcher plasma chamber. Notice that the larger PFC molecules (C5F8 and C4F8) are almost completely decomposed into smaller molecular weight PFC gases or other component gases. However, the injected CF4 gas is almost unchanged in concentration. This is exactly as expected since CF4 is the most stable PFC gas and the most difficult to abate effectively. In fact many abatement systems have less than perfect decomposition efficiencies for the CF4 molecule. Table 27.1 also provides some insight into the difficulty of CF4 abatement. The lifetime of these molecules is far greater than others shown in the table. Finally, the right-most graph (Figs. 27.6, 27.7, 27.8, and 27.9) indicates the concentration and species of gases detected after the exhaust stream passes through the Hitachi SCDS catalytic abatement system. As indicated, even with large loadings of large molecule PFC gases and of the difficult to abate CF4 gas, the Hitachi SCDS catalytic abatement system is capable of decomposing more than 99 percent of the PFC gases. The only remaining gas in the exhaust stream after treatment by the Hitachi SCDS is carbon dioxide.

27.4.3 Servicing Catalyst Lifetime. The catalyst lifetime is governed primarily by the required efficiency of a particular facility. Although the catalyst is not consumed by the decomposition reaction it will begin to degrade over time. In normal circumstances this degradation will be a slow process and decomposition efficiencies will degrade over the course of many months or even several years. For facilities under very tight regulation (e.g., greater than 97 percent DRE), the catalyst lifetime would be shorter than for facilities with more lenient regulations (e.g., greater than 90 percent DRE).

20 SCCM C5F8 oxide etch application 2500

C 2F 4

Etcher exhaust plasma-off

Concentration (ppm)

Etch process

Etcher exhaust plasma-on

2000 1500

C5F8

20 SCCM

CF4

160 SCCM 2 SCCM

CHF3

1000

O2

40 SCCM

Ar

1600 SCCM

N2

−48 L /min.

500 After SCDS treatment 0 0

20

40

60

80

100

120

140

160

180

C 2 F6 C 5F 8 CF4 CHF3 CO COF2 HF SiF4 Catalyst age: 200 8 months

Arbitrary time FIGURE 27.6

Abatement results for 20-sccm C5F8. 11,12

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

20:54

Page 27.13

PFC ABATEMENT PFC ABATEMENT 80 SCCM C5F8 oxide etch application 2500

Etcher exhaust plasma-off

Concentration (ppm)

C 2F 4

Etcher exhaust plasma-on

2000 1500

Etch process

C2F6

C5F8 80 SCCM

C 5F 8

CF4 160 SCCM

CF4

8 SCCM

CHF3

1000

O2

10 SCCM

Ar

400 SCCM

N2

−48 L/min.

CHF3 CO COF2 HF

500

SiF4

After SCDS treatment 0 0

20

40

60

80

100

120

140

160

180

Catalyst age: 8 months

Arbitrary time FIGURE 27.7

Abatement results for 80-sccm C5F8.11,12

20 SCCM C4F8 oxide etch application 2000 1600

Concentration (ppm)

C2F4

Etcher exhaust plasma-off

1800

Etch process

Etcher exhaust plasma-on

1400

C4F8

C 2 F6

20 SCCM

C4F8

CF4 100 SCCM

1200

CHF3

1000

O2

40 SCCM

800

Ar

400 SCCM

600

N2

−48 L/min.

CF4

8 SCCM

CHF3

400 200

After SCDS treatment

0 0

20

40

60

80

100

120

140

160

180

200

CO COF2 HF SiF4 Catalyst age: 8 months

Arbitrary time FIGURE 27.8

Abatement results for 20-sccm C4F8.11,12

80 SCCM C4F8 oxide etch application 2000

C 2F 4

1800

Etch process

Etcher exhaust plasma-off

1600

Concentration (ppm)

Geng(SMH)_CH27.qxd

1400

C2F6

C4F8 80 SCCM

Etcher exhaust plasma-on

CF4

1200

CHF3

1000

O2

C 4F 8

40 SCCM

CF4

8 SCCM

CHF3

10 SCCM

800

Ar 1600 SCCM

600

N2

−48 L/min.

400 200

After SCDS treatment

0 0

20

40

60

80

100

120

140

160

180

200

CO COF2 HF SiF4 Catalyst age: 8 months

Arbitrary time FIGURE 27.9

Abatement results for 80-sccm C4F8.11,12

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

27.13

Geng(SMH)_CH27.qxd

04/04/2005

20:54

Page 27.14

PFC ABATEMENT 27.14

GASES AND CHEMICALS

TABLE 27.3 Maintenance Requirements for the Hitachi SCDS Catalytic Abatement System11,12 Prepacked tower and prespray

Clean annually

Catalyst Cooling room Wastewater tank Packed tower

Replace 12–24 months Clean annually Clean annually Clean 2–3 years

In the field, the Hitachi catalyst has proven to exhibit greater than 99 percent DRE values even after 18 months of continuous usage making the cost-effectiveness of the Hitachi SCDS catalytic abatement system very favourable. Maintenance. Table 27.3 indicates when maintenance is necessary on different parts of the Hitachi SCDS catalytic abatement system. Ease of maintenance was designed into the SCDS from the beginning of the conceptual phase to ensure that in a busy fab environment, there was not any time lost to production due to lengthy or frequent PFC abatement tool maintenance. Additionally, the Hitachi SCDS catalytic abatement system has a three-way valve for the exhaust gas stream prior to entering the system. This valve can isolate the system for maintenance purposes so that no exhaust gases enter the system while maintenance is being performed. In this manner, even during the maintenance of the Hitachi SCDS, production can continue because the exhaust can be rerouted to a redundant SCDS tool planned into the overall facility PFC abatement strategy.

REFERENCES 1. Van Gompel, J., “PFCs in the Semiconductor Industry: A Primer,” Semicond. Int., July 2000. 2. “Greenhouse Gases and Global Warming Potential Values,” U.S. Environmental Protection Agency, April 2002. 3. “Inventory of U.S. Greenhouse Gas Emissions and Sinks: 1990–1998,” U.S. Environmental Protection Agency, April 2000. 4. “Emission of Greenhouse Gases in the United States 1999,” Energy Information Administration, 2001. 5. “Global Warming,” Trane Company, 2004. 6. Miotke, J., “U.S. Voluntary PFC Emission Reduction Partnership for Semiconductors,” U.S. Department of State, July 1999. 7. “EPA, Semiconductor Industry Agree to Cut Global Warming Gases,” Environmental Protection Update, Pennsylvania Department of Environmental Protection, March 2001. 8. Raoux, S., and J. G. Langan, “Remote NF3 Chamber Clean Virtually Eliminates PFC Emissions from CVD Chambers and Improves System Productivity,” Semicond. Fabtech, March 1999. 9. Schedlbauer, O. F., and H. F. Winzig, “Cost Reduction Challenges in CVD Chamber Cleaning: Strategies to Reduce Gas Costs,” Future Fab Int., July 2002. 10. “Abatement of Emissions of Global Warming Gases,” Praxair, Inc., Sept. 1997. 11. Cox, J., S. Koenigseder, and T. Decker, “Using a Catalytic Technique to Abate PFC Emissions in a 300-mm Etch Tool,” Micro Magazine, Los Angeles, March 2001. 12. Decker, T., J. Cox, and S. Koenigseder, “Perfluoronated Compound (PFC) Abatement for the SC Industry: Results from a Catalytic Method,” Future Fab Int., July 2001. 13. “PFCs and the Semiconductor Industry,” Advanced Energy Industries, Inc., Fort Collins, CO.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 28

CHEMICAL AND SLURRY HANDLING SYSTEMS Kristin Cavicchi Dan Barsness BOC Edwards Chanhassen, Minnesota

28.1 INTRODUCTION Process tools drive the semiconductor manufacturing process by managing a complex set of chemical reactions. A process tool’s lifeblood consists of raw materials that include bulk inert gases, toxic and reactive gases, ultrapure water, process chemicals, and chemical mechanical polishing (CMP) slurries. The systems that generate, handle, purify, and/or measure each of these five classes of materials are typically designed and operated by a fab’s facility management team and are referred to as critical process systems. Each critical process system comprises standard products from specialized vendors that are engineered and assembled into site-specific systems to meet the unique needs of the customer’s physical facility and process requirements. Selecting and managing a critical process system thus requires an understanding of the relevant issues and choices that are common from fab to fab, and an understanding of the facility or process-specific issues and options. Automated chemical and slurry handling systems, in particular, represent a specific field of expertise with tremendous implications to the safety, purity, and uptime of a fab’s manufacturing processes. Chemical and slurry systems impact many process areas in a fab including CMP, lithography, etch, and clean. Wet process chemicals are typically divided into five classes: • Acids: Usually used for cleaning or etching • Bases: Also used for cleaning; include developers used as part of the lithography process • Oxidizers: Used to create or augment reactions with other chemicals or on the wafer surface, such as facilitating photoresist removal or metal polishing processes • Solvents: Used to aid drying or as strippers for other materials such as residue from back-end plasma etch processes • Slurries: Suspended solids in a chemically active or buffered solution used in polishing processes to remove and/or planarize deposited materials 28.1.1 History of Chemical and Slurry Handling While liquid chemicals have been part of the semiconductor manufacturing process from the beginning, automated chemical handling developed during the late 1980s and early 1990s to lower costs and improve the following: Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

28.1

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.2

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.2

GASES AND CHEMICALS

• • • •

Safety Purity Repeatability Cost

Safety. Initial mass-production wet processes relied on pouring chemicals by hand into baths in which wafers were immersed to perform a specific process step. This approach required significant manual handling effort and inherently exposed technicians and operators more directly to the aggressive and potentially dangerous chemicals. In addition to the exposure risk, the manual process was error prone, creating the potential for adding chemicals in the wrong order or in inadvertent combinations. Increased consumption of chemicals also created strains on the manual pour process. Thus, technicians sought automation methods to manage increasing volumes and to reduce operator exposure and human-error risks. Purity. As geometries decreased, it became apparent that particle contamination, in particular, was a problem with direct-pour, manual processes. The nominal rule for particle control is to ensure that the wafer is not exposed to particles larger than half of the device half-pitch. Particles that can span across two elements of the circuit can obviously result in shorts or other forms of damage. No matter how clean the source container, static materials are never as pure as materials that have recently been properly filtered. In addition to improved safety, automation may improve particle purity, but at the same time introduces the increased risk of ionic contamination, a subject that to this day is still fundamental to the design of chemical management components, equipment, and systems. Repeatability. As in all manufacturing processes, reproducible semiconductor manufacturing relies on the control and repeatability of key parameters. Controlling the process conditions permits the process engineer to focus on the inherent capabilities of each manufacturing step. Two such variables— purity and blend ratio repeatability—are more repeatable when delivered through automated means. Cost. The transition from manually handled small chemical packages to automated bulk systems provides direct cost benefits by reducing material and labor costs and by realizing the cost-of-ownership benefits in purchasing chemicals in bulk containers. Removing the 1-gal bottle also reduces disposal and labor costs. Indirect cost benefits are derived from the increased safety and reproducibility benefits of automated chemical delivery. These cost benefits are offset by the need to acquire and install delivery systems. Simply put, automated chemical and slurry systems enable improved process results while saving cost and improving safety. All designs, capabilities, and attributes of chemical and slurry handling systems flow from this value proposition.

28.2 ELEMENTS OF CHEMICAL AND SLURRY HANDLING SYSTEMS AND IMPORTANT TERMS In this chapter, the following terminology is used. Point of use (POU): A process tool or a portion of a process tool to which a chemical or slurry is supplied Chemical (or slurry) system: Typically a term applied to the integrated package of all components, piping, wiring, controllers, and equipment dedicated to the delivery of one or more chemical streams Equipment: Typically one physical cabinet with a specific task such as blending, pumping, filtering, or a combination of tasks

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.3

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.3

Equipment controller: An electrical subsystem that manages the operational and safety-related tasks of a given piece of equipment Distribution system: The network of tubing, valves, valve boxes, controllers, and wiring, typically located in the subfab, related to a chemical or slurry system Distribution controller: An electrical computation device that manages the operational and safety-related tasks required to transport chemicals from the equipment to the points of use Engine: That portion of the distribution system, often a part of the equipment, that moves the fluid, for example, diaphragm, bellows, or centrifugal pump, or pressure vessel Day tank: A permanent on-site storage vessel that provides a buffer volume of a chemical or slurry At a basic level, a chemical or slurry system consists of the following elements: • • • • • •

A source container A method to move the chemical (pump or pressure vessel) A day tank A filtration system A piping network, including valve boxes, to provide flow to multiple points of use A control system In a 300 mm fab, there are typically:

• • • •

20 to 35 high-purity chemicals, 2 to 10 of which require blending or dilution 3 to 12 CMP slurries, most of which require blending or dilution 50 to 150 valve boxes 200 to 300 points of use

28.3 EQUIPMENT 28.3.1

High-purity Chemical Systems As opposed to CMP slurries, which contain abrasive particles suspended in a carrier fluid, high-purity chemicals are manufactured to minimize all forms of impurities (typically, particles and metal ions). Particle concentrations are measured by quantity at various sizes in a fixed volume of chemical. A typical specification calls for fewer than 10 0.1 µm particles per milliliter of chemical. Filtration is a means for controlling particle concentration, and most systems reduce the particle level found in the source container; that is, a properly designed delivery system does not add particles to the chemical. Ionic contamination is measured in parts per million or parts per billion by sophisticated instruments. Unwanted ions on the wafer can change the electrical properties of the device and result in a loss of die yield. Unlike ions in gas streams, ions in liquid chemical streams cannot typically be removed online by ion-exchange methods, with a few exceptions. This fact shifts the ion control strategy from removal to prevention. Every component, tube, pump, and tank must be made to prevent ionic contamination from the start. Although Teflon materials such as PFA and PTFE are inherently pure, they do not provide the robust mechanical properties of steel or aluminum, and thus create a design challenge between the purity and physical characteristics of the machine, such as uptime, cycle rating, and capacity. The design challenge for a high-purity chemical system is to remove particles that exist in the source containers, while not creating sources of particle contribution, and to prevent the contribution of ionic contamination using clean but mechanically weak materials to design a machine with nearly 100 percent uptime and little or no required maintenance.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.4

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.4

GASES AND CHEMICALS

28.3.2 High-purity System Conceptual Overview High-purity chemical dispense systems feature a wide variety of designs. Customers and vendors make a unique series of value judgments and corresponding design choices that optimize various attributes of the chemical system. In addition to purity, other major design drivers are uptime and cost. High uptime and low cost are competing goals that drive the high number of equipment variations from one device manufacturer to another. A typical design, referred to as a chemical distribution module (CDM) or chemical dispense unit (CDU), is shown in Fig. 28.1. While the number of designs is large, each high-purity chemical system may be condensed to two simple functions: • Function one: Transfers the chemical from the transportation container (drum or tote) to the storage day tank while providing filtration. • Function two: Transfers the chemical from the day tank to the distribution system while providing filtration. 28.3.3 Engine Types The system in Fig. 28.1 shows two pumps. While pumps are a common method to move chemicals, a variety of other “engines” are commonly used in semiconductor manufacturing, as shown in Table 28.1. The word “engine” is a general term used to refer to the mechanism that causes the motive power of a CDM. 28.3.4 CDM Engine Design Implementation and Redundancy The primary mechanical CDM design challenge is to manage the trade-offs of cost and uptime. Uptime is related to component reliability, and component unreliability is “managed” by redundancy. Subsystem redundancy is also used to reduce unscheduled and scheduled downtime. If the goal is to reduce the unscheduled downtime, then redundancy must permit the unit to operate in the event of a failure long enough to permit replacement of the failed component when downtime repair can be scheduled. If downtime cannot be scheduled, the redundant design must permit the replacement of the failed components while the system is operational. The difference relies on the quantities of various components and the use of valving for isolation. Note the design differences shown in Fig. 28.2. With the proper policies, training, personal protective equipment, and isolation, Design B (with isolation valves) could permit the replacement of one pump while the other pump is operational. The design without isolation valves, or dual isolation valves, requires downtime for maintenance. Referring to the transfer and dispense functions of a CDM and adding filtration to maintenance and uptime redundancy considerations, one can see that the desire for uptime to prevent scheduled or unscheduled downtime can quickly escalate the cost of a system. To prevent the need for four pumps

Daytank Drum

Pump

Filter

Transfer FIGURE 28.1

Pump

Filter

Dispense

A high-purity chemical dispense system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.5

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.5

TABLE 28.1 Characteristics on Chemical Delivery Engine Engine type 1. Positive displacement pump with pulsation dampener

Benefits

Weaknesses

Bellows or diaphragm pumps are reliable and provided by many vendors

Moving parts under high pressure require maintenance, typically in the form of rebuilds

Best for chemicals where a gas-tochemical interface is not desired

Pulsation dampeners reduce pulsations, but add cost and maintenance requirements

Developers that contain surfactants are well suited for pump-based engines. Nitrogen can dissolve in the developer and outgas in the track, and surfactants are more likely to foam in “nonpump-based” systems

2. Pumps are driven by compressed air

Common applications

3. Pump-pressure A system of one or more pumps and at least two pressure vessels. A pump is used to fill one pressure vessel while another is pressurized with nitrogen and dispenses chemical to the fab Pressure vessels can range from ten to thousands of liters

Steady dispense rate/pressure Less pump maintenance Higher purity Larger vessels provide higher instantaneous flow levels and the potential for higher uptime in the event one vessel fails

Cost of pumps and pressure vessels Requires more space

Appropriate for most chemicals Fabs with higher flow requirements tend to use larger pressure vessels, but to obtain higher flows, the dispense system piping must not experience significant pressure drops. If pressure drops are high, larger pressure vessels will not provide a benefit

4. Vacuum pressure A system of two vessels filled by applying a vacuum and emptied by applying nitrogen pressure

Lowest-cost system

Protected by patents, and hence not widely available Can reduce the assay of volatile chemicals such as NH4OH Sustained outlet flow limited to rate at which vessels can be filled

Appropriate for chemicals without assay loss concerns, surfactants or exceptionally high demand

and two filter banks in each system, one method, known as optimized redundancy, creates two engine banks consisting of a pumping method and a filter bank as shown in Fig. 28.3. Valving connects two flow paths for each pump. One path is from the supply drum to the day tank (the transfer function). The other path is from the day tank to the fab (the dispense function). This permits each engine to perform the transfer and dispense tasks. This design assumes that with a properly sized day tank, the system can operate on one engine for a prolonged period of time, permitting maintenance to the other. Table 28.2 summarizes the range of redundancy solutions used in the industry today. Choosing the optimal redundancy model is a highly subjective decision based on the particular uptime requirements of each fab. The desire to avoid even the slightest risk of chemical unavailability typically pushes most fabs to level four, five, or six, but increased capability can increase cost. 28.3.5 Peripheral Equipment for High-purity Systems In addition to the CDM, the typical chemical dispense system also consists of the following peripheral equipment and subsystems: Drum Cabinets. A drum cabinet is an enclosure that provides secondary containment for the drum. Secondary containment is required if the chemical from the drum is circulated under pressure. The drum cabinet can also provide containment in the event of spill.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.6

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.6

GASES AND CHEMICALS

Daytank Drum

Pump

Design A: Simple redundant transfer pumps without isolation values

Daytank Drum

Pump

Design B: Redundant transfer pumps with dual isolation valves FIGURE 28.2

FIGURE 28.3

Redundant transfer pump designs.

A chemical delivery system flow path that offers optimized redundancy.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.7

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.7

TABLE 28.2 Summary of Redundancy Solutions Protection

Cost factor

Level zero

One pump

Design None

0.80X

Level one

Two engines, one flow path, no isolation

One engine fails (leak, no flow)—can’t transfer while dispensing to the fab

1.0X

Level two

Two engines, one flow path, isolation

Same as one plus safe maintenance

1.10X

Level three

Two engines, two flow paths, no isolation

Same as one, but permits transfer while dispensing to the fab (if both online)

1.15X

Level four

Optimized redundancy—two engines, two flow paths, isolation

Same as three plus online maintenance

1.15X

Level five

Two transfer and dispense pump engine sets, two pumps each

Can have two pumps for transfer, two for dispense to the fab

1.80X

Level six

Two units, same capabilities

Two complete units, equipped with all capabilities

2.10X

Lorry Systems. Lorries (trucks) fitted with special chemical tanks serve as a source of supply for high-consumption chemicals. More popular in Asia and Europe than in the United States, lorry systems require a coupling system, storage tank, and transfer station. The coupling system is a CDMlike unit that houses specialized fittings that connect with a mated fitting on the truck. The coupling system cleans the fitting, permits sampling, and then pressurizes the lorry tank to transfer the chemical to the on-site storage tank. Sample Stations. A sample station is a system that permits the safe and controlled collection of chemicals from one or more distribution systems. If multiple chemical streams are plumbed to one sample station, the sample station permits flushing of the chemical supply line with chemical and water and also provides nitrogen purge. Door interlocks provide safety for the operator. Valve Boxes. Valve boxes are enclosed manifolds that permit supply from the main distribution line to individual points of use. Blending Equipment. Blenders are specialized systems that dilute concentrated chemical or blend various components to meet highly controlled specifications. Particle Counters. Particle counters are in-line devices that rely on laser-based optical particle counting technology for various particle diameters. Particle counters are used to qualify the system on initial commissioning and may also be used during the normal system operation to warn of specification excursions.

28.4 HIGH-PURITY CHEMICAL BLENDING Many chemicals used in the semiconductor industry are “ready to use,” that is, the concentration of the chemical in the drum is suitable for wafer processing. Other chemicals must be diluted with deionized (DI) water or blended with additional chemicals to achieve the desired process result.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.8

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.8

GASES AND CHEMICALS

28.4.1 Reasons for Blending A device manufacturer may choose to blend chemicals on-site rather than purchase preblended drums. By far, the most common reason to do this is to reduce the cost of ownership of a process or chemical stream. Most chemical blends are, in fact, dilutions of a concentrated chemical with ultrapure water. Depending on the final blend concentration, the final blend may be primarily water (DIW) with a very small amount of chemical. Since all fabs have large quantities of highly pure DI water available, many choose to dilute various chemicals on-site rather than ship drums of water. Table 28.3 provides a summary of the most common on-site high-purity blending applications in the semiconductor industry. The prerequisites for on-site blending include the availability of concentrated chemicals and suitable blending equipment, and the agreement of the fab process owners that the risks of blending on-site (versus premixed material from a chemical vendor) are acceptable for the process. There are other reasons to pursue on-site blending. Depending on the process type or the stage of process development, the ability to alter the chemical concentration may be required. With on-site blending equipment, process owners can vary the blend recipe to achieve different target concentrations. This ability may be useful during the initial stages of process development, or if an individual process could benefit from a changing concentration, such as reducing the concentration as a process approaches the end point. The ability to change the blend concentration during the process requires POU blending equipment, but processes that require a constant, stable concentration generally make use of bulk blending equipment located in the subfab. In situations where a particular chemical blend is not commercially available, it may be more cost-effective for a device manufacturer to blend the chemical on-site rather than contract with a chemical manufacturer to make relatively small volumes of custom chemistry. Finally, some chemical blends required for a specific process step are not stable for a long enough period to permit shipping, and other process steps require the immediate effect of active chemical reactions. Thus, chemicals with a short “pot life” require on-site, and often on-tool, blending solutions. Oxidizers used in various CMP and cleaning applications often have short pot lives.

TABLE 28.3 Common On-site Blending Applications Chemical

Typical target concentration

Application

Comments

Hydrofluoric acid (HF)

Typically 10:1, 100:1 or 500:1 dilution of 49 percent HF

Front-end etch processes

HF is by far the most common chemical blended on-site

Tetramethyl ammonium hydroxide (TMAH)

2.38 percent (can be written as 0.263 N)

Developer chemistry

Extremely tight blend specifications are required for on-site developer blending

Ammonium hydroxide (NH4OH)

2 percent

Post-CMP cleaning chemistry

Potassium hydroxide (KOH)

Variable (generally <5 percent)

Post-CMP cleaning chemistry

Citric acid chemistries

Variable (generally <5 percent)

Post-CMP cleaning chemistry

Citric acid blends tend to be multiconstituent blends rather than just DI water dilutions

TMAH + acid

Variable (<2 percent TMAH)

Post-CMP cleaning chemistry

TMAH blends usually have a pH >10 at the target concentration, and contain a very small amount of acid

Benzotriazoale (BTA)

0.03 percent

Anticorrosion agent for the copper process

Raw BTA may be in solid powder form or diluted in DI water or alcohol.

Surfactant dilutions

Variable (generally in the ppm range)

Post-CMP cleaning chemistry

Surfactant dilutions typically have a very high dilution ratio (>100:1)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.9

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.9

TABLE 28.4 Typical Accuracy and Repeatability Requirements for Common On-site Blending Applications Chemical/application

HF blending

TMAH developer blending

Post-CMP cleaning applications

Accuracy / repeatability requirements

1 percent RE∗

0.1 percent RE

3–5 percent RE

*RE = Relative error

28.4.2 Critical Blending Parameters When considering an on-site blending process, in addition to its capacity, the two most critical parameters are the accuracy and repeatability of the process. Accuracy reflects how close the blend system’s output is to the target concentration. Repeatability measures the blend system’s ability to produce a blend of the same concentration over and over again. In most blending systems, the same concentration is used for a long period of time; thus, as a practical matter, most of the attention to the design of such blend systems is to ensure repeatability. If the accuracy is slightly off, the system can be adjusted during setup or calibration. Hence, day to day, repeatability is the more significant system parameter. Table 28.4 lists the typical repeatability requirements for various high-purity blending applications. The accuracy and repeatability in Table 28.4 are listed in terms of relative rather than absolute error. Absolute error has some unit of measurement, usually weight percent or normality (e.g., 0.49 wt percent HF ± 0.005 wt percent, 0.263N TMAH ± 0.001N or 40 ± 2 ppb). Relative error is the absolute error as a percentage of the target value. It has no unit value. The equation for repetability relative error is shown next: Relative error =

absolute error ×100 target concentration

The blend capacity must be considered differently depending on whether the blend equipment uses a batch process or an online process. A batch process is one in which a discrete batch of some volume of blended chemical is produced. A batch process has a clear beginning and ending point. At the end, the batch is typically transferred to an external day tank where it is held until it is needed by the fab. A common batch blend system configuration is shown in Fig. 28.4. With a batch process, the daily capacity of the blend system should exceed the anticipated daily consumption of the fab. The external day tank should be sized to provide a sufficient buffer volume for the fab in the event of maintenance on, or failure of, the blend system for some period of time. Optional metrology

DIW chemical

Blend technology Daytank

Mix tank

Pump

Pump

Blend FIGURE 28.4

Transfer

Filter

Dispense

Batch blend process schematic.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.10

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.10

GASES AND CHEMICALS

Online blend processes blend chemical on demand and deliver it directly to the wafer or to the distribution system. Online processes may or may not have large day tanks to provide a buffer volume of chemical. Two examples of online blend system configurations are shown in Fig. 28.5. If no buffer volume is available, the capacity of an online process must be designed to support the peak consumption of the fab at any given moment, rather than the daily consumption of the fab. If there are five process tools and each demands 5 L/min of chemical for 120 min every day, the daily consumption is 3000 L (or an average of 2 L/min). A batch system would need to be sized to provide at least 3000 to 4000 L of chemical per day. If the blend system is online and there is a possibility that all tools will demand at the same time, the online system would need to be sized to provide 25 L/min of chemical. In addition to the higher capacity requirements, redundancy is more critical for online systems where a large buffer volume may not be available. After the accuracy/repeatability and capacity issues have been addressed, other factors must be taken into account when considering an on-site blending process: • Blend redundancy: Does the blend system offer any type of redundancy? At one end of the spectrum, redundancy could mean two pumps rather than one pump. At the other end of the spectrum, redundancy could include two complete blending flow paths including tanks, pumps, and metrology devices. • Type of metrology: The relationships among the chemicals that will be blended and the accuracy/ repeatability requirements of the process impact the type of metrology (if any) that is required. The system vendor must perform exhaustive qualification tests, and device manufacturers must be comfortable with the type of metrology proposed. Typical metrology selections range from conductivity or pH probes to titrators, spectrometers, and sonic velocity measurements. • Cost of ownership: On the surface, on-site blending appears to offer significant cost-saving opportunities compared to the purchase of preblended drums of chemicals. However, the additional costs that must be taken into consideration are the utility costs to run the blending equipment (DI water, CDA, nitrogen, electricity, exhaust), the maintenance costs associated with adding another piece of equipment to the fab, and the maintenance costs specific to a unique piece of equipment (e.g., different spares, additional training, frequent laboratory testing of the blended chemical assay). In most cases, these costs are not prohibitive, but it demands an informed decision to justify them. • Integration with the dispense system: The blend system must be integrated with the fab control and distribution system. The integration challenges vary depending on whether the blend system will also serve as a delivery system to transfer blended chemical to the POUs, or whether it will be integrated with a separate delivery system.

DIW chemical

DIW chemical

Blend technology

Blend technology

Wafer

Daytank

Pump

Blend and consume

Blend FIGURE 28.5

Filter

Dispense

Online blend process schematics.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.11

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.11

• System purity: Minimizing ionic contamination is always critical in a blend system design because there is no practical way to remove ionic contaminants from most chemicals once they have entered the fluid stream. The criticality of particle control in the blend system depends on the dispense system integration. If the blend system will also deliver chemical to the fab, every effort must be made to use advanced particle removal technologies. If, however, the blend system will just transfer blended chemical to an independent delivery system, particle control is less critical because the delivery system will be equipped with the appropriate particle removal technologies.

28.4.3 Blending Challenges When considering an on-site blending system, a series of challenges are faced by both the equipment supplier and the device manufacturer. The issues facing the device manufacturer depend on whether a new fab is being built or a new blend system is being added to an operational fab. Equipment Supplier. The equipment supplier’s three main issues are to choose or develop a blend methodology and a metrology integration plan and to determine cost. Technologies used to blend chemicals include volumetric, flow-based, and weight-based blending and pump-stroke measurements. Each of these methodologies has advantages and disadvantages, as indicated in Table 28.5. Equipment suppliers must be capable of balancing the strengths and weaknesses of each technique against the requirements of the processes. Some equipment suppliers choose to focus on one technology and adapt it to the process requirements. Others use different techniques depending on the applications. Metrology is a second challenge to equipment manufacturers. Some processes require metrology devices to validate the concentration of the blended chemical and/or to provide a feedback blending capability to a system. Feedback blending utilizes the concentration data from a metrology device for a given blend to dose a batch to achieve the target concentration. The challenge for equipment manufacturers is to find metrology devices capable of measuring accurately to meet today’s blending specifications. Blend specifications are approaching or exceeding the capabilities of many commonly used metrology devices, which means the variability in the concentration reported by the device is too large

TABLE 28.5

Strengths and Weaknesses of Various Blend Methods

Blend method

Strengths

Weaknesses

Volumetric Precise volumes measured in one or more vessels

Simple to understand and operate Robust design (few failure modes)

Limited accuracy and repeatability Limited blend ratio range Difficult to change blend recipes

Flow Flow measuring devices totalize flow or precisely control flow to control volumes of constituents

Simple to understand Can provide a high blend capacity Can be used as an online blend technology

Pressurized chemical source required Flow meters can be prone to drift and require frequent calibration

Simple to understand Recipe changes are quick and easy Scalable for small or large capacity requirements

Load cells can be prone to drift Weight-based blending is always a batch process

Can provide a high blend capacity Can be used as an online blend technology

Pump stroke volume can drift so pumps require frequent calibration Pump required for every constituent (can be costly)

Weight Precise load cells measure weights of constituents in a batch process

Pump stroke Pump strokes counted and volume calculated based on volume per stroke

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.12

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.12

GASES AND CHEMICALS

to control the process within the specification. Another challenge is to select devices that are easily and effectively integrated into the blend system. This includes using real-time measurements whenever possible, reducing the maintenance required for the metrology device, and selecting devices that are not susceptible to ambient changes. Finally, equipment suppliers must always balance the capabilities of the system against the system cost. Although it is possible to develop highly featured blend systems that offer self-calibration, complete redundancy, and other upgrades, the challenge is to offer the features and capabilities required by the market (device manufacturers) without adding so many additional components that the unit cost becomes prohibitive. New Fabs. When a new fab will include on-site blending systems, device manufacturer facility engineers must first decide if the blend methodology will be a batch or online process. A batch process offers the ability to integrate metrology to validate concentration, but an online process can offer higher capacity and, possibly, the ability to vary the concentration based on the needs of the process. Secondly, they must select an equipment supplier. Different equipment suppliers will most likely offer different blend techniques (flow versus weight versus volumetric). Different types of metrology and/or process controls will also probably be proposed. The device manufacturer must be comfortable with the blend technique, the facility’s ability to support and maintain the equipment in the long term, and the ability of the equipment and metrology to measure and control the specified concentration. Existing Fabs. If blending equipment is being considered for an existing fab, it will likely replace an existing supply of prediluted chemicals in drums. An element of risk is introduced when blending chemicals becomes the responsibility of the fab rather than the chemical supplier. The first challenge is to balance the cost savings against the additional risk, and determine how the risk can be managed (via metrology validation, backup suppliers, or other means). If the process owners agree to on-site blending, all the decisions that face a new fab will apply to the existing fab. The fab must decide on batch versus online blending, and select equipment that is capable of supporting the process requirements. Perhaps the biggest challenge is integrating blend equipment into an operating fab. The new equipment must be integrated into an existing distribution system or with an existing chemical delivery system, which will likely require some downtime. So, the integration process must be planned and managed to minimize interruption to the fab. Finally, most fabs will require that the new chemical supply be qualified. Multiple approaches to requalification include split lots, layer-by-layer qualification, a single process tool dedicated to the new chemical source, and other methods. The time and costs involved in process requalification must be taken into consideration during return-on-investment (ROI) discussions. An experienced vendor can help guide the process for minimal impact.

28.5 SYSTEM PURITY 28.5.1 Why Purity Matters Purity matters because the levels of particles and ionic contamination in chemicals will have a direct effect on the process yields in the fab. Once ionic contamination is in the fluid stream, it cannot easily be removed. The only viable technique is preventing ionic contamination from entering the fluid stream. Process tools may or may not have filtration at the POU, so it is critical that chemical dispense systems use the most effective particle removal technologies available. 28.5.2 What Is System Purity? System purity refers to the levels of contaminants added to the fluid stream by the chemical delivery system. Contamination generally refers to ionic elements and particles.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.13

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.13

• Ionic contamination refers to the inorganic contaminants that may be added to the fluid • Particle contamination refers to the particle levels that remain in the fluid after it has passed through a filter 28.5.3 Ionic Contamination Not every element in the periodic table is of concern when measuring for ionic contamination. Only those likely to be present after the chemical manufacturing process or those that may be contributed by fab contamination events are of interest. Table 28.6 lists the 34 ions that are generally measured, their classification, and the likely sources of the ions. Understanding contamination sources is critical to being able to troubleshoot contamination problems. Due to the relatively high integrity of a modern chemical system, a failure event usually has one root cause. Generally, ionic contamination levels are tested by subjecting a chemical sample to inductively coupled plasma-mass spectroscopy (ICP-MS). In ICP-MS, a plasma source converts the atomic contamination in the sample to ion form. A quadrupole filters the ions based on mass-to-charge ratio, and then a detector, coupled with software, identifies the type and concentration of the elements present in the sample. Several factors can impact the ability to measure the ionic contamination levels in chemicals. The first, potential peak interferences for specific elements in different chemicals, has been largely eliminated through the use of advanced ICP-MS equipment. The second factor is that the incoming contamination levels in the chemical impact the measurement variability. If there are 100 ppb of TABLE 28.6

Ion Contaminants Monitored by the Semiconductor Industry Ions

Process concerns

Likely contamination sources

Gold (Ag), lithium (Li), potassium (K), sodium (Na)

Mobile ions

Ag: Rarely occurs Li: Catalyst in PFA manufacturing process K, Na: Environmental contamination (esp. people)

Nickel (Ni), copper (Cu), cobalt (Co)

Form silicides

Ni: Component of stainless steel Cu: Process cross-contamination Co: Cobalt electroless process; used as a dye

Aluminum (Al), barium (Ba), cadmium (Cd), calcium (Ca), chromium (Cr), iron (Fe), lead (Pb), maganese (Mn), magnesium (Mg), molybdenum (Mo), tin (Sn), titanium (Ti), vanadium (V), zinc (Zn)

Gate oxide killers

Al: Can be present in ammonium hydroxide Ba: Can occur in polymer materials exposed to chemical Cd: Occurs in alloys Ca, Mg: Environmental contamination (esp. people) Cr: Leaches out of stainless steel components Fe: Leaches out of stainless steel and polymers Pb: Can be leached from gaskets; PVC stabilizer Mn: Potassium permanganate added in distillation process Mo: Occurs in alloys Sn: Hydrogen peroxide stabilizer; common additive Ti: Occurs in fillers and alloys; polymer catalyst V: May be polymer catalyst (rarely occurs) Zn: Leaches out of polymers (drums, welds, and the like)

Antimony (Sb), arsenic (As), boron (B)

Dopants

Sb: Raw material for phosphoric acid manufacturing As: HF manufacturing B: DI water

Beryllium (Be), bismuth (Bi), gallium (Ga), germanium (Ge), niobium (Nb), silver (Ag), strontium (Sr), tantalum (Ta), thallium (Tl), zirconium (Zr)

Other trace metals

Rarely occur

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.14

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.14

GASES AND CHEMICALS

iron in the chemical before it is introduced into a chemical delivery system, it is unlikely that ICPMS would be able to accurately resolve ionic addition in the order of 10 ppt. It is likely that 10 ppt variations would be within the measurement noise. Finally, it is important to make a distinction between low-level detection limits and method detection or quantification limits. Low-level detection limits refer to the ability of an ICP-MS to resolve a specific ion in a specific chemical under ideal laboratory conditions. Method detection limits or quantification limits are more likely to take sampling and other possible error sources into account. Ionic contamination specifications should be based on quantification limits rather than low-level detection limits. Typical ionic contamination specifications for high-purity semiconductor chemicals are in the order of 0.1 to 1 ppb added by the chemical distribution system per element measured. 28.5.4 Particle Contamination Particle levels are tested by providing a slipstream of chemical to an optical liquid particle counter after the chemical has passed through a filter. Most particle counters work by shining an illumination source of some wavelength through the fluid stream. The light is scattered, and the scattering is measured by a detector. The software calculates the number and size of particles in the fluid, based on the volume of chemical that is being sampled by the counter, and the scattering pattern. Different types of chemicals exhibit significantly different particle behavior even when dispensed in the same chemical delivery system and filtered with the same type of filter element. There are several reasons for these behavior differences. Some chemicals, such as hydrofluoric acid (HF), hydrochloric acid (HCl), acetone, and isopropyl alcohol, are very clean and easily filtered. These chemicals can exhibit particle levels in the order of 10 particles per milliliter >0.1 µm in size. The particle levels for most other chemicals are higher, either because of interference with particle counters or the actual presence of particles in the fluid. Several chemical properties can impact particle measurements. Chemicals such as hydrogen peroxide or ammonium hydroxide tend to form microbubbles as the pressure drops between the chemical delivery system in the subfab and the POU two levels up. Chemicals that contain surfactants, such as TMAH developer chemistries, can also form microbubbles. Microbubbles in the fluid cause light scattering, and are interpreted by the counter as particles. Even though these chemistries may be just as “clean” as HCl or HF, the particle levels detected by the particle counter are more likely to be in the order of 30 particles/mL >0.1 µm in size. Finally, some chemicals are not as clean as HCl or HF, and cannot be cleaned up to reach the same particle levels, regardless of the filter elements chosen. Chemicals such as phosphoric acid and many back-end post-etch residue removal solvents tend to have particles in the order of 100 particles/mL >0.1 µm in size. One of the most critical particle issues in the industry is the ability to measure small particles. Commercially available chemical particle counters in 2004 cannot measure particles smaller than 0.060 to 0.065 µm in size. According to the International Technology Roadmap for Semiconductors (ITRS),1 the critical particle size dropped below 0.065 to 0.05 in 2003. Some equations can be used to model the number of particles at a small size based on the number counted at a larger size. When plotting particle concentration on the y axis and particle size on the x axis, the negative slope of the line is fairly predictable due to the normal particle distribution. Figure 28.6 depicts the negative slope as measured by four types of particle counters. Calculated particle levels are not sufficient in the long term for several reasons. First, calculated particle levels are more accurate when the measured and predicted particle sizes are similar. For example, it would be more accurate to use the number of particles measured in the 0.065-µm channel to predict the number of 0.05-µm particles than to make the prediction based on the measurement of 0.2-µm particles. Second, as the critical particle size shrinks, so will the number of particles of measurable size (as predicted by the relationship between particle size and particle concentration). As the number of particles in the measurable channels approaches zero, the particle counting statistics suffer. Electrical noise in the smaller size channels represents a significant portion of the measured particle levels. Poor statistics and noise make it inappropriate to use mathematical equations to predict the number of particles at the critical size. As shown by the 2004 update of the ITRS roadmap, new particle-measuring technologies are needed in 2005. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.15

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.15

10000

Concentration (number/ml)

1000

M65 Liquistat 100 KS-16F Microcount 100

Ammonium hydroxide

100

10

1

0.1

0.01 0.06 0.07 0.08 0.09 0.1

FIGURE 28.6

0.2 Particle size (µm)

0.3

0.4

0.5 0.6

Linear relationship between particle size and concentration.2

28.5.5 Sources of Contamination All components in a chemical delivery system will contribute some level of ionic and particle impurity to the fluid stream. The way in which components contribute varies based on the type and function of a component. The ionic levels a component contributes to the chemical are based on the cleanliness of the raw materials, the manufacturing process, and the surface area of the component that is exposed to the chemical. The most common wetted materials in a chemical delivery system are PFA Teflon, PTFE Teflon, and electropolished 316 stainless steel. The primary concerns with Teflon components are the purity of the resins used to produce components and the manufacturing processes. Typically, Teflon parts are produced in molds and machinery used only to manufacture components for the semiconductor industry to reduce the possibility of cross-contamination. Most components are manufactured in a cleanroom environment, and the components are subjected to rigorous cleaning procedures before they are shipped. The primary issue with stainless steel components is to ensure that they are chemically compatible with the fluids they will be used to deliver. Some chemicals will corrode stainless steel or extract iron, which will result in increased ionic contamination levels. The surface area of a component is also a factor. A pump, for instance, has a relatively small surface area exposed to chemicals as compared to a large-area component such as a day tank. While it is critical that all components be as clean as possible, cleanliness is especially important for components that contribute significant surface area to the system, such as tanks and tubing. Ionic contamination can come from the surface of system components or from within the bulk component material. Surface contamination generally comes from handling during the installation process and is quickly flushed away when the component is exposed to the chemical. Contamination from the bulk material is more difficult to remove. When a component is exposed to a chemical over time, the chemical will leach ions from the bulk material. The only way to reach the baseline ionic contamination level is to expose the component or system to the chemical for an extended period of time. Some chemicals, such as HCl, are more extractive than others, so it will take longer for an HCl system to reach the ionic contamination baseline than it will take for an IPA system. Particle purity is also a function of the cleanliness of a component’s raw material, but unlike ionic contamination, particle levels are affected by the behavior of the component. Components such as Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.16

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.16

GASES AND CHEMICALS

tanks, tubing, and filter housings are static. They have no moving parts and generally are very clean from a particle shedding standpoint. Pumps and valves have moving parts, and the movement of diaphragms results in higher levels of particle shedding than with stationary components. When equipment suppliers evaluate components, they should study their shedding characteristics, especially for large surface area components and components with moving parts. Unlike the ionic contamination baseline, which is a function of the time the system has been exposed to a chemical, reaching the chemical baseline for particles is a function of the volume of the chemical that has passed through the system. Neither time nor DI water flushing will allow the system to reach the baseline; only flushing with the chemical is effective. This is likely related to the effect the chemical pH has on particle shedding characteristics.

28.5.6 Contamination Control There are several ways to significantly reduce the ionic and particle contamination in a chemical delivery system. First, the equipment manufacturer must select component vendors that focus on using clean raw materials and maintain clean manufacturing processes. If the components contribute high ionic levels, it will take a very long time for the chemical delivery system to reach the steadystate ionic level, and the system may continue to leach contaminants throughout its service life. A second factor is the start-up procedure used when the chemical delivery system is first installed. As stated previously, reaching the ionic contamination baseline level is a function of time, and the particle baseline is based on the volume of the chemical dispensed through the system. During start-up, the system should be charged with the chemical and allowed to leach or “pickle” for a sufficient period of time to remove the majority of the ionic contaminants from both the surface and bulk component materials. To reach the particle baseline, a significant volume of the chemical must be flushed through the system. The aforesaid factors affect the ionic and particle levels of a new system during the start-up and qualification phase. In addition, design steps can reduce contamination levels throughout the life of the system. Ionic contamination levels will essentially approach zero the longer the system is in a chemical. Two events that can cause ionic contamination are improper maintenance and failed components. During maintenance activities, technicians should make every effort to maintain the integrity of the system, that is, avoid opening tanks or flow paths. When it is necessary to break the lines, the systems should be thoroughly flushed prior to returning them to service. To prevent failed components from affecting ionic levels, only compatible materials should be used, components should be regularly changed based on the preventative maintenance schedule, and regular chemical samples should be taken to monitor the ion levels. In order to take a more proactive approach for long-term particle control first filters that will achieve the lowest possible particle baseline must be selected. Filters will vary, so each application must be reviewed to select the filter membrane material, pore size, and configuration most appropriate for the chemical being dispensed. Even if the best filter for the application is used, the behavior of the chemical delivery system will impact particle levels. If the filters are hammered with significant pressure or flow rate changes, particles that have been trapped by the filter can be released into the fluid stream, causing a particle spike. There are two ways to combat this type of filter shock. One is to limit the pressure pulsations across the filter bank by using a pressure-dispense system, which provides a steady dispense pressure across the filter bank. If a pump system is used, the pump must be paired with a pulse dampener that is efficient in dampening the pulsation output by all positive-displacement pumps. The other technique is filter stabilization. When a chemical delivery system has been idle and then receives a chemical demand from the fab, the system will transition from zero flow to some level of flow through the filters. This can cause filter shock, and in turn, particle release. To prevent this from happening, the filters should be stabilized by continually dispensing a volume of the chemical across the filter bank and back to the drum or day tank, even when there is no fab demand. By stabilizing the filters with a low flow rate, the flow rate change experienced in the filter bank when there is fab demand is less significant and, therefore, the particle spike can be eliminated or significantly reduced.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.17

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.17

28.6 CMP SLURRY SYSTEMS In the mid-to-late 1990s the drive for increased metal interconnect layers and the commensurate desire for increased planarity of various deposited layers drove the wide development of chemical-mechanical planarization (sometimes referred to as CMP). As the name implies, semiconductor planarization relies on a combination of chemical and mechanical processes. CMP slurry typically consists of silica or alumina particles suspended in a chemical mixture. Bulk dispense and blending methods are required because of the large quantities of slurry required in high-volume manufacturing fabs. Slurry systems include many of the basic design features and capabilities found in high-purity chemical systems; however, the presence of abrasive particles introduces significant challenges caused by settling and other phenomena related to the presence of suspended particles in a complex chemical solution. In addition to particle challenges, most slurry systems require blending that led to the design of integrated blend and dispense systems. 28.6.1 Links Between the Slurry Management System and the Polishing Process The high number of variables associated with slurry chemistries tends to create a more significant link between the quality of the slurry delivered to the tool and the success of the polishing process on the tool than one finds with high-purity chemistries. Though the polisher controls and influences most of the outcome of the CMP process, the slurry plays a large role in avoiding defects and influences the polisher’s mean removal rate. Defects. Wafer defects caused in the CMP process are typically scratches, chatters, gouges, or other physical maladies, as shown in Fig. 28.7. While these defects can be caused by foreign objects, such as debris from tubes in a peristaltic pump or pad fragments, “bad” slurry particles, or agglomerations, are well-documented sources of critical defects. Thus a primary requirement of any slurry delivery system is to deliver bad-particlefree slurry to the tool. The equipment manufacturer’s design goal is to minimize the creation of bad particles, while maximizing the ability to remove the particles that end up in the flow path. One way to measure a system’s slurry health is to monitor the particle size distribution over time, as shown in Fig. 28.8. Almost all slurries are impacted negatively by prolonged handling in a dispense system. Initial equipment and system designs as well as operational procedures prolong the lifetime of a slurry. Note the particle size distribution (PSD) curves over a period of time for an unoptimized slurry dispense system.

Gouge FIGURE 28.7

Chatter

Examples of defects characterized as a gouge or a chatter.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.18

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.18

GASES AND CHEMICALS

Normalized cumulative number (# part > = diameter)

40 0 hour 5 minutes 6 hour 24 hours 72 hours 192 hours

30

20

10

0 1

10 Particle diameter (microns)

FIGURE 28.8 Changes in particle size distribution after circulation in a slurry dispense system.

Increased counts of larger particles may cause concern since the larger particles are either the source of defects or may be correlated to the presence of unmeasured defect-causing particles. The ideal system would prevent the drift of the PSD over time; the adequate system prevents drift before the slurry is consumed by the polisher. Mean Removal Rate (MRR). Most polishing processes are timed, that is, a known thickness of the material must be removed over a fixed time, assuming a fixed removal rate. Properties that impact the MRR are thus critical to control. If the observed MRR differs from the expected value, the wafer could be scrapped or require rework. As far as the slurry is concerned, the chemical concentration serves as the primary linkage to MRR. For metal slurries, oxidizer concentrations impact MRR by softening the barrier layer at the polishing pad contact point. Excessive oxidizer can speed MRR, while too little makes the process slower. In the slurry delivery system, the critical chemical concentration must be monitored and/or controlled in the blending and dispense circuits. Using metrology, feedback, and dosing mechanisms in the slurry management system will deliver consistent results to the polisher. 28.6.2 Slurry Blend and Dispense Equipment Design Features While slurry systems have been in use for high-volume manufacturing for years, slurry applications are still considered challenging in 2004. New processes, new materials, and ever-increasing performance requirements result in a rapidly evolving field. The often conflicting needs for slurry management also create unique challenges. Slurry system design involves a constant search to find the balance between “too little” and “too much” of any given parameter. As an example of finding balance, note the following example. Early oxide interlayer dielectric slurries have two seemingly unrelated characteristics—they tend to settle, and they tend to be sensitive to shear forces. Therefore, the slurry must be stirred, but it cannot be stirred too much. In this case, the slurry particles are repelled by weak electrical charges. When subjected to significant mechanical shear energy (as the shear experienced through a partially closed valve or from excess stirring energy), the repelling force can weaken, resulting in agglomerations of the slurry. Minor agglomerations can damage wafers during the polishing process, and large agglomerations can clog the dispense system. To manage this particular challenge, the system must be configured with minimal stirring and shear energy from the engine, flow path geometry, and valves.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.19

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.19

Agitation. In general, the solid particles in a slurry tend to settle over time, requiring specific capabilities to control the homogenization of drums and tanks. The settling rate and redispersion effort is characterized for each slurry by professional slurry management system providers. Drum Stirring. Drums can require little-to-significant stirring in order to homogenize the particles. In most cases, 10 to 20 min of initial stirring, followed by occasional stirring thereafter, is required. As another conflicting requirement, some slurries contain organics that tend to cause foaming under excessive agitation that entrains gas. The stirring system must be configured and operated to prevent foaming at all drum levels, a particular challenge as the level of the chemical in the drum approaches the bottom of the container. Tank Stirring. Tanks also require stirring for particle suspension as well as homogenization, if the chemical requires blending. As an alternative to mechanical stirring, one can create agitation from pump circulation or the use of eductors, that is, static devices that cause turbulent flow. Minimum Velocities. If the velocity of the slurry in the distribution piping is not sufficient, the particles in the slurry may fall out of suspension (resulting in settling), and eventually clog the piping network. Minimum velocities are prescribed for each slurry with a range of one to several feet per second. The flow rate required to achieve the linear velocity is a function of the tube diameter. Humidification. As solutions of suspended particles, slurries also pose challenges where there are gas-to-liquid interfaces that occur in drums, day tanks, and pressure vessels. If the gas above the liquid level in a vessel is not moisture saturated, the liquid will tend to evaporate. Evaporation occurs across the liquid surface as well as on the sides of the vessels as the liquid level drops. When a slurry formulation evaporates, slurry eventually dries, which can create large particles. Large particles entering the dispense system could cause defects on the wafer. Humidification of the gas, typically nitrogen, satisfactorily solves the problem. Humidification systems may be high- or low-pressure systems and rely on membrane cell, bubbler, or heating technologies. Dead Legs. The tubing in high-purity chemical systems is typically routed to promote the efficient use of space and easy maintenance access. In slurry systems, the tubing layout requires careful consideration to avoid the creation of dead legs, that is, any section of the tubing through which a slurry does not typically flow. The most common dead legs occur in the downward legs of vertically oriented “tee” fittings. Dead legs can clog within days or weeks. Filtration. Slurry filtration, a topic of great focus and debate, can be introduced through a few simple concepts. As opposed to high-purity chemical filtration, where there is a low concentration of small particles, slurries pose a distinctly different filtration challenge due to the high concentration of particles of various sizes (most of which are required by the process). In such applications, the primary concerns are filter efficiency and life cycle. If a large slurry volume flows through a tight pore filter, it will clog quickly. If the pores are too large, the filter will only remove the largest particles, thus solving only part of the problem. Based on the slurries and filters currently available, today’s approach is to use a combination of main distribution filters and POU filters. The main loop filters are usually larger pore (3 to 20 µm), while the POU configuration is 1 to 3 µm. The slurry filtration system design must also consider practical issues such as ease of replacement, clog detection, and filter life extension. POU Pressure Control. A slurry is dispensed on the platen directly from the main slurry distribution loop that typically runs directly under the polisher. Because there is no intermediate vessel between the source and the use point of the slurry, the tool relies on the pressure from the slurry dispense system to control the flow rate of the slurry delivered to the platen. While most tools have a pump to help regulate flow, these pumps are often sensitive to incoming pressure changes. Consider the following example. Assume “tool one” is calling for a chemical and the pressure in the main slurry dispense loop is 30 psi. If two more tools call for the slurry, the pressure in the loop may drop to 28 psi due to dynamic Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.20

CHEMICAL AND SLURRY HANDLING SYSTEMS 28.20

GASES AND CHEMICALS

TABLE 28.7

Process-Specific Slurry Characteristics

Property

Ox

W

STI

Cu

Settling rate Resuspension rate Shear sensitivity Large particle formation Constituents

Low-k Not a concern A moderate concern A primary concern

Pot life Foaming Aggressive oxidizers

pressure losses (losses due to frictional forces). When the pressure drops, the flow rate of the slurry at tool one drops, and the MRR or other key process factors may change. The most effective way to control dispense pressure at the tool is to use a dynamically controlled pressure dispense system or a purpose-built flow controller at the tool that is not sensitive to pressure fluctuations. A dynamic pressure control system relies on a dispense engine that adjusts dispense pressure or loop backpressure based on a signal from a mid-loop pressure sensor. As the loop pressure drops due to higher demand, the system compensates by increasing the dispense pressure or the backpressure. 28.6.3 Handling Considerations for Various CMP Processes One truth in the application space of chemical and slurry management is the need to understand and respond to the subtle and profound differences between various materials. There are more than 600 distinct chemical formulations used in the semiconductor industry today, and any two may require different handling or safety considerations. In the world of slurry management, properties and challenges align roughly by process type. Table 28.7 lists the handling challenges associated with the major process types. Oxide and tungsten, as the most mature, served as the learning platforms for the industry. Each presented challenges. The advent of STI, copper, and low-k brought a new set of challenges. Two simple design philosophies guide a successful approach to slurry system designs. Slurries designed to polish different film layers exhibit a variety of different properties. 1. For those properties or issues that are common across many slurries, the equipment should be designed to be immune to the challenging properties. For example, many slurries interfere with common optical or capacitive level sensors. Since this is the case, and since great effort is required to find the right sensor for each application, they should be designed out of the system. Load cells are a better level detection device for slurries. 2. For those properties that are more unique, slurry-specific configurations should be created to control cost across all applications, but provide the value required in special circumstances. A few of the low-k and Cu slurries tend to foam due to the presence of organic additives. Slurry-specific drum management systems can reduce foaming, but the cost is not required for all systems.

28.7 CONCLUSIONS The number one rule of chemical and CMP slurry management is to know the behavior of the material and know how to design around them to provide a perfect chemical or slurry to the tool, all of the time. With safety and process protection as the driving design parameters, the growing world of wet processing will continue to rely on critical process systems that handle, purify, blend, and control high-purity chemicals and CMP slurries.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.21

CHEMICAL AND SLURRY HANDLING SYSTEMS CHEMICAL AND SLURRY HANDLING SYSTEMS

28.21

REFERENCES 1. International Technology Roadmap for Semiconductors, 2003. 2. D. Carrieri, D. C. Grant and W. Kelly, “Comparison of Optical Particle Sensors Used to Measure Particle Concentrations in High-Purity Chemicals, Phase II—Sensor Comparison in Chemical,” Presented at Semicon West, San Francisco, CA, July 1999.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH28.qxd

04/04/2005

20:56

Page 28.22

CHEMICAL AND SLURRY HANDLING SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 29

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES Charles K. Gould Entegris, Inc. Chaska, Minnesota

29.1 INTRODUCTION The management and handling of liquid chemicals in the semiconductor fab have evolved with the increased need for chemical purity, factory automation, and more complex chemical processes. The fluid handling components used to protect, transport, measure, and control these liquid chemicals have evolved and continue to evolve with new products and innovations, especially in the area of the measurement and control of high-purity chemicals and slurries. There are numerous chemicals used in the manufacturing of semiconductors; the most common chemicals used in the greatest quantities are the following: • Acids • • • • • •

Hydrofluoric acid Sulfuric acid Hydrochloric acid Nitric acid Buffered oxide etch (BOE) Phosphoric acid

• Bases and oxidizers • • • • •

Hydrogen peroxide Ammonium hydroxide Tetramethyl ammonium hydroxide (TMAH) Sodium hydroxide Potassium hydroxide

• Solvents • Isopropyl alcohol (IPA) • n-Butyl acetate (IBA) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

29.1

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.2

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.2

GASES AND CHEMICALS

• Ethylene glycol monomethyl ether amine (EGMEA) • Propylene glycol monomethyl ether amine (PGMEA) • n-Methyl pyrrolidinone (NMP) • Aqueous-based slurries • Oxide slurries • Metal slurries The aforementioned chemicals are typically shipped in bulk containers to the manufacturing site and then pumped throughout the facility via lengths of tubing using bulk dispensing equipment. The type of chemical being pumped will influence the fluid handling techniques, components, and materials used to transport the chemical to manufacturing tools typically located in the cleanrooms. The greatest number of measurement and fluid control points (flow, pressure, level, and temperature) are found in the manufacturing tools located in the fab cleanroom.

29.2 MATERIALS OF CONSTRUCTION FOR FLUID HANDLING COMPONENTS Fluid handling components used in the semiconductor industry must be constructed with appropriate materials that are compatible with the intended chemical usage. Components having surfaces that are wetted by high-purity chemicals must be chemically inert to prevent the contamination of the process fluid. The nonwetted surfaces must also be compatible with the chemical in order to maintain the mechanical and structural integrity of the component. In general, fluid handling components for acids, bases, slurries, and deionized (DI) water are constructed using fully fluorinated high-purity polymers, most typically perfluoroalkoxy (PFA) or polytetrafluoroethylene (PTFE), for the wetted surfaces. In some cases, a partially fluorinated polymer, such as PVDF, may be used for DI water and some slurries. Parts constructed from PFA and PVDF are typically manufactured using injection molding techniques, whereas PTFE is manufactured using machining techniques. 29.2.1 Polymers Here is a list of polymers by its trade name and manufacturer: Fully Fluorinated High-purity Polymers PFA: perfluoroalkoxy ® TEFLON PFA (DuPont) ® Neoflon PFA (Daikin)

[(CF2CF2)n

MFA: perfluoromethylalkoxy ® Hyflon MFA (Ausimont)

[(CF2CF2)n

(CF2

(CF2

CF

)m]x

O

C3F7

CF

)m]x

OCF3 PTFE: polytetrafluoroethylene ® TEFLON TFE (DuPont) FEP: fluorinated ethylene propylene ® TEFLON FEP (DuPont)

(CF2CF2)n (CF2CF2)n

(CF2

CF)m CF3

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.3

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.3

Partially Fluorinated High-purity Polymers ETFE: ethylene tetrafluoroethylene Tefzel® (DuPont)

(CH2CH2

CTFE: polychlorotrifluoroethylene Kel-F ® (3M)

(CF2

CF2CF2 )n

CF)n Cl

ECTFE: ethylene-chlorotrifluoroethylene Halar ® (Ausimont)

(CH2CH2

CF2

CF)n Cl

PVDF: polyvinylidine fluoride Kynar ® (Atochem North America, Inc.) Solef ® (Solvay) Foraflon ® (Ugine Kuhlman)

(CH2CF2)n

High-Performance Engineering Thermoplastic Polymers O PEEK: polyetheretherketone (Victrex plc) PPS: polyphenylene Sulfide Ryton®(Phillips)

[(C6H4)

C

[(C6H4)

S]n

(C6H4)

O

(C6H4)]n

Additional Polymers HDPE: High-density polyethylene LLDPE: Linear low-density polyethylene

(CH2CH2)n (CH2CH2)n

29.2.2 Description and Performance of PFA and PTFE PFA is manufactured from a fluoropolymer resin; thus most products constructed with PFA are manufactured by injection molding. PTFE is manufactured by pressing and sintering fluoropolymer powder. PFA is a melt-processable thermoplastic with similar chemical resistance to PTFE. PTFE is white in color, whereas PFA has a much lower porosity and is translucent. Most high-purity fluid handling applications will utilize PFA and PTFE as the materials of choice for the wetted surfaces. Other polymers that are used in ultrapure systems include TFM, FEP, and various modified versions of PTFE. TFM is essentially similar to PTFE but with reduced porosity and improved tensile strength, and may be thermally welded. This material is typically used for components that must be thermally welded to PFA piping or tubing. The properties of a filled or modified PTFE can vary. A range of fillers, typically glass fiber, carbon, graphite, metal powders, and molybdenum disulphide can be blended with PTFE resins, usually in the proportion of 2 to 40 percent, to improve certain physical characteristics. The incorporation of fillers can increase compressive strength, improve thermal conductivity and abrasion resistance, reduce thermal expansion and cold flow, and impart electrical conductivity. The use of fillers may downgrade other properties of PTFE, such as chemical and electrical resistance. 29.2.3 Chemical and Thermal Resistance of PFA The relative reactivity of a polymer to chemicals and to heat depends on several parameters, the most important being the atomic bond energy of the polymer atoms. Fluorine atoms encircle the carbon

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.4

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.4

GASES AND CHEMICALS

backbone of the PFA polymer. The carbon-fluorine single bond is among the strongest known and results in PFA being virtually chemically inert and nonwettable by fluids such as water. By chemically inert, we mean that PFA resins can be in continuous contact with another substance with no detectable chemical reaction taking place. The carbon-fluorine bond also accounts for the excellent thermal properties of PFA. This is not only important in elevated temperature service, up to 500°F (260°C), but also during the processing of the resin into usable parts. In general, PFA is inert to virtually all chemicals except molten alkali metals, fluorine at elevated temperatures, and certain complex halogenated compounds at elevated temperatures and pressures. It is also chemically resistant to strong mineral and oxidizing acids, bases, halogens, metal salt solutions, organic acids, and anhydrides. Aromatic and aliphatic hydrocarbons, alcohols, aldehydes, ketones, ethers, amines, esters, chlorinated compounds, and common cleaning solvents have little effect. 29.2.4 Absorption and Permeation of PFA Plastics and elastomers, in contrast to metals, absorb varying quantities of materials they contact, especially organic liquids. Absorptives in PFA are unusually low, and a chemical reaction between the resin and other substances is rare. When absorption is combined with other effects, this property can influence the serviceability of a component in a particular chemical environment. Closely related to absorption is permeation. The permeability of gases, vapors, or liquids through a plastic is generally considered to be an activated diffusion process. The gas, vapor, or liquid dissolves into the membrane and then diffuses to a position of lower concentration. The permeation rate may be determined by the size of the permeating molecule, the presence of a pressure differential, the temperature, and the density of the plastic membrane. 29.2.5 Safety in Handling of PFA In the last 45 years, experience has shown that no reported cases of serious injury, prolonged illness, or death have resulted from the handling or manufacturing of products that use fluoropolymer resins. Tests further indicate that the resins may be taken in food without ill effects and are nonirritating and nonsensitizing to the skin. There have been no known instances of dermatitis, allergy, or other ill effects in humans caused by handling unheated fabricated forms of the resins. In the case of human exposure to heated fluoropolymer resins, no lethal effect has been observed. Instead, such exposure has merely caused a temporary flu-like condition called polymer fume fever. The symptoms do not ordinarily occur until about two or more hours after exposure and pass off within 36 to 48 h, even in the absence of treatment. Observations indicate that these attacks have no lasting effect and the effects are not cumulative. When such an attack occurs, it usually follows exposure to vapors evolved from the polymer at high temperatures used in resin processing operations. Ventilation is typically provided to eliminate this potential problem and the resultant operator discomfort. During the welding of pipe components, additional ventilation other than that found in the normal workplace is usually not required. This is due to the relatively small quantity of PFA that is heated. To further safeguard against the potential discomforts of polymer fume fever, workers must not smoke tobacco while welding piping components. This will reduce the possibility of inhaling any decomposition products, although small in quantity, that may be overheated by drawing them through a lit cigarette.

29.3 METAL IMPURITIES, TOTAL OXIDIZABLE CARBON, AND PARTICLE CONTAMINATION The analytical technique of choice for the determination of metallic impurities in high-purity materials or chemicals is called inductively coupled plasma/mass spectrometry (ICP/MS). ICP/MS is used almost universally to generate quantitative data on virtually all elements in the periodic table.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.5

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.5

Ions are extracted into liquids from the wetted surfaces of the fluid handling components, and the liquid is commonly evaporated to eliminate background interference. The trace metals are then dissolved into dilute nitric acid and analyzed. The total oxidizable carbon (TOC) present in process systems may contribute to biofilm growth by providing a food source for microorganisms. Components manufactured from PFA have very low extractable TOC levels. For most high-purity applications, it is important to use products that do not contribute particles to the process fluid. Fluid handling components must pass stringent particle count tests to meet industry expectations for particle contamination.

29.4 INDUSTRY TEST STANDARDS AND PROTOCOLS Typically, a supplier of fluoropolymer-based fluid handling components serving the semiconductor industry must invest a significant amount of time and money in the continual testing of the products it produces and sells. The manufacturer will typically refer to several standards used for the qualification and ongoing testing of the fluid handling products. In conjunction with these standards, numerous other testing programs to accommodate the unique designs and materials of construction are often employed to ensure the products will perform in a safe and reliable manner. Typical standards for fluid handling components: ASME standards ASTM standards ANSI standards PPI standards DOT standards ISO standards SEMI standards ISA standards

29.5 FLUID HANDLING COMPONENTS Fluid handling components used for storage, transport, measurement, and control of high-purity chemicals include tubing and pipes, fittings, valves, drums, tanks, flowmeters, pressure transducers, and level indicators. 29.5.1 PFA Tubing and Pipe Several purity grades of PFA tubing are commercially available. In general, there are two categories— high-purity grades manufactured from virgin materials and high-purity grades manufactured with virgin and “regrind” material. Regrind is the term often used to describe excess or scrap material that is recycled from the manufacturing process. Tubing grades manufactured from virgin materials typically have the best purity and consistency; however, several applications may not require such high purity or the associated expense. Tubing is usually sold in long continuous sections coiled on large reels. The tubing is typically permanently serialized with laser marking along the tubing exterior to allow immediate tube material and size identification. Laser marking also allows 100 percent traceability to a specific material lot, production date, and production inspection record.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.6

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.6

GASES AND CHEMICALS

Tubing made from 100 percent virgin high-purity PFA has shown to have the highest resistance to specialized photoresist developers containing harsh surfactants and is ideal for ultrapure and highly corrosive applications. Typical standard wall tubing available in English units include—1/16, 1/8, 1/4, 3/8, 1/2, 3/4, and 1 in outside diameters. PFA tubing and pipes should have an exceptionally smooth bore. This provides for optimum flow performance, limited entrapment areas, less frictional drag, less turbulence at high flows, no corrosion, no wetting of the PFA, and resistance to bacterial growth. PFA tubing and pipes retain these characteristics over their service lives. For applications where dual containment PFA tubing is required, some manufacturers offer long continuous lengths of double-contained PFA tubing. This reduces installation costs as the tubing is supplied ready to install in long runs. Typical applications for dual containment tubing include the subfab area for bulk chemical distribution. Welding of PFA Tubing and Pipe. Both PFA tubing and piping may be welded to fittings, valves, and other fluid handling devices into an ultraclean, chemically resistant, leak-free fluid delivery network. The welding process is a unique noncontact, butt-fusible process. A special tool and fixtures, in addition to proper operator training, is required to perform the welding operation. The welding tool allows for the proper cutting, facing, and heating of components to be joined into whatever design is needed. The welding tool holds pipes, fittings, and valves in proper alignment. A facing tool presets the distance the parts extend into the welding tool with a flat and smooth surface. A guided slide mechanism holds the parts together while the material cools, joining the components permanently. A noncontact heater is centered by guides on the welding tool. Preset locking prevents molten ends from being pressed too far together. The welding tools provide bonds of consistent quality. If welding is not used as the connection method, the user must use an assortment of fittings, which is discussed later. Pipe Support of PFA Tubing and Pipe. Long lengths of PFA tubing and pipes must be supported to provide trouble-free services. Pipe supports minimize the degree of stress and strain within the pipe wall to an acceptable level and allow for adequate draining. The minimum recommended distance between pipe supports is calculated by taking into account the weight of the pipe, its contents, and an allowable stress. The distance between the supports is also affected by the pipe size and temperature. The specific gravity of a fluid greater than 1.0 can adversely affect the spacing of the pipe supports. The manufacturer of the tubing or pipe should be contacted for the recommended spacing distance. The pipe supports specified should not be of the type that clamp the pipe tightly and restrict movement, especially when thermal expansion and contraction are involved. Not using this type of clamp will prevent abrading and damage to the pipe wall. An excellent option to intermittent pipe supports is to continuously support the pipe by laying it in a plastic trough. A commonly extruded shape such as an angle, channel, or conduit works well as a trough and is less costly than numerous pipe brackets. Vertical sections of pipes, referred to as risers, must also be supported. The top and base of the risers should always be supported. Accessory items such as valves, filter housings, and the like should not be fully supported by the pipe. Individual supports should be specified for all heavy components connected to a piping system. Thermal Expansion and Contraction of PFA Tubing and Pipe. Thermal expansion and contraction of PFA tubing and pipes should be considered during the system design and installation stages. Any significant temperature changes from the installed temperature will affect the pipe length. One common guideline is to install the pipe when it is within 10 to 15°F of its operating temperature. When this is not practical, a thorough examination of the piping layout should be made. Small temperature changes may be tolerated because of the lower modulus of elasticity and inherent stress relaxation property of PFA. When large temperature changes are present they should be compensated for in the piping layout. To determine the extent of the length change, a formula is used that takes into account the coefficient of linear thermal expansion of the specific material.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.7

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.7

An easy rule of thumb for estimating the length change is to assume that for every 10°F change, a change of 1 in will occur in any 100-ft linear length. When substantial length changes are evident, they must be compensated for by the use of flexible sections, expansion loops, expansion joints, and the like. Should this prove to be a concern in a piping system, the manufacturer should be contacted for advice in properly incorporating these options. Shipping, Storage, and Handling of PFA Tubing and Pipe. PFA tubing and pipe components are shipped with protective coverings to reduce the possibility of contamination and prevent damage due to shipping and handling. The pipe sections (10 ft or 3 m) are typically capped at both ends and placed in a protective poly bag. Tubing is typically sold in large continuous sections and rolled onto reels. Fittings and accessories are also individually poly bagged for shipment. The protective poly bag surrounding the pipe products should be left intact until that part is needed. This will help prevent particulate contamination. If the parts are to be placed in storage, they are to be kept in a clean and dry area. The pipe should be stored in only the horizontal position with continuous support. This will eliminate any problems associated with bowed pipe and damaged ends. 29.5.2 Fittings Fittings are most commonly used when using PFA tubing, whereas a PFA pipe is typically welded and requires fewer fittings. Tube fittings are used extensively for connecting polymer components used in ultrapure water and liquid chemical distribution systems. A leak-free performance of the fitting connection is achieved with minimum dead volume for ultrapure fluid applications by using fittings that attach to a flared-tube end. Fittings of the flared-tube type maintain seal integrity in high vibration applications and are ideal for compact plumbing and Fitting body Flared tube systems requiring a small cleanroom footprint. The tube flaring process provides a permanent expansion (flare) of the tubing end, allowing insertion onto the fitting body and is secured using a threaded nut. Proper tube flaring and fitting assembly results in a secure tubing connection. The connection may be tightened and untightened by hand without the use of tools, which is ideal for maintenance. (See Figs. 29.1 and 29.2.) Increased performance of the fitting maybe achieved by using an integral ferrule that locks onto a groove engraved onto the exterior diameter Tube nut of the tube. The performance reliability of this fitting type is dependent on the care and caution FIGURE 29.1 Schematic of flared-tube fitting conused in grooving the tube and tightening the fitting nection. (Courtesy of Entegris, Inc.) properly. 29.5.3 Valves High-purity, corrosion-resistant valves are needed throughout piping networks to safely and reliably control the flow of chemicals and slurries. Valves vary in size, design, and functionality according to the usage and application requirements. Valves are also chosen based on temperature, pressure, flow, size, configuration, and installation needs. A very common attribute used to compare valves to one another is performed by comparing CV factors. A valve’s CV factor is the number of gallons of water that will pass through a valve orifice area in 1 min at a pressure drop of one psig. The metric equivalent is KV factor, which is the number of liters per minute of water that pass through a given orifice area at a pressure drop of 1 bar. When designing a piping network, valves with high CV factors are considered desirable since the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:57

Page 29.8

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.8

GASES AND CHEMICALS

FIGURE 29.2 A typical tube-to-tube union fitting for flaredtube connections. (Courtesy of Entegris, Inc.)

pressure drop will be lower, typically saving the cost and complexity for the pumping systems and piping network. A well-designed valve will have “swept” surfaces, whereby there are little or no regions where fluid flow is stagnant. Valves with no stagnant areas are especially important for slurry applications, slurries tend to settle, harden, and form agglomerations in valves without swept surfaces. Diaphragm Valves. A diaphragm valve (Figs. 29.3 and 29.4) uses a flexible diaphragm to control fluid flow by positioning the diaphragm against a fixed stop in order to cease flow, or releasing the diaphragm to open the fluid-flow path. The reliability of this type of valve is usually proportional to the cycle life rating of the diaphragm. Diaphragm valves will typically use PTFE or molded PFA wetted surfaces for purity, chemical inertness, and high temperature capabilities. These valves should not have any external metal parts that can corrode or represent a safety hazard in aggressive chemicals. Most valves are available in manual or pneumatic two-way, three-way, and sampling styles. Custom valve configurations are typically available, as are remote position indication and leak detection options.

FIGURE 29.3 Photo of a typical diaphragm valve for highpurity chemical and slurry. (Courtesy of Entegris, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.9

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.9

3.83" (97.3 mm)

C

B

A FIGURE 29.4

Schematic of a typical diaphragm valve. (Courtesy of Entegris, Inc.)

Pinch Valves. The pinch valve uses two diaphragms that, when touching each other, close the fluid flow path. When the diaphragms are moved apart, the fluid path is opened. The two diaphragms may be fabricated as a single entity, sometimes appearing like a flattened section of tubing. Pinch valves tend to have the best characteristics for low hold-up volume and swept surfaces, making them an ideal solution for slurry and high-viscosity chemical handling. See Figs. 29.5 and 29.6. Other Valves. Other valves used for high-purity, high-corrosive fluid control applications are needle valves, metering valves, stopcocks, solenoids, check valves, and fast action plug valves, all of which are available in a wide variety of styles and sizes. (See Figs. 29.7 and 29.8.) 29.5.4 Drums, Tanks, Containment Vessels Chemicals are typically transported in bulk form to the semiconductor manufacturing facility. An assortment of chemical container products are available for the transportation, storage, and dispensing of ultrapure and hazardous materials where safety is critical. Such products include reusable composite PFA and polyethylene drums, pressure vessels, intermediate bulk containers, quick-connect systems, PFA sheet lined containers, PFA sheet lined tanker trucks, and custom containers and bottles (Fig. 29.9). Reusable packages, typically 55-gal drums, 500, 800, and 1200 L intermediate bulk containers (IBC) (Fig. 29.10), and larger bulk containers help reduce packaging disposal costs. For reusable packages, the actual package cost is rapidly amortized over several round trips (fill and refill cycles) of the package. The container product must maintain the purity of the chemical by minimizing metallic, organic, and particle contamination during transport.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.10

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.10

GASES AND CHEMICALS

FIGURE 29.5 Photo of a pinch valve used for slurry and highviscosity applications. (Courtesy of Entegris, Inc.)

The DOT (Department of Transportation) and the United Nations have various approvals for transporting hazardous chemicals such as nitric, sulfuric, and hydrofluoric acid. Manufacturers of transport containers must test their products to meet various approval standards for domestic and international shipping. For operator safety, transport containers use specialized key-coded fluid connection systems to provide a safe method of connecting containers to dispense systems. A key-coded connection fitting Normally open pneumatic port

f 3.93" (99.82 mm)

7.20" Normally closed (187.88 mm) pneumatic port 6.83" (173.48 mm)

3.43" (87.12 mm)

1.44" (36.58 mm) A FIGURE 29.6

Schematic of a pinch valve. (Courtesy of Entegris, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.11

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.11

FIGURE 29.7 Multiple diaphragm valves mounted on a common manifold using a surface mount technology. (Courtesy of Entegris, Inc.)

will only fit with the associated mating fitting with the same key code. This key-code system assures against unsafe chemical mixing and minimizes human exposure to the chemical and fumes. When choosing transportation containers, it is critical to ensure that the integrity of ultrapure chemicals is not compromised when being transported in the containers. The container must maintain low particle contamination and metal and organic extractable elements to ppb or ppt (parts per billion or parts per trillion) levels needed for semiconductor fabrication.

29.6 FLUID MEASUREMENT DEVICES Choosing flow, pressure, and level measurement instrumentation for the semiconductor industry can be particularly challenging. The primary challenge is maintaining a high level of purity of process liquids that are often highly corrosive. To meet this challenge, the following basic product attributes should be chosen for measurement instrumentation: • • • •

No moving parts within the fluid path No usage of fill fluids within the instrument Wetted surfaces to be constructed of PTFE or PFA materials Dual containment for all fluid seals

1.81" (46.0 mm) 2.67" (67.8 mm) 0.43" (10.9 mm) FIGURE 29.8 Entegris, Inc.)

Schematic of multiple diaphragm valves mounted on a common manifold. (Courtesy of

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.12

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.12

GASES AND CHEMICALS

Transparent PE splash hood and flex hose Dispensing head

Shipping plug

Drum insert

FIGURE 29.9 A typical reusable 55-gal drum with a PFA liner and keycoded dispensing head. (Courtesy of Entegris, Inc.)

• Metal-free and chemically resistant instrument construction • Compact design with small footprint • Reliable instrument technology from an experienced manufacturer

FIGURE 29.10 A 1200L storage tank with a PFA liner used for high-purity chemicals and slurry. (Courtesy of Entegris, Inc.)

Instrumentation with moving parts that are used for prolonged periods inevitably risk becoming worn or degraded over time. When wearing or degradation occurs, devices with moving parts in the fluid stream can generate increased levels of particles. Worn or partially degraded devices that generate particles will often function normally, making it difficult to identify the particle generation source within complex high-purity fluid systems. Simply avoiding the use of instruments with moving parts will minimize the risk of particle contamination. Instruments with fill fluids, typically pressure gauges with gauge protectors, typically have a metallic pressure sensor in contact with a stationary fill fluid. The fill fluid is in contact with a flexible seal (or isolation membrane) that separates it from the high-purity process fluid. The fill fluids from these instruments may leak, causing initial contamination from the fill fluid and hence a continuous stream of contamination after the process chemical invades and attacks the exposed metallic surfaces. While appropriate applications do exist for instruments utilizing fluid-filled cavities, their use in ultrapure corrosive environments should be avoided.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.13

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.13

If a measurement instrument, a valve, or another fluid handling component requires a seal in the fluid stream, the seal should have a back-up seal, typically referred to as “dual containment.” The dual containment seal prevents a catastrophic failure from occurring. When constructed properly, the dual containment seal isolates the fluid from any part of the device that may contaminate the highpurity fluid, in addition, the seal routes the fluid to a safe location, typically into a chemical waste drain with a leak detection sensor. Chemicals commonly used in the semiconductor industry, such as hydrochloric acid, may chemically attack various metal parts of an instrument due to contact with the liquid chemical or corrosive fumes. The resultant attack on the metallic surfaces (fasteners, wiring, or circuitry) can lead to premature instrument failure or contamination of the ultrapure process. The severity of this phenomenon is dependent on a number of factors such as the specific fluoropolymer or other materials used for wetted parts, the instrument design, chemical concentration, fluid temperature, and line pressure. In general, instruments in ultrapure or corrosive fluid environments should be constructed of metal-free, high-purity inert substances that are resistant to the chemicals being used. Flow, pressure, and level measurement devices come in all shapes and sizes, each with different installation requirements. Piping network valve boxes, semiconductor processing tools, chemical distribution systems, and other fluid handling equipment often have limited physical space available for large fluid handling components. Some instruments may not be appropriate for installation into applications where footprint size is a critical factor. It is beneficial to choose instruments that are not too large, require specific installation or mounting constraints, or are susceptible to electronic noise, vibration, or gas bubbles. Critical applications require instruments with proven designs in order to provide years of problemfree, reliable, continuous duty in ultrapure and corrosive environments. It is critical to choose components that will allow the greatest time before instrument failure or routine repair.

29.6.1 Pressure Measurement Special considerations are necessary when choosing pressure measurement instrumentation for ultrapure corrosive fluid environments. For most applications, high-purity fluoropolymer wetted parts are needed for compatibility or purity reasons. These materials are used in a number of pressure measurement technologies, some of which utilize fluid-filled transducers or gauge protectors. Choosing a fluid-filled technology for an application may lead to process contamination and equipment downtime. Fill-fluid-type pressure transducers, gauges, and gauge protectors typically have a metallic pressure sensor in contact with a stationary fill fluid. The fill fluid can be oil, silicone, or other material, and is most often DI water for high-purity applications. The fill fluid is in contact with a flexible seal (or isolation membrane) that separates it from the process fluid. As the process pressure changes, the fill fluid pressure correspondingly changes. The pressure sensor actually measures the fill-fluid pressure that will typically correspond with the process pressure. The primary disadvantage of fluid-filled instruments is the risk of fluid leaks through a breach in the flexible seal. If a seal breach occurs, the fill fluid (e.g., DI water, or oil) will leak into the process stream and expose the pressure sensor to the high-purity or corrosive process fluid. Fill fluid leaks inevitably occur and their frequency is most often reduced through preventive maintenance programs. Harsh operating conditions, corrosive fluids, and frequent changes in line pressure typically increase the likelihood of such a seal breach. Pressure transducers and gauge protectors (Figs. 29.11 and 29.12) with fill fluids typically do not indi- FIGURE 29.11 A typical pressure gauge and a cate when they have failed. As noted earlier, failed gauge protector that uses fill fluid. (Courtesy of units may still function after the fill fluid has leaked Entegris, Inc.) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.14

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.14

GASES AND CHEMICALS

Fill port 5.95" (151.1 mm) 2.88" (73.2 mm) 0.74" (18.8 mm) A

FIGURE 29.12 Entegris, Inc.)

2.89" (73.4 mm)

Schematic of a pressure gauge and a gauge protector assembly. (Courtesy of

out, and the cavity has been filled with the process fluid. Therefore, there can be a period of time when the unit is contaminating the process, but the failure cannot be detected from the instrument output. As noted earlier, fluid-filled pressure measurement instruments can experience undetected isolator seal leaks. An undetected leak on any part of a pressurized system with hazardous or corrosive chemicals is a safety hazard. Instrument failure and subsequent process contamination can ultimately lead to significant and costly downtime. From the aforementioned discussion, it is the obvious choice to use pressure transducers that do not use fill fluids. See Figs. 29.13 and 29.14. 29.6.2 Flow Measurement Flow measurement and control components for high-purity, corrosive applications must be chosen according to the needs of the specific applications. Most liquid flow measurement and control products FIGURE 29.13 Photo of a pressure transducer that uses no fill designed for the semiconductor industry are manufactured with PFA fluids. (Courtesy of Entegris, Inc.) or PTFE wetted surfaces for purity and chemical compatibility. Several technologies for flow measurement are available. However, only the most commonly used technologies will be discussed in the next sections. The following application information should be determined prior to choosing a flowmeter or controller: • • • • • •

Fluid physical properties (i.e., specific gravity, viscosity) Temperature and pressure at the point of measurement Flow rate—note the minimum, maximum, and expected nominal flow rates Accuracy and performance needs (i.e., response time, repeatability) Installation constraints Long-term reliability needs

Variable Area Flowmeters, Rotameters. The most basic form of measuring flow is performed by using variable area flowmeters, or rotameters. Variable area flowmeters may be used where a visual indication and manual adjustment of the chemical flow is needed. Basically, rotameters use a float that moves up or down a tapered and clear graduated tube in proportion to the fluid flow rate. When flow occurs, the float is visible through the clear tube and moves upward for

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.15

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.15

Polypropylene electrical connector option Signal conditioning circuit

Electronic pressure sensor Solid PTFE

Flared tube process connection FIGURE 29.14 Schematic of a pressure transducer that uses no fill fluids. (Courtesy of Entegris, Inc.)

higher flows and downward for lower flows. Most rotameters are supplied with an adjustment valve. (See Figs. 29.15 and 29.16.) Paddlewheel Flowmeters. Paddlewheel style flowmeters, sometimes referred to as “turbine” flowmeters, use a wheel or rotor to measure fluid velocity. Wheel rotation may be detected via magnets in the paddlewheel, optical sensors, or other detection methods. Wheel rotation is proportional to fluid velocity at most flow rates for fluids with physical characteristics similar to water. The flowmeter or signal receiver mathematically converts the fluid velocity (ft/sec or similar units) to a volumetric fluid flow rate. The most common complaint for users of paddlewheel flowmeters in high-purity and slurry applications is mechanical failure that can lead to particle generation, equipment downtime, and particle contamination. Since particle contamination is a critical variable for many processes, many wafer manufacturing units and process tool manufacturers will not consider paddlewheel technology due to the risk of inadvertently introducing particles to the process. FIGURE 29.15 Photo of variable area Particles may be generated from paddlewheel flowmeters by flowmeters (rotameters) manufactured the degradation of the flowmeter moving parts leading to parti- from PFA materials. (Courtesy of Entegris, cle generation, and in slurry applications, the paddlewheel may Inc.) form and release large agglomerated slurry particles. The paddlewheel rotor is a continuously moving part, thus erosion of the rotor can occur and lead to particle generation in the fluid stream. This erosion may be accelerated by contact with highly corrosive fluids. For slurry applications, the slurry may agglomerate into larger particles when small amounts of the slurry become trapped in low-flow regions of the flowmeter. There are two relevant installation constraints typical for paddlewheel flowmeters—mounting orientation and straight lengths of pipes. Many paddlewheel flowmeters require a number of straight lengths of pipes before and after the device for best measurement accuracy, and most paddlewheel flowmeters must be installed in a fixed horizontal position in order to function properly. Some paddlewheel flowmeters measure flow by the use of optical sensor technology. For these units, light of a certain wavelength passes through the process fluid, is detected on the other side of the device interior, and detects wheel rotation. Some chemicals and slurries that are more turbid may

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.16

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.16

GASES AND CHEMICALS

Panel mounting nuts: PVDF or PFA

Molded housings: TEFLON® PFA HP plus material

TEFLON® PFA HP plus material stem/handle provides 75% stronger connection than alternative flowmeters

New, smaller handle: PVDF Tapered sight molded from TEFLON® PFA HP plus material Guide rod: Kel-F™ CTFE PureBond® welded connections eliminate potential feak paths

Float: PTFE

Wide variety of industry standard end connections, including Flaretek® with PFA nuts and FNPT FIGURE 29.16 Entegris, Inc.)

Schematic of a variable area flowmeter constructed with PFA material. (Courtesy of

affect light transmittance through the liquid and will thus affect the fluid flow measurement. Other factors that affect light transmission or detection may interfere with paddlewheel flow measurement such as physical vibration and close proximity to electrical noise. Gas bubbles affect the ability of a fluid to turn a rotor and the magnitude of this effect will vary with the volume of gas bubbles in the fluid stream. At best, bubbles will affect the paddlewheel motion and alter the flow measurement accuracy. In some cases, gas bubbles will entrain in and around the wheel mechanism, significantly affecting the output. Note that hydrogen peroxide and various slurries can create gas bubbles under certain process conditions. Vortex Flowmeters. A vortex flowmeter detects flow by measuring the frequency of vortices created as fluid travels around a fixed object. A fixed post or “shedding bar” is typically placed in the flow path to create these vortices. The vortex frequency is proportional to the flow and by measuring the frequency of the vortex formation generation, the fluid flow may be determined. Gas bubbles in the liquid flow stream may interfere significantly with vortex formation and lead to poor flow measurement. Mechanical vibration of or near the instrument may also affect vortex generation and measurement, such as vibrations from pumps and electrical noise from power relays, solenoid valves, or other factory equipment.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.17

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.17

Vortex flowmeters need to be mounted in specific orientations and the fluid flow pattern prior to the vortex meter must be straight with minimal turbulence created by other devices and typically require significant lengths of straight tubing before and after the flowmeter to ensure that the fluid flow is not affected by elbows, valves, or other components. Ultrasonic Flowmeters. Ultrasonic flowmeters detect flow by transmitting sound waves through a flowing fluid stream. The length of time for sound to travel through the moving fluid is proportional to the flow rate. Typically, an ultrasonic transmitter and receiver are mounted onto the exterior of the tubing and sound waves are transmitted from one end and are received at the other end. The time required for travel from one end to the other varies with the fluid flow and characteristics such as specific gravity—the time difference between the different flow ranges is generally a fraction of a second. Some ultrasonic flowmeters use a Doppler or transit time effect to measure fluid velocity. Gas bubbles in the liquid flow stream interfere with sound wave transmission and detection, thus affecting flow measurement. Some flowmeters will utilize electronic signal dampening techniques to mask the effects of bubbles; however, the response time and accuracy typically are reduced. Differential Pressure (DP) Flowmeters and Controllers. The accurate control of liquid flow is critical for attaining defect-free process yields in semiconductor wafer-processing tools. To maintain the high-purity levels of the process fluid, a flow measurement and control technology must not add particles or other contaminants to the fluid stream. For example, particles may cause defects for wet etch applications where the control of hydrofluoric acid (HF) flow is critical. Wet cleaning and ondemand chemical blending applications requiring accurate control must also use devices that generate as few particles as possible (Fig. 29.17). To meet the requirements for a “particle-free” flow measurement and controlling device, some fundamental design rules should be followed: • The flow measurement technology should contain no moving parts. • The control valve technology should minimize the movement of the wetted valve parts. • The amount of “dead-volume” should be minimized throughout the instrument. To meet the needs of a flow measurement technology with no moving parts, a DP-based flow measurement technology is used. Since DP technology calculates flow by measuring the pressure drop across an orifice region, there are no moving parts in the fluid stream. Pressure is detected prior to the orifice region and after the orifice. The square root of the difference in pressure, or DP, is proportional to the fluid flow rate (Fig. 29.18).

FIGURE 29.17 DP flowmeters to measure flow rates from 5 mL/min to 120 L/min of high-purity chemicals and slurries. (Courtesy of Entegris, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.18

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.18

GASES AND CHEMICALS

Outlet pressure sensor, P2

Inlet pressure sensor, P1 Orifice region Fluid flow

Fluid flow Flow ∝ k (P1 − P2)

FIGURE 29.18 DP is proportional to fluid flow rate. (Courtesy of Entegris, Inc.)

In common practice, a DP flowmeter for the semiconductor industry is constructed with PTFE and PFA materials. The actual pressure loss through the device is engineered to be low, typically 3 psig at the flowmeter nominal flow rate. The flow measurement is easily corrected for changes in fluid viscosity and specific gravity and is generally unaffected by bubbles in the fluid steam. A flow controller device (Fig. 29.19) typically consists of three main components—a flow measurement module, a control valve module, and an electronic controller module. Microprocessor-based electronics link the measurement and control elements; the user’s set point is compared to the measured flow rate, and by using standard electronic control techniques, the valve position is adjusted accordingly. 29.6.3 Level Measurement Liquid level measurement is used throughout the semiconductor industry for large bulk chemical storage tanks to small wet bench chemical tanks used for wafer processing. A number of different technologies exist for liquid level measurement. The available technologies include optical, floats, capacitance, ultrasonic, and pressure measurement. Levels may be measured by using pressure transmitters, whereby the fluid level is a function of the hydrostatic pressure produced by a column of liquid at a given height. The liquid level is obtained by knowing the liquid density and the liquid hydrostatic pressure. In addition to using the head pressure to compute the level, another common method of level measurement is the use of noncontact

FIGURE 29.19 A flow controller for controlling fluid flow of high-purity chemicals and slurries. (Courtesy of Entegris, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.19

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.19

capacitance sensors. These sensors may be mounted directly on the outer wall of the tank or onto a sight tube alongside the tank. Special considerations are necessary when choosing liquid level measurement for the semiconductor industry. It can be challenging to source instruments for semiconductor liquids that are highly corrosive, opaque, nonconductive, or have a tendency to coat material surfaces.

29.7 PROCESS CONTROL APPLICATIONS There are many applications for liquid measurement and control components in the semiconductor industry. Existing manufacturing tools may be upgraded with measurement and control equipment to improve the performance of the tool, typically enabling process improvements to current standards. Field retrofits may allow a tool user to extend the life of a multimillion dollar wafer processing tool by investing in measurement and control components for a fraction of the cost of a new tool. 29.7.1 Chemical Blending Application Many semiconductor manufacturers will blend or dilute chemicals on-site. It is extremely important that chemicals are blended properly with high precision. Chemical blending may occur in the facility bulk chemical distribution area, at the chemical dock, at off-site chemical manufacturing facilities, or within the wafer processing tools at the point of use. Chemical blending, for example, may be accomplished by using two or more liquid flow controllers installed in parallel. For blending applications, each flow controller is supplied pressurized liquid and each receives a user-generated control set-point signal. Two, three, or more chemicals may be blended simultaneously using this method. In contrast to procuring chemicals in a multitude of concentration, the advantages of chemical blending using flow controllers include: • • • •

Chemicals may be purchased and managed in bulk form Infinite concentrations may be blended on-site Less retention time for blended chemicals that destabilize quickly Eliminates the need for several bulk containment vessels for the various blends

For applications requiring critical blends with high accuracy of the resulting concentration, inline flow controllers may be used with a small intermediate tank and a concentration analyzer. The fluid volume within the intermediate tank is constantly circulated while the concentration analyzer commands the flow controllers to provide the correct flow of chemicals. The intermediate tank system then serves as a constant reservoir of properly blended chemicals. 29.7.2 Flow Control Application for Wafer Manufacturing Tools Using Slurry One of the most demanding liquid flow applications for the semiconductor industry is the measurement and control of chemical mechanical polishing (CMP) slurry. Oxide slurries are typically composed of 2 to 10 percent solids suspended by means of chemical dispersants, surfactants, pH extremes, and physical agitation. The solids in some slurries have a propensity to clog fluid handling components, so some flow measurement and control technologies are not desirable for use with some slurries. It is important to use devices that offer compatible materials of construction and nonintrusive designs. CMP slurry liquids are often corrosive and should only be in contact with compatible materials such as high-purity fluoropolymers. Flow measurement and control devices for slurry applications are typically installed in cabinets where corrosive chemical spills are expected. Therefore, resistant splashproof-rated instrument enclosures are necessary.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.20

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES 29.20

GASES AND CHEMICALS

Rotameters, paddlewheels, ultrasonic, and vortex flowmeters are susceptible to flow errors and intermittent operation when used with liquids containing bubbles. Many CMP slurries contain hydrogen peroxide, ammonium hydroxide, and other chemicals that generate bubbles during decomposition. Measurement and control products using DP are typically not susceptible to these issues. Moving parts can generate contamination particles and provide interior cavities for slurry agglomeration to occur, sometimes to the extent of clogging the device. It is also important that all devices in the slurry flow path are flow-through designs with no dead ends. Dead ends and eddies cause slurry to settle and agglomerate into larger particles. Under adverse conditions, the suspended solids in CMP slurries can agglomerate into larger solids, risking wafer defects due to scratches on the wafer surface. The slurry particle size for optimum planarization is typically 0.1 to 0.5 µm. When slurry particles inadvertently agglomerate to larger sizes, scratches can occur on the wafer surface as a result of the CMP process. Slurry solids are more likely to agglomerate into large particles because of system upsets, exposure to moving parts, operation under non-steady-state conditions, exposure to dead ends where solids can settle, system start-up, and pilot plants using slurry pumped from poorly mixed drums. CMP systems have historically utilized peristaltic pumps to deliver slurries to the point of use. In most cases, the flow rate of slurry to the polishing system is not directly measured as it is pumped; only the pump rotation speed is regulated. Fluctuations of the slurry flow occur due to changes in the supply pressure and the gradual deterioration of the peristaltic pump flexible tubing. Too little slurry flow may lead to damaged wafers due to an inadequate slurry supply to the CMP process and excess slurry flow is wasteful, burdening the waste treatment facility. The measurement and control of the slurry flow rate allows the end-user to optimize the slurry flow for each point of use. By retrofitting a pumping system with a flow measurement device, the system becomes a closed-loop flow control system, allowing the user to maintain a constant flow rate at a desired set-point by increasing or decreasing the pumping speed of the peristaltic pump. Fluctuations of the slurry flow occur due to changes in the supply pressure, the gradual deterioration of the peristaltic pump flexible tubing, and other factors. In some cases, the entire pumping system may be replaced with flow controllers using an integrated flowmeter and control valve. Implementing a closed-loop flow control system onto a CMP process tool has the following advantages: • • • • • • •

Eliminates the need for pump calibration Reduces the maintenance needed, allowing greater tool uptime Maintains a constant flow of slurry to the polishing pad Optimizes the slurry flow for each process step Reduces overall slurry consumption Monitors and alarms for low- or no-flow conditions Minimizes slurry and chemical waste burden on facility treatment systems

29.7.3 High-Purity DI Water Application Semiconductor wafer manufacturing facilities use a number of unit operations to create high-purity DI water on-site. Once the DI water has been created, it is distributed throughout the fab to different locations at different pressures. Due to the complexity of the DI process and the DI water distribution process, the liquid pressure should be measured at many different points to verify unit operations are functioning properly. Many DI systems use fluid-filled pressure measurement instrumentation that typically uses a metallic pressure sensor in contact with a stationary fill fluid. The fill fluid is in contact with a flexible seal (or isolation membrane) that separates it from the process fluid. As mentioned earlier, fluidfilled pressure measurement devices have a number of disadvantages for ultrahigh purity applications. A seal leakage causes instantaneous contamination when the fill fluid enters the process stream, and continuous contamination as the process fluid comes into contact with the metallic pressure sensor.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.21

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

29.21

Consequently, ions are introduced to the process stream. Accuracy can be affected by too much or too little fill fluid or bubbles in the fill fluid pocket that lead to errant pressure measurement. Additionally, the unit requires periodic maintenance potentially leading to downtime.

29.8 CONCLUSIONS Fluid handling components used to protect, transport, measure, and control liquid chemicals must maintain the integrity of high-purity chemicals and slurries used in the semiconductor industry. The management and handling of corrosive, high-purity liquid chemicals must be performed with fluid handling components constructed with high-purity fluoropolymers. Measurement and control equipment used for chemicals and slurries should be designed for high reliability and low contamination potential. The need for increased chemical purity, factory automation, and more complex chemical processes will continue to place new demands on fluid handling components used within the semiconductor industry.

FURTHER READING Liptak, B. G., Instrument Engineers Handbook, 3rd ed. Chilton, Radnor, PA, 1995. Miller, R. W., Flow Measurement Engineering Handbook, 2d ed. McGraw-Hill, New York, 1989. Spitzer, D. W., Flow Measurement Practical Guides for Measurement and Control, Instrument Society of America, Research Triangle Park, NC, 1990, 1991.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH29.qxd

04/04/2005

20:58

Page 29.22

FLUID HANDLING COMPONENTS FOR HIGH-PURITY LIQUID CHEMICALS AND SLURRIES

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 30

FUNDAMENTALS OF ULTRAPURE WATER David J. Albrecht Entegris, Inc. Minneapolis, Minnesota

30.1 INTRODUCTION As the technologies available for water treatment have developed, the specifications for ultrapure deionized (UDI) water have evolved as well. UDI water is also referred to as ultrapure water (UPW). Several industries require very strict UPW standards, including pharmaceutical, medical (water for injection), chemical manufacturing, nuclear, and semiconductor. In terms of ionic contaminants, semiconductor grade water typically has stricter standards than any other industry (Table 30.1). The standards are so stringent, some are beyond current analytical detection limits.

30.2 UNIT OPERATIONS FOR UPW SYSTEMS There are a number of unit operations necessary to generate UPW from the initial feedwater. Some of the unit operations are used by nearly every fab, some are dependent on the feedwater characteristics and some are optional depending on user preferences. The stages for manufacturing UPW may be divided into three categories: • Pretreatment • Primary treatment • Final treatment, polishing, and distribution Figures 30.1 and 30.2 illustrate two generalized semiconductor grade UPW treatment systems.

30.3 INITIAL FEEDWATER Semiconductor grade UPW is typically generated from local municipal water that is treated water from available ground or surface water sources. Surface water sources (lakes, rivers) tend to have greater organic, chlorinated by-products, and ammonia content but lower ionic constituents.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

30.1

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.2

FUNDAMENTALS OF ULTRAPURE WATER 30.2

GASES AND CHEMICALS

TABLE 30.1 UPW Standards for Semiconductor Water from SEMI F63-07011–4 Parameter Resistivity online at 25°C (MΩ-cm) TOC online (ppb) Dissolved oxygen online (ppb) Online Particles/L (micron range) 0.05 – 0.1 0.1 – 0.2 0.2 – 0.3 0.3 – 0.5 >0.5 Bacteria (CFU/L) 1 L Sample Silica Silica—total (ppb) Silica—dissolved (ppb as SiO2)

Range of performance

Ions and metals (ppb)

Range of performance

17.9–18.2 1–5 0.5–20

Ammonium Bromide Chloride Fluoride Nitrate Nitrite Phosphate Sulphate Aluminum Barium Boron Calcium Chromium Copper Iron Lead Lithium Magnesium Manganese Nickel Potassium Sodium Strontium Zinc

0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–20 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1 0.02–0.1

100–1000 50–500 20–100 10–50 0–4 0–5 0.5–3 0.2–1

Groundwater sources (wells) tend to have greater ionic constituents, but lower organic and ammonia content. The feedwater characteristics determine the pretreatment steps necessary. The goal for the pretreatment processing stage is to make the initial feedwater ready for processing by the primary treatment steps. If the water available for primary treatment is not properly pretreated, it can lead to fouling, scaling, or pass through for the primary treatment components. The consequences of which can lead to final UPW that does not meet specifications, increased time and expense for primary treatment cleaning and maintenance and/or capital expense in the form of increased equipment and component replacement. For the water to be ready for primary treatment, it must have appropriate characteristics in terms of scaling contributors (including CaCO3, CaSO4, silica), suspended solids, dissolved organics, oxidizable metals such as Fe and Mn, dissolved gases, and less common items such as boron, silicates, and ammonia.

30.3.1 Scaling Contributors Feedwater can contain ionic constituents such as CaCO3, CaSO4, silica, and other items that have limited solubility in water. If, for example, CaCO3 is available in the feedwater at 30 percent of its solubility limit at a given pH level and if the water is concentrated with reverse osmosis (RO) or similar unit operations 4×, then the CaCO3 would be expected to reach its solubility limit and a portion of it would precipitate out during the concentration process. The precipitated ionic material can form difficult to dissolve crystals that can coat the interior of equipment, causing limited equipment life, increasing maintenance and leading to poor downstream water quality. Common scalants include calcium carbonate (CaCO3), calcium sulfate (CaSO4), and silica (SiO2); although other less common scalants exist depending on the water source. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.3

FUNDAMENTALS OF ULTRAPURE WATER FUNDAMENTALS OF ULTRAPURE WATER Cationic polymer Lime

Al2(SO4)3 or Fe2(SO4)2

City

Plant

NH3 Cl2

Acid

Sand

Multi media

Filtration

Filtration

Feed water Clarifier

Raw water

Scale inhibitor

Sulfite RO storage Storage

RO

Reverse osmosis

RO

Reverse osmosis

30.3

≥5 µ

Heat

Filtration

Heat exchanger

Deges

UV

MB

UV

≥1 µ

Vacuum degesification

TOC reduction UV irradiation

Primary ion exchange mixed beds

Bacterial inactivation UV irradiation

Filtration

N2 UV

≥1 µ

MB

UV

Bacterial inactivation UV irradiation

Filtration

Polishing ion exchange mixed beds

TOC reduction UV irradiation

≥ 0.02 µ

DI storage

Loop

Final filtration

Ozone

Manufacturing

FIGURE 30.1 Schematic of a typical ultrapure water system.2 (Source: Guidelines for Ultrapure Water used in Semiconductor Processing, SEMI F63-0701, 2001)

Methods to address scaling include: • Processing the feedwater to a lower concentration so the solubility limit is not achieved • The use of polymeric antiscalants that inhibit crystalline scale formation and allow the ionic material to surpass the solubility limit without significant precipitation • pH adjustment increases the solubility limit of some scalants and can change the concentration of some ionic constituents. For example, lower pH causes some dissolved CO2 to gas off, decreasing the amount of it available to form CaCO3 during the concentration stages • If none of the aforementioned steps are sufficient, the prior removal of the scalants with ionexchange or similar unit operations may be necessary Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.4

FUNDAMENTALS OF ULTRAPURE WATER 30.4

GASES AND CHEMICALS DI water from storage City water

HCI SHMP NaOCI

Sand bed

Heat exchanger

Carbon bed

Static mixer

RO prefilters

5 µm

1 µm Two-stage RO system 0:2 array

Mixed bed A Mixed bed B

Filter (1 µm)

Degasifier

3000-gal storage

3000-gal storage

Return

FIGURE 30.2 Consulting.)

(0.2 µm)

Polisher B

Final filter

Post filter Points of use Filter Filter (0.1 µm) (0.1 µm)

Polisher A

UV sterilizer

(0.1 µm)

Supply

A typical high-purity water production system.1 (Courtesy of Dr. T. H. Meltzer, Capitola

30.3.2 Suspended Solids Suspended solids in the form of organics, microorganism waste, organic and inorganic particles, or similar sources can be present in feedwater sources, more often from surface water that can be affected by seasonal factors. These solids must be removed to keep downstream processes from fouling. Typically several levels of treatment in series are necessary to remove suspended solids in a costeffective manner. This may include biotreatment, clarification (coagulation and flocculation), media filtration (sand filters), and surface filters (bag and cartridge filters). Additional contributors to suspended solids can be microorganisms that can collect and grow in the water treatment equipment. Regular dosing with sanitizers such as chlorine is necessary depending on the unit operations in use. 30.3.3 Dissolved Organics Some organic constituents in the feedwater can be suspended, and some can be dissolved, such as organic acids and urea. Organic acids can cause issues with downstream processes and can act as nutrients for microorganism growth. Removal of organics can be achieved with activated carbon, oxidation, and media filtration and other unit operations. 30.3.4 Oxidizable Metals Some metals dissolved in water are soluble in one oxidation state and less soluble in another. For example, ferrous iron Fe2+ is relatively soluble. Contact with air or other oxidizing sources causes its

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.5

FUNDAMENTALS OF ULTRAPURE WATER FUNDAMENTALS OF ULTRAPURE WATER

30.5

valence state to change to ferric iron Fe3+ that is much less soluble and precipitates out onto downstream processes. The same is true of manganese, although it is less commonly found in feedwaters than iron. As noted during the scaling discussion in Sec. 30.3.1, precipitation can affect downstream processes and increase capital and maintenance costs. An effective way to remove oxidizable metals is to purposely increase the valence state using chlorine, dissolved air, or other oxidizing steps and then remove the precipitated metals with clarification or media (sand) filtration. It is not uncommon to achieve both the oxidation and media filtration steps during the same unit operation by using manganese greensand that both oxidizes the metals and provides media filtration for their removal. Manganese greensand is typically used after suspended solids removal so that the media are not also fouled with organics.

30.3.5 Dissolved Gases The primary specification for semiconductor UPW is the 17.9 to 18.2 MΩ-cm resistivity requirement. Dissolved gases such as oxygen, carbon dioxide, and ammonia affect resistivity and need to be removed from the fluid stream. They are most often removed through pH adjustment (3.6), reverse osmosis (Secs. 30.5.1 and 30.5.2), and vacuum degasification (Sec. 30.5.4).

30.3.6 Less Common Items Ammonia, silicates, and boron are feedwater constituents that can often pass through both primary treatment and pretreatment and negatively affect downstream water quality. These may be removed during pH elevated second pass reverse osmosis (high-efficiency RO) as discussed in Sec. 30.7.1.

30.4 PRETREATMENT The goal for the pretreatment processing stage is to make the initial feedwater ready for processing by the primary treatment steps. It is important to install pretreatment equipment to address scaling, suspended solids, microorganism growth, dissolved organics, oxidizable metals, and other common factors. Occasionally an initial feedwater source is nearly ready for primary UPW processing, and only limited pretreatment steps are necessary. Other feedwaters require significant unit operations to prepare for primary treatment. Common pretreatment unit operations include: • • • • • • •

Chemical addition Biotreatment Coagulation and flocculation Media filtration Activated carbon Ion exchange Surface filtration

30.4.1 Chemical Addition Chemical addition through the pretreatment, primary, and final stages of UPW generation is common. The water may be pH adjusted to either increase or decrease the solubility of dissolved solids, to increase or decrease bioactivity, to keep ionic constituents close to the solubility level from precipitating and

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.6

FUNDAMENTALS OF ULTRAPURE WATER 30.6

GASES AND CHEMICALS

other effects. Additional chemicals added may include polymeric antiscalants or dispersants, chelating agents, sanitizers, oxidizing chemicals, and reducing agents (for oxidant removal). Many of the unit operations mentioned subsequently require chemical addition to function to peak capacity. 30.4.2 Biotreatment Some surface water can contain significant microorganisms and organic material such as tannins from vegetation, and the like. This organic material can exceed the suspended solids quotient typically removable by media and surface filtration. If so, the use of biotreatment is a good initial step for reducing the suspended solids load. Biotreatment takes many forms, but its basic configuration allows slow moving water to pass through large containers with selected microorganisms that use organic contaminants as nutrients. The selected microorganisms are larger than the feedwater suspended solids, and thus are easier to remove with downstream clarification, screen filters, press filters, and media filtration. 30.4.3 Clarification Clarification is typically a multistep process to reduce suspended solids, organics, and oxidizable metals. It often uses coagulation and flocculation steps and is sometimes referred to by these names. First, coagulants, pH adjustment chemicals, or oxidants are added to the feedwater to cause suspended solids to generate from dissolved constituents or to cause existing suspended solids to agglomerate or grow. The enlarged suspended solids (floc) have a different specific gravity than water and may be removed by means of baffle-assisted settling tanks in the later stages of clarification. Clarification can remove a high percentage of suspended solids at a relatively low cost per unit volume, but is not completely effective and typically requires additional unit operations. 30.4.4 Media Filtration Media filters are used to remove suspended solids from the feed stream. Earlier water treatment stages are sometimes used to create suspended solids that may be removed during this stage or the clarification stage, such as biotreatment or iron oxidation. The media within the filtration tank (or tanks) are typically layered with larger coarse particles initially and smaller fine particles later, to remove larger particles first. One medium used in this type of filtration is sand, which may remove particles as small as 10 to 20 µm in size, although it is most effective at removal of larger particles. Other media exist such as diatomaceous earth, which can filter particles up to 5 µm and lower in size, but requires more frequent replacement. A typical media filter is sized to not exceed 5 gal/min/ft2 of bed area. A maintenance consideration is that media filters must be backflushed periodically to remove particulates. Additionally, media filters require periodic sanitization to decrease bacterial growth. As noted in Sec. 30.3.4, dissolved oxidizable metals such as iron can be oxidized, precipitated, and removed in one step using manganese greensand filtration. Manganese greensand is typically used after suspended solids removal so the media does not also become fouled with organics. 30.4.5 Activated Carbon Activated carbon (AC) is widely used for its adsorptive qualities and is used in large pressure vessels similar to media filtration. AC adsorbs many dissolved organics and eliminates chlorine and other oxidants. If chlorine addition is used as a pretreatment oxidation step, it is often removed prior to primary treatment using AC. Because AC eliminates chlorine, it can become a breeding ground for bacteria and other water-borne microbial species. The AC must be sanitized or changed periodically

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.7

FUNDAMENTALS OF ULTRAPURE WATER FUNDAMENTALS OF ULTRAPURE WATER

30.7

in order to avoid bacterial growth. Also, after long-term use many of the adsorption sites can become used, requiring reactivation by a controlled heat process or change out. 30.4.6 Ion Exchange There are three primary means to remove ionic components from feedwater—deionization, reverse osmosis, and distillation. For large-scale semiconductor water treatment processes, distillation is typically considered to have high energy costs. Reverse osmosis is discussed in Sec. 30.5.1. Deionization via ion exchange is often used as a pretreatment for reverse osmosis. Ion-exchange systems consist of tanks containing small beads of synthetic resin (Fig. 30.3). The beads are treated to selectively adsorb either cations or anions and release (exchange) counter ions. The ion-exchange process continues until all or most of the sites are filled, at which point the resin is exhausted and must be chemically regenerated. Most ion-exchange systems use both anionic and cationic resins in series. The regenerant solution is typically either acid or base, depending on whether the resin is established to remove cations or anions. A home water softener is a simple example of ion exchange. The advantages of ion exchange are that it is an established, well-known, predictable technology. It is not high-pressure driven, as is reverse osmosis, and this has lower electrical costs. Also, it is sometimes a necessary unit operation to remove potential scalants such as calcium. Disadvantages of ion exchange: • Can become a breeding ground for bacteria and requires periodic sanitization • The regenerant chemical use and disposal can be costly • Iron and other feedwater constituents can block adsorbing sites, leading to more frequent resin replacement

30.4.7 Surface Filtration Media filters trap suspended solids in gradated sand or similar materials. Sand filtration may remove particles as small as 10 to 20 µm in size, although it is most effective at the removal of larger particles.

FIGURE 30.3 Representation of an ion-exchange resin bead.5 (Source: Pure Water Handbook, GE Water, 1997)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.8

FUNDAMENTALS OF ULTRAPURE WATER 30.8

GASES AND CHEMICALS

FIGURE 30.4 Depth filters. (Courtesy of GE Infrastructure Water & Process Technologies.)

FIGURE 30.5 Pleated membrane filters. (Courtesy of GE Infrastructure Water & Process Technologies.)

Surface filters do not use three-dimensional media to trap and remove solids, but instead have a surface, or layers of surface area, that remove particles based on the porosity of the filtration material. Three common types of filters include: • Bag filters that are typically nominally rated between 1 to 50 µm, do allow some pass through of smaller solids, but are inexpensive, can retain large amounts of solids and are easy to maintain. • Depth filters are constructed with a thin (1 to 4 cm) wall of filtration media (Fig. 30.4). The filtration media is typically constructed of cotton, cellulose, blown microfibers of polymers such as polypropylene, or similar materials. The water passes through the filtration matrix that commonly has lower density on the outside and greater on the inside allowing “graded density” that traps coarser particles toward the outside of the filter. Depth filters are commonly available with filtration ratings 0.5 to 25 µm and are moderately expensive. • Membrane filters use a thin porous membrane to trap particles against its surface (Fig. 30.5). They are typically rated 0.05 to 1.0 µm, can remove a high percentage of microorganisms, and are considered to have “absolute” rather than nominal filtration ratings. Membrane surface filters are used as final polishing in the pretreatment process and require significant particulate removal before their use. They are relatively expensive and without preremoval of most particles they can become plugged prematurely and require more frequent replacement. It is common to use bag, depth, and membrane filters in series to obtain 0.05 to 1.0 µm particlefree water with greatest effect and prepare the water for the primary treatment.

30.5 PRIMARY TREATMENT The goal for the primary treatment stage is to take pretreated water that is ready for primary treatment unit operations and generate UPW that is within specifications. The 17.9 to 18.2 resistivity specification is generally the most difficult to achieve.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.9

FUNDAMENTALS OF ULTRAPURE WATER FUNDAMENTALS OF ULTRAPURE WATER

30.9

Common primary treatment unit operations include: • • • • •

Reverse osmosis Two-pass reverse osmosis Continuous elecrodeionization Degasification Ozone or UV sterilization

30.5.1 Reverse Osmosis Reverse osmosis is the workhorse of most semiconductor UPW operations. RO is configured in crossflow spiral wound membranes (Fig. 30.6). Crossflow spiral wound membrane configurations are also used for nanofiltration for softening and other applications, and ultrafiltration and microfiltration for microorganisms and larger organics removal. In crossflow filtration, the primary direction of flow is parallel to the filtration membrane surface, with a small portion of the pressurized feed passing through the membrane. In this way, the rejected or filtered constituents do not blind or plug the membrane pores very rapidly as they would during surface filtration. The tangential flow is a self-cleaning mechanism, and sweeps the surface clean. Membrane blinding or plugging occurs slowly and reaches a stasis condition. It is important that the feedwater is adequately prefiltered so that the membrane elements do not foul early. The majority of the liquid flow is across the membrane surface, and the filtered flow is over a relatively low per membrane surface area. An example crossflow membrane spiral wound element may have 40 ft2 (3.7 m2) of surface area, with a tangential crossflow of 20 gal/min (76 L/min) and a filtration or “permeate” rate of 2 gal/min (8 L/min) or a flux of 0.05 gal/min/ft2 of membrane surface area (2.2 L/min/m2). So for a single crossflow membrane element, the tangential crossflow is approximately 10 times the filtered permeate flow. High-performing RO membrane systems can remove 99 to 99.9 percent of ionic constituents (salts), 99 percent or higher of dissolved organic constituents—200 molecular weight or higher, and lower percentages of smaller organics and lightly ionized constituents (Fig. 30.7). The operating pressure required for RO processes is typically 150 to 250 psig (10 to17 bar), typically supplied by multistage centrifugal pumps. By configuring many crossflow membrane elements in parallel and series, a high recovery rate may be obtained. An example application may have feedwater of 100 gal/min (378 L/min) with total

olution

Perforated central tube

s Feed

ate Perme ntrate Conce Permeate collection material Membrane Feed channel spacer Outer wrap FIGURE 30.6 Technologies.)

A spiral wound membrane element. (Courtesy of GE Infrastructure Water & Process

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.10

FUNDAMENTALS OF ULTRAPURE WATER 30.10

GASES AND CHEMICALS

Pressure 200 MW 500 MW

1000 MW

350 MW

Solution flow 100 MW

50 MW 200 MW

300 MW

FIGURE 30.7

Pure water boundary layer Membrane surface Membrane support layer

300 MW

Reverse osmosis. (Courtesy of GE Infrastructure Water & Process Technologies.)

dissolved solids (TDS), or dissolved ionic constituents, of 250 mg/L and 500 µS/cm conductivity, or 2000 Ω-cm resistivity. In this example the feedwater requires 50 membrane elements, filtered or “permeate” flow of 80 gal/min (303 L/min), and final rejected crossflow “concentrate” of 20 gal/min (78 L/min), for an overall 80 percent recovery rate. At 99 percent TDS rejection, the permeate would contain approximately 2.5 mg/L TDS with conductivity 5 µS/cm and resistivity 200,000 Ω-cm. The concentrate containing approximately 1250 mg/L TDS would typically be rejected to sewer water. Depending on the feedwater characteristics in terms of organic foulants and scalants, the membrane system may require chemical cleaning from 3 to 12 times per year, and membrane element replacement every 2 to 5 years. Higher-quality RO feedwater, from better pretreatment equipment and optimal water sources, generally leads to longer membrane life and less frequent cleanings. As noted in Sec. 30.4.1, the treatment of the RO feedwater often requires the addition of chemicals such as acids and bases for pH adjustment, antiscalants or dispersants, chelating agents, sanitizers, oxidizing chemicals, and reducing agents (for oxidization removal). Additionally, the higher rejection RO elements are manufactured with polyamide membranes that are chlorine intolerant, thus requiring chlorine removal prior to RO use. 30.5.2 Two-Pass Reverse Osmosis Following the aforementioned example, the RO feedwater contains 500 mg/L ionic constituents, and the permeate contains 2.5 mg/L TDS ionic constituents with conductivity 5 µS/cm and resistivity 200,000 Ω-cm. RO membranes pass dissolved carbon dioxide gas to a greater degree than other species. The CO2 gas forms carbonic acid on reaching equilibrium, thus the pH of the permeate is typically lower than the feedwater. The end goal of the semiconductor ultrapure water specification is 17.9 to 18.2 MΩ-cm resistivity, equivalent to 0.055 µS/cm conductivity, or about 0.025 mg/L TDS. The permeate from first-pass RO is commonly fed to a second-pass RO system for further purification. For most two-pass RO systems, the second-pass concentrate is recycled for use as the firstpass RO feedwater, increasing water use efficiency. If the second-pass RO is also capable of removing 99 percent of the remaining ionic constituents, then the 17.9 to 18.2 MΩ-cm resistivity specification is reached. However, the rejection of ionic

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.11

FUNDAMENTALS OF ULTRAPURE WATER FUNDAMENTALS OF ULTRAPURE WATER

30.11

constituents with the second-pass RO typically is not quite as high due to lowered pH, dissolved gases that are not easily rejected by RO, low molecular weight acids that contribute to conductivity, and other ionic species in the first-pass RO permeate that have lower rejection due to reduced ionization. There are several ways to raise second-pass RO rejection or to remove ionic constituents with other unit operations. These include continuous electrodeionization (Sec. 30.5.3), ion exchange Sec. 30.4.6, vacuum degasification (Sec. 30.5.4), and significant pH adjustment to obtain a higher rejection of specific components during the second-pass RO (high-efficiency RO, 30.7.2). 30.5.3 Continuous Electrodeionization Continuous Electrodeionization (CEDI) is a trend in UPW processing (Fig. 30.8) that has been gaining market share for the late primary treatment and polishing stages. The process stream is fed through mixed cation and anion resins for the removal of ionized organics, carbon dioxide (CO2), and ions. A dc electrical current is applied across the CEDI stack that consists of alternating diluting and concentration chambers. The ions are removed from the process system by the standard ion-exchange reactions that take place in a conventional resin bed. However, in the electric field within the stack, the ions will migrate from bead to bead through the resin bed toward their respective electrodes where they are removed in the concentrate stream. The applied current continuously regenerates the ion-exchange resin. CEDI units typically require higher capital and ongoing electrical costs than conventional ionexchange units. However, the CEDI resin is continuously regenerated unlike conventional ionexchange where regeneration requires both chemicals and downtime. Since the fab chemical waste

Anion permeable membrane Cation permeable membrane

Feed Cl– Na+ Cation permeable membrane

Cl–

Na+

Anion exchanges

Anion permeable membrane

Cation exchanges Na+

Na+ (+)

(–) Cl–

Cl–

H+

OH– H+ OH–

OH–

H+ H+

Concentrating compartment

Diluting compartment

Concentrating compartment

Concentrate

Product

Concentrate

FIGURE 30.8 Principle of continuous electrodeionization.1 (Source: High Purity Water Preparation, Tall Oaks Publishing, Inc.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.12

FUNDAMENTALS OF ULTRAPURE WATER 30.12

GASES AND CHEMICALS

treatment is a significant issue, CEDI is generally advantageous compared to standard ion-exchange technology. Also, since the resin does not saturate, the ion extraction levels from CEDI are considered to be more consistent. 30.5.4 Vacuum Degasification The removal of dissolved oxygen, carbon dioxide, and other gases is a necessary treatment step. These constituents add to conductivity and must be removed to meet the SEMI-UPW standard. Typically degasification takes place after first- or second-pass RO and often requires a pH adjustment to cause dissolved gases to approach the saturation point. Vacuum degasifiers are most often in the form of vacuum towers or membrane contactors (Fig. 30.9). Vacuum towers consist of baffles where water is sprayed into the top and broken into a thin film as it flows through the tower. The process creates a large contact area between the gas and the water. Inside the tower a vacuum is drawn, creating a driving force to remove dissolved gases from the water. Membrane contactor vacuum degasifiers operate at low pressures and use hydrophobic membranes with pore sizes in the range of 0.03 µm that allow the passage of gases but retain water. A vacuum or sweep gas is established on the opposite side of the membrane to lower partial pressure for the removed species, increasing efficiency. A number of membrane elements in series and parallel are typically arranged to obtain maximum degasification effects. Vacuum degasification with membrane contractor vacuum degasifiers typically has greater capital cost than vacuum towers, but is capable of removing dissolved gases to lower levels than towers. 30.5.5 Ozone or UV Sterilization

Vacuum and/or sweep gas

Liquid

Liquid

After first- and second-pass RO ion exchange and degasification, there can still be small amounts of total organic carbon (TOC) and microorganisms in the water. Microorganisms are a particular concern because they can multiply in the postprimary treatment recirculation loops and therefore must be eliminated.

Gas/liquid contact area FIGURE 30.9 A membrane contactor vacuum degasifier.6 (Source: How to Meet Today’s Dissolved Oxygen Specification with Degasification Membranes, Ultrapure Water, March 2003)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.13

FUNDAMENTALS OF ULTRAPURE WATER FUNDAMENTALS OF ULTRAPURE WATER

30.13

Oxidation with ozone or ultraviolet (UV) light sterilization is very commonly used as the last primary treatment step to address TOC and microorganisms. Ozone is an extremely reactive oxidant, kills microorganisms and can convert low levels of TOC to ionized compounds removed during the polishing stages. Ozone systems diffuse ozone bubbles into the feedwater to counter current with the liquid flow to increase the contact time. One of the disadvantages of ozone is that it adds dissolved oxygen to the feed stream that needs to be removed in later treatment steps to meet the UPW specification. Ozone gas itself is a potential safety hazard and as a powerful oxidant, it can damage equipment, particularly filtration media such as membranes, and therefore must be destructed prior to downstream unit operations. An advantage of ozone is that it is a more powerful oxidant than UV or other alternatives. UV sterilization is a standard method of reducing TOC and microorganisms. The liquid passes through channels exposed to bulbs generating UV light. UV light at 185 nm generates ozone in the liquid, while UV light at 254 nm catalyzes the destruction of dissolved ozone. Thus within the UV light portion of the fluid flow, ozone is generated, TOC reduced, microorganisms destroyed, and the ozone is destructed. The ozone destruction is key in that it protects downstream processes and reduces personal safety concerns with respect to ozone exposure.

30.6 FINAL TREATMENT, POLISHING, AND DISTRIBUTION Once UPW that meets specifications has been generated, it must be recirculated, distributed throughout the fab, and continually treated to maintain the UPW standards. Since UPW is a powerful solvent, it can be easily contaminated with ionic and organic contaminants. Thus continual polishing treatment steps are generally considered necessary so that the recirculating UPW remains within specifications. A significant potential contaminant in UPW systems is microorganism growth in lower flow areas and subsequent organic contamination when they are dislodged or destructed. To control and eliminate microorganisms and their contaminating by-products, ozonation, UV sterilization, and microfiltration are commonly in continual use on the recirculating UPW loop. Ion exchange is also sometimes used during the polishing and distribution stages depending on the water characteristics and needs. 30.6.1 Recirculating Distribution System Nearly every fab utilizes distribution systems to supply many of the ultrapure chemicals used within the cleanroom tools. This includes gases, acids and bases, and solvents, as well as UPW. The distribution systems for UPW are typically operated and maintained from the bulk chemical distribution subfab area or similar arrangement where the primary components of the distribution equipment are outside of the cleanroom and easier to maintain. The goal for distribution systems is to have pressurized UPW within the purity specification available at every tool throughout the fab. This requires adequate pressure and flow availability, the use of all fluoropolymer wetted parts, and polishing treatment systems that ensure the UPW remains within specification at all times, even though it is being constantly recirculated. Typically UPW distribution systems use a small reservoir, pumping system, and tubing that provides pressurized liquid to the cleanroom tools, point of use microfiltration, return plumbing to the pump and reservoir, backpressure control system and online instrumentation to ensure the UPW specifications are being met. The reservoir is typically necessary to maintain the pump feedwater but should have low retention time. The backpressure control on the return loop is necessary to maintain pressure and available flow to all tools, so when many tools demand flow simultaneously, UPW remains available. Figure 30.10 depicts a typical UPW fab distribution system. The pumping and tubing systems are typically manufactured with all fluoropolymer wetted parts such as perflouroalkoxy (Teflon PFA). PFA is a fully fluorinated translucent, slightly flexible polymer with a low coefficient of friction and resists stress cracking in nearly all chemicals and solvents. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.14

FUNDAMENTALS OF ULTRAPURE WATER 30.14

GASES AND CHEMICALS

Low ∆P

PHI (UPWR)

PLow (UPWS)

Tool UPWR Tool UPWS

Decreasing ∆P

Tool

Tool

Tool

PLow (UPWR)

High ∆P

PHI (UPWS)

Return Supply (s) FIGURE 30.10

A DI water fab distribution system.7

The primary characteristic for semiconductor applications, though, is that it is inert to nearly all industrial chemicals and solvents and adds significantly fewer contaminants to liquid streams than metallic tubing or other polymers. SEMI F57-0301, Provisional Specification for Polymer Components Used in Ultrapure Water and Liquid Chemical Distribution Systems, denotes the desired PFA mechanical and purity characteristics, as well as the traceability, certification, and packaging requirements of the polymer to ensure that it meets the specification.8–10 30.6.2 UV Sterilization As noted in Sec. 30.5.5, water passing through a properly operated UV light treatment system will destroy microorganisms, reduce TOC (often a by-product of microorganisms in the water) and destruct the residual ozone. 30.6.3 Microfiltration It is very important to recognize that microorganism growth in the final UPW loop is likely to occur, even though properly maintained primary treatment unit operations eliminate nearly all of them. Microfiltration in the 0.05 to 0.2 µm range is used to filter out whole microorganisms and portions

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.15

FUNDAMENTALS OF ULTRAPURE WATER FUNDAMENTALS OF ULTRAPURE WATER

30.15

of their by-products. Microfiltration may be in the form of surface filtration 30.4.7 or crossflow membrane microfiltration 30.5.1. Surface filtration has lower capital cost and greater ongoing replacement cost, while crossflow filtration has greater initial capital cost and lower ongoing costs. Most larger new fab builds use crossflow microfiltration during the polishing stages.

30.7 FUTURE TRENDS 30.7.1 High-Efficiency RO High-efficiency RO is a general term used to describe standard RO operations used at elevated pH levels that reject some dissolved species more effectively than others. RO is often the workhorse of the primary treatment stage and can typically remove 99 percent or more of dissolved ions and organics from the feed stream. However, certain species that are either smaller in molecular weight or weakly dissociated have lower RO removal rates. This includes dissolved gases, silicates, weak acids, organics, and boron. Recent studies and field installations use significant pH adjustment with caustic during second-pass RO to ionize these species and increase their rejection. For example, pH elevation will convert poorly rejected carbon dioxide gas to easily rejected carbonic acid. Dissolved carbon dioxide gas reacts with water molecules to form carbonic acid:11 CO2 + H2O → H2CO3 A consequence of pH elevation is that RO can reject a higher percentage of weakly dissociated species as noted earlier, but subsequently can reject a lower percentage of other ions. Thus pH elevation between RO stages is only recommended when problematic species cannot be removed with other unit operations. 30.7.2 Water Reuse Water use at semiconductor manufacturing facilities is intensive. A large amount of water is used to rinse and clean semiconductor wafers, and a great deal of this is fully treated UPW. In general, 1400 to 1600 gal of city water is needed to produce 1000 gal of UPW. More than 2000 gal of UPW can be used in the production of one 8-in wafer. As a point of reference, a typical 200-mm wafer fab processes 40,000 wafers per month. A large facility can use up to 3 million gal of UPW per day. This is similar to the water requirements for a city of 30,000 people. An approximate breakdown of UPW use:12 • • • •

Wet cleans: 60 percent Acid processes (etch): 20 percent Solvent processes: 10 percent Tool cleaning processes: 10 percent

Due to the high UPW usage, semiconductor facilities all over the world are facing issues dealing with both incoming water availability and wastewater treatment discharge requirements. One relatively simple way to address both incoming water volume and waste treatment issues is to reuse those portions of the fab effluent that have lower contaminant levels. A large semiconductor facility can use up to 3 million gal of UPW per day. One-third of that water is rejection from RO, ion exchange, and other UPW unit operations. Of the remainder, a significant portion is used for simple rinse operations that do not significantly add contaminants to the water when compared to the initial incoming city water feed. By redirecting a portion of the low contaminant waste streams within the fab, a significant overall water use reduction can be established. Many new fabs already utilize water reuse, and the trend is expected to continue.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH30.qxd

04/04/2005

21:00

Page 30.16

FUNDAMENTALS OF ULTRAPURE WATER 30.16

GASES AND CHEMICALS

30.7.3 Outsourcing More and more semiconductor fabs are outsourcing operations in the fab that do not affect the core competency of wafer design and manufacturing. Operations such as tool repair and upgrade, parts cleaning, cleanroom supplies, chemical delivery, security, and spare parts stocking are being contracted out to support companies more and more. For other industries, incoming water treatment has been an outsourcing option for many years. In the semiconductor industry it is becoming increasingly common to contract UPW equipment companies or local engineering firms to install and maintain the UPW equipment, and assure necessary volumes of UPW are supplied within the proper specifications. Special thanks to David Paulson of GE Water Technology for his assistance on this chapter.

REFERENCES 1. Meltzer, T. H., High Purity Water Preparation, 1997, pp. 17–22, 481, 660. 2. SEMI F63-0701, Guidelines for Ultrapure Water Used in Semiconductor Processing, 2001. 3. Owen, L., and M. Tragesser, “Fundamentals of High Purity Water Used in Microelectronic Applications,” Ultrapure Water, May/June 2001, Vol. 18, No. 5. 4. Balazs Analytical Laboratory, Ultrapure Water Monitoring Guidelines, 2000. 5. Pure Water Handbook, GE Water, 1997, p. 42. 6. Wiesler, F., “How to Meet Today’s Dissolved Oxygen Specification with Degasification Membranes,” Ultrapure Water, March 2003, p. 40, Vol. 20, No. 13. 7. David, S., and P. E. Buesser, “Part 2: Loop Configuration, Balancing, and Cost,” Ultrapure Water, December 2002, p. 25, Vol. 19, No. 10. 8. Entegris Teflon PFA Material Data Sheet 4000-1047MAX-0502. 9. Govaert, R., and A. Lueghamer, “Materials of Construction,” Ultrapure Water, December 2001, pp. 32–39. 10. SEMI F57-0301, Provisional Specification for Polymer Components Used in Ultrapure Water and Liquid Chemical Distribution Systems, 2001. 11. Dey, A., et al., “Part1: Effect of Interstage Caustic Dosing on the Silica, Boron, and Organic Removal Using Double-Pass RO,” Ultrapure Water, July/Aug 2001, pp. 52–58; Jun, L., et al., “High-Purity Water System Upgrade in Singapore Using High—Efficiency RO,” Ultrapure Water, May/June 2004, pp. 27–32, Vol. 21, No. 4. 12. Pollution Prevention Resource Exchange, Energy and Water Efficiency for Semiconductor Manufacturing, 2000.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

P

●

A

●

R

●

T

●

6

FAB YIELD, OPERATIONS, AND FACILITIES

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.2

FAB YIELD, OPERATIONS, AND FACILITIES

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.3

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 31

YIELD MANAGEMENT Bo Li Wayne Carriker Intel Corporation Hillsboro, Oregon

31.1 INTRODUCTION Semiconductor manufacturing is an established yet rapidly advancing industry. Companies are continually challenged to meet market demands by delivering increasingly sophisticated products in high volume, on time, and more cost-effectively than ever before. As Moore’s law has driven smaller feature sizes, cost-effectiveness has driven a shift to larger wafers. Together, these forces have added significantly to process development and manufacturing complexity. In addition, current market conditions require manufacturers to introduce and ramp production of new products more quickly than was attainable even a few years ago. To do this, it requires adopting entirely new approaches to yield management (YM) that not only deliver higher yields but also achieve maturity levels more quickly than ever before. Traditionally, capital expenditures for production equipment have had the highest priority, while expenditures for yield growth and assurance have been of secondary importance. In the past, yield improvement systems were not seen as value added processes and were justified based only on expected steady-state yield gains. A better metric to understand the significance of yield management evaluates the cost benefits for the engineer’s ability to detect, fix, and quickly recover (DFQR) from unexpected yield “busts.” The productivity losses resulting from these unexpected events are more costly to the fab than not meeting the planned yield growth because of the immediate impact to on-time deliveries and product performances. As it is reasonable to assume that these yield issues will occur early in a process ramp, it is even more important that they be addressed quickly to minimize the impact during this critical window. Figure 31.1 shows what a single percent of the yield loss means to the fab profitability. As shown, the impact is a function of the die revenue and of the demand for the die produced. The average sales price for a die is typically greatest at the time of introduction, and the ability of a manufacturer to meet the demand is most stressed during a factory ramp. Thus, rapidly recovering from an early yield loss is financially more important than achieving a long-term improvement in average yields. Investing in yield management is not, however, as simple as buying another tool for the fab. Yield management encompasses advanced technologies in semiconductor product design, process development, measurement, processing, and test phases for yield improvement purposes. Leading edge yield management systems need to integrate world class yield modeling and improvement practices, tools, and methodologies developed by exceptionally talented engineers, technicians, and managers from all over the world. An advanced yield management system depends on new approaches that are both broader and deeper than ever before to enable semiconductor companies to make well-informed decisions to recover from excursions as well as more rapidly achieve mature yields.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

31.3

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.4

YIELD MANAGEMENT 31.4

FAB YIELD, OPERATIONS, AND FACILITIES

Every part of a percent counts What is one percent of yield worth?* What is your average FAB yield lines your average probe yields for the whole sites? For example.......70% What is the total site die revenue? For example......$600 million Then 70% going to 71% means: 1.4% more die or: $8.4 million more profitability for every 1% gain of yield *Applies to bottom line profitability when the Fab can sell every die it makes FIGURE 31.1 What a 1 percent yield improvement means to the fab profitability.

Factory automation systems such as the manufacturing execution system (MES), process control system (PCS), and engineering analysis system (EAS), are powerful vehicles to enable a yield management system to detect and respond to yield issues correctly and rapidly. The automation system puts the fruits of the yield management system to work by enabling continuous yield learning that not only communicates changes to the manufacturing line, but also enables a real-time determination of whether or not those changes are having the desired effects. This makes it possible to identify and fix the root causes of issues promptly, and significantly shorten the yield learning process. Obviously, technology alone will not produce a world class manufacturing performance. Yield management crosses over the entire life cycle of a semiconductor product, and it requires the full commitment of engineers, technicians, and management in all areas to maximize yields in the production line. Everyone involved needs to be aware of what each 1 percent of yield means to the company and assume ownership, employing the yield management system to maximize yields and profitability. The rest of this chapter will examine yield management in greater detail, starting with a definition of the overall yield management system scope in Sec. 31.2. Next, Sec. 31.3 will examine the implementation of a yield management system, including both tools and methodologies. Section 31.4 will then discuss a model for system optimization. Finally, Sec. 31.5 will look at the future trends in yield management and conclude the chapter.

31.2 WHAT IS YIELD MANAGEMENT AND WHY IS IT IMPORTANT? Yield issues can be defined as “defects” or “faults.” Defects are defined as anything that may cause a product to fail, whereas a fault is any form of defect that induces product failure. Though the difference may appear subtle, it is significant. Inadequate process control, reliability problems, particulates, and other forms of contamination in the wafer environment are all sources of defects, and defects are ultimately the cause of all faults. However, only a fraction of all defects become faults. To contribute to fault reduction and yield improvement, a yield management philosophy must promote the detection, control, reduction, elimination, and prevention of sources of the right defects.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.5

YIELD MANAGEMENT YIELD MANAGEMENT

31.5

These defects are classified by type. While there are many types of defects, a complete classification is beyond the scope of this chapter. At a high level, the most prominent class of defects is photolithographic. Within this class, defects can be further classified as “missing pattern” or “extra pattern” defects. Missing patterns include notches, voids, and intrusion defects. Extra patterns include extensions, bridges, and protrusion defects. Beyond these, other defect types include insulator pinholes and leakage defects. To further complicate the problem of yield management, each of the many types of defects may be the result of multiple causes. These include particles, bubbles and pinholes in photoresists, and crystalline dislocations. Finally, defect densities can vary substantially with the maturity of a process or even the introduction of new tools, or modifications to existing tools, in an established manufacturing line. One of the primary functions of a yield management system is to act as the focal point for in-line defect monitoring and classification. The yield management system serves as a data hub for the storage of inspection data generated by automated wafer inspection tools and provides the tools to retrieve data for defect review and analysis. Summarized in Table 31.1 are common types of data that may be stored in a yield management system database. The yield management system can facilitate correlating data across many different axes to rapidly identify the root causes to yield issues. One of these correlations involves the partitioning of defect data across process steps to assist the user in isolating defects that are added to a wafer by a particular process sequence. A typical analysis of this sort involves collecting inspection data in the form of wafer defect maps, from two or more process steps, overlaying the wafer maps, and mathematically subtracting the positional data to identify: (1) the new defects added by each set of process steps, (2) the defects that become permanent, and (3) the defects that are removed by subsequent processing. By extending this analysis to further group the defects according to a predefined classification schema, the defect characteristics can be further used to help pinpoint the exact origin of the defects, so that permanent defects may be eliminated. In cases where the physical characteristics of the defects themselves are insufficient to identify and correct issues, spatial information may be utilized instead. Defect, bin, bitmap, and parametric data can contain unique signatures. The on-wafer location and orientation of a signature can serve as a key indicator for a process or process integration problem and help identify the defect origin. A yield management system can provide tools to easily overlay maps from multiple wafers to visualize signatures. Or, if equipped with sufficient spatial pattern analysis capability, the system may automatically analyze data for signatures and report the results to the user, allowing for faster yield learning. As noted previously, some defects are not the result of a manufacturing process in general, but of a specific tool within the manufacturing line. In these cases, a correlation between the yield and parametric data may be useful. If the device performance is sensitive to changes in specific parametric values, yield losses associated with these shifts or variances can appear across a single wafer, wafer to wafer, or lot to lot. Using known “good” and “bad” lots, tools unique to the bad lots can be identified and evaluated. They can be checked for equipment history, unusual process events, and deviations in the performance from the baseline to determine if there is an issue with the tool or with any activities being performed on the tool. TABLE 31.1

Common Data Types and Their Physical Association

Data description

Physical associations

Data type

Yield Bin Bitmap Process Parametric Defect Image WIP

Die, wafer Die, wafer Die, wafer Die, wafer, lot Die, wafer, lot Event, die, wafer Event Lot

Continuous Discrete Discrete Continuous Continuous Discrete Analog or digital Discrete

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.6

YIELD MANAGEMENT 31.6

FAB YIELD, OPERATIONS, AND FACILITIES

Finally, it is important to be able to correlate visual defects and electrical failures. The ability to overlay and map visual defects observed during processing with electrical test failures is a powerful tool for reducing the failure analysis time and increasing the failure analysis efficiency. Correlation of defect data to electrical test results can be performed to bitmap data or to bin data. It provides a method to rapidly pinpoint the locations of potential killer defects and quantify the yield impact of specific types of defects. Using analytical instruments with full wafer navigation capability, in-line inspection or bitmap information can be used to locate defects or electrical failures of interest and confirm the cause of device failures. Obviously, these types of data correlations require proper tools to analyze and manage the immense volume of process and electrical test data generated by process metrology, in-line inspection monitoring, and electrical test operations. Issues frequently encountered in immature yield management systems include, but are not limited to—(1) inaccessibility of data due to storage in separate, incompatible databases, (2) multiple extraction interfaces running under different operation environments, (3) incompatible data output formats, and (4) lack of visualization and analysis tools. When these issues require that data from different sources be manually tabulated in a spreadsheet prior to performing the analysis, the tedious and time intensive nature of this task severely limits the sophistication of analyses that may be performed. The goal of a modern yield management system is to provide fab personnel with near real-time access to all the data required to support the manufacturing process. Clearly, one of the most important areas that must be addressed is the ability to visualize the large data sets and different correlations being sought. Visualization tools should be provided to review data in common formats such as trend charts, bar charts, box plots, and wafer maps. Basic trend analysis is a time-tested method of monitoring changes in a manufacturing line. The complexity in semiconductor manufacturing is identifying the right trends that can influence the overall yield trend. With a yield management system, trend analysis can be performed on defect and yield data, bitmaps, and the like with the push of a few buttons. The data can be filtered by a multitude of criteria set by the user. When an undesirable trend is found, the yield management system can assist the user in determining what went wrong. Alternatively, when a desirable trend is found, the yield management system can assist the user in pinpointing the changes that led to the improvement.

Fab

Wafer inspection tools

Analysis lab

Images

Analytical equipment

Probe

Images

Bitmap tools

CIM

WIP tracking

Equipment tracking

Images

Process control Review stations

Images Databases

In-line SEM

Office

Datahub Software tools

FIGURE 31.2

Yield management system data flow network diagram.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.7

YIELD MANAGEMENT YIELD MANAGEMENT

31.7

Beyond providing visualization of the large data sets available, a yield management system should be expected to provide engineering analysis tools to perform a variety of analysis tasks such as line monitoring, defect partitioning, correlation and trend, split lot, and failure analyses. Many of these analysis functions are repetitive in nature, and when performed manually consume a large amount of fab personnel time. This is costly both in terms of the staffing required to perform the analysis and in lost revenue when a yield problem is not caught immediately. By providing the facilities to build recipes to automate repetitive analyses, a modern yield management system can improve productivity and reduce the response time to potential issues. As shown in Fig. 31.2, such a yield management system consists of defect analysis specific components such as in-line and off-line inspection tools, a defect data hub, and visualization stations as well as general manufacturing components such as equipment tracking and automated process control systems. It is expected to perform a variety of interface and analysis functions, including provide an integrated database for the storage of wafer inspection data, provide a unified interface to access multiple types of data, provide tools for engineering analysis, provide data analysis automation, and provide automatic report generation capability. In summary, a comprehensive yield management system supports the collection of many types of data from many sources in the manufacturing process. In addition, it supports a range of analyses across the data and the correlation of many different factors. To aid the human users of the system, it must provide powerful and flexible visualization tools that allow the user to focus on the data analysis rather than the data manipulation. Finally, it must also be capable of automatically performing standard analyses to eliminate repetitive tasks that would otherwise have to be done by fab personnel.

31.3 WHAT ARE THE ELEMENTS THAT YIELD MANAGEMENT CONSISTS OF AND HOW ARE YIELD MANAGEMENT SYSTEMS IMPLEMENTED? As described previously, yield management involves manipulating large quantities of data to identify yield trends. Thus, it is easy to focus on the data collection and analysis tools when describing a yield management system. As shown in Fig. 31.3, however, a full system involves not only analysis tools, but a yield model to aid in predicting potential issues, operational methodologies to support the appropriate yield learning at each stage of a process generation, and an organizational commitment to yield management. 31.3.1 Yield Modeling The first step in managing yield is understanding what yields can be expected. Previously, yield modeling consisted of “macroyield modeling,” in which die size, device densities, and other large scale factors were used to predict the yield for a new process and product design. The Poisson method of yield modeling is a particularly well-known example of this type of macroyield modeling. Initially, the ease of using this model and the success with which it could predict yield values made it quite convincing. Engineers could use wafer yields and physical die size areas to back calculate the overall defect density of their individual product type. However, the limitations of this type of yield modeling have become apparent as die size and mask level complexity have increased. Predicted yields are now too optimistic and defect modes are over simplified compared to the physical realities. Today’s advanced fabs need a modeling technique to partition the components of yield losses to their individual levels and types. It is important for the fab managers to be able to explain and predict yield prior to starting manufacturing, to understand and compare best case product design efficiencies without having to wait for the product to actually be manufactured. This allows products to be compared purely on a design basis without having to try to isolate fab-caused defects from fundamental design issues. It is also key to identifying a product design early enough to achieve the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.8

YIELD MANAGEMENT FAB YIELD, OPERATIONS, AND FACILITIES

B ench M

ark

Custom er

t en tm

Re

y bilit lia

Com m i

31.8

Preproduction engineering

Long loop analysis • Yield enhancement analysis • Limited yield ownership • Objectives/targets CIM • Logistics • Test • Engineering • Enterprise

Yield modeling • Critical area • Delayered • Entitlements • Validation

Short loop control • Scribe line analysis • Automatic defect inspection (ADI) • In-line YEA • Limited yields analysis

Operations • Self-directed teams • Mfg. yield objectives • Practices FIGURE 31.3

Integrated yield management illustration.

time-to-market cycles required in today’s industry. Inversely, when companies want to compare defect densities across fabs that aren’t producing the same products, it is important to understand what yield limiters may be inherent to a specific product versus steps being taken in a fab to eliminate manufacturing defects. Finally, over time, it is important to understand defect density learning trends without clouding the data between design issues and manufacturing excursions. The Poisson method has proven to be inadequate in addressing these needs, leading to the introduction of microyield modeling. The world class method in this space today is negative binomial yield modeling using defect clustering and critical area analysis (CAA). By obtaining a detailed understanding of the circuit design, the microyield modeling uses critical area, parametric sensitivities, redundancy effects, and other factors to estimate the yield effects of different classes of defects, process variability, and layout variations. The critical area is defined as the physical area on a die where a defect of a given type and size will cause a failure. The total, average critical area is determined by integrating the probability of a failure for all defined defect types over the available defect sizes. This concept of critical area stems directly from the limited yield concept developed by numerous outstanding contributors to the yield modeling field and was introduced to quantify differences in circuit layout complexities as reflected in actual yield results. Beyond simple circuit probe yield modeling, however, the use of the CAA methodology allows advanced organizational practices like: • • • • • •

Yield predictions based on new designs, prior to even building the first silicon Proactive yield predictions to cover cost and manufacturability issues with business units Design efficiency metrics—minimum critical areas for given die sizes Partitioned yield learning plans delivered as a function of time Yield entitlements for individual processes and equipment purchases Foundry yield expectations with respect to costs and yield promises

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.9

YIELD MANAGEMENT YIELD MANAGEMENT

31.9

• Targeting and validation of short loop defect inspection tools against circuit probe yields • Fab-to-fab benchmarking independent of whether they are running single device rectifiers or advanced microprocessors Obviously, an analysis method alone does not automatically provide these benefits. Realizing the advantages of CAA requires sophisticated support tools. 31.3.2 Computer Integrated Manufacturing Computer integrated manufacturing (CIM) systems, long considered critical for their flow control and productivity enhancement aspects, serve as the basis for a strong yield management system as well. As shown in Fig. 31.4, the key ingredients of a CIM system include the manufacturing execution system (MES), automated material handling system (AMHS), process equipment interface (PEI), and engineering analysis (EA) system. These systems integrate and interact with each other via the use of industry standards, wherever possible, and through custom adapters, where no standards exist. The CIM system provides rapid analyses and responses to issues impacting yields in production lines to resolve yield problems effectively and efficiently. Manufacturing Execution System. In a large semiconductor fab, there may be in excess of 10,000 lots, each of which may contain 25 wafers. These lots will be processed through several hundred steps across upward of 100 different types of equipment. In the early days of semiconductor manufacturing it was sufficient to control the flow of this activity through the use of run cards attached to each lot. As the process became more complicated, however, it became necessary to introduce a systematic formalization of production methods and procedures, which is implemented in an MES. As an MES significantly reduces faulty processing via production and process controls and improves the process stability via process diagnostics and controls, it serves as the foundation for yield learning and improvement in the yield management system. Before looking at a specific example of how an MES can impact YM, it is important to understand the scope of an MES. Though a complete definition of an MES is beyond the scope of this chapter, a brief introduction is provided by the Manufacturing Execution System Association (MESA) International, a nonprofit organization comprising companies that work in supply chain, enterprise, yield management, product life cycle, production, and service environments as:

Tool control Tool setup Data collection Statistical process control

Manufacturing execution

Workflow control Equipment management Engineering specifications Experiment execution SPC FIGURE 31.4

Process equipment interface

Stockers Monorail systems Control systems Scheduling systems

Automated material handling

Hardware, network and user interfaces

Engineering analysis

Yield analysis Device performance analysis Advanced process control

Factory computer integration manufacturing system modules.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.10

YIELD MANAGEMENT 31.10

FAB YIELD, OPERATIONS, AND FACILITIES

An MES delivers information that enables the optimization of production activities from order launch to finished goods. Using current and accurate data, an MES guides, initiates, responds to, and reports on plant activities as they occur. The resulting rapid response to changing conditions, coupled with a focus on reducing non-value-added activities, drives effective plant operations and processes. The MES improves the return on operational assets as well as on-time delivery, inventory turns, gross margin, and cash-flow performance. An MES provides mission-critical information about product activities across the enterprise and the supply chain via bidirectional communications.

In other words, the MES serves as the central clearinghouse for all information collected during the manufacturing process, and also orchestrating the operations in the factory. The principle functions of such a system include scheduling, resource allocation, dispatching production units, performance analysis, maintenance management, quality management, and data collection. It is this collection, and trending, of defect data that is the key to yield management. As an example, the statistical process control (SPC) system monitors the progress of defect reduction at critical points in the manufacturing flow. A YM system then provides applications for trending defect densities on SPC charts and correlating defect trend data to yield using linear regression. By identifying a correlation between an increase in the rate of a particular defect type at a particular process step and a negative yield impact early, a large-scale yield crash can be avoided. Automated Material Handling Systems. If the MES is key to managing the data complexity inherent in semiconductor manufacturing, then the AMHS is key to managing the physical logistics of processing tens of thousands of lots on hundreds of pieces of equipment. Other analogies between the systems also hold true. The growth of the use of AMHS in semiconductor manufacturing has paralleled the growth of the use of MES. Initially introduced with 150 mm wafers, AMHS has grown in significance and sophistication as semiconductor processing has become more complex. And, just as the principal function of an MES was originally viewed as productivity enhancement, the YM aspects of AMHS were not a key driver. While automated lot handling has been viewed primarily as a productivity enhancement, automated wafer handling was identified as a yield enhancement opportunity early on. Through yield analysis, it was noted that a major source of the die yield loss (up to 7 percent) is related to wafer scratches. This correlation became apparent as a result of mapping physical defects on wafers and analyzing the types and frequencies of defects. Further analysis indicated that the vast majority of scratches (approximately 95 percent) were randomly located over the wafers, often showing either arc-shaped patterns or short-liner segments typical of wafers rubbing against one another during manual loading or unloading into production cassettes. This analysis provided the understanding of benefits to proliferate automated wafer handling operations across the fab. Across 150-mm and 200-mm fabs, it was possible to fully automate wafer handling while maintaining completely manual or only semiautomated lot handling, the overall material handling problem was significantly impacted by the transition to 300-mm wafers. While partial automation, in the form of automated storage and retrieval systems (stockers), and cross factory transport (interbay), was common in 200 mm fabs, tool interfaces were largely customized for each tool vendor, making transport directly to the tool difficult and costly to implement. Thus, the immediate yield problem of wafer scratching was eliminated by automating the extraction of wafers from the lot carrier at the tool, but getting the carrier to the tool was still a manual process. This also left the door open for extensive manual handling of wafers for other reasons. With the standardization of tool interfaces and the introduction of sealed carriers (front opening unified pods, or FOUPs) in 300 mm fabs, completely automated material handling has become not only practical, but practically required. The shift to 100 percent automated material handling has at a surface level simply completed the process started with the introduction of automated wafer handling. By eliminating manual handling at all levels, the AMHS reduces damage to wafers during transport, storage, and equipment loading. More importantly, however, through the proper integration with the MES, fully automating factory operations provide an opportunity to improve yield learning and management by eliminating off-line activities and variability that often impact the yield and are hard to track, and by reducing cycle time through the fab, allowing for faster turnaround of yield information.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.11

YIELD MANAGEMENT YIELD MANAGEMENT

31.11

Process Equipment Interface and Defect Monitoring. Of course, if managed incorrectly, automated operations can negatively impact YM as well. Removing engineers and technicians from the processing picture eliminates a major source of contamination in the fab. It is well known that particle contamination is still the dominant reason for yield drop, and thus eliminating a major source of contamination is a positive step. Unfortunately, removing the human element from the manufacturing process also removes the most necessary component of any YM system—human intelligence and flexibility. Compounding this is a natural tendency to focus on the cost reduction and productivity aspects of automation. It is important that factory management, and the organization as a whole, not lose focus on defect management. Fortunately, a focus on defect management is not necessarily at odds with a cost reduction and productivity focus, but it does introduce additional requirements. In a simple manufacturing line, it is possible to automate the process and provide only a final quality assurance step that usually involves a manual evaluation of the final product. In the complex world of semiconductor manufacturing, however, these quality checks must occur repeatedly throughout the line. To achieve the productivity benefits of fully automated operations, these data collection and analysis steps must also be automated at the tool level to ensure defects are detected at the earliest opportunity, while ensuring that the manufacturing line is interrupted only when an issue is found. The process equipment provides the interface to CIM to convey the manufacturing process data such as CVD, PVD, and implantation recipes and time information to the YM system. As noted previously, particle contamination is the largest contributor to yield issues, especially in the high volume manufacturing of VLSI/ULSI circuits. Depending on their size and location within a die, particles deposited on the wafer surface may cause permanent defects in integrated circuit (IC) structures. Therefore, comprehensive in-line defect inspection techniques interfacing with the process equipment are of crucial importance in yield management for state-of-the-art technologies. Of course, particle defects are not the only issue, and in-line techniques are also necessary for smooth deposited layer monitoring after resist development inspection and after-etch line inspection. Ideally, all such techniques would be able to identify potential issues at each tool during production. In reality, only some in situ monitoring is possible. The primary technologies available for wafer inspection include laser scanning, Fourier filtering, and digital image processing. For some defect types, some of these technologies can be used to do in situ particle monitoring. In other cases, it is necessary to run bare wafers, or specially prepared test wafers through a tool and then measure the wafers at specific metrology tools to collect information on equipment cleanliness and performance through simple particle counts or film thickness measurements. In still other cases, it is necessary to do a more detailed defect source analysis on both product and test material, for example, using scanning electron microscopes (SEM) with delayering. Engineering Analysis. Though the in-line monitoring techniques described previously are clearly critical for defect detection, engineering analysis is one of the most central CIM components to YM. As shown in Fig. 31.4, EA can be broadly categorized by yield analysis, device performance analysis, and advanced process control. As with other CIM components, a complete definition of EA is beyond the scope of this chapter. However, a brief introduction to the PCS aspect of EA is in order. PCS is fundamentally a continuous improvement discipline that impacts a wide variety of manufacturing technologies and job functions. Specifically within the semiconductor industry, PCS has evolved to include very sophisticated fab-wide infrastructures and distributed application frameworks supporting multiprocess “cascaded” and hierarchical control applications. As shown in Fig. 31.5, PCS implementations are currently mapped to fault detection and classification (FDC), run-2-run (R2R), and SPC. The usage model is different for each PCS component, as is YM implications. For example, FDC applications are usually implemented at the tool level, perform real-time analysis on process data, and manipulate large amounts of data to monitor the equipment. In this sense, they are closely aligned with in-line defect monitoring. R2R applications typically operate within a lot or within a collection of lots to adjust processing parameters (such as polish time and downforce) on a wafer-by-wafer or “run-by-run” basis. This is done to compensate for incoming variability as well as observed or predicted tool drift. In general R2R compensation occurs over longer time periods using smaller data sets than FDC, and is focused on process yield

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.12

YIELD MANAGEMENT FAB YIELD, OPERATIONS, AND FACILITIES

Process control approaches Lot-fab

Correlation with electrical test

Lotlayer Span of control

Lotoperation

Inter-process/cascade control Real-time sensor/actuator control Lot-level control Wafer-level control

SPC R2R

Water FDC Die Real-time/embedded Site-level control 0.01 sec 0.1 sec

1 sec

10 sec

Minutes

Hours

Days

Weeks

Time scale

FIGURE 31. 5

Variations of process control technology.

DB

SPC

issues rather than particle induced defects. Finally, SPC applications may tackle metrology or postprocess data over a large section of the manufacturing line, manipulating even less raw data, but using univariate or multivariate analysis techniques to monitor the health of a fab module or entire process. Though they function quite differently, FDC, R2R, and SPC all perform three basic functions— data collection, manipulation or reduction, and interpretation. Ultimately, these functions then result in decisions and/or actions that impact the manufacturing process. Figure 31.6 illustrates at a high level how these systems can be implemented. As shown, it is important that these systems should be able to interact and update or share tool state information. Consider that the majority of R2R algorithms are based on linear or polynomial models that relate pre- and/or postprocess product metrology values (such as film thickness, critical dimension, and alignment error vectors) to the process recipe parameters (such as process time, exposure dose, and RF power). Likewise, the algorithms in most FDC systems use univariate or multivariate statistical techniques and experimental trace/metrology data sets to characterize tool/metrology

FDC

DB

Data collection Station controller

R2R

Data + control

DB Data + control

31.12

UI UI

Control Process Process Equipment equipment

MES FIGURE 31.6

Process control system application groups.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.13

YIELD MANAGEMENT YIELD MANAGEMENT

31.13

behavior and develop a set of fault models. When R2R and FDC solutions are both deployed in a given process area, they will be working at cross purposes if the FDC system is unaware of tool behavior changes being driven by the R2R algorithm. On a small scale, this interdependence of process control systems is indicative of the larger dependencies within the overall YM system. Advanced yield modeling techniques and sophisticated CIM tools are necessary, but not sufficient to achieve the yield improvements required in today’s competitive semiconductor industry. As shown in Fig. 31.3, operational methodologies and an overall commitment to yield management are also required, even before manufacturing begins. 31.3.3 Preproduction Engineering Semiconductor manufacturing has grown increasingly complicated, while the expectations of the development cycle time have remained constant, or even become shorter. Therefore, it is very important to establish a highly efficient research and development pilot line. As shown in Fig. 31.7, while process generation moves from research through development into manufacturing, the willingness to take risks diminishes rapidly because the costs of making mistakes increase dramatically. Yield learning and improvement must be established during the research and development phases, so that the focus of manufacturing can be on the replication of already proven solutions. Certainly, yield improvement opportunities will continue to exist throughout the manufacturing life of a process/product, but the greatest profit opportunities exist early in the manufacturing ramp, and thus high early yields are critical. A study on competitive fabs by the University of California at Berkeley presented the defect density yield learning from 16 participant fabs from the time of device part number introduction to mature manufacturing. Their report discusses many salient fab comparisons, but specifically highlights the impact of yield differences in products at the time of introduction into manufacturing. The analysis clearly shows that even with substantial yield learning on the part of some companies, they cannot catch the companies with higher initial yields. This yield “head start” at the time of new product introduction results in substantial revenue. In addition, meeting on-time delivery requirements early in a product introduction can set the stage for a larger number of future satisfied customers. Thus, every YM investment in the preproduction phase has significant dollar return when it reaches manufacturing. Further, YM approaches established during the preproduction phase set the stage for additional yield enhancements in manufacturing. For example, the utilization of the right information technologies can improve the communication speed and effectively reduce loss time in production for the research and development line. A monitor/browsing system that displays well-defined data that can be understood at a glance by fab personnel can be employed to visualize yield management data,

Research

Development

Manufacturing

Generation

G3

G2

G1

$/year:

~107

~108

~109

Risk taken:

High

Moderate

Low

Tech focus:

Evaluate

Integrate

Replicate

Mgmt focus:

Plan

Synchronize

Control

FIGURE 31.7

Semiconductor technology life cycle.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.14

YIELD MANAGEMENT 31.14

FAB YIELD, OPERATIONS, AND FACILITIES

allowing rapid response and recovery. With the help of such a monitor view, technicians are able to watch defect trend charts regularly, investigate the distribution of defects, calculate distribution maps, determine equipment yield impacts, and take action to improve the yield throughout the research and development phases. This type of coordinated yield improvement can significantly reduce the development cycle time, as well as transition directly from development to manufacturing to provide a seamless product introduction and ramp. 31.3.4 Short Loop Control The rapid turnaround on yield issues facilitated by the data visualization systems described previously is typically characterized as short loop control. As listed in Fig. 31.3, this area includes scribe line analysis, automatic defect inspection (ADI), in-line yield enhancement analysis (YEA), and limited yields analysis. Each of these capabilities is designed to capture yield losses immediately after they occur in the process where maximum control can be exerted. Effective short loop systems are essential value-added tools in every fab. Applying control at the point of defect introduction allows the organization to realize the greatest possible benefit. Should there be any question of the value of these systems, it is the function of the yield engineers to ensure that everyone understands the value and importance of short loop tools through the evaluation of metrics such as DFQR. Using a failure mode and effects analysis (FMEA), a yield engineer can quantify the yield and/or customer impacts of failing to identify defects at their source. This technique provides an extremely powerful tool for quantifying the value of short loop systems. ADI is a prime example of such a short loop tool. It has become an integral part of today’s modern fabs, but is usually not fully implemented. Ideally, yield engineers would use nonvisual yield components from YEA and electrical test site results to exercise short loop control. This analysis should be quick to perform and identify immediate fixes to yield issues. In practice, a large number of today’s fabs perform this analysis instead in the “special cause zone.” Failure detection in the special cause zone could be caused by one or more issues and results in more time consuming analysis. The reason for this is a lack of adequate short loop electrical monitors. The design and implementation of these test structures is not trivial, but they are very important, and it is up to the yield engineers to quantify the benefits and coordinate within the organization to implement the best approaches to short loop control. 31.3.5 Long Loop Analysis In comparison to short loop analysis, long loop analysis focuses on generating a 100 percent yield explanation. As listed in Fig. 31.3, this area includes YEA, limited yield ownership, and the objectives or targets for the organization. YEA is a systematic approach to performing failure analysis on common issues in the yield distribution. Routine failure analysis is performed on selected, bit mappable arrays that are product or product-like line monitors. Limited yield ownership is defined heuristically as the upper limit for the circuit yield that would be obtained if a particular defect type were the only factor limiting the overall yield. This limited yield data itemizes all the “trivial many” yield detractors found in the common cause yield population and hence can be used to prioritize yield improvement efforts. Finally, the up-front definition of organizational objectives and targets has the exceptional power to integrate yield ownership from across the total enterprise. Traditionally, yield ownership has been the domain of process engineering, but yield ownership rightfully also belongs in the design/development organization, purchasing and equipment engineering, and even facilities engineering as the introduction of foreign materials in the building of the fab can limit the yield. The introduction of long loop analysis as a YM component is often the first time management and engineering have the opportunity to define, prioritize, target, and set realistic yield plans against all the detractors. This process goes well beyond the advantages of targeting only the top yield limiters in the Pareto. All the “low hanging fruit” from each partial yield percentage can be addressed and improved across the organization.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.15

YIELD MANAGEMENT YIELD MANAGEMENT

31.15

31.3.6 Total Yield Ownership This approach to total yield ownership has become a necessity as yield improvement requirements have become more and more stringent. A complete YM system consists of many powerful tools and methodologies, but ultimately organizational alignment and ownership is key. By considering all the possible defect sources throughout the global fab environment and uniting the team through common objectives and a common language, the organization can achieve significantly improved yield results much faster than an organization relying solely on a few yield management owners. Of course, achieving a level of total yield ownership is not easy. In particular, an implementation plan that encompasses many process generations at different stages of development and many levels of integration presents enormous communication and coordination challenges. The nature of these challenges varies from one level of integration to another. At the lowest level, a large number of experiments need to be performed with data cycles ranging from as little as a few minutes to upward of a week. It is important that these activities be coordinated and performed in as analogous a manner as possible to maximize information sharing with minimum overheads. As the level of integration increases, the number of experiments is typically much smaller, but their cycle times are also much longer, so it remains important that commonalities are maintained. One management approach to this problem is to define a two-dimensional ownership matrix. One ownership dimension consists of the individual functional owners—machine owners, operators, and maintenance personnel. The other consists of fab-wide system owners such as engineers in charge of similar equipment sets, AMHS owners, or integration engineers. Because operators and maintenance personnel represent the largest population in today’s fabs, they are one of the most critical ingredients in short loop engineering. They are often aware of problems before the process engineers identify them and are also aware of the possible causes of these failures. The higher level system owners, however, have a greater visibility into the interrelations of different factory activities and are critical to long loop engineering to identify and fix issues involving more than one module. The engineers and technicians assigned to the system-wide or cross-functional teams are pulled from the process, equipment, and materials areas and collectively specify the expectations and limits for all the factory systems. This includes the obvious matters of concern—acceptable contaminant levels for the cleanroom air, gases, ultrapure water, and the like, as well as other cleanroom specifications such as acceptable vibration levels, temperature, and humidity. These teams also assume responsibility for the quality of these items on a continuous basis. They are in charge of monitoring and generating automated inspection data, and assisting in the analysis of yield issues stemming from factory-wide systems. In contrast, module teams are typically multiphase, multigenerational forums for all process integration issues pertaining to a specific module. Typically composed of process engineers and technicians from the relevant equipment sets, as well as process integration engineers and yield and reliability specialists, these teams cover specific process layers and modules. A module team serves as the first line of defense against electrical faults, as well as specifies the defect density requirements for each aspect of the module. The members of the team are then responsible for driving fault reductions by reducing defect densities in their areas. As stated previously, this approach to total yield ownership is easier described than implemented. Defects and faults must be fought concurrently, continuously, and consistently in all phases of process development, at all levels of integration, and in every process generation. The pursuit of analogous methods can reduce coordination and communication challenges. If all personnel use common experimental strategies, test chips, measurement methods, and methodology and data analysis tools, more people will have a better understanding of the result data. However, prevailing in this tenuous struggle cannot occur without a strong and persistent commitment by management. Defect or fault reduction in any area cannot proceed unless all the underlying issues have been explored because yield improvement efforts at high levels of integration are orders of magnitude less efficient than they are at the individual tool level. Thus, management support of defect reduction at all levels, and especially at the base, is critical for shortening the learning curve for process development.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.16

YIELD MANAGEMENT 31.16

FAB YIELD, OPERATIONS, AND FACILITIES

31.4 WHAT ARE THE CONSIDERATIONS IN OPTIMIZING YIELD MANAGEMENT SYSTEMS? The final aspect of YM to be examined in this chapter is that of optimization. An organization with all the right tools, accepted ownership across all levels, and the full support of management can still only be successful if they have direction. A fundamental framework for yield management consists of the three-dimensional space shown in Fig. 31.8 where the axes represent quality, process integration, and scaling. Defect density and the capability indices (Cp and Cpk) are the primary parameters that characterize the quality axis, while the milestone acronyms WS, ES, CS, and VP stand for work sample, engineering sample, customer sample and volume production, respectively. The intrinsic data cycle time and product complexity are associated with the process integration axis. Finally, the minimum features of VLSI/ULSI circuits quantify the scaling axis. By understanding the interrelationships within this space, an organization can focus its efforts better in the right direction. 31.4.1 The Quality Axis Quality improvement efforts can be divided into four discrete phases—research, control, transfer, and manufacturing. Throughout each of these phases the defect density of all the failure modes should decrease, and the degree of control over all the parameters should increase. This is formally quantified through the measure of defect densities and Cpk. Defect densities correspond to simple functional yield values while Cpk numbers are based on specification limits that reside infinitesimally within the brink of values that induce an electrical fault. In the research phase, specifications are not determined yet, and distributions of parameters are typically neither stable nor normal. Therefore, at this stage, systemic process problems are the dominant contributors to the defect density. During the control phase, distributions of all the relevant process parameters are narrowed and centered. The process usually yields working samples when the average of the Cpk values of all process parameters is around 0.5. By the end of the control phase, Cpk for most parameters runs around one and the systemic process problems have been minimized.

Level of integration

Packaged part VLSI fab Process module Process layer Workcell pass Station pass SECEM

n

G1 1.0 um G2 0.7 um 0.5 um ize

G3 0.35 um

0.25 um

0.15 um

Scaling axis FIGURE 31.8

it Cr

ica

lf

t ea

ur

e

0.5 10 Syst

s

1.0 1.0 Mixed

1.5 0.1 Random Manufacturing

G5

Quality milestone

VP

CS

Transfer

oc G4

n

WS

ES

Control

ge

tio

Research

Pr

s es

a er

th on 1m k e e 1w y a 1 d ft hi 1s r ou 1h

Intrinsic data cycle time

Process integration axis

Cpk

Quality axis

DD (cm−2 ) Dominant defect type

Development phase

A three-dimensional space comprising an integrated framework for yield management.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.17

YIELD MANAGEMENT YIELD MANAGEMENT

TABLE 31.2

31.17

Most Complex Products of Specific Process Segments

Process segment type (level of integration)

Most complex product

Packaged part VLSI fab Process module Process layer Work cell Station SECEM

Fully functional and reliable VLSI circuit in a package Fully functional VLSI circuits on a wafer Parametric test structures with multiple conducting layers Parametric test structures with single conducting layer Multiple films or single-level, nonelectrical structures Modified preexisting film or structure None

As shown in Fig. 31.8, the majority of the key quality milestones occur during the control phase with the production of working samples in the early stages, engineering samples in the middle of this phase, and customer samples at the end as Cpk values approach one. However, quality improvements must continue to be driven through the transfer phase to achieve a process/product that can be manufactured cost-effectively. By properly understanding where the process is along this axis, the organization can set reasonable YM expectations and focus on the correct problems. 31.4.2 Process Integration Axis Likewise, by understanding the implications of different process integration levels, the organization can ensure that the appropriate focus and tools are being applied to different problems. Process integration is defined as combining a series of short process segments into longer process segments that yield more complex products. In this case, a product is defined as any tangible entity produced by a process segment that can be evaluated quantitatively. Typically a product is considered to be fully functional circuit on a wafer, but as shown in Table 31.2, a product can be as simple as a modified film or simple structure on a wafer. The nature of the most complex product fabricated by a process segment associates the segment with one of seven levels of integration, as exhibited in Table 31.2. For example, the SECEM (site, environment, consumables, equipment, and materials) level, due to its real-time nature, requires no wafer processing and thus yields no products. At the next level, a station segment, or single fabrication step, can either add a film to a wafer or make a simple modification to an existing film or structure. This continues through a work cell segment, which can only add a few films to a wafer or make slightly more sophisticated modifications to a film or structure, up through a fully packaged part that can be fully tested. Table 31.3 indicates which methods of defect detection are appropriate for each level of integration. The quality of the SECEM level of integration is ideally determined on a real-time and in

TABLE 31.3

Defect Detection Methods for Various Levels of Integration

Level of integration Packaged part VLSI fab Process module Process layer Work cell Station SECEM

Method of Defect Detection Real-time in situ

PWP

Auto inspect

Parametric test

Functional test

Life test *

*

* *

* * *

* * *

*

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.18

YIELD MANAGEMENT 31.18

FAB YIELD, OPERATIONS, AND FACILITIES

situ basis. At this level there is no product to measure. However, each higher level of integration involves separate fabrication and measurement steps. In a station segment, for example, wafers pass through a single piece of process equipment that modifies the state of the wafers, and separate metrology equipment perform measurements on the modified wafers. In a work cell segment a wafer passes through more than one piece of process equipment before it undergoes a defect detection step. Moving up the process integration axis, a process layer is a process segment that contains at least one thin-film deposition, at most one patterning step, and at least one etch step. P-active, N-doped polysilicon, and metal interconnect layers are examples of conducting process layers that are electrically testable. Automatic inspection of critical layers prior to parametric testing can establish a direct correlation between defects and electrical faults but only if the test pattern contains electronic microstructures that yield with statistical significance. A process module is a process segment that yields circuitry that can be parametrically but not functionally tested. Process segments that yield NMOS, PMOS, or bipolar devices as products are examples of more complex modules. Finally, a process segment that yields products that can be functionally tested without dicing wafers is defined as a VLSI/ULSI fab segment, and the final integration layer involves packaging the die to allow life testing. 31.4.3 The Scaling Axis The final axis in this model is the scaling axis. This axis differs from the other two in that each new process/product does not restart at the origin, but instead extends the axis even further. It is the persistent effort to increase the density and performance of integrated circuits (ICs) that drives the need for improved YM tools and methodologies through each process/product cycle. Yield models that once provided an adequate picture of defect densities are no longer sufficient. FDC, R2R, and SPC systems that resulted in acceptable yield learning rates only a few years ago are now obsolete. As integrated circuit (IC) scaling is expected to continue along its historic trend for the foreseeable future, the drive for new YM systems can also be expected to continue. As critical feature sizes shrink, smaller defects may develop into faults. Unfortunately, the defect frequency grows geometrically with the defect size, which makes the potential impact of defects on yield even more severe as the scaling axis is extended. The detection, prevention, reduction, control, and elimination of increasingly smaller defects thus become key components of any YM strategy, even if increasingly expensive tools and methods must be deployed. Even though the YM system technology will become more and more challenging and complicated, this need for increasingly complex and expensive YM systems does not exist across the entire spectrum. The basic test structures needed for exploring the defect environment at higher levels of integration are well known and typically scalable. In fact, many of these designs have been scaled to cover upward of three consecutive process generations. In addition, scaling the overall die size has required only manageable design modifications that incorporated new physical phenomena.

31.5 TRENDS AND CONCLUSIONS Financial success in the semiconductor industry depends on rapid yield learning. To enhance yield, defect reduction engineers and manufacturing operations personnel need quick and easy access to process control, partitioning, defect image, and wafer yield information. The YM approach allows this by providing the hardware and software to locate, visualize, analyze, and correlate submicron defects to yield. However, the rate of change in semiconductor manufacturing shows no signs of slowing. Thus, YM systems must also be expected to change to keep pace and continue to enhance productivity and generate revenue and profits. Yield management strategies essentially entail exploring the space shown in Fig. 31.8 in an orderly manner. To facilitate integration and allow interoperability, the leading semiconductor manufacturers are

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.19

YIELD MANAGEMENT YIELD MANAGEMENT

31.19

driving SEMI standard task forces to develop yield management system standards. The goal of the standards is to significantly reduce the systems integration time and the cost associated with implementing a YM system. This enables the manufacturers to focus on YM functionality when designing and implementing a system instead of the integration complexities. As shown in Fig. 31.9, these efforts include both equipment specific and factor-wide systems. These efforts become even more critical with the introduction of the sub-100 nm technology nodes. There is a need for tighter process control resulting in a need for quicker yield management capabilities development and deployment. To support the continually changing requirements of a modern wafer fab, no fixed set of YM system features can be sufficient. Even if a complete solution was available at some point in time, it is extremely unlikely that a single product or company could keep up with the pace of innovation required. In fact, the pace of innovation continues to accelerate as process engineers are armed with more and more data. Consequently, YM solutions must have the inherent flexibility necessary to enable their providers to respond quickly with new control application capabilities. By focusing on the integration of individual components, the SEMI standards provide a framework for employing the best of breed YM tools that have been developed in-house, or from multiple suppliers. Determining what constitutes the best of breed, however, requires some scale against which to measure components. The DFQR metric provides this today. Demonstrating that a particular capability enhances an organization’s ability to quickly correct yield issues, can provide the justification for implementing the capability in the first place as well as for implementing one specific solution instead of another. The vendor community today offers numerous YM solutions in the areas of tool connectivity, database integration, and knowledge-based analysis systems. Also, integrated solutions are being provided with ADI equipment to provide defect clustering analysis. With these types of capabilities, more experienced, larger fabs are moving toward information generation, instead of just data collection, allowing more rapid responses to yield excursions. Looking forward, YM systems are expected to not only improve the response time in the current mode of detect, fix, and quickly recover, but also move into the space of predictive yield performance. In fact, unit-level traceability has prestaged the move into an era of predictability. Models relating wafer sort parameters with final device performance are constantly improving. This will eventually lead to trusted models for similar relationships among fab metrology data, e-tests, wafer sorts, and final tests. Once these capabilities are employed as part of an overall YM strategy, the automation systems controlling the fab should be able to route individual wafers based on tool capabilities and availabilities to maximize each wafer’s revenue at the lowest possible cost.

FIGURE 31.9 An example of the yield management system standard—the process control system standard.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH31.qxd

04/04/2005

21:01

Page 31.20

YIELD MANAGEMENT 31.20

FAB YIELD, OPERATIONS, AND FACILITIES

FURTHER READING Aloni, C., “TYM System: An Integrated Tool for Inherent Line Yield Improvements for Entire Fab,” Proc. Ninth Int. Symp. Semicond. Manufac., pp. 237–240, 1997. Effron, M., “Integrated Yield Management: A Systematic Approach to Yield Management,” IEEE/SEMI Adv. Semicond. Manufac. Conf., pp. 397–403, 1996. Chatterjee, A., R. K. Nurani, S. Seshadri, and J. G. Shanthikumar, “Role of Yield Management in FablessFoundry Partnerships,” IEEE Int. Symp. Semicond. Manufac. Conf., pp. 31–34, 1997. Castrucci, P., G. Dickerson, and D. Bakker, “Utilizing an Integrated Yield Management System to Improve the Return on Investment in IC Manufacturing,” IEEE/SEMI Adv. Semicond. Manufac. Conf., pp. 25–29, 1991. Chung, S., and M. Jeng, “Fabulous MESs and C/Cs—An Overview of Semiconductor Fab Automation Systems,” IEEE Robot. Automat, Mag., Vol. 11, No. 1, pp. 8–18, 2004. Geng, H. Y., “Design, Plan, and Implement a CIM Project,” ASME Manufac. Int. Conf., Vol. 1, pp. 27–32, 1990. Guldi, R. L., M. T. Whitfield, D. E. Paradis, F. D. Poag, and D. P. Jenson, “Automation of Wafer Handling In Legacy Semiconductor Fab—A True Culture Change,” IEEE/SEMI Adv. Semicond. Manufac. Conf., pp. 120–125, 1997. Kittler, R., M. Mclntyre, C. A. Bode, T. J. Sonderman, S. Reeves, and S. Zike, “Achieving Rapid Yield Improvement,” Semicond. Int., Vol. 27, No. 8, pp. 53–60, 2004. Lee F., and S. Smith, “Yield Analysis and Data Management Using Yield Manager®,” IEEE/SEMI Adv. Semicond. Manufac. Conf., pp. 19–30, 1998. Mullenix, P., J. Zalnoski, and A. J. Kasten, “Limited Yield Estimation for Visual Defect Sources,” IEEE Trans. Semicond. Manufac., Vol. 10, No. 1, pp. 17–23, 1997. Nurani, R. K., R. Akella, and A. J. Strojwas, “In-Line Defect Sampling Methodology in Yield Management: An Integrated Framework,” IEEE Trans. Semicond. Manufac., Vol. 9, No. 4, pp. 506–517, 1996. Parikh, M., “Automation in IC Manufacturing: Past, Present and Future,” IEEE Int. Symp. Semicond. Manufac. Conf., Keynote Speech, 2003. Recker, C. L., and M. Hackerott, “Win-Win Supplier-Customer CIM Partnering,” IEEE/SEMI Adv. Semicond. Manufac. Conf., pp. 306–308, 1995. Stapper, C. H., and R. J. Rosner, “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Trans. on Semicond. Manufac., Vol. 8, No. 2, pp. 95–101, 1995. Srinivasan, K., “The Evolving Role of Automation in Intel Microprocessor Development and Manufacturing,” Intel Tech. J., Vol. Q3, pp. 1–7, 2001. Seshadri, S., J. G. Shanthikumar, R. K. Nurani, and A. Chatterjee, “Fabless-Foundry Parternerships: Research and Coordination Issues,” IEEE/SEMI Adv. Semicond. Manufac. Conf., pp. 386–390, 1997. Srinivasan, K., “Intel’s Use of Advanced Process Control in Si Technology Development,” University of California at Berkeley, Distinguished Guest Lecture, 2003. Weber, A., “APC: 2004 Technology and Market Update,” Semicond. Int., Vol. 27, No. 8, pp. 63–66, 2004. Weber, C., B. Moslehi, and M. Dutta, “An Integrated Framework for Yield Management and Defect/Fault Reduction,” IEEE Trans. on Semicond. Manufac., Vol. 8, No. 2, pp. 110–120, 1995. Wang, E., M. Holtan, R. Akella, I. Emami, M. McIntyre, D. Jenson, and D. Fletcher, “Valuation of Yield Management Investments,” IEEE Int. Symp. Semicond. Manufac. Conf., pp. 1–7, 1997. Wu, J., O. Rozmarin, and B. Li, “A Flexible Execution Controls Framework for 300 mm Factory Automation,” Semicond. Manufac., Vol. 4, No. 11, pp. 162–174, 2003.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 32

AUTOMATED MATERIAL HANDLING SYSTEM Clint Haris Brooks Automation Chelmsford, Massachusetts

32.1 INTRODUCTION 32.1.1 What Is an AMHS? In order to stay competitive, integrated circuit (IC) manufacturers must continually improve the productivity of their factories. Increasing wafer size as well as a trend toward larger fabs with thousands of wafer starts per day are two methods that IC manufacturers use to minimize their manufacturing costs. To support the material logistics requirements of these factories, companies have turned to automated material handling systems (AMHS) (Fig. 32.1) to ensure that the right material is delivered to the right place at the right time. An AMHS comprises a set of components utilized to store and move materials from one place to another in a factory without the need for human intervention. Stockers, a key component of AMHS, are placed in each bay of the factory and are utilized to store carriers as well as to act as a connection point between distinct transport systems. The material movement in an AMHS is accomplished by transport systems that usually take the form of an overhead hoist transport (OHT), overhead shuttle (OHS), automated guided vehicle (AGV), rail guided vehicle (RGV), or conveyor system.

32.1.2 Drivers Behind AMHS There are several drivers behind the move to the fab-wide automation of material transfer. These drivers include personnel utilization, ergonomic considerations, risk reduction, improved tool utilization, and reduced manufacturing cycle time. Personnel Utilization. It is often not practical to provide the necessary number of employees or aisle space needed to support the manual movement of material between bays in fabs. For example, consider a 40,000 wafer start per month (WSPM) factory manufacturing a chip that requires 450 process steps. For such a factory, one can calculate the number of moves per hour = 450 process steps × 40,000 WSPM × (1/25 wafers per lot) × (12 months/year/365 days/year/24 hours/day) × (safety factor = 2) = ~2000 moves per hour. If one assumes that an employee can move on average six moves per hour, 200 employees would be required per shift just to move material. Minimizing the number of employees dedicated to menial tasks such as material movement is one of the drivers of AMHS.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

32.1

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.2

AUTOMATED MATERIAL HANDLING SYSTEM 32.2

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 32.1 An automated material handling system. (Courtesy of Brooks Automation.)

Ergonomic Considerations. A 200-mm wafer carrier weighs approximately 10 lb and a 300-mm wafer carrier weighs approximately 20 lb. While an individual can easily lift these weights infrequently, experience in 200-mm fabs has shown that repetitive stress injuries result when individuals carry and frequently place 200-mm carriers to and from process tools. Therefore, with the conversion to 300 mm, most companies determined that it would be ergonomically unsuitable to have manual transport of carriers. Risk Reduction. In 2005, the value of a carrier of wafers can vary from $10,000 to $1,000,000. The risk of human error causing a carrier to be dropped is another of the key concerns leading fabs to implement AMHS systems. Tool Utilization. Ten to twenty percent of a semiconductor fab’s output is often lost due to tools sitting idle waiting for material to be delivered. Manufacturers view automation as a means of eliminating variability in delivery times and improving tool utilization. Improved tool utilization through the use of automation can result hundreds of millions of dollars of savings over the life of a factory. Manufacturing Cycle Time. By improving tool-to-tool delivery time and providing a method for automatically and predictably scheduling workflow, AMHS offers the potential of reducing the manufacturing cycle time. Cycle time is an important metric for semiconductor fabs because faster time to market or faster delivery time of product to customers has a significant impact on the value of that product and simultaneously enables the fab to achieve faster cycles of learning when trying to raise the yield of a particular product or technology.

32.2 PRINCIPAL COMPONENTS OF AN AMHS An AMHS is utilized to transport and store carriers within a semiconductor factory. There are a variety of carriers as well as AMHS components utilized in the semiconductor industry each of which has particular usage characteristics. The AMHS components can be broken into three categories— the storage system, the transport system, and the software that controls the overall system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.3

AUTOMATED MATERIAL HANDLING SYSTEM AUTOMATED MATERIAL HANDLING SYSTEM

32.3

32.2.1 Wafer Carriers As wafer sizes have evolved over the last few decades from 3 in or smaller wafers to state-of-the-art 300-mm wafers, the carriers that contain them have also changed. With the advent of 200-mm semiconductor production in the early 1990s, a significant emphasis was placed on designing carriers that could be automatically moved through a factory with an AMHS. This philosophy was extended with the design of 300-mm carriers that were envisioned from the start to be optimized for AMHS. 200-mm Carriers. There are two cleanroom concept philosophies for 200-mm fabs that dramatically impact the style of carrier utilized—standard mechanical interface (SMIF) and open cassette. SMIF. A SMIF factory utilizes enclosed carriers that are opened by a standard load port on each tool. In addition, each process tool in a SMIF factory contains a minienvironment that provides a clean environment for the wafers once they have been removed from the carriers. SMIF carriers are well suited to AMHS because they have a common automation interface as well as because the wafers are kept isolated from any potential contamination that might be generated in the movement of the carriers through the fab. Open cassette. Open cassette factories utilize wafer carriers in which the wafers are exposed to the environment. As such, an open cassette factory must be kept cleaner than a SMIF factory. Open cassettes may be transported by themselves or placed in a sealed storage box prior to transport. One of the key disadvantages to open cassettes and their storage boxes is that they were not designed with automation in mind. Therefore, custom interfaces and custom robots must be utilized to move open cassettes into and out of automated material handling systems. 300-mm Carriers. With the transition to 300 mm a significant amount of effort was placed into standardizing the style of carrier utilized by fabs worldwide. Ultimately, a minienvironment friendly, automation ready, integrated carrier called a front opening unified pod (FOUP ) was selected as the industry standard. Similar to the 200-mm SMIF concept, the 300-mm FOUP seals the wafers in a controlled environment. Additionally, the same style of robotic handle used on SMIF carriers is utilized to enable FOUPs to be automatically transported through the factory. The difference between the FOUP and SMIF concepts primarily exists in two areas—(1) the door is on the front of the FOUP while it is at the bottom of the SMIF carrier and (2) the FOUP contains an integrated wafer cassette, while a SMIF container has a removable wafer cassette. 32.2.2 Transport Systems There are four primary styles of transport systems used in factories today: OHT, OHS, RGV, AGV, and conveyor systems. (Fig. 32.2) Vehicles that move carriers within a process bay are known as intrabay transport systems and those that move carriers between bays are known as interbay transport systems. Overhead Hoist Transport. An OHT is a vehicle that travels at ceiling height on a rail above the load ports of the tools and has the capability to raise and lower a carrier onto these load ports. OHT systems are primarily utilized in 300-mm factories; however, they can also be utilized for 200-mm SMIF fabs. One key advantage of the OHT is the fact that it does not utilize any fab footprint. Additionally, with appropriate sensors, an OHT can be used simultaneously with operators without worry of operator injury. Another key benefit of OHT systems is that they are relatively flexible to support changes in a factory layout. Lastly, as will be discussed later in this chapter, an OHT is the only transport technology that is practical in a unified AMHS. Overhead Shuttle. An OHS travels at ceiling height on a rail and transfers carriers from stocker to stocker. In other words, OHS is used as an interbay transport system. OHS systems are utilized in 200-mm and 300-mm factories. An OHS holds one or two carriers and is often used in conjunction with an OHT, RGV, or AGV to support intrabay moves. There are two styles of OHS—one utilizes an on-board robot to transfer carriers from a stocker to the OHS, and the second utilizes a robot located inside of the stocker to load and unload carriers.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.4

AUTOMATED MATERIAL HANDLING SYSTEM 32.4

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 32.2 Overhead transport (left), automated guided vehicle (right). (Courtesy of Brooks Automation.)

Rail Guided Vehicles. RGVs are ground-based vehicles that travel on a rail in the floor. RGVs can be used for interbay as well as intrabay delivery. RGVs are typically the fastest of the different styles of transport systems and therefore have often been utilized for the bays with the highest move rate requirements. One limitation of RGVs is the fact that they cannot coexist with fab personnel due to safety considerations. A second limitation arises from the inflexibility of RGVs to be moved to support layout changes within the fab. RGVs were utilized in 200 mm fabs but are increasingly being replaced with OHTs for 300 mm fabs. Automated Guided Vehicles. AGVs are ground-based vehicles that can be programmed to travel anywhere in the fab. AGVs are used for both interbay as well as intrabay deliveries. AGVs are slower than most other material handling systems; however, they are the most flexible support layout changes. With some limitations, AGVs may temporarily be utilized in bays in which fab personnel are working. AGVs were utilized in 200 mm fabs but are not commonly found in 300-mm fabs. Conveyors. Roller-based conveyor systems are placed at ceiling height and are utilized to transport both 200-mm and 300-mm carriers. While slower than many other material handling technologies, conveyors can support a high throughput of materials due to the fact that the carrier movement is not limited by a limited number of vehicles. Conveyor technology is typically utilized for pointto-point applications such as the delivery of carriers between two separate fab buildings; however, fabs are currently considering applying conveyors in conjunction with OHT in high-throughput areas of the fab. 32.2.3 Storage Systems Stockers. Stockers are the traditional system utilized by fabs to store bulk amounts of carriers (Fig. 32.3). Stockers consist of one or more input/output ports, a series of shelves in which carriers can sit, and a robotic system that enables the carriers to be delivered to and from the shelves. Stockers come in a variety of shapes and sizes, and their capacity can range from as low as 50 carriers to multifloor systems that can hold over 1000 carriers. There are two primary types of stockers available in fabs today—cartesian and carousel. Cartesian. Cartesian stockers have a robotic arm that moves along at least three axes and transports carriers from the input/output port to vertical rows of shelves located within the system. Cartesian stockers are the most prevalent systems in 200-mm and 300-mm factories today. Typically,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.5

AUTOMATED MATERIAL HANDLING SYSTEM AUTOMATED MATERIAL HANDLING SYSTEM

32.5

FIGURE 32.3 A 300-mm FOUP stocker. (Courtesy of Brooks Automation.)

these stockers are placed at the end of each process bay. However, with the advent of unified transport systems for 300 mm, fabs are remotely placing stockers and sharing them across multiple bays. Carousel. Carousel stockers store their carriers on rotating shelves that either move in the horizontal or vertical direction. Carousels offer better storage density than cartesian stockers, and due to their single axis of motion, are more reliable. Traditionally, carousels have been utilized for semiautomated applications in fabs (such as wafer starts and parts storage); however, 300-mm factories are now starting to utilize carousel stockers in fully-automated applications in which they are interfaced with the OHT. Under Track Storage (UTS). UTS is a storage option that can be used with OHT installations (Fig. 32.4). UTS consists of a shelf located below the OHT track on which carriers can be stored. UTS offers three significant benefits—(1) it is a zero-footprint storage solution, (2) it is highly reliable, and (3) it can improve the efficiency of the AMHS. AMHS efficiency is improved with UTS because carriers for intrabay moves can be stored near the next process tool, and thus the need to return the carrier to a stocker is eliminated. UTS therefore can be used to buffer surges in requested AMHS moves throughout the factory. This approach not only reduces the stocker utilization but can reduce congestion of the OHT vehicles since the UTS provides several interface points for the OHT instead of the two interfaces typically available at a stocker. 32.2.4 Software Control In order to provide an AMHS instead of a highly mechanized set of modules, sophisticated software systems must be deployed to control the AMHS hardware. At a bare minimum, a material control software (MCS) must be utilized to translate operator requests into move commands that can be understood by the AMHS. With advanced 200-mm factories as well as 300-mm factories, the MCS is supplemented with scheduling and dispatch software that analyzes the status of all materials in the factory and triggers the execution of “where” each lot should be delivered as well as “what” operations should be performed next.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.6

AUTOMATED MATERIAL HANDLING SYSTEM 32.6

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 32.4 UTS-under track storage system. (Courtesy of Brooks Automation.)

Material Control Software. The MCS is a centralized real-time system that controls the transport and storage of lots, reticles, and other materials in semiconductor fabs. The MCS translates instructions from operators or other software systems into commands that the material handling equipment understands. Additionally, the MCS includes a database to identify and track material in the fab. Advanced tracking, batching, space partitioning, material starvation prevention, and contamination prevention algorithms are required in an MCS to ensure factory optimization. Along with a 99.999 percent availability required for a mission critical software system, dynamic expansion and reconfiguration is also required in an MCS to enable the constant changes that occur in a fab. Scheduling and Dispatch Software. The scheduling and dispatch system analyzes the state of the factory and triggers moves within the MCS to improve flow, reduce WIP, and increase on-time deliveries. The current status of the fab is continuously reviewed and the software determines when lots should be started and completed and how best to balance customer shipping requirements versus minimizing inventory levels. Rules are employed within the scheduling and dispatching software to optimize the performance of individual bays but also to consider more strategic overall aims (such as inventory levels or on-time delivery targets) when selecting a lot to process. As improvements are made to the overall dispatching, logic and dispatch policies are applied consistently, orders move more smoothly through production, resulting in reduced cycle time and cycle time variability as well as reduced operational variability across crews and shifts.

32.3 THE DESIGN OF AN AMHS In building a semiconductor fab, several decisions must be made regarding the layout of the fab and how that layout will impact the AMHS. Given the high cost of semiconductor factories, multiple layout approaches are usually considered, and complex simulation models are executed to determine which approach is most appropriate given the particular business constraints of the company. 32.3.1 Simulation Following the initial approval of a fab, the first phase of activity traditionally centers around the fundamentals of how the fab will operate. In this phase, decisions such as how big the fab will be,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.7

AUTOMATED MATERIAL HANDLING SYSTEM AUTOMATED MATERIAL HANDLING SYSTEM

32.7

exactly what mix of products will be run, and what kind of layout will be used are made. In addition, operational philosophies are determined (such as whether the fab is going to try to minimize the cycle time or maximize wafers out and whether the fab is going to support research and development or 100 percent production). One way in which automation systems play a key role in this phase is with the use of simulation tools to analyze and optimize fab operational philosophies. For example, simulation tools such as Brooks Automation’s AutoSched and Static Capacity Modeler products enable the fab planner to determine which layout and equipment set works best, to analyze the impacts of differing levels of material handling automation, to forecast tool and operator requirements as well as to provide a visual representation of how the factory will operate. 32.3.2 Process Tool Layout Methodologies Different fabs choose different tool layout methodologies and there is no consensus on which approach is optimal. Nonetheless, there are several approaches that are commonly utilized for process tool layouts. Bay and Chase. In a bay and chase configuration, the process tools are mounted along walls in the aisles, which are typically half the width of the fab in length and extend off a long central aisle. This construction creates process bays—the cleanroom side of the wall, and chases—the tool side of the wall, hence the name. Operators access the tools from the bay side, and maintenance technicians access the tools from the chase side. The chase side is commonly called the “gray area” due to its less clean status (Fig. 32.5). Ballroom. The ballroom layout does not have the walls of the bay and chase layout. Instead, the process tools are all located within one large room, hence the name. As this cleanroom is typically dirtier than one found in a bay and chase fab, many ballroom configurations require each tool to have a clean minienvironment in which the wafers are handled. When minienvironments are utilized, wafers are transported and stored in SMIF or FOUP carriers that allow them to be transferred into the tool’s minienvironment without being exposed to the cleanroom atmosphere. 32.5 Bay and chase configurations. There can be considerable variation in the process FIGURE (Courtesy of Brooks Automation.) tool arrangements with the ballroom layout. Tools are generally arranged in rows but each row may not be the same length nor have the same regularity as in the bay and chase layout. It is possible to place the transport above the process tools in the ballroom but maintenance and move in requirements must be kept in mind. In this fab type, the stockers may be located in proximity to the tools they service making them appear to be located randomly about the fab. At the other end of the spectrum a ballroom fab may have exactly the same layout as a bay and chase fab except that there are no physical walls. Farm Layout. The term farm layout refers to one methodology of grouping process tools within the fab. In the farm layout, process tools of a particular type are all colocated within the same bay or adjacent bays of the bay and chase or in the same general area of the ballroom. Architect construction firms favor this layout because it simplifies the building of the fab and the facilities infrastructure required to support the process tools. With few exceptions (some time-sensitive steps are grouped, for example, cleaning before diffusion is frequently done in the diffusion bay) only one process step is preformed on a wafer each time it visits a particular group of process tools. This layout puts a high load on the interbay portion of the material handling system since a wafer lot must be moved from one bay to another after each process step. The grouping of tools also results in very heavy traffic to and from the metrology area.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.8

AUTOMATED MATERIAL HANDLING SYSTEM 32.8

FAB YIELD, OPERATIONS, AND FACILITIES

Hybrid Layout. The hybrid layout results when metrology tools are removed from the metrology bay of a farm layout and collocated with the appropriate process tools. The hybrid layout reduces the load on the interbay system (at the expense of the intrabay system), eliminates the heavy traffic metrology area, and has the potential to reduce the overall wafer manufacturing process time. Hybrid layouts require a larger number of metrology tools than farm layouts but that cost is offset by its somewhat smaller footprint requirement. Simulations show that fabs with a hybrid layout could potentially reduce the manufacturing cycle time by 10 to 15 percent of fabs with farm layouts. Modified Hybrid. The modified hybrid layout results when a variety of process tools along with metrology tools are grouped to allow a few (four to six) sequential steps to be performed in the same bay or area. For example, strip and clean tools can be located in the same area as implanters so that photoresists can be stripped and the wafers cleaned before they are sent to the next process step in diffusion or litho. In addition, metrology tools can also be included in the grouping of process tools. The modified hybrid layout further reduces the load on the interbay system (at the expense of the intrabay system) and eliminates the heavy traffic metrology area. It requires a larger number of process tools and is more expensive to construct than farm or hybrid layouts. 32.3.3 AMHS Layout Methodologies Segregated Systems. A segregated system is an AMHS in which interbay and intrabay transport systems are separated. In the segregated system, an OHS is typically used for interbay transport and the OHT is used for intrabay transport although other combinations with person guided vehicles (PGVs), AGVs, and RGVs are possible. For the segregated system, each bay or set of linked bays has a dedicated intrabay system, and each intrabay system operates independently from what is happening in other bays. Material flow in a fab with segregated AMHS. The material flow for a segregated system is essentially the same in 300-mm and 200-mm fabs. A carrier is transferred from a process tool to a stocker dedicated to that process area. The carrier is then sent from that stocker to the stocker dedicated to the process area where the tool that will perform the next process step is located. The carrier is pulled from the stocker when the process tool is ready. When the process step is complete, the sequence repeats. When more than one process step is performed within a bay or area, the carrier may move directly to the next process tool without returning to the stocker; however, the move sending the carrier to a tool cannot begin unless there is an empty load port on that tool. The higher the percentage of direct tool to tool moves, the lower the move rate the AMHS must support. The benefit of using direct tool-to-tool moves is significant. Consider the simple case of lots moving to a tool that has a 70 percent utilization. By definition the tool will have no material available 30 percent of the time, if it has two load ports, one will be empty 51 percent of the time and if it has three load ports, one will be empty 66 percent of the time. The use of tool groups where any one of several tools can perform the same process steps dramatically increases the probability of being able to make a move directly to the next tool. Simulations of various fabs have shown that, on average, 80 percent of all intrabay moves could be made directly tool to tool avoiding the additional move of returning to the stocker. A segregated AMHS has several detractors compared to an alternate approach known as a unified system. These include—increased numbers of stockers, longer delivery time, and throughput limitations. Unified System. In a unified system the transport for the intrabay and interbay systems is combined, and a single system is used for all transport. This allows lots to be moved directly from tools in one bay to tools in another without passing through a stocker. There are three types of unified AMHS. They are: • Partially unified: This is a segregated AMHS with several groups of bays linked via OHT. • Fully unified: This is an AMHS using only OHTs for both inter- and intrabay moves. Lots can be moved to and from any tool in the fab without going through a stocker. • Combined unified: This is a full unified AMHS supplemented with a loop of OHS linking the stockers and used to reduce congestion on the OHT track. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.9

AUTOMATED MATERIAL HANDLING SYSTEM AUTOMATED MATERIAL HANDLING SYSTEM

32.9

Material flow in a unified system. The integrated track of the unified system allows moves to be made directly between any two load ports in the fab. However, because a move to a tool cannot start unless a load port on the destination tool is open, some completed lots are moved to a stocker or to a UTS before being moved to the next process step. That storage location is generally in close proximity to the bay or process area in which that tool is located; however, in theory any storage location can service any tool. The exception to this material flow is for the case of hot lots. Some fabs hold a tool load port open when a hot lot is expected, allowing the carrier to be moved directly from one tool to another. Eliminating the need for transferring through stockers dramatically reduces the hot lot delivery time for unified systems. Delivery times for normal lots are also improved in a unified system since at most they only pass through one stocker during a tool-to-tool move. Therefore, unified systems reduce the number of AMHS moves required for each “process step” move by one-third for normal lots and two-thirds for hot lots compared to a segregated system. OHT track layouts in unified bays. In fabs with unified AMHS, the bay throughput is not limited to the throughput of the stockers as with segregated AMHS. Carriers from any stocker can be delivered to any bay, and carriers from several stockers can be sent to a single bay. The bay throughput is limited by the ability of the AMHS to move carriers through the bay as long as the capacity of the process tools is not exceeded. Typical applications for unified layouts. Unified AMHS works well with hybrid or modified hybrid tool layouts. In a hybrid layout, metrology tools are placed in the same bay as the process tools they support. This increases the demand on the intrabay material handling system. In a modified hybrid layout, metrology tools and other process tools are distributed throughout the fab in the same bays or areas as the process tools they support. Therefore, a route might involve several sequential process steps in the same bay. This further increases the demand on the intrabay transport system and reduces the loading on the interbay movement system. Benefits of unified transport. There are two major benefits of unified transport: Shared storage, process and metrology tools across bays. Because unified transport allows bays to be linked, it is possible to reduce the number of stockers and process and metrology tools by sharing them across bays. In turn, this allows greater flexibility in the placement of stockers and process and metrology tools. Faster delivery of lots. Unified transport is capable of delivering both production and hot lots faster than segregated transport. The main reason is that there are fewer handoffs, and only one stocker is required for a move between tools.

32.4 OPERATIONAL CONSIDERATIONS With the cost of 300-mm factories approaching $3 billion in 2005 and the AMHS increasingly being recognized as a mission critical application, several key operational considerations must be made in the evaluation and selection of an AMHS. At a macrolevel, fabs must select an AMHS that meets their performance requirements while minimizing the overall cost of ownership of the system. 32.4.1 Performance Requirements The International Technology Roadmap for Semiconductors (ITRS) highlights the roadmap for key performance criteria for AMHS (Fig. 32.6). Some of the key criteria to note are—average delivery time and transport throughput: Average Delivery Time. Average delivery time is the average time it takes for a carrier to be delivered to a load port after a request is made for the carrier to be moved to that load port. In general, factories are driving toward average delivery times of 5 min or less. Average delivery times can be somewhat reduced by adding additional vehicles and tracks; however, sophisticated software routing algorithms are required to prevent the increased amount of vehicles from running Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.10

AUTOMATED MATERIAL HANDLING SYSTEM 32.10

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 32.6 International Technology Roadmap for Semiconductors key metrics for AMHS. (Courtesy of International Sematech.)

into traffic jams. Additionally, since delivery time is significantly impacted by the layout and process flow of each individual factory, it is critical that the layout is optimized to support fast delivery times in an automated factory. Transport Throughput (Moves/Hour). The transport throughput is the number of moves per hour between load port pairs in the factory. The ITRS indicates that while segregated AMHS are common today, unified AMHS will be required for future factories. For an assumed 40,000 wafer start per month factory, the ITRS indicates that 5000 moves per hour will be required by unified systems. To increase the overall number of moves per hour, typically one must increase the number of vehicles in the fab. Once again, with increased vehicles it is absolutely necessary to have software routing algorithms that can dynamically adjust the travel path of vehicles to minimize traffic concerns. 32.4.2 Cost of Ownership The cost of ownership for an AMHS is driven by three primary factors—equipment cost, overall equipment effectiveness (OEE), and operations cost. Equipment Cost. The cost of an AMHS can vary greatly depending on the wafer size, factory size, and level of desired automation. In 2005, typical 200-mm factories that utilize only interbay automation may require between $10 million and $30 million of initial capital outlay for an AMHS installation and 300-mm factories that require both interbay and intrabay automation often require $25 million to $50 million worth of AMHS. Oftentimes, the installation is made in two to three phases with the primary phase consisting of the basic AMHS infrastructure in addition to enough vehicles and storage locations to support the early ramp of the fab, while the additional phases consist of adding incremental vehicles and storage locations. Overall Equipment Effectiveness. The OEE of an AMHS is driven by the performance as well as the availability of the system. As mentioned earlier in the chapter, the primary metrics for performance

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.11

AUTOMATED MATERIAL HANDLING SYSTEM AUTOMATED MATERIAL HANDLING SYSTEM

32.11

are average delivery time and transport throughput. The availability of an AMHS is measured by the reliability of the system (mean time between failures, or MTBF) and the maintainability of the system (mean time to repair, or MTTR). It is important to note that MTBF and MTTR metrics are most critical at a system level for an AMHS and not at a component level. For example, if an individual vehicle fails and prevents the delivery of a particular carrier, it is a far less severe problem than if a vehicle fails and shuts down an entire bay or shuts down the entire fab. Operations Cost. The operations cost of an AMHS is made up of the utilities and consumables needed to operate the system, the service and spare parts cost required for the system, and the cost of taking up the valuable factory footprint by the system. While AMHS do not typically utilize consumable parts, they do require a significant amount of electricity. In particular, due to their relatively inefficient power transfer method, inductively powered OHT systems can utilize in excess of $1 M/year of electricity in a large 300 mm fab. Service and spare parts costs can also be significant due to the large number of moving parts and the need to have multiple technicians available to solve problems quickly due to the mission critical nature of an AMHS. Lastly, the AMHS may require a large amount of factory footprint and thus the physical size of the AMHS may greatly impact the overall operations cost to the factory. Due to the high costs of operating a cleanroom, as well as the desire to fit as many process tools as possible into the fab, factory planners are increasingly utilizing a variety of zero-footprint AMHS designs such as OHT and UTS to minimize the impact of the AMHS footprint on operations costs.

32.5 FUTURE TRENDS In the semiconductor industry AMHS were first utilized as efficient storage systems (stockers), then as a means to improve operator efficiency (stockers plus interbay transport), and are now being used to replace manual transport entirely (stockers plus interbay plus interbay transport). In today’s fabs, however, human intervention is still required to support error handling, complex decision making, as well as to serve as a backup for relatively frequent AMHS failures. In the future, the trend will be for the AMHS to address each of these human-based operations automatically. Error handling and complex decision making are frequently required in a fab due to the fact that the process flow is complex (many hundreds of steps), reentrant (certain tools are used multiple times to process a wafer), constantly changing (process recipes are frequently adjusted to improve yields and performance) and must be robust enough to support repeatable yields across multiple process tools. Additionally, customer demands often require the mix of products running in the fab to change frequently. In order for an AMHS to automatically support the decisions required in such a dynamic environment, increasingly sophisticated software systems are being deployed. These systems range from rule-based engines in which the AMHS reacts to a set of predetermined events to learning algorithms in which the AMHS adapts its behavior over time to optimize the overall system performance. While AMHS designers continually strive to improve the physical reliability of the system in order to minimize failures, increasingly fabs are looking for fault-tolerant systems that can avoid system-wide failure in the event of an individual component failing. For example, in a unified AMHS, in the event that a vehicle fails in a bay, additional vehicles can be dispatched to service that bay and to prevent the overall system performance from degrading. As another example, a redundant MCS architecture is often utilized to ensure that if one instance of the MCS fails, a backup system is immediately available. Lastly, fabs are pushing their AMHS designs to support higher throughputs, faster delivery times, larger numbers of wafers per month, smaller lot sizes, and shorter cycle times. To support these needs, it is generally recognized that a unified AMHS with sophisticated software routing algorithms is required. However, the design and implementation of novel concepts such as single wafer transport AMHS, fab-wide conveyor systems, and linked process tool architectures that enable tool-to-tool wafer transport rather than carrier transport are all being considered for future AMHS designs.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH32.qxd

04/04/2005

21:03

Page 32.12

AUTOMATED MATERIAL HANDLING SYSTEM

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 33

CD METROLOGY AND CD-SEM Ram Peltinov Mina Menaker Applied Materials PDC Israel

33.1 INTRODUCTION One of the key drivers of the semiconductor industry is constant improvement, which is based on the ability to measure what is done. In the submicron world, this is not a trivial thing to do. Critical dimension (CD) metrology is a basic concept in manufacturing that helps keep a process stable. The measured critical dimension is used for statistical process control (SPC) in which a process is kept within the specification limits of the design and within control limits to maintain stability. The CD-SEM monitors a range of features—(1) lines/space/pitch [one dimensional (1D)] and also to a lesser extent minimum distances between features that are becoming more common and important, (2) round features (2D), and (3) depth/sidewall angle information (3D). The layers that are measured can be any layers with topography, such as all patterned photoresists after develop inspection (ADI) and all etched wafers after etch inspection (AEI). Usually the monitored layers are: • • • • •

Shallow trench insulator (STI) ADI/AEI Gate ADI/AEI Contact ADI/AEI Metal 1, 2 ADI/AEI for copper (trench 1, 2 ADI/AEI) Via 1, 2 ADI/AEI

The CD measurements are used both for engineering and production in the fab where engineering tasks require relatively more data than they did in the past due to optical proximity correction (OPC) characterization. 33.1.1 Engineering Improving a Process. The advancements and shrink of semiconductor devices require constant improvement that must go along maintaining stable CDs. The CD-SEM is the enabler of this need. Also, there is a need to introduce new metrics to control a process in places where the CD is insufficient. Developing a New Process. The aggressive semiconductor roadmap pushes us to develop new processes that will enable more transistors and more speed for the same IC space. The search for new

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

33.1

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.2

CD METROLOGY AND CD-SEM 33.2

FAB YIELD, OPERATIONS, AND FACILITIES

materials, smaller design rules, and advanced structures requires a huge amount of CD data to develop, integrate, and stabilize these processes. Litho and Etch Optimization. In order to decide what are the best focus and exposure scanner conditions and define your process window, you need a large amount of CD data that represent each combination of focus and exposure shot, as it is represented in a focus exposure matrix (FEM) wafer. This optimization is also true for etch conditions settings where the litho to etch bias should be studied before being turned over to production. 33.1.2 Production Controlling a Process. The major task is controlling the process according to device specifications and tight statistical control limits for the desired chip performance and yield. Advanced Process Control (APC). In today’s environment tight control requires advanced techniques to keep a process in control within a short and fast feedback loop. These automatic loops exist forward to the etcher and backward to the scanner. The data fed into these loops can be the CDs from a CD tool, layer thickness, and defect information.

33.2 FUNDAMENTAL CD METROLOGY CONCEPTS The path for understanding the fundamentals of CD metrology is through the definition of the qualities required for a reliable measurement. The three key factor qualities are—precision, accuracy, and sensitivity. Precision: The closeness of the agreement between independent test results, on the same feature, obtained under the same conditions. This value defines the amount of “uncertainty” or “confidence level” that the reported value contains within a known probability. For example, 100 nm ± 1 nm, 3 sigma, means that in a probability of 99.7 percent (assuming the error to be random and therefore a normal distribution is obtained) the value measured is between 99 and 101 nm. Without knowing this precision value, the measurement would be insignificant. The precision of a metrology tool is commonly divided into repeatability and reproducibility to learn about the source of the error (see Sec. 33.4.1). Precision, however, is not enough; a metrology tool must also be accurate. Accuracy: The closeness of a measured value to the true value. For a CD-SEM, this is the range between the reported value and the real value. The problem with this quality in the semiconductor world is the method of determining the true/real value (Fig. 33.1). The common way is by calibrating the tool to a traceable standard that is certified by different means in a laboratory.1,2 Being accurate on a certain feature type/“size”/material, though, doesn’t mean that the same quality is maintained in the adjacent slightly different feature. The quality of sensitivity is needed to ensure that we will continue being accurate through a known range. Sensitivity: The capability to distinguish between small changes within a given range. For a CD-SEM, it means the ability to “see” small differences in critical dimensions in a linear manner and report them. The sensitivity quality is complementary to precision. A tool that is both precise and sensitive, with the correct calibration, can be considered as accurate. Now that we understand precision, we can define one of the most fundamental terms for process control—the (tools) precision to (process) tolerance ratio (P/T). The process tolerance is the permitted margin in the process that will ensure the proper performance of the device. The typical tolerance is 10 percent of the nominal CD, and the typical P/T ratio, as

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.3

CD METROLOGY AND CD-SEM CD METROLOGY AND CD-SEM

33.3

6 4 2

Accuracy

8

Avg measured value

Real value

Number of observations

Accuracy

Precision

0 80

FIGURE 33.1

90

100 110 Measurement (nm)

120

Precision

Accuracy versus precision graph and illustration.

defined by the ITRS, is between 0.1 and 0.2. This means that the tool precision is left with a 1 percent margin of the nominal CD. For example, when a design engineer defines work in dimensions below 50 nm, he is dealing with tolerances in the range of approximately 5 nm. In the case where he has a 10 percent precision tolerance ratio, it implies that a CD-SEM with precision in the range of less than 0.5 nm is required.

33.3 BASIC CONCEPTS OF CD-SEM SYSTEM The following is a list of CD-SEM system components. 1. External wafer handling: For the insertion of the wafer in the tool 2. Main chamber: The SEM operates in a vacuum environment; therefore there is a need for a sealed chamber and a vacuum pump system 3. Stage: Enables the movement of the wafer within the chamber 4. Load chamber: A small chamber to insert and remove wafers quickly 5. Optic microscope: Enables accurate navigation to the right location 6. SEM column: Enables a close examination of the wafer through SEM magnification and resolution qualities 7. Computers: For controlling navigation, wafer handling, measure algorithms, recipe programs, and the like 8. Operating console: The user interface The CD-SEM concept can be divided into three categories: 1. Reaching the exact required location on the device 2. Acquiring the SEM image for measurement 3. Applying the right algorithm to measure the required dimension 33.3.1 Reaching the Exact Location This involves a series of alignments. First, the wafer is inserted into the load position in the load chamber. (The load chamber is a small chamber that allows the insertion of the wafers in two steps while maintaining the vacuum level in the main chamber.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.4

CD METROLOGY AND CD-SEM 33.4

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 33.2

An optic pattern recognition example.

In the load chamber there is a mechanooptical prealigner device that aligns the wafer to be inserted in the same rotation angle and offset into the main chamber by finding the conventional flat area or notch in the wafer (the most common today is the notch for 8- and 12-in wafers). Once the wafer is in the main chamber on the stage, the previous alignments allow us to navigate correctly in the field of view (FOV) of approximately 0.5 mm and identify a prelearned pattern mark under an optic microscope (Fig. 33.2). The distances between the assumed position of the mark and the actual position are used to further calculate the wafer positioning errors and provide the capability to navigate with a small error of approximately 1 to 3 µm. This phase is known as global alignment (GA); it is common to align through two to four alignment marks. At this level of navigation accuracy, it is possible to identify the required feature in a SEM image FOV of 5 µm or below. At this point the stage is static and the following sequence takes place: In the SEM field of view (Fig. 33.3), the SEM pattern is identified as an anchor reference.

FIGURE 33.3 The basic CD-SEM measurement sequence by Applied Materials.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.5

CD METROLOGY AND CD-SEM CD METROLOGY AND CD-SEM

33.5

From this mark two vectors are obtained—first, the location where SEM autofocus is performed and then (once the focus value is known) the scan for measurement in the exact required location— acquiring the SEM image for measurement. 33.3.2 The SEM Image for Measurement The electron beam is accelerated in the column and decelerated to land on the specimen with the required energy (typically 300 to 1000 V). The principle of the SEM relies on the idea that electrons that scan the edge of a feature emit more secondary electrons than the surface area. This quality enables the identifying of the location of the edge to some extent. The beam scans in the x direction, and by adding scan lines in the y direction the SEM image, referred to also as the signal, is built in the required area. Signal. A signal is the electron current intensity per location that hits the detector for each electron beam scan line of the target area (Fig. 33.4). Usually one scan of each line is not enough to get an image with a good signal-to-noise ratio (although it depends on the scan rate and the speed of the scan), and the image acquisition requires several frames. Frame. A frame is a scan of all the target area. The number of frames (thus the number of scans per scanned line) is determined by the duration of the scan, given a constant scan speed. 33.3.3 Applying the Right Algorithm to Measure the Required Dimension The basic CD-SEM algorithm can be divided into three sections—edge detection, required point of the edge definition, and the CD measurement between the defined edges (Fig. 33.5). The first step is the detection of the edge location. The SEM image is analyzed and filtered to define the edges that are suspected as valid edges. Once the edge location is achieved, the intensity and first derivative of each scan line around the chosen edges are analyzed, and a threshold is defined in order to locate the right point on the edge that represents the bottom or top of the line. Then these points are aggregated from the left edge and the right edge. The results are welldefined edges. The last part, the distance between these two edges, can easily be calculated and reported as the CD of the line. It is important to have a reliable algorithm that will catch the same location on the edge; while it is understood that this point doesn’t necessarily represent the absolute real location, to some extent any change in the monitored CD will represent a real relative change (see Fig. 33.6). The absolute change can be in the magnitude of 10 to 20 nm. Today, when the gate size can be in the range of 50 nm, this may be not sufficient.

Scanning E-beam

Specimen Waveform (‘Signal’) display

Secondary electrons detection FIGURE 33.4

Gray scale (‘Image’) display The SEM signal.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.6

CD METROLOGY AND CD-SEM 33.6

FAB YIELD, OPERATIONS, AND FACILITIES

CD SEM algorithm flow Top Bot 1 Bot 2

1. Measurement scan

12

34

4. Line fit FIGURE 33.5

2. Averaging

CD Edges bottom (nm)

3. Topographic points

CD top (nm)

Results

1,2

41.5

38.0

Host

2,3

138.9

139.3

Fab SPC charts

5. Results

6. Results transfer

A basic algorithm flow.

33.4 CD-SEM SPECIFICATION AND SELECTION PROCESS The selection process of a CD-SEM, as for any tool in the semiconductor fabrication environment, is done through a set of parameters, of which some are related directly to tool performance and others to the overall commercial appeal of the tool. This section elaborates the most important specifications

FIGURE 33.6 SEM images from left top to bottom right, (1) KrF resist contact hole, (2) Etched contact hole imaged through 15 degrees tilt beam from the left, (3) ArF resist line with standing waves imaged through 15 degrees tilt beam from the right, (4) ArF resist line with standing waves imaged through 15 degrees tilt beam from the down direction. (Courtesy of Applied Materials.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.7

CD METROLOGY AND CD-SEM CD METROLOGY AND CD-SEM

33.7

of tool performance. The tool performance specification for a CD-SEM contains three major groups— metrology performance, SEM imaging capability, and tool productivity. 33.4.1 Metrology Performance Metrology performance is the overall performance of the tool as a measurement tool—that is, its ability to give precise and accurate measurements under different conditions. For example, you expect to get the same reading whether you measure in a different magnification, location in the FOV, day, repetition, or tool. These changes are the basis of many tests done on the CD-SEM. Magnification Linearity. Measures the same line and changes the magnification conditions of the tool (e.g., 100 kx, 150 kx, 200 kx, 300 kx, 400 kx). The expectation is to obtain a less than 0.5 percent change. Field of View Linearity. Measures the same line and changes the location of the line in the FOV (e.g., right, center, left, top, and bottom). The expectation is to obtain a less than 0.5 percent change. Repeatability. The closeness of agreement between independent measurements when these measurements are obtained with the same recipe and measurement algorithm, on the same tool, on the same sample and feature, within a short interval of time. The test includes measurement of the same line over again within a short interval of time (e.g., Rep 1, Rep 2, Rep 3, . . . ).The expectation is to obtain a less than 0.5 nm change. Reproducibility. This is a complementary component to repeatability. It is the closeness of agreement between independent measurements when these measurements are obtained in different loadings at different times, on the same feature. The expectation is to obtain a less than 0.5 nm change.3 Tool Matching. Measures the same line over again within different tools (e.g., tool 1, tool 2, tool 3, . . . ). The expectation is to obtain a less than 1 nm change. Tool matching is the ability to get the same output from a tool set of a tool that can be of the same or a different brand. Total precision (3 sigma) = 3 × ( repeatability)2 + ( reproducibilty)2 + ( tool matching)2 Another factor on which metrology performance is judged is the intrusiveness of the tool in terms of how much interaction with the sample we have or, in other words, how much we change the actual feature. Most of the effects are physical, and the most significant are charging, contamination, and feature slimming. Charging. This is an inherent characteristic of a SEM. The measurement is done by emitting electrons from the column to the specimen (primary electrons) and collecting secondary electrons to an electron sensitive detector. The amount of primary electrons can be controlled by the column, but the emission of the secondary electrons back from the specimen is dependent on the materials, landing energy, and the feature geometry on each location. This makes our ability to maintain an equilibrium of primary versus secondary electrons very challenging. Whenever this equilibrium is not maintained, the specimen becomes electrically charged. This is more critical in dielectric layers where the charge is trapped and cannot dissipate. Most vendors have their own proprietary methods to reduce this phenomenon, including smart scan techniques, special wafer handling designs, and the use of minimum currents. The amount of charging applied by a CD-SEM usually does not affect the device, but does affect the metrology performance by: • Attracting carbons that change the actual feature size • Deflecting the electron beam and causing navigation accuracy issues and incorrect representation of the actual feature, hence producing accuracy issues Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.8

CD METROLOGY AND CD-SEM 33.8

FAB YIELD, OPERATIONS, AND FACILITIES

Contamination. Although the measurement is performed under high levels of vacuum, there are still some molecules of carbon in the chamber. During repetitive exposure to the electron beam, the scanned area attracts these carbons that are deposited to the feature. This has two main effects—(1) The carbon reduces the amount of secondary electrons emitted and (2) they change the real actual size in that location in the magnitude of up to a few nanometers. This change inserts a level of uncertainty to the measurement that affects one’s ability to control the process tightly. Fortunately, this change is small and predictable and can be linearly compensated if needed. Feature Slimming. Feature slimming (also determined as the line shrinkage) is a relatively new phenomenon in which the new family of sensitive photoresists for the wavelength of 193 nm (ArF) reacts to exposure to the electron beam by shrinking the actual size of the feature.4 This effect is stronger with the first exposure, but as it repeats on the same location, the feature shrinkage becomes saturated. 33.4.2 SEM Imaging Capabilities Since the measurement is derived from the image, the SEM imaging capabilities are very important. The CD-SEM is also known as “the eyes in the fab”; when one needs to see how the process looks, a CD-SEM is used. This brings us to the important parameters to evaluate the imaging capabilities, resolution, and signal-to-noise ratio. Resolution. Resolution is the ability to separate and distinguish between two adjacent features. The metric is quantified as the minimum distance in “nm.” This is a very basic parameter to evaluate the SEM, but also a very difficult one. Since the features are very small, special software is used that is based on a fast Fourier transfer (FFT) to determine the resolution of the taken image. Also this software should be adjusted to the target type. There are several types of targets for this use; the most common are from the following materials—Au on carbon (Fig. 33.7), TiN, and latex spheres.

FIGURE 33.7 Resolution target: Mag 200 kx (FOV 0.6 µm) Au on carbon. (Courtesy of AMAT taken with the VeritySEM.)

Signal-to-Noise Ratio (S/N). This is the ratio of the signal intensity to the noise levels. The higher the ratio, the better the image looks. The signal is the peak, and the noise is the nonrelevant junk information that is not related to the sample. The S/N is affected by the amount of frames (Fig. 33.8).

FIGURE 33.8 Resolution target: Mag 200 kx (FOV 0.6 µm) Au on carbon—low versus high S/N. (Courtesy of Applied Materials taken with the VeritySEM.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.9

CD METROLOGY AND CD-SEM CD METROLOGY AND CD-SEM

33.9

Apparent Beam Width (ABW). This is an indirect method to measure the beam width by measuring the edge width of an isolated line that is specially designed with very sharp edges (90°). When the edge is so steep—in theory, if the beam width would be ideally close to zero—there will be no edge signal. Since the beam has a width that is not negligible for today’s structures, the edge width measured is a good estimate for the beam width. There is a special software to calculate the edge width correctly for this application. Today’s apparent beam widths are at the magnitudes of 10 to 12 nm. The resolution of a tool is highly correlated with the electron beam width—the smaller the beam, the higher the resolution. ABW is a method developed by IBM and accepted later by SEMATECH as an important standard.5 Tilt Imaging. Traditionally the CD-SEM is a top down imaging tool that enables two-dimensional analysis. But, the device structures are three dimensional. The capability to tilt the beam enables three-dimensional imaging and the retrieval of three-dimensional information such as depth, sidewall angles, and profile shapes. First, the target location is scanned in two different known beam tilt angles (Fig. 33.9), then the images are registered, and finally an algorithm calculates the depth, sidewall angle, and profile shape through the differences in the edge width.6,7 33.4.3 Productivity In the competitive chipmaker’s environment, it is not enough that the CD-SEM have the best metrology performance and SEM imaging capabilities, but the tool must also be production worthy. The most important parameter to measure the production worthiness is the cost of ownership (CoO). The CoO gathers all the productivity aspects into one number. Generally, this metric is known as cost of ownership per wafer. In the cost part we consider the capital investment, depreciation, foot print (cost of the cleanroom space), service, cost of consumables (usually negligible for CD-SEMs), power, and the cost of operators needed. In the output part we consider throughput, production throughput, and tool uptime, at a given sample rate. CoO =

cost per year = CoO per wafer actual throughput per year

FOV 1 mµ

Dual damascene profile analysis (height /slope) (1127.2/85.39) 1280

No tilt:

1120 960 800 640

Height

480 15° tilt right:

Slope 320 160 0

0

200

400

600

800

FIGURE 33.9 A 3D profile analysis of a dual damascene structure. (Courtesy of Applied Materials NanoSEM 3D CD-SEM.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.10

CD METROLOGY AND CD-SEM 33.10

FAB YIELD, OPERATIONS, AND FACILITIES

Start

End Load

FIGURE 33.10

Alignment

9XMAM

Unload

An example of the measurement sequence scheme for nine sites.

The higher the throughput, the better the CoO. The throughput is divided into two major parts— the time to load and unload the wafer and the measurement period. In a pipeline mode in production, the load and unload time is not so critical, since this action is done while the tool is measuring a different wafer. The measurement period also has two main parts (Fig. 33.10): first, the alignment that is fixed no matter how many sites are measured and second, the actual measurement sequence that is repeated for each measurement site. This period is also known as MAM, since the routine of each measurement site includes the move (stage), acquire (SEM image), and measure (algorithm). To achieve an effective high throughput for a large period of time in production, a robust and reliable recipe automation level is needed. The automation level is maintained by three main factors: Navigation capability: The ability to reach the right location again and again Pattern recognition engine robustness: The ability to operate under process variations without mistaking the right location Measurement algorithm robustness: The ability to measure under process variations and provide a precise measurement The last, but not least, aspect to consider is tool reliability. The CD-SEM is expected to have a very high reliability that is measured by several factors. Availability: The percentage of the total time that the tool is ready for service. The reasons for periods when the tool is not available vary from scheduled maintenance, unscheduled maintenance, and tool failures. Mean Time Between Failures (MTBF): MTBF is defined as failures requiring more than 6 min to recover. Mean Time to Repair (MTTR): This is a metric that measures the service level and is defined as the average time it takes to recover from a failure. Mean Time Between Assists (MTBA): This measures the automation robustness level and the period of time between events that need interference by an operator, such as finding the right pattern or location. An assist I is defined as an action that can bring the tool back to the routine in less than 6 min. For more detailed reliability definitions, please refer to the E-10 SEMI standards.

33.5 FUTURE TRENDS AND CONCLUSIONS The future trends may be already present or altered by the time you read this book due to the dynamics of this industry. The main drivers continue to be the shrinking of design rules and new materials. The road maps of the most advanced integrated circuit (IC) manufacturers are already set for the 65-nm and 45-nm nodes, and the 32-nm node is on the horizon. These will require: 1. Extremely expensive 193 nm/157 nm lithography supporting numerical apertures (NA) higher than one through immersion lenses 2. Advanced mask resolution enhanced techniques (RET) through optical proximity corrections (OPC) and other techniques 3. Very accurate etchers with tight uniformity performance on large silicon wafers of 300 mm or above (450 mm today seems very far away)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.11

CD METROLOGY AND CD-SEM CD METROLOGY AND CD-SEM

33.11

These challenges not only elevate the meteorology importance and the amount of monitoring data needed to develop OPC techniques and to keep the process stable in the future, but also introduce new challenges to the metrology tools. The new photoresist materials for 193 nm/157 nm are more sensitive to the SEM electron beam affecting the measured feature. As dimensions decrease, the process tolerances decrease as well while pushing the precision specifications lower to keep the precision-to-tolerance ratios constant. Also, the dimension decrease brings the feature size closer to a subelectron beam spot size range, although the SEM is already verified as the best solution down to the 32-nm node.8 The rising cost of the work in process pushes for solutions with shorter feedback loops through the integrated metrology information. The CD-SEM is the most common metrology in-line production monitoring tool. Integrated metrology tools are smaller devices that are integrated within the process tool including their interfaces. While a CD-SEM has the capability to provide the best working conditions for a large variety of process steps, the integrated metrology is usually designed for the specific layer, since the host tool is dedicated to that layer, for example, front-end litho, gate etch, silicon etch, dielectric etch, and metal etch. The optical critical dimension (OCD) has the right qualities to fill this need. OCD, known also as “scatterometry,” is a technology for measuring the CD, sidewall angle, and the depth of grating structures. Optical CD metrology is based on specular reflected light measurements (ellipsometry and reflectometry). A light source that can be modulated by wavelength or by angle illuminates grating structures of at least 50-µm diameter. The signal is yielded as a function of the wavelength or angle as a curve; this curve is then best fitted to a library of precalculated curves that represent a range of dimensions for a given stack structure and materials. When this mathematical curve fitting is obtained, the structure dimension is given. The OCD is relatively small and can be integrated with the process tool. It is still quite complicated to set a recipe, but the fact that each tool is set to a certain layer makes it much easier and a one time task. Also the OCD provides the result but not the image that is critical for the development of the process. Wafer and mask metrology are increasing to become critical challenges together with wafer and mask design and production on the path to smaller design rule integrated circuits. There are additional measurement techniques that are used mainly for analytical purposes and not used as in-line monitoring metrology tools. These techniques are usually part of an analytical lab for fabrication. Some examples are: Atomic force microscope (AFM): AFM is used for the depth measurement of structures and trenches, including very shallow step heights. Focus ion beam (FIB): A method in which a small crater is made with an FIB in the measurement location, enabling SEM imaging of the structure of the stack, a hidden defect, or the dimension of the stack. Transmission electron microscope (TEM): TEM enables a very high resolution, but it is possible only by slicing a very thin layer of the sample, which makes the measurement destructive.

REFERENCES 1. International Standard ISO 5725-2, “Accuracy (Trueness & Precision) of Measurement Method and Results; Part 2, Basic Method for the Determination of R&R of a Standard Measurement Method,” 1994. 2. Banke, G. W., et al., “Characteristics of Accuracy for CD Metrology,” Proc. of SPIE 3677, The International Society for Optical Engineering, Bellingham, WA, p. 291, 1999. 3. Menaker, M., “CD-SEM Precision Improved Procedure and Analysis,” Proc. of SPIE, The International Society for Optical Engineering, Bellingham, WA, 2000.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH33.qxd

04/04/2005

21:04

Page 33.12

CD METROLOGY AND CD-SEM 33.12

FAB YIELD, OPERATIONS, AND FACILITIES

4. Laufer, I., et al., “Three-Dimensional Aspects of the Shrinking Phenomenon of ArF Resist,” SPIE Microlithography Conf. 2002, Proc. of SPIE 4689, The International Society for Optical Engineering, Bellingham, WA, p. 841, 2002. 5. Archie, C., et al., “Modeling and Experimental Aspects of Apparent Beam Width as an Edge Resolution Measure,” Proc. of SPIE, The International Society for Optical Engineering, Bellingham, WA, pp. 3671–77, 2003. 6. Peltinov, R., et al., “New Approach for Mapping and Monitoring Damascene Trench Depth Using CD-SEM Tilt Imaging,” Proc. of SPIE 4689, The International Society for Optical Engineering, Bellingham, WA, 2002. 7. Kris, R., et al., “Height and Sidewall Angle SEM Metrology Accuracy,” Proc. of SPIE 5375, The International Society for Optical Engineering, Bellingham, WA, p. 1212, 2004. 8. Rice, B., “CD Metrology for Logic: 45 nm and 32 nm Nodes/ Intel Corp,” SPIE, The International Society for Optical Engineering, Bellingham, WA, 2004.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 34

SIX SIGMA Bruno Scibilia Yoan Dupret Altis Altis Semiconductor Corbeil Essonnes, France

34.1 WHAT IS SIX SIGMA? Six Sigma Versus Other Quality Initiatives. Quality and yield problems arise fundamentally from two causes—critical dimension variations and contamination. By reducing the process variation, the cost of poor quality decreases and profitability increases. Six Sigma is, basically, a quality objective. It is an organization-wide, leadership-driven, processoriented initiative, designed so that processes produce no more than 3.4 defects per million opportunities (DPMO). To achieve this, a relentless pursuit of variation reduction in all critical processes needs to be carried out. Processes are required to operate so that the engineering specifications are at least plus or minus Six Sigma (sigma stands for standard deviation) from the process target. The Six Sigma initiative has contributed to a change in the discussion of quality from one where defects were measured in percentages to a discussion of defects per million. It emphasizes setting extremely high objectives. Goals are stretched to focus people on process improvements. With the knowledge that more than 200 process steps are usually necessary to manufacture a chip, old ideas about satisfactory quality levels are no longer acceptable. With shrinking dimensions, semiconductor yields will become increasingly sensitive to manufacturing variations. Six Sigma brings together problem-solving tools that are already known (such as gauge repeatability and reproducibility studies, flow charts, capability analysis, control charts, probability distributions, and design of experiments) into a methodology that enables people to improve their processes. The Six Sigma philosophy has managed to overshadow other quality initiatives, for several reasons: • Six Sigma has received serious attention from senior management by tying process improvement and process variation reduction to financial performance. Success stories from some of the largest and most successful corporations in the world have encouraged other companies to deploy Six Sigma programs. • Six Sigma is a structured project-based approach for breakthrough process improvement. • Six Sigma entails the use of statistical thinking as well as project management tools to bring about process improvements. Six Sigma in the Semiconductor Industry. Six Sigma concepts evolved out of work carried out by Bob Galvin and Bill Smith in the 1980s at Motorola. Eventually Motorola established the Six Sigma Institute and Six Sigma training has been extensive throughout the company. Motorola’s quality

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

34.1

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.2

SIX SIGMA 34.2

FAB YIELD, OPERATIONS, AND FACILITIES

improvement process, under the banner of Six Sigma, has stood the test of time. Texas Instruments, Samsung, Chartered, National Semiconductor, as well as Honeywell practice Six Sigma. IBM launched a program entitled market-driven quality (MDQ) to achieve Six Sigma; however, at the end of the 1990s the focus changed due to reengineering and a management change. IBM’s problems were perceived to be due to a lack of innovation rather than a lack of quality. Other companies like Infineon, ST, and Intel do not formally perform Six Sigma projects although they embrace its basic ideas and statistics-based methodologies for improving quality and reducing costs. Even though, in these companies, variation reduction programs are not labeled Six Sigma, the essence of Six Sigma is still there.

34.2 FUNDAMENTAL STRENGTHS OF SIX SIGMA 34.2.1 A Project-Based Approach Six Sigma Change Agents. Six Sigma takes the form of projects conducted by black belts or by green belts that are then overseen by master black belts. The black belt certification ensures that these experts effectively master Six Sigma tools and techniques. Project management skills are also essential. Ideally black belts will be able to dedicate all of their time to one or more Six Sigma projects. Green belt projects tend to be less involved and focus on processes related to their current work. The DMAIC and DMADV Methodologies. There are two Six Sigma methodologies: Six Sigma DMAIC and Six Sigma DMADV. Each one of these terms are related to the major phases in the cycle. Six Sigma DMAIC is a methodology that defines, measures, analyzes, improves, and controls processes that do not match the Six Sigma objective. Six Sigma DMADV defines, measures, analyzes, designs, and verifies new processes or products that are to be designed for Six Sigma quality.

34.2.2 Statistical Thinking Knowledge Acquisition for Quality Improvement. At its most fundamental level, quality improvement is about generating knowledge. A major contribution of the Six Sigma initiative has been the institutionalization and comprehensive diffusion of statistical thinking and methods. Providing simple tools, such as the design of experiments, run-to-run control loops and tool matching, and promoting their use throughout the company can ensure that the people who are close to the processes produce information on how problems may be solved. Benefits of Using Simple Tools. Six Sigma programs enable companies to get their entire workforce to approach quality improvement with a simple, tools-oriented, common sense methodology, emphasizing a data-based approach rather than relying on intuitions or perceptions. The Six Sigma DMAIC (define, measure, analyze, improve, and control) cycle looks somewhat similar to the “plan, do, check, act” (PDCA) cycle developed by W. Shewhart. It provides a structured and systematic approach as well as a list of tools for performance improvement. Generally, only a fraction of these tools will be used in a single project according to the needs and opportunities for improvement.

34.2.3 Management Commitment Breakthrough Management. Senior management is bottom-line oriented. Other quality programs tend to get too involved in how to count defects and defect report rates. The understanding that lower defect rates save millions of dollars has a real impact on companies. They begin

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.3

SIX SIGMA SIX SIGMA

34.3

to appreciate the contribution of effective variation reduction projects to their companies. Six Sigma has been instrumental in encouraging them to adopt a more aggressive strategy for breakthrough improvement. Six Sigma requires the judicious selection of projects and personnel. Strong management commitment from the very top is essential. Teamwork, internal politics, and communication are just as important as the technical aspects of Six Sigma. A common quality metrics. Six Sigma is often used more as a communications metric than a statistical one. Everyone in Motorola knows what you are talking about when you mention Six Sigma. It is a way to express the capability of a process. It establishes accountability to drive improvement. Reviews are performed weekly, monthly, and quarterly. Six Sigma measurement methods fall into the category of process capability (Cp/Cpk) metrics. Cp considers the spread of a process whereas Cpk considers the shift from the target as well as the spread. Six Sigma represents a Cp value of 2 and a Cpk value of 1.5. The specification width needs to be twice as large as the data distribution width (which is approximately ±3 sigma) and if the distribution is decentered, the distance between the closest specification and the mean should not be smaller than 4.5 sigma. The assumption of a 1.5 sigma shift. A process operating at Six Sigma levels will produce 0.002 defects per million opportunities (Fig. 34.1). However, the Six Sigma philosophy assumes that the process mean drifts 1.5 sigma from the target in either direction. The area of a normal distribution beyond 4.5 sigma from the mean represents 3.4 ppm (Fig. 34.2). The 1.5 sigma shift assumption is based on the fact that for a subgroup of four, control charts will easily detect any process shift of 1.5 sigma of the data distribution. If the process shifts by 1.5 sigma or more, it will be shut down. The 1.5 sigma shift assumption is actually a worst-case scenario for two reasons: 1. Measured samples are usually larger than 4 data, therefore, even smaller shifts than 1.5 sigma will easily be detected by statistical process control (SPC) charts. 2. The process mean will usually be located well within the control limits. Hence when the Six Sigma objective is achieved, the actual number of defects will lie somewhere between 3.4 and 0.002 defects.

LSL

USL

0.25 0.2 6s 0.15 6s 0.1 0.05 0 90

95

100

105

110

FIGURE 34.1 The Six Sigma process capability with the process adjusted to its target. Cpk = 2.0 and the defect rate is 2 ppb.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.4

SIX SIGMA 34.4

FAB YIELD, OPERATIONS, AND FACILITIES

0.25 4.5s

0.2 7.5s 0.15 0.1 0.05 0 90

95

100

105

110

FIGURE 34.2 A Six Sigma process with a 1.5 sigma shift from the target. Cpk = 1.5 and the defect rate is 3.4 ppm.

34.3 THE MAJOR DMAIC PHASES 34.3.1 Measurement Critical-to-Quality Identification. The primary list of critical parameters is usually defined in the engineering specifications (from technology transfer phases); additional parameters from process learning for yield enhancement are later included in the list. Repeatability and Reproducibility (R&R) Studies. Measurement system capability studies quantify measurement errors. Typically, in the semiconductor industry, the degree of accuracy of a measurement process only depends on equipment (repeatability) not on operators or appraisers (reproducibility). 34.3.2 Analysis Capability Analysis. The standard formulae for Cp and Cpk are the following: Potential capability Cp =

USL − LSL 6 sigma

Capability index once decentering from the target is considered  USL − mean mean − LSL  Cpk = minimum  and  3 sigma 3 sigma   where USL is the upper specification limit, LSL is the lower specification limit, and sigma is the standard deviation.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.5

SIX SIGMA SIX SIGMA

34.5

The area of a normal distribution between ±3 sigma represents 99.73 percent of the data. This area is compared to the specification interval. It is important to eliminate outliers before Cp, Cpk indices are estimated. Moreover the formulae described above are valid only when the data follow a normal distribution (the well-known bell-shaped curve). When raw values from critical parameter measurements are available, estimating the standard deviation is straightforward. However, when the amount of data storage is restricted, usually, only summary statistics will be stored. In that case, the normal nested method is used to estimate the total standard deviation value from summary statistics. The normal nested method. In the semiconductor industry, within-lot processing conditions are often quite homogeneous, whereas lot-to-lot conditions can vary extensively. This is even truer for within-wafer conditions that are usually far more homogeneous than wafer-to-wafer conditions. Therefore Cp, Cpk indices cannot be estimated solely from within the sample data, every component of variations needs to be considered to estimate the total sigma value. The nested normal distribution method takes into account within-wafer variations and variations between wafers from the same lot as well as between lot variations, it is the only correct method to estimate Cpk indices from summary statistics: Sigma 2total = sigma 2lots + sigma 2wafers + sigma 2site Many fabs though, report to their customers Cpk indices that are based only on within sample data variations. Variations among subgroups are ignored, hence the true process variability is underestimated, and Cpk indices are overestimated. Distribution-free Cpk. Cpk indices are based on the normality assumption; however, violations to this assumption are not uncommon. For example, systematic differences on a wafer, say between a measured site at the center of a wafer and a measured site at the edge, are one of the causes for departure from the normality assumption. This phenomenon may artificially degrade a Cpk index. This is also true for systematic differences within a lot, when, for example, the mean of the first measured wafer is systematically higher or lower than the mean of the last measured wafer. When there are multiple distributions according to the position of a measured site on a wafer, or the wafer position in a lot, the overall distribution is much flatter than a normal distribution and the tails are much shorter (Fig. 34.3) leading to a degradation of Cpk estimates. A possible solution to that is to rely on distribution-free Cpk methods. In a normal distribution, 99.73 percent of all data are contained within 3 sigma from the mean. Empirical quantiles may be used to estimate the two values between which 99.73 percent of all data are included. Cp =

USL − LSL Q99.865% − Q0.135%

 USL − mean Cp k = min  ;  Q99.865% − mean

mean − LSL  mean − Q0.135% 

LSL

USL

Q99.865%

Q0.135%

99.73% Six Sigma FIGURE 34.3

Multiple distributions due to within-wafer or within-lot systematic differences.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.6

SIX SIGMA 34.6

FAB YIELD, OPERATIONS, AND FACILITIES

That method, however, relies on very few data that are located at both edges of the distribution, it is therefore quite unreliable and may only be used when a large data set is available (say 1500 data or more). It remains very sensitive to outliers though. Identification of Causes of Variation and Graphical Analysis. Six Sigma emphasizes a quantitative, disciplined approach to quality improvement. In the past, statisticians may have focused too narrowly on complex statistical tools. Simple graphical analyses may be very powerful too. A semiconductor manufacturer reported that a Six Sigma project enabled them to identify production problems related to shifts, variations in acid bath concentration and etching times through graphical (multivariate charts), and Cpk analyses. 34.3.3 Improvement Design of Experiments (DOEs). There are two ways to ensure that a product achieves high yields at the end of the manufacturing stage: • Identifying the most sensitive process parameters so that they may be tightly controlled • Setting product design and process parameters so that these products become more robust to manufacturing variations Designs of experiments enable one to identify the most sensitive parameters while minimizing the total number of experimental runs that need to be performed. DOEs are useful to maximize the degree of accuracy of the parameter effect estimates for a given number of runs. Interactions between parameters may be identified when their effects are statistically significant. Designed experiments are a very effective tool for improving processes. There are several types of DOEs—factorial designs, fractional factorial designs to reduce the number of runs to a fraction of the total number of possible tests, and response surface designs to estimate nonlinear effects. A project-based approach to improve the degree of uniformity of a chemical mechanical polishing (CMP) process while maximizing its removal rate is presented in Sec. 34.5.1. Several DOEs were used to identify the most important parameters, these parameters were set to optimize the process while ensuring that this process window was made robust to manufacturing variations. Advanced Process Control (APC). APC is a very efficient and promising approach to variation reduction in the semiconductor industry. Fault detection and classification (FDC) methods and runto-run control loops are discussed in the following section. Log file analyses provide an opportunity to evaluate and enhance global tool performance. FDC consists of identifying and monitoring error logs either for tool correction or for software (recipes) correction. In the litho area, for example, FDC has been used to systematically track prealigner test problems or to discover missing prelayers. Litho misalignment is significantly correlated with yields. In Altis’ fab, 100 percent control of orthogonal alignment as well as X/Y shifts is currently carried out using FDC. The most frequent failure type for a given recipe on a given stepper, the recipe with the most frequent error messages for a given stepper, and the stepper with most frequent messages are currently tracked and a pareto histogram of log alarms may be established. This process has led to a 25 percent reduction of warnings at a typical stepper by specific actions as well as a significant reduction in the amount of reworks and scraps. FDC may also be related to early maintenance, leading to long-term improvements in its efficiency. However, due to a frequent lack of adequate tool features, the presence of occasional bugs and the fact that data are often not well structured and easy to integrate, the use of FDC is still restricted. Common development with tool suppliers is required for a more extensive deployment. Tool parameter critical key numbers (end point signal intensity, for example) may be extracted from log files through filters and algorithms. This has allowed real-time control on end point signal intensity in the etch or CMP areas, for example, based on transformation methods, spectral software filters, and the selection of the pre- and post-end point areas by process engineers. Key number alarms may then be correlated with raw data to quicken the process learning phase.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.7

SIX SIGMA SIX SIGMA

34.7

Run to Run. Run-to-run methods are a very effective approach to variation reduction when processes do not behave in a totally random way. In the litho area, for example, run-to-run adjustments are routinely performed on offsets to optimize overlay data based on tool parameter model fits or to optimize critical dimensions by modifying the dose. These adjustments are based on a feedback loop and are carried out according either to a moving average of, say, the last five points or if the last point is very recent, according to an exponentially weighted moving average (EWMA). In our fab, a reduction of STI depth variation has been achieved by semiautomatically adjusting the etch time per chamber to prevent chamber mismatch. This has led to a Cpk value improvement from 0.8 to 1.1 in this case. Run-to-run control is possible only if real-time measurements are available, therefore integrated metrology and sensors are essential. This allows a reduction in the response time in case of process excursion as well. A wafer-towafer closed loop control has been established between chemical vapor deposition (CVD) and CMP tools in our fab, using an automated recipe distribution system. A major benefit of that project was an increase in the Cpk and product quality. 34.3.4 Control Statistical Process Control (SPC). Once process improvements have been achieved, the gains need to be sustained in the long term. Deviations from the target that are related to identifiable special causes need to be discovered and eliminated as soon as possible. X-control charts utilize the sample average to monitor the process mean. Thanks to the fact that the variability of averages is much smaller than the variability of raw values; control limits on averages are usually quite tight. Therefore, SPC monitoring facilitates the early discovery of deviations due to special causes. Control limits are often set at plus and minus 3 sigma that corresponds to 99.73 percent of all data with a rate of false alarms of 0.27 percent. Wider control limits may be used to monitor processes that are not critical (the so-called economical charts). Chart sets. When each sample includes more than one wafer, the related set of charts may include a chart for the lot mean, a chart for the ranges between wafer means, and a within wafer range (or sigma) chart. Sometimes, however, the dispersion between wafer means and the within wafer dispersion are compounded into only one chart, leading to a loss of information. Standardization. Some fabs have a very wide range of products, in this context the number of charts may be easily reduced by normalizing and standardizing averages and sigmas (or ranges) according to each product target and long-term variation estimates. The role of SPC is now evolving. The primary objective is still to ensure that tools are properly shut down before a major crisis occurs. Increasingly, however, there is a stronger emphasis on identifying long-term tool decentering, in order to improve Cp/Cpk indices. Cumulative sum (CUSUM) charts, moving average (MA) charts, or exponentially weighted moving average (EWMA) charts are very effective techniques to detect such long-term shifts. There also is more emphasis on the monitoring of the SPC system itself. Some fabs use synthetic performance scores for critical parameter control charts to assess how well they are being monitored by process engineers. Such scores may take into consideration process decentering, the adequacy of control chart limits, and the percentage of out of control data. They are useful to enhance the level of awareness and to drive continuous improvements. SPC versus run-to-run control. SPC is effective when a process is generally stable in normal conditions. Some processes, however, behave in a very cyclical way. Calculated control limit estimates on such autoregressive processes will usually be much too tight. Wider control limits are required in such a context, on the other hand the variability of autoregressive processes may be reduced by using run-to-run control loops to eliminate cycles. Therefore run-to-run control loops are a natural complement to SPC when processes behave in a cyclical way. Interactions between SPC and run-to-run control will play an increasing role in the future. Equipment control. Equipment parameters also need to be monitored. Some of them are critical and may trigger alarms when necessary. The number of data from equipment parameters, however, often becomes so large that fabs are rapidly overwhelmed with data. One solution to this is to only

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.8

SIX SIGMA 34.8

FAB YIELD, OPERATIONS, AND FACILITIES

3 2 1

FIGURE 34.4

04/16/2004

04/01/2004

03/16/2004

03/01/2004

02/16/2004

02/01/2004

01/16/2004

01/01/2004

12/16/2003

12/01/2003

11/16/2003

11/01/2003

10/16/2003

0

Yield losses according to process tools.

monitor summary statistics, and another solution consists of deploying multivariate SPC to monitor Hotelling’s T2 in multivariate SPC charts. When T2 multivariate charts are used, it is important to assess the impact of each equipment parameter on product characteristics, otherwise alarms are often triggered due to deviations of unimportant parameters. Equipment parameters need to be weighted accordingly. Analysis of Variance (ANOVA). Complex phenomena involving several parameters or parameters that have not been considered to be critical up to that moment may eventually affect yields. Unfortunately, these phenomena are not always detected by SPC charts. Data analysis is the link between these process and equipment parameters and yields. The ANOVA test is useful to compare and identify equipment that cause yield losses. It is essentially a hypothesis test designed to identify the differences between means that are statistically significant. Yield data do not follow a normal distribution, therefore nonparametric tests such as the KruskallWallis test are often performed. Such nonparametric tests are also more robust to the presence of outliers than the standard ANOVA method. Figure 34.4 illustrates how the Kruskall-Wallis test precisely identifies the equipment and corresponding process operation that is causing a yield loss, from among hundreds of tools. This deviation had not been previously detected by any SPC chart.

34.4 DESIGN FOR SIX SIGMA (DFSS) 34.4.1 Define, Measure, Analyze, Design, Validate (DMADV) With shrinking dimensions, design sensitivity to manufacturing process variations has become even more critical. DFSS is an efficient way to obtain high parametric yields. The goal of DMADV is to conduct DFSS. Its five phases define a project cycle, from the idea (define) to the final design (verify). Measure is the determination of customer needs and specifications. Analyze stands for the circuit options to meet customer needs. Finally, design is the detailed circuit construction. 34.4.2 Achieving Six Sigma in the Design Phase To achieve the objective of 3.4 DPMO, a circuit design should ideally have a degree of sensitivity to process variations, which is small enough so that its performances remain within the specification ranges (i.e., USL and LSL). This is also known as robust design. An iterative procedure is always carried out to ensure this.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

21:05

Page 34.9

SIX SIGMA SIX SIGMA

34.9

Yield Prediction. Once the initial circuit design has been established, it is necessary to estimate the parametric yield. This estimate represents the number of circuits whose performances remain within specifications divided by the total number of virtually produced circuits, taking into account losses due to process dispersions and bad designs. Three methods are widely used in the semiconductor industry today—case design, Monte Carlobased methods, and DOE/RSM methods. Case design. Also known as corner simulation, it is the oldest method. For each device of the circuit, the upper and lower specification limits of the key parameters are defined. Then, at least three models are generated for each device—nominal case, worst case, and best case. The circuit is first designed with all devices at their nominal values. Simulations are then conducted with all the devices at their worst values and finally at their best values. Due to global and local variations as well as correlations between design parameters, even when these device parameters individually match the Six Sigma objective, the probability of device failure will not be equal to 3.4 DPMO. This may sometimes be partially represented by describing the corners of the performance variations surface HT-L L-L between two devices. Figure 34.5 shows an example for the threshold voltage of a P and an N metal-oxide-semiconductor-fieldH-LT effect transistor (MOSFET). DOEs may also be used to simulate the impact of combinations of worst and best case values for each device. Case simulation often results in estimates that are too pessimistic. This can induce an overcautious approach by the designL-HT ers and lead to a loss of time. Moreover, good corner models are not simple to build since the choice of the key parameters may H-H LT-H differ according to the kind of circuit. Cp and Cpk estimates are also difficult to obtain from corner analysis. Monte Carlo-based methods. Each element of the circuit is N-Vth characterized by a mean and a variance of its distribution. Local FIGURE 34.5 The threshold voltage variations (i.e., matching) may be taken into consideration by of a P and an N MOSFET. mathematical models like Pelgrom’s one. Circuit simulations are carried out with values of the device key parameters that are randomly set according to their underlying distribution. This method, unfortunately, has a very high computational cost. If the circuit performances are expected to match the Six Sigma requirements, the number of simulations that is necessary to obtain 3.4 failures out of one million tests is almost impossible to reach. Sampling techniques such as Latin hypercube sampling (LHS) are often deployed to reduce the number of simulations. Monte Carlo methods are widely used due to their efficiency. Cp and Cpk indices are then easily calculated from the performance distributions. However, these methods are not effective if strong variations or nonlinear effects are present, as well as if the normality assumption of the distributions is violated. Appropriate transformations may sometimes help solve these problems. Key parameters are, as for corner analysis, difficult to select and require a deep knowledge of the system. DOE/RSM-based methods. This is not the most frequently used technique today, but these methods are gaining more and more attention from designer teams. In the first phase, device models are extracted from sample dies and wafers. Correlations between the model parameters with typically five to ten pseudoparameters are studied using principal component analysis (PCA) or factor analysis (FA). A reduced number of uncorrelated parameters is retained in this way. These new pseudoparameters are linear combinations of the primary model parameters. The second step consists of using response surface modeling (RSM) to model the circuit as a function of the new pseudoparameters. RSM is a linear or quadratic regression technique based on DOEs to minimize the number of necessary simulations. The main advantage of the Monte Carlo method lies in the fact that new parameters are mathematically chosen from data, so that a reduced amount of knowledge is required. However, when a response surface model is obtained for a circuit, direct relations between circuit performances and device parameters are known and are available. There are two major limitations to the Monte Carlo P-Vth

Geng(SMH)_CH34.qxd

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.10

SIX SIGMA 34.10

FAB YIELD, OPERATIONS, AND FACILITIES

approach—a large number of device models is needed and extensive variations cannot be taken into account. Sensitivity Analysis. Once the yield has been estimated, the device parameters that may cause a reduction in the yield rate, due to process variations, need to be identified. The Monte Carlo approach consists of identifying the random selections that made the circuit performance move out of specifications. When DOEs are performed, device parameters that are sensitive to process variations can easily be discovered. However, such a method is computer time expensive. Another commonly used technique is to make a sensitivity analysis by varying each known key device parameter around its mean, also according to a DOE. One problem related to this approach is that it is difficult to handle the interactions between devices. An advantage of DOE/RSM methods for parametric yield calculation is that a regressive model is obtained. The sensitivity of the circuit performances to parameter dispersions is encapsulated in the mathematical model formulation. Redesign and Recentering. Identifying the parameters that lead the circuit performances to be out of specifications helps the engineer redesign his circuit. The objective is to meet the DFSS requirements. Most of the time, there is no need for a complete redesign of some circuit parts. Changing the size of some devices is often sufficient to recenter the circuit performances. This may sometimes be automated. Whenever a device remains too sensitive and no satisfactory design solution to limit the effects of parameter variations has been found, process engineers need to focus their attention on controlling the process parameters that are directly linked to the device performance. This procedure is iterative—design with nominal values, yield analysis, sensitivity analysis, recentering, and/or redesign, until the circuit performances meet the DFSS requirements.

34.5 SOME APPLICATIONS 34.5.1 A DOE Project in the CMP Sector The goal of CMP processes is to produce wafers that are as flat as possible in order to maintain high yield rates. Planarization is compulsory if optical lithography is to be successfully used with feature sizes that are increasingly small. At the same time, high removal rates and a high degree of uniformity are desired. These two goals, however, are often conflicting ones. The objective of this subsection is to present a successful application of an experimental approach to process improvement in the CMP area. It begins with a brief summary of the problem. Then examples of DOEs and a description of the project are provided. The objective was to eliminate liner residues after polish. Because of liner residues, the yield was impacted and costly reworks were needed. A better uniformity with a good removal rate was required to solve that problem. An engineer was dedicated to this project with the support of the rest of the CMP team and of a statistician. Experiments were first carried out to identify the best carrier design then several DOEs were performed to optimize the process window for two given pads. Initially, the level of the back press parameter was increased, the tests indicated, though, that this had no significant effect on the degree of uniformity. Then the carrier design was modified, that is to say, holes were drilled at different positions over the insert. The results were quite impressive (Fig. 34.6). The degree of uniformity of the carrier design that was in current use (standard current carrier design) was much lower than that of the other carrier designs that had been tested. In particular, the carrier design that corresponded to Test 2 in the graph (see Fig. 34.6) was later chosen as the new optimized solution. The next phase of the project consisted of identifying the best process window for the new optimized carrier design. Six parameters were tested for significance and a design of experiment was carried out.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.11

SIX SIGMA SIX SIGMA

34.11

Comparison between different carriers 2000

W thickness A

1900

Standard, Unif = 4.8%

1800

Test 1, Unif = 2.3%

1700

1600

Test 2, Unif = 2.5%

Test 3, Unif = 3.1%

1500 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10

0

10

20

30

40

50

60

70

80

90 100

Across the wafer (mm)

FIGURE 34.6

The wafer topography and degree of uniformity according to carriers.

A 26-2 fractional factorial design was performed to reduce the number of tests to only 16 (Table 34.1). Two different types of pads were tested, the other parameters were—the downforce, the back force, oscillations, carrier speed, and table speed. The Pareto graph of the absolute effects of the parameters clearly shows that the carrier as well as the table velocities have a significant impact on uniformity (Fig. 34.7). The results also indicated that the down force as well as the carrier and table velocities had significant effects on the removal rate. Due to the interaction effects between these three factors, their combined effects were greater than the addition of these individual factor effects (Fig. 34.8). Clearly, to minimize the amount of variation while maximizing the removal rate, the carrier and table velocities needed to be kept low (to decrease the standard deviation), whereas the level of down force had to be increased (to improve the removal rate).

TABLE 34.1 Fractional Factorial Design: Parameter Level Combinations and the Associated Measured Response for Each Run Responses

Test 1 Test 2 Test 3 Test 4 Test 5 Test 6 Test 7 Test 8 Test 9 Test 10 Test 11 Test 12 Test 13 Test 14 Test 15 Test 16

Down force

Back force

Oscillations

PAD

V carrier

V table

Std dev [percent]

RR [A/min]

180 250 180 250 180 250 180 250 180 250 180 250 180 250 180 250

50 50 100 100 50 50 100 100 50 50 100 100 50 50 100 100

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

10 100 100 10 100 10 10 100 10 100 100 10 100 10 10 100

10 10 100 100 100 100 10 10 100 100 10 10 10 10 100 100

142 490 413 213 753 299 175 429 535 552 381 249 552 262 527 622

869 1493 1042 1327 1099 1382 853 1489 1090 1558 1075 1126 1085 1151 1103 1680

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.12

SIX SIGMA FAB YIELD, OPERATIONS, AND FACILITIES Standardized Pareto Chart for Std Dev E:V carrier F:V table D:PAD AF + DE C:Oscillations B:Back force AC + BE AB + CE A:Down force AE + BC + DF BD + CF AD + EF BF + CD 0

2

6

4

8

10

Standardized effect

FIGURE 34.7

Standardized parameter effects on the standard deviation.

Standardized Pareto Chart for VA A:Down force E:V carrier F:V table AE + BC + DF AD + EF D:PAD C:Oscillations AF + DE BD + CF AC + BE AB + CE BF + CD B:Back force 0

10

20

30

40

Standardized effect

FIGURE 34.8

Standardized parameter effects on the removal rate.

45s Polish time 2300

2200

W thickness

34.12

Former process window, Unif = 3,72%

New process window, Unif = 1,74% PAD: 263/325 wafers old

2100

2000

1900

1800 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10

0

10

20

30

40

50

60

70

80

90 100

Across the wafer (mm)

FIGURE 34.9

The wafer topography—comparison between former and new process windows.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.13

SIX SIGMA SIX SIGMA

34.13

STD DEV

WIWMU

Estimated response surface 4.4 3.9 3.4 2.9 2.4 1.9 1.4

0

0

20

40

60

80

V carrier

VA

RR

80 10 40 60 0 2 100 0 le V tab

1790 1590 1390 1190 990 0

20

40 V carrier

FIGURE 34.10

60

80

0 100 0 2

0 80 10 40 60 le V tab

Response surfaces of the standard deviation and the removal rate (RR).

Additional tests were performed at the factor settings recommended after the design of experiments. The results were consistent with the conclusions that had been drawn (Fig. 34.9) from the DOE, and a substantial reduction in the amount of variation was achieved. This graph also shows that there is still room for improvement though. In particular the wafer edge behavior needs to be studied. A second DOE was performed to identify the best process window for another type of pad with the same configuration of holes. The conclusions were similar. DOEs are a very effective method to identify the factors that have a real effect by making them clearly emerge from the surrounding noise. This important property has been very useful in this application. They also enable one to discover the significant interactions between parameters. Ideally test conditions should be realistic so that the conclusions from the DOE may easily be extended to operating processes. Optimal solutions are not enough though, the robustness of the process window to manufacturing variations also needs to be taken into account. Figure 34.10 illustrates response surfaces obtained from an additional 32 (two factor, three level) DOE to study the behaviors of carrier as well as table velocities on the standard deviation and on the removal rate. This type of DOE is useful to estimate nonlinear effects. These nonlinear effects may be exploited to improve the degree of robustness to changes in the parameter values. Flatter and more stable areas within the response surface are clearly preferable. It is possible to minimize the standard deviation by setting the carrier velocity at values between 40 and 80 and the removal rate (RR in the graph) may be maximized by setting the table velocity between 40 and 80. This solution is also robust since the slope of the response surface in this area is rather flat so that the amount of variation that is transmitted from small changes in the carrier or table velocity to the removal rate and to the degree of uniformity will be much reduced. 34.5.2 Graphical and Cpk Analysis A simple graphical analysis is often necessary to enhance the level of awareness of process engineers to problems related to tool mismatches. Variation decomposition methods are also useful to quantify the different sources of variations (within-wafer uniformity, between-wafer and between-lot variations) in order to identify and focus on the major causes of instability. Here, for example, a very substantial Cpk improvement may be achieved by adjusting the tools to their targets. The total mean of that process is centered on the target. However, if the individual tools are considered (see the graph in Fig. 34.11 on the left side), the data from one of the tools are well above the target and the data from the other tool, well below the target (Fig. 34.11). This source of variation may easily be eliminated. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.14

SIX SIGMA 34.14

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 34.11

Cp/Cpk monitoring of a process parameter according to tools.

34.5.3 A Simple DFSS Design Example The optimization of a low pass sallen-key active filter cutoff frequency is described in this section to provide an illustration of the DFSS approach. A first nominal design has been carried out and a 500 runs Monte Carlo simulation has been performed. Process dispersions have been accounted for on every passive component based on the normal distribution assumption (Fig. 34.12). LSL is 200 Hz and USL 450 Hz. The mean value that is obtained is 267 Hz and the standard deviation is 17.56 Hz. These values result in a Cp of 2.37. Since a minimal Cp value of 2 is required, the Cp index respects Six Sigma design rules. However the Cpk value estimate is 1.27 for a required value of 1.5. This clearly indicates that the distribution is decentered. The nominal cutoff frequency needs to be set at a higher value. For more complicated designs, a sensitivity analysis should be considered to identify devices for which the values need to be modified. Here, the frequency is driven by the inverse of a resistance. Therefore, the value of this resistance needs to be lowered. After calculating a new value for the resistance, a new distribution is obtained using a 500 runs Monte Carlo simulation again (Fig. 34.13). The new mean is 288 Hz and the new standard deviation is 18.25. That leads to a Cp of 2.28 and Cpk of 1.61. The design is now robust, from a Six Sigma point of view, according to the cutoff frequency.

Frequency de coupure 70 60

LSL

USL

50 40 30 20 10 0 FIGURE 34.12

The cutoff frequency of the initial design.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.15

SIX SIGMA SIX SIGMA

34.15

Frequency de coupure 80 70 60 50 40 30 20 10 0

LSL

FIGURE 34.13

USL

The cutoff frequency after modification of the resistance value.

To optimize real case designs, such studies are required on every key performance of the filter. Tools are used to summarize the information in terms of parametric yields. 34.5.4 An Application of Run-to-Run Control for Six Sigma Improvement An example of how an automated recipe distribution system may be linked to an SPC system is presented in this section. The objective is to adjust the recipe according to the measured values so that the amount of variation is reduced. Measurements at a previous process step are recorded and sent to control charts. According to where the measured data are situated with respect to the limits of the control charts, recipes at a latter process step are selected. This reaction loop introduces more flexibility into this process and therefore more accurate final dimensions. Here, the mask open etching time is adjusted according to the measured dimensions at the photolithography development phase. If the developed dimensions at the photolithography phase remain within certain limits a standard recipe is used, otherwise recipes with an adjusted etch trim time are sent to the tool (see Fig. 34.14).

3 kind of recipes according to the dim dev If the dim dev is > +7 nm then rework photo

+7 nm +5 nm Target −5 nm −7 nm

The longer the trim step, the smaller the etched dim

If the dim dev is between +5 nm and +7 nm then a recipe with a longer trim step is used, ex: PC MO HI If the dim dev is between ± 5 nm then standard recipe is used, ex: PC MO ST If the dim dev is between −7 nm and −5 nm then a recipe with a shorter trim step is used, ex: PC MO LO If the dim dev is < −7 nm then rework photo

FIGURE 34.14 A feed-forward loop—the recipe selection depends on the values in the control charts of the previous process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH34.qxd

04/04/2005

21:05

Page 34.16

SIX SIGMA 34.16

FAB YIELD, OPERATIONS, AND FACILITIES

According to the dimensions at the development phase, the most adequate recipe is used, for example, PC MO ST, then according to the tool status, the recipe sequence is completed, for example, if only chambers B and C are available, then PC MO ST BC. Thanks to that feed-forward loop, the final critical dimensions are much less sensitive to excursions at the photo phase. This has resulted in much improved Cpk values for this process (Fig. 34.14).

34.6 FUTURE TRENDS AND CONCLUSIONS The semiconductor industry is highly innovative. That rate of innovation forces companies to proceed with high-volume production before their processes reach maturity. Process capability issues need to be resolved before ramping up the volume. In this context, continued advances in process capability and process control are essential and the Six Sigma approach can help reduce the amount of intrinsic variability. Problems related to a lack of skills have prevented statistical methods from realizing their potential impact. Six Sigma can be viewed as an attempt to provide a tool kit of statistical techniques to the people who understand semiconductor manufacturing processes. There is an enormous profitability challenge facing the manufacturers, and Six Sigma is becoming essential to compete in today’s markets. Processes need be optimized using designs of experiments and robust design, they need to be controlled using SPC and APC to prevent excursions and Cpk reports to assess the process health. The future of the industry depends on yield enhancement which is, to a large extent, the result of quality improvement efforts.

FURTHER READING Brue, G., Six Sigma For Managers, McGraw-Hill, New York, 2002. George, M., Lean Six Sigma, McGraw-Hill, New York, 2002. George, M., What Is Lean Six Sigma, McGraw-Hill, New York, 2003.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 35

ADVANCED PROCESS CONTROL Robert H. McCafferty RHM Consulting Sandy Hook, Connecticut

35.1 TECHNOLOGY OVERVIEW Advanced Process Control (APC) within semiconductors has essentially come to mean three separate efforts, each engaging software tools and mathematical techniques best suited to the scope and complexity of the task at hand. The first of these is, effectively, line level data analysis and overall process optimization, typically conducted by a Product Engineering (sometimes known as Characterization) organization acting under the mantle of Yield Management to essentially tune the manufacturing line for production of an optimum parts distribution at high yield. This typically involves limited experimentation combined with data mining and modeling techniques—polynomial models are popular, with more comprehensive multidimensional methods (Geometric Process Modeling) and neural nets occasionally in use as well—but seldom approaches what would be recognized as control in other industries. Detection of problems visible at the level of in-line parametric measurements is also a focus and, with rare exception, all fabs have standing efforts of this nature in place. Second in popularity is R2R Control. Originating at Semiconductor Research Corporation’s MIT SEMATECH Center of Excellence (SRC’s MIT SCOE) as “Run-by-Run” Control in the late 1980s, this became “Run-to-Run” Control once effort was focused at SRC’s University of Michigan SCOE and has since been abbreviated by industry as “R2R” control. This relies on a model to adjust variable settings in a process recipe. That model is usually linear, as limited time series effects associated with a previous wafer or wafers may also be considered, while a small number of variable set points are manipulated to compensate for deviations from the norm. Those deviations typically encompass film thickness variation on incoming wafers, changes in desired output, and modest departure from expected tool performance. Leading fabs use this method with relatively unsophisticated control algorithms acting on a wafer-bywafer or occasionally lot-by-lot basis (hence the term “R2R”) implemented at what is generally only a selection of key process steps. This is in keeping with the control engineer’s creed of designing against everything he knows about—and spending the time it takes to get that right—then feeding back against everything else. Hence, R2R Control damps out variation in process outputs by feeding forward against incoming variability and backward against tool performance deviations. Finally, and also within the generally accepted domain of APC, is the notion of Fault Detection and Classification (FDC). The detection element of this technology, which was brought to the forefront of industry attention during the course of SEMATECH’s J88 Project,1 is essentially a highly sophisticated version of SPC. Rather than relying on univariate mathematics from the 1920s, however, this draws heavily on either statistical variation models, multidimensional Alarm Management and Geometric Process Control, or multiple univariate pattern recognition methods to discern when

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

35.1

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.2

ADVANCED PROCESS CONTROL 35.2

FAB YIELD, OPERATIONS, AND FACILITIES

an out-of-pattern event is occurring within tool or process data. That event can then be investigated and classified pursuant to assignment of a cause and corrective action associated with the anomalous pattern of measurements. Such efforts are less common than R2R Control, being seen as reactive in nature, but gaining ground as the scrap cost of a processed wafer increases.

35.2 FUNDAMENTALS OF ADVANCED PROCESS CONTROL The understanding of process data and conversion of that knowledge into a form which is unambiguous as well as easily comprehensible and readily used by anyone in the fab is at the very heart of successful implementation. To that end, data analysis designed to uncover basic information followed by capture of process behavior in a model best suited to control objectives is the first step. The order of activities is significant as what is learned in analysis is generally key to building useful models. 35.2.1 Data Analysis The act of analysis is essentially a search for structure, discrepancy, and patterns within a body of numerical information. At its outset, one has a vast spreadsheet of numbers, and by its conclusion we must understand: 1. Which observations are spurious? These must be dismissed before models are built. 2. Whether the dataset exhibits clusters of observations that are mathematically closer to one another than the main body of data and if those clusters are in some sense useful (e.g., exhibit very high yield) or simply striations in the overall population. 3. If there are striations in the data, do they actually represent distinct subpopulations? Is the dataset really a mix of several unique populations that must be treated separately? The latter question is key as “lurking variables” may be present, and models built across multiple populations with differing properties can produce particularly treacherous predictions. 4. Once unknown variables have been identified and significant subpopulations pulled apart from one another, do any variables exhibit schizophrenic behavior or other oddities indicative of atypical process or tool operation? Further, examined multidimensionally, is there anything fundamentally wrong with the picture those variables portray? 5. Which variables or sets of variables appear to be most significant in driving variation evident within the data? 6. Are there identifiable ranges of any variables which map to desired process outcomes (i.e., sweet spots) and can variables wielding the most influence on those outcomes be discerned? Numerical Methods. Given the large number of variables and interactions typically involved conventional graphical methods—plotting a matrix of 2D or 3D views from the raw dataset—become intractable, and one is effectively left with numerical analysis and multidimensional visualization techniques. Beyond dimensional analysis,2,3 which leverages the property of dimensional homogeneity to deduce components of the differential equation physically governing behavior among variables but can reduce dimensionality of the underlying dataset by at most five factors, commonly available numerical methods all hail from the field of statistics. That particular branch of mathematics operates by drawing inferences based on central tendencies of data; hence mean values, standard deviations, and other properties are calculated and employed in analysis for each variable of a dataset taken independently. Connectivity among different variable values within the same observation, therefore, is broken. Standard statistical analysis systems, such as SAS JMP, STATISTICA, and Cornerstone, are widely available to pursue the questions listed above, with that analysis likely starting by testing for outliers

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.3

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.3

then calculating basic statistics once they have been excised. Distribution fitting is next, followed by visual inspection of each distribution to search for schizophrenic behavior (bimodal distributions) and other characteristics that simply shouldn’t be present given engineering knowledge of the system generating data. Finally, once the dataset has been numerically combed free of high-influence outlier points and one is reasonably sure (i.e., all distributions look sensible) that no sharp divisions exist, the importance of variables can be assayed. After scaling and mean centering the data, a variation model, which relies on linear, orthogonal combinations of the original dataset variables known as principal components,4 can be mechanically built. Each principal component will be uncorrelated to the others and potentially contain a fraction of each original variable. Further, there will be as many principal components as original variables. However, in general (there are frustrating exceptions to this) much of the variation observable in the original dataset will be explained within its first few principal components.5 Hence, given a set of data for 100 variables, 100 principal components each containing as its constituent “loadings” some fraction of each original variable (all 100 of them) would result. But fortuitously, the first handful of principal components will typically encompass nearly all of a dataset’s variation allowing, by inspection of loadings for those dominant principal components, direct numerical isolation of key variables in a dataset. Pattern-Based Analysis. It would be difficult to find two technologies as different—or synergistic— as those of multidimensional data visualization and analysis and the numerical techniques discussed above. Where numerical methods focus on statistical calculations and software packages operated by small numbers of highly skilled individuals, multidimensional methods, implies, instead render an entire dataset both visible and comprehensible. This sets up discovery through rapid probing via visual queries combined with pattern recognition by a broad cross section of a fab’s population. Hence, numerical analysis methods are well suited to use by a small number of experts pitted against plant issues while multidimensional visualization methods, although almost frighteningly effective in the hands of an expert, are uniquely effective for consensus problem solving. As long as data is present, both do yield understanding of and consequent solution to plant problems, and both are multiplied in their effectiveness by use in conjunction with the other. Data analysis by multidimensional visualization, which has the generic objective of deducing a process’s Best Operating Zone (BOZ) just as statistical analysis seeks to clear the way for regression modeling, operates by transforming N-dimensional data onto a two-dimensional surface where it can be readily seen and interrogated. The number of variables involved (columns in the dataset) can be arbitrary while absolutely no information is lost as no assumptions (e.g., concerning distribution properties) or abstractions (such as limited information in discarded higher-order principal components) are made or models built. Hence, per the schematic of Fig. 35.1,6 what one sees is what one gets, and no information latent within a dataset can escape. This is probably best illustrated by an example of data analysis through what have informally become known as Nehring plots (after the

y

P

P z

x

x

Orthogonal coordinates FIGURE 35.1

y

z Parallel coordinates

The parallel coordinate transform.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.4

ADVANCED PROCESS CONTROL 35.4

FAB YIELD, OPERATIONS, AND FACILITIES

product engineer who pioneered their current use) in semiconductor applications.7,8 Consider the diagram of Fig. 35.2, where line level CMOS data is plotted in parallel coordinates—the multidimensional data visualization and analysis technology whose basic underpinnings are sketched by Fig. 35.1—to illustrate the reality of what had escaped purely numerical analysis. By laying data out along parallel, rather than conventionally orthogonal axes, one can engage however many variables are rationally necessary to describe a process—depicting, in this case, yield and speed sort along the two leftmost axes while 14 product engineering variables thought to drive them are spread to the right, and every line (black or gray) represents an actual lot-level observation. Between triangular query markers on the yield and speed sort axes are isolated, in gray, all lots falling within desired specification for both those criteria and hence very rewarding for the line to process. Note, however, the dark region (or “black hole”) associated with poor performance lots in variable X15 positioned between two bands of gray (highly desirable) production. For reasons unknown—but eventually rectified by circuit redesign—there existed a subrange within an ostensibly usable range (from the lowermost to uppermost gray observations) on X15. Since this subrange behaves as a void (hence, the term “black hole”) any lots processed within its span are essentially poisoned as high yield, high speed sort product. More troubling still from a manufacturing perspective is the position of that hole, which itself is unobservable by any means other than parallel coordinate data visualization. Being nearly centered in the design manual range of X15, everything manufacturing did to mean center and reduce variability in X15 simply worsened the problem. Compounding this is the behavior of X13 and X14, where the mean of all points (black as well as gray) is clearly different from the mean of only gray (premium production) lots. Hence, those variables too were mistargeted relative to the line’s most economically desirable results. Unsurprisingly, none of this had proven observable by conventional means of numerical analysis, which in fact served only to mask the true nature of this situation. Note, however, that whether across a full line or simply a large, intricate unit process, the key to solving difficult problems often lies in restricting the number of variables to only the few hundred that might be unequivocally involved. Hence, engaging principal component methods or engineering analysis followed by multidimensional visualization frequently proves a very powerful combination. Eventually, one will have visually mined all that can be learned from a dataset. As the analysis engaged is entirely visual while the leading system for such discovery (Curvaceous Visual Explorer, or CVE) supports a wide variety of queries (all logically combinable by AND, OR, and NOT operators) as well as cluster algorithms and other calculation capabilities, that outcome is typically very swift. At this juncture it will be time to finish dissecting data and determine which variables really count, leading directly to the deduction of a BOZ. Given the assumption of negligible interaction among variables—something of a stretch in most of semiconductors, but one corresponding to the “window” in which fab processes are conventionally operated—a very quick handle on what variables are significant can be quite readily obtained. This is done by simply selecting desirable results, such as the yield and speed sort combination of Fig. 35.2 and fitting a visual “box.” That box operates by ordering variables to the extent a range query on any variable selects desired results, executed for all possible orderings and feasible ranges of variables driving results. Hence, at its completion, one has an N-dimensional box defined by process variables and ranges that associate with desirable process results as well as ordered by their degree of variable selectivity. Such a box is illustrated by Fig. 35.3 for the data of Fig. 35.2. Interactions have been neglected, so this result is simplistic in nature but an excellent place to start in terms of quickly deducing variables that actually drive performance. Keeping all selected variables and adding back anything non-selected from, potentially, a field of several hundred variables—which engineering judgement suggests really should be involved—then querying again on desirable process results generally produces an excellent BOZ couched in terms of variables essentially known to be significant. 35.2.2 Process Modeling The fundamental objective of modeling is to produce a faithful representation of process behavior suitable for the control task at hand. Hence, models vary not only by the mathematical technique applied—there are several different types, for instance, useful in FDC—but also by control objective.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

21:12

Page 35.5

A parallel coordinate plot of CMOS manufacturing data—note black hole in parameter X15.

ADVANCED PROCESS CONTROL

FIGURE 35.2

Geng(SMH)_CH35.qxd

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

35.5

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.6

FIGURE 35.3 Best Operating Zone (between triangular markers) for independent variables of the original dataset in Fig. 36.2, as devised by a multidimensional “box” query.

ADVANCED PROCESS CONTROL

35.6

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.7

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.7

Product level models of functional yield and speed sort distribution employed to tune the line as a function of ∆L, ∆W, electrical insulator thickness, and so on, will consequently have a somewhat different structure than models of polish rate and uniformity as a function of carrier speed, platen speed, and the like. The latter, of course, are engaged in R2R Control of Chemical Mechanical Polishing (CMP), but both are polynomials. Thus, the topic of process modeling essentially becomes application specific, but the basic types of utility in APC as currently practiced in semiconductors (variation, univariate pattern fitting, polynomial, and geometric) are discussed next. Note that there are other salient model types such as neural nets and time series models which have respectively found application in line optimization (with limited effect) and highly successful real-time adaptive control on an individual parameter level (reducing variability by nearly a factor of three).9,10 They are omitted here, however, due to limited applicability within current practice. Variation Models.11 The variation models discussed under numerical data analysis find broad application in the area of chemometrics, which deals largely with handling of measurement data in the field of chemistry. In specific, however, it engages mathematical and statistical methods to deduce state information regarding a chemical system from the set of all measurements taken. Hence, in semiconductor manufacturing this is the purely mathematical method for wringing event information out of the virtually indiscriminant piles of numbers native to databases throughout the industry. Per Fig. 35.4, this is done by transforming (after various scaling and mean centering operations) multidimensional data into principal components—orthogonal linear combinations of the original variables—then modeling principal component relationships and discerning (ideally graphically) deviations from the norm. Such deviations take two forms—those that are excessive in magnitude but still within the principal component modeling and those stemming from observations to which the model simply has no relevance. In either event, from a process perspective, something unusual has happened and in uncovering that a variation model originating from what would elsewhere be called chemometric analysis has done its job, even though what actually happened remains an open question. That answer is often readily found, however, by discerning the principal component

8

Sample with large Q Unusual variation outside the model

First PC

6 Sample with large T 2 Unusual variation inside the model

4

2

Second PC

0 6 6

4

Va

riab

le 2

4 2

2 0

FIGURE 35.4

0

ble 1

Varia

The relationship between a principal component model and unusual observations.12

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.8

ADVANCED PROCESS CONTROL 35.8

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 35.5

Library of primitive shapes for univariate pattern fitting methods.

farthest from the bounds of normal behavior and examining its loadings (contribution from each original variable) to deduce likely candidates for investigation. Univariate Pattern Fitting (Shape) Models.11 Key to getting answers in real time is an ability to algorithmically recognize and react appropriately—while conducting any useful calculations—to features or patterns apparent in signal data from modern manufacturing tooling. This is the semiconductor industry equivalent of telemetry data analysis, with objectives being to drive sophisticated forms of real-time (vice R2R) process control, find specific fault signatures, and check conformance of an overall signal profile with its expected norm. To accomplish this via means of syntactic (as opposed to discriminant) recognition, individual signals are parsed against templates created with a small lexicon of primitive shapes (Fig. 35.5). The library of shapes recognized, each of which is tailored to match a test shape of interest by statistical calculation of primitive fitting parameters, can consequently be combined to match signals of arbitrary complexity and profile. This builds a model for process behavior as encompassed in one or more signals based on their expected shape during normal processing. Hence, real-time or postprocess parsing amounts to associating each shape-enumerating segment of a template with a corresponding stretch of signal data, then reporting a match (of the entire template) if and only if all specified shapes are found. Figure 35.6 illustrates such a scenario, where the recognition engine has been instructed to report on the matching of all individual shapes, which are consequently outlined within separate boxes. In addition to facilitating process control decisions such as endpoint and checking signal conformance (from the processing of one or a stretch of many wafers), such capability is immensely useful when interrogating large bodies of data for specific signatures. Essentially this solves the “needle in haystack” problem of archival signal data analysis to the extent that characteristics of sought after features are known. Polynomial Models. Polynomial models of process outputs (Y1, Y2, Y3 . . .) as a function of inputs (X1, X2, X3 . . .) are the desired result from regression modeling, a highly useful statistical technique whose path will have been cleared of mathematical obstacles by the data analysis described previously.

0.9 0.4 −0.1 −0.6 −1.1 −1.6 0 50 FIGURE 35.6

150

250

350

450

550

650

750

850

950

1050 1150 1250 1350 1450 1550

Shape recognition via syntactic methods for a complex, repetitive signal.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.9

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.9

These are point modeling methods, fitting coefficients to a function which will predict a numerical value (as opposed to the interval or range generated by geometric models) for any set of input values. Although there are variations, the basic functional form for such models is typically one of Y = aX1 + bX2 + cX3 . . . + constant (linear, or first order) Y = a1X 12 + b1X1 + a2X 22 + b2X2 . . . + constant (quadratic, or second order) Y = a11X 12 + b1X1 + b12X1X2 + a22X 22 + b2X2 . . . + constant (second order, with first order interactions) Clearly, as the number of process inputs or predictor variables (Xs) increases, the number of coefficients necessary to fit such a model does as well with a full quadratic model including first-order interactions among N variables requiring ((N + 1)2 + (N + 1))/2 coefficients. This, in turn, drives a data requirement in terms of both the quality and quantity of observations necessary to accurately fit model coefficients. Moreover, if such models will be used for control, their quality becomes a paramount issue, and modeling data of unimpeachable quality becomes required. For this reason the technique of experimental design which, like numerical data analysis and regression modeling will be well addressed by any major statistical analysis system, has become the method of choice for data generation to fit polynomial models of a critical nature that are expected to see little change. Further, once fit using data from any source, polynomial models will typically be refined by deleting terms of marginal statistical significance to produce a higher adjusted R2 value or, essentially, the percentage of variation explained. Residual values—the deviations between predicted model values and observations—will then be examined for evidence of cycling or any indication of either poor fit or an unknown variable that, although not considered, is driving results. Also worth noting are point centered quadratic models, which rather than implicitly referencing the origin, instead calculate X values with respect to a point in space. The most salient example of this useful in-process control are the models created by a sequential optimization system known as Ultramax,13 which are actually Taylor series expansions about a point that can shift as optimization proceeds. Being at the core of what amounts to an adaptive control engine, these are quite sophisticated in their development, progressing from limited linear models to quadratic models, and finally, when sufficient data become available full second-order models with first-order interactions. Adding intrigue to their growth, moreover, are proprietary heuristics able to weight the influence of individual data points on the model as a function of age and distance from a perceived local optimum. Notably, data is also acquired in a sequential fashion (geometric models share this characteristic in certain applications) as opposed to being generated by rote execution of an experimental design matrix before any form of model can be created. Whatever the sophistication of modeling technique engaged; however, all models are subservient to the objectives behind their creation. Hence R2R Control applications, which need only a few degrees of limited freedom to essentially trim process results, are often driven by simple linear models while line level process tuning executed by Product Engineering relies on full second-order polynomials with first-order interactions, and adaptive control engages sequential models. Geometric Process Modeling.7 Consider again the high yield, high speed sort lots highlighted in gray in Fig. 35.2. The “holes” on X15, notwithstanding, represent instances where the manufacturing line has performed in an ideal fashion, not only delivering optimum material but also tracing the multidimensional path along which best results occur. The pathway, which contains both range and interdependency information for process variables, hence defines our BOZ. Moreover, because data is expressed in parallel coordinates, where all the variables can be simultaneously seen, we can see that optimum parameter range and interdependency information as well. Referring once again to the gray (economically optimum) query in Fig. 35.2, one can define a multidimensional shape by tracing only the outline of area—both on axes and between them—corresponding to the uppermost and lowermost appearance of gray lines. Such is displayed in Fig. 35.8 and encompasses the area where desirable production outcomes prevailed, hence forming this process’s BOZ and creating a geometric

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.10

ADVANCED PROCESS CONTROL 35.10

FAB YIELD, OPERATIONS, AND FACILITIES

72.00 100.0 97.30 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 0.488 0.326 0.903 149.0

55.70 89.40 84.00 93.20 97.30 92.00 94.90 96.80 90.60 96.90 94.70 97.10 0.333 0.272 0.782 141.0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 FIGURE 35.7 A Multidimensional BOZ (between jagged upper and lower lines) for rescaled CMOS data of Fig. 35.2. A centerline between established process measurements represented as balls and bisecting projected available ranges traces optimal product trajectory with range arms described in the text projecting working process latitude at various measurement gates.

process model that describes its behavior. At their intersections with variable axes, the jagged upper and lower lines of a geometric process model define historically valid ranges for high performance production, while between them they encode variable interdependency information. As a practical matter it is best if holes are eliminated, but by staying within this zone—which represents how a product design will manufacture under the given process and tool set for which data was available—it can be guaranteed that a particular lot will deliver optimum results as defined by the initial (gray) query of Fig. 35.2. Projecting the BOZ shape as a function of upstream results, which do change the picture in a batch sequential manufacturing scenario such as that of semiconductors onto parallel coordinate axes, then yields the available process latitude as portrayed by the distance between working range arms in Fig. 35.7. This is true for a product lot at each process step as it moves down the manufacturing line to eventually return economically rewarding results at test. Working range arms themselves start at a point on each variable axis, where the process is either observed (symbolically represented as a ball) or estimated (in which case no symbol is used beyond the origination point of a bisector line) and spread as two arms to the adjoining axis bisected by a centerline.

35.3 APPLICATIONS This section keys off the data analysis and modeling methods described previously to discuss APC applications that leverage them. Hence, with the necessary groundwork laid fault detection and classification, R2R Control, and optimization with adaptive control will be addressed, while variations in all three as a function of the modeling technology engaged are contrasted. Consequently, at the conclusion of this section, the reader will understand which analysis and modeling techniques are

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.11

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.11

applicable within what domain of APC application as well as their relative strengths and weaknesses. Equally obvious will be those technologies that exhibit more generic applicability and those best applied as a point solution against a particular class of problem. 35.3.1 Fault Detection and Classification Consistent with its nomenclature the objective of fault detection and classification (FDC) is to evaluate a set of measurements—typically taken in real time (i.e., trace data), although analysis may actually occur after the fact—to ascertain whether any data or patterns therein are inconsistent with “normal” operations. Hence, a credible model of “normality” must be available with an underlying assumption that deviations from the expected behavior represent tool or process issues which, once classified, can be swiftly resolved by activities that have been derived in advance. As a result of this, the type of model engaged (variation, univariate pattern fitting, and geometric models are all relevant to the task) becomes key and effectively drives both the course and efficacy of FDC. This has a typical goal of determining whether any process tool deemed critical enough for a model to exist is or is not fit to process its next wafer. If not, the question becomes what must be altered or repaired. Further, given variation and in particular, geometric model types, this technology is applicable to product as well as tool level data. That level of awareness is rare in product engineering organizations, however, which tend to engage less sophisticated forms of data monitoring to detect line level process issues and focus primarily on line optimization, leaving FDC to equipment, process, and APC organizations instead. Variation Model Application.14 Based on the results of SEMATECH’s J88 project in FDC for metal etch data (including induced faults) taken over three distinct time periods, it is clear that chemometric methods offer at least part of the solution to the generalized FDC problem. Experience from that project, where a broad variety of models and analytical techniques were engaged on test data, strongly suggests that a 50 to 60 percent capture rate can conservatively be achieved for process faults on arbitrary semiconductor data.12 Further, the simplest technique tested—principal component analysis on parameter mean values, which is relatively easy to execute—proved very competitive in sensitivity to the most complicated of methods engaged. Hence, under the presumption that models are updated to maintain their sensitivity and robustness, the J88 recipe for chemometric fault detection is: 1. Reduce sample data for initial model building to mean parameter values of each observation then mean center and scale the resulting dataset. 2. Derive principal components from the scaled, centered dataset. Note that there will be as many principal components as parameters in the original data. 3. Keep the minimum number of principal components necessary to capture an acceptable amount of variation apparent in the original dataset. 4. Build a model, ideally graphically (and potentially even using parallel coordinates) of the relationship between retained principal components. 5. Compare new data to the existing model, declaring a fault condition when something is obviously wrong graphically or Q and T2 statistics display excessive magnitude. 6. Regenerate the comparison model either periodically or based on an event trigger to include new process data. The mathematical techniques behind this marriage of variation models and chemical industry methods have been well worked out. Hence, they have stood the test of time with (for once) an industry beyond semiconductors paying the price of their inception and will detect numerical anomalies within complex systems. Mapping those anomalies back to end of line results or equipment failures, however, is generally not feasible, which undercuts the credibility of such detection methods in semiconductor application. Further, as there is no direct linkage between detected faults and tool or process conditions, there is, in effect, no classification mechanism, and

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.12

ADVANCED PROCESS CONTROL 35.12

FAB YIELD, OPERATIONS, AND FACILITIES

one must investigate anomalies through the analysis of errant principal component loadings. This, combined with relative mathematical complexity and issues surrounding variation model maintenance for a large number of process chambers, has acted to limit the application of such methods within semiconductor manufacturing. Univariate Pattern Recognition Methods.14 Mechanistically figuring out when any one of the numerous data streams available from manufacturing tooling doesn’t follow its typical pattern is often key to recognizing that a problem has occurred and driving its diagnosis. To accomplish this end all relevant signals—those with a significant bearing on performance of the equipment or viability of the process it orchestrates—must be identified. Usually this is not difficult, and one has more than enough signal candidates to work with. Each signal, however, then must be broken down (typically along lines of process recipe steps) and modeled as a template describing its expected behavior. This is done in terms of a lexicon of primitive shapes—such as steps, ramps, and straights—including gaps over sections where signal behavior is of no interest, with governing parameters for each primitive shape statistically fit to a sample signal. Once complete, this battery of “conformance” templates is then used to parse signals from tool data streams, either in real time or post process, with templates for which no match is found indicating problems and reporting an error condition. This can be usefully augmented by numerical analysis of raw signal behavior comparing mean, standard deviation, and other properties against allowable levels while, once issues are detected, recognition templates can be engaged to localize and classify the fault condition. Hence, by automated means, a broad spectrum of tool signals (but not their interactions) can be tested in parallel for adherence to expected norms. Note that Fig. 35.8 actually represents a failure condition since only two of the pattern matches found are normal; an equipment problem had in fact been detected. Once a fault condition is detected, it must obviously be localized and, if at all possible classified in some recognizable sense to both speed resolution and drive “tool learning” against its future existence. This problem is somewhat simpler than overall conformance checking in that once an issue has been discovered and analyzed by engineering means, one must only assemble a template to match the specific failure mode rather than the process run pattern of an entire signal. To illustrate such, consider a chamber pressure abnormality where a sealing issue or transient outgassing from an unexpected source creates a glitch in what should otherwise be a smooth pumpdown curve. Given that spikes of this nature leave no other artifacts around them, they are easily matched as a glitch, i.e., a sharp rise followed by an almost equally sharp drop in the measured signal level. In the lexicon of a system designed for this purpose and known as Patterns, this amounts to a “Trending-Up,” followed immediately by a “Trending-Down,” governing parameters which are statistically synthesized against the failing sample signal. Such parameters effectively train a template to the specific class of feature being sought, so a “glitch” template matches only glitches and not other rising then

900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 −0.2

FIGURE 35.8

−0.1

0

0.1

0.2

0.3

The template-driven detection of hardware failure.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

0.4

Geng(SMH)_CH35.qxd

04/04/2005

21:12

Page 35.13

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.13

falling behavior, with matching results analogous to those of the abnormality in Fig. 35.8. This character of signal templates effectively encapsulate and, when engaged to parse signals, mimic human intelligence. Hence, they take a fair amount of forethought to set up—one must have intellegence to encapsulate—and are a far cry from strictly numerical and somewhat rotely mechanistic detection schemes. Thus, univariate pattern recognition methods, which require time based data and cannot deal with variable interactions (this latter would be effectively lethal in a Product Engineering scenario), do provide an excellent, fine-grained means for Fault Detection with explicit Classification on semiconductor tools and processes that have been carefully studied. Such is particularly true if templates have been devised to allow parsing against multiple signals from the same system. Geometric Process Control.7,15 Some fabs possess the skill and infrastructure to directly associate wafer level EOL test results with wafer level in-process measurements available at a tool level. Often time it is found the parallel coordinate methods of data analysis discussed previously allow the deviation of a BOZ directly tied to product performance. Hence, by drawing visual queries against desirable product properties such organizations can “see” what the bounds of “normal” tool and process behavior are, entirely without resorting to assumptions that either numerical anomalies or departure from typical patterns of univariate signal behavior are, by definition, problematic. This allows the deduction of a tool level geometric model for unit process behavior of unassailable credibility—nothing outside its bounds ever produced desirable product results—and thereby overcomes the principal problem (that of credibility) plaguing FDC implementation. For fabs that cannot link equipment and product level data, there are other options. Consider the case of sputter cleaning prior to PVD, where incomplete ashing of photoresists can wreak havoc with downstream processing but effective handling of jReturn Goods Authorizations (RGA) data deftly detects faults from incoming wafers, process failures, or tool problems.16 The objective, of course, is not simply to numerically detect those faults but do so in a fashion consistent with process control that readily leads to their classification, diagnosis, and elimination. Examining available data from all dataset rows, good and bad, yields the parallel coordinate plot of Fig. 35.9 where min., max., mean, and standard deviation are plotted consecutively following the observation number (axis P1) for chamber pressure and concentration for each of eight potential chamber contaminant species. Note that this compression, to “key numbers” synopsizing the behavior of real-time data (usually per step within a process recipe) with only a handful of information-rich parameters, is an excellent technique for reducing huge volumes of data to a basis useful in wafer by wafer (the typical objective) as opposed to second by second FDC. Values of minimum chamber pressure where the pumps could not pull vacuum below 10−5 torr have been highlighted by the visual query in gray, since this obviously represents abnormal processing. Eliminating those observations from consideration—that is, focusing only on known good data—and forming clusters for min., max., mean, and standard deviation of each variable taken as a group (yielding cluster axis one, Cl1, for pressure; cluster axis two, Cl2, for species one, etc.) draws a parallel coordinate plot with an additional axis for each cluster. The problem then reduces to eliminating anomalous observations or those stemming from known faults to build a BOZ characteristic of operation with no incoming wafer problems, process issues, or equipment faults (incipient, or those representing obvious casualties) when the tool is running well. Observations falling into the “no cluster” bucket (the lowermost value, ~1, on each cluster axis) are obvious candidates for this, as are clusters with very few members. Shifting our focus to exclude these and all similar observations finally yields a dataset, which contains the information necessary to build a known good BOZ. Conducting that operation essentially establishes a channel within which an individual tool must operate when exhibiting fault free production in this instance. Consequently, taken as a group, such data—which will appear in parallel coordinates as a black mass—defines the multi-dimensional shape for desirable tool operation. Within that shape are encoded two types of information drawn from the historical sum of all valid operations: 1. Extreme limits, found where the upper- or lowermost black lines cross the vertex of a variable axis, over which an RGA key number measurement has ranged before and still yielded good tool operation. 2. The interrelationship, depicted by an outline of black lines between adjacent variable axes, of RGA key number measurements for valid operation.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.14

FIGURE 35.9

Post-sputter-clean RGA data with pressure issue highlighted in gray.

ADVANCED PROCESS CONTROL

35.14

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.15

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.15

The second class of information, concerning interrelationships, is particularly key since it allows us to determine when any variable, which may be well within its historically valid limits, is beyond the pale of normal relationships with all other variables and the sputtering system, hence in a fault condition. This adds enormous sensitivity to fault detection and R2R Control schemes, since it allows the derivation of working limits (these project as straight lines between adjoining variable axes in Fig. 35.10) within extreme limits (the jagged upper and lower lines defining our geometric model) for any configuration of current measurement points symbolized by balls. Such, in turn, allows much more processing latitude to achieve good results than fixed limits, which by definition cannot consider the ramifications of current data for all possible variable interactions and must be extremely tight to generate desirable results under all conditions. Of further benefit consider, in the sputtering “process camera” of Fig. 35.10 (which is actually a combined fault detection and R2R Control vehicle) the transgression of the working limit borders on variable vertices M29 and M37. These two, taken together, characterize an underlying event, which drove the sputtering system to an alarm condition. Treating each variable vertex as a letter in an alphabet spells the name of that event, which now need only be cataloged and its resolution recorded to mechanize the response in the future. Hence Geometric Control methods, initially developed for use within industries where control problems are much more demanding (as well as exothermic), provide an elegant and entirely visual solution, which does not suffer from high modeling or model maintenance costs to the FDC problem within semiconductors.

35.3.2 Run-to-Run Control Leaving aside the question of real-time control practiced at an actuator level, there are effectively two chances for optimization in batch processing operation: 1. Between batches, to essentially steer product lots down the manufacturing line—although a gray area exists, this is a product engineering responsibility, for fabs that operate at such a level of sophistication—to assure a better distribution of results at test. 2. Within batch, which, in the semiconductor case, amounts to tuning control—typically wafer by wafer or R2R—through the adjustment of recipe set points (polish time, down force, etc.) to compensate for incoming variability as well as observed (or at least predicted, usually by wear factors) tool drift. Note that this approach occasionally extends17 to manipulation of two or more unit processes (e.g., in a photo/etch sector) to achieve an outcome desired overall. Although the former is an interesting topic18 its treatment would be lengthy while the relationship to the current domain of APC (i.e., FDC plus R2R Control) is notably avant-garde. Hence, for the purposes of this section only, the second item, which readers will no doubt recognize as the standard definition of R2R Control, will be discussed. Further, as with FDC that discussion will be structured by applicable model types, or polynomial, sequential, and geometric model approaches. Polynomial Based R2R Control. Polynomial models have been at the very heart of R2R Control efforts since the first R2R recipe update recommendations were transmitted to a major semiconductor manufacturer based on output from an experimental algorithm at MIT in the early 1990s. That manufacturer’s motivation was simply to find a means of gradually weaning its operations of an overzealous and rigidly imposed SPC implementation that had become, essentially, dysfunctional. By leveraging internal funding with the SRC SCOE in Cambridge, Massachusetts, however, they got a great deal more than was bargained for as the entire industry has seen dramatic Cp and Cpk improvements from a relatively simple process level control method that is now rapidly displacing the use of SPC alone. Successful implementations have been reported in etching, photolithography, film deposition, and CMP with, clearly, products in manufacture today at yields that would not have been technically feasible without R2R Control methods. Numerous variations of R2R Control algorithms have been tried over the past half-decade, during which the absolute prohibition (as per the Statistical Process Control doctrine) against process

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.16

FIGURE 35.10

Process camera for sputtering system using BOZ derivation method described in text.

ADVANCED PROCESS CONTROL

35.16

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.17

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.17

level recipe changes has been eroded at major manufacturers to the point of all but breaking down. This has yielded some interesting, and generic lessons: 1. Any reasonable R2R implementation, even if simplistic and executed on a single process scale, will yield striking benefits for problematic processes over no R2R Control. 2. Performance differences between R2R implementations, from the crudest to the most intricate, are relatively small. 3. Straightforward methods, based on linear models with exponentially weighted moving average (EWMA) compensation of a constant term for tool drift and potentially modest adaptation work well and can be easily deployed. 4. Logistically integrating the correct data for the right tool and current wafer with the appropriate algorithm will be the biggest implementation problem, and potentially pose an ongoing nightmare that requires an integration framework for its solution. Development of R2R approaches continues but, leaving the last point above for IT organizations to overcome, the workhorse model for R2R Control implementation within the semiconductor industry has become19 YP,t = at−1 + bXt E = Yo,t − YP,t at = WEt + (1 − W) at−1 where P = predicted O = observed t = run number W = EWMA weighting factor, between zero and one Note that Xt are process recipe settings for manipulable variables (time, down force, carrier speed, etc.), with a separate constant (b) for each such term and—per the “law of requisite variety”—at least one X for every Y (polish rate, uniformity, etc.) under R2R Control. Hence, since the system of linear equations implied can be both readily and rapidly solved, with demonstrably good effect across the industry, R2R Control by the most conventional of methods is clearly here to stay. Optimization and Adaptive Control Based on Sequential Polynomial Models. Another option for dealing with variation among incoming material properties combined with drifting tool performance is to simply leave a sequential optimizer that has adaptive properties on line as a controller. Even if that approach might seem a bit heavy handed, such artificial intelligence systems have been successfully in use since the mid-1980s on very demanding control problems.20 Further, the sequential optimization technology involved (as best embodied in a system known as Ultramax) relies upon the notion of producing information about a system while driving its performance. Hence, trials concerning how to best run a system are conducted one (or at most, a handful) at a time, with routine process runs acceptable as trials and results from those tests—whether trial recommendations were followed faithfully, modified, or completely ignored—fed back into the sequential optimizer. With the shot of fresh data Ultramax remodels, fitting local second order polynomials as an optimum is approached (less sophisticated and data hungry models are used when fewer observations are available). This is followed by the generation of new control advice designed to both step toward the optimum while generating more information about how to further tune the process under control. Hence, a jagged, but remarkably efficient, hill climbing approach is followed, with internal safeguards in play to preclude sticking on a local optimum or stepping into foul territory where excessively poor results are produced, as ideal performance is continuously sought. Consequently, this system behaves as a multiple-input, multiple-output adaptive controller, adjusting for changes to optimization requirements (such as a maximum acceptable nonuniformity) and external conditions

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.18

ADVANCED PROCESS CONTROL 35.18

FAB YIELD, OPERATIONS, AND FACILITIES

(off-spec incoming film thicknesses or varying pattern densities) while learning to optimally control a polisher, photo/etch cluster, CVD system, etc. The net result is a very powerful, albeit “black box” tool, which to run one need only know process inputs, outputs, and external influences, and for which models will be automatically built in the course of normal operation. As the optimizer engaged is somewhat relentless, however, and unless switched off deliberately experiments to probe for improved performance such an approach is best reserved for very problematic control situations, typically characterized by high variable counts as well as excessive noise (line level optimization has these properties) and frequent upsets. In this realm steady-state behavior is virtually unknown and continuous optimization of process, as opposed to control, performance will always be regarded as a blessing. Geometric Process Control for R2R Application. The objective of R2R Control is to derive revised set points which feed-forward against incoming material variability and backward against changes in equipment behavior by the interrogation of a model. Hence, as long as that model contains terms for incoming material properties and observed or predicted drift characteristics (e.g., the previous run’s polish rate) it can be engaged for R2R Control. In geometric modeling, which is highly visual, there are no equations and hence, no terms, only data entries joined by polygonal lines for incoming material factors, operational variables, measured results, and previously observed results. Consequently, by an appropriate ordering of geometric model variable axes, one can input incoming material and previous performance information in addition to aging factors as well as desired outcomes (polish rate, uniformity, etc.) and obtain a “how-to” projection. That projection, moreover, will be in terms of viable ranges for all manipulable variables to accomplish desired ends given current tool behavior and incoming film properties. Consider again the geometric model of Fig. 35.7, by graphically entering values for X1 and X2 viable ranges for X3 through X16 are returned. Thus, aside from inclusion of previous performance information, geometric control for R2R operation is no different than that for lot disposition in product engineering applications. Now, however, one can see all information as well as—by the incorporation of observed deviations from predictions— whether R2R Control itself is in a fault condition.21

35.4 APPLICATION CONSIDERATIONS As the breadth of deployment for APC widens—from univariate to multiple univariate then multivariate applications paralleled by single process to multiprocess and, eventually, global cascaded implementation (see Fig. 35.11), the investment and coordination necessary to effectively drive control efforts increases proportionally. As noted previously, however, their return is anything but linear—with simplistic approaches generating positive but pedantic results while broader based efforts deliver line level wins, as recently reported by AMD’s Fab30 at the 5th European AEC/APC Conference in Dresden.18 Aside from knitting together a cohesive organization to accomplish a comprehensive task, however, there are other considerations to beware. 35.4.1 Data Integrity Primary among those considerations is the simple reality that no control or analysis system can prevail beyond the borders of valid information. Hence, at an individual variable level the accuracy of all relevant measurements must be known—standards can prove key in this regard, particularly across multiple fabs—and their uncertainty (repeatability and reproducibility) assessed. Measurement information must further be validated as it is gathered into data structures no less comprehensive than the issues they are intended to resolve, as little will halt an APC program with greater swiftness or certainty than high ticket databases crammed with suspect or narrow scope information. In general, it is better to possess limited information which is known to be both good and relevant than boundless access to every number that any instrument or process tool in the plant can produce. More is not necessarily better, and before any value is introduced into a database that will be used for decisions, consideration must be given to how its accuracy and uncertainty will be quantified and consistency against other data validated. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.19

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.19

Integrated structure creation Inputs - First primitive structure Electrical properties - 2nd primitive structure Electrical properties . . . Outputs - Integrated elec. properties Primitive structure creation Inputs - Level N − 1 dopant conc. and distribution - Level N etched image properties - Level N + 1 planarized image properties Outputs - Structure elec. properties Image transfer and film manipulation level N − 1 Inputs - Deposited film properties - Implant mask thickness - Implant mask location - Implant energy - Implant dose - Diffusion time - Diffusion temp. Outputs - Redistributed dopant location - Redistributed dopant conc.

Image transfer level N + 1 Image transfer level N Inputs - Deposited film properties - Developed image properties - Etch anisotropy and selectivity - Etch rate and uniformity Outputs - Isolated etched image feature size - Dense etched image feature size - Etched image feature profiles

Inputs - Deposited film properties - Developed image properties - Etch rate and uniformity - Etched image properties - Polish rate and uniformity Outputs - Isolated image feature sizes after planarization - Dense image feature sizes after planarization

Film deposition

Photolithography

Etch

Inputs - Pressure - Temperature - Flowrates . . . Outputs - Thickness - Uniformity - Physical properties

Inputs - Resist thickness - Resist uniformity - Exposure dose - Exposure focus - Alignment properties - Develop concentration - Develop time Outputs - Developed image properties (dense) - Developed image properties (iso.)

Inputs (per step) - Power - Pressure - Flowrates - B-field - Time Outputs (per step) - Etch anisotropy - Etch selectivity - Etch uniformity - Etch rate

FIGURE 35.11 Abbreviated hierarchy of cascaded control implementation. Note that this does not pertain to any specific process, while extending upward and outward to encompass all steps necessary for device fabrication. Hence, “Image Transfer & Film Manipulation Level N-1” and “Image Transfer Level N+1” intermediate processes would both have their own sub-processes, which are not shown here due to space constraints.

35.4.2 Control Integration Although less obvious, if smooth fab operation is desired the fit of APC efforts with everything they influence is not to be neglected. For simple R2R implementation this means selecting a process operating point, which is relatively insensitive to all process variables except those engaged for control, and linear in response to the latter. Hence, process reaction to unintentional variation will be Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.20

ADVANCED PROCESS CONTROL 35.20

FAB YIELD, OPERATIONS, AND FACILITIES

negligible while response to control variables is both well understood and readily tailored. On a grander scale, and reflective of broader control strategies common in mature process industries, is the notion of cascaded control among a hierarchy of processes (shades of this thinking are only now beginning to emerge in semiconductor R2R application) subservient to overall objectives of the line. This is diagrammed in Fig. 35.11 where upper-level processes—which do not exist in a physically identifiable process tool—control lower-level processes by manipulation of their target outputs. Intermediate-level processes then manipulate their inputs, which themselves may be the outputs of still lower-level processes, as a slave to meet requirements established by higher-level controlling processes. This cascade continues, from high level abstractions at the pinnacle of manufacturing control—where plant goals concern throughput, product quality, and ultimately profitability—to more concrete objectives (gate length, transferred image size, test structure resistivity, etc.,) pursued by aggregates of unit processes controlled at an intermediate level. These, in turn, eventually feed marching orders (e.g., resist thickness and etch uniformity) to be executed at a unit process level by individual pieces of manufacturing equipment. For this scenario to work, as it commonly does in established industries where control investment has become a competitive priority, one must be able to rapidly build and adapt control models that encapsulate the transfer function from inputs to outputs at each node in this hierarchy. Some industries, with large unit processes governed by well understood chemistry and physics that change only slowly—that is, places where a 30-year plant life is common—can afford that investment on a first principles basis. Others, where, predictable change remains a dominant factor, however, must obviously devise mechanistic methods to create and maintain such models as well as engage them against both process tuning (optimization) and control objectives. Those methods, moreover, must be operable across a swath of plant population no less broad than the overall control hierarchy. Hence, technologies which require doctoral degrees to run or create cubic yards of models that need departments of specialists to maintain will simply fail in the long term, as even if plant management is interested the demographics of manufacturing organizations (certain quarters of Europe excepted) cannot support that load. Unavoidably, such modeling and control activities will also cut across the organizational boundaries found in most facilities, but their recognition and subsequent implementation as an overall control strategy will deliver strong return given: 1. Timely as well as accurate measurability of all inputs and outputs in the hierarchy. 2. Assurance that upper levels of the hierarchy operate more deliberately (hence, react more slowly) than lower levels, to preclude driving an entire line into oscillation. 3. An equal or greater number of inputs (knobs which can be turned) than outputs (objectives to be achieved) at each node in the hierarchy, thereby satisfying the “law of requisite variety.”

35.4.3 Ongoing Operation Finally, and inescapably, one must deal with the effects of time, particularly in change driven manufacturing operations where any process is fair game as a work in progress until the product family it serves is discontinued. From the moment they are placed in service control models, and hence the systems built upon them, degrade in quality and frequently application relevance—to the extent that they will eventually be switched off by Operations—unless assiduously maintained. In essence, just as equipment must be maintained so must the control mechanisms that drive it, and the extent to which effective process controls can be implemented will be governed by an organization’s ability to service that implementation. As suggested earlier, decisions made on the control and optimization technologies applied will have a large influence on this, with resource hungry—typically best measured in terms of manpower and data required rather than raw cost alone—selections effectively serving to limit the scope of overall implementation. Further, such also implies the need for a standing organization, much like those that drive product engineering or develop and maintain device models, to monitor and maintain the efficacy of APC. This includes R2R and FDC work as well as any ongoing optimization, encompassing the address of issues and maintenance of models as well as appropriate (change for change’s sake is seldom welcome) upgrade of underlying technology.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.21

ADVANCED PROCESS CONTROL ADVANCED PROCESS CONTROL

35.21

As semiconductors continue to mature and escalating levels of control technology proliferate from conventional process industries into chip manufacture, moreover, that same organization must both maintain its awareness and steward the implementation of new technology. Hence, older and less effective methods will not be allowed to preclude the implementation of new methods or themselves be irrationally demolished by fitful and unplanned implementation of revolutionary change. A comment by one keynote speaker at the 11th AEC/APC conference that “people lose their heads in revolutions”22 is particularly apropos. The upshot being that control technology is best leveraged when planned as a function of the objectives desired and resource available, just as all other business aspects of the semiconductor industry are planned, and its implementation, wherever possible, evolutionary.

35.5 FUTURE TRENDS AND CONCLUSIONS Process Control implementation is a cash cow for any fab not too unimaginative or manpower starved to pull it off. Further, that return increases with the duration of time a process generation can be left in place, while such investment is subject to considerable efficiencies as a function of opportunities offered by savvy organizational and technical choices. In current fab organization Product and Control Engineers—with the latter still being a rare and generally overworked species—operate in disparate worlds with similar tools on opposite sides (line level versus tool or unit process level) of the same process. This would be simply unthinkable in competitive enterprises of an established, cost/ton industry. Both efforts tend to be undercapitalized, but if staffed to critical mass and operated in unison could effectively multiply their joint effectiveness. Further, some technologies discussed above, stemming from far more recent and unified mathematical development, readily go double duty. These are effective in both FDC and R2R Control on a unit process as well as line level, thus halving integration and software costs while greatly speeding implementation. As always, but more so now than ever, the future belongs to the efficient and smart money will win in the end.

REFERENCES 1. Barna, G. G., “Fault Detection and Classification on a LAM 9600 Metal Etcher,” presented at the SEMATECH AEC/APC Workshop VII, New Orleans, LA, November 1995. 2. Eshbach, O. W., and M. Souders (eds.), Handbook of Engineering Fundamentals, 3d ed., Wiley, New York, 1975. 3. Fox, R. W., and A. T. McDonald, Introduction to Fluid Mechanics, Wiley, New York, 1973. 4. BBN Domain Corporation, Principal Components, pp. 5–21, Cambridge, MA, 1995. 5. Rampf, G., and R. H. McCafferty, “Application of Residual Gas Analyzers for Multivariate Fault Detection via Geometric Process Control at Sputter Process,” Proceedings of the SEMATECH AEC/APC Symposium XIII, Banff, Canada, October 2001. 6. Brooks, R., R. Thorpe, and J. Wilson, “Geometric Process Control for Improved Alarm Management,” presented at AIDIC, Florence, Italy, May 2001. 7. McCafferty, R. H., “High Road to Process Control: Multivariate Methods,” Semiconductor International, Vol. 24 (8): pp. 257–264, July 2001. Referenced passages originally printed in Semiconductor International and used by permission. 8. Nehring, U., A. Steinbach, and R. McCafferty “Linking Plasma Process Parameters to Tool Parameters and End-of-Line Results,” Micro Magazine, May 2002. 9. McCafferty, R. H., “Real-Time Automation of a Dry Etching System,” SPIE Advanced Techniques for Integrated Circuit Processing, Vol. 1392: pp. 331–339, Santa Clara, CA, October 1990. 10. Bresnock, F. J., and T. Stumpf, “Implementation of Adaptive Process Control to a Dry Etching Process,” Journal of Vac. Sci. Technol., Vol. 20 (4): p. 1027, 1982. 11. McCafferty, R. H., “Part I—Technology: How to Make a Sensor Smarter,” Solid State Technology, pp. 111–116, Oct. 2000. Reprinted from the October 2000 edition of Solid State Technology. Copyright 2000 by PennWell.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH35.qxd

04/04/2005

21:13

Page 35.22

ADVANCED PROCESS CONTROL 35.22

FAB YIELD, OPERATIONS, AND FACILITIES

12. Wise, B. M., and N. B. Gallagher, “Process Monitoring and Fault Detection Using Multivariate Methods,” Short Course Given in Association with SEMATECH AEC/APC Symposium XI, Vail, CO, September 1999. 13. Moreno, C. W., “Self-Learning Optimizing Control Software,” Proceedings of the Instrument Society of America, Robotics and Expert Systems Conference (Robexs’86), Houston, Texas, June 1986, pp. 371–377. 14. McCafferty, R. H., “Operation: How to Make a Sensor Smarter,” Solid State Technology, Feb. 2001, pp. 105–113. Reprinted from the February 2001 edition of Solid State Technology. Copyright 2001 by PennWell. 15. Rampf, G., and R. H. McCafferty, “Devising an APC Strategy for Metal Sputtering Using Residual Gas Analyzers,” Micro Magazine, July/August 2002, pp. 47–58. Referenced passages originally printed in Micro Magazine. Copyright Cannon Communications, LLC. Used by permission. 16. McCafferty, R. H., and R. W. Brooks, “Multivariate Fault Detection Via Geometric Process Control,” Proceedings of the 2nd European Advanced Equipment Control/Advanced Process Control Conference, Dresden, Germany, April 2001. 17. Moyne, J., “Advancements in Integrated Multi-Process R2R Control Developed on a Fab-wide Integrated Manufacturing Platform,” Proceedings of the SEMATECH AEC/APC Symposium XIII, Banff, Canada, October 2001. 18. Holfeld, A., J, Rabiger, L. Herrmann, V. Heinig, and G. Grasshof, “Application of Novel APC Methods for Improved Device Parameter Control Down to the Wafer Level in Microprocessor Manufacturing in AMD’s Fab30,” Proceedings of the 5th European Advanced Equipment Control/Advanced Process Control Conference, Dresden, Germany, April 2004. 19. Lee, M., and F. Hsiao, “Integration of Adaptive EWMA Controller Design with Process Statistical Monitoring,” Proceedings of the 4th European Advanced Equipment Control/Advanced Process Control Conference, Grenoble, France, March 2003. 20. McCafferty, R. H., “Sequential Optimizer Offers Different Approach for NOx Control,” Power Engineering, Vol. 34 (10): pp. 84–93, October 2000. 21. Brooks, R. W., and R. H. McCafferty, “A Dilemma Defeated—Seamlessly Integrating Run-to-Run Control with Fault Detection and Classification,” Proceedings of the SEMATECH AEC/APC Symposium XIV, Snowbird, UT, September 2002. 22. Rozich, W. R., “Minimizing the Risk of 300 mm Wafer Introduction into Semiconductor Manufacturing,” Proceedings of the SEMATECH AEC/APC Symposium XI, Vail, CO, September 1999.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:14

Page 36.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 36

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES Brett J. Davis Steven R. Trammell Freescale Semiconductor, Inc. Austin, Texas

36.1 INTRODUCTION The semiconductor industry manufactures an array of products on substrates of silicon dioxide and compound (e.g., periodic table groups III and V and groups II and VI) materials, including gallium arsenide and indium phosphide. It does so using chemicals with a wide range of hazards, including the characteristics of health hazard, toxicity, corrosivity, combustibility, flammability, pyrophoricity, reactivity, oxidation, ozone precursor, and global warmer. In addition, the manufacturing equipment poses ergonomic, electrical, mechanical, and electromagnetic energy hazards. The hazards of these substrates, chemicals, and the equipment, as well as the associated wastes and by-products, result in the applicability of a host of environmental, health, and safety (EHS, or alternatively ESH, ESIH, or HSE) programs. EHS programs can be enforced both domestically and internationally by governmental agencies, professional and standards organizations, and customers. This chapter discusses the hazards of semiconductor manufacturing and describes existing EHS programs applicable to them. Also discussed are pending EHS programs and new EHS technologies of interest to the industry. Because EHS professionals typically rely upon an array of resources to benchmark best practices and to stay current on regulations, the chapter includes a table that lists professional support organizations and references useful to EHS professionals in the semiconductor industry.

36.2 EHS HAZARDS FROM SEMICONDUCTOR MANUFACTURING Semiconductor manufacturing poses numerous uncommon workplace hazards to manufacturing personnel, public health, and the environment. Hazards posing risks to personnel include ergonomic, mechanical and potential energy, electrical, chemical, ionizing and nonionizing radiation, and laser. Hazards posing risks to the public and the environment include accidental chemical releases and intentional chemical releases through contaminated exhaust, contaminated waste water, and solid and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

36.1

Geng(SMH)_CH36.qxd

04/04/2005

21:14

Page 36.2

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.2

FAB YIELD, OPERATIONS, AND FACILITIES

liquid chemical wastes. And while not addressed in detail here, EHS professionals at semiconductor fabrication facilities must also be concerned with such common workplace hazards as fire, dangerous weather, and seismic activity (see the Information Resources and Bibliography for resources related to common hazards). An effective EHS hazards control system incorporates security and safe handling of chemicals and wastes during delivery and storage and personnel protection from hazards posed by the manufacturing equipment. Actually accomplishing hazards control requires a combination of complying with generally prescriptive EHS regulations, as discussed in Sec. 36.3, and going beyond compliance by aggressively risk managing under- or unregulated hazards, as described in Sec. 36.4. Most of the hazards discussed in this chapter are encountered in the front-end semiconductor fabrication processes, including photolithography, wet and dry etching, and diffusion and metals deposition. Unique hazards from other front-end processes, such as chemical mechanical planarization (CMP), or from back-end assembly and packaging processes, including probe, bump, assembly, and test are addressed where appropriate. 36.2.1 Substrates Hazards The substrate material used for silicon-based semiconductors, silicon dioxide, which is the primary constituent of sand, does not pose significant hazards itself. On the other hand, gallium arsenide and indium phosphide substrates pose significant health and physical hazards for which many EHS programs apply. The toxicological information for gallium arsenide (GaAs) is derived from the hazards of arsenic, as gallium has low toxicity. The most common exposure route for gallium arsenide is inhalation of particulates. Gallium arsenide has a very low threshold limit value (TLV) of 0.01 mg/m3 or 10 µg/m3, as arsenic, and is considered a human carcinogen. The toxicological information for indium phosphide (InP) is derived from indium. The most common route of exposure is the inhalation of particulates. Indium phosphide has a very low TLV of 0.01 mg/m3, as indium. The target organs are the liver, heart, kidney, blood, and lungs. This material, which is itself flammable, can react with water vapor and acids to form phosphine, which is a toxic and flammable gas. 36.2.2 Process Chemicals Hazards Table 36.1 lists the health and physical hazards of many process chemicals used in the semiconductor industry. The corrosive, toxic, flammable, and pyrophoric characteristics of many of these chemicals result in the applicability of many EHS programs for their storage, use, and waste disposal. In addition to those compounds listed in Table 36.1, there are also a large number of organic compounds used in the photolithography process with varying hazards, including n-methyl pyrrolidone (NMP), ethyl lactate, novolak resin, propylene glycol monomethyl ether acetate (PGMEA), anisole, and a host of proprietary compounds. Generally, the objective of a semiconductor chemical safety program is to prevent any significant personnel exposure to process chemicals, unwanted reactions, and fires. So even where mandatory EHS programs are nonexistent, general concepts of chemical and materials compatibility and prevention of personnel exposure will result in common chemical delivery and use designs. 36.2.3 Ergonomic Hazards Typical ergonomic hazards associated with semiconductor manufacturing revolve primarily around equipment design and material handling. Equipment designers are often faced with control functionality versus process constraint issues and will occasionally locate displays and equipment controls in areas where awkward postures, repetitive motions, or uncomfortable reaches are necessary. Additional issues include the movement of heavy objects—such as wafer carriers, large equipment or process chamber access ports, and final packaged products—that could result in injury. Many of these latter issues have taken on increased importance as the substrate wafer size has increased to 300 mm.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

C3H6O NH3 NH4(OH) AsH3 BCl3 BF3 CO2 Cl2 ClF3 B2H6 SiCl2H2 Si2H6 F2 GeH4 C6H19NSi2 HCl HF H2 HBr HCl HF C3H8O CH4 CH4O HNO3 NO NF3 N 2O O3 POCl3

Acetone Ammonia Ammonium hydroxide Arsine

Boron trichloride

Boron trifluoride Carbon dioxide Chlorine Chlorine trifluoride Diborane Dichlorosilane

Disilane Fluorine Germane Hexamethyl disilazane (HMDS) Hydrochloric acid Hydrofluoric acid Hydrogen Hydrogen bromide Hydrogen chloride Hydrogen fluoride Isopropyl alcohol

Methane Methanol

Nitric acid Nitric oxide Nitrogen trifluoride Nitrous oxide Ozone Phosphorus oxychloride (POCL)

Common chemical name

Chemical formula

Liquid Gas Gas Gas Gas Fuming liquid

Gas Liquid

Gas Gas Gas Liquid Fuming liquid Liquid Gas Gas Gas Gas Liquid

2 25 10 50 0.1 0.1

Asphyxiant 200

5 0.1 0.2 Not established See hydrogen chloride See hydrogen fluoride Asphyxiant 3 5 3 250

1 Asphyxiant 0.5 0.1 0.1 5

Flammable, global warmer Flammable, toxic, ozone precursor Corrosive Highly toxic, oxidizer Oxidizer Oxidizer, global warmer Highly toxic, oxidizer Highly toxic

Pyrophoric Highly toxic, oxidizer, corrosive Highly toxic, flammable Flammable Corrosive Toxic, corrosive Flammable Toxic, corrosive Corrosive Toxic, corrosive Flammable, ozone precursor

Toxic, corrosive Global warmer Toxic, oxidizer, corrosive Toxic, oxidizer, corrosive Highly toxic, flammable Toxic, flammable, corrosive

Corrosive

Flammable Flammable, corrosive Corrosive, flammable Highly toxic, flammable

Characteristic hazard(s)

(Continued )

By-product from NF3 based clean Should never be used as cleaner at above 10 percent

Low pressure may necessitate storage in subfab

Being developed for “dry cleaning”

Low pressure may necessitate storage in subfab

Available in subatmospheric gas cylinder option

Notes of interest

21:14

Gas Gas Gas Gas Gas Gas

Not available

750 25 See ammonia 0.05

TLV* (ppm unless otherwise noted)

04/04/2005

Fuming liquid

Liquid Gas Liquid Gas

State at standard temperature and pressure

TABLE 36.1 Physical and Health Hazards of Semiconductor Process Chemicals

Geng(SMH)_CH36.qxd Page 36.3

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

36.3

36.4 CHF3 C2F6 C3F8 C4F8 PH3 H3PO4 SiH4 SF6 H2SO4 C8H20O4Si C3H9Sb C3H9As C3H9Ga C3H9In WF6

R 23 (Freon 23) R 116 (Freon 116) R 218 (Freon 218) R C-318 (Freon C-318) Phosphine

Phosphoric acid Silane Sulfur hexafluoride Sulfuric acid Tetraethyl orthosilicate (TEOS) Trimethyl antimony (TMA) Trimethyl arsenic (TMAs) Trimethyl gallium (TMGa) Trimethyl indium (TMI) Tungsten hexafluoride Liquid Gas Gas Liquid Liquid Liquid Liquid Liquid Liquid Gas

Gas Gas Gas Gas Gas

Gas

1 mg/m3 5 Asphyxiant 1 mg/m3 10 0.05 0.2 Not set. 0.1 Not established

Asphyxiant 0.3

Irritant

Asphyxiant

TLV* (ppm unless otherwise noted)

Corrosive Toxic, pyrophoric Nonhazarous Corrosive, water reactive Flammable Highly toxic, pyrophoric Highly toxic, pyrophoric Highly toxic, pyrophoric Highly toxic, pyrophoric Toxic, corrosive

Highly toxic, flammable, pyrophoric

Nonflammable, global warming Nonflammable, global warming

Characteristic hazard(s)

Low pressure may necessitate storage in subfab

Available in subatmospheric gas cylinder option

Acknowledged by-product from R23 and R218

Notes of interest

21:15

* Threshold limit values reflect the level of exposure that the typical worker can experience without an unreasonable risk of disease or injury. TLVs are published by the American Conference of Governmental Industrial Hygienists (ACGIH).

CF4

R 14 (tetrafluoromethane)

State at standard temperature and pressure

04/04/2005

Common chemical name

Chemical formula

TABLE 36.1 Physical and Health Hazards of Semiconductor Process Chemicals (Continued)

Geng(SMH)_CH36.qxd Page 36.4

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.5

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

36.5

36.2.4 Mechanical and Potential Energy Hazards Mechanical hazards found in a semiconductor facility involve clearances associated with equipment design, factory layout, and supporting infrastructure limits. Cleanroom space is extremely valuable, therefore spacing of equipment is necessarily minimized. Such spacing presents challenges during maintenance, as access points tend to be small. Additional mechanical hazards such as pinch points are posed internal to the equipment. Cleanliness standards are forwarding the use of robotics for wafer handling, which themselves pose significant risks. Normally unoccupied spaces, such as plenum areas above the cleanroom and mechanical support areas below the raised floors, are designed such that runs of utility piping, wiring, and controls are as short as possible. This design concept results in the creation of spaces where head clearance, egress, and maintenance accessibility are potential issues. These situations can increase the hazards faced by personnel responding to chemical spills or other fabrication facility related emergencies. Outside of maintenance activities, potential energy hazards are relatively few in semiconductor manufacturing. However for facilities with occupied subfabs, constant consideration must be given to leaking pipes, leaking chemical baths, and dropped objects. In addition, personnel have been known to fall through floor grates that have been removed during equipment installation or maintenance. 36.2.5 Electrical Hazards There are two distinct categories of electrical hazards. The first category of hazards relates to the incoming, high power electrical distribution system that involves hazards associated with high voltages and currents, in three phases. The second category of hazards relates to equipment (or, in NFPA 70, National Electrical Code, parlance, appliances) electrical power distribution, which involves hazards from the maze of wires distributing power throughout the equipment. 36.2.6 Ionizing and Nonionizing Radiation Ionizing radiation is characterized as extremely short wavelength, highly energetic electromagnetic energy (greater than 10 eV). Types of ionizing radiation include x-rays, gamma rays, and alpha and beta particles. Nonionizing radiation is defined as radio frequency (RF) and microwave radiation in the frequency range from 30 kHz to 300 GHz and includes RF radiation, lasers (discussed in the next section), ultraviolet radiation, infrared radiation, and visible light. Nonionizing radiation is electromagnetic radiation that lacks the energy needed to energize particles. Typical equipment producing nonionizing radiation include process equipment where plasma is created via RF energy, transmission systems (high-power antennas), base stations, induction welders, some types of high-powered heaters, and certain test and calibration equipment. 36.2.7 Lasers Hazards Lasers produce an intense, highly directional beam of light. If directed, reflected, or focused upon an object, laser light will be partially absorbed, raising the temperature of the surface and/or interior of the object, potentially causing an alteration or deformation of the material. Highpowered lasers can produce acute effects on personnel and can be especially hazardous to the eyes. ANSI Z136.1, American National Standard for Safe Use of Lasers, and most international laser standards classify lasers by the ability of the beam to cause biological damage to the eyes or skin.

36.3 EHS REGULATIONS APPLICABLE TO SEMICONDUCTOR MANUFACTURERS Semiconductor manufacturing incorporates a multitude of processes using an array of hazardous chemicals and other hazards. Historically, the primary responsibility of EHS professionals has been to implement programs that ensure the protection of employees, the company’s capital assets, the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.6

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.6

FAB YIELD, OPERATIONS, AND FACILITIES

public, and the environment. More recently, EHS professionals have also been tasked with ensuring the security of hazardous chemicals and processes. The future holds requirements for restricting and eliminating various substances from process use and/or incorporation into the final product. Table 36.2 lists a number of organizations that are available to assist EHS professionals with this ever expanding list of responsibilities. 36.3.1 Employee Protection Programs In the United States, safety regulations promulgated by the Occupational Health and Safety Administration (OSHA) are compiled in the Code of Federal Regulations (CFR) 29. Several of these requirements that apply to semiconductor operations are discussed here. Many of these requirements have recently been published for international reference in SEMI S21, Safety Guideline for Worker Protection. Protection from Process Hazards. For each of the hazards described in Sec. 36.2, there are related safety protection programs. Process chemicals hazards. Chemicals are usually stored in chemical dispensing rooms characterized by chemical compatibility and physical state. Thus, there are commonly separate storage areas for corrosives and oxidizers, flammables and combustibles for liquids, and for toxics and flammables, corrosives and oxidizers, and pyrophorics for gases. SEMI S4, Safety Guideline for the Separation of Chemical Cylinders Contained in Dispensing Cabinets, provides chemical compatibility listings for common semiconductor process gases. Once proper separation is achieved for chemical storage, the next consideration is safe delivery. Again, physical and reactivity characteristics will determine the selection of piping materials. The same considerations will apply to the selection of exhaust duct and waste liquid drain and collection tank materials of construction. Information on materials compatibility can be obtained from material safety data sheets (MSDS) and from product specifications provided by chemical and waste handling systems components suppliers. Chemical Storage Notifications. The Hazardous Materials Ordinance (HMO) that originated in the 1980s in San Jose, California, is now codified in International Fire Code (IFC) Chap. 1. This ordinance requires detailed tracking and reporting to the local fire department of chemical storage quantities and locations at semiconductor and other facilities. Chemical Releases Response. Response to accidental releases, such as spills of hazardous materials requires special training and organization. Detailed training requirements for hazardous materials technicians are provided by OSHA in CFR 1910.120. Responses should be managed using the Incident Command System (ICS). Online ICS training is available as a course, IS 195 Basic Incident Command System, from the U.S. Federal Emergency Management Agency (FEMA). Guidance on developing a hazardous materials response team to function in a semiconductor manufacturing environment is available on CD-ROM from SESHA’s Semiconductor Emergency Response Forum (SERF). When releases do occur, it is important to determine if a quantity reportable to an authority having jurisdiction has been discharged to the land, water, or air. Typically, regulations include a maximum time period, often 24 hr between the discovery of the release and its reporting. Ergonomic hazards. Comprehensive guidance on evaluation and mitigation of ergonomic hazards is found in SEMI S8, Safety Guideline for Ergonomics Engineering of Semiconductor Manufacturing Equipment. Lifting hazards are magnified as equipment is scaled up to meet the requirements of larger wafer dimensions. For this reason, newer generation factories have incorporated unmanned transport vehicles (UTVs), such as automated guided vehicle (AGV), rail guided vehicle (RGV), and overhead hoist transport (OHT) systems, which themselves pose mechanical hazards. Mechanical and potential energy hazards. Mechanical hazards are often protected against using machine guards. Some details on the need for and uses of machine guards are provided in 29 CFR 1917.151. Safety considerations related to mechanical hazards from UTV are detailed in SEMI S17, Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.7

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

36.7

TABLE 36.2 Semiconductor EHS Support Organizations Organization

Membership

Activities

Internet URL

Air and Waste Management Association (A and WMA)

Environmental technical and legal professionals

Provides education and professional networking opportunities

www.awma.org

Electronic Industries Association (EIA)

National trade organization representing the electronics industry

Provides technical, political, and policy information relating to the electronics industry

www.eia.org

European Semiconductor Industry Association (ESIA)

European member companies in semiconductor manufacturing

Reports on EHS metrics and represents the semiconductor industry to EHS regulatory agencies and governments

www.eeca.org

International SEMATECH Manufacturing Inititative (ISMI) EHS Programs

International Sematech and ISMI member company representatives

Performs selected EHS projects and hosts list server ([email protected])

www.sematech.org

Japan Electronics and Information Technology Industries Association (JEITA)

Japanese member companies in electronics and information technology (IT) fields

Reports on EHS metrics and represents the semiconductor industry to EHS regulatory agencies and governments

www.jeita.or.jp

Joint Electron Device Engineering Council

Members of the Electronic Industries Alliance (EIA)

Publishes semiconductor engineering standards for the EIA

www.jedec.org

Korea Semiconductor Industry Association (KSIA)

Korean member companies in semiconductor manufacturing

Reports on EHS metrics and represents the semiconductor industry to EHS regulatory agencies and governments

www.ksia.or.kr

SEMI EHS Committee

Equipment suppliers, semiconductor manufacturers, and “third party” equipment reviewers

Develops EHS standards and guidelines for semiconductor equipment and hosts EHS Grapevine list server ([email protected])

www.semi.com

Semiconductor Environmental, Safety and Health Association (SESHA) Compound Semiconductor Forum

EHS personnel, process and equipment engineers, manufacturing and support equipment suppliers, chemical suppliers, and researchers

Provides professional networking and education on compound semiconductor (CS) EHS issues and hosts list server ([email protected])

www.seshaonline.org

Semiconductor Industry Association (SIA) EHS Committee

U.S. member companies in semiconductor manufacturing

Reports on EHS metrics and represents the semiconductor industry to EHS regulatory agencies and governments

www.semichips.org

Society of Fire Protection Engineers (SFPE)

Fire protection professionals, researchers, academicians

Provides technical information on fire protection subjects, education and a networking forum.

www.sfpe.org

Taiwan Semiconductor Industry Association (TSIA)

Taiwanese member companies in semiconductor manufacturing

Reports on EHS metrics and represents the semiconductor industry to EHS regulatory agencies and governments

www.tsia.org.tw

World Semiconductor Council (WSC)

International members of ESIA, JEITA, KSIA, SIA, and TSIA

Reports on EHS metrics and represents the semiconductor industry to EHS regulatory agencies and governments

www.semiconductorcouncil.org/

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.8

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.8

FAB YIELD, OPERATIONS, AND FACILITIES

Safety Guideline for Unmanned Transport Vehicle (UTV) Systems. Industrial robots should meet the safety design requirements of such international standards as ANSI/RIA R15.06 and ISO 10218, as detailed in SEMI S2, Environmental, Safety, and Health Guideline for Semiconductor Manufacturing Equipment. Potential energy hazards are generally controlled using a hazardous energy control (HEC) or lockout-tagout (LOTO) program. OSHA’s Directorate of Technical Support (DTS) has posted a comprehensive “Lockout-Tagout Interactive Training Program” on their website. Protection from leaks and falling objects and prevention of falling people, is generally accomplished through the use of physical barriers. (Certainly, fall protection systems, such as those discussed at http://www.osha.gov/SLTC/ fallprotection/, are also useful to protect personnel from this common workplace hazard.) Electrical hazards. High-power distribution system design is guided by National Fire Protection Association (NFPA) 70, National Electrical Code. The best practices for the internal wiring of semiconductor manufacturing equipment are detailed in SEMI S22, Safety Guideline for Electrical Design of Semiconductor Manufacturing Equipment. This document also prescribes design and operation requirements for fail-to-safe equipment control systems (FECS), which are programmable circuits controlling safety functions. HEC/LOTO during maintenance is a paramount concern for both types of electrical power distribution. It is important that proper energy control procedures are developed, especially for maintenance personnel, to minimize the chances of an electrical accident. A key component of an energy control program is the ability to isolate these hazardous energies. To facilitate this, fit-up of equipment should include review and strategic configuration of energy isolation points, such that this can be accomplished conveniently (i.e., not in a location requiring removal of cleanroom gowns, such as in the subfab) and with minimum disruption to process operations. It is not uncommon for maintenance or service activities to be performed on subassemblies, while other components of the manufacturing tool continue to operate. It is imperative that the hazardous energies of the subassembly and any other hazards that might cause harm to the maintenance personnel be properly isolated through a lockout. Reliability demands sometimes drive the need for power redundancy, with some factories having secondary power loops that provide backup in the event a primary power line is disrupted. Manufacturing tools, especially those susceptible to power sags, may contain localized backup power via uninterrupted power supply (UPS) systems. Consideration must be given to these secondary energy sources during maintenance to ensure the equipment is indeed de-energized. Ionizing and nonionizing radiation. Equipment generating ionizing radiation (such as ion implanters, scanning electron microscopes, and x-ray machines) are designed with protective enclosures to prevent exposure of personnel. Careful maintenance of these enclosures and interlocks is required to ensure long-term personnel safety. Typical protective measures for employees include a radiation badging system, which collects information on cumulative exposure to ionizing radiation. In some jurisdictions, the registration of equipment producing such radiation, as well as specific training for personnel operating the equipment and those managing the safety aspects of the program (i.e., radiation safety officers) is required. As for nonionizing radiation, high levels of RF produce acute affects, therefore monitoring of equipment enclosures and shielding is important, as is testing of interlocks. Exposure limits for ionizing and nonionizing radiation are established and can be referenced in the TLV handbook published by the American Conference of Governmental Industrial Hygienists (ACGIH). Lasers hazards. Controls can include engineering controls (protective housings with interlocks, protective filter installations, key-controls and system interlocks) or administrative/procedural controls (standard operating procedures and personal protective equipment). Extensive recommendations for the safe use of lasers have been developed by the American National Standards Institute (ANSI Z 136.1) and adopted by the ACGIH. More information is published in Section III, Chapter 6, of the OSHA Technical Manual. SEMI S2 contains, as related information, a laser checklist that should be provided by equipment suppliers so that an appropriate laser safety program can be developed. Employee Protection. Beyond the generally prescriptive regulations related to the specific hazards discussed above, there are also performance programs establishing a general duty to ensure employee safety and continuous improvement. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.9

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

36.9

Employee hazard communication. Hazard communication training should be provided to all employees prior to beginning their employment. For all employees, this training must address general workplace chemical hazards and include how to read an MSDS, use of personal protective equipment (PPE), and proper container labeling. Employees who might be exposed to specific chemicals and other hazards from semiconductor manufacturing should be given special training by their supervisors. The SEMI 19, Safety Guideline for Training of Semiconductor Manufacturing Equipment Installation, Service and Maintenance Personnel, lists the types of concerns that should be addressed for new employees in a semiconductor manufacturing facility. OSHA’s Inorganic Arsenic Standard establishes regulated areas where arsenic particles may be generated. Entry to the regulated area is limited to “authorized persons.” A written exposure control and reduction plan that includes air monitoring, industrial hygiene sampling, medical surveillance, appropriate signage and filtering of exhaust, must be prepared and implemented. Human element controls. Semiconductor manufacturing, by its very nature creates a wide variety of potential EHS hazards, many of which are not specifically addressed in codes, regulations, or standards. Therefore, the key components to a robust EHS program in this industry include reviews of activities, identification of hazards, and development of programs that provide guidelines to control these hazards. EHS personnel should be included early in the equipment and/or process design. When these processes and the associated equipment are installed, EHS review and approval should be a part of the startup authorization procedure. This will help assure that EHS features associated with the process/equipment have been correctly installed and are operational. For installation, maintenance, and retrofit work, where potential hazards can be encountered (such as electrical energy or chemical exposure) or hazards can be created (such as cutting and welding), an activity request system can be useful for the control of these hazards. A typical activity request system will require pre-planning, review, and EHS authorization of the work in advance. Job safety analysis. In semiconductor operations, a job safety analysis (JSA) should be performed for maintenance and decontamination on semiconductor processing equipment, including associated chemical delivery, waste handling, and life safety systems. Unique hazards that these procedures should attend to are prevention of fires from phosphorus collected in cold traps, control of arsenic and phosphorus particles, and ventilation of gases evolved from pooled liquids and solid deposits. Regulators notification. In the United States, OSHA mandates the recording and reporting of work-related injuries and illnesses that result in any of the following: death, days away from work, restricted work or transfer to another job, medical treatment beyond first aid, or loss of consciousness. This is in addition to the new health effects reporting required by the Environmental Protection Agency (EPA) described in Sec. 36.3.4. To protect employees and public health, many jurisdictions have instituted licensing and inspection programs for specific hazards. Common semiconductor manufacturing equipment related hazards for which such programs apply, are radioactive materials and sources of lasers and x-ray radiation.

36.3.2 Process Safety Programs The relatively small quantities of hazardous materials utilized in semiconductor manufacturing usually exempts these operations from specific programs associated with controlling catastrophic hazards. The OSHA Process Safety Management (PSM) rule is such a regulation that creates a structured and specific approach to managing catastrophic risk. Although not specifically applicable to semiconductor operations at this time, the rule does provide a framework for many safety programs that should be considered by all manufacturers as part of their overall risk management approach. The elements of this program include an employee participation plan, the documentation of process safety information, process hazard analyses, written operating procedures, employee training, contractor management, a pre-startup safety review, a mechanical integrity plan, hot work permits, management of change procedures, incident investigation, an emergency response plan, and compliance audits. Ammonia, arsine, chlorine, diborane, hydrochloric acid, nitric acid, nitrogen trifluoride, ozone, and phosphine are PSM listed chemicals. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.10

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.10

FAB YIELD, OPERATIONS, AND FACILITIES

Process Risk Assessments. As described in such international standards and guidelines as EN 1050, Safety of Machinery—Principles for Risk Assessment, and SEMI S10, Safety Guideline for Risk Assessment, risk management incorporates formal risk assessment, which is composed of selecting system limits, identification of hazards and risk estimation, followed by risk evaluation and, when necessary, risk reduction. Risk management is often mandated by regulatory programs, for the protection of human health and the environment and by customers and the corporation to ensure compliance with quality and environmental management expectations. In many cases however, regulations or prescribed standards do not directly address design requirements or operational controls that are intended to mitigate risks within a semiconductor facility, and the burden is placed on the system owner to evaluate and judge whether or not additional risk reduction activities are warranted. Fortunately, a variety of risk assessment tools are available to assist in these endeavors. Generally, risk assessment methods can be categorized into four groups—hazard identification methods, frequency identification methods, consequence assessment methods, and risk evaluations methods as shown in Fig. 36.1. Some hybrids that are combinations of two or more methods from differing groups have also evolved. The selection of an appropriate methodology involves an evaluation of several parameters of the system of interest. These will include the complexity of the system, desired outcome of the evaluation,

Risk assessment methods

Frequency assessment methods

Hazard identification methods

Consequence assessment methods

Risk evaluation methods

δI Literature search

δI Historical records

δI Source term models

δI Risk matrix

δI What-if review

δI Fault tree analysis

δI Atmospheric dispersion models

δI Risk profile

δI Safety audit

δI Event tree analysis

δI Walk-through

δI FMEA

δI Checklist

δI Human reliability analysis

δI Brainstorming δI Barrier analysis δI HAZOP

FIGURE 36.1

δI Blast and thermal δI Aquatic transport models

δI Risk isopleth δI Risk density curve δI Risk index

δI Effect models δI Common cause failure analysis

δI Mitigation models

δI External events analysis

Risk assessment methods.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.11

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

36.11

and available resources to perform the analysis. A complex system that has an array of failure mechanisms may lead to use of the hazard operability (HazOp) or failure modes effects analysis (FMEA) methodology, where simpler systems may be effectively reviewed via the what-if checklist or brainstorming methods. For situations where a failure mechanism of interest is known or can be predicted, consequence assessment methods may be appropriate. Consequence assessment methods, such as air dispersion and explosion over-pressure modeling, may also be suitable for assessing the off-site impacts of larger events, especially if these events are of concern to the neighboring community. A large part of an effective risk management program is the risk evaluation phase. The strength of many of these assessment methods is the determination of the failure mode and/or its consequence, which are the components that make up overall risk. To complete the risk assessment, some decision criteria must be established to help management determine when corrective actions should be applied. A useful tool for this is a severity and likelihood (and occasionally occurrence, which takes into account existing detection and response systems) risk matrix, allowing the analyst to qualitatively estimate risk. Such a matrix allows prioritizing among multiple risk scenarios and establishment of an acceptable risk threshold value, such that effective application of risk reduction resources can be accomplished. A hybrid risk assessment technique that incorporates a risk matrix specific to continuous, direct delivery semiconductor fabrication facility utilities, and environmental treatment systems is described in “Integrated Hazards Analysis: Using the Strengths of Multiple Methods to Maximize Effectiveness,” which was published in Professional Safety Magazine in May 2004. A hazard analysis method specific to semiconductor manufacturing equipment has been published by International Sematech as Document 99113846A-ENG, Hazard Analysis Guide: A Reference Manual for Analyzing Hazards on Semiconductor Manufacturing Equipment. 36.3.3 Capital Assets Protection Programs Capital assets, including buildings and manufacturing equipment, must be protected from the hazards of semiconductor manufacturing. Building Protection. The IFC, NFPA 318, and many other model codes and standards, including Factory Mutual FM 7-7, Property Loss Prevention Data Sheet for Semiconductor Fabrication Facilities, have specific requirements for the construction, fire suppression, gas detection and alarming, chemical storage, and use of semiconductor facilities. These requirements even extend to the materials of construction and fire suppression for equipment, piping, and ducts used in semiconductor manufacturing. For example, Chapter 18 of the IFC (Semiconductor Fabrication Facilities) requires the special construction requirements for Group H-5 Occupancies, as defined in the International Building Code. Chapter 18 also calls for unobstructed building sprinkler flow patterns and sprinklers within the branchline or plenum of combustible workstations using hazardous production materials (HPM). Catastrophic releases of toxic gases must be treated to a concentration of less than one-half of the immediately dangerous to life and health (IDLH). Concentration and quantities of pyrophoric solids and liquids, such as metal organics used in vapor phase epitaxial deposition, are strictly limited within the factory. Gas monitoring and alarm systems within semiconductor fabrication facilities are required by model fire codes. However, the best practice for systems design is constantly changing. Design considerations, such as whether to monitor for the process gases or their by-products, what concentrations should be used for warning and alarm, and where to locate sensors, continue to be debated. An excellent resource for gas-detection system design considerations, hosted by Scott Instruments, is found at www.semigasdetection.com. This website includes a version of the article “Toxics and Combustibles: Designing Gas-Detection Systems,” which originally appeared in the July 1, 1998, edition of Chemical Engineering magazine. Because of the toxic nature of many air emissions from semiconductor facilities, protection of facility personnel from air intake entrainment should be provided as recommended by the Fundamentals Standard of the American Society of Heating, Refrigeration, and Air Conditioning Engineers (ASHRAE).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.12

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.12

FAB YIELD, OPERATIONS, AND FACILITIES

Manufacturing Equipment Protection. Equipment purchase agreements (EPA) are usually the vehicle used to notify semiconductor manufacturing equipment suppliers of relevant safety and environmental regulations and standards. Compliance with Semiconductor Equipment and Materials International (SEMI) safety guidelines, particularly SEMI S2, Environmental, Health, and Safety Guideline for Semiconductor Manufacturing Equipment, and SEMI S8, Safety Guideline for Ergonomics Engineering of Semiconductor Manufacturing Equipment, is now a common requirement. In addition, many semiconductor manufacturers are requiring that equipment undergo Design for Environment (DFE) and Life Cycle Assessments (LCA). International SEMATECH (ISMT) has published a document, 01064135B-ENG, Uniform Environment, Safety, and Health (EHS) Specification for Equipment Procurement (v.1.3), that provides a uniform environmental, safety, and health EPA language for use by the industry. Of great concern to the entire semiconductor industry is that OSHA might require Nationally Recognized Testing Laboratory (NRTL) listing of semiconductor manufacturing equipment. Such a requirement is becoming more viable as segments of the industry move toward standardized tool sets, for which the equipment could be viewed as mass produced instead of one-of-a-kind. In Europe, the CE mark and machine directives are required of all manufacturing equipment. Complying with these requirements can be difficult when shipping or transferring manufacturing equipment from the United States to Europe. Similar marks are required in China and Korea. Typically EHS personnel are assigned the responsibility to ensure that prior to being used for production, the manufacturing equipment is installed in accordance with applicable regulations and with site or corporate standards. This task is usually accomplished using an equipment “sign-off” procedure incorporating checklists related to the completion of tasks by the various installation crafts (i.e., electrical, piping, ventilation, and gas detection), availability of maintenance manuals and required safety documentation (e.g., SEMI S2 and S8 third-party reports), testing of equipment safety interlocks and related life safety systems, demonstration of appropriate chemical and waste handling systems and procedures, and proof of necessary registrations and permits. While particular to equipment installation considerations in Austin, Texas, ISMT Document #:98103579A-XFR, Equipment Installation Sign-off Procedure, serves as an example of the types of procedures to be followed and records to be kept by EHS personnel when authorizing equipment for production. 36.3.4 Environmental Protection Programs The basic principles of corporate environmental stewardship are universal. While pollution prevention is the ultimate objective, semiconductor manufacturing still qualifies as a hazardous process chemical intensive industry that produces significant quantities of hazardous waste. As such, the industry expends tremendous resources on the reduction of pollution to the land, water, and air, by a combination of using less hazardous substances and control of discharges, in order to protect human health and the environment from deleterious affects. In the United States, many prescriptive federal environmental acts have been promulgated to ensure this protection. The resulting regulations are enforced by the U.S. EPA or by state environmental agencies through delegation. For the purpose of giving examples of command and control type environmental regulations, several of these U.S. rules and their application to semiconductor operations are detailed below. Water Quality Protection. The Clean Water Act (CWA) establishes requirements for the quality of waste water and storm water discharges. In the U.S. most semiconductor manufacturing facilities discharge to a Publicly Owned Treatment Works (POTW), which establishes permit limitations for discharges from those facilities, as opposed to discharging directly to a waterway. In this circumstance, semiconductor facilities generally need only raise the pH of industrial waste water discharges to comply with POTW requirements. Another commonly regulated contaminant is fluoride. Meeting fluoride discharge limits has become a challenge with the advent of nitrogen trifluoride based chamber cleaning technology, as the process by-products are absorbed into the recirculated water of exhaust scrubbers. In addition, silicon oxide operations using copper for circuitry interconnection and compound semiconductor operations manufacturing gallium arsenide products must also meet copper and arsenic discharge standards, respectively. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.13

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

36.13

CMP and back end of line (BEOL) processes generally contribute substrate particles, which for silicon oxide semiconductors are not typically regulated through the CWA. The CWA also mandates the control of storm water discharges from many industrial facilities. Permits that include requirements for best management practices (BMP) and stormwater pollution prevention plans (SWPPP) are required. All semiconductor facilities must comply with the requirements applicable to the electronics industry, which includes quarterly storm water sampling and specific limits for listed metals. Air Quality Protection. The Clean Air Act (CAA) establishes limits for discharges of particles— such as vapors and gases, including combustion by-products—into the air. New source review (NSR) permits are required prior to construction of industrial facilities with air emissions. More restrictive permits, known as federal operating (Title V) permits, are required of facilities with emissions above the major source thresholds for hazardous air pollutants and criteria pollutants. Arsine and phosphine are both hazardous air pollutants and semiconductor facilities can emit large quantities of the criteria pollutants nitrogen oxides (NOx) and carbon monoxide (CO), which are combustion by-products. Recently, the Semiconductor Industry Association (SIA) and EPA negotiated on maximum achievable control technology (MACT) for the semiconductor industry’s major sources of hazardous air pollutants. The final rule, which mandates the oxidation of volatile organic compounds and water scrubbing of soluble acid vapors, was published in the Federal Register on May 22, 2003. For information on best practice technologies for abatement of the full array of emissions common to semiconductor manufacturing, see SEMI F5, Guide for Gaseous Effluent Handling. Many communities in the United States do not, or soon will not, attain CAA National Ambient Air Quality Standards (NAAQS) for ground level ozone. Semiconductor operations within such communities can expect lower thresholds for restrictive Title V permits and the implementation of ozone precursors’ (i.e., volatile organic compounds (VOC) and NOx) emissions reductions programs, such as low NOx burner installation and mandatory employee trip reductions. The CAA also establishes the Risk Management Program (RMP) that is designed to protect the public and environment from catastrophic releases of toxic chemicals. This program requires a hazard assessment, prevention program, emergency response plan, risk management plan, and extensive record keeping. Ammonia, arsine, chlorine, diborane, hydrogen, hydrogen chloride, hydrogen fluoride, methane, nitric acid, phosphine, and silanes are listed in the RMP rule. The applicability thresholds for arsine and phosphine are only 100 lb. In addition, the General Duty Clause (GDC) requires a similar assessment for all hazardous materials at any quantity. Also applicable to semiconductor operations are subparts BB and CC of the Resource Conservation and Recovery Act (RCRA), which require programs for preventing solvent emissions to air from waste solvent collection and storage systems, partly by requiring conservation vents on tanks and leak inspections for piping system components. Solid Waste Handling. RCRA establishes the “cradle to grave” hazardous waste disposal procedures that incorporate a waste manifest system. Semiconductor manufacturing produces a variety of mostly liquid hazardous wastes that require special handling. Generally, wastes are collected in separate, chemically compatible acid and solvent streams, either as mixtures or in segregated systems. Many alternatives to the disposal of these wastes as hazardous waste have been implemented. Segregated waste sulfuric acid has been reprocessed, through distillation, for reuse in the factory and has also been sold as a product. Segregated hydrofluoric acid and mixtures including a high percentage of hydrofluoric acid have been treated using lime to produce a nonhazardous filter cake. As for solvents, waste isopropyl alcohol can be reprocessed for reuse on site, while mixed solvent wastes with sufficient energy value can be sold as a fuel. Gallium is a limited resource that is produced as a by-product of aluminum and zinc processing. Presently, demand exceeds new production necessitating resource recovery. Recyclers in Germany, Japan, the United Kingdom, Canada, and the United States are capable of reclaiming gallium from waste semiconductor wafers and chips, as well as from other waste streams including the sludge produced from arsenic treatment of waste water. Gold and other precious metals can also be recovered prior to recycling. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.14

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.14

FAB YIELD, OPERATIONS, AND FACILITIES

General Environmental Protection. The Toxic Substances Control Act (TSCA) establishes requirements for “new chemical” production and import/export controls. TSCA has many provisions, including a requirement to report newly identified health effects from chemical exposures in the workplace. Under this rule, EPA has recently published a significant new use rule (SNUR) that includes an exemption for the photolithography use of perfluoroalkyl sulfonates (PFOS) by the semiconductor industry. The Emergency Planning and Community Right to Know Act (EPCRA) requires reporting of chemical storage and releases. Annual chemical storage of listed chemicals is required using “Tier II” forms submitted to the Local Emergency Planning Committee (LEPC) and the local fire department. In addition, MSDSs for certain chemicals must be provided to nearby hospitals. Annual discharges must be reported for a short list of chemicals using the toxic release inventory (TRI) forms. TRI reporting for persistent bioaccumulative toxics (PBT), ozone (which is not well destroyed in exhaust handling and treatment systems), nitrates discharged into waste water, and lead from final manufacturing activities should not be overlooked by semiconductor manufacturers. Many nations around the world have TRI-like requirements under pollutant release and transfer register (PRTR) programs that require reports to governments on releases of substances to the environment and on offsite transfers of substances for final disposal. The United Nations Environment Program maintains information about PRTRs at http://www.chem.unep.ch/prtr/default.htm. Also under EPCRA, federal and local emergency notification procedures are established for accidental releases into the environment. In addition, semiconductor facilities with chemicals approaching or above RMP thresholds are obligated to participate in the annual emergency planning activities of their LEPC. Compared to the newer generation silicon oxide semiconductor factories, most compound semiconductor operations are relatively small, allowing their location proximate to neighborhoods. Environmental justice issues, which can be reported to and acted upon by EPA as part of their 1995 Environmental Justice Strategy, are likely to surface, as communities become aware of the chemical transportation and accidental release hazards these facilities pose. 36.3.5 Security Programs Since the terrorist attacks on the World Trade Center on September 11, 2001, much attention has been placed on the security of chemicals in transportation and use. In the United States, this has resulted in new regulations and pending legislation. Chemical Security. The proposed Chemical Security Act (CSA) would require EPA to work with the Department of Homeland Security (DHS) to identify high-priority chemical plants based on the volume and toxicity of chemicals that the plants produce or store and their proximity to population centers. EPA and DHS would then develop regulations to require these plants to conduct vulnerability assessments and to implement response plans that include security improvements and safer technologies. EPA and DHS would then review the assessments and plans to ensure that they meet the new federal standards. The American Institute of Chemical Engineers’ (AIChE) Center for Chemical Process Safety (CCPS) has published guidance for chemical facilities entitled Guidelines for Analyzing and Managing the Security Vulnerabilities at Fixed Chemical Sites. Transportation Security. The Federal Motor Carrier Safety Administration (FMCSA) has promulgated requirements for transporters and shippers of hazardous materials to develop security plans and to provide personnel training on how to recognize and react to potential security threats. Guidance on developing transportation security plans is available from FMCSA and the U.S. Department of Transportation’s Research and Special Programs Adminstration (RSPA) at http://hazmat.dot.gov/hmt_security.htm. 36.3.6 Future EHS Regulations In order to remain up to date on regulations, EHS professionals should have some system for the notification of proposals and final versions of new or modified regulations and legislation. Two subscription services that provide worldwide coverage related to the electronics and semiconductor

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.15

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

36.15

industries are EIATRACK, available through the Electronics Industry Alliance (EIA) and SEMITRACK, available through SEMI. At the time this chapter was written, there were many proposed and pending EHS regulations in the United States, as well as in Europe and Asia, that could significantly impact semiconductor operations. Hazardous Substances Restriction and Elimination. In the United States, the EPA is moving to decrease arsenic discharge limits for industrial waste water and prohibit most uses of perfluoro alkylsulfunates (PFAS) and its telomers. Many companies in the silicon oxide segment of the industry have signed a Memorandum of Understanding with the EPA for the reduction of fluorinated compounds (often called perfluorocompounds, including CF4, C2F6, C3F8, C4F8, CHF3, NF3, and SF6) emissions, which are implicated in global warming. There is potential that these reductions will become mandated for all of the industry through air permits. EPA’s Climate Leaders program and various private-sector “cap and trade” initiatives, such as the Chicago Climate Exchange, are being implemented for the reduction of all greenhouse gases, including combustion by-products (e.g., carbon dioxide, methane, and nitrous oxide) from fuel oil and natural gas consumed by boilers, fire pumps and oxidizers, process nitrous oxide and fluorinated compounds emissions. The European Union has recently passed the Restriction of the Use of Certain Hazardous Substances (RoHS) Directive that will introduce a substitution requirement for substances that pose significant environmental risks during disposal and recycling of electrical and electronic equipment waste. The Directive was published in the Official Journal on January 27, 2003, and member states have until August 13, 2004, to comply. The RoHS Directive provides that after July 1, 2006, electrical and electronic equipment cannot contain any lead, cadmium, mercury and hexavalent chromium, and brominated flame retardants (PBB and PBDE). Many of these compounds are used in the leads and packaging of semiconductor products. The European Commission is proposing a new EU regulatory framework for chemicals called the Registration, Evaluation, and Authorization of Chemicals (REACH) Regulation. Under this system enterprises that manufactured or imported more than one ton of a chemical substance per year would be required to register with a centralized database. REACH transfers new responsibilities to industry to manage the risks from chemicals and to provide safety information on them. In October 2003, China promulgated the Regulations on the Environmental Management of New Chemical Substances regulation, requiring importers and exporters of toxic chemicals to register with the State Environmental Protection Administration (SEPA). Similar to the EU’s REACH rule, registration will include a declaration of technical data on the chemical related to its chemical properties, test methods, uses, amounts intended for manufacture or import, toxicological and ecotoxicological characteristics, accident prevention and emergency measures, and pollution prevention, abatement, and waste disposal methods. This rule could affect the ability of semiconductor operations to quickly implement new processes requiring chemicals not previously used in China.

36.4 BEYOND REGULATORY COMPLIANCE Constituencies outside of governmental jurisdictions, insurers, and internal corporate programs, including shareholders, local residents, and purchasers of semiconductors, have taken an increasing interest in the EHS risks posed by semiconductor manufacturing. In the extreme, this interest may result in a demand to modify or relocate manufacturing processes and prohibit the incorporation of hazardous chemicals in the final product. 36.4.1 Shareholder and Lender EHS Expectations Annual global corporate citizenship reports and environmental stewardship reports are becoming a popular method for companies to communicate their commitment to and recent successes at human health and environmental impact reduction, to consumers and stockholders. Many such reports from semiconductor manufacturers are available publicly on the Internet. The preparation of these reports requires the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.16

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.16

FAB YIELD, OPERATIONS, AND FACILITIES

compilation of “metrics” related to such EHS issues as employee injuries and illnesses rates, hazardous and nonhazardous waste generation, incineration, recovery and recycling rates, various air contaminant emission quantities, waste water and contaminant discharge quantities, and energy and water use and conservation rates. (It is important to recognize that the types of metrics that are communicated outside of the industry are often different from those used to compare semiconductor manufacturing equipment performance. The latter are well described in ISMT Document # 02034261A-TR, Environment, Safety, and Health Metrics for Semiconductor Manufacturing Equipment (SME), and the International Technology Roadmap for Semiconductors (ITRS) (available at http://public.itrs.net/.). Potential monetary lenders, as well as insurers and shareholders, expect “due diligence” when purchasing new property to ensure that no significant environmental concerns exist that could result in unexpected employee health problems or remediation costs. Generally this involves an environmental site assessment (ESA), in accordance with ASTM Standard E 1527, Standard Practice for Environmental Site Assessments: Phase 1 Environmental Site Assessment Process. The most thorough investigations also incorporate an indoor environmental quality assessment, as well as surveys for mold, asbestos, and lead. 36.4.2 Community EHS Expectations Recently, semiconductor manufacturers are being asked to develop natural resource conservation programs. Partly because some communities have begun asking large users to reduce peak power demand, typically during times of extreme temperatures, energy conservation is being implemented at the equipment and facility-utility level. Since many semiconductor facilities are located in arid areas, water conservation, which is composed of use reduction, reclaim and recycle, is also being implemented. Processes that have been demonstrated to be high water using and relatively easily treated for reuse or recycle, include wet-hood rinses, sonic baths, dehumidification condensate and exhaust scrubber blowdown in the front end-of-line (FEOL), polishers and scrubbers in CMP, and backgrinders and saws discharges in the BEOL. Resource conservation can result in additional benefits, beyond community good will. Energy conservation activities reduce fuels used by energy utilities, thereby resulting in “indirect” emissions reductions of the global warming combustion by-products (e.g., carbon dioxide, methane, and nitrous oxide) and criteria pollutants. Another benefit of resource conservation is the associated reduction in utilities cost per unit production. 36.4.3 Customer EHS Expectations Customers of semiconductor products worldwide have begun demanding that the semiconductor industry implement and demonstrate best practices for EHS programs, as well as business continuity management. The industry has responded by instituting EHS Management Systems, typically in compliance with or modeled after the International Organization for Standardization (ISO) 14000 series of environmental management standards, and by publishing Business Continuity Guideline for the Semiconductor Industry and its Supply Chain through SEMI. Customers are also becoming more interested in ensuring that semiconductor products do not contain banned substances and are recyclable, because of product take-back requirements in some nations. Accordingly, product content surveys that can be exceedingly difficult to complete, are becoming ever more common. The European Information and Communication Technology Industry Association (EICTA), Electronic Industries Alliance (EIA), and Japan Electronics and Information Technologies Association (JEITA) have developed lists of common reportable materials and standardized solicitation and reporting procedures. JEITA has posted a consensus list that is expected to eventually become a standard published by EIA’s Joint Electron Device Engineering Council (JEDEC). 36.4.4 Professional Certification Authorities There are several certifications and licenses appropriate for EHS professionals, most requiring a competency demonstration and the imposition of an ethical code of conduct. Competency is typically demonstrated by the completion of specific secondary education, serving of a term of practice

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.17

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES

36.17

as an associate or “in-training” professional, passing of a skills demonstration test, and completion of continuing relevant education. As to the code of conduct, most certifying and licensure authorities exist for the expressed purpose of ensuring that EHS professionals place the protection of public safety and the environment ahead of the interests of clients and employers. The American Board of Industrial Hygiene (ABIH, http://www.abih.org/) offers the Certified Industrial Hygienist (CIH) credential, for professionals tasked with identifying and protecting against risks to worker health, especially from chemicals, noise, and electromagnetic radiation. The Board of Certified Safety Professionals (BCSP, http://www.bcsp.org/) offers the Certified Safety Professional (CSP) credential, for professionals “engaged in the prevention of accidents, incidents, and events that harm people, property, or the environment.” The Institute of Hazardous Materials Management (IHMM, http://www.ihmm.org/) offers the Certified Hazardous Materials Manager (CHMM) credential, for “professionals engaged in the management and control of hazardous materials.” The Institute of Professional Environmental Practice (IPEP, http://www.ipep.org/) offers the Qualified Environmental Professional credential, allowing EHS professionals to demonstrate “big picture” understanding of the best practices for multimedia environmental protection. In addition, many EHS enforcement jurisdictions require that submissions for permits and demonstration of compliance be “sealed” by a professional engineer (PE) licensed in an appropriate discipline, such as environmental, safety, civil, or chemical engineering. In the United States, the professional engineering licensure process, including taking disciplinary actions, is overseen by state licensing boards.

36.5 THE FUTURE OF SEMICONDUCTOR EHS Semiconductor manufacturing EHS professionals have traditionally worked in a reactive mode, in that process research and development did not include an assessment of relevant safety and health protection programs or environmental controls systems that might be necessary before transitioning into production. The new, more progressive approach is to integrate EHS programs development into the multiyear process development process, through Design for Environment, Safety, and Health (DFESH). This positioning also allows the consideration, development, and possible application of new EHS control technologies. For semiconductor EHS professionals, keeping abreast of pending EHS challenges is as important as keeping abreast of pending legislation. The ITRS (http://public.itrs.net/) contains an EHS needs section that is useful for this purpose. 36.5.1 Controlling Future EHS Risks Implementing DFESH concepts into semiconductor EHS programs requires participation by EHS professionals in the process research and development process. Important DFESH considerations during process development are ensuring that full EHS control programs are developed for new chemicals (including designing safe chemical storage and delivery systems, selecting chemical resistant personal protective equipment, and identifying environmental emissions control technologies), appropriate operating and maintenance programs are developed, and the final product is not manufactured using and does not contain restricted and prohibited substances. ISMT sponsored a DFESH project and published ISMT Document #95103006A-ENG S70, Design for Environment, Safety, and Health (DFESH) Implementation Strategy for the Semiconductor Industry. 36.5.2 Emerging EHS Control Systems Several new technologies are commercially available allowing safer storage and delivery of toxic hydrides utilized in semiconductor manufacturing. Subatmospheric gas cylinders incorporating adsorbent media maintain cylinder pressures at near or below atmospheric pressure. Vacuum actuated cylinders use pressure regulators inside the cylinder that lower the maximum delivery pressure to below the internal cylinder pressure. Source generation of hydrides from solid sources dramatically lowers the storage quantity at any one time. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH36.qxd

04/04/2005

21:15

Page 36.18

ENVIRONMENTAL, HEALTH, AND SAFETY CONSIDERATIONS IN SEMICONDUCTOR FABRICATION FACILITIES 36.18

FAB YIELD, OPERATIONS, AND FACILITIES

New exhaust emission abatement technologies provide improved removal efficiency for continuous emissions and catastrophic releases. Integrated combustion and scrubbing units are available for pointof-use abatement of epitaxial deposition process exhaust, which can contain flammable, pyrophoric, and corrosive gases. Canister-type resin adsorber systems are available for the removal of hydrides from process exhaust. Roof-mounted resin adsorbers can treat catastrophic releases of hydride gases. NOx emissions from natural gas fired combustion sources, primarily boilers, can be reduced from over 100 ppm to 30 ppm and lower using variations of oxygen trim technology. Process logic based combustion management systems (CMS) vary combustion air and flue gas recirculation feed rates as functions of heat demand. Some of these technologies are also effective at lowering carbon monoxide emissions. Several new water treatment technologies have applications in semiconductor wastewater discharges. Metal matrix adsorption media have been proposed in place of iron coprecipitation for arsenic removal. Electrodeionization and continuously cleaned membrane systems utilizing vibration, have application both in waste water treatment and for replacing ion exchange and supplementing reverse osmosis unit processes in ultrapure water production.

FURTHER READING Bedford, T., and R. Cooke, Probabilistic Risk Analysis, Foundations and Methods, Cambridge University Press, New York, 2001. Factory Mutual Insurance Company (FM Global), Property Loss Prevention Data Sheet CD ROM: 7-7 Semiconductor Fabrication Facilities, Rhode Island, 2002. International Code Council, International Fire Code, Falls Church, VA, 2000. National Fire Protection Association, National Fire Code, Quincy, MA, 2003. Pham, L., and D. Pryor, “Toxics and Combustibles: Designing Gas-Detection Systems,” Chemical Engineering Magazine, July 1, 1998 (also available as Key Considerations for Designing a Gas Detection System at www.semigasdetection.com). Semiconductor Equipment and Materials International, SEMI International Standards, San Jose, CA, March 2004. Sutton, I. S., Process Reliability and Risk Management, Van Nostrand Reinhold, New York, 1992. Trammell, S. R., D. K. Lorenzo, and B. J. Davis, “Integrated Hazards Analysis: Using the Strengths of Multiple Methods to Maximize Effectiveness,” Proceedings of the 2003 American Society of Safety Engineers Professional Development Conference, June 2003. Wentz, C. A., Hazardous Waste Management, McGraw-Hill, New York, 1989.

INFORMATION RESOURCES AIChE Center for Chemical Process Safety, www.aiche.org/ccps ASHRAE Handbook of Fundamentals CD-ROM, www.ashrae.org EM (Environmental Manager), Air and Waste Management Association, www.awma.org Fire Protection Engineering, Society of Fire Protection Engineers, www.pentoncmg.com/sfpe International Sematech Technical Reports, www.sematech.org Occupational Hazards, www.occupationalhazards.com Pollution Engineering, www.pollutionengineering.com Professional Safety, American Society of Safety Engineers, www.asse.org Semiconductor Fabtech, www.fabtech.org SEMI Facilities Standards and Safety Guidelines, www.semi.org SESHA e-Journal, www.seshaonline.org SESHA SERF CD-ROM, www.seshaonline.org U.S. Code of Federal Regulations 29 (U.S. OSH Act), www.osha.gov U.S Department of Transportation FMCSA, www.fmcsa.dot.gov U.S. Federal Emergency Management Agency, www.fema.gov

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 37

PLAN, DESIGN, AND CONSTRUCTION OF A FAB IDC Corporation Portland, Oregon

37.1 INTRODUCTION Those who are in the semiconductor business realize that there are many pressing issues that determine the success or failure of semiconductor manufacturing facilities. This single chapter can’t address all of those issues in detail. Accordingly, our intent is to address at an overview level many of the concerns, as well as the business strategies, that are among the most pivotal in the planning, design, and construction of these facilities. The semiconductor industry is renowned for the accelerated rate of its technological evolution. The pace of that evolution is like no other dominant manufacturing enterprise since the Industrial Revolution, not even the steel, automotive, agriculture, timber, or textile industries. Much of that breakneck pace is attributable to the unprecedented expectations placed upon the product ultimately produced. At the heart of this relentless technological march is the renowned Moore’s law, which dictates a doubling of semiconductor performance every 18 months. Such ambitious expectations for the products manufactured apply similar expectations to those responsible for producing the products. Semiconductor fab owners increasingly want more performance for their money. At the same time costs are soaring above $2 billion for a new fab and the margins earned on every chip are shrinking due to increased competition and the migration of the industry to lower cost locations. Today prudent owners are making comprehensive business planning and cost modeling as important a part of their fab planning process as the design and construction processes for the fab itself. Design/build continues to gain popularity as a delivery solution that can add value to fab projects in multiple ways, not just for buildings but also for the individual systems within those buildings. Design/build has been particularly well received outside the United States in the semiconductor industry because of its inherent placement of overall project responsibility within a single source, rather than an assorted cast of contractors unfamiliar to an owner. Design/build is also better able to facilitate the global technology transfer that is an increasingly important driver in the industry as semiconductor manufacturing globalizes. The following is a review of some of the key factors manufacturers need to consider for the planning, design, and construction of semiconductor facilities.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

37.1

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.2

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.2

FAB YIELD, OPERATIONS, AND FACILITIES

37.2 PLANNING Semiconductor facility planning is a challenging undertaking that, like other complex processes, is best analyzed by component. As these topics reflect, the planning process encompasses much more than a fundamental assessment of the physical characteristics of semiconductor sites and facilities. Good planning also requires a careful scrutiny of the short- and long-term economic characteristics of semiconductor manufacturing, including the use of accurate diagnostic tools for cost modeling, energy optimization, and risk assessment. 37.2.1 Site Selection In the semiconductor industry’s early days, competition for the siting of new facilities was particularly intense among U.S. states, which developed many creative approaches to attract new facilities. These included long-term tax abatement, land gifts, cash, revenue bonds (at times reaching billions of dollars in value and with lenient payback periods reaching 20 years or more), and a host of other incentives ranging from worker training to special mass transit discounts for employees. As the industry spread to Asian and European locations, the competition for new fabs became more intense. U.S. states had to start competing with other countries as well as each other. This phenomenon has brought both good and bad news to fab owners. On the positive side, it is refreshing for an owner to be lavished with so many apparently attractive gifts. On the negative side, however, owners can be overwhelmed by the sheer mass and complexity of the incentives being offered. When multiple locations are vying for an owner’s attention, it is vital that the particulars of each package be carefully reviewed in detail. Incentives are not always as desirable as they appear. The most prudent owners seek help in sorting through the many factors that guide the site selection process. Incentives are only one of those factors. Environmental implications have gained importance, as regulations have become more stringent related to a fab’s proximity to wetlands, accessibility to adequate waste discharge resources, and air emissions implications. If owners have aspirations to expand their existing operations on a site (and most owners eventually do), they must factor in the site’s future ability to absorb expansion without exceeding the location’s environmental permitting limitations. Many owners have found themselves “trapped” in under-producing facilities on sites with plenty of room for physical expansion, but no additional regulatory capacity for wastewater or air discharges. Here is a list used by a leading international semiconductor manufacturer that points out some key considerations used for selecting sites for semiconductor fabs: • Site topography issues, such as susceptibility to flooding, hills, or other elevation irregularities. • Any unique climatic conditions, such as temperature, humidity, pollution, or wind patterns that would affect contamination control. • Proximity to a major airport and highways. • Adequate utility service, especially for power and water. Semiconductor plants are heavy water users, so this is a priority issue. • A large, flat parcel with no major geotechnical issues, such as vibration problems due to proximity to railroads, highways, or other manufacturing processes in the vicinity. • Access to a sizable labor pool with technical workforce ability. • A local government and business environment supportive of and receptive to new industry. (Incentives are tangible demonstrations of this, but even the subtle expression of a welcoming attitude within a community is a factor noticed and appreciated by owners.) • A permitting process with rapid cycle times and local requirements that are consistent with uniform codes and standards. Communities lacking fast-track permit approval may find themselves passed over, since the industry is rife with tales of major projects encumbered by protracted permitting delays.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.3

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.3

• The “livability” issues; a community that offers employees low cost of living, affordable housing, and quality education opportunities. • A region that promotes investment in high-tech industry, including industries that are not semiconductor-related. • For international sites, the priorities are stable economic and political systems, competitive costs for construction and ongoing operations, and logistics infrastructure to support the development of future operations.

37.2.2 Master Planning Just as the need for larger yields in the semiconductor industry has demanded more performance per square foot from wafer fabs, so too are fab sites expected to yield more usability per acre. Accordingly master planning must not only accommodate an owner’s immediate building needs but also anticipate the addition of future buildings to a site, as well as future additions to existing buildings. Depending on the needs of the owner, master planning may be a highly dynamic process with an emphasis on rapid updates and conceptual exploration. In larger and less schedule-driven scenarios, master planning may focus more on phasing with links to anticipated capital expenditures over a period of years. Sometimes the role of master planning is perceived primarily as an exercise in the appropriate placement of buildings on a site. However, like so many other aspects of semiconductor fab delivery, the expectations of this specialized skill have become more demanding. In earlier eras, larger owners in the industry often purchased large parcels with the expectation that sizeable portions of those parcels would be “banked” for development at a time and in a manner to be determined in the future. Rising land costs have made this type of strategy a luxury for all but the industry’s most affluent leaders. The focus of master planning today is making the maximum use of every acre or hectare on a site, both now and in the future (Fig. 37.1). Some semiconductor campuses are master planned for dense packing of fabs, with some manufacturers co-locating fabs with adjacent test and assembly facilities. This approach reduces transportation costs for semiconductor products as they move through the supply chain from raw silicon wafers to processed die to finished, packaged chips. Site master planning combines facts and ideas to explore options, alternatives, or concepts intended to ultimately benefit and enable an owner’s business goals and objectives. Master plans

FIGURE 37.1 Example of a master plan for a semiconductor manufacturing campus.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.4

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.4

FAB YIELD, OPERATIONS, AND FACILITIES

are best prepared in concert with owner stakeholders. They should serve as a roadmap that guides the utilization of sites to their highest potential while establishing a desired corporate image, achieving operational efficiencies, and practically providing for security and other functional siterelated factors. Well-rounded providers of master planning services coordinate the functions of development feasibility analysis and land-use and zoning compliance with site master plan preparation and site design. 37.2.3 Cost Modeling “Cost modeling” is a relative term. In the past the term’s use in the industry was primarily associated with relatively short-term implications, such as the forecasting of a fab’s construction costs, with perhaps some rough estimates of a few fundamental operational metrics such as anticipated ramp-up times. New technologies and tools have greatly expanded the powers of the cost modeling science, when in the right hands. The cost modeling suite of skills still delivers modeling metrics for capital improvements, but the good news is that the refinement of cost modeling expertise has made those models increasingly reliable. This is largely attributable to the industry’s maturation, which has enabled the compilation of fab performance statistics based on years of performance and not on the theoretical speculation that prevailed in the industry’s earlier eras. Cost modeling is most useful when it is based on hard data from real-world fab operations that allow owners to accurately benchmark the performance of their existing or planned fabs against the best performance in the industry. Such data can be better exploited today, thanks to advanced cost modeling software that brings greatly enhanced validity to the output of such models. Today’s cost modeling methodologies can yield accurate projections for such crucial decisionmaking data as facility ramp-up times, production capacities by product type, proximity to customer, complementary logistics, carrying costs, and most importantly, overall return on investment. Considering the power and accuracy of advanced cost modeling methods, cost modeling should be among the priority activities undertaken by owners planning either new fabs or fab upgrades. 37.2.4 Environmental/Permitting It is a mistake to regard permitting as a perfunctory activity when planning a semiconductor fab project. An unfortunately large number of owners in the industry can attest that permitting can pose many pitfalls during the planning process, including some that can turn out to be tragic “deal breakers.” The first precaution related to permitting is to seek the assistance of specialists with local regulatory relationships. This requires more than connections to regulatory officials, however; the localized knowledge must be combined with semiconductor-specific technical knowledge relevant to the requirements of semiconductor facilities. This knowledge comes in handy when the inevitable unexpected obstacles arise that can cause debilitating delays in a fab’s design and construction schedule. For an industry whose owners are most acutely and often painfully aware that “time is money,” delays related to permitting must be resolved quickly. Scheduling is an important element of timely permit processing. Seasoned experts use an “umbrella” strategy that consolidates multiple permits from multiple phases within a single permitting package to avoid wasteful duplication of regulatory processes. In fast track situations, which are often the norm on semiconductor fab projects, individual permit packages are overlapped to further accelerate the schedule. Owners must be mindful of the variety of environmental issues that can create semiconductor fab permitting delays. These include permitting concerns related to a semiconductor fab’s use of hazardous chemicals and gases, traffic, water consumption, discharge of wastewater and air emissions, storm water management and resolution of potential wetland, and wetland buffer conflicts. Of these, air emissions and wastewater discharge have tended to be the more common permitting-related impediments for semiconductor facilities.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.5

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.5

Semiconductor owners considering new sites or expansion on existing sites need to accurately determine the water supply and wastewater discharge requirements to be able to develop and incorporate the appropriate water conservation, recycle, and reuse strategies. In addition, criteria and hazardous air pollutants and air toxic potential emissions from their operations need to be characterized to assure that planned changes in the quality or quantity of emissions will be compatible with national, regional, and local air quality standards and emission limits. Some good news for manufacturers is that recent improvement in technologies for water management and air emission abatement specific to semiconductor manufacturing can help ease permitting requirements. Owners can find more information about these technologies from permitting specialists. Such seasoned specialists can offer other negotiating and technological approaches capable of resurrecting fab projects that might otherwise seem doomed. For example, environmental concerns related to storm water, air emissions, wetlands, and endangered species can be addressed applying “mitigation credits.” One of the most important pieces of advice related to permitting is to permit facilities for the future as well as the present. There are many cases of semiconductor operations with a need to expand that find themselves constrained by outdated permits that lack provisions for larger building footprints or increased water consumption, employment, impervious areas, air emissions, and wastewater discharges. When contemplating their capital improvement plans, owners need to ask “What could this facility look like in five years and beyond?” and plan a permitting strategy accordingly. An important part of fab planning design and construction is the early identification of potential environmentally related issues, concerns and government notifications and permits that could result in prohibiting the project, delaying the project schedule for construction or operation, or adding substantial unplanned capital, and/or operating costs. There are often historical, current, and/or perceived future issues, sensitivities, or commitments of the local community and local, state, and federal officials that could pose roadblocks. 37.2.5 Groundwater Monitoring To be able to understand potential site environmental issues, an initial or updated environmental site assessment or environmental due diligence is required prior to either purchasing the property or proceeding with the final design. The environmental site assessment should include a thorough researching of existing data related to the quality of the soil, surface water, and groundwater beneath and near a site. This is particularly essential for larger projects. If soil and groundwater data aren’t available, new data should be collected. It is important to determine and understand how your site has been used previously, as well as researching present and past industries within a mile radius of your site. Groundwater monitoring is a prudent response to the reality that today’s owners can inherit responsibility for damage done to a site in past years by former owners. In earlier years the dumping and release of chemicals, petroleum products, and garbage onto the land and into surface waters has resulted in soil, surface, and groundwater contamination from industrial, commercial, municipal, and federal government plants and operations. Contemporary owners want to be assured that underground water pollution plumes are not migrating to or from their site. Establishing baseline groundwater quality prior to proceeding with a major project, as well as performing ongoing groundwater monitoring, will verify that your operations are not contributing to or adversely impacting groundwater contamination. This is increasingly important for semiconductor plants where the source of the water supply is from on-site or nearby groundwater production wells, or the surrounding community water supply is from individual or common supply wells. In addition, before any on-site project requiring soil excavation and underground utility work begins, a soil management plan should be developed to address the presence of contaminated soils. The soil management plan should include the anticipated location and level of contamination present and proper classification of the soil as either hazardous or nonhazardous waste. Protocols should also be developed to protect the construction workers, provide off-site transportation and disposal, on-site backfilling, or other on-site reuse of the excavated soil.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.6

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.6

FAB YIELD, OPERATIONS, AND FACILITIES

37.2.6 Leadership in Energy and Environmental Design/Green Considerations Green buildings achieve much of their gain in performance through the superior integration of all building systems during design. Unfortunately, the traditional approach to building design is compartmentalized, meaning that the building subsystems—siting, exterior surface, HVAC, interiors, and the like—are designed in virtual isolation from one another. The preferred way to achieve sustainability in building design is through an integrated design approach, which takes into consideration the effects these subsystems have on each other. Integrated project teams can facilitate sustainability early in the project, when the entire team— owner, designers, and, if practical, contractor, tenant, and operator—organize a charette, or workshop, to agree on an overall vision for the building and prioritize green building goals and design criteria. Typical design criteria cover energy efficiency and renewable energy, direct and indirect environmental impacts, resource conservation and recycling, materials selection, and indoor environmental quality. Progressive building design firms often benchmark their planned designs against other green buildings to determine “best in class” practices and to assure that products or systems will perform as designed. Databases maintained by the U.S. Environmental Protection Agency, the U.S. Department of Defense, the U.S. Green Building Council, and a number of U.S. and non-U.S. governments and organizations are very useful in benchmarking. There is a growing familiarity with and application of the Leadership In Energy and Environmental Design (LEED) program developed by the U.S. Green Building Council, which offers a building rating system that evaluates building performance over a building’s life cycle. A comparable system, called Building Research Establishment Environmental Assessment Method (BREEAM), exists in England and other building rating systems are being developed around the world. 37.2.7 Programming, Schematic, Design Development, and Construction Document Programming is a melding of minds between the owner and those who are helping transform an owner’s vision for a facility into reality. The ideal programming session combines these individuals in an extended interchange of aspirations and project data that may last for hours or days. The fundamental goals of programming are to establish the owner’s goals, collect facts, identify needs, develop concepts, and determine issues and action items. Programming also clarifies the respective roles of a project’s responsible parties. Conducting programming as a formalized process helps initiate a project team with a culture of sound project management and collaboration. It is true that many projects have been designed and built successfully without a formalized programming approach. It is also true that many projects have produced great disappointment for owners and those on their project teams because strong lines of communication weren’t opened among all parties early in the project planning process. Programming was not always characterized by a spirit of free exchange and close teamwork. In the past, programming resembled the process of childbirth in less progressive times, when obstetrics was treated as a shielded medical procedure involving only the mother and doctor or midwife. Programming was similarly performed in a “vacuum” without client involvement. This produced the inevitable conflicts that arose when clients learned of questionable design concepts after they had been developed, instead of before, creating many a costly project restart. Happily, the trend in programming has moved toward an emphasis on client involvement, just as hospitals have learned the benefits of making family members feel welcome in the delivery room. The result is that programming has become a much more open and dynamic process that welcomes candid input from all participants, often in marathon programming sessions intended to create a “total immersion” atmosphere of collective brainstorming among a fab’s owner, designer, and constructor. The legitimacy of the role of programming role is rooted in the reality that no two projects or owners are alike—each project deserves its own fair hearing and nurturing through programming.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.7

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.7

Programming sessions are intended to define and refine the vision for a planned facility in the categories of function, form, economy, and time. Strong graphics are a staple ingredient of effective programming (Fig. 37.2). During the programming session, experienced programmers post “programming cards” on the wall that capture concepts being discussed with impromptu graphics. The graphics help direct the programming team’s focus on such central planning issues as functional relationships among internal spaces, air management concepts, the interaction of multiple buildings on a planned site, ergonomics and human traffic management, and many others. The heavy use of graphics has proven particularly effective for improving the quality of communication in programming sessions involving multinational project teams, which already face inherent language and cultural barriers. Most importantly, programming can save time and money for owners by promoting early team consensus on the definition of project goals, clarification of roles, confirmation of schedules, and collective contribution to the conceptualization of the finished product. Depending on the degree of comprehensiveness desired from the programming process, programming deliverables may include data related to cost estimates and project schedule. In the programming phase, these data may take the form of a range of general project cost and schedule parameters, understanding that specific cost and schedule data can’t be developed until project particulars are more precisely defined. The design process that follows programming is often divided into conceptual design, schematic design, design development, and construction document phases. The design phases continue the completion of information gathered during programming, verify existing conditions, survey existing installations, and collect existing documentation. Conceptual options are developed and reviewed. A limited number of alternatives carry forward into schematic design, whose deliverables include layouts, flow diagrams, life cycle cost analyses, equipment recommendations, and others as required. A formal schematic design report and estimate is often prepared to serve as a basis for owner decisions on the alternative to be carried into design development, which advances the design process to the point that construction documents can be initiated. At this point permit packages are prepared, long lead equipment is specified, and construction documents are developed including drawings and specifications. Tools that help keep the facility systems organized include utility matrices to coordinate a fab’s many utility requirements and load matrices to help plan energy allocations in an orderly way throughout the facility. Construction administration services can typically include answering contractor questions (RFIs), reviewing submittals, providing support for construction meetings, holding periodic site visits to observe the construction, and providing assistance with commissioning. It is recommended that formal review meetings be held at the end of conceptual design, schematic design, design development and before the issue of the construction package.

FIGURE 37.2 “Programming cards” are posted on the wall to capture design concepts and facilitate dialogue.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.8

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.8

FAB YIELD, OPERATIONS, AND FACILITIES

37.2.8 Energy Optimization In the semiconductor industry’s earlier days, product margins were high enough to make the output of product a priority, taking precedence over all other issues related to fab development and operation. In a fab’s financial model, energy as a percentage of the total fab cost was typically a relatively minor expense when compared to the extravagant costs of a fab’s tools and complex systems such as cleanrooms. While reducing energy costs in any industry is desirable, the economics of semiconductor production did not make it a significant concern for many years. As was the case in many other maturing industries, however, increasing competition in the semiconductor business brought a tightening of product margins that subsequently inspired a more vigorous pursuit of operational savings wherever possible. Rising energy prices during the 1990s exacerbated the interest in improving the economics of energy. Owners began to explore energy reduction as a cost reduction strategy. Technology was able to provide solid solutions, but predictably there was resistance to the “first cost” of implementing new energy reduction approaches. Owners are justified in approaching energy optimization in the same way they approach every decision related to the development and operation of a fab—from the business perspective of seeking the best possible return on their capital improvement investment. The problem is that many owners have deprived themselves of savings by pursuing resource reduction using a piecemeal approach that seeks to improve one system at a time within a fab. While that approach is better than doing nothing, it fails to exploit the full potential of the energy savings that can be realized in most fabs. The best way to approach the issue of energy optimization is with a value engineering effort that analyzes potential energy savings in a holistic manner, recognizing the complex interrelationships of energy-consuming fab systems (Fig. 37.3).

Support spaces

Utilities

FAB

:N2 CDA UPW WWT

Tools

Cleanroom

Heat to PCW

Recirculation fans

Lighting and misc.

Pressurization air

Cooling coil

Heat to room

Exhaust

MAH

Chiller plant FIGURE 37.3 Illustration of the interrelationships of fab systems that must be analyzed to achieve facilitywide energy reduction savings.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.9

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.9

Power reduction strategies yield revenue benefits not only through the obvious form of utility dollars saved, but also through energy reduction rebates that are widely available to industrial users from utilities. In addition, reduction in chiller plant power consumption and operating costs can sometimes also earn utility credits. The following are some other areas of opportunity for energy savings within semiconductor facilities. • Specialized equipment that combines improved energy efficiency with improved performance efficiency. Examples include innovative air handling equipment that consolidates humidity and temperature controls into a single system while delivering energy savings of 25 percent or more compared to conventional makeup air handling approaches. • Premium efficiency motors. These are often overlooked during a project’s procurement process because they are more costly than conventional motors. When viewed in terms of long-term cost saving potential, however, premium efficiency motors often involve short payback periods and generate impressive residual returns on investment over the life of a facility. • Adjustable frequency drives on motors and pumps. These can be incorporated into many motors and pumps used for air and fluid handling equipment and many other systems subjected to varying loads, including cooling towers. • High-efficiency chillers. These are often overlooked by fab designers, who may specify commercial grade chillers instead of the high-efficiency industrial grade equipment that is better suited to the achievement of long-term energy savings. Care must be taken in the specification of highefficiency chillers, however. Engineers must study the shape of a facility’s anticipated climate load so that the larger chillers are configured to remain loaded and thereby be able to consistently operate at their highest efficiency levels. • Heat recovery from condenser water. A specialized design approach has been devised that enables an industrial facility to derive approximately 40 percent of its heating needs through heat recovered from condenser water using heat exchangers. This approach has been successfully implemented in multiple semiconductor wafer fabs. • Acoustically designed fans. This innovation is the result of a collaboration between a fab design firm and an equipment manufacturer to apply acoustic technology used in jet engine design to the design of extremely high-performance cleanroom fan systems. • Condenser water temperature reset. A reduction in the set point for condenser water improves chiller efficiency as the condenser water supply sent to the chillers declines. This strategy must be carefully implemented, however, since it carries a point of diminishing return. • Advanced technologies in emissions abatement have produced equipment that consume significantly less energy than alternative emissions abatement systems while providing superior abatement efficiency. 37.2.9 Risk Assessment Anyone in the semiconductor industry can recite a list of concerns reflecting their individual interpretation of “risk.” The industry has been fortunate that it has been able to maintain a low profile and genuinely benign image in the public eye regarding the risks it poses. Part of the reason for that low profile has been the fact that the industry enjoys a good safety record, especially when compared to many other industries involving large numbers of employees and high volumes of output. The basic risks attending the semiconductor manufacturing process include the involvement of some hazardous chemicals and gases. The industry has responded responsibly to the mitigation of such risks with exhaustive life safety systems and protocols, double-containment approaches for piping carrying hazardous materials, and advanced approaches to early warning fire detection and suppression. Indeed, the advent of the “H6 occupancy” codes, which regulate spaces housing hazardous materials or processes, can be credited to the semiconductor industry. All industries faced a new array of risk assessment challenges resulting from contemporary concerns about terrorism. While once semiconductor manufacturing posed risks that were known and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.10

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.10

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 37.4 Closed circuit monitoring systems and photometric lighting simulation software are just two of many technologies used to meet today’s facility security requirements.

controllable, the post-9/11 world has removed much of the predictability from the industry’s conventional approach to risk assessment. For that reason, risk assessment has gained much greater stature as a priority planning issue. Following 9/11, owners in all industries began frequently unfocused, reactive, and impulsive efforts to grapple with the new paradigm in risk assessment. Many owners attempted to buy their way to greater peace of mind by purchasing pallets of security equipment such as closed circuit surveillance systems, alarms, and fencing. It is important for semiconductor owners to resist this temptation and acknowledge that security is about much more than hardware. Industry owners that have seen their risk assessment needs best served are those who accept the reality that no security budget can eliminate all risk. The best way to approach this challenge is rationally and thoughtfully, beginning with a vulnerability assessment that methodically prioritizes risk-related issues related to fab operations. See Fig. 37.4. The following are some key tasks that are routinely performed for semiconductor fab risk assessments: • Perform a risk vulnerability assessment to identify and prioritize potential risks and security vulnerabilities. There are well-developed checklists to guide owners in performing a detailed analysis of their sites, buildings, personnel, and operational/ procedural issues related to risk. The assessment should address: 1. Site planning of facilities and infrastructure, transportation and utility systems, and area-wide particulars of vulnerability. 2. Determination of a central security command center appropriate to the size of the operations and workforce. • Design of tamper- and blast-resistant structures, windows, and door treatments. • Review of area lighting and landscaping considerations, particularly at pedestrian pathways and sidewalks. Advanced photometric simulation software models can help assess lighting levels throughout a campus, identifying lighting deficiencies and recommending solutions. • Review of emergency call location areas, enabling residents or staff members to summon assistance in the event of emergency conditions. • Development and implementation of security for networks, software and hardware, encryption, and telecommunications. • Potential need for web-enabled video cameras allowing real-time remote monitoring of facility activities. New systems enable a quality of remote video surveillance far superior to that of the

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.11

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.11

past. This includes enhanced abilities to remotely monitor security conditions in remote locations from anywhere in the world, using password-protected Internet access. • Video motion detection systems permit the detection of entry or intrusion using video images. This new technology is based on computer algorithms that analyze the received video images and compare them to the stored images in the system memory. “Smart” fencing systems also offer unprecedented advantages for pinpointing and relaying to command centers the precise location of intruders attempting to penetrate a site’s perimeter.

37.3 DESIGN The structural and systematic complexity of microelectronics manufacturing facilities requires a level of attention to design detail that may be greater than that required by any other previous manufacturing industry in history. Complicating this challenge is the fact that a large percentage of the capital improvements undertaken in this industry, whether to develop new facilities or upgrade existing ones, must be performed under accelerated project schedule conditions. This blend of technological complexity and schedule intensity has made it increasingly important for design teams to closely integrate the multiple disciplines that comprise a fab’s design throughout the design process. A related strategy is to also integrate a fab project’s designers with the project’s constructors. Close and continuous communication between designers and constructors enhances the constructability of the design as it is being developed. This is greatly preferable to attempting to remedy constructability issues after designs have been implemented on the construction site. The following is a review of some of the key areas of focus during the design process.

37.3.1 Regulatory Compliance Designing a new semiconductor fab requires compliance with a complex and sometimes conflicting set of requirements regulated by an alphabet soup of regulatory entities—IBC, IFC, IMC, UBC, UFC, UMC, OSHA, NFPA, NEC, and many more. These regulations are there to protect factory workers, emergency responders, and the general public put in harm’s way in case of an accident. Insurance providers sometimes add their requirements on top of these, in order to limit the potential for damage to equipment and buildings. It requires an experienced team with code expertise to successfully navigate this intricate set of rules and regulations. When the industry began in the 1970s, it introduced design challenges that were unprecedented and therefore not addressed by conventional codes. Wafer fabs use a broad spectrum of hazardous materials from corrosives to explosives, reactives to flammables, and pyrophorics to highly toxic agents. However, unlike many traditional industries, cleanroom requirements stipulate that these materials be used within the chambers of manufacturing equipment and that fumes or vapors not be allowed to escape into surrounding spaces where they can pose a hazard. Leading fab designers and owners worked closely with federal, state, and local regulatory officials to devise codes that responded to the fledgling industry’s needs. The Uniform Building Code in 1984 was the first to create a special H6 occupancy to address the unique requirements of semiconductor manufacturing facilities. It incorporated a detection and controls strategy addressing individual equipment called a workstation, in lieu of overly restrictive building regulations. This is akin to modern drugs designed to attack only cancerous cells versus the older approach of blanket annihilation of all cells in order to destroy a few bad ones. Since the first version published in 1984, there have been several improvements leading up to the development of the International Building Code (IBC). The IBC incorporates the lessons learned from the failures and successes of the last 20 years and matches it with the technological advances of 21st century systems.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.12

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.12

FAB YIELD, OPERATIONS, AND FACILITIES

The regulations designed to ensure life safety in these facilities are based on the following key concepts: 1. Reduce potential fire hazards by restricting the amount of flammable and combustible materials allowed per square foot of manufacturing space and within one workstation. 2. Reduce potential health hazards by limiting the amount of toxic and highly toxic materials allowed per square foot of manufacturing space and within one workstation. 3. Reduce potential explosion hazards by increasing the ventilation rates to four cubic feet per minute per square foot of manufacturing space. 4. Limit the storage of hazardous materials within the cleanroom to those needed in a process. All additional materials are required to be in separate chemical rooms. 5. Require detection and control systems at workstations and in the manufacturing and storage areas to detect leaks and spills early. 6. Require fire and smoke detection to detect fires before they get out of control. 7. Require a trained emergency response team that is ready to respond to any emergency 24/7 well before the fire department. 8. Require adequate exhaust ventilation to dilute and remove any fumes or vapors promptly. Separate exhausted enclosures are required at potential leak areas to prevent mixing with the room air. 9. Require adequate exit doors to ensure prompt egress by occupants. 10. Require that chemical storage rooms be located on the building perimeter to allow emergency personnel to contain a fire easily. 11. Limit the number of stories to prevent very tall structures that pose significant challenges in case of an emergency. 12. Require separation of chemical transport paths and exit routes. Later, as the industry globalized, this process of the industry’s advocacy for code improvement crossed international borders. In some countries codes are antiquated, not applicable to hightechnology facilities, and seemingly unsuitable to Western standards. Code standards for life safety designs can also require special acculturation effort. If local suppliers cannot provide products that meet standards for U.S. safety requirements and insurance underwriters, local officials may require a thorough explanation of why imported technologies are required. An example is early warning smoke detection systems that are required by U.S. code NFPA 318 for cleanrooms. This requirement may be unfamiliar to many non-U.S. officials. Another example of code acculturation is the typical reliance of U.S. companies on the National Electric Code for electrical design. This standard, too, may be unknown in non-U.S. locations. Owners may find that some officials in international locations prefer to use ISO standards in lieu of U.S. code standards. To help remedy this problem, the fab design process can be expedited using a “code equivalence matrix” that reduces the complication and delay of reconciling U.S. and non-U.S. codes. 37.3.2 Architecture Vision and leadership are two of the most important qualities architects can bring to a project. The most successful projects are led in a true spirit of collaboration, based on open communication, trust and respect, where innovation and invention can be given the best chance to flourish. This is how an owner’s vision is transformed into successful architecture. This architectural philosophy is best initiated with a refined approach to project planning and programming emphasizing listening to the client. Once a project team has gained a thorough understanding of an owner’s objectives, the team can more effectively investigate appropriate design options for the owner’s consideration. Architectural design is best performed in an integrated planning-design-construction team, which can provide early constructability and maintainability input into the planning and design process, along with construction planning and scheduling. The ability to blend functionality, accountability,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.13

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.13

design excellence, and project coordination into a unified team, minimizes the client risk and maximizes the opportunities for success. A highly collaborative project team structure of this kind ultimately delivers faster, better, and more cost-effective projects. Here are some of the protocols applied to build a team environment and hone the architectural design process to best capture and implement an owner’s vision for design: • Listening: A commitment to listen to the owners, project team partners, and each individual team member enhances a team’s ability to create accurate design solutions in a timely manner. Daily informal communication is encouraged throughout the design and construction process to reinforce this emphasis on communication and respect of all contributing opinions. • Programming: Projects that begin with targeted programming sessions involving all stakeholders increase their odds of a successful outcome. Programming session participants jointly define project goals, list design criteria, identify concepts, and capture unresolved issues for further investigation. This focused effort evaluates previously conceived ideas for validity and develops a basis of design for the entire team to build upon. • Wall meetings: Weekly wall meetings are excellent unifying exercises in which current design status prints are pinned on a review wall to formally bring all design disciplines together (Fig. 37.5). Each design lead presents their status and indicates areas of question where more specific coordination is required. The owner is also invited to participate in these meetings as an internal member of the team. • Design charrettes: Periodically throughout the design process, design charrettes are used to hone in on a specific issue. The areas in question, represented by key individuals and owner representatives, are worked through in focused sessions, resulting in timely solutions with multidiscipline input and buy-off. • Web-based interactive tools: On projects involving international design teams, secure projectspecific web sites can be used to facilitate a rapid exchange of information and real-time simultaneous review of drawings and other documents by geographically dispersed project team members. These sites are also beneficial for collecting comments from a broad group of constituents to enhance the project schedule. • Management meetings: Weekly management meetings attended by the owner, contractor, project manager, and the superintendent ensure quality control and coordination throughout the course of the project. 37.3.3 Interiors Semiconductor facilities consist of a diverse variety of interior spaces ranging from conventional office space to cleanrooms that must meet rigorously controlled environmental specifications. In that regard,

FIGURE 37.5 Regular “wall meetings” help keep design teams in tune and on track.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.14

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.14

FAB YIELD, OPERATIONS, AND FACILITIES

these facilities present among the most formidable and stimulating challenges for interior designers. As integrated circuit linewidths have continued to shrink, microelectronics cleanrooms have been burdened with greater responsibility for controlling contamination at the molecular as well as the particulate level. Interior designers working in advanced wafer fabs must not only have skill in the craft of design, but also intricate knowledge of the composition of the specialized finishes and base build materials that go into the latest submicron cleanrooms. Every piece of material used in a cleanroom is a potential source of airborne molecular contamination (AMC). Interior designers work closely with materials manufacturers, procurement specialists, and contractors to analyze inventory and select materials with the lowest “off-gassing” characteristics. These professionals must also understand how to apply those materials using the precise protocols that comprise “clean building” construction methods. “Clean building” approaches stipulate the exact order and manner in which materials are introduced and installed in the cleanroom. If any step is out of sequence, the entire fab can suffer impaired product yields at significant cost to the fab owner. The need for carefully sequenced steps in a cleanroom continues long after the construction is complete. Interior designers help develop dressing protocols used in the gowning areas to assure that workers moving into clean areas pose a minimal risk of contamination. Gowning protocols must be continuously maintained. Interior designers deal with nonaesthetic design issues as well, such as assuring that interior corridors are properly sized and structurally sound enough to accommodate today’s very large and heavy semiconductor processing tools. See Fig. 37.6. Semiconductor facilities also pose unique ergonomic challenges to interior designers. Semiconductor cleanrooms are far from ordinary work environments. White is the traditional color of their walls, yellow is the color of the light, windows with views to the outside are nearly nonexistent, and workers are confined to bunny suits in cleanroom settings for hours at a time. In recent years creative interior design has been able to break some of these stereotypes. In at least one prominent U.S. fab, designers were able to carefully position windows that offered an outside view to workers without jeopardizing the delicate photosensitive cleanroom processes. In another major U.S. fab, multicolored walls provided a refreshing departure from the exclusive decades-old tradition of “cleanroom white.” 37.3.4 Engineering Semiconductor facilities rank as among the most costly and complex of buildings. For this reason, every fab project carries with it numerous opportunities for significant cost and schedule overruns. That is why one of the most formidable challenges faced by the owners in the semiconductor industry is how to structure project delivery approaches that provide the greatest assurance that projects will be designed and built to meet the owner’s expectations for safety, schedule, budget, and quality.

Assembly and gownroom

Fab support

SEM, TEM, SIM, AFM, etc. Plenum Fab ballroom Subfab E-beam, STEM, AFM, etc.

Back-end processing

Test and NEMS processes

FIGURE 37.6

Section view of a large fab.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.15

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.15

This challenge has been complicated by the diverse range of architectural, engineering, process, and construction expertise needed to complete such projects successfully. The traditional approach to wafer fab design was to have owners shoulder the responsibility for evaluating, hiring, and managing the myriad contractors required for fab projects. This included managing and frequently troubleshooting the individual contractual relationships with each contractor. History has shown that each additional contractual relationship added to a project increases not only the workload for owners, but also the number of opportunities for breakdown of communication between the owner and project team members. An approach that has proven successful in overcoming this problem over many projects around the world is the use of integrated multidiscipline project teams. This approach emphasizes the centralization of project control to encourage more cohesive and streamlined decision-making processes. The approach focuses on physically consolidating staff in all design disciplines who work side by side in a common space to facilitate the cross-pollination of design ideas throughout the duration of the project. In an industry whose preferred project delivery approach is fast-track, integrated project teams working in a unified manner offer owners the best capability to resolve conflicts and respond quickly to unforeseen circumstances, all with the intent of more reliably meeting the owner’s critical time to market demands.

37.3.5 Life Safety Systems Like so many aspects of semiconductor facility planning and design, life safety isn’t just about systems—it is about analytical planning. Life safety also isn’t just about protecting human life—it is also about enhancing the quality of the work environment by adding to social responsibilities. The early 2000s saw semiconductor manufacturers confronted with litigation brought by workers, alleging illnesses related to unsafe fab operations, an event that reminded owners that no industry is exempt from safety concerns. The long-term ramifications of life safety is another good reason to avoid the owner’s temptation to make life safety decisions based only on the first cost of life safety investments. For example, a traditional approach to fab fire protection was to liberally distribute smoke detectors throughout the building to assure adequate coverage. This approach was relatively inexpensive for both the hardware and installation. The problem came in the form of long-term maintenance costs; it is both difficult and hazardous for maintenance workers to service numerous smoke detectors mounted in high-bay ceilings. By contrast, a more advanced smoke detection approach using very early smoke detection apparatus (VESDA) air sampling technology carries a higher first cost, but its intelligent pinpointing of smoke sources provides better localized response and much lower maintenance costs than the massive mounting of cheaper smoke detectors. Life safety planning is best accomplished with coordination among the multiple disciplines involved in the design and installation of life safety systems. An example is elevators, which require such life safety provisions as recall in emergency situations and power restoration if elevator systems are sprinkled in a fire. Architects, electricians, and mechanics need to work with procurement specialists and suppliers to specify safety-related components such as elevator equipment, correct hardware for exiting systems, and coordinate air handler shutdown with smoke detectors and smoke fire damper systems. All of these systems interrelate and they all need to comply with national and local codes. Consistent with the focus on gaining more value for every capital improvement dollar, fab owners expect optimal long-term safety and reliability from their life safety systems. Semiconductor manufacturers now require that fab systems have Ethernet connectivity to enable centralized control and remote monitoring, further reducing costs. Today a full complement of security monitoring and alarm systems, including the detection of smoke, gas, and intrusion, can be remotely monitored and reactively modified to meet changing threat levels. Airflow modeling has become a standard tool used in the development of sophisticated life safety systems. Modeling can anticipate the dispersion paths of chemical or gaseous releases inside an air duct or outside a building. This technology can also be used to analyze dead air zones within a building to mitigate “sick building syndrome” caused by poor air circulation (see Figs. 37.7 and 37.8).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.16

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.16

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 37.7 Indoor airflow modeling accurately predicts airflow and temperature variations as well as concentrations of airborne contamination for cleanroom design and smoke for life safety system design.

FIGURE 37.8 Outdoor airflow modeling helps situate buildings on sites to reduce contamination threats from the outside.

37.3.6 Vibration Control and Foundation Design The relentless march toward greater miniaturization of integrated circuit widths has placed greater emphasis on the control of vibration that can disrupt the delicate processes that photographically apply a chip’s circuitry to silicon. Over the years the design and construction communities have evolved new approaches to respond to calls for greater stiffening of floors to resist vibrational interferences. A number of exotic techniques were tried and for a time “isolation joints” built into factory floors were a favored approach to impede the transference of vibration throughout a facility. However, building design technology has approached the limit to which design and construction methods can further decrease vibration threats within the structure itself. Accordingly, more of the responsibility for vibration control has shifted to semiconductor tool manufacturers, who have been striving to produce tools with greater on-board vibration resistance. The advent of multilevel fabs has added another dimension of challenge to structural design issues for wafer fabs. Increasingly owners are being confronted with sites that are physically constrained either because they are located in land-scarce locations or because they have little remaining room on their multifab sites. The practical approach to dealing with multistoried fabs is to take a more strategic approach to the planning of manufacturing processes, rather than attempting to achieve maximum vibration resistance throughout the entire structure. For example, the most vibration-sensitive processes can be housed on lower levels, where it is easier to buffer against vibration threats. While the smaller footprints of multilevel fabs require less land, they also necessitate more careful planning of the location of processing equipment, since they require the product to be moved vertically between floors rather than the horizontal sequence of operations used in traditional singlelevel fabs. 37.3.7 Ceiling Elevation Considerations In the past, areas above fab ceilings housed makeup air and exhaust systems. Connections for tools were often also located overhead. When the semiconductor industry moved to open ballroom layouts, an accompanying trend was the relocation of exhaust systems, tool utility distribution systems, and tool hookup access into the subfab. Today exhaust air handling equipment, gas piping, and utility support infrastructure is typically located in the subfab. Areas above the fab ceiling focus on sprinkler piping and air handling equipment for makeup air. (see Fig. 37.9) In general, using this configuration has resulted in less contamination threat in fabs. It stands to reason that reducing the pieces of equipment located above a fab can also enhance the cleanliness levels, since all equipment and other cleanroom components can serve as potential collectors of contaminants. Shifting more of the equipment and utility infrastructure from the ceiling to the subfab

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.17

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

FIGURE 37.9

37.17

Subfab clearance requirements.

can also lower costs by shortening the length of runs for utility piping that in the past, had to run all the way down to the floor from the ceiling. Fabs with higher ceiling heights may want to consider providing for maintenance access from above via catwalks or a “walkable ceiling.” 37.3.8 Seismic Bracing Generally most regions bordering the Pacific Rim have high levels of seismic activity. For semiconductor fab designers and builders, this means that not only must the building be designed to meet seismic hazards, but also a building’s individual components including the floors, ceilings, and processing tools also need to benefit from proper seismic design. Because fabs house quantities of hazardous materials, seismic criteria are understandably more stringent than those governing many other types of manufacturing operations. Seismic bracing has become more prevalent in semiconductor fabs in recent years in various forms, ranging from the added bracing of walls to “strapping” stabilization of individual tools. Some owners with greater experience in the industry have chosen to make the investment in applying seismic criteria more stringent than the requirements of prevailing codes as a risk management decision. Greater attention to structural strength in fabs has also been precipitated by new automated material handling systems to support 300 mm manufacturing. The conveyor equipment supporting these systems is often suspended from fab roofs, which must bear the weight of heavily loaded cassettes as they travel from one process to the next inside the fab. Heavy 300 mm tools have also boosted the need for greater structural strength in floors. Specialized structural/seismic consultants can be used to help calibrate the level of structural design to the seismic conditions that prevail

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.18

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.18

FAB YIELD, OPERATIONS, AND FACILITIES

at a given site. This can help assure that the owner is receiving the right balance of protection and cost-effectiveness when it comes to seismic issues. 37.3.9 Emergency Response and Disaster Recovery Emergency response and disaster recovery plans should be a required component of standard operating procedures in any semiconductor operation. The goal of emergency response and disaster recovery programs is to preserve worker safety, protect physical assets including products, and provide a recovery program that minimizes downtime for the manufacturer. These include response plans for natural disasters, force protection, public involvement, and information programs for residents, staff, and the public. In the semiconductor industry, every hour of down time can represent millions of dollars in lost revenue. A mandatory requirement for every semiconductor operation should be comprehensive planning for business recovery and staff training in emergency response to enable a rapid restoration of operations following unexpected interruptions. Emergencies can be managed by following these key steps: 1. 2. 3. 4.

Identify the cause of the incident and deploy the available staff to mitigate ongoing damage. Identify the effect on operations and take the needed steps to return service to normal. Follow up with a root cause analysis to prevent possible reccurrences. Restore all affected areas to pre-emergency condition.

Following are additional recommendations to help restore facility operations following an emergency: 1. Perform scheduled backups of all critical computer files to both magnetic media and web accessible file servers. 2. Customize your response plan to ensure the rapid deployment of key management, technical, and support personnel to aid in recovery efforts. 3. Enter into agreements with key vendors to provide 24 × 7 access to parts, labor, tools, machinery, and supplies if additional support should be needed. 37.3.10 Systems Integration The goal of systems integration is to build a cohesive network of controls that gives semiconductor fab operators optimal convenience while building a database of fab-wide tool and systems performance to benchmark present and future performance. A common shortcoming in the planning of systems integration strategies is the exclusive reliance on equipment suppliers for the selection of controls systems. Owners are best served with an objective third party that can recommend the best systems integration approach for a given fab environment without bias. An effective approach for the objective analysis of systems integration options is the owner’s collection of preferences related to systems integration requirements in a “design guide.” In effect these guidelines serve as the “rules” for a fab’s control system architecture—a standardized approach for all vendors to follow as system options are recommended. The owner can then review the recommendations so that the best systems can be selected and integrated to meet the specialized needs of a given fab. Systems integration technology has spawned new innovations in recent years that have brought dramatic advantages for fab owners. Examples include wireless operator stations and remote monitoring. Wireless operator stations are portable devices that allow workers to control fab operations from anywhere in the fab and with fewer operators. At one time web security concerns caused reluctance among some owners to implement remote monitoring approaches. Improvements in web link security makes remote monitoring a more attractive alternative to maintaining higher counts of operations staff within fabs.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.19

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.19

37.3.11 Telecommunications A semiconductor manufacturer’s telecommunications system can be expected to support data and voice communication requirements for the factory automation system, the building automation (facility management system), and the business administration of the factory. As wafer manufacturing technology has progressed, there is a corresponding increase in the need for automation in the factory. Increased automation allows fab managers to move products, optimize tool usage, maintain environmental protocols, and track tool telemetry. All of this relates to the owner’s ultimate goal of increasing wafer yields. Automation systems utilize the telecommunications system to transport data. It is common in a state-of-the-art 300 mm fab for every manufacturing tool to require at least one Ethernet connection. Some tools may require more than this. Tool manufactures may require an analog connection near their tools in order to provide remote tool diagnostics and software upgrades without requiring the tool vendor to be in the cleanroom or even at the factory site. In a microelectronics factory, the facilities management system is separate from the automation system, but still utilizes the same telecommunications cable plant and infrastructure. An integrated facility management system is required for these large manufacturing facilities to operate within specifications. There has been a slow evolution in the instrumentation and controls industry to adapt more open networking solutions such as Ethernet and to rely less on proprietary communication systems. The telecommunications system is a factory-pervasive utility that needs to be included in the initial programming of the facility. A state-of-the-art factory will require space for the communications equipment and cabling throughout the factory. 37.3.12 3-D Design Fab design is complicated by the many complex systems that go into these factories that are often packed tightly together on factory floors and in subfab spaces. These many components often conflict with each other on drawing boards as well as in the field during construction. One of the ways to minimize those complications and the “interferences” among fab pipes, ducts, and tools is through the use of multidimensional or 3-D design tools. 3-D is not widely applied in the semiconductor industry today, but it has proven its ability to improve performance and save costs on major semiconductor fab projects. Computerized multidimensional design systems instantly detect quantities of design irregularities that would take manual designers weeks to detect and correct. Multidimensional tools also track space usage changes, utility loadings, utility routings, tool pedestal changes, labor and material costs. These systems can also embed unit pricing and other data related to the labor and material associated with facility drawings. Multidimensional systems also provide lasting value by remaining as a permanent “virtual model” of the factory that can be reused in subsequent facility modifications, thus saving additional long-term costs. In one project consisting of a fab and three other support buildings, the owner was able to document the recovery of the cost of the multidimensional design system’s implementation within the project’s first 90 days. The owner attributed nearly $2 million in project savings to the use of multidimensional design tools.

37.4 CONSTRUCTION A deficient construction approach can quickly convert the best planned and executed design effort into disappointment or disaster. The need for careful front-end planning isn’t restricted to only the design phase of a project. The construction campaign also requires careful early planning to assure that the good work conducted during the design phase is properly reflected in the quality of work performed in the field. Close linkage of design and construction activities is a practice that can greatly improve the odds of success for construction activity. The design/build approach, of course, represents the epitome of design and construction integration. Far from being a transient trend in

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.20

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.20

FAB YIELD, OPERATIONS, AND FACILITIES

industry, the increasing popularity of design/build in some parts of the world is based upon the method’s inherent practicality. Clearly design/build isn’t right for every project, but when conditions favor its use it can produce significant advantages to owners in the form of speed, quality, and value. No matter which construction approach is applied, successful construction efforts begin and end with thorough planning and sound project management. 37.4.1 Project Management The semiconductor industry’s history of rapid process technology changes suggests that a desired outcome of every semiconductor construction project should be a facility that is adaptable to new production processes. In earlier days fabs were designed to produce a single product. Today a given fab may see many products and processes come and go before its life cycle is complete. The construction team’s first responsibility is to understand the needs of the facility and then make sure that the facility is not overdesigned and overbuilt. A simple example of the common tendency to overbuild is a water system with specifications that call for costly stainless steel piping, when all the owner needed or expected was PVC. Preplanning is an important first step to help avoid misunderstandings such as this. At the preplanning stage, forthright dialogue involving the owner, designer, and contractor occurs to meet the needs of an individual project and budget and not of standards applied on other projects. The schedule to be driven must be agreed upon by all parties and accurately reflected in the construction plan. Semiconductor construction will always require special considerations. Clean construction protocols are an example. In the past contractors didn’t use prescribed clean protocols—they simply made up the rules as they went along. Today’s fab constructors generally agree that clean protocols prove their worth in the form of improved fab ramp-up times and improved product yields after startup. Building clean is an example of an effort whose additional initial cost can be quickly surpassed by the loss of revenue to the owner in the form of reduced product yields. Making the decision to build clean is like many other decisions in semiconductor construction that are site- and clientdependent; it isn’t always justified, but you have to recognize when it is. A strong construction management approach includes the following characteristics: • • • • • • • • •

Effective front-end planning and budgeting Defined processes allowing the integration of design, procurement, and construction activities Proven tools to measure project performance and accurately forecast project costs Commitment to personnel safety and health on the project Preparation, training, and enforcement of clean construction protocol Respected quality assurance and control compliance program Ability to recognize impacts to the project cost and schedule and manage these changes effectively Formal and informal communication processes that allow for prompt and effective decision-making Strong community and labor relations programs that support the owner’s goals

37.4.2 Procurement When procurement is part of a semiconductor capital improvement project, a procurement plan is needed to establish goals for cost and schedule. This plan also serves as an ongoing gauge by which to measure a project’s ability to meet procurement goals. The plan needs to set clear expectations and designations of responsibility for procurement, delivery, and installation activities. For items coming from out of country, a logistics plan is needed to assure free importation entry. It never pays to wait until a project is well advanced to begin delegating procurement responsibilities. The expediting function is essential in any well-developed procurement program. It must be proactive, not reactive in nature, and it should assure that the status of every item procured is being carefully tracked at all times. The expediting process provides direct contact with manufacturers to

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.21

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.21

help remove obstacles impeding the delivery of materials by manufacturers, and if necessary finds alternative sources. The complexity and expense of semiconductor processing tools typically relegates responsibility for their purchase to the fab owner. These are exceptionally long lead items and require very careful handling due to their bulk and sensitive specifications. Some owners use “dock coordinators,” expediters on the fab site who assure that the timing of the tool arrival is precisely sequenced to match the pace of fab construction. Procurement specialists can assist the owner by helping with the inspection of critical pieces of equipment at the manufacturer before shipment to the job site. Procurement specialists also frequently help owners with prequalification of suppliers and contractors selected to work on a project. On international semiconductor projects, many basic materials may not be available from local suppliers or available in sufficient quantity to support the construction of a major facility such as a semiconductor fab. During such a project’s planning stages, the project team may find it useful to compile a materials procurement and contractor coordination matrix. This matrix records the required base build materials as well as more complex fab systems and it is useful as a procurement coordination tool. This type of tool can be used to document the availability and recommended source of all project materials before procurement actually begins and coordinate responsibility for the installation of each individual material. As globalization of advanced technology advances, it shouldn’t be assumed that certain specialized materials or systems aren’t available locally in a given project location. Owners may be surprised to find how many materials and systems may be available at an equivalent cost and quality from local suppliers.

37.4.3 Estimating and Cost Control The unusually high levels of complexity and capital commitment that typify semiconductor projects make them particularly susceptible to missed targets for cost and schedule. Compounding the complexity issue is the routine requirement that these projects be performed on a fast track basis to meet the aggressive “time to market” windows of opportunity that drive owner decisions to expand their operations. It is vital that semiconductor project estimators maintain close relationships with their project teams and vendors to stay abreast of any changes in project scope and field costs. Industry databases are available to detail materials, formulas, assemblies, and productivity and conversion factors unique to the industry. An effective cost-estimating method organizes estimates in chronological accordance with the sequence of a project’s contracting and construction. Original estimates developed in the early stages of design establish a baseline for the control of construction costs as the project is being engineered. The initial construction cost model can then be refined through successively more detailed estimates and by corresponding changes to design criteria modifications during the construction document phase. In addition, value engineering ideas, as they are presented and approved, can be included in updated estimates. This approach can also provide a rapid “what if” analysis when new ideas for changes are being considered. The Association for the Advancement of Cost Engineering (AACE, International) describes the five classes of estimates as follows: • Class 5 estimates: These estimates are often termed “rough order of magnitude” estimates. They are generally prepared based on very limited information, and subsequently have wide accuracy ranges. (Expected level of accuracy 25 percent to +40 percent.) • Class 4 estimates: These estimates are often termed “budget estimates” and are used for feasibility or predesign studies. They typically form the initial control estimate against which all actual costs and resources will be monitored, when engineering is about 15 percent complete. (Expected level of accuracy 15 percent to +30 percent.) • Class 3 estimates: These estimates are generally prepared to form the basis for budget authorization, appropriation, and/or funding. As such, they typically form the initial control estimate against

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.22

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.22

FAB YIELD, OPERATIONS, AND FACILITIES

which all actual costs and resources will be monitored, when engineering is near 40 percent complete. (Expected level of accuracy 10 percent to +15 percent.) • Class 1 and 2 estimates: These estimates are typically used for comparison to subcontractor bids and owner check estimates. They are often referred to as the current control estimate and become the new baseline for cost/schedule control of the project. Engineering is typically between 70 percent to 90 percent complete at this point. (Expected level of accuracy 3 percent to +15 percent.) It is crucial that realistic construction budgets be developed as early as possible in the design phases of a project. It is equally important that owners achieve consensus about what is included in a project’s budget and that the budget accurately represents the scope of work discussed during the predesign phase. As the project progresses into the schematic design phase, the entire project team must monitor changes to the project scope or criteria. Changes to the project scope or criteria must be quickly analyzed for impacts to the budgeted cost or schedule and reported to the project team. Decisions can be made at that time as to whether to incorporate individual changes into the formalized project scope. This process, often called cost trending, is an effective cost control method to track and report changes that can impact the project cost, scope, or schedule. Cost trending will assist in identifying both “scope creep” and value engineering opportunities and provide an opportunity to control cost impacts throughout the duration of the project. A formal change management process must be implemented to control “scope creep” and “cost creep.” Changes that impact scope, schedule, or cost must require approval of the project management team before being implemented. When comparing approaches to cost control, it is important to note the difference between constructibility and value engineering. Constructibility correlates the practicality of a facility’s design to the reality of construction processes in the field. Constructibility analysis should help reveal inconsistencies between the conceptualized design and the feasibility of actually executing that design. The spirit of value engineering is to apply ingenuity to achieve design functionality at a reducing project cost. Sometimes the term “value engineering” is inappropriately applied to the simple cheapening of construction materials or practices as a shortcut to achieving cost reductions. This is an unfortunate misuse of the value engineering ideal, which can ultimately penalize the owner with a lower quality end product. 37.4.4 Process Equipment Installation Engineers and architects are accustomed to beginning their design processes from the ground up. In the case of tool installation, however, a reverse process is preferable; a program-level scheduling approach, integrating design and construction that works backwards from the intended performance requirements of the tools. Only total design/construction integration can anticipate all of the needs that must be met to deliver tool installation projects on schedule and with quality. For example, it doesn’t benefit an owner to have tools installed and hooked up long before test and assembly resources are in place. Integration between a tool installation project’s designers and constructors can help avoid wasteful sequencing of project activities. Multiple skill sets are needed on tool installation project teams in order to understand the technology basis for the specific type of products being produced in a given fab and the corresponding technology basis for the tools being installed. Owners and their tool installation teams must also anticipate future variations of products to be produced within a given fab, so that layouts can accommodate those future applications. As an example, a fab anticipating large and heavy 300 mm tools needs to offer sufficient turn radii at the corners of move-in corridors, sufficient carrying capacity of freight elevators, and adequate strength of flooring systems to bear the weight of the numerous tools of this kind that the facility must house. Tool installation projects benefit from a database of simple, succinct, standards-driven design details that are tied to schematic-level design documents so that contractors don’t have to spend excessive time interpreting nonessential information. Utility connection databases are available to provide guidance for activities related to the connection of tools to utilities. Such databases also help provide long-term management of connected loads to the distribution system for balancing purposes. It is also valuable for tool installation teams to understand SEMI standards that apply to tool installation and integrate those standards into the procurement specifications and hookup design standards being used. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.23

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.23

Critical factors to facilitate smooth tool installation projects include maintaining schedule flexibility to deal with unpredictable equipment manufacturing issues (both delays and accelerations), anticipation of long lead item scheduling, material availability/allocations, and the orderly sequencing of trade labor within the construction zone. In an ideal project, all of these factors should combine to result in a series of smoothly integrated activities that seamlessly blend design, construction, vendor startup, and tool qualification. 37.4.5 The Design/Build Option The design/build approach consolidates design and construction activities under one contract that can offer the advantage of creating a single point of responsibility for all project activities. The design/build contractor may perform construction work using direct-hire labor and/or subcontracting to trade contractors. Design/build is not a preferred approach everywhere. Understanding where to apply this approach is as important as knowing how to apply it. In the United States for example, design/build has not yet been embraced to the degree it has been in Asia and Europe. The best design/build approaches involve the owner as an equal partner early in the design process. This allows the owner’s requirements and preferences to be incorporated early on, as the project is being defined. The approach also helps resolve budget and scope options more quickly so that the defined project satisfies the client’s business objectives. If a design/build effort is to be successful from the standpoint of all participants, an atmosphere of mutual trust and responsibility must prevail from the beginning of the project through to the end. Making the owner a direct participant in the process is a good way to promote such team trust (see Fig. 37.10). In summary, the primary potential benefits of applying a design/build approach on semiconductor projects include the following: • • • •

Provides single point of responsibility Reduces risks to owner Provides maximum integration of design and construction project team members Can create more opportunities to achieve the lowest overall project cost

37.4.6 Turnkey Equipment Systems Beginning in the early 1990s, turnkey system delivery was recognized as an approach that could offer advantages in cost, speed of delivery, and consistency of product and performance quality for systems supporting the semiconductor industry. These systems have continued to advance to create a new era in design and construction delivery. Turnkey delivery has assumed greater prominence as the industry has migrated to “lower technology” international locations. Turnkey systems avoid the concerns experienced by owners who are relying on local suppliers to install advanced semiconductor manufacturing systems with which those suppliers may have little or no familiarity. Examples of wafer fab systems conducive to turnkey delivery include exhaust abatement systems providing rapid startup efficiency and superior performance while providing optimal flexibility, reliability, portability, and expandability. Another example is ultrapure water systems that arrive on site as skid-mounted packages. The focus in today’s fabs on automation makes automation systems another logical candidate for turnkey delivery. Such systems are prepackaged and tested to provide the benefit of near-immediate performance following delivery. Even though turnkey systems are by nature self-contained, they are not entirely trouble-free. Owners selecting turnkey systems need to make sure that those systems will be installed by skilled personnel on the project site who have a comprehensive understanding of the technology involved. 37.4.7 Quality Assurance There are many approaches to maintaining quality on semiconductor projects, but all should include ongoing and systematic analysis of the work being performed and the means to learn from mistakes and adjust methodologies to promote continuous improvement of project performance. As an adjunct Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.24

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.24

FAB YIELD, OPERATIONS, AND FACILITIES

Owner

Design/Build firm

Site civil landscaping

Design team

Architectural structural

Local architect

Mechanical process & controls Local civil Electrical Local MEP

Special systems LSS, telecom

Geotechnical consultant

Long lead purchases Contractual relationship FIGURE 37.10

Example of a design/build project team organization.

to scheduled reviews, periodic over-the-shoulder reviews by designated reviewers, including owner representatives, are an effective means of promoting quality as the work progresses. There should be continuous monitoring and implementation of “lessons learned” to help keep the focus on quality fresh. Project self-evaluations at the end of each phase can be performed to identify improvements that can be implemented in the next phase. Post-project evaluations, often including the owner, document suggestions and successful improvements developed by the team. Some additional approaches and tools used to monitor the success of quality include: • Documentation of all required quality reviews and validation of the adjudication of all comments and suggestions. Ideally the review and adjudication process can be extended to owners at every major project milestone. • Project audits that assess conformance to baseline procedures and help the project team efficiently meet its commitments within contractual requirements. • Active tracking of submittals and requests for information from contractors and vendors to assure a prompt and timely response. • Tracking of contractors’ requests for clarification and change orders.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.25

PLAN, DESIGN, AND CONSTRUCTION OF A FAB PLAN, DESIGN, AND CONSTRUCTION OF A FAB

37.25

• Definition of quality standards (i.e., what is to be measured) as part of the contract documents and the project’s quality assurance program. • Assignment of design staff to the construction team to provide on-site interpretation of documents and to expedite submittal reviews and response to requests for deviations. A variety of tools and data can be incorporated into the quality evaluation process: • Factory inspections and acceptance tests can expedite systems delivery and installation. • Progress reports and deficiency notices can reduce inappropriate deviations from the intent of the designs. • Quality assurance calibration and test forms can be used to validate the quality of each installation and its compliance with the intent of the design. • Standard system acceptance forms requiring owner, contractor, and designer approvals bring consistency and consensus to a project team’s collective understanding of quality standards definitions on a given project. • Vendor/contractor “report cards” can be used to measure performance against mutually agreed to standards. On international projects, quality can be enhanced by providing more details on drawings than would normally be expected. On project sites where language, technology, or culture barriers are a factor, mockups of construction scenarios can be used to familiarize and train local workers in the proper performance of construction practices or the assembly of unfamiliar system components under the supervision of quality specialists. An example is a mockup of a concrete waffle slab floor that was repeatedly and successfully used to train workers on the site of a new semiconductor plant being built in China (see Fig. 37.11). In such situations it is always important to work in a manner that accords respect and cultivates a sense of partnership with local workers on the project team. 37.4.8 Safety The trend in the semiconductor industry has been to design fabs not only for efficient production of products, but also for long-term maintainability. Safety in semiconductor facilities should be similarly

FIGURE 37.11 Example of a mockup used to train workers in the construction of a waffle slab floor for a semiconductor plant in China.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH37.qxd

04/04/2005

21:16

Page 37.26

PLAN, DESIGN, AND CONSTRUCTION OF A FAB 37.26

FAB YIELD, OPERATIONS, AND FACILITIES

regarded. Safety is a priority that should not be project-specific, but rather a goal to be met throughout a facility’s life cycle. Strong safety performance also carries financial benefits to owners in the form of reduced insurance and litigation costs. Basic safety requirements in construction projects include: • Site-specific program development and implementation. • Contractor/subcontractor controls including prequalification, program submittal and review, injury/illness reporting, and work site appraisals. • Training and enforcement for project management, supervisory and support personnel, and downstream contractors in project-specific and regulatory compliance requirements as well as client and company standards. A recent innovation that is an outgrowth of semiconductor fab design and construction is the concept of life cycle safety. This approach has worked effectively to indoctrinate project teams with the philosophy that safety is more than a compilation of favorable statistics during construction; it is a set of values under which safety is designed into every building component. Typical approaches to safety rely on managing risk as designs are issued for construction. Life cycle safety is different in that it anticipates potential risks prior to construction and then finds ways to limit those risks through the design process. The process calls for a continuous cycle of capturing and addressing safetyrelated issues as the design process proceeds. Key principles of the life cycle safety strategies include the belief that actively incorporating safety into a project does not have to increase that project’s cost. The standard approach to safety is to impose it through the use of documentation tools such as site safety appraisals, ergonomic checklists, and safety incident reports. While such tools are effective, an approach such as life cycle safety demonstrates that safety is best encouraged when it is promoted as an integral and positive part of a project’s culture.

37.5 CONCLUSIONS In the last 30 years, the semiconductor industry has made remarkable strides in the improvement of its manufacturing technologies. The evolution to 300 mm production introduced a new set of production challenges, each of which has been confronted and controlled, if not solved outright. With no more than a brief pause to catch its breath, the industry dove into a new set of tests related to the production of nano-level integrated circuits. Regardless of what new technologies may emerge as the semiconductor industry continues to evolve, the fundamentals of sound planning, design, and construction will retain their perennial roles as the prerequisites for success.

ACKNOWLEDGMENTS Dick Sheehy, Jack Payne, Michael O’Halloran, Bill Headley, Jon Henderson, Dennis Grant, John Elmore, Forrest Gist, Samir Mokashi, Pat McCluskey, Rod McLeod, Tim Kuhlman, Mark Varon, Paul Turner, Steve Lewis.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 38

CLEANROOM DESIGN AND CONSTRUCTION Richard V. Pavlotsky Pavlotsky and Associates Danville, California

Stephen C. Beck LeChase Holley, New York

38.1 INTRODUCTION Today’s manufacturing cleanroom is a complex organism whose purpose is to both support and protect manufacturing processes and personnel. Every cleanroom comprises walls, ceilings, floors, and air systems. For the purpose of this chapter, the cleanroom will be considered to be the classic cleanroom with central plant heating, ventilation, and air-conditioning (HVAC), exhaust systems, utilities, and so on. When developing an overall manufacturing strategy, the cleanroom should be considered as a process element. Just as each manufacturing process associated with high-tech manufacturing shall be studied and analyzed in depth in order to optimize its function for producing the finished product, the cleanroom shall be studied and analyzed for optimal support of the manufacturing process. The intent of this chapter is to provide an overview of the issues regarding functionality of the cleanroom as it relates to high-tech manufacturing. This chapter addresses cleanroom standards, types of cleanroom, airflow patterns, cleanroom environmental conditional requirements, process contamination control, vibration and noise control, magnetic and electromagnetic flux (MEF) and electrostatic charge (ESC), life safety, and cleanroom economics. It concludes with practical problems encountered while designing and their solutions as well as constructing a state-of-the-art cleanroom.

38.2 CLEANROOM STANDARDS, CLASSIFICATIONS, AND CERTIFICATION The reference standards guiding cleanroom design, construction, and certifications currently include FED-STD 209E (English based) and ISO standard 14644 (metric based) (see Tables 38.1 to 38.4).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

38.1

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.2

CLEANROOM DESIGN AND CONSTRUCTION 38.2

FAB YIELD, OPERATIONS, AND FACILITIES

TABLE 38.1 Cleanroom Standards Comparative Analysis U.S. Federal Standard 209E IP

IS

1 10 100 1,000 10,000 100,000

M1 M1.5 M2 M2.5 M3 M3.5 M4 M4.5 M5 M5.5 M6 M6.5 M7

EU GMP guide* At rest

In operation

ISO Standard 14644–1

0.5 µm/ft3

ISO-1 ISO-2

0 4 10 35 100 352 1,000 3,520 10,000 35,200 100,000 352,000 1,000,000 3,520,000 10,000,000 35,200,000

ISO-3 ISO-4 A-B

A

ISO-5 ISO-6

C

B

ISO-7

D

C

ISO-8

D

ISO-9

0.3 µm/ft3

0.1 µm/ft3 10 100

1

1,000

10

10,000

100

100,000

1,000

1,000,000

10,000 100,000

*European Union Good Manufacturing Practice A = At Class 100, At Rest, maximum allowed 3520 particles/ft3 @0.5 µm.

TABLE 38.2 Air Cleanliness Classification: U.S. Federal Standard 209E Measured particle size µm per ft3 Class 0.1 1 10 100 1,000 10,000 100,000

0.1

0.2

0.3

0.5

5

1 35 350 NA NA NA NA

NA 7.5 75 750 NA NA NA

NA 3 30 300 NA NA NA

NA 1 10 100 1,000 10,000 100,000

NA NA NA NA 7 70 700

TABLE 38.3 Typical Cleanroom Air Velocities: IES-RP-CC012 Cleanroom classification

Airflow type

Airflow velocity (fpm)

Air changes per hour

0.1 1 10 100 1,000 10,000 100,000

Unidirectional Unidirectional Unidirectional Uni/nonunidirectional Nonunidirectional Nonunidirectional Nonunidirectional

60–100 60–90 50–90 40–80 25–40 10–15 1–8

360–600 360–540 300–540 240–480 150–240 60–90 5–48

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Class M3.5

Class M4.5

Class M5.5

Class M6.5

ISO-6 Particle counts ≥ 0.1 µm–1,00,000 ≥ 0.5 µm–35,200

ISO-7 Particle counts ≥ 0.5 µm–352,000

ISO-8 Particle counts ≥ 0.5 µm–3,520,000

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. Class 100,000 Particle counts ≥ 0.1 µm–3,450,000 ≥ 0.5 µm–100,000

15%

30%

40%

Class 1000 Particle counts ≥ 0.1 µm–34,500 ≥ 0.5 µm–1,000 Class 10,000 Particle counts ≥ 0.1 µm–345,000 ≥ 0.5 µm–10,000

75%

Class 100 Particle counts ≥ 0.1 µm–3450 ≥ 0.5 µm–100

80%

Class 100 Particle counts ≥ 0.1 µm–991 ≥ 0.5 µm–28.3

Class M3

ISO-5 Particle counts ≥ 0.1 µm–100,000 ≥ 0.5 µm–3520

100%

100%

Class 10 Particle counts ≥ 0.1 µm–99.1 ≥ 0.5 µm–2.83

Class M2

Class 10 Particle counts ≥ 0.1 µm–345 ≥ 0.5 µm–10

100%

Class 1 Particle counts ≥ 0.1 µm–35 ≥ 0.5 µm–1

Class M1.5

Suggested filter type

HEPA filters providing efficiency of 99.99% at 0.3–0.5 µm.

HEPA filters providing efficiency of 99.99% at 0.3–0.5 µm.

HEPA filters providing efficiency of 99.999% at 0.12 µm.

15 to 20 fpm (0.08 to 0.10 m/sec)

20 to 30 fpm (0.10 to 0.15 m/sec)

30 to 50 fpm (0.15 to 0.25 m/sec)

50 to 70 fpm (0.26 to 0.36 m/sec)

50 to 70 fpm (0.26 to 0.36 m/sec)

HEPA filters providing efficiency of 99.999% at 0.12 µm. HEPA filters providing efficiency of 99.999% at 0.12 µm.

70 to 80 fpm (0.36 to 0.41 m/sec)

70 to 80 fpm (0.36 to 0.41 m/sec)

75 to 90 fpm (0.38 to 0.46 m/sec)

75 to 90 fpm (0.38 to 0.46 m/sec)

ULPA filters providing efficiency of 99.99995% at 0.12 µm.

ULPA filters providing efficiency of 99.99995% at 0.12 µm.

ULPA filters providing efficiency of 99.99995% at 0.12 µm.

ULPA filters providing efficiency of 99.99995% at 0.12 µm.

Suggested minimum air, velocity @ ceiling level

36 to 100

60 to 100

180 to 300

300 to 480

300 to 480

420 to 600

420 to 600

450 to 640

500 to 640

Suggested minimum cleanroom air changes/hour

21:17

Class M2.5

100%

Suggested minimum ceiling coverage

Class 1 Particle counts ≥ 0.1 µm–9.9 ≥ 0.5 µm–0.3

Federal Standard 209E (English) particles/ft3

Class M1

FED-STD 209E (SI)

04/04/2005

ISO-4 Particle counts ≥ 0.1 µm–10,000 ≥ 0.5 µm–352

ISO-3 Particle counts ≥ 0.1 µm–1000 ≥ 0.5 µm–35

ISO 14644-1 particles/m3

TABLE 38.4 Cleanroom HVAC Requirements: Recommended to Meet and Exceed FED-STD 209E, FED-STD 209, Class 1 VLF, and ISO Standard 14644-1

Geng(SMH)_CH38.qxd Page 38.3

CLEANROOM DESIGN AND CONSTRUCTION

38.3

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.4

CLEANROOM DESIGN AND CONSTRUCTION 38.4

FAB YIELD, OPERATIONS, AND FACILITIES

38.2.1 Standards and Classifications FED-STD 209E establishes standard classes of air cleanliness for airborne particle levels and testing and analysis methodology for verifying and monitoring air cleanliness. It also addresses other factors to the extent that they affect the control of airborne particulate contamination. ISO (International Standards Organization) charged IEST (Institute of Environmental Science and Testing) to develop and maintain an international standard for cleanrooms and contamination controlled environments. The ISO Standard 14644 addresses a broader basis (including design considerations) than FED-STD 209E. ISO 14644 consists of five parts that include: Part 1—Classification of Air Cleanliness Part 2—Specification for Testing and Measurement Part 3—Metrology and Test Methods Part 4—Design and Construction Part 5—Cleanroom Operations To achieve the desired cleanroom performance the requirements of both standards shall be evaluated. Definitions of cleanroom standards are as follows: Federal Standard 209E—“A room in which the concentration of airborne particles is controlled to meet a specified airborne particulate class.” ISO Standard 14644 and British Standard 5295—“A room with control of particulate contamination, constructed and used in such a way as to minimize the introduction, generation, and retention of particles inside the room and in which temperature, humidity, and pressure shall be controlled as is necessary.” 38.2.2 Certifications Certifications of the cleanroom during construction execution, including process equipment (tools) installation, typically occur at three stages: “as-built,” “at-rest,” and “operational.” 1. “As-built” certification occurs after the installation of the terminal filters [high-efficiency particulate air (HEPA) or ultra-low penetration air (ULPA)] with all ventilation systems fully operational and balanced. Typically three tests are conducted during this certification: cleanliness classification, terminal filter integrity (air leakage from the actual filter due to damage or manufacturing issues and leakage at the grid/plenum filter seal), and air velocity/volume. This initial certification verifies that the cleanroom is in an acceptable condition for the process tools and provides valuable data that will be used to “fine tune” the ventilation systems. 2. “At-rest” certification occurs after the installation of the process equipment (tools), prior to their commissioning and qualifications, and without any personnel present in the cleanroom. The purpose of this certification is to determine the effect of the process tools on the ventilation systems and to ensure that the installation of the process tools has not had a negative effect on the cleanliness of the cleanroom. Typically, cleanliness classification is the test performed during this certification (provided that it was preceded by an “at–rest” certification). 3. “Operational” certification occurs after the process equipment (tools) have been commissioned and with the normal operating quantity of personnel in the cleanroom. The “operational” certification is the definitive measurement of the cleanroom functionality because it simulates actual operational conditions and tests for all critical functions. Typical tests include cleanliness classification, pressurization, airflow parallelism, temperature, and humidity uniformity. Other tests may be incorporated into the “operational” certification if desired by the client or if required to verify a function that has a particular potential impact on the process. One of the key reasons for a “staged or phased” approach to certification is that this process allows for easier troubleshooting by isolating the facility from the influence of process tools and personnel.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.5

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.5

Supply air

Turbulent airflow Filters Unidirectional airflow Cleanroom

Return air

FIGURE 38.1 Associates.)

Turbulent airflow

Ballroom concept unidirectional airflow. (Courtesy of Pavlotsky and

38.3 TYPES OF CLEANROOM Today’s microelectronics facility cleanroom is a complex system whose purpose is to support and protect manufacturing processes and personnel. Cleanrooms generally constructed the following basic conceptual configurations: 1. Ballroom (see Figs. 38.1 and 38.2): Ballrooms are typically open areas with ancillary functions at the perimeter. 2. Bay and chase (see Figs. 38.3 and 38.4): Bay and chase cleanrooms are typically configured as clean “fingers” with supporting functions behind the chase’s walls.

Supply air

Turbulent airflow Filters Turbulent airflow Cleanroom

Equipment Return air

FIGURE 38.2

Turbulent airflow

Ballroom concept turbulent airflow. (Courtesy of Pavlotsky and Associates.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.6

CLEANROOM DESIGN AND CONSTRUCTION 38.6

FAB YIELD, OPERATIONS, AND FACILITIES

Return air

Supply air

Turbulent airflow Cleanroom chase Cleanroom bay

FIGURE 38.3

Unidirectional airflow

Bay and chase concept unidirectional airflow. (Courtesy of Pavlotsky and Associates.)

3. Minienvironments (see Fig. 38.5): A greater level of cleanliness in a localized area to effectively and economically support manufacturing functions may be achieved with minienvironments. Minienvironments offer significant savings in both the initial and life-cycle cost of the cleanroom. Minienvironments are commonly constructed of a framing system (internal of the cleanroom structure) and equipped with fan-filter units (FFUs) and a sidewall enclosure. The minienvironment isolates the equipment and process from the influence of surrounding conditions and particles. The FFUs take preconditioned and filtered air directly from the cleanroom, filter the air to a higher level of cleanliness, and distribute it appropriately to achieve a desired contamination control strategy. 4. Combination of ballroom with installed minienvironments: Most often, current design practice in cleanrooms uses a mix of these configurations in order to address the specific process requirements, economics, and space limitations. The objective of investing in a construction of a cleanroom is to achieve certifiable cleanliness in an optimized space with the most economical solution for a given manufacturing process type and known constraints.

Return air

Filters Cleanroom chase Equipment

FIGURE 38.4 Associates.)

Supply air

Turbulent airflow Cleanroom bay

Turbulent airflow

Bay and chase concept turbulent airflow. (Courtesy of Pavlotsky and

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.7

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

Return air

Cleanroom chase

38.7

Supply air

Cleanroom bay

Fan-filters Unidirectional flow minienvironment Work surface

FIGURE 38.5 Bay and chase concept with minienvironment. (Courtesy of Pavlotsky and Associates.)

38.4 AIRFLOW LAYOUTS AND PATTERNS The airflow in cleanrooms may be vertical with air supply coming from the ceiling and return air being removed through the openings in the floor, vertical with air supply coming from the ceiling and return air being removed through the openings in the sidewalls, horizontal with air supply coming from the wall and return air being removed through the openings in the opposite wall, or a combination of high and low returns. 38.4.1 Unidirectional Airflow When the air leaves the face of a clean HEPA filter, it travels at a uniform velocity, which allows the flow to be almost unidirectional. The unidirectional airflow (see Figs. 38.3 and 38.6 ) limits the dispersion of contaminants from internally generated sources. In the unidirectional airflow cleanroom the particles or molecules of contamination substance move along the airflow pass and exit boundaries of the clean process area. The unidirectional airflow cleanroom is easiest to model with computational fluid dynamics (CFD) software for particles’ travel and control. If unidirectional airflow is only necessary over small, sensitive areas of the cleanroom, it may be handled with minienvironments. Sources of contamination may be localized with glove boxes, filtration modules, and the like. The majority of cleanrooms designed for total unidirectional flow can achieve unidirectional flow only at rest, without workers, equipment, and room exhausts. The choice of vertical or horizontal airflow depends on the room configuration and equipment layout. In many facilities, turbulent airflow with properly engineered exhaust and return air locations works fine for contamination removal. Raised floors were developed to help the distribution of electrical wires, communication cables, utilities, piping, and so on between tools, equipment, and utility sources. Subsequently, for economy purposes, they were utilized for returning air from the bays to the chases in a bay and chase cleanroom configuration. In a pure unidirectional cleanroom the particles are expected to flow from the working space toward the holes in the floor. Many successful Class 10 and Class 100 ballrooms operate with low-wall returns, without raised floors, and the cleanroom airflow is designed to be turbulent. Another option in product contamination control is to isolate an ultraclean area with a thin air jet moving at a speed of 500 to 800 fpm. It functions exactly the same way as the plastic curtain. Several modern cleanrooms were designed, built, and operated with ultraclean areas cleaner than class ISO-4 inside the general turbulent airflow cleanroom class ISO-7. 38.4.2 Turbulent Airflow When the air strikes a solid object, it changes direction. When this happens, the laminar flow may be disrupted, causing turbulent currents in the air. The main sources of air turbulence in the cleanroom

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.8

CLEANROOM DESIGN AND CONSTRUCTION 38.8

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 38.6

CFD model for unidirectional airflow with low side air return.

are people and equipment. When a person walks in a unidirectional flow air stream the air gets pushed in front of the body and a partial vacuum is created behind. The surrounding unidirectional air is thus affected. This same effect is caused by moving equipment parts in the vicinity of an area of laminar unidirectional airflow. Stray particulates may accumulate in the turbulent air pockets and may eventually affect the products being manufactured. For areas where extreme cleanliness is required, it is important to keep these areas as free as possible of people and other causes of air movement. The effects of obstructions to unidirectional airflow are shown in Figs. 38.2 and 38.4. It is important to realize that pure unidirectional airflow may exist only few feet from the air outlets (HEPA filters). In nonisothermal environment the airflow is affected by convection streams, ricochets from solid objects air streams, stray currents, and the like. Other elements of cleanroom performance are sweep, the rate of room air changes, and the percentage of particles removal per set time. These elements are dependent on many factors such as the air temperature gradient, cleanroom shape and configuration, location of solid and moving objects on the floor, and inlet and outlet location. Sweep is the most overlooked function in a cleanroom or in the design process equipment. Great emphasis is placed on particle counts with little attention to sweep. Sweep is an action of the airflow to capture contaminants from a surface and transport them away (return air) from the critical area of exposure. These captured contaminants are then removed

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.9

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.9

from the airflow by the action of the filters. One of the most important functions of the cleanroom system is to sweep the internally generated contamination from the area of susceptibility. It is imperative to maintain proper velocity and pattern of airflow around the product and process. Considering that turbulent airflow cleanroom is less expensive to construct and maintain and that the turbulent airflow cleanroom may have an advantage in room sweep and particles removal, the realistic approach may be to construct a turbulent flow ballroom with local unidirectional airflow minienvironments and barrier enclosures. The required level of cleanliness is continuously maintained by the cleanroom air-conditioning systems (supply, exhaust, and recirculation), cleanroom ionization and static electricity control systems, and cleanroom operational protocol.

38.5 AIR CHANGES The air distribution devices in cleanrooms (usually ceiling filters) are designed to provide a uniform “shower” of filtered clean air. The quantity of air supplied to the room brings to mind the analogy of a fire hydrant as opposed to an ordinary showerhead. American Federal Standard 209E, Japanese JIS B9920, and ISO 14644-1, entitled Cleanrooms and Associated Controlled Environments—Part 1: Classification of Air Cleanliness, provide guidelines for cleanroom parameters, classification, and testing, but do not tell you how to get there economically. This is because each process and, therefore, cleanroom requirements are different, and desired conditions may be reached utilizing different quantities of recirculating air. There are always at least five different “possible” designs to achieve the desired results. However, there is only one design that “fits” best. Finding the optimal and most economical solution for the project is a fundamental goal of the project concept for cleanroom air changes. As may be seen in Table 38.4, the air changes and quantity of recirculation vary significantly even for the given room class. The cleanroom Class M2, for example, may be achieved with 300 air changes and sometimes even 540 air changes may not be enough. The rate of room contamination and live-particles generation is one of the major factors in cleanroom air-quantity selection. The rate of particles removal from the room may be very important for one manufacturing process and may not have any effect on another. Other variables that may impact the quantity of recirculating air are room configuration, equipment location, equipment surface temperature, convective flux, type of the airflow (unidirectional over sensitive areas only or over the entire room), room operations and protocol, materials and chemicals used, and so on. The room may need to be certified at rest only, certified at working conditions, validated for the process, or current good manufacturing practice (CGMP) validated. Federal Standard 209E, set by the General Services Administration, suggests that air in a Class 100 cleanroom shall be at 90 cfm/ft2 or 90 fpm. However, it is possible to build a better than Class 100 rooms with lower air movement. In fact, it has been done with as low as 45 cfm/ft2.

38.6 ELEMENTS OF A CLEANROOM Regardless of configuration, cleanrooms consist of common elements required to support and protect the clean manufacturing process that is housed within the cleanroom. These elements include ceiling systems with HEPA filters, walls, floor systems, and the environmental conditioning systems that will be described in the following sections in detail. 38.6.1 Ceiling Systems Ceiling systems found in cleanrooms are the complex enclosure elements. The two most common systems are extruded aluminum grid with field-constructed plenum and modular prebuilt integrated

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.10

CLEANROOM DESIGN AND CONSTRUCTION 38.10

FAB YIELD, OPERATIONS, AND FACILITIES

plenum with grid. Both of these systems serve as the mounting for terminal filtration (HEPA or ULPA) or FFUs and lighting. The ceiling system also may be supported from freestanding walls or columns or suspended from existing structure. The factors involved in the selection of the ceiling system are typically site-specific depending on required free span, available vertical volume, access, and load carrying requirements. 38.6.2 Wall Systems Wall systems for cleanrooms are most commonly of a premanufactured, modular design. They are constructed of extruded aluminum framing members and honeycombed aluminum panels. The finish is typically either an anodized or epoxy coat. These systems are commonly used because they do not generate particles, have very low outgassing characteristics and are easy to reconfigure. Such systems are well suited for the bulk heading of process tools and utilities connections. The drawbacks are initial costs and limited structural characteristics. Occasionally in less precise applications the “stick built” wall systems are used. These wall systems are constructed of metal studs and metal faced drywall finished with epoxy coating. While such systems may be constructed at a lower cost, they require a much more stringent construction protocol. The “stick built” wall systems offer good structural capabilities but are difficult to reconfigure without excessive particles generation and therefore have a negative impact on the quality of operational cleanroom. 38.6.3 Floor Systems Floor systems for cleanrooms most commonly are perforated wafer concrete panels over the subfab, raised stand floor panels or slabs on grade with side air grilles. Typically these systems are provided with electrostatic dissipating composition (ESD) or an ESD grade epoxy. A significant factor influencing the decision during the selection of floor systems is airflow management. Where unidirectional airflow and parallelism are critical factors, the raised panel floor system or perforated wafer concrete panels over the lower floor (subfab) provide superior performance. The disadvantage of raised floor systems is relatively high cost and limited structural capability. When unidirectional airflow is not a major concern the slab on grade with sidewall air returns may perform effectively and at significantly lower cost.

38.7 ENVIRONMENTAL CONDITIONAL REQUIREMENTS Environmental conditioning systems typically consist of recirculation and makeup air systems (temperature and humidity control of the cleanroom is accomplished via these systems), general exhaust, acids exhaust and scrubbing, solvents and violent organic compounds (VOC) exhaust and absorption, toxic gases exhaust and destruction. An emerging trend in cleanroom design is the use of airborne molecular contamination (AMC) control systems. These systems incorporate the cleaning of outside air used for ventilation and pressurization, removing VOC and fugitive emissions from the recirculation air system, and cleaning process emissions from the exhaust stream. AMC systems are typically classified by their chemical properties: acid, base, condensable, and dopants. SEMI Standard F-21-1102 offers a cleanroom classification system, based on their molecular contaminant levels rather than particulate levels. AMC can address concerns regarding personnel exposure to toxic and hazardous materials. AMC systems typically consist of specific filtration and monitoring and can provide an effective removal rate of as high as 90 percent. 38.7.1 Exhaust Systems Process exhaust systems typically are acid exhaust, solvents and VOC exhaust, toxic exhaust, heat exhaust, and general room exhaust. If ammonia is present in the exhaust air stream, some facilities prefer to run a separate ductwork and abatement for ammonia fumes. The most common abatement Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.11

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.11

for acid exhausts is a horizontal or vertical scrubber. Solvents and VOC exhausts require absorption, concentration, and removal of condensed solvents or on-site incineration. Toxic exhaust is usually abated by in-place or on-site high-temperature destruction. The abatement types should be carefully determined along with the quantities of required exhaust air streams. Good facility air management can help minimize quantities of exhaust air and therefore lower construction cost and energy waste during operation. It is important to maintain a balance between potential needs for increase in exhaust quantity and expansion and economical value of installing such provisions initially or in the future. Far too often, oversized, expensive, lined stainless steel or fiberglass-reinforced plastic (FRP) exhaust systems have been built considering future expansion in cleanrooms while other utilities and mechanical systems, makeup air and cooling for example, couldn’t support such an expansion. It is also common that acid exhaust systems have been built without consideration for future needs, where velocity in the ductwork exceeds 4000 fpm with added airflow and new ductwork branches. Such systems were difficult or impossible to balance and expensive to operate. 38.7.2 Makeup Air Systems Typically, the makeup air handling units (primary AHUs) provide the necessary makeup air for the recirculating air handling units (secondary AHUs) (see Figs. 38.7 and 38.8). The makeup air AHUs consist of draw through centrifugal, vane axial or plug fans with filters, hot water coils for preheat and reheat, chilled water coils for cooling and dehumidification, and steam or adiabatic humidifiers. In addition, there are many available add-ons and variations, including static air mixers, steam preheat coils, ultrasonic humidifiers, brine, DX or glycol sub cooling coils for dehumidification, VOC absorption filters, sound attenuators, and variable frequency drives (VFD). The makeup AHUs typically discharge into a common header with ductwork laterals balanced to supply the required makeup air to the recirculation AHUs. Air measuring stations shall be installed in the primary air and the secondary air supply main ducts to modulate the supply fans VFD drives or inlet vane dampers to maintain constant airflow. Magnahelic gauges shall monitor the loading of the HEPA filters, bag filters, and prefilters located at each AHU. In situations where ceiling fan-filters are provided, the makeup air shall be evenly distributed in the space above fan-filters. Air from the makeup AHUs enters cleanroom through recirculation AHUs. 38.7.3 Recirculation Air Systems Each recirculation air handling unit typically consists of an energy efficient centrifugal fan with filters and sensible (dry) cooling coil (see Figs. 38.7 and 38.8). Add-ons and variations are available, including reheat coils for zone temperature control, steam or ultrasonic humidifier for zone humidity control and constant volume control boxes. Whisper-Air and Compac Space, or equivalent, fan systems used for this application proved to be cost saving and energy conscientious selections. Multiple recirculation AHUs discharge into supply ducts feeding the cleanroom through ULPA or HEPA filters, which typically cover 100 percent of the ceiling in the Class 10 and Class 1 areas. This vertical unidirectional flow passes down through the room, through the perforated raised floor tile into the return air space under the floor, and then up through vertical return air shafts, which are open to the ceiling, return air plenum. The air then reenters the recirculating AHU and the cycle repeats. In the case of ceiling fan-filters the sensible cooling may be provided by water or DX cooled fancoil units located in the ceiling space above fan-filters. 38.7.4 Temperature Control Temperature and humidity variations cause process equipment misalignment, impact the repeatability of the developed process, and eventually reduce the useful output of the product and increase the quantity of waste. It is understandable that the goal is the most stringent cleanroom temperature requirements, but the cost often dictates otherwise. Often, in an attempt to lower the construction cost the engineer is asked to design a precise temperature control area within a large space where the temperature is allowed to swing between +/−4 and 6°F (i.e., the warehouse area with roll-up doors). Without hard walls and airlocks it may be a Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.12

CLEANROOM DESIGN AND CONSTRUCTION 38.12

FAB YIELD, OPERATIONS, AND FACILITIES

Coils and prefilters

Makeup air handler

Final filters Humidifier

100% outside air

Makeup air to other zones

Recirculation air handler

Reheat coil (optional)

Interstitial level Distribution plenum HEPA or ULPA filters Service chase Cleanroom

Production tools

Cleanroom

Unidirectional airflow

Unidirectional airflow Access floor Subfab level

Heat exhaust FIGURE 38.7 Associates.)

Corrosive exhaust

V.O.C. exhaust

Air conditioning systems for unidirectional airflow cleanroom. (Courtesy of Pavlotsky and

very expensive alternative with virtually uncontrollable variations of humidity. Therefore, the quality of the said cleanroom is substandard and the cost remains relatively high. Common sense tells that cascading levels of cleanliness, temperature, humidity, and pressure are easier to achieve and maintain. The allowable tolerance should be carefully evaluated. Mechanical equipment and control systems for cleanrooms with stringent temperature control requirements (+/−0.1°F) may cost 20 to 50 percent more than a cleanroom with typical requirements (68 to 72°F) and set point (70 to +/−2.0°F). A zone thermostat typically controls the design temperature in each cleanroom zone. It actuates the duct-mounted zone reheat or recool coil to satisfy the room sensible load conditions. In the case of fancoil units the zone thermostat controls the temperature of air, leaving the fan-coil unit coils in the zone. 38.7.5 Humidity Control The design relative humidity for each cleanroom is controlled by a zone humidistat. If there is a high relative humidity in the room, the humidistat lowers the cooling coil discharge air temperature to provide

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

21:17

Page 38.13

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

Preheat coil

Cooling coil

Cooling coil

HW

CHW

CHW

38.13

Sound attenuator Sound attenuator

HEPA filters Outside air 30% 9.99%

Charcoal filters if necessary

UV light

Sound attenuator S.A. fan

Sound attenuator

Geng(SMH)_CH38.qxd

Preheat coil

HEPA filters

HW

Clean steam humidifier

99.9995%

Makeup air Clean-pack Cooling coil Prefilter Return

c

Supply air

Air damper

c

Plug fan

FIGURE 38.8 Make-up air unit (top). Recirculating air unit (bottom). (Courtesy of Pavlotsky and Associates.)

more dehumidification. At the same time, the reheat coil provides heat to maintain the room temperature. If the relative humidity of any cleanroom falls below the design limit, the zone humidistat actuates the duct mounted zone humidifier. When precise humidity control is required it can typically be achieved with adiabatic humidification of makeup air in the air handler and by maintaining the cleanroom dew point. Local variation in humidity levels may be handled with ultrasonic humidifiers located in the ductwork plenum before the filtration terminals. The ultrasonic humidifiers for cleanrooms work well with RO/DI water quality and water resistivity near 3 to 5 mgohm. The design relative humidity for each cleanroom in that case is usually controlled by a zone humidistat. If the relative humidity falls below the design limit, the humidistat actuates the humidifier to increase the moisture content of the supply air. If there is a high relative humidity in the room, the humidistat lowers the makeup air handlers cooling coil discharge air dew point temperature to provide more dehumidification.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.14

CLEANROOM DESIGN AND CONSTRUCTION 38.14

FAB YIELD, OPERATIONS, AND FACILITIES

38.7.6 Air Pressure Differential Cleanroom pressurization is necessary to protect the cleanroom against contamination from adjacent areas, to control the flow of unwanted contaminants, to prevent cross-contamination between areas, and to help maintain temperature and humidity at required levels. Typical air pressure differential between cleanroom and reference corridor and other areas of the facility is maintained at 0.25 to 0.005 in w.g. The higher number is usually more applicable to pharmaceutical facilities with cascading air pressures between areas to avoid cross-contamination. Such areas normally require series of cascading airlocks between them with pharmaceutical doors that allow air to escape at a high velocity, therefore creating a pressure differential. A well-designed microelectronics cleanroom normally operates at 0.02 to 0.005 in w.g. with a semihermetic air lock at the cleanroom entrance. The cloth change and gowning rooms often serve as said airlocks. The presence of mechanical air showers at the entrance is more a question of facility culture and facility cleanroom protocol than a necessity. Many microelectronics and photolithography cleanrooms operate successfully with passive air pressure control and maintain only a minimum air velocity of 50 to 100 fpm over the entrance with the door fully open. Some biopharmaceutical facilities require an active differential pressure control and supplement air escaping through the door (at the time when the door is being opened) with makeup air automatically. Differential pressure monitors by Henry G. Dietz Co., Inc., may be utilized for this task. Monitors may be mounted outside the cleanroom with a small light emitting diode (LED) inside the cleanroom, having an audible alarm and two indicators to show when pressure is normal or abnormal. The device detects negative pressure in biocontainment areas common in biopharmaceuticals as well as the positive pressure common to electronic facilities. It has a digital differential pressure display with a resolution of 0.001 in w.g. and a pressure/vacuum range of 0.5 in w.g. Differential pressure is indicated by illuminated light emitting diodes (LEDs) and an audio alarm. Internal adjustable time delay prevents activation of the audible alarm by momentary door opening.

38.8 PROCESS CONTAMINATION CONTROL 38.8.1 Air Filtration Cleanroom air typically is filtered with terminal high-efficiency particulate air (terminal HEPA) filters providing efficiency of 99.99 percent at 0.3 to 0.5 µm, HEPA filters providing efficiency of 99.999 percent at 0.12 µm, or ULPA filters providing efficiency of 99.99995 percent at 0.12 µm. Other devices may also be required depending on cleanroom purpose, that is, HEPA filtration in recirculating and makeup air handlers, VOC absorption with charcoal type or similar synthetic filters, electrostatic filtration chambers, and so on. Fan-filters are no longer new to the cleanroom market, and if properly applied shall provide an excellent and economical solution for many high-level cleanrooms especially in buildings with ceiling height limitations. Applying higher-grade terminal filters should be economically justified and weighted against first cost and lower pressure drop of more expensive filter media. It is not always obvious, but often true, that higher-grade filters with lower pressure drops are more economical in the long run, through the life of the cleanroom. 38.8.2 Prevention Properly designed equipment and properly selected materials can minimize internally generated contamination. Uses of sliding surfaces and belts should be minimized or isolated from a process. Materials should be analyzed for shedding and outgassing. For example, perfluoroalkoxy (PFA) is orders of magnitude cleaner than polypro while Teflon is an order of magnitude cleaner than PFA. Typically aluminum is far less contaminating than steel. The selection of anodized aluminum over stainless steel may remove serious contamination from the process.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.15

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.15

38.8.3 Isolation Properly designed through the wall installations, flexible or hard shielding of contamination sources, utilization of a variety of system such as standard mechanical interface (SMIF), vacuum processing, nitrogen purged processing, isolation carriers, transport tunnels, hanging shields and robotics can dramatically reduce the contamination of the product or process. External isolation also includes isolation and consolidation of processes and the layout of equipment. For example, such processes as photolithography and ion implant shall be isolated from the rest of the manufacturing. The intent is to isolate the product from all internally induced contamination and crosscontamination. 38.8.4 Sweep Properly designed airflow and velocity shall insure the effective sweep. If the air velocity is too low, there will not be a particles removal effect; if the air velocity is too high an unexpected turbulence will result.

38.9 VIBRATION AND NOISE CONTROL The size and weight of equipment affects vibration transfer and control. Concrete “waffle” slabs under the cleanroom floor worked sufficiently well for keeping equipment vibration from transfer to other areas of production or to metrology tools. Waffle slabs remain rigid even if holes are drilled in the floor for piping and conduits access to the cleanroom. Because the strength of the floor is in the grid system, rearrangement is feasible. Additional holes can be punched in the floor without adversely affecting vibration considerations. All mechanical equipment should be isolated with springs, flexible connections, and isolated foundations to minimize the vibration effect. Quiet, energy-efficient fans and motors allow to maintain the desired noise criteria (NC) level in the cleanroom. The vibration and sound consultant should be a part of the team to verify mechanical and architectural concept for vibration and noise control. It could be very expensive to fix it later. Many potentially costly measures may be eliminated or replaced with more economical solutions if these factors were considered from the start of the project with architects, mechanical engineers, client, and consultants involved in the decision process.

38.10 MAGNETIC AND ELECTROMAGNETIC FLUX Magnetic flux proposed to be the flow of the background oceanic particles of the Galaxy. Galactic rotation is also proposed to be electromagnetic in nature. The word “flux” means flow and we may think of magnetic field lines as lines of some type of fluid flow through an imaginary surface. The magnetic field magnitude is like a rate of flow and its direction is the direction of flow. The magnetic flux is like total volume of flow through the surface. Better yet, we may think of magnetic flux as the number of field lines passing through the surface. At a given speed, this force is greatest when the particle moves perpendicular to the magnetic field and zero when the motion is parallel to the magnetic field. At the most basic level, magnetic forces are exerted on moving charges by other moving charges, just as electrostatic forces are exerted by electric charges on other electric charges, whether or not they are moving. It appears from comparative studies of planets that the Earth has a strong field because it rotates and has a molten metallic core. In theory, the field arises in internal electric currents that are induced by the Earth’s rotation and by circulation in its fluid core. Magnetic flux density has its own unit, the Tesla T. The typical value of the Earth’s field near its surface is about half of a gauss, which is about one 200,000th of a Tesla. Occupational safety and health requirements limit magnetic field strength in areas open to the public to the 5 G limit. Magnetic shielding of the cleanroom can be very expensive. For example, 4- to 5-mm thick shielding on the envelope of the cleanroom with magnetic (Fe-Si) steel, M15 type, may lower the strength of the magnetic

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.16

CLEANROOM DESIGN AND CONSTRUCTION 38.16

FAB YIELD, OPERATIONS, AND FACILITIES

flux from MRI equipment from 13 to 2.6 G. However, 14 mm of ordinary low-carbon steel shielding may not be sufficient. Current semiconductors, metrology, and communication laboratories require the strength of the magnetic flux in the area to be limited to 0.05 G or less.

38.11 ELECTROSTATIC CHARGE OF AIR AND SURFACES “Static electricity” effect is present when surfaces in contact are separated. If the charge that arises from differences between the surfaces cannot escape to Earth quickly enough, then it is trapped and the charge is spread out over the surface of a material—it is “static.” Retained electrostatic charge creates risks and causes problems in many areas of the industry. It can cause ignition of flammable gases and even shock personnel. It can make thin films and light fabrics cling, attract airborne dust and debris, damage electronic devices, and upset the operation of precision equipment. The hazard that static presents in the case of flammable gases, vapors, and powders relates both to the capacitively stored energy in relation to minimum ignition energies and to the breakdown voltage of the minimum gap from which an ignition will propagate. Typically, the minimum ignition energies of common hydrocarbon gas/air mixtures are 0.2 mJ with a few kilovolts of minimum breakdown voltages. With powders, minimum ignition energies start at a few millijoules. Shocks from electrostatic discharges become discernible around 1 mJ and are likely to be uncomfortable in the 10 to 100 mJ range. They will cause major muscular contraction above 1 J. Mechanical handling problems arise when electrostatic forces become comparable to gravitational or other constraining forces. This relates to the strength of local electric fields and, hence, on insulators to surface charge density. In general, electrostatic forces are weak, but dust will be attracted to surfaces at charge densities less than few millijoules multiplied by 10−7 /m2. Electrostatic charge will be generated on people by such normal activities as walking across carpets, getting up from chairs, rubbing clothing against surfaces, and the like. The levels of charge will be higher in low humidity environments and where artificial fibers are extensively used. Body potentials up to 15 kV may be expected. Electrostatic discharges will occur from charged fabrics, a charged body, and any metal objects held in the hand, and the like. These electrostatic discharges may involve high potentials and so may be able to jump several millimeters of air through gaps in equipment casings directly to internal circuitry. The discharges can involve currents up to several amps and involve frequency spectra extending up to several hundred megahertz—particularly where a metal conductor acts as the source of the discharge. Problems with the upset of microelectronic systems are also usually expressed in relation to a human body model discharge. System immunities of several kilovolts are likely to be needed (preferably over 15 kV for uncontrolled environments) because high potentials can readily be generated on personnel in normal working environments by movements across flooring and the like. To minimize risk and avoid potential problems it is necessary to ensure that static charge can dissipate more quickly than it is generated. For normal, manual handling and body motion activities this means the charge decay time needs to be 1/4 s or less. A new concept, relevant to risk control, is that if static charge experiences a high capacitance on a material then only low surface voltages will be observed and potential problems and harm will be prevented.

38.12 LIFE SAFETY Safety always shall be a major consideration in the design and operation of cleanrooms. Critical life safety systems and safety egress are required by codes and industry accepted practices. Major underwriters such as Factory Mutual Global (FMG) publish guidelines for materials to be used in the construction of cleanrooms and generally will not insure a cleanroom that has not designed, constructed, and operated per the recommended practices. Typical safety systems for cleanrooms include toxic gas monitoring (TGM), leakage sensors in the containment piping, waste systems, enhanced (early detection), fire alarms, and oxygen level monitoring. These systems provide levels of alarming ranging from basic visual and auditory to automatic dial out to emergency responders and digital storage of 365 × 24 × 7 information about all supporting life safety systems alarms and operations.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.17

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.17

38.13 COMPUTATIONAL FLUID DYNAMICS One of the most powerful tools available for determining the optimal ventilation (recirculation, make-up air, and exhaust) for the cleanroom is computational fluid dynamic modeling (CFD) or airflow modeling (see Figs. 38.9 and 38.6). The very essence of the cleanroom contamination control is defined by ventilation. Electrical energy necessary to support HVAC equipment to support the cleanroom function represents a significant portion of the energy used by the cleanroom. With the development of high-powered personal computers, CFD modeling can be used for even the smaller projects. The CFD modeling allows for better anticipation of design inadequacies so that they can be remedied before the start of construction, better ability to quickly and efficiently reveal areas of opportunity for improved performance in operation of the cleanroom, and ability to model various options for both planned and operating cleanrooms so that the most economical solutions can be pursued with a high degree of confidence. Unfortunately there are still too many cleanrooms being designed based on simplistic “rules of thumb.” With the cost of manufacturing facilities increasing by “double digit” figures with each tool generation, it is projected that a new 300-mm facility will cost over $1800/ft2. “Time is of the essence” regarding the design and construction of a clean manufacturing facility. Marketing analysis indicates that in a high-tech manufacturing, the first company to bring a new product (or an upgrade to an existing one) will maintain a 40 percent market share during the product’s life (providing that they maintain competitive pricing).

FIGURE 38.9

Computational fluid dynamic modeling.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.18

CLEANROOM DESIGN AND CONSTRUCTION 38.18

FAB YIELD, OPERATIONS, AND FACILITIES

As a consequence of the above, enormous pressure is placed on the project team to deliver the cleanroom on or ahead of schedule, therefore discovering problems at the late stage of the game during certification, validation, and commissioning and hoping that the problems may be solved by simply rebalancing the air systems is an expansive misconception.

38.14 CLEANROOM ECONOMICS A high-tech cleanroom design specification (Table 38.5) must result in a system that is capable of operating under conditions, which will yield a net profit. Since net profit equals total income minus all expenses, it is essential that the engineer designing the plant be aware of the various diverse types of costs involved in high-tech manufacturing. Capital must be allocated (invested) for direct plant expenses, such as raw materials, labor, and equipment and in addition to direct expenses, many other indirect expenses are incurred, and these must be included if a complete analysis of the total cost is to be obtained. NP = I − E where NP = net profit I = total income E = all expenses A significant capital investment is always required for any high-tech manufacturing process and determination of the necessary investment is an important part of a design project. The total investment for high-tech manufacturing process consists of fixed capital investment for manufacturing equipment and facilities plus working capital, which must be accessible to pay salaries, obtain raw materials, and pay for other items requiring direct cash expenditure. TI = FCI + WC where TI = total investment FCI = fixed-capital investment WC = working capital The handling of depreciation, interest, profits, and income taxes in the analyses must also receive consideration. There is a potential shortcoming in using past costs to estimate future expected cost TABLE 38.5 Generic Cleanroom ISO Class 3 Criteria Specifications 1. Air change rate 2. Airflow 3. Air filtration 4. Air handlers 5. Air pressure 6. Temperature 7. Humidity 8. Exhausts 9. Vibration and noise 10. Magnetic flux 11. Electrostatic charge 12. Energy 13. Form, Function 14. Particulate 15. Process piping Expected cost (mechanical)

600 times per hour Unidirectional Terminal (ULPA) filters 99.99995% efficiency at 0.12 µm Rooftop makeup AHUs, recirculating indoor units Pressure differential + 0.005" w.g. versus reference corridor 70°F +/−0.5°F, no more than 0.75°F variation in 4 h 45% RH +/−2%, no more than 3% variation in 4 h Scrubbed acid, abated solvents, general, and heat exhausts NC-50, < 300 µin/s peak to peak, 0–15 Hz 0.5 G maximum 1 mJ × 10−7 m2 maximum 1,200,000 BTU/ft2 per year (operating 24h per day, 365 days) 60,000 ft2 floor. Bay and chase, subbasement, mech. floor, office Particles per cubic foot, 0.3 µ in size <1; 0.12 µ in size <35 DI water-virgin PVDF, ultrapure gases, ultrapure chemicals-seamless 316L electropolished tubing stainless steel Between $453 per ft2 and $810 per ft2

Estimate @2004 dollars. (Courtesy of Pavlotsky and Associates.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.19

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

(WC)

38.19

(MC)

NI

(GE)

(FCI) FIGURE 38.10

NI—net income WC—working capital MC—manufacturing cost GE—general expenses FCI—fixed-capital investment

Analysis of costs.

without complete understanding of the dynamics of the economy and effects of research and development (R&D), government regulations, and international trends. For better understanding of the process based on the economics of total investment and profit making it shall be modeled and analyzed as an open discrete system. Accordingly, in an analysis of costs in high-tech manufacturing process, capital-investment costs, manufacturing costs (MC), and general expenses (GE) including income taxes shall be analyzed in an entirety of an open discrete system (see Fig. 38.10). An economic evaluation of the open system may involve very simple procedures in one case and very complex and technical ones in another. There are several basic elements common to all economic analyses: 1. The first and critical step in any economic evaluation is a logical statement of the goals to be achieved. 2. When the comparative importance of these goals has been determined, they will provide the basis for establishing the criteria for the alternative solutions. 3. Research, evaluation, decision-making, flexibility, and optimism to stay on course. Tables 38.6 and 38.7 provide a comprehensive list of construction breakdowns and multipliers. The tables could be used as valuable cost references during cleanroom design and construction life cycle. Some action steps are recommended for cutting construction and operating costs: 1. Precisely define the class of cleanroom desired, making sure it fits the process requirement. Precisely define the room operating air temperature and humidity, making sure it fits the process requirement. 2. The amount of air exhausted from the cleanroom should be the minimum required by the process. 3. Apply the exhaust air management program from the beginning. Start with providing flow and differential pressure indicating instruments at all process exhaust air ductwork branches and tools.

TABLE 38.6 Generic Cleanroom Class M 3.5 (ISO Class 5) Mechanical Only Construction Cost Breakdown Systems

% of total

$/ft2

% of total

$/ft2

Makeup AHUs with ductwork Recirculating AHUs with ductwork Cooling: Refrigerant coir. Air cooled with piping Heating: Steam. Zone reheat-electric Humidification: Steam with piping Exhaust systems with ductwork Process piping Fan-filter units with grid Cooling: Chillers with cooling towers Heating: Hot water. Zone reheat-hot water Humidification: Adiabatic

5.7 31.1 4.5 6.6 1.0 4.9 46.2 -

20.3 112.9 16.7 24.0 3.9 17.6 167.8 -

7.9 8.2 55.1 12.0 9.24 7.16 0.4

13.13 19.30 111.60 24.43 18.63 14.53 0.85

TOTAL for 40,000–80,000 ft2 facility with actual cleanroom occupying 30%–40% of facility space

100%

208.47

100%

363.20

Estimated @2004 dollars.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.20

CLEANROOM DESIGN AND CONSTRUCTION 38.20

FAB YIELD, OPERATIONS, AND FACILITIES

TABLE 38.7 Cleanroom Construction Cost Multipliers Total cost multiplier

Variables that influence cleanroom construction cost 1. Air changes per hour from 20 to 640 air changes per hour 2. Unidirectional or turbulent airflow, vertical or horizontal, air jets. minienvironments 3. Air filtration from 99.99% HEPA filter efficiency at particles 0.5 µm in size to 99.999995% ULPA filter efficiency at particles 0.12 µm in size, where a micron is one millionth of one meter 4. Air handlers. Makeup AHUs, recirculating AHUs, fan-filters 5. Air pressure differential from 0.3 to 0.005 in w.g. Active or passive differential pressure control 6. Temperature control: from +/−2.0°F to +/−0.15°F. Rate of deviation from the set point 7. Humidity control from +/−10%RH to +/−1.0%RH (dew point variation from +/−5.0°F to +/−0.2°F); rate of deviation from the set point 8. Exhaust systems: acid exhaust, ammonia exhaust, solvents and VOC exhaust, toxic exhaust, heat exhaust, general exhaust; sizing, materials of construction, and abatement equipment 9. Vibration limits between 600 and 150 µin/s or less, peak to peak, 0–15 Hz; noise control criteria from 65 NC to 40 NC 10. Magnetic and electromagnetic flux criteria; process specific requirements 11. Electrostatic charge of air and surfaces: from 1.0 mJ/m2 to less than 0.1 mJ/m2 12. Energy and operating cost; lower first cost usually mean higher energy consumption and therefore; up to 55% higher operating cost 13. Form, function, and site specific requirements 14. Particulate: Particles per cubic foot, 0.3 µm in size <1; 0.12 µm in size <35 to particles per cubic foot, 0.5 µm in size <10,000; 0.12 µm in size <345,000 15. Process piping and utilities sizing, materials of construction, and equipment

−0.0800 to 0.19 −0.0738 to 0.18 −0.0320 to 0.10 −0.0700 to 0.15 −0.0410 to 0.18 −0.0320 to 0.15 −0.0340 to 0.19 −0.0310 to 0.16 −0.0270 to 0.10 −0.0370 to 0.15 −0.0370 to 0.12 −0.0170 to 0.15 −0.0380 to 0.16 −0.0400 to 0.15 −0.0210 to 0.20

(Courtesy of Pavlotsky and Associates)

4. Limit ductwork and piping pressure drops by establishing maximum and minimum air velocities for the facility and following these guidelines through construction. 5. Loop supply and exhaust systems to reduce pressure drop and save space. 6. Use energy efficient motors with VFD drives. 7. Use minienvironments, glove boxes, vacuum chambers, and modular enclosures; reduce the need for large ballroom space and therefore reduce operating cost. Noted variables that influence high-tech facility construction cost are given below: 1. Materials of construction: add or subtract 5 percent. 2. Construction labor costs: add or subtract 3 percent. 3. Architectural concept, people movement, and material flow organization, open process area or multiple compartments organization: add or subtract 2.5 percent. 4. Uniqueness of process equipment, single source suppliers, or competitive bidding: add or subtract 7 percent. 5. Time-factor and market constraints: add or subtract 3 percent. 6. Materials supply just in time or in-place warehousing: add or subtract 2 percent. 7. Interpretation of certification data acquisition requirement: add or subtract 1 percent. 8. Interpretation of life safety, fire safety, environmental safety, product safety, and abatement requirements: add or subtract 1 percent. 9. HVAC requirements—air changes, unidirectional or turbulent airflow, and air pressure cascading, once through air systems, active or passive differential pressure control: add or subtract 2 percent. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.21

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.21

10. Utilities availability, requirements, and constraints: add or subtract 4 percent. 11. Lack of competence and lack of ability to make decisions: add 15 percent.

38.15 PRACTICAL PROBLEMS AND SOLUTIONS SAMPLES From design through construction life cycle of a cleanroom, many problems will be encountered by practitioners. Solutions to some of the problems, by Pavlotsky and Associates, are illustrated in the following section. 38.15.1 Ballroom with Minienvironments Technical Description (Sample) The Minienvironments. Facility shall have self-contained Class 1 minienvironments for each process tool and a partial HEPA-coverage vertical flow laminar clean ballroom that is capable of Class 100-turbulent cleanliness (operating conditions) by use of turbulators on the output side of the HEPA filters to improve cleanroom air mixing and operating cleanliness. The performance will be measured per Federal Standard 209E, except for the performance conditions defined here. Class 1 Manufacturing Environment (Operating) Definition. “The Class 1 manufacturing environment is defined as less than 1 particle per cubic foot, of 0.03 µm and larger, measured at 3 in above the top wafer location of all tool indexers.” Measurement. The Class 1 manufacturing environment is the airborne particle environment measured directly above the production wafer occupying the top slot of wafer indexers of the process tool. This location is within the microenvironment enclosure that is installed on the tool’s atmosphericside wafer handling, and has tool covers permanently removed, which would interfere with the laminar airfield used to attain the Class 1 wafer environment. Measurement Conditions. Measurements to demonstrate attainment of the Class 1 manufacturing environment are made with the tool on, in a standby mode. The rest of the cleanroom shall be in normal manufacturing operations at the time of the measurement. Class 100-Turbulent Room Environment (Operating) Definition. “The Class 100-turbulent room environment is defined as less than 100 particles per cubic foot, of 0.5 µm and larger, measured as defined for Class 100 in Federal Standard 209E.” Measurement Conditions. Measurements to demonstrate attainment of the Class 100-turbulent room environment with the cleanroom in normal manufacturing operations at the time of the measurement. Class 10, 100-Turbulent and 10,000 measurements. Excepting the Class 100-turbulent, these cleanliness classes are measured per Federal Standard 209 of the latest version. The following is a description of the style and features needed to meet the requirements for the Class 100-turbulent clean ballroom. Flexibility. The Class 100-turbulent clean ballroom is a partial HEPA-coverage ballroom with movable interior walls for yellow light separations and for protection from fumes. The interior ceiling and wall/structure system shall be highly flexible, suitable for moving on one foot steps. This allows the process area to be increased if ever needed in future. The movable cleanroom walls shall be a floor-standing structure. The interior wall system shall be nonprogressive. Recirculating-Air Path. The air shall be fed to the ceiling HEPA filter boxes via a pressurized overhead ducting system. The return air from the clean ballroom shall pass through the perforated raised access floor, then through the open concrete waffle floor into the lower level, then into perimeter verticaltype recirculating-air fan/coil units, then into the overhead pressurized distribution ducting system. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.22

CLEANROOM DESIGN AND CONSTRUCTION 38.22

FAB YIELD, OPERATIONS, AND FACILITIES

Recirculated air from lithography cleanrooms shall not mix with the rest of the manufacturing facility cleanroom air, to provide protection from chemical fumes and smoke to the metrology, reticle, deep UV, and lithography equipment. Cleanroom Ceiling Height. Due to the need for overhead clearance for rail delivery systems and for servicing of vertical furnaces, the cleanroom shall have a minimum 12 ft clear height. The lighting in the clean ballroom shall be flush lighting, not extending into the 12 ft clear height; however the fire sprinkler heads may extend into the 12 ft clear height. Tool Minienvironments. The minienvironments are described in a separate section, after Class 100-turbulent ballroom specification. The cleanroom ceiling grid system shall easily accommodate the attachment and the hanging weight of the rail systems and tool mini enclosures, without additional modifications. The bottom face of the ceiling grid shall have an easy and structurally adequate connection method to hang rails and other equipment. This system, including connections and handing equipment, shall be capable of meeting the local seismic zone requirements or shall meet Seismic Zone 4 if not otherwise specified. Gowning Entry. Near the employee entrance, a separate locker room will be used for outside clothes, storage of personal articles and shoes, and changing into clean building shoes. All personnel entering the manufacturing building shall wear building shoes or shoe covers. Cleanroom entry shall be via a gowning room through an air-shower system. The gowning room shall act as an air-lock, so the entrance and exit doors from gowning shall not be opened at the same time. The gowning room shall be a full coverage of unidirectional Class 100 area. 38.15.2 Air Flow Systems Technical Description (Sample) Recirculating Air Units. The cleanroom system shall use perimeter vertical-type recirculating air fans with controlled chilled water coils to remove sensible heat and to regulate the incoming room temperature. These fan units shall feed the pressurized air to the ceiling via a pressurized ducting system, then into the HEPA boxes. The HEPA filters shall be mounted in the ceiling grid with a cast-in-place type elastomer 0-ring gasketed HEPA filter box. These boxes shall be clamped in place to ensure that the flexible ducting connections do not tip the boxes and decompress one side of the seal. The fans used shall be lowvelocity vertical fans. The fans shall be suitable to run 24 hours per day, 7 days per week, for at least one year between scheduled maintenance. Belts may be allowable, if the maintenance schedule period is one year or greater. Prefilters shall be used during startup at the entrance to the fan housing. They shall be rated at 30 to 35 percent ASHRAE efficiency, and shall be of sufficient area to minimize pressure drop across the filter. After Phase 1 tool installation is complete, the prefilters may be removed to save electrical running horsepower (electrical costs). The electric motors shall be wired with equally addressed electrical wiring, to minimize electromagnetic field (EMF) generation. For cleanrooms with EMF limitations, motors shall be fully enclosed types, with cast iron end caps to minimize the EMF radiation. Alternatively, the EMF of the motors shall be measured and EMF calculations made to demonstrate that the EMF limitations of the areas are not exceeded. If electronic speed control equipment is used, it must not send electrical noise to the process tool by conduction or radiation, and there shall be no audible noise heard in the cleanrooms. Any cleanroom sound-attenuation filler material shall be a suitable inorganic mineral or glass fiber of a density sufficient to obtain the specified acoustic performance. Material shall be inert and moisture-proof. Filler material shall be protected from particle erosion by airflow by the use of a sealed surface protection of 1 mL Mylar-type film, (or equal). Recirculating air fan module redundancy is not feasible due to the high number of fan units. As a result, the units must be extremely reliable and service access must be provided for easy replacement of the motor or fan-wheel or bearings, without shutdown of the rest of the cleanroom system. All servicing and repair required for the prefilters and fan/coil units shall be readily accessible without going into the cleanrooms. The HEPA filters, sprinkler heads, and lights shall be serviced from the cleanroom side. Controls. The sensible cooling coil shall be provided as part of each fan unit, to remove heat for the control of the air temperature entering the room through the ceiling. The process module temperature is Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.23

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.23

controlled, by sensors located at 8 to 10 in below the HEPA ceiling. The temperature and humidity sensors should be mounted with only the probe exposed in the cleanroom. The probe must be located under active HEPA filter area and not the structure. The requirement is to control the air temperature entering at the HEPA ceiling, and not at the process tools—where localized heat load changes (tools being turned on or off) might cause variations with the temperature control zone. A highly accurate wide-flow-range chilled water valve is required for sensible heat control, which is capable of accurately handling the flow for all tool set heat load situations (50 to 100 percent tool sets) and for the initial tool set heat load situation. The start/stop fan control is normally provided through the building management system (BMS). This allows for sequential startup to avoid overloading the electrical service after a power outage. Local manual override shall be also provided for maintenance and emergency shutoff needs. An air pressure switch shall be incorporated in each fan unit output to detent a condition on nonnormal airflow. Alarms shall be signaled automatically to the BMS. A liquid-level detector shall be incorporated to monitor any internal leaks within the fan coil unit. Alarms shall be signaled automatically to the BMS. Electrical. Each fan unit shall have a unit-mounted motor starter/disconnect that can be reached by the maintenance person at the fan service floor level. The motors shall be high-efficiency 3-phase types, and operate on the 3-phase 480 V service, taken from a facility feeder and not from a process tool feeder. The flush lighting in the cleanrooms shall be mounted in blank panel locations in the HEPA filter grid structure. It shall operate from a facility feeder, not a process tool feeder, to minimize conducted EMI to the process tools. Cleanroom and service areas shall have some lighting on the emergency generator service to provide exit lighting. Also, battery powered lights shall be provided to ensure exit lighting in case the emergency generator fails to start. Structural. The ceiling grid system shall include an easy attachment system that is capable of hanging rail transportation systems, without modification of the ceiling system. Also, there shall be a seismic resistance capability to meet the local requirements. If not otherwise specified, the USA Seismic Zone 4 capability shall be met. This capability shall be present at all locations within the cleanroom, regardless of initial tool layouts, or the lack of support rails in the initial startup. The design should avoid columns inside the cleanroom area by use of a long-span structural design. However, a design cost-reduction alternative, with a single row of columns, shall be also studied and the cost difference shall be presented to the owner for decision. The air distribution plenum and the HEPA ceiling shall be supported from the overhead structure, not from the floor structure. The movable interior wall system shall be supported from the raised access floor and shall sit on top of it. It shall be structurally vibrationindependent from the overhead structure, so that vibration is not transmitted into the cleanroom floors. There is no soft wall joint required between the grid system and the movable interior cleanroom walls, which are sitting directly on the cleanroom raised floor. This has been found acceptable because normally there is not enough vibration power transmitted into the concrete facility floor by this route to take the concrete floor out of vibration limits. (This design point must be verified with the project vibration engineer, however.) The constructed system shall meet local seismic zone requirements. Air-Balancing Dampers. It is desirable that a very low-pressure drop recirculating system shall be built to minimize running horsepower. As part of this, the cleanroom system shall use a pressurizedduct design, with the individual HEPA boxes flow-matched at the factory to meet the flow rate specifications; flow adjustment dampers should not be required in the HEPA ceiling boxes. Also, the cleanroom floor shall not have slide dampers for aerodynamic adjustments. Return-Air Path. The cleanrooms air return shall be through the raised perforated floor. The return air shall be taken through the raised floor into the lower level, then to perimeter vertical-fans, and returned to over-head pressurized ducting system. The return-air path shall be constructed to be reasonably particle, pressure, and humidity tight. It shall meet the fire/smoke draft-stop requirement for the fume/smoke removal mode. Differential-Pressurization Limitations. The cleanroom complex should have no significant pressure differentials between the similar connected cleanrooms, to avoid air currents stirring up dirt from the floors whenever doors are opened. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.24

CLEANROOM DESIGN AND CONSTRUCTION 38.24

FAB YIELD, OPERATIONS, AND FACILITIES

The following guide gives the maximum pressure differentials desired within the cleanroom complex: 1. No pressure differentials between ISO-3, ISO-4, and ISO-5 areas. 2. No pressure differentials between ISO-3, ISO-4, and ISO-5 areas and the perimeter clean corridors and the clean technical support rooms. 3. +0.05 to +0.3 in (water) from gowning rooms (airlocks) to rest of the building, outside the cleanroom complex. 4. The differential pressures are referenced from areas ISO-3, ISO-4, ISO-5 of the cleanroom complex to the other area. 5. The +ve value means that the ISO-3, ISO-4, and ISO-5 room are at higher pressure. The clean corridor connecting the process tool areas with the clean technical support rooms shall have a Class 100-turbulent partial coverage ceiling. 38.15.3 Ceiling Grid Technical Description (Sample) Grid-to-Filter Sealing Method. The HEPA filter boxes are mounted in the ceiling grid with a castin-place type elastomer 0-ring gasketed HEPA filter box. A gel-seal system shall also be allowed, if not at additional cost. The HEPA boxes shall be clamped in place to ensure that the flexible ducting connections to not tip the boxes and decompress one side of the seal. Grid Construction. All metallic members shall be of a corrosion-resistant material or have a corrosion-resistant finish. An antistatic finish is not required, but is allowed if not at additional cost. The grid shall consist of 2-in wide construction. Grids wider than 2 in might be allowed but require prior user approval. Lighting shall be located in blank panel areas, not as part of the grid. The channel grid system shall be installed in a manner that it shall be possible to install or remove filters and other system components from the cleanroom side. Structure. The ceiling grid system shall include an easy attachment system that is capable of hanging rail transportation systems without modification of the ceiling system. There shall be a seismic resistance capability in the grid to meet the local requirements. This capability shall be present at all locations within the cleanroom, regardless of initial tool layouts, or the lack of rails in the initial startup. The entire unidirectional flow ceiling system and wall system shall meet the seismic requirements. Fire Sprinkler Penetrations. Fire sprinklers shall penetrate in blank panel areas and not through the grids. The fire sprinkler penetrations shall be leak-tight and particle free. Fire sprinkler pipes visible on the clean side of the cleanroom shall have a cosmetic cover (or other provision) to blend aesthetically with the HEPA ceiling system (if allowed by the local code). HEPA Ceiling Coverage. The HEPA filters configuration of the ballroom shall be fixed and is not intended to be changed with the tool configuration. This assumes that adequate air circulation has been provided for heat removal in each corral by the cleanroom designer. Unidirectional Flow Ceiling Height. The unidirectional flow ceiling shall have an unobstructed clear height of 12 ft for automation monorails and for exceptionally tall process tools (such as vertical furnace service access). Unidirectional Flow Ceiling Grid Alignment. The ceiling grid spacing shall be held within +/−0.25 in at all locations, matched to the 2 ft by 2 ft intervals of the already installed access floor face. The ceiling height shall be held within +/−0.25 in at all locations, matched to the already installed access floor face.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.25

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.25

38.15.4 Cleanroom Lighting Technical Description (Sample) Lighting Type. Lighting fixtures in cleanrooms shall be sealed and fully compatible with the ISO-3, ISO-5 cleanliness requirement and the lamp ballasts fully compatible with the EMF limitation requirements. Lighting fixtures shall be flush mounted, located in blank panel locations in the ceiling. This is done to facilitate running mono-rails diagonally and to install micro-enclosures where needed. Lighting Levels. Lighting shall provide 90 to 85 ft-candles (initial) over the work surfaces at 30 in height along both sides of walls, when measured as white light, for both white and yellow light areas. High-efficiency fluorescent lamps should be used. The preferred color is a warm white, rather than a cool white—if available in the high-efficiency lamps. Yellow Lighting. Yellow lighting shall be provided in all rooms and their related corridors and service corridors where white-light sensitive materials may be exposed. It might also be required in adjacent to white-light sensitive rooms. The yellow light may be done by either gold tubes, or filter sleeves over white tubes. The gold tubes are preferable, if the lamps meet the user’s other performance criteria. The yellow sheet is normally sandwiched between window glass for door and window applications. The yellow filters shall meet user performance criteria. The yellow filters used for tubes and windows shall meet the criteria of blocking all light from 250 to 450 nm, at energy levels as low as 20 mJ/cm2. The preferred filter will block all light from 250 to 650 nm. Lighting Level Control. The lighting in the cleanrooms shall be capable of locally being reduced by 50 percent, or shut off in a local area. The user shall identify the size areas requiring this local light control during the cleanroom layout development. All windows and doors at the perimeter of the yellow light rooms shall have yellow windows, so that no white light can stream into the yellow-light process areas, including their service sides. 38.15.5 Cleanroom Walls, Windows, Doors and Flooring (Sample) Perimeter Walls Construction. The perimeter interior wall shall be permanent and shall be firerated. The cleanroom walls shall be constructed with interior cleanroom side face of painted aluminum. All edges shall be sealed. Holes cut through the wall shall also be carefully sealed to control particles and air leakage. Interior Movable Walls Construction. Movable interior walls shall be present in the cleanroom where required for light separation and fume/smoke separation purposes. The interior movable walls shall be double-faced of non-fire-rated materials. These cleanroom walls shall be constructed with aluminum honeycomb panels, painted with antistatic epoxy paint. Alternative construction materials require the owner’s prior approval; however, no flammable materials shall be used. The wall system panels shall be field-cut capable for process support piping, duct penetrations, and process tool penetrations with a minimum of dust. The wall system must include the means of thoroughly sealing the cut edges against further emitting of particles. Interior cores of gypsum or particle board are not acceptable for these walls due to contamination when these walls are drilled and cut. The wall system shall be noncombustible with a finish that conforms to at least Class III, as defined by Uniform Building Code (UBC). The cleanroom wall members shall be held within +/−0.25 in of true vertical. The cleanroom side of the wall shall be flush within 1/2 in with the edge of the ceiling grid and filter, to avoid turbulence at this interface, which can cause particle migration between areas. Rearrangement Flexibility. The interior cleanroom (non-load-bearing) walls and their support structure must allow for easy rearrangement, to allow for unplanned large process equipment rearrangements.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.26

CLEANROOM DESIGN AND CONSTRUCTION 38.26

FAB YIELD, OPERATIONS, AND FACILITIES

The interior cleanroom walls shall be of nonprogressive type. Walls shall be easily movable and re-arrangable to accommodate new types of tools with significantly different footprints or other changes affecting the size of the cleanroom. Windows. Windows in perimeter walls and doors shall be of fire-rated glass. Transparent panels in interior walls and doors shall be made of nonbreakable glass, plastic, or firerated glass. The wall panels and doors shall generally have windows in the top half. The windows shall be as wide as practical for the panel and door width, and extend from 3 ft 6 in above the access floor to 6 ft 6 in above the floor. Yellow filtered windows will be required in some of windowed panels, when they are used between areas sensitive to white light. Finish. The wall system finished surfaces must be nonparticle generating and nonoutgassing. Powder-type epoxy paint, factory cured, is preferred. Color shall be U.S. Standard 595A, Color number 27780 (oyster white), or user specified. The complimentary color panels, mixed in patterns with the white panels, shall be used for reducing the stress effect on personnel from the starkness of all white rooms and yellow light room. It is possible to get complimentary colors for the wall panels that are available in standard epoxy paint colors. Doors. Doors used by normal manufacturing operations to pass into, out of, or between ISO-3, ISO-5 Class cleanrooms, shall be the automatic sliding type, constructed to be suitable for cleanroom use. Fiber-type weather stripping should be avoided, due to particle generation. Enclosed, exhausted, closure mechanisms should be used in clean locations. Doors used for ISO-8 Class areas and for maintenance may be swinging type, with their nonventing closure mechanisms located on the service chase side. Caulking Practice. The material used for sealing cleanroom air ducts and walls, and for HEPA filter repair, is a process-critical material regarding the type of gases evolved during and after the specified cure time. These gases can affect the yield of the manufacturing operation. Any caulk material to be used in the cleanroom and related ducting construction shall be tested at a lab for outgassing and the data reviewed by user’s quality control to obtain written permission to use. Example of the approved caulk is GE Type 162 silicone caulk (alcohol-cure type). The GE Type 162 caulk is more expensive, so it is imperative that the contractors understand that the cheaper types cannot be used. (The cheaper caulk types may evolve acetic-acid fumes during curing that will corrode the cleanroom and ducting surfaces.) Clean Flooring. Flooring shall be made of perforated panels with chemical-resistant antistatic tile, rather than grating. The access flooring system shall have aluminum construction. No rustable or corrodible materials shall be used. Panels shall be set in place and fastened for seismic resistance. The fastening method shall allow technicians to be able to easily remove and replace panels when required for tool installation or service. The floor system shall be suitable for site-specific seismic requirements, including structurally allowing for fastening down of process tools to the flooring for seismic protection. Adjustable aluminum pedestals shall be used. Floor system shall meet all seismic requirements. The floor system shall be designed to support a live load of 350 psf. Where panels are cut for penetrations and at intersections with interior perimeter walls and interior columns, floor system shall still provide all support required to maintain panel floor load performance equal to that of uncut panels. Perforated panels shall have a minimum air-pressure drop configuration. Panels shall not have dampers. Antistatic Flooring. Electrical conductivity flooring shall be provided throughout the ISO-3–ISO-8 Class areas. The floor tile surface shall be antistatic, with a surface resistivity of 106 to 5 × 10 ohms per unit area. The access floor system, including panels, shall be grounded during installation. The exceptions are assembly and component test areas that shall have ESD-type conductive flooring (not antistatic) protection.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.27

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.27

Floor Finish. All floor parts shall be finished to protect from corrosion and spilled chemicals. Perforated aluminum panels should be covered with antistatic-type sheet material. The panel system design should be carefully evaluated to ensure that edge-trim pieces are securely fastened and will remain intact with repeated panel removals during operations. Floor Installation. Surface will be flat to +/−0.25 in of the access floor plane, regardless of slope to the concrete floor underneath. The access floor will be installed to match +/−1/4 in to the geometry of the cast-concrete floor waffle structure throughout all clean bays and service chases. The concrete subfloor, beneath the access floor, should be painted with a solvent and corrosive-liquid resistant paint. This shall be done to protect the concrete floor from any chemical spills damage. Vibration-Sensitive Tool Mounting. Where highly vibration-sensitive process tools are installed, they shall be mounted directly to the concrete floor on vibration-stiff stands. These stands may be moved and secured to the floor along with moving the tools. 38.15.6 Final Adjustment and Certification Testing (Sample) The following procedures are used for the definitions and certification testing of the HEPA ceiling. Performance of the cleanroom filters and room environment shall fully meet the technical and performance requirements of this specification. The Federal Standard 209E should be used for definitions and testing methodology. Pretest Conditions. The tests shall be performed during owner installation of the initial process tooling set. As a result, the cleanroom contractor’s adjustments and testing activities must work around the owner’s first priority process tool installation work. The cleanrooms and chases shall be first visually examined for any dirt left over and not cleaned. No debris, dust particles, machine parts, wires, stain, or paint marks, and the like should be visually seen at the part of particle count certifications. A thorough and in-depth visual cleanliness check shall be done, and a written report submitted—including the follow-up on the check list execution. All areas shall be checked along the clean air path, including all interstitial floors, wall structure from all sides, fans, ducts, under raised floor, and subfab. No penetrations, or holes, in the floor shall be open while testing or certifying. All doors shall be in their normal positions. The cleanroom contractor shall arrange with the owner that no construction work, tool hookup, or other personnel activity takes place locally while the contractor is measuring the cleanliness levels, if that activity may affect the test results. It is expected to continue large tool installation and hookup in other parts of the Class 100-turbulent rooms, due to facility and tool set completion schedule requirements. Balance of HVAC Fans Purpose. Adjustment of each cleanroom fan module, recirculating and maintaining fresh air makeup fan unit’s flow rate within specifications, prior to doing all other performance testing. Setting of correct pressurization for that clean area to match local area exhaust flows and attain correct differential pressurizations. Percentage Tested. All units shall be set and measured. Performance Required. The cleanroom shall be final air-balanced and set at the correct pressurization throughout. All fans shall be operating together. Each fan shall be adjusted to produce the volumetric output equal to the design requirements for heat removal and cleanliness. Pressurization limits between cleanrooms shall be within the limits specified. Measurement Procedure. Flow rate measurement shall be made at the module fan inlet, using a duct velocity profile measured with a suitable calibrated instrument. This measurement shall most accurately determine the (standard cubic foot per minute) SCFM delivered into the fan. The total flow can also be determined by measurement of the SCFM output of each HEPA filter, using a collector method. Other methods, such as averaging velocity methods, are not accurate enough for this purpose, especially when turbulators are being used.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.28

CLEANROOM DESIGN AND CONSTRUCTION 38.28

FAB YIELD, OPERATIONS, AND FACILITIES

HEPA Filters Flow Settings Purpose. The purpose of this procedure is to ensure that each of the installed ceiling HEPA filter units produce the correct unidirectional airflow rate. Percentage Tested. All HEPA filter units shall be adjusted and measured. Performance Required. The performance may be changed by the cleanroom contractor during engineering design. The change then needs the approval of the owner. 1. Output flow rate: The HEPA filter units shall produce an SCFM flow of 90 ft/min of average room velocity. 2. Output Flow Rate Variation: The total output flow of each HEPA filter unit shall be within +/−10 percent. 3. Measurement Procedure: The output flow measurements will be made using a calibrated collector volumetric unit. All tests will be made with all doors and wall hatches closed. 4. Report: These adjustment and measurement results data shall be delivered as part of the test report. These data shall include a description of the test setup and instruments used. HEPA Ceiling Leak Testing Test Purpose. The purpose of this test is to ensure that the entire cleanroom ceiling, including HEPA filters, grid and seals, lights, sprinkler penetrations, room-to-ceiling edges, and so on, of the HEPA ceilings are leak-free after installation. Performance Required. The leak-test scanning shall cover all HEPA filter faces, light fixtures, all seals and edges, all fixtures and their seals, and edge seals of all filters and light fixtures and blank panels. All leaks shall be detected, corrected, and retested to establish that the leak has been fixed. Measurement Procedure. After installation, passes will be made of the filter face and the frameto-gasket seal at the gap between the filter and the grid system. The testing challenge method and the scan and measurement method shall be demonstrated to user’s quality control for approval. Any test procedure, other than the one described here, requires prior approval of the owner. The test shall be done with a laser-type particle counter of 1 cfm flow rate, calibrated and sensitive to particles of 0.12 µm and larger. The probe head will be square, 1 in long in the direction of scan and 1.5 in wide. The probe head shall be an isokinetic type. The filter under test shall be subjected to a challenge of approximately 1 × l07 particles per cubic foot. The challenge media shall be as Polystyrene Latex Spheres (PLS) of 0.12 µm size. All particle leak-test challenges shall only be done on the upstream filter face. These data shall include a description of the test setup and instruments used. Any other test technique requires prior user approval. The scanning shall be accomplished by passing the strokes so that the entire area of the filter is sampled. A separate pass shall be then made around the entire periphery of the filter, along the adhesive bond between the filter pack and the rigid frame. The probe shall be held at 1 in from the filter face. An addition pass shall be made under the gap between the filter and the grid system. The scan shall be at a rate of less than 2 in/s. Any single particle reading requires that a 1-min count then be taken with the probe stationary under the location of concern. A reading of two to three counts, within 10 to 15 s is a significant leak that requires repair. Methods using collector funnels for leak detection are not acceptable for this test. Other leak detection procedures require prior written user approval, from their designated quality assurance person. Leaks must be fully repaired and retested to prove that the leak no longer exists. Repairs may be done using GE type RTV 162 silicone caulk or user approved equal. Excessively repaired filter units may be rejected at the discretion of the user’s quality control either at the time of shipment or at the time of unpacking in the field. A description of the test procedure, instruments, and calibration shall be part of the data delivered to user’s quality control prior to the start of testing. Clean Areas Certification Tests Test Purpose. The purpose of this test is to demonstrate that the cleanrooms run within specified standby cleanliness limits. Performance Required. The performance and technical requirements as set by the project and approved by the owner. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.29

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.29

Procedure. The measurements shall be made per Federal Standard 209E and IES RP-006 procedures. The cleanroom certification measurements shall be made with all related facility systems running with process tools off and all personnel activities at rest. The measurements shall include: 1. Particles count: The cleanliness measurements shall be statistically measured and calculated as the statistical mean with a percent confidence interval, using the method described in Federal Standard 209E. In determining the statistical mean, a normal distribution may be assumed for the calculations. The cleanliness measurement shall be made with a 0.1 µm of calibrated laser-type counter. Each particle measurement shall be for a measured counter air volume of at least 10 ft3. The unidirectional ceiling shall not be challenged during this test. The recirculating fans, exhausts, and fresh air makeup system shall be operating normally. Particle measurements locations shall be per Federal Standard 209E. These locations shall be included in addition to the grid pattern measurements required per Federal Standard 209E. 2. Temperature and humidity testing: Application: All cleanrooms with temperature or humidity limitations. These performances shall be met in all the following conditions: (a) with the initial Phase 1 Tools Set installed and operating, (b) with the Phase 2 Tools Set installed and operating, and (c) with the Phase 1+2 Tool Set installed and operating. Purpose of test: The purpose of this test is to demonstrate that the completed cleanroom operates within temperature and humidity limits of the individual cleanrooms. Percentage tested: All cleanrooms with relative humidity (RH) specifications limitations. Performance required: Dew point, RH, and temperature performances shall be as specified. Procedure: These temperature and humidity performance of the cleanrooms shall be measured directly below the HEPA filters in the air entering the cleanroom. Temperature: The intent is that the temperature should be controlled and measured at unidirectional air entry into the cleanroom before the heat is added from the process tools. The sensor location can be at any distance between 6 and 10 in below the HEPA filter face, providing it is in the normal unidirectional air flow from the HEPA filters. It should be more than 12 in from any structure, such as lighting or grid structure. The purpose is to measure/ control the incoming air temperature to produce a stable air temperature envelope surrounding the process tool. Humidity: The relative humidity should be measured at the entry into the cleanroom, before the heat is added from the process tools. The sensor location can be at any distance between 6 and 10 in below the HEPA filter face, providing it is in the normal unidirectional air flow from the HEPA filters. It should be more than 12 in from any structure, such as lighting or grid structure. The purpose is to measure/control the incoming air dew-point temperature to produce a stable air humidity envelope surrounding the process tool. The room measurements shall be made over a continuous period of 5 days, 24 hours per day. Data shall be recorded on a recorder of sufficient resolution to be able to read changes of less than 0.1°F or °C. The temperature measurement instrument shall have combined resolution and calibration to 0.1 degree accuracy (accumulated error) and be calibrated to a secondary NBS standard. The dew-point measurement will be made over the same continuous period of 5 days, 24 hours per day. Data will be recorded on a recorder of sufficient resolution to be able to read changes of more than 0.3 percent RH. The dew-point measurement instrument shall have resolution and calibration to better than 0.3 percent RH (accumulated error) and be calibrated to a secondary NBS standard. 3. Lighting level testing: Application: Cleanrooms final acceptance test. Test purpose: The purpose of this test is to establish that the cleanrooms provide adequate lighting levels cleanroom. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.30

CLEANROOM DESIGN AND CONSTRUCTION 38.30

FAB YIELD, OPERATIONS, AND FACILITIES

Percentage tested: All lighted areas shall be measured. Performance required: The performance requirements are that the entire cleanroom complex produce the required lighting levels listed in the design criteria and approved by the owner. Measurement procedure: The lighting measurements shall be made at a height of 32 in from the floor and 24 in from the side walls, along all areas where process equipment might be installed. The lighting measurements shall also be made in the operator corridor centerline at a height of 32 in. The lighting measurements shall be made with a calibrated light-meter, measuring in footcandles or equal unit. All illumination measurements will be made in white light conditions, prior to installation of any yellow light. Alternatively, an initial empirical calibration of the instrument shall be made between white light and the yellow light present in the facility under test. Then, lighting can also be measured under the installed yellow light. 4. Noise level testing: Application: Cleanroom final acceptance test. Test purpose: The purpose of this test is to ensure that the cleanrooms operate within noise limitations. Percentage tested: All cleanrooms shall be measured. Performance required: The cleanrooms shall not exceed the noise levels specified, measured with all process tools off, the fresh air makeup system running, the facility exhausts fans running, and all cleanroom fans running at normal velocities. Procedure: The noise measurements shall be made at a height of 32 in from the floor and 24 in from the side walls, along all areas where process equipment might be installed, and in the operator corridor centerline at a height of 32 in. Measurement shall be made at 10 ft intervals along both sides and down the centerline of each cleanroom. The noise measurements shall be made with a calibrated acoustic meter, measuring noise levels on an NC curve. A decibel (dB) curve measurements shall not be acceptable. 5. Electromagnetic fields testing: Application: All cleanrooms and SEM locations in quality assurance room. Test purpose: The purpose of this test is to ensure that the completed cleanroom operates within EMF limitations. Percentage tested: All cleanrooms and SEM locations in quality assurance room. Performance required: The EMF limitations in the cleanroom locations and in their associated service aisles, shall not be exceeded. Procedure: The EMF measurements shall be made at a height of 32 in from the floor and 24 in from the side walls, along all areas where process equipment might be installed in the cleanroom and in the associated service aisles. The EMF measurements shall be made with a calibrated instrument. EMF measurements shall be made with all cleanroom motors and lighting on, and all process tools off. The measurement procedure and calibrated instrument shall be approved by the owner prior to measurements. 6. Vibration-level testing: Application: All cleanrooms and die-sort rooms. Purpose of test: The purpose of this test is to ensure that the cleanrooms and technical rooms operate within their vibration limits. Percentage tested: All cleanrooms and die-sort rooms. Performance required: Vibration performance limitations specified on the basis of design. Procedure: The vibration measurements shall be made with a calibrated instrument, with the sensor floor mounted directly to the concrete cleanroom floor. Measurements shall be made under the conditions of all cleanroom modules operating for the acceptance test. All cleanroom motors shall be running, and all process tools shall be off. Data shall be recorded of the floor vibrations levels

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.31

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.31

both on the process-equipment slab and on the service aisle slab. Vibration measurement data are required on top of the perforated raised floor in areas where the floor has to be fastened down for access-floor standing vibration-sensitive process tools, but no specification has to be met. 38.15.7 Cleanroom Construction Protocol (Sample) Cleanroom construction shall be divided into six phases that include demolition, rough-ins, cleanroom perimeter, cleanroom enclosure, HEPA installation and certification, and postcertification. From one phase moving to next, construction protocol control becomes more stringent. The following sections, prepared by Le Chase, describe changes on controlling badge color, garments, housekeeping, cleaning of materials, equipment, tools, and protocol. Phase 0—Demolition if Applicable (Badge Color: None) Starts: With the demolition of the existing walls, ceiling, flooring, mechanical, and electrical services supporting the area Ends: After completion of all demolition activities and the area has been “gross” cleaned Activities: Removal of walls, ceiling, flooring, ductwork, piping, electrical conduit and wiring, and so on. Salvage materials as directed by the construction manager Garments: Normal work clothes and shoes Housekeeping: Daily construction clean-up; removal of dirt and debris Protocol: Normal construction procedures; use special care in handling materials scheduled for salvage and reuse Phase 1—Rough–Ins (Badge Color: Green) Starts: After the completion of the “gross” cleaning of the area. Ends: At the completion of the installation of the exterior walls of the cleanroom area, when air can be supplied to the area for pressurization and at the completion of the “gross” cleaning of the area. Activities: Installation of supply and return ductwork, HVAC units, sprinkler piping, under-floor waste system piping, high-purity piping rough-in, electrical rough-in, data telecommunications wiring rough-in, replacement of raised floor tiles, installation of cleanroom walls. Garments: Clean work clothes and clean shoes. Housekeeping: Daily vacuuming of the clean zone with vacuums equipped with HEPA filters. Clean zone shall be mopped weekly (at minimum) with cleaning solution of high-purity water and cleaning agent designed to remove oil residues (isopropyl alcohol, Buckeye Blue or other approved product; product shall be approved by the construction manager). Cleaning of Material, Equipment, and Tools: All material and equipment scheduled for incorporation into the cleanroom area below the raised floor and 10 ft above finished floor shall be free from contaminants when viewed under ambient light. All materials, equipments, and tools shall be free from dirt, debris, and oil. Prefabrication of components is required to the greatest degree possible. • Work Activities Not Permitted in the Cleanroom Area and Preparation Zone (Clean Zone): • • • • • •

Grinding Open flame cutting Plasma arc cutting Pipe threading Sanding, sandblasting, or other forms of air-driven abrasive removal Sawing (except with hole saw)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.32

CLEANROOM DESIGN AND CONSTRUCTION 38.32

FAB YIELD, OPERATIONS, AND FACILITIES

• Work Activities Permitted with Special Requirements: • Drilling (immediate clean-up of debris. If drilling into concrete, “contain and capture” technique is required) • Sawing with hole saw (immediate clean-up of debris) • Brazing (requires the use of a HEPA filter equipped “smoke eater”) • Soldering (requires the use of a HEPA filter equipped “smoke eater”) • Welding (requires the use of a HEPA filter equipped “smoke eater”) • Protocol: • All personnel shall enter and exit the clean zone through the designated entrance (as determined by the construction manager). • There shall be no food, beverages, or tobacco products permitted in the clean zone. • All “gross” packaging (crating, cardboard, and so on) of materials and tools shall be removed prior to the material or equipment being moved to the preparation area. • No materials, equipment, or tools shall be stored in the cleanroom area or preparation area (clean zone). • No aerosols or sprays are permitted in the cleanroom or preparation area (clean zone). • All spills or other sources of contaminants are to be immediately cleaned up and cleaning materials properly disposed of. • All trash and debris shall be placed in proper containers for daily removal from the clean zone. • All materials, equipment and tools shall enter the clean zone through the designated entrance. Materials, equipment, and tools shall be free from dirt, debris and oil (construction clean). All materials and equipment scheduled for incorporation into the cleanroom areas below the raised floor and 10 ft above finished floor shall be free from contaminants when inspected under ambient light (Level 1). • Work activities shall be governed by the requirements indicated above. Phase 2—Cleanroom Perimeter (Badge Color: Brown) • Starts: At the completion of the “gross” cleaning of the cleanroom area at the end of Phase 1 and air being supplied to the cleanroom area for pressurization • Ends: At the completion of the installation of the high-purity piping rough-ins, electrical rough-ins and other utility work in the chases, above the ceiling and elsewhere within the boundary of the cleanroom area • Activities: Completion of the high-purity piping rough-ins, electrical rough-in, data telecommunications rough-in, ductwork drops to terminal HEPA filters • Garments: • • • •

“Clean” work clothes and shoes Disposable shoe covers (provided by the construction manager) Disposable head covers (bouffant; provided by the construction manager) Disposable shoe and head covers are to be changed whenever dirty or torn

• Housekeeping: • All requirements of Phase 1 • Daily mopping of cleanroom floor areas • Cleaning of Materials, Equipment, and Tools: All materials, equipment, and tools scheduled for incorporation into the cleanroom area or for use in the installation shall be free of contamination when viewed under ambient light. • Work Activities Not Permitted in the Cleanroom Area: As per Phase 1 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.33

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.33

• Work Activities Permitted in the Cleanroom Area with Special Requirements: As per Phase 1 • Protocol: • All requirements from Phase 1. • Air shall be supplied to the cleanroom area filtered with 95 percent ASHRAE filters to provide a minimum pressure differential of 0.03 in w.g. (positive) between cleanroom area and adjacent areas at all times. Ensure that air handlers and ductwork not being used for pressurization of the cleanroom area are not contaminated by air being returned or exhausted from the cleanroom area. • All materials, equipment, and tools entering the cleanroom area shall be free from contaminants when viewed under ambient light (Level 1). Tools may remain in the cleanroom area if stored in cleaned tool boxes or other designated storage containers approved by the construction manager. Phase 3—Cleanroom Enclosure (Badge Color: Yellow) • Starts: At the completion of all ductwork drops, piping, electrical, and data telecommunications rough-ins and at the completion of “gross” cleaning of the cleanroom area • Ends: At the completion of the installation of the ceiling grid, light fixtures, ceiling blank panels and the area has been “gross” cleaned • Activities: Testing of all piping systems, electrical distribution and data telecommunication wiring, installation of wiring devices, installation of ceiling grid, sprinkler heads, light fixtures, ceiling blank panels, and flooring. • Garments: • • • • • • •

“Clean” work clothes and shoes Disposable coveralls (provided by the construction manager) Disposable shoe covers (provided by the construction manager) Disposable head covers (provided by the construction manager) Disposable face mask, beard cover if required (provided by the construction manager) Disposable latex gloves (provided by the construction manager) Disposable garments may not be worn outside the cleanroom area

• Housekeeping: All requirements of Phase 2 • Cleaning of Materials, Equipment and Tools: All materials, equipment, and tools schedules for incorporation into the cleanroom area (cleanrooms and chases) shall be free from contaminants when viewed under high-intensity oblique white light (Level 2) • Work Activities Not Permitted in the Cleanroom Area: • • • • • •

As per Phases 1 and 2 Drilling Sawing Brazing Soldering Welding

• Work Activities Permitted in the Cleanroom Areas with Special Requirements: • • • • •

Drilling (“contain and capture” technique required) Sawing (hole saws only, “contain and capture” technique required) Brazing (chases only, with HEPA filter equipped “smoke eaters”) Soldering (chases only, with HEPA filter equipped “smoke eaters”) Welding (chases only)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.34

CLEANROOM DESIGN AND CONSTRUCTION 38.34

FAB YIELD, OPERATIONS, AND FACILITIES

• Protocol: • All requirements of Phase 2. • Personnel shall enter the cleanroom perimeter from the designated entrance. They shall remove “outer” garments and store as directed by the construction manager. They shall then proceed to the temporary gowning or staging area located adjacent to door number XX. • In the temporary gowning area, personnel shall “gown up” as follows: • • • • •

Head cover Shoe cover Coveralls Face mask (beard cover if applicable) Latex gloves

• After “gowning up” personnel shall then proceed to the cleanroom areas (cleanrooms and chases). • All materials, equipment and tools shall enter the cleanroom perimeter by the designated entrance. They shall enter the cleanroom area through the temporary gowning or staging area only. • Tacky mats shall be installed at the entrance to the temporary gowning area from the preparation area and from the entrance of the temporary gowning area to the cleanroom area. • All materials, equipment, and tools scheduled for incorporation into the cleanroom areas or for use in installation shall have no more than 12 particles per square foot when inspected under black light or 72 particles per square foot when inspected under high-intensity white light (Level 2 cleanliness). • Prior to the installation of any light fixtures, sprinkler heads, and blank ceiling panels in the ceiling grid, the grid shall be free of contaminant when inspected under high intensity oblique white light. Phase 4—HEPA Installation and Certification (Badge Color: Red) • Starts: When all interior “finishes” of the cleanroom areas are complete and the cleanroom areas have been “gross” cleaned • Ends: At the completion of the “as-built” certification of the cleanroom areas • Activities: Installation of the terminal HEPA filters, HEPA FFUs, air balancing, precision cleaning of the cleanroom areas, “as-built” certification of the cleanroom areas • Garments: As required in Phase 3 • Housekeeping: As required in Phase 3 • Cleaning of Materials, Equipment, and Tools: As required in Phase 3 • Work Activities Not Permitted in the Cleanroom Areas: As required in Phase 3 • Work Activities Permitted in Cleanroom Areas with Special Requirements: By permission and under the direction of the construction manager only • Protocol: • All requirements of Phase 3. • Terminal HEPA filters and FFUs shall remain in secured storage until required immediately for installation. They shall be handled and installed by personnel trained in their care and installation only. These personnel shall be approved by the construction manager. • HVAC units serving the cleanroom areas shall be cleaned and have the final set of filters installed at the time of the installation of the terminal HEPA filters. • HVAC systems serving the cleanroom areas shall be prebalanced (air) prior to the installation of the terminal HEPA filters. • No other work is permitted in the cleanroom areas after the installation of the terminal HEPA filters has started.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.35

CLEANROOM DESIGN AND CONSTRUCTION CLEANROOM DESIGN AND CONSTRUCTION

38.35

• After completion of the installation of the terminal HEPA filters and FFUs, the cleanroom areas shall be finally air balanced. • After the completion of the final balancing, all surfaces of the cleanrooms shall have no more than 6 particles per square foot when inspected under black light or 18 particles per square foot when inspected under high intensity white light (Level 3 cleanliness). This is the “precision cleaning” of the cleanroom areas and will be performed by an independent cleanroom cleaning contractor as directed by the construction manager. • After completion of the “precision cleaning” of the cleanroom areas, the cleanrooms shall be “asbuilt” certified as per ISO 14644. Phase 5—Post Certification (Badge Color: Red with White Stripes) • • • • •

Starts: After the completion of the “as-built” certification of the cleanroom areas. Ends: At the direction of the construction manager. Activities: By written permission of the construction manager only. Garments: As required by the owner’s operating protocol and as directed by the construction manager. Housekeeping: By owner, personnel working in the cleanroom areas are required to comply with all requirements of the owner’s operating protocol. • Cleaning of Materials, Equipment, and Tools: As required by the owner’s operating protocol; materials equipment and tools shall be no more than 3 particles per square foot when inspected under black light or 18 particles per square foot when inspected under high intensity white light (Level 3 cleanliness). • Work Activities Not Permitted in the Cleanroom Areas and Permitted under Special Requirements: By permission and under the direction of the construction manager. • Protocol: Personnel shall follow all requirements of the owner’s operating protocol. Personnel shall enter the cleanroom area through the designated gowning rooms only. Certification In order to measure the effectiveness of the project team in meeting the functional requirements of the cleanroom, various tests are conducted to measure the performance of the critical systems against accepted reference standards. This testing process is commonly referred to as certification of the facility.

FURTHER READING American Society of Heating, Refrigerating, and Air-Conditioning Engineers, ASHRAE Handbook, Heating, Ventilating, and Air-conditioning Applications, Atlanta, GA, 2003. Conference Proceedings, Cleanrooms East 2003, Boston, MA. Federal Standard 209E, Cleanroom and Work Station Requirements, The General Service Administration, Washington, D.C. Gale, S. F., “FFUs: Setting a Course for Energy Efficiency,” Cleanroom, Vol. 18, No. 9, September 2004. IEST RP—CC012, “Considerations in Cleanroom Design and Construction,” Institute of Environmental Science and Testing. ISO–14644, Parts 1–8, Cleanrooms and Associated Controlled Environments, International Standards Organization, Geneva, Switzerland. ISO 14698, Cleanrooms and Associated Controlled Environments: Biocontamination Control, International Standards Organization. IEST RP–CC006, Testing Cleanrooms, Institute of Environmental Science and Testing. Jaisinghani, R., Design for Energy Efficient Low Operating Cost Clean Rooms, Technovation Systems, April 2003, Boston.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH38.qxd

04/04/2005

21:17

Page 38.36

CLEANROOM DESIGN AND CONSTRUCTION 38.36

FAB YIELD, OPERATIONS, AND FACILITIES

Jeng, M. S., T. Xu, and C. H. Lan, “Toward Green Systems for Clean Room: Energy Efficient Fan-Filter Units,” Proceedings of Semiconductor Equipment and Materials International Conference (SEMICON) West 2004— SEMI Technical Symposium: Innovations in Semiconductor Manufacturing (STS: ISM), pp. 73–77, San Francisco, CA, July 2004, LBNL-55039. Chubb, J., “New Approaches for Electrostatic Testing of Materials,” Journal of Electrostatics, March 2002, p. 223. Pavlotsky, R. V., “Arriving at Approximate Cost for Pharmaceutical, R and D and Biopharmaceutical Facilities,” Cleanrooms, Vol. 18, No. 8, August 2004. Pavlotsky, R. V., “Clean Room Design, Technical Features,” Cleanrooms, Nashua, NH, Vol. 16, No. 1, January 2002. Pavlotsky, R. V., “Cost Savings Opportunities in Biotech Clean Room Operations,” International Society of Pharmaceutical Engineer, Presentation, Vol. 18, No. 2, Boston, Feb 2004. Pavlotsky, R. V., “The Whole Cleanroom Is Indeed the Sum of Its Parts. Technical Features,” Cleanrooms, Vol. 16, No. 3, March 2002. Pavlotsky, R. V., “15 Factors That Influence Clean Room Design and Construction Costs,” Cleanrooms, Vol. 18, No. 4, July 2004. Standard ANSI/ESD S20.20, Development of an Electrostatic Control Program for Protection of Electrical and Electronic Parts, Assemblies and Equipment, ESD Association. Tschudi, B., D. Sartor, and T. Xu, An Energy Efficiency Guide for Use in Clean Room Programming, sponsored by Lawrence Berkeley National Laboratory, Northwest Energy Efficiency Alliance, and California Energy Commission, Berkeley, Dec 2001. Tschudi, W., T. Xu, G. Bell, E. Mills, D. Sartor, Cleanroom Energy Benchmarking Results, sponsored by California Institute for Energy Efficiency, Pacific Gas and Electric Company, and Rumsey Engineers, Berkeley, CA, 2000, LBNL-49112. Xu, T., and M. S. Jeng, “Laboratory Evaluation of Fan-Filter Units’Aerodynamic and Energy Performance,” Journal of the IEST, Vol. 47: pp. 116–120, Institute of Environmental Sciences and Technology, Rolling Meadows, IL, 2004, LBNL-54250. Xu, T., “Considerations for Efficient Airflow Design in Cleanrooms,” Journal of the IEST, Vol. 47: pp. 24–28, Institute of Environmental Sciences and Technology, Rolling Meadows, IL, 2004, LBNL-55970. Xu, T., “Performance Evaluation of Clean Room Environmental Systems,” Journal of the IEST, Vol. 46: pp. 66–73, Institute of Environmental Sciences and Technology, Rolling Meadows, IL, August 2003, LBNL-53282. International SEMATECH, 98013447A-STD, SEMATECH Guide for Documenting Process Tool Installation Time and Cost, SEMATECH Technology Transfer. International SEMATECH, 98103579A-XFR, SEMATECH Equipment Installation Sign-Off Procedures, SEMATECH Technology Transfer.

INFORMATION RESOURCES ASHRAE (American Society of Heating, Refrigeration and Air Conditioning Engineers): htt://www.ashrae.org/ A2C2 (Advanced Applications in Contamination Control) magazine: http://www.a2c2.com/ Cleanrooms magazine: http://www.cleanrooms.com/ Institute of Environmental Science and Testing (IEST): http://www.iest.org/ International SEMATECH: http://sematech.org/ Lean Construction Institute: http://www.leanconstruction.org/ Micro magazine: http://www.micromagazine.com/ Semiconductor Manufacturing magazine: http://dom.semi.org/ John Chubb Instrumentation: http://www.jci.co.uk/

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 39

MICRO-VIBRATION AND NOISE DESIGN Michael Gendreau Hal Amick Colin Gordon and Associates San Bruno, California

39.1 INTRODUCTION Noise and vibration are contaminants in semiconductor processing and research. Since the tools used in semiconductor manufacturing are sensitive to vibration and noise to varying degrees, excessive amounts of these contaminants can adversely impact yield, throughput, or the operating linewidth or resolution of the tools. In addition to the potential impact to tools, noise impacts personnel working in the cleanrooms and labs, and it is usually regulated in the external environment. The vibration and noise performance of semiconductor and other advanced technology research and manufacturing buildings must be considered early in the conceptual design stage and throughout the design and construction of the project. This procedure applies not only to new buildings but also to retrofit projects, service or process modifications, and tool installations. It starts with site vibration and noise evaluations and reviews of manufacturers’ tools specifications or selection of generic criteria. The structural design of the building, layout of the process and mechanical equipment, and the tool layout in the lab or cleanroom, are all critical to a successful vibration and noise design. When vibration and noise cannot be controlled solely by equipment layout, as is often the case, specification of appropriate vibration and noise control devices (e.g., isolators and silencers) will be necessary. Finally, appropriate care must be taken in the tool hook-up stage, so that the vibration and noise environment of the base building is not excessively elevated. This chapter discusses these and other considerations necessary to provide acceptable noise and vibration environments for semiconductor manufacturing and other advanced technology work (e.g., nanotechnology research, LCD-TFT manufacturing, and sensitive biotechnology work). 39.1.1 Vibration and Noise Sources There are many sources of vibration and noise that may contribute to the operating production or research environment. Sources external to the building include general ambient conditions (due to many sources near and far); local traffic, rail, and aircraft; and adjacent industrial facilities. Internal sources include automation and product handling machinery, walking and other personnel activities, materials movement, electrical and mechanical equipment, piping and ductwork, and the tools themselves. Since the building owner will have limited control over off-site external vibration sources and since there are limits to the mitigation that can be provided with the building, site selection and layout on Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

39.1

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.2

MICRO-VIBRATION AND NOISE DESIGN 39.2

FAB YIELD, OPERATIONS, AND FACILITIES

the site with respect to external conditions is critical. With enough flexibility in the site selection and layout, adequate control of internal noise and vibration sources (and external noise sources) can usually be provided in the design and layout of the building and infrastructure. 39.1.2 Vibration and Noise Sensitive Areas and Equipment The people occupying the building are sensitive to noise and the tools are sensitive to noise and vibration to varying degrees. The degree of vibration sensitivity of the tools may be gauged by comparison with more familiar vibration amplitudes. For example, the most demanding metrology or characterization equipment specifications may require environmental vibration amplitudes 10 times lower than typical microelectronics (photolithography) production floors, 100 times lower than typical laboratory (400 × microscope) or semiconductor support function (e.g., CMP, implant, etch, and wafer starts) floors, and 500 to 1000 times lower than just-perceptible vibration that might be experienced, for example, on a suspended office building floor under normal conditions. Most inline semiconductor process equipment is not highly sensitive to noise, although a few tools have criteria within the range of typical operating cleanroom noise levels (NC-55 to NC-70*). Metrology and nanotechnology characterization tools (such as SEM, FIB, and TEM) are typically more sensitive to acoustic noise, many requiring moderate noise levels (NC-30 to NC-50)—noise levels more commonly found in an office environment than in a cleanroom. Some require very low noise levels (NC-15 to NC-30)—that are similar to those required in recording studios, auditoria, or conference rooms. Special cases often requiring the most stringent noise and vibration criteria include nanotechnology instrument development suites and semiconductor research and development laboratories. The remainder of this chapter is divided into several subsections covering the following topics: measurement methodologies and criteria; vibration and noise sources; advanced technology building foundation and structural design; vibration and noise control in the mechanical, electrical, and process design; acoustic design; tool hook-up; purposes and timing of facility vibration surveys; maturation of the vibration and noise environment; and future trends.

39.2 MEASUREMENT METHODOLOGY AND CRITERIA Vibration and noise are fairly complex physical phenomena that can be measured and represented numerically. Existing spaces may be assessed by comparing the measured data with established criteria or one may impose those criteria on a design. There are established methodologies and standards for numerical representation of vibration and noise data, some of which are general and others of which are more applicable to either one or the other. In this section we will discuss the measurement approaches (generalities and then specialized), followed by an introduction of the relevant vibration and noise criteria. 39.2.1 Measurement Methodologies There are many possible ways to measure and represent vibration and noise. In any particular case, how one goes about it depends on the type or sophistication of information one wishes to obtain. The general goal of measurement and signal processing is to adequately represent the nature of the environment with appropriate complexity so that critical elements of the environment are not obscured. Both overly complex and overly simplified representations of the vibration or noise environment can obscure the results, depending on the form of the information required. In general, vibration and noise can be described as continuous fluctuations in the amplitude of some environmental variable over time. Vibration involves movement (generally of a surface) and * There are several standardized or commonly used noise criterion curves designed to rate human response to noise.1 Since there are no generic noise criteria for tools, it is common in the high-tech industry to reference one of these perception-based indices. See Ref. 2 for more information.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.3

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.3

can be represented as acceleration, velocity, or displacement. Noise involves fluctuation in air pressure and is generally represented in units based on pressure. These are environmental variables; the representation of the vibration or noise associated with a particular source is typically and more usefully given in more inherent terms,* such as its sound power or the amount of force it applies to its support structure. The fluctuations can occur at specific frequencies or randomly over a wide range of frequencies or a combination of the two. Thus, vibration or noise can be separated into several classes: 1. Tonal versus random:3 a. Tonal vibration is periodic vibration at a single frequency. It is usually associated with periodic processes, such as rotating or reciprocating mechanical equipment or magnetostriction in transformers. Likewise, tonal sound is at a single frequency, but there is a wide variety of causes, so that an environment such as an operating cleanroom can have many tonal components in the noise. b. Random, often known as “broadband” vibration or noise, contains random energy at many frequencies. Sources of random vibration and noise include turbulent fluid flow and impacts such as footfall and door closures. 2. Steady-state versus transient: a. Steady-state† vibration or noise does not change significantly on average, over time. This is produced by continuous or relatively continuous sources, such as operating machinery, constant traffic, and heating, ventilating, and air conditioning (HVAC). b. Transient vibration is time dependent. Sources include passing walkers, trains, intermittent machinery such as robotics and automatic material handling systems (AMHS), and impacts. The vibration in semiconductor production floors, or on sites under consideration for the location of a factory, can contain all of these elements. However, in the stiff floors used for production and research activities, the vibration environment is often best characterized as “steady-state random,” that is, shaped by various random sources and often including some steady-state tonal components associated with building mechanical equipment and tools.4,5 Softer floors such as used for offices and production support functions (and stiff floors as well in more exceptional cases) will often in addition be punctuated by occasional transient vibration, such as due to footfall. The airborne noise in a cleanroom also contains a mix of random and tonal elements. The noise in a cleanroom without operating tools is mostly random, generated by air movement, and perhaps containing low-frequency tonal components associated with recirculation fan blade passage frequencies. The tools contribute a great deal of tonal and random noise to the cleanroom or lab environment. A measurement characterizing the variation in amplitude over time—in representational form known as time domain—is necessary to record all of the information about the environment. However, given the complexity of the environment from the standpoint of frequency, time domain representations of the environment do not provide a simple readable representation of the significant components of the vibration or noise in high-technology facilities. There are exceptions to this, of course. If one is primarily interested in the response of a floor to a transient—especially if this excites a fundamental mode of the structure—it is readily visible in time domain data. Perhaps the most useful aspect of time domain data is that it is completely re-analyzable, and can be used to produce any of the other representations of data to be discussed presently. The reverse is not true, since basic time domain data cannot be reconstructed from other data representations, giving the time domain representation the distinction of having the greatest information depth, although often unreadable in its complexity. * By “inherent” we refer to quantities that are absolutely dependent on properties of the source, and are not dependent on or mediated by the environment. † Strictly speaking, continuous random vibration or noise is said to be “stationary,” and the term “steady-state” is used for tonal content. However, we will use the latter term interchangeably.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.4

MICRO-VIBRATION AND NOISE DESIGN 39.4

FAB YIELD, OPERATIONS, AND FACILITIES

Structures and tools are subject to resonance response, meaning that they are more sensitive to vibration and noise at some frequencies than at others. With many tools, the sensitivity to vibration or sound will be based upon whether or not internal resonances are excited. This suggests that it is important to have some knowledge of the frequency content of vibration or noise. When vibration or noise is represented as a function of frequency, it is said to be in the frequency domain. There are several ways to obtain data in the frequency domain. Using fast fourier transform (FFT) methods, a snapshot of the time domain data can be transformed into a representation of amplitude as a function of frequency over the measurement period.* The parameters used in the FFT sample are critical to accurate representation of the data and in the allowance of adequate mutability, if needed. The following paragraphs note a few considerations in this regard: • Type of vibration environment: The presence of the various types of vibration listed previously may dictate the measurement parameter settings: • Stability of the environment during the sample period: If the environment is steady-state, representations of the average environment may be used, as long as the averaging time is long enough to represent a stable value. In the case in which the environment is not steady-state, representations of the maximum value obtained at each frequency may be used. If the environment contains significant transients, representations of the average value are usually not useful unless accompanied by time domain data for the sample period. In either case, maximum representations are useful if one wishes to know the maximum impact during the measurement period. It is especially important in this case to state the measurement time. • Tonal versus broadband vibration: The frequency resolution of the data may be influenced by the level of detail needed to identify tonal frequencies or resonances. Also, the type of frequency analysis used may be determined by the presence of tonal or broadband vibration. For example, while power spectral density (PSD) analysis is more general than representations of amplitude for arbitrary bandwidths in random vibration analysis, PSD is not defined for measurement of environments containing significant tonal vibration components.4,5 • Measurement time: Implications of the relevance of this are given in the bullet item above. The measurement time must also be long enough to adequately characterize the lowest frequency of the desired frequency range. • Frequency range: This is the overall range of frequencies used in the analysis. • Bandwidth: The measurement bandwidth affects the time for each individual sample† and the frequency resolution of the data. This also represents another potential limit in the mutability of the data, as relatively low resolution data can be constructed from higher resolution data (e.g., transforming constant narrowband data with a resolution of 0.125 Hz to one-third octave bands), but not vice versa. Selection of appropriate bandwidth will be determined by the extent of frequency resolution required. In FFT analysis, the bandwidth is constant over the entire spectrum and is some multiple times the frequency resolution. That multiple is dictated by the windowing function being used (see below). • Windowing functions: Windowing functions, for example, Hanning, rectangular and flat top, are used to mitigate sampling errors in the FFT process.6 Selection of the appropriate windowing function is important in vibration analysis, for example, because one might provide better accuracy in frequency (Hanning) and another might provide better accuracy in amplitude (rectangular). • Acceleration, velocity, displacement: Various types of transducers measure one of these values (e.g., accelerometers versus velocity sensors or geophones), but the data can be integrated at the time of measurement or later into any of the other representations. Thus, there need be no preference for

* FFT analysis results in spectra with amplitudes spaced at uniform increments of frequency, which we call the spectrum’s resolution. † The measurement sample time is T = 1/B = L/Rf, where B is the frequency resolution in Hz (1/s), Rf is the frequency range, and L is the number of divisions of the range used in the analysis.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.5

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.5

one format over another so long as significant errors are not introduced in the transformation or measurement, such as due to integration errors or inadequate dynamic range. Another form of spectral representation is the proportional bandwidth spectrum, in which the frequency bandwidth of each band is proportional to the center frequency of that band. The two most common forms are the octave band (in which each center frequency is double the previous frequency, or an octave) and the one-third octave band (in which there are three proportional bands per octave and the bandwidth is 23 percent of the band center frequency). Proportional bandwidth spectra may be obtained either directly or indirectly. The former involves using a spectrum analyzer containing multiple parallel one-third octave band filters. Many of the previously listed bullet items that apply to FFT spectra may also be applied here, though the concept of windowing functions does not apply. The spectra may also be obtained indirectly by first carrying out an FFT measurement and then transforming the constant bandwidth spectrum into a proportional bandwidth one. This process is called “synthesis” and is described in Amick and Bui4 and Amick.5 This allows a single measurement to offer the level of detail required for diagnostic efforts as well as a simpler spectrum for characterizing how a vibration might affect a tool. Sound spectra are most often obtained directly, though the use of spectrum analyzers designed for this purpose. Octave band spectra are the most common, but one-third octave band and narrowband acoustic spectra are used in some instances. A third form of data representation used in acoustics is the single-value quantity, such as the Aweighted sound level, commonly denoted with units of dBA. There are several standard “weighting” curves—the most popular being A and C—which are used to emphasize content at some frequencies and de-emphasize it at others. A-weighting is used to simulate how the human ear perceives sound at moderate amplitudes, de-emphasizing content at low frequencies. The most important shortcoming of A and C weighting in measurements pertaining to tools is that it is impossible to extract frequency characteristics from the data.2 As we have noted, building site and production or research environment vibration and noise can be classified as steady-state random much of the time. For this reason and due to the frequency dependence of tool vibration sensitivity, basic analysis and representation of vibration and noise environments in advanced technology facilities is usually in the frequency domain, represented as an average (for steady-state vibration) or a maximum (for transient vibration) value, and using a constant narrow bandwidth that may later be simplified in wider bandwidth formats for comparison with specific tool specifications or generic criteria. The use of PSD is not recommended when there are significant tonal components in the vibration environment. 39.2.2 Criteria—Equipment-Based Criteria Versus Generic Criteria There are several ways to approach criteria selection for the project. When the facility is being designed for specific analytical tools and when the manufacturers can provide reliable criteria for these tools, engineering may be carried out accordingly. However, in most cases, specific requirements are often not identified or are not available at the time of initial design (especially at the time floors are designed), or perhaps may not be known until after building commissioning. They may also change in the future. In these cases, it is common practice to use in the design one or several generic criteria, which may conservatively represent entire classes of tools. This practice lends itself to improved flexibility over the life of the facility, presuming this is useful. (One might argue that if a facility is unlikely to be renovated then a tool-specific design might be more cost-effective than a design based on generic requirements, but in most cases it is hard to make a prediction of this sort with a great deal of certainty.) 39.2.3 Criteria—Generic Vibration Criteria VC Vibration Criteria. The most popular generic vibration criteria are those developed in the early 1980s by Ungar and Gordon,7 originally known as the BBN Curves. They are now denoted as VC-n, where n is a letter from A through G. VC-A has a nominal velocity amplitude of 50 µm/s Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.6

MICRO-VIBRATION AND NOISE DESIGN FAB YIELD, OPERATIONS, AND FACILITIES

10000

Workshop (ISO)

1000

Office (ISO) Residential day (ISO) rms velocity, µm/s

39.6

Operating theater (ISO)

100

VC-A (50 µm/s) VC-B (25 µm/s) VC-C (12.5 µm/s) 10

VC-D (6.25 µm/s) VC-E (3.12 µm/s) VC-F (1.56 µm/s) VC-G (0.781 µm/s)

1

0.1 1

10 One-third octave band frequency, Hz

100

FIGURE 39.1 Graphical definition of VC criterion curves.8 (Courtesy of the Institute of Environmental Sciences and Technology (IEST), Rolling Meadows, Illinois, www.iest.org.)

or 2000 µin/s. The amplitude associated with each subsequent letter is one-half the amplitude of the previous letter. These criteria have been published in numerous places, including Recommended Practice RP-12 of the Institute of Environmental Sciences and Technology.8 The generic VC criteria were developed to represent the requirements of “families” of equipment or “process geometries.” They tend to form a lower bound for all equipment of a particular type working at a particular feature size. Thus, a facility designed generically for a process at 0.1 µm will be more likely to work for all tools working at that geometry than one designed specifically for one tool at that geometry, if that tool is not the most sensitive one of its kind. The VC curves have recently undergone some modifications, which change the shape of the more stringent curves,* and add several more stringent curves for use in characterizing ultraquiet research spaces. The newer form is shown in Fig. 39.1 and tabulated in Table 39.1. The criteria are to be applied to data represented in rms velocity amplitude, as determined in one-third octave bands. Extensive discussions of technical and historical perspectives of the VC curves may be found in Gordon10 and * This change makes the VC curves more consistent with the recommendations of Ungar, Sturz, and Amick (1990),9 and better accommodates tools whose vibration sensitivity is based upon the performance of internal vibration isolation.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.7

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.7

TABLE 39.1 Numerical Definition of VC Criterion Curves8 Criterion VC-A VC-B VC-C VC-D VC-E VC-F VC-G

Definition 260 µg between 4 Hz and 8 Hz; 50 µm/s (2000 µin/s) between 8 Hz and 80 Hz 130 µg between 4 Hz and 8 Hz; 25 µm/s (1000 µin/s) between 8 Hz and 80 Hz 12.5 µm/s (500 µin/s) between 1 and 80 Hz 6.25 µm/s (250 µin/s) between 1 and 80 Hz 3.12 µm/s (125 µin/s) between 1 and 80 Hz 1.56 µm/s (62.5 µin/s) between 1 and 80 Hz 0.781 µm/s (31.2 µin/s) between 1 and 80 Hz

Amick.5 The International Standards Organization (ISO) recommended criteria for workshops, offices, residences, and operating theaters also shown in Fig. 39.1 are discussed in ISO 2631.11 NIST-A Vibration Criterion. A special vibration criterion was developed for the design of the Advanced Measurement Laboratory (AML) at the National Institute of Standards and Technology (NIST) in Gaithersburg, Maryland. It has become popular for application in some of the more demanding spaces in nanotechnology research facilities such as those used for imaging and molecular manipulation. The NIST-A criterion was based on two considerations. At low frequencies, some of the ultrasensitive metrology research was thought to be sensitive to vibration characterized by a constant value of displacement (as opposed to the constant velocity associated with the VC curves). At higher frequencies, the sensitivity of other processes was thought to be more consistent with the constantvelocity criterion VC-E. Thus, the NIST-A criterion may be defined as follows: 0.025 µm (1 µin) displacement for 1 ≤ ƒ ≤ 20 Hz and 3.1 µm/s (125 µin/s) velocity for 20 ≤ ƒ ≤ 100 Hz. This criterion is defined in terms of rms amplitude, using one-third octave bands of frequency. 39.2.4 Criteria—Floor Dynamic Stiffness Requirements Many photolithography tools such as steppers involve positioning mechanisms so that a wafer can be positioned at predetermined locations for photolithographic exposure. However, the wafer is usually stationary during the important operation, with settling time allowed after each positioning. They generate internal vibrations by their own internal positioning systems but come to rest for exposure, and are thus dependent only upon the ambient vibration environment. On the other hand, some of the newer photolithography tools, called step-and-scan systems (or scanners), increase throughput and resolution (i.e., smaller linewidths) by carrying out the critical lithography operation “on the fly” while both reticle and stage are moving. The motion during exposure must be exquisitely smooth. In order to achieve this, a control system generates dynamic positioning forces to coordinate the positions of the reticle and stage. Those forces must be resisted by the structure supporting the tool. As a result, tool manufacturers specify “resistance” characteristics in addition to ambient vibration requirements. Those resistance characteristics are stated in terms of accelerance (the FFT of response acceleration divided by the FFT of the causative force) or mobility (responsive velocity divided by the force) or dynamic stiffness (causative force divided by response displacement). The dynamic measurements involved and the consequences for building designers were explored by Amick and Bayat.12 In addition to scanners, other tools used in advanced technology production and assembly, such as laser drills, may have foundation dynamic stiffness requirements that must be considered in the design of the building. 39.2.5 Other Forms of Vibration Criteria There are other, less common forms of vibration criteria, including those involving time domain and others involving response spectra. It should be noted that time domain criteria are subject to the same caveats as time domain data representation: there is no consideration of frequency content. Vibrations at all frequencies are given equal importance and the importance of resonance response is disregarded. For further discussion, see Ref. 10. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.8

MICRO-VIBRATION AND NOISE DESIGN 39.8

FAB YIELD, OPERATIONS, AND FACILITIES

39.2.6 Generic and Tool-Specific Acoustic Noise Criteria Acoustic noise may be regulated with respect to impact to tools and to people. In the latter case, there are several established and commonly used families of rating curves available as octave band spectra, such as the NC (or NCB1), RC1, and NR curves.13–15 These curves are based on empirical data derived from perceived differences in noise levels and are generally shaped in frequency in accordance with the human perception of balanced noise spectra. In addition, the single-value indices mentioned earlier (such as dBA and dBC) are sometimes used, but only in certain limited cases such as in compliance with occupational health standards or environmental noise regulations. Due to the lack of definition of relative frequency amplitudes, single-value indices should not be used in the design of regularly occupied interior acoustic spaces. There are currently no generic noise criteria for tools. The generic perception-based criteria have often been used for this purpose, which has the benefit of giving architects and mechanical engineers a first indication of the level of effort that will be required in the acoustic design, although there is no physical basis for it. Tools are not sensitive to noise in the same way humans are (although it may be arguable that there are some similarities). The design of acoustic spaces housing them must, at this time, be based on the specific and tested sensitivity characteristics of the tools. As tools are generally sensitive to noise as a function of frequency, similar to the way in which they are sensitive to vibration, tested tool noise sensitivity curves must be provided as a function of frequency. The use of a single-value acoustic criterion (such as dBA or dBC) is generally discouraged for tools, because it provides no information regarding the frequency distribution of a tool’s sensitivity.2 The following paragraphs give an example of the range of criteria used in semiconductor production facilities and other advanced technology buildings, in both the technical (cleanrooms, laboratories) and nontechnical (conference rooms, offices) areas. These comments are expressed in terms of the NC criteria, but comparable referents from the other families of curves may be substituted in most cases. For ISO Class 1 to 5 cleanrooms, it is difficult to achieve HVAC noise levels of better than NC55 to NC-60 due to the extreme air movement requirements. Lower noise levels may be achievable in cleanrooms of reduced cleanliness requirements, depending on the type of air movement systems used. For traditional laboratories, criteria of NC-45 (with fume hoods) and NC-40 (without fume hoods) are common, but it is not unusual to require much more stringent criteria for very sensitive nanotechnology work, perhaps on the order of NC-25. Table 39.2 lists typical noise criteria for some common room functions. These criteria are generally provided with respect to noise impact to personnel, so it should be noted that certain laboratories may contain special tools or processes that will require a lower background noise than what is noted above. Occasionally the generic criteria are modified to provide more stringent requirements at low frequencies. There is, however, a limit to the amount of laboratory test information available on the

TABLE 39.2 Typical Room Noise Criteria (NC)13,16,17 Room function

Typical NC ranges

Cleanrooms (ISO Class 1 to 5) Probe–test Computer rooms Corridors and public circulation areas Laboratories with fume hoods Laboratories without fume hoods Open-plan offices Private offices Conference rooms Auditoria Teleconference rooms

55–60 55–60 40–50 40–45 40–45 35-40 35–40 25–35 25–30 25 25

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.9

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.9

acoustic properties of materials (sound transmission and absorptive qualities) and noise control devices (e.g., silencers, absorptive treatments, and wall designs), at frequencies below 63 or 125 Hz. However, sensitivity to infrasonic noise (at frequencies less than 100 Hz) does occur occasionally. It may need to be addressed in the design stage, as the special designs required are not easy to retrofit into traditional laboratory spaces later. Early in the project it must be clarified where and how the noise criteria will be applied, with respect to people and tools. The criteria may be applied to the space-averaged noise level measured in the room or at specific locations in the room. Failure to provide this clarification early may lead to conflicts near the end of the project. These criteria are often intended to apply to HVAC noise sources only. On occasion, they may be applied to other sources, such as the room noise level due to external noise sources (such as aircraft and traffic) or due to known equipment in the room. This must also be explicitly identified in the programming design documents. 39.2.7 Measurement Instrumentation (Including General Range of Tool Sensitivities) The extremely stringent environments required in some advanced technology facilities place high demands on the capabilities of the instrumentation required to accurately characterize them (as well as the operator of the equipment). This equipment includes spectrum analyzers and other data recorders, transducers (such as accelerometers, velocity sensors, and microphones), conditioning amplifiers, and the associated cabling. There are particular challenges in measuring environments that require characterization at very low amplitudes and very low frequencies, which implies that the measurement equipment should have very low internal system noise levels. It is preferred that the instrumentation be capable of accurately measuring substantially lower vibration amplitudes than the criteria or the ambient amplitudes. Other advanced technology environments will have less stringent requirements (e.g., most areas in LCD-TFT or crystal growth facilities and semiconductor process support areas) and consequently, somewhat less sophisticated equipment may be employed in their characterization. Similarly, acoustic measurement instrumentation must be compatible with the environment to be measured. Instrumentation of “ANSI Type 1” quality18 is usually adequate, as long as the frequency and dynamic ranges of the microphone, preamplifier, and spectrum analyzer are compatible with the required frequency range and noise level of the environment to be characterized. It is important that the instrumentation operator has enough experience to be able to identify the best methodology with which to characterize a variety of environments and to recognize faults and limitations in the measurement instrumentation. The particular challenges in measuring very low frequency vibration and noise must be understood. This cannot be emphasized enough. Several times the authors have been called in to solve “problems” in facilities that were represented previously by inexperienced technicians with a measurement of the inappropriately high noise floor of their measurement instrumentation. The instrumentation should be calibrated regularly using reference standards traceable to appropriate national standards organizations (e.g., NIST in the USA or NPL in the UK).

39.3 VIBRATION AND NOISE SOURCES 39.3.1 Site Vibration Sources The vibration environments of all potential building sites for advanced technology research are limited to varying degrees by groundborne vibration from a variety of potential sources: microseismic activity, transportation, other nearby facilities containing mechanical equipment, and so on.19 Gordon20 examined the effects of locale on site vibrations showing that proximity to developed areas also impacts the vibration environment.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.10

MICRO-VIBRATION AND NOISE DESIGN 39.10

FAB YIELD, OPERATIONS, AND FACILITIES

A site vibration survey is generally recommended for any facility with requirements more stringent than that in VC-C, or when the site is proximate to a source of high vibration, such as a railroad. It is important that the survey be conducted by experienced personnel using instruments with appropriate sensitivity.21 The survey can identify potential vibration-related problems at the site and whether the site is compatible with the vibration requirements of the proposed facility. Consideration of the site conditions is critical, because the future building owner may not have control over them (in contrast to sources within the building). In addition to existing conditions uncovered in the site survey, potential future impacts, such as construction, changes in transportation routes, and potential future changes in adjacent land zoning must be considered in the site selection process. 39.3.2 Vibration Sources Within the Facility There are myriad sources of vibration in an operating fab or research facility. Air handling devices and pumps are part of any technological building, as are the associated ducting and piping. These are under the purview of the facility designer and are discussed in a later section of this chapter. However, there will also be interior sources that are not addressed by the building designer, because they are put in place after the facility is complete. Gendreau and Amick22 discuss the issue of maturation, which generally involves mechanical equipment (such as dry pumps) installed in connection with individual tools. Over the life of a facility, these sources can have a deleterious effect. It is not economical to design a building to prevent their impact; rather, it is incumbent upon users and facilities staff to be vigilant and treat these sources appropriately with layout and vibration isolation measures. 39.3.3 Noise Sources Most of the noise that impacts sensitive tools and people has its source within the building, but occasionally external noise sources must be considered. Aircraft can be particularly troublesome to tools sensitive to low frequency noise and to conversation in inadequately designed labs, conference rooms, and offices. Vehicular traffic may have to be considered in some cases. Impact from external sources can be treated in the building layout and shell design, but at certain sites, such as near an airport under a flight path, this can be prohibitively costly. Internal noise sources include building mechanical and electrical equipment and the activities of people. Noise from these sources can be transmitted via air- or duct-borne paths or via structureborne paths. The process and research tools can also be significant sources of noise, and the concept of maturation or deleterious effects with the installation of tools and ageing of mechanical equipment also applies from an acoustic standpoint. Strategies for the control of these noise sources are discussed in subsequent sections of this chapter.

39.4 FOUNDATION AND STRUCTURAL DESIGN 39.4.1 Soil and Foundation Design (with Respect to Environmental and Local Sources) Especially with respect to very low frequency vibration, there are limitations to the amount of improvement of the site ambient conditions that can be designed into the building foundations. In addition, due to the extreme complexity in characterizing site specific soils in the soil-structure dynamic interaction, the accuracy of predicting these effects is quite limited unless this can be improved with site-specific test data. Nevertheless, there is enough test data in the literature from which one can draw some general principles: • The presence of a building on a site will suppress some of the vibrations observed in a vibration survey at an undeveloped site. This effect is frequency dependent and is difficult to quantify, though it appears that pile foundations may enhance attenuation in some frequency ranges.23

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.11

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.11

• A solid slab will attenuate about 25 to 50 percent at most frequencies above 10 Hz. There is little difference between the three directions (vertical and two orthogonal horizontal axes).23 • The use of a structural isolation break (SIB) in an on-grade slab will generally not improve performance significantly when the slab is the same thickness on both sides of the SIB, particularly if an “island” is created. It has been observed that vertical vibrations may decrease above a certain frequency associated with the slab thickness, but horizontal vibration amplitudes may increase. If an island is created that is significantly thicker than the surrounding slab, then there may be attenuation in all three directions.23 • Vibration resistance is maximized if a slab or foundation is underlain by a soil with a high dynamic subgrade modulus. This is achieved through the use of (1) dense virgin soil, (2) well compacted engineered fill, or (3) well-densified granular fill.24

39.4.2 Process Floors The structural design of the floor that will support the vibration-sensitive equipment is of paramount importance in achieving a good quality of vibration performance. Low-vibration structures can be constructed of concrete, steel, or combinations of the two. There are two generic floor concepts used in fab design: 1. Slab-on-grade, where a concrete slab is placed directly on the soil. 2. Suspended floor, where the floor is suspended on columns or trusses. • The floor structure is usually of concrete and may be of several generic types: • “Waffle” slab, which provides a flat surface on the top (or “topping” slab) and a pattern on the bottom that resembles a waffle, with some portions thicker than others. The thicker parts form a two-way framework of members that resist bending. There may be openings (or potential openings) for piping and other connections between the fab and subfab. • “Grillage,” which has been described as a waffle without a topping slab. It is open on the top and consists simply of beams running in two directions. This allows air to flow through the floor. • “Flat” slab, which is simply a slab of constant thickness. Post-construction penetrations pose challenges, as the reinforcement should not be cut during coring. • “Cheese” slab, which is a flat slab with cylindrical penetrations created with tubular forms at the time the concrete is poured. • Support may be provided in either of two ways: • Columns supporting the floor can form a direct path to the ground. This provides the stiffest floor, but limits the flexibility of the space beneath the floor (subfab). • The floor may be supported on a long-span steel truss and there may or may not be columns between the floor and the truss. This provides a space beneath the floor that is free of columns and is a popular approach for the support of the upper process floors in the design concept known as the “stacked fab” and in LCD-TFT factories that require several process levels. Suspended Floors. The design of suspended floors and the types of vibration sources that control their performance largely depends on the nature of the space being supported. Table 39.3 identifies typical structural design approaches to achieve various criteria.25 The design elements mentioned in Table 39.3 primarily address vertical vibration performance. For stiff suspended floors, input from the vibration consultant to control the horizontal performance (for example, using shear walls, or moment framing) is also critical. For less stringent floors, the horizontal performance is usually dictated by the requirements of the structural engineer, although the vibration consultant will typically review this.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.12

MICRO-VIBRATION AND NOISE DESIGN 39.12

FAB YIELD, OPERATIONS, AND FACILITIES

TABLE 39.3 Generic Criteria Assignable to Advanced Technology Spaces and the Structural Approaches to Achieving Them25 Space type

Criterion

Structure

Research offices, computer modeling

ISO office

9- to 12-m spans, column or truss support, concrete slab on moderate-depth steel or concrete framing

Generic laboratory space, optical microscopes, epitaxy tools and ion implanters, CVD, CMP

VC-A/B

6.5- to 10-m spans, column or truss support, concrete slab on deep steel or concrete framing

Photolithography, nanofabrication

VC-D/E

Slab-on-grade; or concrete waffle or open grillage with 3.5- to 5-m column spacing

Metrology, surface characterization, SEM, SPM, AFM

VC-E or NIST-A

Slab-on-grade (NIST-A or VC-E); or concrete waffle or open grillage with 3.5- to 5-m column spacing (VC-E only)

The vertical vibrations of fab floors may be excited by two types of loading. Vibrations may be generated by personnel walking (or other related activities) and they may be generated by the mechanical systems within the building (equipment, piping, and ductwork). In general, the vibration performance of floors with less stringent requirements (e.g., VC-A and VC-B) will be governed by walkers. The performance of “stiff” floors intended to achieve the more stringent criteria (e.g., VCD and VC-E) is more likely to be governed by mechanical systems. An exception is in the case of the massive automated material handling systems (AMHS) used in LCD-TFT production, which generate transient forces high enough to significantly excite any of these floor types. Design of fab floors for walker-generated vibrations is usually approached using a derivation attributed to Ungar and White26 (1979), which is most readily accessible in Chap. 6 of a publication from the American Institute of Steel Construction (AISC),27 even though it is equally applicable to concrete floors. That approach may be expressed as Eq. (39.1) Vw =

Cw kf

(39.1)

where Vw = amplitude of vibrations generated by the person walking k and f = floor stiffness and resonance frequency, respectively Cw = parameter that accounts for the characteristics of the footfall loading including walker weight and speed Design of floors for mechanically generated vibrations may be approached using a model developed by Gordon28 based upon the observed statistical performance of actual fab floors.* The vertical vibrations are represented by Eq. (39.2). Generally the frequency associated with this vibration is the vertical fundamental frequency of the floor, usually between 10 and 50 Hz for stiff floors. The stiffness used in this model is the point stiffness at the middle of a typical structural bay (centered between four columns), which is usually the location with the lowest stiffness. VV =

*

CM k

The statistical methods associated with Gordon’s model are discussed in Ref. 29.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

(39.2)

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.13

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.13

where VV = rms amplitude of vertical vibration (in one-third octave bands) k = floor stiffness CM = an empirically derived coefficient based upon the statistical analysis Gordon’s model predicts horizontal vibrations by Eq. (39.3). The frequency associated with this amplitude is the horizontal (sway) frequency of the floor, usually between 2 and 8 Hz. The stiffness is calculated from the combined effect of columns, shear walls, and any other structural components resisting lateral movement, and typically requires a computer model of the structure. VH =

CH k

(39.3)

whereVH = rms amplitude of horizontal vibration (in one-third octave bands) k = global stiffness of the structure supporting the process floor in the horizontal direction CH = an empirically derived coefficient Design of Floors Subject to Walker Vibration Impact. As noted above, relatively soft floors (VCC and less stringent) tend to be more easily excited by the activities of personnel than by mechanical systems. The degree of impact of a walker is a function of the walker’s weight, speed (usually expressed as “pace rate” or paces per minute), gait, footwear type, and other factors. Before the structural design based on walker impact can begin, the location of the source (person) and receiver (tool) within a bay or bays must be determined. Otherwise, the impact is calculated in the worst-case condition, that is, walking at a relatively fast pace (say 100 paces per minute) immediately adjacent to the tool, assuming both to be located near the center of a bay. However, less conservative assumptions may be used in some instances to reduce project costs, if the relevant details are known. Some of these considerations are as follows: • Walker speed: It is typical to assume a walker speed on the order of 100 paces per minute for “high speed” corridors. These are generally the straight, wide, general building corridors containing traffic outside the work area over which the tool user has no control. Quite often they have walls. From the standpoint of vibration control, it is preferable that high speed corridors be separated from lab areas by at least one column line. For “ghost corridors,” which typically parallel high speed corridors but are inside the work area, it is common to assume a slower speed in the design, say 85 paces per minute, because the walker will exercise some care to avoid tools and other workers. For “low speed” corridors, generally obstructed areas in bays and between tools, one may assume even lower speeds, on the order of 70 to 85 paces per minute. The affected users generally have more control over the traffic in the two latter cases. • Walker weight: One may wish to consider the local or international average body weight. • Position of walkers and tools on the structure: For layouts that are uniform with respect to the structural layout (such as column positions), one may wish to account for the relative stiffness of the bay at the position of the walker and/or tools, especially if either of these are always located anywhere other than at mid-bay. The prediction of walker-generated floor vibration amplitudes is an inexact science. Experimental studies have demonstrated that the variability of amplitudes generated by a “standard” walker (85 kg at 100 paces per minute)—going to great lengths to maintain consistency—leads to a standard deviation of about 30 percent. When we consider a larger population at the same speed, the variation in footwear, gait, and so on, leads to a standard deviation of over 50 percent, even when there is a correction for variation in weight. On-Grade Floors and Engineered Fill. The vibration performance of an on-grade floor depends on the site ambient vibration conditions, soil conditions, foundation type, and slab thickness. One key to good performance of an on-grade slab is the nature of the soil beneath it. The ideal condition

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.14

MICRO-VIBRATION AND NOISE DESIGN 39.14

FAB YIELD, OPERATIONS, AND FACILITIES

would be to have a quiet location and support the slab directly on bedrock or stiff virgin (undisturbed) soil. However, this is generally not possible. In many cases, it is necessary to fill in surface irregularities, which can be quite substantial in some cases. In other cases, it is necessary to have a granular drainage layer beneath the slab to prevent hydrostatic uplifting of the slab. If imported fill is required, it should be examined by a soil engineer to ensure that it is of adequate quality and has dimensional stability. If it can be characterized as “engineered fill,” it should be compacted to 95 percent of the maximum dry density as determined by the Modified Proctor Test, ASTM D-1557. If the fill material is granular for the purposes of drainage or leveling, then the above specifications are irrelevant. In that case, it is desirable to have the maximum possible densification of the material, to be specified by a soil engineer in a manner appropriate for the material being used. Structural Isolation Breaks. In general, there is a trend away from the use of structural isolation breaks (SIBs) in slabs, whether on-grade or elevated. This shift in position has been based upon a growing collection of data suggesting—for frequencies less than about 40 Hz—that the positive contribution of an isolation break is minimal and may actually be harmful. In on-grade slabs, the only purpose an SIB serves is to attenuate high-frequency vibrations and not the low-frequency ones of primary concern. The low-frequency vibrations propagate through the soil. The reason for shifting away from the use of SIBs in this case is that they can actually make the horizontal vibrations worse if they are isolating too small a segment, and the isolated slab is of a thickness similar to that of the surrounding slab. All things considered, the solid slab is better than a jointed slab (or “island” in a larger slab) at the frequencies generally of concern for sensitive equipment and processes. However, at higher frequencies, particularly audible frequencies, they may be quite beneficial.* There are a few notable exceptions to this position regarding slab breaks. One of these is NIST’s Advanced Measurement Laboratory completed in 2004 at NIST’s campus in Gaithersburg, Maryland. A great deal of thought and negotiation went into the decision to use slab breaks in the underground metrology wings, where the criterion was NIST-A or better. With this approach (including the effect of depth), the floor achieved excellent performance. The following issues were considered: • The slab-on-grade is 14 m below the surrounding surface elevation, thus the horizontal component of surface waves is much smaller. • The users were very concerned about what was dubbed the “dropped hammer” condition, wherein a neighbor dropped a hammer and the high-frequency impulse generated in the concrete propagated through it and affected a neighbor’s space. • The users felt that the corridor traffic would not have a significant effect, except for large rolling loads (with hard wheels) and “dropped hammers.” They required large rolling loads (such as nitrogen dewars) to have pneumatic tires. Very stringent (and expensive) slab flatness requirements were also imposed. • The users acknowledged the deleterious effect of small slabs and compromised on slabs that were at least two lab-modules in extent. If they were going to be bothered by a neighbor’s “dropped hammer,” it would only be one neighbor. No isolated slab cutouts were smaller than two lab modules unless specific reasons (such as pits) dictated them. Another exception is the positive experience—in numerous locations—of thickened “islands” for the support of electron microscopes and other highly sensitive imaging systems. The best practice appears to be one in which the island—the isolated part—is very thick with respect to the surrounding slab (e.g., a 900-mm thick island in a 300-mm slab.). Support Floor Design for Source Mitigation. In the structural design, in addition to the design of the critical floors that will support vibration-sensitive equipment, it is important to consider the design * Portions of the studies on which this position is based have been published. The effect of SIBs on suspended slabs is discussed in Sec. 7 of Ref. 30. The effect on slabs-on-grade is discussed in Ref. 23.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.15

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.15

of the support and other floors that will carry mechanical and personnel loads. Typically, these floors are designed first by the project structural engineer to carry the design live load and in most cases, this is adequate to serve the vibration design as well. However, many cases are documented where in the vibration transmission from support areas was exacerbated by floor resonances. It is therefore recommended that these supplementary floor designs also be reviewed by a vibration consultant. In particular, the following should be considered for support floors within or near the sensitive building: • The fundamental resonance frequencies of the support floor systems (the composite system and components such as slabs and columns) should be designed such that they do not match with the fundamental rotational speed of supported mechanical equipment. For example, when designing a fan deck floor containing large fans rotating at 900 rpm, it would be best to avoid designs with a fundamental resonance near 15 Hz (equivalent to 900 rpm). Note that the same consideration is necessary for process floors that will support vibration generating tools, such as implanters, CMP tools, polishers, and assembly tools. • Likewise, floors or structures supporting mechanical equipment should be stiff enough to provide adequate impedance to allow any vibration isolation systems supported on the floor to function properly. The degree to which the support floor designs are critical depends on their proximity to vibrationsensitive areas and whether they are separated by isolation breaks (to the degree that these provide a benefit, as discussed earlier).

39.5 VIBRATION AND NOISE CONTROL IN THE MECHANICAL/ ELECTRICAL/PROCESS (MEP) DESIGN No structural design will perform well with a poor mechanical design. Furthermore, it is not cost-effective to provide an excessively stout structural design with the intent that the mechanical design will be less relevant. The most cost-effective (and historically successful) method is to provide a balanced structural and mechanical design. With this in mind, in the structural design a specific quality in the mechanical design must be assumed. Critical aspects of the MEP design quality are discussed in this section. 39.5.1 MEP System Layout The layout of the MEP systems is particularly important. From the standpoint of vibration impact, the best design adequately separates vibration-generating equipment from vibration-sensitive areas. As it is used here, adequately separate means that enough “natural” attenuation of the vibration forces is provided by radiation and material damping (i.e., in the soil or building structures) in the horizontal and vertical path between the source and the receiver. This type of vibration reduction is separate from that provided by vibration isolation hardware, assuming that these are not required for adequately separated sources. In this design philosophy, isolation hardware, as discussed below, may be considered a compromise that effectively reduces the required separation distance, but at the cost of increased maintenance and amplification of vibration at the isolator resonance frequency, when this is relevant. Of course, long separation distances are not always practical due to the increased cost in building footprint and piping, thermal losses, and for other reasons, and therefore the use of isolation hardware may become a more desirable compromise. In addition, it may not be possible to isolate certain equipment (e.g., vibration-generating process tools), and adequate separation may be the only practical means of isolation other than selecting the source and receiver equipment for compatibility. General Layout. The natural vibration attenuation (or amplification) provided in a building structure is a function of the specific structural design. The use of generic “rule-of-thumb” vibration transfer

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.16

MICRO-VIBRATION AND NOISE DESIGN 39.16

FAB YIELD, OPERATIONS, AND FACILITIES

functions (e.g., “transfer mobility” *) are likely to cause either overdesign or underdesign of the MEP vibration control, which is in either case costly. It is possible, however, to calculate transfer mobilities within a building with a fairly high degree of accuracy using finite element analysis (FEA) methods, as long as the contribution from the soil-structure interaction is secondary. Calculations of paths involving the site soils are more accurate when supplemented with empirical propagation and soil stiffness data from the specific site in question. These considerations influence the MEP layout in a vibration-sensitive building, in addition to the specifics of the vibration sources, that is, the forces generated (a function of the dynamic balance of the equipment and its internal support structures), number of sources, source locations, presence of external isolation hardware, and other details. In general, the structural analysis or experience of the vibration engineer will identify the amount of mechanical energy that can be applied to various locations within or nearby the vibration-sensitive structure. Uncertainties (e.g., those due to the specific dynamic balances or anomalous operating conditions, or those that arise with the use of vibration isolators) may dictate the application of a reasonable amount of conservatism to ensure that the impact to the sensitive floors is within acceptable amplitudes even under temporary unusual conditions. For example, the design of a specific structure may reveal such things as: (1) the path attenuation from the subfab is less than from the fan deck, (2) a small amount of horizontal separation from the building provides significantly more attenuation than when sources are located directly below the process floor, or (3) vibration from piping attached to the process floor support columns is better attenuated than vibration from piping attached directly to the underside of the process floor. These sample concepts, while true in most cases, are but examples of design considerations verified and informed by a detailed structural analysis. 39.5.2 Recirculation Air Systems Recirculation air systems could in some ways be considered the nucleus of the cleanroom MEP system, as their presence and proximity define the degree of cleanliness achievable in the space. To prevent air (and hence energy) losses and reduce contamination, they must be immediately adjacent to the cleanroom. Yet this very concept is in opposition to vibration and noise goals. Nevertheless, with good design practice, several types of recirculation air systems have been effectively employed in semiconductor and other advanced technology facility designs: • Packaged centrifugal or plug-type recirculation air handling (RAH) units: This system usually requires a moderate number of units, typically ranging in flow rate from 4000 to 120,000 m3/h per unit, most often installed above the cleanroom on a fan deck. Each unit is self-contained, containing the fan/motor assembly, temperature and humidity control devices, and noise and vibration control hardware. Noise control features include special lining materials, “dump walls” (devices to block line-of-sight from the inlet or outlet to the fan wheel), silencers, fan wheel size selection, and fan inlet flow straightening devices. Vibration control measures include isolation hardware under the fan/motor assembly within the cabinet, drive systems that allow improved dynamic balance (i.e., direct drive), and certain types of base designs. There are modular systems known as “fan tunnel units” and “fan coil units” that also fall into this category from the standpoint of vibration and noise. • Vaneaxial fan tower systems (VFT): This system normally requires fewer units for a given cleanroom design, typically ranging in individual flow rate from 45,000 to 450,000 m3/h. These systems are usually installed in a “tower” configuration at the outer edges of the cleanroom, most often with the fan axis in the vertical direction (although horizontal orientation also occurs). Temperature, humidity, noise, and vibration control are usually provided within the tower. This allows some flexibility in noise and vibration control. However, these systems are often found to be the most significant source of vibration and noise of the three recirculation air systems mentioned, all else being equal. Thus, they will require the most attention by the vibration and noise consultant. From the

* “Transfer mobility” is the velocity spectrum that arises at one location due to a unit dynamic force applied at another location. See Ref. 30 for further explanation.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.17

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.17

vibration standpoint, the problem is often due to the fact that these fans are located at the process level or one level below, which is usually more deleterious when compared with fan deck locations. Turbulent inflow conditions, often due to a “system effect,” since the intake path to these fans sometimes incorporates the building itself, can produce elevated noise levels. Usually, open coil spring systems are supplied for vibration control and passive or active/passive silencer systems are supplied for noise control. In both cases these may be integrated systems supplied by the fan manufacturer or custom devices designed for the project. • Fan filter units (FFUs): FFUs are autonomous units usually consisting of a small plug-type or centrifugal fan (often variable in speed, which is controlled at the unit or remotely) often operating in the 700 to 1,700 m3/h range, and a high-efficiency particulate air (HEPA) or ultra low penetration air (ULPA) filter at the discharge that is either 1.2 m × 0.6 m or 1.2 m × 1.2 m in area. Cleanroom ceiling grids are fitted out with FFUs in varying density depending primarily on the clean class required. FFUs rarely provide capacity for temperature control. Instead in cleanrooms using FFUs, temperature control is provided by external coils or by make-up air units containing temperature controlling elements. Unlike the other recirculation air handlers discussed, FFUs are normally not custom built. Often, hundreds of a manufacturer’s standard units are installed in a ceiling space. The small cabinet size provides fewer options for internal noise and vibration control, although most manufacturers have taken steps in this regard.* The use of an external silencer or vibration isolation is usually not feasible for FFU installations as their integral outlet filters make up the ceiling of the cleanroom. Therefore options for vibration and noise control are often limited to the selection of the varying performance of standard units by various manufacturers and by operating point selections.31,32 Based on this information and general industry experience, a few general conclusions can be given regarding recirculation air handler location and type selection: • The location of the units is critical. The best location will depend on the specific structural design employed, but it is often found that locating the units above the cleanroom level has its advantages, so long as the fan deck structural design avoids the fundamental operating frequency of the fans. • From a vibration standpoint, in order of the greatest challenge to the least, industry experience shows that these systems can often be ranked as follows: VFT, RAH units, and FFUs. This ranking not only accounts for the typical forces generated by the total number of units, but also typical mounting conditions and orientation and other considerations. Exceptions are possible, of course. • From a noise control standpoint, the three systems are almost alike, except that there are typically fewer options for the control of FFU noise. 39.5.3 Other Mechanical Equipment (Air Handlers, Compressors, Fluid Pumps, Vacuum Pumps, Cooling Towers, and the like) and General Considerations The aforementioned conditions regarding layout, dynamic balance quality, drive type, and isolation also apply to other types of building mechanical equipment. Some general design principles may be mentioned in addition: • Certain types of equipment in a particular class may be preferred. For example, a vertical in-line pump may generate less force at its base than an equivalent horizontal split-case pump. Rotary screw compressors certainly generate less disruptive vibration than equivalent reciprocating compressors. * From a vibration standpoint, the authors have yet to encounter a situation where the standard internal vibration isolation supplied with an FFU, usually a simple elastomeric isolator supporting the fan/motor assembly, was inadequate to control FFU vibration impact to vibration-sensitive floors located at lower levels [also see Ref. 31]. However, if the FFUs serving a cleanroom must be suspended from another vibration-sensitive floor above, more extensive isolation may be required.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.18

MICRO-VIBRATION AND NOISE DESIGN 39.18

FAB YIELD, OPERATIONS, AND FACILITIES

• The type of equipment used may influence the type of isolation required. To use the previous examples, the isolated horizontal split-case pump will certainly require an inertia base (as described subsequently), but the equivalent in-line pump may not. The reciprocating compressor, if allowable at all in a particular case, may require an inertia base mass of 5 to 10 times the supported equipment mass. (For well-balanced rotating equipment, an inertia base mass of 1 to 2 times the supported equipment mass is usually adequate). The structural design of the mechanical areas will have to take these loads into account. • The drive type (belt or gear drive versus direct drive) influences the practically achievable dynamic balance quality, and thus, the forces generated. In certain critical installations, only by the use of direct drive can the resultant forces be constrained to within manageable amplitudes. • Variable frequency drives should be configured so that they do not allow operation of the equipment at certain critical frequencies, such as at or near resonance frequencies in the equipment and support structure or floor. • It is not practical to design a facility such that one may locate any arbitrary mechanical load at any location within the building, even if it is provided with vibration isolation. Areas with compliant transmission paths to the process area (e.g., subfabs, the process floor itself, and other areas depending on the design) can only accept a limited amount of mechanical force before causing excessive vibration. The extent of this will depend on the structural design. The placement of equipment and support conditions must be considered early in the conceptual design of the facility. 39.5.4 Piping and Ductwork Fluid flow in piping and ductwork generates vibration in proportion to the amount of turbulence in the flow. Turbulence is increased by obstructions in the flow (cross-sectional area changes, elbows, dampers, valves, and so on), but it is also a normal component in unobstructed flow, generally increasing in amplitude with increased flow rate and velocity.33 For this reason, it is necessary to put restrictions on the flow velocity, size, support condition, and location (all mutually dependent variables) of piping and ductwork within vibration and noise sensitive facilities. Flow turbulence is generally broadband in nature, producing energy at a wide range of frequencies. Figures 39.2 and 39.3 show the change in vertical and horizontal vibration amplitude, Narrowband data (bandwidth = 0.375 Hz) 100

rms velocity, µm/sec

Pumped water system on Pumped water system off 10

1

0.1

0.01 0

10

20

30

40

50

60

70

80

90

100

Frequency, Hz FIGURE 39.2 Vertical vibration on stiff floor due to fluid flow in piping (average-plus-onestandard-deviation of 10 locations distributed over the floor).

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.19

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.19

Narrowband data (bandwidth = 0.375 Hz) 100 Pumped water system on

rms velocity, µm/sec

Pumped water system off 10

1

0.1

0.01 0

10

20

30

40

50

60

70

80

90

100

Frequency, Hz FIGURE 39.3 Horizontal vibration on stiff floor due to fluid flow in piping (average-plus-onestandard-deviation of 10 locations distributed over the floor).

respectively, on a floor with a pumped water system powered on and off. This particular building had inadequately isolated piping systems attached to the underside of most of the floor bays and thus easily excited the entire floor structure. Note the range of excitation frequencies, and that the structure is most strongly excited at its resonance frequencies (20 to 45 Hz vertical and 7 to 8 Hz horizontal). Note in particular that the excitation reaches fairly low frequencies, and that these correspond with the horizontal modes of the floor. One may infer that the use of isolated piping supports with relatively high-frequency resonances (e.g., elastomeric isolators with typical resonances in the 7 to 20 Hz range) could be detrimental in this case. Thus, if possible, it is preferable to design the piping and ductwork systems so that isolation is not necessary. This is done by limiting the flow velocities and pipe and duct diameters and the use of rigid attachment to less critical elements of the structure, such as the columns and subfab floor. This ideal design may not always be possible, in which case attachment using high deflection (25 mm minimum) spring isolators may be practical, along with the requisite periodic inspection and maintenance. There are no generic “rules of thumb” for piping support. Support in each case must be determined by the vibration specialist based on the pipe and duct layout, diameters, flow velocities, structural design of the floor, and other details. The latter consideration may include determination of the capacity of the floor to resist mechanical excitation, which is a function of its stiffness with respect to the design criterion for the floor. 39.5.5 Central Utilities Buildings, Support Buildings, and Equipment Yards Locating mechanical equipment in areas remote from the vibration-sensitive areas has the potential advantage of large horizontal separation, thus requiring proportionally less isolation. In addition to the attenuation factors through the fab and support or Central Utilities Buildings (CUB), ground transmission attenuation will play a role. Vibrations through the ground are attenuated by distance, as discussed by Amick and Gendreau34 (although that presentation deals with construction-generated vibration, the same principles are applicable to mechanical vibrations from a CUB). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.20

MICRO-VIBRATION AND NOISE DESIGN 39.20

FAB YIELD, OPERATIONS, AND FACILITIES

From a noise standpoint, impact from separate utility areas to the sensitive areas is unlikely. However, the equipment located in these areas is typically extremely loud, and noise control considerations may be required with respect to occupational health and safety, and environmental noise regulations. 39.5.6 Electrical Equipment (Diesel Generators, CPS Systems, Transformers) Certain items of electrical equipment are significant sources of vibration and noise, such as emergency generators, continuous or uninterrupted power systems (CPS and UPS), and transformers. • Diesel emergency generators can usually be well separated from the sensitive areas by locating them in utility buildings. Nevertheless, as reciprocating machines, they generate significant unbalanced forces and the vibration impact must be considered. Furthermore, they are notorious sources of environmental noise. Most facilities use these to provide power to critical systems only and not to process equipment. Others may use large banks of generators to allow continuous processing during power shortages. In the former case, the generators will be less of an impact if periodic testing can be scheduled to avoid sensitive operating times in a research facility, but this is rarely possible for a continuously operating production facility. • CPS and UPS systems come in several varieties. The most innocuous are systems using banks of passive batteries, which have no impact to the building from the standpoint of vibration and noise. Other uninterruptible power supply systems use energized elements that must be adequately isolated from the sensitive areas. • Transformers generate noise and vibration at twice the mains frequency plus harmonics due to magnetostriction of the core elements. This may be relatively less problematic for several reasons: (1) many tools are less sensitive to high-frequency vibration; (2) high-frequency vibration attenuates at a relatively high rate in the ground and in structures; and (3) relatively simple low-deflection elastomeric isolators are effective at reducing high-frequency forces. Nevertheless the vibration impact must be considered, as well as the radiated noise, which can be particularly intrusive in certain cases. 39.5.7 Machine Dynamic Balance Requirements As already implied, the first order of vibration control is at the sources. The amount of vibration generated by a rotating machine is a function of its static and dynamic balance quality. The dynamic forces due to imbalance are variable, controllable by initial balance or rebalance during the life of the equipment, and they typically worsen gradually during normal operation. Thus, periodic reviews and maintenance of dynamic balance is required. There are several standards commonly referenced in high-tech building design that regulate balance quality. International Standard ISO 394535* lists several grades of balance classification for rigid and nonrigid (isolated) support. These are equated to vibration amplitudes measurable in various axes on the equipment bearing caps, which provides a convenient means of verification and monitoring. Generally, the higher quality balance requirements are necessary in semiconductor and other advanced technology buildings, especially for the larger equipment located in the process building near the sensitive areas. This is especially the case for densely packed centrifugal or vaneaxial recirculation air fans serving cleanrooms. For example, depending on the layout and isolation quality, tolerances in the high ISO “good” range (0.5 to 0.7 mm/s rms) might be used for “critical” fans near the sensitive areas, but the lower end of the ISO “good” range (1 to 2 mm/s rms) might be acceptable for other equipment found in smaller numbers such as major pumps, compressors, and small fans.

* Also often referenced is American National Standards Institute ANSI S2.41 (1985),36 which is in complete technical agreement with ISO 3945.35

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.21

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.21

The balance quality achievable is a function of the type of equipment, among other things. For example, significantly higher-balance qualities are achievable with direct-drive equipment than with belt-drive equipment. In the former case, speed control, if necessary, is by the use of a variable speed drive (an adjustment of the line frequency or waveform going into the motor). Belt drive and geared equipment also have the disadvantage of producing tonal vibration at several frequencies, whereas in a well-balanced and aligned direct-drive system the primary impact is at a single frequency related to the rotation speed. This issue is especially critical when the structural design attempts to account for the primary impact frequencies of the mechanical equipment by designing the structural resonances to avoid those frequencies. Finally, it is necessary to establish a preventive maintenance or machinery health monitoring program to control increasing vibration due to bearing wear and fouling, and more important, to prevent catastrophic failure. 39.5.8 Vibration Isolation Hardware When equipment cannot be located at an adequate distance from sensitive areas, vibration isolation hardware can reduce the transmission of vibration into the structure at selected frequencies. Transmitted vibration can also be radiated as noise from machine and architectural components and vibration isolation can also reduce this effect. There are many types of isolation hardware and their short-term and long-term effectiveness and maintenance requirements can vary dramatically by design. (They can also vary by accident if not properly selected, installed, and maintained.) Isolation Hardware and Systems. In the simplest terms, vibration isolators work by superimposing the response of a single degree of freedom spring-mass-damper system on the vibration or force spectrum of a source (machine, pipe, and so on.). The idealized response of a simple spring-massdamper system is shown in a plot of transmissibility versus the ratio of the forcing frequency to the undamped resonance frequency of the isolator in Fig. 39.4, for several values of damping. When the curve is above the unity transmissibility line, amplification is indicated, and attenuation (reduction) is indicated when the curve drops below unity transmissibility. The figure illustrates several important features of ideal isolators: • There is a relatively low-frequency resonance at which the transmitted vibration is increased, especially when the forcing frequency closely corresponds to the isolator resonance frequency (frequency ratio = 1). • Below resonance there is either amplification (transmissibility > 1) or unity response. • At frequencies greater than 2 times the frequency ratio, there is attenuation of the transmitted energy (transmissibility < 1). • With higher damping, the amplification at resonance is reduced, but with a corresponding reduction of attenuation at high frequencies. The typical damping factors shown are z = 0.005 for steel springs, z = 0.05 for neoprene, and z = 0.33 for a friction damped spring.37 The fundamental resonance frequency of the system is a function of the static deflection of the isolator, defined as follows: fR =

5 d

(39.4)

where d is the static deflection of the isolator in centimeters, defined as the difference between the unloaded and loaded height of the isolator. The static deflection of the isolator is a function of the isolator stiffness and the mass of the supported load, and is a common means of specifying the isolator performance or efficiency. Thus, isolators are useful when the primary vibration of the source—and the resonance frequencies of the critical building structures—are significantly higher than the isolator resonance frequency fR. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.22

MICRO-VIBRATION AND NOISE DESIGN FAB YIELD, OPERATIONS, AND FACILITIES

1000

100 Steel spring

Transmissibility

39.22

Neoprene pad

10

1.414 1

0.1

0.01 0.1

Friction-damped spring

1 Frequency ratio

10

FIGURE 39.4 Vibration transmissibility for idealized single-degree-of-freedom isolators with various damping coefficients.

The response of real isolation systems is more complex than the ideal response shown in Fig. 39.4. In general, their performance is degraded from the ideal curve due to several factors. These factors include other resonances in the supported system such as surge (longitudinal) resonances in steel coil springs and resonances in the supported equipment base or platform. The latter case includes the dynamic response of the supported equipment frame or inertia base and the compliance (resonance response) of the table structure of isolation tables. In addition, the compliance of the building structure that supports the isolated system can degrade the isolator performance. All of these effects tend to reduce high-frequency isolator attenuation at certain frequencies or in ranges of frequencies.38 Isolators are commercially manufactured of various materials and for a wide range of operating and environmental conditions. The most common types are elastomerics (e.g., neoprene, rubber, and fiberglass), steel springs, and pneumatic springs, described in more detail as follows: • Steel springs are often selected for their durability and relatively simple response, in static deflections ranging typically from 10 to 100 mm ( fR = 5.0 to 1.6 Hz). Damping at resonance is relatively low unless separate damping elements are used. High-frequency response is degraded by surge frequencies, but sometimes a neoprene isolator is used in series with the steel spring to improve isolation at high frequencies. • Elastomerics generally have a better damping response, with reduced attenuation at high frequency. The available static deflections are generally smaller for commercial systems, in the 1- to 10-mm range ( fR = 16 to 5 Hz). Hence, they tend to amplify at relatively high frequencies, and their isolation range

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.23

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.23

begins at a higher frequency. They are commonly produced in pad or “puck” form, or in the higherprofile form operating in shear. • Pneumatic isolators (sometimes known as air springs) are somewhat of a compromise between the other two types listed, typically consisting of a pressurized elastomeric vessel (analogous to a rubber tire) with a low resonance frequency ( fR = 1 to 2 Hz is common). These are available in commercial systems installed as units at the base of a vibration source or sensitive tool, or as elements contained in an isolation table. They usually require air pressure maintenance, which can add to the cost and complexity of the installation and maintenance of air springs. The vibration isolation systems described above are passive isolators. “Active” isolation is also used. Active isolators employ electronic signal detection circuitry and so-called smart materials such as piezoelectric elements that sense the incoming vibration signal and add an inverted copy to it, thus partially canceling the vibration. The technology of these systems is rapidly advancing, but as of the time of this writing they are generally only applicable within limited amplitude and frequency ranges, generally performing best at low frequencies. They are also somewhat limited in the dynamic force they can exert. They are often used in series with conventional passive isolators that work best at higher frequencies. Active and active/passive isolation systems are commercially available as base isolators and in isolation tables. Equipment, piping and ductwork, and other vibration sources or sensitive equipment can either be supported from isolators attached at the base to the floor below, or suspended from above on isolation hangers. For the most part, the important technical features of these two types are similar. In addition to the isolator type and static deflection,* other critical details that must be specified include: material properties and corrosion resistance, attachment details, isolator locations, horizontal-to-vertical stiffness ratio, overload capacity, integration with seismic control devices, and other details that will increase the likelihood that the isolator will function as required after installation. Some equipment is supplied with rigid framing allowing the equipment to be supported directly on springs. However, many systems require bases between the equipment and the spring isolators. Base types include rigid steel frames and rails as well as relatively high-mass inertia bases—usually composed of a steel frame filled with concrete.† Inertia bases are specified to reduce vibration amplitudes on the isolated equipment in normal operation and the impact during start-up when the equipment speed momentarily corresponds with the isolator resonance. They also provide a very stiff platform for equipment with interconnected elements such as horizontal split-case pumps. Critical base details to specify include the base dimensions, total mass, and materials properties. The horizontal dimensions are typically defined by the equipment footprint plus any supplemental attachments to be supported on the base (such as pipe elbows and fan diffuser cones). The vertical dimension (depth) is typically a function of the horizontal dimensions, selected to provide adequate resistance to bending and the required base mass. It is important to control detrimental resonance effects by specifying the base details. The dynamic response of the supported system (steel frame, concrete inertia base, or even the equipment itself) changes when supported at discreet points—as when several isolators are used—rather than when it is continuously supported as it is without isolation. Resonances in the isolated support frame can lead to excessive vibration in the supported mechanical equipment and can cause misalignment problems in interconnected systems (such as pumps attached to a motor by a shaft). There are several other types of isolation devices found in advanced technology facilities that must be mentioned: • Flexible pipe, duct, and conduit connectors are used in these services between rigid and isolated components to allow flexibility in the isolated components and to reduce the transmission of vibration in

* The isolator static deflection is usually specified as a minimum value, as higher deflections than required are usually not detrimental. † In the context of this discussion, inertia bases refer to massive bases supported or suspended from isolators. An inertia base in this case is to be distinguished from a housekeeping pad, which is a massive concrete pad attached to the ground or floor structure directly, and supporting isolated or unisolated equipment.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.24

MICRO-VIBRATION AND NOISE DESIGN 39.24

FAB YIELD, OPERATIONS, AND FACILITIES

• •

• •

the pipe and duct walls.* Flexible connectors are sometimes used at service crossings of structural isolation joints. Not all flexible connectors are equal, and, in general, some types work better for micro-vibration control (e.g., twin-sphere elastomerics, multi-convolution stainless steel bellows) than others (e.g., stainless steel braided flexes). The latter type may be more suitable for expansion control and the flexibility required under seismic load. When installed at isolated mechanical equipment, there are cases when flexible connectors may be substituted for the support of piping on isolators near the equipment (or vice versa). Thrust restraints are spring elements used primarily with fans to resist lateral thrust that would otherwise overcome the limits of base isolation and flexible connectors. Resilient penetration sleeves are used to maintain flexibility in isolated piping or ductwork when passing through a rigid wall, ceiling, or floor structure, or to prevent the transmission of vibration into these structures. Resilient lateral guides are elastomeric or steel spring isolators used for isolated support of duct and pipe risers when these pass through floor/ceiling structure. Seismic control devices normally have the opposite performance goal of vibration isolators, which is to restrain equipment or piping under earthquake loading. However, some of these devices are compatible with both the seismic restraint requirements and the isolation requirements and should be specified during the design stage along with the isolation devices. For example, certain types of base snubbers function without rigid contact except in a seismic event. Likewise, cable restraints for pipe and duct installations can be designed with adequate slack to allow the isolation supports to function. Seismic snubbers should be of a design that allows easy inspection for binding that would reduce the isolation effectiveness during normal operation.

Isolator Installation and Common Faults. Unfortunately, many things can go wrong in the design, specification, installation, and maintenance of isolation systems. In a detailed inspection of any facility with a significant number of isolation devices employed, one is likely to find several of the following faults: Design faults: • Inadequate static deflection for equipment, based upon its rotational or low-frequency turbulence vibration • The supporting building component (floor system, ceiling, or pipe rack) being excessively soft with respect to the spring stiffness • Lack of consideration for long-term performance and reliability • Improper isolator selection with respect to loading, causing either inadequate static deflection or overloading of the isolator, either of which reduces or defeats the isolator performance Installation and maintenance faults: In general, the isolated equipment should be able to move freely. If it does not and if there has not been a design error, one or more of the following problems may be indicated: • Binding or shorting of isolation systems due to improperly adjusted isolators, the presence of improperly adjusted or designed seismic snubbers, the presence of shipping restraints or temporary supports, debris under the isolation base, rigidly attached piping or conduits, rigidly attached pipe stanchions, binding between nested spring elements, binding at spring cages, and so forth • Spring misalignment or collapse • Corrosion • Poor load distribution on pad elements * In certain cases flexible connectors can also reduce transmission of vibration in the fluid. For example, some types of elastomeric connectors can be used to reduce impeller pressure pulses in pumped water by absorbing some of the energy in the pulse by flexure of the connector walls. See Ref. 39.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.25

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.25

It is important that the project vibration specifications define specific isolator types, operating parameters, and installation details in order to avoid these faults and the resulting excessive vibration and noise.

39.6 ACOUSTIC DESIGN Noise can affect both personnel and tools within the facility, and if projected in excess into the environment, it can also affect the attitudes of the neighboring communities. Control of HVAC noise and the careful selection of relevant architectural details can improve communications, speech privacy, and the general condition of work environments, and reduce long-term work-related hearing damage, fatigue, and general annoyance. As regards environmental noise, quite frequently facilities are required to show proof of compliance with state or local environmental noise regulations. It is best to consider noise control, if necessary, during the design stage, rather than to have to apply—as a retrofit—potentially more costly noise control measures later.

39.6.1 Interior Noise Design Cleanrooms. Cleanrooms pose particular challenges in noise control design. This is due to several unique characteristics of these environments from an acoustic standpoint. First, the air change requirements can be quite significant, calling for large volumes of air-flow and consequently the attendant noise. Second, cleanrooms can be quite reverberant due to the acoustically reflective architectural materials from which they are typically constructed (e.g., concrete, cleanroom wall panels, and stainless steel). Third, due to outgassing and contamination limitations, the usage of traditional acoustic absorption materials is limited. The situation is far from hopeless, however, and it is possible to model and construct the cleanroom to provide workable environments for people and most process tools.40 Cleanroom noise can be modeled using traditional acoustic hand calculations, or with computerbased ray tracing models. In either case, there are special considerations that must be taken. The models must include the unusual construction materials used in the room (e.g., honeycomb cleanroom wall panels, and HEPA filters) to properly account for absorption and reverberation. Appropriate consideration of the general layout condition, whether bay-chase or ballroom, must be taken. The HVAC sources to be considered include the inlets and outlets of the recirculation air systems, the make-up air systems, any self-noise generated at HEPA filters (generally relevant only in cases where there is an attempt to achieve relatively low noise levels). Other noise sources associated with the base building systems include piping and valve noise and coil pumps. Using conventional cleanroom designs, it is generally very difficult to achieve HVAC noise levels below NC-55 to NC-60 in ISO Class 1 to 5 cleanrooms.8 With appropriate considerations in the design, such as the use of low air velocities and adequate means of quieting fan noise, it is possible to achieve lower noise levels in cleanrooms rated at numerically greater ISO clean class values. In any case, the first means of noise control in cleanrooms is by fan specification and selection. As discussed in Sec. 39.5.2, the means of noise control within or at the fan units depends on the type of units used. The use of external “packless” silencers or silencers with encapsulated fill and cleanroom compatible absorptive treatments is possible, but the efficiency of these means is reduced due to clean compatibility requirements, especially in the low-frequency regime (63 to 500 Hz) typically dominated by fan noise. A potentially more difficult problem is controlling noise from the tools and tools-support equipment (e.g., dry pumps and local chillers) located in the cleanroom. These are added by the end user according to process or research requirements. Pre-purchase noise requirements for this equipment, which might be used to maintain acoustic compatibility with the HVAC system design criterion, are unfortunately still uncommon in many areas. Thus it is not unusual to find that noise levels within the cleanroom are elevated significantly with the addition of the tools. In addition to the support Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.26

MICRO-VIBRATION AND NOISE DESIGN 39.26

FAB YIELD, OPERATIONS, AND FACILITIES

equipment mentioned, primary sources associated with the tools include mini-environments, wafer handling equipment, servo actuators, and air leakage noise. Several ongoing pilot studies have shown that it is possible to contain this noise, especially with advanced planning. This includes designing appropriately ventilated pump and chiller rooms, requirement or provision of appropriate isolation and enclosure of mechanical sources, and the use of appropriate maximum noise specifications for individual equipment. Clean Chases, Subfabs, and Support Areas. Cleanrooms often use support areas that also function as cleanroom air returns. Often the noise criterion can be reduced in these areas if they are not normally occupied and contain nonsensitive mechanical equipment. However, it is usually desirable to limit noise levels within chases that may contain a significant portion of the bulkheaded tools in a bay-chase arrangement. Specialty Labs. The most stringent noise requirements in wafer fabrication and other advanced technology facilities are often found in the labs used for failure analysis, characterization, and other metrology. The types of tools used in these processes are often among the most sensitive to acoustic noise. Fortunately, or necessarily in cases where the acoustic requirements are very stringent, these labs often have no—or relatively less stringent—cleanliness requirements. If the temperature control requirements are stringent, this can add another challenge as specialty air delivery systems are required, however, these can be designed to be consistent with the acoustic requirements. Layout, as discussed in Sec. 39.7.1, is critical. These labs will often require designs to control the following: • The transmission of noise between labs and from corridors and mechanical areas outside the labs • HVAC noise from fans, air terminal units, and diffusers, and considering both duct-borne and duct “breakout” noise11 • Reverberation within the room, by the use of appropriately specified and distributed absorptive ceiling and wall treatments 39.6.2 Noise in Mechanical Rooms and in the Outside Environment The foregoing comments regarded the provision of “comfortable” environments for people and tools. In contrast, this section discusses environments that may be regulated in addition by outside authorities, such as occupational heath organizations and local and national governments. Control of environmental noise and noise in mechanical rooms are more “traditional” acoustic design problems, so we only discuss aspects unique to advanced technology facilities herein. The most significant noise sources in advanced technology facilities are located in the mechanical rooms and equipment yards, including exhaust fans, chillers, large primary and secondary pumps, compressors, air dryers, boilers, cooling towers, and the like. When enclosed in the hard (concrete and steel) and reverberant environments typical of mechanical rooms and CUB buildings, they can produce significant hazards with respect to hearing damage. When these sources are exposed to the environment, as is necessary in the case of exhaust fans, cooling towers, make-up air and boiler combustion air intakes, they can produce formidable noise control problems, especially when the facility is located near urban or semi-urban areas.41 Noise criteria in these cases are most often expressed as a maximum overall value in dBA. As an example, national or international hearing protection regulations or guidelines might define a maximum noise exposure level of 80 to 90 dBA for an 8 h day in a mechanical room. Property line noise limits may range in absolute values from 40 to 70 dBA depending on the zoning use of the adjacent property, or they may be referenced to existing ambient conditions (i.e., before the addition of the new sources of noise). The actual regulations to which a facility is subject can vary significantly, of course, so these must be identified early in the design stage. The conditions under which these apply, such as measurement methodologies and meteorological conditions, must also be identified. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.27

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.27

In both cases, it must be emphasized that the criterion is not applied to individual sources, but to the totality of the noise from all relevant sources. In the case of semiconductor production facilities, there can be hundreds of individual sources that must be considered in the design, and advanced computer modeling methods are often necessary to adequately characterize the impact of all of these sources simultaneously, and to test various forms of noise control to provide the most acousticallyeffective and cost-effective design. Thus, a detailed analysis often reveals that the effective criterion for an individual source is significantly lower than the overall design criterion in a mechanical room or at a property line. Traditional means of noise control in these cases include specified maximum noise limits, layout, barriers and enclosures, silencers, application of absorptive materials, and so on.

39.7 TOOL HOOK-UP 39.7.1 Tool Layout The location of the functional areas within a cleanroom or laboratory within the building, and with respect to vibration sources outside the building, influences the vibration and noise environment achievable in the room. A judicious layout is the most cost-effective way (and sometimes the only way) to achieve a good vibration and noise environment. For example, the most sensitive labs should be located as far as possible from internal sources of vibration and noise such as mechanical and electrical equipment, elevators, major corridors, and loading docks. The position with respect to external sources—such as on-site and off-site roads and central utilities buildings—should also be considered. Likewise, the layout within the cleanroom bay or lab module is important for the most efficient control of noise and vibration. The designer should plan to separate the tools and tool support mechanical equipment in the lab or fab to reduce vibration and noise impact. Consider using a separate and acoustically sealed equipment chase to contain dry pumps, chillers, power conditioners, and other equipment that can disturb the tools and personnel with excess noise. The need for peripheral equipment chases will depend on whether these items of equipment are operated during times of critical tool use. 39.7.2 Passive Tool Pedestal Design It is typically during the hook-up stage, and during any later tool installation, that rigid pedestals are designed to support tools at the elevation of the raised access flooring. These serve several purposes. From a structural standpoint, they are sometimes needed because the load bearing capacity of the access floor is inadequate (e.g., in the case of implanters). In other cases, due to the flexibility and relatively high-vibration amplitudes found on the raised access floor, they are used as a separate rigid support to extend the good vibration environment of the structural floor to the elevation of the raised access floor. Rigid pedestals are not intended to reduce the structural floor vibration environment, and care must be taken in their design so that they do not amplify the structural floor vibration within the critical frequency range. The pedestal may be custom-fabricated from conventional steel members such as structural tubes, or may be off-the-shelf prefabricated structures such as appropriately designed tripods. The pedestal must be independent from the access floor with a minimum of 25-mm gap all around. The platform is normally designed by the structural engineer to carry all appropriate structural loads. It is then dynamically designed such that its fundamental resonance frequencies (in the horizontal and vertical directions) are very high and removed from the supported tool’s most sensitive frequency range, the modes of the fab structure to which it is attached, and the shaft speed of rotating equipment. In summary, the platform must be designed to minimize the vibration amplification from the fab floor (to which it is attached) to the top of the platform. A detailed dynamic analysis using finite element modeling is generally necessary. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.28

MICRO-VIBRATION AND NOISE DESIGN 39.28

FAB YIELD, OPERATIONS, AND FACILITIES

39.7.3 Active Tool Pedestal Design Active isolation elements can also be used in pedestals and isolation tables. This technology was discussed briefly in Sec. 39.5.8, and the same benefits and limitations apply when used in tool-support pedestal design. Active isolation is not compatible with some types of tools. 39.7.4 Hook-up Equipment Vibration and Noise Control Subfab systems associated with process level tools can generate substantial vibration unless their installation is handled carefully.* Subfab systems include vacuum pumps (often stacked), small chillers and scrubbers, power conditioning equipment, and other mechanical and electrical tool support systems. While the power rating of these systems is relatively small (1 to 10 kW), they are often many in number and widely distributed. Dry pumps have “dry” bearings and their installation must be such as to allow their easy removal for maintenance. For this reason the pumps are typically installed on carts with casters. The casters incorporate a locking foot to prevent accidental movement of the system when in service. Most manufacturers of these pumps provide on-board elastomeric vibration isolation mounts between the base of each pump and the frame of the cart. These isolators can work well in limiting the vibration transmitted to the subfab floor. However, isolation is not always provided, nor is it always as effective as one might wish. In these cases, soft neoprene-in-shear or steel spring mounts can greatly improve the isolation efficiency. An alternative to on-board isolation is to support the pump cart from the floor on springs or from racks on hanger springs. This method of isolation can be more efficient than onboard isolation but it would, necessarily, complicate the issue of pump maintenance. It is equally important that the piping and exhaust systems associated with the vacuum pumps include flexible elements to limit the transfer of vibratory forces between the pumps and the building structure and the tools served by the pumps. It is important also that gas lines and electrical connections be flexible.

39.8 PURPOSES AND TIMING OF FACILITY VIBRATION SURVEYS It is quite common to carry out a vibration survey of a site prior to the construction of a facility. This may be just the first of several vibration evaluations carried out over the life of a fab or research facility. There are a variety of reasons for these surveys, some of which are discussed below: Site survey: The purpose of the pre-construction site survey is to aid in the process of selecting or accepting a site. There is a limit to the amount of attenuation of poor site vibration conditions that can be achieved at or inside a building. Thus, depending on the circumstances, it may be necessary to verify that vibration due to external sources (e.g., rail and automobile traffic and industrial facilities) will be adequately low for the proposed function of the site and future buildings and processes. Fab construction process: There are two vibration evaluations carried out during the construction process, but they are done for quite different reasons. The earlier of the two is often called a “structural evaluation” and the later one is commonly called a “final evaluation” or “as-built evaluation.” Both may be somewhat extensive in scope. The intent of a structural evaluation is to validate specific structural parameters associated with the structural dynamics design, such as the stiffness and resonance frequency of floors, performance of SIBs, and structural attenuation or amplification between points in the building (such as between the subfab and the fab). If inadequacies are found, they are much more easily corrected during construction than after the cleanroom and mechanical systems are in place and operating. The intent of a final evaluation is to document the performance of the vibration-critical portions of a fab at the time that the facility is “delivered” to the owner. Inadequacies may be found at this

*

For an example of the vibration impact associated with hook-up mechanical equipment, see Ref. 22.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.29

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.29

time as well, but those inadequacies are (hopefully) limited to easily correctible items such as improperly aligned vibration isolators for mechanical systems. Note that for a final evaluation survey to be valid, most of the building MEP systems must be operating at or near normal capacity during the measurements, since these equipment are the primary sources of vibration in the building. Tool site evaluation: This type of evaluation is generally rather limited in scope. Its intent is to evaluate the planned locations for one or more particular tools to document that those locations meet the tools’ specific installation requirements. Diagnostics: As a fab matures, problems may occur with ageing mechanical systems or specific tools, which may suggest that vibrations are exceeding a particular tool’s tolerances. The vibration measurements are more of a diagnostic tool for the vibration consultant as a source of excessive vibration is sought. Documentation of “current” state: Some facility owners wish to update their records periodically with regard to the environmental status of a production area as a facility ages. This may include vibration and/or acoustics surveys. The timing of the last three survey types is somewhat obvious. Circumstances or owner policy will dictate when they must be carried out. The timing of the surveys carried out during construction is less obvious, and poor timing can lead to an improper interpretation of results, or complications with the remediation of any inadequacies they identify.

39.9 MATURATION OF THE VIBRATION AND NOISE ENVIRONMENT The term maturation refers to the change in the vibration environment over time (generally a worsening) due to a variety of reasons. Gendreau and Amick22 documented a number of aspects pertaining to this. There are several key issues that contribute to the maturation of a facility after it passes beyond the “as-built” state. 39.9.1 Hook-up Hook-up, whether at the time of initial commissioning or at an advanced age, provides the greatest risk for causing the maturation of the vibration and noise environment. In many cases, hook-up is not carried out with the same level of care or conservatism as is employed in the base building. Users or facility maintenance personnel may not always remember to provide vibration isolation and noise control for support equipment, or may not install it properly. 39.9.2 Process Changes Some fabs undergo a change in layout and tools periodically, due to changes in the owner’s process. This poses the same problems as hook-up. 39.9.3 Aging Structure and Mechanical Installations and Maintenance As a structure ages, several things may happen. First, if the facility has a concrete structure, it will get stiffer as time passes. This is not a dramatic effect, but it can lead to subtle shifts in structural resonance frequencies, and may provide a slight reduction in amplitudes. However, the more common trend is that mechanical systems degrade over time, which leads to increases in the resulting vibrations. Bearings will degrade with age, eventually requiring replacement. Balance can degrade as well, particularly if fans or impellers are subject to fouling or minor damage. Each time a pump or other mechanical system is maintained, there is a risk that vibration isolation hardware might become misaligned. Mechanical system degradation will lead to a much more gradual change over time than the incremental changes associated with hook-up.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.30

MICRO-VIBRATION AND NOISE DESIGN 39.30

FAB YIELD, OPERATIONS, AND FACILITIES

39.10 FUTURE TRENDS AND SPECIAL CASES 39.10.1 Microelectronics Facilities The vibration and noise sensitivity of microelectronics production equipment has remained fairly static for almost a decade and it appears that industry pressure will continue to push tool makers to provide equipment that will work in current environments. If production technologies are forced to shift to new hardware concepts more in tune with those used in nanotechnology, there may be some revision of vibration and noise requirements. This will likely be met with a great deal of resistance from the chip makers, which have gone on notice in the International Technology Roadmap for Semiconductors (ITRS) as insisting on the continued use of current facilities and facility concepts. One trend that may affect tools is wafer size. Most current facilities are shifting from 200- to 300-mm wafers, with correspondingly larger tools. Another shift to even larger wafers will lead to even larger tools, with the potential for generating even larger internal forces requiring resistance from the structure. 39.10.2 Flat Panel Display Facilities Flat panel display (FPD) and LCD-TFT facilities tend to get larger with each generation of production equipment and there is no immediate sign that this trend is going to change. The larger production equipment generally means larger materials handling systems, which generate larger forces that require stiffer structures. At this time, design concepts appear to be keeping pace with the technology, though the larger forces associated with larger robots provide a significant challenge to designers. 39.10.3 Nanotechnology Facilities It is difficult to predict where nanoscience is going to head and what it will require with regard to vibration and noise environment. It is probable that equipment for imaging (e.g., SEM, TEM, STEM, and AFM) will continue to become more sensitive to both, though the noise requirements of some of the most sensitive instruments are already at the edge of what is practical using today’s technologies. One can only hope that tool vendors become better at internal vibration and noise isolation, as the more established vendors of photolithography tools have become. Some facilities are finding the noise concerns so demanding that the only way to meet the needs of a few cutting-edge systems (mostly dealing with microscopy) is to sequester them in their own sealed rooms, with no personnel present while they are being used. The situation is not as bleak with regard to vibration, though this discipline is also reaching its limits. Some technologies, including steppers, are fairly robust. Others, such as some of the e-beam photolithography tools and nanoprobes, impose stringent requirements that may limit the use of even moderately quiet sites. Current technology for active vibration control is not particularly adequate for reducing the vibration amplitudes of an already quiet environment. Correcting this shortcoming may extend capabilities some distance into the future, but a great deal of technological development is still required. 39.10.4 MEMS Facilities Microelectromechanical systems (MEMS) have been evolving and will be critically sensitive to vibration or noise; a few facilities have been designed and intended for this (such as CAMD in Louisiana and several facilities using LIGA technology). Currently, most MEMS systems have geometries still so large that they are ten years behind the general semiconductor industry in terms of sensitivity. However, some of the research in nanotechnology is aimed toward nanoscale products to be implemented using MEMS (such as drug delivery systems), suggesting that the marriage of the two might require facilities appropriate for nanotechnology. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.31

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.31

ACKNOWLEDGMENTS The authors wish to acknowledge the contributions of the “initiators” of this discipline, Colin Gordon and Eric Ungar, as well as our colleagues who have helped evolve the design and measurement approaches we use.

REFERENCES 1. American National Standards Institute ANSI S12.2-1995 (R1999), Criteria for Evaluating Room Noise, Acoustical Society of America, Melville, NY, 1995. 2. Gendreau, M. L., “(Specification of the) Effects of Acoustic Noise on Optical Equipment,” Optomechanical Engineering and Vibration Control, E. A. Derby, C. G. Gordon, D. Vukobratovich, P. R. Yoder, Jr., C. Zweben, (eds.), Proceedings of SPIE, Vol. 3786, Denver, CO, SPIE—The International Society for Optical Engineering, Bellingham, WA, pp. 4–13 (July 1999), reprinted and updated in Noise and Vibration Worldwide, Vol. 32, No. 4, pp. 17–21, April 2001. 3. Bendat, J. S., and A. G. Piersol, Random Data: Analysis and Measurement Procedures, Wiley-Interscience, New York, 1989. 4. Amick, H., and S. Bui, “A Review of Several Methods for Processing Vibration Data,” Vibration Control in Microelectronics, Optics, and Metrology, San Jose, CA, Colin G. Gordon, (ed.), Proceedings of SPIE, Vol. 1619, SPIE—The International Society for Optical Engineering, Bellingham, WA, pp. 253–264, November 1991. 5. Amick, H., “On Generic Vibration Criteria for Advanced Technology Facilities: with a Tutorial on Vibration Data Representation,” Journal of the Institute of Environmental Sciences, pp. 35–44, September/October 1997. 6. McConnell, K. G., Vibration Testing: Theory and Practice, Wiley, New York, 1995. 7. Ungar, E. E., and C. G. Gordon, “Vibration Challenges in Microelectronics Manufacturing,” Shock and Vibration Bulletin, Vol. 53, No. I, pp. 51–58, May 1983. 8. Institute of Environmental Sciences (IEST), Appendix C in Recommended Practice RP-012, “Considerations in Cleanroom Design,” IES-RP-CC012.2, Institute of Environmental Sciences, Rolling Meadows, IL, 2005. 9. Ungar, E. E., D. H. Sturz, and H. Amick, “Vibration Control Design of High Technology Facilities,” Sound and Vibration, Vol. 24, No. 7, pp. 20–27, Acoustical Publications, Bay Village, OH, July 1990. 10. Gordon, C. G., “Generic Vibration Criteria for Vibration-Sensitive Equipment,” Optomechanical Engineering and Vibration Control, E. A. Derby, C. G. Gordon, D. Vukobratovich, P. R. Yoder, Jr., C. Zweben, (eds.), Proceedings of SPIE, Vol. 3786, Denver, CO, SPIE—The International Society for Optical Engineering, Bellingham, WA, pp. 22–35, July 1999. 11. International Standards Organization, ISO 2631, Guide to the Evaluation of Human Exposure to Vibration and Shock in Buildings (1 Hz to 80 Hz), ISO, Geneva, Switzerland, 1981. 12. Amick, H., and A. Bayat, “Meeting The Vibration Challenges Of Next-Generation Photolithography Tools,” Proceedings of ESTECH 2001, 47th Annual Technical Meeting, IEST, Phoenix, AZ, April 2001, reprinted in Sound and Vibration, Vol. 36, No. 3, pp. 22–24, March 2002. 13. American Society of Heating, Refrigerating and Air-Conditioning Engineers, ASHRAE 2003, “Chapter 47: Sound and Vibration Control,” 2003 ASHRAE Handbook: Heating, Ventilating, and Air-Conditioning Applications, ASHRAE, Atlanta, GA, 2003. 14. Blazier, Jr. W. E., “RC Mark II; A Refined Procedure for Rating the Noise of Heating, Ventilating and AirConditioning (HVAC) Systems in Buildings,” Noise Control Engineering Journal, Vol. 45, No. 6, pp. 243–252, 1997. 15. Beranek, L. L., “Balanced Noise Criterion (NCB) Curves,” Journal of the Acoustical Society of America, Vol. 86, pp. 650–654, 1989. 16. Kingsbury, H. F., “Review and Revision of Room Noise Criteria,” Noise Control Engineering Journal, Vol. 43, No. 3, pp. 65–72, May–June 1995.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.32

MICRO-VIBRATION AND NOISE DESIGN 39.32

FAB YIELD, OPERATIONS, AND FACILITIES

17. Towne, R. M., and K. Anderson, “The Changing Sound of Education,” Sound and Vibration, Vol. 31, No. 1, pp. 48–51, January 1997. 18. American National Standards Institute, ANSI S1.4, Specification for Sound Level Meters, 1983. 19. Gendreau, M. L., H. Amick, and T. Xu, “The Effects of Ground Vibrations on Nanotechnology Research Facilities,” Proceedings of the 11th International Conference on Soil Dynamics and Earthquake Engineering (11th ICSDEE) and the 3rd International Conference on Earthquake Geotechnical Engineering (3rd ICEGE ), Berkeley, CA, January 2004. 20. Gordon, C. G., “A Study of Low-Frequency Ground Vibration in Widely Differing Geographic Areas,” Proceedings of Noise-Con 87, Penn State University, State College, Pennsylvania, June 1987. 21. Amick, H., and C. G. Gordon, “Specifying and Interpreting a Site Vibration Evaluation,” Microcontamination, October 1989. 22. Gendreau, M. L., and H. Amick, “Maturation’ of the Vibration Environment in Advanced Technology Facilities,” Proceedings of ESTECH 2004, 50th Annual Technical Meeting, Institute of Environmental Sciences and Technology (IEST), Las Vegas, NV, April 2004. 23. Amick, H., T. Xu, and M. L. Gendreau, “The Role of Buildings and Slabs-on-Grade in the Suppression of Low-Amplitude Ambient Ground Vibrations,” Proceedings of the 11th International Conference on Soil Dynamics and Earthquake Engineering (11th ICSDEE) and the 3rd International Conference on Earthquake Geotechnical Engineering (3rd ICEGE ), Berkeley, CA, January 2004. 24. Gordon, C. G., and H. Amick, “Groundborne Vibration—Thoughts on Control by Foundation Design and Other Techniques,” Proceedings of Inter-Noise 89, International Institute of Noise Control Engineering, Newport Beach, CA, Noise Control Foundation, Poughkeepsie, NY, December 1989. 25. Amick, H., M. L. Gendreau, and C. G. Gordon, “Facility Vibration Issues for Nanotechnology Research,” Proceedings of the Symposium on Nano Device Technology, National Chiao-Tung University, Hsinchu, Taiwan, May 2002. 26. Ungar, E. E., and R. W. White, “Footfall-Induced Vibrations of Floors Supporting Sensitive Equipment,” Sound and Vibration, Vol. 13, October 1979, pp. 10–13. 27. Murray, T. M., D. E. Allen, and E. E. Ungar, “Floor Vibrations Due to Human Activity,” Steel Design Guide Series 11, American Institute of Steel Construction, p. 69, Chicago, IL, 1997. 28. Gordon, C. G., “The Design of Low-Vibration Buildings for Microelectronics and Other Occupancies,” First International Conference: Vibration Control in Optics and Metrology, L. R. Baker, (ed.), Proc. SPIE 732, London, SPIE—The International Society for Optical Engineering, Bellingham, WA, pp. 2–10, February 1987. 29. Amick, H., and A. Bayat, “Dynamics of Stiff Floors for Advanced Technology Facilities,” Proceedings of 12th Engineering Mechanics Conference, San Diego, CA, American Society of Civil Engineers (ASCE), Reston, VA, pp. 318–321, May 1998. 30. Amick, H., M. L. Gendreau, and A. Bayat, “Dynamic Characteristics of Structures Extracted from In-situ Testing,” Optomechanical Engineering and Vibration Control, Eddy A. Derby, Colin G. Gordon, Daniel Vukobratovich, Paul R. Yoder, Jr., Carl Zweben, (eds.), Proceedings of SPIE, Vol. 3786, Denver, CO, SPIE— The International Society for Optical Engineering, Bellingham, WA, pp. 40–63, July 1999. 31. Gordon, C. G., and M. Q. Wu, “Noise and Vibration Characteristics of Cleanroom Fan-Filter Units,” Proceedings of ESTECH 1998, Institute of Environmental Sciences and Technology (IEST), Phoenix AZ, April 1998. 32. Gendreau, M. L., “Noise in Cleanrooms served by Fan-Filter Units: Design Considerations” Proceedings of the 11th International Congress on Sound and Vibration (ICSV11), St. Petersburg, Russia, 5–8 July 2004. 33. Blevins, R. D., Flow-Induced Vibration, 2d ed., Van Nostrand Reinhold, New York, 1990. 34. Amick, H., and M. L. Gendreau, “Construction Vibrations and Their Impact on Vibration-Sensitive Facilities,” Proceedings of the Sixth Construction Congress, American Society of Civil Engineers (ASCE), Orlando, FL, February, 2000, pp. 758–767. 35. International Standards Organization, ISO 3945, “Mechanical Vibration of Large Rotating Machines with Speed Range from 10 to 200 rev/s”—Measurement and Evaluation of Vibration Severity in Situ, ISO, Geneva, Switzerland, 1985. 36. American National Standards Institute, ANSI S2.41-1985 (R1997), “Mechanical Vibration of Large Rotating Machines with Speed Range from 10 to 200 rev/s”—Measurement and Evaluation of Vibration Severity in Situ, ANSI, New York, 1985.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.33

MICRO-VIBRATION AND NOISE DESIGN MICRO-VIBRATION AND NOISE DESIGN

39.33

37. Lindeburg, M. R., Mechanical Engineering Reference Manual for the PE Exam, 10th ed., Professional Publications, Belmont, CA, 1998. 38. Ungar, E. E., “Vibration Isolation,” in Beranek, L. L., and Ver, I. L. (eds.) Noise and Vibration Control Engineering: Principles and Applications, Wiley, New York, 1992. 39. Paulauskis, J., and W. E. Blazier, Jr., “Centrifugal Water Pumps,” in C. Ebbing, and W. E. Blazier, Jr. (eds.), Application of Manufacturers’ Sound Data, American Society of Heating, Refrigerating and AirConditioning Engineers, (ASHRAE), Atlanta, GA, 1998. 40. Gordon, C. G., and A. M. Yazdanniyaz, “Noise Prediction and Control in Microelectronics Cleanrooms,” Proceedings of Inter-Noise 89, Newport Beach, CA, December 1989. 41. Gendreau, M. L., and M. Q. Wu, “Environmental Noise Control for Semiconductor Manufacturing Facilities,” Proceedings of Inter-Noise 99, The 1999 Congress and Exposition on Noise Control Engineering, Fort Lauderdale, FL, December 1999.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH39.qxd

04/04/2005

21:19

Page 39.34

MICRO-VIBRATION AND NOISE DESIGN

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 40

ESD CONTROLS IN CLEANROOM ENVIRONMENTS Larry Levit ION Systems, Inc. Berkeley, California

40.1 ELECTROSTATIC CHARGE IN SEMICONDUCTOR CLEANROOMS Electrostatic charge grows to extremely high levels in the environment of a semiconductor fab. This is due to several properties of the cleanroom. First, since the mechanism for developing static charge is a surface phenomenon related to contact followed by the separation of dissimilar materials, the presence of water absorbed into the surface of the material from the humidity in the air diminishes the effect. The phenomenon, called triboelectrification, involves the transfer of electrons from the conduction band of one material to the conduction band of the other material. The presence of water at the surface decreases the difference between the energy levels of the bands and diminishes the amount of static charge that is transferred.1,2 Second, many of the items in the cleanroom are constructed from plastics, which, in general, are extremely good insulators. In fact, it is necessary to employ these materials because they are inherent to the process. For example, quartz is required for reticles because of its optical properties, and Teflon is required because it is impervious to hydrofluoric acid. Also, the extreme cleanliness of the surfaces of objects in the fab denies static surface charge a conduction path to ground on an insulator. These issues of increased static charge generation and decreased static charge dissipation result in significantly higher static charge levels in a semiconductor fab than in a conventional room. In fact, it is not uncommon for a fab with no safeguards against static charge to achieve levels of tens of kilovolts on a variety of critical surfaces.

40.2 PROBLEMS RESULTING FROM CHARGE IN CLEANROOMS 40.2.1 Contamination The relationship between electrostatic charge and contamination control in high-technology cleanrooms is a strong one, representing a significant source of particle deposition on charged objects such as wafers. The rate of electrostatic attraction (ESA) of small particles to charged objects has been calculated for a controlled environment,3 and particle deposition data recorded in cleanroom environments have been found to be consistent with the calculation.4

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

40.1

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.2

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.2

FAB YIELD, OPERATIONS, AND FACILITIES

One of several studies involved employing a high-voltage power supply to bias one wafer to a voltage of 2 kV and connecting another to ground electrically. In one of the studies 8-in wafers were exposed to the environment in an isolated part of a class 1 cleanroom.5 Human traffic through the area where the exposure occurred was eliminated by cordoning off the area. In order to assure that a statistically valid sample was acquired, an exposure time of 6 weeks was employed. The wafers were scanned using a Tencor Surfscan with a particle size threshold of 0.2 µm. The Surfscan results are illustrated in Fig. 40.1. While the numbers of particles observed on the two wafers are not representative of real-world contamination levels for semiconductor processing, the ratio of the number of particles on the neutral wafer (3389) compared to the number of particles on the wafer at a voltage of 2000 V (22,764) is accurate. In this case, the ratio is 6.7:1. The calculation of electrostatically driven contamination sums the components of the deposition velocity due to each deposition mechanism. Deposition velocity, loosely defined, is the rate at which particles move toward the surface of the object due to the forces on the particle. Particles deposit on wafers, flat panel displays, disk drive components, and equipment surfaces due to gravity, diffusion, and other forces. High efficiency particle attenuator (HEPA) filtration attempts to keep particles out of the cleanroom, and laminar airflow is designed to minimize the sedimentation rate of contaminating particles by entraining them into the airflow. While a cleanroom is maintained at a high level of cleanliness, particles are still present due to people, equipment motion, and process. The forces on the particle are aerodynamic (viscous drag), gravitational, diffusional, and electrostatic in nature. Of course, gravitational forces decrease as the size (mass) of the particle decreases. Similarly, the magnitude of the viscous drag on the particle is also smaller for smaller particle sizes. In contrast, the magnitude of the diffusional forces is greater for smaller particles because of the greater efficiency of momentum transfer to particles that are closer in mass to the gas atoms that strike them. The calculation showed that the force of electrostatic attraction exceeds the other physical forces, for the conditions normally present in a cleanroom, surface voltages of several thousands of volts, and for particles in the micron to submicron range. The calculation assumed that the particles in the air were neutral on average but had a distribution of charges with a width that was monotonically related to the total number of electrons on the particle. Thus, larger particles have the possibility of more charge on them and can experience greater electrostatic forces but are also more massive. Thus, the deposition velocity due to electrostatic forces exhibits a maximum for a specific size. Theoretically, increased particle deposition due to electrostatic forces will occur at any voltage but at field strengths of 500 V/in or more, the effects are significant and easy to measure. Field strengths of 10,000 V/in or more are not uncommon in cleanrooms. Figure 40.2 illustrates some of the forces that act to attract particles to wafer surfaces.6 For small particles (0.01 to 1.0 µm in size), electrostatic forces are the primary cause of increased particle deposition. What size of particle is to be expected in a modern high technology cleanroom? Figure 40.3 gives a bit of insight into the expected size range. The figure shows that the nature of a HEPA filter is to stop virtually all particles that are incident upon it, but that the efficiency of the filter is lowest in the

FIGURE 40.1

Surfscan results.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

21:19

Page 40.3

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

40.3

Deposition velocity versus particle diameter

Deposition velocity (cm/sec)

1

10−1 Combined 10−2

10−3

10−4

Electrostatic (at 500 volts/cm) Diffusion

Gravitational

Data from the original publication was traced and replotted

10−5

0.1

0.01

1

10

Particle diameter (µm) FIGURE 40.2

Forces acting on particles.

near submicron range (~0.1 to 0.2 µm). In this size range, and with the forces shown in Fig. 40.2, it is expected that the major contributor to contamination at 500 V/cm is electrostatic attraction. How significant are the calculations and the measurements discussed previously? Is electrostatic attraction a significant factor in high technology manufacturing? In a typical high technology manufacturing cleanroom without an electrostatic charge control program, insulators in a room (e.g., reticles, wafers with oxide coating, and disk drive media) typically achieve voltage levels of 5 to 20 kV. Thus, based upon the data presented above, the majority of the contamination is electrostatically driven. Often this major factor goes unnoticed because the cleanliness levels are so good in the cleanroom. In sub-class 1 cleanrooms, the number of particle adders (PWP) in a typical modern process can be as low as 0.1 to 1.0 (>75 nm). Over the course of processing many layers of the product, this can represent 2 to 20 particles, which is still a very small number. If the average static charge level in the process is only 500 V, due to the fact that there is static control in some parts of the process

1.5 99.99999%

0.00001

0.0001

0.001 0.01 FIGURE 40.3

99.9999%

3.0

99.999% 0.02

0.05 0.1 0.2 Particle diameter (µm)

0.5

1

Size of particle to be expected in a modern high technology cleanroom.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Filter efficiency (%)

99.999999%

0.000001

Penetration (%)

Geng(SMH)_CH40.qxd

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.4

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.4

FAB YIELD, OPERATIONS, AND FACILITIES

delivered by the process tool manufacturer, the part of the contamination contributed by electrostatic attraction would likely be in the range of 0.25 to 10 particles. In a process with such low contamination levels, it is very difficult to devise a method for measuring the contribution due to one source. Nonetheless, the economic impact of removing this contamination source is profound. 40.2.2 Electrostatic Damage Electrostatic attraction and its effect on contamination control is not the only negative effect of static charge. In addition, static charge is responsible for electrostatic damage due to the discharge from one object to another. Such a discharge can cause physical damage to a product that experiences the discharge owing to either electrical overstress (voltage punch-through) or damage caused by the energy deposit by the discharge (spark). Electrostatic discharge (ESD) is particularly important in photolithography. Damage to reticles is caused by either charge on the reticle or by induced discharges caused by electric fields from other charged objects in the proximate environment. The rapid uncontrolled transfer of static charge from one object to another is referred to as ESD. One aspect of such a discharge is that the source and destination of the electrical current are extremely localized (~µm). This means that the energy dissipated in the two objects that participate in the discharge are heated extremely locally. When such a discharge takes place between two electrical conductors, the speed of the transfer is typically in the nanosecond regime. The nominal capacitance of nominal objects in a fab (~tens of cm) are on the order of 10−11 to 10−10 F. Thus, if they are conductors, they have RC time constants <1 ns. So even including inductive effects, metal-to-metal discharges are extremely fast. ESD damage can be caused by tribocharging of the victim object followed by a discharge to ground. In this case, the object becomes charged by handling and then, when it is moved toward a socket or is approached by an end effector, the discharge occurs. The other effect that can lead to damage is called the field induced model.7 When a victim object (typically a die, wafer, or reticle) is subjected to an electric field, a potential difference is created between the victim and an adjacent ground. This damage mechanism is common in back-end processing. In this case, the insulating package becomes charged from handling and produces an electric field. This field drives a discharge from the die in the package to a ground pin on the test socket. See Fig. 40.4. In another example of field induced model (FIM) damage, a reticle can experience a discharge from one chrome structure to an adjacent one when the reticle is subjected to an external electric field. This commonly happens when the reticle is stored in an insulating reticle cassette that becomes charged. Most often the charge is located immediately beneath the handle, which becomes charged when the operator lifts the cassette and inadvertently rubs his fingers over the cassette structure. Such discharges can be very serious, because the manufacturing process can experience a precipitous yield

++++++++++++++++++++

FIGURE 40.4 Field-induced damage driven by the field from a charged package.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.5

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

FIGURE 40.5

40.5

Another example of FIM damage.

drop in spite of the fact that the tiny discharge across the reticle cannot be sensed by the operator. See Fig. 40.5 for such FIM damage. Most recently, semiconductor wafers with the smallest feature sizes (≤0.090 µm) have exhibited occasional gate oxide punch-through due to processing steps that are known to cause high charging (i.e., cleaning and certain wet-processing steps). 40.2.3 Electromagnetic Interference The remaining issue caused by electrostatic charge is that of robotic malfunction. When a metal-tometal discharge takes place, the frequency content of the discharge is extremely high (~multiple gigahertz).8 Thus, the discharge dissipates quite a bit of its energy in the form of electromagnetic transients (transient electromagnetic interference [EMI]), which are within the band pass of microprocessors controlling the robots. This energy results in local heating at the site of the discharge but also creates eddy currents that are broadcast into the fab. Because the bandwidth of the discharge extends into the microwave frequency range, it is extremely difficult to shield electronic equipment from this EMI. A typical discharge is shown in Fig. 40.6. It was recorded using a passive antenna/digital oscilloscope with a composite bandwidth of ~600 MHz. The oscilloscope was sampling at 4 GS/s, and the sweep speed is 50 ns/div.

FIGURE 40.6

A typical EMI discharge.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.6

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.6

FAB YIELD, OPERATIONS, AND FACILITIES

It is of interest to estimate the peak current in such a discharge. If the object being discharged represents ~10−11 F and is charged to 5 kV q = CV = 10−11 F × 10+4 V = 10−7 C Then, if the excursion is similar to the one above, 2.5 ns wide, the peak current is ipeak = 2q/2.5 ns = 8 A assuming a triangular pulse shape. This is an amazingly high current for a little spark and means that the magnitude of the radiated power is extremely high even though the total energy in the discharge is only a few hundred micro-Joules. Because the instantaneous radiated power is high, the voltage that is induced on nearby objects can be appreciable. One example of a nearby conductor might be the trace on a printed circuit board. If a voltage of ~ 1 V is induced on the circuit board, there is the possibility of digital circuitry being disrupted resulting in an operation error of the device. Occasionally (daily to weekly), such a discharge can cause the microprocessor to try to execute meaningless or invalid instructions. When this happens, the robot will either stop and display a difficult-to-interpret error message or, worse, exhibit some strange behavior, such as bumping into a wall or trying to insert a wafer into an incorrect location. Most often this behavior is assumed to be a software bug. While this may be the case, the problem can also be the result of EMI transients generated by ESD. It is important to understand the mechanism for the interruption. While the discharges take place relatively often, typically one discharge (or ESD event) for each wafer passing through the tool, they rarely cause a problem even if they are large in amplitude. The ESD event must be timed to coincide exactly with a data strobe on the microprocessor board. When this coincidence occurs, the digital information (microprocessor instruction, address, or data word) becomes corrupted. As a result, the processor either detects the error and stops or executes the bad data. In the case of the former behavior, the tool typically stops and displays an error message that may or may not be intelligible to the operator. This phenomenon is called lockup and usually requires that the tool be rebooted. The associated operations of the reboot process may require as much as 45 min to execute. During this time, the tool is unavailable. If the data are corrupted, the tool may make an incorrect decision based upon the information. This can result in strange behavior. For example, if the corrupted data word is a robot location coordinate, the tool may cause the robot to strike a wall and result in damage to the robot and the product. Because the aberrant behavior requires the coincidence of two things, the rate of occurrence of the phenomenon is low. Also, because the events are stochastic in nature, their time distribution occurs with a Poisson distribution. It is not at all uncommon for the rate of such events to be on the order of one or two per week on average. Because of the nature of the Poisson distribution, these events have the appearance of occurring in clusters. There may be five in one week and then none for the next two weeks. This makes them extremely difficult to diagnose. To test the hypothesis that a given bad tool behavior is due to this effect, it is best not to look for the lockup effect but for the ESD-induced EMI instead, which occurs at a considerably higher rate and is therefore easier to diagnose. A discussion of instrumentation for this measurement is included in this section. In addition to ESD-induced EMI, another problem in a fab is continuous EMI. This sort of EMI is usually broadcast by electronic circuitries in the fab. The amplitude of such EMI from a product and the immunity of a product to such EMI are regulated to much lower levels than those observed in association with ESD-induced EMI. Such EMI is normally regulated by the FCC in the United States and by CISPR (CE Mark) abroad. The measurement protocol specified for this sort of continuous EMI is based upon a spectrum analyzer and is an averaging measurement. As such, the transient EMI that is generated by ESD does not register on a spectrum analyzer. A typical ESD event occurs at time scales of 10 s to 1 min and has a duration of <1 µs. Thus, the duty cycle is 10−7 or less and the average radiated energy is negligible. For this reason, it is important to realize that a device that passes a conventional radiated power standard can still be a source of ESD-induced EMI. Similarly, if a radiated EMI study is done with a spectrum analyzer and antenna, there are no conclusions that can be drawn about the presence of ESD-induced EMI, as that test is blind to the effect.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.7

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

40.7

40.3 STATIC CHARGE GENERATION Whenever two dissimilar surfaces placed in close contact are separated, one surface loses electrons and becomes positively charged, while the other surface gains electrons and becomes negatively charged. This is known as triboelectric charging. Any material, solid or liquid, may be charged triboelectrically by friction, contact and separation of materials, or fluid flow. The magnitude of the charge will be affected by the surface condition, area of contact, speed of separation or rubbing, and the humidity. Whether the material remains charged depends on its conductivity and the availability of a path for the charge to flow to ground. If charge is allowed to accumulate on a material it may attract and bond particles to its surface. The principle of triboelectric charging is related to the work function of each material. This is defined as the energy required to remove an electron from the surface of the material. Since the work function is related to the electronic energy levels of the material, the work function of each chemical element or compound is unique. Thus, whenever two materials are placed in contact with each other, electrons are transferred from one material to the other. The amount of transfer is dependent upon the nature of the surfaces and the nature of the contact. Smooth surfaces with a significant amount of contact pressure and relative motion (sliding) result in a greater amount of charge transfer. When the materials are separated, the capacitance between them decreases, so the potential difference (voltage) between them increases. Thus, the mechanism of triboelectric charging results from contact of dissimilar materials followed by their separation afterward. The environment of a cleanroom lends itself to increased levels of tribocharging and decreased dissipation of the charge from the surface of insulators as compared with levels on insulators in a conventional room. First, any contamination that exists on the surface of an insulator provides a discharge path to ground for the charge. In a cleanroom, all objects are wiped down to eliminate this discharge mechanism. Studies9 have shown the relationship between humidity and tribocharging. In a location with 60 percent relative humidity, an equilibrium is achieved between water vapor and the surface of each material. At a lower humidity (~35 to 45 percent), the equilibrium condition dictates that less water vapor will be present in the surface of the material. This water vapor modulates the work function of the material, placing its value part way between the work function of the material and the work function of water. Thus, materials in a low humidity environment exhibit more triboelectric charging than those in a higher humidity environment. Since cleanrooms are maintained at low humidity, more charging is observed in the cleanroom that in the conventional room. Static charge is also generated by induction. Static charge on an object can create or “induce” opposite polarity charges on the surface of another object by causing the positive and negative charges on the object to separate. As with charge generated triboelectrically, the induced charges can attract particles, and contact with ground can result in damaging ESD events and EMI. An example of contamination resulting from induction is when a wafer is stored in a highly charged container (i.e., a FOUP), assumed negative for discussion purposes. If wafers without an oxide coating are held in an inner support structure that is conducting (as is the case with a FOUP) and connected to ground, the charge on the wafer-support structure will separate and the negative charge will be displaced from the wafers to the support structure and from there to ground. When the container is removed from the ground structure, the wafers will be charged positively and represent a contamination issue.

40.4 INSULATORS VERSUS CONDUCTORS All materials can be characterized as either electrical conductors or as electrical insulators. A conductor is a material through which an electrical current can pass and an insulator is a material through which an electrical current cannot pass. There is a good deal of variation in the electrical properties of conductors (electrical resistivity) that allows electrical conductors to be further classified as conductors (good conductors) and as dissipative (poor conductors), but both are differentiated from

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.8

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.8

FAB YIELD, OPERATIONS, AND FACILITIES

insulators by their ability to sustain an electrical current. The parameter of electrical resistivity is a measure of the voltage that must be applied to a sample of the material to stand a unit current through a cubic sample of the material 1 m on a side. Surface resistivity is a similar parameter corresponding to currents passing along the surface of a material rather than through a bulk sample. It is defined in terms of the voltage required to pass a unit current through a square sample of the material. Resistivity is measured in units of Ω-m and the surface resistivity (relating to currents passing along the surface of a sample) is measured in Ω/sq as shown in Fig. 40.7. 40.4.1 Conductive Materials10 Conductive materials are defined as those having a surface resistivity less than 1 × 105 Ω/sq or a volume resistivity less than 1 × 104 Ω-cm. With a low electrical resistance, electrons flow easily across the surface or through the bulk of these materials. Charges travel to ground or to another conductive object that the material contacts. Metals like copper and aluminum have exceptionally low resistivities on the order of 10−8 Ω-cm, making them extremely good conductors of electricity. 40.4.2 Dissipative Materials11 Dissipative materials have a surface resistivity equal to or greater than 1 × 105 Ω/sq but less than 1 × 1012 Ω/sq, or a volume resistivity equal to or greater than 1 × 104 Ω-cm but less than 1 × 1011 Ω-cm. For these materials, the charges flow to ground more slowly and in a somewhat more controlled manner than with conductive materials. Dissipative materials are used for ESD control, because they discharge so slowly that they often avoid ESD damage to microstructures that are manufactured in high technology cleanrooms. 40.4.3 Insulative Materials12 Insulative materials are defined as those materials with a surface resistivity greater than 1 × 1012 Ω/sq or a volume resistivity greater than 1 × 1011 Ω-cm. It is clear that the ability of an insulator to dissipate surface charge is so poor that it can be ignored. For a typical 30 cm × 30 cm object sitting ~1 cm from a ground plane, the capacitance of the object is ~10−10 F so that the characteristic time to discharge will be given by the product of its resistance times its capacitance.13 For a conductor, this corresponds to a time of much less than a nanosecond. For a fairly good insulator (>1013 Ω/sq), this corresponds to >1000 s. For extremely good insulators like quartz, Teflon, or SiO2, the material can be assumed to never discharge. Thus, in a cleanroom where high levels of charge are developed on such surfaces, they will build up over the period of days, achieving extremely high levels. Grounding one of these extremely good insulators accomplishes nothing, and the charge remains on the surface. Grounding of conducting or dissipative materials is an important first step in cleanroom static charge control but of no help in dealing with insulators. Details of how to ground the materials, utilization of dissipative materials, selection of insulators that have similar work functions to the materials that they contact (called tribo matching), and techniques for dealing with static charge developed on insulators is a discipline called electrostatic management.

105 Ω/sq Conductive

Dissipative

104 Ω -cm FIGURE 40.7

1012 Ω/sq Insulative

1011 Ω -cm

Surface resistivity.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.9

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

40.9

40.5 CLEANROOM ELECTROSTATIC MANAGEMENT 40.5.1 General Principles A variety of methods have been developed to deal with static charge. The basic methods are grounding facility components (walls, floors, workbenches, and equipment), appropriate use of conductive and static-dissipative materials, and employing local or room ionization to control static charge on insulators. In addition to these basic methods, education of cleanroom personnel in the practice of static control and auditing for compliance with the static control program, are essential for the program’s success. Modern cleanroom environments make extensive use of grounding with conductive and static dissipative materials in an attempt to control electrostatic charge. Grounding prevents the generation of static charge on materials that are connected to ground. If a conductive or static dissipative material does become charged, connecting it to ground will remove this stored charge. To be effective in controlling static charge, conductive and static dissipative materials must be provided with a reliable path for the static charge to flow to ground. The success of any grounding method depends on the integrity of the ground path. In critical applications, ground path monitoring and periodic verification may be important aspects of a static control program. By creating the ground path, the static charge on objects is conducted to ground, rendering the object neutral and eliminating electric fields that had extended from the charged object. It is particularly important to ensure grounding of those surfaces within 300 mm (12 in) of static sensitive product. Care should also be taken with moving parts of equipment. A ground connection that exists when a robot handler is stationary may be lost when the robot is in motion. Flexible grounding connections are advisable rather than relying on conductive lubricants. Static dissipative materials are used in the construction of cleanrooms and minienvironments to reduce the accumulation of static charge. The walls and floors of a cleanroom and panels of a minienvironment may be constructed of these materials. Static dissipative materials should be selected over conductive materials in order to slow down the charge removal process and prevent a damaging ESD event. The static-dissipative materials may be used for parts of equipment that come into contact with sensitive products. Dissipative reticle pods and dissipative work surfaces used for reticle inspection stations are two examples of locations where dissipative materials are the best material choice. In contrast with metal work surfaces or insulative minienvironment walls, the cost of the dissipative material is higher, but often the payback in terms of decreased ESD damage makes the dissipative materials a good investment. Also, in some cases, the properties of the dissipative material may be preferable. For example, metal reticle pods are impractical because of their weight and it is impossible to make a metal viewing port for a minienvironment. Static dissipative packaging materials are also used to shield the product from static charge buildup as it is transported between processes in the cleanroom. This is a common practice in the back end of the fabrication line (BEOL). The slower discharge associated with dissipative packaging will have a lower peak current than the faster discharges. Due to the deep submicron feature size of modern electronics, the time required to dissipate heat from the structure is extremely short14 on the order of nanoseconds. Thus, a discharge from a dissipative object can be orders of magnitude large and not cause damage, whereas the same discharge from a conductor is often lethal to the product. While it is important to employ static dissipative materials to minimize the peak current in a discharge, the use of dissipative materials does not ensure that the product will not charge. To be effective in any static control application, static dissipative materials require a secure path to ground. It will also be important to verify that the materials are cleanroom compatible. Without a path to ground, dissipative materials, while not an ESD hazard, can still become charged and as such represent a contamination hazard. Particularly with construction materials used in cleanrooms, static dissipative properties may be sacrificed to achieve other features such as dimensional stability, low outgassing, or low cost. Grounding methods and static dissipative materials are also used to ensure that charge does not accumulate or transfer from personnel to sensitive products or equipment. A variety of personnel

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.10

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.10

FAB YIELD, OPERATIONS, AND FACILITIES

grounding methods are employed using garments, booties, gloves, static-dissipative flooring, and wrist or heel straps. For successful static charge control, all of these methods must be monitored and verified periodically. It is important to note that dissipative booties do not provide protection unless the floor is dissipative or conductive and provides a path to ground for the person wearing them. Unfortunately, cleanrooms must use many materials that are insulators, such as Teflon, various plastics, and quartz. Very often the insulating materials are an essential part of the product itself. It is not possible to remove the electrostatic charge on insulators by connecting them to ground. Most insulators are easily charged, retain their charge for long periods of time, and are often close to, or part of, the product. Teflon and quartz wafer carriers, oxide-coated wafers, epoxy integrated circuit (IC) packages, and glass hard disk media are examples of insulators in the cleanroom. The requirements of cleanrooms preclude the use of carbon particle or chemical additives to insulating materials to make them static dissipative. Antistatic sprays and solutions can create a contamination problem. Humidity control was proposed in the past as a static control method, but has been shown to be expensive and ineffective. Also, increased humidity plays havoc with photolithography chemistry. Neutralizing static charge on insulators (and isolated conductors) has become a necessity for achieving high product yields in cleanrooms. With few other methods available, some type of air ionization is often used. Using only the highly filtered cleanroom air, ionizers create clouds of both positive and negative air ions to neutralize static charges wherever they exist in the cleanroom environment. 40.5.2 Conductors and Insulators The first principle of static charge control is to ground conductors whenever possible. A corollary to this rule is that conducting or static-dissipative material should be substituted for insulating material wherever possible. Reticles, for example, are made of quartz, which for optical reasons is required and cannot be replaced with a conductor. As a second example, there are cassettes and chemical containers made of Teflon, which is the material of choice due to its chemical immunity to most of the corrosive chemicals used in semiconductor processing. In many cases, it is possible to replace conventional insulating plastics with dissipative material. While this plastic is somewhat more expensive, often the return on investment (ROI) for the dissipative material can be just a few days to a few weeks. This is particularly the case for dissipative plastic in load ports of process tools. In this case, the issue of contamination control is eliminated by the application of dissipative plastics. The ROI for dissipative plastic reticle boxes due to the prospect of reticle damage is even shorter than for dissipative inspection ports in a minienvironment. While it is important to employ dissipative plastics when possible, it is also important to ground them. Because triboelectric charging is strictly related to the differences in the energy levels in dissimilar materials, conductors as well as insulators will charge. Without grounding, the dissipative plastics will still hold any static charge that is created in them. 40.5.3 Grounding It is important to provide a path to ground for every noninsulator in the facility. These grounds come in a variety of formats, several of which will be described here. In each case, the objective is to provide a path to ground for any static charge that is generated in the facility. Personnel. Personnel are a constant source of static charge. The action of walking is inherently a static charge-generating mechanism. For that reason, it is a good ESD control practice to provide a path to ground for static charge. In manual applications such as reticle inspection and handling of dies, the conventional solution is the use of a wrist strap on the operator. This involves having the operator wear a dissipative strap that is connected by a wire to a ground point in the work area. Another approach is the use of ESD-safe chairs that ensure continuity of the operator to ground. This is done in concert with ESD-certified garments that have some number of dissipative threads sewn into the cloth. The wrist strap technique is not practical in a Class 1 fab area as it requires exposed skin at the wrist to make the contact. Also, many operations in a Class 1 fab are performed standing,

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.11

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

40.11

so the use of ESD-safe chairs is also not applicable in Class 1 applications. In these cases, the use of foot appliances may be used to ensure electrical contact between the operator and ground. Foot appliances are usually in the form of boots with dissipative soles or in the form of a heel strap that fits inside the operator’s shoe and extends beneath the sole. It is important to note that such appliances are of no use unless the floor is conductive or dissipative. A dissipative floor is typically made of a bulk material that is rolled into place and installed, or of a dissipative coating that is, in effect, painted onto the floor. Part of a good ESD control program involves periodically checking the continuity of the floor to ground. Transporting and Storage. Reticles wafers and packaged parts are often transported through the facility. Packaged parts will fare best if they are carried in dissipative carriers by operators wearing proper footgear and walking on an ESD-safe floor. When carts (sometimes called personnel guided vehicles, or PGVs) are used, they should be electrically continuous to ground, either equipped with a drag chain or with ESD-safe wheels. The latter are made up of dissipative tires and have special bearings with conductive lubricant. Drag chains are simply light weight chains that hang down from a cart to provide electrical contact to the ESD-safe floor. Generally, it is good practice to use two chains to avoid discontinuity as the chain moves along the floor. This technique is highly effective in avoiding both EMI as the cart docks to a tool and damage to product as it is lifted from the cart by a grounded operator. 40.5.4 Air Ionization When insulators cannot be avoided, the problem of electrostatic charge cannot be solved by simply grounding them. Insulators will not support an electrical current, so they cannot be handled by providing them continuity to ground in this conventional way. Air ionization is the tool for eliminating surface charge on an insulator. The action of air ionization is to make the air slightly conductive and provide a path to ground from all parts of the surface of the insulator. This technique is discussed in detail in the following section.

40.6 AIR IONIZATION FOR STATIC CHARGE CONTROL Air is a good insulator, so any static charge that develops on a clean surface of a good insulator will remain on that surface indefinitely. Air ionizers are used to decrease the electrical resistivity of the air through the addition of ions that act as charge carriers. Air consists primarily of nitrogen, oxygen, and carbon dioxide, with water vapor and trace gases. Air ions are gas molecules in the air that have either lost or gained an electron. Air ionizers are used to introduce air ionization into the room. Ions naturally occurr in the air, especially after a lightning storm, but in a cleanroom the HEPA or ultra low penetrating air (ULPA) filters the ions from the air. Because air ions are naturally occurring items, they have no negative effects on the health of operators. Positive and negative air ions are present in normal outside air, where they are the result of radioactive decay of materials in the soil (e.g., uranium) and gases in the air (e.g., radon). But most air ions are stripped out of cleanroom air by high efficiency air filtration. This makes the air in the cleanroom very insulative and encourages the generation of static charge. Air ionizers restore and increase the level of air ions in the filtered cleanroom air. When the ionized air comes in contact with a charged insulating surface, the charged surface attracts air ions of the opposite polarity. As a result, the static charge on the insulator is neutralized. Air ions of both polarities are required for neutralization, because both polarities of static charge are created in the cleanroom. This is shown in Fig. 40.8. There are three methods that are commonly used to make air ions for charge control. These methods are corona, photoelectric, and radioisotope ionizers. While the ions created by each are identical, each method generally has its own application. The tradeoffs involve issues of cleanliness, ion distribution requirements, shielding issues, voltage balance (precision) level, and government regulations. Each type is discussed in the following sections.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.12

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.12

FAB YIELD, OPERATIONS, AND FACILITIES

+ +

Charged air molecules

−

−

+

+

+ + +

−

−

+

−

+ −

−

−

−

+

−−−−−−−−−−−−−−−−

+

+

+++++++++++++++

Insulator FIGURE 40.8

Neutralizing surface charges with bipolar air ionization.

40.6.1 Corona Ionization The most common method used to create air ions in cleanrooms is corona ionization. In corona ionization, a very high electric field is created by applying high voltage to one or more sharp emitter points. This technique involves the use of high voltage (~5 to 20 kV). The voltage is applied to a set of sharp points. An intense electric field is established very near (~100 µm.) the points. This field accelerates free electrons to a sufficiently high energy to allow them to ionize molecules with which they collide. When the voltage on the point is positive, positive ions are repelled into the environment, and when the point is negative, negative ions are delivered. Corona ionizers are made with ac and with dc voltages. The basics of corona ionization for positive and negative polarities are illustrated in Fig. 40.9. Corona ionizers can be made using ac or dc voltages. Each has an advantage. Both will be described next. The ac Ionizer. uses a step-up transformer to create the high voltage bias (~7 kV rms) that is required to make ions. See Fig. 40.10. The transformer can be easily used to automatically create equal positive and negative voltage swings so that ac ionizers do not require any form of adjustment to work. Because of the simplicity of the ac ionizer, it is the least costly of most ionizer applications. Because the ac type ionizer produces the positive and negative ions in sequence from the same emitter

Positive high voltage

• Negative high voltage delivers negative ions • Positive high voltage delivers positive ions Sharp point Positive ion moves away Electron dislodged

FIGURE 40.9

Corona ionization.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.13

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

FIGURE 40.10

40.13

AC ionizer.

point(s), these ions are separated in time by half of the period of the ac power line (i.e., 1/100 or 1/120 s). This means that the waves of positive and negative ions are rather close to each other, making loss through recombination a large factor. AC ionizers typically use fast airflow velocity to minimize recombination. This is not always desirable in a cleanroom environment. The airflow issue and the increased emitter point current, used to offset the recombination, limits the ac ionizer to Class 100 cleanrooms or above. Experience shows that the actual offset voltage15 of an ac ionizer as measured with a charge plate monitor (CPM) is typically less than 10 V. It has been shown,16 however, that the CPM is not capable of recording voltage excursions faster than 1 Hz. In contrast, small objects like a single chip are capable of tracking the voltage excursions driven by the time-varying electric fields from an ac ionizer. ac ionizers are not recommended for the handling of diced dies. AC ionizers do find application in many of the BEOL processing steps to protect wafers from ESD damage. This is in part due to their simplicity and in part due to their lower cost as compared with all other types of ionizers. The dc Ionizer. Employs a high-voltage power supply to create the necessary voltage. DC ionizers use separate emitter points for the positive and negative dc HV power supplies to create the ions. In order to provide equal numbers of positive and negative ions from separate sources, dc ionizers need some form of control to maintain this balance. Owing to the fact that the positive and negative emitters are well separated from each other, recombination is a lesser effect, and the dc ionizers can sometimes use lower airflow velocity to deliver the ions to the location where the ionization is required. Because of their lower recombination rates as compared with ac ionizers, dc ionizers are used in more contamination-critical applications. Their more efficient delivery allows them to be operated at lower currents and therefore to operate with cooler emitter tips. Thus, any contamination from the tip can be extremely well controlled. Many dc ionizers achieve Class 10 operation and are only limited by the turbulence and particulation issues of the fan and its motor. DC ionizers with fans cannot be used in the front end of the line due to the prospect of contamination due to air turbulence. In the BEOL, however, fan type ionizers are common. Pulsed dc Ionizers. The other notable use of dc ionizers in a Class 1 cleanroom is as a ceiling emitter. An array of ceiling emitters is mounted to the ceiling of the cleanroom, typically on 4 to 6 ft centers and the laminar airflow from the HEPAs drives the ionization through the entire room. Normally the ionizers are operated in a mode called pulsed dc. This is very much like the steadystate dc mode described earlier, but the two polarities are turned on one at a time, with on times of Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:19

Page 40.14

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.14

FAB YIELD, OPERATIONS, AND FACILITIES

1 to 10 s. Pulsed dc provides even less recombination than steady-state dc. As a trade-off, objects in the room swing through voltage levels of ±50 to ±200 V, making this method unacceptable for the most sensitive products such as magnetoresistive (MR) heads, but ideal for applications where such sensitivity is not an issue and where large levels of charge must be eliminated globally. 40.6.2 Photoelectric Ionization The photoelectric ionizer uses extreme UV to soft x-ray photons to create ions. When the energy of a photon exceeds the ionization potential of the medium it traverses, the photon can create an ion by collision with an atom. This is called the photoelectric effect.17 The most common method of photoelectric ionization involves the use of very soft x-rays. These are x-rays in the range of 5 to 10 keV as contrasted with medical or dental x-rays, which are in the range of 80 to 175 keV. The lower energy makes them suitable for use as an ion source, because the air is rather opaque to photons in this energy range. A soft x-ray source has a ~100 percent efficiency for creating an ion within about 1.5 m for each photon it emits. While neither the licensing (in the United States by the FDA) nor the safety requirements are very difficult to manage, photoelectric ionization represents extra steps that are necessary for the use of this technology. This type of ionizer is not common in semiconductor processing due to the high cost of the product. It is, however, a very efficient method for generating and delivering ions in a mini-environment. 40.6.3 Alpha Ionization The alpha ionizer method involves the use of ionizing radiation to make ions. While several forms of ionizing radiation sources are available, only a (alpha) sources are used for static control. The other forms of radiation source have a much longer range and thus require shielding in impractical amounts. Most commonly, Polonium210 is employed. It produces a particles with a range of only 3.8 cm in air and 0.02 mm in aluminum18 so that virtually none of the a particles travel far enough to represent a health hazard or create a shielding requirement. The other aspect of Po210 that makes it an ideal choice is that it decays to Pb206, which is a naturally occurring stable isotope. Unlike Po210, many other sources decay into isotopes that may be active as well. Alpha ionizers can be used in high temperature (~100°C) and in vacuum applications.

40.7 ELECTROSTATIC MEASUREMENT 40.7.1 Measuring Electric Field The presence of electrostatic charge is indicated by an electric field. For that reason, identifying the presence of an electric field is an important diagnostic technique in dealing with static charge. An electrostatic field meter is the tool that is used for this application. Figure 40.11 shows a typical field meter. The field meter is calibrated in units of volts/length and typically quoted in kV/in for historical reasons. The field meter measures the field at a distance of 1 in from the object. To operate it accurately, it is necessary to ensure that it has a ground reference. This is normally supplied by a ground wire from the case to a grounded object nearby. Often, the instrument is used by a grounded operator with no gloves on or with dissipative gloves, and the ground can be made simply by contact of the operator’s hand. 40.7.2 Measuring Ionizer Performance Because the majority of ionizers use corona to make ions, a high voltage is required. With high voltage come electric fields. These fields are responsible for making the ions, but they also drive the voltage on objects around them to a nonzero voltage. While the induced voltage is most often much

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

05/04/2005

15:55

Page 40.15

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

40.15

lower than the voltages caused by static charge, it can be problematic nonetheless. For that reason, one of the parameters that must be measured to benchmark ionizer performance is the balance voltage. Loosely speaking, it is a measure of how accurately the ionizer’s positive and negative voltages can be set equal. Balance voltage is measured using a CPM.19 It is also used with pulsed dc ionizers to measure the variation of the balance voltage, referred to as the swing voltage. The CPM, Fig. 40.12, is the instrument that is used to measure the performance of an ionizer. It includes a 6 in × 6 in (150 mm × 150 mm) plate isolated from ground with a capacitance of 20 pF, as the voltage sensor. The balance voltage is the voltage to which the ionizer drives the plate. In addition, the CPM is used to measure the discharge time that is defined as the time to drive the plate from 1000 to 100 V. 40.7.3 Measuring ESD-induced EMI Because of the transient nature of ESD-induced EMI, it is impossible to detect it using a spectrum analyzer. The average energy broadcast by ESD FIGURE 40.11 An electrostatic field meter. events is much too low when the averaging time is less than a second or slower, as is the case for a spectrum analyzer. What is needed is an instrument that is some type of an event detector or a transient analyzer. The most common method for making this sort of measurement involves a digital sampling oscilloscope (DSO) and a wide bandwidth antenna. This type of measurement has been reported elsewhere.20,21 An advantage of this technique is that it can be used to determine the location of the ESD event and by measuring the pulse shape, it can differentiate ESD events from other sources of noise (e.g., ozone generators and gaseous discharge flash lamps). The signature of ESDinduced EMI is now a wave-shape which is a sum of multiple, damped, and high frequency sinusoids. The signal has a fast attack (~1 ns) and a slower decay (~100 ns). The signal is also characterized by large variations in amplitude. See Figs. 40.13 and 40.14. Another technique for detecting the presence of EMI from ESD events is through the use of a device called an EMI locator. Such a device is a transient detector with a signal source based upon an integral antenna. These devices are tuned to a bandpass that is appropriate for ESD-induced EMI and are sensitive only to narrow signals (typically with durations <<1 µs). Such instruments are available from several companies. One example is shown in Fig. 40.15. The advantage of the DSO approach to measurements is that a DSO can be much more selective of pulse shape. In addition, it offers the possibility of determining the location of the event. Moreover, the DSO can be used with a probe to look for signals on conductors. Notably, these sorts of EMI transients can sometimes be found on the neutral line of the power to a process tool. The disadvantage of the DSO approach is that the technique is more costly to implement and much less portable than the ESD detector approach. FIGURE 40.12 Charge plate monitor.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:20

Page 40.16

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.16

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 40.13

A typical ESD event.

FIGURE 40.14

An event that is not ESD related.

FIGURE 40.15

EM aware.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:20

Page 40.17

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

40.17

Whether an oscilloscope or an event detector is employed, it is important to use the instrument to make a diagnosis. The existence of a signal is useful information to have when a robot exhibits unwanted behavior. It is possible to identify the effect more completely by observing the environment while listening to the detector or watching the oscilloscope triggers. It is often possible to identify that the events are taking place at the same time as some other phenomenon. For example, the triggers might be occurring at the same time as a front opening unified pod (FOUP) passes by a certain location on the overhead track, or the events may coincide with a robot approaching a wafer in a given cassette. This suggests that there is a charged object involved and helps lead one toward a solution to unwanted robot behavior.

40.8 AIR IONIZER APPLICATIONS 40.8.1 Common Applications Static charge can cause problems anywhere in the cleanroom environment. To control these problems ionizers are used in a variety of configurations. Applications can involve cleanrooms that operate in the Class 10 to Class 100 range and are typical of the BEOL. In contrast, front-end cleanrooms are most often characterized by high levels of automation and typically require cleanliness levels in the Class 1 or higher realms. These two scenarios require very different ionization solutions. Each of these situations are discussed below. The most common method used in Class 1 ballroom-style cleanrooms is room air ionization. Such ionizers are mounted at or near the HEPA-covered ceiling and the laminar airflow is ionized as it passes the ionizer emitter points. The advantage of this type of system is that it brings static charge control to any surface that is exposed to the room airflow. Corona ionizers provide global coverage of the insulators moving through the room. These ionizers are either bars hung from the ceiling or ceiling emitters extending down from the ceiling. The distance that the emitter points stand off the ceiling is generally 30 to 100 cm. The purpose of this distance is to separate the sources of the ions from the grounded elements of the ceiling. A typical room system will provide global coverage with discharge times (90 percent reduction in charge levels) in the range of 20 to 120 s. High ceilings and low airflow velocities represent the upper level and 8-ft ceilings with 0.5 m/s (100 fpm) provide the fastest discharge times. Many cleanrooms today employ mini environments to protect the product from contamination. This configuration involves keeping silicon wafers in clean enclosures (Standard Mechanical Interfaces or SMIF for wafers or reticles and FOUPs for 300 mm wafers) as they are transferred from one process tool to another. The individual tools are also fully enclosed to isolate contamination from the room. While this strategy blocks the contamination from contacting the product, it also blocks the ionization from contacting the products. Ions recombine as they pass through a HEPA filter, so room systems do not provide any electrostatic protection of objects within the process tools. To provide protection within the process tools, ion bars are mounted within the mini environments as illustrated in Fig. 40.16. The bar, most typically a pulsed dc corona bar, should be mounted below the HEPA filter within the mini-environment if possible. To minimize offset voltages, the bar should be located at least 30 cm from the product. If the direct HEPA location is not feasible (due to mounting particulars or due to a metal structure in the path of the airflow), a location should be chosen that is not immediately adjacent to a grounded metal structure, if possible. Care should be taken to select a location such that the airflow direction will carry the ions toward the object to be protected, as the ions are not efficiently drawn against the wind electrostatically for more than a few inches. For 300 mm applications, bars are located below the HEPA in the area of the factory interface module, as illustrated in Fig. 40.17. In general, the FOUPs shield the wafers from the laminar airflow, making it difficult to provide ionization. For this reason, and as the 300 mm wafers are larger than their 200 mm ancestors, two bars are used for 300 mm applications, and one bar is used for 200 mm applications. The question often comes up as to whether room ionization is necessary in a mini environment cleanroom. In fact, from a contamination standpoint, most of the electrostatically-driven sedimentation

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:20

Page 40.18

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.18

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 40.16

Ionizer applications in the Class 1 cleanroom.

occurs in the mini environments and in the carriers. The electric fields from objects outside the carriers penetrate them and add to the electric fields inside. As the carrier moves through the room, or as charged objects in the room move past the carrier, the fields cause contamination within the carrier to mobilize, representing a secondary contamination issue. Also, charged objects within the room, but external to the mini environments, can drive a discharge from one object to another. While this will not affect the contamination control of the product directly, it does generate EMI in the room and can easily cause irrational performance by the robotics. For these two reasons, many operations choose to install ionization both within the mini-environments and in the cleanroom itself.

HEPA

Ionizer

40.8.2 Severe Discharge Applications Severe discharge requirements in tools are the ideal applications for the photoelectric ionizer, and in particular in environments where it is possible to mount an ionizing bar at a distance of 30 cm or greater from the FIGURE 40.17 HEPA. product, or in applications involving high levels of charge. Practically, this means either >20,000 V or highly capacitive objects. Cleaning processes tend to produce high charge levels. Also, processes that place flat products (such as wafers or plates) on a flat surface and then raise them up a significant distance when the processing is complete are candidates for high charging. In order to use the photoelectric ionizer, it is necessary to have an enclosure that serves as a complete shield against the photons. A thin shield is adequate (~5 mm of plastic or 750 µm of aluminum),

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:20

Page 40.19

ESD CONTROLS IN CLEANROOM ENVIRONMENTS ESD CONTROLS IN CLEANROOM ENVIRONMENTS

40.19

but it is necessary to ensure that there are no hairline cracks in the structure such as doorways without an overlapping seal, as these can represent a way for the photons to escape. In addition to the shielding requirement, a physical knife switch is required that shuts down the ionizer when the door is open. If these requirements are followed, it is straightforward to get an FDA x-ray cabinet license for this type of ionizer. While this small amount of paperwork is not required for a corona ionizer, there are severe applications where this type of ionizer is the only solution that will provide protection for the process. The other ionizer type that may be used in tight confines, or where static charge levels can be quite high, is the alpha ionizer. The alpha ionizer involves no high voltage and so has a balance voltage of zero. It can be used with the most static-sensitive products, such as MR heads. The alpha ionizer requires airflow to deliver the ionization to the item to be protected, so it needs either a blower (discussed below) or it needs to be placed in a laminar flow field. It can, however, be operated very close to the product with no significant effects. Since the range of Po210 alphas in air is 3.8 cm, placing the ionizer within a distance of 2 in of the source is perfectly acceptable. Again, at a short distance, the alpha ionizer is capable of dealing with extremely high charge levels. It requires minimal licensing, but, in practice, it does cause concern to manufacturing workers who do not understand it and require training by the ESD team on site.

40.9 CONCLUSIONS Reduction of product defects to the levels acceptable in world-class cleanroom manufacturing requires continual attention to static charge control. Uncontrolled, static charge is responsible for increasing the number of particle-related defects, for damaging products and equipment with ESD, and for interfering with factory automation. As factory profitability increasingly depends on both high yields and high product throughput, solving static-related problems in cleanrooms has become a necessity. Static charge control starts with the grounding of personnel, equipment, and any materials that come close to static-sensitive products. Insulating materials should be removed whenever possible and replaced with static dissipative equivalents. When insulators must be used to satisfy other process requirements, ionizers are used to neutralize static charges on the insulators. It should be remembered that insulators are very often a part of the product itself and cannot be eliminated. Air ionization is one of the few methods available for controlling static charge in high-quality cleanroom environments. In some cases, it is the only method that can be used. Ionizers can reduce the number of contamination and ESD-related defects occurring in both mini environments and in production equipment.

REFERENCES 1. Trigwell, S., C. Yurteri, and M. K. Mazumder, “Unipolar Tribocharging of Powder: Effects of Surface Contamination on the Work Function,” Proceedings of the Electrostatic Society of America Annual Meeting, East Lansing, MI, June 27–30, Laplacian Press, San Jose, CA, pp. 27–35. 2. Levit, L., and W. Guan, “Measuring Tribocharging Efficiency in Varying Atmospheric Humidity and Nitrogen,” Proceeding of the Electrostatic Society of America Annual Meeting, East Lansing, MI, June 2001, Laplacian Press, San Jose, CA, pp. 43–50. 3. Donavan, R. P., Particle Control for Semiconductor Manufacturing, Marcel Dekker, New York, 1990. 4. Wu, J. J., R. J. Miller, D. W. Cooper et al., “Deposition of Submicron Aerosol Particles During Integrated Circuit Manufacturing: Experiments,” Proceedings of the Ninth International Symposium on Contamination Control, Los Angeles, ICCCS, 1988, pp. 27–32. 5. Levit, L. B., T. M. Hanley, and F. Curran, “In 300 mm Contamination Control, Watch out for Electrostatic Attraction,” Solid State Technology, Vol. 43(6): June 2000, pp. 209–214.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH40.qxd

04/04/2005

21:20

Page 40.20

ESD CONTROLS IN CLEANROOM ENVIRONMENTS 40.20

FAB YIELD, OPERATIONS, AND FACILITIES

6. Steinman, A., “Static-Charge—The Invisible Contaminant,” Cleanroom Management Forum, Microcontamination, Vol. 9 (1992): 46–512. October 1992. 7. Montoya, J., L. Levit, and A. Englisch, “A Study of the Mechanisms for ESD Damage to Reticles,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 24(2): 78–85, April 2001. 8. Semiconductor Equipment and Material International, SEMI, E78-0998, Electrostatic Compatibility—Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment, SEMI, San Jose, CA, 1998. 9. Levit, L. B., and W. Guan, “Measurement of the Magnitude of Triboelectrification in the Environment of the 157-nm Stepper,” Proceedings of the 21st Annual BACUS Symposium on Photomask Technology, SPIE Publishing Services, 2001, pp. 307–312. 10. ESD Association, ESD ADV1.0-2003, Glossary of Terms. ESD Association, Rome, New York, June 1, 1998. 11. Electronic Industries Alliance, EIA-541, Packaging of Electronic Products for Shipment, EIA, Arlington, VA. 12. Institute for Environmental Sciences Technology, IEST-RP-CC-022.2, Electrostatic Charge in Cleanrooms and Other Controlled Environments, IEST, Rolling Meadows IL, January 2004, pp. 9, 10. 13. Halliday, D., R. Resnick, and J. Walker, Fundamentals of Physics Extended (6th ed.), Wiley, New York, 2000. 14. Levit, L. B., and A. Walash, “Measurement of the Effects of Ionizer Imbalance and Proximity to Ground in MR Head Handling,” Proceedings of EOS/ESD Symposium, Vol. EOS-20, 1998, pp. 375–382. 15. ESD Association, ANSI-EOS/ESD-S3.1-1991, For the Protection of Electrostatic Discharge Susceptible Items-Ionization, ESD Association, Rome, New York, 1994. 16. Newberg, Carl E., “Analysis of the Electrical Field Effects of ac and dc Ionization Systems for MR Head Manufacturing,” Proceedings of EOS/ESD Symposium, Vol. EOS-21, 1999, pp. 319–328. 17. Annalen der Physik, “On a Heuristic Point of View Concerning the Production and Transformation of Light,” (öber einen die Erzeugung und Verwandlung des Lichtes Betreffenden Heuristischen Gesichtspunkt), March 1905. 18. Trower, P., “High Energy Particle Data,”UCRL-2426, Vol. II (1966 revision), 1966, p. 42. 19. ESD Association, ANSI-EOS/ESD-S3.1-1991, For the Protection of Electrostatic Discharge Susceptible Items-Ionization, ESD Association, Rome, New York, 1994. 20. Bernier, J., G. Croft, and R. Lowther, “ESD Sources Pinpointed by Analysis of Radio Wave Emissions,” Proceedings of the 19th Annual EOS/ESD Society, September, 1997, Santa Clara, CA, Paper 2A.2. 21. Levit, L. B., L. G. Henry, J. A. Montoya, F. A. Marcelli, and R. P. Lucero, “Investigating FOUPs as a Source of ESD-induced Electromagnetic Interference,” Micro Magazine, April 2002.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:20

Page 41.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 41

AIRBORNE MOLECULAR CONTAMINATION Chris Muller Purafil, Inc. Doraville, Georgia

41.1 INTRODUCTION TO CHEMICAL CONTAMINATION AND DEFINITION OF AMC The term airborne molecular contamination (AMC) covers a wide range of chemical contaminants that can be present in cleanroom air. Outdoor air, manufacturing processes, fugitive emissions from process equipment and chemical supply lines, cross-contamination between manufacturing areas, chemical storage areas, off-gassing from building and construction materials, accidental spills, and bioeffluents from cleanroom personnel can all contribute to the overall AMC load in the cleanroom. AMC can be detrimental to many processes and products and can also represent considerable health hazards to personnel. AMC can be in the form of gases, vapors, or aerosols, and their chemical nature can be organic or inorganic and can result in a large number of potential processing problems. Cases of uncontrolled boron and phosphorus doping, etch rate shifts, changes in the wafers’ electrical properties, silicon carbide formation following pre-oxidation clean, stepper optics hazing, threshold voltage shifts, high efficiency particulate air (HEPA) filter degradation, fab corrosion, and more have been reported. However, the effects of specific AMC on individual processing steps are still not very well understood. As semiconductor device geometry continues to decrease into the deep submicron level, the importance of chemical contamination has now become as important as particulate contamination. AMC can impact almost all aspects of submicron device fabrication, from overall fab operation to final device performance. New chemistries introduced to manufacturing processes have also been shown to cause unforeseen AMC-related effects. Hydrogen sulfide, for example, poses a significant threat to the metallization process as the transition is made from aluminum to copper. As copper appears ready to become the main on-chip conductor for all types of integrated circuits (Fig. 41.1), it is showing up in the plans of chip and production equipment makers worldwide and is quickening the shift to AMC-free manufacturing environments.1

41.2 CLASSIFICATION OF AMC The first consideration in the selection of an AMC control system should be an assessment for the type and quantities of AMC to be controlled. This can be done by direct gas monitoring or with semiquantitative techniques using passive or real-time monitors.2,3 There can be dozens of contaminants

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

41.1

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.2

AIRBORNE MOLECULAR CONTAMINATION 41.2

FAB YIELD, OPERATIONS, AND FACILITIES

1100 1000 900 800 700 600 500 400 300 200 100 0

1996

FIGURE 41.1

1997

1998 1999 2000 2001 2002 Worldwide sales in US$ millions

2003

2004

Expected growth in copper film tools.

present in a makeup or recirculation airstream, but there may only be relatively few that require close control. Contaminant classifications can help to group similar contaminant types and help make the selection of the proper AMC control system more straightforward. 41.2.1 AMC Classifications SEMI Standard F-21-1102 classifies AMC in cleanrooms by their chemical properties providing a way to characterize the environment by groups of materials that could have similar effects on an exposed wafer.4 The purpose of this standard is to classify cleanrooms with respect to their molecular (nonparticulate) contaminant levels. The classifications are defined as follows: • • • •

Acid: A corrosive material whose chemical reaction is that of an electron acceptor Base: A corrosive material whose chemical reaction is that of an electron donor Condensable: A chemical substance capable of condensation on a clean surface (excluding water) Dopant: A chemical element that modifies the electrical properties of a semiconductive material

Given the unfavorable publicity that personnel exposure to potentially toxic and hazardous materials in semiconductor manufacturing has received, AMC control systems must also be designed to protect people as well as products. Thus, another way to characterize AMC would be based on the potential health effects to exposed personnel. In this light, we could generally classify AMC as below (in order of decreasing severity): • Toxic: Substances that can cause damage to living tissue, impairment of the central nervous system, or in extreme cases, death • Corrosive: Substances that are likely to cause deterioration or damage to the interior of a building or its contents • Irritant: Substances that can cause discomfort, and potentially permanent damage, to an exposed person • Odorous: Substances that primarily affect the sense of smell For personnel protection, various regulations and guidelines are in place pertaining to exposure to chemical contaminants. The guidelines for exposure to materials listed in Table 41.1 are those established for worker exposure in (typically) industrial environments. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.3

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

TABLE 41.1

41.3

Chemical Substances Common to Semiconductor Manufacturing Contaminant Types

Representative compounds

Toxic

Corrosive

Irritants

Odorous

Ammonia Arsine Boron trifluoride Carbon tetrafluoride Chlorine Hydrochloric acid Hydrofluoric acid Methyl alcohol Nitric acid Methylene chloride Phosphine Phosphorus pentafluoride 1,1,1-trichloroethane

Acetic acid Ammonia Chlorine Fluorine Hydrochloric acid Hydrofluoric acid Nitric acid Nitrogen dioxide Ozone Sulfur dioxide Sulfuric acid

Acetic acid Acetone Ammonia Chlorine Formaldehyde Isopropanol Methyl alcohol NMP Ozone PGME PGMEA Toluene Xylene

Acetic acid Ammonia Butyl acetate Chlorine Formaldehyde Hydrofluoric acid Hydrogen sulfide Isopropanol NMP PGME PGMEA Phosphine Xylene

Although none of these classifications are definitive, an environmental assessment can at least provide the AMC control system designer a starting point with an indication of the types of contaminants that may be present and levels to which they must be controlled. Even with a classification system in place, it does not always guarantee a quick and easy selection of the most effective and economical AMC control system. What it does do is help determine if absolute contaminant control is required or whether a system with a fractional efficiency could be employed. 41.2.2 AMC Effects In much of the world today, the outdoor air contains levels of ozone, sulfur and nitrogen oxides, and volatile organic compounds (VOCs) high enough to cause problems in cleanrooms. There are elevated levels of sulfur and nitrogen oxides from automobile exhaust and combustion processes in urban areas. Atmospheric chlorine and boron can be found in coastal locations. Ammonia and amines may be present from agricultural activities. AMC can cause damage to raw materials, inprocess and finished products, manufacturing and mechanical equipment. Some of the effects that have been well documented are listed below: Deep ultraviolet (DUV) photoresists T-topping Uncontrolled boron or phosphorus doping Etch rate shifts SiC formation following pre-oxidation clean Adhesion failure Threshold voltage shifts Resistivity shifts Nucleation irregularities

Wafer and stepper optics hazing Decreased optical transmission High-contact resistance Corrosion on disk media and recording heads HEPA filter degradation Ineffective cleaning Facility/equipment corrosion

41.3 AMC CONTROL CONSIDERATIONS Although there will be differences in how AMC control will be applied, there are general guidelines that can be considered. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.4

AIRBORNE MOLECULAR CONTAMINATION 41.4

FAB YIELD, OPERATIONS, AND FACILITIES

41.3.1 Overview of AMC Control Systems 1. Makeup air systems will see primarily atmospheric contaminants if the outside air intake locations are chosen carefully. Zero downtime systems should be considered for makeup air handlers. A balance should be struck between the desired levels of AMC control versus pressure drop versus service life. 2. Recirculation air systems require that AMC control be chosen based on functional area requirements. 3. Exhaust air systems generate a significant number of complaints from neighboring facilities due to nuisance odors from exhaust abatement equipment. Continuous monitoring and regular maintenance is called for. Careful location of exhaust stacks to prevent reentrainment, compliance with environmental regulations, and dispersion modeling is required for all production facilities. 4. Minienvironments with self-contained chemical contaminant control systems can significantly reduce the occurrence of odors related to production processes. Added benefits include increased protection for the product and the reduction of the total exhaust requirements. Source control for outdoor air contaminants is not feasible or practical, therefore, ventilation control would be a likely option explored for general or specific AMC control. However, this may not prove viable because the increased use of dilution air is neither cost-effective nor energy-efficient. TABLE 41.2

Air Quality Survey Showing Levels of AMC in Different Areas of a Fab

Contaminant measured Acetic acid Acetone Ammonia Benzene n-Butyl acetate Chlorine Decane Dichlorobenzene Ethoxyethylacetate Ethylebenzene Ethyltoluene Formaldehyde Freon Hydrogen sulfide Isopropanol Isopropylbenzene Methylethylketone Methylmercaptan Methylamine Nitrogen dioxide NMP Ozone Styrene Sulfur dioxode Tetrachloroethylene Toluene Trichloroethane Trichloroethylene Trimethylbenzene Xylene TVOC

Outside airstream

Recirculation airstream

Cleanroom air

3.0 mg/m 31–166 mg/m3

242 µg/m 3.9 mg/m3

8.8–44.2 µg/m 38.95 µg/m3

11.6–60.4 µg/m3 0.32 mg/m3

3.13 µg/m3

5.61 µg/m3 2.63 µg/m3 5.6–12.3 µg/m3 2.26–6.11 µg/m3 0.60 µg/m3 1.67 µg/m3 10.15 µg/m3 1.60–7.67 µg/m3 38–65 µg/m3

3

3

Minienvironments

3

1.46-3.48 mg/m3 1.2–10.9 µg/m3 1.87 µg/m3 5.8–8.8 µg/m3 12.28–49.13 µg/m3 4.4 mg/m3

0.97 µg/m3 0.99 µg/m3

0.31–0.70 mg/m3 1.5 mg/m3 0.79 µg/m3 1.2 mg/m3 0.04–0.10 mg/m3 0.15–0.38 mg/m3 0.291–1.457 mg/m3 0.65 mg/m3 0.10–0.40 mg/m3 0.08–0.37 mg/m3 33.3–157.6 µg/m3

0.34 mg/m3 195 µg/m3

12–25 µg/m3 20–80 µg/m3 1.19 µg/m3 15–200 µg/m3 0.99 µg/m3 0.93 mg/m3 3.09 µg/m3 0.79–1.77 µg/m3 7.3–153.9 µg/m3 84–110 µg/m3

30–40 µg/m3 10–20 µg/m3 2.36 µg/m3 10–15 µg/m3 3.97 µg/m3 40.98 µg/m3 0.61 µg/m3 1.80–9.91 µg/m3 9.28–36.39 µg/m3 129.67 µg/m3

0.82–2.5 µg/m3

17.85 mg/m3

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.5

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.5

Further, bringing in additional quantities of outside air could result in substituting one group of contaminants for another—those with sources outside the cleanroom for those that are internally generated. In areas with poor outdoor air quality, air cleaning must be employed. A chemical filtration system as an integral part of a cleanroom HVAC system, can effectively reduce AMC to levels that are at or below the level of detection for the monitoring techniques employed. Properly applied, gas-phase air filtration also has the potential for energy savings. Makeup air-systems must typically be designed to control SOx, NOx, ozone, VOCs, and some site-specific contaminants such as chlorine, organophosphates, and ammonia. Chemical filtration equipment in recirculation systems must be designed to remove a wide array of acids, bases, hydrocarbons, and other VOCs. As a rule, organic compounds, although perhaps not the most damaging, are the most abundant types of AMC found in these facilities. An example of an air quality survey performed at one facility is shown in Table 41.2. It shows the types and amounts of AMC being introduced from the outside, the effect of dilution (if any) with ventilation air, as well as the contamination being introduced from inside the facility.

41.4 IMPLEMENTING AMC CONTROL 41.4.1 Three-Step Methodology for Optimum Control of AMC AMC control has now become fully integrated into the cleanroom environmental management requirements of high-tech manufacturing facilities. The optimum control of AMC involves three steps: 1. Assessment of the air quality both outside and inside the facility to identify target contaminants as well as those that could affect the performance of the AMC control system. 2. Selection and qualification of an AMC control system. 3. Ongoing monitoring of both the controlled environment and the performance of the AMC control system.5 Cleaning the outside air being used for ventilation and pressurization, removing tramp and fugitive emissions from recirculation airstreams, and cleaning process emission and exhaust streams are some of the many applications that require AMC control. Just as there are a wide variety of AMC control applications in the cleanroom, there seems to be an equal number of control options available to contamination control personnel. With what may seem to be an overwhelming number of items to be considered, how is the contamination control engineer supposed to make the proper choice for a particular application? Following are some of the key issues to understand and the steps one needs to take to establish a successful AMC control program.

41.5 GAS-PHASE AIR FILTRATION PRINCIPLES Gas-phase (chemical) air filtration, as applied in mechanical ventilation systems, uses two main mechanisms to remove airborne gaseous contaminants. One, which is a reversible physical process, is known as adsorption. The other, which involves adsorption and irreversible chemical reaction(s), is termed chemisorption. Before chemical filtration media or equipment are discussed, it is appropriate to present a brief overview of gas-phase air filtration at this time. 41.5.1 Adsorption Adsorption is a surface phenomenon and the removal capacity of an adsorbent is directly related to its total surface area. Therefore, it is important to develop as large an accessible surface area per unit

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.6

AIRBORNE MOLECULAR CONTAMINATION 41.6

FAB YIELD, OPERATIONS, AND FACILITIES

volume as possible. Granular activated carbons (GACs) and activated aluminas are the most common materials that fulfill this requirement. The rate at which adsorption occurs is dependent on the time required for the gases to diffuse from the external surface to the interior adsorptive sites. Therefore, this rate is inversely proportional to the size of the adsorbent. The removal capacity, however, depends on the total available surface area of the adsorbent. Since the internal surface area of the walls of the pores makes up practically all of the surface area of the adsorbent, the capacity is independent of the particle size. Adsorbed water reduces the capacity of the media for the target gases due to a reduction in the number of available adsorptive sites. Therefore, adsorption occurs more readily at lower temperatures and humidity. The reverse is true for higher temperatures and humidity. Also, at higher temperatures, the rate of gas desorption increases. The adsorptive capacity of media is also a function of the contaminant concentration. It is directly proportional inasmuch as the higher the contaminant concentration, the more that will be adsorbed, up to an adsorptive capacity of the media. This is due to the increased pressure of the gas forcing adsorption to occur deeper in the media. Because of the relatively weak forces holding the adsorbed gases on the adsorbent, adsorption is (essentially) totally reversible. Thus, the net rate of adsorption depends on the rate at which gas molecules reach the surface of the adsorbent, the percent of those making contact that are adsorbed, and the rate of desorption. However, many other factors can affect the removal of gaseous contaminants by physical adsorption. Among these are the type of adsorbent, the resistance to airflow, the adsorbent bed depth, the air velocity through the bed, the characteristics of the contaminant(s) in the space around the adsorbent, and the removal efficiency required. 41.5.2 Chemisorption Adsorbent materials do not adsorb all contaminant gases equally. For instance, higher molecular weight (>80) gases and nonpolar gases may be preferentially adsorbed over lower molecular weight gases and polar gases when present in the same airstream. Also, if these lower-weight/nonpolar gases were initially adsorbed, they may be desorbed by the introduction of a higherweight/polar molecule. If the sorbent bed is of sufficient depth, these displaced molecules may again be adsorbed. However, at some point, they would be released back into the airstream. One way to improve the effectiveness of sorbents for these materials is by the use of various chemical additives (impregnants) that will react with these “less-adsorbable” gases. These impregnates react (essentially) instantaneously and irreversibly with these gases forming stable chemical compounds that are bound to the media as organic or inorganic salts or released into the air as carbon dioxide, water vapor, or some material more readily adsorbed by other adsorbents. Therefore, it is very common to have a gas-phase air filtration system that uses a combination of unimpregnated and chemically impregnated adsorbent media. In contrast to the reversible process of physical adsorption, chemical adsorption or chemisorption is the result of chemical reactions on the surface of the adsorbent. Chemisorption is specific and depends on the chemical nature of both the adsorbent medium and the contaminants to be controlled. Some oxidation reactions have been shown to occur spontaneously on the surface of the adsorbent. However, a chemical impregnant is usually added to the adsorbent, which makes it more or less specific for a contaminant or group of contaminants, for example, activated carbon impregnated with potassium hydroxide (KOH) for the removal of acid gases such as chlorine, hydrogen fluoride, and sulfur dioxide. Although some selectivity is apparent in physical adsorption, it can usually be traced to purely physical, rather than chemical, properties. In chemisorption, stronger molecular (valence) forces are involved. Many of the same factors that affect the removal of gases by physical adsorption also affect their removal by chemisorption. The chemical reactions that occur during chemisorption are favored, to an extent, by higher temperatures and humidity. Higher temperatures increase the rates of reaction and the extra water enhances the ability of the adsorbed gases to contact the chemical impregnant. Gases that are adsorbed but not chemically reacted are subject to the same effects of temperature and humidity as for plain activated carbon, and as with plain carbon, desorption of these gases is also possible.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.7

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.7

Chemisorption may be employed whenever physical adsorption by itself is inadequate or ineffective against a particular contaminant or group of contaminants. Desorption of target contaminants, once adsorbed and chemically reacted, does not occur.

41.6 DRY-SCRUBBING AIR FILTRATION MEDIA 41.6.1 Adsorbents/Chemisorbents Practically all commonly available chemical filtration media today are manufactured from (granular) activated carbons and/or aluminas; however, they do not remove all contaminant gases equally. Specific chemical additives, or impregnants, added during the manufacturing process impart special characteristics to the media and make them more or less specific for various chemical species. Many different chemicals are being used on activated carbon for general and specific applications. However, one of the more broad-spectrum chemical impregnants in common use, potassium permanganate (KMnO4), cannot be effectively used with activated carbon and, therefore, is almost exclusively used as an impregnant on activated alumina (see Table 41.3). These impregnants react essentially instantaneously to form stable chemical compounds that are irreversibly bound to the media as inorganic or organic salts or released into the air as CO2 and/or water vapor. The optimum manufacturing technique for impregnated media is via a dry feed process in which the chemical-impregnant solution is added to the powdered adsorbent material(s) in such a way as to assure a uniform distribution throughout in the finished product. The medium is then cured to have sufficient hardness to prevent particle attrition in handling and use, but still maintain a well-developed pore structure to allow gas molecules to be physically adsorbed and/or chemically reacted. These media are available in number of particle sizes and size distributions that can be well controlled in order to maintain product uniformity and predictability in use. Potassium permanganate-impregnated alumina (PPIA) is often used in conjunction with plain or impregnated GAC to provide a very broad-spectrum gas-phase air filtration system. It is fairly common to have a chemical filtration system that uses a combination of unimpregnated and impregnated adsorbent media to provide removal of a wide range of AMC. However, this multimedia approach continues to be the exception rather than the rule, as many manufacturers prefer to focus their AMC control efforts on the control of a specific contaminant or contaminant type. 41.6.2 Adsorbent-Loaded Nonwovens One of the main compromises in using sorption (adsorption or chemisorption) for the control of chemical contaminants is between the objectives of efficient contaminant control and minimizing the resistance to airflow. In a gas-phase filtration system, the contaminant gases must first come in contact with the media before they can be adsorbed. By maximizing the contact efficiency of the system, one can virtually be assured that the maximum removal efficiency of the system is realized. TABLE 41.3

Common Types of Impregnated Chemical Filter Media Media composition

Target gases (typical)

Activated carbon + activated alumina with potassium hydroxide (KOH) Activated carbon with phosphoric acid (H3PO4) or citric acid (C6H8O7) Activated alumina with potassium permanganate (KMnO4) Activated alumina with sodium thiosulfate (Na2S2O3)

Chlorine, hydrogen chloride, hydrogen fluoride, sulfur dioxide, hydrogen sulfide, boron trifluoride Ammonia, NMP, amines Sulfur dioxide, arsine, hydrogen sulfide, nitrogen oxides, low molecular weight organics Chlorine, chlorine dioxide

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.8

AIRBORNE MOLECULAR CONTAMINATION FAB YIELD, OPERATIONS, AND FACILITIES

However, it must be understood that maximizing the contact efficiency does not necessarily mean 100 percent contaminant removal efficiency. All it means is that the system has the opportunity to operate at its own particular maximum removal efficiency. The smaller the media particles are, the quicker the contaminants from the airstream can reach the interior adsorption/chemical reaction sites and the smaller the concentration gradient that is needed to produce high removal efficiencies. Thus, the most efficient form for these media would be as a powder. However, one cannot economically blow air through a packed bed of powder. A patented manufacturing technology has been developed for a chemical filter medium that allows for the application of multiple plain and chemically active sorbents to a nonwoven bicomponent fiber matrix. The resulting product is a robust, pleatable roll good with many advantages over existing alternatives. The main benefits of this adsorbent-loaded nonwoven product are the ability to use smaller medium particles and the maximization of the available surface area. These features combine to give higher initial and average contaminant removal efficiencies and lower pressure drops than competitive technologies.6 Figure 41.2 shows the difference in performance for a 25 mm (1 in) deep bed of a standard size (4 × 8 mesh) activated carbon and the smaller sized carbon (20 × 50 mesh) used in this type of product. When tested against a constant gas challenge, the smaller medium had adsorbed almost 15 times more than the regular-sized medium. However, the pressure drop through this medium bed was 81/2 times higher. Putting the smaller medium into the nonwoven fiber matrix and pleating it to a 25-mm depth reduced the pressure drop below that of the standard carbon and showed a breakthrough capacity that was roughly equal. Another important feature of this product is that it can also be produced with an integral particulate filter that practically eliminates retrofit costs. Particulate removal ratings of 90 to 95 percent ASHRAE (MERV 15-16) are possible and allow for the use of existing filter hardware. The result is a unique and effective combination filter medium that can be pleated into essentially any standard filter size for the removal of both gaseous and particulate contaminants. It provides for flexible filter design, allowing easy application into new or existing HVAC systems. The main trade-off when using this type of filter is a shorter service life due to the reduced amount of adsorbent media contained in the filter, typically 1/3 to 1/10 the amount contained in a comparable-sized granular media system.

100 90

∆P 38 Pa

80 70 % breakthrough

41.8

60

∆P 75 Pa

50 40 ∆P 640 Pa

30 20 10 0 0

50

100

150

200

250

300

350

400

450

Amount adsorbed, mg/g of carbon 4 × 8 Mesh (3−4 mm) carbon

20 × 50 Mesh (0.3−0.9 mm) carbon

20 × 50 Mesh, pleated nonwoven

FIGURE 41.2 Performance comparison for two different media particle sizes and an adsorbentloaded nonwoven media. (All filters tested were 25 mm [1 in] in depth.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.9

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.9

A variation on this filter type takes beaded activated carbon or other adsorbent particles smaller than the 20 × 50 mesh particles described previously and puts them into a carbonized foam matrix. This produces a product that can be supplied as a flat sheet with thicknesses of up to 50 mm (2 in) that can be cut to specific sizes and shapes. Sheets with different adsorbent granules can be layered into a filter frame to provide performance against multiple contaminants. This media has a very low pressure drop and relatively high removal efficiency. Media loadings are comparable to the above; however, filter capacities are appreciably lower than comparable-sized bulk media filters. A major concern about these products is the media particle shedding that occurs. Cut edges especially are prone to shedding and most of these products are supplied with a nonwoven scrim that covers both sides of the media in a finished filter or totally encapsulates the sheet of media. Costs are significantly higher than the adsorbent-loaded nonwovens. 41.6.3 Bonded Media Panels Manufacturers have developed processes whereby activated carbon or other granular adsorbents are bonded and formed into monolithic panels using a polymeric binder or sintering processes. The panels are framed in an aluminized, stainless steel, or other specified (metal) frame with edge gasketing commonly provided. The panels can be made to specific sizes and shapes for retrofit or custom applications. The main appeal of this filter type is that the media panels are self-supporting and there are no loose particles or dust coming from the media. However, despite manufacturers’ claims about “zero dust” almost all panels as supplied are covered on both sides with a nonwoven polyester particulate filter media to prevent adsorbent granules from chipping or flaking off during shipping, handling, and installation. These panels are quite fragile, which makes them prone to damage during shipping and installation. Manufacturers report that this filter type retains a high level of open pore structure and no postactivation of the carbon is required after the bonding process. However, the reality is that most of these bonding processes often suffer from one or more serious drawbacks; the main one being the loss of a significant portion of adsorptive capacity due to the binder blocking a large percentage of the external and/or internal surface area of the media particle. Other problems include a less than optimum pore size distribution, lower removal efficiencies, reaction with chemical impregnants (when present), high pressure drops, and high manufacturing costs. Test results comparing loose granular media to three commercially available bonded media panels illustrate these deficiencies (Fig. 41.3).

100 90

% breakthrough

80 70 60 50 40 30 20 10 0 0

50

100

150

200

250

300

350

400

Amount adsorbed, mg/g of carbon Bulk granular carbon Bonded carbon B

FIGURE 41.3

Bonded carbon A Bonded carbon C

Comparison of bulk carbon versus bonded carbon panels.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.10

AIRBORNE MOLECULAR CONTAMINATION 41.10

FAB YIELD, OPERATIONS, AND FACILITIES

The bulk media was filled into a 1-in (25-mm) tray. All media were plain activated carbons and the performance of each was measured against toluene as the challenge gas. 41.6.4 Ion Exchangers Ion exchangers refer to any of a wide variety of synthetic polymers containing positively or negatively charged sites that can interact with or bind to an ion of opposite charge from a surrounding solution. Most frequently used in liquid filtration applications, ion exchange products are finding a niche as an ammonia filter for lithography tools and as a specialty filter for use in other specific AMC control applications. Ion exchange filters can be extremely effective in removing AMC at and to parts per billion (ppb) and even parts per trillion (ppt) levels. They have shown high removal efficiencies at extremely low AMC concentrations. Common ion exchange media frequently found in the fab are in the form of pleated membranes or sponge-like flat sheets. Ion exchangers are also available in granular or powdered forms. A polymerbased medium known as a “cation” filter resin has a special chemistry giving it a strong affinity for basic contaminants (primarily ammonia and some amines). However, many gas-phase contaminants are not amines, but are organic or acidic in nature. As a result, there are many contaminants that would not be effectively removed by a cation ion-exchange media. It would require an “anion” exchange filter to eliminate acid gases such as HCl, HF, SO2, HNO3, H3PO4, acidic organic compounds, and some boron compounds. Neither type of ion exchanger would be very effective against organic compounds. Ion exchange filters may be very good at a single targeted contaminant (such as ammonia), but they do not offer broad-spectrum AMC control. A better solution would be to employ carbon or alumina-based adsorbent filters that can offer a broader spectrum of control. Given the oftentimes unknown and variable nature of chemical contamination in the fab, broad-spectrum filters are better suited to address chemical contamination caused by external or internal sources. A single chemisorptive filter can accomplish both the physically and chemically adsorptive processes that are required to protect manufacturing processes and material from AMC.7 Ion exchange reactions are reversible reactions with equilibrium conditions being different for different ions. This reversibility is one of the concerns about the wide use of ion exchangers in the fab. For example, the exposure of a cation filter resin to acid gases creates the potential for release of materials back into the airstream. This, along with being too specific and costing significantly more than other more common AMC filters, are the main reasons why ion exchangers are limited almost exclusively for use as ammonia/base filters in lithography applications.

41.7 CHEMICAL FILTRATION EQUIPMENT DESIGNS 41.7.1 Chemical Filters Chemical filters used in AMC control applications are available in a wide variety of commercial designs, usually as packed-bed media filters where a dry, granular media is filled in the space between perforated metal or plastic screens. Others incorporate pleated filters and media panels of the types described in Sec. 41.6. The filter types most commonly used in cleanroom HVAC systems include: • Serpentine: These contain thin-bed (0.375- to 0.5-in [9.4- to 13-mm]) convoluted filters and are used in medium-duty recirculation applications. • Thin-bed trays/panels: These contain multiple filter trays or panels of thin depth (0.5 to 1.5 in [13 to 38 mm]) arranged in a “Z” configuration in a frame to achieve an extended surface area. Granular media, adsorbent-loaded nonwovens, beaded activated carbon, and bonded carbon panels are all employed in this type of filter. • Intermediate bed-depth trays: These are similar to thin-bed trays except bed depth is on the order of 0.875 to 1 in (23 to 25 mm). They are designed for higher efficiency and longer service. • Intermediate bed depth V module: Filters are in a “V” configuration, with a bed depth of 1 to 1.125 in (25 to 28 mm) and attain a low bed velocity by using extended surface area techniques. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.11

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.11

• Pleated media filters: These are single filters employing a pleatable chemical media in depths of 2 to 12 in (50 to 300 mm). These are designed for use with adsorbent-loaded nonwoven or pleatable ion exchange media. • Thick-bed trays: These are single filters with a bed depth of 2 in (50 mm) or greater, oriented perpendicular to the airstream. They have a high pressure drop and are used with low air velocities. • Thick bed depth “V” module: This unit has an average bed depth of 3 in (75 mm) and is similar to the intermediate depth “V” module. The above filters can be installed in front, rear or side-access housings or frames, or other standardized equipment. They can also be installed in some self-contained air cleaner units. 41.7.2 Chemical Filtration Equipment Manufacturers of chemical filtration systems offer many combinations of filters and equipment to handle distinct AMC control applications. Equipment is grouped into two main classifications, HVAC-integrable systems and self-contained systems. HVAC-Integrable Systems. These are the most commonly applied chemical filter systems and are most often supplied in the form of front or rear-access systems designed to be easily integrated and adapted into a fab’s existing air handling systems. These systems are effective for treating low-tomedium concentrations of AMC in both makeup and recirculation air handling systems. These systems are usually installed as built-up banks of 24 in × 24 in (600 × 600 mm) or 12 in × 24 in (300 × 600 mm) frames which can be stacked in virtually any size configuration to meet the specific space requirements of most systems (Fig. 41.4). Frames stacked on top or to the side of each other are fastened with rivets or bolts, or spot-welded. Frames are typically constructed of 16 to 20 gauge steel, aluminum, or stainless steel with or without special coatings are required for specific applications. The chemical filtration media are contained in ether refillable or disposable filter panels or modules. This modular approach offers a wide combination of media bed depths, media types, and particulate filtration. Frames can be used for either front (upstream) or rear (downstream) access applications and can be designed to hold virtually all types of chemical filters. Multiple stages of filters can be held in

FIGURE 41.4

Front/rear access frames.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.12

AIRBORNE MOLECULAR CONTAMINATION 41.12

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 41.5

Emergency gas scrubbers (L, single-stage; R, multi-stage).

a single frame depending on the fastening device chosen. Each frame is typically supplied with a gasket around the inside flange return to provide a positive seal between the filter and the frame. Self-Contained Equipment. The primary use of self-contained AMC control systems in semiconductor facilities is for the removal of hazardous production gases from process tool and gas cabinet exhausts, as well as providing “safe havens” for personnel in the event of a catastrophic release of a toxic material from process tools, gas cylinders, gas cabinets, storage tanks, and so forth. For waste gas treatment, these systems should be installed as close as possible to the tool outlet or gas cabinet . Exhaust streams from multiple tools or gas cabinets may be combined as long as the total combined gas challenge is not greater than the capacity of the system. Concentrations of hazardous gases are reduced well below threshold limit values (TLVs) when using the appropriate chemical filter media. Emergency gas scrubbers (EGS, Fig. 41.5) have become necessary components of the health and safety plans for many facilities due to the use and storage of large quantities of toxic chemicals, including arsine (AsH3), phosphine (PH3), hydrogen fluoride (HF), chlorine (Cl2), and boron trichloride (BF3). An accidental chemical release, even from a cylinder as small as one pound, can be fatal. As a result, manufacturers must take emergency precautions to protect personnel and the surrounding communities. EGSs are designed for the complete removal of accidentally released gases and with removal capacities for gas cylinders of 1 lb to 1 ton and greater in size. EGSs can be designed with a single media bed for a single contaminant challenge or with multiple deep media beds to allow for the use of multiple chemical media, each targeting a specific contaminant or group of contaminants.

41.8 AMC MONITORING Just as there are many ways to apply chemical filtration for the control of AMC, there are many different methods being used to measure AMC inside and outside the cleanroom environment and to evaluate the filter-system performance. Once an AMC control strategy has been decided upon and implemented, whether it involves the use of chemical filtration or not, one must be able to monitor the success or failure of meeting specified AMC control criteria. As a minimum any AMC monitoring program must provide the following: • • • •

Type(s) of contaminants present and their relative levels Ambient air quality correlated to specific air purity classifications Chemical filtration system performance assessment Verification of the attainment of specified or standard AMC levels

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.13

AIRBORNE MOLECULAR CONTAMINATION 41.13

AIRBORNE MOLECULAR CONTAMINATION

TABLE 41.4

Selection Matrix of Sampling Instruments and Analysis Methods in Relation to Expected AMC Concentrations

Detection Limits

(10n g/m3) ACID

Chemical category

Note:

0

−1

−2

−3

IPM, IC, UVS, RM

−4

−5

−6

−7

IMP, IC, IMP, DIFF, UVS, CLS IC, UVS, IR, CPR IR, CLS, CPR

BASE

−8

−9

−10

−11 −12

IMP, DIFF, IMP, DIFF, IC, CLS IC, CZE, CLS

IMP, CZE

IMP, DIFF, IC, IMS, CLS

IMP, IC, CZE

ORGANIC

SOR, SB, GC-FID, GC-MS, IR

SOR, WW, GC-FID, GC-MS

INORGANIC

IMP, AA, AA-F, AA-CF, UVS, ICP-MS, CL, CLS, IR, ECS

IMP, WW, ICP-MS, CLSi

ICPMS

The applicable analysis method for a given contaminant concentration is dependent on the sampling rate and duration.8

The biggest problem today is not whether specified levels of chemical contaminants can be reached, but whether they can be accurately measured to assure compliance with any standards or control criteria. There is a wide range of real-time (active) monitoring instrumentation available with many claiming detection limits in low ppb range and some claiming ppt levels. There is an increased interest in portable systems as opposed to those that are installed facilitywide and accessed through the facility-monitoring system. Instrument manufacturers should be able to provide an understanding of the different technologies available, what to look for, and what would be most appropriate for a particular application. Table 41.4 provides an idea of the monitoring technologies available and the types of levels of different classes of chemical contaminants that can be measured. It is not meant to be inclusive, but rather to illustrate the point that one monitoring technique will most likely not provide information on all of the contaminants of concern. These instruments and analytical techniques can provide real-time data on AMC levels, but have a significantly higher cost when compared to other monitoring techniques. Because of this, a number of manufacturers now perform AMC monitoring using what may be referred to as “semiquantitative” monitoring.3 These are analytical techniques that provide quantitative information on environmental air quality, but do not measure specific contaminants. They can involve passive or real-time monitoring using devices such as litmus paper, witness wafers, impingers, multisorbent tubes, surface contamination monitors, and reactivity monitors. 41.8.1 Reactivity Monitoring Of the semiquantitative monitoring techniques in wide use, the one that has seen the largest increase in use is reactivity (or corrosion) monitoring.9 This is a low(er)-cost monitoring technique that has proven especially useful for establishing AMC baselines and identifying AMC episodes and their sources. It can help reduce the number of reported health and safety incidents by allowing proactive investigation of potential problems. When incorporated into a facility’s preventive maintenance program, it can reduce the number of AMC-related incidents that are reported with the ultimate goal being to eliminate production downtime due to AMC in the fab. Employed in either real-time or passive form, reactivity monitoring is being used as a method of gauging AMC levels and to evaluate the effectiveness of AMC control strategies. Whether controlling AMC directly or indirectly, reactivity monitoring can provide an overall indication of the ambient air quality as well as AMC levels within the controlled spaces. Where chemical filtration is employed for AMC control, reactivity monitoring can provide information on filter performance in both quantitative and relative terms. One can directly quantify the reduction through a chemical

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.14

AIRBORNE MOLECULAR CONTAMINATION 41.14

FAB YIELD, OPERATIONS, AND FACILITIES

FIGURE 41.6 Picture of metal-plated quartz crystal microbalances (QCMs on left) used in environmental reactivity monitors (ERMs) and environmental reactivity coupons (ERCs on right) after exposure to corrosive gases.

filter system for a number of contaminant species with this technique. It can also provide evidence as to the types of contaminants present and a system’s effectiveness against these contaminants.10 Reactivity monitoring (Fig. 41.6) is commonly used for evaluating long-term air quality trends inside and outside a facility and in performing environmental surveys as part of the development of an AMC control program. It can also be used to differentiate between classes of chemical contaminants and to provide estimates of the airborne AMC concentrations. The presence of low levels of chlorine and sulfur compounds and many other corrosive and problematic AMC including sulfur dioxide, nitrogen dioxide, hydrogen sulfide, hydrogen fluoride, ammonia, and ozone (all of which have been cited as the cause of a number of AMC-related process effects) can be detected using this technique (Table 41.5). An air quality classification scheme has been established for use with reactivity monitoring and it has gained wide acceptance throughout the semiconductor industry. Reactivity monitoring can provide information as to the types and relative concentrations of many contaminants problematic to manufacturing processes. It can provide the information required to determine if direct AMC control is indicated and, if so, what form it should take.

TABLE 41.5

Reactivity Monitoring Sensitivities for Various AMC Types

Chemical class

Chemical types

Detection limits

Inorganic chlorine compounds Halogen acids Strong oxidants Active sulfur compounds Sulfur oxides Nitrogen oxides Ammonia and derivatives

Cl2, HCl F2, HF, HBr, HI O3, ClO2, HNO3 H2S, mercaptans, elemental sulfur SO2, SO3 (sulfuric acids) NO, NO2, N2O4 NH3, NMP, amines

<1 ppb <1 ppb <2 ppb <3 ppb <10 ppb <50 ppb 200–500 ppb

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.15

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.15

Whatever techniques and instrumentation are employed to detect and monitor AMC, there are a number of important characteristics to consider: Sensitivity: A detection limit of 1 ppb/µg/m3 is required for a majority of contaminants. Accuracy: How close to the actual concentration? Repeatability: Will you get the same answer every time for a given set of conditions? Selectivity: Could there be interference from other compounds? Identification: What specific contaminants are present? Ease of use: Calibration required, prep time, complexity, and so forth. Response time: Real-time (active) versus passive. Size/weight: Lab-scale, portable, hand-held. Cost of ownership: Includes consumables, operator time, maintenance, and calibration.

41.9 AMC CONTROL APPLICATION AREAS 41.9.1 HVAC System Designs Most air handlers employed in semiconductor cleanrooms are large custom units moving tremendous quantities of air used for both pressurization and recirculation. A typical cleanroom HVAC system might consist of makeup air handlers for pressurization air, recirculating air handling units, or, fan filter units to move the supply air to the cleanroom, ducts to route the air, plenums to distribute the air, and filtration systems to clean the air before it is introduced to the cleanroom. Whichever type of air handling system is employed in a semiconductor fab, there are a number of locations in which chemical filtration can be applied. Ultimately, the nature of the contaminants, their source(s), and the cleanroom layout and design, all have to be considered for determining the best location for these filters and equipment. Makeup (Outside) Air. One of the main applications of chemical filtration is to treat the air brought into the facility for ventilation and pressurization. This air oftentimes contains chemical contaminants of the types and quantities to be of concern to semiconductor manufacturing processes. Ozone, oxides of sulfur and nitrogen, and VOCs are the most common chemical contaminants encountered in outside air. Also, depending on the geographic location of the facility (e.g., seaside, northern climates) and the activities being performed in the surrounding areas (industry, farming, and so forth) significant sources of other contaminants such as boron, ammonia, chlorine, and hydrogen sulfide, may also be present. Makeup air handlers (MAUs) are a combination of air handlers and air treatment systems. These units contain the components necessary to prepare outside air for use in a cleanroom environment. Heating and cooling coils, humidification distribution systems, fans, filters, electrical systems, and controls can all be contained in these units. Outside air is typically delivered at the rate of ~2 to 6 cfm/ft2 for pressurization of the cleanroom floor space. In a “typical” 100,000-ft2 ballroom-type semiconductor fab, this would require between 200K and 600K cfm of air. Because of these large amounts of outside air required and the corresponding large size of most MAUs, chemical filters are employed in built-up banks of front (or rear) access frames for ease of access and maintenance. Single banks of bulk media filters can be used, but it is common to see two or more banks employing different chemical filter media based on the types and levels of the contaminants expected. Recirculation Air. Because of the tremendous quantities of air required to maintain a semiconductor cleanroom, most of the air within the space is recirculated to keep the amount of energy used by the HVAC to condition the outside air to a minimum. The MAUs deliver clean, pressurization air Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.16

AIRBORNE MOLECULAR CONTAMINATION 41.16

FAB YIELD, OPERATIONS, AND FACILITIES

to the clean space either through ductwork or through a pressurized plenum. Perforated floor panels allow the air to flow into a large common plenum from which air is to be treated through recirculating air units (RAUs). These air handlers deliver air at a rate of 72 to 90 cfm/ft2 of clean space. RAUs employing chemical filtration are thus used to treat or “polish” the air to and from the clean space as well as remove AMC from specific sources within the fab. Sources of AMC within the cleanroom include process chemicals and raw materials, process tools, spills, and so forth. Because RAUs are many times comparable in size to the MAUs, the use of front (or rear) access frames is usually indicated. However, some fab designs employ the use of numerous smaller RAUs to compartmentalize and isolate airflows in order to prevent possible cross contamination. This smaller size could allow for the use of side-access housings integrated into the air handlers. Fan Filter Units/Minienvironments. Fan filter units (FFUs) combine a fan and motor with a prefilter and a HEPA/ ULPA filter and can be installed directly into a ceiling system. They can replace RAUs and can be used to achieve 100 percent coverage of the cleanroom, eliminate ductwork by drawing air from the interstitial area above the cleanroom, and reduce the outside air requirements by eliminating the pressure plenum. Chemical filters are employed in FFUs to provide additional levels of AMC control to sensitive process areas. Minienvironments are enclosures with engineered airflows that surround process tools. They are used to maintain cleanliness levels at the wafer environment that is independent of the external room environment. Steppers and reticle stockers are common examples of the use of minienvironments. Chemical filters can be integrated into the process tool supply air for final cleaning of the air or into the exhaust duct to prevent fugitive emissions from being distributed throughout the facility. 41.9.2 AMC Application Areas Table 41.6 provides a design summary for these applications and shows the common target contaminants along with the recommended chemical filtration media, filters, and equipment. Figure 41.7 shows a schematic of a cleanroom with the most common locations for AMC control within the HVAC system and within the cleanroom itself. In addition to MAUs and RAUs, chemical filtration is applied to clean up the air to process tools. Tool exhaust air has been implicated as one of the major sources of fugitive chemical emission with the semiconductor cleanroom.

TABLE 41.6

AMC Control System Design Summary Filter fan unit (FFU), minienvironments, point-of-use filters

Emergency gas scrubbers, exhaust air

NH3, NMP, amines, acids, alcohols, VOCs, AsH3, BF3

NH3, NMP, amines, Cl2, HCl, HF, VOCs

AsH3, PH3, BF3, Cl2, HCl, HF, ClF3, VOCs

GAC, impregnated carbons/alumina

GAC, impregnated carbon/alumina, adsorbent-loaded nonwovens

Adsorbent-loaded nonwovens, ion exchange, beaded activated carbon

Specially impregnated carbon/alumina

Filters

Thick/thin bed trays/ modules

Thin bed trays/ modules, pleated media filters, flat panel filters

Pleated media filters, flat panel trays

Bulk media

Equipment

Front/rear access cells, 2–3 passes

Front/rear access cells, 1–2 passes

Side access systems, integrated recirculation air filters, OEM filter housings

Deep-bed scrubbers, emergency gas scrubbers

Application areas

Outside air

Recirculation air

Target contaminants

SOX, NOX, O3, Cl2, NH3, VOCs

Media

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.17

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.17

HEPA filter ASHRAE filter Chemical filter Prefilter Chemical filter

ULPA

B-ULPA

Blank panel

OA

FFU

Chemical free area

AHU for OA

Boron-free area FFU

FFU

Machine

Chemical filter Wafer stock box

FFU FFU

Chemical filter

FFU

ASHRAE filter

NH3-free area

Chemical filter Chemical filter

Eximer stepper

Machine

Maintenance area AHU for recirculation air

FIGURE 41.7

Possible locations for AMC control in a semiconductor manufacturing facility.

Because of this growing numbers of process tool manufacturers provide gas-phase filtration as an integral part of their equipment design.

41.10 AMC CONTROL SPECIFICATIONS AND STANDARDS AMC control specifications are often based upon individual chemical species or groups of chemical contaminants (bases, chlorides, VOCs). This is not surprising as many of these were developed from an “industry-wide” perspective. Individual semiconductor manufacturers, due to intellectual property issues and competitive pressures, tend to use their own contamination control criteria that have been developed through their own experience, capabilities, and expectations. There is no general consensus on what may be considered acceptable levels of airborne chemical contamination, but the ranges have been narrowing over the last several years and this trend is expected to continue over the next several years (Table 41.7). 41.10.1 SEMI Standards SEMI Standard F-21-1102 titled “Classification of Airborne Molecular Contaminant Levels in Clean Environments,” classifies microelectronic clean environments with respect to their AMC levels.4 These standard classifications are used in the specification of semiconductor clean environments (including

TABLE 41.7 Projected Chemical Contaminant Design Criteria for Current and Future Device Geometries11 Semiconductor design geometry Contaminant class

0.25 µm

0.18 µm

0.13 µm

0.10 µm

VOC (µg/m3) Ionics (µg/m3) Total hydrocarbons (ppb) Metals (ppt)

30 1 10 0.1

10 0.3 3 0.03

3 0.1 1 0.01

1 0.03 0.3 0

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.18

AIRBORNE MOLECULAR CONTAMINATION 41.18

FAB YIELD, OPERATIONS, AND FACILITIES

TABLE 41.8

Technology Requirements for Wafer Environmental Contamination Control—AMC (pptM)

Year of first product shipment technology generation

2003 100 nm

2004 90 nm

2005 80 nm

2006 70 nm

2007 65 nm

2008 57 nm

2009 50 nm

Lithography-bases (as amine) Gate formation-metals Gate formation-organics Salicidation/contact formation-acids/bases

750 0.15 80 10/12

750 0.1 70 10/10

750 0.1 60 10/8

<750 0.07 60 <10/<4

<750 <0.07 50 <10/<4

<750 <0.07 50 <10/<4

<750 <0.07 50 <10/<4

process tool environments) and of contamination control and measurement equipment performance. This standard determines environmental classifications by the maximum allowable gas-phase concentration of four specific contaminant categories—acids, bases, condensables, and dopants. The combination of a quantitative class for each of the four categories yields a classification describing the environment. SEMI Standard F21 does provide a consistent means of communicating acceptable levels for groups of specific contaminants. In practice, however, it is rarely used in the specification of clean environments and contamination control and measurement equipment performance. This is primarily due to the lack of standard AMC classifications for semiconductor manufacturing environments and monitoring requirements in the standard. There is a need for better AMC monitoring instrumentation in the cleanroom to measure AMC at the ppt levels. 41.10.2 International Technology Roadmap for Semiconductors According to SEMATECH’s International Technology Roadmap for Semiconductors (ITRS),12 the percentage of process steps affected by nonparticulate or molecular contamination is expected to increase. The impact of AMC on wafer processing can only be expected to become more deleterious as device dimensions decrease. Pregate oxidation, salicidation, contact formation, and DUV photolithography have been identified as particularly sensitive production steps. The Yield Enhancement section of the ITRS, and specifically the wafer environment contamination control (WECC) technology requirements, indicate target levels of ambient acids, bases, condensables, dopants, and metals for specific process steps (Table 41.8). 41.10.3 ISO Standard 14644-8 ISO 14644-8 covers the classification of molecular contamination in cleanrooms and associated controlled environments in terms of airborne concentrations of the specific compound or chemical and provides a protocol to include test methods, analysis, and time weighted factors within the specification for classification. It considers only concentrations of airborne molecular contamination between 100 and 10−12 g/m3 under normal cleanroom conditions of temperature, relative humidity, and pressure, and is not relevant for application in those industries, processes, or production, where the presence of AMC is not considered a risk to the product or process. This standard cannot be used to characterize the nature of airborne molecular contaminants nor does it provide a classification of surface molecular contamination. Most importantly, it will not set standard AMC levels or make recommendations for air cleanliness classes for specific operations.

41.11 SPECIFYING AN AMC CONTROL SYSTEM As manufacturers have become much more sophisticated in their knowledge and understanding of AMC and its effects in the cleanroom., they have also developed a better general understanding of where AMC control should be applied and why. As their knowledge of AMC-related problems have increased, so too have their expectations for an AMC control system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.19

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.19

Some manufacturers’ concerns about the proper selection of an AMC control system have become so acute that it is being reflected in their control specifications. One manufacturer may call for a minimum of 90 percent removal of target contaminants, while another will set AMC control limits at 1 ppb or less. Still another may require that the system must last a minimum of one year between filter changeouts. As strict as they may seem individually, there are manufacturers whose specifications require all three of the above criteria to be met. Compounding the situation, some manufacturers insist on trying to find a “one filter fits all” solution for AMC control, demanding that a single filter should meet all of their control criteria for all contaminants of concern. However, chlorine requires one type of filter, ammonia another, and organic compounds still another. The type of filters/systems used for toxic gases would not be the same for odor control. “Are you looking for high efficiency or long service life?” “Do you require absolute control of one contaminant or relative control of a group of contaminants?” These are only some of the questions that an AMC control system designer must consider, even though his customer may not understand the implications of not taking all of this into consideration. 41.11.1 Specification by Removal Efficiency The removal efficiency of an AMC control system can be considered as the fraction of a single contaminant or group of contaminants that are removed either by physical or chemical means. Many manufacturers are able to provide test data for their systems that show removal efficiency over time. However, this testing has been performed almost exclusively under accelerated conditions using high contaminant challenge concentrations that can be up to three to four orders of magnitude higher than what would be expected under actual use conditions. Although realistic extrapolations of filter efficiency can be provided, many manufacturers are now requiring low-level gas challenge testing for efficiency ratings of the filters (see Fig. 41.8).13

100% 90%

Removal efficiency

80% 70% 60% 50% 40% 30% 20% 10% 0% 0

40

80

120

160

200 240 Time, days

280

320

360

HF

HCI

NO2

Toluene

SO2

PGMEA

PGME

Ozone

400

FIGURE 41.8 Removal efficiency of a single chemical filter against a 20 ppb challenge concentration for each of eight different chemical contaminants. The filter tested was a 24 × 24 × 12 in (600 × 600 × 300 mm) box-type filter employing an adsorbent-loaded nonwoven pleated media. (All gases were tested individually.)

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.20

AIRBORNE MOLECULAR CONTAMINATION 41.20

FAB YIELD, OPERATIONS, AND FACILITIES

This is the best way to gauge filter performance, however, testing of this sort is more complicated, takes a long time to complete, and is much more expensive to perform. One of the main problems in trying to provide an efficiency rating for a particular contaminant/filter combination is that any rating has to have a time component specified along with it. If a specification calls for 90 percent minimum removal efficiency, the end user is expecting that to hold true over the entire life of the filter. Most tests, however, are only run long enough to provide an “initial” efficiency, and the test is stopped after 1 hr, 8 hr, 24 hr, and so on. All this does is provide information on how well the filter may work under a specific contaminant load, but it does not provide or predict an indication of performance beyond the stated test period. An examination of the efficiency curves can provide some additional indication of future performance; however, it still cannot guarantee performance under actual-use conditions. Further, a filter that performs well against a single contaminant, for example, ammonia, can perform poorly when gas mixtures are considered. 41.11.2 Specification by Contaminant Limits Some manufacturers have investigated specific AMC-related process problems so well that they have been able to set specific control levels for one or more contaminants. Common control specifications call for less than 1 ppb of ammonia in lithography bays or less than 1 ppb of chlorine or HF in metallization processes. Regardless of the ambient levels of ammonia, chlorine, or HF, the AMC control system is expected to keep the controlled environment at or less than 1 ppb over the service life of the system. Depending on ambient levels, this could require a minimum working filter efficiency of 50 percent, 80 percent, 95 percent, and so on. If transient high-level episodes are probable, filter efficiencies greater than 99 percent may be required to maintain a 1 ppb level coming out of the AMC control system. 41.11.3 Specification of Service Life Cost-of-ownership is always a major consideration when applying AMC control and can unfortunately be the primary factor when the final purchasing decision is made. Budget cycles, production schedules, capital expenditures, or simply a customer’s preconceived notion of how long a filter should last, can be the basis for specifying filter life. Testing to determine the working removal capacities of a certain AMC control product for a specific contaminant follows the same basic protocol as for efficiency testing. Using a known contaminant concentration at a specified airflow (typically the filter’s maximum rated airflow), and running to a specific efficiency endpoint, one can calculate the amount of contaminant that has been removed. The media’s removal capacity is reported as a volumetric capacity (g/cc) or as a weight percent. This can then be used to estimate media consumption rates under a given set of conditions and provide an estimate of service life for a specific filter type. Capacities have to be determined for each contaminant of concern in order to provide a total consumption rate for a particular application. This is not practical, however, due to the uncertainty of the total contaminant load, the nature of the contaminants in question, and any associated safety concerns as well as the time and costs involved. Further, the effects other contaminants in the cleanroom may have on the AMC control system have to be accounted for. Using observed removal capacities are useful in providing estimates of service life, and if a conservative approach is taken, these estimates can be valid tools for the determination of filter service life (see Table 41.9).14 Ultimately, filter changeout schedules will often come from experience. Actual-use conditions often dictate that different media types in individual AMC control systems will need to be replaced at different intervals to maintain optimum performance. This is not the answer that manufacturers want to hear because they want to be able to set maintenance schedules and budgets. However, the reality is that one cannot predict, much less guarantee, filter service life from testing on one or two target contaminants while not knowing the total contaminant load the system will actually see. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.21

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

TABLE 41.9

41.21

Breakthrough Capacity Test Results for Chemical Filter Media Removal efficiency

Contaminant gas

Recommended media

Initial, percent

Acetic acid Ammonia Arsine Chlorine Ethylene Formaldehyde Hydrogen chloride Hydrogen fluoride Isopropyl alcohol Methyl amine Methyl ethyl ketone n-Methyl pyrrolidone Nitrogen dioxide Ozone PGME PGMEA Phosphine Sulfur dioxide Toluene

Purafil Select† Purakol AM‡ Purafil Select Puracarb§ Purafil Select Purafil Select Puracarb Puracarb Purakol¶ + Purafil Select Purakol AM Purakol Purafil Select Puracarb Purakol Purakol Purakol Purafil Select Puracarb Purakol

94 99 37 84 100 73 100 100 66 98 78 99 91 91 80 88 60 100 85

Average, percent 64 50 8 57 94 27 94 95 25 34 36 85 70 67 49 55 14 86 57

Capacity removal, percent

Service life estimate, hours*

15.6 10.9 0.4 11.4 2.6 2.8 12.4 6.9 14.8 1.6 13.8 32.4 9.2 4.5 7.9 14.8 0.3 7.7 10.2

1,641 10,197 106 2,231 790 779 2,844 2,873 7,701 1,212 4,202 3,036 2,265 1,108 1,417 1,619 542 2,201 2,542

At a 50 ppb challenge concentration using a 24 × 24 × 12 in (600 × 600 × 300 mm) adsorbent—leaded nonwoven fiber filter Activated alumina impregnated with potassium permanganate (KMnO4) ‡ Activated carbon impregnated with phosphoric acid (H3PO4) § Activated carbon + activated alumina impregnated with potassium hydroxide (KOH) ¶ Granular activated carbon * †

41.12 FINAL CONSIDERATIONS AMC control has become an essential design requirement for all new semiconductor manufacturing facilities, as well as for a large number of existing facilities. Subsequently, chemical filtration in many forms is being used in makeup and recirculation air handlers, fan filter units, minienvironments, and process tools. Given the proper attention, one can successfully specify and implement an effective and economical AMC control solution for most applications. One cannot, however, go in with preconceived notions about how a particular system will perform under a given set of conditions, rather, one should determine what they ultimately want to achieve by the installation of such a system. The following five points should always be considered in the design and specification of an AMC control system: 1. Does AMC pose an immediate health threat to cleanroom personnel or is it primarily an odor control issue? Personnel protection requires 100 percent control of the offending contaminants whereas odor control could be achieved with a system operating at an overall efficiency of 50 percent or less. Process protection requires very high performance, but that does not mean absolute control. Many specifications today call for removal efficiencies of at least 90 percent and this is realistic to expect. 2. Accept filter performance testing for what it truly is. That is, a comparison of different systems being offered for a particular application. Efficiency or capacity test data for a single contaminant cannot be used as an absolute predictor of system performance. It can, however, provide an indication of the relative performance differences between competitive systems. 3. Request performance data for contaminant concentrations at or near expected use conditions if at all possible. If the system performance and/or filter life estimates are based on accelerated test results, consider limiting gas challenge concentrations to no more than two orders of magnitude, above what would be expected under actual use conditions. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.22

AIRBORNE MOLECULAR CONTAMINATION 41.22

FAB YIELD, OPERATIONS, AND FACILITIES

4. Filter service life should not be a part of a performance specification. Filter life estimates should be required for all systems being considered, but again, these should be used as relative comparisons and not absolute values. There is no practical way to provide service life estimates without having performance data for the total contaminant load and not just a handful of target contaminants. Monitoring of filter performance using direct gas monitoring, reactivity monitoring, or by using grab samplers (e.g., impingers, adsorbent tubes, witness wafers, and coupons) should be started along with system start-up and should continue as long as the AMC control system is in place. 5. Use a multistage AMC control system. Just as particulate control in cleanrooms requires several stages of filtration to achieve the desired cleanliness level in the protected space, the same should be considered for an AMC control system. A “prefilter” stage should be used to remove as much of the “junk” AMC as possible. This would help protect and preserve the “final filter’s” ability to remove those contaminants of concern with good efficiency and capacity. If the types of contaminants targeted for control require different filters, serious consideration should be given to individual stages for each filter type. Blended media may be used, but at a trade-off in service life. A properly designed, installed and maintained AMC control system can fairly easily achieve the removal efficiencies required for specific target contaminants. How long a system will take to meet specific performance criteria depends on the average and peak values of all the contaminants present, which must be considered in the final design of the AMC control system.

41.13 SUMMARY AMC continues to grow in importance as a barrier to semiconductor manufacturers as they continue the transition toward 300 mm wafers, copper interconnects, and the 65 nm technology node. It represents a wide range of chemical types that can result in a large number of potential processing problems. However, many fabs have only recently begun to actively address AMC and the effects of specific contaminants on individual processing steps are still not very well understood. Direct correlations between process yield and individual contaminant concentrations, although one of the current “Holy Grails” of contamination control, are either rare or not published. With the rapid pace of technological advancements, semiconductor manufacturers have fully recognized the fact that sensitive electronic and electrical components and equipment will be damaged if exposed to AMC. The ITRS has proposed that AMC will be the next technical challenge to overcome in order to maintain high reliability and yield for semiconductor devices. New requirements for AMC control are being added to each new edition of the Roadmap. “Next generation” semiconductor devices will require the strict control of AMC in order to assure productivity, competitiveness, and profitability. Manufacturers are actively addressing AMC and its control, each according to the specific requirements of their own manufacturing processes and concerns. At the very least it now appears that the incorporation of chemical filtration into makeup air handlers will become a requirement for these facilities. An assessment of outdoor air quality should be one of the first steps toward establishing any AMC control program. In review of air monitoring data from semiconductor fabs around the world, there are very few areas today where the outside air quality would meet specific area quality requirements with respect to AMC. Even ambient levels of AMC are high enough to be of concern. As the industry’s knowledge about the damaging effects of AMC on processes and materials continues to increase, more facilities are implementing AMC control programs. Suppliers of specialized chemical filtration systems are being asked to assist in determining the types of AMC present, the specific control system(s) required, how best to determine if the systems are working, and if so, then whether they are meeting specific design requirements. As the necessity to control chemical contamination increases, more information and feedback from semiconductor manufacturers is going to be required for continuous improvement of AMC monitoring and control technologies. Intellectual property, new technology, and competitive considerations must be protected, but the suppliers of monitoring and control technologies must be able to address AMC issues with as much information as possible at their disposal. Only then can we be assured that we will keep pace with AMC.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.23

AIRBORNE MOLECULAR CONTAMINATION AIRBORNE MOLECULAR CONTAMINATION

41.23

REFERENCES 1. Arnold, Bill, “Future of Copper Shines Through Fog of Transition,” Semiconductor Magazine, Vol. 1(6): 32–36, 2000. 2. Muller, C., “Developments in Measurement and Control of Airborne Molecular Contaminants,” Proceedings of Semicon Taiwan 2001, Taipei, Taiwan, September 17–19, 2001. 3. Kwan, M. L., C. Muller, and R. Thomas, “Semiquantitative Analysis Techniques for AMC Monitoring,” Proceedings of SEMICON Taiwan 2004, Taipei, Taiwan, September 13–15, 2004. 4. SEMI F21-1102, Classification of Airborne Molecular Contaminant Levels in Clean Environments, Semiconductor Equipment and Materials International, Mountain View, CA, 2002. 5. Jones, W. R., J. H. Knight, and C. O. Muller, “Practical Applications of Assessment, Control, And Monitoring of AMC in Semiconductor and Disk-Drive Manufacturing,” Proceedings of ESTECH 2002, 47th Annual Technical Meeting of the Institute of Environmental Science and Technology, Anaheim, CA, April 28–May 1, 2002. 6. Middlebrooks, M. C., and C. Muller, “Application and Evaluation of a New Dry-scrubbing Chemical Filtration Media,” Proceedings of the Air & Waste Management Association 94th Annual Meeting and Exhibition, Orlando, FL, June 24–28, 2001. 7. “Advantages of Carbon in Broad-Spectrum Chemical Filtration for Lithographic Processes,” White Paper, Donaldson Company, Inc., 2001, http://www.donaldson.com/en/semiconductor/support/datalibrary/ 034062.pdf 8. ISO/DIS 14644-8, Cleanrooms and Associated Controlled Environments—Part 8: Classification of Airborne Molecular Contamination, International Organization for Standardization, Geneva, Switzerland, 2004. 9. Muller, C. O. (1999). Reactivity Monitoring: An Alternative to Gas Monitoring for Semiconductor Cleanrooms? In Proceedings of the 45th Annual Technical Meeting of the Institute of Environmental Science and Technology, Ontario, CA, May 2–7, 1999. 10. Muller, C., “Evaluating the Effectiveness of Airborne Molecular Contamination Control Strategies with Reactivity Monitoring,” Journal of the IEST, Vol.(45), Annual Edition, 2002. 11. Lockwood Greene Engineers. (1997). “Division of Excellence in Semiconductor Manufacturing: A 300 mm Forum,” Teffen, Ltd., Bechtel, & Lockwood Greene Design Team Seminar, Spartanburg, SC, November, 1997. 12. International Technology Roadmap for Semiconductors, 2003 Edition, Yield Enhancement, URL: http://public. itrs.net/Files/2003ITRS/Home2003.htm. 13. Nelson, G. O. “Purafilter Gas Challenge Test Results: 2001–2003,” Report presented to Purafil, Inc., Doraville, GA (unpublished). 14. Muller, C., “Specifically AMC: Guidelines for Specification of AMC Control,” Cleanroom Technology Magazine, pp. 28–30, April 2004.

INFORMATION RESOURCES A2C2 (Advancing Applications in Contamination Control) magazine: http://www.a2c2.com/ CleanRooms magazine: http://cr.pennnet.com/home.cfm Cleanroom Technology magazine: http://www.cleanroom-technology.co.uk/ International Confederation of Contamination Control Societies: http://www.icccs.net/ International SEMATECH Manufacturing Initiative: http://ismi.sematech.org/index.htm International Technology Roadmap for Semiconductors (ITRS) web site: http://public.itrs.net/ MICRO magazine: http://www.micromagazine.com/ SEMATECH Standards and Guidelines: http://ismi.sematech.org/standards/index.htm Semiconductor Fabtech magazine: http://www.semiconductorfabtech.com/ SEMI Standards Publications: http://wps2a.semi.org/wps/portal/_pagr/116/_pa.116/121?docName=P001204 Semiconductor International magazine: http://www.reed-electronics.com/semiconductor/ Semiconductor Manufacturing magazine: http://www.semimfg.com Solid State Technology magazine: http://sst.pennnet.com/home.cfm

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH41.qxd

04/04/2005

21:21

Page 41.24

AIRBORNE MOLECULAR CONTAMINATION

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:22

Page 42.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 42

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING Steven Kochevar Jerry Gromala Particle Measuring Systems Boulder, Colorado

42.1 INTRODUCTION Consider for a minute the possibility to design and implement a microcontamination monitoring strategy, using a blank sheet of paper. Think of how nice it would be to not have to deal with old or obsolete particle counters, making do with an insufficient number of sensors or equipment with insufficient sensitivity and sample volume, or possibly a system that requires too much manual labor to collect and analyze data. This is generally not the case for most microcontamination control professionals whose job requires them to maintain and deliver clean air, water, process chemicals, and gases to the manufacturing operation on a daily basis. Particle counters have been around for 30 years, and most semiconductor fabs have improved their monitoring capabilities over many years, sometimes a decade or more. Over the years, monitoring instrumentation gets added when the budget is available, or when serious particle upsets necessitate the purchase of new equipment. This approach has worked; otherwise, the technologies behind today’s consumer electronics, guidance systems, manufacturing equipment, and telecommunications technology would not be anywhere near their current capabilities. Of course, the list of modern technological advancements that touch our everyday life in so many ways seems to be virtually endless. Moore’s law is still alive and well, and the future looks promising for sustaining this remarkable technology trend. It does raise an intriguing question, though, regarding what would be the basis for the “ideal” microcontamination monitoring strategy, given what we know about the current International Technology Roadmap Standards (ITRS), capabilities and limitations of current manufacturing processes, and the latest technology available for particle monitoring. The obvious answer is that there is no single solution that would fit the needs of all semiconductor manufacturing firms. Guidelines have evolved that can be applied to a firm’s unique monitoring challenges when it is finally deemed necessary to modernize an antiquated monitoring plan. The first step is optimizing the existing approaches that work satisfactorily but could provide more useful information if improved. Next, adding entirely new monitoring capabilities that will satisfy the needs of today and beyond will result in a balanced and useful monitoring plan that provides valuable information for the manufacturing floor. This chapter seeks to consolidate the latest in particle monitoring strategies. The goal is to provide readers with enough information so that the right questions can be asked when making decisions for Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

42.1

Geng(SMH)_CH42.qxd

04/04/2005

21:22

Page 42.2

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.2

FAB YIELD, OPERATIONS, AND FACILITIES

creating or optimizing a particle monitoring program. The discussion begins with guidelines for creating a monitoring strategy and a description of the three fundamental monitoring models. A high-level review of the theory of operation of optical particle counters and an explanation of the factors that affect the price of the instrument are presented. The key performance specifications for a particle counter are defined and descriptions are provided for the most common particle counters used in semiconductor manufacturing today. The unique challenges associated with both aerosol and liquid particle monitoring applications are summarized, and the emerging requirements for future monitoring are identified.

42.1.1 Creating a Monitoring Strategy A well-designed particle monitoring strategy can mean the difference between a successful contamination monitoring program and one that contamination control engineers and process owners “live with” because of the capital outlay required to purchase the system in the first place. Considering the time and money that will be spent both on the initial investment and the long-term maintenance, it certainly makes sense to spend time up front to identify the success drivers and the goals and objectives of the program. Although individual circumstances may vary, experience has shown the following elements particularly important in the planning process: • Determine the scope of the monitoring program. This normally starts with identifying the media that will require monitoring. Examples include general cleanroom, minienvironments, deionized (DI) water, process chemicals and gases, slurry, and vacuum environments. • Determine the number of sample points and level of frequency that each point will need to be sampled. Sample intervals are generally determined based upon the expected cleanliness of the medium. Both contaminated and clean media pose unique challenges for an effective monitoring program. • Determine what level of particle sensitivity is required for each of the process steps that need to be monitored. • Think about the level of sophistication that will be needed to simplify data collection and management, as well as provide the desired presentation of data. Modern facility-monitoring software can provide a vast selection of reporting capabilities including individual sample point or grouped sample point summary reports, statistical summaries, event logs, and time plots. • Forecast the capital budget that will be available for initial equipment purchases, as well as what may be available for future expansion. It is important to include annual calibration and maintenance costs. • In the early planning stages, estimates should be made regarding the availability of human resources to manage the overall pool of instruments, operate portable particle counters, troubleshoot and correct problems in the fab or in process tools, and work with the vendors to schedule maintenance and repairs.

42.1.2 Basic Particle Monitoring Models The best monitoring strategy is the one that provides useful information. Hardware, software, and experience are all certainly important, but in the end, reliable data are what matter the most. The particle counters, software, and ancillary accessories enable data to be easily collected. Experience and insightful analysis of the data will produce information that helps keep the fab running smoothly. There are three primary particle monitoring models commonly utilized in modern semiconductor production fabs. These are continuous, frequent, and mobile monitoring. Table 42.1 compares the primary trade-offs for these models. A combination of continuous, frequent, and mobile monitoring models has generally proven to be the best overall particle monitoring strategy in modern fabs. From a high level perspective, these models are distinguished by the trade-off between how frequently data are collected reported, and the cost. Semiconductor manufacturing processes are complex and have varying degrees of cleanliness requirements. For this reason, it is unreasonable to expect a single monitoring

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:22

Page 42.3

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.3

TABLE 42.1 Comparison of Basic Particle Monitoring Models

Detection Ability Equipment Cost Installation Cost Operating Cost

Continuous

Frequent

Mobile

High High Medium Low

Medium Low High Low

Low Low Low High

strategy to provide data that helps maintain desired yields and production tool performance across an entire fab. Continuous Monitoring. Continuous monitoring guarantees that all particle excursions will be detected, so actionable information is made available to the appropriate personnel as soon as possible. The initial cost in terms of purchasing the necessary hardware is the highest among the three monitoring models; however, the degree of certainty that a process remains in control is also the highest. Installation costs must be factored into the project budgeting, as well as annual maintenance costs such as calibration. The attractiveness of a continuous monitoring system is that after the installation is completed, it runs automatically and provides myriad levels of data. Continuous monitoring is deployed in those processes that are most critical to yield and production tool up-time. The current strategy for new 300 mm cleanrooms being built is to use instruments providing 0.3-µm sensitivity at 0.1-cfm (cubic feet per minute) flowrates for continuous monitoring. Minienvironment monitoring has also proven effective at 0.3 µm, with flowrates depending on the number of sample points and length of tubing used. Particle counters used for cleanroom continuous monitoring are commonly referred to as “smoke detectors,” since particle excursions are infrequent and often large in magnitude. The same is generally true for minienvironments. There is a great deal more variability in the specifications for liquid particle counters used for continuous monitoring. Ultrapure water (UPW) is being monitored at 0.05 µm to 0.035 µm, process chemicals anywhere between 0.065 and 0.3 µm, and chemical mechanical planarization (CMP) slurry at 0.5 µm. Continuous monitoring is not widely used for process gases but is beginning to gain popularity for vacuum applications. Sensitivity requirements for vacuum monitoring range anywhere from 0.08 to 0.3 µm, depending on the tool. Frequent Monitoring. Frequent monitoring provides an effective monitoring strategy for those environments that have proven to be well controlled, or for those processes that have less of an impact on yield. The largest installed base of frequent monitoring systems in use today is in 200 mm cleanrooms. Figure 42.1 shows a frequent particle monitoring system including a multiport aerosol manifold, particle counter, pump, data collection system, and associated hardware. Manifold systems provide a reasonable amount of coverage at a lower cost than what would be necessary for continuous monitoring. The primary benefit of a frequent monitoring system is that only one particle counter is required. The aerosol manifold samples in a serial, programmed sequence. The number of sample points and sample duration depends upon the cleanliness of the particular environment and the rate at which out of control conditions need to be identified. The obvious drawback of this model is that the system provides data, with a duty cycle of less than 10 percent. Duty cycle is defined as the percentage of time that a particular location is actually being monitored. Efficiency here is defined as the inverse of the total number of manifold sample ports, and represents the rate at which particle concentration data are measured and reported to the data management systems. Particle counters with either 0.1-µm or 0.3-µm sensitivity are commonly used with aerosol manifolds. The class of the environment that will be monitored is what determines which sensitivity is ultimately chosen. Mobile Monitoring. Mobile monitoring is generally considered the preferred approach for certifying cleanrooms and minienvironments, and also for troubleshooting water, process chemical, and gas delivery systems. It is the least effective approach for ongoing monitoring. Mobile monitoring

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.4

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.4

FAB YIELD, OPERATIONS, AND FACILITIES

Aerosol manifold II system diagram Control box Controller cable Pressure monitoring tubing

Sample tubing from ISPs

PC + facility monitoring software

Manifold module Capped off Ethernet cable Lasair II sample tubing

L2 exhaust tubing Ethernet cable Vacuum adjust knob Filter

Pump Lasair II FIGURE 42.1

Example of frequent monitoring system using a manifold.

is convenient to deploy and is viewed by many to be the lowest cost particle monitoring model (mainly for aerosol applications). Many fabs in reality have fairly extensive mobile monitoring strategies that require well-trained engineers and technicians to operate the equipment and manage the data. It is easy to downplay the cost associated with these activities. If one were to actually add up all the labor and opportunity costs, hits to yield and product quality due to reacting to fab upsets rather than finding them before they cause damage, and the initial investment in the mobile particle counters, the appeal of a frequent or continuous monitoring strategy may be higher. The advantages and disadvantages for mobile, frequent, and continuous monitoring have been debated for many years and in the end, personal preference and history play a big part in what type of model is implemented. Figure 42.2 shows an aerosol particle counter suitable for mobile monitoring. The two most important performance specifications for particle counters used for mobile monitoring are sensitivity and sample volume. Since an adequate number of particles must be detected to ensure data validity, selecting a combination of first channel sensitivity and sample volume that gets to statistical significance the fastest should be the goal. The most popular aerosol mobile monitor today has 0.1-µm sensitivity at a 1-cfm flowrate. First channel sensitivity for mobile monitoring of high purity process gases is also common at FIGURE 42.2 Aerosol particle counter used for mobile monitoring. 0.1-µm, except the flowrate is typically 0.1 scfm

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.5

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.5

(standard cubic feet per minute). Mobile monitoring of UPW and process chemicals use specifications similar to those listed for continuous monitoring. Other features that make a particle counter attractive for mobile monitoring are small size and light weight, battery operation, local printer, internal memory for data storage, and ease of use, since operation may be infrequent, or many different operators may have to use the equipment. In some cases, external analog inputs for use with temperature, relative humidity, and differential air pressure sensors can be valuable.

42.2 PARTICLE COUNTER THEORY OF OPERATION The theory of operation of particle counters has received considerable attention over the years and an extensive library of information exists on the subject. The purpose of this section is to briefly review the basic theory of operation of a particle counter from a high level. The authors wish to make a clear association between a few critical light scattering relationships and the cost of a particle counter. As with all technology products, there are usually a small number of components that drive product manufacturing cost. This is also true with particle counters in terms of the optical bench that is generally considered the most important part of the overall design of the instrument. Perhaps one of the least understood relationships in particle counter technology is sensitivity versus cost. As semiconductor feature sizes have continued to shrink over the last decade, so has the need to control lower concentrations of smaller-sized particulate contamination. The current semiconductor technology roadmap is pushing conventional particle measuring equipment design to the limit. As a result, manufacturers of particle counters have developed higher sensitivity instruments for UPW, air, high-purity gases, process chemicals, and vacuum environments. The associated costs for instruments using advanced laser and optical designs have increased accordingly. 42.2.1 Light Scattering and Index of Refraction Most commercially available particle counters used in semiconductor fabs for microcontamination monitoring and process control are based on light scattering. Scattering occurs when light reaches the boundary between two different indices of refraction. The index of refraction is a complex number equal to the speed of light in vacuum divided by the speed of light in a given medium. As an example, for an aerosol particle counter monitoring in a cleanroom, laser light travels through a sample stream of air (index of refraction essentially equal to 1), and upon striking a particle (index of refraction of 1.46 for silicon dioxide in the near infrared), light is scattered. Diffraction, refraction, reflection, and phosphorescence are all forms of scattered light. Figure 42.3 shows the four components of scattered light produced by incident light interacting with a particle.

Diffraction Particle

Refraction Phosphorescence raman scattering thermal emission FIGURE 42.3

Reflection

Scattering forms as light interacts with a particle.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.6

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.6

FAB YIELD, OPERATIONS, AND FACILITIES

A different type of particle counter is used predominantly in applications where particles larger than 2 µm need to be detected. Extinction is the principle by which these particle counters work. Rather than quantifying scattered light as particles pass through the laser beam, the beam power is measured. These types of particle counters are best suited for particle size ranges from two to several hundred microns in size. The magnitude of light scattering by the large particles causes a measurable decrease in beam strength. The liquids found in semiconductor fabs are generally far too clean for this type of instrument, so it is unlikely they will be specified.

42.2.2 Design Considerations Based on Light Scattering Relationships The primary scattering relationships that drive the design of the particle counter are based on the diameter of the particle that needs to be detected. • At sizes below 0.2 µm, scattering changes by 1/(diameter)6 (predominately Rayleigh scattering) • At sizes larger than 0.5 µm, scattering changes by 1/(diameter)2 (Mei scattering) Figure 42.4 shows that this important scattering relationship also depends on the wavelength of light that will interact with the particle. The rule of thumb commonly used is that scattering increases by 1/λ4 for relatively small particles, where small implies a size less than 0.5 µm. To illustrate the impact particle size has on instrument design, assume there is a requirement to improve a liquid instrument’s sensitivity from 0.2 to 0.05 µm. Based on the Rayleigh scattering relationship given above, the signal to noise ratio of the system has to be improved over 4000 times (all other things being equal). If the 0.2-µm instrument used a 780-nm laser, some of the much needed signal could be gained by incorporating a shorter wavelength laser. It must be remembered that there are many practical limitations that ultimately determine what laser type can be designed into a particle counter. The most important factors include cost, size, power requirements, power dissipation, and lifetime. Changing to a shorter wavelength laser will help in this example, but it will only provide some of the increased signal that will be required for proper particle counter operation at 0.05 µm. Additional design criteria that will need to be addressed are; the optical power density of the focused laser spot that illuminates the sample region, the flowrate of the liquid sample stream, and electronic noise of the optical detector and signal processing electronics.

532 nm

Cross section

1E + 4 1E + 2

633 nm

1E + 0

780 nm

1E − 2 1E − 4 1E − 6 1E − 8 1E − 10 0.01

1

0.1

10

Diameter FIGURE 42.4 Scattering relationships for different wavelengths of light and particle cross-sectional area.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.7

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.7

42.3 SPECIFYING A PARTICLE COUNTER Once the basic monitoring model has been decided upon as discussed under the heading Introduction, specifics about the type of particle counter can be considered. The sensitivity of the particle counter is generally considered first since cost is closely tied to this capability. Equally important to sensitivity is the rate at which particles are detected in the desired media. The actual volume of media sampled during the selected interval should be considered equal to sensitivity when it comes to choosing a particle counter. For critical monitoring applications, the higher the number of raw particle counts observed in a single sample interval, the better. 42.3.1 Key Performance Drivers The key performance drivers for particle counters are sensitivity, sample volume, resolution, and coincidence limit. In general, the cost of a particle counter is tied closely to these parameters. There is also an interdependence between these parameters that strongly influences a particle counter’s effectiveness for a given application. Definitions for these terms are as follows: Sensitivity: Sensitivity defines the smallest particle a particle counter is capable of measuring. Increasing sensitivity refers to the capability of being able to measure smaller particle sizes. Sensitivity has the greatest influence on cost when comparing particle counters with different sensitivities. Sample volume: Sample volume defines the percentage of media sampled per unit time. Particle counters are not all volumetric, meaning a particle counter may only “view” a fraction of the total flow based on its design. A volumetric particle counter measures the particles in 100 percent of the flow that is provided. A nonvolumetric particle counter does not. All other specifications being equal, the particle counter with higher sample volume would be desirable over a rival instrument. Resolution: Resolution defines the ability of a particle counter to discriminate between particles closely spaced in size. A particle counter with high resolution would be able to separately count a 0.20-µm particle from a 0.25-µm particle, whereas a lower resolution particle counter could not tell the difference and would bin the two in the same channel. Sample volume growth is also associated with low resolution instruments. This topic is discussed further under the heading “Special Considerations for Liquid Applications.” Coincidence limit: All particle counters have an upper particle concentration limit. Electronics within the detection circuitry attempt to count one particle at a time and resolve individual light scatter produced by discrete particles. The coincidence limit is defined as the number of uncounted particles at a given concentration. When multiple particles simultaneously enter the laser beam, the electronics may resolve two small particles as one large particle. This particle coincidence is accompanied by a perceived shift in the size distribution, where particles that should normally bin in smaller channels now bin in larger channels. Particle counters should not be used in applications where the actual particle concentration exceeds the specified concentration limit. 42.3.2 Particle Counter Types It is probably not important for the purpose of this work to get overly concerned with textbook definitions for particle measuring instruments. What is relevant, and what will help those needing to specify a particle counter, is to understand a few general concepts that distinguish the many types of instruments available in the marketplace. Semiconductor manufacturers implementing particle contamination monitoring are most often concerned with detecting episodic events. These events are often rare and short-lived. The magnitude of the event may not be as important as just knowing that a cumulative particle concentration level exceeded a control level or specification. In addition, if the general particle size distribution could also be determined for the event, insight into its cause may be ascertained. The number of channels a particle measuring instrument provides is what distinguishes

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.8

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.8

FAB YIELD, OPERATIONS, AND FACILITIES

it as a spectrometer, counter, or monitor. The description—“counter” in this definition may sound strange, but is actually needed since a significant difference exists between a spectrometer and monitor. The term “particle counter” is used extensively throughout this chapter as a generic name for all instruments that monitor particle contamination. The names themselves do not matter as much as understanding the differences between the instruments, and making the best choice when specifying an instrument based on the application’s requirements. Spectrometers. Spectrometers can distinguish between particles closely spaced in size. The number of size channels depends on the dynamic range of the sizes covered. Typically, an order of magnitude particle size range would indicate a minimum of 10 size channels.1 Spectrometers are available for both aerosol and liquid applications, and depending on the number of sizing channels, they can be two to three times the cost of an instrument with the same first channel sensitivity. From a practical standpoint, 10 or more channels does not provide any significant value for most microcontamination monitoring applications in the semiconductor industry. The few instances where the performance of a spectrometer is required would be in filter design and testing, and instrument calibration studies. Liquid spectrometers have been shown to provide value because of their high resolution and stable sample volume. Monitors. Monitors are on the opposite side of the resolution spectrum compared with spectrometers. Monitors have poor resolution, although they can have very high sensitivity. Monitors have become very popular in many aerosol and liquid applications, especially those using the continuous monitoring model discussed earlier in this chapter. Monitors are ideal for those applications that require high sensitivity, where a detailed size distribution is not needed, or if there are cost constraints for making a purchase. Aerosol monitors have the largest installed base out of all particle counters throughout semiconductor fabs around the world. Specifically for aerosols, handheld monitors are ideal for routine checking and troubleshooting because of their small size, easy operation, portability, and low cost. When every particle event must be detected, monitors are typically used in a continuous particle monitoring plan so that quick decisions can be made on the impact to product and the type of action that must be taken. On the liquid side, monitors have been the preferred instrument of choice for UPW systems and many bulk chemical delivery systems, although spectrometers are becoming more popular. Monitors in general are the lowest cost type of instrument at a given sensitivity, and come with a minimal list of features. Counters. Counters are somewhere in the middle between spectrometers and monitors in terms of resolution and sensitivity. The most common “counter” found in the industry is used for aerosol mobile monitoring. Counters usually come with a more complete set of features, including on-board displays, built-in printers, temperature and relative humidity probes, analog inputs, ac power and battery operation, Ethernet communication, and the ability to be remotely controlled.

42.4

SPECIAL CONSIDERATIONS FOR AEROSOL APPLICATIONS Monitoring aerosol particle contamination requires some understanding of particle physics. Airborne particles in stagnant air can freely travel in many directions and settle onto various surfaces. Particles as small as 0.1 µm can remain airborne for very long periods of time if the local environment is not properly controlled. An airborne particle’s mobility is a function of size, mass, external forces, airflow patterns, and filtration strategies. Mobile, frequent, and continuous monitoring are all affected by these considerations, and therefore, they must be taken into account when developing a monitoring strategy. This section will discuss these and give guidelines for aerosol sampling.

42.4.1 Particle Settling Since small particles tend to carry for long distances in air, particle monitoring for particle sizes less than 1.0 µm is a primary concern. If one ignores slip coefficients (the effects of resistance at the particle’s surface), the settling velocity for a 0.1-µm particle is 8.82 × 10−5 cm/s, and the settling Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.9

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.9

velocity for a 1.0-µm particle is 3.54 × 10−3 cm/s.2 The slow settling velocity is one reason why smaller particles are particularly troublesome to control. Additional difficulty arises when the small particles settle onto surfaces, only to ascend when a force acts upon them. These forces include the movement of personnel, equipment, or changes in airflow patterns. Consequently, one must understand the nature of small particle transport with the purpose of reducing their impact upon an operating cleanroom. Ultraclean manufacturing environments typically require well balanced, highly laminar airflow to reduce small particle deposition. Conversely, large airborne particles settle much more quickly due to gravity and inertial forces. Large particles on the order of 10.0 µm settle at 3.06 × 10−1 cm/s, while 100.0-µm diameter particles settle at a rate of 2.62 × 101 cm/s.2 Their presence has catastrophic effects on wafer yields, so cleaning surfaces is common in areas with high levels of large particles. These areas may include gowning rooms for cleanroom personnel, construction zones, or tool installation areas.

42.4.2 Particle Transport in Tubing It is very common in aerosol monitoring applications to use tubing to deliver the air being sampled to the particle counter. The tubing length varies depending on the physical characteristics of the environment, as well as the monitoring scheme. Particles that get stuck or trapped in the tubing will result in data that is not truly representative of the area being monitored. Manifold systems generally require the longest lengths of tubing, and great care must be taken when specifying a system. Particle transport in tubing is affected by the bend radius, Reynolds number, electrostatic forces, and techniques to minimize particle settling and traps. The bend radius is the radius of curvature of the tubing measured in inches or centimeters. This is different from bend angle, which is the angle of the bend measured in degrees. Consequently, a tube may bend up to 90° but if the bend radius is large, the restrictions in the airflow will be small. A common bend radius is 6 in for 3/8-in internal diameter tubing, which upholds the necessary Reynolds number for particle transport. The Reynolds number is a composite figure that takes into account the sampling tube’s shape, the smoothness of the tube’s inner surface, the straightness of the tube, the media’s (e.g., air) viscosity, pressure, and temperature, and other factors that affect the flowrate inside a tube. In general, typical values for Reynolds numbers indicate the following: • Reynolds numbers less than 2000 indicate laminar flowrates • Reynolds numbers from 2000 to 4000 indicate transitional flowrates • Reynolds numbers greater than 4000 indicate turbulent flowrates Specifically, when considering particle monitoring for 3/8-in inside diameter tubing, a Reynolds number of 2200 is adequate for turbulent flow and particle transport. The other important characteristics for sample tubing include electrostatics, that is, conductive and nonconductive tubing. Simply, one should select tubing that carries minimal electrical charge; otherwise, the charged particles will stick to the tubing’s inner walls and contribute to particle counting errors. Selecting the correct sample tubing for the application is an important task. Based on general experience, the following materials are suitable for sampling lines and are listed in order of preference: 1st 2nd 3rd 4th 5th 6th 7th 8th

Stainless steel Bev-A-Line Polyester (as Polyurethane) Polyester-lined vinyl Copper High-density polyethylene Glass Teflon

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.10

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.10

FAB YIELD, OPERATIONS, AND FACILITIES

Cost is an obvious consideration in the selection of sample lines, so stainless steel is usually reserved for corrosive, reactive, or heated chemistries. The second choice, Bev-A-Line, is the most commonly installed sample tube within manifold-based semiconductor systems. Bev-A-Line utilizes a thin Teflon lining to reduce particle adhesion, and a conductive external coating, which minimizes the static buildup associated with Teflon. It is possible to design installations using Bev-A-Line tubing that transport particles up to 40 m without significant losses due to electrostatic forces. This tubing offers superior durability and greater strength than other economical solutions, plus the tubing is resistant to freezing, thermal cycling, and corrosion. The third choice, polyurethane, is the most common material for individual airborne particles monitoring over distances up to about 3 m. The tubing is inexpensive, malleable, and available in a wide range of diameters. The other sample line choices see limited use in a modern semiconductor fab with the exception of Teflon. Due to Teflon’s ability to withstand corrosive and heated chemistries, Teflon sample lines are often used in liquid particle counting applications. These applications will be discussed later. 42.4.3 Isokinetic Sampling Isokinetic sampling occurs when the probe’s sampling velocity at the face or opening is the same velocity as the cleanroom’s laminar airflow. If the probe’s sampling velocity is much greater than the laminar airflow, it can influence the natural drift of particle motion and result in higher particle counts. Conversely, if the probe’s sampling velocity is much lower than the laminar airflow, the probe will suffer backpressure and particles will vault over the probe and result in lower particle counts. Although sampling errors for particles below 1.0 µm are generally insignificant (few percent range), employing isokinetic probes provides the most accurate particle monitoring across a large range of particle sizes. Expounding upon this thought, if any larger particles are present, the isokinetic probe will help capture these particles, which provides a more representative sample.3 Designing an isokinetic sampling probe requires knowledge of the particle counter’s sampling rate and the velocity of the cleanroom’s laminar airflow. The radius of the sample probe’s face can be computed using the following formula:

r=

sampling volume (ft 3 /min) cleanroom flowrate (ft/min) p

As one may expect, higher velocities in laminar flowrates, or lower sampling volumes, require smaller sampling probes. 42.4.4 Particle Size Distributions The relationship between particle counter sensitivity and particle counter cost was explained in Sec. 42.2. Mobile particle counters with first channel sensitivity of 0. 1 µm range in cost from $15,000 to $20,000. Conversely, mobile particle counters with first channel sensitivity of 0.3 µm range from $5000 to $10,000. Purchasing a particle counter with the appropriate sensitivity not only saves money, but also prevents erroneous data caused by challenging the instrument with too many particles. Understanding particle size distribution relationships can be an extremely useful troubleshooting and diagnostic tool. The ISO 14644-1 cleanroom classification table is built around a 1-particle diameter (refer to Sec. 42.2.1) relationship. Basically, if the particle concentration at one particular size is known, the cumulative concentration of a different particle diameter can be computed. Particle size distribution for liquid applications will also be discussed in more detail in Sec. 42.5. 42.4.5 Maintenance Typically, annual maintenance and calibration cycles are required for all particle counters. This requirement satisfies ISO obligations and is not a function of the particle counter’s limitations.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.11

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.11

Modern particle counters, if properly maintained and operated, can exceed the annual cycle, and still meet calibration specifications. Calibration consists of challenging the particle counter with known size particles, and adjusting the output to correctly report the size. It is very important to develop a method to document the unit’s ability to measure the smallest size channel particle. An aerosol particle counter should also demonstrate the ability to count zero particles when exposed to ultrafiltered air once the calibration is complete. The older Helium-Neon (HeNe) lasers require periodic cleaning of both the laser optics and detection optics. This can be a simple yet time-consuming task because one must disassemble the optical components, clean, and reassemble. In addition, the HeNe laser will gradually lose power over time; so yearly calibrations will include a procedure to compensate for losses in laser power. Conversely, laser diodes require no cleaning because the unit has only one optical surface, and this surface is small and better shielded against contamination. Moreover, the laser diode has constant power for the laser’s life, so periodic power adjustments are not required. Laser diode based instruments have smaller detection optics—due to the smaller size of the laser diode—so contamination on the detection optics is minimized. Smaller optics, less issues with contamination, and constant power outputs are a few reasons why current and future particle counters will employ laser diodes whenever possible. Inlet jets are another critical component of an aerosol particle counter. Since the particles pass through the inlet jet on their way to the laser and detection optics, inlet jet alignment is critical. If the inlet jet does not eject the particles into the center of the laser beam, the particle counter will not properly size the particles. That is, if the particles pass through the edge of the laser beam, the lower amount of scattered light will cause the detection optics to undersize the particles. In addition, misalignment of the inlet jet may cause some particles to circulate through the detection optics several times, which leads to the same particle being counted more than once. Inlet jet alignment should be checked at each calibration and whenever the inlet jet is removed from the particle counter. Effective particle monitoring in aerosol applications requires some familiarity with the physics of airborne particles. Discussed in this section were various factors that influence airborne particle movement and how one can best sample this type of contamination. Understanding how to monitor airborne contamination is the first step when determining what level of sensitivity or particle size is critical for a particular monitoring process.

42.5 SPECIAL CONSIDERATIONS FOR LIQUID APPLICATIONS Specifying a particle counter for liquid applications is more complicated compared to aerosol applications in semiconductor manufacturing. This is due to design trade-offs related to sensitivity and sample volume for the particle counter, and the characteristics of the chemistry that will be monitored. Even after the best liquid instrument for a given application is identified, care must be taken in the installation to ensure that data are actually representative of the particle concentration in the liquid being sampled. There are two primary types of particle counter systems for liquid applications: online and batch sampling. Online applications are characterized by distribution lines under pressure supplying the liquid to the process or manufacturing tool in the fab. The most common online plumbing configuration is to tee off the main line using the appropriate diameter tube as required by the inlet of the particle counter. Generally, 1/4 in Teflon tubing with Flaretek connections are most commonly used with liquid particle counters. A flow meter is connected downstream of the particle counter and must be adjusted to match the flowrate that the instrument was calibrated at. Depending on the application, the outlet of the flow meter can be returned to the main distribution line or sent to drain. In many instances a liquid must be sampled from a drum or other vessel. In these instances, a sampler must be used in conjunction with the particle counter to deliver the liquid at a constant pressure and flowrate. The two main types of batch sampling systems are syringe and compression. Table 42.2 summarizes the features of both of these types of samplers.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.12

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.12

FAB YIELD, OPERATIONS, AND FACILITIES

TABLE 42.2 Comparison of Syringe and Compression Samplers Features Sampler type

Bubble suppression

Service life

Sample consumed

Ease of use

Cost

Syringe

None. Can also aspirate effervescent chemicals causing bubble formation.

Not intended for continuous sampling because of wear and tear on the syringe. Compatibility issues with corrosive and viscous chemicals.

Adjustable based on the volume of the syringe. Good choice for expensive chemistries.

Basic. Very little operator training is required.

$5 to $10K in addition to the cost of the particle counter.

Compression

Yes. Best choice for sampling effervescent chemicals or liquids having large concentrations of dissolved oxygen.

Continuous sampling is not a problem.

Fixed. Typically consumes more than syringe samplers.

Complex. Compression samplers have numerous settings that must be optimized for the chemical being tested.

$15 to $20K in addition to the cost of the particle counter.

Although in theory syringe samplers could be used in semiconductor manufacturing applications, they rarely are because of the corrosive and effervescent nature of most of the chemicals used in the fab. In addition, syringe pumps have a difficult time drawing samples of viscous fluids. 42.5.1 Volumetric Instruments Liquid particle counters can be classified as either volumetric or nonvolumetric. The term “volumetric” refers to whether or not the particle counter is viewing the entire sample flow provided. It has been discussed how index of refraction boundaries produce scattered light the particle counter interprets as particles. Liquid instruments require a means of delivering the sample flow to the region where the laser beam will illuminate it. A capillary is a precision optical component commonly used for this purpose in high-sensitivity instruments. Minute imperfections in the optical surfaces where laser light intersects with the capillary causes background scatter that can compromise the instrument’s signal to noise ratio. If this noise becomes excessive, it will limit the sensitivity of the particle counter. Figure 42.5 shows an example of how the laser beam interacts with the capillary. The laser beam in a volumetric particle counter is focused so that its intensity is mostly uniform across

Max. Min.

FIGURE 42.5 Typical laser intensity profile for a volumetric particle counter.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.13

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.13

the capillary. This allows the particles flowing in the liquid to be exposed to the same amount of light energy, regardless of where they are located in the flow path. The benefit of this type of design is that particles in the entire volume of liquid passing through the capillary are counted and sized, resulting in shorter times to statistical significance in clean liquids. The drawback to this design is that the capillary walls are illuminated with the high-intensity laser beam, and as previously discussed, unwanted scatter (noise) will result limiting first channel sensitivity. The highest sensitivity volumetric particle counter available today provides 0.1 µm first channel sensitivity. Volumetric instruments with this level of sensitivity may require frequent capillary cleaning as residue can collect in the area of illumination and cause false counts in the first channel. Volumetric instruments provide good sensitivity, large sample volumes, and generally lower flowrates compared to nonvolumetric instruments. The key advantage is sample volume. Furthermore, due to lower flowrates, and large sample volumes, volumetric devices can be used in both batch and inline sampling. 42.5.2 Nonvolumetric Instruments

Intensity

Nonvolumetric particle counters provide high sensitivity, smaller sample volumes, with higher flowrates than volumetric particle counters. Sampling particles within an optically defined sample volume near the center of the flow path eliminates noise caused by scattered light from the capillary wall. Consequently, eliminating background noise provides higher sensitivity. The laser is focused more tightly in nonvolumetric instruments, further increasing sensitivity but reducing the sample volume. Although nonvolumetric particle counters have poor resolution, they are ideal for sampling main process Max. supply lines or point of use delivery lines where continuous contamination monitoring is necessary. The typical spatial intensity profile for most lasers used in commercially available nonvolumetric particle monitoring instruments is shown in Fig. 42.6. Min. There is one drawback to using a nonvolumetric monitor for monitoring liquids that have fairly high levels of particle contFIGURE 42.6 Typical laser intensity amination. Large particles that pass through the edges of the profile for a nonvolumetric particle laser beam (areas of low intensity relative to the center of the counter. beam) have sufficient cross-sectional area to scatter small amounts of light. In these instances, the particle counter will size and count this scatter as small particles generally showing up in the first channel. This phenomenon is termed sample volume growth and results in the particle counter incorrectly reporting cumulative and differential counts. It is generally prudent to consult with an applications engineer from the chosen vendor of the particle counting equipment to review the application prior to purchasing a high sensitivity, nonvolumetric liquid monitor. 42.5.3 Installation Guidelines A well thought-out installation plan is essential to get meaningful particle concentration data. There are several areas related to the installation that need to be carefully observed for optimum performance. Plumbing. Small particles will stick to the inner tubing walls if given the chance. Even at flowrates as high as 1 L/min, particles in UPW will collect in tubing over time. This is less of a problem for corrosive chemicals because of the aggressive nature of the chemical. Still, good technique regarding plumbing connections should be practiced whenever possible. The best practices require

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.14

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.14

FAB YIELD, OPERATIONS, AND FACILITIES

keeping the tubing lengths as short as possible and minimizing connections. It is extremely important to make well-formed Flaretek connections on all tubing to prevent leaks and particle traps. For particle counters where there is a vertical offset between the inlet and outlet (due to the design of the instrument and how it is mounted), the inlet should be the lower of the two to minimize potential bubble problems. Also, pressure drops upstream of the particle counter must be avoided. Dissolved gases can be released as bubbles and counted as particles if a pressure drop occurs prior to the liquid flowing through the particle counter. Finally, valves are notorious particle generators and can shed thousands of particles upon activation. Valves and all fittings upstream of the particle counter should be carefully chosen to minimize unnecessary particle generation. Flowmeters should be plumbed downstream of the particle counter and always set to the specified flowrate to ensure that the correct particle concentration levels are reported. Contamination. Contamination that requires significant cleanup time has proven to be a problem for mobile liquid monitoring applications. As previously mentioned, the act of physically connecting the inlet tubing to the monitoring tee will produce a burst of particles that can be quite significant, depending on the prior liquid that was sampled and the age and quality of the tubing and connections. When practicing mobile liquid monitoring, make sure to provide adequate time after making connections and initiating fluid flow to allow the particle counter to cleanup and reach an appropriate baseline level prior to collecting actual particle concentration data. In some cases the time to reach the baseline can be improved by flowing at high rates for a short time period after starting. Always make sure to set the correct flowrate prior to collecting data. Data Output. Particle counters used for mobile and frequent monitoring will generally have a local display and some ability to export data to a computer. In many cases a simple printed output for each sample is sufficient for a mobile monitor used to certify a cleanroom or clean manufacturing area. Because frequent monitoring can collect vast amounts of data, some ability to export data to a PC is usually desirable. Particle counters used in the continuous monitoring model almost always communicate with a facility monitoring PCs using RS232, RS484, or Ethernet communications. RS232 is designed for point-to-point contact between a single instrument and PC, with a maximum cable length of approximately 15 m. RS484 can communicate data up to 1200 m at fairly high speeds. It has been a standard method for configuring facility monitoring systems consisting of a large number of individual particle counters for many years. Ethernet communication has become very popular in recent years as the communications backbone for large facility monitoring projects. This type of communication protocol is also the least expensive to implement mainly because modern semiconductor fabs come wired with Ethernet jacks, and therefore no extraordinary communication installation is required.

42.5.4 Effervescent Chemicals There are several process chemicals used in semiconductor manufacturing that are extremely difficult to measure with an optical particle counter. Hydrogen peroxide, ammonium hydroxide, sulfuric peroxide mixture, and buffered oxide etch are but a few considered effervescent. These chemicals whether treated separately, or as a blend with other chemicals, release gas or through reaction, create bubbles that corrupt particle counter data. In these instances, the bubbles produced are typically 1 µm or larger in size. It is fairly easy from an analysis standpoint to identify these bubbles counted as particles because large spikes will appear in the data in the larger channel sizes. The most effective method proven to eliminate bubbles is with the use of a compression sampler. This type of instrument integrates a particle counter with a sampling and flow system designed to compress bubbles back into solution prior to flowing the liquid through the particle counter for measurement. There are two other instances worth mentioning when a compression sampler may be required. The first is for liquids with high levels of dissolved gases. The second involves agitating viscous chemicals. As an example, as a chemical becomes agitated from pouring it into a container, air can become entrained, forming bubbles. Depending on the viscosity, these bubbles may remain

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.15

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.15

present in the liquid for hours or days, and pose difficult challenges for measuring particle concentration levels. 42.5.5 Contrast Ratio Optical particle counters measure the equivalent optical size of real-world particles. Particle counters base their sizing on the magnitude of scattered light produced by the particles in the medium of interest, compared to light scattered by polystyrene latex spheres (PSLs) in UPW. PSLs are traceable size standards used throughout the industry to calibrate optical particle counters. PSLs come in a vast assortment of sizes, have well known optical properties and a low-variance size distribution. Particle counters assume that all real-world particles are spherical and have an index of refraction of 1.59 based on the use of PSLs in their calibration. Table 42.3 assumes a particle counter using a 780-nm laser and particles that have an index of refraction of 1.59. The values in the columns HF, H2O2, HCl, and H2SO4 represent the size of the real-world particle in microns that would be necessary to scatter light equivalent to the PSL size listed in water (H2O) or ammonium hydroxide (NH4OH). 42.5.6 CMP Slurry Optical particle counters have been used to measure particle concentrations in CMP slurries. This application is quite complex, and proper treatment goes well beyond the scope of this chapter. Particle counters can be made to work in this application, although it certainly is pushing the basic technology to its limits. Particle counters are generally used to measure low to medium levels of particle concentrations in semiconductor UPW and process chemicals. Concentrations range anywhere from 1 particle per milliliter greater than 0.05 µm in UPW to several thousand greater than 0.2 µm in the dirtier chemistries. CMP slurry can have 1014 particles per milliliter at a distribution mode of 0.05 or 0.1 µm. For the same distribution at 0.5 µm, particle concentrations can exceed 106 particles per milliliter. The basic challenge is to dilute the slurry sufficiently so that the particle counter is not limited in performance by coincidence problems as discussed in Sec. 42.3 of this chapter. Additionally, if the dilution is not performed properly, pH shock can cause the slurry to agglomerate, resulting in an increase in the number of large diameter particles. 42.5.7 Liquid Particle Size Distributions The particle size distributions in filtered, closed-loop liquid distribution systems, vary from 1/d 2 to 1/d 5. The main reason for this large difference is the quality of the filtration. The important point is that once the size distribution is known for a given type of chemistry in a particular distribution loop, it is repeatable, as long as the loop is operating properly. If the distribution changes, there is a good indication that something in the loop, filtration, mechanical components such as pumps, degas modules or other, has changed. In these instances, the particle size distribution, together with the cumulative particle counts can aid system troubleshooting and maintenance. Knollenberg and Veal conducted an extensive analysis of semiconductor UPW distribution systems in 1990, and found that the particle size distribution closely followed a 1/d 3 relationship.1 As a

TABLE 42.3 Comparison of Particle Sizing in Common Process Chemistries PSL size in H2O and NH4OH (µm)

HF

H2O2

HCl

H2SO4

0.3 0.5 1.0

0.28 0.46 0.87

0.31 0.52 1.1

0.36 0.62 1.80

0.4 0.72 2.30

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.16

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.16

FAB YIELD, OPERATIONS, AND FACILITIES

general rule of thumb, using the 1/d 3 relationship for all liquids provides a good first order approximation for estimating cumulative counts. An example is provided below for calculating the particle concentration at 0.05 µm, based on a known concentration of 0.1 µm, for a typical semiconductor fab DI water system. 3

d  ( d )µm =  2  × ( d 2)  d1  where (d) µm = calculated cumulative counts at the particle diameter of interest d2 = particle diameter where cumulative counts are known d1 = particle diameter of interest It can be seen from this formula that as the particle size decreases by one half, the cumulative number of particles increases by a factor of 8. Using the example above, a DI water system having 1 count per milliliter at 0.1 µm would have eight counts per milliliter at 0.05 µm. 42.5.8 Maintenance As with aerosol/gas particle counters, liquid instruments generally follow an annual calibration cycle. Periodic flushing or cleaning the sample flow cell or capillary is the only other type of maintenance that is sometimes required. Particle counters used to monitor DI water, almost never require cleaning since this liquid is so clean. Process chemicals on the other hand can have high concentrations of particle contamination, so periodic cleaning and flushing of particle counters used for this type of monitoring is more common.

42.6 CONTAMINATION CONTROL HIERARCHY Contamination control strategies continue to evolve as semiconductor manufacturing moves to 300 mm wafers with continually shrinking critical dimensions. The responsibility for managing particle monitoring equipment, as well as the overall scheme of where to monitor, has changed in recent years. The responsibility has shifted from facility management personnel to dedicated microcontamination staff for specifying, operating, and maintaining particle monitoring instrumentation. With production wafers generally protected from the cleanroom air, emphasis is now placed on in situ monitoring, or monitoring within the production tool. This section discusses the evolving contamination control hierarchy in semiconductor manufacturing. 42.6.1 Facility Monitoring Facility monitoring is a rather generic term that has been used for many years and includes particle monitoring in cleanroom air, DI water, process chemicals, and gases. Baseline particle levels in these media must be first understood, so that control limits can be determined and excursions readily detected. Cleanroom air monitoring can be accomplished in several different ways, but in general, there are two primary approaches adopted in fabs—manifold systems or individual particle monitors. Manifold systems, which were explained earlier, are more easily installed during fab construction. Manifold sample lines may extend up to 40 m from the manifold to the sample probe. These sample lines are installed from the manifold, through the subfab or fan-deck, and penetrate through areas to the sampling locations. This installation usually requires drilling holes into walls and running the sample lines under raised floors. Care must be taken when locating sampling hardware to ensure continued access to the equipment over time and to make sure that other equipment does not interfere with the sample tubing. Manifold systems are most easily installed during fab construction because of the complexity associated with the plumbing.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.17

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.17

Individual particle monitors can be installed within an operational fab and have minimal impact upon wafer production. Most modern fabs have vacuum, power, and Ethernet communication ports located equidistantly throughout, so the installation is much less complex and less of a drain on resources. Unlike sampling with a manifold, dedicated sampling provides continuous coverage of critical points. Brief and intermittent particle excursions can be detected without fail. This type of monitoring should utilize short sampling intervals from a minimum of 10 s to a maximum of 10 min. Shorter sample intervals accentuate the magnitude of particle excursions, while maintaining minimal demand upon system resources. Manifold style monitoring for liquids has not been implemented because the valve used for sample point switching would be a particle generator. Liquid monitoring in facilities therefore relies upon individual particle counters plumbed inline or used in a mobile monitoring approach. It is not uncommon for airborne and liquid facility monitoring systems to report to different data collection systems. Although one of these systems may report an alarm caused by particle counts exceeding a control limit, facility monitoring is “open loop” in the sense that a person must react to the disruption and take action. 42.6.2 Process Tool Monitoring As mentioned previously, the responsibility for particle monitoring equipment has shifted from facilityoriented individuals to tool/process-oriented individuals. It is quite common now for a microcontamination department to manage particle monitoring operations within a fab. Microcontamination personnel analyze data and react to excursions. In this respect, tool monitoring as it exists today is the same as facility monitoring, an open loop strategy that requires people to react to particle data. Consequently, these individuals must effectively communicate with the fab’s process engineers to keep a particular process running smoothly. Failure to develop and encourage this level of cooperation often results in a less than optimum performance from the investment in contamination control. Monitoring production tools requires an extensive understanding of the manufacturing process. Tool-level particle monitoring in photolithography, ion implantation, diffusion, and wet etch have caught particle excursions providing financial savings large enough to pay for the monitoring equipment many times over. Metrology tools such as surface scanners and wafer probers have also proven excellent candidates for dedicated particle monitoring. Air, process chemicals, UPW, and purge gases are all reasonable candidates for tool-level monitoring. A brief discussion providing general monitoring guidelines for each of these is presented next. Air/Minienvironments. Minienvironments isolate product from people, who are the largest sources of particle contamination in a cleanroom. Minienvironments, however, do not stay particle free indefinitely. A minienvironment may be certified as ISO class 1 or 2 when it is new, but robotics, door seals, and filter problems develop within most minienvironments over time. Therefore, particle monitoring combined with differential air pressure monitoring provides valuable insight into a minienvironment’s ability to maintain process integrity and protect the product from die-killing contamination. Minienvironment monitoring presents a few unique challenges. First, there can be hundreds operating inside a production fab, so instrument cost matters a great deal. Next, these environments are fairly large in size with moving parts separated from each other, so monitoring coverage is important. First channel sensitivity of 0.3-µm has proven to provide the best combination of excursion detection ability and cost, as well as the fact that substantial wafer-yield issues occur at this size. Minienvironment process monitoring tools that meet the challenges of low cost while providing high coverage, are now available. The tool uses an ensemble manifold including up to seven ports. Each port is connected to sample tubing that is plumbed to the desired sampling location. Therefore, multiple zones of coverage are monitored by a single particle counter.4 Particle monitoring in the minienvironments should focus on wafer process areas and wafer transport paths. One does not need to monitor areas where a wafer will never be exposed, so particle-monitoring probes should be mounted along definitive paths of the wafer process. These sample probes should mount at the lowest point

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.18

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.18

FAB YIELD, OPERATIONS, AND FACILITIES

along the wafer path. The benefits of monitoring multiple sample zones are obvious, but often, manufacturers will question the location of a particle excursion when samples are mixed from all zones. Experience has shown that when a minienvironment suffers a particle excursion, the personnel responsible for the minienvironment immediately recognize the particle source. Therefore, they do not need to investigate the source of the particles because the problem is intuitively obvious: preventative maintenance issues, doors not properly closed or sealed, fan-filter-unit failures, or gross product defects. A handheld particle counter can be connected sequentially to the manifold tubing in the instances where particle excursions are not so obvious. It is important to keep the air pressure higher in the minienvironment than in the outside cleanroom air. Differential air pressure sensors built into the process monitoring tool provide this capability. The high-pressure input should be connected somewhere in the minienvironment, with the low-pressure input routed to the fab’s manufacturing bay or service chase. Monitoring both particles and differential pressure at the same time provides valuable insight into the minienvironment’s functionality. This information reveals instantaneous problems within a minienvironment and long-term contamination trend analysis.5 Figure 42.7 shows a process monitoring tool designed for use in minienvironments. Vacuum. Monitoring particles in vacuum chambers has been done for some time and successes have been realized on almost every type of vacuum-process tool. Most defects occur during processing and 70 to 80 percent of process steps are done in a vacuum so the motivation for monitoring particles in a vacuum is huge. Benefits can include real-time detection of anomalies, extension of maintenance intervals, eliminating test wafers, and faster recovery from maintenance and anomalies. In many instances the economic benefits of process monitoring are difficult to quantify because the occurrence of particle anomalies and yield improvements are difficult to predict. However, if one sensor detects a problem that saves one shift of production on a tool, the money saved will pay for sensors for every tool in the fab. There are many anecdotes that demonstrate the value of monitoring the vacuum process. Recently a customer detected a problem on a 300-mm tool that saved over 20 front opening unified pods (FOUPs) worth of products. Without real-time monitoring the problem would not have been detected until the next particle check at the end of the shift. The value of each FOUP exceeded $50,000 so the total savings was in excess of $1,000,000. Return on investment (ROI) on improved productivity and material savings are easier to quantify. A major manufacturer has been able to eliminate all test wafers on a 300-mm process step.

FIGURE 42.7

Minienvironment process monitoring tool.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.19

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.19

Previously, they ran three particle checks per day. Each particle check costs more than $1000 given the cost of the silicon, the test equipment, and the lost production time. Simple arithmetic shows a savings of over $90,000 per month per tool. Monitoring vacuum processes, however, requires development effort and ongoing maintenance to be successful. Before 300-mm production, the cost of lost wafers and downtime was bearable and the manufactures typically opted to roll the dice and gamble that particle problems would be rare, rather than invest in monitoring equipment. Now the risks are too high and downtime too expensive to not invest in equipment and people to monitor contamination. Wet Etch. In situ monitoring of the wet etch process has been getting some attention lately. The traditional method of qualifying a production bath and maintaining it based on time or product exposure has its limitations. Mechanical problems in the recirculation loop and product accidents (wafer breakage) sometimes go undetected for prolonged periods of time. During this time, production wafers are exposed to baths that can have an elevated concentration of particles, resulting in a significant number of adders that are potential die-killers. A technique that has been proven effective from preventing this undesirable situation is to implement in situ liquid monitoring in a production wet bench. Compression liquid samplers are the best choice because they can remove bubbles that are common in many of the chemicals that are used to clean wafers. In situ monitoring offers one additional area for potential cost savings by allowing the process engineer to optimize the process used for chemical and filter changes. As a bath processes more batches of wafers, the background particle concentration will rise as the filters become loaded. If chemicals and filters are changed on a time schedule, the filters may still be functional, and the chemical within specification. If both are changed when the bath fails to qualify after test wafers are run, the product may be unnecessarily exposed to high concentrations of particles. Continuous particle monitoring will provide a constant process signature so the condition of the recirculation loop and the chemical quality is always known. An often debated topic is exactly where to monitor, that is, from where to collect the chemical sample. From a cost and convenience standpoint, plumbing a particle counter into the recirculation loop after filtration can give some meaningful particle data but it is not the best choice for two reasons. First, the filters will have removed the majority of the particles resulting from an excursion, so the magnitude of an event will not be known. Next, this location is nowhere close to the product so you can never really be sure what levels of contamination production wafers are seeing. Assuming that there is sufficient pressure in the loop, bubbles from effervescent chemistries may be removed, but this cannot be guaranteed. Also, as filters load, a pressure drop is likely to develop, further increasing the possibility of bubble formation. This technique does offer the advantage that a liquid sampler is not required, therefore providing a lower cost solution. The best monitoring approach is to use a compression liquid sampler in combination with a volumetric particle counter, and monitor directly from the bath itself. This method provides data that represents the closest picture into the condition of the chemical the product was directly exposed to, data can be easily correlated to the product batch that was processed and the compression prior to sampling eliminates bubbles for corrupting measured results. The sample inlet tube is normally placed near the edge of the tank to prevent it from interfering with the product, and as close as possible to the liquid surface without the possibility of sampling air, if the liquid level drops during processing. Purge Gases. Airborne molecular contamination in the form of hydrocarbons and acid gases found in the purge gases used in photolithography can cause damage to the reticle and imaging optics. The financial consequences of this can be devastating. The ability to monitor in real-time and with high sensitivity can mitigate irreversible damage from occurring. (Airborne molecular contamination is briefly discussed under the heading “Airborne Molecular Contaminatio”). 300 mm semiconductor manufacturing offers more imposing challenges for all forms of particle monitoring, but as described in this section, several tool-level monitoring approaches have met the challenge. Production tool and process monitoring will become more important as manufacturing approaches the HP 65 node and below.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.20

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.20

FAB YIELD, OPERATIONS, AND FACILITIES

42.6.3 Next Generation One thing seems to be clear as Original Equipment Manufacturers (OEMs) develop more sophisticated tools allowing the state of the art in semiconductor manufacturing to advance. Process tools will accept inputs from various monitoring equipment to automate production. Future applications require higher sensitivity and integrated data from particle counters designed for process control rather than contamination control. Potential applications include the following: • Online monitoring of slurry to control percent solids and polishing performance. • Vacuum particle monitoring in ion implant to control tuning of the beam. • Controlling wet bench pevative maintenance scheduling based on actual particle concentration data. • Controlling chemical filter maintenance in lithography tools based on real-time molecular contamination levels. • Shutting production down when fan-filter units fail in minienvironments. • For immersion lithography, how will bubbles and particles affect production? This is still being researched at the present time.

42.7 AIRBORNE MOLECULAR CONTAMINATION Airborne molecular contamination (AMC) is gaining an ever-increasing focus as semiconductor manufacturers and other leading edge technology producers face process drift and yield losses attributed to this gas-phase form of contamination. Yield improvements through the reduction of AMC are now a significant challenge as facilities stabilize other sources of contamination. As more and more sites gain control over their particle contamination issues and circuit geometries continue to shrink, emphasis is shifting to AMC as the next target for improving productivity.6 Molecular contamination takes many forms, such as condensable organics, dopants, and acidic and basic gas species, and can originate from a variety of sources such as makeup air, process gases, chemicals, materials, and even humans. In a cleanroom, AMC either comes from the outdoor “makeup air” or is generated within the facility. Examples of AMC sources within a facility include recirculated air (with inadequate filtration), cross-process chemical contamination, outgassing of cleanroom materials (filters, gel sealants, construction materials, and the like), people/personal care products, and equipment.7,8 AMC deposition on surfaces (wafers, optics, product transport containers, and the like) can occur in a reversible or irreversible manner. Reversible AMC is usually physically adsorbed on the surface. It is always either in equilibrium or trending toward equilibrium with the ambient air. When the chemical contamination levels increase in the ambient air, the mass on the surface will increase proportionally (and rapidly). When the air contamination decreases, the contamination mass on the surface will decrease proportionally. The rate of mass loss from the surface depends on the volatility of the chemical compound and any interactions with other surface contaminants. More volatile compounds reequilibrate faster than less volatile compounds. Irreversible AMC can be either physically adsorbed or chemically bonded to the surface, and results in surface molecular contamination (SMC). SMC can be highly reactive with the surface and have very low volatility. In either case, once it contacts the surface, it remains on the surface. Figure 42.8 illustrates high, medium, and low volatility surface contamination events. AMC interactions with surfaces are complex, physically and chemically, and occur on time scales ranging from seconds to days to weeks. To fully understand AMC issues in an ultraclean manufacturing environment, observations must be made: • With high sensitivity • On time scales considerably shorter than brief AMC events • Over sufficient duration to be able to establish a baseline contamination level

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.21

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.21

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

AMC near photoresist tool Medium volatility, reversible deposition

Mass (ng/cm2)

High volatility, reversible mass deposition events 9 8 7 6 5 4 3 2 1 0

Low volatility or surface bonded, irreversible deposition 13

14

15

16

17

18

Day FIGURE 42.8

High, medium, and low volatility surface contamination events.

When these monitoring criteria are met, short-term AMC events can be distinguished from longterm contamination trends, and AMC events can be directly correlated to activities and process steps.9

42.8 CONCLUSIONS An effective particle monitoring strategy is more important today than in the past. The reason is that there is now considerably more financial risk associated with particle contamination on 300 mm production wafers. Not only is there more invested in the work in process, but also the size of killer particles has shrunk accordingly with circuit feature sizes. This chapter has identified that a “one size fits all” contamination-monitoring strategy does not exist. The trend today is to incorporate a mixed model containing some combination of continuous, frequent, and mobile monitoring. Microcontamination control professionals must choose between monitors, counters, and spectrometers depending on the sensitivity requirement of the application, balancing sample volume, resolution, and instrument cost. The physics behind particle transportation in aerosols affect the data a particle counter reports. Clean manufacturing requires unidirectional airflow that is balanced and of sufficient velocity to “sweep” away particle contamination before it can land and stick to product surfaces. The type and length of sample tubing used must be carefully chosen to prevent undercounting due to particles getting stuck in tight bends or because of electrostatic attraction. Stainless steel is a good candidate for applications requiring long runs but is seldom used because of its cost and the difficulty associated with installation. Frequent monitoring applications that use a manifold generally employ Bev-A-Line tubing because it is cheaper and easier to work with than stainless steel. Polyurethane is the most popular tubing material because of its low cost and good performance up to about 3 m in length. Isokinetic sampling is sometimes used in applications requiring the most precise particle concentration data. In these instances, it is important to make sure that the isokinetic sampling probe has been designed for the correct air velocity in the environment that will be monitored. Monitoring particle contamination in liquids may be the most challenging group of applications in the fab. Effervescent chemistries contain bubbles that can be counted as particles resulting in inaccurate cumulative counts and skewed size distributions. Actual particle concentrations, whether very large or very low, will minimize the success of a monitoring program. Large particle concentrations can overwhelm the particle counter and produce data that is inaccurate or completely meaningless when the instrument becomes saturated (the most extreme case). On the other hand, detecting too few particles in a given sample interval will produce highly variable data due to a lack of statistical

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.22

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING 42.22

FAB YIELD, OPERATIONS, AND FACILITIES

significance. For these reasons, the choice between a volumetric and nonvolumetric style of particle counter must be seriously considered for each individual application. Particle counters are fairly robust instruments and require little maintenance. Both solid state and gas lasers are used in commercially available instruments, and the specific maintenance, such as periodic cleaning, depends on the type of laser that is used. In general, aerosol instruments using gas lasers require more periodic cleaning than instruments using solid state lasers. This is because some designs require critical optical surfaces to be exposed to the sampled air. The type of laser used has less of an effect on cleaning for liquid particle counters. The main thing that impacts the frequency for periodic cleaning in liquids is usually the cleanliness of the liquid itself. Liquids with high concentrations of particles can contaminate the sample cells used in liquid particle counters. Cleaning this contamination out may be as simple as flushing with DI water, to aggressively forcing a chemical cleaner through the instrument. Molecular contamination is emerging as the latest monitoring and control challenge for microcontamination specialists. AMC that turns into SMC has been shown to change the electrical, optical, physical, and chemical properties of a surface. The duration of molecular contamination events can be as short as a few minutes. Sub parts per billion concentration levels of nonvolatile organic species, acidic gases, and chemical bases can be highly destructive in processes such as implant, lithography, and diffusion. For these reasons, high sensitivity and real-time monitoring have shown promise early in this next generation contamination control challenge. The role of particle monitoring has changed, and continues to change as semiconductor manufacturing becomes more complex. Facility monitoring is a term that broadly describes monitoring for particles in the production process inputs. Tool-level monitoring emerged as the best strategy with the introduction of 300-mm wafer production. In both of these instances, fab engineers respond to reported particle data and take the necessary action to minimize product loss, and keep the tool running within specification. Next generation particle monitoring instrumentation or tools will be designed for process control. These tools will play an active role in automating, maintaining, and optimizing complex manufacturing processes. A well-designed and implemented particle monitoring program will pay for itself by providing information that can be used to maximize yield and optimize production tool efficiency. The key to success is to evaluate the monitoring requirements for each individual application so that the most appropriate particle counter can be selected.

NOTE FLARETEK is a registered trademark of Entegris, Inc. TEFLON is a registered trademark of E. I. Dupont De Nemours and Company. Bev-A-Line is a registered trademark of Thermoplastic Processes, Inc.

REFERENCES 1. Knollenberg, R. G., and D. L. Veal, “Optical Particle Monitors, Counters and Spectrometers: Performance Characterization, Comparison and Use,” Proceedings of the Institute of Environmental Science, IES, 1991. 2. Knollenberg, R. G., B. T. Haley, and D. E. Steidtmann, “An Examination of the Effects of Instrument flowrate, Sensitivity, and Background Noise on Cleanroom Particle Count Statistics,” Proceedings Institute of Environmental Sciences, IES, Anaheim, CA, April 1995. 3. Particle Measuring Systems, “Clean Area Operation Monitoring with Isokinetic Probe,” Particle Measuring Systems’ Application Note No. AP05, Particle Measuring Systems, Boulder, CO, 1999. 4. Kochevar, S. D., “Particle Monitoring in Minienvironments,” Particle Measuring Systems’ Application Note No. 44, Particle Measuring Systems, Boulder, CO, March 2004.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.23

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

42.23

5. Belew, B., R. P. Lucero, S. D. Kochevar, and S. Jorgensen, “High-yield Manufacturing: Particle Monitoring in Minienvironments,” Cleanrooms, April 2004. 6. Middlebrooks, M. C., “Airborne Molecular Contamination Control and the Effects of Filter Media Technical Parameters,” Cleanrooms East, 2000. 7. “Airborne Molecular Contamination in Cleanrooms,” Cleanrooms, Vol. 12 (1): pp. 1–5, January 1998. 8. Hope, David A., and W. D. Bowers, “Measurement of Molecular Contamination in a Semiconductor Manufacturing Environment Using a Surface Acoustic Wave Sensor,” Productronica 97, Productronica, Munich, Germany, November 1997. 9. Rodier, D., “Real-Time Monitoring of Airborne Molecular Contamination (AMC),” Particle Measuring Systems’ Application Note No. 38, Particle Measuring Systems, Boulder, CO, 2002.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH42.qxd

04/04/2005

21:23

Page 42.24

PARTICLE MONITORING IN SEMICONDUCTOR MANUFACTURING

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.1

Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 43

WASTEWATER NEUTRALIZATION SYSTEMS Richard E. Pinkowski Digital Analysis Corp. Skaneateles, New York

43.1 INTRODUCTION pH is a ubiquitous measurement that impacts the most important qualities of water. These characteristics include the ability to dissolve metals, hold nutrients, hold or dissolve oxygen, and support aquatic life. As little as one cup of sulfuric acid in a tank of 1000 gal of water can lower the pH from 7.0 to less than 3.0, illustrating that very little acidic or basic material is required to effect a significant change of pH. Most processes in industry can have a big impact on the pH of water. Wastewaters generated in industry are most often discharged to the local publicly owned treatment works (POTW) via the sanitary sewer system. These municipal systems/operators must discharge within a pH range of 6.5 < pH < 8.5 as mandated by the Clean Water Act. Most POTWs do not have the ability to adjust the pH; therefore, it is incumbent upon the users of that system to ensure that the effluent from that plant falls within this federally mandated range. This can only be accomplished by very tightly limiting the pH of industrial effluents. Many pH adjustment systems implemented in industry fail to perform as expected, or do not perform at all because of a myriad of design deficiencies stemming from a basic misunderstanding of the parameter referred to as pH. To discuss the design and implementation of pH adjustment systems we must first have a basic understanding of water and the chemistry of pH. This chapter first introduces the reader to basic water chemistry, the concept of pH, and the objectives of a pH adjustment system. We then proceed to discussing the information that is required to properly design a system and we examine the architecture of standard pH adjustment systems. After discussing the architecture of standard systems that we see in industry, we dissect the weak points and optimize the standard architectures once we have identified the weak points. Finally, we discuss an overall design and construction strategy and methods.

43.2 WATER AND pH 43.2.1 Water Water as we know it, is not as it appears—a strange substance indeed, that does not act at all as it should, at least according to the laws of physical chemistry. While most substances contract with

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

43.1

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.2

WASTEWATER NEUTRALIZATION SYSTEMS 43.2

FAB YIELD, OPERATIONS, AND FACILITIES

descending temperatures, water is the densest at 4°C, and expands at lower temperatures. That is why ice is so slippery. As pressure is applied to ice, the surface actually thaws under compression and gets lubricated. This gives ice skates their slippery edge. Water exhibits other strange characteristics such as existing in all three states (solid, liquid, and gas) at one temperature. Essential to life as we define it, water makes up more than 70 percent of the human body and 75 percent of the earth’s surface. Less than 4 percent of the earth’s water supply is available as fresh water. Because water is an excellent solvent, “pure” water does not occur naturally. There are a myriad of elements and compounds dissolved in the natural water supply. These compounds range from the salt in the ocean to naturally occurring, yet lethal levels of arsenic in some parts of the world. When water vapor condenses and precipitates in clouds it is normally very clean and relatively pure. However, as it falls through the atmosphere it immediately begins to acquire impurities ranging from CO2 to pollutants that yield carbonic, sulfuric, and nitric acids. Even if water successfully made it to the ground in a relatively pure state it would immediately begin to pick up impurities, as the minerals and elements that make up our earth’s crust begin to dissolve into water. The cleanest waters in our land are far from pure. As a matter of fact pure water is so toxic and corrosive that it can destroy living tissue and erode stainless steel. Additionally pure water would taste absolutely terrible. The level of contaminants in clean drinking water may only be in the range of 10 to 50 ppm. Yet these contaminants, usually minerals and elements such as iron, calcium, and manganese (also referred to as hardness) add to the flavor of water and mellow its aggressive nature. The term “pure water” must be used very carefully. An extremely polluted and toxic waste stream may contain as little as 100 ppm of contaminants, which is 99.9999 percent pure. This is predominantly pure water with 0.0001 percent or less pollution. One hundred percent pure water with a resistivity of 18.3 MOhm can potentially be more dangerous to an aquatic environment than many industrial pollutants. Therefore, we must exercise caution when we use the term “pure water”. 43.2.2 Analysis of Water There are many parameters used to measure the qualities of water. Some of the most commonly used terms are defined below: pH. Defines the free hydrogen ion concentration in solution. It is a measure of free acidity or alkalinity with a scale that ranges from 0 to 14. This parameter is discussed in much greater detail later in the chapter. Total Dissolved Solids (TDS). As the name implies, this is a measure of all dissolved impurities. This is measured by evaporating all the sample liquid and measuring the weight of the deposits left behind. Conductivity or resistivity can also be used as an indirect measurement of TDS. Total Suspended Solids (TSS). A measure of the solids that can settle out from the sample. This is usually measured by mechanically filtering the sample and weighing the dried deposits left behind in the filter media. Chemical Oxygen Demand (COD). This is a measure of the oxidizable contents of the water or the total oxygen demand of the water. Biological Oxygen Demand (BOD). This is a measure of biological activity such as bacteria. Of course, there are many more parameters used to measure the quality of wastewater such as concentrations of specific elemental species like heavy metals or toxic organic species. Those listed above are some of the more commonly used terms that will be encountered. The most commonly measured and controlled parameter in wastewater effluent streams is pH. As stated above pH is the measure of free acidity or alkalinity of water. Living organisms are extremely sensitive to the pH of the water in which they thrive, therefore, the U.S. Environmental Protection Agency (EPA) very tightly restricts the pH of wastewaters that enter our nation’s lakes, rivers, and streams.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.3

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.3

43.2.3 pH pH is the measure of free acidity of water. The actual definition of pH is the inverse logarithm of free hydrogen ion concentration. pH = −log[H+] It is important to emphasize that pH is the measure of free acidity, as opposed to total acidity. Since the solubility of various compounds varies, pH quantitatively measures the active and free hydrogen ions in solution, as opposed to total. This is discussed further later in the chapter. The pH scale ranges from 0 to 14. Acids have a pH less than 7 while bases have a pH higher than 7 (Fig. 43.1). As stated earlier, water is known as the universal solvent in that it has the ability to disassociate the individual elements that make up a compound including itself. Water sitting in a glass weakly disassociates as follows: H2O → H+ + OH− As seen from the equation water disassociates into free hydrogen (H+) and free hydroxyl (OH−) ions. In a neutral solution there are an equal number of (H+) and (OH−) ions. An acid is a substance with an excess of (H+) ions while a base is a substance with an excess of (OH−) ions. Nearly any industrial process that utilizes water will have an effect on the pH of the water. Whether the process is etching a silica substrate or mopping the floor, the effluent stream generated will likely be out of the acceptable discharge range. As per the definition of pH, an acid is any aqueous liquid with an excess of (H+) ions, likewise a base is any material with an excess of (OH−) ions. It is the objective of the pH adjustment system to bring into equilibrium the number of H+ and OH− ions in solution. This is done by precisely adding a base to an acid, or an acid to a base, depending on the starting pH. Consider the following neutralization reaction HCl + H2O + NaOH → NaCl + 2H2O In this reaction hydrochloric acid (HCl) in water is neutralized with sodium hydroxide (NaOH), which yields two parts water and one part sodium chloride, also known as table salt. Most industrial processes are limited to a range of 6.0 to 9.0 pH units for effluent flows that are discharged to a POTW. The range is even tighter for effluents that are discharged to a lake, river, or stream. At first glance, a range of 6.0 to 9.0 may sound like a fairly broad range when in fact this represents only 0.00055 percent of the pH scale. How is this so? One must remember that the pH scale is a logarithmic scale. This means that to increment one unit on the scale, a change of 10:1 in acidity or alkalinity must occur. An acid with a pH of 5.0 is ten times more acidic than an acid with a pH of 6.0. An acid with a pH of 2.0 is 10,000 times more acidic than the same acid with a pH of 6.0.

The pH scale

0

1

2

Acids 3 4

5

6

7

8

9

12

13

14

um di So ide M ox 1 ydr dium h o s e M id 1 ox / 0. ydr ts h en ag s g er in an an le le c C oor fl

ap r So ate w a I Se Ω D M .3 r 18 ate w as ol C in ra e id ic Ac e ju ng ra O id ac ric lo c M h ri 1 oc lo 0. dr ch y H dro y H M 1 cid a FIGURE 43.1

Bases 10 11

The pH scale.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.4

WASTEWATER NEUTRALIZATION SYSTEMS FAB YIELD, OPERATIONS, AND FACILITIES

Acid-base titration curve 12 10 pH

43.4

8 6 4 2 10

20

30

40

50

ml acid FIGURE 43.2 Acid-Base titration curve showing the relationship between the pH of an alkaline solution as it is titrated with a solution of dilute HCl.

Likewise, a base with a pH of 9.0 is ten times more alkaline than a base with a pH of 8.0. The titration curve in Fig. 43.2 illustrates this well. Figure 43.2 depicts the affect of a strong acid on a strong base. Note that in this example we begin with an alkaline solution with a pH of 12. This solution is pH- adjusted with dilute hydrochloric acid (HCl). In this titration, approximately 20 ml of acid is added to drop the pH from 12 to 11. The amount of acid required to achieve another 1.0 pH unit drop is only 2 ml, and so on. The logarithmic nature of the pH scale is well illustrated in this example. The logarithmic nature of this curve is one of the issues that complicate the design of a pH control system. Control is not terribly difficult in the flatter portions of the curve at either a high or low pH. However, the curve is extremely steep, nearly vertical, within the normal discharge range of 6.0 < pH < 9.0. If the control system is not carefully designed, a great deal of process instability will occur in the near neutral range of the titration. An interesting anecdote: the author has observed hundreds, perhaps thousands of systems in operation over the last three decades. While onsite observing an existing acid neutralization system in operation the potential client conceded, “We must do something as the neighbors are complaining about too many dead fish in the river.” The final effluent monitor on the subject system was observed to be oscillating from 0 to 14 and back to 0 again at a period of about 1 min. The user explained that the system vendor told him that this was normal, as the average of 0 and 14 is 7, therefore, his discharge was neutral! Obviously an absurd assertion. The problem that plagued this system is common to many pH adjustment systems. The control system, along with many other aspects of the system failed to consider the nearly infinite process gain at or within the normal discharge range. Many systems can be observed to be stable at a high or low pH and run out of control in the target pH range. In such systems one can observe the pH rise slowly and predictably from 2.0 to 2.5 to 3.0 to 3.5, but, without any indication that there is a problem, the pH spikes through the effluent pH range and begins to settle at 10 or higher. The target pH range of 6.0 < pH < 9.0 was observed on the pH monitor for only a brief instance. This oscillation wastes chemicals (as acid must now be added to lower the pH overshoot), time, and degrades the effluent quality. The goal of the pH system designer must be to very accurately and efficiently raise or lower the pH of the effluent stream to a range that is acceptable for discharge. Additionally the system must confirm that the effluent stream is stable and not prone to change minutes after discharge. Every pH adjustment system designer must very carefully consider the following design issues: 1. Time: Sufficient time must be allowed for the measurement of pH, injection of chemicals, mixing of the treatment tank, and for the chemical reaction to take place. All these functions are time dependent. pH probes, the Achilles’ heel of any pH system are inherently slow and do not react quickly, particularly in solutions of weak electrolyte strength (typical of the semiconductor industry, as a lot of deionized (DI) water is present). Chemical injection must be controlled and methodical, as precision is paramount. Tank mixing and destratification of the tank is a function

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.5

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

2.

3. 4.

5.

43.5

of the mixing rate, obviously a time dependent function. Although some chemical reactions are quick, they require sufficient time to come to completion, especially if tank stratification is an issue. Chemical injection precision: Considering that in a given system a volume of 1 L of sodium hydroxide (NaOH) may be required to raise the pH of a captured batch of acid from 2.0 to 3.0 the same batch will need as little as .0001 L to raise the pH from 6.0 to 7.0. This places a big demand on the chemical injection system. Mixing: Since large tanks are always involved, tank mixing is a very important consideration. In most systems a mixing rate of 1.5 to 2.0 tank turns per minute is required. pH measurement: pH is a very difficult water quality to measure accurately and with repeatability. pH probes are prone to interference, coated or fouled easily, do not react very quickly, and do not hold a calibration for long. This leaves us with a device that must be installed in an optimum environment and must be very easy to access and service, as this is a high-maintenance item (e.g., once a week, the probe will have to be removed from service to be cleaned, inspected, and calibrated). Control system accuracy: The control system of any well-designed pH adjustment system must consider the nature of the pH titration curve and must consider the practical application of the equipment that is available for us to use in industry. A standard linear Proportional, Integral, Derivative (PID) algorithm or controller cannot be used, as pH is not a linear process. The control system must also consider the limitations of chemical metering equipment and accommodate the need for multiple chemical addition pumps/steps. For true pH control a device capable of accepting a titration curve input, and then adjusting based upon the current chemistry, is required.

43.3 APPLICATION EVALUATION Prior to commencing the design of any pH adjustment system, the process engineer must carefully consider all the critical application information with the knowledge of the nature of the chemistry of pH. The process engineer must be equipped with detailed flow information and chemistry data. Additionally, we must know the effluent discharge criteria, installation and logistical limitations, installation environment, chemicals available for the neutralization process, and the like. 43.3.1 Flow Profiling A detailed flow profile is critical if not imperative. At an absolute minimum, the design engineer must know the peak flow volume (not rate) in any 60-min period of the day, followed by the total daily flow. Often this information is difficult to ascertain; however, it is imperative. If this information is not available, then a reasonable estimate must be compiled, upon which the system is designed and will be limited. The system design, in most cases, will be based upon the highest flow volume in any 60-min period. A daily flow estimate must also be available, as well as the instantaneous peak flow into the system. In a theoretical system we may have a daily flow of 50,000 gpd (gallons per day) with all the flow occurring in an 8-h period. A further analysis of the flow profile may reveal that the flow peaks during the midafternoon hours with a peak flow volume of 10,000 gph (gallons per hour) from 1 pm to 2 pm. Since the point sources in this theoretical application are from many different locations throughout the plant, a collection system is installed below grade, thereby allowing all the drains to flow by gravity to a common point, from which the wastewater is pumped to our pH adjustment system. Note that contrary to the custom of the industry, we will avoid using the term pH neutralization system since neutralization of the wastewater stream is not truly our goal and a neutral pH (pH = 7.0 +/− 0.0) can be nearly impossible to establish and maintain. If in a typical application we are adjusting to a pH range of 6.0 < pH < 9.0, then we are at or near neutral, but we are not truly neutral. Therefore, we will more accurately refer to the system as a pH adjustment system. With a peak flow of 10,000 gph we decide to install a collection transfer system (CTS) with a volume of 1000 gal and a duplex pump capacity of 200 gpm each. This gives us nearly 150 percent capacity per pump.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.6

WASTEWATER NEUTRALIZATION SYSTEMS 43.6

FAB YIELD, OPERATIONS, AND FACILITIES

Based upon this we have established our flow profile as follows: • Total daily flow = 50,000 gpd • Peak hourly flow = 10,000 gph • Peak flow rate = 200 gpm The critical factor above is the peak hourly flow of 10,000 gph, which is an average flow of 167 gpm; this will become our system design flow. It is advisable to design for 125 percent capacity, and not for 100 percent capacity, always leaving reserve capacity for data variability and unknowns. Therefore, we will actually design a system that is capable of treating at least 210 gpm, yet we will only advertise a capacity of 167 gpm. 43.3.2 Chemistry The chemical characteristics of the wastewater stream are much more difficult to determine quantitatively than flow. A general qualitative description is about the best that we can normally ask for. In some rare cases we can quantify this information; however, in most applications the information simply is not available or changes too much to accurately quantify. Nonetheless, some basis of design must be established. In the best-case scenario, we would have the following information to begin with: • • • •

Average 60 min total acidity/alkalinity (expressed in mg/L) Peak total acidity/alkalinity (in either molar concentration of mg/L) Source of acids and bases Volume of dilution waters, if any

This information is very rarely available; therefore we must at least establish design limits. These design limits help us to evaluate the peak hourly acid/base chemical demand (flow rates) and temperature rises (neutralization reactions are exothermic,1 and in some cases, significant heat can be liberated). Additionally, we need to know the peak influent acid/base concentration in order to determine the overall system architecture (batch versus continuous flow and number of stages). We also need to know whether we are dealing with a strong acid/base chemistry or weak acid/base chemistry. The semiconductor industry is historically strong acid/strong base. Strong acids and bases are those chemicals that totally disassociate in water. Mineral acids such as hydrochloric (HCl), sulfuric (H2SO4), nitric (HNO3), and to a lesser degree hydrofluoric (HF) are considered to be strong acids as they totally disassociate in water. Very low volumes of strong acids will have a dramatic effect on pH; additionally, strong acids will react very quickly during the neutralization process. Weak acids, such as acetic, citric, phosphoric, and a variety of organic acids do not totally disassociate in water and generally do not lower the pH nearly as far. A weak acid, for example, with a Acid base titration curve

pH

14.0

7.0

0.0

0

5

10

15

20

25

ml of NaOH FIGURE 43.3

Strong acid and strong base neutralization.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.7

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.7

pH

Acid-base titration curve molar concentration of 1 mol/L may only lower the 14.0 pH of water to 4.5, while a strong acid with a molar concentration of 0.1 mol/L (one tenth the concentration) will drive the pH of water to as low as 1.0! The weak acid at a pH of 4.5 will require 10 times 7.0 the volume of base material to neutralize and will react much slower, yet the strong acid at a much lower acidity has a much higher impact on the pH of water. Therefore, pH alone cannot be used to 0.0 directly determine the amount of neutralizing 0 10 20 30 40 chemical that is required. ml of NaOH added In some cases the weak acid can be easier to pH adjust because the titration curve is flatter, yielding FIGURE 43.4 Weak acid and weak base neutralsubstantially lower process gains,* but more time ization. may be required due to longer reaction times. Consider the example (Fig. 43.3) of a strong acid/strong base neutralization. Take note of the amount of reagent needed to raise the pH at lower values versus the amount needed at or near a pH of 7.0. This curve displays that the process gain is constantly changing. The control algorithm response at a pH of 2.0 is 10 times greater than at a pH of 3.0 and 10,000 greater as compared to the output at a pH of 6.0. Effective control with a single gain PID controller is not possible with most titration curves. The controller for this curve needs to have a logarithmic response. Now consider the example (Fig. 43.4) of a weak acid/weak base neutralization. The curve shown at the right is representative of an effluent stream that buffers in the mid acid ranges (i.e., 3.0−5.0 pH). This is a stream that can no longer be characterized mathematically in an easy way. This is typical of a weak acid/weak base neutralization. These reactions tend to be slower, sometimes much slower than strong acid/base neutralization; however, they can be much easier to control due to lower process gains.

43.4 ARCHITECTURE OF STANDARD pH ADJUSTMENT SYSTEMS Three basic system architectures that are used in industry are as follows: • Inline • Continuous flow through (also referred to as continuous batch) • Batch Inline systems are all doomed to fail and should never be considered as an option. A description of this system architecture is provided; however it is recommended that this be eliminated from any consideration. Continuous flow through or continuous batch systems are the mainstay of the industry and can be used in most, but not all, applications in the semiconductor industry. Batch systems can be used for any application regardless of the flow or influent chemistry. Batch systems are larger and more complicated than continuous systems, however, this is the safest design in that there are no limitations on the load handling capability. High flows of clean dilution water and a minimal amount of acidic and alkaline wastes characterize most applications in the semiconductor industry. The influent tends to be within a range of

* Process gain refers to output change percentage vs. input. For example, in a strong acid/strong base neutralization (typical of those found in the semiconductor industry), an addition of 2 ml of 50 percent NaOH may effect a pH change of 3 units, whereas in a weak acid neutralization the same 2 ml may effect a pH change of only 0.5 units. The strong acid neutralization yields a very high process gain while the weak acid neutralization yields a much lower process gain. Lower process gains put less of a demand on control system and chemical addition system accuracy. High process gains require very precise control algorithms with a very fast response. Additionally, very precise chemical addition is required with high process gain.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.8

WASTEWATER NEUTRALIZATION SYSTEMS 43.8

FAB YIELD, OPERATIONS, AND FACILITIES

2.0 < pH <12.0 and the acids and bases are all strong acids/strong bases. This stream is an excellent candidate for treatment with a continuous flow through system. If there are periodic discharges of highly concentrated acids or bases driving the influent pH out of the range of 2.0 < pH <12.0, then a batching system needs to be considered. If the effluent stream can, even for a brief period, exceed an acid/base concentration of 0.05 mol/L, then the use of a batching system is an imperative as a complete isolation of influent and effluent must be established. A detailed description of each of the three architectures follows. It is important to note that the descriptions that follow are for the basic system as it is most commonly described in texts and implemented in industry. However, these descriptions do not describe or depict the most optimum design. Design optimization will be discussed after the basic system architectures are established. 43.4.1 Continuous Inline pH Adjustment Continuous inline pH adjustment systems (Fig. 43.5) are characterized by their simplicity, low cost, ease of implementation, and chronic unreliability. Most “cookbook” solutions covering the topic of inline treatment often fail to warn of the hazards of this treatment scenario. In this section we will discuss the various implementations and the hazards associated with this technique. In the simplest form, inline treatment consists of a pH probe and controller, a chemical injection point, and a static mixer. Unidirectional or bidirectional systems can be implemented, but this type of system is usually appropriate for a unidirectional system only. Figure 43.5 is an extremely simple pH adjustment system that can function well if properly applied. However, practical applications of this system are quite limited. For effluent streams that are of relatively constant flow and water chemistry, this system can be tuned to perform adequately. Load changes, even of small magnitude, are not tolerated well and will most likely yield a pH contravention at the discharge. Flow compensation is often implemented with inline systems by installing a flow sensor in the treatment line to measure the effluent flow. The pH controller would have to be equipped with a flow-sensor input to adjust metering pump output as the flow changes. With this system design it is best to hold the flow constant with little or no flow changes, despite the availability of flow compensation. The limitations of this system are a result of inadequate contact time to allow the chemical reaction to come to completion. Additionally the pH probe, an inherently slow device, will not react quickly enough to allow for an accurate response. Therefore this system should be arranged such that there is a maximum fluid travel time between the static mixer and the pH probe. A minimum of 30 to 60 s is required and 2 to 3 min is desirable. A common problem with inline (and many other techniques as well) is control-response oscillation. Since a large tank volume is not available to dampen these oscillations, the effluent discharge will often oscillate wildly (i.e., ±2 pH units).

Metering pump Chemical injection line pH probe and Controller 50% NaOH

Influent pH 5.0 to 6.0 constant

FIGURE 43.5

100 ft min

AIC

Static mixer AE Chemical injection “T”

2−3 ft/s

Effluent pH 6.0 to 8.0 constant flow

pH 0−14

Continuous inline pH adjustment.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.9

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.9

A simple linear PID feedback controller operating with the proportional (P) element only will suffice to control this system. Since the primary limitations are beyond the control of even the most sophisticated controller there is no need to invest heavily in a sophisticated controller. This type of system is more likely to function successfully when treating alkaline waste streams with CO2. Carbon dioxide will self-buffer at a pH of 7.0 (±0.4) pH units, thereby eliminating the need for sophisticated control. The system depicted above utilizes a “feed back” control scheme that is typical of most of the systems that we will be discussing. In this control scheme we “feed back” to the metering pump the amount of caustic to add to compensate for the control error currently measured. This type of pH adjustment system can also be used in a “feed forward” control scheme and is often referred to as an anticipation system. In a “feed forward” setup the chemical addition would be added downstream of the pH probe. The system is then configured to “guess” the amount of chemical addition that is required. This can only be used as a pretreatment stage ahead of a more sophisticated “feed back” system and is rarely found in industry. Rarely in industry is an application found that can be handled by a continuous inline system. A continuous inline system should only be considered when the logistics of a tank installation render other scenarios impossible. An inline system has potential only if the flow rate and chemistry of the influent stream changes little to none. Otherwise, it is advisable to avoid this treatment technique at all costs. Consider this system architecture only if the installation of a tank is impossible and space is extremely limited or if the influent flow is within 1.5 pH units of the target range and the chemistry is constant. 43.4.2 Continuous Batch pH Adjustment Probably the most commonly implemented pH adjustment system, continuous batch systems (Fig. 43.6), offer high-system throughputs with minimal component count and simple control systems. By no means a treatment panacea, continuous batch systems or derivatives thereof, can handle the majority of the waste streams that we encounter in the semiconductor industry. There are many ways to design continuous batch pH adjustment systems and we will discuss several. Regardless of the final implementation they are all essentially the same. Some may be singlestage systems while others may be two-, three-, or even four-stage systems; they still operate on the same basic principles. The first system that we will examine will be the standard “cook book” Acid metering pump

Caustic metering pump

Acid drum Caustic drum Untreated influent Mixer

pH controller

pH

Treated effluent

Continuous batch treatment tank

FIGURE 43.6

Continuous batch pH adjustment.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.10

WASTEWATER NEUTRALIZATION SYSTEMS 43.10

FAB YIELD, OPERATIONS, AND FACILITIES

approach to a single-stage continuous batch pH adjustment system. The full description for the system shown in Fig. 43.6 is a single-stage bidirectional continuous batch pH adjustment system. The system depicted in Fig. 43.6 shows a batch tank that is always full. Immersed in this tank are a mixer, acid and caustic injection valves, and a pH probe. Influent flow entering the tank displaces an equal volume through the discharge overflow port. This system obviously requires a gravity flow to drain. The limitations of this system should become immediately obvious when considering the fact that the tank is always full and the discharge flow must equal the influent flow. The primary disadvantage of this system is that discharge flow will occur regardless of effluent pH. Load changes of significant magnitude may cause the effluent pH to deviate from the control band limits. The control concept behind this treatment technique is very much misunderstood in industry. Although this style of treatment can be found in countless texts, none sufficiently describe the dynamics of the system. The adjustment of influent pH in this system occurs as the incoming flow mixes and reacts with the tank contents. The purpose of the control system is to maintain the pH of the buffer fluid within the batch tank. The purpose of the control system is not to directly treat the incoming flow. If the control system intent were to treat the influent flow, then we would assemble an inline pH system followed by a batching tank. This system, however, relies on a large buffer fluid within the batch tank to treat the influent flow. With this fact in mind, we are able to properly construct this system. The physical layout of the components within this system is critically important to the operational success of this system. The treatment tank size must be large enough to ensure a minimum of 10 min of retention time at the highest flow expected. This means that we need a working volume of at least 300 gal for a 30 gpm peak. This, of course, assumes that the influent pH is within 2.0 pH units of the expected discharge pH. The treatment tank dimensions are as important as the tank volume. Contrary to popular belief, a symmetrical square or cylindrical tank is not desirable. Although it may be true that it is easier to provide good mixing in a symmetrical or cylindrical tank, these tanks do not provide the flow or pH profiles that we require. Since we know that the tank will be dynamic, with constantly changing characteristics whenever influent flow exists, we can recognize that some instability will exist as we are treating a waste stream. It is, of course, desirable to maintain a stable discharge as opposed to one that is unstable. Therefore, a homogeneous tank will have rather constant characteristics throughout a given cross section, and we would expect to see an equal amount of instability at the influent and effluent ports. By carefully configuring the tank layout, we can establish a desirable gradient within the tank and isolate influent instability from effluent stability. The tank will be long, narrow, and shallow. This may not make the best use of plant floor space, but it will offer superior performance. The tank dimensions should have nearly equal tank heights and widths, and a length of 1.5 to 2.5 times greater than the width (Fig. 43.7). Although good mixing is very important, we will locate the mixer closer to the influent port than the discharge port. Additionally, we will locate the reagent injection ports near the influent port at a point where the tank agitation is the most aggressive. The pH probe will be located at the opposite end of the tank from the influent port and will be very near the discharge port.

Caustic pH probe and transmitter Influent port

W=H

Effluent port

Acid L=W×2

FIGURE 43.7 This mechanical layout of a single stage bidirectional continuous batch pH Adjustment System depicts an optimum system configuration. Note the tank dimensional ratios as well as the location of the Mixer with respect to the other major system components.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.11

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS Untreated influent

Acid metering pump

43.11

Caustic metering pump

Influent equalization/ collection tank Acid drum

Caustic drum Mixer

pH controller

pH

FIGURE 43.8

Treated effluent

Single-stage continuous flow through pH adjustment system.

After all, it is the effluent pH that we are most interested in. The pH probe will not be at the center of the tank or near a tank wall, it will be very near the discharge port and at the same elevation. With a system that is properly designed, one should expect to be able to handle relatively large flows with influent pH deviations as high as +/− 2.0 pH units. Actual throughput is a function of many variables including the titration curve; therefore, accurately predicting the performance is nearly impossible without knowing all the influent characteristics. This system architecture is further enhanced through the use of additional stages. A passive influent equalization stage is an inexpensive way to improve system performance when the influent is characterized by sudden changes in flow or chemistry. An influent equalization stage, such as the one depicted in Fig. 43.8, significantly enhances the utility of the system in that sudden load changes in the form of flow or chemistry changes can be easily absorbed by the equalization system without seriously impacting the performance of the system. The size of the load changes is limited by the size of the influent equalization tank. A 60-min tank volume* is normally recommended. The ability to absorb load changes is obviously a function of tank volume, therefore, bigger is better. Large bulk storage tanks are generally inexpensive, so a large tank does not necessarily break the budget, but floor space may be an issue. This design is further enhanced via the use of an influent control valve between the influent equalization tank and the treatment tank. This valve can be automatically closed by the control system in the event that an effluent instability is detected or a contravention is imminent. A passive effluent equalization system is an inexpensive method to improve effluent quality, particularly for larger systems that may not quite have the treatment tank volumes that are required for the optimum tank architecture. This stage essentially stabilizes or filters fluctuations from the primary or final treatment stage. The passive influent and effluent equalization stages shown in Figs. 43.8 and 43.9 are, as the name indicates, passive in that no active treatment takes place. Continuous flow-through systems are often supplied as two- or three-stage active treatment either with or without equalization systems. Typically multistage active treatment systems do not utilize equalization systems. The advantage of multistage active treatment is that a wider range of influent pH can be handled. The downside is expense and complexity. In the two-stage continuous flow-through diagram depicted in Fig. 43.9, the recommended volume for tank T1 is flow × 10 min (with flow expressed in gpm). The minimum recommended volume for T2 is T1 × 1.5. Therefore, at a design flow of 170 gpm the volume of T1 should be 1700 gal and the minimum volume for T2 is 2550 gal. * A 60-min volume refers to average 60-min flow volume. A 100-gpm average flow would dictate the use of a 6000 gallon, or larger, influent equalization tank.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.12

WASTEWATER NEUTRALIZATION SYSTEMS 43.12

FAB YIELD, OPERATIONS, AND FACILITIES Acid metering pump

Caustic metering pump

Acid drum Caustic drum pH controller

Mixer

Untreated influent

Treated effluent

pH

Continuous batch treatment tank

FIGURE 43.9

Effluent equalization/ tank

Single-stage continuous flow-through pH adjustment system.

The two-stage system depicted in Fig. 43.10 is a very common system configuration. With typical semiconductor fab-type effluent flows this system should handle an influent pH range of 3.5 < pH < 10.5. The use of an influent equalization system would allow for brief spikes to 0.5 pH units below and above this range. This first stage of this system is generally referred to as a coarse adjust stage while the second stage is the fine tune stage. To properly implement this system design the second stage is roughly 1.5 to 2 times the volume of the first stage. Every system will have a natural oscillation frequency that is primarily a function of the tank volume. These oscillations are generally undesirable and can be filtered and almost eliminated by the use of subsequent stages that are substantially larger in volume than the preceding stage. If equal tank volumes are used, then it is possible to setup a condition of positive interference whereby the subsequent stages amplify, or exacerbate the oscillations. It is important to note that this drawing shows pH probe and reagent injection points installed in conflict with the methods that we would normally recommend. This is done in an effort to simplify

Acid metering pumps

Caustic metering pumps

Acid drum Untreated influent

Caustic drum Mixer pH controller

Mixer

pH controller

pH

Treatment tank T1

FIGURE 43.10

pH

Treated effluent

Treatment tank T2

Two-stage continuous flow through pH adjustment system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.13

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.13

the process diagram for the purpose of this discussion. Component “optimization” is discussed in several system descriptions that follow, therefore, we have elected to skip it here. The primary limitation of a continuous flow-through system is the fact that discharge occurs regardless of the discharge pH. It is possible, if not common, to find systems that are not capable of handling influent load changes. The result is an effluent contravention, since there is no way to shutdown discharge flow. 43.4.3 Batch pH Adjustment System The systems that we have discussed so far are all continuous batch type systems that allow for uninterrupted flow of the incoming waste stream. Continuous pH adjustment with no interruptions in the influent stream is obviously desirable or even mandatory for most industrial applications. However, if the characteristics of the stream are such that the pH system temporarily falls behind, then the effluent stream will have to be shutoff or a contravention will result. There are many industrial applications that require the treatment of fairly concentrated acidic and alkaline waste streams (e.g., 2.5 < pH < 11.5). Many effluent streams are also characterized by periodic spikes in alkalinity or acidity. Both of these conditions can easily overwhelm a continuous batch or a hybrid batch system. As will be discussed in Sec. 43.5, pH adjustment is a very difficult task due to the nature of a typical titration curve. For streams that are subjected to sudden load changes or periodic spikes, we must be in a position to shut off the discharge flow and provide sufficient time for treatment. Additionally, for any application that may have a relatively concentrated discharge of acid or alkaline material (i.e., concentration >0.1 mol/L) of significant volume (i.e., >1 percent of the total flow), then a batch system is an imperative. A batch pH system accepts various batch sizes up to the size of the tank. Once the treatment tank is full the influent must be shut off and treatment begins. When the tank contents have been treated the tank is drained and the process is repeated. Since industrial discharges are not batch in nature, an influent equalization system is always used so as to allow continuous uninterrupted flow of factory effluent to the treatment system. The system shown in Fig. 43.11 is a standard batch pH adjustment system. This is a two-stage batching system consisting of an equalization tank and a batch treatment tank. The equalization system is used for the purpose of homogenizing influent flow and to provide a reservoir for accepting waste when the second stage cannot. The second stage of the system is a batch treatment stage that is designed to accept a fixed batch size from the equalization system and to treat that volume as a batch. An obvious disadvantage of a single-stage batch system is that the influent flow must stop when the treatment tank is full. The implementation of an equalization stage allows for a continuous influent flow. In a typical cycle the influent equalization will transfer a batch of a fixed volume into an empty batch treatment tank. Once full (~90 percent full) the transfer will halt and the treatment cycle will commence. With the mixer running, concentrated chemicals are added as required to bring the tank contents into the acceptable discharge range. At this point the automated discharge valve opens, thereby draining the tank. Once the tank is empty (~10 percent full) the discharge valve closes and the cycle repeats. Note that an optional effluent monitoring system is shown. The local authorities often require continuous monitoring of the discharge pH and flow, along with maintaining a log of the total daily flow. Therefore, the effluent recording system shown is typically installed on most systems. To simplify the illustrations within this paper many of the systems are depicted without the effluent monitoring system. Batching systems are by far the safest type of treatment system to implement because the system design ensures that the effluent stream will meet specified criteria before going to the drain. A batching system, however, can bottleneck a plant process by restricting the flow. For this purpose, it is essential that we carefully evaluate the discharge flow rates, the titration curve, and supply a sufficiently large equalization tank. An alternative to an equalization system is a second batching system configured in parallel. This is referred to as a duplex batching system, which offers double the throughput and redundancy.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

43.14 LE

FIGURE 43.11

Mixer

Batch treatment tank

Batch pH adjustment system with passive influent equalization system.

Influent transfer pump (Duplex pumps are commonly used)

Caustic drum

Caustic metering pump

pH

pH controller

Automated discharge valve FE pH probe Flow sensor

pH

Final effluent recorder (optional)

Treated effluent to drain

21:24

Acid drum

Multipoint Acid lebel metering pump

04/04/2005

Influent equalization/ collection tank

Untreated influent

Geng(SMH)_CH43.qxd Page 43.14

WASTEWATER NEUTRALIZATION SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.15

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.15

43.5 SYSTEM OPTIMIZATION 43.5.1 Optimization Fundamentals In many of our discussions, references have been made to the inadequacies of typical “cookbook” approaches to pH adjustment. There are four areas in which the typical system is deficient—tank mixing, pH probe installation, chemical injection, and the control algorithms. Among the four major deficiencies, tank mixing is the least of our concerns because it is an easy objective to achieve properly. The traditional approach of putting a large mixer in a cylindrical tank is not necessarily the best approach in all applications. In a batching system, standard tank design and mixing mounting is utilized. In these applications we solicit the advice of the experts—the mixer manufacturers. We inform them as to the tank volume required and any space limitations and let them do the rest. The mixer manufactures have excellent application engineers on staff who offer good advice. Mixer performance is a function of many parameters, simply sticking a mixer in a tank in not adequate. The problem with applying typical tank mixer technology comes into play when dealing with “flow-through” systems such as continuous batch and multistage continuous batch systems. In these systems we do not want a well-mixed homogeneous tank. The reasons for this are discussed in the sections covering Mixer continuous batch and hybrid batch pH adjustment systems. pH probe Briefly, in these systems we are looking for a well-defined profile from inlet to outlet. The inlet is expected to be well agitated with continuously changing characteristics. The outlet, however, is expected to be much more stable. Many factors are considered when sizing tanks and placing mixers in these applications. pH probes are, undeniably, the most critical and the weakest point of most pH adjustment systems. One of the most common ways to install a pH probe is to immerse it in a tank through the top (Fig 43.12). In the case of a batching system the probe must be installed near the bottom of the tank so that it will remain wet at all times, even when the Treatment tank tank drains. In the case of a flow-through system the probe FIGURE 43.12 pH probe location. is usually installed in an arbitrary location (although there should be much thought in deciding the proper location). In any case, the probe, which is a high service item, must be withdrawn frequently for service. Rarely is there a tank installation that allows for convenient access to the pH probe. Access to the top of the tank is difficult and there is a long, unwieldy probe assembly to deal with. There is an ungainly conduit to tangle with and a long wand to wrestle with once the probe is removed. Most people would agree that removing a pH probe from a tank is a difficult job. Installing a probe deep within a tank is a major maintenance issue. Aside from the maintenance issue, there is a significant process concern with installing a pH probe within a tank. Most pH probes require a well-defined flow across the face of the probe to attain optimum probe performance. When immersed in a tank the flow around the face of the probe cannot be controlled and may be random. When installed inline, such as in a recirculation loop, the flow can be directed across the face, as is required for many probe designs. Additionally, when a probe is installed inline (Fig. 43.13) we can control the pressure and flow velocity, thereby optimizing the installation environment. Experience has shown that in an optimized environment the pH probe performance far exceeds that which can be attained within a tank. Installing a recirculation loop for the pH probe is usually the first step in pH system optimization. Standard pH adjustment system design does not just place pH probes directly within tanks, it also places the chemical injection points directly into tanks. Typically all pH adjustment systems will have at least one, and usually two chemical injection pumps. Normally the chemicals are injected directly into the tank where they fall to the surface of liquid and are eventually mixed in. This is a

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.16

WASTEWATER NEUTRALIZATION SYSTEMS 43.16

FAB YIELD, OPERATIONS, AND FACILITIES

very inefficient mechanism to introduce chemicals into solution. If a clear beaker is filled with clean water and one drop of 50 percent sodium hydroxpH probe ide (NaOH) is placed into the water, the drop will remain intact and fall to the bottom of the beaker, indicating that more than just a little effort is required to mix the chemical into solution. Concentrated reagents do not readily mix into Flow solution without some direct agitation. Although most systems will have adequate agitation, there is Recirculation line a significant amount of stratification within the tank for some time after the chemical injection FIGURE 43.13 Inline pH probe shown installed in a stops. In conventional systems this leads to a perirecirculation/sample line. Note that the flow travels across the face of the probe. Probe can be withdrawn in od of time where the measured pH of the tank is any number of ways. The most common are 1/4 turn quite unstable and there may even be oscillations twist lock, threaded, and wet tap. that are uncontrollable. The author has demonstrated that if the chemical injection takes place in a high velocity recirculation stream, a substantial dilution of the reagent takes place before the chemicals enter the tank. This significantly decreases tank stratification and enhances the performance of the system. Therefore, since a recirculation loop exists for the pH probe, we can use the same recirculation loop for chemical injection. So far, we have established that installing a pH probe directly into a treatment tank does not make best use of the probe. Additionally, we have established that conventional chemical injection techniques are also inadequate. In our “optimized” pH adjustment system we have, at this point, installed the pH probe inline in a recirculation loop, and placed the chemical injection points inline in the loop as well. Note that in the Fig. 43.14, the loop is designed to provide a relatively slow fluid velocity for the pH probe and a relatively fast velocity for the chemical injection points. As discussed previously most pH probes perform best when there is a flow velocity of 2 to 3 ft/s across the face. The dilution of the concentrated reagents occurs best in a high-velocity stream. Since 6 to 8 ft/s is the design limit of most thermoplastic piping systems, we use this as our target flow. The recirculation loop now provides two very useful functions. One is to provide a sample flow for the pH probe and the other is to provide an optimum environment for the chemical injection.

Treated effluent

Acid Caustic

Influent

Mixer

Recirc/ discharge valve A

pH probe and controller AIC AE

Recirculation/ discharge pump(s)

Flow velocity 2−3 ft/s

Flow Velocity 6−8 ft/s

FIGURE 43.14

Optimized batch treatment tank.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

21:24

Page 43.17

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.17

As with the pH probe, installing chemical injection points in the recirculation line improves the serviceability of the associated components. So far we have optimized the system design by installing a recirculation loop to provide a controlled environment for the pH probe and the chemical injection points. Probably an even more important consideration to the installation environments of the probe and injection points is the control algorithm. The response of pH to chemical injection is not a linear process. Most processes that are controlled in industry are linear (e.g., flow, temperature, and pressure) and respond well to simple PID control loops. In the simplest of applications, pH is a logarithmic response to control input (Fig. 43.15). In most applications, however, there is no mathematical equation to define the response of pH to the control input. Conventional controllers calculate a process output by first determining the process error. The process error is defined by the difference between the user defined set point and the measured process value. This difference, called the process error is then multiplied by a factor that is usually referred to as the proportional gain. The result is an output value. PID controllers will further combine this number with an integral term and a derivative term. Yk = [(PV − SV) × K] + b where Yk = process output PV = current measured process variable SV = set point value K = process gain or controller gain b = bias value This is a typical linear process control algorithm for the proportional term of a PID controller. The integral term will bias the output based on the amount of process error with respect to time. The derivative term will look at the rate of change and adjust the output based on the rate of change. In pH applications the use of an integral term is useful and is discussed further. The use of a derivative term is not practical because the rate of change can be, and usually is, caused by factors such as tank level, stratification, water chemistry, and probe delays. As can be seen from the curves (Fig. 43.16), the controller must be able to use many different process gains. The first titration curve clearly shows that at lower pH values a low process gain is

Acid-base titration curve 14.0

Acid-base titration curve 14.0

7.0 pH

pH

Geng(SMH)_CH43.qxd

7.0

0.0 0

5

10 15 20 ml of NaOH added

25

FIGURE 43.15 Take note of the amount of reagent needed to raise the pH at lower values versus the amount needed at or near a pH of 7.0. This curve displays that the process gain is constantly changing. The control algorithm response at a pH of 2.0 is 10 times greater than at a pH of 3.0 and 10,000 greater as compared to the output at a pH of 6.0. Effective control with a single gain PID controller is not possible with most titration curves. The controller for this curve needs to have a logarithmic response.

0.0

0

10

20

30

40

ml of NaOH added FIGURE 43.16 The curve shown at the right is representative of an effluent stream that buffers in the mid-acid ranges (i.e., 3.0 to 5.0 pH). This is a stream that can no longer be characterized mathematically in an easy way. For true pH control the system controller should have the ability to be “taught” to respond to the anticipated titration curve, by programming a response curve into the controller.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.18

WASTEWATER NEUTRALIZATION SYSTEMS FAB YIELD, OPERATIONS, AND FACILITIES

required since the change in pH is very slow with respect to the pump output. However, at the near neutral range (6.0 < pH < 8.0), the 100% (3.0,90%) process gain must be very high. For true pH control a control algorithm must (4.0,75%) be provided that allows an operator to program titration curves into the controller. Typically two independent control bands are provided— one for the acid side and the other for the base/alkaline side. These bands then provide the process engineer with several segments per band in which (5.0,25%) a fixed control output can be specified for a given segment on the band. In the illustration (6.0,10%) (Fig. 43.17), six segments are programmed 0% into the controller, each with a different pro1 2 3 4 5 6 7 portional gain. As you can see at a pH of 2.0 FIGURE 43.17 The curve depicted on the left is a typithe metering pump output will be 100 percent, cal control curve that is programmed into the control sysand at a pH of 3.0 the metering pump output is tem at the time of start up. This is programmed by defining 90 percent, as specified by the tuning paramea pH point and an output. The operator is allowed to break ters. At a pH of 2.5 the output will be 95 perthe curve up into 6 or 7 segments and define a pH and outcent as calculated by the control algorithm. put at each point. The curve shown here is for the low band that controls the caustic pump. There is an identical but As you can clearly see, a curve of virtually independent setup for the high band (acid pump). any shape can be programmed into the controller. The programming of the curve is the basis upon which the control algorithm calculates an output for a metering pump. Since there are many variations to typical industrial streams there must be a way by which the controller can adjust for influent variations. This is done with several other programmable variables. As with a typical linear PID controller an integral output is also calculated, which is used to bias the output. This output examines the process error and integrates this error with respect to time. The longer a given error exists the higher the output bias. This bias is then added to the output that was calculated from the programmed titration curve. Control output vs. pH

(2.0,100%)

Metering pump output %

43.18

YI = N ∫ ( PV − SV) dt where YI = integral output N = integral time constant PV = current measured process variable SV = set point value The output can also be varied based upon the rate of change of pH. Although not a true derivative output, this function is analogous to the derivative function of a PID controller. Since an excessive rate of change of pH is rarely due to excessively high process output, a true derivative output is of no use. Instead, we must consider what causes this change. Although the actual causes are beyond the scope of this discussion, we can summarize by saying that once an excessive rate of change is detected, all reagent addition must halt immediately. Once we have detected an unstable condition within a treatment tank, it is safe to assume that we do not really know what the pH of the tank is. Until the tank destratifies, the chemical reaction slows down, and the pH probe responds, we cannot accurately measure the pH. Therefore, we halt all chemical addition once the rate of change exceeds a threshold limit. At this time we wait for a specified period of time (usually 1 min) after the tank meets the definition for stability before allowing chemical addition to resume. Once it does resume, the rate of addition is slowly ramped up to the normal output. This is to ensure that we do not begin a period of wild oscillations. Digressing for a moment to the pH titration curves one can see that there must be very precise control over the chemical addition devices. Turndown ratios of 2000:1 are often required. Most

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

21:24

Page 43.19

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.19

metering pumps can provide a turndown ratio of about 150:1. Control valves can provide turndown ratios of 10:1. This is the reason why control valves are rarely used for chemical addition. Some applications do lend themselves to chemical addition by control valves, but these are rare. One must ask, at this time, how do we attain our chemical addition flow rates with metering pumps if a turndown ratio of 2000:1 is required? The answer is that we usually do not. If there is sufficient time the metering pumps ramp up to maximum output and remain there for quite sometime before a decrease in output is realized. Undersizing the metering pump in this manner is required because precise control at or near our set point is imperative. How then do we handle highly acidic or alkaline discharges in a reasonable amount of time? The answer is with bulk assist reagent pumps. These are pumps that are many times larger than the metering pumps and are used to raise or lower the pH at the extreme ends of the band. The graph in Fig. 43.18 depicts an output for a bulk assist feed pump. Since this larger pump does not possess the accuracy for fine control at or near our set point it must be shutoff far in advance of reaching this point. By this point, however, the output of the smaller metering pump should be sufficient to bring the pH up in a timely manner. The bulk pump allows us to rapidly raise the pH at very low values to a point where the smaller pump can take over the chemical addition. The curves shown in Fig. 43.18 depict the low band or the caustic addition control outputs for acidic conditions. Identical, yet independent controls exist for the high band or the acid addition (see curve in Fig. 43.19). In addition to the acid and caustic controls the system controller also examines the pH for discharge consideration. Figure 43.19 depicts the acid and caustic control outputs charted on the same graph. Notice that the shapes of the acid and caustic output curves are identical. This is done to add symmetry to the chart. In reality the shape of the two curves can be, and usually is, radically different. Notice something new on the chart in Fig. 43.19. Bands called discharge window and treatment window have been added. The treatment window represents the set points to which the control system algorithms attempt to adjust the pH. The discharge window is the acceptable range in which discharge may occur. The treatment window is always narrower than the discharge window. This is done so that the actual discharge pH is well within range before the discharge commences. If we began to discharge at the edge of our acceptable limit, then the slightest drift in pH

(2.0,100%) 100% (3.0,90%) (4.0,75%)

Metering pump output %

Geng(SMH)_CH43.qxd

(5.0,25%) Bulk assist output

(6.0,10%)

0% 1

2

FIGURE 43.18

3

4

5

6

7

Control output versus pH with bulk assist.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.20

WASTEWATER NEUTRALIZATION SYSTEMS FAB YIELD, OPERATIONS, AND FACILITIES

Pump output %

100%

0% 0.0

100%

Discharge window Caustic metering pump output

Treatment window

Acid metering pump output

Acid bulk assist pump output

Caustic bulk assist pump output

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

Pump output %

43.20

0% 10.0 11.0 12.0 13.0 14.0

pH

FIGURE 43.19

Control window and output graphs.

could cause a contravention or cause discharge to halt. Therefore, bringing the fluid pH well with in the acceptable discharge range ensures that the discharge pH will remain in range throughout the entire purge cycle. A discharge qualification algorithm must also be employed. Simply measuring the pH of the treatment tank and discharging whenever the pH is within the discharge window is not sufficient. We must ensure that the pH discharged will remain within the acceptable discharge limit. Since the treatment tank may be stratified, or chemical reactions may not be complete, or the pH probe may not have completely reacted; we cannot just assume that the pH of the treatment tank is acceptable. A discharge qualification consisting of the measured pH and stability must be considered. Obviously the pH must be within the discharge window, but we must also consider the stability of the pH. If the pH is changing beyond an acceptable limit (e.g., pH∆ > 0.5 pH/min), then discharge must halt. The actual drift change/limit is determined on a case-by-case basis. If we refer back to the titration curves in Fig. 43.2, we will see that when the pH of water is near neutral, it is very unstable. An almost immeasurable change in the total acidity or alkalinity in this range can cause a very large change in pH. The control of pH in acid etching baths is very easy since the pH is held very low in a highly buffered range. Likewise the control of the pH of soap cleaning tanks is very easy since the pH is held high in a highly buffered range. The control of pH in neutralization systems, however, is often very difficult since the pH is held near neutral in a highly unbuffered range. Therefore, unless a system is very carefully designed, pH instability will plague the entire system. The control requirements described cannot be accomplished in any other way than a programmable logic controller (PLC). PLCs such as the Allen-Bradley SLC500 family and higher are capable of handling the math and control requirements of a typical pH adjustment system, whether it be single stage or multiple stages. 43.5.2 Optimized Batch pH Adjustment System The system architectures that we have investigated so far are all of the standard design that is often described in texts and often installed in industry. These systems are all plagued by a number of problems that have already been addressed in our discussion on optimizing system design. In summary these problems are: 1. Inproper tank design and mixing 2. Inadequate pH measurement and inappropriate pH probe installation

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

04/04/2005

21:24

Page 43.21

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.21

3. Inadequate chemical metering precision, inadequate chemical metering range, and poor chemical metering technique 4. Inadequate control system and the lack of accurate control algorithms We have already discussed standard batch system design. This discussion served to explain the design of a simple batch system, which is a very common implementation. The system that follows addresses all the weaknesses identified previously. A brief review of Fig. 43.20 reveals a batching system with a few more components. The system shown in Fig. 43.20 is an “optimized” batch pH adjustment system. This is a twostage batching system consisting of an equalization tank and a batch treatment tank. The equalization system is used for the purpose of homogenizing the influent flow and to provide a reservoir for accepting waste. The second stage of the system is a batch treatment stage that is designed to accept a fixed batch size from the equalization system and to treat that volume as a batch. An obvious disadvantage of a single-stage batch system is that influent flow must stop when the treatment tank is full. The implementation of an equalization stage allows for a continuous influent flow. Note that the addition of the recirculation loop allows us to create an optimum environment for the pH probe and for chemical addition. The pH probe has been removed from the tank where an optimum environment can be created and chemical injection takes place in the loop before the sample stream is reintroduced into the treatment tank. Furthermore, all the control algorithms and control features discussed previously in Sec. 43.5 must be employed here as well. In a typical cycle the treatment tank control logic will continuously monitor the tank level and allow for transfer from the equalization tank whenever the level descends below the 1/3 full point. Transfer from the equalization tank will continue until the batch treatment tank reaches the high level (approx. 85 percent full). As the level in the treatment tank rises above the 1/3 full point, a treatment cycle is initiated by starting the recirculation pump and continuously monitoring the tank pH. Chemicals are added as required and the pH is brought up into range. Once the tank contents are in the acceptable discharge range and meet the discharge criteria, the recirculation loop diverter valve routes the flow from recirculation to discharge. As long as the discharge criteria are met the tank is pumped to the low level shutoff point (approx. 10 percent) at which point the pump will be shut down.

AIT

Influent stream

Acid Caustic Recirc/transfer A

Recirc/ discharge valve

Geng(SMH)_CH43.qxd

Mixer

A

AE pH probe and controller

FE

Treated effluent

AIC Recirculation/ discharge pump AE

LIT Influent equalization tank

FIGURE 43.20

Recirculation/ transfer pump

Optimized batch treatment tank

Continuous level transmitter

Optimized batch pH adjustment system.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.22

WASTEWATER NEUTRALIZATION SYSTEMS 43.22

FAB YIELD, OPERATIONS, AND FACILITIES

In an effort to promote efficiency the equalization transfer is allowed to resume once the treatment tank level descends below the 1/3 full point. This is done so that treatment of the influent stream can begin immediately without having to wait for the tank level to rise. The purpose of the batch system is to keep the equalization tank empty (or nearly empty); therefore, the batch system may run nonstop if the equalization tank has liquid to be treated. We used a term in our control system description that is not used very often with treatment systems. The term “discharge criteria” refers to the conditions that must exist before we can allow discharge to occur. A very important consideration in any pH system design is allowing time for the chemical reactions to come to completion and for the pH probes to react. We have observed many systems in the field that do not properly evaluate all of the discharge criteria. The result is a system that is discharging an effluent stream with a pH that substantially differs from that which is measured at the system. It is not uncommon to take a sample in a manhole downstream of the treatment system and to see a pH higher or lower than displayed at the system. When determining if an effluent stream is suitable for discharge, one must consider at a minimum, the measured pH and stability. Stability is defined as the rate of change of the measured pH. We typically look for a stability of greater than pH < 0.50/60 s. This means that if the measured pH changes by more than one half of a unit in the last minute then we cannot discharge, regardless of the actual value. An unstable value indicates a chemical reaction that is still taking place, a probe that has not had time to settle, or a tank mixing time that is insufficient. Regardless of the reason for the instability, one cannot be sure of the final pH, therefore discharge cannot take place. Batching systems are by far the safest type of treatment system to implement because the system design ensures that the effluent stream will meet specified criteria before going to the drain. A batching system, however, can bottleneck a plant process by restricting flow. For this purpose, it is essential that we carefully evaluate the discharge flow rates, the titration curve, and supply a sufficiently large equalization tank. An alternative to an equalization system is a second batching system configured in parallel. This is referred to as a duplex batching system, which offers double the throughput and redundancy. “Optimized batch” systems can be deployed in many different ways ranging from simplex systems with no influent equalization, to triplex systems including influent equalization.

43.5.3 Hybrid Batch pH Adjustment Our discussions so far regarding continuous batch pH adjustment systems dwell on their inability to tolerate large load changes. This single fact is the limiting factor in the initial design consideration. The primary problem with a continuous system is that, as the name implies, the discharge flow is continuous. If, however, we increase the usable volume within the treatment tank and provide an automatic discharge valve such that we can shut off the discharge flow, we can possibly overcome this limitation. The benefits of the design in Fig. 43.21 are that influent flow can continue uninterrupted even if a large load change should overwhelm the system. In this event the discharge valve would close and the system would attempt to bring the pH back into the acceptable discharge range with the effluent shut off. The influent flow could continue because of the reserve volume within the treatment tank. Although not a cure-all, this combination of continuous batch and batching will allow for some relatively large load changes. The limitation, obviously, is the amount of reserve volume in the treatment tank. If the equilibrium within the treatment tank is not reestablished by the time the fluid level reaches the overflow port, then the discharge flow will resume through the overflow. This treatment scenario is well suited for continuous streams with occasional sudden load changes. A five-minute reserve volume in the tank should be planned. Alternatively, the overflow port can be directed back to the influent equalization system or the collection system ahead of the treatment system to be recycled through. Additionally, if an influent equalization system is employed an influent automated influent valve can be employed that is automatically closed when the discharge valve is closed, thereby allowing for even more batching volume and time.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.23

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.23

Caustic Acid pH probe and controller Mixer

Influent stream

AIC Recirculation pump AE Overflow A

Discharge valve

FIGURE 43.21

Treated effluent

Hybrid batch pH adjustment system.

In this example we see a process diagram that depicts the use of an influent flow chamber. The purpose of this chamber is to provide an evenly distributed flow to the influent side of the tank. On tanks with widths of 36 in or more, an influent chamber can significantly enhance system performance. The alternative is to bring the influent pipe into the tank and terminate it near the bottom. The influent chamber, or laminar flow baffles, help to ensure that the fluid path through the tank is as long as possible. The problem with a pipe terminated near the bottom of the tank is the flow distribution. If the tank is 60 in wide, for example, and the influent pipe has a 4-in diameter, we will have a concentrated “hot spot” of influent within the tank. The use of an influent flow chamber will disperse this flow over an area that is the entire width of the tank. Since the flow chamber uses valuable treatment volume within the tank the chamber should be kept to a size of less than 10 percent of the overall tank volume.

43.6 THE CONTROL SYSTEM The control system for any well-designed pH adjustment system must be capable of handling the logic sequencing of the control valves, pumps, mixers, and provide all required alarm annunciation and handling. Additionally, the control system must be capable of handling the complex control algorithms that are required for fast, efficient, and accurate pH control. These algorithms have been thoroughly discussed in prior sections. 43.6.1 A Programmable Logic Controller The use of a programmable logic controller (PLC) is an imperative. It allows the system designer to perform all of the required control system functions in a single unit. This makes for a simple electrical design using standard off-the-shelf components. The entire control system should be directly monitored and controlled via the PLC. By interfacing all the system components to the PLC, the human machine interface (HMI) is simplified. Any PLC, such as the Allen-Bradley SLC500 family or higher that is capable of handling the control and logic, will be equipped with the necessary communication interface(s) to allow for interfacing to standard data communication networks such as

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.24

WASTEWATER NEUTRALIZATION SYSTEMS 43.24

FAB YIELD, OPERATIONS, AND FACILITIES

Ethernet, Data Highway, MODBUS, and so forth. Supervisory control and data acquisition (SCADA) systems are becoming common place in industry. SCADA systems offer a plethora of HMI, data logging, and report generation options to the system designer. By using a PLC we facilitate the interfacing of the pH adjustment system to a third-party SCADA. 43.6.2 HMI The HMI consists of the following at a minimum: • Pilot lights for the annunciation of alarms, and for status indication for pumps, mixers, valves, and so forth. • Selector switches, such as hand-off-auto (HOA) switches for the control of all automated devices. It is imperative that all automated devices be isolated from the automation system so that automatic control can be interrupted and manual control be provided. • Audible alarm device utilizing standard Instrument Society of America (ISA) alarm annunciation logic. This provides a mechanism by which alarms can be annunciated without an operator in direct contact with the main control panel (MCP). The device, as per ISA standards must be equipped with a silence circuit. • Keypad and display, a mechanism by which the operator can conveniently view measured process variables (e.g., pH, tank level, and pump output.) must be provided. Additionally, the operator interface unit (OIU) must provide a way to view and change system set points and tuning parameters. A complete SCADA system is an excellent mechanism by which this can be done, however, a small keypad with a multiline LCD display will suffice for most applications. The design of the system should be such that the system can be operated without accessing the keypad and display. 43.6.3 Main Control Panel The MCP should house all of the control system components in a single enclosure (unless the size dictates more than one panel), including motor controls. The MCP should be a National Electrical Manufacturers Association (NEMA) 4 or 4X device, as it will be installed in a known wet and corrosive environment. Low-voltage controls such as 24 Vdc, should be used throughout, in as much as is possible. This is to minimize electrical shock hazards in a known wet environment. The MCP should be equipped with a main disconnect that provides lock out tag out (LOTO) protection. Additionally, each motor driven device (pumps and mixers) should be provided with individual nonfusible disconnects for the purpose of LOTO. 43.6.4 pH Probes pH probes, as has been previously mentioned, are the Achilles heel of any pH adjustment system. pH probes are prone to premature failure as a result of fouling, contamination, or breakage. The proper installation, as discussed in the Sec. 43.5, will prolong the life of the probe as well as enhance the response. The construction of pH probes varies little throughout the industry. Some variation in packaging occurs but the basic design is essentially the same. The best probe to use in most applications is a flat surface double junction probe. The probe will require a transmitter to convert the high-impedance low-voltage signal to a 4 to 20-mA current loop for interfacing to the PLC, or other devices. Frequent calibration is required, therefore the transmitter, from which the calibration is performed, should be located as close to the probe as possible. Additionally, if the transmitter is kept reasonably close to the pH probe then a preamp at the pH probe is not required, thereby simplifying the design. 43.6.5 Temperature Compensation Temperature compensation of pH probes used in wastewater applications is not necessary. Temperature does impact the slope of a pH probe, thereby impacting accuracy. However, at a pH of 7.0, temperature

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.25

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.25

has no impact on the probe response or accuracy and the overall impact within a range of 6.0 < pH < 9.0 is minimal. The response to temperature can be expressed as follows: ∆pHtemp = 0.001 pH/°C/(|7-pH|) At a pH of 7.0, temperature has no effect on pH probe output. At a pH of 9.0, at the edge of most discharge bands, a 40oC change in temperature will only impact the probe output by 0.08 pH units, an insignificant amount, considering that 40°C is a big change. Therefore temperature compensation is normally not recommending as this has very little upside and a big downside (i.e., if the temperature compensation circuit should fail the pH transmitter can be disabled or yield a large measurement error). 43.6.6 Design Standards The following design standards should regulate the design of the electrical control system: • National Electrical Code (NEC): The NEC is the minimum design standard for wire sizing, branch circuit protection, motor load interfacing, and wiring practices. • Occupational Safety and Health Administration (OSHA): Particularly with reference to LOTO procedures. • National Fire Protection Association (NFPA) 79: This code expounds upon the NEC and is specific to industrial controls. This standard further defines wiring practices, branch circuit protection, motor load protection, and even, to some degree HMI in that a standard for pilot light and selector switches is provided. • Underwriters Laboratories (UL) 508: This standard essentially integrates the NEC and NFPA 79 into a single standard. Unlike the NFPA or the NEC enforcement and policing of the standard is provided by field inspectors. All controls panels should be UL 508 listed to ensure a safe compliant control system. • Instrument Society of America (ISA): An excellent reference for instrumentation standards and recommended practice.

43.7 CHEMICALS USED FOR pH ADJUSTMENT The selection of the chemicals used for the neutralization of an acid or base can be an important design decision. There are many considerations ranging from health and safety to cost and convenience of operation. Some of the major points to consider in the selection of chemicals are listed below: • Health and safety • Cost and convenience • Storage environment and location To neutralize an acid or base a source of hydroxide ions (OH−) or hydrogen ions (H+) are required, respectively. An acid must be neutralized with a base, which, by definition, is characterized by an excess of OH− ions. Likewise, a base must be neutralized with an acid, which, by definition, is characterized by an excess of H+ ions. For example, in a simple neutralization process hydrochloric acid (HCl) can be neutralized by using sodium hydroxide (NaOH). An explanation of chemical selection criteria follows. 43.7.1 Health and Safety Whenever mixing chemicals extreme caution must be exercised. Hazardous or noxious reactions may occur. For example, adding any acid to a cyanide bearing solution may result in the release of

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.26

WASTEWATER NEUTRALIZATION SYSTEMS 43.26

FAB YIELD, OPERATIONS, AND FACILITIES

deadly HCN gas. Due to the complexity of the myriad of processes that are run in industry, most of which are either proprietary or undefined, it is impossible to comment on the suitability of an acid or base selection for the neutralization of all wastewater streams. Although adverse reactions are very rare, the possibility exists and must be considered. 43.7.2 Cost and Convenience Most acids and bases will work in most applications. Therefore, the determining criteria are usually cost and convenience. Sulfuric acid (H2SO4), for example, is less costly and more potent than nitric acid, however, if sulfuric is not currently inventoried then nitric may look more favorable because it may already be on hand. Concentrations are also an important consideration in evaluating cost. Sulfuric acid, for example, can be purchased in concentrations ranging from near 0 percent up to 98 percent. If a 55-gal drum of 50 percent sulfuric is purchased, obviously half of that purchase cost is for water. Higher concentrations are generally less expensive. 43.7.3 Storage Location and Environment The physical properties of the selected reagent must be considered carefully. Fifty percent sodium hydroxide (NaOH), for example, begins to freeze at temperatures near 60°F. In most places throughout the country, if not all, the possibility of caustic freezing in tanks or in pipelines is a genuine concern. Decreasing the concentration to 25 percent eliminates this concern altogether. Hydrochloric acid (HCl), for example, outgasses severely. The gas is highly corrosive and will attack all metallic objects including building structures, sprinkler heads, copper wiring, and stainless steel and the like. Therefore, if HCl is used it must be properly vented or used outdoors where the gases can easily dissipate. 43.7.4 Chemicals Used for Treatment The most commonly used neutralizing chemicals are listed below: • Acids • • • • •

Sulfuric acid (H2SO4) Hydrochloric acid (HCl) Nitric acid (HNO3) Phosphoric acid (H3PO4) Carbon dioxide (CO2)

• Bases • • • •

Caustic (NaOH) Ammonium hydroxide (NH4OH) Magnesium hydroxide [Mg(OH)2] Calcium hydroxide (lime) [Ca(OH)2]

Acids Sulfuric acid (H2SO4). Sulfuric acid is he most widely used and produced chemical in the world. Available in concentrations ranging from 0 to 98 percent sulfuric is also the least expensive acid to use. Sulfuric acid is the almost universally for neutralization reactions. It is easier and safer to use than HCl or HNO3 and is more potent than all of the other acids except for phosphoric. Although adverse reactions are always a possibility, they are rare. If calcium is present then calcium sulfate (CaSO4), also known as gypsum, will precipitate, leaving behind a white sticky sludge.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.27

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.27

Unless calcium is abundantly present this is not an issue. Sulfuric acid is typically used in concentrations ranging from 25 to 93 percent. Hydrochloric acid (HCl). Also known as muriatic acid, HCl is the second most commonly used acid in industry (sulfuric is number one). HCl is a very effective and relatively inexpensive acid. At a maximum available concentration of 37 percent HCl is about 1/3 as potent as sulfuric acid, further contributing to the fact that HCl is more expensive to use than sulfuric. Depending on the temperature and agitation, HCl at concentrations above 10 percent will evolve a hydrogen chloride vapor that forms very corrosive vapors when combined with the water vapor already in the air (humidity). The gas is highly corrosive and will attack all metallic objects including building structures, sprinkler heads, copper wiring, and stainless steel. Therefore, if HCl is used it must be properly vented or used outdoors where the gases can easily dissipate. For this reason alone, the use of HCl is not recommended. Nitric acid (HNO3). A widely used chemical in many industries, nitric does not enjoy the popularity that hydrochloric or sulfuric does. As such, nitric is more expensive to use than either sulfuric or hydrochloric acid. As with hydrochloric acid nitric will evolve a noxious gas that combines with water vapor already in the air (humidity) to form a very corrosive gas. The gas is highly corrosive and will attack all metallic objects including building structures, sprinkler heads, copper wiring, and stainless steel. Therefore, if HNO3 is used it must be properly vented or used outdoors where the gases can easily dissipate. For this reason alone the use of HNO3 is not recommended. Phosphoric acid (H3PO4). Phosphoric acid is very widely used in the production of agricultural fertilizers and detergent products. Though relatively inexpensive, it still does not compete well with sulfuric and hydrochloric acid. Due to its disassociation constant phosphoric is a weak acid. Unlike sulfuric or hydrochloric it will not fully disassociate in water at normal concentrations. This renders phosphoric safer to use than sulfuric or hydrochloric and the evolution of gases is rarely, if ever, a problem. Due to its weak disassociation constant phosphoric acid does not react with the normal logarithmic response as a strong acid and tends to buffer neutralization reactions. This makes for a slower reaction that is easier to control. Due to its cost (as compared to sulfuric) and availability, phosphoric acid is not commonly used in neutralization systems. Carbon dioxide (CO2). The third most concentrated gas found in the earth’s atmosphere (preceded by nitrogen and oxygen), CO2 is itself not an acid. CO2 forms carbonic acid (H2CO3) when dissolved in water. It is carbonic acid that leads to the neutralization of alkalinity in solution. Carbon dioxide is not easy to use and its use is limited. However, for some applications CO2 can be a very effective choice. The most appealing feature of CO2 is that it will not lower the pH of water below 7.0 (for practical purposes). Additionally, CO2 is not corrosive as a gas; however, since CO2 is heavier than air, asphyxiation is always a hazard. CO2 can be difficult to use because the gas must be dissolved into solution to be used. This requires the use of a carbonator, or some method to dissolve the gas into solution such as a diffuser. Generally a tall tank must be used to ensure that there is sufficient fluid pressure to promote the dissolution of CO2 in water. Significant outgassing will occur, which is not a problem unless the process also requires the settling of solids. Bases Sodium hydroxide (NaOH). Also known simply as caustic, this is the most widely used alkalineneutralizing chemical in use in industry today. Sodium hydroxide is easy to handle, inexpensive, and very effective for the neutralization of strong or weak acids. NaOH is available in concentrations of up to 50 percent, which is the most commonly used concentration. One must be careful when using 50 percent NaOH because of the freezing point. NaOH at a 50 percent concentration will begin to freeze at temperatures below 60°F. This happens to be a very common problem and can render a system useless. The best way to circumvent this problem is to use lower concentrations, such as 25 percent. Caustic has a high affinity for CO2 in the atmosphere. The absorption of CO2 results in the formation of insoluble carbonate species. This results in the formation of solids that can be problematic for small pumps. A lower concentration of caustic not only alleviates the problem of freezing but also decreases the formation of solids as a result of CO2 absorption. Caustic is more expensive than lime or magnesium hydroxide, but due to its solubility, it is much easier to handle.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.28

WASTEWATER NEUTRALIZATION SYSTEMS 43.28

FAB YIELD, OPERATIONS, AND FACILITIES

Neutralization reactions form salts as the pH is brought near the end point. Sodium salts are normally quite soluble in water. Therefore, reactions using NaOH will normally not generate high solids, unlike calcium products (lime) or magnesium products (magnesium hydroxide). Ammonium hydroxide (NH4OH). One of the more commonly produced chemicals in the United States, ammonium hydroxide is a poor choice for a neutralizing chemical. It is relatively expensive, hard to handle, evolves noxious and corrosive gases, and is a relatively weak base. Nonetheless ammonium hydroxide can be used as an effective neutralizing chemical. Magnesium hydroxide [Mg(OH)2]. Also commonly referred to as mag, this chemical is effective in neutralizing acids and has been pushed by some chemical companies. Despite some attempts to advertise it as such, mag is no treatment panacea. Magnesium hydroxide is relatively insoluble in water at neutral pH values and higher. Given this mag has little or no effect on water alkalinity above a pH of 7.0. This means that even in a poorly designed system mag will not raise the pH above a pH of 7.0, rendering this chemical safe to use from a control point of view. Additionally, magnesium hydroxide, also known as milk of magnesia, is quite safe to handle and is not normally toxic. The characteristic that limits mag’s ability to raise the pH above 7.0 (solubility) also contributes to very long reaction times. The typical reaction times for complete neutralization are in the order of 90 min. This means that a single reactor tank must have the capacity of 90 min of flow. In a 100 gpm system, for example, the first stage reactor must be approximately 9,000 gal in volume. The alternative is to discharge with an incomplete reaction. This means that the pH will continue to change as the effluent is discharged (never favorable) and an excessive amount of mag must be used. Also as a result of solubility the use of magnesium hydroxide will significantly increase the loading of solids in the effluent. Magnesium hydroxide is a slurry that will rapidly separate from solution, making it difficult to handle. The storage tank must be constantly agitated and chemical delivery lines must be kept in motion. Typically recirculation loops are employed with a metering valve, inline, for chemical delivery. Static lines are not acceptable because the slurry will separate, and the lines will plug, over time. There are a few applications where magnesium hydroxide will produce favorable results; however, due to its solubility and long reaction time, magnesium hydroxide is not normally a good choice. Calcium hydroxide [Ca(OH)2]. Also commonly referred to as slaked lime or hydrated lime; calcium hydroxide is formed as a result of hydrating lime (calcium oxide, CaO). Lime is by far the most economical alkaline reagent to use for acid neutralizations. Lime is significantly cheaper than caustic NaOH, but is much more difficult to handle. As with magnesium hydroxide, lime is not very soluble in water. Although the reaction times of lime are substantially less than magnesium hydroxide, lime is difficult to handle because it is handled as a slurry. Ca(OH)2 is divalent [as is Mg(OH)2], yielding two moles of OH2 for every one mole of Ca(OH)2. When compared to caustic (NaOH), which is monovalent, twice the neutralizing power is available for a given molar volume of lime, thus contributing to the economy of lime. As with magnesium hydroxide, lime is normally delivered in dry crystalline form. This must then be mixed with water to form a slurry to be delivered to the process. When compared to the handling ease of caustic (NaOH), this can be a significant disadvantage. Lime is a slurry that will rapidly separate from solution. The storage tank must be constantly agitated and the chemical delivery lines must be kept in motion. Typically recirculation loops are employed with a metering valve, inline, for chemical delivery. Static lines are not acceptable because the slurry will separate, and the lines will plug, over time. Lime offers very significant advantages when the precipitation of metals or fluorides is the goal. Calcium salts are normally quite insoluble, and due to the fact that lime is divalent, sludge densities are normally much higher than those formed with caustic NaOH. Lime is an excellent choice for acid neutralization. If volumes are relatively low, and precipitation of metal or fluoride ions is not paramount, then caustic NaOH may be the better choice because it is easier to handle. Limestone. At one point in time limestone was used for the neutralization of acidic wastewaters. Although no longer an option because of its limited efficacy, limestone is occasionally considered

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:24

Page 43.29

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.29

by those not intimately familiar with the nature of pH adjustment systems. Therefore, a brief discussion follows, although the use of limestone cannot be advocated. Limestone is an alkaline agent with the ability to neutralize, or partially neutralize strong acids. The neutralization process occurs when strong acids, in intimate contact with limestone chips, react with calcium carbonate (CaCO3, the primary constituent of limestone) to form water, CO2, and calcium salts. Due to the liberation of CO2 (resulting in the formation of carbonic acid) limestone does not have the ability to raise the pH of an effluent stream above 7.0. Due to the solubility of these products even a pH of 7.0 is not usually practical. Considering that CO2 is only liberated as a result of the neutralization of an acidic solution, limestone is not effective in neutralizing alkaline solutions. In fact, limestone will not at all contribute to the neutralization of alkaline materials. One of the byproducts of the neutralization process is calcium salts. Calcium salts tend to be very insoluble in water. This results in the precipitation of salts that deposit on the limestone chips forming very effective coatings. Once coated with the precipitated products limestone is rendered useless and must be replaced. Other solids and organic materials that are suspended in the waste stream will often come out as a result of mechanical filtration thereby contributing to the coating of the limestone chips. The chemistry stands—limestone will neutralize strong acids, at least partially. However, in practice limestone cannot be relied upon to neutralize acidic waste streams. The chips are very easily rendered useless from coating by the highly insoluble calcium salts and other products that precipitate out of the effluent stream. Additionally, the design of the system cannot inherently guarantee the treatment of the effluent stream. There are no controls that regulate the addition of acidic or alkaline neutralizing agents. The system designer simply hopes that sufficient alkaline products dissolve into solution to achieve the desired treatment. For these reasons the use of limestone cannot be considered.

43.8 THE APPLICATION OF pH ADJUSTMENT IN CHEMICAL MECHANICAL POLISHING, METAL REDUCTION, AND FLUORIDE REDUCTION The most commonly controlled wastewater quality in semiconductor effluent streams is pH. However, there can be many other water qualities that require our attention; these include heavy metal reduction and fluoride reduction. Heavy metals and fluorides can be toxic, have an extremely detrimental impact on aquatic wildlife, and affect the performance of the local POTW to which the effluent stream is discharged. All over the United States, and in most locations throughout the world, heavy metal levels are very tightly regulated. Fluoride level limitations vary widely from location to location and are not quite as restrictive as heavy metals. Both heavy metals and fluorides can be reduced to below permit levels with a properly designed wastewater treatment system. The most critical process in any of these systems is pH adjustment. All of the heavy metals typically found in wastewater streams, including copper (Cu), nickel (Ni), lead (Pb), and tin (Sn) can be precipitated as solids with proper pH adjustment (assuming that complexing agents do not sequester the metals). An in-depth discussion of the design of these systems is beyond the scope of this paper and can easily fill an entire book, or even volumes of books, therefore only a brief overview follows. In the system in Fig. 43.22 metal laden wastewaters are collected in the influent equalization tank, from here they are transferred, in batches, to the treatment tank. In the treatment tank the batch is pH adjusted to the point where the target metal solubility is at a minimum. For example, for a chemical mechanical polishing (CMP) waste stream containing Cu the target pH would be greater than 8.0. At this point soluble Cu precipitates and can be separated via gravity as a sludge. The sludge is then dewatered via the filter press and hauled off. Supernatant or “clear” water is pumped from the treatment tank through a simple mechanical filtration system and then to the drain. It is not unreasonable to yield effluent Cu levels of less than 0.5 ppm (parts per million) with this configuration.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

43.30 Ultrasonic level

Filtrate lift station

LE

Influent transfer pump

Lift pump

FE

Sludge pump

pH

NaOH injection

Ultrasonic level Polymer injection

Treatment tank and clarifier

Mixer

Flow switch

FS

A

Bag filters 2 µm 5 µm

Treated effluent to drain

21:25

Filter press

Influent equalization

FE

04/04/2005

FIGURE 43.22 Depicted here is a simple, yet typical metal hydroxide precipitation system suitable for low flows. A pH adjustment system is the primary component as metals, such as copper (Cu) are precipitated as a hydroxide through pH adjustment to a specific endpoint.

Untreated influent

Geng(SMH)_CH43.qxd Page 43.30

WASTEWATER NEUTRALIZATION SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:25

Page 43.31

WASTEWATER NEUTRALIZATION SYSTEMS WASTEWATER NEUTRALIZATION SYSTEMS

43.31

As seen in Fig. 43.22, pH adjustment systems are not used for acid/base neutralization only; they have applications in many other systems as well. pH adjustment systems are often an integral component of the following: • • • • • • •

Metal hydroxide precipitation systems, as depicted in Fig. 43.22 Influent pretreatment for metal reduction via ion exchange systems pH conditioning of reverse osmosis (RO) feed water Fluoride reduction systems Cyanide destruct systems Hexavalent chrome reduction (Cr+6 → Cr+3) systems Fume scrubber sump pH control

Whether applied for acid/base neutralization, fluoride reduction, or Cu reduction of a CMP waste stream, the system designer must be concerned with accurate and repeatable pH adjustment, as discussed in this chapter.

FURTHER READING Freeman, H. M., Standard Handbook of Hazardous Waste Treatment and Disposal, 2d ed., McGraw-Hill, New York, 1997. Haas, C. N., and R. J. Vamos, Hazardous and Industrial Waste Treatment, Prentice Hall, Englewood Cliffs NJ, 1995.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

Geng(SMH)_CH43.qxd

04/04/2005

21:25

Page 43.32

WASTEWATER NEUTRALIZATION SYSTEMS

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.