.
IEEE Nuclear and Space Radiation Effects Conference
Short Course
Advanced Qualification Techniques; A Practical Guide for Radiation Testing of Electronics
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July 17, 1995 Holiday Inn Madison, Wisconsin
Sponsored by IEEE NPSS Radiation
Effects
Committee **>
Cosponsored by Defense Nuclear Agency/DoD Sandia National Laboratories/DOE Phillips Laboratory/USAF Jet Propulsion Laboratory/NASA
[&) MADISON
1995 IEEE Nuclear and Space Radiation Effects Conference
Short Course
Advanced Qualification Techniques; A Practical Guide for Radiation Testing of Electronics
Ju1y 17,1995 Holiday Inn Madison, Wisconsin
Copyright@ 1995 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. For all other copying, reprint, or replication permission, write to Copyrights and Permission Department, IEEE Publishing Services, 445 Hoes Lane, Piscatawav, NJ, 08855-1331.
TABLE OF CONTENTS
SECTION I Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 1-4 James R. Schwank, Sandia National Laboratories SECTION II SINGLE-EVENT EFFECTS QUALIFICATION William J. Stapor, Naval Research Laboratory
. . . . . . . . . . . . . . . . . . . . . . . . II 1-68
SECTION III A FIRST-PRINCIPLES APPROACH TO TOTAL-DOSE HARDNESS ASSURANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III 1-69 Daniel M. Fleetwood, Sandia National Laboratories SECTION IV ADVANCED TEST METHODOLOGIES Nick van Vonno, Harris Corporation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV 1-55
SECTION V QUALIFICATION FROM THE BUYER’S PERSPECTIVE Lee Mendoza, The Aerospace Corporation
. . . . . . . . . . . . . . V 1-44
1995 NSREC SHORT COURSE
(J@&-) MADISON
FOREWORD This is the 16th year that a Short Course has been offered at the Nuclear and Space Radiation Effects Conference (NSREC). The Short Course format provides an opportunity to cover topics in considerably more depth than is possible by individual contributed papers. The themes of the Short Courses have varied over the years reflecting the important subject areas of the time. The theme of the 1995 Short Course is Advanced Qualijkation Techniques: A Practical Guide for Radiation Testing of Electronics for radiation-hzu-dened and commercial systems. This Short Course is intended to be a practical guideline, giving students the background, and know-how to test and qualify present-day and future electronic devices using reliable, costeffective techniques. The development of hardness assurance and qualification testing techniques is a rapidly evolving area. As more emphasis is placed on the use of commercial devices in military systems and the margin between device capability and system requirements becomes increasingly less, knowledge of practical and reliable testing and qualification techniques and their implementation becomes increasingly more important. This year’s Short Course addresses those radiation testing techniques which guarantee that only the most radiationtolerant parts are used in our spacecraft systems. This timely theme should be of interest to attendees having a wide spectrum of backgrounds, from those interested in the mechanisms of radiation effects to users and buyers of electronic components and systems. The course is divided into four sections. The first section, Single-Event Effects Qualification, will emphasize techniques for qualifying electronic devices and integrated circuits for singleevent effects. It will start with an overview of the space environment and how it relates to singleevent effects. Cosmic particles and trapped particles in the earth’s radiation belts can cause softerror upset and hard errors in an integrated circuit. Students will learn about what ground-based measurement sources are available for simulating Single-Event Effects (SEE), their uses, and their limitations, Students will next learn about methods for predicting SEE. This is an area of considerable importance due to the complexity of today’s devices and the variability in radiation environments. Hardness assurance test methods presently available will be discussed. This segment will end with a discussion of problems and trends for future SEE testing. The second section, A Fi.mt+rinciples Approach to Total-Dose Hardness Assurance, will emphasize total-dose hardness assurance techniques for qualifying electronic devices and integrated circuits. It will start with a description of several radiation environments with varying total-dose requirements. The student will then learn of laboratory radiation sources used to simulate and test for total-dose effects. Students will learn of time-dependent effects and device response and failure modes. This knowledge is essential in order to correlate laboratory measurements to system requirements. Present-day test methods will be discussed. This segment will end with an overview of possible non-destructive tests and future trends for hardness assurance testing. The third section, Advanced Test Methodologies, is divided into two parts. The first part is an overview of traditional approaches to qualification testing. In addition to issues such as wafer-
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level testing and screening for latchup and burnout, students will also learn of the special case of testing and quali&ing cryogenic electronics. The second part is on advanced approaches to electronics qualification testing. In this part, students will learn of advanced approaches that can result in substantial savings in cost and time in qualification testing, including the qualified manufacturers list (QML) methodology. The difllcult issue of how to quali~ VLSI components will also be covered. This section will end with a discussion of future trends for hardness assurance testing and the impact of commercial off-the-shelf (COTS) mandates. The fourth section, Qz.uzli@ztionjiom the Buyer’s Perspective, will cover qualification from the buyer’s perspective. This perspective presents different problems from that of the device engineer or manufacturer. The student will first learn how to choose parts to meet system requirements. This can often be a difficult problem considering the wide variety of available parts and test methods for qualification. Due to their lower costs, commercial devices are seeing increased use in military and space systems, Students will learn of the tradeoffs between commercial and radiation-hardened devices. This section will end with several case histories of real system failures caused by radiation-induced part degradation. I would personally like to thank the four authors Bill Stapor, Dan Fleetwood, Nick van Vonno, and Lee Mendoza for the effort they have made in putting this Short Course together. A great deal of pecsonal time and sacrifice is required for assembling and writing the Short Course manuscript and preparing the Short Course presentation. Only those who have endeavored to undertake such a task can appreciate the intense labor that is involved. The authors have done an exceptional job in putting together this Short Course. I also thank Lew Cohn for his efforts in ensuring that the Short Course notebook was printed on time and the DNA Printing OffIce for printing the notebook, Without their efforts, this Short Course notebook would not have been possible.
James R, Schwank Albuquerque, New Mexico
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Biographies James R. Schwank Short Course Organizer Sandia National Laboratories James R. Schwank received his B. S., M. S. and Ph. D. degrees in electrical engineering at the University of California at Los Angeles in 1970, 1974, and 1978, respectively. He joined Sandia National Laboratories in 1979 where he is a senior member of the technical staff. At Sandia, he has been involved in numerous studies investigating the mechanisms of radiation effects in semiconductor devices, in developing techniques for improving the radiation hardness of MOS devices, and in hardness assurance activities. Dr. Schwank has served the NSREC as short course instructor, publicity chairman, session chairman, and reviewer, and the Hardened Electronics and Radiation Technology (HEART) Conference as technical program chairman, guest editor, associate guest editor, and session chairman. He has won six outstanding or meritorious conference paper awards and has authored more than 65 papers on radiation effects in electronic devices. Dr. Schwan.k is a Fellow of the IEEE. William J. Stapor Naval Research Laboratory William J. Stapr has a B. S. in physics from William and Mary, Williamsburg, Virgini% and an M. S. and Ph. D. in nuclear physics from The Catholic University of America, Washington, D. C. He initially worked for a while in the photonuclear physics community making high-energyelectron scattering measurements of nuclear charge distributions. He has worked in the radiation effects area for over eleven years at the Naval Research Laboratory, Washington, D. C., in the Radiation Dynamics Section of the Radiation Effects Branch, specializing in single event effects in microelectronics. Dr. Stapor is presently the Defense Nuclear Agency Program Advisory Reviewer for the single event task area. He has chaired the last two Single Event Symposia held every two years in the Los Angeles area. He performs basic research and development as well as performing practical engineering consulting to the spacecraft community. Dr. Stapor has authored and co-authored over 45 publications. Daniel M. Fketwood Sandia National Laboratories Daniel M. Fleetwood received his B. S,, M. S., and Ph. D. degrees in physics from Purdue University in 1980, 1981, and 1984, respectively. There he received the Lark-Horovitz Award for his work on l/~ noise in metals. Dan joined Sandia National Laboratories’ Advanced Microelectronics Development Department in 1984, and moved to the Radiation Technology and Assurance Department in 1986. He was named a Distinguished Member of the Technical Staff in 1990. He has authored more than 110 papem on radiation effects and Iv noise in microelectronics and has received seven outstanding or meritorious conference paper awards. Dan has served the IEEE NSREC as guest editor, poster session chairman, session chairman, and He presently is vice-chairman for publications and technical technical program chairman.
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program on the radiation effects steering group. Dan is a senior member of IEEE and a member of The American Physical Society, Phi Beta Kappa, Phi Kappa Phi, and Sigma Pi Sigma. Nick van Vonno Harris Corporation Nick van Vonno received his B. S, degree in electrical engineering from the University of Florida in 1966. Upon graduation, he joined Radiation, Incorporated (now Harris Corporation). After initial assignments in reliability engineering, he moved to process development and device engineering with participation in both bipolar and CMOS projects. Later responsibilities were in the design, development, and production of htidened analog components on a variety of strategic programs. Specific areas of interest included mixed-signal design, cryogenic CMOS process development, and SOI technology. Mr. van Vonno has been active in NSREC affairs. He served as session chairman of Isolation Technologies and Poster sessions, and was guest editor for the 1992 conference and awards chairman in 1994. He has authored over 20 technical publications in the field of hardened component design and processing and is a senior member of IEEE. Lee Mendoza The Aerospace Corporation Lee Mendoza received his B. S. degree in applied mathematics and physics from the University of Wisconsi~waukee in 1978 and his M. S. in physics from the University of California at Los Angeles in 1980. He has been employed by The Aerospace Corporation since 1980, currently as the lead project engineer for the Early Warning Systems Program Technology Office. Mr. Mendoza has provided systems engineering and integration support in on-board processing systems and technologies for the Boost Surveillance and Tracking System (BSTS), Advanced Warning System (AWS), and Follow-on Early Warning System (FEWS) programs. In the technology office, he has had a strong role in the development of 32-bit radiation-hardened processors and memories. He has also been very active in the Qualified Manufacturers List (QML) program as an auditor at QML Validation reviews,
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1995 NSREC SHORT COURSE
/. ., (4iiii+ “’” -- :4
*
NSREC ’95 MADISON
SINGLE EVENT EFFECTS (SEE) QUALIFICATION
William Naval
J. Stapor
Research
Washington,
Laboratory DC
20375
This work was supported in part by the Naval Research Laboratory. II-1
SI-NtiLM MVMN”l’J!XNJ!L..-lS (SM!J QUA.JJFICATKJN WILLIAM J STAPOR NAVAL RESEARCH LABORATORY WASHINGTON DC 20375 1.0
2.0
3.0
4.0
5.0 6.0
7.0
Introduction 1.1 SEE Chronology and Definitions 1.2 Concept of Cross Section Single Event Effects (SEE) and the Space Environment Ground Based M easurements 3.1 Accelerators and Ions 3.1.1 Protons 3.1.2 Heavy Ions 3.2 Procedures to Collect Data at the Accelerator 3.3 Laborato Simulators and Tools Y 25 Cf 3.3.1 3.3.2 PUkd Lasers 3.3.3 Microbeams 3.4 Procedures to Collect Data Using Simulator Tools Prediction of SEE Rates 4.1 Methodologies 4.2 Commercial Modeling Codes (CREME, Space lladiatio~ etc.) 4.3 Problems with the Predictions (Realism, Enviromnen~ Statistics, etc.) 4.4 Issues in Single Event Rates 4.4.1 Discrete Devices, Components, Circuits, Systems 4.4.2 Level of SEE Rate Tolerance 4.4.3 SEE Hardening and/or Mitigation Hardness ksurance Test Methods Future Trends 6.1 Increased Device and System Complexity 6.2 -c and Static Operation Better Environmental Models 6.3 6.4 Meaningful Ground Data 6.5 Meaningfid Space Data Conclusions 1.0 INTRODUCTION
Single events have played and continue to nuclear and space radiation effects. As a simple Transactions on Nuclear Science December issues this conference) from the past 15 years beginning II-3
play a major role in the business of measure, let us consider the IEEE (notably the premier publication of with 1980. The single event papers
from only the Single Event specified sessions have strongly averaged nearly 18 + 4 papers out of 100 * 18 papers (or about 18% at least) with a slight increase (0.4 papers per year) and no obvious decline in sight. At this conference last year, the single event session was split in two, and this year there are three single event sessions (NonDestructive Single-Event Effects, Destructive Single-Event Effects, and Space SingleEvent Effects) to accommodate the increasing number of papers. One can readily see how large this role has bee~ and we have not even considered the European IL4DECS or the LA Single Event Effects (SEE) Symposia. Clearly this average 18% mark indicates that single events have held significant importance to our community and to the aerospace community in general. Believer, or skeptic, single events from nuclear and space radiations are real and ultimately unavoidable in nature, especially as we enter a new age utilizing more “commercial technological stufl” that was not originally conceived or developed with single events in mind. The challenge is to determine what to do with these effects so that low cost, high petiorrnance, advanced technologies become realities to the aerospace applications. Speaking of aerospace applications, anything is to fly it successfi.dly. Table 1 have “qualified” single event effects, some reader already knows of others where single
the only real way to ultimately “quali~’ contains a list of some space programs that more successfi.d.ly than others. Perhaps the events have been an issue.
Table 1: List of actual space programs that have “qualified” single events. SINGLE GALl LEO IANDSAT TDRS I(JS DSCS NAVSTAWGPS PIONEER VENUS SDS INTELSAT IV VOYAGER
EVENT
UPSETS
OBSERVED
SHUITLE HUT SPACE TELESCOPE OPEN AMTE GEOSAT SMM DMSP TIROS N LES8 & 9
IN SPACE CRRES ERS-1 ETS-V LEASAT METEOSAT-3 HUBBLE UOSAT CENTAUR MAGELIAN CLEMENTINE
This portion of the short course concentrates on single event effects qualification techniques. It directly addresses our challenge, ‘what to do.’ No previous knowledge in this area is required to understand or participate in this part of the short course, because the problem area is described in a general way, without pedantic details, however, with emphasis on practical effort. It will become evident that this stuff on single events (especially when considering SEE qualification techniques) is arbitrarily complicated and therefore difficult, if not impossible to understand. In a problem area so widely varied and rapidly changing in parameter space, it is possible that there are no “experts.” There are only “damned fools” and “novices,” (and I’m no novice). A reasonable goal of this
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SEE discussion is to give the short course students a clear overview of the general SEE problem so that they maybe at least able to take appropriate steps when investigating and solving SEE problems and issues. This discussion begins with some brief definitions or really descriptions of the classically accepted single event effects followed by the importance of the concept of cross section to the single events problem. Everything else that follows will lead the student (hopefidly) to an awareness of ‘what to do’ for single events. We will very briefly look at the space environment as it relates to single events to make all aware of the various regions and sources. There is great complexity to the space environment. It is not homogeneous, isotropic, or even static which greatly complicates the SEE problem. Next we will investigate what I consider to be the most essential part of SEE qualificatio~ the ground based measurements and discussion on various sinndations of radiations for single events. The ground based tools are essential to ultimately be able to predict or determine the scope of single event type problems in radiation environments. A discussion on the prediction of single events will follow with the intent to bring awareness of different methodologies emphasizing practicality. Afler these first four sections, the discussion will turn to description of existing documentation, guides, and standards. These have served the community well, but may be over-ambitious in the attempt to “cookbook” the single event problem. And lastly, before the conclusion of this part of the short course, the discussion will be directed towards fiture trends and issues which will undoubtedly bring new challenges as materials, devices, integrated circuits, sub-systems and systems become ever more complex and diverse. In the most generic sense, single event effects may occur whenever charge is deposited in electronic devices by energetic ionizing radiation from outside or within the devices themselves. Before discussing specific single event effects details, there are really only two categories of single events that are meaningful, destructive and nondestructive. Destructive single events are not acceptable. Non-destructive single events can be trouble to any system, but usually, they can be tolerated or mitigated with some carefid considerations. The SEE qualification of anything requires knowledge of the destructive or non-destructive mture of the possible single event effects. If a particular SEE in any component or device is destructive, then the device must be eliminated from potential use in any system. If the single events effects in any component or device is non-destructive, then SEE qualification requires knowledge of scope of the problem so that designers can make reasonably accurate assessments of risk and impact to their desired performance. Ideally, we would like to build systems from parts that do not undergo SEE. However, the reality is that with present (and projected) technologies, SEE will occur in space systems and it behooves us, therefore, to attempt to understand the problem area and do the best we can to make our best technologies work in aerospace applications. Let us begin with a ftily extensive discussion on definitions and concepts. These are by no means complete or exact since the field of SEE study is so widely varied. They are meant to provide basic information to the starting point of the SEE Qualification process. At the II-5
same time this discussion is meant to give the reader a general idea of the overall variety and complexity of the problem. 1.1 SEE CHRONOLOGY
AND DEFINITIONS
It maybe useful to SEE novices (and perhaps entertaining to SEE experts) to look at SEE “definitions” and concepts in a historical manner. This is an attempt to put some substantial historical and technical reference well in our path before going into any qualification details. To start, Table 2 contains a list of some of the important SEE acronyms in the business with the associated brief descriptions and the year of earliest reference. This list is by no means complete, but is intended to give the reader some immediate idea of the multitude and complexity of possible single event effects and issues. The list largely contains the most common classical single events accepted by the community. The rest that follows are discussions containing the SEE acronym definitions (when invented), as well as concepts and important observations in chronological order. Included with each is a the earliest technical reference, a reasonable definition, and a brief discussion. Table 2: Single Event Effects acronym list. LIST OF SINGLE . SEU ● SEL
I
. SET
SINGLE EVENT
● SED . SEB
SINGLE EVENT SINGLE EVENT
●
SEGR
. SEMBE c SEIDC
EVENT
EFFECTS
IN MICROELECTRONICS
ACRONYM SINGLE EVENT UPSET SINGLE EVENT LATCHUP
SINGLE EVENT RUPTURE SINGLE EVENT ERROR SINGLE EVENT CURRENT
EFFECT BIT FLIP DIGITAL ELEMENT FAILURE IN CIRCUIT ] OPERATION TRANSIENT I CURRENT TRANSIENT IN DIGITAL OR ANALOG DISTURB BIT UNSTABLE EQUILIBRIUM BURNOUT DESTRUCTIVE BURNOUT OF A MOSFET GATE DESTRUCTIVE RUPTURE OF MNOS OR SNOS MEMORY MULTIPLE BIT MULTIPLE BIT ERROR FROM SINGLE EVENT INDUCED DARK DARK CURRENT INCREASE IN CCD
●
✎✎✎
✎✎✎
✎✎
●
SE?
SINGLE EVENT ?
NOT YET DISCOVERED
YEAR 1979 1979 1983 1984 1987 1987 1989 1989 ✎✎✎
199?
It is most interesting to note that the concept of the possibility of single particle induced effects in microelectronics was first speculated on in 1962, only 15 years after the invention of the bipolar transistor. Then it took another 15 years before single events were actually observed. This 30 year interval illustrates that the initial progress of a device technology towards smaller and denser circuits was relatively slow as compared to the rate of technology progress today. Let us begin with that 1962 speculation.
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1962- COSMIC-RAY UPSETSOFA4.lcmcnwurrs
[1]
Remonable definition A bit flip (upset) in a microcircuit ionization fi-om a heavy ion msrnic ray traversing the circuit.
caused by local
Jn a paper that was considerably ahead of its time, Wallmark and Marcus of RCA predicted in 1962 W as microcircuit feature sizes ccdnued to be made ever da, M point would be reached that microcircuits would start getting upset by the direct ionization of heavy ion cosmic ray tracks and by cmmic ray induced spallation reactions. They were, however, timed in @imat@ that feature sizes could not go much below 10 pm. This paper was largely overlooked until this effect actually started to be observed both on the ground and on orbit in the middle and late 1970’s. 1975- COSMC-IUY UPSETSN llrMLoP
Cntm
ONSPACESATELLITES[2]
Reasonable di?j?nition A cosmic ray upset is an upset in a microcimuit caused by the direct ionization of a heavy ion cosmic ray that has traversed the microcircuit. It is usually a bit error. Partly because the nurnlxr of upsets observed was d, the claim made in this paper by Binder et al., that the flipflop upsets were due to cosmic rays in the “iron grcq” was disputed by most radiation effi experts. The paper was remmkable in that it already showed how to calculate the rate at which cmm.bray upsets could be expected and in that the calculations reported therein were within a fhctor of two of the number of upsets tiy observed.
Reasonable akj?nition A soil error is a non-dam@ng emr in a microcircuit caused by local ionization from an a-particle, a heavy cosmic ray ion traversing tie microcircui~ or fim a nuclear reaction. It is usually a bit enor and maybe wrected if it is found. Random “soft emcq” began to appear as a serious reliability problem in large dynamic IL4Ms in the middle 1970’s. In 1978, May and Woods discovered that the cause of these random “soft errors” were trace amounts of alpha-particle-emitting uranium and thorium isotopes in the materials from which the microcircuits were made. The upsets did not permanently damage the RAMs aud so were called “soft errors.” Reports of this discovery reached the radiation effects cmn.munity and had an impact on it in 1978, i.e. before the paper was published in 1979. 1978- SINGLEPARTICLEErutoru [4],[5]
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Reasonable dejnition Single particle emors are those that are caused by the direct ionizxition iiom a single ionizing particle, such as an cz-parlicle or a heavy ion cosmic ray which has traversed the microcircuit This paper reported a model for calculating the cosmic ray bit error rate in an operating satellite memo~ which consisted of 24 NMOS RAMs, each with 4096 memory bits. The upsets were explained as being due to direct ionization from cosmic mys in the “aluminum” and “iron” groups. The number of upsets observed on this satellite was large enough to be convincing, and it was this paper that particularly alerted the space and nuclear radiation effkcts community to the existence of a new aad important radiation effect Also in a 1979 paper, Ziegler and Landford discussed the effkds of cmn.ic rays on computer memories and developed a scheme for calculating upset rates. 1979- SINGLEEVENTUPSETS(SET-I)[6] Reasonub2e dej%zition A single event upset is a bit flip in a digital element that has been caused either by the direct iotition from a traversing particle or by the ionization produced by charged particles and recoiling nuclei emitted from a nuclear reaction induced near the microcircuit element. Most ofte~ the upset is nondamaging and can be corrected if found. This paper reported upsets due to 14 MeV neutrons and 32 MeV protons in 4K and 16K dynamic NMOS IU4Ms. First upsets were observed at neutron fluences of 1E8 neutnms/cm2 and proton fluences also of 1E8 protons/cm2. In particular, the discove~ that dynamic FL4Ms were vulnerable to such low neutron fluences was startling at the time because dynamic RAMs were majority carrier devices and were expected to be hard to neuh-on fluences three to four orders of magpitude larger than the observed 1E8 neutrons/cm2. It was clear in these measurements that the neutron induced upsets had to be due to nuclear reactions such as the ?3i(La) 25Mg reaction in which case the ionization causing the upset would be due to the emitted energetic a-particle and the recoiling 25Mg nucleus. The term “single particle” was therefore not appropriate for such upsets. For the protons also, direct iotition could not produce enough charge to upset the microcircuit and a nuclear reaction had to be the cause. For these reasons the paper was entitled “Single Event Upset of Dynamic RAMS by Neutrons and Protons.” This was the first use of the term “Single Event UpseG (SEW,” and this term was quickly accepted and used in the radiation effects community. A 1980 paper by Campbell and Wolicki [7] fi.wther showed the inappropriateness of tie term “single particle” because the upsets reported in that paper were caused by single high energy photons which induced photodisintegration nuclear reactions in the silicon. (Note: This was the first paper that discovered a deleterious radiation effect caused by a single photon!) 1979- SINGLEEVENTLATCHUP(SEL) [8]
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Reasonable dij?nitiom A single event Iatchup is a circuit “latchup” (or nonfimctionality) caused by the local ionization from a traversing heavy ion or tlom a nuclear reactiom SEL can be nondestructive or destructive. In CMOS circuits sometimes an SEL can trigger large supply currents which can be &maging to bond wire attachment (or the semiconductor material itself) if the circuit is not protected by current limiting measures. A Iatchup maybe a serious system problem because latchups usually persist until power to the latched element is cycled. Kolasinski et al. reported the first obsemed SEL. This paper reports experiments that were performed with high energy heavy ions iiom an accelerator and was the first observation of heavy ion induced Iatchup. Since then SEL has been a ve~ important consideration in SEE performance for any space system. 1980- CMOS IUM COSMIC-RAYINDUCEDERROR-RATEANALYSIS[9] Reusonuble definition A detailed analysis model was developed for predicting the galactic cosmic-my induced bit-error rate in CMOS RAM devices. Although the 1975 Binder-Smith paper already contained a way of estimating cosmic-ray induced error rates, it was largely overlooked and did not influence the community. The Pickel and Blandford paper reported the development of the “CRIER” model descendants of which are still in use today. Their CRIER model used closed form expressions for a path-length distribution fimction through tie sensitive regions of a device and a l.iuear charge deposition spectrum for the cosmic ray environment to determine the bit error rate (errors per bit per day). 1980- ALPHAPARTICLEEFFWRS rNCHARGE-COUPLED IMAGESENSORS[10] Reasonable dejnitiom A change in the charge stored in individual pixels or cells due to the ionization produced by single alpha particles. This paper by Ko seems to be the first to look at single alpha particle efkcts in a CCD image sensor. The paper reports changes in the charge collected from individual cells as a result of single alpha “hits” and also reports overall total dose effkcts on dark current and charge transfer efficiency. 1981- CHARGEFUNNELING[1 1],[12],[13]
Reasonable dej?nition The extension of charge collection iiom an ionization track to a region beyond the original depletion depth is called a Wmnel” and the extra charge collection from this funnel is called “charge funneling.” The calculations in these papers showed that if an ion track traverses a reverse biased semiconductor junctio~ the density of ionization can be so high that the resulting current flow collapses the field across the junction aud the collection of charge from the rI-9
track reaches fhrther into the semiconductor than the original depletion region. The extension of the collection region is ulled a “fhnnel” or “field fi.mneling” and the collection of charge fbm this region is called “charge funneling.” The paper by Hsie~ Murley, and O’Brien caused considerable controversy at the time because many semiconductor experts refused to believe that a heavily ionized track could cause a field collapse and a resulting charge ‘Yiumeling” in a semiconductor. 1981- FAULTTOLERANTMmoms
FORSINGLEPARTICLERADIATIONEFFECTS1981 [14]
Reasonable a%finition Fault toleraut techniques such as error detection and cmection codes (EDAC) and spatial configurations (e.g. to avoid having adjacent charge collection volumes in the same digital word) can be used to reduce the impact of single particle upsets on memories. This paper addresses the use of fkult tolerant techniques (developed by the reliability community to rninimk effects from electrical noise, transients, etc.) The use of EDAC is mentioned. Also, the memory organization and computer protocols presented in the paper extend the suscqtibility reduction to latchup and to multiple soft or hard errors in a common memory “word.” It must be noted that there is a trade+ff in the use of EDAC techniques, i.e. there is a cast to performance. This performance cost is larger for larger bit error detection and mrrection schemes. Extensive sometimes caunot be used because the compromise is too great which renders the system or components ineffective by def&ating the @onnance advantages. Care must be taken to undmtand the EDAC tradedfs to performance. 1981- SINGLEEvmrr UPsm Reasonable single events.
m MICROPROCESSORS ANDLooIc DEVICES[15],[16]
akjinitio~
Upsets in microprocessors
snd logic devices caused by
W.E. Price et al. and C.S. Guenzer et al. were the first two papers to report SEUS in microprocessors. The Iirst ref~ce also observed upsets in combinatorial logic devices. This work was important because fault tolerant techniques such as EDAC codes could not be used in logic devices and the effects of single bit errors in logic devices could lead to disastrous consequences as, for example, if an instruction word or address change could turn on a thruster rocket on a space system. The Guenzer-Campbell-Shapiro paper reported that many of the errors caused the microprocessor to cease normal operations. This latter paper also was the iirst report of logic upsets in microprocessors from neutrons. 1981 - USE OF w ION MICROBEAMm Sm-mY SINGLEEvm’r UPSETSm MICROCIRCUITS [17],[18] Reasonable Definition. The use of an ion microh with dimensions as small as device cell sizes, fiwm an accelerator to study charge collection and SEUS in microcircuits.
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Van de =accelerator microbeams ranging in size from a 2.5 pm diameter hole uptoa250 ymbyllOO p.rnrectan@ar apertumwere usedtostudy single event upsets and charge cd.lection in microcircuits. The ions used were protons, helium ions (a-particles), snd nitrogen ions. Di.f&ent threshold energies and sensitivities were found for sense amplifiers, normal cell areas, snd inverted cell areas. This paper also reported for the first time that the sensitivity of microcircuits to single event upsets can be increased as a result of the accumulation of total dose in the device. 1982- UPsm ERRORDETECTION~
CO~ON
(EDAC) IIW_EGRATED Cmcurrs [19]
Remonable De@nition. Single event upsets in EDAC integmted circuits which are themselves supposed to detect and correct errors in other microcircuits. This paper reprted the first single event upsets in EDAC integrated circuits. This finding was important because, as mentioned earlier, EDAC circuits are themselves supposed to detect aud correct errors in other microcircuits. In memories, particularly, EDAC circuits and algorithms mu be designed to detect and correct even more than one error in a digital word. Two types of EDAC circuits were tes@ only one of them showed upsets with 40 MeV protons and neither type showed upsets with neutrons. If the circui@ that provides the error protection upsets itself, then obviously, there can be no confidence in the uhimate performance which maybe critical in some applications. This sort of _ points to an important area for SEE qualification in terms of using EDAC schemes. 1982- SNGLE Em
ERRORIwurm
CMOS RAM [20]
Reasonable Dejnition The circuit of a CMOS RAM was redesigned SEU sensitivity of the RAM was greatly reduced.
so that the
report of using resistive decoupling to decrease the sensitivity of a lli.s was the first RAM to single event upsets. Essentially this decoupling technique used the fhct that the charge collection puke from a single ionizing event was much fhster than the opemtion of the memory cell. By slowing down the response of the cell to a charge collection puke, the sensitivity of the cell to upset was greatly reduced while the normal operation of the cell was not a&cted.
1982- SEU Mm? SCALINGN VLSI DEVICES[21] Reusonuble Definition. In a given cosmic ray environmen~ microcircuit upset rates depend on device fsize and critical charge for upsetA simple method of calculating cosmic ray upset rates was developed. This method was then used to study upset mtes as a fi,mction of device size aud critical charge for upset. Although the critical charge was shown to decrease as a fimction of fwture size, perhaps surprisingly; for a given cosmic ray environment the error per bit per day did not
11-11
increase significantly as the fsize became smaller. Part of the reason for this eff’t is that as the fwture size decreases, the probability of a “hit” in the cell area decreases approximately as the square of the linear dimension decrease. 1983- SINGLEEvmrr Tmmslm
(SET) [22]
Reasonable Definition The km “Single Event Transients,” is so general as to de~ easy definition. It maybe usefid, however, to take as a particular meaning for this term the situation in which a single event charge collection at one location in a combinatorial logic circuit is propagated down a path (“pipe”) such that the actual upset occurs at a location at some distance from the original charge collection. In non-storage logic, voltage transients produced by a single ionizing event may propagate down a logical “pipe” to reverse the state of a latch “fed” by the “pipe.” The criteria for the propagation of the voltage transient are discussed in the paper. This paper by S.E. Diehl et al. examines the usefidness of resistive and capacitive SEU hardening techniques for logic circuits. 1983- SEU FIGUREOFMmrr [23] Reasonable Definition. An approximate calculation for the number of upsets per bit per day is given which uses tie cell area and the threshold LET for upset For a 10% wonst case differential spectrum in cosmic ray LET values, a threshold value of LET which can cause an SEU, and for the area of a device cell, a formula was derived which gives the approximate SEU error rate in errors per bit per day. This formul~ which is just an algebraic expression does not require the use of a computer program yet gives an etite of error rate tit has been found usefid by space system designers. 1984- SINGLEEVENTDIsm
(SED) ERRORS[24]
Reasonable Definition. An SED error is an error in a static IU4M cell which is initiated or disturbed by a single event ionization such that it will, by itself, return to its original state. In some high density static R4M designs, however, the disturbed state can last for milliseconds and a reading of the bit during that time will be erroneous. In some high density static RAM designs a memory bit can be misread for milliseconds after a single event interaction that disturbs it but does no~ finally, cause upset. Computer simulations demonstrate that disturb errors have critical charges less than or equal to those for logic upset, Errors due to “disturbs” cannot be prevented by resistive decoupling and elude single event error testing methods that are not designed to catch disturb errors. 1984- CHARGECOLLECTIONINMULTILAYERSTRUCTURES[25]
II -12
Reasonable Definition. Fast and slower charge collection measurements have been made on special layered device structures which are representative of CMOS and bipolar silicon semiconductor layers. Charge collection was studied in special layered device structures with micmbeams of ions of oxyg~ chlorine, and copper. The charge collected fi-om the various layers was studied as a function of ion type, energy, and angle of incidence. Both fast and slower charge collection was measured. For the first time, the existence of both polarities on a circuit node, after the passage of a charged particle, was seen in certain cases. The charge collection process was seen to be more complex than would have been expected form single junction measurements. The measurements also demonstrated the necessity of using at least nanosecond time resolution to look at the transient currents flowing in the device. 1984- SEU lUATEESTIMATESFORTHEEARTH’SPROTONBELTS[26] Reasonable De~nitiom A one-parameter model for predicting the SEU rate in the earth’s proton belts fi-om a measurement of the SEU cross section at a single proton energy. A one parameter model is developed that can estimate the SEU rates in the earth’s proton belts from a measurement of the proton induced SEU cross section at just one proton energy. The model is semi-empirical and comes km the observation that proton upsets are due to nuclear reactions which is an energy dependent phenomena. The one parameter in the model is related to the proton energy threshold to produce an upset. Later research determines that the one parameter model is inadequate for modern technologies and that a second parameter is required to make accurate proton upset rate predictions. [27],[28] 1985- IONTRACKSHUNTEFFECTSm MULTI-JUNCTIONSTRUCTURES1985 [29] Reasonable Definition, For heavy ion hits across multiple p-n junctions in bipolar transistcms and CMOS structures, a resistive ion track shunt was observed bridging two like conductivity regions, The dense ionization of a heavy ion track traversing multiple p-n junctions can cause the development of a resistive path or “shunt” between the layers traversed. It was found thai the charge collection at a given p-n junction is influenced and can even be changed in sign by voltages present at a second p-n junction when the ion track penetrates both junctions. This paper reports the first observation of such a “shunt.” 1987- LASER SIMULATIONOF SINGLE-EVENTUPSETS 1987 [30] Reasonable Definitionmicrocircuits.
A pulse picosecond laser was used to produce upsets in
This paper reported the first use of a picosecond laser to produce SEUS in microcircuits. Comparing the laser energy necessary for producing upsets showed that a
II -13
laser could measure circuit sensitivity to SEUS. Furthermore the small size of the laser spot could be used to ident@ single sensitive trausis-tors. 1987- SINGLEEvmr
EFFECTS(SEE) OR SINGLEEm
PHENOMENA(SEP)[31]
Reasonable Definition Single event effkcts or single event phenomena are the generic terms used to identi~ any observable effi in a microcircuit that can be attributed to the local ionization produced either by direct ionization or by a nuclear mwtion. When the first single event Iatchups wm obsemed it became obvious that the term “single event upsets” was no longer adequate and that a more generic term was needed to describe other effkcts or phenomena that could be caused by single local ionizing events. Single Event Phenomena or SEP came into use, as discussed above, in 1982, Single Event Effects or SEE was fit used in 1986. There is no clear distinction between them and perhaps SEP is somewhat more general thau SEE. 1987- Sm EFFEH OFIONTwxs
ONSINGLEEvmr
MULTIPLEBm UPSETS[32]
Reu.sonuble Definition Double-bit physical upsets caused by a single particle tie in the proximity of satellite memory cells may be explained by track sizes that are larger than previously postulated. A high ratio of multiple (5 to 10%) to single-bit rates over a two-year period was reported on a satellite subsystem. The probability of consecutive hits was estimated to be negligibly small. The explanation given in this paper is that the ion track diameters are larger than previously postulated. However, it must be noted that all double-bit upsets are not necessarily physically adjacent bits in a device. 1987- SmGLE Evmvr Bumou’r
(SEB) [33]
Reasonable Definition The plasma filament (charge track) from an ion traversing the power MOSFET structure, causes an avalanche breakdown between the n-epi and n+substmte regions and produces a burnout and permanent darnage at this interface. The plasma filament (charge track) tim an ion traversing the power MOSFET stmture causes current to flow hm the source to the drain. Since the n+-drain cannot supply holes to the filarnen~ a negalive space charge layer immediately builds up at the nepi-n+ substrate interface until the resulting field causes avalanche breakdown and a permanent burnout. 1987- SmGLE Evmr
GATERummw (SEGR) [34]
Reasonable Definition SEGR is permanent darnage, i.e. a rupture in dielectric gate materials due to avalauche breakdown caused by the traversal of a heavy ion.
II -14
Heavy ion induced hard errors had been observed in some types of microelectronics circuits, particularly in nonvolatile metal-nitride-oxide-semiconductor (MNOS) and siliconnitride-oxide-semiconductor (SNOS) memories. In this paper heavy-ion induced ftilures in SiOz and SiO#3i~N1 composite capacitors were studied for LETs from 15 to 85 MeV/(mg/cm2). Among the findings were: 1) Hard errors are caused by a combination of energy deposited by the ion and from electrical conduction through the plasma channel formed by the ion strike and 2) there is an inverse linear relationship between the ion energy deposition and the bias voltage required to produce composite device failure. 1988- CHARGECOLLECTIONFORIONSOF SAMELET BUTDIFFERENTENERGY[35] Reasonable Definition. Charge collection from ionization tracks produced by ions with the same LET but different energies is different and the differences cannot be explained alone by uncertainties in energy loss calculations. This paper reports the first charge collection measurement for ion tracks produced by ions with the same LETs but different energies. The amounts of charge collected were different and the differences could not be explained by uncertainties in energy loss calculations. A possible explanation is the differences in initial track structure. The higher energy track is more diflhse and may yield more charge to be collected because there is less initial electron-hole recombination. 1988- SEU ERRORSINVLSI LOGICDEVICES[36],[37] Reasonable Definition.
Errors in VLSI Logic devices caused by a single ionizing
event. In these papers Newberry identified two new types of SEU errors in logic devices. One was a “lost data” error. Such an error occurs when one of the control bits in a word, is changed in such a manner that a single word does not get to the output. A control bit is defined as any bit contained in a word in addition to the data. The other words in a data stream (at the output pins) remain intact. Data stream refers to the series of commands, operations, or words initiated and anticipated at the output during a device test. In the second type of error, called a “lost data path”) a control bit is changed in such a manner that the entire data stream is lost (i.e. it does not reach the designated output pad.) These errors have been observed in testing of VLSI logic devices. The “lost data path” in particular, can result in significant system-level failures. Because of these ftilures and the potential for catastrophic system-level results, it is imperative to harden VLSI logic devices against SEU. The paper then discusses six hardening options. The six methods, in brief, are: a) increase the channel width of sensitive devices thereby increasing the critical charge for upset, b) increase the operating voltiges, c) in the logic cell design, increase the loading on sensitive transistors thereby impacting critical charge and error propagation, d) use multiple input cells, thereby reducing the probability of error propagation through interconnected cells, e) isolate critical fi.mctions and use SEU hardened components for them, and f) adjust the timing or use a distributed reset approach to reduce the errors observed a output pads. 11-15
1989- SINGLEEVENTMULTIPLE-BITERRORS(SEMBE) [38],[39] Reasonable Definition. SEMBE was first defined as multiple-bit errors produced in physically adjacent cells by a single ion event or track. For a penetrating ion, the electric field is restored before all of the charge is collected. The remaining charge is transported by diffision. That portion of the charge that diffises to (or along) the surface of the chip may be captured by other charge-collection junctions. By contrast, if an ion track does not intersect a junction, nearly all of the charge is transported by diffbsion. Charge collection in this case is more widely distributed. Lateral charge transport from single-ion tracks can lead to multiple-bit errors in IC chips. Although this paper does not discuss ion tracks that lie in the plane of the chip, such tracks can also produce multiple bit errors but they make them directly and do not require a mechanism of lateral charge diffusion. SEMBE has subsequently been expanded to include multiple bit flips fi-om single events that are not physically adjacent. [40] Multiple bit errors in the same logical address are particularly troublesome and require more extensive error correction schemes to recover. 1989- SINGLEEVENTDARKCURRENTINCREASESINSILICONCID IMAGERS [41], [42],[43] Reasonable Definition. SEIDC is single event induced displacement damage in a single CID pixel accompanied by an increase in dark current so that the pixel is no longer usable. Low energy Coulombic interactions can cause large, although rare, displacement damage events. Such events can be analyzed by extreme value statistics. The effects of displacement darnage on dark current in individual pixels can be enhanced by high electric fields. The increases in dark current from displacement damage thus can be device dependent. The combination of the large rare darnage events and the electric field enhancement lead to increases in individual pixel dark currents that far exceed the increase expected solely on the basis of the amount of displacement darnage produced. 1993 - TOTAL DOSE FAILURES IN ADVANCED ELECTRONICS FROM SINGLE IONS [44], [45],[46] Reasonable Definition. A “hard error” produced in a device as a result of the ionizing track fi-om a single ion. In 1981, Oldham and McGarrity examined the possibility of a total dose failure from the passage of a single ionizing heavy ion and concluded then “that such failures were a long way off.” Koga et al. in 1991 and Dufour et al. in 1992 observed such errors. In the 1993 paper Oldham et al. conclude that hard errors fi-om single heavy ions traversing gate oxides “are to be expected and should not be considered surprising.” The mechanism is simply that, if the transistor is small enough, the total dose produced in the gate oxide by a
11-16
single heavy ion may change the threshold of the device beyond its operating range. also the discussion of SEGR above, 1987.)
(see
1.1 CONCEPT OF CROSS SECTION It is evident that there are several types of single event effixts, the most noted being SEU. No matter what the effect or how very different the outcome, they all have one thing in common, the device single event cross section, a. In the most generic and simple fonnulatio~ this cross section is defined in the following Equation (1) as,
u
(1)
“F where U is the number of events and F is the fluence (usually expressed in particles/cm2), so that u is defined as the number of events per unit fluence. This simple definition addresses the fi.mdamental question of how many particles per unit area does it take to produce the signature single event. It is in this definition that all single events are related. It is in this definition that any ground based qualification begins. Like most true “cross sections,” the meaning is geometrical, expressing an “area” of observed single event sensitivity. The single event cross section is simply the number of observed signature device events, U, (whether they be upset, Iatchups, etc.) divided by the fluence, F, of particles per cm2, with which the single device under test has been irradiated. The only constraints on the measurement are that the beam diameter of the irradiating fluence be large compared to the device dimensions and that, within that diameter, the beam particles be distributed uniformly. Virtually any type of single event can be quantified by this relation. Any sort of single event signature in any type of device, whether it be upse~ latchup, burnou~ gate rupture, or anything that can be uniquely measured as an eveng can be associated with a fluence to achieve that event. This quantity when known over the appropriate parameters allows us to estimate the rate in any application where there is particle radiation and that particle radiation is reasonably known. The issue of single event rate is the essential issue in SEE qualification. The question of SEE rate for the application bounds the probability in time and gives meaning and scope to the possible solutions of SEE problems. In additio~ the SEE rate allows assessment of the impact to the system, whether it be ultimately destructive or nondestructive to the performance. Some single events are meaningfid if they significantly impact successful spacecraft operatio~ while other single events maybe inconsequential. The cross section formulation gives a way to quanti~ SEE through direct measurement. It reduces half of the SEE rate problem to making measurements of U and F simultaneously as used in Equation (1) for the appropriate incident radiations and parameters specified by the environment. More discussion on the rate issue later.
II- 17
The statistical uncertainty associated with the cross section or any scientific measurement for that matter is also important. For any measurement the statistical uncertainty gives important information about the extent of the variability of the data. In SEE qualification it is important to be able to know this because the statistical variability from the measurement can be folded into the rate calculation to give an idea of the statistical range of expected rates from the cross section data. Following Bevington [47] the statistical uncertainty squared in o due to statistical uncertainties in the measurements of U and F is,
@“~=(%’92+(%42 (2)
where AU and AF are the statistical uncertainties in the number of events and fluence respectively. For counting experiments where the average number of “successes” is very much smaller than the total possible number (as in this case for SEE measurements where you have large number of potential single event targets) the statistics are driven by Poisson statistics. Therefore, the statistical uncertainties in U and F are AU and AF respectively and go as U’n and #n respectively. Taking the partial derivatives and substituting for AU and AF in Equation (2) leads to an expression for the statistical uncertainty in ISand is given by,
(3)
Equation (3) is useful in analysis of By plotting useful in SEE analysis. directly see the possible statistical appropriate analysis on the resulting yielded by the dataset.
the SEE cross section data. This quantity Acr is the two curves, u+Acr and also cr-Acr, one can variation in the dataset and then perform the curves to give the statistical range of SEE rates
From Equation (3), it is evident that SEE statistics are strongly driven by the number of observed single events, U, since the fluence, F’, issued in any measurement irradiation is usually a large number compared to U. Lastly, for zero observed single events measured, that is for WI in any measurement the statistics on U becomes U=l so that the statistical uncertainty in the SEE cross section is at least +1 00°/0 for large incident particle fluences. In this special case, the cross section takes on the meaning of being an upper limit, That is, the observed cross section is no worse than 1 event per the amount of issued fluence.
II- 18
2.0 SINGLE
EVENT EFFECTS
(SEE) ~
THE SPACE ENVIRONMENT
Energetic nuclear and space radiations come in many varieties fiwm photons to electrons, neutrons, protons, and heavy ions. It is the overall annual topic of this conkence to investigate and try to understand the consequences and impact of all such radiations on microelectronics and materials. However, not all ionizing radiations readily cause single events. To reduce the overall scope and to try to obtain a fi.mdamental appreciation and understanding of the SEE problem, let us consider only the natural space radiations, and only those components of radiations that can readily cause single events. (An excellent discussion on the overall basic mechanisms of radiation effects in the natural space environment can be found in the 1994 IEEE NSREC Short Course Notes by Jim Schwank.) When considering SEE and space radiation we need to be primarily concerned with protons and heavy ions. Each can cause single event effects, and it is important to emphasize that the mechanisms for the initiation of single events are different. Figure 1 shows a schematic of the difkent mechanisms to initiate single events from protons and pm 1 1 1 1 1
smwrlw
m
heavy Ion
1
1 I1 I
VOLUME
,’
/’
,
sENsrrlvE
NUCLEAR REACTION
1 1
VOLUME
gl
SENSITIVE VOLUME
1 1
DIRECT IONIZATION
L!l f’ t’
NUCLEAR EIASTIC REACTION
Figure1:
SEE initial mechanisms
ions. The arrows in Figure 1 indicate charged particle traversals in a schematic “sensitive volume” of a microelectronics device where the arrow thickness is roughly proportional to the iotition. Both proton interactions and heavy ions involve ionization but the source of the iorhtion is different. The protons themselves are ve ~ fil$flY iofig (e.g. a 60 MeV proton in Si has an LET of only= 0.008 MeV/(mg/cm ) aud usually cannot cause single
II-19
events via their own direct ionization (although there is a trend to the more advanced high performance technologies where this may become an issue). Protons, however, can have nuclear interactions in Si, either a inelastic scatter (or nuclear reaction) or an elastic scatter which results in one or more energetic high energy and high LET fragments traveling through the material depositing energy. If the energy deposited in the “sensitive volume” is greater than the minimum energy required to cause a single event then a single event may occur if the subsequent charge transport meets all the conditions. On the other hand, heavy ions have much higher LET and usually can initiate a single event on their own direct ionization with sufficient energy deposition and charge transport. Since protons initiate single events via some sort of nuclear reactio% not every proton trajectory through a sensitive volume causes a single event effixt. The typical single event production rate for protons in a modem microelectronics device is very roughly 1 in 105 protons traversing a sensitive volume causes a single event. At first thought this may seem like good news. However, there are many protons available in various portions of space and during Solar Flare conditions and many sensitive volumes so that the single event rates in space may be large, Energetic protons can be a significant part of the single event problem for many applications. As already mentioned heavy ions or cosmic rays can directly deposit sufficient energy in the sensitive volume to cause single events, so their single event effectiveness per unit particle seems higher than that for the protons. The fmt thought may be that heavy ions are deadly. However in the space environment in general, there are not significantly large flux populations of cosmic rays compared to the protons, so the heavy ion portion of the single event problem is not as ominous as it appears. Althou~ the heavy ions cannot be ignored in SEE Qualification because of the potential destructive impact.
II -20
.-.-r
mr--T ‘ ““ ~“
Pnorm
‘-
Eaxxm
______
-
,
-1
Ikvl
Figure 2: Trapped proton spectra for various thickness’ of a~~rber.
The main point for space applications and certainly for SEE qualificatio~ is that the environment is an important consideration. The space environment is not homogeneous or isotropic in radiation content. Figure 2 shows the trapped proton flux (in units of 107 protons/(cm2-year-MeV)) obtained horn the NASA AP8 model under Solar maximum conditions behind various Aluminum shield thickness’ as a fimction of proton energy (in MeV) for a particular orbit. The spectrum of protons described in Figure 2 is peaked at around 5x 107 protons/(cm~-year-MeV) between 30 and 60 MeV and shows non-zero l/E type behavior out towards the high energies. Figure 3 shows the relative abundance (in arbitrary units) of heavy ions with energies greater than 450 MeV/nucleon observed at 1 AU. The most abundant elements are hydrogen (or protons) and helium with the heavier elements being 2 to 5 orders of magnitude less abundant. Even though the heavies are relatively few in numbers compared to the protou they are quite penetrating due to their relativistic kinematics.
II -21
COSMIC 1000000
t
10000
AS OBSERVED
AT lAU
E
[ . 100000
RAY COMPOSITION
I [
H
>0.45 GeV
from JA. Lezniak and W.R. Waber, Aalrophya J., 223:1978.
+ 4He >1.8 GeV
‘2C>5,4 GeV ●
lEO
>7.2 GeV
☛
24Mg >10.8 GeV
**
. 100
.
●
‘% >12.6 GeV
.
●
{
.
●
.-
>25.2 ( 9V
‘Fe
●
10
n“
. m.
n
5ENi>26 I GeV E
.=m R
[
1
,
o
I
5
,
1
10
15
I
20
,
25
i
30
z Figure 3: Cosmic ray composition at 1 AU as a function of atomic number Z. The environment is not completely static, but widely dynamic in nature varying with many conditions and phenomena such ss Solar cycle, Solar wind, magnetic field etc. Figure 4 is a schematic representation of the Solar cycle “sawtooth” which strongly Figure 5 is a picture of the SEU modulates the near Earth radiation environment. radiation environment as seen be some devices flown on the CRRES mission fkom July 1990 to October 1991.. In Figure 5 one can readily see the effects of the proton belts for L-shell values less than 3 and also the occurrence of the March 1991 Solar flare around UT 450. A full description of the natural space radiation environment is well beyond the scope of this part of the Short Course and will not be addressed.
II -22
SOLAR CYCLE “SAWTOOTH”
FLARES
j
MINAND MAX CORRELATED
=3 + 8 YEARS+
1-
WITH SUNSPOTNUMBER
11 YEARS 4
FIARE BLAST MAGNETICFIELDCOLIAPSE ● CONSTANTSPECTRUM (1972 KING FLARE) ● ●
1996
Figure 4: Representation
CRRES
MEP
of the solar cycle “sawtooth.
SEUS
e
–
4
DEVICE A.E. NRL
A
C.mp&ll. cRR ES
TYPES
P.l_.McDomdd. ..d FliEht
Data
W.J.
Smpor.
Analysis
L-I. mni.
IM H
L-
Figure 5: Distribution altitude and time.
of CRRES
MEP upsets for four device types versus
II -23
R=) R=)
What k important for SEE qualification is to consider the application, and address the issue of what SEE producing radiation will be present throughout the mission. For example, if the mission will spend a lot of time and proximity in the proton belts, then protons are of major importance in assessing SEE impact and heavy ions of smaller importance due to the Earth’s magnetic shielding. If the mission is intended to spend time outside the proton belts, then the major contributor to the SEE impact would come from the heavy ion cosmic ray component, although there may bean occasional source of single event effects from Solar emitted particles including Solar flare protons. In addition, for low Earth applications where radiation is not a major factor, the South Atlantic Anomaly [48] (or SAA as it is commonly known) becomes a contributing factor containing populations of energetic protons trapped in the belts.
3.0 GROUND BASED MEASUREMENTS The most essential part of any SEE qualification process is ground measurements. While simulation tools derived from first principles may be useful in providing some indication of SEE device sensitivity, no reasonable predictions of actual performance may be made in the absence of data collected with actual devices. There are several factors to consider when approaching the questions of what types of measurements should be performed and how the data should be collected, some of which are: ●
●
●
●
Does data exist on other devices or technologies similar to the one being considered? If so, are the similarities sufficient to provide guidance and expectations for the anticipated response? Examining the measured response of similar devices and technologies can be valuable in forming a testing plan. Is the environment for the application known? As already mentioned the SEE response is partly a function of the incident radiation environment, and measurements for SEE qualification should be tailored to the target environment. Are simulator tools available to model and predict device response? Simulation tools tailored to the device being considered for SEE qualification can be a valuable resource in formulating an experiment plan Has a failure mode analysis been performed? When quali$ing complex systems, it is often useful to identifi critical failure modes and single points of failure. This analysis should also consider the operating modes and system software demands. Many systems are SEE fault-tolerant, obviating the need for SEE-immunity as long as the scope of the device and system response is well known.
II -24
3.1 ACCELERATORS
AND IONS
One of the considerations in the design of an SEE experiment is the target environment of the application. As seen in the previous section, the radiation environment in space is widely varied in compositio~ spectroscopic or energy characteristics, orbital position, time, and largely omnidirectional. The “environment” at a particle accelerator, on the other hand, tends to be monoenergetic and unidirectional. Therefore, ground-based measurements are, at best, an approximation of the space environment. Moreover, in the case of galactic cosmic rays, relatively low energy heavy ions are used at accelerators to predict the SEE response to much higher energy (but having the same LET) particles. It has been proposed that differences in track structure may lead to different SEE response even where ions have the same LET. [35] For all of these reasons, it is important to keep in mind that while particle accelerators are powerful tools in performing SEE qualification, you must give consideration both to their limitations and the differences between ground-based measurements and actual on-orbit conditions. 3.1.1 PROTONS Typical trapped proton spectra were shown in Figure 2 for various thickness’ of Aluminum shielding. As can be seem the typical spectrum is peaked around 50 MeV. There are a number of accelerator fmilities available which provide protons at these and much higher energies. As will be shown in the subsequent sections, in order to perform accurate modeling, it is necessary to make accurate measurements of the asymptotic cross section at a variety of energies, although fairly reliable predictions can be made with data from a single energy. Table 3 lists some of the facilities available in North America and the range of energies available at each. Table 3: Proton fmilities in North America and their approximate energy ranges. RANGE
FACILITY Crocker Nuclear Laboratory (UC Davis Cyclotron) Davis CA Indiana University Cyclotron Facility (IUCF) Bloomington IN Tri-University Meson Factofy (TRIUMF) Vancouver BC NRL Pelletron Washington DC Harvard Cyclotron Cambridae MA
II -25
OF ENERGIES 5-65 MeV
Up
to 200 MeV
Up to 500 MeV Low MeV & Micmbeem Up to 150 MeV
Every fhcility has unique characteristics and requirements. There are, however, some common fwtures and considerations when conducting radiation effects experiments with protons. Some of these are as follows: .
Due to their relatively long range in air, it is usual to irradiate targets without the use or hindrance of a sealed vacuum chamber when working with protons. This normally makes for fewer problems with cabling and electrical noise and provides relatively unhindered access to the DUT and associated measurement equipment. However, the i.mediations typically take place in rooms which are remote to the experimenters due to the radiation hazards of the high energy protons beams directly in open air.
.
The fluxes available at accelerators are normally several orders of magnitude larger than those encountered in space and as a consequence, it is possible to deliver on target years worth of fluence in a matter of minutes or even seconds in high beam current conditions. However, these high fluxes can lead to erroneous results and conclusions in those cases where a DUT exhibits a flux-dependent response.
.
It is possible, when dealing with typical and arbitrary high dose rates and high energies at proton facilities, to nuclear activate targets and the surrounding materials. It is important to closely monitor the level of radioactivity of targets and employ proper radiological safety precautions when handling these materials.
.
A critical element of any SEE qualification experiment is accurate dosirnetry and control of the beam. There are a wide variety of approaches taken in both these regards, but a facility like that in place at the UC Davis Cyclotron is ideal for this kind of work. Highly accurate dosimetry is accomplished by a computer controlled system that utilizes a special vacuum chamber containing a Faraday Cup/Secondary Emissions Monitor (FC/SEM) combination which is at the heart of the measurement system. [49] Experimenters are able to control start and stop of the beam according to a number of presets, dynamically monitor the progress of the run, and log all relevant dosimetric information as the experiment proceeds. Variations on this these theme are employed at various sites for both protons and Heavy Ions.
.
A consideration for protons that is not as important when conducting heavy ion experiments is total dose damage. It is not at all unusual to severely damage a target and thereby modi~ its SEE response in the course of conducting measurements. It is important to closely monitor parameters which give an indication of total dose degradation (such as, for example, DUT standby current) and where total dose performance is unknown, it is always a good idea to make initial measurements at a low flux and in small incremental irradiations.
3.1.2 HEAVY IONS Performing SEE measurements with heavy ions has some similarities to proton testing and some significant differences. In section 4 of these notes it will be shown that
II -26
while it is important to measure the asymptotic cross section, accurate determination of the threshold LET or critical charge has a far greater impact in subsequent modeling and event rate calculations. It is important, therefore, to be able to make measurements with a wide range of LET values. At heavy ion accelerators this is accomplished either by direct energy and species changes of the beam, or by changing the angle of incidence of the beam into the “sensitive volume” of the DUT to obtain what is called an “effective LET” value. The “effective LET,” or L~~~, is the beam LET divided by the cos of the incident angle 0 and accounts for the increased path length of the particle through the device. Table 4 lists some of the heavy ion facilities which have been used to perform SEE qualification. Table 4: Heavy ion facilities and their approximate heavy ions available. FACILIN
energy range for a wide variety of
RANGE
Brookhaven National Laboratory Tandem (SEUTF) Upton NY Chalk River Tandem Accelerator and Superconducting Cyclotron (TASCC) Chalk River ONT Berkeley 88” Cyclotron Berkeley CA NRL Pelletron Washington DC GANIL (France) GSI Darmstadt (Germanv)
OF ENERGIES
35-350
MeV
Up to -2.5 GeV
70-600
MeV
Low MeV & Microbeam up to 100 MeV/amu UDto 2 GeV/amu
As is the case with protons, there are some common issues to consider when performing SEE experiments with heavy ions. ●
Heavy ions of the limited energies typically found at accelerators have also a limited range in materials. For this reason, accelerator testing with heavy ions will be conducted within a sealed vacuum chamber of some kind. This arrangement can introduce some cabling and connection problems to your DUT and also make it somewhat tedious if not impossible to gain ready access to your device. Additional cabling makes it difficult to successfully operate devices and associated microelectronics at high speed and power. Experimental design should take this into consideration and your test plan should minimize the need to have physical access to the test structure or support electronics.
●
Because of their limited range, you also need to be sure to choose incident ion species and energy which will be able to penetrate the sensitive volume of your test structure and which does not suffer significant energy loss across this region (or if it does, to at least know what the residual range of the particle is in order to perform
II -27
accurate energy deposition calculations). It is a common practice to rotate structures through a series of angles and thereby increase the deposited energy or the effective LET of the incident beam (by increasing the path length through the material). However, at large angles, the sensitive volume may become shadowed by the packaging material or the increase in path length may introduce significant range and LET differences for the ion trajectories through the target material. Range and energy loss calculations should be performed when the target surface materials are known or accurately estimated. Simulation tools such as the TRIM code are useful in this task in minimizing these kinds of problems. ●
As is the case with protons, accurate dosimetry and beam control is an important factor in conducting heavy ion SEE qualification experiments. It is equally important to be able to accurately determine ion energy since the event threshold LET is so critical to subsequent upset rate modeling and calculations. Facilities such as Brookhaven’s SEUTF which provide an advanced dosimetric and beam control end station as well as a large target vacuum chamber with 5 axis target rotation are ideal for this kind of testing.
●
Dose damage is not a typical consideration when performing heavy ion testing but owing to the different nature of the interaction mechanisms of the heavy ions with the target material, some effects may be observed with heavy ions that are not seen with protons. As a consequence, it is not unusual to modify testing procedures and experimental software to be different for heavy ions than for protons. Single Event Latchup, for example, which is not unusual for certain kinds of devices when tested with heavy ions, is not typically of concern when performing proton testing.
3.2 PROCEDURES
TO COLLECT DATA AT THE ACCELERATOR
The procedures and methodologies employed to perform SEE qualification at an accelerator are as widely varied as the numbers of technologies, applications, and instrumentation available to perform them. Just as the definition of “SEE bnnzzme” depends not on some objective standard but rather on specific applications and needs, the parameters and types of measurements which are important are largely subjective. There are, however, some common considerations when performing experiments of this type. 1. Microelectronics devices are often capable of operating over a range of electrical characteristics. SEE sensitivity is often a function of parameters such as the chip supply voltage. When possible, measurements should be made which cover the range of such parameters if the application is not well defined. There is sometimes a tradeoff in this regard in that operating a device at a lower supply voltage may increase the SEE rate while decreasing total dose degradation. 2. Environmental conditions such as temperature may have a dramatic impact on SEE response. Designing an experiment where the temperature of a DUT can
II - 28
be controlled and measured is sometimes a difficult task, especially operating the DUT in a sealed vacuum chamber.
when
3. The SEE rate of a DUT may be (and often is) a fi-mction of total dose damage, especially for proton testing. It is important to be able to measure throughout the irradiation process some characteristic parameter of the DUT (such as supply current) as an indication of damage effects, and correlate this degradation with changes in SEE rates measured. 4. Some devices, such as DRAMs, are dynamic in nature while others are essentially static such as SRAMS. Others can be operated and tested either dynamically (a ~Processor) or statically (a pProcessor’s register page or cache). There can be significant differences between static and dynamic testing, and when operating a device dynamically, the clock timing of the operations (both the speed of the clock and the duty cycle as compared to incident beam flux) can have a dramatic impact on SEE rates. Static testing is normally useful in establishing baseline SEE rates, but gives an incomplete picture of actual SEE performance when studying complex devices such as processors (which could be the topic of an entire Short Course by itself). 5. Digital devices being studied in an SEE qualification trial may often display analog effects, such as latchup, single event disturb, and others. The impact of such effects at the system level rather than the DUT level should be considered and accommodated. In addition to general testing issues, specific classes of devices have unique aspects and considerations which often need to be addressed. For example: ●
SRAMs/DRAMs - When testing RAMs, it is not sufficient to simply count the numbers of upsets produced by a given fluence of incident particles. This approach provides far too incomplete a picture of the nature of the SEE response of the device. It is often useful to note, for each upset bit: 1.
The polarity of the upset - Was the transition from 1 to O or Oto 1?
2.
The location of the upset - This location should be both logical and physical address as well as the time of upset relative to any relevant refresh cycle or other timing waveform event.
3.
The numbers of multiple bit upsets - It is important to note the numbers of upset bits which are physically adjacent as well as which occur within the same logical address.
4.
The refresh rate - Upsets in DRAMs are often dependent refresh rate of the chip.
II -29
on the
5.
.
Other parametric information - Shifts in access time and the occurrence of stuck bits (imprinting) are often useful measures of degradation mechanisms within the DUT.
MICROPROCESSORS - The design of an adequate SEE qualification test for a microprocessor is a complex task owing to the complexity of the device itself, Microprocessors, in some respects, are best thought of as a collection of discrete devices with common circuitry and in fact can often be tested and operated in such a way that only specific portions of the chip are used at any given time. For example, some common regions of a typical CPU which are amenable to being operated independently include: 1. Registers/Cache - The processor registers and data/instruction caches can often be treated as simple static storage and testing in the same While there are usually a limited way you would test a SRAM. number of bits which can be directly addressed in this way, this kind of test can provide a usefhl baseline to the general SEE sensitivity of the chip itself. 2. Memory Management Unit - Most microprocessors chip MMU which can be exercised independently.
contain and on-
3. Floating Point Unit/Accelerator - On many microprocessors, the FPU (when it exists) is an independent and asynchronous element of the chip and can be independently operated with test vectors that generate a known result. 4. Central Processing Unit - Like the FPU, the CPU can be exercised with a set of test vectors like a finite state machine with the intermediate and final states compared against expected values. In addition to testing various regions of the microprocessor independently from each other, it is also important to examine their SEE response as a cohesive unit. In a complex device, an SEU may not manifest itself in an apparent way until a long time after the original upset, or it may propagate by physically and temporally far away from the site of the original event. In addition, a single upset at the right time or in the right place may exhibit a “fanout” of tens or hundreds of errors, or the upset may never manifest itself as an error at all. Only by examining both discrete areas of a complex device as well as how those regions interact can a complete picture of the SEE device sensitivity be gleaned. .
Gate Arrays - When evaluating devices like performance is often sensitive to the arrangement
II -30
gate arrays, the SEE of logic elements, and
distinctions should be made between combinational elements, and timing propagation differences.
and sequential
logical
.
FIFOs/Buffers - Devices such as FIFOS normally have inherent single point ftilure modes in their desigq such as the ring pointer. While is possible to measure SEE in the FIFO stack, a single upset in the ring pointer can effectively corrupt the entire stack and in these instances it is necessary to distinguish and quanti& these events.
.
ADC/DAC - In the case of devices such as this which have both digital and analog circuit elements, it is Use&l to distinguish between digital upsets and analog disturbances which lead to an apparent digital corruption and vice versa.
The design of a proper SEE qualification plan incorporates many aspects, as has been show including the utilization of other data on similar devices, information and analysis of the specific application where known, the selection of an accelerator faility which will adequately simulate the environment and the implementation of a test system which will properly and completely exercise and measure parameters and SEE response of the DUT or subsystem being considered. Having made these preparations, it is equally critical that the experiment be conducted with precision once on-site at the accelerator. There are some usefid things to keep in mind when conducting the actual ground measurements: .
Accelerator facilities are complex. It is helpfid to gain an appreciation of the procedures and operation of the facility in order to optimize data collection efforts. Moreover, these facilities are not always turn-key operations and delays and breakdowns are inevitable. Do not schedule run time so tightly that your plans cannot accommodate slippages.
.
Keep detailed records of everything. In addition to the usual recording of SEE data and associated dosimetric information keep records of any adjustments made to experimental test setup (hardware, software, cabling, etc.) and chronological sequencing of beam changes, device changes, nominal beam characteristics (species, energy, flux, etc.). Where possible, it is useful to record this information manually and electronically.
●
Accelerator testing can be an expensive proposition and there are significant pressures to optimize beam utilization, It is importan~ however, to not allow these pressures to interfere with sound measurement and analysis. This is especially true in the case of SEE qualification on a DUT for which the expected response is unknown that whatever preliminary test plan you start out with will require modification. If you are able to perform interim analysis during the data collection effort, this analysis will provide sensible guidance
11-31
to adjusting response.
the data collection
procedures
to accommodate
the observed
.
The typical procedure at an accelerator will be to perform pre-irradiation measurements of all relevant device operational parameters followed by irradiation increments in which the DUT is exposed to fixed fluences of particles and then measured again. In the case of SEE qualification, these interim measurements will typically quanti~ the number of events which have occurred for a given fluence. In the absence of any prior experience or data with a given DUT, it is useful to start with small increments and gradually increase to larger fluences as dictated by the observed response.
.
For purposes of statistical analysis of SEE data after data collection is concluded, it is usefid to collect data on several devices of the same heritage and date/lot code. Repeatability of result is a key component in performing accurate upset rate modeling and predictions.
3.3 LABOIUTORY
SIMULATORS
AND TOOLS
There are three usefhl tools which can be used in the test snd measurement of single event effects. The tools are similar to accelerators in the sense that they issue ionizing radiation to the target structures and/or devices as does sn intense particle beam from an accelerator. Nonetheless, these tools are different from the accelerator facilities in that the tools are more like specialized instruments to look more closely at special SEE problems. These tools have been developed over the years snd are not intended to replace accelerator, but are meant to complement and clari~ accelerator results. .Three laboratory simulators tools are the 252Cf source, the pulsed laser source, and the ion microbeam source. These three tools are not generally usefid in the broad field of SEE study and analysis but can be quite usefid in specific circumstances to screen or investigate for particular single event effects. The relatively high LET spectrum produced by 252Cf sources can give a quick look or preview of potential single event effects problems on a target device. The spatial and temporal localization associated with the puked laser and ion microbeam sources can provide detailed information on single event effect processes not easily available when using ion accelerators. These tools are used most effectively as supplements to ion accelerator data rather than direct replacements for such data. 3.3.1 252cf The 252Cf source is a simple way to screen for SEE effects. A schematic of .a typical 252Cf source set-up along with other pertinent technical information is shown in Figures 6A, 6B, and 6C. It uses the radioisotope 252Cf as the source of particles. 252Cf emits a variety of energetic particles in it’s decay including mostly a psrticles (96.91 ‘%0), neutrons, and spontammus fission fragments (3 .09°/0) which are the most interesting in the SEE application. This type of source requires little effort to operate, but has limited
II -32
utility since the range of most of the fission fragments is very limited to typically <15 ~m in Silicon. The problem here is that if the target device contains any appreciable surface layers over the sensitive volumes, then the particles will not penetrate and the results are invalid. Another problem with these sources is that they emit a limited range of LET particles between 41 and 45 MeV/(mg/cm2) which does not usually cover cross section versus LET sufficiently for SEE rate assessment. Nevertheless, because of the simplicity of a 252Cf set-up there have been some attempts in the community to provide improved 252Cfmeasurement capabilities. [50] Overall, these tools are good for screening purposes and could be used in a SEU Hardness Assurance sense to compare relative SEU cross section values between devices fabricated in the same lot as long as they had a measurable event rate for the limited LET range of the spontaneous fission fragments.
Figure 6A: Schematic of the advanced SEU Chamber.
II -33
Figure 6B: Scintillator MCA spectrum showing heavy and light fission fragment groups
8
0 M3637Bs
404142 434445484748 LtmsL *V-U+-
Figure 6C: LET distribution of 252Cffission fragments 3.3.2 PULSED LASERS Ion-beam testing is an essential step in the SEE qualification process for electronic circuits intended for space applications. However, the technique has several shortcomings for use as an effective tool in SEE troubleshooting, such as the limited availability of accelerator time and the lack of information on both the temporal and spatial origins of SEE. Therefore, considerable effort has been devoted to the development of a laboratory technique that is convenient, nondestructive, and provides both spatial and temporal information. The pulsed laser is such a technique because the laser light that is absorbed in the semiconductor generates charge. The track of charge
11-34
produced by the laser light differs from that produced by an ion because of the differences between the interactions of light and ions with the semiconductor material. Other fatures of the pulsed laser that make it attractive for SEE measurements and studies include the ability to focus the light down to a spot with a diameter of about 1 micro~ the delay of the light pulse relative to the clock signal on the circuit, and the nondestructive nature of the technique. [51],[52] Since the emphasis in this course is on practical SEE measurements, we will not make detailed comparisons between ion and laser beam testing, referring the reader, instead, to the available literature Figure 7 shows schematically the equipment required for doing pulsed laser testing. [53] Although the technique itself is relatively simple compared to an accelerator, maintaining the laser in good operating condition is nontrivial and requires specific training.
1
rT-~---+--+ ml 1
........- ....
‘-
tic
wstcllJe
Figure 7: Pulsed laser set-up schematic. An optical table, mounted on shock absorbers, is essential because even relatively small vibrations can alkt the measurement of SEE thresholds when lenses with high magnification are used. The most suitable laser for doing these experiments is the argon ion/Ti :sapphire laser system. The argon- ion laser synchronously pumps the Ti:sapphire laser which is cavity dumped and emits very short, high intensity pukes of light. The following are the primary requirements for the laser: ●
Wavelen@ s 800 nm. We have previously pointed out that pulsed laser testing for most current circuits is best accomplished at a wavelength of 800 nm where the nonlinear effects are rninimize~ the focused beam spot is small, and the optics are simpler than when laser light with a photon energy equal to the bandgap of Si (1. 1 eV) is used together with visible light for viewing the circuit.
II -35
. Pulse lengths 10 ps. The main requirement for the laser pulse is that it deposit its charge at the sensitive node in times much shorter than the response time of the circuit. It is not necessary for the light to be deposited in times comparable to that of an ion. In fac~ if the pulse length is much shorter, nonlinear optical absorption effects become importan~ whereas for much longer pulses, the response of the circuit is not the same as for short pulses. . Sui%cient intensity to produce SEE. The pulse energies should be on the order of a few nJ to ensure that even the hardest parts can be upset. . Suitable repetition rate. The repetition rate should be adjustable. Very high repetition rates (Mhz) are required for charge collection measurements, whereas for measuring upsets in certain microprocessors, single pulses are desirable, so that the state of the circuit can be determined before the next pulse arrives.
To determine the upset threshol~ the beam intensity is varied with a halfwave plate sandwiched between two polarizers. This avoids the problem of beam movement that occurs when neutral density filters are used. The pulse energy is measured with a detector and meter to determine the upset threshold. By placing a beam splitter that directs about 5% of the incident light to a detector and energy meter, the energy of each pulse can be measured. The actual energy at the circuit must be measured with a second detector placed where the circuit would normally be placed and the ratio of the energies at the two meters determined. Because one lens is not suitable for all situations, a series of microscope objective lenses with different magnifications should be available. The following set of lenses should be adequate - 10x, 40x, lOOx, and 150x. Usually, the greater the magnificatio~ the smaller the spot size. For testing circuits that are recessed in the package, we use a lOOx lens with a long (3 mm) working distance. The spot size, which should be as small as possible, is determined by the wavelength of the light as well as the F# of the lens, and is given by Equation (4): d=(4kf)/n
D.
(4)
For example, our 40x lens had a working distance of 3 mm and a diameter of 4 mm, so that at a wavelength of 0.8 ~m (800nm) the difliaction-limited spot size was 0.8 pm. This means that if the beam was comparable to the size of the lens aperture, the smallest spot size one could obtain with minimum interference pattern would be 0.8 ~m. In practice, the beam will always be bigger, depending on the quality of the optics. By inserting a second beam splitter together with a eyepiece lens, one can view both the illumina ted circuit as well as the focused laser beam. For safety reasons, a CCD camera with a monitor is used for indirect viewing. The eyepiece lens further magnifies
II -36
the image so tha~ in some cases, we have obtained magnifications 150x microscope objective and a 30x eyepiece lens.
of 4500 by using a
An X-Y stage with a minimum step size of 0.1 y.m that can be controlled by a computer is usefhl for accurate measurements of spatial dependence of upset thresholds. The microscope objective is mounted on a stage that moves only in the z-direction. This can also be controlled by a computer that makes it possible to do automatic focusing since the part usually goes out of focus when the X-Y stage is moved.
The pulsed laser has been applied to a wide variety of SEE studies that have been detailed in the literature. One example, not previously published, that demonstrates the usefidness of the pulsed laser is the generation of bit maps for memories. For this application one uses the fact that the focused light can be accurately positioned on a single memory cell whose physical location is known. Frequently, bitmaps are not available because of the reluctance of manufacturers to provide any information they consider proprietary. However, for determining whether error detection and comection (EDAC) codes will work it is essential to know the bitmap. Using the laser, one can determine the bitmap by generating errors in cells and then reading the address of the upset cell. This was done for the 93L422, a 256x4 bipolar SRAM that was flown on a satellite, CRRES. Upsets were recorded even though the part was protected against SEU with EDAC. We found that in some rows, cells from the same physical address were adjacent to one another. As a result should sn ion travel between the two cells or pass through both of them, two upsets in the same word would occur, and the EDAC code being used was incapable of correcting for such an event. The pulsed laser is a useful tool for SEE studies and measurements because one can generate upsets at precise locations in a circuit and at precise times relative to clock signals. It cannot replace accelerator testing because the difference in the physical mechanisms between ionhnaterial and laser lightimaterial interactions is significant and also the pulsed laser technique possesses immense difficulties in determiningg the asymptotic cross section. One area where the laser may prove quite usefi.d is in SEE hardness assurance measurements where the relative change from one memory to another can be measured and the absolute values determined by comparison with accelerator measurements on some of the same parts. 3.3.3 MICROBEAMS The need to understand the mechanisms of single event effects immediately suggested to those in the radiation effects community, who were familiar with ion accelerators, the use of ion microbeams to obtain information on such phenomem An ion microbearn is a system of magnetic and/or electrostatic quadruple lenses snd apertures used to produce an ion beam with a diameter on the order of micrometers. The first SEU studies utilizing a microbeam were performed by Campbell, Knudsow and Wolicki [54] at
II -37
the Naval Research Laboratory in 1980. The setup for this experiment is shown in Figure 8A. An electrostatic quadruple triplet produced a reduced-size image of an aperture located about 2 m upstream. The minimum obtainable beam spot size was about 17 pm in diameter. A piece of quartz located next to the device under test was used for focusing the beam and for positioning the desired area of the device under the beam spot. Initial efforts were directed at mapping the sensitivity of various areas of a DRAM, but difficulties were encountered due to the fact that by the time adequate upset statistics had been obtained on a spot, sufficient radiation damage was produced to alter the sensitivity of that spot.
EQUIPMENTINSIDEDASHED LINE IS MOUNTEDONTRANSLATION STAGE TO PROVIDEVARIATIONOF 0.
Figure 8A: Schematic of original NRL Microbeam
As this microbeam was configured, it was inconvenient to reduce the beam flux to the levels desired and, since only low fluxes were needed, it was decided to change to a notiocussing microbeam. [55] As shown in Figure 8a the incident ion beam is focused to a spot about a millimeter in diameter on a thin scattering foil. The scattered particles emerge fi-om the foil in all directions with their intensity having a 1/ (sin4 (3/2) dependence on the angle between the scattering direction and the incident beam. Therefore the scattered particles are strongly peaked at zero degrees and at small values of 0, small changes in 0 produce large changes in the ion flux. The pinhole aperture defining the beam spot size is about a meter downstream from the scattering foil. Pinhole apertures are commercially available with holes down to a micron in diameter. The entire end of the beamline is mounted on a translation stage so that the scattering angle of the particles passing through the pinhole aperture can be changed to adjust the particle flux. Beam spot diameters of a few pm have been obtained with this facility. Although more sophisticated microbeam facilities have been developed for SEU and charge collection studies, this configuration has the virtues of simplicity, low cost, and portability. It has been used for numerous experiments at five different accelerators. Horn, Doyle, and Sexton [56] at Sandia have recently applied a more sophisticated microbeam to the task of obtaining a map of the upset sensitivity of a RAM. Figure 8B shows their setup which uses two computers, one to exercise the RAM and a second to step the position of the microbeam over the selected area of the RAM by controlling the voltages
II -38
on horizontal and vertical deflection plates, and to record data on SEUS and secondary electron emission ftom the RAM so that it is correlated with the ion beam position. The data on secondary electron emission intensity versus beam position is used to produce an image of the portion of the device being studied so that the exact area being measured may be identified by comparison of the image with the circuit design mask. The data on SEUS then provide a map of upset sensitivity correlated with the elements of the RAM. Obtaining useiid secondary electron images generally requires ion beam currents high enough to darnage the RAM, so usually the SEU data is acquired first at low beam current (femtoamperes) and then the beam current is increased (picoarnperes) and the secondary electron image is acquired. [57] The beam is focused to a spot 1-2 pm in diameter by the Sandia microbeam, but experiments have also been done at the University of Melbourne in Australia [58] which has a microbeam capable of producing beams less than 0.1 pm in diameter. The secondary electron imaging process does not work with chips having a polyimide passivation layer. Even an oxide passivation may degrade the resolution sufficiently to make identification of features difficult with high density memories. “
SEM
Data
!!!
Acquisition
IC Exercising Computer
Computer )6
Figure 8B: Schematic of Sandia Microbeam
The output signal from a DRAM or SRAM being exercised to detect SEUS is a binary signal and does not provide much information on the effect of an energetic ion. In an effort to obtain more detailed information McNulty [59] has connected a charge sensitive preamplifier to the vdd and V,, pins of a RAM and looked at the amplitude spectrum of the pulses generated when the RAM is bombarded by energetic ions. This procedure has been combined with the use of an ion microbeam by Breese et al. [60] at the University of Oxford and more recently by Horn et al. [50],[51] at Sandia. This technique has been named IBICC (ion-beam-induced charge collection) by analogy to EBIC (electron-beam-
11-39
induced conduction/current). Although this technique may have application to tilure analysis and reverse engineering problems, thus fiu the proponents of this method have not presented a strong case for its utility in understanding SEU. The junctions that show up most clearly are the junctions connected to ground or the power supply.[51 ] Hence charge collection at these junctions makes no contribution to SEU. The output signal ii-em a DIL4M or SR4M is several stages removed from the actual signal directly produced by the passage of sn energetic io~ so the desire for more quantitative measurements of the charge collection resulting from the ion motivated the change to the use of test structures, such as MOS capacitors, diodes, and transistors, which are the building blocks of MM cells. In order to measure charge collection as a fhnction of position on these structures at the relatively low particle fluxes suitable for these studies, the simple microbeam described above, composed of scattering foil and pinhole aperture, has been used. Charge collection measurements generally involve either a measurement of the total charge in the charge collection puke or a m easurement of the time dependence of the transient. In the first situation charge sensitive preamplifiers are used with ampliikrs and multichannel pulse height analyzers. The processing of the transient results in a pulse whose amplitude is proportional to the integrated charge collected within a time period of the order of several microseconds, as selected by the amplifier settings. In the case of time dependence measurements a wide bandwidth oscilloscope, together with high frequency components between the device under test and the oscilloscope, are necessary in order to faithfidly capture the time dependence of a f~ charge collection transient. Most measurements of this type have used the Hypres sampling scope which achieves a 70 Ghz bandwidth through the use of superconducting components in the tint end, Although it is not uncommon for sampling scopes to achieve this bandwidth in the analysis of periodic pulses, the Hypres instrument is unique in providing this bandwidth for randomly occurring pulses. An interesting finding fiam charge collection measurements on devices with two junctions, such as a bipolar transistor, is that when the ion track passes through both junctions the charge collected at one junction can be significantly modified by the bias conditions at the other junctio~ even to the @nt of changing the polarity of the charge that is collected. [61 ],[62],[63] This effect is generally ref&rred to as the ion shunt effec~ since some of the experimental observations can be explained by viewing the ion track as a plasma wire bridging the two junctions and connecting two regions of like conductivity type (p-type or n-type) titi the charge transported along the plasma wire being determined by the potential di.lTerence between the ends of the wire. However, the data also display some ckacteristics of a bipolar eff~ [64] particularly when one junction is at zero bias voltage or slightly forward biased. Examples of the occurrence of the geometry required for this effect are bipolar transistors and FETs fabricated in wells. Pulsed lasers have also been used as an alternative to ion microbeams for the study of charge collection. As mentioned above they have the advantage of not inducing radiation II -40
damage in the device under study, but this is coupled with the disadvantage of the laser beam not being able to pass through metallizations. The initial charge track produced by the focused laser beam is also larger in diameter and has a different variation along the length of the track than in the case of the ion beam. A few picosecond after the laser pulse or ion passage ambipolar diffusion makes the radial differences insignificant and for most devices with charge collection only from a limited region near the surface the variation along the track is also unimportant. 3.4 PROCEDURES
TO COLLECT DATA USING SIMULATOR TOOLS
The methodologies for using various simulator tools in conducting SEE experiments are by no means universal due to the specific nature and use of these tools. There are some similarities in the experimental procedures and to varying degrees the hardware implementations themselves. Details of 252Cf and ion microbeam SEE data collection beyond those of a general nature are outside the scope of this short course. The student is directed to the appropriate reference documents for additional information regarding these methods. The following procedural example cited for a specific instance of Ti:sapphire pulsed laser is unique to the cordiguration shown in Figure 7. For this example, we describe how to measure upset thresholds in CMOS SRAMS using a Ti:sapphire pulsed laser focusing on 4Kx1 part - HM6504RH, pointing out the advantages and limitations of the technique as well as pitfalls that should be avoided. The general methodology is described in the following paragraphs. The identification of the SEE-sensitive areas can be simplified by using electrical schematics and layouts of the memory cell obtained from the circuit designer. For instance, in an SRAM memory cell there are four SEE sensitive areas, two n-channel and two p-channel transistor drains. Without the schematics, the problem is more difficult but not intractable The software for testing the SRAM cell should be able to write, pause and then read from the entire chip. If an upset occurs, the program should specifi both the erroneous data and the upset address. There should also be a “strobe” mode in the program in which only a single memory cell is written to and then read to determine whether an upset has occurred. Having the computer signal an upset with an audible beep makes measurements more convenient. Other circuits may require different software. After mounting the test board containing the chip on the X-Y stage and moving the chip into position so that the pulsed laser light can be directed at the sensitive parts of the circuit, a 10x lens should be used to find the general area of interest and then a more powerful lens used when probing localized areas. After positioning the circuit so that the light is focused on a spot sensitive to SEU, the laser pulse energy is increased to the point where an upset will occur and the address
11-41
is noted. With the address know, it is possible to switch into the “strobe” mode, so that only the particular memory cell being upset is addressed. In analyzing the data, one should be aware of the fact that the minimum laser energy required to produce an upset will not translate directly to an equivalent LET for an ion. This is due to at least two reasons; the charge track profiles are not the same, and the amount of energy required to produce an upset varies across the sensitive region, so that the location for the minimum threshold measured with the ion may be covered by metal, and so not be accessible to laser light.
4.0 PREDICTION
OF SEE RATES
A key concept in SEE qualification is in the calculation of expected or predicted single event rates. The prediction of SEE rates for intended applications is a critical part of “what to do” as challenged in the SEE qualification process. There are many ways to tackle the problem and many ingredients to be considered. This section deals with some of these areas and tries to give the readers the overall picture in the SEE rate prediction business. We begin with a description of the methodologies. 4.1 METHODOLOGIES All SEE rate prediction depends on some methodology or reasonably effective way to combine these single event cross sections (which have units of area, typically expressed in cm2/unit device or bit, whatever the case may be) with environmental flux (which have units of number/ (cm2.s)) to obtain a rate. Now, keep in mind that a single event cross section for protons is a fimction of proton energy, and that a single event cross section for heavy ions is a fiction of LET due to the different initial mechanisms of nuclear reactions and direct ionizations for protons and heavy ions respectively. However, the generic methodologies for protons and heavy ions are essentially analogous. Each requires ground based measurements. Each cross section exhibits a “threshold-like” behavior rising up to some asymptotic value at large energy or LET values for protons or heavy ions respective y. And, as hinted before, each single event rate calculation requires a folding of the cross section with the appropriate environment for the intended application. A summary of the generic calculational technique is given in Table 5.
II -42
Table 5: Generic SEE rate calculation technique.
.
●
●
PROTONS MEASURE PROTON SINGLE EVENT CROSS SECTION (#OF EVENTS / FLUENCE) AS A FUNCTION OF PROTON ENERGY USE THE DATA IN ABENDELMODEL(l PARAMETEROR2 PARAMETER WHICHEVERWORKS BEST)TOOBTAIN CROSS SECTION ASAFUNCTIONOF ENERGY
.
.
FOLDTHE ENERGY DEPENDENT CROSS SECTION WITH THE APPROPRIATE DIFFERENTIAL PROTON FLUX(FROMAPROTON ENVIRONMENT MODEL)INSIDETHE SPACECRAFT
●
HEAVYIONS MEASURE HEAVY IONSINGLEEVENT CROSSSECTION(# EVENTS/ FLUENCE)ASA FUNCTION OF EFFECTIVE LINEAR ENERGY TRANSFER(=LET/cos 9) USE THE DATATO DETERMINE THE EFFECTIVELETAND THEASYMPTOTIC CROSSSECTIONOR USETHEDATAIN AWEIBULLFUNCTION ANALYSISTO OBTAINTHECROSS SECTIONASA FUNCTION OFEFFECTIVE LET FOLDTHE STEPFUNCTIONOR WEIBULLFUNCTION WITH THE APPROPRIATE LET SPECTRUM(FROM AHEAWION ENVIRONMENT MODEL) INSIDETHE SPACECRAFT
For protons, the formalism of the Bendelmethodology is straightforward. The single event rate is given by the integral of the product of the best fit Bendel fhnctionto the data with the differential flux spectrum behind the appropriate shielding, integrated from the threshold parameter, A, out to some large energy value. The 1 parameter Bendel model uses the threshold parameter as the sole free parameter. The two parameter Bendel model uses not only the threshold parameter, but also another parameter which is related to the asymptotic cross section value. Figure 9 shows the 1 and 2 parameter Bendel models which can be used in proton SEE rate prediction. The 1 parameter model is applicable to older device technologies or when there is a limited number of data points (<3) versus proton energy. The two parameter model is applicable to modern devices where the threshold energy persists around 20 to 30 MeV, but the asymptotic cross section varies and is a lower value than allowed by only the one parameter Bendel fhnction. The differences can be seen in Figure 10 which shows some SEU data for an 8Kx8 NMOS SRAM where both 1 and 2 parameter fits are indicated. Clearly the 2 parameter fit is better.
II -43
1 AND 2 PARAMETER
BENDEL
MODELS
A = ENERGY THRESHOLD (in MeV) .. free parameter
1 PARAMETER MODEL
~(E,=(:)’4{1-ex(-o.18.((:)1’2(E2 PARAMETER MODEL:
A = ENERGY THRESHOLD (inMeV) ... free parameter B = ASYMPTOTIC CROS SECTION (usuallyin cmz) . free parameter
a,E,=+-ex{-0.18([:)1’2,E-A,)’’2][
Figure 9: Description of 1 & 2 parameter Bendel Models
1 ANO2 PARAMETERBHWELMODEL ~t2
1
1
1
1 8K
~-n
$ya
X
1
1
I
I
I
1
I
I
1
I
8 M40S STATC RAM
/
//’
/.””
---
----
-----
1
I
I
I
I
1
4
A = 25.53 h4eV -------------
I
I I II,l,lli[ll,llillklll I
o
50
150
100
200
EhERGY(MN)
24
Figure 10: Comparison experimental data.
of 1 and 2 parameter
Bendel fits to the same set of
For heavy ion SEE rates, there are three primary methodologies. These are called the Right Rectangular Parallelepipeds or RPP methods, the Effective Flux methods, and the step function methods in descending order of complexity and possibly ascending order of practicality. Each set of methodologies has it’s own advantages and
II -44
disadvantages. The intent in this brief discussion, however, is to make the student aware of the different methodologies, nol to select or endorse one methodology over the other. The important point is that for SEE Qualification, some sort of SEE rate calculations or estimates based on reasonable assumptions must be made for the intended applications. Otherwise, SEE qualification takes place on-orbit with great risk. Because of the history of single event effects has been largely based in single event upsets, most of the methodologies that have been have been developed directly apply to the upset problem. However, the techniques are not single event type specific and generally apply when the sensitivity can be described as we have indicated via a measurable cross section versus energy or LET. Let us take a look at some details of each of the methodologies. There are two RPP methods, the standard RPP method [65] and the Integral RPP [66] or IRPP method. Let’s begin discussion with the standard RPP method. The basic RPP approach assumes the following: . . .
that all sensitive volumes in the device are identical right rectangular parallelepipeds in geometry with identical electrical performance characteristics, that some threshold LET exists which is identical to each cell, and, that the amount of charge collected through the RPP is a function of path length.
With these assumptions the SEE rate is then determined as the integral
N=:LT’’’’”43’
(5)
Lo
where N= single event rate for a single cell S = surface area of the device A./3= critical energy for single event L = linear energy transfer LO= minimum L that produces single event I(L) = integral LET spectrum D = differential path length distribution p = density of sensitive volume material In this formulation of the SEE rate calculation, the intent is to add up all the cases for incident particles where the pathlength and LET are sufficient to cause the single event. There are no obvious advantages to this method. The method overestimates the error rate since it does not take into account the real shape of the cross section especially in the threshold region. Real, measured heavy ion SEE cross sections versus effective LET are not step functions. There is usually some finite slope to the threshold region which makes any sharp threshold ambiguous. Because datasets are sometimes incomplete, there are some questions about the asymptotic values, that is, does the data
II -45
saturate over the measured effective LET range. Therefore the method depends on some guesswork in determining the threshold LET and the asymptotic cross section which are important for use in the RPP method. Lastly, the RPP assumption itself for the sensitive volume shape is not accurate for many real device sensitive volumes. Sensitive volumes are simply not right rectangular parallelepipeds. They are complex three dimensional structures determined by the device geometry which may be complex and asymmetric, and further complicated by charge transport properties in high and low electric field regions.
The use of the RPP is used here in the interest of mathematics since the differential path length distribution can be calculated for the RPP geometry. Nonetheless, it is an approach which typically yields conservative estimates and is the most used method to date. The other RPP method called Integral RPP or IRPP is similar but recognizes the fact that all sensitive volumes are not identical in shape and electrical characteristics, and assumes that they form some distribution. The distribution lends itself to partial cross section which are weighted by the asymptotic cross section and then added up to get a total error rate. An off-shoot of this methodology is the “Petersen figure of merit” formula which is given in the following Equation (6).
R = 200X
~L ~:25
events [
(MeV
bit. day
/ (’mg / cm2 )2 cm2
1
(6)
where CL is the limiting or asymptotic cross section and L0,Z5is the LET at 25°/0 of the limiting cross section. This is a good approximation for the heavy ion single event rate, R, in Solar minimum geosynchronous orbit and is usefid for comparing relative SEE performance of different devices. Equation (6) is appealing since it is so easy to use. All that is required are reasonable estimates for o~ and LO,z~which can be obtained by the cross section versus effective LET data. The Effective Flux method for SEE rate calculation [67],[68] is similar to the approach used for protons. Recall that the proton case takes cross section, multiplies by the appropriate particle flux at a given energy and integrates over all possible energies. The effective flux method for heavy ions assumes the following: .
●
that the cross section data represents effective LETs
the SEE sensitivity
of the device over all
and that the rate is formed as the integral of the cross section times the appropriate effective flux spectrum over effective LET.
II -46
So the problem treats the device as a “black box” and no information on the device geometry is required. Since the data is taken versus effective LET or LET of the beam divided by the cosine of the incident angle, the heavy ion flux spectrum must also be converted to “effective” flux. This is done by a reasonable redistribution of the spectrum to higher LETs to account for particles passing through longer path lengths through the device. A typical redistribution of the flux spectrum is to separate the spectrum into small bins and them shift fractions of each bin out to higher LET according to an inverse cosine law to make a new flux spectrum which is related to effective LET used in the ground based dataset. This approach is appealing since it does not require intimate knowledge of the details of the target device. It basically assumes that the data represents the overall SEE sensitivity and that the simple multiplication of cross section times flux gives you rate when integrated over some reasonable representation of LET. It is also a good approach since the uncertainties of the calculation are largely driven by the uncertainties in the environment over which we have no control. Another advantage is that it is relatively easy to use and no extensive code or difficult calculation is required to produce reasonably good and practical SEE rate numbers for any application. The disadvantages of this method are that a relationship must be assumed between LET and effective flux and then specified. The Step Function method is the easiest to use, although potentially the least accurate. It is the simple multiplication of the asymptotic cross section times the integral flux of particles above a threshold LET. Like the effective flux approach it treats the target device like a “black box” where details of the device geometry are not required. But as usual, with simplicity and ease of use, comes disadvantage in accuracy. The Step Function method overestimates the error rate if the threshold LET is estimated from the dataset to be lower than actual threshold LET value and it underestimates the error rate if the threshold LET is estimated from the dataset to be higher than the actual threshold LET value. Also it does not take into account the shape of the cross section curve. Nonetheless, it is the quickest and easiest SEE rate calculation to implement as long as the cross section data gives reasonable coverage to the threshold region and a good value for the asymptotic cross section in addition to a good integral LET spectrum for the intended application. It is important to recognize in any SEE rate calculation that the statistical uncertainties in the environment (both for protons and heavy ions) dominate the statistical uncertainties caused by the finite ground or accelerator data. Certainly it is always desirable to achieve the best possible statistics in any measurement, however, resources may not always be available and data must be taken practically. Typically in any SEE measurement, 25°/0 statistics should be good enough to make a reasonable rate calculation, especially considering that the space environments are not usually known to better than factors of typically 2 to 3.
H -47
For SEE Qualification it is important for the reader to understand in a generic way what parameters play the dominant role in the determination of SEE rates. This is addressed in Figures 11 through 15 where SEE rates are computed as a function of the respective cross section models, the Bendel 2 parameter for protons and the Weibull function for heavy ions using a generic calculation technique. For the protons, the high energy is important since most of the protons upsets come from the high energy component of the proton spectrum. So, the accurate SEE rate prediction depends on how well the asymptotic cross section is determined, which corresponds to the Bendel B parameter. For the heavy ions, the situation is different. The important parameter is the threshold parameter, indicating the importance of having good data in the threshold region. The differences in these findings are because of the differences in the incident particle spectra. The proton fluxes from AP8 typically behave like a Lorentzian fi.mction centered around 50 to 100 MeV depending on the shielding followed by an energy dropoff that goes like 1/E where E is the energy. The heavy ion fluxes typically follow an LET dependence that goes more like l/(LET)3’4 indicating a much more severe fall off in the LET flux spectrum.
100
5 ~
,5
m F(E)
~ M so < ~ g ~~ 0 ,.O
PROTON SINGLE EVENT RATE AS A FUNCTION OF UPPER INTEGRATION LIMIT
m
10
~3
U(T)= jcr(E) .F(E)dE
,.4
A
EFERGY (MeV]
EFKRGY (MeV)
Et.ERGY (MeV)
Figure 11: Effect of proton integration cutoff energy on SEE rate calculation.
II -48
PROTON
I
SEE RATE
TRENDS AS A FUNCTION OF BENDEL PARAMETERS ... THRESHOLD A~~~~~~ A50%CHANGE IN THRESHOLD PRODUCES ONLY A 7% CHANGE IN RATE ... (NO BIG DEAL)
●
64 z
12345
o
NORMALIZED
ASYMPTOTE BBEND~~
ABENDEL
A 50% INCREASE IN THRESHOLD PRODUCES ONLY A 50% CHANGE IN RATE . LARGER CHANGE THAN PRODUCED BY THE THRESHOLD
●
-~20 Q
z :
15
----------------,
/:
50%
% n u ~
10
4
.5
----------,
~
50% ‘ :,/(:,
i? 00 z
POINTS TO THE IMPORTANCE OF THE ASYMPTOTE B ~
~
o
15
10
NORMALIZED
20
BBEWDEL
Figure 12: Relative effects of shifts in Bendel A and B parameters on predicted SEE rate. ,Co
;
cw
?
b\ iw ‘o”’1 ik y t < ~ 10”4 > o z ,06
HEAVY ION SEE RATE TREND F(L)
,,\,]
AS A FUNCTION
OF
~ 10
1
ASYMPTOTE
100
A
LET
100 i 00 $ ~ o 0 LL N
7
.$ g
[
R(A) ASYMPTOTE
N JCJ(A,B, C, D, L). F(L)dL
A B
75
50
25
z o
1
10
100
LET
Figure 13: Effect of heavy ion asymptotic cross section on predicted SEE rate.
II -49
ION SEE RATE TREND
HEAVY
AS A FUNCTION THRESHOLD
OF
LET B
LET
100 100 L _,
= Jo(A,
11 o
THRES
OLD LETB
“F(L)dL
1
L!_-__!
1
B, C,D,L)
B
Weibull o(A,B,C,D,L)
75
E
R(B)
/’”7
F-
10
100
LET
Figure 14: Effect of heavy ion threshold LET on predicted SEE rate.
HEAVY
ION SEE RATE
TRENDS AS A FUNCTION OF ASYMPTOTE A c I
3;’
I
15
10
5
20
THRESHOLD ●
m F !2 u
r’..
lo
[
1
●
--
1 ~%
390% 57%---
, 1----, l–––-~–– 1, 1, ; 5’3%50%
●
/
I
12
5
LET B
A 50% INCREASE IN THRESHOLD PRODUCES A - si’~o DECREASE IN RATE A 50% DECREASE IN THRESHOLD PRODUCES A 390% INCREASE IN RATE
POINTS
TO THE IMPORTANCE
OF THRESHOLD LET
L
01
A 50% INCREASE IN ASYMPTOTE PRODUCES A 50% INCREASE IN RATE
i
12
NORMALIZED
5 3
Figure 15: Relative effects of heavy ion asymptotic cross section and threshold LET on predicted SEE rates.
II -50
4.2 COMMERCIAL
MODELING CODES (CREME, SPACE RADIATION,
ETC.)
There are a number of available “upset” codes which calculate rate. There maybe others, but Table 6 indicates most of the more popular codes. They were developed largely to address the SEU problem, but they can be usually used to calculate other types of SEE rates if the appropriate cross section data is obtained. Table 6: Summary list of “upset” calculations. CODE NAME
,
0 CRIER (COSMIC RAY INDUCED ERROR RATE)
●
CRUP, HCRUP (COSMIC UPSET PROGRAM. HONEYWELL CRUP) CREME
●
NASA EFF FLUX APPROX
T. SCOIT
●
MODIFIED FIGURE OF MERIT APPROXIMATION
E. PETERSEN
●
SPACE RADIATION
J. LETAW (SEVERNS)
●
SE ANALYST
WEITZ (SAIC)
●
RAY
PRIMARY AUTHOR J. PICKEL (MAXWELL, SCUBED) P. SHAPIRO (NRL)
I I J. ADAMS (NRL)
(IBM)
(NRL)
I,
COMMENTS RPP, IRPP, FUNNEL, TRUNCATION, ADAMS’ GEOSYNCHRONOUS ENVIRONMENT RPP, FUNNEL, ADAMS’ GEOSYNCHRONOUS ENVIRONMENT
I BASED ON CRIER, RPP, PROTON UPSETS, ADAMS’ COMPLETE ENVIRONMENTS BASED ON BINDER EFF FLUX, NEEDS CREME INTEGRAL ENVIRONMENT, ASSUMES ANGLE CUTOFF AT 80° AND LET CUTOFF AT 110 (MeV/(mg/cm2)) BASED ON RPP, SIMPLE ANALYTIC FORM FOR GEOSYNCHRONOUS UPSET RATES BASED ON CRIER AND CREME, AP8, AE8, JPL FIARES, SHIELDOSE, INCLUDES TOTAL DOSE AND DISPLACEMENT DAMAGE, RPP, IRPP, FUNNEL, 1 AND 2 PARAMETER PROTON UPSETS” BASED ON CREME, AP8, AE8, SHIELDOSE, INCLUDES KESSLER DEBRIS MODEL, INCLUDES TOTAL DOSE, RPP, AND PROTON UPSETS
All of the codes require input from at least two main areas, the environment and ground based data as schematically indicated in Figure 16. Occasionally, as with the RPP techniques, some information about the target devices is required to infer accurate information about device sensitive volume geometry. This figure is somewhat simplistic and really applies to discrete integrated devices. The analyses required for system level SEE rate predictions can be significantly more complex and are well beyond the scope of this part of the short course. It has been shown that SEE rate prediction techniques which neglect to consider error propagation in systems of interconnected devices can significantly underestimate the actual rate and impact of discrete events .[69] Measured and applicable information from any of these input areas for SEE predictions is not For SEE Qualification, reasonable best guesses and/or worst case always available. estimates for the missing parameters can be applied in order to obtain an upper limit for In no case or level of application the SEE response rate for the intended application. should SEE rate be ignored or overlooked just because no well defined environment,
11-51
ground based data, or device information is available. On the other hand, the predicted SEE rate must not be taken as absolute truth because it is built upon assumptions, simulations, and uncertainties both statistical and systematic.
i“-=:’””
1 W;E’R’D’C’’”NC
4&
““””--””””””
Figure 16: General schematic of components and flow relevant to SEE rate calculations. 4.3
PROBLEMS WITH STATISTICS, ETC.)
THE
PREDICTIONS
(REALISM,
ENVIRONMENT,
Some of the problems associated with the SEE rate predictions have already been mentioned in the discussion of the rate methodologies. To start, ground based accelerators, principally in the case for heavy ions, do not produce actual cosmic ray heavy ions. They produce lower energy ions which are assumed to be approximations to the cosmic rays, For example, the ~ or speed compared to the speed of light in a vacuum of an actual cosmic ray ion typically approaches the value 1. This is simply a statement that real cosmic rays are highly relativistic or are very energetic. The P of a typical Brookhaven Tandem type ion, say a 285 MeV 79Br ion is only 0.09, much less than the cosmic ray. Even a 2000 MeV 79Br ion has a ~ of only 0.23. Charge transport has been shown to be dependent on the initial e-h charge density distribution [70],[71 ] which itself is highly dependent on not only the species or Z, but also (and more importantly) dependent on the kinetic energy. In addition, the ground based set-up is not omnidirectional. All measurements are taken at fixed angles when in the ideal situation, the omnidirectional cross section is most desirable. We are forced to use the accelerators as tools to issue ions that only approximate the natural environment and it is important to recognize their inherent limitations. Another important problem associated with the SEE rate estimation is that the environments are not well known and are not static as is usually assumed in the calculations. The result of some of these difficulties in SEE rate predictions based on ground measurements can be seen in Figures 17 and 18 which compare predicted versus actual SEU rates for several device types onboard the CRRES
II -52
MEP. Some of the predictions were in good agreement with observed rates and others were off by an order of magnitude. This does not mean that SEE rate prediction is not as advanced as thought. It means that SEE rate prediction is critically dependent on both the ground based measurements and analysis and the environmental models used. All must be carefully considered for the intended applications. CRRES
MEP PREDICTIONS/MEASUREMENTS PROTON UPSETS
4K NMOS SRAM (92L44) ,!,, ,,,, , ,,,,,4,,,,: ..,. , , ,,, ,,, ,,, ,,, ,,, ,,, .,,,, .,,,, !!.,,,, . . ......
4K NMOS SRAM (21 L47) 1 K BI PO SRAM f33L422)
,,, ,,,,
1K BIPO SRAM (93422)
,,, ,,,,
,,, .,,,,,,, ,,, ,,.,,,, .,, .,”,,,, ,,,,,, ,,,,,, ,,, ,,, ,, ,,,., . . ,, ...” .. ..... . .,.,. .:::::::::: :::::!::::: ,, ..,,..,, ,,,.,, ,, ..,.,,, ,,, ,,,, . .<.,,.,,,, ... ....,. . .,,,,,, ...,,,,, . . ,,,,, .,,,,, , ,, ,,, ...... ,,,,, ,,!,, ,,,,, ,,!!, ,, ,,, ,,, ,!,. ,... , ,, ,,, ,,, ,,,, ,,,, ,,,,+!,,,, ,,, . .,,,...,,, ,,,... ::....,...,,,,,,,,,, ., ...,, ,,,,,,,,,., ,,. ., ..:: ,,,,,... ...,, . . ,, .,,,,,,,. . ,,,,.,,,....< ,,, ,,, , ,, ,. ..... #,,,,,,,,, .,,,, , ,,,,, !,!!!! ,,,,,
16K NMOS SRAM (61 16) 16K NMOS SRAM (71 681) GaAs 256 MCD GaAs 1 K MCD GaAs 1K ROC 0,001
0,01
0.1
1
10
100
UP SETS/Kl LOB IT/DAY
Figure 17: Comparison of predicted and observed SEE rates due to trapped protons for a selection of devices in the CRRES MEP experiment.
CRRES MEP PREDICTIONS/MEASUREMENTS COSMIC RAY HEAVY ION UPSETS
I 0001
0.01 UPSETS/Kl
0.1
1
LOBI T/DAY
Figure 18: Comparison of predicted and observed SEE rates due to heavy ions for a selection of devices in the CRRES MEP experiment.
II -53
4.4 ISSUES IN SINGLE EVENT R4TES There are three major issues in assessment of SEE rates. These are: .
the variability and differences between SEE rates from discrete devices, components, circuits, and systems,
.
the level of SEE rate tolerance for any sub-system or system, and
.
the possibility of applied SEE hardening and/or mitigation of the SEE problem,
4.4.1 DISCRETE DEVICES, COMPONENTS,
CIRCUITS, SYSTEMS
Much of the SEE work that has taken place over the years has almost exclusively addressed SEE in discrete devices. Because a spacecraft is a vastly complex system there is reason to believe that the discrete device SEE performance may not be always related to the actual on-orbit system SEE performance. In the interest of performance, reliability and cost effectiveness, it is most important to try to understand if there are differences and what those discrete versus system differences may be. 4.4.2 LEVEL OF SEE R4TE TOLER4NCE A space system designer usually must assess fault tolerance rates for a whole variety of sources of faults. The single event source of faults should be folded into the assessment in some reasonable way to determine the impact on the system and investigate ways of elimination and/or mitigation without significant performance, reliability or cost impact. This job is usually difficult since there are no easy ways to determine the outcome for single event effects which are random in nature and relatively infrequent in most space applications. It may well be that an SEE rate of say 100 events per day, for example, is completely tolerable to a given system provided that the impact each of the SEES is non-destructive. It also maybe that for another given system or application, that an SEE rate of 1 event per year is catastrophic if it is destructive and/or unrecoverable and/or provides unacceptable system down time. The major point is that the level of SEE rate tolerance becomes a measure of the SEE immunity. In other words, the degree to which a system may be considered SEE immune is what SEE rate may be tolerated. For SEE Qualification, the issue of SEE rate assessment becomes essential, and is meaningful when combined with a system-level fault analysis. 4.4.3 SEE HARDENING
AND/OR MITIGATION
Device SEE hardening has been demonstrated from some technologies, especially in the cross coupled resistor scheme for CMOS devices and in the reduced material
II -54
thickness’ in the SOI technologies. However, as microelectronics technology advances, discrete hardening approaches to the SEE problem are becoming difficult to implement and maintain, and do not immediately enhance the transfer of advanced technology insertion to spacecraft. The SEE Qualification approach lends itself to mitigation techniques once the SEE rate determination and level of tolerance are reasonably achieved. A sample SEE hardness assurance flow as applied to a spacecraft SEE Qualification program is shown in Figure 19.
Procure GENERIC Engineering
odificstions
Units
Required? NO, Engineering Units or existing Data
FLIGHT [
Figure 19: Sample SEE Hardness Assurance flow diagram.
5.0 HARDNESS
ASSURANCE
TEST METHODS
In a world where so much diversity and variability exists, especially in the research, design, and manufacturing trends of microelectronics, it becomes important to be able to use standards, procedures, and guidelines. These standards assist spacecraft designers in utilizing SEE data which may have been collected by disparate groups which nonetheless adhere to the guideline principals in that the standards documents provide for basic common definitions and techniques to SEE investigators. Moreover, for those performing SEE qualification with limited experience, the standards documents provide a basis for performing simple SEE measurements in a uniform manner. The ASTM F 1192-90 Standard Guide for the Measurement of Sirwle Event Phenomena CSEP) Induced by Heaw Ion Irradiation of Semicond uctor Device s and the JDEC 13.4 Test Procedure for the Measure ments of Sinde Event Effects in Semiconductor Devices from Heavy Ion Irradiation are examples of such documents. While these documents can be useful tools in the formulation of SEE qualification plans, their utility is somewhat limited in some respects. No testing or procedural guide can adequately address or account for unexpected on-line results nor can it satisfactorily address complex devices and systems
II -55 ..
and the unique needs of specific applications. While the area of SEE hardness assurance will take on added significance with the growing utilization of commercial technologies in a hostile radiation environment over-dependence on generic guidelines and methodologies may adversely impact in the experimenter’s SEE rate predictions and should be avoided. SEE Hardness Assurance is one of the areas where the pulsed laser simulation tool can really make a significant contribution.[53] Since the puked laser can be easily implemented for virtual table top operation, relative single event effects thresholds can be measured from “lot-to-lot” to detmn.i.ne the variations and compared to heavy ion data fi-om a representative lot sample. 6.0 FUTURE TRENDS It has been shown that the level of interest in SEE phenomem has remained steady or even increased since the early eighties in spite of the tremendous gains in knowledge and experience with various aspects of field. There exist today technologies and strategies which can be employed to render systems essentially SEE “immune.” Why then does the field continue to generate such interest? One reason is the fact that many of the technologies which are employed to counteract SEE phenomena have undesirable characteristics such as high cost, high power, and slow speed. Increasingly, spacecraft designers are looking to commercial technologies which are less expensive, have far better performance characteristics, and are readily available, when compared against “rad hard” technologies, The challenge for the researcher engaged in SEE qualification is to fidly characterize these commercial technologies and to seek strategies which allow their use in a radiation environment for which they may not be well suited.
6.1 INCREASED
DEVICE AND SYSTEM COMPLEXITY
The trends in commercial electronics which make them desirable are also the fhctors which render them, in many instances, more susceptible to SEE. There are three design goals which are relevant here: 1. Smalleiv Device cells and sensitive volumes are continuing to shrink into the sub-micron region in order to achieve higher and higher packing densities. Single chips with hundreds of millions of transistors are not uncommon. This high level of integration present two problems with regard to SEE. First the smaller sensitive volumes may also have smaller critical charges for upset. Secon~ the high packing densities will tend to make such devices more sensitive to ion track structure effects and complicate the comparison of ground based accelerator data to actual space response. 2. Faster: At the same time device fkature sizes are growing smaller, clock hquencies are increasing. Devices operating at very high clock speeds are
II -56
prone not only to increased SEE sensitivity owing to simple statistics and timing issues, but the short clock waveforms themselves become sensitive to the small analog disturbances caused in control lines by the passage of incident ions. 3. Low Power: The third factor driving advances in current technology is the desire for low voltage and low power consumption. These devices tend to have both a reduced tolerances for shifts in logic levels (a reduced margin for error) but also a reduced critical charge for any type of single event effect. We can see that those factors which spacecraft designe~ find most attractive in choosing technologies and devices with which to build their systems are, at the same time, potentially problematic in terms of SEE phenomena It becomes critical to have an accurate measure of these devices and subsystems SEE response and predicted on-orbit behavior in order to develop adequate strategies which address potential problems introduced by these enhanced sensitivities.
6.2 DYNAMIC AND STATIC OPEIL4TION At the same time that individual devices are growing smaller, they are also growing more complex. In addition to hybrid technologies and packaging, we are seeing many fi.mctions being carried out on a single chip. Thus, a single event upset in one area of a chip may manifest itself in a variety of ways at the chip output pins. Likewise, subsystems and systems are themselves growing in complexity, functionality, and speed of operation. It is no longer adequate, in msny cases, to consider a complex system to simply be an aggregation of independent static devices and operations. Many times the amplification and feedback of errors in one part of a complex system may result in an overall SEE response which is far greater than simply a sum of individual SEE responses. It may well be the case that the only way to properly evaluate the SEE response of a complex system outside of very sophisticated modeling techniques is to measure entire system and subsystem responses rather than simply evaluating critical components of these systems. While static testing is useful to provide a baseline evahwtion of SEE response, operating devices and subsystem “at speed” is required to gain a complete understanding of this response. It may not always be possible, but at least an attempt should be made to observe the trend of the SEE response with speed. For example, if technical limitations such as cabling or electromagnetic interference preclude operation “at speed” in ground based SEE measurements, then an achievable set of operational rates is certainly more useful than relying on purely static measurements. 6.3 BETTER ENVIRONMENTAL
MODELS
An equally important part of any SEE prediction technique is an accurate model of the radiation environment of the target application. It is a tautology that this environment is not going to go away and moreover, is largely variable. In addition to
II-57
modulations in the environment due to the normal solar cycle, we have cosmic ray and solar particle models that are not well understood. We have also seen from experiments such as onboard CRRES that our existing trapped proton and electron models are not as good as we would desire. In the CRRES case, for example, a third proton belt was observed in the “slot” region which endured for several months. An important fiture trend in the field of SEE qualification, therefore, is to not only have a better understanding of the SEE response of emerging technologies but to gain a better understanding and better models of the radiation environment which will give rise to these phenomena in the first place. Better SEE rate prediction capabilities will result in the appropriate reduction of “safety margins” or “factors” and enable expanded use and more rapid insertion of advanced technologies. 6.4 MEANINGFUL
GROUND DATA
We have seen in the section on prediction methodologies that the development of predictive techniques and models have provided important feedback to the experimenter as regards what constitutes important data at the accelerator. In the case of protons, we have seen that: 1. Good rate prediction depends principally on accurate high energy asymptotic cross section data. It is this measure which has the greatest impact on SEE response models. 2. In dealing with complex high speed systems, it is necessary to have accurate definitions of what constitutes an “event” and to be able to independently measure and quanti~ discrete types of events in order to form a complete SEE response picture over a variety of operating conditions. 3. Accurate fluence and dosimetry are more critical than ever in evaluating the performance of increasingly large scale integration in devices which may be subject to flux and timing effects. Likewise, for heavy ions, we have seen that: 1. Good rate prediction depends principally on accurate deterrnination of the threshold LET, which value has the greatest impact on SEE response models. 2. It is important to use high energy particles at accelerators both as a more accurate simulation of galactic cosmic rays and which will have sufficient range to penetrate surface layers and sensitive volumes, and that the LET within the sensitive volume must be known accurately. 3. As is the case with protons, accurate fluences and fluxes are increasingly important when dealing with complex technologies, and additionally the large scale integration makes consideration of track dependent effects such as simultaneous single event multiple bit upsets even more important.
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6.5 MEANINGFUL
SPACE DATA
The traditional method for predicting application SEE rates is to collect ground data at an accelerator, use this data with environmental device modeling codes, speci~ a target environment/orbit, and produce a predicted upset rate. In an indirect fashion, the observed upset rates are sometimes compared to the predictions and used as feedback to improve either the predictive techniques, the environmental models, the ground test methodologies, or some combination of the three. This feedback is often incidental. CRRES was an example of a program developed with the specific goal of measuring SEE rates in space for a variety of devices and technologies in order to validate and improve these models. One of the limitations in evaluating CRRES data for this purpose was that there were significant differences between the operating conditions for those devices flown and those used as part of the ground test program so that direct comparisons between predicted and observed SEE rates were complicated. The Microelectronics and Photonics Test Bed represents a significant trend in advancing the field of SEE qualification. In the case of MPTB as shown in Figure 20, DUT experiment cards are developed such that the identical hardware and software which will be flown in the experiment are used at accelerator facilities. This will allow not only for direct SEE qualification in space of selected devices, technologies, and subsystems, but also a direct validation of predictive techniques currently employed as well as the supporting environmental models. The data from this kind of one-to-one experiment will be invaluable to assessing the state of the art in SEE response prediction and ground test methodologies. SPACE
GROUND
RADIATION
RADIATION
/p
MINIMIZE SYSTEMATIC AND UNCERTAINTIES
ERROR
IDENTICAL MEASUREMENT AND SPACE
FOR GROUND
Figure 20: Measurement scheme for the MPTB Experiment.
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7.0 CONCLUSIONS
SEE Qualification is a critical area in the overall space qualification process. It has been shown that ground based measurements, reasonable analysis, and mission radiation environment scenario fold together to promote system performance, reliability, The era of specific device and technology hardening is moving and cost effectiveness. high performance aside to the systems approaches which take advantage of microelectronics produced in the free market world. Figure 21 is a sample of the new age. This Figure shows the full picture of SEE assessment on advanced technology high performance GaAs MESFET devices from ground based measurements to analysis to
I
GaAsSCFLSR
1 B
O.,”1
1
3
10
Klo
COMPLEMENTARY GaAs SR
EFFECTIVE LET(MeV/[m@n2))
UPPER A
I= T
GaAaSCFLSR COMPLEMENTARY (timeper upaatper GaAsSR davic8) (timeper upaatper device)
GEO@ 15” indin
11.9to 23,5 daya
1 0.2MeVl(n@xn2) 0.7MeV/(m@an’)
B
LOWER
I 2.2X1O’ cnl%av I 1.2x104 cm*/dav I I 1.4 MeV/(mg/un’) 1.8 MeV/(m@rn2)
19 to 4.5 yeara
J
1
!
Figure 21: Sample of SEE analysis showing progression from raw data collection to pararneterizing of data to on-orbit SEE rate predictions for a current generation device. upset rate predictions for an application. This is the type of information that is required to begin to address the SEE Qualification issue. The future will bear SEE Qualifications for not only devices, but flight boards, sub-systems, and systems as they become measurable on the ground and in space with experimental programs. In summary, then, the student is directed to keep in mind the following major points:
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●
We have seen a wide variety of single event effects observed ranging from simple transients to complex and catastrophic interactions as the field of SEE phenomena has matured over the last two decades.
●
The wide variety of observed phenomena may still be loosely quantified concept of cross section as a measure of event rate.
●
Ion accelerators are useful tools in approximating the natural radiation environment with certain limitations. While the underlying mechanisms are somewhat different, both protons and heavy ions can initiate SEE phenomena and both must be considered.
●
Simulator tools such as 252Cf, ion microbeams, and pulsed lasers are useful and practical in screening and investigating specifics of SEE effects. These tools are generally best utilized in conjunction with or supplemental too particle accelerator data.
●
Ground-based measurements should be used in conjunction with one or more of several SEE rate prediction methodologies and associated environmental models to assess single event effect rates. Each of these methodologies has advantages and disadvantages, and all are subject to the inherent limitations and uncertainties in the existing environmental models.
●
SEE rate predictions should be coupled with system fault tolerance determining SEE immunity and impact.
by the
analysis
in
●
SEE hardness assurance is a difficult and complex issue, depending on reproducibility of the manufacturing process. One way to provide SEE hardness assurance is with the pulsed laser simulator tool at the appropriate manufacturing step.
●
The future trends of device and system integration demand innovative techniques to properly assess SEE rates and response for these systems. Programs such as Microelectronics and Photonics Test Bed are in part specifically designed to address system-level issues.
ACKNOWLEDGMENTS I would like to gratefully acknowledge the generous help, contributions, and technical support of my wonderfil colleagues and friends, particularly Mr. Patrick McDonald, Dr. Al Wolicki, Dr. Al Knudson, and Dr. Steve Buchner, all excellent contractors to our efforts at the Naval Research Laboratory. I also would like to acknowledge the generous encouragement and technical discussions from my close colleagues Mr. Jim Kinnison from the Johns Hopkins Applied Physics Laboratory and soon to be Dr. Heather Dussault from Rome Labs. Lastly, I would like to thank my
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section head, Dr. Art Campbell and my branch head, Mr. Jim Ritter, for providing me opportunities and resources beyond that which I thought were possible.
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REFERENCES [1] J, T. Wallmark and S. M. Marcus, “Minimum Size and Maximum Packing Density of Non-Redundant Semiconductor Devices,” IRE Proc., W, 286, (1962), [2] D. Binder, E. C. Smith, and A, B. Hohnan, “Satellite Anomalies from Galactic Cosmic Rays,” IEEE Trans., on Nucl. Sci., NS-30, 2675, (1975). [3] T. C. May and M. H. Woods, “Alpha-Particle Induced Soft Errors in Dynamic Memories,” IEEE Trans. on Elec. Dev., ED-26, 2, (1979). [4] J. C. Pickel and J. T. Blandford, “Cosmic Ray Induced Errors in MOS Memory Cells,” IEEE Trans. on Nucl. Sci., NS-25, 1166, (1978). [5] J. F. Ziegler and W. A. Lanford, “Effect of Cosmic Rays on Computer Memories,” Science, Vol. 206,776, (1979). [6] C. S. Guenzer, E. A. Wolicki, and R. G. Allas, “Single Event Upset of Dynamic RAMs by Neutrons and Protons,” IEEE Trans. on Nucl. Sci., NS-26, 5048, (1979). [7] A. B. Campbell and E. A. Wolicki, “Soft Upsets in 16K Dynamic RAMs Induced by Single High Energy Photons,” IEEE Trans. on Nucl. Sci., NS-27, 1509, (1980). [8
W, A. Kolasinski, J. B. Blake, J. K, Anthony, W. E. Price, and E. C. Smith, “Simulation of Cosmic-Ray Induced Soft Errors and Latchup in Integrated-Circuit Computer Memories,” IEEE Trans. on Nucl. Sci., NS-26, 5087, (1979).
[9 J. C. Pickel and J. T. Blandford Jr., “Cosmic-Ray Induced Errors in MOS Devices,” IEEE Trans. on Nucl. Sci., NS-27, No, 2, 1006, (April 1980). [10] S. Ko, “Obsemation of Alpha Particle Effects in the Charge-Coupled IEEE Trans. on Nucl. Sci., NS-27, 1500, (1980).
Image Sensor,”
[11] C. M. HsieL P. C. Murley, and R. R. O’Brien, “A Field-Funneling Effect on the Collection of Alpha-Particle Generated Carriers in Silicon Devices,” IEEE Elec. Dev. Ltrs., EDL-2, 103, (1981). [12] F. B. McLean, and T. R. Oldham, “Charge Funneling in N- and P- Type Si Substrates,” IEEE Trans. on Nucl. Sci., NS-29, 2018, (1982). [13] G. C. Messenger, “Collection of Charge on Junction Nodes from Ion Tracks,” IEEE Trans. on Nucl. Sci., NS-29, 2024, (1982). [14] J. P. Retzler, “Fault Tolerant Memories for Single Particle Radiation Effects,” IEEE Trans. on Nucl. Sci., NS-28, 3998, (1981). II -63
[15] W. E. Price, J. C. Pickel, T. Ellis, and F. B. Frazee, “Cosmic Ray Induced Errors in 12L Microprocessors and Logic Devices,” IEEE Trans. on Nucl, Sci., NS-28, 3946,(1981), [16] C. S. Guenzer, A. B. Campbell, and P. Shapiro, “Single Event Upsets in NMOS Microprocessors,” IEEE Trans. on Nucl. Sci., NS-28, 3955,(1981). [17] A. B. Campbell, A. R, Knudson, and E, A. Wolicki, “Investigation of Soft Upsets in MOS Memories with a Microbeam,” Nucl. Inst. and Meth., Vol. 191,427, (1981). [18] A. R. Knudson and A. B. Campbell, “Use of an Ion Microbeam to Study Single Event Upsets in Microcircuits,” IEEE Trans. on Nucl. Sci., NS-28, 4017, (1981). [19]A. B, Campbell, “Upsets in Error Detection and Correction Integrated Circuits,” IEEE Trans. on Nucl. Sci., NS-29, 2076, (1982), [20] J. L. Andrews, J. E. Schroeder, B. L. Gingerich, W. A. Kolasinski, R. Kog~ and S. E. Diehl, “Single Event Error Immune CMOS RAM,” IEEE Trans. on Nucl. Sci., NS-29, 2040 (1982). [21] E. L. Petersen, P. Shapiro, J. H. Adarns, Jr., and E, A. Burke, “Calculation of CosmicRay Induced Upsets and Scaling in VLSI Devices,” IEEE Trans. on Nucl. Sci., NS-29, 2055, (1982). [22] S, E. Diehl, J. E. Vinson, B, D. Shafer, and T. M. Mnich, “Considerations for Single Event Immune VLSI Logic,” IEEE Trans. on Nucl. Sci., NS-30, 4501, (1983). [23] E. L. Petersen, J. B. Langworthy, and S. E. Diehl, “Suggested Single Event Upset Figure of Merit” IEEE Trans. on Nucl. Sci., NS-30, 4533, (1983). [24] S.
E. Diehl-Nagle, “A New Class of Single Event Errors,” IEEE Trans. on Nucl. Sci.,
NS-31, 1145, (1984). [25] A, R. Knudson, A. B, Campbell, P. Shapiro, W, J. Stapor, E. A, Wolicki, E, L. Petersen, S. E. Diehl-Nagle, J. Hauser, and P. V. Dressendotier, “Charge Collection in Multilayer Structures,” IEEE Trans. on Nucl. Sci.,NS-31, 1149,(1984). [26] W. L. Bendel and E. L. Petersen, “Predicting Single Event Upsets in the Earth’s Proton Belts,” IEEE Trans. on Nucl. Sci., NS-31, 1201, (1984) [27] Y. Takami, F. Shiraishi, T. Gok~ Y. Shimano, M. Sekiguchi, K. Shida, N. Kishida, H. Kadotani, T. Kikuchi, N. Hoshino, S. Murakarni, H. Anayama, and A. Morio,
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“Investigation of Single Event Upset Subject to Protons of Intermediate Range,” IEEE Trans. Nucl. Sci., NS-37, 1953, (1990).
Energy
[28] W.J. Stapor, J.P. Meyers, J.B. Langworthy, and E.L. Petersen, “Two Parameter Bendel model Calculations for Predicting Proton Induced Upset,” IEEE Trans. Nucl. Sci., NS-37, 1966, (1990). [29] J. R. Hauser, S. E, Diehl-Nagle, A. R. Knudson, A. B, Campbell, W. J. Stapor, and P. Shapiro, “Ion Track Shunt Effects in Multi-Junction Structures,” IEEE Trans. on Nucl. Sci.,NS-32,4115, (1985). [30
S, P. Buchner, D. Wilson, K, Kang, D. Gill, J. A. Mazer, W. D, Raburn, A. B. Campbell, and A. R. Knudson, “Laser Simulation of Single Event Upsets,” IEEE Trans. on Nucl. Scit, NS-34, 1228, (1987).
[31 The earliest references to the term: “Single Event Phenomen~” are the following: The 1980 IEEE NSREC had a session entitled: “Single Particle Upset Phenomena.” In the 1981 IEEE NSREC, the session title was: “Single Event Upset Phenomena.” And, finally, in the 1982 IEEE NSREC the session title was: “Single Event Phenomena.” It would appear, therefore, that the IEEE NSREC began naming this area as “Single Event Phenomena” and then others also began using this term. From 1982 to 1993 (and perhaps also 1994) the NSREC each year had a session entitled: “Single Event In the 1986 IEEE NSREC a fnst paper (by Japanese authors) which Phenomena.” used the term Single Event Effects in its title. A June 1987 draft of an ASTM test method (document 11A38) was entitled: “The Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices.” [32] R. C, Martin, N. M. Ghoniem, Y. Song, and J. S. Cable, “The Size Effect of Ion Charge Tracks on Single Event Multiple-Bit Upset” IEEE Trans. on Nucl. Sci., NS34,1305, (1987). [33] J. H. Hold and K. F. Galloway, “Analytical Model for the Single-Event Burnout of Power MOSFETS, IEEE Trans. on Nucl. Sci,, NS-34, 1275, (1987). [34] T. F. Wrobel, “On Heavy Ion Induced Hard-Errors in Dielectic Trans. on Nucl, Sci., NS-34, 1262, (1987).
Structures,” IEEE
[35] W. J. Stapor, P. T. McDonald, A. R. Knudson, A. B, Campbell, and B. G. Glagol~ “Charge Collection in Silicon for Ions of Different Energy but Same Linear Energy Transfer,” IEEE Trans. on Nucl. Sci., NS-35, 1585, (1988). [36] D. M. Newbeny, J. D. Towey, D. H. Kaye, and S. P. Sexton, “Single Event Induced Errors in VLSI Logic Circuits,” J. Radiation Effects, Res. & Engrg., Vol. 5, No. 1, June 1987, 11-65
[37] D, M, Newbemy, “SEU Hardening Approaches for VLSI Logic Circuits,” J. Radiation Effects, Res. & Engrg., Vol. 6, No. 2, 146 September 1988. [38] J. A. Zoutendyk, L. D. Edmonds, and L. S. Smith, “Characterization of Multiple-Bit Errors from Single-Ion Tracks in Integrated Circuits,” IEEE Trans. on Nucl. Sci., NS36,2267, (1989); see also Martin et al 1987. [39] R.C. Martin, N.M. Ghoniem, Y. Song, and J.S. Cable, “The Size of Ion Charge Tracks on Single Event Multiple-Bit Upset,” IEEE Trans. on Nucl. Sci., NS-34, 1305 (1987). [40] P.T, McDonald, W.J. Stapor, A.B. Campbell, and L.W. massengill, “Non-Random Single Event Upset Trends,” IEEE Trans. Nucl. Sci., NS-36, 2324 (1989). [41 ] J, R. Srour, R. A. Hartmann, and K. S. Kitazaki, “Permanent Darnage Produced by Single Proton Interactions in Silicon Devices,” IEEE Trans. on Nucl. Sci., NS-33, 1597, (1986), [42] P. W. Marshall, C. J. Dale, E. A. Burke, G. P. Summers, and G, E. Bender, “Displacement Damage Extremes in Silicon Depletion Regions,” IEEE Trans. on Nucl. Sci., NS-36, 1831, (1989). [43] J. R. Srour and R. A, Hartrnann, “Enhanced Displacement Darnage Effectiveness in Irradiated Silicon Devices,” IEEE Trans. on Nucl. Sci., NS-36, 1825, (1989). [44] R. Kogzq W. R, Crain, K. B. Crawford, D. D. Lau, S. D. Pinkerton, B, K. Yi, and R. Chitty, “On the Suitability of Non-Hardened High Density SIU4MS for Space Applications,” IEEE Trans. on Nucl. Sci., NS-38, 1507, (1991) [45] C. Dufour, P. Gamier, T. Carriere, J. Beaucour, R. Ecoffet, and M. Labrunee, “Heavy Ion Induced Single Hard Errors on Submicronic Memories,” IEEE Trans. on Nucl. Sci., NS-39, 1693, (1992). [46] T. R. Oklham, K, W. Bennett, J. Beaucour, T. Carriere, C, Colvey, and P. Gamier, “Total Dose Failures in Advanced Electronics from Single Ions,” IEEE Trans. on Nucl. Sci,, NS-40, 1820, (1993). [47] P.R. Bevington, “Data Reduction McGraw-Hill, 1969.
and Error Analysis for the Physical
[48] G.S. West, J.J. Wright, and H.C. Euler, “Space and Planetary Environment
Guidelines for Use in Space Technical Memorandum 78119.
Vehicle
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Development,
Sciences,”
Criteria. 1977 Revision,” NASA
[49] K, Murray, W.J. Stapor, and C. Casteneda, “Calibrated Charged Particle Radiation System with Precision Dosimetric Measurement and Control,” Nucl. Instr. and Meth. A, 616 (1989). [50] A. Constantine et al., “A new Method for Using 252Cf in SEU Testing,” IEEE Trans. Nucl. Sci., ns-37, 1916 (1990). [51] S. Buchner, K. Tang, IEEE Trans. Nucl. Sci. (1987) [52] J, Melinger, IEEE Trans. Nucl. Sci. (1994) [53] S. Buchner, “Laser Simulation of Single-Event Effects: A State of the Art Review”, ARL-CR-185 (1995) [54] A. B. Campbell, A. R. Knudson, and E. A. Wolicki, “Investigation of Soft Upsets in MOS Memories with a Microbeam,” Nucl. Instr. and Meth,, 191,427, (1981). [55] A. R, Knudson and A. B. Campbell, “Use of an Ion Microbeam to Study Single Event Upsets in Microcircuits,” IEEE Trans. Nucl. Sci. NS-28, 4017, (1981). [56]
K. M. Horn, B. L. Doyle, and F. W. Sexton, “Nuclear Microprobe Single-Event Upsets,” IEEE Trans. Nucl, Sci. NS-39, 7, (1992).
Imaging of
[57] K. M. Horn, B. L, Doyle, F, W, Sexton, J. S. Laird, A. Saint, M. Cholew~ and G. J. F. Legge, “Ion Beam Induced Charge Collection (IBICC) Microscopy of ICS: Relation to Single Event Upsets (SEI-1),” Nucl. Instr. and Meth, B77,355, (1993). [58] F. W. Sexton, K. M. Horn, B. L, Doyle, J, S. Laird, M. Cholewa, A. Saint, and G. J. F. Legge, “Ion-Beam-Induced Charge-Collection Imaging of CMOS ICS,” Nucl. Instr. and Meth. B79, 436, (1993). [59] P. J. McNulty, “Track Sh_ucture Effects at p-n Junctions in Microelectronic “Nuc1. Tracks Radiat. Meas. 16, 197, (1989).
Circuits,
[60] M. B, H. Breese, G. W. Grime, F. Watt, “Microcircuit Imaging Using Ion Beam Induced Current,” Oxford Nucl. Phys. Report OUNP-91-33 (1991). [61] A. R. Knudson, A. B. Campbell, P. Shapiro, W, J. Stapor, E. A. Wolicki, E. L. Petersen, S. E. Diehl-Nagle, J, Hauser, and P. V. Dressendorfer, “Charge Collection in Muhilayer Structures,” IEEE Trans. Nucl. Sci. NS-31, 1149, (1984).
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[62] J. R. Hauser, S. E. Diehl-Nagle, A. R. Knudson, A, B. Campbell, W. J. Stapor, P. Shapiro, “Ion Track Shunt Effects in Multi-Junction Structure,” IEEE Trans. Nucl. Sci. NS-32, 4115, (1985). [63]
A. R. Knudson, A. B. Campbell, J. R. Hauser, M. Jessee, W. J. Stapor, and P. Shapiro, “Charge Transport by the Ion Shunt Effect,” IEEE Trans. Nucl. Sci. NS-33, 1560, (1986).
[64]
A, R. Knudson and A. B, Campbell, “Charge Collection in Bipolar Transistors,” IEEE Trans. Nucl. Sci. NS-34, 1246, (1987).
[65] J.C, Pickel and J.T, Blandford, “Cosmic-Ray IEEE Trans. Nucl. Sci., NS-27, 1006 (1980).
Induced Errors in MOS Devices,”
[66] E.L. Petersen, J,B. Langworthy, and S.E. Diehl, “Suggested Figure of Merit,” IEEE Trans. Nucl. Sci., NS-30, 4533 (1983).
Single Event Upset
[67] D, Binder, EC. Smith, and A.B. Holman, “Satellite Anomalies Cosmic Rays,” IEEE Trans. Nucl. Sci., NS-22, 2675 (1975),
from Galactic
[68] D. Binder, “~alytic SEU Rate Calculations Compared to Space Data,” IEEE Trans. Nucl. Sci., NS-35, 1570 (1988). [69] D. Newberry, “Single Event Upset Error Propagation Between Interconnected Logic Devices,” RADECS Proceedings, 471 (1991).
VLSI
[70] H. Dussault et al., “High Energy Heavy-Ion-Induced Single Event Transients Epitaxial Structures,” IEEE Trans. Nucl. Sci., NS-41, 2018 (1994).
in
[71] J. W. Howard et al., “A Novel Approach for Measuring the Distribution of Charge in a Heavy-Ion Track,” IEEE Trans. Nucl. Sci., NS-41, 2077 (1994).
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1995 NSREC SHORT COURSE
(aicJ MADISON
A First-Principles
Approach to
Total-Dose Hardness Assurance
Daniel M. Fleetwood Sandia National Laboratories Albuquerque, NM 87185-1083
This work was supported by the U. S. Department of Energy through contract number DE-AC 04-94AL8 5000, and by the U. S, Defense Nuclear Agency through its hardness assurance program.
III- 1
m-2
A First-Principles
Approach to Total-Dose Hardness Assurance
Daniel M. Fleetwood Sandia National Laboratories Radiation Technology and Assurance Department 1 2 3 4 5
6
7 8 9 10
Introduction Design Margin and Safety Factors Focus Sources and Environments MOS Testing Issues 5.1 Defects in MOS 5.2 Dose-Rate Effects Technical Basis for MIL-STD 883D, Test Method 1019.4 (TM 1019.4) 5.3 5.3.1 Time Dependent Effects 5.3.2 Constraints on Low-Dose-Rate Hardness Assurance 5.3.3 “Rebound” Testing 5.4 TM 1019.4 5.4.1 Main Flow 5.4,2 Comparison to BS 22900 5.5 Overstress Requirement in TM 1019.4 5.5.1 Switched-Bias Effects 5.5.2 pMOS Transistors 5.5.3 Interface-Trap Annealing 5.5.4 Latent Interface Traps 5.6 IC Data 5.7 Relaxing Rebound Test Requirements 5.8 Less Conservative Oxide-Charge Tests Weapon Applications 5.9 5.9.1 Issues 5.9.2 10-keV X-ray h-radiation 5.9.3 Possible Test Methods Synopsis of MOS Test Methods 5,10 Effects of Bum-in 5.11 If Parts Fail 5.12 Testing Issues for Bipolar Devices QML Non-destructive Testing Conclusions and Future Trends Acknowledgments 1. INTRODUCTION
When I first began doing radiation tests in 1984, the subthreshold (midgap) test method of Winokur and McWhorter [1,2] had just been developed, and I wasn’t sure exactly what sort of response to expect from the MOS transistors I was trying to test. Still, I was fairly sure that the drastic changes in threshold-voltige shifts due to interface- and oxide-trap charge (AVit and AVOJ
III-3
that occur in Fig. 1 between the first and second (30 and 60 krad(Si02)) radiation levels were not due to the radiation-induced charge trapping that I was trying to measure. What went wrong? One can see from the current-voltage (I-V) traces of Fig. 2 that the gate oxides were not destroyed. However, from the large “stretchout” (likely due to interface traps) and shifts (likely due to oxide traps) in the curves [1,2], it was clear that a lot more damage had been done to the device between the end of the first exposure and the end of the second exposure than during any of the other irradiation intervals. 6 4 “Interface 2
Traps”
0I -2
“Oxide Traps”
A
o
Dose
0.8
0.6
0.4
0.2
1
[Mrad(Si02)]
Figure 1: Inferred threshold voltage shifts due to interface- and oxide-trap charge for nMOS transistors wi;h 45-nrn gate oxides irradiated with CO-60 gamma rays at a dose rate of -400 rad(Si02)/s at +10 V bias. 1E-02
PRE
3!Z4
6E4
IE5
2E5
4E5
lE-03 lE-04 l!z-05
lE-OG if-07 I E-Oe 1E-09 lf-10
IE-11 [E-12 IE-13 IE-14 lE-
15_
Gate Voltage (v) Figure 2: I-V curves for the devices and exposures of Fig. 1.
III-4
7E5
1E6
Figures 1 and 2 turned out to be a simple and dramatic illustration of the point that, if one follows a poorly thought-out test plan, one often gets a meaningless result. I was originally shown “how” to do total-dose exposures by someone who did not realize a basic point about device testing. That is, if one simply flips a switch to turn on some types of non-current-limiting power supplies while MOS gates and drains sit unprotected, one can get transient spikes that can darnage the device for reasons (high-field or high-current stress induced damage) that have nothing to do with the device’s fimdamental radiation response. I quickly learned not to do this! The example of Fig. 1 is extreme, but it serves to illustrate the important point that blindly following a test plan is not enough. One must have an idea of the likely impact of test conditions on the test results, and on how the test results relate to device response in the use environment. This will be a recurring theme of our discussion below. 2. DESIGN MARGIN AND SAFETY FACTORS
The groundwork for a cost-effective hardness assurance program is laid at the system design level, If radiation hardness constraints are not adequately considered at this point, hardness assurance testing can be difficult or impossible. If a 3-krad(Si02)-hard commercial device is selected as the cornerstone of a 200-krad(SiOz) system, without hefty shielding, no amount of cleverness (or expense) in hardness assurance will salvage a poor design. On the other hand, if parts are selected on the basis of characterization tests that have demonstrated the part can survive radiation levels well in excess of system requirements, hardness assurance testing difficulty, time, and expense can be kept to a minimum. For discussions of conservative design practices and safety factors in the designhrdness-assurance cycle, the reader is referred to the short course segment and related articles by Pease and co-workers [3-5], the recent review by Holrnes-Seidle [6], as well as military handbooks [7,8] and other related publications [9-14]. Because these issues have been discussed so thoroughly in Refs. [3-14], we will not repeat the discussions here, but we cannot overemphasize their importance to a successful hardness assurance program. As just one practical example of how design margin can be used to reduce hardness assurance costs and difficulty, the Qualified Manufacturers List (QML) test methodology permits reduced sampling in lot acceptance tests of components certified to meet radiation levels 2-10 times more severe than system requirements. Further, routine lot acceptance tests may be waived if the parts are certified to levels more than 10-times greater than the intended application [5,15-19]. Thus, judicious use of design margin and safety factors can reduce lot acceptance costs without significantly increasing system risk. 3. FOCUS Keeping in mind the importance of design margin and safety factors, our remaining discussions will focus on how to perform cost-effective, conservative total-dose tests in several common applications. These test methods are based on a first-principles approach to estimating (or bounding) device response in the use environment, and can be used in support of the device characterization phase ofs ystem design as well as in the ultimate lot acceptance testing. So, for example, if one wishes to establish a well-defined safety factor for a particular use environment,
III-5
one should base this factor on tests performed with a similar use environment in mind. Else one may be unpleasantly surprised to find that parts thought to be hard enough for the intended application on the basis of testing under one set of conditions may actually fail in the environment of interest, as we will illustrate below. The discussion will focus primarily on small-signal MOS device and circuit response, though bipolar response will also be discussed briefly. Special issues associated with power electronics [20,21] are not treated, though many of the test methods discussed here can also be applied to evaluate their response [22,23]. We will also not discuss total-dose testing issues for GaAs or other III-V semiconductor technologies, because (lacking gate insulators) they usually are not nearly as sensitive to ionizing radiation effects as MOS or bipolar devices. However, the reader is referred to treatments of displacement effects due to high-energy protons and electrons that may impact their response in a space environment [24-30]. Further, special total-dose testing issues associated with CCD’s [31-34], photonic components [35-40], specialized sensors (e. g., HgCdTe [41-43]), etc. will not be addressed here, though they can be critical to system survivability. Both ionization and displacement effects can be important to the response of many optoelectronic components in a space environment [31-44]. The primary radiation environment considered below is the natural, near-earth space environment, which has been described in detail in previous short courses and recent reviews [45-51], and which will not be described here. Of course, conclusions reached for a low-dose-rate space environment also apply to equivalent low-dose-rate radiation environments, such as electronics in high-energy particle accelerators or nuclear reactors. We will also briefly discuss testing issues associated with generic tactical and high-dose-rate weapon environments. Finally, we will concentrate on the response of electronics at ordinary ambient temperature (- 25°C). The special challenges associated with cryogenic or high temperature operation [52-56] will not be addressed in this section, but will be covered in Part IV of this short course [52].
4. SOURCES AND ENVIRONMENTS Sources employed in typical total-dose radiation effects studies are grouped schematically by dose rate in Fig. 3. For high-dose-rate exposures, which are representative of a generic highdose-rate weapon environment, a good choice is a linear accelerator (LINAC), though LINAC’S are more commonly used for dose-rate-induced photocun-ent testing. For some experiments described below, the White Sands Missile Range (WSMR) LINAC was used. The beam consisted of 20-MeV electrons, and was tuned to provide - 8 ps pulses at a dose rate of - 6 x 109 rad(Si02)/s. Thus, the dose per pulse was -48 krad(SiOz). For higher total-dose irradiations, multiple pulses were generated at a rate of 10 Hz. For the parts considered here, these conditions allowed repeatable operation of the LINAC, reliable dosimetry, and avoidance of space charge effects--all of which are very important considerations when using a LINAC for high-rate totaldose testing [45,57-59].
m-6
LINAC
6X109 rad/s 8 ps Pulse -50 krad/ Pulse
ARACOR X-RAY CO-60 Y-CELL
I
50-5000
I
rad/s
CS-137
0.05 -O.2rad/s
I 109
10-6
10-3
TYPICAL
10°
EXPOSURE
103 TIMES
106
109
(SeC)
Figure 3: Sources suitable for simulating high-dose-rate weapon and low-dose-rate natural space environments, as well as laboratory (intermediate dose rate) sources more appropriate for simulating some types of tactical military applications and for hardness assurance testing. Typical laboratory sources were also used in the studies discussed below. An AECL Gammacell 220, with a dose rate of - 100-400 rad(Si02)/s, and an ARACOR Model 4100 Semiconductor X-ray Irradiator [60], with dose rates from - 50 to -5000 rad(Si02)/s, were chosen as common laboratory sources that are often used in lot acceptance and.lor QML-based hardness assurance programs [16, 17,59,6 1,62]. These sources are also excellent simulations of many types of “tactical” military environments. Finally, to approach a “space-like” environment, devices were also exposed in Shepherd Cs137 gamma sources at dose rates ranging from 0.002 to 0.2 rad(Si02)/s. Dosimetry can be a challenge in many of the sources, and (while important) is beyond the scope of this course. The reader is referred to Refs. [59,63,64] for discussions of appropriate dosimetry practices in these different radiation sources. With some care, however, one can achieve inter-source calibrations accurate to better than t 10- 15°/0 [59], which is just outside typical part-to-part variations in radiation response for MOS threshold voltages on a well controlled line [61]. To make contact with possible use environments, one must know not only the relative dose rates of the irradiation sources and the environments of interest, but also the typical irradiation type and energies. In a high-dose-rate weapon environment, one can have a wide range of x-ray and garnrna-ray energies, which can make simulation fidelity a very difllcult challenge. These issues are beyond the scope of the present short course [65]. In a typical satellite environmen~ the dose is deposited by energetic protons and electrons, whose relative densities and energies will depend on many factors. The most notable of these are the orbit of the satellite and the status of the solar cycle (i. e., whether there have been recent flares) [45-51]. Because satellite electronics are typically shielded at least modestly [49], it is generally presumed that the lowest
III-7
energy electrons and protons do not reach the electronics, and that CO-60 irradiations provide a reasonable simulation of the ionization effects in a space environment. (Note that CO-60 irradiation does not provide a good simulation of displacement darnage effects, without at a minimum correcting for differences in nonionizing energy loss in the particle versus photon environments [24,29].) However, some adjustments may be required to compensate for the potentially large differences in CO-60 and proton charge yield [45,66]. For the purposes of this course, we assume that corrections for the effects of shielding and proton charge yield have been applied to arrive at the total ionizing dose and dose rate specifications for a given system. The primary remaining issue to confront is that of the widely different dose rates of laboratory irradiation sources and the use environment. Finally, we should mention that, with corrections for dose enhancement and/or charge yield [17,59,6 1,67], 10-keV x-ray irradiations can also be useful in a hardness assurance program, as we discuss later. 5. MOS TESTING
ISSUES
Because of their low power requirements, and increasing dominance in the digital IC world, MOS electronics are very important components of virtually all military and space systems. For that reason, and because of their sometimes complex and occasionally bewildering response, we will give an especially thorough treatment of MOS total-dose testing issues. And, because of the attention being given to the natural space environment at present, most of the discussions will center around total-dose qualification of parts for space and other low-dose-rate radiation environments. Further, a detailed discussion of the technical basis for US MIL-STD 883D, Test Method 1019.4 [68] will be provided. 5.1 Defects in A40S MOS total-dose response is governed almost exclusively by ionization effects in critical insulating layers in the devices, and by defect buildup at or near the critical interface between the Si channel layer and the Si02 gate oxide [45,57,69]. A schematic illustration of the most important defects in modem MOS gate oxides [70] is shown in Fig. 4. Defect location is shown in Fig. 4(a), and their impact on electrical response is indicated in Fig. 4(b). Historically [69], defects in the MOS system have been grouped into “oxide traps” and “interface traps.” Oxide-trap charge shifts the threshold voltage of MOS transistors. For thermal oxides in a radiation environment, the dominant oxide-trap charge is positive and due primarily to radiation-induced trapped holes [45,57,69]. These shift the threshold voltage of a MOS transistor negatively. Interface traps will shift the threshold voltage of an n-channel MOS transistor positively, and that of a p-channel transistor negatively [45,57,69]. Interface traps also lead to mobility degradation [71,72], Recently, it has become clear that it can be difficult with standard characterization techniques to distinguish between the effects of interface traps and near-interracial oxide traps (i. e., “border traps”) on MOS transistor I-V characteristics [70,73-85], like those of Fig. 2. Although this can be an important distinction in studies of the physics of MOS charge trapping, it is not critical to the discussions of MOS hardness assurance here. Moreover, for the hardened transistors for which most of the charge separation measurements have been performed in this study, interfacetrap effects usually are more important than border-trap effects [79,82]. So, for the remainder of this course we will adopt the historical convention of assuming that most of the defects that do III-8
not exchange charge with the Si during the measurements (“fixed states” in Fig. 4(b)) are oxide traps, and most of the defects that exchange charge with the Si (“switching states” in Fig. 4@)) are interface traps. Gate
SI
Oxide
‘a) /“-
+-
++ +
+
Defect Location
v
~
*
+
Oxide Traps— ++
+
++
“Border Traps”
+
/
‘InterfaceTraps
(b)
“Swltchlng States”+ Electrical Response
v ~
“Fixed States”~
<
i, Gate
Oxide
SI
Figure 4: Physical location (a) and electrical response (b) associated with defects in MOS gate oxides. (After Ref. [70].) Properties of interface traps and oxide traps and methods to estimate their densities in irradiated MOS devices have been reviewed in detail many times [45,57,69], and the nature of border traps is an emerging topic of great interest [70,73-85]. However, here we will concentrate on the significance of these defects in radiation hardness assurance testing, and will not discuss the basic mechanisms that underlie this response in significant detail. For a review of the basic mechanisms of radiation response and hardening techniques, the reader is especially urged to read last year’s short course segment by Jim Schwank [45], as well as many other reviews in the literature [57,69,85]. Of course, it is not only important to understand the radiation response of MOS gate oxides, but (as discussed later) the response of parasitic isolation oxides (e. g., field oxides) can also be quite important to MOS radiation response [45,57,69]. 5.2 Dose-Rate E#ects The principal difficulty associated with defining a simple total-dose test method for MOS electronics is illustrated clead y in Fig. 5, which shows threshold voltage shifts for an early version of a radiation-hardened CMOS process developed at Sandia National Laboratones [86]. Irradiations at dose rates typical of conventional laboratory sources (20-200 rad(Si02)/s) showed relatively large negative threshold voltage shifts at a dose of about 1 Mrad(Si02). A negative
III-9
threshold voltage shil? in an nMOS transistor can cause failures due to excess leakage current in MOS IC’S. Unfortunately, testing at lower dose rates, closer to space environm~nts, showed large positive threshold voltage shifts at even lower doses! Positive threshold voltage shifts (often called “rebound” or “super-recovery,” in which the value of the threshold voltage not only “turns around” with increasing total dose but also exceeds its preirradiation value [87,88]) can lead to circuit and system failures due to reductions in noise margin, speed, and timing problems [86,89]. So, testing MOS devices at rates of 20-200 rad(SiOz)/s gave both the wrongfailure dose and the wrong failure mode for a space application. Conversely, if one were using low-rate irradiation to attempt to qualifi a MOS device for use in a higher-rate application (e. g,, some highdose-rate weapon applications [58,59]), again the wrong failure doses and failure mechanisms would be observed. The origin of the response in Fig. 5 is the combination of the neutralization of trapped oxide charge with increasing time or decreasing dose rate, and the continued increase in interfiice traps with time, as we will discuss in detail below. 1 , I , m, ,, , 1 1, 111 , , r 1 1mm 2.0
1.0 THRES140LOVOLTAGE SHIFT A
‘FAllJMETIMINO
V,h (V) 0.0
LEAKAGS ‘FAKURE——— —— -1.0 ———————————— t 1 1 1 1 11111 1 1 1 111I~ 11
,04
35
,05
35
,06
DOSE (rad (S!))
Figure 5: Threshold voltage shifts versus dose and dose rate for CO-60(2 -200 rad(Si02)is) and Cs- 137 (0, 1 rad(SiOz)/s) irradiations of MOS transistors with 45-rim oxides from Sandia’s old baseline technology. The “failure levels” indicated on the figure at * 1 V are for illustration purposes only. Real failure doses in MOS IC’S maybe at higher or lower levels. (After Ref. [86]). A similar type of effect is illustrated in a different way in Fig. 6, based on experiments and modeling performed by AlIan Johnston on a Z80A NMOS microprocessor [87]. Here the dose required to produce a given positive or negative threshold voltage shifi (* 0.45 V) on an input transistor is plotted as a function of dose rate. Again, at higher rates, the failure is due to oxidetrap charge which causes negative threshold voltage shifts. At intermediate rates, the level of oxide-trap charge has decreased somewhat and the amount of interface-trap charge has increased, leading to a near cancellation of the two effects at - 1 rad(SiOz)/s. How this cancellation may naturally occur in some types of process development, in which process step selection is based on minimizing the net n-channel threshold voltage shift of nMOS transistors, has been discussed by Winokur et al. [90]. At lower rates, interface traps lead to rebound effects and device failure
111-10
due to positive threshold voltage shifts at lower doses again. While the dramatic peak observed in Fig. 6 at intermediate dose rates may not exist for all MOS IC’S, this kind of behavior certainly is a concern for establishing MOS total-dose test standards. By testing only after a single irradiation at one dose rate, as was allowed in versions 1019.1 - 1019.3 of the US military total dose test standard [86,9 1], one could never be sure whether one could accurately assess the correct failure dose or failure mode for MOS devices and IC’S with responses like those of Figs. 5 and 6. The examples we have provided here are for simple transistor parameters; similar effects for a wide range of IC parameters are observed in Refs. [58,88,89,92-101]. 120 ,
!
100
1
80 FAILURE LEVEL (krad (S1))
.1
FAILURE DUE To POsmve THRESHOLD SHIFT
60
●
MODEL CALCULATION
● I MEA9URED FAILURE LEVEL9 I FAILURE CRITERIA: Avth - f 0.45V I
I
v %1
4
40 1
20
//
I I ~
/
({
FAILURE DUE TO NEGATIVE THRESHOLD SHIFT
r.
—0
;~
n . 10
-3
I
I
,.-2
,..l
I 10°
I 10’
I
I
102
103
104
DOSE RATE (rad (Sl)/s)
Figure 6: Dependence of nMOS circuit failure level for Z80A microprocessors on the dose rate of the irradiation. (After A. H. Johnston, Ref. [87]). 5.3 Technical Basis for MIL-STD 883D, Test Method 1019.4 The above discussion of Figs. 5 and 6 shows why a new test method was required for space applications of MOS devices and IC’s. In this section and those that immediately follow, we illustrate the technical basis of the present US Military Standard 883D, Test Method 1019.4, which is the first standard test method that checks specifically for rebound failures in space. Unless otherwise stated, discussions apply equally to bulk, epitaxial, or silicon-on-insulator (S01) MOS devices. An exception is that some issues associated with parasitic field oxides in bulk or epitaxial MOS devices must be discussed in the context of sidewall and/or buried insulators on SOI materials [102]. 5.3.1, ~ J)eD*rlt Effects. To lay the groundwork for the new test method, a series of experiments was performed to determine the equivalence between higher-dose-rate exposures and subsequent annealing and low-dose-rate testing [59]. Figure 7 shows threshold voltage shifts as a fh.nction of postirradiation anneal time for nMOS transistors with 60-nm gate oxides. “Zero” on the time axis is taken to be the beginning of each of the respective irradiation periods. Data are shown for LINAC, x-ray, and Cs- 137 irradiations to a total dose of 100 krad (SiOz) at 6 V
HI-11
bias, followed by room-temperature anneal at the same bias. Dose rates range from 6 x 109 to 0.05 rad(SiOz)/s. Trends in the data Me qualitatively consistent with those illustrated by Figs. 5 and 6 above, That is, at high rates, the threshold shifts are fairly large and negative, dominated by oxide-trap charge. At lower rates, the shifts are positive, indicating an excess of interface traps. Threshold-voltage shifts following high-rate irradiation plus room-temperature anneal at
0.8 0.4
0 \
AVth (v) -0.4 -0.8
CS-137 0.16 rad/s
-1.2
CS-137 0.05 rad/s
-1.6[,
I
1
1
I
I
I
10
10
10
10
1:
1;
1 7
10
1
TIME (see) Figure 7: Threshold voltage shifts for nMOS transistors with 60-nrn gate oxides built in a variation of Sandia’s old baseline technology versus postirradiation anneal time for varying dose rate exposures to a dose of 100 krad(Si02). The irradiation and anneal bias was 6 V. (After Ref. [59].) 10-4
1o-e
d
I
I
g
10-’0
I
10-’2 —-
1
I
I
1
-2
-1
0
1
CS-137, 0.105 rad/s 100 krad (7dy) 1 I I I
2
3
4
VG(V) Figure 8: I-V curves for the devices of Fig. 7 following a 7-day exposure to Cs-137 irradiation to 100 krad(Si02) at 0.165 rad(Si02)/s, and a 10-keV x-ray exposure to the same dose followed by room temperature anneal for 7 days. The irradiation and anneal bias was 6 V. (Ai?er Ref, [59].)
m-1 2 ,,
the same bias are, to within the experimental uncertainty, equal to low-dose-rate exposures at equivalent times [59]. This common response is reinforced by Fig. 8, where I-V curves are overlain from 10-keV x-ray exposures followed by a 1-week anneal, and from a 1-week Cs- 137 exposure to the same dose. Clearly, there is no difference in response. 0. I I I I I I I Cs-137 -0.4
-
s
-0.0
-
Z * d
-1.2
-
(0.0S rad/s)
0 CS-137
(0.165
rad/8)-
X-ray, 52 rad (S102)/s X-ray, 5550 rad (S102)/s
-1.6
“
LINAC, 2 PULSES, 6 x 109 rad (S102)/s 1 1.0
-2.0 0.1
I 10
1 ,.2
I
I
,03
,04
1
I ,&
,.6
,07
t (s)
Figure 9: AVOIversus irradiation and anneal time for the devices and irradiation conditions of Fig. 7. (After Ref. [59].) 1.2
0.9 ●
AVit
(v)
●
, AU
CS-137 (0.16 rad/s)
CS-137 (0.05 rad/s)
X=ray
0.6
A A
~
0.3 LINAC 0 10’
I
I
I
I
I
I
I
10°
10’
102
103
104
105
106
7
10”
TIME (see) Figure 10: AVit versus irradiation and ameal time for the devices and irradiation conditions of Fig. 7. (After Ref. [59],)
Figures 9 and 10 show the values of AVOtand AVi~,respectively, inferred via the subthreshold technique of Winokur and McWhorter [1,2] for the data of Figs. 7 and 8. Values of AVOtin Fig. 9 show an approximately linear-with-log-time decrease, and lie on a common “transient-
111-13
annealing curve,” which has been observed by many authors to govern the trapped-hole neutralization rate in MOS oxides [59,86,103-107]. (This behavior is apparently independent of whether the dominan t oxide-trap charge neutralization mechanism is true annealing or compensation by electron capture at border traps [83,88,108], or whether the hole neutralization process is dominated by tunneling or thermally activated processes [109].) In contrast, the interface-trap buildup in Fig, 10 increases with increasing time, at least up until times greater than -105 s for these devices. At long times and fixed total dose, the value of AVit is approximately constant with increasing i.mdiation time or annealing time. The mechanisms responsible for this type of interface-trap buildup have been discussed extensively [45,57,69,85], and are beyond the scope of this course, No “latent” buildup, corresponding to a tier increase in interface-trap density after an apparent saturation, is observed for these devices [110,111]. It is the different time dependencies of oxide-trap charge neutralimtion (Fig. 9) and interface-trap buildup (Fig. 10), as well as their different effects on MOS threshold voltage, that lead to the changing magnitude and sign of the threshold voltage shift (Fig. 7). Despite these dependencies, it is reassuring that the response of MOS devices under these irradiation and anneal conditions fall on universal defect growth and annealing curves over an extremely wide range of dose rates [59]. Thus, fid.arnentally different processes are not occurring during irradiation at different dose rates; differences are just due to differences in time dependent oxide-trap charge neutralization and interfhce-trap buildup. It is important to note that the equivalence of high-rate irradiation and annealing to low-rate response occurs only when electric fields and temperature are constant throughout the irmdiation and annealing sequences [59]. This does not present a practical problem for MOS devices under typical worst-case radiation response conditions, but causes difficulties in deftig hardness assurance tests for bipolar devices [1 12], as we will discuss later. The results of Figs. 7-10 show that 5,3.2. Co~ on J,ow-Dose-Rate ~ Ass~. MOS device response in a low-dose-rate application (e. g., space or high-energy particle accelerator) should be no different than after a higher-rate irradiation and equivalent annealing period. While this is extremely usefid information, very-low-dose-rate exposures and very-long-term anneals are often expensive and impractical for hardness assurance tests. To shorten the irradiation and/or annealing period, it must be recognized that one cannot perform a cost-eflective sfandard test that filly simulates the response of a b40S device at the end of its lzjle in a space environment, This is because, with higher-rate imdiations and/or anneals, one cannot simultaneously reproduce the amount of oxide- and interfhce-trap charge that will exist in an irradiated MOS oxide after years of exposure in space. Instead, one can only define a test sequence that will ensure that a device will perform within consistent, bounded limits during its lifetime [104,113,114]. There have been several approaches to attempt to explicitly address MOS hardness assurance for low-dose-rate applications [17,18,22,23,58,59,88,91,93,100,103,104,106,1 13-125]. These have included part categorization methods [1 17,125], attempts to model and predict device longterrn response [18,22,23,91,103,106,1 15,1 18-122,124], and methods to conservatively bound the response of MOS devices and IC’S at low dose rates [17,58,59,88,93,100,104,1 13,114,1 16,123]. Some of these techniques require extensive characterization tests, test structure data, and/or teststructure-to-IC-correlations which are often not possible to obtain given system cost and part
111-14
availability constraints. Therefore, the most common general approach used in the past, and that employed in US MIL-STD 883D, Test Method 1019.4 (TM 1019.4) [68], is that of bounding part response in the space environment. TM 1019.4 was developed subject to the following general constraints [104,113,1 14]: 1. The test must screen out both interface- and oxide-charge related failures. 2. The test must work for both hardened and commercial IC’S. 3. The test must be conservative (that is, some good product is allowed to be excluded on the basis of the test method, but bad product is not allowed to be accepted). 4. The test must be relatively inexpensive, and easy to perform and interpret. 5. The test must not depend on the availability of test structures. Indeed, the method should be useful even in absence of pre-existing knowledge about an IC’S radiation response. Because of these constraints on a standard test method, optimized tests can be developed for a well-characterized technology that improve on standard tests, for example by being less conservative, as illustrated below. We now discuss in detail the technical basis that underlies the main sequence of MIL-STD 883D, Test Method 1019.4, as applied to MOS IC’s. Throughout this discussion, we will cite examples that primarily deal with well-characterized Sandia technologies; however, qualitatively similar effects (at least with respect to their relevance to a discussion of test methods for low-dose-rate applications) have been reported on many other technologies in the literature [20,22,23,56,58,87,91-99, 117,123]. Thus, it should not be presumed that these recommendations are relevant to only one type of technology. In general, the tests outlined below are conservative (and perhaps too much so for some) for all MOS technologies of which we are aware. 5.3.3. “Rebound” Testirw. The idea behind MIL-STD 883D, Test Method 1019.4 (TM 1019.4) is very straightforward, Because the two dominant defect types in MOS oxides shift the threshold voltage differently, and because their time dependencies are so strikingly different (compare Figs. 9 and 10), it is recognized that a single device or circuit test performed immediately after any single irradiation cannot provide a conservative estimate of CMOS response in space. Because oxide traps shifi the threshold voltage negatively, and interface traps shifl the threshold voltage of an nMOS transistor positively, at least two independent tests are required to bound the separate contributions of each type of defect to the device response [104,113,114]. How one accomplishes this task can be debated; indeed, there are a number of plausible methods one might envision to do this. What cannot be disputed, though, is that at least a two-step test must be performed to assess the suitability of MOS devices or IC’S in a low-dose-rate environment in a practical, cost-effective manner (unless either oxide trap or interface trap effects can be rigorously demonstrated to be negligible in a technology of interest). Bounding oxide-trap charge effects in space is relatively straightfonvard. As illustrated in Fig. 9, oxide-trap charge decreases monotonically with decreasing dose rate or annealing time [103-109], Thus, as long as the dose rate of any laboratory exposure is greater than the expected dose rate in space, there will be more oxide-trap charge a>er the laborato~ irradiation than in space. Further, because interface-trap charge tends to increase with increasing irradiation III- 15
andlor annealing time, there will be less interface-trap charge afier a laborato~ exposure than in space, Together, these two points ensure that gate (or field) oxide transistor threshold voltage shifts will be more negative after a laboratory exposure than in space (see Fig. 7), so a laboratory test is already conservative with respect to oxide-trap charge effects [104,113,114], That the test may be overly conservative for many devices is an important issue that is discussed below. Bounding interface trap effects in space is a more difllcult matter. With room temperature irradiation and/or room-temperature annealing, one can never be confident that one has performed a fully conservative test for positive threshold voltage shifts and mobility degradation effects associated with interface traps. This is because, as discussed in the previous point, there will simply always be more oxide-trap charge and fewer interface traps following such a sequence than in space. See Fig. 7 for example. With increasing irradiation and/or anneal time, the nMOS threshold voltage shift is becoming more and more positive. Thus, MOS IC’s built with processes like that of Fig. 7 will always have a more positive threshold voltage shift in space than in a corresponding laboratory test, unless the test sequence is modified to get around this difficulty. Hence, attempts to “simulate” MOS response in space simply by performing a low-dose-rate irradiation (at a rate that does not approximate the actual rate experienced in the application) are inherently nonconservative, unless characterization tests have been performed to show that no hrther interface-trap growth or oxide-trap charge annealing will occur in the devices of interest on time scales longer than that of the exposure. This is an important point that is often not appreciated in discussions of testing MOS devices for space applications. To provide a conservative test for interface-trap effects in space, one must ensure that the secondpart of the test sequence leads to a more positive nMOS threshold voltage shljlfollowing the laboratory test than will occur in space [104,113,114]. (The reader should note that other conditions are sometimes placed explicitly or implicitly on “rebound” testing in the literature that are stronger than this requirement [88, 100], e. g., that the method must anneal out the oxide charge while leaving the intetiace traps, but the text condition is sufficient for the test to be conservative with respect to interface trap effects.) Figures 11-13 build on the early work of Schwank et al. [88] to show how one can design a “rebound” test to accomplish this goal. First note in Figs, 11-13 that, as in the case of Figs. 7-10, CO-60 irradiation to 300 krad(SiOz) at a dose rate of -400 rad(Si02)/s followed by - 10b s of room-temperature annealing at the same bias (6 V) is equivalent to a 0.165 rad(Si02)/s Cs-137 exposure [59,1 13]. In Fig. 11 AVO~ recovery is accelerated by raising the temperature during annealing to 100”C [88], and in Fig. 12 the interface-trap buildup rate increases with 10O°C annealing. This combination is ideal for providing a conservative test of interface traps at low dose rates; the oxide trap charge is miniThus, both components act to make the mized, and the interface-trap charge is maximized. threshold shift more positive during annealing, as shown in Fig. 13. More importantly, the value of the threshold voltage shift in Fig. 13 is significantly more positive after the annealing sequence shown than it would be after a much longer period at 25”C, given any kind of reasonable extrapolation of the threshold-voltage shift during the next 1-2 decades of time in the 25 “C data of Fig. 13. The comparison between interface trap effects at 25°C and 10O°C is made more explicit in Fig, 14 for these devices, where times corresponding to 1 wk, 1 yr, and 10 yr are indi-
111-16
cated for the interfhee-trap data- Indeed, it appears that the room-temperature curve is approaching a limit defined by the high-temperature data in this case. 0.2 i I I I I CO-80 (400 rad/a) +100 ‘C ANNEAL o
~ -0.2 w s z
-0,4
.
CO-137 (0.165
rad/s)
CO-60 (400 rad/s)+25 -0.6
-
-0.8
“
, ~2
I
1
1
I
1 , #
,04
,03
‘C ANNEAL
,07
, @
t(8)
Figure 11: Threshold voltage shift due to oxide-trap charge for nMOS transistors with 32-rim oxides, irradiated to 300 krad(Si02) with CO-60 or Cs- 137 gamma rays. Gates were biased at 6 V during irradiation and annealing. Anneal temperatures were 25°C or IOO”C. (After Ref. [1 13].) 1.0
I
0.8
CO-60 (400 rad/s)+ 100”C ANNEAL
I
I
I
,/ a
0.6 ~ w s q 0.4
1
I
A +
/ tt f f t
It
CS-137
(0.165
rad/a)
~
0.2
CO-60 (400 rad/a)+25°C
0
102
I ,03
ANNEAL
I
I
,.6
,.4
I ,.O
I 107
t(s)
Figure 12: Threshold voltage shifts due to interface traps for the devices of Fig. 11. (After Ref. [1 13].)
III-1 7
0.8 [
CO-60 (400 rad/s)
+ 10O°C
ANNEAL
CO-60 (400
rad/s)
+
/
0.2
CS-137
rad/s)
(0.165
0
-“.,~ , “2
, “4
103
, “s
,.8
,.7
t (s)
Figure 13: Net threshold voltage shifts for the devices of Figs. 11 and 12. (After Ref. [1 13],) 1.0
I
I
I
I
1 yr
1 wk
100”C ANNEAL
I
I
I
10 yr
OJ3
y: ~
.Lti
\\
------
---
0.6
E 0.4
a
.J’’?T--””””
Y 0.2
25”~ ANNEAL
C&137
(0.165
rad/s)
I
I
I ,.8
300 krad CO-60 (400 radla)
i I n w
I
,~2
, fJ3
I ,~4
1 ,.6
,~e
107
, ~e
t (s)
Figure 14: Extrapolation of the data of Fig. 12 to space-like time scales. (After Ref. [59].) Figures 11-14, as well as other studies on MOS devices [59,88,92 -97,100,104,1 13,1 14], suggest that a “rebound test” at 10O°C might be a suitable accelerated aging test for interface-trap effects at low dose rates. Why one should not try to raise the temperature more to further accelerate rebound effects is illustrated in Fig. 15, where it is shown that one risks of reducing the value of AViLif still higher temperatures are used [56]. For lower temperatures, AVit increases or is constant with anneal time. Above a given temperature, though, interface traps begin to anneal.
HI-18
The temperature at which interface traps begin to anneal appears to decrease with increasing levels of damage, ranging from a low of 100”C for the baseline devices irradiated to 1,0 Mrad(SiOz) toahigh of-1750C for Mod Bdevices irradiatedtol Mrad(Si02). A similar range of results was observed for other technologies in later work by Lelis et al. [126]. Hence, “rebound testing” can provide an effective way to test for interface-trap related failures in space, but care must be exercised that significant interface-trap annealing does not occur at the temperature chosen for the rebound test. \
4
~OST-RAD
KEY
O
BL (1 Mrad)
❑ BL (0.1 Mrad)
3
0
MOD B (3 Mrad)
A MOD B (1 Mrad)
2 A Vlt (V) 1
0
.
1 25~25
I
I
75 1
I
I
I 1.1 I I 100 450 200
125 1
175
I
1 250
25(
~
225
TEMPERATURE(“C) I I 1
I
I
1
I
10
14
16
18
20
02468
12
TIME (DAYS) Figure 15: Postinadiation interface-trap buildup and annealing as a function of increasing anneal tem-
perature over a period of up to 20 days. All irradiation and annealing was at 10 V bias. Devices were built either in !%ndia’s old baseline (circles and squares) or improved “Mod B“ process. The annealing sequence consisted of 3 days at 25”C, 1 day each at 75°C, 100”C, etc., as shown by the dual x-axis. At the end of the sequence, the baseline devices were held at 250”C for 3 days, and the Mod B devices were held at 250”C for 10 days. (After Ref. [56].) one usually cannot use a single test after a high-temperature annealing sequence to simulate (as opposed to assist in bounding) the low-dose-rate response of MOS devices is confirmed in Fig. 16. Here we show leakage current as a fh.nction of irradiation and anneal time for devices built in a commercial process by Oki Semiconductor [86,89,114]. At higher dose rates and shorter anneal times, the leakage is a primarily a result of parasitic field oxide inversion due to radiation-induced-hole trapping; at low dose rates ador very long annealing times, the leakage is primarily due to hole trapping in the gate oxide (because of the more effective recovery of the parasitic field oxide leakage current at long times or low dose rates [86,89,114]). In Fig. 16 it can be seen that CO-60 irradiation at any of the dose rates shown provides a conservative estimate of the leakage at long times, because the leakage current decreases with decreasing dose rate or increasing anneal time. However, even if the device is irradiated to 5-times the dose level of interest (here -6 krad(SiOz)), i. e., to 30 krad(SiOz), the leakage current at the end of a subsequent one-week, 100”C anneal is less than that after room-temperature anneal or low-dose-rate irradiation to an equivalent or longer time. The high-temperature anneal here neutralizes too That
111-19
much of the oxide-trap charge to simulate the low-dose-rate response. Thus, as expected from the above discussion, one cannot ordinarily design a single-point test to conservatively estimate both interface- and oxide-trap charge effects in a space environment [1 14]. ,0-2 I I I I I OKI
,~4 ,0-6 g A 104
,01
,02
,~ 3
,~ 4
106
,05
,07
t (s) Figure 16: Leakage current at O-V gate bias as a function of total dose, dose rate, and annealing time and temperature for Oki transistors, The open symbols are for room temperature annealing; the solid symbols are for 10O”Canneals. (After Ref. [114].) I I 1 I I I
10’2
109
106
lf)3
100
10-3
10%
Typical Dose Rates (rad(Si)/s) Figure 17: Schematic illustration of typical dose rates associated with weapon, laboratory, and space and accelerator radiation sources/environments. 5.4 TM1019,4 5.4.1. m “transform”
Flow. Figure 17 conceptually illustrates how rebound testing can be employed to laboratory irradiations into an assessment of interface-trap effects at low dose rates
111-20
in a space, accelerator, or other low-dose-rate irradiation environment. This is translated into a detailed flow chart of the main sequence of TM 1019.4 in Fig. 18 [68,93,113,114]. The initial irradiation to 50-300 rad(Si)/s is specified to be performed in a CO-60 gamma source at a temperature of 24 * 6°C. A (1.5 mm Pb)/(0.7 mm Al) container for the devices is required to minimize potential dose enhancement effects [64], unless these effects have been characterized and shown to be negligible for the sources being used.
I
Imadiate to spec level 50-300 rad(Si)/s
I
YeElectrical Test <2hr
I
Parts OK
Figure 18: Main sequence of the US military-standard ionizing radiation effects test method (MIL-STD
883D, Test Method 1019.4). (After Refs. [68,93,1 13,114].) The range of dose rates and the timing requirements specified in the document are intended to assist in standardizing test results [16,86], and to make contact with some types of tactical radiation environments. If all dose rate and timing specifications in the main flow of TM 1019.4 are satisfied, a part that passes the testing sequence of TM 1019.4 is qualified for use in either a tactical or space application. For parts that are intended for use only in a low-dose-rate space application, the text of TM 1019.4 permits testing at lower dose rates, as discussed below. Below we will also discuss some details of the test flow at length, as there has been some confusion and controversy about these points. It is hoped that this discussion will at least make the original intent of the test method clearer, and facilitate decision making about its “proper” use in a totaldose hardness assurance program. Before discussing these points, though, it is also necessary to
111-21
briefly consider how TM 1019.4 compares with its European ESA/SCC Basic Specification (BS) No. 22900 [16,127]. 5.4,2. ~
standard
test counterp~
to J3S q.~.
T?vf 1019.4 shares many similarities with BS 22900, but also contains some differences in test philosophy and test details. These similarities and differences have been discussed in detail in a recent review article by Winokur et al. [16]. Some important differences between the methods are summarked in Table 1. Table 1: Summary of some important differences between the US military total-dose testing standard, TM 1019.4, and its European counterpart for space, BS 22900. (After Ref. [16].) Parameter Environments Covered Radiation Source Dose
Dose Rate Anneals
I
BS 22900 TM 1019.4 I Tactical and Space space CO-60 Gamma CO-60, Electron Accelerator * 100/0of specification; * 10’%of specification; additional 50% overstress reno overstress required cmired before rebound test before rebound test 50-300 rad(Si)/s; lower rates Exposure times 96 h; Window 1:1-10 rad(Si)/s; permitted for space applications Window 2: 0.01-0.1 rad(Si)/s No room temperature anneal; 24 h room temperature anneal; 1-wk, 100”C rebound test 1-wlG 100°C rebound test
The lower dose rates specified in BS 22900 are a consequence of its focus purely on space and other low-dose-rate radiation environments. TM 1019.4, which also covers tactical military environments in its main test flow, specifies higher dose rates unless it is known that the parts will only be used in a space or similar low-rate application [68]. The lower rates and the 24-h room-temperature anneal in BS 22900 will be less conservative for oxide-trap charge related effects in space (but still sui%ciently conservative that the test remains effective) than will be the main sequence of TM 1019.4, for reasons discussed in section 5.8 below. Using an electron accelerator instead of a CO-60 source allows one to increase the amount of displacement damage for a given level of ionizing radiation damage [24,25], which may be beneficial for simulating the space environment for some types of analog bipolar circuits, CCD’S, and other components that are more sensitive to displacement effects than are typical MOS devices [24-34]. The lack of a 50 0/0overstress in BS 22900 could be significant, for reasons discussed in the next section, if characterization testing is not sufficient to ensure that worst-case bias conditions are used in the irradiation and anneal portions of the test. Nevertheless, in general, the two tests are quite similar in spirit and in most details, and discussions of one overlap significantly with the other [16]. This is convenient for discussions of hardness assurance for low-dose-rate applications.
III-22
5.5 Overstress Requirement
in TM 1019.4
Data like that of Figs. 11-15 led to the recommendation of performing a one-weelq 10O”C biased anneal after irradiation as a standard rebound test to serve as a conservative screen for interface-trap related failures in space [59,88,104,113,114]. However, several issues other than just nMOS postirradiation response under static irradiation/anneal bias conditions were also considered before arriving at a final recommendation for the TM 1019.4 main test sequence [104,1 13]. We consider several of these points in the next section, which discusses the addition of- 50 ?40margin in the rebound test described in TM 1019.4 [68]. 5.5.1. Switched-Bias F.ffecU. MOS IC’S in real system applications are not usually held in one bias condition for the duration of a mission. Therefore, it is important to consider the effects of changing the MOS gate bias during or after irradiation. For example, in Fig. 19 it is shown that switching the bias between irradiation and annealing can sometimes lead to more positive nMOS transistor threshold voltage shifts than for constant irradiation and anneal bias conditions [102,122,128-132]. For Fig. 19, devices irradiated with O V on the gate and annealed at 6 V (the “0/6” case) show nearly a -40 0/0more positive n-channel threshold voltage shifl than devices irradiated and annealed at static bias (the “6/6” case) [129]. This trend has also been observed after 10O°C annealing [129]. The increase in nMOS threshold voltage shift is due both to a decrease in the amount of net positive oxide-trap charge in the 0/6 case than the 6/6 case, and to an increase in the number of interface traps [115,122,129]. 2.0
[
1
I
I
—IRRADIATE ~ANNEAL
I
I
i
(2S”C)
1.6
(6/6) ‘o’’;’&: (0/0) ev
(6/0)
0 Ov . . .. ~ .
0.1
1.0
100
1000
TIME’:h) Figure 19: Threshold voltage shifts (in V) as functions of irradiation and annealing time for nMOS transistors with 32-rim oxides irradiated to 1.0 Mrad(S i02) in a CO-60 gamma source at a dose rate of 278 rad(Si02)/s. Devices were irradiated either at 6 V or OV bias, and then annealed at room temperature either at the same or at switched bias conditions. Devices are labeled by (irradiation/annealing) bias; for example, (0/6) = (OV rad/6 V anneal), etc. (After Ref. [129].)
A significantly more positive value of nMOS threshold voltage shift has also been observed for AC-bias stressed devices than for DC-bias, for example in Fig. 20. This is associated with radiation-induced charge neutralization effects during the AC-bias irradiations, as discussed in
HI-23
detail in Refs. [1 15,122,133]. Moreover, these effects have been observed for many different types of devices with significant interface-trap densities [102,115,122,128-1 33]; that is, devices for which rebound effects are most important to assess correctly! Thus, some margin is required in a standard test method to guard against underpredicting the interface-trap density in a device operated under switched-bias conditions. A second irradiation to a level -50 0/0 above that of the specification is one way to achieve this margin, and has been incorporated into the main testirw. sequence of TM 1019.4 [68,104,1 13]. 1
0.5
0: s -c $-0.5
-1
CO-60 19.6 krad (Sl~ )/mln 48 nm OXIDE -1.5
0
0.2
1
I
I
I
0.4
0.6
0.8
1
1.2
DOSE [Mrad (S102 )] Figure 20: Threshold voltage shifts versus dose for 10-V, O-V, and 50-kHz (10/0 V) square-wave irra-
diations of nMOS transistors built in Sandia’s old baseline process. The dashed curves are fits to the steady state data. The solid curve is the AC response predicted by a semi-empirical model discussed in Ref. [122]. The triangles are the measured AC-bias data, (After Ref. [122].) 5.5.2. pMOS Tra_. Up until now, we have been discussing nMOS transistor response almost exclusively, because of its importance to NMOS and CMOS circuits, and because the nMOS transistor is the more challenging case to account for in hardness assurance testing. We should not neglect the point that pMOS transistors in CMOS circuits will recover somewhat during the 100”C anneal associated with the rebound test in TM 1019.4, Figure 21 shows threshold voltage shifts and components due to oxide- and interface-trap charge for a pMOS transistor irradiated to 200 krad(SiOz) and annealed at 100”C [113]. The change in pMOS threshold voltage during annealing will not be as great as the change in the nMOS threshold voltage because AVo~and AVit are both negative for pMOS transistors [45,57,69], and the AVi~ component’s growth can compensate partially for the AVO~component’s annealing, as in Fig. 21. Still, a 1-week, 10O°C anneal may not be simultaneously consemative for n and pMOS response, because the pMOS threshold voltage shift in space maybe more negative than that following the anneal. However, because the interface-trap growth at long times in pMOS transistors is nearly
III-24
always less than the trapped-positive-charge neutiization sure and subsequent test should be conservative for pMOS overstress in TM 1019.4, however, will increase the pMOS may assist in the detection of potential speed and timing nMOS and pMOS characteristics [1 13].
(see Fig. 21), the initial CO-60 expothreshold-voltage shfts. The 50 0/0 threshold shift afier the anneal. This problems in circuits with degraded
o
-0.1
1{ , ,1
-0.2 s s ~ -0.3
/“-’”0’
4
/‘~
‘v”
/*vth
-0.4
BIAS =OV had +
-0.5
I
1
0.01
0.1
I
I
10 1.0 TIME (h)
●noal)
1
1
100
1000
Figure 21: Threshold voltage shifts (in V) as a function of irradiation and anneal time for pMOS transistors with 32-rim oxides irradiated to 200 krad(Si02) in a CO-60 gamma source at a dose rate of -278 rad(Si02)/s at OV bias, then annealed at OV. (After Ref. [1 13].)
In Fig. 15 above it was shown that, for some device types, in5.5.3. ~erface-Trap ~. terface-trap annealing can be a significant problem in rebound testing if the anneal temperature was significantly higher than 10O”C. Even at 100”C, though, some (apparent) annealing of interface traps has been reported in the literature [22,23,97,129], although it cannot be ruled out that some of this apparent interface-trap annealing may be due to border-trap effects [70,73,74]. One case is shown in Fig. 22, where nMOS transistors are irradiated and annealed at 6 V and O V [129]. In two cases, the bias is constant between irradiation and anneal; in the other two, the bias is switched. Independent of other factors in Fig. 22, devices annealed at O V show small, but significant, interface-trap annealing. Devices annealed at 6 V show no reduction in the inferred interface-trap density during the annealing period. This raises the possibility that devices which are biased in the “off’ condition during rebound testing may recover somewhat, though this becomes less important if one has already built in the 50 0/0 margin via overstress testing in TM 1019.4. 5,5.4. tent Interface Traps. Although interface trap buildup ordinarily is observed to saturate at long annealing times, as shown in Figs. 12 and 14 for example, long-term increases have been observed after an initial saturation period in some technologies [1 10,11 1]. Although oxygen vacancies and hydrogen have been inferred to play a role in latent interface-trap buildup [73,1 10,11 1], the mechanisms causing this “latent” buildup are not well understood at this time.
III-25
1.01
1 LRAD
25°C
0.8
s : s
I
I
I
~—
ANNEAL
(
I
I
100° C) -4
-
0.6
a
ev 0.4
0.2
0
0.01
0.1
1.0 TIME
10
100
1000
(h)
Figure 22: Threshold voltage shifts due to interface-trap charge versus irradiation and anneal time for nchannel transistors with 32-rim oxides from Sandia’s old baseline process, irradiated to 200 krad(Si02) and annealed at 100°C. Irradiation and anneal labeling is the same as for Fig. 19. (After Ref. [129].) Nor is it known what fraction of technologies will show latent buildup. In all cases observed to date [73, 11O,111], latent interface trap buildup is significantly accelerated at 100”C over the buildup rate at room temperature. However, in some technologies it is not clear that a 1-wk rebound test filly factors in the possible contribution of latent interface trap buildup for MOS lowdose-rate response [1 10]. The additional 50 % overstress provides some extra margin against this type of response, though checking for additional interface-trap buildup at long times during elevated-temperature anneal tests during device characterization would seem prudent. We conclude that, though the text of TM 1019.4 permits one to omit the 50 VOoverstiess on the basis of characterization testing, one should be carefid first to perform a series of characterization tests that checks for (1) switched-bias effects, (2) pMOS response, (3) interface-trap annealing, and (4) latent interface-trap effects before waiving the overstress [1 13]. For complex MOS ICYs, it may not be straightforward from conventional parametric tests to assure that these areas are not of concern for a given processhechnology. This is an example where detailed characterization studies and/or test structure irradiations, like the transistor testing illustrated here, may give a better feeling for these effects. 5.6 IC Data.
Although TM 1019.4 was developed on the basis of a first-principles approach to hardness assurance, it is always worthwhile to check to see whether it really works for circuits! One bmrier to acquiring data of this type is that irradiation and annealing data taken according to the conditions of TM1019.4 must be compared to low-dose-rate IC data. These comparisons are in relatively short supply in the literature, though there is no shortage of data supporting large rebound effects in some types of MOS IC’S [58,86-89,92-100]. One example in which an explicit III-26
comparison of TM 1019.4 and low-dose-rate data was performed is shown in Fig. 23 [58]. For CMOS SRAM’S, read access time is particularly sensitive to rebound effects in nMOS transistors. Here, it is plotted as a function of dose for relatively low-rate (solid symbols) and TM 1019.4 testing, including the 50 % overstress discussed above. Clearly, as intended, the rebound overtest in TM1 019.4 leads to enhanced read-access-time degradation over that observed in the low-rate exposures. While this is by no means a definitive check of the assumptions underlying TM101 9.4, which was mostly developed on the basis of test structure (transistor) da@ it is always reassuring to see that the circuit response follows that of the test structures. We will discuss the comparison of IC and test stxucture radiation response further below, in connection with the QML approach to radiation hardness assurance. 400 “ ‘ox = 31nm 300
trdjns
-
VDD=5V 0,2 rad (S102)/s Cs= 137 Rebound Overtest
~o
200
0 100(
o PRE
ft )1
I
I
0.1
1
Dose,
SA3240 16 k SRAM 10
Mrad(S102)
Figure 23: Read access time as a function of different test conditions and total doses for 16k SRAM’S
irradiated either at a dose rate of 0.2 rad(Si02)/s, or according to TMl 019.4 (including a 50°/0overstress at a given dose before rebound testing), (Ai?er Ref. [58].) 5.7 Relaxing Rebound Test Requirements Rebound testing is an absolute necessary for many part types, and is a small price to pay to avoid possible catastrophic system failure due to improper part selection. Nevertheless, it is certainly more expensive to do rebound testing than it would be to omit it, if “safe” to do so. For this reason, TM 1019.4 contains many possible ways to avoid having to do rebound testing as part of a rouline lot acceptance program [68]. One way to determine whether a rebound testis required during lot acceptance for a device of interest is to perform full characterization tests on devices made in the same process technology. If it can be demonstrated that rebound failures are not a problem for the devices and irradiation conditions of interest, TM 1019.4 allows the rebound test to be omitted during lot acceptance [68]. We emphasize that this action should not be taken lightly, and certainly not without evidence that the devices are being manufactured on a process line for which variables that affect
III-27
radiation-induced interface-trap buildup, like postoxidation temperatures and annealing ambients [17,45,57,69,90,134-138], are under carefid control. Evidence of sufficient control could be demonstrated, for example, with lot sample tests using a 10-keV x-ray source to irradiate test structures that accompany the product wafers [17, 18,6 1], as discussed further below. If, and only if, (1) interface-trap densities of the test structures remain under statistical process control, and (2) the control level is below trap densities for which it has been demonstrated that product circuits will pass testing for the given application per the full TM 1019.4, including rebound testing, then it is reasonable for the parties to the test to agree to waive rebound testing during routine lot acceptance of product from that line to avoid unnecessary expense [68,104]. Unfortunately, not all product required for low-dose space systems can be procured from vendors who can (or will) demonstrate sufficient control of interface-trap densities to allow a waiver on rebound testing. Certainly, this would almost never be the case for a commercial line in which radiation hardness is neither a requirement nor a consideration during the product cycle [69,1 39, 140]. And, for a commercial line, a successful “spot test” on one product run cannot be used to “bless” Iiture (or past!) product runs, without evidence of control of variables impacting radiation hardness [18] (which is virtually impossible to obtain from a purely commercial line). However, for low-dose systems, it may be possible to waive rebound testing on the basis of a first-principles estimate of the maximum number of interface traps that can be generated in a MOS transistor with a gate oxide of a given (known) thickness. In Fig. 24 we plot the maximum positive threshold voltage shift that interface traps may induce in MOS devices with 20-nm, 50nm, and 100-nm oxides. These curves are derived from a simple calculation performed in the same spirit as a previous estimate of maximum hole trapping in MOS devices by McGarrity [141]. Specifically, it is assumed that interface-trap buildup can be described with the equation [104,141,142]: AVit s (q/&ox)Kgfy fit (tOX)2D ,
(1)
is the oxide dielectric constant, Kg (the charge generation where -q is the electronic charge, &OX efllciency) is the number of electron-hole (e-h) pairs generated in Si02, fYis the probability that a given e-h pair does not recombine, it is the interface-trap generation efllciency (i. e., the total number of interface traps eventually created per e-h pair), tOXis the thickness of the Si02 gate oxide, and D is the dose. The values of Fig. 24 were calculated assuming a charge generation efficiency of -8 x 1012 cm-3rad-l(SiOz) [143], and a charge yield of - 80% [143,144], both of which are reasonable for biased MOS devices in space. A value of ~~of - 20% was selected as typical of, or greater than, literature values of ~~ for MOS devices that exhibit very large interface-trap buildup [20,90, 104,136,142, 145]. Shifts in Fig. 24 assume no offsetting contribution to threshold voltage due to oxide-trap charge, even though this will be non-zero in space, and thus are intended to provide an approximate upper bound on the maximum device rebound for a given gate oxide thickness [104]. (Interface traps in field oxide regions of MOS devices do not adversely affect device response, because they shift the field oxide threshold voltage away from depletion, so omy interface traps in the gate oxide need be considered in this estimate.)
III-28
.3 F --------------H
=
o.ol~
1
2
5
10
20
50
100
DOSE [krad(S102)]
Figure 24: Maximum positive threshold voltage shift as a fimction of dose for nMOS transistors, calculated under the conditions of Eq. (1), (After Refs. [104,14 1].) Except for circuits with delicate timing requirements or low noise margin [87], or devices like power MOSFETS where it may not be possible to tolerate even small reductions in output drive current [20-23], circuits and devices with gate oxides thinner than - 100 nm can often fiction with the small positive threshold-voltage shifts observed below 5 krad (dashed line) in Fig. 24. For thinner oxides, this point of “automatic” acceptability moves to higher doses. For example, Eq. (1) suggests that a 10-rim oxide should have less than about +0.06 V rebound at 100 krad(SiOz) ! Thus, for thin enough gate oxides and low enough total dose requirements, it should be possible to waive rebound testing in many cases [104]. As technologies continue to evolve, MOS gate oxide thickness continues to shririk, State-of-the-art commercial oxides are now about -9-12 nm, so rebound should become less of a concern in the future, at least for systems with modest total dose requirements. This is good news! Of course, in absence of knowledge about device processing or circuit response, even for these types of devices, a limited amount of characterization testing that includes elevated-temperature annealing to screen for possible interface-trap effects certainly would be prudent for sensitive devices and IC’S. Still, oxides in older technologies are thicker, so MOS IC’s with oxides much thicker than 10-20 nm are routinely used in space systems. Thus, rebound testing cannot be dismissed without appropriate characterization testing and process control. Especially for advanced ICS in low-dose space applications, however, it is expected that some reduction in testing expense can be realized via fust-principles analysis per Eq. (1) [104]. 5.8 Less Conservative
Oxide-Charge
Tests
The above discussions have centered on using TM 1019.4 as a consemative test for MOS hardness in space. However, there is also evidence that many devices that fail the initial “oxidecharge” portion of TM 1019.4, when it is performed at a dose rate of 50-300 rad(Si02)/s, may actually be hard enough to function in space because of oxide-trap charge neutralization [86,93,1 03,104,1 16,121]. Although it is better to throw out a good device than to fly a bad one, it is useful to consider alternate approaches to the first part of TM 1019.4 (i. e, the initial irradiation-to-specification and test) that are less conservative with respect to oxide-trap charge. Such a test is especially useful for low-dose space systems (e. g., 5-20 krad(Si02)), for which some
III-29
commercial non-radiation-hardened devices might fill system needs. We present this example in quite a bit of detail, because of its practical significance, and because it illustrates the type of analysis one must do during the device characterization phase of a project to relax some of the requirements of TM 1019.4. Figure 25 illustrates how the “failure dose” of three commercial devices depends on the dose rate of the exposure. The Oki 8 1C55 is a device with a rapidly-recovering field oxide that causes failure during CO-60 irradiation at 50-300 rad(SiOz)/s, but not at dose rates (< 0.1 rad(Si02)/s) typical of space applications [89]. At low rates, failure is caused by oxide charge trapping in the MOS gate oxide [86]. The SGS 4007 and the Harris HM6504 are commercial devices that recover very slowly after CO-60 irradiation at 50-300 rad(Si02)/s, and exhibit failure doses at low dose rates that are similar to those observed at high rates [104,114]. Thus, the Oki device is typical of devices that will function at much higher doses in space than during CO-60 exposure at 50300 rad(Si02)/s, and the HM6504 and the SGS 4007 are typical of slow-annealing devices that will fail in space at doses only slightly higher than during CO-60 exposure at 50-300 rad(Si02)/s. 30 i
I
I
I
I
1
I
, I
I
OKI 81C55 \ s x
I
20
I I
t
I
I
I
1 I 1
SGS4007 I
&
1
~~ 1
1
● II
6.001
I 1
1
I
I
1
0.01
0.1
1
10
b
I 100
I
1 1000
Dose Rate [rad(Si)/s]
Figure 25: Failure dose versus dose rate for three types of commercial MOS devices. Irradiations at dose rates greater than 1 rad(Si)/s were performed with Shepherd or AECL gamma sources. Irradiations at lower rates were performed with Shepherd Cs-137 sources. For these sources, dose (Si) = dose (Si02). (After Ref. [104].) The wide range of variation in annealing rates among commercial devices is further illustrated with the vintage data of Fig. 26, in which n-channel transistor threshold voltage (not shifts, here) is plotted versus irradiation and anneal time for 4007-series inverters made by five different manufacturers [106]. The Fairchild inverter shows rapid hole annealing, as well as some interface-trap buildup. In fact, the primary issue raised by the Fairchild data is whether there is so much oxide-charge annealing and interface-trap buildup that the devices might fail in space due to positive threshold-voltage shifts (i. e., rebound), At the other extreme in annealing rate, the Solid State Scientific (SSS) devices show almost no recovery for the times measured. The National, RCA, and Motorola devices show intermediate recovery rates. Thus, Figs, 25 and 26 illustrate the wide range of device recovery rates that a test must cover to maximize acceptance of
111-30
good parts while rejecting all bad parts. Moreover, both gate- and field-oxide recovery due to oxide-charge annealing must be accounted for, as in modern commercial technologies the isolation oxides are likely to be of more concern than the gate oxides [139,140] (though the same annealing principles apply [104]). 3i 1 1 1 1 1
}-,-=+=’-’,(-+ 2
1
0 15
krad(Sl)x
‘
-1 ‘
1
1
IN
I@
I@ Irradiation
I
I 1@ and Anneal lime
lti
1~7
(s)
Figure 26: nMOS transistor threshold voltage versus dose for 50 rad(Si02)/s CO-60 irradiations of 4007-series inverters. The gate bias was high during all exposures. (After Ref. [106].) One (very) obvious candidate for a less conservative test for oxide-trap charge failure in space is simply to irradiate at lower dose rates. This is illustrated by the Oki data of Fig. 25. Clearly, lower-dose-rate irradiation leads to a higher dose-to-failure than CO-60 irradiation at 50300 rad(SiOz)/s, but still provides a conservative test for oxide charge effects at the still lower dose rates (<< 0,01 rad(SiOz)/s) typical of many space systems. One could therefore replace the CO-60 irradiation at 50-300 rad(SiOz)/s in TM 1019.4 with lower-dose-rate irradiation and still obtain a conservative estimate of oxide charge effects in space, as is done in BS 22900 [16,127]. Indeed, the body of TM 1019.4 allows one to do so, if it is known that the application of the devices being tested is exclusively a low-dose-rate radiation environment [68]. Such an option is not allowed for higher-rate applications (e. g., some weapon applications), where a low-rate test would be inherently non-conservative for oxide-charge effects, as discussed further below. There are a few practical difficulties with this approach. Low-dose-rate exposures are often expensive, difficult, and time consuming. There are also special challenges associated with dosimetry at very low dose rates [59]. Moreover, for devices like the HM6504 and the SGS 4007 in Fig. 25, one could perform very-long-term exposures and still find that the device is unsuitable for system application. These potential difilculties do not rule out low-dose-rate irradiation as a less conservative test of oxide-trap-charge related effects in space, especially for systems with modest total dose requirements that allow low-rate exposures to be performed on manageable time scales. Still, it is worth considering an alternative approach based on CO-60 irradiation at 50-300 rad(SiOz)/s and room temperature annealing, as has been proposed recently [93,104,116].
III-3 1
To illustrate the technical basis of the tests outlined in Refs. [93,104], for example, consider Fig, 27. Here we have simulated the response of non-radiation-hardened oxides following CO-60 irradiation and 25°C anneal via linear response theory [104,106]. The approach taken to derive these results is very general, and has been validated for many types of MOS circuits and devices [103-1 07]. The specific modeling is described in Ref. [104]; however, the general conclusions drawn do not depend on the exact details of the analysis. In Fig. 27 we compare the response of MOS devices following CO-60 irradiation and room-temperature anneal to their projected response after low-dose-rate irradiation to the same dose. (Interface trap effects are neglected in this discussion, and would have to be assessed separately via rebound testing at the conclusion of the room temperature anneal [93, 104,113,1 14].) The results of Fig. 27 are derived from measured (commercial, 45 nm thick) gate-oxide response to 40-krad(Si02) CO-60 irradiation at a dose rate of- 240 rad(Si02)/s, followed by a 1-week room-temperature anneal (curve B). In previous work, this CO-60 irradiation and annealing response has been shown to match low-dose-rate response over more than 4 decades of annealing time [104,114], justi~ing the approach illustrated here. In Fig. 27, this response is extrapolated an additional 2 decades to -109 rad(Si02)/s via linear response analysis, per the method of Refs. [104, 106], and plotted as curve B, which illustrates a 10 1%0per decade annealing rate. To generalize the discussion to higher and lower annealing rates, projected irradiation and anneal cumes are plotted in Fig. 27 for otherwise identical devices having annealing rates of 5 % and 15 YO per decade of annealing time (Curves A and C, respectively). 1 hr
18 r
1.2
15
1.0
~-
9 -
s
~
0.6
6
=
0.4
~ w
0.2
~
0.0
03 n do IA -3
ldy
lwk
I
I
30 yr Low Dose Rate
0.8
12 s -c
I
@i!isii
CO-60
+ Ill
Anneal
-0.2
-6
-0.4
.Q. t
.n -“.
”
E
102
103
10’
,05
,06
,07
,00
,09
,~lo
TIME (Seconds) 27: Projected values of nMOS gate-oxide or pamitic field oxide threshold voltage for nonradiation-hardened MOS transistors. Data points are derived from linear response analysis predictions, which are variations on a set of experimental annealing dat~ as described in Ref. [104]. The starting value of the threshold voltage is taken to be 1 V for the gate oxide and 15 V for the field oxide. No significant changes occur for times less than 107s for the low-rate response curves. Figure
As a convenient criterion for the discussion of Fig. 27, we can define failure to be the point at which the nMOS gate- or field-oxide threshold voltage becomes less than O V; that is, the point at which the gate or parasitic field oxide transistor goes into depletion mode [86]. At or near this point, increased leakage in the device can lead directly to circuit fi.mctional failure, or to system
III-32
failure because of excessive power dissipation [86,89]. Figure 27 shows that devices with gate or field oxides that trap large amounts of oxide charge and anneal very slowly (Curve A) fail after CO-60 irradiation (Vti <0 V), and also fail in space for the same reason. Faster annealing devices (Curves B and C) also fail after CO-60 irradiation (Vti <0 V), but function acceptably at low dose rates (Vti >0 V; solid symbols, low-rate curves). In Fig. 27, the devices of Curve C recover (Vti >0 V) approximately one day after higherrate irradiation, and the devices of Curve B recover after about 11 days (- 10s s). However, for any reasonable annealing time, even up to 1 year (- 3 x 107 s), the threshold voltage is more negative following CO-60 irradiation and room-temperature annealing than at the end of the lowdose-rate exposure for Curve A. Thus, Fig. 27 confh-ms that CO-60 irradiation and roomtemperature annealing can provide a conservative response of oxide-charge related failure in space, but the estimate is less conservative than that provided by TM 1019.4 [93,104,116]. Continuing with our analysis of the model results of Fig. 27, in Fig. 28 we compare the response at four points along the annealing curves of Fig. 27 to the responses projected at the end of the low-dose-rate irradiation, again as a fimction of the trapped-hole annealing rate. As expected iiom the discussions above, the amount of net positive oxide-trap charge remaining after CO-60 irradiation followed by short annealing periods at room temperature is greater than that present during low-dose-rate exposure, for all cases except (obviously) for zero annealing rate, where the quantities are equal. For an annealing rate of 10°/0per decade in Fig. 28, for example, CO-60 irradiation plus 1-rninuie anneal overpredicts the net oxide-trap charge in space by 129’Yo, while CO-60 irradiation plus 1-week anneal overpredicts the oxide-trap charge in space by only 52’Yo. In fact, increasing the anneal time from - 1 minute to - 1 week reduces the amount by which oxide-trap charge effects are overpredicted in space by about 2.5-times at all annealing rates. Because leakage currents (especially near the point at which devices go into depletion mode) can scale exponentially with gate- or field-oxide trap charge density [61,146], such a reduction in oxide-trap charge can lead to huge changes in measured leakage currents.
50%
“
o%
(i%
2%
4% Anneallng
6% Rate
8% (per
10% decade
1%6
14%
16%
of time)
28: Ratio of net oxide-trap charge following CO-60 exposure plus varying 25°C anneal times to that at the end of a 30-year low-dose-rate exposure, as a fimction of trapped-hole annealing rate, for the data of Fig. 27. Linear response analysis was used to simulate these results. (After Ref. [104],)
Figure
III-33
Onthebasis of theresults of Figs. 27and28, Oneconceivably could ex-tendtheaedtig period as long as patience and practicality allows, to obtain progressively more realistic estimates of oxide-trap charge effects in space. However, one must ensure that the total annealing time at room temperature, t*, does not exceed the following limit, tA,~w, where (2)
Here D~ is the system total-dose specification and R~ is the maximum dose rate at which any significant dose is deposited [104]. The limitation on tA is necessary for systems in which a significant fi-action of the dose can be deposited during a relatively short portion of the mission, for example, during a solar flare or an excursion into the radiation belts [45-51]. Equation (2) is also potentially an important constraint to military space systems, where a satellite must” not only survive the natural radiation encountered in space, but must also survive higher-rate weaponrelated radiation environments. Keeping tA < tA,~ti prevents devices that could fail during the brief period of exposure at higher dose rates from being accepted on the basis of their longertirne recove~. Obviously, for systems in which nearly all of the total dose is deposited at approximately the same rate, Eq. (2) provides no practical limitation on the allowed annealing times. And, for mixed-rate systems, as long as the above limit on anneal time is observed, CO-60 irradiation plus room-temperature annealing can provide an estimate of the effects of oxide-trap charge on MOS response in space that is less conservative than TM 10 19.4’s main test sequence (Fig. 18.) [104]. Thus, especially for commercial technologies, annealing rate is ojen a crucial parameter to monitor during technolo~ characterization and hardness assurance testing for low-dose-rate applications. Dose >5 krad ●~r* Gate Ox > 100 nm
CO-60 50-300
PASS
Rad 6 Test
FAIL
rad(Sl)/s
OPTION TO
Rebound Test =-
per 1019.4
CONTINUE -
“s
Duration < (Spec Dose)/Max System Rate ~
I
Room-Temperature Anneal & Teat
PA-SS ~,
I
FAIL *,
Figure 29: Example of a less consemative test for oxide-charge effects in space based on TM 1019.4.
This test flow is not part of TM 1019.4, though testing at reduced rates is allowed by TM 1019.4 for space park, (After Refs. [93, 104].) One possible way to incorporate a room-temperature anneal into a hardness assurance test plan based on TM 1019.4 is illustrated in Fig. 29. The dose and oxide thickness conditions at the
III-34
outset of the test refer to the need to perform rebound testing [113], as discussed in the previous section, and do not apply to the oxide-trap charge related portion of the test (the initial CO-60 irradiation). The oxide-trap portion of the test (i. e., irradiation to the specified dose) must, of course, always be done (though not necessarily at the dose rate specified in Fig. 29, for low-doserate applications). If devices pass the initial CO-60 test, one then can proceed directly to the rebound test in TM 1019,4. If one fails the CO-60 test, the text flow in Fig. 29 allows one to repeat the test after room-temperature annealing, subject to the time constraint of Eq. (2). If the devices pass after the room-temperature annealing, rebound testing must still be done to check for irzterface-trap related effects [104, 113]. A test sequence like this can be used during the characterization phase of a hardness assurance program as well as during lot acceptance [93]. A complicating factor in applying the test method of Fig. 29 to IC’S, or similar test flows discussed recently in the literature [93,104,116], has been pointed out by Sexton et al. [93]. That is, if the leakage current induced by the initial radiation exposure becomes so large that it heats the devices significantly, the test can become non-conservative due to thermally-assisted “overannealing” of the oxide-trap charge. Hence, it is important that the IC remains truly at room temperature during the annealing portion of the test, and does not self-heat [93]. This is an issue for both TM 1019.4 and BS 22900. Of course, each method also specifies control of the device temperature during irradiation for the same reason [68, 127], so such parts that have this problem ideally should be identified at the irradiation-testing phase.
5.9 Weapon Applications 5.9,1. Issues. The above discussions of TM 1019.4 have centered on adapting CO-60 irradiations and elevated temperature anneals to provide conservative estimates of MOS response in space, or for a similar low-dose-rate application. As discussed above, the initial CO-60 irradiation at a dose rate of 50-300 rad(SiOz)/s in TM 1019.4 (but not the lower-rate irradiations in BS 22900) can also provide a reasonable simulation of many types of “tactical” weapon applications [86]. For tactical and high-dose-rate weapon applications in which the dose rate of exposure greatly exceeds 300 rad(Si02)/s, though, the main test flow of TM 1019.4 often does not provide a conservative estimate of MOS response [58,59]. One example of this is shown in Fig. 30. Here the quiescent leakage current, 1~~, is plotted as a function of dose for three different dose rates: 106, 1833, and 100 rad(Si02)/s. At the higher rates, there is a large increase in leakage current at 100200 krad(SiOz) due to the turn-on of a parasitic edge transistor associated with the field oxide in these devices [58, 140]. At the lowest rate, no such increase is observed. These differences in response are due to the decrease in oxide-trap charge and increase in interface-trap charge in the edge region with decreasing dose rate (and/or increasing anneal time) that prevents the parasitic device from turning on and increasing 1~~ at the lowest rate. Thus, oxide-charge related failures in high-dose-rate radiation environments are not always identl~ed in testing via TM 1019,4. For these environments, one must either test under conditions that simulate the environment of interest, e. g., by exposing the devices at a LINAC or flash x-ray source [58], or an equivalent derivative test method must be employed.
III-35
,~-1
,~-2 106radls ,~-3 e & o
10”4 ~
,~-s
10-8 PRE
))
1
0.1 Dose,
10
Mrad(Si02)
Figure 30: Quiescent leakage current versus dose for IC’S fabricated in Sandia’s CMOS 111Aprocess irradiated at rates of 100, 1833, and 106 rad(Si02)/s. The 100 racVsexposures were in a CO-60 source, the 1833 racVsexposures were with 10-keV x rays, and the 10brad/s tests were with 230-MeV protons at the TRIUMF cyclotron at the University of British Columbia in Vancouver, Canada. (After Ref. [58].) 10-keV x-ray tests are often performed to (1) characterize the 5,9.2. 10-keV X-ray Irradiati. basic radiation response of MOS structures, (2) track the hardness of a given technology via test structure irradiations, and (3) provide quick feedback about the hardness of a lot before submitting it to the further expense of packaging the devices and performing Co-60-based lot acceptance testing [60,6 1,67, 146]. The data of Fig. 30 suggest that, because of the higher dose rates associated with typical 10-keV x-ray exposures [146], such irradiations might also be useful in a hardness assurance test plan for MOS electronics intended for use in some types of weapon applications. And this is true. However, a few issues must be addressed before one can use 10-keV x-ray irradiation to quali~ parts for high-rate radiation environments. The first issue is that of the x-ray penetration depth. 10-keV x rays do not have enough energy to penetrate IC packaging material, so testing must either be performed at the wafer level or on unlidded parts [60,67,1 47]. On the other hand, 10-keV x rays penetrate nearly unattenuated the first 2 pm of common semiconductor materials [147], so one need not worry about attenuation effects (even for the thickest SOI materials) in chip-level x-ray exposures. Two issues that have received a lot of attention in comparisons of 10-keV x-ray and CO-60 response are charge yield and dose enhancement [57,67]. Charge yield refers to the number of electron-hole pairs that escape initial recombination processes, and is very sensitive to electric field and ionizing radiation energy. At a given electric field, 1-MeV CO-60 gamma rays will have higher charge yield than lower-energy x rays. Differences ae most pronounced at low electric fields. Dose enhancement occurs when low-energy x rays pass through an interface of materials with significantly different atomic numbers [57,67]. Because of the strong dependence
III-36
of x-ray interaction (typically via the photoelectric effect) on atomic number, Z, “extra” dose is initially deposited in higher-Z material than the lower-Z material. Some of the secondary electrons generated by the x rays leave the higher-Z material and increase the dose in the lower-Z material above the equilibrium level that would have been deposited in absence of the nearby high-Z material [57,67]. Dose enhancement can also be observed during CO-60 irradiations if very-high-Z materials (e. g., Au or ~ are nearby [63,64]. However, as long as Pb/Al filter boxes are employed during CO-60 exposures [64,68], dose enhancement is not usually an issue in hardness assurance testing of typical semiconductor devices because the primary interaction of CO-60 gamma rays with Si and other low-Z materials is via the Compton effect, which has a much weaker Z-dependence [45,57,67]. Dose enhancement effects have been discussed in detail previously, and (despite some initial controversy) are generally well understood for x-ray irradiations [67, 143,144,147- 152]. Nevertheless, one must take into account differences in amounts of dose enhancement in use and test environments when attempting to use low-energy x-ray sources for high-dose-rate hardness assurance. Monte Carlo and discrete ordinates codes have been developed to do this [148,153155], though results can depend strongly on the precise system environment and device geometry. Consequently, a standard treatment of dose enhancement effects is difficult to offer, though the problem is quite treatable on a system-by-system basis. This is an important issue to consider when establishing radiation and test requirements for systems in which MOS electronics may be exposed to high-dose-rate x-ray environments, especially if the devices or their immediate surroundings contain high-Z metallization layers [65,153-156], but is beyond the scope of the present discussion. Charge yield (except perhaps for low-temperature applications with large dose enhancement [156]) can be addressed in a more general manner. A breakthrough in the understanding of x-ray charge yield was the ionization current measurements of Benedetto and Boesch [143], which showed that x-ray charge yield was much lower than earlier studies [147, 157- 159] had suggested. Their measurements are compared to others in the literature [143,144,149,158,160,161] in Fig. 31. Charge yield for CO-60 irradiations as estimated by Srour and Chiu [162], and later independently confirmed and extended by Shaneyfelt et al. using an entirely different method [144], are shown in Fig. 32. A comparison
of these data illustrates some of the issues involved in using low-energy x-ray sources. For gate oxides, the electric field under worst-case bias is usually 0.5 -2.0 MV/cm (though fields are increasing in modem devices with thin oxides). At -1 MV/cm, Fig.31 shows that the charge yield for x-ray irradiation is -0.5. Figure 32 shows that the charge yield for Co60 imdiation is -0.7, which is -40 VOhigher. However, the presence of dose enhancement in the x-ray test almost perfectly counter-balances charge yield differences for MOS gate oxides. In Fig. 33, the relative amount of net positive oxide-trap charge for x-ray and CO-60 irradiations is plotted as a function of oxide electric field for Si-gate devices with 105-nm and 350-nm oxides [144]. A dose enhancement factor (DEF) of - 1.4 is assumed for the 105-nm oxide, and of 1.0 for the 350-nm oxide [144]. To within - 20%, these values agree with model predictions of dose enhancement in these devices [148]. Charge yields are estimated from Figs. 31 and 32 to arrive at the predicted response (solid lines), which is in excellent agreement with the experimental data III-37
1.0 0 Benedetto and Boesch (1986)” c Dozier and Brown (1980)’ m 47.5 nm oxide a 60 nm oxide ■ 105 nm oxide ■ 35o nm oxide
0.8 0.6 0.4 0.2 0.0
I
I
I
1
11111
I
0.001
I
I
I
1 1
0.01
1111
I
I
I
I [1111
0.1
I
I
I 1 I II
10
1
Eox (MV/CM)
Figure 31: Charge yield as a function of oxide eleclric field for 10-keV x-ray irradiations of Si-gate MOS devices. The Benedetto and Boesch data are from Ref. [143]; the Dozier and Brown data are from Ref. [160]; the 47,5 and 60 nm oxide data are from Ref. [158]; the 350 nm oxide data are from Ref. [161]; and the 105 nm oxide data are from Ref. [144], (A!ler Refs. [143,144,149],) 1.2 Srour and Chlu (1977) ■ 91 nm oxide
1.0
o . O ●
0.8 0.6
47.5 nm oxide 60 nm oxide 105 nm oxide 350 nm oxide
0.4
8
0.2
0.0
1
1-
0.001
1
1
1
1
1
1
111
0.01
1
1
1
1
1 1
Ill
1
0.1 Eox (MV/cm)
1
I
1
I
1
Ill
1
1
1
1
1
11
1
10
Figure 32: Charge yield as a function of oxide electric field for CO-60 irradiations of MOS devices. The Srour and Chiu data are from Ref. [162]; the rest of the data are from Ref. [144]. (After Ref. [144].) (open and solid circles), suggesting that the dose enhancement and relative charge yield factors have been accounted for accurately in these x-ray and CO-60 irradiations. Thinner oxides show response similar to the 105-run oxide in Fig. 33, though the dose enhancement factor is slightly higher [144, 148]. For the 105-nrn oxides, the device response is similar for x-ray and CO-60 irradiations at - 1 MV/cm due to the aforementioned near-cancellation between charge yield and dose enhancement effects [143, 144, 148]. At higher fields, the x-ray response is enhanced; at lower fields, the CO-60 response is enhanced, in agreement with the general rule that charge yield issues in 10-kc V x-ray irradiations are more signljicant at 10w electric jiela% than at high j?elak.
III-38
For the thicker oxide, the x-ray irradiation shows an under-response for all field conditions. At 0.1 &fV/cm, typical of the electic field across a MOS parasitic field oxide, the amount of underresponse is nearly a factor of 2 [143, 146,161].
TO
t
o 1.2 to & 2 1,0
DEF = 1.4
J ? 0.8 ?2 m L & 0.6
1 ~’
5 > Q 0.4 -
0.2
Otox = 105 nm Poly Gate
/
●tox
DEF = 1.0
= 350 nm Metal
Gate
,
0.01
0.03
0.1
0.3
1
3
10
Eox (MV/cm)
Figure 33: Ratio of x-ray to CO-60 radiation-induced AVOIas a fimction of oxide thickness and electric field during irradiation, The curves are predicted responses using the charge yield data of Figs. 31 and 32 and dose enhancement factors of 1.4 and 1.0. (After Ref. [144].) X-ray charge yield can be an especially important concern for SOI devices. A cross-section of a mesa-isolated SOI device is shown in Fig. 34 [102,163]. For this type of device, the gate oxide, sidewall passivation, and buried oxide each typically have different thicknesses. The buried oxide frequently has no applied back-gate bias (a negative back-gate bias can mitigate total dose problems with the buried oxide [102, 163, 164]) to sirnplifi system and circuit power supply issues [165- 168]. Thus, fringing fields from the drain and the built-in work fimction potentials are often the dominant sources of the electric field across the buried oxide, which can be very low [102].
v~ 9
, Gate Oxide
Sidewall Passlvation Burled
Oxide
Figure 34: Cross-section of a mesa-isolated SOI transistor, highlighting different insulating layers. (After Refs. [102,163 ].)
III-39
The effects of the low fields across the buried oxides for comparisons of x-ray and CO-60 response are shown in Figs. 35 and 36 for SIMOX (Separation by Implanted Oxygen) and ZMR (Zone Melting and Recrystallization) materials, respectively. The SIMOX buried oxide is -400 run thick, and the ZMR buried oxide is - 2 pm thick [102,163]. All irradiations were performed with O V back gate bias at an equilibrium dose rate of- 278 rad(SiOz)/s. For the SIMOX oxide in Fig. 35, the dose at which the back-gate threshold voltage crosses zero (and the parasitic backgate transistor goes into depletion mode) is -60 % higher for the x-ray exposure than for the Co60 irradiation. The amount by which the CO-60 response exceeds the x-ray response is even larger (nearly a factor of 3) for the thicker ZMR buried oxide in Fig. 36. For other SOI (and SOS) technologies, these factors can vary with buried oxide thickness--as well as back-gate, topgate, source, drain, and body bias [102, 165- 168]--s0 this is an important parameter to quantifi during characterization testing.
-4
Pre
‘-
1.0
100
3.0 DOSE
[kr~d
300
(Si02;;
Figure 35: Back-gate threshold-voltage shifts (in V) as a function of equilibrium x-ray and CO-60 dose for SIMOX devices with 0.4pm buried oxides. (After Ref. [102].) Based on the above discussions, similar differences in charge yield for x-ray and CO-60 irradiations are to be expected for any type of electronics technology in which low electric fields are experienced in thick insulating layers under operating conditions critical to device response, So, for example, large differences in charge yield are expected for some types of bipolar devices with thick isolation oxides [62, 169-171 ]. Whether the lower x-ray or higher CO-60 charge yield factors are more appropriate for an environment of interest will of course depend on the dominant type of radiation anticipated under device use conditions. For example, soft x rays will have a charge yield comparable to a 10-keV x-ray source, and high-energy electrons will have a charge yield comparable to, or greater than, the CO-60 gamma rays [141]. Protons show an especially wide variation of charge yield with energy due to their greater mass [66]. Because of the uncertainties inherent in anticipating radiation types and energies for most systems, allowing some
111-40
margin in x-ray testing for reduced charge yield Seems appropriate, if x-ray tests are to be used for part qualification for high-dose-rate weapon applications. For further discussions of technical issues associated with the use of a 10-keV x-ray source, please see Ref. [67]. Pro
.-
60 .
40
.
Co-60~
20
-0 > VBQ =Ov
-20 -
?? 1./
-40 Pre
‘-
I
I
I 10
1.0
D30\E
[krad
1
I
30
100
300
(Si02)]
Figure 36: Back-gate threshold voltage shifts (in V) as a function of equilibrium x-ray and CO-60 dose for ZMR devices with 2.0pm buried oxides. (After Ref. [102].) 5.9.3. possible Test Methods. Figure 30 above illustrates the point that any testing based on Co60 or 10-keV x-ray exposures will be fundamentally non-consewative for high-rate response due to oxide-trap charge neutralization effects. That is, a significant fraction of the positive oxidetrap charge that can significantly affect MOS device response at very short times (for example, on the ~s - ms time scales associated with some high-dose-rate weapon applications) can (1) anneal out, (2) be compensated via electron capture in border traps associated with the trapped positive charge [83, 108, 109], or (3) be offset by the time-dependent growth of interface-trap charge on the time scales of lower-dose-rate irradiations [86-89]. Short of using high-rate sources for lot acceptance testing, which is often expensive and impractical, one can only circumvent this problem via characterization testing and the use of margin and safety factors in hardness assurance testing [58,59]. These safety factors are above and beyond those employed as part of the system design phase (e.g., Section 2 above). An example is shown in Fig. 37, where the threshold voltage of an MOS transistor exposed to 50 krad(SiOz) at a LINAC at a dose rate of 6 x 109 rad(SiOz)/s is compared to a 10-keV x-ray exposure at 5550 rad(Si02)/s to 100 krad(Si02) [59]. A negative shift at 10 s following the x-ray exposure that is equal to the shift at - 10 ms following the LINAC exposure is obsemed, thus illustrating that additional dose in a laboratory test can sometimes (but not always) make-up for the increased
III-4 1
annealing time. However, the dose rate still must be kept as high as possible in the laboratory exposure for devices which tend to have large interface-trap densities in gate gr field oxid e regions, as otherwise the positive shifts due to interface traps can prevent one from reaching the negative threshold voltage levels one can see at very short times following high-rate exposure [58,59]. Still, Fig. 37 highlights that, with characterization testing, one can often define practical 10-keV x-ray tests based on overtesting and margin that can be useful for hardness assurance testing for high-dose-rate weapon environments [58,59]. The amount of margin required will depend on the neutralization rate of the oxide trap charge in the gate and field oxides, the relative of amount of interface traps in these two regions and their buildup rates, and the system performance requirements (that is, the amount of leakage current associated with negative threshold voltage shifts that can be tolerated at short times). 0.8
T
0.4 LINAC, 1 Pulse, 6X109 rad/s
A Vth (v)
0
50 krad I
-0.4 -4-0.8
.-
~
-“H
9-99
99
X-ray, 5550 rad (S102)/s
Equal AVth
100 krad
-1.2 -1.6
‘
10-4
I
10-3
I
10-2
I
10-’
I
I
100 TIME
101
I
102
I
103
I
lfJ4 10
(see)
Figure 37: Comparison of high-dose-rate LINAC and intermediate-rate 10-keV x-ray exposures of MOS transistors with 45-rim oxides from Sandia’s old baseline technology. (Atler Ref. [59].) 5.10 Synopsis of MOS Test Methods
Defining optimized tests for high-dose-rate environments requires an understanding of system requirements and device time-dependent response that probably never can be captured in a simple test standard the way TM 1019.4 and BS 22900 allow low-rate response to be estimated. Still, we can offer the following test matrix for epiibulk and S01/S0S technologies as a starting point for characterization testing for high- and low-dose-rate radiation environments. The split between these two groups is necessary because of the dramatic impact charge yield in the buried insulator can have on SOI/SOS device response. The matrix also presumes it is not already known from characterization testing that a particular failure mode can be neglected for a given technology. For example, SOI devices with intrinsically hardened buried oxides at high dose rates could be qualified the same as epfiulk devices, as the charge yield issues in the buried oxide would not be significant if the buried oxide is not impacting device response. We emphasize, however, that the absence of one failure mechanism (especially field or buried oxide Ieahge) in laboratoW testing does m ensure its absence in a high-rate environment. Look at Fig. 30 carefully again! For radiation environments in which a significant portion of the total dose is depos-
111-42
ited at rates above the maximum rate achievable in laboratory sources (- 1000-3000 rad(SiOz)/s in an ARACOR Model 4100 X-ray Irradiator), characterization testing at a Ll_NAC or equivalent high-rate source is necessary to avoid risk from possible non-conservatism of the test with respect to oxide-trap charge. The matrix presented in Table 2 should therefore only be used as a general guideline, and should not be presumed to be a serious attempt at a rigorous standard. Table 2: Matrix of possible sources/tests useful for characterization testing and for developing hardness
assurance plans for MOS devices used in weapon or space environments. For purposes of illustration, the breakpoint between high and low doses in this table is -5 krad(Si02), unless modified by arguments on maximum interface-trap buildup such as those in Section 5.7 above.
Epi/Bulk MOS
Environment Low Dose Space
I
Either x-ray or CO-60 testing.
SOI/SOS MOS I
CO-60 preferred.
CO-60exposure per 1019.4 or BS 22900, plus rebound testing.
CO-60 exposure per 1019.4 or BS 22900, plus rebound testing.
CO-60per TM 1019.4 preferred, or x-ray with 2x margin.
CO-60 per TM 1019.4.
High Dose Weapon (Strategic)
X-ray preferred, with 2-3x margin.
Both x-ray testing and CO-60 testing per TM 1019.4 with 2-3x margin.
Military Space
Both x-ray testing with 2-3x margin, and CO-60 plus rebound testing required.
Both x-ray testing with 2-3x margin, and CO-60 plus rebound testing required.
High Dose Space Low Dose Weapon (Tactical)
Several points must be noted about Table 2. For all applications involving possible highdose-rate exposure, the tests should be supplemented with high-rate characterization testing (for example, with a LINAC). The break-point between a high- and low-dose environment is - 5 krad(SiOl) here, though this is for purposes of illustration only, and should not be taken as absolute guidance. Analysis like that in Section 5.7 above is required to modifi this boundary, which is set by the requirement to check for significant interface-trap effects at low dose rates. Rebound testing is only required in Table 2 when stated explicitly. For example, in the “low-dose” space environment, rebound testing is not required (unless gate oxides are thicker than -100 nm or devices or ICS are exceptionally vulnerable to small interface-trap densities [104]). If one cannot eliminate the need for rebound testing by means of characterization testing or analysis along the lines of Section 5.7 above, the “high dose” conditions apply. The “military space environment” is a combination of “high-dose-space” and “high-dose-weapon” environments. X-ray testing presumes using a 10-keV x-ray irradiator at a rate of> 1000 rad(Si02)/s, and that tests are performed immediately after the end of the exposure. When both x-ray and CO-60 testing are suggested, of course separate lot samples are used for each type of exposure. For example, x-ray testing could be performed at the wafer level, subject to the constraints of Sections 5.9 above and 5.11 below, and CO-60 testing (and rebound tests, if required) would be performed on a separate
III-43
I
I
group of packaged parts. So, Table 2 is a useful starting point in hardness assurance test definition for MOS devices in weapon, space, or mixed environments. 5.11 E#ects of Burn-in A complication in the traditional MOS lot acceptance flow is recent work showing that reliability screens normally given devices before product is shipped can sometimes significantly affect their radiation response [169], Because burn-in is performed at a much lower temperature than the device has already experienced during processing, it had previously been presumed that the radiation response of burned-in and non-burned-in devices would be similar, so lot samples for radiation testing could (to save time and expense) be pulled without receiving a burn-in, Figure 38 illustrates the danger of testing devices without burn-in. These commercial octal buffer/line drivers have a problem with excess leakage current in a radiation environment. In Fig. 38, devices which received a burn-in show much higher leakage currents after CO-60 irradiation to 150 krad(SiOz) than do parts which did not receive a burn-in. Distressingly, the nonburned-in parts easily pass the parametric test limits for these devices, while burned-in parts (more representative of shipped-product response) fail the test. At higher dose rates typical of some weapon environments, these parts could cause system failure due to their high leakage currents. Failures could even occur in space systems in oxide-trap charge annealing rates are not high enough for the devices to recover before the leakage current becomes great enough to cause circuit or system failure [104,169]. 1
()-1 .
10-2
.
■
150°C
●
pJo
Burn-in
Burn-In
10-3 -“.------”--”----”Failure Level 10-4 110-5 10-6 10-7
1 o-e 1 ()-9
fl---
8= Lr. Pre
104
103
105
Dose [rad(Si02)] Figure 38: Static power supply leakage current as a fimction of dose for commercial octal buffer/line
drivers with or without a pre-irradiation 150”C bum-in, irradiated with CO-60 gamma rays at 90 rad(Si02)/s. The dashed line represents a parametric failure level of 1 mA. (After Ref. [169].) Enhanced leakage currents associated with burn-in have also been observed in the hardened SRAMS of Fig. 30 [169]. An initial characterization study of gate and field oxide transistors suggests that burn-in may alter some interface-trap precursors in these technologies, perhaps due
III-44
to hydrogen motion [169]. Without compensating interfhce traps, gate-, field-, or edge-transistor leakage can be unacceptably high in high- or low-dose-rate applications [86,89, 140]. If devices are to be burned-in before being used in such systems, the results of Ref. [169] show clearly that one must perform radiation testing on burned-in parts (unless the devices have been shown not to exhibit changes in radiation response due to burn-in, or unless the response of burned-in devices can be correlated accurately to that of non-burned-in devices). This effect must also be considered in interpreting the results of wafer level irradiations on non-burned-in devices for technologies that show this effect [169]. Finally, we should mention that the sensitivity of device radiation response to burn-in is most likely not unique to MOS technologies, as bipolar and BiCMOS devices which are prone to show parasitic leakage in recessed or trench field oxides (discussed below) may also be susceptible to these burn-in effects. 5.12 ~. The final topic to be covered in this section is what to do if parts fail a radiation test like TM 1019.4 or BS 22900, during the hardness assurance phase of a project. The glib (and sometimes only comet) answer is to throw away the bad parts and buy or build better ones! However, there are some steps to go through before making this decision. First, one should check to see that the parts were biased and tested correctly. Doing something as simple as putting a part into a socket the wrong way or applying bias incorrectly can damage a part quite independently of its radiation response (see Figs. 1 and 2, for example). Second, one should review the cause of the failure. Does it make sense with what is known about the part? For example, if failure analysis shows a blown input protection device, that’s probably not a radiation-induced ftilure. On the other hand, if it’s a commercial MOS IC that fhils functionally or shows high leakage at a few hid, you may be stuck, because that’s fairly normal behavior for commercial, off-the-shelf devices! About the only options for dealing with real radiation-induced IC failures are (1) for oxide charge related failures, to use the less conservative tests in Section 5.8 above, if the application is a low-rate environment, and if permitted to do so by the contracting authority, (2) for interfacetrap charge related ftilures, to consider a detailed characteri=tion of the part over a wide range of dose rates and/or annealing times to try to accurately extrapolate device response in space, as was done for oxide charge in Fig. 27 (this can be a very difficult task, and is not recommended for the non-expert), (3) to re-evaluate the radiation requirements for the system to see if the requirements on the part of interest can be relaxed without jeopardizing the system (and/or consider spot shielding the device), (4) try to get a more radiation-tolerant part (or a harder version of the present part), or (5) fly the bad part anyway, and accept the risk of reduced system lifetime. It is presumed that option (5) would not be chosen lightly. 6. Testing Issues for Bipolar Devices Bipolar devices can fail in radiation environments due to parasitic leakage effects similar to those in MOS IC’S [170-172], or due to gain degradation, where the device physics can be entirely different from that of MOS devices [173-176]. Figure 39 illustrates a typical parasitic leakage path for a bipolar IC [172]. As in a MOS parasitic field oxide, trapped positive charge in the oxide overlying the p-region between the two buried layers can cause the surface to invert, III-45
forming a parasitic leakage path. For this or other types of parasitic leakage-related failure modes associated with trapped-positive-charge buildup in insulators, either in weapon or space environments, test methods for bipolar devices are similar to those for MOS devices [1 14]. Moreover, for gain degradation in high-dose-rate (e. g., strategic weapon) environments, similar tests can also be employed to those discussed for MOS devices above, though more attention must be paid to displacement effects associated with high-energy electrons and protons for bipolar devices (sensitive to minority carrier lifetime) than to MOS devices (sensitive to majority carrier lifetime). Where testing issues become more difficult for bipolar devices than for MOS devices is for IC’S in which gain degradation is the primary failure mode, for space or other lowdose-rate applications. We now discuss why this is the case, and provide some preliminary testing recommendations. INCREASED SIDEWALL 3
2
CURRENTS
Y
P
COLLECTOR TO EMITTER CHANNELING ON WALLED EMITTERS
7
BASE
RECESSED FIELD
OXIDE N EPITAXIAL
7 L
,.-
..:,;.. ,,
+ N+ BURIEDLAYER
N+ BURIEDLAYER P SUBSTRATE I
T
o 1
BURIED LAYER TO BURIED LAYER CHANNELING
Figure 39: Cross-section of parasitic MOSFET that can invert during ionizing radiation exposure, causing buried-layer to buried-layer leakage in some bipolar technologies. (After Refs. [67, 172].) A cross-section of a modern bipolar junction transistor (BJT) similar to those used in Analog Devices Inc.’s (ADI’s) XFCB complementary bipolar process is shown in Fig. 40 [177], The screen oxide that overlies the emitter-base junction is the primary problem in a radiation environment for many types of modern bipolar/B iCMOS technologies [1 12,173,174, 178], The buildup of positive oxide-trap charge in the screen oxide can greatly enhance the surface recombination rate in the p- base region of NPN transistors. (Analogous effects also apparently can occur in p-emitter regions of lateral or substrate PNP transistors with similar screen oxides [179181].) The excess base current responsible for the gain degradation in these devices scales as exp (NOX2),where N OXis the net positive trapped charge density in the screen oxide. Thus, the devices are extremely sensitive to the oxide charge [173,174]. Moreover, the oxide electric field in the screen oxide ordinarily is small, and due primarily to base-emitter fringing fields (in the absence of accidental overlapping metallization). Finally, the screen oxides are typically of much poorer quality than MOS gate oxides, due to processing constraints associated with the need for a high base surface doping density and the high-temperature emitter drive-in anneal [1 12], The combination of poor oxide, low electric fields, and extreme sensitivity of the excess
III-46
base CUITent can lead to dramatically different radiation response with respect to dose- rate and annealin [g effects for some bipolar devices than for the MOS devices considere( iin Slectifm 5 above, Base
❑
Eti~r
■
Oxide
Chllector
Base
❑
Metal
Polysilicon
Figure 40: Cross-section of bipolar devices built in ADI’s XFCB complementary bipolar process. The
oxide above the emitter-base junction is - 545 nm thick for this process. (After Ref. [177].)
——— —— ——— —— —— .— —— ——— ——— ——— F ——— ——— — — —— —— ——— —— ———— 1 F- ———
1
I
Range
of 1.1 rad/s
,
1
I
I
Data
1
~o-2 .
m:
300 rad(Si02)/s ■
., 5 0 -2 0
100° 200 krad I @
,
1 104
Time
,
, ,
I ~05
, 106
(see)
Figure 41: Comparison of low-dose-rate and high-rate plus high-temperature annealing data for a de-
velopment version of ADI’s RBCMOS process. Devices were irradiated to 200 krad(Si02) at 1.1 or 300 rad(Si02)/s. High-rate irradiations were followed by 100”C anneals. The band of low-rate response after irradiation to the same total dose is indicated by the region between the dashed lines. (After Ref. [182].) Two examples of these differences in response are shown in Figs. 41 and 42 [182,183]. These are representative of much recent data in the literature that show similar effects [181-188], Figure 41 is the data of Enlow et al. in which the differences in bipolar and MOS post-irradiation response were first noticed [182]. For these devices, irradiation at a rate of 1.1 rad(Si02)/s
III-47
caused much worse gain degradation than does irradiation at 300 rad(Si02)/s andor performing a subsequent high-temperature anneal. Before this report, it had been considered likely that both MOS and bipolar devices would show gain degradation in space that were dominated by interface-trap effects [175, 176], and that rebound tests might be an effective way to simulate bipolar gain degradation in space [1 14], Figure 41 showed this was simply not the case. Figure 42 is a follow-on study by Nowlin et al. which reinforces the inability of room-temperature or elevated temperature anneals to increase the amount of gain degradation to levels observed at low dose rates [183]. More recent IC data have shown this type of response is also seen in other technologies [181,1 85,186]. AIB/l Bo 12 ‘
Room Temperature
Annealinf I
10 ‘0 co Data
a -
Standard
Emitter
2 V Reverse Bias 1.5 w x 1.5 I.IM Emitter
6 -
4 -
2Isochronal Annealing hit
poatrad
1 A
1 B Meaaurament
1 c
1 D
)
E
Figure 42: Room-temperature and isochronal annealing data for ADI XFCB transistors. All measurements were taken after the devices were irradiated to 500 krad(Si02) with CO-60 gamma rays at a rate of -240 rad(SiOz)/s, Annealing points during the isochronal anneal correspond to 30 minutes of annealing at (A) 60°C, (B) 100”C, (C) 150”C, (D) 200”C, and (E) 250”C. The room temperature parts were characterized at the same times as the isochronally annealed parts. (After Ref, [183],) Recent capacitance-voltage (C-V) and thermally stimulated current (TSC) tests on MOS capacitors processed similarly to bipolar screen oxides have strongly suggested that differences in the amount and distribution of oxide-trap charge following high- and low-rate irradiation maybe responsible for the enhanced gain degradation of bipolar devices at low dose rates [112]. In particular, for O-V irradiation of capacitors simulating bipolar screen oxides at - 25°C, the net trapped-positive charge density (NO,) inferred from midgap C-V shifts is -25-40 ‘A greater for low-dose-rate (< 10 rad(Si02)/s) than for high-dose-rate (> 100 rad(Si02)/s) exposure [1 12]. Device modeling shows that such a difference in screen-oxide NO. is enough to account for the enhanced low-rate gain degradation often obsemed in bipolar devices, due to the - exp(NOX2)dependence of the excess base current [174,178]. At the higher rates, TSC measurements revealed
III-48
a -10 VOdecrease in trapped-hole density over low rates. Also, at high rates, up to - 2.5-times as many trapped holes are compensated by electrons in border traps than at low rates for ADI devices under the irradiation conditions of Ref. [112]. Both the reduction in trapped-hole density and increased charge compensation reduce the high-rate midgap shift. A physical model has been developed which suggests that both effects are caused by timedependent space charge effects in the bulk of these soft oxides associated with slowly transporting and/or metastably trapped holes (e. g., in Ea’ centers) [112]. Figure 43 is annealing data from electron-spin-resonance experiments that supports the asertion that metastably trapped holes in E5’ centers anneal more rapidly than more deeply trapped holes in E; centers [189]. The space charge associated with these slowly transporting or metastably trapped holes was argued to both reduce the charge yield in the bulk of the screen oxides during high-rate irradiations more than during low-rate irradiations, and to force holes to be trapped somewhat nearer to the Si/SiOz interface during the high-rate irradiations than during the low-rate irradiations. Holes trapped nearer to the interface can be more easily annihilated or compensated by tunneling electrons, consistent with the TSC data. Additional details of this physical model are in Ref. [1 12].
.!! 1.0 .tn c
-0
o
0.8
m m w n
0.6
.2 0.4 a E b 0“2 z 0.0 0
50
100 Temperature
150
200
25
0
(“C)
Figure 43: Normalized densities of holes in metastable (Eb’) or deep (~)
hole traps, as measured via
electron paramagnetic resonance. (After Ref. [189].) On the basis of the model outlined in Ref. [1 12], it was predicted that bipolar transistors with enhanced gain degradation at low dose rates might show comparable behavior after higher-rate exposure, if irradiated at a temperature that was high enough to enhance the annealing of holes in metastable traps (and/or slowly transporting holes) at high dose rates, but low enough that holes in deeper traps are not significantly affected [112]. Figure 44 verifies that prediction for XFCB devices [1 12]. The triangles represent the normalized excess base current (responsible for the enhanced gain degradation) as a function of dose rate for XFCB transistors irradiated with 10keV x rays at 25”C. The squares are 60°C irradiations of the same devices. At 200 rad(SiOz)/s, the 60°C data match the low-rate 25°C data exactly. At 20 (SiOz)/s, the 60°C show even greater
III-49
degradation than at low dose rates. However, some annealing apparently occurs at 60”C at the lowest rate shown here, -1.7 rad(SiOz)/s. The results of Fig. 44 strongly reinforce the ideas behind the model of enhanced gain degradation at low dose rates outlined in Ref. [1 12], as do preliminary results on RBCMOS devices. Moreover, Johnston et al. also have irradiated LM324 operational amplifiers, with sensitive substrate PNP’s, that show similar dose rate effects [181]. Their results are shown in Fig. 45. Here the parts irradiated at elevated temperature clearly show a response that is degraded from that at 25”C, but the low-rate response is worse still. Thus, more work is required to determined whether elevated-temperature irradiations might fill the same role as do elevated-temperature anneals in rebound testing of MOS devices [112,180,181]. 6
n
A 25° C
5 4
‘-m60C
/n\
\ \
/
600C
/
.
\
/
A
\
/
3
. /
A /
●
2
250 C 1 0
1
0.1
,
m
m n . . . .
1
m
m
,,
10
n
m
m a
,
,,
,
100
,
m
an
,
1000
Dose Rate [rad(SiO 2)/s] Figure 44: Excess base current (normalized to preirradiation values) versus x-ray dose rate and irradiation temperature for ADI XFCB devices irradiated to 100 krad(Si02) at OV bias. (After Ref. [112].) Kosier et al. [184] have reported that the amount of gain degradation possible in bipolar structures like that depicted in Fig. 40 is ultimately limited by geometric factors that are independent of device bias or radiation dose rate. Thus, if a given bipolar device or circuit can still operate successfully after receiving the large amount of radiation (typically more than 1,0 h4rad(SiOz)) required to reach this level of saturation, the difficult testing issues posed above can be avoided [184], For many types of devices, however, failure occurs at lower levels, and testto-saturation is not an option. At the present, it seems that one must perform detailed characterization testing of bipolar devices and circuits that are intended for use in a low-dose-rate environment. Once the basic response is characterized, then some combination of low-rate tests (e.g., at a rate below 10 rad(Si02)/s), elevated temperature irradiation, and/or use of safety factors must be combined to provide a consemative test of bipolar/13 iCMOS devices prone to failures due to gain degradation in low-dose-rate radiation environments [1 12,179,180,187]. Clearly, defining improved standard hardness assurance tests for bipolar and BiCMOS devices is an important area for future work.
111-50
300
I
I
0.02rad(S~a
‘7’
‘
‘
30
35
0.005 md(Sl)/S
0.002
5
1
10
15
20
25
TOTAL DOSE [rad(Sl)]
Figure 45: Change in input bias current as a Ilmction of dose, dose rate, and irradiation temperature for LM324 operational amplifiers, (After Ref. [181].) 7. QML Many of the test methods described in Section 5 above, though based on a first-principles understanding of total-dose radiation effects, were designed to be applied without any special knowledge about the radiation response of the devices being tested. A clear example is TM 1019.4, in which the main test flow can be applied to consematively test MOS devices for tactical or space applications even without the requirement for characterization testing to understand the response of the particular devices being tested. While this has advantages from the standpoints of standardization and simplicity, it also may lead to increased qualification costs for some types of devices. For example, if a given technology has been processed so that an insignificant number of interface traps are created at the dose levels of interest, why go to the time and expense of performing rebound testing? This issue was explored in Section 5.7 above for devices which “happened” to have been processed acceptably to meet these conditions. Recently, there has been a lot of interest in applying some of the time and expense heretofore spent on lot acceptance testing to improve the underlying radiation response of a particular process, and then use the knowledge developed in improving the process to reduce hardness assurance costs. That is, apply resources to “build in” the quality, not try to shake it out during testing. This is the cornerstone of the Qualified Manufacturers List (QML) approach to radiation hardness assurance [15- 19]. The QML methodology will be described in more detail by Nick van Vomo in the next section of the course [52], but I will introduce the topic briefly here in the context of qualifying MOS devices for use in space applications.
III-5 1
The basic principle that underlies the QML approach to radiation hardness assurance is illustrated schematically in Fig. 46 [18]. On the y-axis are savings, represented by reduced hardness assurance costs. On the x-axis is knowledge, which is obtained from studies of the fundamental radiation response of a given process, and from implementing that knowledge via improved processes. With very little knowledge about the response of a process, one must resort to simple, conservative tests--like TM 1019.4 for space environments, or like LINAC testing for high-doserate weapon environments. If one increases his or her knowledge about a process, and finds that a few basic parameters control the radiation response (for example, nMOS transistor interfacetrap buildup or field-oxide threshold-voltage shifts), one can shift the lot acceptance problem from a circuit-assessment task to a test-structure assessment task [16-19,61]. And test structures are much easier and less expensive to test than IC’s. Finally, if one can isolate the critical areas of a process that determine the hardness of a given technology, radiation hardness assurance for that technology ultimately could be accomplished via process control verification [18]. For example, in-line statistical process control of initial threshold voltages, gate- and field-oxide thicknesses, and post-oxidation annealing temperatures may satis@ the needs of some low-dose (e. g., less than 5-10 krad(SiOz)) tactical weapon applications [16,141]. Unfortunately, Figure 46 is easier to think about schematically than to apply in a verifiable way to actual IC technologies. However, the spirit of this process can certainly be useful in minimizing testing costs, as we discussed briefly in Section 5 above, and as we further illustrate in the discussions that follow.
I
s
Test
A
v
Structure to [c
DETAILED
EXPERIMENTS ON TEST STRUCTURES
I
IN LINE SPC OF RELEVANT
I&!&k
I N G
(:: E
Use/Threat
KNOWLEDGE Figure 46: Key correlationsrequired to increase one’s knowledge about a process technology to realize
cost savings in hardness assurance testing. (After Ref. [18].) A key element of a cost-effective QML program is wafer-level irradiation of test structures using a 10-keV x-ray irradiator, or an equivalent technique (if available), to ensure that appropriate process control is maintained [16-18,61]. As one example of a historical record of such data, consider Fig. 47. This is a chart of threshold-voltage shiils due to oxide-trap charge and interface-trap charge for Sandia’s 3-pm radiation-hardened “Mod-B” process. Taking this one
III-52
step t%rther, Fig. 48 shows a AVit control chart based on the same da@ with deviations from statistical process control (SPC) marked with solid symbols. The reader is directed to Ref. [18] for a discussion of what it means to be under SPC, and how deviations from SPC can be identified and corrective measures taken. 2
z~ z > v * E W Q m m z >
o
-1
-2
-3 12104
12/85
12/06
12187
Gate Oxldatlon
12/88
Date
Figure 47: “X-bar, moving R’ plot of threshold voltage shifts due to interface and oxide trap charge for nMOS transistors with 45-rim oxides built in Sandia’s Mod B process. (After Ref. [18].)
0.8 -
Sandla 4 /3-pm Technology 500 krad(S102)
■
0.7 0.6
UCL
0.5 0.4 0.3
■
0.1 0.0
■ –~
w
0.2
1 o
I I 20 40
LCL
.
Non SPC
I 60
I 80
I 100
Consecutive
I
1
1
I
I
1
1
I
120 140 160 180 200 220 240 260 Lots
Processed
Figure 48: SPC of interface-trap charge for the data of Fig. 47. Average values (X-bar) and upper and lower control limits (I-JCLand LCL) are indicated. SPC violations are denoted by solid symbols. (After Ref. [18].)
III-53
Although one can see several “glitches” through the years that the process was monitored, some attributable to identifiable changes (mostly unintended) in the processing and some not traceable to a clear origin, it can be seen that the process was generally centered around welldefined mean values for interface- and oxide-trap charge densities. These were reasonably small for applications requiring total-dose hardness of- 500 krad(Si02) or less. This is a very reasonable hardness “capability” level for a radiation-hardened technology with - 45-rim oxide thickness. Just as importantly, the deviations were manageable, and it was verified over the course of running the process that IC’S whose test structures remained under control always passed lot acceptance tests [16- 18]. Conversely, a lot that showed poor test structure data occasionally had After a while, the only reason we kept doing the IC tests at trouble in meeting specifications. Sandia on a regular basis on the parts that came from the lots processed during periods when the line was under demonstrated process control was because contracts forced us to do so! The idea behind QML is to allow such “wasted” lot acceptance tests to be waived if sufficient control of the process is demonstrated. 25
SA3001 2k SRAM n- Channel
20
~ w
0.20
,5
rad(Si)/s
+Iov
n K z
‘0
5
d
0 0.0
I
I
I
I
I
I
I
0.2
0.4
0.6
0.8
1.0
1.2
1.4
8
AVlt (Volts) Figure 49: Change in read access time versus nMOS transistor AVit for static RAMs and test transistors from Sandia’s Mod B technology. RAMs were irradiated in a Cs- 137 source at 0.2 rad(SiOJ\s, and
transistors were irradiated with 10-keV x rays at 16.7 krad(Si02)/s. Doses corresponding to data points (left to right along the line) are 84,280,420,840, and 1120 krad(Si02), respectively, (After Ref. [18].) As one example of how the QML test methodology can be applied to streamline lot acceptance testing, consider Fig. 49. Here, the change in read access time is plotted for a 2k static RAM as a fi-mction of the threshold voltage shift due to interface-trap charge measured at the wafer level immediately after processing [18]. An obvious correlation is present, suggesting that one could use these test structure data as a measure of the circuit response. That is, as long as interface-trap charge densities during wafer level testing remain below those at which the IC still
III-54
functions acceptably, the process is verified to be under sufficient control that lot acceptance testing with respect to this parameter is not required. Of course, tests to ensure control of oxidetrap charge in the gate and field oxide would also normally be required. The QML approach to radiation hardness is still undergoing growing pains, being relatively new in philosophy compared to more traditional approaches based on simple lot acceptance testing of IC’S. Time will be required for vendors and users to agree on what must be measured to ensure that proper control of a process is being maintained, so that the fidl cost-saving capabilities of QML can be realized [15-19,52]. However, there is no doubt that some elements of QML (i. e., knowledge-based reduction in lot acceptable tests) are very usefhl, indeed essential, to defining cost-effective radiation hardness assurance test plans in the Mure,
8. Non-destructive
Testing
Until now we have been discussing test methods that involve either imdiating a lot sample of the devices of interest (e. g., TM 1019.4), or a test structure that serves as a hardness verification surrogate. There has been a lot of interest in the past on trying to find electrical tests that can be used to predict, before irradiation, the hardness of an individual IC or device. An extensive report on early activities was generated by Ron Pease in 1978 [190]. Basically, his conclusion was a lot of things made sense to try, but nothing really worked convincingly. This general rule remains true today for integrated circuits having more than a few transistors. It has been shown recently that, for discrete MOS transistors or perhaps small-scale circuits in which individual transistor response can be isolated, the preirradiation l/jnoise of the transistor can predict the postirradiation oxide-trap charge [142, 191-1 94]. This correlation is illustrated in Fig. 50, for five different wafers processed with different gate oxidation snd annealing treatments from the same lot, but with all other process steps being identical [112, 191-193]. The preirradiation noise power scales exactly with the postimadiation AVot for these devices. This correlation evidently occurs because both the preirradiation noise and postirradiation AVot are proportional to the density of oxygen vacancieshacancy complexes in the oxide [195]. A correlation similar to that in Fig. 50 was noted for these devices between the preirradiation channel resistance and the postirradiation AVit [196], but this is more difllcuh to exploit for a hardness assurance test, for reasons discussed in Ref. [192]. Unfortunately, it is difficult to extend these correlations to integrated circuit tests, which have more interest and impact on hardness assurance testing. Moreover, preirradiation tests for field oxide isolation (other than measurements of the initial field oxide threshold vol~) are not possible in an integrated circuit, since the parasitic field oxide transistor characteristics are only accessible after the device is irradiated. Some promise has been demonstrated for using l/’noise as a screen for power MOSFETS [197]; however, more work is needed to determine the utility of the method, We conclude that non-destructive tests of radiation hardness using l/~noise can be performed (at most) on discrete transistors and small-scale circuits, but it is unlikely that such a method can be developed with general applicability to large-scale IC’S.
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I
1O-”L 0.1
A D. M. Fleetwood and J. t-f. Scofield, Phys. Rev. Let t. 64, 579 (1990) 1
1
1 0.3
1
t
m 1 &a I 1.0
1
I 3.0
1
1 1 1 1I I 10
-AVOT (V) Figure 50: Postimadiation AVOtversus preirradiation noise magnitude for MOS transistors with five different gate oxide processes. Wafers D and E received an 1100”C Nz anneal to additionally soften the oxide; wafers A-C did not receive this anneal. (After Refs. [112,191-193].) 9. Conclusions
and Future Trends
A first-principles approach to radiation hardness assurance was described that provides the technical background for the present US and European total-dose radiation hardness assurance test methods for MOS technologies, TM 1019.4 and BS 22900. These test methods could not have been developed otherwise, as their existence depends not on a wealth of empirical comparisons of IC data from ground and space testing, but on a fundamental understanding of MOS defect growth and annealing processes [16, 113]. Because defect growth and annealing, and their effects on device response, can differ strongly in MOS and bipolar devices, it is not possible to apply the same rebound tests to bipolar devices that have been successfully applied to MOS devices in space applications [182-187]. Work continues to develop an optimized test for bipolar devices in space applications [180]. Rebound testing should become less of a problem for advanced MOS small-signal electronics technologies for systems with total dose requirements below 50-100 krad(SiOz) because of trends toward much thinner gate oxides [104]. For older technologies with thicker gate oxides and for power devices, rebound testing is unavoidable without detailed characterization studies to assess the impact of interface traps on device response in space [22,23,104]. Commercial technologies will continue to be limited by positive trapped charge in their field oxides. For low dose rate applications, the annealing rate offield-oxide leabge will be one of the most important parameters determining whether or not a given commercial MOS device or
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IC can be used in the natural space environment. This is not yet recognized in hardness assurance test methods like TM 1019.4, and must be fmtored into fi.dure test methods and guideline documents, as discussed in detail in Section 5,8 above. The QML approach is promising for fiture hardened technologies. A sufficient understanding of process effects on radiation hardness has been developed that we should be able to reduce testing costs in the future for hardened parts. Of course, this point may be moot if the present trend continues toward the increasing use of commercial parts in space systems [52,139]. On a commercial line, one cannot derive benefits fi-om knowledge gained during part development and characterization, because factors controlling radiation hardness are not identified and controlled. In the fiture, it seems prudent for hardness assurance standards to allow more relief to manufacturers who attempt to build in the quality via QML, and not just assess the innate hardness of an as-built commercial part. Finally, to paraphrase an old joke, nondestructive testing is the “Holy Grail” of total-dose radiation hardness assurance for IC’S, and probably always will be. It is hoped that the above discussions have demonstrated that the foundation for costeffective hardness assurance tests is laid with studies of the basic mechanisms of radiation effects. Without a diligent assessment of new radiation effects mechanisms in fiture technologies, we cannot be assured as a community that the present generation of radiation test standards will continue to apply. Witness the difilculties qualifying bipolar devices and IC’s at present. If the past tells us anything, it is that there will always be these kinds of surprises to deal with. I would rather deal with these surprises up front during the device characterization or hardness assurance phase of a project than in assessment of a field failure. It is hoped that there will be budget enough in the future to do so.
10. Acknowledgments I wish to thank my Sandia colleagues and fiends Peter Shaneyfelt, Fred Sexton, Bill Warren, Paul Dressendorfer, Tim Beutler, Leonard Riewe, and Sylvia Tsao for their patience, course of our hardness assurance studies on MOS devices.
Winokur, Jim Schwank, Marty Meisenheimer, Dick Reber, Dave support, and guidance over the I also would like to thank Ron
Schrimpf, Steve Kosier, Nathan Nowlin, Mike DeLaus, Ron Pease, Dawn Schmidt, Russ Graves, and Bill Combs for their assistance with bipolar device testing, and John Scofield and his students at Oberlin for assistance with the l~noise and non-destructive testing. Also thanks to Lew Cohn, Harvey Eisen, and Dennis Brown for partial fimding support from DNA, as well as for many helpfi.d discussions on hardness assurance test standards. Finally, thanks go to the members of the NASA/SSD Space Parts Working Group and the DNA Time Dependent Effects Working Group for providing user and vendor perspectives and sanity checks on hardness assLuance testing recommendations.
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102. D. M. Fleetwood, S. S. Tsao, and P. S. Winokur, “Total Dose Hardness Assurance Issues for SOI MOSFETS,” IEEE Trans. Nucl. Sci, 35, 1361 (1988). 103. W. J. Stapor, J. P. Meyers, J. D. Kinnison, and B. G. Carkhuff, “Low Dose Rate Space Estimates for ICS Using Real Time Measurements and Linear System Theory,” IEEE Trans. Nucl. Sci. 39, 1876 (1992). 104, D. M. FleetWood, P, S. Winokur, and T. L. Meisenheimer, “Hardness Assurance for Low-Dose Space Applications,” IEEE Trans. Nucl, Sci. 38, 1552 (1991), 105. F. B. McLean, “Generic Impulse Response Function for MOS Systems and Its Application to Linear
Response Analysis,” IEEE Trans. Nucl. Sci. 35, 1178 (1988). 106. P. S. Winokur, K. G. Kerris, and L. Harper, “Ptiicting CMOS Inverter Response in Nuclear and Space Environments,” IEEE Trans. Nucl. Sci. 30,4326 (1983). 107. H. H. Sander and B. L. Gregory, “Unified Model of Damage Annealing in CMOS, from Freeze-In to Transient Annealing,” IEEE Trans. Nucl, Sci. 22,2157 (1975). 108. A. J. Lelis, T. R. Oldham, H. E. Boesch, Jr., and F. B. McLean, “The Nature of the Trapped Hole Annealing Process,” IEEE Trans. Nucl. Sci. 36, 1808 (1989), 109, P. J. McWhorter, S. L, Miller, and W. M. Miller, “Modeling the Ameal of Radiation-Induced Trapped Holes in a Varying Thermal Environment” IEEE Trans. Nucl. Sci. 37, 1682 (1990). 110. J. R. Schwank, D. M. FleetWood, M. R. Shaneyfelt, P. S. Winokur, C. L. Axness, and L, C. Riewe, “Latent Interface Trap Buildup and Its Implications for Hardness Assurance,” IEEE Trans. Nucl. Sci. 39, 1953 (1992). 111. J. R. Schwank, D. M, Fleetwood, M. R, Shaneyfelt, and P. S. Winokur, “Latent Thermal]yActivated Interface-Trap Generation in MOS Devices,” IEEE Electron Dev. Lett. 13,203 (1992), 112. D. M. FleetWood, S. L. Kosier, R. N. Nowlin, R. D. Schrimpf, R. A. Reber, Jr., M. DeLaus, P, S. Winokur, A. Wei, W. E. Combs, and R. L. Pease, “Physical Mechanisms Contributing to Enhanced Bipolar Gain Degradation at Low Dose Rates,” IEEE Trans. Nucl. Sci, 41, 1871 (1994). 113. D. M, FleetWood, P. S. Winokur, C. E. Barnes, and D. C. Shaw, “Accounting for Time Dependent Effects on CMOS Total-Dose Response in Space Environments,” Radiat. Phys. Chem. 43, 129 (1994).
114. D. M. Fleetwood, P. S. Winokur, L. C. Riewe, and R. L. Pease, “An Improved Standard Total-Dose Test for CMOS Space Electronics,” IEEE Trans. Nucl. Sci. 36, 1963 (1989). 115. V. S. Pershenkov, V. V. Belyakov, and A. V. Shalnov, “Fast Switched-Bias Annealing of RadiationInduced Oxide-Trapped Charge and Its Application for Test of Radiation Effects in MOS Structures,” IEEE Trans. Nucl. Sci. 41,2593 (1994). 116, R. Verkasalo, “Effect of Test Method on the Failure Dose of SEEQ 28C256 EEPROM,” IEEE Trans. Nucl, Sci. 41,2600 (1994). 117. A. Holmes-Seidle and L. Adams, “Mapping CMOS Radiation Tolerance Data on a 4-Lane Chart,” IEEE Trans. Nucl, Sci. 41,2613 (1994). 118. P, Pavan, R. Tu, E. R, Minami, G. Lure, and P. K. Ko, “A Complete Radiation Reliability Software Simulator,” IEEE Trans. Nucl. Sci. 41,2619 (1994).
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119. I. N, Shvetzov-Shilovsky, S. V. Cherepko, and V. S. Pershenkov, ‘The Improvement of MOSFET Prediction in Space Environments Using the Conversion Model,” IEEE Trans. Nucl. Sci. 41, 2631 (1994). 120. V. S, Pershenkov, V. V. Belyakov, S. V. Cherepko, and I. N. Shvetzov-Shilovsky, “Three-Point Method of Prediction of MOS Device Response in Space Environments,” IEEE Trans. Nucl. Sci. 40, 1714 (1994). 121. W. C. Jenkins and R. L. Martin, “A Comparison of Methods for Simulating Low-Dose-Rate Gamma Ray Testing of MOS Devices,” IEEE Trans. Nucl. Sci. 38, 1560 (1991), 122. D. M. Fleetwood, P, S. Winokur, and L. C. Riewe, “Predicting Switched-Bias Response from Steady-State Irradiations,” IEEE Trans. Nucl. Sci. 37, 1806 (1990). “A Comparison of Methods for Total Dose Testing of Bulk CMOS and CMOS/SOS Devices,” IEEE Trans. Nucl, Sci, 37, 1818 (1990).
123. M. P. Baze, R. E. Plaag, and A. H. Johnston,
124. D. B. Brown, W. C. Jenkins, and A. H. Johnston, “Application of a Model for Treatment of Time Dependent Effects on Irradiation of Microelectronic Devices,” IEEE Trans. Nucl. Sci. 36, 1954 (1989). 125, H, E. Boesch, Jr,, “A Proposed Scheme for Measuring and Categorizing the Total Ionizing Dose Response of MOS Devices,” IEEE Trans. Nucl. Sci. 33, 1337 (1986). 126. A. J. Lelis, T. R. Oldham, and W. M. DeLancey, “Response of Interface Traps During HighTemperature Anneals,” IEEE Trans. Nucl, Sci. 38, 1590 (1991). 127. Total Dose Steady-State Irradiation Method, ESA/SCC (European Space Agency/Space Components Coordination Group) Basic Specification 22900, Draft Issue 5, July 1993. 128. M. G. Buehler, B. R. Blaes, and Y-S. Lin, “Radiation Dependence of Inverter Propagation Delay from Timing Sampler Measurements,” IEEE Trans. Nucl. Sci. 36, 1981 (1989). 129. D. M, FleetWood, P. V. Dressendorfer, and D. C, Turpin, “A Reevaluation of Worst-Case Postirradiation Response for Hardened MOS Transistors,” IEEE Trans. Nucl. Sci. 34, 1178 (1987), 130. D. M. Fleetwood and P. V. Dressendorfer, “A Simple Method to Identifj Radiation and Annealing Biases that Lead to Worst-Case CMOS Static RAM Postirradiation Response,” IEEE Trans. Nucl. Sci. 34, 1408 (1987), 131. T. Stanley, D. Neamen, P. V. Dressendorfer, J. R. Schwank, P. S. Winokur, M. Ackermann, K. Jungling, C. Hawkins, and W. Grannemann, “The Effect of Operating Frequency in the Radiation Induced Buildup of Trapped Holes and Interface States in MOS Devices,” IEEE Trms. Nuc1, Sci, 32,3982 (1985). 132, P. V. Dressendorfer, J, M. Soden, J. J. Barrington, and T. V. Nordstrom, “The Effects of Test Conditions on MOS Radiation-Hardness Results,” IEEE Trans. Nucl. Sci. 28,4281 (1981). 133. D. M. FleetWood, “Radiation-Induced Charge Neutralization and Interface-Trap Buildup in MOS Devices,” J. Appl. Phys. 67,580 (1990). 134. R, A. B. Devine, D. Mathiot, W. L. Warren, D. M. Fleetwood, and B. Aspar, “Point Defect Generation and Oxide Degradation During Annealing of the Si/Si02 Interface,” Appl. Phys, Lett. 63, 2926 (1993). 135. J. R, Schwank and D, M. FleetWood, “The Effect of Postoxidation Anneal Temperature on Radiation-Induced Charge Trapping in Poly-Si Gate MOS Devices,” Appl, Phys. Lett. 53, 770 (1988).
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136. J. R, Schwank, D. M. Fleetwood, P. S. Winokur, P. V. Dressendorfer, D. C. Turpin, and D. T. Srmders, “The Role of Hydrogen in Radiation-Induced Defect Formation in Poly-Si Gate CMOS Devices,” IEEE Trans. Nucl. Sci. 34, 1152 (1987). 137. G. F. Derbenwick and B. L. Gregory, “Process Optimization of Radiation-Hardened CMOS ICS,” IEEE Trans. Nucl. Sci, 22,2151 (1975), 138. K. G. Aubuchon, “Radiation Hardening of pMOS Devices by Optimization of the Thermal SiOz Gate Insulator,” IEEE Trans. Nucl. Sci. 18, No. 6, 117 (1971). 139. M. R. Shaneyfelt, P, S. Winokur, T. L. Meisenheimer, F. W. Sexton, S. B. Roeske, and M. G. Knoll, “Hardness Variability in Commercial Technologies,” IEEE Trans. Nucl. Sci. 41,2536 (1994). 140. J. M. Terrell, T. R, Oldham, A. J, Lelis, and J. M. Benedetto, “Time Dependent Annealing of Radiation-Induced Leakage Currents in MOS Devices,” IEEE Trans. Nucl. Sci. 36,2205 (1989). 141. J. M, McGarrity, “Considerations for Hardening MOS Devices and Circuits for Low Radiation Doses,” IEEE Trans. Nucl. Sci. 27, 1739 (1980). 142.
D. M. FleetWood and J. H. Scofield, “Evidence that Similar Point Defects Cause l~Noise and Radiation-Induced-Hole Trapping in MOS Devices,” Phys. Rev. Lett. 64, 579 (1990).
143.
J. M. Benedetto and H. E. Boesch, Jr., “The Relationship Between CO-60 and 10-keV X-ray Damage in MOS Devices,” IEEE Trans. Nucl. Sci. 33, 1318 (1986).
144. M. R. Shaneyfelt, D. M. FleetWood, J. R. Schwank, and K, L. Hughes, “Charge Yield for 10-keV Xray and CO-60 Irradiation of MOS Devices,” IEEE Trans. Nucl. Sci. 38, 1187 (1991). 145. N. S. Saks and D. B. Brown, “Interface Trap Formation Via the Two-Stage H+ Process,” IEEE Trans. Nucl, Sci. 36, 1848 (1989). 146. D. M. FleetWood, R. W. Beegle, F. W. Sexton, P. S. Winokur, S. L. Miller, R. K. Treece, J. R. SchwanL R. V. Jones, and P. J. McWhorter, “Using a 10-keV X-ray Source for Hardness Assurance,” IEEE Trans. Nucl. Sci. 33, 1330 (1986). 147. C. M. Dozier and D. B, Brown, “The Use of Low Energy X-rays for Device Testing: A Comparison with CO-60 Radiation,” IEEE Trans. Nucl. Sci. 30,4382 (1983). 148. D. M, Fleetwood, D, E. Beutler, L. J. Lorence, Jr., D. B. Brown, B, L. Draper, L. C. Riewe, H. B. Rosenstock, and D. P, Knott, “Comparison of Enhanced Device Response and Predicted X-ray Dose Enhancement Effects on MOS Oxides,” IEEE Trans. Nucl. Sci. 35, 1265 (1988). 149, C. M. Dozier, D. M. Fleetwood, D. B. Brown, and P. S. Winokur, “An Evaluation of Low-Energy X-ray and CO-60 Irradiations of MOS Transistors,” IEEE Trans. Nucl. Sci. 34, 1535 (1987). 150, J. M. Benedetto, H. E. Boesch, Jr., T. R. Oldham, and G. A. Brown, “Measurement of Low-Energy X-ray Dose Enhancement in MOS Devices with Metal Silicided Gates,” IEEE Trans. Nucl. Sci. 34, 1540 (1987). 151. R.N. Harem, “Dose Calculations for Si-Si02-Si Layered Structures Irradiated by X-rays and CO-60 Gamma Rays,” IEEE Trans. Nucl. Sci. 33, 1236 (1986). 152. D. B. Brown, “The Phenomenon of Electron Rollout for Energy Deposition and Defect Generation in Imdiated MOS Devices,” IEEE Trans. Nucl. Sci. 33, 1240 (1986). 153. L. J. Lorence, Jr., “Electron Photoemission Predictions with CEPXS/0NETIL4N,” Nucl. Sci, 35, 1288 (1988).
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IEEE Trans.
154, J. A. Halbleib and T, A. Melhorn, “ITS: The Integrated TIGER Series of Coupled Electron/Photon Monte Carlo Transport Codes,” Nucl. Sci, Eng. 92,338 (1986). 155. L. J. I.mrence, Jr., W. E. Nelson, and J. E. Morel, “Coupled Eleciron-Photon Transport Calculations Using the Method of Discrete Ordinates,” IEEE Trans. Nucl. Sci. 32,4416 (1985). 156. D. E. Beutler, D, M. Fleetwood, W. Beezhold, D. Knom L. J. Lorence, Jr., and B. L, Draper, “Variations in Semiconductor Device Response in a Medium-Energy X-ray Dose-Enhancing Environment,” IEEE Trans. Nucl. Sci. 34, 1544 (1987). 157. C. M. Dozier, D. B. Brown, J. L. Throckmorton, and D. I. M% “Defect Production in SiOz by X-ray and CO-60 Radiations,” IEEE Trans. Nucl. Sci. 32,4363 (1985). 158. D. M. FleetWood, P. S. Winokur, R. W. Beegle, P. V. Dressendorfer, and B. L. Draper, “Accounting for Dose-Enhancement Effects with CMOS Transistors,” IEEE Trans. Nucl. Sci. 32,4339 (1985). 159. T. R. Oldham and J. M. McGarrity, “Comparison of CO-60 Response and 10-keV X-ray Response in MOS Capacitors,” IEEE Trans. Nucl. Sci. 30,4377 (1983). 160. C. M. Dozier and D. B. Brown, “Photon Energy Dependence of Radiation Effects in MOS Structures,” IEEE Trans. Nucl. Sci. 27, 1294(1980). 161. D. M. Fleetwoo~ P. S. Winokur, C. M. Dozier, and D. B. Brown, “Effects of Bias on the Response of MOS Devices to Low-Energy X-ray and CO-60 Irradiation,” Appl. Phys. Lett. 52, 1514 (1988). 162. J. R. Srour and K. Y. Chiu, “MOS Hardening Approach for Low-Temperature Application,” IEEE Trsns. Nuc1. Sci. 24,2140 (1977). 163. S. S. Tsao, D. M. Fleetwood, H. T. Weaver, L. Pfeiffer, and G. K. Celler, “Radiation-Tolerang Sidewall-Hardened SOI/MOS Transistors,” IEEE Trans. Nucl. Sci. 34, 1686 (1987). 164. G. E. Davis, H. L. Hughes, and T. I. Kamins, “Total Dose Radiation-Bias Effects in LaserRecrystallized SOI MOSFET’S,” IEEE Trans. Nucl. Sci. 29, 1685 (1982). 165.0. Flamen~ D. Herve, O. Musseau, Ph. Bonnel, M. Raffaelli, J. L. Leray, J. Margail, B. Giffard, and A. J. Auberton-Heme, “Field Dependent Charge Trapping Effects in SIMOX Buried Oxides at Very High Dose,” IEEE Trans. Nucl. Sci. 39,2132 (1992). 166. H. E. Boesch, Jr., T. L. Taylor, L. R. Hite, and W. E. Bailey, “Time-Dependent Hole and Electron Trapping Effects in SIMOX Buried Oxides,” IEEE Trans. Nucl. Sci. 37, 1982 (1990). 167. F. T. Brady, W. A. Krull, and S. S. Li, “Total Dose Radiation Effects for Implanted Buried Oxides,” IEEE Trans. Nucl. Sci. 36,2187 (1989). 168. M. Matloubian, E. J. Zorinsky, and D. B. Spratt, “Total Dose Radiation Characterization of SOI MOSFETS Fabricated Using Islands Technology,” IEEE Trans. Nucl. Sci. 35, 1650 (1988). 169. M, R. Shaneyfelt D. M. FleetWood, J. R. Schwank, T. L. Meisenheimer, and P. S. Winokur, “Effects of Burn-In on Radiation Hardness,” IEEE Trans. Nucl. Sci. 41,2550 (1994). 170. E. W. Enlow, R. L. Pease, W. E. Combs, and D. G. Platteter, “Total Dose Induced Hole Trapping in
Trench Oxides,” IEEE Trans. Nucl. Sci. 36,2415 (1989). 171. R. L. Pease, D. Emily, and H. E. Boesch, Jr., “Total Dose Induced Hole Trapping and Interface State Generation in Bipolar Recessed Field Oxides,” IEEE Trans. Nucl. Sci. 32,3946 (1985). 172. R. L. Pease, R. M. Turfler, D. Platteter, D. Emily, and R. Blice, “Total Dose Effects in Recessed Oxide Digital Bipolar Microcircuits,” IEEE Trans. Nucl. Sci. 30,4216 (1983).
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173, S. L, Kosier, A. Wei, R. D. Schrimpf, D. M. Fleetwood, M. DeLaus, R. L, Pease, and W. E. Combs, “Physically-Based Comparison of Hot-Camier-Induced and Ionizing-Radiation-Induced Degradation in BJTs,” IEEE Trans. Electron Dev. 42,436 (1995). 174, S. L. Kosier, R, D. Schrimpf, R. N. Nowlin, D. M. Fleetwood, R. L. Pease, M, DeLaus, W. E. Combs, A, Wei, and F. Chai, “Charge Separation for Bipolar Transistors,” IEEE Trans. Nucl. Sci. 40, No. 6, 1276 (1993). 175, A, R. Harg J. B. Smyth, V. A. J. van LinC D. P. Snowden, and R. E. Leaden, “Hardness Assurance Considerations for Ixmg-Term Ionizing Radiation Effects on Bipolar Structures,” IEEE Trans. Nucl. Sci. 25, 1502 (1978). 176. L. L. Sivo, H. L, Hughes, and E. E. King, “Investigation of Radiation-Induced Interface States Utilizing Gated-Bipolar and MOS Structures,” IEEE Trans. Nucl. Sci. 19, 313 (1972). 177, S. Feindt, J-J. J. JaJar. J. Lapham, and D. Buss, “XFCB: A High Speed Complementary Bipolar Process on Bonded SOI,” IEEE BCTM Tech. Digest, 264 (1992). 178. A. Wei, S. L. Kosier, R. D. Schrimpf, D. M. Fleetwood, and W. E. Combs, “Dose-Rate Effects on Bipolar Junction Transistor Gain Degradation,” Appl. Phys. Lett. 65, 1918(1994). 179, D. M. Schmidt, R. J. Graves, R. D. Schrimpf, D. M. Fleetwood, R. N. Nowlin, and W. E. Combs, “Comparison of Ionizing Radiation Induced Gain Degradation in Lateral, Substrate, and Vertical PNP BJTs,” to be presented at 1995 IEEE NSREC, Madison, WI, and submitted to Dec. 1995 IEEE Trans. Nucl. Sci. 180, R. J. Graves, D. M. Fleetwood, D. M. Schmidz R. N. Nowlin, R. D. Schrirnpf, W. E. Combs, R. L. Pease, and M, DeLaus, “Hardness Assurance Issues for Lateral PNP Bipolar Junction Transistors,” to be presented at 1995 IEEE NSREC, Madison, WI, and submitted to Dec. 1995 IEEE Trans. Nucl. Sci. 181. A. H, Johnston, G. M. Swift, and B. G. Rax, “Total Dose Effects in Conventional Bipolar Transistors and Linear Integrated Circuits,” IEEE Trans. Nucl. Sci. 41,2427 (1994). 182. E. W. Enlow, R. L. Pease, W. Combs, R. D. Schrimpf, and R. N. Nowlin, “Response of Advanced Bipolar Processes to Ionizing Radiation,” IEEE Trans. Nucl. Sci. 38, 1342 (1991). 183. R. N. Nowlin, D. M. Fleetwood, R. D. Schrimpf, R. L. Pease, and W. E. Combs, “HardnessAssurance and Testing Issues for Bipolar/BiCMOS Devices,” IEEE Trans. Nucl. Sci. 40, 1686 (1993). 184. S. L. Kosier, W. E. Combs, A. Wei, R. D. Schrimpf, D. M. Fleetwood, M. DeLaus, and R. L. Pease, “Bounding the Total Dose Response of Modem Bipolar Transistors,” IEEE Trans. Nucl. Sci. 41, 1864 (1994). 185. J. Beaucour, T. Carriere, A. Gach, D. Laxague, and P. Poirot, “ToM Dose Effects on Negative Voltage Regulator,” IEEE Trans. Nucl. Sci. 41,2420 (1994). 186. S. McClure, R. L. Pease, W. Will, and G. Pemy, “Dependence of Total Dose Response of Bipolar Linear Microcircuits on Applied Dose Rate,” IEEE Trans. Nucl. Sci. 41,2544 (1994). 187. R. N. Nowlin, D. M. Fleetwood, and R. D. Schrimpf, “Saturation of the Dose-Rate Response of Bipolar Transistors Below 10 rad(Si02)/s: Implications for Hardness Assurance,” IEEE Trans. Nucl. Sci. 41,2637 (1994). 188. R.N. Nowlin, E, W. Enlow, R. D. Schrimpf, and W. E. Combs, “Trends in the Total-Dose Response of Modem Bipolar Transistors,” IEEE Trans. Nucl. Sci. 39,2026 (1992).
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189. W. L, Warren, M. R. Shaneyfelt, J. R. Schwank, D. M. Fleetwood, P. S. Winokur, R. A. B. Devine, W, P. Maszara, and J. B. McKitterick, “Paramagnetic Defect Centers in BESOI and SIMOX Buried Oxides,” IEEE Trans. Nucl. Sci, 40, 1755 (1993). 190. R. L. Pease, “Identification
and
Verification of Total Dose Hardness Assurance Techniques,”
BDM/TAC-78-764-TR (1978). 191.
D. M. FleetWood, T. L. Meisenheimer, and J. H. Scofield, “1/&_Noiseand Radiation Effects in MOS Devices,” IEEE Electron Dev. Lett. 41, 1953 (1994).
192. J, H. Scofield and D, M, Fleetwood, “Physical Basis for Nondestructive Tests of MOS Radiation Hardness,” IEEE Trans. Nucl. Sci. 38, 1552(1991). 193. J. H. Scofield, T. P. Doerr, and D. M. Fleetwood, “Correlation Between Preirradiation l/f Noise and Postirradiation Oxide-Trapped Charge in MOS Transistors,” IEEE Trans. Nucl. Sci. 36, 1946 (19s9). 194.
L. K. J. Vandamme, X. Li, and D. Rigaud, “l/’Noise in MOS Devices: Mobility or Number Fluctuations?” IEEE Trans. Electron Dev. 41, 1936(1994).
195.
D. M. FleetWood, W. L. Warren, M. R. Shaneyfelt, R. A. B. Devine, and J. H. Scofield, “Enhanced MOS I/&Noise due to Near-Interracial Oxygen Deficiency,” accepted for publication, J. Non-Crys. Solids (1995).
196. J. H. Scofield, M. Trawick, P. Klimecky, and D. M. Fleetwood, “Correlation Between Preirradiation Channel Mobility and Radiation-Induced Interface-Trap Charge in MOS Transistors,” Appl. Phys, Lett. 58,2782 (1991). 197. P. Augier, J. L. Todsen, D. Zupac, R. D. Schrimpf, K. F. Galloway, and J. A. Babcock, “Comparison of 1/’Noise in Irradiated Power MO SFETS Measured in the Linear and Saturation Regions,” IEEE Trans. Nucl. Sci, 39,2012 (1992).
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1995 NSREC SHORT COURSE
Advanced Test Methodologies
Nick van Vonno
Harris Semiconductor
Iv
NSREC ’95 SHORT COURSE - SECTION 4 Section
Oblective
While this section is entitled “Advanced Test Methodologiesm perhaps a more appropriate name would be “Radiation Testing: The Manufacturers Perspective” since that is what we will seek to provide. In that sense the Short Course provides a fairly logical flow: it leads off with two sections on the basic technical considerations of radiation testing with focus on total dose and single event effects, taught appropriately enough by recognized experts from government. The student will gain insight from a vigorous, almost “pure science” approach to these two disciplines. Section 3 takes this basic material and views it from the semimnductor manufacturers perspective; he is not interestad in science, but would like to ship compliant parts! The emphasis here is on practical testing and standards, first in the context of traditional approaches and then from the standpoint of today’s rapidly changing markets. Sedlon 4 shifts perspectives to the system integrator, who is the semimnductor vendor’s direct wstomer and whose interests are different again.
Section Roadmap ●
Review some terms and definitions.
●
Review total dose testing, including wafer and package level testing, test correlations and dose rate effects.
●
Review dose rate testing.
●
Tie these topics together in a review of in-orbit verification.
●
Digress to cryogenic radiation testing, a little out of sequence but a topic of current interest.
●
Summarize limits of traditional approaches.
●
Introduce and review the QML concept, including certifications, methodology and SPC applications.
●
Compare US standards to European standards.
●
Review several somewhat disparate future trends, including dose packaging, bumin effects and the impact of current commercial off-the-shelf (COTS) mandates.
lV-i
NSREC ’95 SHORT COURSE - SECTION 4
1.
Traditional
1.1.
Introduction
Approaches
In this section of the Short Course we first review conventional test methods for total dose, SEE and transient environments. These methods have been developed to a high degree of maturity but as device complexity inweases and ASIC applications extend to hardened systems, alternatives have become necessary to control costs leading to advanced methods such as QML.
1.1.1. Definition of Hardened Pafts Radiation Hardness Assured (RHA) pads are semiconductor components that have demonstrated predictable performance after inadiation to a specified level. These parts can include those specifically designed and processed for hardness as well as commercial parts that have been characterized for hardness. Clearty the higher levels of radiation will require specialized processing and design using post-red models to predict performance. Procurement of RHA components has been defined by military standards such as Ml L-S-l 9500 (discrete components) and MIL-M-3851O (microcircuits), while test methods are incorporated in to the environmental test draw-rigs MIL-STD-750 and MIL-STD883. Recent trend has been towards Qualified Manufacturer Listing (QML) based qualification as defined by MIL-I-38535, a topic we will cover in detail later on. A second, less cJeariy defined category is that of radiation-tolerant parts. These components feature lower radiation levels and are typically commem-al parts that have been characterized by radiation testing; they are then sold against this experimentally defined radiation spec. Implicit in this approach is the possible sudden disappearance of the part’s hardness capability due to process changes in what is basically an uncontrolled situation. Nonetheless these red-tolerant patis can be effective in many programs, given adequate lot screening and qualification procedures. 1.1.2.
Testing Testing is the key pati of a well structured hardness assurance program. Its primary objective is the verification of hardness performance, usually on a lotby-lot basis; this will also allow establishment of a database of hardened parts. These databases[’2Jq are useful in selecting hardened parts or assessing the potential hardness of standard commercial parts. They can also be used for verifying hardening techniques and understanding basic radiation damage mechanisms.
1.2.
Total
Dose Testing
Since the first section of the Shotl Course has covered total dose testing in great detail this section will be kept brief. The standard US method for total dose acceptance
Scs!sdx
Iv-1
5/1 t3m5
testing is MI L-STD-883 Test Method 1019.4; it describes procedures for testing in a ‘Co source at moderate dose rates, and has been in use for a number of years. The procedure also specifies accelerated aging evaluation as a means for estimating low dose rate radiation effects. Total dose testing can also be performed using an alternative source, usually an Aracor x-ray system; this has a major advantage in being able to do acceptance testing at the wafer level and is of current interest in the context of QML approaches, both for qualification testing and process monitoring. It is well adapted to wafer-level testing since X-ray irradiation of packaged devices suffers from limited penetration of the 10 KeV photons, Correlation to ‘Co results[”q is provided by ASTM Standard ASTM-F 1467, “Standard Guide for the use of an X-ray Tester -10 KeV Photons) in Ionizing Radiation Effects Testing of Microelectronic Devices”. L While this correlation requires careful attention to device physics and test conditions, it is accurate and enables qualification testing to be wried out in a predictable manner. In particular, dose enhancement effects need to be taken into account; electrons absorbed in one region of the device can deposit energy in other regions through electron transpoti and diffusion. High-Z materials such as W or Ta used for siliciding operations can provide substantial dose enhancement. Dose enhancement factors as high as 2.5 have been reported.m Alternatives to ‘Co and 10 KeV X-ray sources include linear accelerators (LINAC) that deposits high-energy (20 MeV) electrons at high dose rate to the order of 10g rad(Si)/sec. This approach is best suited to high levels of total dose irradiation. Finally radioisotopes such as ‘Sr and ‘37CS are in use and are convenient laboratory sources. From a simulation fidelity standpoint, most of these sources have rather narrow energy ranges as compared with the attenuated, broad spectrum that reaches actual components after passing through the shielding of spawxaft structures. It should also be noted that Method 1019.4 specifies a greatly accelerated dose rate in comparison to actual natural environments; the actual dose rate specified[8] is from 50 rads(Si)/sec to 300 mds(Si)/sec. 1019.4 does permit dose rates outside this range if mutually agreed upon. The use of Gammacells and so on introduces reflections and dose enhancement, and accurate dosimetry is still a key requirement. Packaging also plays a role and dose enhancement can occur here as well. The low energy (1O Kev photons) of x-ray sources leads to significant absorption k# packaging materials,and this effect is a component of the correlation issue between Co and x-ray results. The table below summarizes total dose radiation sources and some of their characteristics.
Table 1: Total Dose Radiation Source Sourca
Type
Enargy
Doss Rata
‘co
Photon
1.25 MeV
104-103 rads(si)kec
103-1 d radqsi)tsec 103-104 rads(Si)/sec 103-1011 rads(Si)/sec (pulse mode)
Natural Environment
SC95.C!OC
Electrons Protons Photons
1 MeV 100 MeV
IV-2
104-10-2 rads(si)lsec
A subject of great cunent interest is the effects of low dose rate radiation on commercial pads. Recall that ground testing proceeds at dose rates in the 150-300 md(Si)/sec range of ‘Co sources and that dose rates in space are much lower, in the .001 -.01 rad(Si)/sec ran e. MOS technology response to low dose rates has been extensively investigated. A Charge separation techniques[’q have been used to develop test standards that enable the testing of MOS parts at high dose rates, followed by high temperature anneals. [”] These techniques separate the interface trap density (NJ and the fwed charge at the SiOJSi interface (Nd), enabling correlation with the respective threshold voltage shift components AVnand AVd. The degradation mechanisms in bipolar devices are dearly much different. Degradation of current gain is caused by excess base current increases; these occur under imadiation by charge deposition in the oxide over the active base area. Excess base current components are determined by surface recombination velocity and depletion layer spreading; both are caused by net positive charge (N4 in the oxide. Bipolar oxides are not as ‘clean” as MOS oxides, in particular because of ion implantation damage, and are very effective at trapping positive charge. The actual mechanism responsible for the low dose rate sensitivity of these structures is implicated by the fact that there are two components to the radiation damage. “q Analysis of these mechanisms has shown that the increased degradation at low dose rate is caused by large amounts of net trapped charge in the base oxide at lower electric fields. [’a This increased amount of charge has been found to lead to much larger excess base cuments, in some cases as high as 10 times. The dependence of Albon Na has been shown [’41to be proportional to exp (NU2), explaining the severe gain degradation encountered. An excellent treatment by Nowlin, et al[’a shows the low dose rate sensitivity saturating below 10 rads(Si)/second, using data for dose rates mnging from .01 md(Si) to 1760 rad(Si)/sec. Fig. 1 shows the dose rate dependence of the excess base current for singl~poly SOI NPN bipolar transistors[’6”q- the saturation at 10 rad(Si)/sec shows up dearty. The implications on hardness assu;ance for the commercial components that are increasingly being used are significant. Worst-case testing at the breakpoint (see Fig. 1) of 10 mds(Si)/second appears to be adequate, and acceleration factor can be computed from the mtio of the two response regimes. Work has also been done in testing these bipolar parts at Method 1019.4 dose mtes (50 -300 mds(Si)/see), but with the devices heated to 60°C during inadiation. A great deal of work remains to be done in this area, and intensive research is ongoing. Note also that the saturation below 10 md(Si)/sec as shown in Fig. 1 will not apply to all bipolar processes, and that the breakpoints on this plot may also vaty from lot to lot.
Scsmcc
IV-3
Wlm
[
1
I
35
3 2.s
o ●
=2
■
m
x+9y
G
1.s
1
100M
(SJOJ
0.s 0.0 I
1
1 1 111111 1 1 I 111111 1 1 I 111111 1 1 1111111 1 I I 111111 1 1 11
0.01
Figure 1:
0.1
10
1
100
10W
Dose rate dependence of excess base current for devices irradiated at room tempemture. After Nwdim et al. [lq
Dosimetry for total dose testing can use various approaches, and we will review two frequently used ones. Thermoluminescent detector (TLD) devices are widely used for compactness and convenience. TLD’s operate by light emission from lattice sites excited by irradiation; they do have a limited lifetime due to wear out mechanisms (fading) which restricts use in very long exposures. Photochromic detectors (PD) use color-sensitive organic dyes in a transparent plastic matrix. Readout is by measurement of absorption as a function of wavelength, a simple spectrophotometric procedure. These are very stable detectors and 1% reproducibility is achievable. They are better suited than TLD’s for monitoring of long-term radiation tests. Table 2 shows representative TLD materials, while Figure 2 shows a representative PD calibration characteristic.
Table 2: TLD Materials Material
I
Dose Range, rads(Si)
I
Thermal Fading
LiF
10-2.104
CaF2/Mn
104-104
Average (1%/day)
CaF2/Dy
103-104
Weak (13%/me)
Weak (5%/yr)
Source:AEATechnologyUK
sc95.doc
IV-4
5/1 em
4
BATCH
%6
IN TERCOMPARISON
AX
3
2.6
2
1.6
wlthln * 1%.
Agroutwnt I
1 0.s o
I o
I
1
0.6
1
1
1
1 2.6
2
1.6
Dow
Figure 2:
I s
1
3.6
I
4
1
I
4.6
5
ffiy
Photochromic detector calibmtion curve. Source AEA Technology
The basic specification for a total dose test will include at least the following parameters in order to fully define the test: Radiation source to be used Dosimetry standards and methods Radiation level(s) and dose rate lmadiation temperature Circuit configumtion:
static, dynamic or unpowered
Circuit measurements: in-situ or pre- and post imadiation; cool down Measurement
period
“cool down”
period,
and
bias
of rebound
effects;
rebound
time period
The basic approach to total dose acceptancetesting is the qualification of a ‘lot” of product, with the definition of a lot being variable over a wide range depending on program requirements. Some commonly specified approaches are discussed below. A. Date Code The manufacturer’s date code can be used to define a reasonably homogeneous lot. The actual meaning of a date code can vary, and the manufacturer needs to be consulted as to the exact meaning of the code. Most often date codes are based on assembly date, and a given code can contain die from many fabrication lots. Since hardness is driven largely by wafer fabrication parameters a date code
Scs.dm
IV-5
WIslm
will likely contain large variability in radiation response. This method is inexpensive, though, and is used to good advantage in radiation-tolerant parts programs with relatively low total dose requirements. B. Lot Code This usually defines a fabrication lot, and requires special attention from the device manufacturer to retain traceability. The use of lot codes has been used extensively in military programs; usually, the lot is kept intact through assembly, test and subsequent hi-ret processing that includes radiation acceptance testing. Clearly the paperwo~ overhead increases dramatically, as does the cost. Lots tend to be small, and record keeping is ~ a function of lot size! The method offers much improved uniformity of radiation response within the lot since it contains only waferwafer variations. C. Wafer Number Here each wafer retains its identification all through the process, and screening and acceptance are done on a by-wafer basis. This method is prevalent in MILSTD-883 “Class S processing for space appli~tions. Processing will include inprocess SEM inspection as well as hi-rel screening and radiation testing, with wafer quadrant traceability a mmmon requirement. Costs and throughput time are high, but the method offers excellent correlation of radiation test results to in-process data. In the above lot conventions acceptance is done by sampling lot populations and performing radiation tests on the samples, with electrical data being taken before and after irradiation. Method 1019.4 provides exhaustive specification of radiation test conditions, device biasing, cool down and biasing during cool down. As an alternative, parts can be monitored in-situ while being irradiated; this approach is limited in accuracy because long leads restrict measurement flexibility. In all cases the complex sequence of selecting samples and then performing the test/irradiate/test flow will take a great deal of time and expense. Since this is a destmctive test the irradiated samples are scrap; this is not diffmlt to accept for SS1/MSl parts but starts to hurt at levels much above that. By the time one gets to the extreme complexity of a large static randomaccess memory or (worse) a 200000 gate ASIC the method becomes impractical. Early attempts at solving the sampling dilemma used test structures as an alternative method of evaluating hardness. These approaches used on-chip test transistors; hardness evaluation must then obviously be indirect in nature. Past experience ‘18’lq used bipolar transistor gain and transition frequency (FT) as indicators of BJT hardness; this works well enough for neutron environments but is of limited utility in total dose environments. Especially in the case of MOS transistors device hardness is such a strong function of processing that extrapolation is diticult. In the MOS device the gate and field oxides dominate total dose hardness, and direct testing is required. Significantly, die-level acceptance schemes invariably require periodic sampling radiation tests to validate the procedure. As we will see later, the introduction of QML methods
has revived interest in test structure physics.
Acceptance testing at the wafer level has been used in the past and eliminates the effort and delay of packaging. Wafer level testing also enables rejection of failed wafers before any further value added is incurred. Total dose irradiation of individual die on a wafer has been performed by collimated low-energy x-rays; in this way
sc95s&c
IV-6
WIws
individual die can be irradiated. Dosimetry by PIN diode can be readily implemented, and the referenced systems can provide dose rates ranging from 1 rad(Si)/sec to 3000 rad(Si)/sec. The collimation system can reduce x-ray s@ter by four orders of magnitude. As we have mentioned elsewhere, the X-ray to ‘Co comelation must be taken into mnsideration due to the differences in energy spectraP1=. At the wafer level package-redu=d dose enhancement is eliminated. An alternative, test structure-based method is part of the QML procedure. In this approach the performance of a test structure is correlated to experimentally defined IC performance. In order to cover the entire range of threat environments, the test structure will actually be a complex chip with both individual active devices as well as circuit functions. We’ll describe this Technology Characterization Vehicle (TCV) approach in more detail in the QML section. QML offers a completely different approach to total dose qualification (as well as all other aspects of reliability and quality assurance) and will be discussed in detail later. Again, correlation of test structure data to actual part-level results is a key consideration.
1.3.
Dose Rate Testing Dose mte is defined as the rate of change of a gamma radiation pulse; it causes hole/electron pair generation in silicon that result in wrrent spikes. These can be simple junction photocment or more complex primary and secondaty photocuments in devices. Low levels of transient mdiation produce noise pulses, while higher levels can cause Iatchup and burnout. The term “upse~ is commonly used in dose mte testing and refers to the device under test changing state. This is easily defined in digital systems as a bit flip, a soft error from which the circuit can recover quickly. In an analog context this is not as straightforward, and a more arbitmfy definition of upset has to be supplied. As an example opemtional amplifiers are commonly connected in a 10X gain configuration and the output is monitored during mdiation exposure; a change in output voltage of more than one volt is then defined as upset. This is very subjective and mre must be taken to define such a criterion clearly. As dose rate increases response will change from a soft-emor upset to potentially more damaging phenomena. In both analog and digital devices that use junction isolation (Jl) the part may latch up due to four-layer devices being turned on. This results in a low-resistance path between supplies that at best will cause a nonfunctional device that can be restored to correct operation by cycling the power supplies through a zero crossing. The worstcase effect simply bums out the device. Use of current limiting and dielectric isolation (Dl) technology can produce a virtually burnout-proof device; this is a mmmon bipolar technique. In MOS technologies the use of epitaxial construction on heavily doped substrates will greatly enhance Iatchup susceptibility, while passive isolation techniques such as silicon-on-sapphire (SOS) and the more recent silicon-on-insulator (SOI) approach will reliably eliminate it, Both of these passive isolation techniques have diminishing source issues, however, with milita~ part volume redutions resulting in only a few viable sources. Commercial SOI is attractive from a performance viewpoint, but has yet to make much of an impact. Defect density problems and high substrate costs are limiters. If commercial SOI catches on the availability of military/space parts in this technology will be eased. Again MIL-STD-883 provides basic guidelines for dose mte testing. Since dose rate sensitivity is a fundamental system consideration, response data needs to be obtained eafiy in the design cycie. Especially in bulk technologies it is essential that samples represent as many fabrication lots as is practhl since the four-layer devices responsible for Iatchup are highly variable. m’z’za
SCS5.*
IV-7
W 6/Qs
Upset testing is nondestructive in nature and so in principle could be done on a 100% basis, although the complexity and expense of this test usually preclude such an approach. Burnout testing on the other hand is considered destructive; even if the DUT does not actually bum out the possibility of latent damage resulting in later reliability problems is very high, Similarly Iatchup testing is also destmctive, and both of these tests are thus performed on a sample basis. The most common radiation sources used for dose rate testing are the linear accelerator (LINAC) or flash X-ray (FXR) machines. The LINAC is useful for testing devices in dose-rate ranges from 1x10° to 1x1 011rad(Si)/see, with variable pulse width. The FXR machine can provide higher dose rates but is restricted to a single pulse width. Since dose rate testing is performed with the device under test in an operating condition, equipment and fixturing to drive and monitor the DUT is needed, and this can be very complex in the case of higher level-of-integration parts. Noise caused by coupling into cables and by air ionization an result in signal corruption, and irradiation of the empty fixture is needed to detect these signals. Accurate dosimeters for dose rate are not readily available and the integrated total dose delivered in each pulse is usually measured along with the pulse shape. Clearly this method is best suited to package-level testing, and acceptance and qualification tests take a long time. Transient radiation testing at the wafer level can be indirectly simulated using a pulsed laser. A Nd:YAG laser operating at 1.00pm has been used~ to provide the transient energy into the DUT. This is clearty an indirect measurement in comparison with actual tmnsient gamma exposure and uncertainty is introduced by reflections, interconnect shadowing and so on. An alternative approach illuminates the back of the wafer, which is optidly more complex but yields more repeatable results. Screening for these effects is needed in the case of Iatchup and burnout-susceptible parts that cannot be eliminated by device substitution. Methods such as DI or epi construction are well known and prevent Iatchup by either outright elimination of fourIayer effects or by reducing their sensitivity through reduction of the parasitic gains that make up such a device. Latchup testing is performed using either a LINAC or a flash x-ray facility, This method enables screening for Iatchup sensitivity by controlling the amount of total dose radiation delivered to the DUT. As an example, a 20 nanosecond pulse at a rise time of 1010 rads(Si)/second will deposit less than 50 rads(Si) of total dose. A carefully designed test configuration is needed, with biasing and power supplies chosen to reflect a worst-case condition. Quick detection of a Iatchup condition is needed, necessitating fast electronics and low impedance, “stiff power supplies to prevent dropping out of the latch condition by power supply loading. Typically latch current over time, dropout curren~voltage and other latch characteristics are measured. Once latch occurs the measuring setup needs to interrupt power to the DUT unless a burnout test is desired. A basic specifidion
Scsdoc
for transient testing will incJude at least the following parameters:
.
Radiation source to be used
.
Dosimetry standards and methods
●
Dose rate
.
Test tempemture
IV-8
Y1S’9s
●
Test configuration, including functional, test vector and power supply levels
.
Clear definition of upset and Iatchup
Again as in total dose testing acceptance is generally on a lot-by-lot basis. Acceptance testing runs into the same cost problems that we saw in total-dose testing, with increased overall testing cost due to equipment and source constraints.. 1.4.
SEE Testing Single-event effects (SEE) testing has been an inmeasing area of interest as geometies in integrated circuits have shrunk dramatically, bringing greater susceptibility to these effects. Much of this testing is done as scientific research in order to improve our understanding of basic mechanisms, while other tests are performed to qualify pads for specific applications and systems. The study of these effects has been mostly confined to digital technology, although noise and output pulses in analog circuitry have also been studied. “1 Figure 3 shows ‘m sensitivity expressed in linear energy transfer (LET) as a function of speed-power product; as feature sizes shrink and operating currents decrease the SEU sensitivity is seen to increase. Over the range of technologies and minimum feature sizes the critical charge is obsewed to vary as the square of feature size, explaining the greatly increased interest in SEE over the past ten years. The basic mechanisms of SEE are covered in detail in the first section of the Short Course, so we will just provide a basic overview for completeness. The basic SEE mechanism is a higkenergy particle strike on an integrated circuit causing an ionized path through the bulk silicon, The diameter of the ionized path is small and particle transit time is also small; however the ionization along the partide track is intense and the electric field across the depletion layer will actually reach beyond the depletion layer. This effect creates a funnel that is able to collect charge from outside the depletion layer, increasing the total charge that can be deposited on a critical circuit node. At best the change ends upon a noncritical circuit node and has no effect on circuit operation. A single-event upset (SEU) caused by charge exceeding a critical threshold for a given node; this is a “SOW error resulting in a logic state change in digital circuits and noise spikes in analog parts. No permanent damage is incurred, and the system can recover by resetting its processors or reloading correct information into memory. In both ~ses error correction is necessary, and a graceful recovery is possible if the frequency of upsets is low. At higher upset rates operability is impaired, and in the limit the system bemmes useless as the error correcting algorithms are saturated. A second single-event effect is single-event gate rupture (SEGR)P- “31] which is of interest mostly in large power MOSFET devices. Here an energetic heavy ion passes through a thin dielectric resulting in rupture of the dielectric. The high electric fields found in these devices enables the release of energy well in excess of that required to destroy the dielectric. SingI&event bum out (SEB)W-= occurs in power devices, both MOS and bipolar. When an energetic heavy ion passes through one of the many parasitic bipolar devices found in such structures, it can turn these devices on and allow them to enter secondary breakdown. Given suhlcient externally supplied energy the device can be destroyed, often at volta es lower than normal device limits. Single-event Iatchup (SEL) is a closely related 8 ‘w phenomenon in which the parasitic devias actually latch up in a classical four-layer stmcture, again providing potential par&destruction.
SC9MOC
IV-9
WI S’95
100
10
.
0
NMOS
●
+
CMOWBULK Ch40WSOS
■ ● 0
PL GaA9 CMOWBOI
~ A
VHSIC BIPOLAR ECL
1.0 Qc (pc) +
0.1
.
9
.01
.
.W1
100
1
1
10
1.0
.1
FeatureSizel(pM) Figure 3:
sc9s.doc
Critical charge required to cause upset as a function of feature size. After Petersen, et al. [28]
Iv- 10
5/1w
SEE testing is a much more complex and expensive procedure than the comparatively simple total dose procedures. During these tests the DUT has to be in an operating mode and monitoring electronics has to be provided to detect upsets. One method uses external test equipment to exercise the part through its test vectors; upsets are detected by simple pass/fail methods. As an alternative two devices can be exercised in parallel, with one exposed to the SEE environment and a second ‘control’ part located outside the test chamber. Memory testing represents a specialized requirement and is usually performed using repeated write/read cycles, with an alternative approach of loading worst--se test patterns into memory and then checking periodically also in use. As circuit complexity increased the difficulty of these tests leads to greatly increased capital expense and recurring rests. Analo parts do not upset in the digital sense; continuous time analog parts can sho & noise spikes and output saturation. Mixed-signal devices such as A/D converters and signal processors show a more complex response of both analog and digital upsets leading to output errors, and the analysis of the circuit mechanisms responsible for these errors is difficult. In Fig. 4A through 4D we show a representative data plot of error rate in an A/D converte~n, using silicon, chlorine, nickel and bromine ions, respectively, to generate LET ranging from 7,5 to 37. The increased error rate shows up clearly, as do specific codes that are more vulnerable than others; this information is valuable in understanding design issues.
10
I
90-
I
Si
1
m-
70-
eoE : *
LEC
1
7.58
I I 1 I I I 1 I I 1 I I 1 I I I 1 I I
so-
40-
so-
zo-
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, , so
I 1 , 1 , , , m, 1’ 1 1 I I l“’” eso
1250
i 1’ 1 m1 1 1’ 1 m
1
1
1’
1
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I
I
leso
Dlglhl Oulput Cd@
FIGURE 4A: A/D convetir
Sc%.doc
error rata, LET= 7.68. After Turflinaer, et al. [37’J
IV-II
w W95
100
1 1 I
eo”
I L=
1
11.64
I I
L
I
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I
m 1
70
I 1 1 1
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1 1
I
~.
I
40, 2020.
10. 0.
-1
m , , l,,
,
,.+
1
! law Dlgltdoutputcods
Figure 48: A/D converter error rate, LET = 11.64. Atir Turflinaec, et al. [3~
NI
w
LET
26.7
i
lo0
■
so
FIGURE 4C: #D
m
I
eeo
convemr
1220
error
rate,
LET=
26.7. After Turflhmer, et. al. [371
IV-12
Y16/9s
: 1
37.2
LET
t
1
I
m
L&
I’&
2iaa liaa DrglId Olqaut C91k
m
FIGURE 4D: ND convefter error rate, LET= 37.2. After Turflin ~
et al. [371
High energy ions for SEE testing can be derived from a number of sources, including accelerators, radioisotope sources and ion microbeams. A representative accelerator is the twin tandem van de Graaff at Brookhaven National Laboratories. This facility is set up for SEE testing and is available on a time purchase basis. Note that the possibly complex test ftiure and equipment have to be transported to the test site and have to be setup and debugged there, fudher contributing to costs. An accelerator facility of this type provides a variable LET range of energetic ions. Table 3 provides a summafy of typical ions available at this facility.
Table 3: Typical Ions Used for SEP Testing at the Brookhaven Twin Tandem van de Graaff Accelerator pJ
●
scs5doc
AMU
Max Energy (MeV)
LE~ (MeV~m2/mg)
(Pm)
c
12
105
1.39
202
F
19
150
302
133
Si
28
195
7.7
81
cl
!35
210
11.5
63.1
Ni
58
255
27
40.3
Br
79
285
37.3
38.4
Ag
107
53.1
30.9
I
127
230
59.9
30.7
Au
197
345
82.3
27.9
LET and rangedata are calculatedat ionmaximumenergy.
IV-13
5/1m
Note the range of the heavier ions is limited to thirty or so microns; in order to approximate the much higher particle energies found in galactic cosmic rays an accelerator with GeV capabilities is needed. In Table 4 we show ion species available at the AECL facility in Chalk River, Canada. Efforts are also underway to establish SEE test =pability at the Brookhaven Alternating Gradient Synchrotrons. All these sources are clearly expensive, and a simple Iaboratoty source would offer the important advantage of being transportable. Califomium 252 provides such a source; it emits alpha particles at 6 MeV and fission fragments at 79 and 103 MeV. We obsewe an average LET of 43 MeV.cm2/mgm, a useful value for many applications. ‘2Cf is available in disc form and used in a vacuum chamber to reduce air attenuation. There are safety issues in handling this material, and the composite energy spectrum necessitates some analytid correction. m The method is also limited to low threshold LETS and devices with thin ovetiayers due to the mmparatively low energy of the fission fragments, and is thus best suited to SEE evaluation of nonhardened commercial circuits. As a second approach ‘a041]tie use of focused high-energy laser illumination allows control of penetration into the silicon by selecting an appropriate wavelength, usually in the IR. The spot can be reduced to a small size, and the beam can be positioned to hit specific sensitive areas to look at layout effects. Since this is still an optical technique it is limited by interconnect shadowing, and the beam must be used off-interumnect to yield any result at all, Laser intensity can be varied, and the short pulse durations (50 psec) attainable help simulation fidelity. A direct correlation of beam energy to particle LET is diiTcult and the method has been used primarily as a diagnostic tool. The net result of an SEU testing sequence is usually expressed as an SEU crosssection curve. Fig. 5 shows SEU cross-section as a function of LET for a Harris HM 6516 static random-access memory, a typid part for space applications. We note that the cross section saturates at perhaps 5x10-2cm2 corresponding to a LET of 23 MeV.cm2/mg. It drops off steeply below LET= 15, and below this threshold value the part will rarely upset. An excellent reference ‘] by Petersen, et al. reviews the predictive calculations used in interpreting SEU testing and contains useful recommendations for laboratory testing and simulations. The need for actually determining the LET threshold is stressed. The actual space environment has a wide energy distribution, with a 10% chance of an LET = 75 MeV.cm2/mg event and a 3% chance of a corresponding event at LET = 130 MeV.cm2/mg.
sc95.doc
Iv- 14
Y1w
A ?
O- ALICS ❑ -cl A--dun
10
6
16
20
2s W
Figure 6: SEU
cross
section
as a function
ao
(*V
3s
40
4s
so
mg+ 08+ (S0 )
of LET, HM8616 static RAM. Source AEA (UK)
Table 4: Representative Ions Available at the AECL TASSC Facilityp Chalk River, Ontario, Canada ~
SC9MOC
~
Max Enemy (Mev)
LET (MeV~/mg)
MM (w)
c
12
600
0.36
4048
N
15
700
0.49
3475
Si
28
1260
2.11
1487
c1
35
1400
3.4
1053
Cu
63
2200
10.4
592
Ge
72
2160
14
453
Br
79
2200
16.8
393
Ag
107
2550
30
280
I
127
2650
38.7
239
Au
197
2900
77.4
157
u
238
2850
98.1
133
IV-15
91&m
1.5.
ln~rbit
Evaluation
This is where a wefully designed testing program is actually verified. This is an important activity since it validates the entire wmulative result of testing and prediction. The three key objectives of in-orbit evaluation are: .
Verification of semiconductor processes and design methodologies
●
Verification of test and prediction techniques
●
Verification of dosimetry technology
In-orbit evaluation can be implemented by three different approaches: .
Modifications to existing payload hardware and software to enable the acquisition of data as the mission progresses. An example of this method is the ESA UOSAT-2 singl-event upset stud~ in which a portion of the main payload memory was reconfigured to serve as an upset monito~ this was accomplished by software modifications by uplink. Note that no hardware modifications were required for this experiment. As noted in the referenced paper, this wok resulted in improved insight into proton-induced upsets. Fig 6 taken from the Adams paper provides representative data, showing SEU rates for the various memory types flown on the experiment. These upset rates were also correlated to geographical location, providing further data on the environment.
IE-4
+ lE-5
t
I
IF-6 t :
lE-7
Figure 6: SEU rates
Scsk%ia
for
v
t
I
+ t
1
I
t
I
I
I
1
UOSAT-2 Memories. After Adam% et al. [43]
IV- 16
w 6/%
Piggyback experiments on existing missions are the next step up in complexity and cost. These experiments take the form of “black boxes” containing the experimental setup, flown on various missions. These missions range from the US Space Shuttle to various satellites to commercial aircraft. An excellent example is the CREAM payload that has been carried on the Space Shuffle as well as Concorde. The Cosmic Radiation Environment and Activity Monitor is designed to monitor the natural space environment responsible for noise and SEU in electronics and sensors. The instrumentation package has been manually deployed[~ in the Shuttle cargo bay to look at shielding effects. The SEU environment is monitored by a P-i-N diode array; passage of an energetic paiticle creates a pulse, and both frequency and pulse height are recorded. The data enables mapping of high-energy particle flux distribution. An adapted version of CREAM has also been flown on Concorde, and Dyer and coWorkersw’q obtained data on SEU rates at high altitude, due mostly to neutrons and protons, and explored the correlation of these SEU rates to solar flares. We show in Figs 7 and 8 a representative result for both quiet time and solar flare environments, plotting padicle munt as a function of flight time (top) and rigidity (bottom). The vertical cutoff rigidity of a particle is defined as the ratio of the particle’s momentum to its charge and is a measure of the energy needed to penetrate the earth’s magnetic field. The dificulty of adequately simulating the SEU environment has led to numerous onorbit experiments since this is the only really accurate way to assess SEU sensitivity.
Quid-TimB,
CREAM Concwdo 1889, LHR4FK 28th Ss@mbu ‘ml ~ CMxloo
b
18.~
18.S0
, 19.00
,=. 19.s0
20.W
20.80
~ ---------------21.s0 21.00
222.00
Thw (GMT)
Figure 7:
Scsiidm
Patiicle counts and rigidity from CREAM experiment on Concorde, quiet solar period. After -r, et al. [461
IV-17
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GREAM cuwords *
Fhs#241h Octowrwm,
IHR+FK
‘all ~
Ch4xloo
1000 0
2
1 0 -1
-2 18.00
lam
19.W
19.s0
20.s0
20.m
21.W
21.s0
22W
TIIne (GMT)
Particle counts and rigidity from CREAM solar flare. After ~r, et al. [~
experiment
on Concorde,
24 Oct.
1989
The third approach to in-orbit evaluation is the use of an entirely dedicated satellite, Obviously the most expensive way, this provides an opportunity to test a w-de variety of microelectronic components, The US Combined Release and Radiation Effects Satellite (CRRES) is the classical (by now) example of a dedicated satellite. Included in CRRES were dosimetry and temperature sensing facilities to measure conditions at multiple locations within the satellite. The effects of total dose and singl-event effects were monitored on a continuous basis and are transmitted to Eatth via a ground link. CRRES was launched in July 1990 and lasted 1087 otiits to Oct. 1991. It flew a highly elliptical orbit (18.2° inclination; 348 km perigee; 33,582 km apogee) in order to traverse the outer (electron) and inner (proton) van Allen belts, and provide a diverse range of environments. This satellite has produced an enormous amount of data, as you would expect, and we will cover some representative examples. Correlation of ‘Co ground-based total dose testing and the much slower dose rate irradiation actually experienced in space is an important area of research. CRRES enabled the exposure of various discrete and integrated mmponents to total dose radiation with rates varying from .0001 to .048 rads(Si)/second, and ground testing at 8 rads(Si)/sec to 48 rads(Si)/sec was also carried out.[’n Good agreement was shown for MOS power devices and digital parts, and we show in Fig. 9 raw data of
sc95.doc
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Wlws
HEXFET performance vs. orbit number. The change in slope of the wwe is due to changes in the environment caused by increases in the trapped particle population.
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Figure 9:
Gate voltage of discrete HEXFET devices as a function of orbit number, CRRES data. After ~, et al. [471 A second sample of CRRES results involves SEU data. SEU testing on the Microelectronics Package (MEP)[W included forty device types including RAMS, microprocessors, gate array, PROMS and EAROMS. The MEP monitors SEU rates and reports each second on each device. To avoid upsets of the monitoring circui~ two redundant systems including the controller and test circuit~ were used. The data generated by this system was put in context by the environmental mapping systems and dosimeters that were also on the satellite; the environment was continuously measured and quantitative mrrelations are possible. The proton flux and total dose were monitored simultaneously. The results for the (largely nonhardened) tested devices were found to vary widely. SEU’S occurred at between 10 and 20 events per day. Some CMOS RAM devices showed Iiffle or no upsets, while bipolar RAM (93 L422) sensitivity was found to be large, The bipolar results clearly line up with results from a practical in-orbit verification test - the Hubble Telescope. As a representative result Fig 10 shows SEU rate as a function of time for seven static RAM parts, and we note variations in this rate as the environment changes.
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CRRES MEP SEU rate as a function of time, aggregate for seven RAM device-s. After QW!W!!, et al. [48]
As a last example of CRRES data we will cite results by Ray et al.[q on highefficiency solar calls. The High Efficiency Solar Panel (HESP) experiment was designad to determine the radiation sensitivity of GaAs/Ge and Si solar cells. Permutations also included packaging and interconnection methods. Damage to the solar cells was incumed mostiy in the electron and proton belts, and again the detailed dosime~ of these environments enabled direct interpretations. Representatively we show Fig. 11 proton fluenca as a function of orbit number, while Fig. 12 shows mmparative degradation of the maximum per-cell power for GaAs/Ge, thin Si and reference Si cells, also as a function of orbit number.
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Proton Fluence as a function of orbit number for 6.8, 10.7 and 19.4 MeV protons. After ~ et al. [49]
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The use of dedicated satellites for radiation effects investigation has been shown to be an extremely powerful method, which we have illustrated by CRRES data. CRRES data resulted in major new discoveries, incJuding multiple bit upsets caused by protons and the existence of a transient proton belt. It also resulted in change; design review criteria for error handling were improved, ground SEU test procedures were updated and modeling of the near-earth radiation environment was improved. Follow-on to CRRES is cumently planned through the Microelectroni& and Photonics Test Bed (MPTB) program; it is based on the CRRES design and is funded by a wide range of agencies. Strong industry participation is planned as well. The mission will be a 100pound package, to be piggybacked on potential satellites such as GPS, Pegasus and defense comsats, with a preference for an elliptical orbit through all radiation belts to geosynchronous orbit. Planning is for inclusion of advanced high level of integration IC’S as well as photonic components.
1.6.
Special Case:
Cryogenics
1.6.1. Introduction Operation of silicon devices at cryogenic (120K and below) temperatures has been extensively studied in the context of IR sensor applications. The highperformance signal processing, multiplexing and A/D conversion functions required for IRFPA applications place severe demands on the process used to implement these functions. These processes require at least the following attributes: .
Vety high packing density
.
Compatibility with extreme low-power operation
.
Low noise, particularly in the critical l/f regime
.
Compatibility with high reliability requirements
●
●
Freedom from such wear out mechanisms as hot electron degradation and time-dependent dielectric breakdown Adequate radiation hardness
In practice this set of requirements has led to the use of analog CMOS processes in the .6-1.2 micrometer gate length range, with appropriate hardening modifi=tions and thorough m-engineering for cryogenic o eration, and these processes have been well-documented in the literature. W-R521 ~~at has not been so well described are the various aspects of reliability, hardness assurance and qualification procedures. This gap is caused by the profound changes in failure mechanisms that occur when operating temperature drops; indeed new mechanisms will appear that do not even exist at “room” temperature. In this section we will discuss some aspects of device physics and failure mechanisms and will then progress to production and qualification testing. Some of this work is not definitive as yet, and new device issues and failure mechanisms may well appear in the future.
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1.6.2. Failure Mechanisms
and Device Physics
Cryogenic operation puts specific demands on CMOS processes. Device failure mechanisms change as well, and exposure to radiation environments further complicates matters. As temperature decreases the absolute threshold voltage of the MOS transistor will increase and ultimately cause circuit nonfunctionality. The design of an effective cryo CMOS process involves adjusting the thresholds so that lowtemperature operation is optimized. This lowers the room temperature thresholds; a compromise is necessary to keep the part functional for testability reasons, Total dose radiation will also shift threshold voltages; here, the value I VTN- VTP I remains mnstant, and both values shift negative. [n contrast the radiation-induced shift increases I Vm - Vm 1. The deli~te balancing act required to keep all this under control is further complicated by counte~ope freeze out effects that eliminate the use of CD implants as a threshold adjusting technique; dual polysilicon doping is then required. The sensitivity of MOS threshold voltage to total dose irradiation is much worse at lower temperatures. Fig. 13 shows A Vm as a function of stress voltage during irradiation for MOS capacitors irradiated at 77K and room temperature. The shifts at 77K can be seen to be nearly an order of magnitude worse. The effect is due to the large reduction in hole mobility at low temperatures; electron mobility remains high, and positive (hole) charge builds up rapidly. Several complex effects take place after initial irradiation as shown in Fig. 14 with holes initially migrating through the oxide by hopping transpor&;these holes are eventually trapped in deep traps near the Si/SiOz interface. Eventually these holes anneal and the device recovem; the time constant mns in the range of a few hours. The effect of the trapped positive charge is a shift in threshold voltage in the negative direction for both polarities of devices. In the limit, the n-channel device will enter the depletion mode, with the channel turned on at zero gate bias; clearly this will cause circuit nonfunctionality. Two approaches have been used to harden these devices; thinning of the gate oxide and changing the gate oxide to a composite dielectric. Fig. 15 shows the effects of oxide thinning on hardness at 80K, and this method can be seen to work well at this temperature. As opemting temperature drops to the 10K-40K mnge of strong current interest gate oxide thinning loses effectiveness, and a different approach is needed. The use of deoxidized nitrided oxide (ONO) gate dielectricsm’H offers a promising alternative to straight oxide dielectrics. The use of a rapid thermal anneal (RTA) step in a NH3 environment has been shown to produce gate dielectrics of excellent dieledic integrity, enabling thinner films to be used; this improves hardness and density. It is also important to note that hot electron effects in these structures are a major limitation. W’w’5mThe use of ONO dielectrics has been shown to reduce susceptibility to hot electron degmdation; one way of interpreting ONO processing is that it allows much thinner dielectric films to be used while remaining reliable, which in turn improves total dose hardness. The annealing behavior of the ONO films is different from oxide annealing and is an interesting topic that is beyond the scope of this section, Note also that the l/f noise performance of ONO dielectrics may be higher than that of conventional dielectrics.
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Flatband voltage shift as a function of gate bias applied during total dose imadiation for MOS capacitors at temperatures of 26° and 77K. After Pickel.
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A second key failure mechanism is totaldose induced device leakage.
The thick field oxides used in these processes ~nnot be readily hardenedm] and such approaches as composite field oxides have not been successful at cryo. Current processes use the proven earlier method of preventing N-channel field inversion by the use of P+ guard rings. This uses some space but has been shown to be effective in controlling Ieakage.m It should be noted that the low power operation of IRFPA applications is very sensitive to leakage. Devices are
Scsmbc
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routinely operated in the subthreshold region, and radiation-induced leakage quickly grows to the same value as the operating currents. Leakage has also been reported[w between the polysilicon gate and the underlying silicon, i.e. gate oxide leakage. This is not yet well understood, but has been seen on test devices; both normal oxide and ONO dielectrics are affected, and the leakage has no correlation to applied bias. The effect worsens with lower temperature, and has been reported to occur under ‘Co imadiation but ~t under 10 KeV xrays. Returning to hot electron effects we note that the customary approach has been to provide lightly-doped drain (LDD) regions at the source and drain regions. This is an effective method at room temperature and works well down into the cryo range. In a hardened application, however, the tradeoff changes. LDD regions are created by deposited spacer oxides on each side of the polysilicon gate; the spacers modify the source/drain doping profiles by attenuating the S/D implants. In a total dose environment these spacer oxides will trap charge which modulates the resistivity of the comparatively lightly doped LDD structures. The P-channel device thus incurs parasitic resistance in its sources and drains, leading to transconductance degradation as shown in Fig. 16. The N-channel of course experiences a decraase in LDD resistivity, and Fig. 17 shows the resulting major increases in GM. A potential approach is the elimination of the P-channel LDD structures, since this device is much less sensitive to hot electron effects than the N-channel.
1.0 0.0 0.0 0.7 0.6 0.5 0.4 o.a 0.2 0.1 0.0
Figure 16:
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P-channel normalized transconductanca as a function of total dose irradiation at 77K. Harris Corporation data.
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1.6.3. Total Dose Testing Conceptually total dose testing at cryogenic temperature seems straightforward: just reduce the temperature. In practice, this is a difiwlt and occasionally
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dangerous procedure. The standad approach is to use a ‘Co source, usually a Gammacell. In the simplest solution a small DeWar is fabricated with a diameter that enables it to be lowered into the Gammacell column. Clearly this is a limited approach since the Dewar design will need to balance refrigerant capacity against DUT capacity; these small Dewars usually offer perhaps four test positions and sufficient refrigerant to enable 100-200 Krad(Si) total dose testing at Gammacell rates of 150-300 rads(Si)/sec. Such a setup can be expected to maintain DUT temperatures of 80K. The test configuration will need to be simple and of a DC nature, since the neassary long cabling makes any kind of AC work difficult. The cabling is among the many difkult areas introduced by the combined uyo/mdiation environments; few cable dielectrics wn stand up to these environments, and cables as well as connectors have to be monitored and changed frequently. This setup is not suitable for liquid helium cooling, and more elaborate methods are needed to go below 80K. Continuous cooling of the radiation Dewar is a means of extending mdiation exposure time. This requires modified Dewar design and a continuous cooling loop into the Gammacell. The management of such a cooling loop is complex and requires attention to safety issues. There have been instances of explosions in gamma irradiation equipment while using liquid nitrogen for cooling. This is believed to be caused by ozone produced from liquid oxygen present in the refrigemnt, and low oxygen-content nitrogen or helium is required. In all cases the refrigemnt is under pressure, and especially with liquid helium careful attention must be paid to freezeup of other constituents that can dog lines and cause explosions. A well-ventilated workspace is essential for safety reasons.
1.6.4. Transient Testing Using a flash x-my or Iinac source, transient testing at ~o =n be conducted. In this case there is ample space available, as opposed to the 6“ or so diameter of a Gammacell column, and instrumentation and cooling are easier.
1.6.5. SEE Testing SEE testing at cryo is relatively unexplored territory. Since most uyo applications are in imaging systems nondestructive single-event effects are not of major importance. Since SEE testing at -55°C requires active cooling, the methodolog~ll can presumably be extended to oryogenic tempemtures. The referenced methodology uses liquid nitrogen expanded Into the gaseous phase, but straight LNZcoolingof a “coldfinger” is also practical. Complex electrical fixturing and testing requirements will make this very much a “on&at-a-time” test.
1.6.6. Qualification
Issues at CIYO
In the last few sections we have outlined some of the device issues unique to cryogenic applidions and the methods used in chamcterization and radiation testing. We now address actual qualification procedures and hardness assurance, topics that are still in a somewhat formative stage.
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●
Qualification Traditional qual sequences for “room temperature” mil temperature range parts consist of life testing and environmental testing. Life testing for uyo components is complicated by the lack of data on acceleration factors. Room temperature parts are life tested at junction stress temperatures of 1WC - 20@C, and the oven temperature can be determined from device power dissipation and package thermal resistance data. Acceleration factors based on Amhenius modeling can then be applied to derive lifetime at the use temperature. This method runs into problems at cryo; many of these specialized parts have degraded operation at even 25°C and are nonfunctional at much above that temperature. The accelemtion factors for stomge or operating life are not well defined since the low volume of these parts has limited the amount of actual test data. A representative current qualification planw specifies a wide range of environmental and electrical stressing, at both the wafer and package levels. Wafer level stressing is of interest here for potential cost savings and compatibility with QML methods. In Table 5 we show proposed wafer-level testing requirements.
Table 5: WLR Testing Requirements Device Type
stress
hDDB(I
)
Gate Oxide
Stress
‘Total
Conditions
Sample
40K
‘Approx.
Intarievel
273K
Conditions
size 120
1000 hrs
Stress N and PMOS transistor arrays and Iarga area capacitors using a constant voltage#current technique.
150
1000 hrs
Stress Poly/Substrate, Poly/Ml and M2Ml capacitors and meander patterned devices using a Vramp technique,
77K 150K 273K Vramp(2)
Stress
Time to Complete
oxides
Device
NMOS
77K
40
1000 hre
Stress devices w/* 6.5V
Stability(3)
PMOS
298K
40
1000 hrs
@25% <50mV.
‘Hot Electron(4)
NMOS PMOS
40K 77K
60 20
2000 hra 2000 hrs
150K 273K NMOS
77K 273K
30
2000 hrs
Elactromigration
NBS
77K
50
2000 hra
(6)
and metal meander patterns
Snapback(5)
StlipSS
look for Vm shifts
stress NMOS and PMOS
davlcas wtth max substrate current and extract expected lifetime.
Electromigration @ cryo-genie temperatures should not bean issue, however, stress cracks in metalli-zation will be evaluated.
. . .. . . a. Number of umts may Include several types. b. Total time to completion of all device stress and anelysls. c, In addition to monitoring Vth and gm degradation, noise wIII also be maasurd. Source:
Hanis
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Corporation.
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The types of tests listed in Table 5 are standard industry WLR stresses, however, due to the cryogenic temperature range of the process and its required capabilities some of the tests have been changed. The hot electron and TDDB testing are modified from industry standad testing to include DIT and 1/f noise monitoring along with the other typical parameters measured for these types of stresses, At these temperature ranges and with the requirements of the process, it is unknown what parameter will be most critical to cause a device failure. Lifetime predictions for these mechanisms are based on changes of the critical parameter that shows the fastest shift. The following test sequences are included: 1. llme
Dependent Dielectric Breakdown ~DDB) of the thin oxide is characterized with an accept criterion of <1 % cumulative failure in 10 years. Sport mode failures must be consistent with the defect density expectations. After exclusion of the sport mode failures, TDDB must have a single distribution (i.e. no bimodal distribution indicative of two failure mechanisms). Testing is based on JEDEC14.2 specification with an activation energy derived from multiple temperature testing.
2.
Intetlevel oxide testing is used to check leakage at high voltages, (-1OOV at low tempemture) and breakdown by voltage ramping at room temperature on defect structures and capacitors. Breakdown of the interlevel dielectrics will be greater than 3MV/cm. Testing based on JEDEC1 4.2 specification.
3.
Device stability (i.e. threshold shift) is characterized and is required to be +0 millivolts after 500 hours at * 6.5 volts gate bias and 298K.
4.
Hot electron stressing is performed at multiple temperatures to extract the true hot electron resistance at the operating condition of 40K. Failure criterion is < 25% degradation in transconductance within 10 years with a substrate current of 0.1 @/pm. In addition to evaluating hot electron at maximum substrate current, degradation with the device in linear and saturation modes where maximum substrate current does not occur is also evaluated.
5.
Snapback stressing of the minimum devices is performed at multiple temperatures to ensure that Vtinm > V-.
6.
Electromigration stress of the process is not conducted since EM is not a factor in a cryogenic system. A close examination of the metallization, both physically and electrically, is performed to look for any indication of stress voiding due to thermal cycling.
In addition to wafer-level device testing, a product life testis also performed. The requirements for the product test are derived from MIL STD 883 and MIL-I-38535 and include an operating life test, storage life and thermal shock stressing. These tests are performed in packaged parts, and Table 6 outlines the test plan.
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Table 6: Product Stressing Plan Test
Conditions
# Unite’
Duration
Acoeptanoe Criterion
Test Equipment
Operating Lifetest
300K 40K
50 sob
2000 hm 1000hrs
PDA c 5% @ 188 hrs
Boatis required for room temp HTOL cxyostress system unktentified
Storage Lifetest
453K 77K
50 50
2000 hm
No failures due to stress voidi~
High temperature ovens
Thermal Shock
77K to 300K liquidto liquid
25
10 cydesc
No failuresdue to die shear or metal scrub
Use a TIS machine with a DeWar of LN2 on low temp side and H20 at 25C for high temp side
Corrosion Resistance
358K at 85% humidity
25
240 hrs
No visible cmosion
Wafer Level Test in bell jar
Autoctave
121“c w/151W in2pressure, 100% humidity
25
336 hrs
A=Ofor EMA A=2 for parametric
Standard autoclave equipment.
THB
85°C185% humidity
50
1000 hrs
A=l at 1000 hrs A=O for EMA
THB beads requir~ for stress.
a, HTOL will require fully functional devices. Other tests can be conductedwith macro cells or defect density structures. b. Will require suitable test system. c. Stress will be continuedthrough 100 cycles, Source: Harris Corporation In order to perform the operating Iifetest at cryogenic temperature as listed in Table 6, a cryogenic burn-in system must be fabricated. The system must be large enough to hold a large number of units (20 to 100) and capable of maintaining cryogenic temperatures for extended period of time. The interface from the units under stress to a tester should allow the units to be tested in situ. Concerns have been raised about removing the parts after stress, moving them to another system and then testing them for functionality. The concern is that bringing the parts to room temperature before cooling them for functionality testing may affect their performance and stress results. The parts need to be tested after 72 hours and 168 hours to obtain a PDA (Percent Defective Allowed) for infant and manufacturing defect fallout and again at 500 and 1000 hours to look for delta shifts in critical parameters. Storage lifetests are conducted at 77K and 453K to look for problems in metallization or device stability on unbiased parts. The high temperature stress will show any tendencies of stress voiding which can result in electromigration failures in the product during useful life. The cryogenic stress is a check of the stability of the part when held unbiased at low temperature for long period so time. It also acts a control for the operating Iifetest, ensuring that bias is the reason for any failures that occur. Testing of the 453K parts will occur at 166, 500, 1000 hour points. For the 77K
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pans fewer test points are used since the warming of the parts to room temperature may change their characteristics. Testing of the 77K parts will occur at 188 and 1000 hours. Thermal shock testing is conducted using a metal meander pattern. In order to evaluate die shear and silicon stress due to temperature cycling, a die with a large area is required. The shock will be a liquid to liquid test with the low temperature side at 77K and the high temperature side at 298K soak has been removed. In this way a skin of frozen liquid, water or Fluorinertm does not form on the liquid nitrogen side. A commercial thermal shock machine is used with a dewar of liquid nitrogen placed on the cold side and either water of Fluorinertw in the high temperature side. The units are tested after 5, 10, 20, and 100 cycles. An additional concern driven by nonhermetic applications is corrosion. This test is performed on die in open packages, preconditioned by 3-10 cycles from 298K to 77K; the parts are then subjected to a fairly conventional humidity test similar to moisture resistance testing. Both unbiased and DC biased approaches are used, and test times can run as high as 240 hours. .
Hardness Assurance HA testing of cryo pa~ remains a difficult problem. Certainly doing total dose testing at cryo in wafer form is impractical, and actual tests will require packaging. The 10 KeV photons from an Aracor source cannot penetrate cryo Dewars and Dewars designed for use in a ‘Co Gammacell attenuate the gamma mdiation, making accurate dosimetry a necessity. There is also an issue with achieving realistic low dose rates. As mentioned eartier a continuous coolant loop through the radiation facility is needed, but even this method becomes impractical when supporting low dose rates, since ~ogen supply Dewars are of finite capacity. The entire cryo hardness assurana would bean excellent application of a QML-like approach, combining sampling techniques, a good understanding of the mechanisms involved and accurate modeling and simulation during the design phase. Conflation to room temperature irradiation would also be a big advance, but the radid differences in degradation mechanisms makes this unlikely.
2.
Advanced
2.1.
Introduction
Approaches to QML
All testing and qualification methods we have discussed so far are based on extensive, repetitive testing of production parts in order to assure hardness. This overall approach is called the Qualified Parts List (QPL), and uses extensive testing and quality conformance inspections. The testing and QCI steps are expensive, with much of the cost incurred in documentation and traceability. It is also easy to see that actual part cost for supplying samples to mostly destructive tests adds to the expense; nonetheless QPL has been an effective system for many years of production. The advent of higher levels of integmtion has made the QPL approach increasingly impractiel. Base cost of the large sample sizes starts to get prohibitive; the limit of this situation is reached in large ASICS in which total production may be only a few hundred and that many parts again are needed to support the product qualification. The notion
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of qualifying the procedure rather than the product suggests itself pretty quickly. An initiative led by Rome Air Development Center (RADC) and the Defense Electronics Supply Center proposed a Qualified Manufacturers List (QML) methodology for hardness and reliability assuranca for IC’S. The QML flow is documented in militay specification MIL-1-38535Bm and “qualifies the procedure” rather than the product. The older MIL-M-3851O drawing is now part of 38535. The QML flow qualifies a manufacturers entire design and fabrication sequence on a “on-time’ basis; following QML certification all product from the certified facility is considered qualified. Clearly this CWfication is a front-loaded activity that demands substantial investment, as we will see when covering the details of QML. The flow depends heavily on in-process control and statistical process control (SPC) to insure quality, reliability and hardness are built into the product. The next section will cover QML methodology details and we will follow up with applications to RH components.
2.1.1. QML Methodology The baseline QML document is MI L-I-38535A dated 29 Nov. 1991. three phases of QML: .
Facility certification
.
Product qualification
.
Quality Assurance
There are
Figure 18 shows a generic qualification flow diagram. The infrastmcture for establishing facility certification starts with the development of a Quality Management (QM) program. A Technical Review Board (TRB) is first formed; it is responsible for development of the QM plan and for maintenance of certified processes, process change control, reliability data analysis, corrective action and reed procedures and technology qualification status. l%e TRB is responsible for communication between activities such as device design, technology development, wafer fabrication, assembly, test, qualify assurance and outside third parties, as well as with the qualifying activity. The TRB also reviews technology status, including SPC data, QM status, reliability data and failure analysis data, and ties together strategic planning and technology development. The TRB~ contains representatives from all activities, including product line management..
IV-33
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FIGURE 18: Generic QML
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qualification
flow.
Source:
IV-34
MIL-I-38636B,
w m
,.
A key TRB responsibility is the maintenance and approval of the Quality Management plan. As a minimum the QM plan contains the following elements: .
A quality improvement plan defining procedures for continuous improvement.
.
A failure analysis plan including procedures and ccnective action.
●
A statistical Process Control (SPC) plan defining an SPC program within the manufacturing prouss.
.
A change control process covering process documentation.
.
A continuous process evaluation program covering evaluation of the Standard Evaluation Circuit (SEC) and the Technology Characterization Vehicle (TCV).
.
A cetifi~tion
and qualification plan.
MIL-I-38535B covers the requirements for each QM plan line item in great detail, and the reader is directed to that specification for further exploration. Some of the key requirements will be ovemiewed briefly. A baseline index of documents defining QML for a given manufacturer is required; note that QML does not define requirements itself, but rather specifies that an orderly system of controlled documents be in place. This illustrates the basic QML approach of basing procedures on “best commercial practice”. A set of controlled design procedures are also required. These inchde design methods, design reviews, simulations and design assurance methods and mask making, all of which are to be covered in great detail. Models must be verified for functionality, predictability and accuracy. Layout verification has to include design rule checks (DRC), electrical rules check (ERC) including connectivity, and adherence to reliability rules such as electromigrationkurrent density, ESD sensitivity and Iatchup vulnerability. A specifically designed chip for performance verification is required to verify the process capability to perform routing and to predict post-routing performance through simulations. A DesignFor-Test methodology must be demonstrated, including standads for fault coverage for digital and mixed-signal designs. These design-related items result in a fully documented baseline defining the entire design procedure, which is particularly valuable for Iovwolume ASIC applications such as gate arrays since it eliminates product qualification on a circuit-by-circuit basis. Process qualification is performed using the Technology Characterization Vehicle. The design of the TCV is specified by MIL-I-38535 and includes test structures for determining process parameters as well as device parameters for active devices such as MOS and bipolar transistors. A key TCV aspect is the requirement for test structures that enable quick evaluation of specific reliability failure mechanisms. Areas of failure mechanisms indude hot-carrier aging of MOS structures, electromigration of metal interconnects, time-dependent dielectric breakdown (TDDB) in dielectric films, contact resistance and gate contact reliability. A wafer acceptance plan based on MIL-STD-883 Test Method 2018 is required, although alternate approaches are acceptable, For initial certification TCV’S from three fabrication lots are subjected to accelerated aging to enable MITF estimation. As a minimum this TCV evaluation will
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inchde hot wrier stress, electromigration stress, TDDB and contact stability. An ESD characterization of QML products is also specified. SPC control points for the technology are documented in detail. Package and assembly qualification is performed using the SEC; this is specified as a device of at least half of the complexity of the most complex anticipated circuit in the technology being qualified. Again SPC control points are specified, and package designs are evaluated for thermal and electrical properties. Package qualifidion plans are also required, with emphasis on qualification of generic package families. In Table 7 we outline the assembly process qualification, while Table 8 shows package technology characterization. Table Group Number la
lb
Process
Di&attach and interconnect
Di*attach and interconnect
7: Assembly
Process
Qualification
Testing
MIL-STDABS3 test msthod and oondltlon or JEDEC teat method
I,
Thermal shock (100 cycles) End-point elect&als X-Ray or Ultrasonic Visual Ins@Ion
TM 1011, conditionC
] Hermetic
Bond Strength Die shear or Stud pull
TM 2011 TM 2019 or 2027
In-1ine visual inspection In-1ine bond strength In-1ine die sheer or Stud pull
TM 2010 (di-mount and wire bond) [ Plastic TM 2011 ‘ TM 2019 or 2027 TM 2012 Hermetic TM 2002, condltlonB ~ 2007, conditionA TM 2001 TM 1014 TM 1010 critetia, 20X magnification Per device specification TM 2012 (die-mount and wire bond) Plastic TM 2030
Test
Post-moldingX-ray Mechanlcel shock Variable frquency vibration Constant acceleration Fine and gross leak Visual Ins@ion End-point elactrlcel X-ray Ultrasonic inspection
Package
Per device specification TM 2012 or TM 2030 TM 2010 (alla-mount and wire bond) plus die cracks
2a
Dl&attach, interconnect and seal
2b
DiwMach, interconnect and molding
3a
Lid seal
Internal wetar vapor (5000 ppm maximum et 100”C)
TM 1018
Hermetic
3b
Di-attach, interconnect and molding
Temperature cycling (1000 cycles) End-point electrical
TM 1O1O, condition C or JEDECSTD 22, /+104 per device specification
Plastic
4a
Lid seal
Lid torque
TM 2024 (glass seal)
Harmatic
4b
Dia-attach, interconnect and molding
Thermal shock (100 cyclas)
TM 1011, condition C or JEDEC-
Plastic
5a, b
Code markina
Resistance to solvents
TM 2015
6a, b
Final package testing
High temperature storage
TM 1006 10CKlhrsat 150°C
Plastic and Hermetic wlepo~ die attach
7a, b
Post bum-in
Solderability
TM 2003 (245°C + 5“C) or TM 2022 (after worse case rabum)
All
STD 22, A-106, conditionC
I 1
Lead finish
I All
;ource: Ml -1-38535
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Table 8: Package Technology Group
Pr0cea8
Test
Testing
MILSTD483 teat method and
Numbsr la, b
Characterization condltlon
Package
or JEDEC tast method
Dimensions
Physical dimensions
TM 2016
Ail
2a
Resistance to moisture
15 thermal shock 100 temperature cycias Moisture resistance Visual inspection Fine and gross leak
TM TM TM TM TM
Hermetic
2b
Resistance to moisture
Preconditioning Electrical testing temperature humidity bias (1000 hrs, 85”C/85% RH) or biased HAST (50 hrs, 130”C, 85%RH) End-point electrical
See note Per device specification JEDEC 22-B,
JEDEC 22A 112 Paf device specification
1011, condition C 1010, condition C 1004, no bias 1010 and TM 1004 critada 1014
Plastic
101
3a
Susceptibility to corrosion
Satt atmosphere
TM 1009, condition A
Hermetic
3b
Susceptibility to leakage and corrosion
Autoclave (no bias) (pressure pot)
JEDEC 22-B, 102 (data must be provided for 96 hours and
Plastic
4a, b 5b
Leads
168 hours)
2 atm., 121°C Lead integrity Moisture intake
168 hours at 85°C/85% RH or bake + minimum guaranteed time at 30°C/60%
Plastic surface
RH
mount
cracking
Reflow
Vapor
at
Safety Fungus resistance AI,l.-a. mflll I aac9c
Note:
All
Susceptibilityto moisture induced
simulation
reflow soldering
6b 7b
TM 2004, condition~ B2 or D TM 2028 for Pin Grid Array
infrared
phase (21 9“C, no preheat) (240eC
Cross-section
or
maximum at 1000X
or ultrasonic
‘ns-iofl ‘or d~am’flatiofls and cracks
(cSAM)
Flammability Fungus resistance
UL94-V-0, ASTM2863-77 MlL-F-l 3927
Plastic Piastic
The manufacturer shall define a ‘preconditioning=procedurethat simulates board assembly of plastic surface mount devices. As a minimum,this procedureshall indude the moisture intake and reflow simulation requirementsof group 5b In Tabte 6. Exposure to soldering fluxes (possible source of corrosiveness)and to bead deanlng agents is also recommended for premnditionhg the devices. Following the definition of a Quality Management program and initial certification, actual qualification is performed. Qualification testing for a given fabrication process is done on two patl types (“demonstration vehicles~ processed in accordance with the QM. These demonstration vehicles are of representative complexity and are evaluated in accordance with a Qualification Test Plan developed during the certification phase. The Test Plan details materials, construction techniques, testing techniques and reporting formats as outlined in 38535; refer to that document for details. A Qualification Test Report is then issued to the qualifying activity to demonstrate that all process variables are in control and repeatable and that parametric monitor, TCV and SEC data collection is adequate and correlatable to the process a certificate of qualification is then issued after both demonstration vehicles have passed
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qualification. Requalification is as specified in the QM, on a periodic basis set by the manufacturer, and may also be ne@ssitated by line shutdowns, quality problems and QM noncompliance. The above is a general ovewiew of QML methodology. Note that QML moves away from previous Source Control Drawing (SCD) specification of integrated circuits and instead uses the more general Standard Milita~ Drawings (SMD). The SMD method provides a much more economical approach than SCD’S, of which no two seemed to ever be alike. Standard flows now become feasible, especially for back-end processing. Application of QML to hardened parts is fully defined in 38535. Several Radiation Hardness Assurance levels are defined, seel Table 7 below, and qualification to a RHA level consists of either the Class Q or V reliability and quality level plus a neutron fluence of 2x1012n/crn2 and the selected RHA level.
Table 9: Radiation Hardness Assurance
Levels
I
RHA Level
I
Total Dose, md(Si)
I
I
I
I
none
I
I
M
I
3000
I
The Wafer A-ptance Plan also specifies, or rather suggests, test structures that @n be used to determine wafer and wafer lot uniformity and dose rate Iatchup immunity. This area addresses Iatchup, single-event effects, dose rate and total dose; neutron effects are not covered but -n be readily monitored using test transistors. As an alternative, conventional quality conformance inspections such as Group E testing for total dose hardness can be performed. If a technology is cJaimed as hard it must confotm to all RHA requirements for qualification and process monitoring; note, though, that hardness is treated as any other parameter, and that once QML acceptance of the technology is complete the parts are considered ‘hard by design” for the neutron and total dose environment. Fore SEU and transient environments this consideration does not apply and lots must be individually qualified. Additionally, any new part designs must be evaluated to determine radiation toleranm, with a possible (and not likely) waiver if suticient simulation fidelity can be demonstrated. The current approach of verifying hardness through actual testing is expensive, requiring either on-site testing for total dose and possibly SEE and off-site testing for such environments as neutron and transient gamma. Even using the streamlined QML approach these tests are still necessa~. The only promising approach to cost reduction is through such areas as in-line SPC on test structures that have demonstrated mrrelation to radiation hardness[=’q, and design and device modeling techniques that guarantee hardness. Such design techniques would include device models, circuit simulators and design assurance tools. It should be noted that this design infrastructure is expensive
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in itself, and smaller manufacturers may not be able to afford the necessaty UP front investment. Correlation of in-line SPC data to actual radiation results is a diticult issue. An example of a tractable comelation is that between transistor geometries and actual part perfonnancem, although dose rate also plays a part in this comelation. Rebound testing of MOS devices has been used to predict device response at low dose rates with good accuracy; in this method parts are irradiated at Gammacell dose rates of 150-300 rad(Si)/sec and then annealed at perhaps 100”C. The response over this sequence was demonstratedm’m-’o] to provide a reasonable approximation of the low dose rates of natural environments. In bipolar devices dose rate correlations are as yet poorly understood. The use of test devices in bipolar circuits was discussed eariier, with reasonable correlation of neutron hardness to device beta and transition frequency. In general predictability of most radiation response is not good except in narrow applications, and such environments as SEE and transient gamma will continue to depend on actual radiation tests.
2.1.2. SPC Applications The use of statistical process control is nothing really revolutionary; this writer remembers manually plotting Shewhart control charts in the mid-sixties, using process data as input. The real progress in this area has been the use of metrics in the interpretation of such charts-eartier woti used the “eyeball” method and a set of control limits. ReferenceP1] provides an instructive case histo~ for the application of SPC techniques to the prediction of SEE response of a large CMOS SRAM. In this WO*, an initial conflation is established between SEE response and the value of the feedback resistors that protect the memory cell from upset. This of course leads to a fortuitously simple test stmcture, a polysilicon resistor, and if it were not for the large variabilities found in these resistors no RH assurance would likely be needed. In Fig. 19 we show a plot of the critical values for this feedback resistor for a Sandia-made 16K SRAMmIm, and we obseme that a feedback resistor value of 200 Kohms protects to well past an LET of 150 MeV.cm2/mg. We have now established a correlation and are in a position to apply SPC to the resistor test stmcture. In Fig. 20 we show a histogram of a definitive number (8700!) of datapoints of resistor value taken from 60 lots processed at Sandia. The variability of these As-implanted polysilicon resistors is clear, showing a range of 50K to lOOOK against a target value of 400K. We can then format this data into a classid control chart (Fig. 21), sorted on a wafer-by-wafer basis and noting that each reading represents the average of 16 wafer sites. The chart shows calculated upper and lower control limits, with the shift at wafer 155 caused by an implant dose change. This shift in itsetf demonstrates an elementary SPC action since the yield against the 200K lower specification limit was cJearly zero; the question as to why it took 155 wafers to change the dose is probably best left unasked. It then becomes possible to calculate capability indices as a direct metric of process capability. Reference ~1] defines these as follows: Cp is an indicator of the range of the distribution as related to the target value, and Cpk is an indicator of the position of the distribution’s center as related to the target value.
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260 p-mnhl Strlka
16k SRAM
t 200
● ●
g
150
CdhraUOn
E!
a
i!!
------
-----
Slmuiatlon
lW
60
■ 0 I 0
A
I I I I I I I : I I
n-ofakl Stl’lks
I
60
I Im
L~
160
2m
2s0
(MoV-cmWmg)
Figure 19: Value of minum feedback resistor value needed to avoid SEU as a function of LET. Data shown for P- and N- drain strikes; solid lines are simulations. After Wlnokur, et al. pl]
Count
-1-
Soo
0
Figure 20:
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SPC data for feedback resistor value. Wmokur. et al. nl]
IV-40
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. —
CMOS HIA 16 Product Dld’Wafet ., . . ... . . . . .
-.,
... ., . .
..
..
7,.-.:.:,.::,1.,,,...”.:. :“ ,,, [:. ~;+, ,: & USL
. .
700 ●
●
●
m
r
!
,.. .,
,. ,,,
.,
.’:..
,.,
.
..” .:.;...’..,, . .:,”.,.,.’” ,
.
.
.
.
.
.
.
UCL
.
Target
..
::,,,
LSL
‘,. ,...~.
1 LCL
Iw
J
I
I .40
o
1
I
I
80
I
I
120
I 180
1
I 200
I
1 240
1
1
280
1
I
1
I
I
~m ~
Com80uWe Wafem Proc88ad
Figure 21:
Control chati of wafer averages for feedback resistor value. Note limit shift after process change around wafer 1S6. After ~nokur, et al. ~1]
In simple mathematical terms we tie:
CP =
Specification Distribution
range mge
in which the specification range is the upper spec limit minus the lower spec limit (see Fig. 21) and the distribution range contains 6 sigma (99.7%) of the overall distribution. Similarly we tite:
C@= C,(l-K) in which K=
2(T -p) Spedlketion
range
In this last expression T is the target value and p is the mean of the distribution. The target value is of course set by worst-=se dculations; the 200K value we discussed eartier is valid for room temperature and nominal supplies only. There is also an upper boundary to this value, determined by memory write time. For the sample distribution of Figure 21 we calculate CP = 1.67 for the first 130 wafers, indicating good control; the parameter changed to .87 in the second part of the distribution. Note also that the conventional upperflower control limits also widened; in this we recognize that CP is proportional to this range. The Cm pammeter similarty provides a metric of how close the avemge of the
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distribution is to the target value, and we can calculate C@ = .65 and Cm = .75 for the two regimes of Figure 21, respectively. In both pam of Figure 21 we obseme significant scatter, whether this is described by CP or by control limits. Given the complex nature of conduction in polysilicon it is not clear that a much better result can be achieved. A similar exercise for the thin-film NiCr resistors commonly used to limit branch currents under transient gamma conditions would show a CP approaching 1. This indicates the tight distribution of thin-film resistors. Cm would also improve, indicating much better control of absolute value as well. Again in this case CP and C@ have to be based on design &ilculations, taking into account the transient gamma level and the maximum power that an be dissipated in each resistor.
2.1.3.
European Standards The European counterpart to MIL-STD-883D Test Method 1019.4 is the ESA/SCC Basic Specification BS-22900. Both specifications have the intent of providing a conservative assessment of pad hardness in low dose rate environments. Method 1019.4 does this in two steps; it first imadiates the samples at moderate dose rate (50-300 rad(Si)/see) to the specified level to screen for n-channel gate oxide N field oxide charging effects. It then extrapolates this data to low dosevqin which additional (50% of specified dose) imadiation is followed by 1000C under bias anneal for 188 hours. This second procedure screens for Iong-term buildup of interface traps. Note that this method applies specifically to MOS devices, and that extrapolation of moderaterate dose effects in bipolars is still developing. The equivalent ESA specification BS22@ allows imadiation in two dose-rate windows (.01 -.1 rad(Si)/sec and 1-10 rad(Si)/see). 1019.4 and BS22900 both specify a oneweek biased anneal at 1000C, but 22900 also requires a 24-hour room temperature biased anneal prior to the 1000C anneal and the post-anneal testing sequence. BS22900 also provides guidance for evaluation and qualification testing, enabling process characterization to be carried out. In general BS 22900 provides more latitude in testing procedures while Method 1019.4 is a more rigorously defined test procedure. BS 22900 also separates technology evaluation and qualification testing, providin separate procedures for each of these. In Table 10 we show a comparison ml of BS 22900 and MI LSTD-883D Method 1019.4 In the field of singl-event effect testing MIL-STD-883D provides no specific guidance; Method 1032.1 covers package-induced soft error testing procedures, specifically restricted to alpha patticles. ASTM standard ASTM F 1192-20 “Standad Guide for the Measurement of Single Event Phenomena Induced by Heavy Ion Irradiation of Semiconductor Devices” and the JEDEC 13.4 Test Procedure on the same topic are the standard references for US testing. The ESA drawing BS-25100 entitled “Single Event Effects Test Method and Guidelines” is wrrentty in draft format, and provides definitions, equipment and procedures and test planning. It also specifies reporting formats and provides useful listings of facilities both in the US and Europe.
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Table 10: Comparison of ESA/SCC Basic Specification and US MIL-STD-883D, Method 1019.4 Parameter
ESA/SSC *SIC Spew. No. =99
MIL4TD-83D,
No. 22900
Method 1019.4
scope
Test method for steady-state irradiationtesting of ICS and dkcretes duringtechnologyevaluation & qualification/procurementfor spaca applications.
Tesl method for stead-state irradiation testing of packaged semiconductor ICS
Radiation Source
‘Co gammas (ionizing);electron accelerator (ionizing& displacement); alternate sourcespermitted
‘Co gammas (ionizing)
Dosimetry
Intensity* 5%; field uniformity* 1O%
Intensity* 5%; field uniformity* 10%
Pb/Al Container
Minimum 1.5 mm PtdO.7mm Al unless Minimum 1.5 mm Pb/O.7 mm Al unless no demonstrateddose enhancement no demonstrated dose enhancement
Dose
* 1O% of specification
* 10% of specification;an additional 0.5x overtest for “rebound=
Dose Rate
lExIMsuretime <98 h; Window 1, Standard Rate is 1 to 10 rads(Si)/s; Window 2, Low Rate is 0,01 to 0.1 rads(Si)/s; or lower rate if agreed to by partiesto test
50 to 300 rads(Si)/s or at 2 dose Me of intended application if agreed to by parlies to test
Elevated temperature
For 24 h At 100°C for188 h
None “Reboundm: At 100”C * 5°C for 168* 12h
Temperature: Irradiation
20”C *
Test
25°C + 3°C
24°C + 6°C 25°C k 5°C
Bias: During Irradiation &
* 10%; Worst-case damage
t 10%; Worst-case damage
Anneals Between Irradiation & Test
Device leads shorted(e.g., in conductive foam)
Device leads shorted (e.g., in conductive foam)
Test Sequence: Time Between
Begin within 1 h, end within2 h
Begin within 1 h, end within 2 h
Irradiation & Test Time Between
2 h maximum
2 h maximum
Anneals: Room temperature
1CPc
Multiple Inadiations . . .. . . ---source: wmowr, er al. [(ISI
2.2.
Future Trends in Hardness Assurance Testing 2.2.1. Impact of COTS Mandates Acquisition reform has been around for a long time, and DoD has attempted for years to modify a cumbersome press that seems to deliver low value for the
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dollars spent. The Federal Acquisition Streamlining Act (1994) was a first step in the wrrent sequence. An important differentiator from earlier attempts is that both the Congress and the White House are backing this effort. Additionally, the cumbersome procurement process almost rwquired special components be developed for military applications. In 1993 Defense Secretary Perry directed that “perfomnance-based spedfications” be used for all future procurements; the use of military standards is acceptable only when no usable industry specification exists, and waivers are required in this last case. The Perry initiative has broad support. Agreement between the Defense Microcircuit Planning Group and the Semiconductor Industry Association (SIA) Government Procurement Committee was put in place in late November. This agreement uses the QML approach as the performance-based specification, and several manufacturers are currently QML certified. As a part of the DoD planning the use of offshore wafer fabrication facilities and assembly/test facilities was allowed, enabling companies without on-shore facilities to remain competitors in the military market. This is still in the approval cycle at DoD, and will substantially broaden the supplier base for this market. In the balance of this section we will examine various aspects of the commercial off-the-shelf (COTS) initiatives, including a detailed look at QPUQML trad~ffs, a discussion of packaging aspects and an overview of seveml interesting hardness issues. Given the effective elimination of milita~ standards, what documentation will take their place? The Qualified Parts List was developed over many years, starting in the Seventies, and besides specifying parts requirements it also required so-called “baseline” processes, in which the process flow was fued and could not be changed without wstomer approval. This was an effective approach when commercial processes were inadequate for either quality or performance reasons, but required a manufacturer to maintain processes specifically for military applications. An adjunct to this method was the use of controlled assembly and test facilities, enabling the entire fabri~tion flow to be canied out in a antrolled environment. Two issues are bringing this approach to an end. The reduced demand for military parts creates a shrinking market in which fewer manufacturers are able or willing to participate; additionally, the increases in the quality and reliability of commercial components eliminates the need for tight controls. Interestingly, the automotive industry has been a major contributor here; the R&Q requirements for demanding under-tlwhood appli~tions combine with extreme pricing pressures to create a very competitive environment. Automotive parts are basidly equivalent to mil parts ... and they cost orders of magnitude less! What takes the place of the de-emphasized military standards? There are no industry standards; each manufacturer independently controls its specs and data sheets. The services and the Defense Logistics Agency (DIA) are in the planning process at this time, and a key to success will be agreement between these agencies. The very interpretation of COTS applicability is in question, since applications vary widely. A military system opemted in a benign, sheltered environment can easily use COTS parts; harsh environments such as mdiation may not, as we will discuss later. Attempts at using “best commercial pmctkes”for mil procurements have been made for years. With the release of MI L-I-38535 in 1993 the QML flow was
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defined, setting the stage for the use of best pmtices. As we have discussed, QML performs an in-depth certification audit to qualify the manufacturer’s quality system. The emphasis is on product performance, not on control of the way the product is built. A combination of QML and Standard Microcircuit Drawings (SMD’S) will provide the best framework of standards for military procurements. Such a framework is key; it is easy to discard a system of mil specifications in an effort to streamline the procurement process, but a replacement must be provided. A specification system is nothing but a framework defining how business is conducted and eases communication between vendors and manufacturers. Lack of such a framework would lead to chaos as each organization specifies components in its own way. A strong SMD system backed by QML avoids these problems by retaining a centralized system to identify sources for each part. The SMD system also provides a procedure by which users and suppliers can manage changes to the drawings. Change in facilities, redesigns and other changes are governed by QML. The alternative to a QMlfSMD system is the procurement and qualification of commercial off-theshelf parts. This is superficially attractive but represents a backwards step; such parts would need to be qualified individually, leading to a system that resembles the QPL system we are @ing to exit. It is instructive to look at the automotive indus~ approach to parts prowrement Reliability and quality requirements for critical under-the-hood applications often exceed those of military components, and these requirements Combine with strong pricing pressures to create a very competitive environment. Automotive parts are basically equivalent to mil parts ,.. they cost orders of magnitude less! This competitive market has settled on systems that bear dose resemblance to the militaty QML system. A recent example is the Ford/GM/Chrysler standard QS9000; this lSO-9000-based dowment defines fundamental quality system expectations for these manufacturers, and is a combination of their in-house quality system requirements. It is “QML-like” in structure in that it sets guidelines for such areas as quality systems, design control, dowmentation control, process control and product identification and traceability. It is impossible to have much discussion of commercial parts without addressing packaging. Driven by cost constraints and commercial compatibility plastic packages are penetrating mil applications, replacing hermetically sealed ceramic packages. Reliability data from demanding commercial applications (automotive) indicates potentially excellent compatibility with mil applications. For a radiation environment, data has been generated demonstrating no Wckag-related degradation after 200 Krad(Si).m Long-tern storage is also an issue. It should also be noted that the cost benef~ of plastic packaging only kick in at high levels of production; for limited production plastic actually is more expensive due to high tmling costs. Added testing and screening can also reduce cost advantages. The most often cited disadvantage of plastic packages is moisture sensitivity due to their nonhermetic nature. Basic moisture resistance has been improved by better molding compounds. At the chip level the use of CVD silicon nitride passivation has eliminated most of these concerns. Again, the automotive application has driven the technology. Table 11 showsm a mmparison between general industry sampling procedures for military/hermetic vs. automotive/plastic parts. In most cases the automotive requirements are more difficult than the equivalent militaty ones.
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Table 11: Comparison of General Industry Sampling& Qualification for Military Hetmetic Versus Automotive Plastic Microcircuits AUTOMOTIVEPtASTIC
MILITARYHERMETIC (M1l.Std. S83)
DESCRIPTION OF TEST
LTPD
I
#LOTS
Bum-In 100%
PDA = 5%
All
Operating Life
5
1
(Typical)
I DURATION 168 Hours lk
I
LTPD PDA = 0.5-2.0%
#LOTS All
DURATION
I
Houra
48-168
tiolm$
2-3
lor3
1k - 2k
Hours
Not
2-3
lor3
lk - 2k
tiours
lor3
Qualification Not
Biasad Humidity
Spacifled
Qualification
Not
Spsdid
Specified 1k Cycles
Temp Cycle Qualification
15
1
100 cycles
1,5-3
Mechanical Qualification
15
1
—
Not Specified
Not
Not
Specified
Group A Sampling
2
1
All
Specified —
—
All
Note: This chart comDares similar stress conditionswith the exceptionof biased humidity and mechanical. Source: Harris Corporation
The failure mechanisms for plastic packages tend to be different from those found in hermetic packages, Many of the mechanical stress environments affecting hermetic packages, such as impact shock, centrifuge and vibration, are usually not even specified for plastic. Three mechanisms unique to plastic packages warrant detailed discussion:m .
●
Penetration of moisture can lead to corrosion of the Al interconnect under bias. This mechanism can be accelerated by such stresses as temperature/humidity/bias testing. This is an infrequent failure mechanism due to improvements in molding compounds, passivation, mold compound adhesion and Ieadframe design. Some end-use constraints such as the elimination of halides and other highly ionic materials during PC board assembly are also helpful. Cracking of SMD devices can occur during reflow soldering due to stresses created by vaporization of absotbed moisture in the package material. These cracks may cause immediate part failure or (worse) may cause timedependent failure by moisture penetration. Shear stresses can also lift or break bond wires, in particular at die comers. Note that plastic packaging of the greater ductdity of gold. uses gold bond vvires, not aluminum, be-use
This introduces a bimetallic bonding system at the die bond and possibly at the package lead, which in turn places an upper limit on storage temperature due to classicalintermetallicfailure mechanisms. Package cracking is seen mostly on high pin count packages. improved molding compounds.
.
SC9MOC
Corrective
action is centered
around
Shear stresses are also introduced between the surface of the die and the molding compound. Since this is a result of thermal coefficient of expansion mismatches, the problem will be aggravated by large die sizes. Better molding compounds, modified layout rules and die coatings are being explored.
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Opemtion of plastic packages in an ionizing radiation environment will require testing and analysis, since organic materials are used for molding compounds and contact the die surface directly. Degradation in a total dose environment can be caused by degradation of the molding compound or by contamination from the molding compound. Work on simple 54AC02 quad 2-input NOR gatesw shows definite differences between plastic and hermetic devices, with an interesting tie-in into the bumin effects we will cover later. The response of hermetic and plastic devices that had not been burned-in was found to be nearly identical, while burned-in parts showed definite differences. The combination of plastic encapsulation and bum-in was concluded to inhibit the formation of interface states during irradiation, leading to reduced compensation of the oxide trapped charge and hence an increase in threshold shifts and leakage. This leads us into die-related hardness issues for commercial technologies, a topic of obviously increasing interest. These technologies are being rediscovered, in a sense, since basic hardness testing was done years ago on many of them. A good current example is the total dose testing of commercial MSI analog fundions, in which it has been found that hardness is a strong function of dose mte,P1] an effect we discussed earlier. While eatly work on bipolar analog technologies did not unmver these dose rate sensitivities it did point out that the lateral and substrate PNP devices are the weak Point.b The obvious remedy was the replacement of these devices with formal vertical PNP transistors~ which eliminated or at least reduce the surface effects that cause lateral device sensitivity; hardened analog parts have been built for years using this approach. Since such hardened processes require dielectrically isolated material that is expnsive, hardened analog parts are limited in availability and the number of patl types is also limited. The commercial parts that are now being evaluated for hardness also show substantial variability. Beaucour, et alm imadiatect LM137 voltage regulators from four manufacturers at low dose rate of .03 rad(Si)/sec. Figure 22 shows results, plotting the voltage threshold for correct arcuit operation (Von) as a fundlon of dose. The variability is clear, ranging from the Mfg. D patts’ good performance out to 100 Krad(Si) to the Mfg. A parts’ wide range of responses. From a testing and hardness assurance viewpoint these variabilities are a major problem since lot by lot characterization is certainly needed; this “radiation tolerant” approach has been used extensively in qualifying commercial parts for moderate hardness level applications. The approach works well enough but is obviously vulnerable to variability in part response. Note also that none of this fits well into a QML scenario, in which hardness assurance depends on a combination of one-time certification and periodic radiation testing. Phrased in another way, we are finding out that the expensive method of baselining fabrication processes was technically valid. A second interesting effect that has been uncovered in the community’s ma uaintance with commercial technology has been described by Shaneyfelt, % . A linkage between bumin stress and post-stress radiation hardness is et al. shown. Most existing work on temperature effects on MOS device radiation response investigates these effects during and after irradiation. Bias/temperature stress after irradiation has been found[q to not have much effect, while the results of stress during irradiation has major impact on device degradation. Figure 23 shows static Idd for a commercial octal buffer/line driver as a function of total dose for samples irradiated with and without a prelimina~
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150”C bumin. The predefine failure level of 1mA is also shown. Order-ofmagnitude differences in Idd between the two populations are evident. This effect was found in numerous other parts using different MOS technologies, and is atttibutedrn to a decrease in interface trap buildup [Nit] in the prestressed parts, resulting in radiation-induced shift being dominated by oxide trap density [Not]. Since interface trap buildup occurs under mdiation conditions, mdiation qualification of prsbumin pafis may result in an inaccumte representation of the part response in the use condition. The conclusion is that radiation qualifications need to be performed on fully burned-in parts. Note also that as in dose mte dependence them are im Iications for QML, since the QML hardness assurance depends heavil & on statistically-based test structure at the wafer level.
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Conclusion In this Short Course segment we have attempted to overview radiation testing methodologies with emphasis on the profound changes we are now witnessing. The drive for cost reduction in the post-Cold War area has already resulted in a totally different approach to procurement and qualification through QML and SMD’S. Use of best commercial practices is based on tmst and market forces rather than focusing on the process itself. In this new relationship the buyer trusts the supplier to perform, and the seller trusts the buyer to accept the product. The emphasis now is on the end product and not on control of the supplier’s procedures and processes. Contracts, documentation and specifications are kept to a minimum, resulting in major cost reductions, In this scenario the supplier can make design changes at will as long as the specifications are met, speeding up technology insertion and leveraging the rapid pace of commercial technology development. The flip side of all these advantages is technical in nature; commercial technologies are being found to be limited in absolute hardness, which is a problem, and also to be quite variable; a bigger problem. The test structure SPC approach promised by QML will need major efforts to be effective, and until that is accomplished we will be firmly in the radiation testing business. As we have reviewed technical issues 1have supplied reference for further reading, and 1would encourage you to do so. 1acknowledge the major contributions made by Sandia wotiers over the last two decades; a brief scan of references and of the IEEE Transactions on Nuclear Science will illustrate the point.
Scsls.doc
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in Military
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M See
IC’S for Space
[81],
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p. 1068,1991.
‘7 See [85]. m see ~1].
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NSREC ’95
IUAC)ISON
)
Qualification
from the Buyer’s Perspective
Lee Mendoza The Aerospace Corporation P.O. BOX 92957 Los Angeles, CA 90009-2957
This work was supported by the U.S. Air Force through contract numberF04701
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v-2
Qualification from the Buyer’s Perspective Lee Mendoza The Aerospace Corporation Space Based Infrared Systems Program Office 1. INTRODUCTION 2. CHOOSING PARTS TO MEET SYSTEM REQUIREMENTS 2.1 UNDERSTANDING THE SYSTEM REQUIREMENTS 2.1,1Pe~ormance
2.1.2Radiation 2.1.3 Milita~ standar~ 2.2 P ARTS AVAILABILITY 2.2.1RadiationHardenedParts 2.2.2 Radiation TolerantParts 2.3 DETERMINING RADIATION CAPABILITY 2.3.1Manufacturer’sdata 2.3,2 Databases 2.3.3 Testing 2.4 Qualification AppROACHm 2.4.1 QkfL 2.4.2 Monitored line 2.4.3 Do it yourse~ 2.5 RADIATION TESTING 2.5.1Test guidelines
2.5.2 Whocan and shoulddo radiationresting 2.5.3 Whattestingshould bepedormed 2,5.4 Potentinlpitfalls 3. COMMERCIAL DEVICES 3.1 WHAT
ARE COMMERCIAL DEVICES? 3.1. I How hard are they? 3.1.2 What does thefiture hold? 3,2 TRADEOFFS BEmvEEN commercial AND RADIAmON 3.2.1 Performance 3.22 Margins 3.2.3 Variabili~ 3.2.4 Cost 3,3 IMPLEMENTATION USING COMMERCIAL DEVICES 3.3. I Shielding 3.3.2 System approaches
4. FAILURECASEHISTORIES 4.1ANIK-E1 AND -E2 4.2S UPERBIRD 4.3C LEMENTINE 5.CONCLUSIONS 6. ACKNOWLEDGMENTS
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HARDENED
PARTS
1. Introduction The previous sessions have dealt with qualification from the radiation effects and envirornnents point of view, along with some suggested test methods for determining the part response to the radiation environments. The purpose of this final session is to attempt to tie these ideas together from the perspective of the person responsible for implementing a system with radiation hardness requirements. As such, some of the material may be repeated, but hopefully with a new insight. Since my experience is limited to space systems (military systems at that), this session will have a space system perspective. Qualification of microelectronics for use in a radiation environment is an area that is undergoing a great deal of change at the present time. There is pressure on the military to reduce or eliminate the military standards and specifications that have been a primary staple for qualifying radiation hardened electronics. Related to this, there is also significant pressure to utilize commercial off-the-shelf (COTS) electronics instead of special purpose electronics. In the government system acquisition arena, “acquisition streamlining” is now the rule of the day. The emphasis is on high-level performance requirements instead of the traditional low-level “how to” requirements. The approach of writing the intent of military specifications into the request for proposals (RFP) conflicts with this emphasis. The main issues facing a system designer are: what parts are available to meet my requirements; how do I know that the part performance claims (both electrical and radiation) are valid; and how do I know that the parts that I ‘m buying are as good as the parts used by the manufacturer to establish the performance claims. In a strict sense, “qualification” addresses the last question. In practice, qualification must be understood in the context of the first two questions. The key to answering these questions is an understanding of the requirements that the Once the part requirements are identified, a search of system imposes on the parts. manufacturer’s data books and the Defense Electronic Supply Center (DESC) databases will often uncover parts that meet the needs. Assuring that the parts used in the system are really as good as the parts tested can be accomplished by several approaches, from ‘do it yourself’ to ‘have the government do it for you.’ This session will briefly touch on the items mentioned above, starting with the choice of parts to meet system requirements. Commercial devices will be discussed and compared with Finally, a few radiation related failures will be presented and radiation hardened devices. discussed.
2. Choosing parts to meet system requirements Unlike most commercial or even avionics products, the selection of parts available for a radiation hardened application is very limited. The environment that the parts must perform in is often not well understood, while the performance requirements can be very demanding. In many cases, the system designer must forsake the latest technology to obtain parts that will perform in a radiation environment for the life of the system. The first step is to obtain a good understanding of the requirements to be placed on the parts. After this, the list of available parts
v-4
can be examined and the approaches to hardening the system selected. selected, the issue of qualification becomes critical.
2.1
Once the parts have been
Understanding the system requirements
In most cases, customer requirements are levied on the system while the part level requirements are left to the system developer as part of the system engineering process. In space systems, the radiation environment is often indirectly specified in terms of the orbit and mission duration, with military systems sometimes adding a nuclear weapons threat. Once the radiation environment is derived, there are a variety of approaches that can be taken to mitigate the radiation effects. It is the responsibility of the system engineer to allocate these requirements to the different elements of the subsystem: part-level radiation hardness, design techniques, system-level mitigation, and operational concept.
2.1,1 Performance Performance of intrinsically radiation hardened parts is generally below that of unhardened parts. This is due to the process and design limitations imposed by hardening the parts. Isolation techniques used for radiation hardened parts, for example, require more area around non-connected transistors to ensure isolation in a total dose environment. As a result of this, less circuitry can be placed on a die of equivalent size, so the circuits either have reduced functions or are split into several die (resulting in a performance penalty for taking signals off chip). The techniques used for Single Event Upset (SEU) immunity often result in reductions in the electrical performance of circuits. Some of the emerging technologies (notably Silicon On Insulator — SOI) have a much less significant penalty, but these do not have a major market presence yet, The desire to obtain high performance, near state-of-the-art parts is one of the primary drivers for the consideration of commercial or modified commercial parts. Shielding and system-level mitigation techniques can allow some commercial parts to be used in a radiation enviromnent. Little can be done for applications that require the use of intrinsically hardened parts. In these cases, the engineer is required to use whatever is available, or projected to be available when the system is to be constructed,
2.1.2 Radiation Part-level radiation requirements are generally the result of a flow down from very high level requirements such as orbit, mission duration, and nuclear threat (if any). The techniques for converting system-level requirements to part-level requirements are generally well known. Most of these involve computer codes for determining the environment at the spacecraft skin, and then use a different set of computer models for determining the transport of radiation to the subsystem, using either component placement or an assumption about the level of shielding provided by the spacecraft and subsystem boxes.
v-5
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Trarmed
IE+06
Proton Soectra
lE-01 0,1
1
10
100
1000
II
1E+7
II
1E<
Tranoed
Electron
Soectra
1E+6
1E-5 0.01
0.1
1
10
Figure 1. Orbit-integrated proton and electron fluences for Low Earth Orbit (LEO, 846 km x 824 km, 98.7° inclination) and geosynchronous orbit (GEO, 35796 km circular, 0° inclination) calculated using SPACE RADIATIONcode [24].
2,1.2.1
Total Ionizing Dose
Total Ionizing Dose (more commonly referred to as total dose) radiation arises from both natural and weapons sources. The natural sources of total dose radiation are charged particles, primarily protons and electrons. The effects of total dose radiation on electronics vary, but include degradation of parametric performance parameters (e. g., standby current, maximum clock speed) and ultimately functional failure. The degradation results from the cumulative effect of the absorption of large numbers of charged particles or photons. Estimating the total dose radiation that the parts in the spacecraft will be exposed to is a straightforward task. The first step is to determine the satellite orbit. Once the orbit is known, the fluence levels and particle energies for trapped protons and electrons at the spacecraft surface can be calculated, typically using a computer model based on measured data. When this data has been calculated, a dose-depth curve can be determined that will provide the radiation dose transported to the parts through a given depth of shielding. This can be used, with an estimate of the intrinsic shielding provided by the spacecraft structures to determine the part level exposure. The Earth’s magnetic field traps electrons and protons into two torroidal belts, commonly known as the Van Allen Belts [1]. The inner belt is centered at about 3,200 km in altitude, and is populated with high energy ( 10s of MeV) protons and high energy (l–1 OMeV) electrons. The outer belt is centered at about 16,000 km altitude and is composed primarily of high energy electrons. The trapped radiation component of the Earth orbit environment is typically estimated using models developed by NASA’s National Space Science Data Center: the AP -8 [2] model for protons and the AE-8 [3] model for electrons. These models are based on data acquired from many different satellites and provide estimates of the omnidirectional fluxes of protons and electrons as a fimction of the orbital parameters. AP-8 models proton fluxes in the range of 50 keV to 500 MeV, while AE-8 models electron fluxes with energies in the range of 50 keV to 7 MeV. Note that these models do not include the time-dependent variations in the particle V-6
I
1E+05
1E+134
I E+(33
1E+(32
fE+ol
I E+()() n
I
,25
50
75 Equivalent
100 Aluminum
150
200
Shielding
[roils]
Figure 2. Dose-depth curve for a Low Earth Orbit (846 km x 824 km, 98.7° inclination) shield (calculated using SPACE RADLATION [24]).
300
400
assuming a spherical shell
fluxes due to geomagnetic storms or short term solar variations. While these models are static, they attempt to bracket the solar variations by providing two conditions: solar maximum and solar minimum. The models predict a larger proton flux at solar minimum than solar maximum, and the reverse for electrons, The AP-8 and AE-8 models divide the radiation belts into inner and outer zones, with the boundary at 3.8 Earth radii (RE) for protons, and 2.8 k for electrons [4]. The proton inner zone is dominated by protons with energies up to 500 MeV (the limit of the model), The peak flux for the higher energy protons (>30 MeV) occurs at about 1.5 RE. The proton outer zone is characterized by protons with energies below 10 MeV that are effectively shielded by typical spacecraft structures and do not contribute significantly to radiation damage [5]. The inner zone electrons have lower energy (<5 MeV) and flux (about an order of magnitude) than outer zone electrons [4]. The AP -8 and AE-8 models show an inner zone that is dominated by protons and Figure 1 shows the proton and electron fluences an outer zone dominated by electrons. calculated using the NASA models for an orbit in the inner zone (low earth orbit) and an orbit in the outer zone (geosynchronous orbit). In addition to variations with the solar cycle, the electron and proton fluxes are also affected by geomagnetic storms that arise from variations in the solar wind. The inner zones were believed to be largely unaffected by geomagnetic storms, Recent data from the Combined Release and Radiation Effects Satellite (CRRES) and Cosmic Radiation Environment and
v-7
I
1 E+07
E+06
E+05
E+04
,E+03
I E+I32
o
50
100 Equivalent
150
200 Aluminum
250 Shielding
300
350
400
[roils]
Figure 3. Dose-depth curve for a geosynchronous orbit (35796 km circular, 0° inclination) shield (calculated using SPACE RADIATION [24]).
assuming a spherical shell
Activation Monitor (CREAM, carried aboard the space shuttle) has placed some doubt on this belief [6, 7, 8]. They have shown the creation of a new proton belt and enhancement of the electron belts by extreme solar wind conditions. The changes in the belts could lead to a significant underestimation by the AP -8/AE-8 models of the total dose received by satellite electronics during active periods, especially for orbits between 1.8 and 3 RE. Outer zone electrons are known to vary greatly over several orders of magnitude, and electron flux can increase as much as 105 in less than a day during a geomagnetic storm [9, 10]. Exoatmospheric
nuclear detonations will contribute to the total dose in several ways. The burst emits y-rays, X-rays, and neutrons. This radiation pulse affects systems within the line of sight of the burst, and falls off according to an inverse square law with distance from the burst. A plasma bubble created by the burst can leave radioactive debris that will decay, emitting electrons, and can plate on the satellite surface. The high energy electrons created can form an artificial radiation belt within 6 hours of the event [10]. This belt decays with time, but its effects can last for periods ranging from months to years.
AE-8 within model region
The natural space trapped particle environment is usually estimated with the AP-8 and models developed by NASA. As a general rule, the NASA models are thought to be a factor of 2 of the averaged environment [ 10]. Excellent agreement with the proton has been observed for orbits below 1.8 RE and above 3 RE, but it can underestimate the between 1.8 and 3 RE during active solar times [7, 11]. The electron models are thought V-8
overestimate the flux at both the inner and outer zones, but there are times when the electron fluxes significantly exceed the NASA AE-8 solar maximum value. One of the shortcomings of the AE -8 model is the lack of any information for electrons with energies above 7 MeV, Populations of electrons with energies in excess of 30 MeV have been observed following an intense solar particle event at orbits between 2 and 3 RE [ 12]. to
It is important to understand that the radiation environment predicted by the NASA models is an estimate, not a certainty, The proton model seems to give good general agreement with the measured quiet environment, but the active solar environment can add significantly to the inner zone fluxes. The electron environment does not agree well with the model in the short term, due to the large variation in the electron levels due to solar wind interactions. The electron model is also thought to overestimate the dose due to electrons on an averaged basis. A significant flux of electrons with energies above the 7 MeV model cutoff has been observed. This flux will penetrate thin shielding and in the thick shielding case will contribute bremsstrahlung radiation that is essentially unshieldable [6]. Once the external environment has been estimated, an estimate can be made of the intrinsic shielding provided by the structure enclosing the electronics. A dose-depth curve can be used to determine the attenuation of the radiation due to the shielding. Figure 2 and Figure 3 show the dose-depth curves for the LEO and GEO orbits used in calculating the electron and proton fluences in Figure 1, Note that the LEO orbit shows contributions from both protons and electrons, while the GEO orbit contribution is solely from electrons (the low energy protons are effectively shielded out at 25 roils equivalent aluminum). Early in the system design, the configuration of the enclosing structure may not be well enough known to provide an accurate estimate of the shielding. In these cases, a thickness of 100 roils equivalent aluminum (0.69 grn/cm2) is often used, although there is some argument that a value of300 roils (2.06 grn/cm 2, might be more appropriate for modem satellites [13]. If the intrinsic shielding is not enough to reduce the total dose to a level compatible with the selected electronics, additional shielding can be added to the package containing the electronics, or to the box that contains the parts. This will be discussed fiu-ther below. The total dose radiation tolerance of the weakest critical component will be a limiter for the satellite lifetime, in the same sense as station keeping propellant. The radiation tolerance forms a budget that is expended over time as the system is exposed to the radiation environment. The impact of inaccuracies in the total dose estimate can be serious. If the environment is underestimated, the system lifetime will be reduced because the failure level for the most sensitive critical parts will be reached sooner than intended. If the environment is overestimated, more shielding will be used than is actually required, increasing the weight of the subsystem unnecessarily. This could lead to a reduction in the amount of consumables (like propellant), reduced capability, or could prevent the use of parts with a higher level of integration (but increased sensitivity to total dose radiation). Example 1: a satellite in an 846 km x 824 km, 98.7° inclination orbit will have a 2 year mission life. This satellite will be exposed to the integrated proton and electron fluences indicated for the LEO case in Figure 1. The appropriate dose-depth curve for this orbit is shown in Figure 2. If the part has 100 roils of equivalent aluminum shielding (conservative estimate), v-9
then the part will be exposed to 3.0 krad(Si) per year, or a total of 6.0 krad(Si) over the mission life, If the part has 300 roils of equivalent aluminum shielding (moderate estimate), then the part will be exposed to 0.48 krad(Si) per year, or about 1 krad(Si) over the mission life. Example 2: a satellite in a geosynchronous (35,796 km circular, 0° inclination) orbit, with a 10 year mission life. This satellite will be exposed to the integrated proton and electron fluences indicated for the GEO case in Figure 1. The appropriate dose-depth curve for this case is shown in Figure 3. For 100 roils of shielding, the exposure will be about 95 krad(Si) per year, or nearly 1 Mrad(Si) for the life of the satellite. For 300 roils shielding, the exposure will be about 1.6 krad(Si) per year, or 16 krad(Si) for the satellite life.
2.1.2.2
Single Event Eflects
Unlike total dose effects, Single Event Effects (SEE) are the result of a single particle passing through a sensitive volume in an electronic circuit. Although many particles may pass through a circuit (contributing to the total dose exposure), most do not pass through regions that can cause disruption of the circuit operation or do not deposit enough energy to disrupt normal operation. SEE is a localized effect, typically affecting only a small portion of the circuit. There are two principle effects that will be discussed here: Single Event Upset (SEU) and Single Event Latchup (SEL). There are other effects in the SEE umbrella, such as Single Event Burnout and Single Event Gate Rupture in power transistors, but these will not be discussed in this session. SEE are primarily natural phenomena. Trapped protons, solar energetic particles, and galactic cosmic rays (including high energy heavy ions) are the principle contributors to SEE [14], The trapped proton environment can be modeled using the NASA AP-8 model described While shielding can prove effective against above, and is subject to the same uncertainties. lower energy protons, high energy protons and galactic cosmic rays cannot be effectively shielded, Galactic cosmic rays are modulated by the solar wind, and partially shielded by the Earth’s magnetic field. The galactic cosmic ray flux is largest at solar minimum, and smallest at solar maximum due to more effective scattering when the sun is active [14]. Adams has developed a Linear Energy Transfer (LET) spectrum based on historical solar cycle (galactic cosmic ray contribution) and flare (interplanetary cosmic rays) data that is exceeded only about 10VOof the time [15]. This spectrum is referred to as tie Adams’ 10’XOworst-case environment, and is used as a standard environment for error rate calculations and comparisons. Solar flares can be a very significant contributor to the SEU rate. The Adams’ 10% worst-case spectrum will be exceeded during major solar flares that occur about once every six months during the solar maximum [5]. About once every solar cycle (approximately 11 years) an “anomalously large” solar flare can be expected. These large flares have fluxes that are about 5 orders of magnitude larger than the Adams’ 10% worst-case environment. Particles from the solar flare will reach the Earth within minutes of the event, reach a peak intensity within a few hours, and decay within 1 to 5 days [16]. Figure 4 shows the approximate proton spectra for typical, a 10% worst-case, and an anomalously large solar flare.
v-lo
12 11 10
C6 o 35 :4 =3 2 1
0 o
100
200 Proton
.“lgure 4. Solar tlarespectra
tortyplcal,
400
300 Energy
500
(MeV)
. .... lW!Aworst-case, andanomalouslyl
argesolart
lares[ After
16],
Solar flares are sporadic events. Equation (1) expresses the probability of having n solar flares during a period of t years, where N solar flares have occurred in T years [16], (1)
The values of N and T will vary for the type of solar flare (ordinary or anomalously large) and the period of solar activity. For solar minimum conditions N = 6 and T = 8;for solar maximum conditions N = 24 and T = 7. For an anomalously large solar flare N = 1 and T = 7. Plots of solar flare probabilities for solar minimum, solar maximum, and anomalously large solar flares can be found in Figure 5, Figure 6, and Figure 7, respectively. The Earth’s magnetic field deflects particles with energies below a certain value called the geomagnetic cutoff [ 16]. The geomagnetic cutoff is specified in terms of a minimum momentum divided by particle charge, usually in units of Giga Volts, called the cutoff rigidity. The cutoff rigidity is a function of the radial distance from the Earth and the latitude, and drops to near zero for magnetic latitudes above 65°, At high altitudes the shielding effect is negligible, while at low altitudes the cutoff can be as high as 10 GV for equatorial orbits. The Earth’s magnetic field intensity is reduced in a region above the Atlantic ocean, off the coast of southern Brazil and Argentina, possibly due to a large deposit of magnetically conductive ores [ 17]. The reduction in the field over this region causes an increase in the V-n
10
Years
Figure 5. Probability of solar flares during solar minimum conditions [After 16].
charged particle flux called the South Atlantic Anomaly (SAA), The proton flux with energies over 30 MeV is up to four orders of magnitude greater than at the same altitude over other regions of the Earth [5]. Many satellites experience increased SEE rates as they pass through the SAA. SEU occurs when the internal state of a circuit is altered due to the collected charge from SEU sensitivity is a charged particle passing through a sensitive volume in the circuit. characterized in terms of a saturated cross section and a threshold LET to upset the internal state of the circuit. Note that an SEU does not always result in an externally observable error. An example would be a bit flip in a microprocessor register that is subsequently written over. In this case, the internal state of the register has been altered, but a new value was written over the changed value so the SEU was not observed. SEU is typically measured for storage devices like memories or latches. The main reason for this is that the SEU usually results in an easily observable external error, and memories and latches are regular arrays of similar cells so it is easy to assign a “per bit” error rate. Combinational logic and analog circuits are also subject to SEU errors, but these may not be easy to detect even when they are externally observable. Functional upsets have been observed in several blocks of a Texas Instruments TMS320-C25 Digital Signal Processor (DSP) on the Meteosat -3 Radiation Effects Experiment [11]. Over a two year period 18 upsets were observed on the DSP; 5 occurred during solar flare conditions.
V-12
‘eers
Figore 6, Probability of solar flares for solar maximum conditions [After 16].
The impact of SEU ranges from correctable errors in RAM to loss of the spacecraft. At the least serious, SEU is either not observed or an annoyance. In memory elements it is possible to use Error Detection and Correction (EDAC) codes that are capable of detecting a single bit error and correcting the flipped bit. In these cases an SEU would be an inconvenience unless there was more than one error in the EDAC protected word (a word here is a group of related bits of fixed size), While most upsets observed usually involve a single bit, multiple bit upsets have been observed in ground testing [18]. Multiple bit upsets could result in uncorrectable errors even when EDAC is used. In extreme cases, the bit flip could affect a microprocessor register, causing an error in the execution of a computer program that might eventually lead to loss of the spacecraft. SEL is a potentially destructive phenomenon that can be induced by passage of a charged particle through a sensitive volume in the electronics. The charged particle can excite a parasitic n-p-n-p (or p-n-p-n) structure leading to a large current flow between power supply rails [ 19]. If not interrupted, this current can lead to melting or electromigration of the material in the current path, This current will persist until power is removed from the circuit, Like SEU, SEL susceptibility can be characterized by a LET and a sensitive area for each circuit. SEL is usually characterized by a large increase in the supply current to the circuit. It is possible to use current monitoring techniques to detect that SEL has occurred and then shut down the affected circuit before it is damaged. Note that SEL does not always cause a large increase in supply current, thus this technique will not be effective in all cases.] SEL can reach destructive levels within
V-13
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0,7
1 0.6
0,5 2 h 0.4 ,= = n : 0 L L
3 0.3
4 0,2 5 0,1
0 1
2
3
4
5
6
7
8
9
10
Years
Figure 7. Probability of anomalously
hundreds of microseconds [20].
large solar flares [After 16].
from onset, so shutdown of power to the device must occur quickly
Another approach often used to eliminate SEL is to process the integrated circuits on an epitaxial layer grown over the bulk silicon. This technique is popular because it does not require a major alteration in the manufacturer’s normal wafer processing flow. Unfortunately, experimental evidence has shown that building CMOS integrated circuits on an epitaxial layer does not always insure against latch up [21]. Recent data indicates single event induced hard errors in SRAMS and DRAMs [30, 22]. One mechanism thought to be responsible for these hard errors is localized total dose resulting from a single event strike. Another suggested mechanism for the hard errors observed in the DRAM is a rupture of the gate dielectric (similar to SEGR, except at lower voltages), but there is also some data that would counter this suggestion. Unlike total dose failure levels, SEE rates cannot be directly measured. What is measured is the upset or latchup cross section and the threshold LET. Using these measured quantities and an estimate of the expected environment, one can infer the SEE rate using computer models like CREME [23] or SPACERAD [24]. While the Adams’ 10°/0 worst-case environment is often used to determine the expected SEE rates, this spectrum is considered by some to be too conservative and the solar minimum spectrum is recommended to provide a more reasonable error rate [25]. V-14
In determining the requirement for SEE the operational requirements of the system (or subsystem) must be taken into account. In some systems it would be acceptable for the system to suffer a brief outage during a major solar flare event. System outage would be about 2°/0 of the time [16]. In these cases, designing to the average environment as specified by the solar minimum or more conservative Adams’ 10°/0 worst-case spectrum will be sufficient. Other systems may be required to operate through solar flares. For these systems the SEE performance of the parts must be such that they do not upset or latch for the peak flux from a worst-case solar flare spectrum, or an anomalously large solar flare.
2.1.2.3 Dose Rate Effects The radiation pulse directly from the burst of a nuclear weapon can deposit a large amount of energy into the circuit in a very short time. This can result in very large currents that are distributed across the entire device. As with SEE, high dose rate exposure can cause upset or even destruction of the circuit. In this case, however, upsets will occur across the entire chip rather than a single bit or small group of bits. Dose rate requirements are generally expressed in terms of an operate through component and a survival component; with the operate through level being several orders of magnitude less than the survival level. Upset levels are usually specified for two conditions: static and dynamic. Static upset applies to storage devices, and covers the retention of data after the radiation pulse. Dynamic upset refers to the ability of the device to operate in an active state (e.g., maintain a logic ‘1‘ at an output during the pulse). Sensitivity to dose rate effects is a combination of both the integrated circuit process and design (primarily power grid layout). One technique that is used to improve the dose rate response of an electronic system is called circumvention and recovery. Parts that are subject to dose rate burnout can be protected by removing power when a nuclear event is detected and keeping the power down until the fluence levels drop. An electronic system can be protected from the massive upsets experienced during a nuclear pulse by disabling the electronics until after the pulse passes by suppressing the system clocks or enable lines. This approach protects the contents of ‘hard memory’ (memory that will not be upset by the pulse), allowing the system to recover using information stored in hard memory.
dose hard need dose
Circumvention and recovery techniques allow the use of parts that have a relatively low rate upset threshold, since the devices will be reset during the recovery phase. Note that the memory must be immune to upset from higher levels than the rest of the parts, but they only to be hard in the static sense. Usually a variety of techniques are used to meet system level rate hardness requirements.
2.1.3 Military standards The application of military standards to government procurements has received a lot of attention recently. A directive by Secretary of Defense William Perry to eliminate military standards from some current and future procurements has created much confusion. This directive does not mean that no standards will be applied, but that “best industry practices” will be favored over military standards where they exist. This directive is part of the government move toward streamlined acquisitions in which the contractors will be required to take a great V-15
deal more responsibility fortheproducts phrase “Insight, not oversight.”
they produce.
This newphilosophy
iscaptured
by the
An example of the impact of this new philosophy can be seen in a comparison of the Space Based InfraRed Systems (SBIRS) and the Follow-on Early Warning System (FEWS) Request For Proposals (RFP) package. These RFPs called for the design and fabrication of space based infrared missile warning satellites and related ground systems. These systems are intended to replace the existing missile warning system, called the Defense Support Program (DSP). FEWS was canceled in February 1994, in the middle of the Demonstration and Validation (Dem/Val) phase. At the time of cancellation, a preliminary RFP had been drafted for the Engineering and Manufacturing Development (EMD, formerly called Full Scale Development) phase. The FEWS EMD RFP had about 70 “compliance documents;” many of these were military standards. In contrast to this, the SBIRS Pre -EMD RFP has 3 compliance documents; none of which directly apply to radiation hardened microelectronics. The compliance documents for the SBIRS EMD phase will be determined by the contractors during the Pre-EMD contract. Military standards have developed as a response to problems observed in past military procurement activities. While it can be argued that some of the military standards perpe~ate costly and largely obsolete processes, other military standards are as valid as the day they were written. Military standards should be viewed as a resource. They have captured a body of knowledge that is directly related to problems observed during the development and fielding of complex systems, including a large number that require the use of radiation hardened microelectronics. Indeed, in some cases the best commercial practices are military standards, sometimes with “tailoring” to customize them to the specific application. The phrase ‘military standard’ here includes military standards, specifications, and handbooks. It is convenient for this discussion to divide military standards into four general categories: requirements, management, qualification, and testing. Requirements standards are generally applied at the system or subsystem level, and contain the “shall” phrases. Management documents typically discuss boards, reviews, and other management structures. Qualification documents address the testing and certification needed for components of the system. Finally, test documents cover the proper methods to use for testing. These documents will typically reference other documents, usually of other types. A requirement document might call out for the establishment of a control board, established in accordance with the requirements set out in a management document. Qualification documents typically reference test documents.
2.1.3.1 Requirements There are no generic requirements documents that are specific to radiation hardened microelectronics. Most of the requirements for the microelectronic parts will be derived (that is, determined by applying engineering principles to flow the part level requirements down from the direct requirements). There are some requirements documents that address radiation hardened components as part of their scope. An example would be MIL -STD -1547, “Electronic Parts, Materials, and Processes for Space and Launch Vehicles.” This document establishes minimum technical requirements for a variety of items, ranging from discrete parts (capacitors, resistors, diodes, etc.) to microcircuits to boards. V-16
Radiation hardness assurance requirements are MIL-STD -1547. This document describes a set of radiation relative hardness of the parts as compared to the radiation document introduces the concept of a radiation design margin for parts that exhibit a log-normal failure distribution.
described in Appendix A of hardness categories based on the specification for the part. This (RDM) that is defined in Eq. (2)
R RDA4 = ~ R SPEC
(2)
R~, = exp[ln(R~~,~)]
(3)
In(RF.IL) = ~~ln(RF,UL, ) n i=l
(4)
where
and
R~AI~iis the failure level for the ith sample in the test group [26]. A part type will have a separate RDM for each radiation environment (e.g., total dose, SEE, dose rate, neutrons). Two basic hardness categories have been defined, Category lM for marginal parts and Catego~ 2 for hardness critical. Parts in Category lM require acceptance tests and/or electrical screens on each production lot of parts. Parts in Category 2 do not require lot acceptance tests but may require occasional sample testing due to possible changes in design or fabrication that could adversely affect the part hardness. As with the RDM, the part categorization is by radiation environment. There are two methods for categorizing parts, a simple method that uses a breakpoint of 10 for the RDM, and a statistical method that uses the standard deviation of the log of failure levels and a one-sided tolerance limit based on sample size, confidence level, and survival probability. In many cases, not enough parts are tested to use a rigorous statistical method. In the breakpoint method, parts with an RDM between 2 and 10 are designated as Category 1M, parts with RDM greater than 10 are Category 2. This standard requires at a minimum that RDM = 3 for total dose and RDM = 2 for other environments.
2.1.3.2 Management There are several management documents that pertain, at least indirectly, to radiation hardened components. From a qualification point of view, the Parts, Materials, and Processes (PMP) documents are the most important. For space systems, MIL -STD-1546, “Parts, Materials, and Proc~sses Control Program for Space and Launch Vehicles” outlines a program to manage the selection, application, and control of parts. This document establishes a “space quality baseline” that was developed by a team of government and industry experts to address problems observed on previous space systems and to capture the methods used by successfid systems in providing high reliability parts. Appendix B of this document describes the requirements for establishing a radiation hardness assurance program. It describes a radiation hardness assurance program plan, documentation of hardness assurance design information, and contractor responsibilities for radiation hardness assurance.
V-17
While not strictly a management document, MIL-HDBK- 179, “Microcircuit Application Handbook” provides much good information about quality systems (see also Section 2.1.3.3), parts selection guidelines, DoD procurement procedures, application practices, and system guidance. The handbook discusses military and industrial quality systems in terms of the advantages and disadvantages, cost considerations, and applicability. Revision A of this handbook (currently in process) will significantly expand the material on radiation hardness. The handbook provides guidance on the additional effort required to assure radiation hardness. As a general guide, the handbook recommends that parts be selected that provide a known and controlled level of radiation hardness (see Section 2,4), When this is impractical, the use of screening and lot sample testing is recommended to assure that the radiation hardness of the selected parts has not degraded since the tests to establish their radiation tolerance.
2.1.3.3
Qualification
The qualification documents discuss the requirements for certi~ing either parts or For manufacturing processes for reliability and, in some cases, radiation hardness. microelectronics the most important documents are MIL-M-385 10, “General Specification for Microcircuits,” and MIL-I-3 8535, “General Specification for Lnteg-rated Circuits (Microcircuits) These documents describe two quality systems that were developed by the Manufacturing.” military in response to problems observed (high defect rates and unreliable performance) in systems using integrated circuits and to changes in the way the integrated circuit manufacture is controlled. Suppliers that conform to the requirements in these documents can list their parts or processes on a government-endorsed list of products. These government lists are commonly referred to as the Qualified Parts List (QPL) for MIL-M-385 10 and the Qualified Manufacturers List (QML) for MIL-I-3 8535. As the name suggests, QPL deals with the requirements of certi~ing individual parts. QML, on the other han~ certifies a manufacturer’s process flow (from orders in to parts shipped out), with the The basic result that any part produced according to that flow is considered qualified. philosophy of QPL was to strictly control the manufacture of the parts, requiring that the The original manufacturer obtain approval from the customer of major process changes. emphasis of QPL was on end-of-line (post-manufacture) screening of parts, but recent changes have recognized the value of in-line (during manufacture) Statistical Process Controls (SPC). QML allows the manufacturer to change his process, but emphasizes the importance of controlling the process by which those changes happen. QML emphasizes in-line controls over end-of-line, but retains much of the screening from QPL, QML covers the entire process flow, from the receipt of orders (“Conversion of Customer Requirements”) to the way the parts are shipped to the customer. This recognizes the importance of all aspects of the manufacture of the part on the reliability and radiation response. A key part of the review is the design system. Manufacturers that will be qualified as radiation hardened are required to show how the design and simulation tools address radiation. Qualification is a two step process for both of these quality systems. In each there is a certification followed by qualification. Certification is where a government team, selected by the Defense Electronic Supply Center (DESC), examines and approves the manufacturer’s quality V-18
assurance program. After receiving certification from DESC, the manufacturer builds parts, subjects them to the testing specified in the quality assurance program, and submits the data to DESC for review. The purpose of qualification is to verify that the manufacturer complied with the quality assurance program and demonstrates that the program is capable of producing devices that meet the reliability and radiation hardness levels specified by the manufacturer. QPL provides for two levels of quality: Class B and Class S. Class B parts are targeted to tactical military systems. Class S parts are targeted to strategic military systems and space systems. The requirements for Class S are more stringent than for Class B, and the manufacturing flow could be different between the two classes, QML provides a single level of quality, but does allow for the addition of’’’value-added” screens for space systems. Appendix B of MIL-I-38535 B contains additional requirements on the screening of parts for space application. Parts that conform to the requirements of Appendix B receive a “V” part number, rather than a “Q” part number to indicate the extra testing. Other than the added screens, there is no difference in the design, fabrication, or assembly between Q and V parts. MIL-M-38510 has been withdrawn as a standard in favor ofMIL-I-38535B. Many of the manufacturers that were certified under QPL have received “transitional certifications” under the QML program. The transitional certifications provide time for the manufacturers to make any changes necessary to meet the requirements of QML without losing their certified status. Parts on the QPL have been moved to the QML. MIL-I-38535B incorporates radiation hardness requirements as part of the main body of the standard, in recognition of the pervasiveness of processes that affect radiation hardness. QML uses the concept of a Radiation Hardness Assured Capability Limit (RHACL) to describe the radiation tolerance of parts that are produced in accordance with a qualified process flow. The RHACL is, in effect, a guarantee by the part manufacturer of the level of radiation tolerance.
2.1.3.4
Testing
The testing documents are generally “how to” books. They typically and provide guidelines for when and how testing should be performed.
detail test methods
The best known of these documents is MIL-STD-883, “Test Methods and Procedures The purpose of MIL-STD-883 is to provide a single standard that for Microelectronics.” contains test methods used by the military and NASA for microelectronics. This document contains test methods for environmental, mechanical, and electrical tests along with a set of test procedures. The latest revision of this standard, MIL-STD-883D, dated 15 November 1991, contains four test methods for radiation effects: neutrons (Test Method 1017.2), total ionizing dose (Test Method 1019.4), dose rate induced latchup (Test Method 1020.1), and dose rate upset (Test Method 102 1.2). It is interesting that there are no test methods in MIL-STD-883 for Single Event Effects (Single Event Latchup and Single Event Upset). mote that there is an ASTM standard for SEE testing, ASTM 1192.] Each of these test methods describes the radiation source(s) to be used, the dosimehy equipment that should be used to measure the radiation exposure, the test procedure, the test report, and a summary of the information that is to be specified in the acquisition document, The MIL-STD-883 test methods are revised as new
V-19
Technology
Manufacturer
Products
ABB Haffo
1,25 Lm CMOS/SOS
Memory (SRAM) ASICS (gate array)
Analog Devices
2.0 ~
Analog-to-Digital Digital-to-Analog
Harris
2.0 ~ Bipolar 2.0 pm CMOS bulk and SOI
Honeywell
BiCMOS
Linear
status Active. CMOS/SOS designs from Harris wil[ be transferred here. Active. Transitional QML/Q qualification (non-RHACL). Active. Transitional
MS1/LSIComponents QML/Qqualification (non-RHACL)for MSI/LSIPaltS.
1.2pm GMOSand CMOS/SOI 0.8 pm CMOSand CMOS/SOI
Active. Full QML/Q/V qualificationwith RHACL.
1,0pm CMOS
Microprocessors Memory(SRAM) Non-VolatileMemory ASICS(gatearray) Microprocessors
0,8 ym CMOS 0,5 pm CMOS
Memory (SRAM) ASICS
Plessey ~
Bipolar Linear CMOS 1.5 pm CMOWSOS m ;“ f—.~
MSULSI Components Memory ASICS (gate array) Microprocessors
U’rMc
1.2 ~m CMOS
qualification with RHACL. Inactive in radiation hardened market. Active. Transitional QML/Q/V qualification with RHACL. Active. Inactive in radiation hardened market. Active. Transitional QML/Q qualification, full QML certification is pending [review held). Active.
Loral (formerlyIBM)
~ National Semiconductor
Active. Full QML/QN
Microprocessors Memory (SRAM) ASICS (gate array) Bus Controllers 1.2 ~m CMOS and CMOS/SOS Westinghouse Microprocessors Non-Volatile Memory ASICS . — . ..— . . ‘~able 1. Radiation hardened part supphers. Products no longer available are indicated in ~
font.
mechanisms are achieved. The decimal number following each of the test methods indicates the revision number. Each of the radiation test methods has been revised at least once. The latest revision modified all the radiation test methods, except the neutron radiation test.
2.2 Parts availability Radiation hardened parts are available from a very limited number of suppliers, and the part selection is not as rich as the commercial parts market. For this discussion, radiation hardened refers to parts with intrinsic total dose tolerance of 300 krad(Si). A number of manufacturers have parts that will remain in specification for total dose in the range of 10 – 300 krad(Si); these will be referred to as radiation tolerant. Parts with total dose tolerance below 10 krad(Si) will be considered as radiation soft.
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2.2.1 Radiation Hardened Parts Radiation hardened parts are available from several manufacturers, but the number of manufacturers has been declining over the past few years. Many of these parts were developed to address the requirements of militmy systems, in particular the U.S, Strategic Defense Initiative (SDI). The Strategic Defense Initiative Organization (SDIO, now the Ballistic Missile Defense Organization) established a technology development program that produced radiation hardened versions of the key building blocks for a space borne sensor system: analog-to-digital converters, microprocessors, memory devices (both volatile and non-volatile), and Application Specific Integrated Circuits (ASICS). These circuits typically have total dose tolerance in excess of 1 Mrad(Si), are immune from SEL, and possess dose rate effects hardening features. As the mission of SDIO changed, fimding for this technology area was reduced. Other organizations have helped to continue the efforts started by SDIO. Table 1 contains a list of radiation hardened electronics manufacturers, their process technologies, and a list of products. The key building blocks mentioned above are still available from several manufacturers. The level of technology for radiation hardened parts available today can be characterized by: 12 bit analog-to-digital converters, 16 bit microprocessors, 256K SRAM, 64K EEPROM, and gate arrays with over 200K usable gates. All the currently active radiation hardened part manufacturers monitor and control the fabrication processes that affect radiation hardness, limiting the variability of the radiation response between manufacturing lots, There are several technology programs that are continuing the development of radiation hardened parts, Honeywell and Loral have recently demonstrated fully functional lM SRAM devices. Honeywell, Loral, and TRW (with fabrication at UTMC) are completing the development of 32 bit RISC (Reduced Instruction Set Computer) microprocessors.
2.2.2 Radiation Tolerant Parts Some manufacturers have processes that demonstrate some limited total dose radiation hardness. These parts are not designed with radiation hardness in mind, and may be subject to variability in their radiation response since the process steps that affect hardness may not be controlled. Another item to note is that total dose tolerance does not provide any indication of SEL susceptibility. In general, the use of parts that are susceptible to SEL should be avoided unless effective detection and power shut down circuitry is available. For information on radiation tolerant parts, browse recent volumes of the IEEE Transactions on Nuclear Science. Test results for a number of commercial parts are often published. A large amount of interest has been shown in 32 bit RISC processors, high density DRAMs, and high density SR4MS. Testing on 32 bit RISC processors indicates a wide range of total dose and SEE tolerance [27, 28, 29]. These tests show that RISC processors manufactured by Siemens, NEC, Performance Semiconductor, LSI Logic, Integrated Device Technology (IDT), and Intel have total dose tolerance above 10 krad(Si), although some of the device show a large variability, ranging from 5 to 70 krad(Si) total dose failure level. Devices from all manufacturers except Siemens showed proton-induced latchup, but the threshold LET was above 24.7 MeV/mg/cm2 and the calculated rate is 1,5x 10’5 latchups/day (or 1 latchup every 182 years). The upset rate measured for these processors was better than 1.2x 104 upsets/day (or 1 upset every 22 years). It V-21
should be noted that the total dose test method was not indicated (other than to say that the parts were tested to failure during proton SEE exposure), so the results may not directly compare to total dose testing conducted in accordance with MIL-STD -883D TM1O 19.4. Non-hardened SIL4M parts have been tested for suitability for use in space. SEE tests were performed on 256K and 1M SRAMS from Micron Technology, Sony, NEC, Hitachi, Fujitsu, Seiko, IDT, and Mitsubishi [30]. Total dose test results for these devices were not reported, but it was indicated that the limit for these devices is typically 10 krad(Si). About half of the die tested were considered suitable for space use based on the SEL measurements. Micron was the only manufacturer that had no latchup for 1M SRAMS. Micron, NEC, IDT, and Hitachi 256K SRAMS also showed no latchup, It is interesting that the Hitachi 256K SRAMS performed better on SEL and SEU testing than the Hitachi 1M SRAMS. This was attributed to the increased sensitivity resulting from reduced feature size. SEU threshold on all the parts was low, with all but one below 4 MeV/mg/cm2 and cross sections above 0.1 cm2. The Micron and Hitachi lM memory die showed multiple bit upsets, with the Hitachi die showing multiple errors in the same byte (potentially a problem for EDAC). These devices also exhibited permanent “stuck-at” damage for LETs larger than 30 MeV/mg/cm2. DRAMs have not received wide use for space systems due to their perceived radiation softness, Tests performed on IBM and Texas Instruments (TI) 16M DRAMs have shown that they may be suitable for some space applications [31]. One of the IBM parts tested (LUNA C) has built in EDAC that allows correction of one bit in a 137 bit word and detection of two bit errors in the same word size. The IBM parts showed inconsistent total dose response: one part showed functional failures at 10 krad(Si); the other part remained fi.mctional until 50 krad(Si). The parts showed no SEL. SEU performance indicates threshold LETs under 8 MeV/mg/cm2 for single errors and for row and column (multi-bit) errors for both part types. The low SEU threshold indicates sensitivity to upsets from trapped protons, SEU rate estimates for the nonEDAC part in an 800 km sun synchronous (97° inclination) orbit is 2,54x1 0-] errors/device-day. The EDAC improves the SEU performance by about 3 orders of magnitude. The four TI parts tested had functional failure ranging from 13 to 27 krad(Si). SEU threshold LETs were about 2 MeV/mg/cm2, for single and row and column errors. The estimated error rate for the TI parts in the same 800 km orbit is 5,03x101 errors/device-day.
2.3 Determining
radiation
capability
The key to qualification of radiation hardness is the determination of the radiation capability of the parts. This is always done by using test data. The main issues are usually the test methods and the sample size. Typical test data is for a very small number of parts (usually under 5). This is a concern from a qualification point of view because data this limited does not provide any indication of the variability of the radiation response. Qualification is concerned with assuring that the part used in the system has the expected radiation response, and determination of the radiation capability is the starting point.
v-22
2.3.1 Manufacturer’s
data
Manufacturers can collect a statistically significant amount of data on the radiation hardness of their parts. In addition to having ready access to finished products, the manufacturers typically use test structures that are more sensitive to radiation effects than product devices. It is well worth the customer’s time and effort to obtain access to this data and to gain an understanding of the processes used by the manufacturer to assure radiation hardness, Radiation test data is not the only useful information in the possession of the manufacturer. The information used by the manufacturer to control the critical process steps for radiation hardness is nearly as usefid as the radiation test data.
2.3.2 Databases Microelectronics radiation test results are available from several electronic databases. Some of these can be accessed by modem or Intemet. These databases include hardened and commercial part test data, with parts ranging from discrete transistors to microprocessors.
2.3.2.1 ERRIC The Electronics Radiation Response Information Center (ERRIC) is a database that was established by the Defense Nuclear Agency (DNA) and is maintained by the DoD Nuclear Information and Analysis Center (DASIAC). ERRIC includes radiation test data on diodes, transistors, and integrated circuits. The information is organized and stored by piecepart identification and includes: device type, manufacturer, sample size, lot number, serial number, date of manufacture, test facility, test date, test descriptions, measured data, radiation dose or fluence, pre- and post-test parameter values, and transient data. ERRIC data is available to the DoD, U. S, Government agencies, and approved U.S. Government contractors. ERIUC is not an interactive database, Approved users can obtain a listing of the pieceparts in ERRIC, and can request data for a specific part by telephone or fax. Turn-around time for requests is typically about 3 days. For more information about ERRIC, contact: Claude Fore Kaman Sciences Corporation 2560 Huntington Avenue Suite 400 Alexandria, VA 22303 Phone: (703) 329-7119
2.3.2.2
ESA Radiation Effects Database
The European Space Agency (ESA) maintains a radiation effects database to support electronic piecepart selection by the ESA community, This database is maintained by:
V-23
SPUR Electron Limited Asgard House Hayward Business Centre New Lane Havant Hants P092NL United Kingdom Phone: 44-705-455-564 Fax: 44-705-470-874
2.3.2.3
GIDEP
The Government-Industry Data Exchange Program (GIDEP) is not a database devoted to radiation effects testing, but it sometimes has information about radiation hardened parts. The database contains information submitted by the participants. The information includes test reports, calibration procedures, failure experience data, and other technical information. GIDEP data is sorted into four major categories: failure experience data, including alerts, advisories, and product change notices; metrology data; reliability and maintainability data; and engineering data, including engineering reports, test reports, management reports, and non-standard parts documentation. The GIDEP Alerts can be a very useful service because they reflect problems Access to GIDEP is limited to government activities and industrial observed in applications. organizations that supply items or services to the U.S. Government or to the Canadian Department of Defence. Additional information and applications for access can be obtained by contacting: GIDEP Operations Center P.O. BOX8000 Corona, CA 91718-8000 Phone: (909) 273-4677 Fax: (909) 273-5200
2.3.2.4
RADA TA
The NASA Jet Propulsion Laboratory (JPL) maintains a total ionizing dose and Single Event Effects database called RADATA. The database contains test results for diodes, transistors, and integrated circuits and is organized by test type (TID or SEE). This database can be accessed using a modem or through Intemet by anonymous FTP (file transfer protocol). RADATA can be accessed by: Intemet FTP
Modem (818) 393-1725 Full Duplex (to 14.4 KBaud) 8 bit, 1 stop bit, no parity
radata.
jpl
(137,79.11.2) usemame: password:
V-24
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gov
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JPL has recently introduced a new service, RADATA-Interactive. This service uses the World Wide Web (WWW) to provide an interactive interface for the RADATA information, Using a WWW browser like Mosaic [32] or Netscape [33] the database can be searched by part number and viewed on-line. The RADATA-Interactive database also contains a list of the data available from ERRIC (see Section 2.3.2.1) and provides an on-line form to make data requests from ERIUC. A sample of the information available from RADATA-Interactive is shown in Figure 8. The URL (uniform Resource Locator) for RADATA -Interactive is: http://kepan
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2.3.3 Testing It is critical that the As mentioned previously, testing is the first step in qualification, test standards. As mentioned in testing be performed according to the appropriate Section 2.1,3.4, MIL -STD -883 contains the appropriate test methods for total dose, neutron, dose rate latchup (survival), and dose rate upset. The standard recommended for SEE testing is ASTM Method 1192, “Standard Guide for the Measurement of SEP Induced by Heavy Ion Irradiation in Semiconductor Devices.” Since radiation testing requires special equipment that is not typically found in a semiconductor characterization laboratory, this testing is usually These facilities generally have staffs that know and performed at special test facilities. understand the appropriate test standards, and can often assist in development of the test plan. Characterization of the radiation response of electronics parts should be done on a sample that reflects the variation expected in the overall part type population. Ideally, samples could be
V-25
chosen to understand the variation of radiation response from the following sources: dice-to-dice across a wafer, wafer-to-wafer within a fabrication lot, and lot-to-lot variation. If this is not practical (and for complex electronics it usually is not), then the sample should attempt to span the largest source of variation, usually lot-to-lot. Parts should be characterized for their worstcase operating environment. It is also important to perform radiation testing after burn-in, since the radiation response of some parts has been seen to change after the parts are burned in, The characterized eclectically before parts must be completely exposure to radiation. Characterization testing often involves testing to failure to understand how a part degrades with radiation. Exposure levels and accelerating factors must be carefully chosen to provide the best understanding of the intermediate behavior before failure.
2.4 Qualification approaches Three qualification approaches will be considered: government qualification through the QML program, use of a monitored line, and a “Do it yourself’ approach. If possible, qualification is probably something that is best done by someone else. Qualification usually involves a lot of preparatory work in understanding the manufacturer’s processes and requires a wide variety of expertise.
2.4.1 QML As discussed in Section 2.1.3.3, the government has established a prog-ram to quali~ manufacturing process flows for reliability and radiation tolerance. QML qualification is a very involved process. When a manufacturer expresses interest in obtaining QML qualification, DESC provides information about the requirements for the Quality Management (QM) plan. The Q M plan is the heart of the manufacturer’s QML system. The manufacturer establishes a Technology Review Board (TRB) that reviews any proposed changes to the process flow. One of the hallmarks of the QML system is flexibility, and the TRB is one of the examples. MIL-I-3 8535 contains requirements for the TRB and even has a suggested organization, but the implementation of the TRB is left to the manufacturer. Ideally, meeting the TRB requirements Typically, the will not involve any significant changes in the manufacturer’s operations. manufacturer needs to synthesize the TRB out of several elements currently in place, and must develop new elements to cover any missing areas. DESC will meet with the manufacturer several times before the formal validation review. The purpose of these meetings is to explain the requirements and review process, and assist in the development of the QM plan. DESC holds a pre-audit to discover any problems prior to the validation review, giving the contractor an opportunity to address the problems before the validation. A QML validation is an endurance contest between the government team and the manufacturer. Most of the validations are 5 working days in length, and typically last about 11 hours per day. During the validation all the manufacturer’s systems are reviewed, from order entry to the shipping docks. The key topics reviewed during a QML validation include: the TRB system, Statistical Process Control (SPC), wafer fabrication, desi~ assembly, test, V-26
Technology Characterization Vehicle (TCV) and Standard Evaluation Circuit (SEC), conversion of customer requirements, and field failure returns. Radiation hardness is discussed in almost all of these sessions. The impacts of wafer fabrication, design, and assembly on the radiation hardness are obvious. Almost as important are the SPC, TCV, and SEC, One of the central premises of QML is minimization of variation through the use of in-line controls. The manufacturer defines the critical processes to maintain electrical performance, reliability, and radiation hardness. For each of these critical processes (or nodes) a set of measurements is defined that characterizes the process. Statistical analysis is performed on the measurements and a set of control limits are defined to provide an early warning of excessive variation in the process. The TCV contains test structures that are processed periodically as an indicator of the low-level health of the process flow. A manufacturer will typically include several dedicated radiation hardness test structures on the TCV. Included in these are various types of transistors to investigate edge and gate problems. TCVS will usually contain SEE structures, such as resistors used in SRAMS. An important aspect of the QML validation is the review of the testing. This assures the customer that the proper test methods are being used, and that the data is being interpreted correctly.
2.4.2 Monitored
line
A monitored line program uses a contractor to assure the reliability of the parts that are handled. The managing contractor works with a set of suppliers to assure the quality of the parts. The U.S. Air Force Monitored Line Program (MLP) managed by Lockheed Missiles & Space Company will be used as a model for this discussion. Lockheed does not manufacture parts for the MLP. Instead it works with suppliers, in this case: National Semiconductor, Siliconix, VLSI Packaging, and Microsemi. Fees for the MLP service are included in the price of the parts, which are purchased directly from the supplier rather than from Lockheed. Lockheed maintains resident personnel at the supplier sites to review MLP part shipments.
2.4.3 Do it yourself This option is only recommended for a part or technology that is not addressed by any other means. An example at the part level would be the so called “lifetime buy” in which enough of a given part type is purchased to satisfy the needs for the entire program. In this case, the QPL program would provide a good model for a lifetime buy qualification. An example of a technology that this would apply to is cryogenic electronics. It is useful to examine the other qualification approaches, especially QML, to understand the types of information that will be needed for a technology qualification program. Developing your own qualification program will require a very detailed understanding of the manufacturing process, sources of variation within the process, and the techniques to measure the variation. To qualifi a process for radiation effects, the damage mechanisms must be understood to determine the effects of variations in the processing of the parts,
V-27
The manufacturer is probably the best source of the information needed to develop a qualification program. While a program modeled on QML would be the best, the manufacturer may not use SPC or may not control the process features that have the greatest effect on radiation response. At a minimum, it will be necessary to perform characterization testing on the product devices, and on test circuits. The process monitoring structures used by many manufacturers are very usefi.d in understanding the radiation damage mechanisms because they allow access to a variety of basic circuit elements: transistors, resistors, capacitors, interconnects, etc. In some cases, it might be possible to add specific radiation test structures to the process monitor or to the saw kerf between die. A collection of radiation effects test structures has been documented, covering characterization and hardness assurance applications [34]. Product circuits are usually much less sensitive than the basic circuit elements, but testing of these devices is very useful because it establishes a baseline for the radiation response of the circuits of interest. Most manufacturers have a good understanding of the process features that affect electrical performance and reliability of their products. This information is a useful starting point for understanding the features that affect radiation. Some of these features, such as gate oxide thickness in MOS devices, have an important impact on the hardness of the devices. A process level qualification program is probably the best, since it derives from an understanding of the underlying mechanisms. In many cases, a process level qualification is not possible. The manufacturer may not have or may not be willing to share the data. In these cases, it will be necessary to establish a program based on product testing. The QPL program could be used as a model for this type of qualification. It will be important to establish an agreement with the manufacturer to be notified of changes to the manufacturing process. If the process features that affect the response to a particular radiation environment are known, these can be specified in the agreement. In summary, ‘Do It Yourself’ qualification is a difficult, and usually expensive prospect. This should not be undertaken lightly. It is important to know the manufacturer of the device, since they are the best source of information about the devices characterized and the devices used for the system are fabricated.
2.5 Radiation testing
Radiation testing is a key component in qualification of devices for use in an application that will result in significant radiation exposure. Two different purposes have been described: characterization testing to determine failure levels and failure mechanisms; and sample testing to assure the radiation hardness of devices planned for use in a system.
2.5.1 Test guidelines In addition to the previously mentioned MIL-STD-883 (See Section 2.1.3 .4), there are a number of military handbooks that provide guidelines for radiation effects testing:
V-28
. MIL-HDBK-8 14, “Ionizing Dose and Neutron Hardness Assurance Guidelines for Microcircuits and Semiconductor Devices,” dated 8 February 1994, This document provides methods and procedures that can be applied to programs with total dose radiation requirements (natural and nuclear), and incorporates suggestions for the implementation of a testing-based hardness assurance program. s MIL-HDBK-815, “Dose Rate Hardness Assurance Guidelines,” dated 7 November 1994. This document provides guidelines for the application of test data and design techniques for assuring the dose rate hardness of piece parts and systems. ●
●
MIL-HDBK-8 16, “Guidelines for Developing Radiation Hardness Assurance Device Specifications,” dated 9 December 1994. This document provides guidelines for developing part-level specifications. It includes recommended procedures for characterization and qualification testing. MIL-HDBK-8 17, “System Development Radiation Hardness Assurance,” 8 Februa~ 1994. This document addresses the hardness assurance problem from a programmatic point of view. It serves as an excellent introduction to the concepts of hardness assurance.
The U.S. Army Space & Strategic Defense Command has also released a test guidelines document.
2.5.2 Who can and should do radiation
testing
Anyone with the proper equipment can perform radiation testing, but unless the proper procedures are followed the results may not be meaningful. An example of this would be dose rate survival testing performed on some radiation hardened parts. In this case, a current limiting power supply was used for the test, and the device under test tripped the limiter, The increase in current was noted, but not associated with a potential problem because an increase in current had been expected. In later testing at another facili~, the same part type experienced dose rate burnout due to violation of a design rule. Had the original test been performed correctly, the design error would have been caught early in the design of the component, rather than in qualification testing for a system application. Testing should be performed by organizations that are familiar with both the devices being tested and the test conditions. Total dose testing can be relatively straightfonvard, but there are some areas where special attention must be paid. At a minimum, the testers should be familiar with the appropriate test methods contained in MIL-STD -883. It is also important to understand the equipment that is being used for the testing. This includes the equipment used to deliver and measure the radiation exposure as well as the equipment to measure electrical parameters.
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2.5.3 What testing should be performed Obviously, testing should be appropriate for the environment that the components will be exposed to during use in the system. In a spacecraft application, this would include total dose and SEE testing. For a military system with a nuclear weapon threat, dose rate testing would also be included.
2.5.4 Potential
pitfalls
Rigid adherence to the test methods and guidelines is not always a guarantee of success, h example of the problem can be seen in the total dose testing of some types of linear bipolar devices. Using the dose rate specified in TM 1019.4, the gain degradation in some linear bipolar devices can be significantly underestimated [35]. These devices show an anomalously large degradation when the dose is delivered at dose rates that are well below the recommendations of the test method (50 to 300 Rad(Si)/s), but representative of the dose rate exposure in the natural environment (about 1 Rad(Si)/day).
3. Commercial
devices
Intrinsically radiation hardened devices are more expensive, fewer functions than non-hardened devices. With this background, serious consideration is being given to the use of the non-hardened commercial market. Some commercial devices offer enough radiation some radiation environments (see Section 2.2.2). Carefi.d consideration use of these devices instead of intrinsically hardened parts.
less available, and offer it is not surprising that devices available on the tolerance to be usable in must be given before the
3.1 What are commercial devices? For the purposes of this discussion, ‘commercial’ devices are devices that are not specifically designed and fabricated for use in a radiation environment. Thus, die that are packaged in high reliability packages, and screened to milita~ requirements are still considered ‘commercial,’ Also, a radiation hardened device used in a commercial system, even if it is not packaged to military requirements, is not considered commercial. The issue of the reliability (for non-radiation failure mechanisms) of military devices as compared to commercial devices will not be considered here. This is not to say that this is unimportant, indeed it can greatly affect the cost of the devices due to the tests and screening of milita~ requirements. Reliability issues, like radiation hardness, are pervasive. They affect the establishment of specifications for the device, the design of the circuits and the layout of the geometric features on the die, and the assembly and packaging. If good engineering practices are followed, commercial die are as reliable as die fabricated in a QML flow. This should not be surprising since the QML approach attempts to exploit the best commercial practices (e. g., Statistical Process Control).
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3.1.1 Howhard
arethey?
Test data indicates that commercial parts exhibit a wide range of radiation hardness, Total dose failure levels can range from a few hundred rad(Si) to over a million rad(Si) [27, 29]. A rule of thumb for total dose hardness seems to be about 10 krad(Si), but the specific part types in consideration should be tested for their total dose tolerance. Like total dose, SEE hardness varies considerably, but is in general significantly less than devices that are specifically hardened against SEE. As a rule of thumb, most commercial devices are subject to SEL, This does not make them unsuitable for use, since in some cases the SEL threshold LET is very high. Again, the SEL characteristics of the devices should be determined before selecting them for use, especially since it is impractical to shield against SEE. As with SEL, the SEU hardness of commercial devices vary, but is substantially less than specifically hardened devices. On the whole, commercial parts are soft to SEU. Typical threshold LETs are under 8 MeV/mg/cm2, making them subject to upsets from trapped protons (and potentially high upset rates in low orbits) [30, 31].
3.1.2 What does the future hold? On the whole, the future is mixed for radiation hardness of commercial parts. As the feature sizes shrink, some of the failure mechanisms improve (e.g., gate oxide trapped charge is reduced as the oxides are thinned) while others degrade (e.g., critical charge is reduced, making the parts more sensitive to upset). There seems to be a general downward trend for both total dose and SEE tolerance as the level of integration of commercial devices increases. Reduction of the supply voltage (a consequence of scaling the gate oxide) increases the sensitivity to threshold voltage shifts in MOS devices, and increases the sensitivity to SEU by decreasing the critical charge. In this case, the critical charge seems to be dominating the decrease in sensitive volume, leading to an increasing trend for SEU. SEL hardness can be improved by fabricating the devices on a thin epitaxial layer grown on a bulk silicon wafer, so there maybe an improving trend here if the epitaxial layer is thin enough. Most of the recent test data collected on SEL is for parts fabricated on an epitaxial layer, indicating that these are the primary choice for use in space systems. 3.2 Tradeoffs between commercial and radiation hardened parts The decision on whether to use commercial or radiation hardened parts requires a consideration of the mission, the effectiveness of mitigation techniques, and the cost. There are few simple answers. The easiest case is for parts that have to perform in a nuclear weapons environment. In this case, the use of commercial parts is not recommended since the radiation is more penetrating than the natural space envirornnent and the dose rate effects are very severe, For natural space applications, the use of parts that have a low SEL threshold LET should be avoided, and any part that is subject to SEL should be used with detection and power down systems to avoid damage to the circuits.
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3.2.1 Performance Commercial parts have a clear advantage in the area of performance. This is not to say that radiation hardened parts have low performance. Radiation hardened SRAMS have been demonstrated with worst-case access time under 20 ns. The design and process features that provide radiation hardness tend to consume area. It is interesting to compare the die for commercial and radiation hardened SRAMS. It is easy to tell them apart: commercial SRAMS have a decidedly rectangular shape (i.e., much longer on one edge than the other), where radiation hardened SRAMS are very nearly square. Since radiation hardened circuits require more die area than non-hardened circuits, less can be placed on an equivalent size die. Implementation of a commercial circuit using radiation hardened technology will increase the die area needed. Since many commercial parts are die area limited, an equivalent radiation hardened part will require multiple die. This means that some of the circuit paths must be broken and taken off-chip. Driving a signal off-chip and receiving it on another chip usually This may result in an increase in the introduces an additional delay of several nanoseconds, critical path, and a reduction in the clock speed.
3.2.2 Margins Radiation hardened parts clearly have an advantage in the area of margins. The RDM for a radiation hardened part will place it in the ‘Hardness Noncritical’ category (RDM 2 100), where no additional lot testing is required, for most natural space applications. Using the typical 10 krad(Si) hardness level, commercial parts barely meet the RDM = 3 requirement for a 10 year mission in an 840 km, 98.8° orbit (about 1 rad(Si)/day behind 227 roils Al)[ 9]. Uncertainty in the models, and the potential variability in the radiation response of commercial parts underscores the importance of adequate margin in the radiation hardness of the parts.
3.2.3 Variability Very little data exists exploring variability in the radiation response of commercial parts (see Table 2), but some general ideas can be explored as a thought exercise. The leading integrated circuit manufacturers are using many of the ideas that are codified in the QML program, Statistical Process Control is almost a requirement to obtain good yields and reproducible electrical behavior in modern integrated circuit manufacturing, The control by commercial manufacturers of processes that affect electrical performance, reliability, and yield is generally excellent. These manufacturers understand the sources of variation in these particular processes and control them very tightly. A problem arises for process features that do not have a profound effect on the electrical performance, reliability, or yield, but have a significant effect on radiation hardness. An example of one of these parameters is epitaxial layer thickness. If the epitaxial layer is too thick, the part will be subject to SEL. In these cases, there is a large potential for variation in the radiation response of the parts. It is possible to partially mitigate this problem by purchasing
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Total Dose Failure Range [krad(Si)] Ratio (Max/Min) IBM 10–50 5 Integrated Device Technology 0,266 -17.5 65.8 LSI Logic 45 – 1070 23.8 Performance Semiconductor 4-80 20 Siemens 48 – 70 1.5 Texas Instruments 13–27 2.1 Table 2. Total dose failure variations in commercial radiation tolerant devices Manufacturer
parts that were manufactured solution.
in the same manufacturing
Source -31: ’27 [;;: [ [::]
lot, but this is not usually a practical
The radiation response of a part is controlled by both the process and the part design. A significant source of variation in the response of commercial parts could be the manufacturer. Some manufacturers will subcontract the die manufacture to other foundries when they have capacity problems. In these cases, there can be variations in both the process and design. Commercial manufacturers will routinely make changes in the process and design of a circuit to improve the electrical performance and yield of the parts. These changes may be benign or beneficial for electrical performance or reliability, but can be detrimental to the radiation response. Radiation hardened parts are typically produced under the QML or QPL system, both of which have mechanisms to assure the radiation hardness of the parts. In the QML system, the RHACL acts as a minimum level for parametric failure (functional failure usually occurs at much higher levels). Manufacturers of radiation hardened parts understand and control the process features that are important for radiation hardness. In the QML program, the manufacturer is encouraged to make changes that improve the process, but is required to show that the changes will not adversely affect electrical performance, reliability, or radiation response.
3.2.4 Cost Probably the strongest perceived advantage of commercial parts is the area of cost. Unfortunately, these costs usually include only the purchase price of the devices, not the total cost to use the parts (“cost-of-ownership”). The per piece cost of radiation hardened parts is very high when compared to equivalent commercial devices, sometimes up to a factor of 100. This is due, in part, to the extra screening these parts are subject to in order to meet military requirements, and in part due to the lower yield per wafer (due mostly to larger die size for equivalent finction) caused by the radiation hardening features. A recent presentation by Hams (a radiation hardened parts supplier) at the Government Microcircuit Applications Conference (GOMAC) gave an example of the cost of ownership for radiation hardened parts in comparison with commercial parts [ 36], Unless a large number (thousands) of a specific part type is purchased, the cost-of-ownership for commercial parts can v-33
be as much as twice the cost of radiation hardened parts to provide the same level of radiation hardness assurance. The sources of this additional cost are: “upscreening” the parts to a “space quality” level; total dose characterization and shielding; SEU characterization and system level mitigation costs; SEL characterization and system level mitigation costs, and single event burnoutmitigation. While some of the costs may be exaggerated, this study clearly shows that the cost situation is not as simple as comparing the piece part price.
3.3 Implementation using commercial devices If commercial parts are used in a system that must perform in a radiation envirotient there are a number of techniques that can be used to improve the system level radiation tolerance. Shielding can be effective in reducing the total dose exposure of the parts, and system level techniques can be used to mitigate the effects of SEE, In either case, there is some penalty to be paid. In most cases it is extra weight, but can also be extra hardware and power requirements.
3.3.1 Shielding Shielding can be a very effective technique to reduce the total dose experienced by parts in a radiation environment. Shielding is also somewhat effective at reducing SEE in parts that are susceptible to low energy trapped protons, but is not very effective at reducing high energy protons or galactic cosmic rays. In a nuclear environment, shielding is only effective to the point that the X-ray flux is reduced to the level of the y-ray flux, since the y-rays will penetrate most practical shielding. Traditional shielding is applied to the box that contains the electronics, either over the entire surface to shield all parts, or spot shielding to protect sensitive parts. Another shielding approach is to incorporate the shielding material as an integral part of the package. The effectiveness of shielding can be calculated using a variety of computer codes. These codes will typically have several different shield models: slabs, spheres, shells, and possibly others. The effect of each shield type varies due to the contribution from scattering of radiation by the shielding material geometry. A spherical shell is often used to calculate the dose received by a part inside a hollow spacecraft from an omnidirectional source. In this case, an appreciable portion of the scattered flux does not impact the part. In a solid sphere, with little distance between the part and the shield, the flux will be higher since most of the scattered radiation will impact the part. The appropriate shield to use will depend on the geometry of the application. It is important to realize that the effectiveness of shielding has limits. A thick shield will almost completely shield a part from direct exposure to trapped electrons, but the brernsstrahlung radiation produced and high energy protons will penetrate the shield. Measurements on the DMSP satellite (840 km, 98.8° inclination orbit) indicate that a minimum unshieldable dose due to high energy protons and bremsstrahlung radiation is 0.3 rad(Si)/day [9]. Space Electronics Incorporated (SEI) offers a line of commercial parts in a shielded package called RAD-PAK. They characterize the part total dose response using the military v-34
standard test method, calculate the environment for the selected orbit and lifetime, perform radiation transport calculations to determine the amount of package shielding necessary to reduce the dose to the part to a level below its failure level, and perform electron and proton testing on the packaged parts. SEI claims that the RAD-PAK shielding approach can improve the component total dose hardness to about 100 krad. They note that RAD -PAK will not improve the SEE characteristics of the parts, thus SEI selects parts that have good SEE characteristics, relying on government sources for the SEE characterization. It is also important to note that SEI does not recommend this approach for nuclear weapon shielding, due to the very penetrating nature of radiation from nuclear sources. SEI offers a variety of parts, including high density memories (up to 4M SRAM) and an 80386 microprocessor,
3.3.2 System approaches There are several system level approaches that can be used to mitigate the effects of SEE. As already discussed, in many cases SEL can be stopped before it destroys the part by monitoring the supply current to the part and providing a mechanism to power down the part if an SEL is detected. SEU in memories can be mitigated by parity when only detection is necessa~, or EDAC when the need to correct an error is required. In the case of EDAC, it is necessary to calculate the expected error rates and to determine the mean time between multi-bit errors in a single word (assuming that the parts are not susceptible to single event multiple bit errors), “Scrubbing” the memory (reading all the locations to allow the EDAC to detect errors, and then writing back the corrected value) is performed at some fraction of the time between multi-bit single word errors. Detection of errors in combinational logic is much more difficult than for storage devices. Parity is usually not preserved across arithmetic operations, so parity protecting the data paths will not be sufficient to detect errors in the logic. Residue arithmetic can be used to detect errors in combinational logic, but correction of errors is very difficult. Most approaches to detecting errors in combinational logic deal with processing the data multiple times. Lockstep-compare uses two identical processors, each running the same software on the same data in lockstep. The results are compared every time the processors write to the bus, and if they do not match then an error has occurred. Lockstep-compare is usually used in conjunction with a checkpoint and rollback scheme. At defined points, the intermediate results of a calculation are written out to memory and then the calculation continues. If an error is detected, the intermediate results can be read back into memory and the calculation can be restarted, minimizing the lost data. Note that in a lockstep-compare configuration it is not usually possible to determine which processor is in error, Also, the synchronization of the processors is a very tricky engineering problem, and a great deal of attention must be paid to the arrival of signals. There are other variations of the multiple processing theme that can be used to mitigate SEE. A commonly considered configuration is Triple Modular Redundancy (TMR), In TMR, there are three processors and they vote on each output. If one of the processors differs, then it is taken off-line and processing continues with the other two remaining processors. This approach provides non-stop detection and correction of processing errors. If the throughput is not an issue, then the results can be calculated multiple times and compared on a single processor.
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4. Failure Case Histories The National Geophysical Data Center (NGDC) maintains a database of spacecraft anomalies [37]. In the period from 1 February 1971 to 22 Februa~ 1993 the NGDC recorded 4,504 anomalies from a total of 250 spacecraft, The anomalies arise from a variety of sources: phantom command (uncommanded status change), part failure, telemehy error, soft error (SEU), hard error (permanent damage or SEL), system shutdown, electrostatic discharge damage, attitude control problem, and the ubiquitous unknown. NGDC also attempts to diagnose the cause of the errors, providing the following categories: electron caused electromagnetic pulse, electrostatic discharge, SEU, mission control problem (“cockpit error” or software error), radio frequency interference, and unknown. Assessment of failures is often very difficult because the direct evidence (the satellite) is unavailable, and the cause must be inferred from the telemetry received by the ground and from the environment as monitored by other satellites in orbit. Three satellite failures have been selected to illustrate radiation effects. The first, Anik-El and -E2 represents a likely case of a total dose related failure. The second, Superbird represents an SEU that ultimately caused loss of the vehicle. The final failure is the Clementine satellite, where failure was initially attributed to a radiation hardened microprocessor, but later determined to be a software problem. None of these failures can be definitively attributed to radiation qualification, but all of them can be attributed to an incomplete understanding of the requirements.
4.1 Anik-E1 and -E2 In January 1994 two Canadian communications satellites (Anik-E 1 and -E2) experienced attitude control failures that left them partially degraded. After a period of enhanced high energy electron flux, one of two redundant momentum wheels on Anik-E 1 and both momentum wheels on Anik-E2 failed with zero speed [38]. The momentum wheel assemblies (MWAS) are used for pitch control on the satellites; magnetic torquers provide roll and yaw control and nutation damping. Failure of an MWA with zero speed prevents the use of the MWA for pitch control or bias momentum. The onboard attitude control logic was not designed to control a zeromomentum satellite, and could not be reprogrammed. This results in the loss of the ability to provide three-axis stabilization of the satellite. Anik-El was switched to the backup MWA and returned to normal operation. Following the successful demonstration of a ground-based scheme to control the satellite pitch using thrusters in July 1994, Anik-E2 was restored to service in August 1994. The environmental evidence strongly suggests that total dose (90Y0 confidence) was the cause of the Anik satellite failures, with suggestive evidence that bulk charging and subsequent discharge (74Y0 confidence) was the cause [39]. Prior to the failures, the high energy electron flux at geosynchronous altitude increased by over two orders of magnitude. The integrated fluence measured by three DoD geosynchronous satellites and a GOES satellite was about 1.5x1012 cm-2 for electrons with energies over 300 keV, and 1.9x109 cm-2 for electrons with energies over 3 MeV, The cosmic ray flux was at normal background levels, and no unusual proton fluxes were observed in the three weeks before the failures. Examination of the part types
V-36
used in the MWA control circuitry and the shielding available indicated that the electron fluences could have caused total dose failure of the parts. Recove~ of Anik-E2 required the development of a ground-based attitude control system that uses the thrusters to maintain pitch control, The attitude control loop required satellite roll, pitch, and yaw rate feedback [38]. In most satellite designs, this rate information is provided by onboard gyroscopes, but the gyroscopes used on Anik were not designed for continuous operation and would have limited the satellite lifetime. Spacecraft rates are estimated using roll and pitch data from the satellite, and yaw data estimated on the ground by analysis of the RF signal from the satellite. The control system developed requires two to three 8 ms thruster pulses per hour to control the satellite pitch. The cost of the Anik-E2 failure and recovery procedure is estimated at $66M [40]. Failure of both MWAS on Anik-E2 requires the use of station keeping propellant for the control of the spacecraft, reducing the service life of the vehicle by about one year. It has been noted that a Mexican communications satellite (Solaridad) in about the same orbit as Anik did not experience any problems. The lack of problems on Solaridad has been attributed to the use of hardened electronics and careful attention to electrostatic discharge. The problems with Anik illustrate how the uncertainties in the environment can lead to an underestimation of the requirements on the electronics. In this case, the total dose tolerance of the parts was not adequate to allow the electronics in the momentum wheel assemblies to survive After the failure of the satellites, the total dose radiation for the length of the mission. vulnerability was determined to be a possible cause by testing of the suspected parts.
4.2 Superbird The Japanese Space Communications Corporation (SCC) was forced to shut down their Superbird-A satellite on 23 December 1990 due to a loss of attitude control propellant [41]. The satellite was launched about 18 months earlier, on 6 June 1989. Superb ird-A began to lose attitude control on 18 December 1990, when a valve malfunctioned and allowed the attitude control oxidizer to leak away, making control of the spacecraft impossible. Loss of the satellite deprived SCC of their ability to provide communications services to their customers. SCC was forced to lease transponders from the Japan Satellite Communication Corporation (JC-Sat) JC -Sat-1 and -2 satellites to provide service to their customers until after the launch of a new Superbird-A on 1 December 1992. A cosmic ray strike on the electronics associated with the attitude control electronics resulted in a minor control problem that was compounded by procedural errors in an attempt to correct it [42]. During the effort to correct the attitude control problem, the valve seals in 9 of 12 attitude control thrusters were damaged, allowing the satellite’s oxidizer propellant to leak overboard. The microprocessors used on the first Superbird-A spacecraft have been replaced with SEU hardened microprocessors developed by Sandia National Laboratory for the NASA Galileo spacecraft. Procedures for turnover of satellite control to the customer have also been changed. v-37
Loral (the satellite manufacturer) will maintain control for 6 to 8 months, and then control will be transferred to the Mitsubishi Electric Kamaden satellite control facility built specifically as a result of the Superbird -A accident. After 6 months of control at Kamaden, control of the satellites will be turned over to SCC. Control of the first Superbird-A was turned over to SCC after only one month on orbit. This example serves to show that the impact of an SEU can be very serious, especially when there are compounding factors like operator error. It is likely (though not certain) that the satellite could have been recovered by suitably experienced operators. The cost estimate for this failure ranges from $95Mto$150M [41, 42].
4.3 Clementine Clementine (also known as the Deep Space Program Science Experiment, DSPE) technology demonstration vehicle for advanced technology components developed Ballistic Missile Defense Organization (BMDO) designed to collect multi-wavelength mapping data of the Moon and a near-Earth asteroid. The DSPE Spacecraft Controller featured processors and controllers connected on a common I/O bus [43]:
was a by the digital (DSC)
. A radiation hardened MIL-STD - 1750A Housekeeping Processor (HKP), responsible for command, telemetry, and attitude control. The microprocessor selected was the Honeywell GVSC (Generic VHSIC Spaceborne Computer). The HKP had fise link PROM and SRAM. ●
A commercial Reduced Instruction Set Computer (RISC) Sensor Image Processor (SIP), responsible for star tracker camera processing, object centroiding, and experiment data processing. The IUSC microprocessor selected was the Integrated Device TechnologyR3081. The SIP had 1 MB of EDAC protected EEPROM and 2 MB of EDAC protected SRAM. Flight software for the HKP was stored in the SIT EEPROM, and the SIP had the capability of loading the software into memory on the HI@.
. A microcontroller Data Handling Unit (DHU), responsible for configuring cameras, compressing image data, controlling a solid state data recorder, and formatting data for downlirdc. The microcontroller selected was a United Technologies Microelectronics Center 69-ROOO,running in RISC mode. ●
Telemetry and command modules to provide interfaces to various control, monitoring, and data collection subsystems, including actuators, valves, and thrusters for the attitude control system,
. Global memory shared by the HKP and SIP. The global memory module featured 384 KB of radiation hardened SRAM and 128 KB of PROM. The DSC was designed to allow the HKP and SIP to perform some of each others functions. The SIP can act as a bus controller if the HKP fails, and the HKP can perform a subset of the SIT functions if the SIP fails.
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After successfully completing the lunar orbit portion of its mission, Clementine was configured for departure from lunar orbit. On 7 May 1994 a closed-loop tracking test was conducted to test algorithms for the asteroid fly-by portion of the mission [44]. During this test, contact was lost with the satellite for 23 minutes. When contact was re-established, the vehicle had transitioned from a three-axis stabilized spacecraft to spinning and uncontrolled. The spacecraft was spinning at 80.62 rpm and had depleted all attitude control propellant. The asteroid encounter was abandoned since the spinning would not allow the cameras to be pointed. An attempt was made to lower the spacecraft into an Earth orbit with at least 6 months duration by a series of timed firings of the satellite main thrust motor. While this attempt was able to slow the spin to 68.58 rpm, the spacecraft experienced a severe undervoltage (due to the decreased sun angle on the solar arrays and the inability to re-orient the arrays), and contact was lost on 4 June 1994. Failure of Clementine was initially attributed to a problem with the radiation hardened HKP, A memory dump was performed on the HKP after contact was re-established, and the memory locations that controlled thruster firings were found to contain the expected “off’ code [45]. The HKP needed to be reset on a regular periodic basis due to an unspecified software problem that caused an interrupt to be set [46]. Upsets attributed to SEU had been observed on the SIP, but this did not appear to be a problem with the HKP. After a complete investigation of the problem, the HICP hardware was cleared of responsibility for the satellite failure. The failure was traced to two software “bugs,” one of which was known [44]. During the mission, there had been numerous resets of the HKP [47]. After each reset, the flight software was loaded into the HKP SRAM from the SIP by a ground command, and patches containing software bug fixes were applied from the ground. In a reset prior to the final closed-loop tracking test, one of the patches had been inadvertently left out of the upload [44]. This allowed the second bug, unknown at the time, to manifest itself resulting in the firing of certain attitude control thrusters until the attitude control fuel was depleted. Clementine provides an example of a satellite failure that was initially believed to be radiation related, but later shown to be a software problem. The complexity of the Clementine hardware architecture and software contributed to the failure.
5. Conclusions Qualification of electronics parts for performance and reliability is a complex and difficult process; adding radiation response makes this task significantly more difficult because of the subtle interactions between manufacturing processes, design, and radiation response. This burden has been shared to some degree by the government and part manufacturers that participate in formal qualification programs like QML and 1S0 -9000, but the selection of parts from these sources is very limited. The increased pressure to use commercial electronics for applications in a radiation environment requires very special attention to qualification. Military standards have a very poor reputation. They are viewed as adding expense to an effort, but not adding value. While this may be the case for some military standards, it is by no means universally true. The military standards, specifications, and handbooks governing v-39
radiation response of electronics represent a vast body of knowledge that was very expensive to acquire. This information should be utilized as a resource. The present trend toward acquisition streamlining in government procurements has resulted in a reduction or even elimination of military standards as compliance documents. This represents a transfer of responsibility fi-om the government to the contractor, not a diminishment of overall responsibility. The contractor remains responsible for the product, but the government is removing itself from specifying the means the contractors will use to discharge this responsibility. Commercial electronics can be just as reliable as military qualified parts. The extra testing that military parts are subject to does not add quality or reliability to the parts; it just provides an extra measure of confidence. Military qualification attempts to control the quality and reliability of parts by controlling the manufacturing process (in QPL) or by controlling the means by which the manufacturing processes are modified (in QML). Radiation tolerance is affected by a variety of processes in the manufacturing flow, from the design of the parts to the packaging and testing. The predictability of the radiation response of the parts is a direct function of the ability to control the specific portions of the manufacturing process that affect the radiation tolerance. Parts that are produced on a dedicated radiation hardened process flow take great care to identify and control the processes that affect radiation response. Commercial process flows control those processes that affect electrical performance and reliability, but many of the processes that affect radiation response have little or no effect on performance and reliability. These processes will not be controlled on a commercial line. Thus, it is important to understand the range of variability in the radiation response if commercial parts are used, and it is important to provide adequate radiation design margin to account for this variability. It is important to realize that testing is not qualification. Testing provides an indication of the radiation response of a specific sample of parts, at a given moment in time. Unless there is a program to control the factors that affect radiation response, the test data may not be indicative of the radiation response of the parts that will be used in a system application. Also, not all test data is created equal. Ensure that the test data is taken using an accepted test method, and that the test conditions are appropriate to the use conditions (or that the proper extrapolations are performed). The use of commercial parts for an application that requires radiation hardness should not be made solely on a part cost basis. There can be a number of hidden costs that may cause the cost-of-ownership of commercial parts to be as high as radiation hardened parts. It is important to consider the intended application, and the consequences of failure of a particular part or part type, There are a variety of part-level and system-level mitigation techniques that can be used to improve the effective radiation hardness of commercial parts to the point that their use is practical, Qualification of parts, especially for radiation, is a complex process, It is essential to understand the requirements on the parts, and to assure adequate margin between the capability of the parts and the expected stress on the parts, A number of sources of information about radiation response are available, but care must be taken to understand the applicability of the test data to the intended application. Radiation hardened parts that are produced on a qualified v-40
[25] E. L. Petersen, J, C. Pickel, J. H. Adams, and E. C. Smith, “Rate Prediction for Single Event Effects – A Critique,” IEEE Trans. Nucl. Sci. NS-39, 1577 (1992). [26] MIL-STD-1547B, “Electronic Parts, Materials, Vehicles,” dated 1 December 1992.
and Processes
for Space and Launch
[27] D. L. Shaeffer, J, R. Kimbrough, S, M. Denton, J. L. Kaschmitter, J. W. Wilbum, R. W. Davis, N. J. Colella, and D. B. Holtkamp, “High Energy Proton SEU Test Results for the Commercially Available MIPS R3000 Microprocessor and R3010 Floating Point Unit,” IEEE Trans. Nucl. Sci, NS-38, 1421 (1991). [28] D. L. Shaeffer, J. R. Kimbrough, J. W. Wilbum, S. M, Denton, J. L. Kaschmitter, N. J. Colella, P. G, Coakley, and C. Castenaeda, “Proton-Induced SEU, Dose Effects, and LEO Performance Predictions for R3000 Microprocessors,” IEEE Trans. Nucl. Sci. NS-39, 2309 (1992). [29] J. R. Kimbrough, N. J. Colella, S. M. Denton, D. L. Shaeffer, D. Shih, J. W. Wilbum, P. G. Coakley, C. Casteneda, R, Koga, D. A, Clark, and J. L. Ullmann, “Single Event Effects and Performance Predictions for Space Applications of RISC Processors,” IEEE Trans. Nucl. Sci. NS41, 2706 (1994). [30] R. Koga, W. R. Crain, K. B. Crawford, D. D. Lau, S. D. Pinkerton, B. K. Yi, and R. Chitty, “On the Suitability of Non-Hardened High Density SRAMS for Space Applications,” IEEE Trans. Nucl. Sci. NS-38, 1507 (1991). [31] P. Calvel, P. Lamothe, C. Barillot, R. Ecoffet, S. Duzellier, E. G. Stassinopoulos, “Space Radiation Evaluation of 16 Mbit DRAMs for Mass Memory Applications,” IEEE Trans. Nucl, Sci. NS+l, 2267 (1994). [32] NCSA Mosaic is a computer code used to view World Wide Web pages, and is available from the National Center for Supercomputer Applications by anonymous FTP at ftp.ncsa.uiuc.edu (141.142.3.75).
[33]Netscape Navigator
is a computer code used to view World Wide Web pages, and is available from Netscape Communications Corporation by anonymous FTP at ftp.mcom. com (198.95.249,20).
[34] D. R. Alexander, “Radiation Effects Test Chip Guidelines,” Report, HDL-CR-91-043-1 (November 1991).
Harry Diamond Laboratories
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