Advances in Computers, Volume 9

Advances in COMPUTERS VOLUME 9

Contributors to This Volume

PAULW. ABRAHAMS A. S. BUCHMAN AVIEZRIS. FRAENKEL L. J. KOCZELA JOHNMCLEOD W. J. POPPELBAUM L. M. SPANDORFER

Advances in

CO MPUTERS EDITED BY

FRANZ L. ALT American Institute of Physics New York, New York AND

MORRIS RUBINOFF University of Pennsylvania and Pennsylvania Research Associates, Inc. Philadelphia, Pennsylvania

VOLUME

9

ACADEMIC PRESS. New York-London4968

COPYRIGHT0 1968,

BY ACADEMIC PRESS, INC. ALL RIGHTS RESERVED. NO PART O F THIS BOOK MAY B E REPRODUCED I N ANY FORM, BY PHOTOSTAT, MICROFILM, OR ANY OTHER MEANS, WITHOUT WRITTEN PERMISSION FROM THE PUBLISHERS.

ACADEMIC PRESS, INC. 111 Fifth Avenue, New York, New York 10003

United Kingdom Eddion publiahed by ACADEMIC PRESS, INC. (LONDON) LTD. Berkeley Square House, London W. 1

LIBRARY OR CONGRESS CATALOQ CARD NUMBER: 59-15761 Second Printing, 1972 PRINTED I N THE UNITED STATES OF AMERICA

Contributors t o Volume 9 Numbers in parentheses indicate the pages on which the authors’ contributions begin.

PAULW. ABRAHAMS, Courant Institute of Mathematical Sciences, New York University, New York, New York ( 5 1 ) A, S . BUCHMAN,Federal Systems Division, International Business Machines Corporation, Electronics Systems Center, Owego, New Yorlc (239)

AVIEZRIS . FRAENKEL,Department of Applied Mathematics, The Weizmann Institute of Science, Rehovot, Israel and Department of Mathematics, Bar Ilan University, Ramat Gan, Israel (113)

L. J. KOCZELA, Autonetics Division, North American Rockwell Corporation, Anaheim, California (285) JOHNMCLEOD, Simulation Councils, Inc., L a Jolla, California (23) W. J. POPPELBAUM, Department of Computer Science, University of Illinois, Urbana, Illinois (1)

L. M. SPANDORFER, Sperry Rand Corporation, UNIVACDivision, Philadelphia, Pennsylvunia (179)

This Page Intentionally Left Blank

Preface

There is a seductive fascination in software. There is a pride of accomplishment in getting a program to run on a digital computer, a feeling of the mastery of man over machine. And there is a wealth of human pleasure in such mental exercises as the manipulation of symbols, the invention of new languages for new fields of problem solving, the derivation of new algorithms and techniques, the allocation of memory between core and disk -mental exercises that bear a strong resemblance to such popular pastimes as fitting together the pieces of a jigsaw puzzle, filling out a crossword puzzle, or solving a mathematical brainteaser of widely familiar variety. And what is more, digital computer programming is an individual skill, and one which is relatively easy to learn; according to Fred Gruenberger, “the student of computing can be brought to the boundaries of the art very quickly. . . . It is becoming commonplace for to-day’s students to write new compilers . . . the beginning student of computing can be involved with real problems very early in his course.” [Commun. ACM 8, No. 6,348 ( 1965) .] All these factors help to account for the currently widespread popularity of programming. In contrast, the design of circuits and the production of computer hardware is a relatively mundane occupation, calling for years of education, fraught with perils and hazards, and generally demanding the joint efforts of a large team with a considerable diversity of skills. Similarly, the use of analog computers is considered equally mundane, even though analog machines are often faster and more versatile than digital computers in solving many important problems in engineering, management, biomedicine, and other fields. The more romantic appeal of software has led most of our universities and schools to overemphasize the computer and information sciences, to the relative neglect of computer engineering, and the almost complete disappearance of analog and hybrid devices, systems, and even course material from computer curricula. [See for example J . Eng. Educ. 58, 931-938( 1968).] Future advances in computer systems are at least as dependent on the full range of analog, digital, and hybrid hardware and techniques as they are on digital software. Future advances in computer applications demand a broader based familiarity and more comprehensive skill with the full complement of tools at our disposal and not just an ability to write isolated digital computer software. In keeping with our past philosophy and practice, the current volume of “Advances in Computers” continues to recognize vi i

viii

PREFACE

this broader based need and again presents a highly diversified menu of articles on analog and digital hardware, software, and applications, each with its own copious bibliography. There are two articles on computer hardware. The opening article by W. J. Poppelbaum describes a number of new devices based upon recently discovered technological effects. These include new computer organizations based upon arrays of computers and stochastic machines, new memory devices using optical holographs and ratchet storage cells, and new circuit techniques that stem from stochastic signal representation. L. M. Spandorfer discusses recent developments in producing integrated circuits whereby a plurality of circuits are mounted on an almost microscopically small silicon chip. The many implications for low cost, low power computers and memories of miniature size are investigated in considerable detail, and the various competing integrated circuit approaches are evaluated for relative reliability and applicability to computers. There are two articles on software. In his article on symbol manipulation languages, Paul W. Abraham defines symbol manipulation as a branch of computing concerned with the manipulation of unpredictably structured data. He then traces the development of such languages from IPL-V through LISP, L6, PL/l, SLIP,SNOBOL,COMIT, and EOL, with comments on their relative capabilities, advantages, and disadvantages. In his article on legal document retrieval, Aviezri S. Fraenkel examines the pros and cons of a number of retrieval systems, both with and without indexing, and evaluates them in light of his general conclusion: that present-day computers are potentially very efficient for problems which can be formulated well, but they are rather clumsy in heuristic problem solving. Legal literature searching still falls largely in the latter category but the computer can provide certain types of assistance. There are two articles on computer systems, both oriented to aerospace computation. L. J. Koczela presents the results of a research study of advanced multiprocessor organizational concepts for future space mission applications, with particular emphasis on a “distributed processor” organization that provides a very high tolerance of failures. A. S. Buchman reviews the special-purpose computers that have been used in space vehicles to date and looks forward to the future systems that must be designed to meet ever-growing space needs for performance and high availability. And last but not least, there is an article on hybrid computers and their ro!e in simulation. Because of his own background and experience, John McLeod writes his article in the setting of physiological simulation, but his comments on simulation attributes, complexity, adaptability, noise, hardware, and software are equally relevant to all areas of hybrid computer application. December, I968

MORRISRUBINOFF

Contents

CONTRIBUTORS PREFACE CONTENTSOF PREVIOUS VOLUMES

V

.

vii

xii

What Next in Computer Technology? W. J. Poppelbaum

1. 2. 3. 4. 5. 6.

Plan for Projections . . Limits on Size and Speeds of Devices, Circuits, and Systems New Devices New Circuits New Memories . New Systems . References .

1 2 6 8 12 17 20

Advances in Simulation John McLeod

1. Introduction 2. A LookBack . 3. Progress . 4. The Best Tool . 5. Physiological Simulation 6. ALook Ahead . References .

23 24 26 30 33

.

45 49

Symbol Manipulation Languages Paul W. Abrahams

1. What Is Symbol Manipulation? 2. LISP 2 3. LISP 1.5

.

lx

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51 57 69

CONTENTS

X

4. 5. 6. 7. 8. 9.

L6 . PL/I String and List Processing

.

SLIP . SNOBOL Other Symbol Manipulation Languages Concluding Remarks . References .

.

74 78 84 92 101 109 110

Legal Information Retrieval Aviezri S. Fraenkel

1. 2. 3. 4.

Problems and Concepts . Retrieval with Indexing Retrieval without Indexing Projects Appendix I Appendix I1 Appendix I11 . References .

114 121 128 150 158 161 163 172

Large Scale Integration--an Appraisal L. M. Spandorfer

1. 2. 3. 4. 5. 6. 7. 8. 9.

Introduction Device Fabrication Packaging . Economic Considerations , Interconnection Strategies . Bipolar Circuits . Mos Circuits LSI Memories Further System Implications . References .

179 180 184 190 194 205 213 218 231 2 34

Aerospace Computers A. S. Buchman

1. Introduction 2. Application Requirements

.

239 241

xi

CONTENTS

3. Technologies 4. Current State-of-the-Art

5. Aerospace Computers of the Future References

.

. . . .

262 269 274 283

. . . . . . . .

286 289 295

.

326 338 346 349 353

. .

355 360

The Distributed Processor Organization L. J. Koczela

1. Introduction

2. Parallelism . 3. Development of the Distributed Processor Organization 4. Architecture 5. Failure Detection and Reconfiguration . . 6. Cell and Group Switch Design 7. Communication Buses . a. Software Analysis References . AUTHOR INDEX INDEX SUBJECT

301

Contents of Previous Volumes Volume 1 General-Purpose Programming for Business Applications CALVXK C. GOTLIEB Numerical Weather Prediction NORMAN A. PHILLIPS The Present Status of Automatic Translation of Languages YEHOSHUA BAR-HILLEL Programming Computers to Play Games ARTHURL. SAMUEL Mechine Recognition of Spoken Words RICHARDFATEHCHAND Binary Arithmetic GEORQEW. REITWIESNER

Volume 2 A Survey of Numerical Methods for Parabolic Differential Equations JIM DOUGLAS,JR. Advances in Orthonormalizing Computation PHILIPJ. DAVIS AND PHILIPRABINOWITZ Microele&ronics Using Electron-Beam- Activated Machining Techniques KENNETHR. SHOULDERS Recent Developments in Linear Programming SAULI. GASS Th9 Theory of Automata, a Survey ROBERT MCNAUGHTON

Volume 3 The Computation of Satellite Orbit Trajectories SAMUEL D. CONTE Multiprogramming E.F. CODD Recent Developments of Nonlinear P r o g r p d f PHILIPWOLFE Alternating Direction Implicit Methods , DAVIDYOUNG GARRETTBIRKHOFF,RICHARDS. V ~ AAND Combined AnalogDigital Techniques in Simulation HAROLD K. SXRAMSTAD Information Technology and the Law REEDC. LAWLOR

Volume 4 The Formulation of Data Processing Problems for Computers WILLIAMC. MCGEE All-Magnetic Circuit Techniques DAVIDR. BENNIONAND H E W ID.~ CRANE

CONTENTS OF PREVIOUS VOLUMES Computer Education E. TOMPKINS HOWARD Digital Fluid Logic Elements H. H. G L A E ~ L I Multiple Computer Systems WILLIAMA. CURTIN

Volume 5 The Role of Computers in Election Night Broadcasting JACK MOSHMAN Some Results of Research on Automatic Programming in Eastern Europe WLADYSLAW TURSKI A Discussion of Artificial Intelligence and Self-Organization GORDON PASK Automatic Optical Design ORESTES N. STAVROUDIS Computing Problems and Methods in X-Ray Crystallography CHARLESL. COULTER Digital Computers in Nuclear Reactor Design ELIZABETH CUTHILL An Introduction to Procedure-Oriented Languages HARRYD. HUSKEY

Volume 6 Information Retrieval CLAUDEE. WALSTON Speculations Concerning the First Ultraintelligent Machine IRVING JOHN GOOD Digital Training Devices CHARLES R. WICKMAN Number Systems and Arithmetic HARVEY L. GARNER Considerations on Man versus Machine for Space Probing P. L. BARGELLINI Data Collection and Reduction for Nuclear Particle Trace Detectors HEREZERT GELERNTER

Volume 7 Highly Parallel Information Proceasing Systems JOHN C. MURTK~ Programming Language Processors RUTHM. DAVIS The Man-Machine Combination for Computer-Assisted Copy Editing WAYNEA. DANIELSON Computer-Aided Typesetting WILLIAM R. BOZMAN Programming Languages for Computationd Linguistics ARNOLD C. SATTERTHWAIT Computer Driven Displays and Their Use in Man/MachineInteraction ANDRIES VAN DAM

xiii

xiv

CONTENTS

OF PREVIOUS VOLUMES

VoIume 8 Time-shared Computer Systems THOMAS S . PYKE, JR. Formula Manipulation by Computer JEANE,SAMMET Standards for Computers and Information Processing T. B. STEEL,JR. Syntactic Analysis of Natural Languagc NAOMI SAGER Programming Languages and Computers: A Unlfied Metathcory R. SARASIMHAN Incremental Computation LIONELLO A. LOMBARD1

What Next in Computer Technology? W. J. POPPELBAUM Department of Computer Science University of Illinois, Urbana, lllinois

1. Plan for Projections . 2. Limits on Size and Speeds for Devices, Circuits, and Systems 3. New Devices . 4. New Circuits . 5. New Memories . 6. New Systems . References .

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1. Plan for Projections

Before setting out on our tour of extrapolated hardware technology, it is perhaps useful to lay down and discuss the principles of such aq operation. All too often the thin line between reasonable guessing and wild science fiction is transgressed because of the ignorance of certain fundamental principles of physics which set a severe limitation t o the attainable performance figures. Section 2 will therefore discuss the physical limitations on size and speed of processing elements and systems. Section 3 will examine devices of novel configuration which have already seen prototype realization. All of them use phenomena which are well known but have not been utilized. We shall not describe devices based on recently discovered effects such as the Gunn negative differential mobility effect [3, #]; such devices are obviously one order removed from the linear extrapolation which is the basis of our forecast. In Section 4 we will examine circuit techniques that have emerged in the area of hybrid analog-digital processing and stochastic signal representation. Again these techniques have proved themselves on a laboratory scale but are only on the point of being used in practical applications. Section 5 examines the outlook in the memory field. Here it is not a. question of discussing whether or not semiconductor memories will become preponderant, but when this type of memory will become more attractive than the magnetic kind. But above and beyond semiconductor I

2

W. J. POPPELBAUM

memories we shall consider such newcomers as high-density optical stores operating in the holographic mode and ratchet storage cells for analog variables. The final section will be devoted to some non-von Neumann machine organizations, ranging from array computers to stochastic machines and intelligent display devices. The relative conservatism of the devices, circuits, and systems under discussion should be attributed not to an unwillingness to consider far-out ideas, but rather as a proof that one can remain with one’s feet on the ground and yet discuss techniques which were virtually unknown a few years ago. 2. Limits on Size and Speeds of Devices, Circuits, and Systems

We shall first discuss the ultimate limitations of speed and size set by the atomic nature of our storage media. To this end we are going to use rather approximate physics. Figure 1 shows a cube containing n3 atoms used as a model of a flip-flop. The two states might, for instance, correspond to all the spins being straight up or straight down. Let us call a the atomic spacing, i.e., the lattice constant. The thermal energy which is inside this little cube at temperature T is approximately n3kT where k is Boltzmann’s constant: This thermal energy could be considered a sort of noise energy. When we want to store information inside the cube, we must inject into it or take out of it energies which are at least of the order of this noise energy. Let us suppose that in order to inject or subtract this energy, AE =n3kT, we have available a time At. Quantum mechanics tells us that the product AE - At cannot be made smaller than h / h , where h is Planck’s constant. Assuming that in the limiting case we have equality and that At =na/c where c is the speed of light (because the information will have to travel at least to the opposite face of the cube and the speed does not exceed that of light) we can obtain an estimate of n, and this turns out to be approximately 102 atoms. This in turn gives us for At about 10-16 sec and for the number of bits sorted B about 1021 per cubic foot. Finally, if we want to keep the dissipation inside this cubic foot to approximately 100 W, the duty cycle for any given bit is 10-5 accesses per second, i.e., approximately one access every 30 hr. Having thus determined the ultimate limitations in size and speed, it is useful to consider what exactly is gained by microminiaturization. Figure 2 shows time as a function of size. There are three types of times which we have to consider when we look at a system consisting of many devices connected together. First, there are times resulting from delays in the devices. One can characterize them by giving the

WHAT NEXT IN COMPUTER TECHNOLOGY?

3

density of carriers (holes or electrons) PO and the distance w that the carriers have to travel across some critical zone, e.g., the base width of a $ransistor. The average drift speed of the carriers, b, is proportional to po/w and consequently the drift time T d is proportional to wZ/po. The second time delay is that necessary to travel from one device to another device at a distance w at approximately the speed of light. The delay caused by this is rt and is given by wlc.

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NB. OF LAYERS:

-

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BITS STORED:

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102' per cu 11

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FIG.1. The ultimate limitations. The influence of high energy cosmic particles is neglected.

The third time we have to consider is the Resistance-Capacitance (RC) rise time inside the semiconductor material. Reasonable approximations for both the capacitance and resistance for a slab of area S and of thickness w show that T R C is equal to PE where p is the resistivity and E is the dielectric constant. Note now that 71 decreases very rapidly as the size w goes down,

4

W.

J. PQPPELBAUM

while rt only decreases linearly and T R C does not decrease at all. It is therefore entirely unwarranted to assume that microminiaturization will ultimately solve all speed problems: It will be necessary to supplement it with considerable redesign of the circuits themselves.

DEVICE‘TIMES:

TRANSMISSION TIMES:

I-

W

RC

- TIMES: 1

s

I

I

FIG.2. Time as a function of size.

At this point, it might be good to remind ourselves that we must supplement the discussion of physical limitations with the criterion of practicability. Figure 3 shows a succession of criteria that a typical device has to meet in order to appear on the market. Among these criteria are some additional physical limitations in the form of due respect to such principles as the conservation of energy and momentum and the finite speed of signal propagation, but beyond these evident limitations we have the group which could be called the technology group: Here we ask such questions as: Is it reliable? Does it have sufficient speed? Is the device reproducible? This group of questions is followed by the questions about blending with other technologies

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COST 0 0 0

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OUT FIELDS

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FIG.3. Additional criteria for devices.

6

W. J. POPPELBAUM

available at this time : Large-scale integration, compatibility of signal levels and, finally, such mundane questions as cost. It is interesting to note that the spectacular demise of the tunnel diode is due to its failure in two directions. First, it could not be produced by integrated circuit techniques, and second, its nonlinear behavior could not be matched to transmission lines which were necessary if its high speed were to be useful. 3. N e w Devices

Until quite recently active semiconductor devices were based on the injection of minority carriers through a junction (in either Boltzmann or tunneling mode) or on the control of carrier density or channel width by appropriate electric fields. Of late, a new device has appeared which seems to have some very attractive properties, especially in the area of high current switching and memory action; this is the Ovonic Threshold Switch, also called QUANTROL [5]. This device uses simultaneous injection of holes and electrons, conserving therefore spacecharged neutrality for very high current densities. What is more, this double injection device (see Fig. 4) can be built out of amorphous semiconductor material, i.e., does not necessitate monocrystalline configurations. This, however, is a minor advantage compared to that of JUNCTION DIODE

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RECOMBINATION LIMITED CURRENT

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2.

HIGH IMPEDANCE -3 RECOMBINATION LIMITED CURRENT.

3.

LOW IMPEDANCECURRENTS OVERRIDING RECOMBINATION.

n

P

*

PHASE CHANGE INDUCED BY FIELD ( MODIFIED X-RAY DIFFRACTION )

FIG.4. Amorphous semiconductor devices.

7

WHAT NEXT IN COMPUTER TECHNOLOGY?

being easily modified to have memory action in the absence of applied potentials. This memory is due to a phase change which can be induced by high enough fields. This phase change corresponds to a modification of the electronic cloud around certain atoms and can be made visible by X-ray diffraction methods. Visibly, the latter device is exceedingly attractive because the absence of volatility would make possible such things as a semiconductor analog of magnetized spots. Here, however, static readout is easy. Finally, it should be mentioned that these devices do not operate in an avalanche mode as witnessed by the fact that they can be cycled in fractions of a microsecond. TO PUMP

CONOUCTING ANO TRANSPARENT FILM

LINEARLY POLARIZED LIGHT

I

CROSSED ANALYZER PRINC. DIR. I

COMPONENT I AT SPEED v ,

PRIM. MR. 2

COMPONENT 2 AT SPEEO V *

FIG.6. Ardenne tube.

A device which has suddenly become of great importance, especially for those interested in electrooptics, is the so-called Ardenne tube shown in Fig. 5. This is the answer to our search for “instant negatives.” In some sense, therefore, we are talking about a highly specialized memory device and it would have been possible to include the Ardenne tube in Section 5. The device aspects are, however, preponderant, as is easily seen from the figure. The heart of the Ardenne tube [I,121, is a KDP crystal charged up by an electron beam, the intensity of which is controlled by a video signal. The charge distribution sets up local electric fields in a crystal of KDP which produce a difference between

8

W. J. POPPELBAUM

the phase velocities v 1 and v 2 along the principal directions. When linearly polarized light hits the crystal, it will be decomposed into components 1 and 2, chosen to be equally inclined with respect to the incident light. When the light emerges, its state of polarization has changed, being typically elliptical, and a filtering action can be obtained by an analyzer passing only vibrations perpendicular to those of the incident beam. The net result is that an eye to the right of the analyzer sees light roughly in proportion to the charge density deposited at each point of the crystal. The immediate usefulness of the Ardenne tube (also-called Pockels’ effect chamber) is evident when we consider that it is now possible to produce a transparency in the time that it takes to sweep out one video frame and that, furthermore, the surface can be prepared for new information by the simple expedient of erasing all charges with a flood gun. Presently the Ardenne tube is used in large screen television projection and in the control of directive lasers. Future applications will include the formation of interference patterns and holograms from charge patterns deposited on the KDP. A last example of a novel device presently being considered is the creep vidicon, shown in Fig. 6. This is a modification of the standard vidicon in which the photosensitive plate is made continuous rather than being a discontinuous mosaic. The purpose of this device is to detect electrically the “inside” of a complicated closed curve. The principle is to choose the semiconductor plate of such a resistivity that the dark resistance of those regions having a boundary projected on them is nearly infinite while the resistance of the illuminated regions is very low. This, then, separates conducting islands from each other in such a way that a charge deposited in an arbitrary point of such an island spreads uniformly and produces a uniform potential for all inside points. A subsequent video scan of the whole plate allows one to measure this potential and to discriminate via the beam current “ inside ’) and “outside.” That such a creep vidicon is useful to the highest degree is apparent when one considers the fact that even fast digital computers run into considerable trouble when the “ inside/outside question )’ has to be decided in a hurry. On-line operation of computers is virtually ruled out. The device can solve easily command and control problems like the one of coloring the inside of a region indicated by its boundary on a tricolor tube. 4. N e w Circuits

circuitry trend that should be followed with great attention is the more intimate mixing of digital and analog signals in hybrid processors. Up to now such processors have generally consisted of a digital and

LIGHT SENSITIVE SEMICONDUCTOR PLATE

CONDUCTING (ILLUMINATED) ISLAND, ISOLATED BY INSULATING ( D A R K ) BOUNDARIES

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0 DEPOSITED INSIDE

LIGHT

BY ELECTRON GUN SPREADS AND PRODUCES EVEN V FOR WHOLE ISLAND

SCANNING RECOGNIZES V AND ANSWERS INSIDE /OUTSIDE QUESTION.

FIG.6. Creep vidicon.

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W. J. POPPELBAUM

analog computer coupled together by a converter interface: This is not what is meant by a hybrid machine in our sense. We feel that a true hybrid machine should consist of a set of circuits in which the information signal is analog in nature while the steering signals are digital. Of course, the analog processing must be made very fast in order to compete speedwise with high-speed digital processing. To process analog signals with rise and fall times of the order of 100 nsec one must give in on the precision requirements. I t is, however, not too difficult to build circuits in which the output differs by less than 0.1% from the theoretical output. The way in which high speed is bought is to forgo very high gain amplifiers and strong feedback and to limit oneself to circuits which are linear enough without using phase shifting loops. Figure 7 shows a typical hybrid circuit in which a constant current SENSITIVITY t2SV 3.3K

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difference amplifier operates a digital output via some collector logic. It is easy to see that the output is high only when the analog voltages are of nearly the same magnitude, the exact width of the overlap zone being controlled by the sensitivity input. Such a circuit is evidently useful whenever an electrical table lookup is required. Figure 8 shows a small hybrid machine called PARAMATRIX 181 in which incoming graphical information is digitized, normalized in size and position, and finally improved by filling in gaps and averaging out cloudy regions. In the operation of this system a clock scans through the output matrix (in the center of the photograph) remaining approximately 1 psec on each one of the 1024 points. The inverse transform of the

WHAT NEXT IN COMPUTER TECHNOLOGY?

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coordinates in the matrix is formed, and a high-speed scanner is positioned to answer within this time slot of 1 psec the question: Is the inverse transform on the input slide or not? A more ambitious machine -ARTRIX [Yl-has been built in which graphical information is processed in such a way that, while the data are on their way from one graphical memory to another (each memory consists of a memotronvidicon pair), we can draw lines and circles, label figures, and erase portions thereof.

FIG.8. PARAMATRIX.

The availability of a compatible set of hybrid circuits makes the design of special-purpose computers using direct analog inputs attractive for those cases in which cost can be diminished and speed improved by so doing. These cases include systems in which both input and output are analog in nature and in which the processing loop is very short. It also includes preprocessors for visual or audio information in which the on-line operation of very fast analog circuitry can save enormous amounts of time to the central computer. It is not too hard to forsee

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W. J. POPPELBAUM

that integrated circuits of the hybrid type will be available in the near future with 0.1O; precision and a bandwidth of over 50 Mc. Another area in which low precision demands can be taken advantage of is that of stochastic computers [Z, 9,101. In these, pulses of standardized shape are generated with an average frequency proportional to the variable to be transmitted. Figure 9 shows a method for producing such random pulse sequences with the additional condition that a pulse, should it occur, must occur within a given time slot. The principle is to compare the output of a noise diode with the voltage v representing the variable, to reshape the output of the threshold difference amplifier, and to clock the output of an appropriate shaping circuit by differentiating and reshaping the transient in a flip-flop, which is set to the " 0 " state a t a high rate by a clock. Figure 10 shows why the use of synchronous random pulse sequences is attractive in computation. The OR circuit forms visibly an output sequence in which the average frequency is proportional to the sum of the incoming average frequencies. Some difficulties arise when two input pulses occur in the same time slot, but this dificulty can be eliminated most easily by having " highly diluted " sequences. The formation of a product can be obtained equally simply by running the representative sequences into an AND circuit. Kote that no restandardization of pulses is necessary because of the appearance of the pulsesshould they appear-in fixed time slots. In Section 6 we shall discuss the implications of having available very low cost arithmetic units on systems design. A t this point it should be noted that there is a vast field in which such processing leads to entirely adequate precisions. Typically, we must wait 100 pulses for 10% precision, 10,000 pulses for 1% precision, and 1,000,000 pulses for O.ly& precision. With pulse repetition rates of the order of megacycles it is easily seen that we can equal the performance of the analog system discussed above within a small fraction of a second. On-line graphical processors would be a typical application for such stochastic circuitry, as would be array computers of considerable complexity in which each computing element is reduced to one integrated circuit performing limited precision arithmetic under the control of a central sequencer. 5. New Memories

One of the neglected areas of memory design is that of long-term analog storage. Such storage is usually both difficult and expensive as long as direct storage is contemplated. Indirect methods are usually based on the conversion of voltage to time but run into drift problems, which limit storage times to a few seconds. Of late it has been realized

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WHAT NEXT IN COMPUTER TECHNOLOGY?

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that indefinite storage can be obtained if we agree t o quantize the voltage to be stored. One way of doing this is shown in Fig. 11. I n this PHASTOR circuit [ 6 ] ,voltages are stored as the phase differences between the synchronized monostable generator and the subharmonic of a central clock. As can be seen from the figure, we have a simple multivibrator circuit in which the feedback loop contains a synchronizing input from the clock which makes sure that at the end of each oscillation

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FIG.10. Addit ion and multiplication using random sequences.

the timing is in step with it. It is obvious that if this clock has a period which is very short compared to the natural period of the monostable (practically 100 times smaller if 1% accuracy is required), the monostable is only able to lock into 100 different phase jumps with respect to the central muhivibrator used to generate the subharmonic 100. It should be noted that circuits like the above-so-called ratchet circuitscontradict the old theorem that in order to store n different numbers one needs logen flip-flops, i.e., 2 l o g 2 n transistors. It should also be noted that the gating in and out of a PHASTOR storage cell can be done bp purely digital means and that integrated circuit technology will make the price of such storage cells competitivc with those of simple binary cells. In the area of binary storage the forecast is curiously enough very simple if we extrapolate to the distant future. There is no doubt

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whatsoever that ultimately semiconductor storage cells in Large-Scale Integration (LSI) arrays will be cheap enough to replace magnetic memories of every kind. The great advantage of semiconductor storage is, of course, the very high output levels that can be obtained and its general compatibility with semiconductor logic. Whether these semiconductor memories will use bipolar or Metal-Oxide Semiconductor (MOS) techniques is not entirely clear, but now that micropower bipolar +25

FIG.11. PHASTOR storage cell.

circuits are available it does not seem excluded that the latter will triumph. The outlook for the immediate future, however, is much harder to assess because of late the plated wire memories (in which a magnetized mantle surrounds a substrate used as a sense wire) have reduced cost and increased speed to such an extent that magnetic memories will have a new lease on life, at least as far as relatively big units are concerned. To show how extremely elegant the semiconductor memories can be when read only designs are considered, Fig. 12 shows a design by Chung of Texas Instruments in which emitter followers are used a t the cross-points of a matrix with horizontal base driving lines for word selection and vertical digit lines connected to the emitters. By

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W. 1. POPPELBAUM

connecting or disconnecting the bases in a given row, a digit pattern can be stored permanently and readout, simply corresponds to a sample pulse injected into the word line which reads-via the digit lines-into the computer. Obviously, this system eliminates complicated sensing devices and is ideally suited to microminiaturization : Access times of the order of 20 nsec are easily attained. Sooner or later every computing system has to supplement random access (now magnetic, later semiconductor) memory by bulk storage of WORD n

WORD n + i

WORD n + 2

FIG.12. Read-only semiconductor memory (designed by Chung of Texas Instruments).

files with a low duty cycle and relatively long read and write times. Memories of this type have recently been made in optical form, and one of the most interesting is perhaps the holographic storage developed a t Carson Laboratories and shown in Fig. 13. Here a matrix of dots is stored in the form of a hologram inside a crystal using F-center techniques. Such crystals differ from the now abandoned photochromic substances in that the electronic configuration of atoms is modified by the incident light encountered. The crystal stores the interference pattern of a laser shining through the matrix of dots (some of which may not be transparent) and a reference beam emanating from the same laser. Reconstitution of the information is obtained by the classical holographic process. i.e., the crystal is examined in laser light occupying the same relative position as the reference beam. One of the advantages of this wave front storage is that many patterns can be superimposed

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by turning the crystal through a small angle between each additional storage operation. Rather exciting storage densities can thus be obtained.

INFORMATON BEAM

ROTATE BETWEEN EXPOSURES

HOLOGRAM 2

HOLOGRAM I

MIRROR

FIG.13. Holographic storage (Carson Laboratories).

6. New Systems

Most computing systems of the last two decades have had a fundamental structure proposed by von Neumann [ 1 3 ] ; i.e., they consist of a certain number of registers connected to a memory on one hand and to an arithmetic unit on the other with appropriate shuffling of numbers dictated by a control unit. It is a tribute to von Neumann’s genius that this arrangement should have become completely standard. The time has come, however, for computer designers to reassess the situation and to think in terms of arrangements in which either the memory and processing functions are more intimately connected or in which there is a very strong parallelism even to the extent of having hundreds of arithmetic units. Finally, it has become mandatory to think again in terms of organizations for specialized computers, in particular those connected with input-output problems. Figure 14 shows, rather symbolically, the layout of an array computer. The idea here is to have a great number of processing elements with considerable autonomy and local storage under the direction of both a (micro-) and an over-all (macro-) control. The advantages of such an array are evidently the possibility of parallel access to all elements for preprocessing purposes, and the facility of connecting the elements together for processing which involves exchanging of information between all of the registers and all of the arithmetic units.

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W. 1. POPPELBAUM

The well-known example of such a highly parallel array computer is ILLIACIV [I]],in which 256 processing elements are used. Here each processing element consists of over 10,000 gates, i.e., has the capability of ILLIACI (but, of course, a much higher speed). Another waj- of realizing the layout of Fig. 14 is to replace each processing element by a general computing element made on one integrated circuit wafer using stochastic techniques. The fantastic reduction in cost (since each element would contain less than 30 I

I

I

MACROCONTROL 1TYPICAL)

--

i-I, j

~-I,J+I

--

--Q----Q+i+l,j-l

i+l, j

I

I

1

I

i+l,j+ I

I

Fro. 14. Array computer (fixed interconnection to nearest neighbors). A11 Processing Element (PE) inputs and outputs can be used as inputs and outputs to the array. Each PE has local (microprogram) and over-all (macroprogram) control facilities. Some local memory is provided.

junctions) is, of course, bought by a considerable decrease in precision or, to be more exact, by having to wait for a reasonable time until the array has processed a high enough number of pulses to give the desired precision. As mentioned before, there are many applications in which such an array . -odd be very useful. Another attractive application of stochastic computer elements is shown in Fig. 15 which represents a graphical processor with a highly parallel structure [9]. On the left is an n x n input matrix with the wire in position ( i , j )carrying a signal in the form of a random pulse sequence called xtj . One could imagine that these signals are generated from photodiodes which receive an incoming picture and have noise

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amplitudes which vary with the incident light. Using simple AND and OR circuits, let us now form output signals Y k l , where (k,I ) are the coordinates in an n x n matrix such that

After addition of a constant term a k l we can consider the above function as the linear portion of the expansion of the most general function of all such xti’s. I n forming this function and displaying the

FIG. 15. TRANSFORMATRIX: (a)input matrix (used in parallel), (b) coefficient matrix (used frame by frame), and (c) output matrix (produced sequentially),

output as a picture, we obviously produce an image mapping from input to output described by 124 coefficients b m j and encompassing therefore translations, rotations, magnifications, conformal mappings, convolutions, and Fourier transforms. In order to define which one of the above transformations we desire, it is necessary to specify all coefficients b k l g j , and this will have to be done by a control unit. The core of the input-output plus processing unit ” is, however, a complex of n4 AND circuits, a. number which can be reduced to 2n2 if sequential operation is contemplated for each one of the output points. It is clear that such an on-line general graphical transformer would be of great usefulness. I n the area of specialized organizations we can consider the one shown in Fig. 16: the so-called POTENTIOMATRIX. This is a modern analog of the electrolytic trough. A matrix of discrete resistors imitates the behavior of a continuous conducting sheet, and potential islands are defined by forcing certain groups of nodes into fixed potential states via electronic switches. All nodes are connected to a bus bar via sensing ‘I

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W. J. POPPELBAUM

elements consisting of a small light which comes on whenever node and bus bar have the same potential. Ultimately, of course, such an array would be made in continuous fashion using electroluminescent panels with built-in comparator amplifiers. When the bus is stepped from the potential of the first island to the potential of the second one, the nodes

I

I

BUS

lying on equipotential lines will be displayed in succession. It might be noted that such an " intelligent display " is capable of generating curves of considerable complication from a small number of input variables: For conical sections we only have to remind ourselves that they are equipotential lines in a field in which the potential islands are a directrix and a focal point. REFERENCES 1 . Calucci. E., Solid state light valve study, Inform. Display, p. 18 (March/ April 1965). 2. Gaines, B. H., Stochastic computer thrives on noise, Electronics 40, 72-79 ( 1967).

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3. Gunn, J. B., Instabilities of current in 111-V semiconductors. I B M J . Rea. Develop. 8, 141 (1964). 4 . Kroemer, H., Theory of Gunn effect. Proc. IEEE 52, 1736 (1964). 5. Ovshinsky, S. R., Ovonic switching devices. Proc. Intern. Colloq. Amorphous and Liquid Semicond. Bucharest, Rumania, 1967. 6 . Poppelbaum, W. J., and Aspinall, D., The Phastor, a simple analog storage element. Computer Technol. Conf ., Manchester, July 1967. 7 . Poppelbaum, W. J., Hybrid graphical processors. Computer Technol. Conf., Manchmter, July, 1967. 8 . Poppelbaum, W. J., Faiman, M., and Carr, E., Paramatrix puts digital computer in analog picture and vice versa. Electronics. 40, 99-108 (1967). 9. Poppelbaum, W. J., Afuso, C., and Esch, J. W., Stochastic computing elements and systems. Proc. Fall Joint Computer Conf., 1967. 10. Ribeiro, S. T., Random-pulse machines. IEEE Trans. Electron. Computers 16, (1967). 11. Slotnick, D., ILLIAC IV. IEEE Trans. Electron. Computers 8 (1968). 12. Von Ardenne, M., Tabellen der Elektronenphysik, Ionenphyaik unsl obermikroskopie, Vol. 1, p. 202, Deut. Verlag. Wiss., Berlin, 1956. 13. von Neumann, J . , Collected Works. Macmillan, New York, 1963.

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Advances in Simulation JOHN McLEOD Sirnulotion Councils, Inc. Lo lollo, Cdifornio

1. Introduction 1.1 Simulation-a Definition . 2. A LookBack . . 2.1 1943andOn . 2.2 Hybrid Simulation-a Definition . 3. Progress . 3.1 Analog Hardware 3.2 Analog/Digital Communications . 3.3 Digital Software-CSSL 3.4 The Price . 3.5 Simulation for Model Development 4. The Best Tool . . 4.1 Analog Advantages . . 4.2 Digital Advantages . 4.3 Hybrid Advantages . . 4.4 Typical Appiications 4.5 Benchmark Problems . 5. Physiological Simulation . . 5.1 System Characteristics 5.2 Attributes of Simulation . 5.3 Complexity and Simplification . . 5.4 Adaptability and Its Control 5.5 Measurement Facilitated . . 5.6 Noise and Its Control 5.7 A Hybrid Example . . 6. ALook Ahead . 6.1 New Fields . . 6.2 Analog Hardware . 6.3 Analog Software 6.4 Digital Computers . 6.5 Toward Greater Hybridization 6.6 The Large Systems . 6.7 The Future of Simulation . . References

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1. Introduction

Although progress in simulation is not directly dependent on progress in computers, the two are certainly closely related. Analog, digital, and hybrid electronic computers are the tools of the simulation tradethe best ones we have found to date, by a good margin.

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Computers, in the broad sense, can do many other things. Analog computers can draw pictures, and digital computers can keep books. (“Accurate” t.o an unlimited number of significant digits, if one is really that concerned.) But important as they are, these related uses of computers will only be given a nod of recognition by this chronicler as he turns his attention, and the reader’s, to simulation. 1.1 Simulation-a

Definition

As used in this article, simulation is “the development and use of models to synthesize, analyze, and study the dynamic behavior of actual or hypothesized real-life systems.” Note that computers are not mentioned. But as already stated, computers are the best tools we have yet found for simulation; therefore, this discussion will be limited to computer simulation exclusively. 2. A Look Back

2.1 1943 and O n

Computer, or at least electronic circuit, simulation began as early as 1943 with a study of the dynamics of aircraft and guided bombs [15]. After World War II, analog computers-or electronic differential analyzers or simulators, as they were variously called-began to emerge from the shadow of security classification. A t first they were used primarily for the simulation of guided missiles as well as aircraft, but with the advent of the space age they were ready to simulate thingspeople, devices, environments, situations-which were literally ‘‘ out of this world.’’ The writer met his first ‘‘ simulator ” in the winter of 1949-50, when a large and-according to the bill of lading-very expensive box arrived at the Naval Air Missile Test Center at Point Mugu, California, identified as a Lark Simulator. Advances in simulation from that eventful date until the end of 1961 followed the usual slow-starting exponential growth pattern and are covered, to the best of this writer’s ability, in a previous article [lo].The birth and childhood of simulation will not be reiterated here. Instead, the author would direct attention to the adolescence of the past few years and the current coming of age of simulation. It was during this period that hybrid simulation began to come into its own, an event that may be largely credited for simulation’s recent maturation. Hybrid simulation has suffered from overambitious parents. Analog

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and digital simulation are genetically unrelated; therefore, having common aims in life, it should have been perfectly natural and proper for them to marry and proliferate. But their parents-and friends-tried to force a marriage before they were mature enough. That was about 1956. Yet in spite of dire predictions analog simulation has survived, digital simulation is beginning to live up to expectations, and the grandchildren, hardy mongrels or hybrids that they are, are exhibiting many of the characteristics of gifted children. To be more specific, in the era 1955-62, attempts were made to combine the advantages of analog and digital computers to produce a better tool for simulation, but the timing was wrong and the philosophy more attractive than it was sound. The analog-to-digital, digital-toanalog hardware necessary for combined (married) simulation (as distinct from hybrid simulation, the offspring)was simply not good enough. The conversion-equipmentvendors were pushing the state-of-the-art too hard. The problem was philosophically skewed by wishful thinking. Anyone should have realized that disadvantages would combine as readily as advantages. To be sure, combined simulation did-to the extent allowed by the interface equipment-permit the speed of the analog to be combined with the precision of the digital computers. But the low accuracy of the analog computer also combined with the relatively slow speed of the digital. It was only through clever programming to alleviate these problems that combined simulation survived. Now we have hybrid simulation, which is in want of a generally accepted definition. There are those who maintain that if all the variables in a simulation are represented by continuous signals, the simulation is analog, no matter how much digital equipment may be used to program, set up, control, and monitor the analog. At the other extreme are those who consider any simulation in which both discrete and continuous signals are involved in any way to be hybrid. So again the author offers a definition which is valid within the context of this article. 2.2 Hybrid Simulation-a

Definition

“A hybrid simulation is one in which the variables of the simuland, the real-life system being simulated, are represented by both continuous and discrete signals.” Having defined “ simulation ” and “ hybrid,” we can now turn our attention to “ advances ”: those improvements in hardware and software which, meshing like the teeth of gears, deIiver the power required to advance the state-of-the-art of computer simulation.

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3. Progress 3.1 Analog Hardware

As previously indicated, most analog computers have married and changed their name, but some “ pure ” analogs are still being produced, mostly as pedagogical or special-purpose computers. But advances in analog hardware as used in combined and hybrid systems are profoundly influencing advances in simulation [ S ] . The most important of these advances stem from the complete shift to improved solid-state electronics resulting in improved accuracy, increased speed, and greater reliability. Because relatively low accuracy and reputedly poor reliability of analog components have been used as arguments against their use, both as analog computers and as components in hybrid systems, the importance of marked improvements in these will be recognized. But how about speed? Speed has always been the analog’s strong point. With equivalent electronics, an analog computer operating in parallel will always be orders of magnitude faster than a digital machine constrained to operate in series. And speed is important because it makes it possible as well as economically expedient to simulate some kinds of systems and solve some classes of problems in faster-than-real-time. Sometimes running in faster-than-real-time may be desirable for purely economic reasons; for instance, in stochastic processes, where many thousands of runs may be required to produce statistically significant results, or in multivariable optimization problems, which also require many runs. A t other times, faster-than-real-time operation may be a requirement imposed by the nature of the system simulated; for instance, in certain adaptive control schemes which require the model to be run at many times the speed of the system to be controlled, or for predictive displays which show the consequences of current action a t some time in the future, or with some techniques for the solution of partial differential equations when the results are required for a simulation operating in real time. 3.2 Analog/Digital Communications

However. speed is not the only reason for using analog hardware with digital equipment to create hybrid computing systems. No matter how man may operate a t the microscopic neuron-synapse level, he communicates with his real-world environment in a continuous fashion. As a

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consequence, if he is to communicate with a digital computer, there must somewhere be a continuous-discrete-or analog-digital-interface. Perhaps partially for this reason, most of our real-life machines are continuous in their mode of operation. Therefore, because one must always pay, either in accuracy or complexity (usually in both) to change the form of information flow in a system (from continuous to discrete and/or vice versa), it is often convenient to avoid the issue by using only.an analog computer so that input, processing, and output can all be continuous. Again, if the man-machine communication only involves monitoring and controlling a digital computer, the simulation, may be all digital. On the other hand, if in the simuland, in the real-life system being simulated, the signal flow is through the man, the simulation is hybrid, even though all of the hardware is digital. In such cases, although it is possible to make the analog-digital interface physically coincident with the manmachine interface, this places the burden of conversion on the man. It is often more expedient to mechanize the analog-digital and digital-analog conversion. This moves the analog-digital interface to within the computing system, and results in a hybrid computing system as well as a hybrid simulation. What has been said of man-in-the-loop simulations also applies to real-world hardware-in-the-loop simulations if the hardware operates in a continuous rather than a discrete fashion. Thus, if it is desired to introduce an actual component-a transducer or servo, for instance-of the simuland into an otherwise digital simulation, there would still have to be an analog-digital interface, and the simulation would be hybrid. 3.3 Digital Software-CSSL

The development of digital languages for the simulation of both continuous and discrete systems was engendered and stimulated primarily by two factors: the ubiquity of the digital computer and the ebullience of its proponents. Many who had a need to simulate did not have access to an analog computer. Others who did have access to one did not appreciate its potential. Indeed, to the great majority the word computer was synonymous with digital computer. If they knew that such a thing as an analog computer existed, they probably did not understand it, in which case it was something to be avoided-no sense in showing one’s ignorance. Simulation languages have had an interesting history [3, 8,161. The first ones were developed to “make a digital computer feel like an analog.” [3]. Then there were many developed for special purposes (a frequent one being to obtain an advanced degree).

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JOHN McLEOD

Recently, an extensive effort has been made to consolidate past gains and give direction to future effort. In March 1965 a group of Simulation Council members organized the SCi Simulation Software Committee. Among its members were most of the developers of important digital languages for the simulation of continuous systems. They reviewed all available previous work and prepared specifications for a Continuous System Simulation Language (CSSL) [I71 which embodied all of the best features of previous languages that were considered compatible with the objectives of the Committee and appropriate in the light of the current state-of-the-art. Like its predecessors, CSSL is intended to allow an engineer or scientist to set up a digital simulation without dependence on an intermediary in the person of a programmer. The man with the problem need have no knowledge of digital computer programming per se; a knowledge of CSSL should be all that is necessary. Implicit in the design of all such languages is the requirement that they be easy to learn. Undoubtedly, CSSL in its present form will not be a final answer. Like FORTRAN, COBOL, and other higher order languages, it will have to be used and abused, reviewed and revised. But it is hoped that the specifications as published, although developed primarily to facilitate the simulation of continuous systems, will bring some order to the chaotic proliferation of simulation languages and give direction to future efforts. Perhaps by the time CSSL-IV is developed the language will have been modified to accommodate the simulation of discrete systems, and the simulation community will for the first time have a standard language. 3.4 The Price

Progress has been expensive, but high-performance aircraft, complex missiles costing in the millions, and space systems involving human lives have elevated simulation from a convenience to a necessity. The bill for the development of hardware and the time and effort required to improve the techniques had to be paid. The United States government, directly or indirectly, paid, and by the mid-sixties it was possible to put together quite sophisticated simulations of complete space systems [ 7 ] . The spillover into industry was slower than might have been expected. This was partially because the pressure in industry was not as great. In most cases there were other ways of doing the job. Furthermore, development costs had not been amortized; hardware was, to a profitoriented organization, well-nigh prohibitively expensive. Even the giants of industry, who had the need and could pay the price, were extremely cautious, as some of us discovered.

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Inspired by the success of the Simulation Councils organized in 1952, some of us with backgrounds in aerospace and automatic control tried in 1954 to organize the Industrial Analysis and Control Council. After two meetings [ I , 21, it folded. Nost prominent among the rocks and shoals that stove it in was the plaint, " I don't know enough about my process to simulate it." It was undoubtedly true that in most cases of interest these people did not understand their process well enough to sit down and develop a mathematical model which could be solved on a digital computer. What they did not seem to realize was that the analog computer is a powerful tool for use in the development of models. 3.5 Simulation for Model Development

The empirical approach to model development is a simple iterative procedure: attempt to build a computer model based on what is known and what is hypothesized concerning the simuland. Exercise the model by driving it with simulated inputs corresponding to those of the reallife system. Compare the outputs. If they differ, guess again. Or in more sophisticated terms, adjust your hypothesis. The forced and directed thinking which this requires will usually improve the hypothesis with each model simulation-model iteration. And the insight gained is in some cases as rewarding as the final simulation itself. An important advantage of simulation, and one which helps make the foregoing procedure feasible, is that the model can usually be much simpler than the real system. The simulation need resemble the simuland only to the extent necessary for the study at hand. Indeed, if a complex system were to be simulated in every detail it would, in some cases, be as difficult to study the model as the actual system. Even were this not so, there would still be powerful incentives to simulate. Many tests which would destroy human life or expensive hardware can be run with impunity on the simulated system. The ability to return to initial conditions if a simulated patient " dies ')or a plant " blows up " is clearly impossible in real life. And of course there are important systems which are not amenable to arbitrarily controlled experimentation, the national economy and the weather, for instance. Yet these unwieldy and complex systems are currently being simulated in some detail, and with a satisfactory degree of success, by using the empirical procedures described. In connection with the method recommended for development of a model of an incompletely understood system, the author is repeatedly asked if similar outputs resulting from similar inputs prove that the model is a valid analog of the system simulated. Rigorously, the answer

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is no. It is possible to have two black boxes (in this case the simuland and the simulation) which w i l l have the same transfer function but different internal dynamics. And it is not difficult to conceive of two systems reacting differently internally and yet producing the same kinds of outputs in response to a step or ramp or sinusoidal or any other given input. But it has been the author’s experience that the chances of the simulation outputs being the same as those of the simuland in response to step and ramp and sinusoidal and arbitrary inputs is very remote. In fact, if the model responds like the system modeled for all inputs of interest, then the model is adequate for the particular study at hand even if the internal dynamics are sufficiently different to make the simulation invalid for other studies. 4. The Best Tool

All too often the choice of the computer for a particular simulation must be made strictly on the basis of availability. This cannot be argued; certainly it is better to use a digital computer to develop a simulation which might be done better on an analog than not to simulate at all. Besides, both kinds of computers are so versatile that either can often be used for jobs which should be done on the other. But given a choice among analog, digital, or hybrid equipment, which should one choose? That depends on the job. It should be possible t o choose the best kind of computer by considering the advantages peculiar to each kind. 4.1 Analog Advantages

In general, analog computers have the following advantages: They are faster. The analogy between the computer simulation and the real-life simuland can be straightforward. Man-computer communication comes naturally. Inputs and outputs do not require quantizing and digitizing. The values of parameters and variables can be easily changed during operation, and the results of the change immediately observed. Being easy to program directly from block diagrams, they are a natural for simulation systems which can be diagrammed in block form, even if the mathematical description of the system is not known in detail. No “ software ” is required.

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4.2 Digital Advantages

Digital computers have quite different advantages: They can be as precise as one desires and can be made as accurate as time and input data will allow. The basic operation is counting, which to most people comes naturally. They handle logical operations exceedingly well. They have prodigious memories. Once set up and debugged, a problem or simulation can be removed, stored indefinitely, then replaced exactly as it was. With floating point machines, scaling is no problem. They are versatile, being able to handle mathematical, scientific, and business problems with equal facility. 4.3 Hybrid Advantages

In general, all of the advantages of hybrid computers (or hybrid facilities) are derived from the combination of the analog and digital elements (or computers) of which they are composed, but to these is added one additional prime advantage-versatility , Hybrid computers allow the user the flexibility required for optimum simulation of complex sirnulands. 4.4 Typical Applications

In the light of the foregoing, it is evident that analog, digital, and hybrid computers are all suitable for simulation, that each offers certain advantages to a potential user, that the choice is highly problemdependent, and that no rigorous procedure for choosing can be devised. However, a consideration of some typical simulations for which each kind of computer would seem to be the best choice may be helpful. 4.4.1 Analog

For the analog computer the typical simulations would be as follows: ( 1 ) simulations for classroom demonstrations, where the effect of changing parameters and variables can be dramatically illustrated; (2) simulation for system predesign, where the effects of various trade-offs can be set up and demonstrated “live ’’ for project review boards and the “ customer ”; (3) simulations involving, primarily, the solution of large sets of simultaneous differential equations wherein high speed is more important than great precision;

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(4) simulations requiring empirical development because there is insufficient a priori information to support the detailed design of a mathematical model; ( 5 ) simulation of stochastic systems where a large number of iterations (probably controlled by binary logic) are required to obtain statistically significant solutions; and ( 6 ) where intimate man-computer rapport is an overriding consideration.

4.4.2 Digital

For the digital computer the simulations would be as follows: (1) the simulation of discrete systems such as the economy and traffic flow; (2) the simulation of continuous systems if: (a) there is an overriding requirement for high accuracy; (b) there is no requirement for real-time simulation, or if the problem is such that the speed-accuracy trade-off will allow real-time operation; (c) the mathematics involves, primarily, algebraic equations and logical decisions; and (d) suitable software is available.

4.4.3 Hybrid For the hybrid computer the simulations would be as follows: (1) simulations where the information flow in the simuland is both continuous and discrete; (2) simulations in which the over-all system requires high accuracy, yet there are numerous high-frequency inner loops; (3) simulation of complex systems involving ordinary and/or partial differential equations, algebraic equations, iterations, generation of functions of one or more variables, time delays, and/or logical decisions; and (4) in short, the misfits and the tough ones. Consideration of the foregoing is a help in determining the best ” tool, but if the nature of the workload is known, there is still another way. ((

4.5 Benchmark Problems

The slow progress of simulation in the process industries notwithstanding, by the early sixties Monsanto Chemical Company, one of the first companies to turn to simulation to aid in the study of the dynamics

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of industrial processes, was sold on it. But when it came to expanding their simulation facility they needed some kind of yardstick with which to measure computer performance; they wished to determine not only which kinds of equipment under consideration could solve their kinds of problems but also which could do it most efficiently. Thus, they developed a descriptive model of a typical chemical process, which became known as the Monsanto Benchmark Problem. The idea was to offer it to competing vendors and see who could handle it most effectively. Surprisingly (or perhaps understandably) the vendors did not fall over themselves to offer solutions, but eventually some were forthcoming r5,141. The Monsanto benchmark experiment was successful enough to warrant consideration of taking a similar approach to problems in other fields. Thus, a t a Simulation Council-sponsored Advanced Simulation Seminar in Breckenridge, Colorado, August 1966, it was suggested that the benchmark concept could be usefully adapted to the simulation of physiological systems-a matter of great interest to many of those present, particularly the author. 5. Physiological Simulation

While engaged in the simulation of intercontinental ballistic missile systems, the author had become interested in the development of an improved extracorporeal perfusion device-a heart-lung machine. The author had seen one, and its complexity motivated him to develop a much simpler pump-oxygenator for blood [9].But when it was tested by connecting it to a living organism to take over the functions of the heart and lungs, the simple device became an element in an amazingly complex organism. Things happened that the author did not understand and that the physicians and surgeons could not explain. To gain insight the author turned to simulation, even though he had little knowledge of how a cardiovascular system should be simulated. However, instead of alternating between the simuland (in this case the living animal) and the computer simulation, he went from the literature to the simulation t o a physiologist interested in the same problem (usually for a clarification of the physiology which might explain shortcomings of the model) and back to the simulation. This procedure resulted in a simulation of the circulatory system [ll] which was adequate for the study for which it was designed, even though the author did not know enough physiology to develop a satisfactory model without extensive empirical, trial and error (hypothesis) testing. After this experience the author was ‘‘ hooked ” on simulation for the study of physiological systems. So were a number of others [a]. Of this

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comparatively small number, however, it was interesting to note how many had doctorates in medicine or physiology as well as in engineering or physics. In short, a significant number of them combined in one person the training required to undertake successfully and appreciate the value of physiological simulation. But compared to the number of researchers--and clinicians, too-who could benefit from simulation, the number with training in both the life and the physical sciences is woefully inadequate. It is fortunate that the team approach can be made to work, even though it is not always easy. Those with a background in the life sciences and those with an education in the physical sciences actually think differently. Unfortunately the sincerest efforts of the twain to work for a common goal are also hampered by language differences, which have a psychologically alienating effect out of all proportion to the actual difficulties of communication. It sounds trivial, but how many engineers know that -when a physician refers to the " lumen " he means the i.d.? And if the question is turned around, the physicians would probably fare even worse. Fortunately, it seems that mutual respect can more than compensate for differences in points of view and vocabulary and make teamwork on physiological simulation a fascinating and rewarding experience. 5.1 System Characteristics

Among the properties that characterize physiological systems and make them difficult to study are (1) complexity, (2) adaptive behavior, (3) measurement problems, and ( 4 ) noise. 5.2 Attributes of Simulation

Among the properties of computer simulation which make it well suited to cope with the foregoing difficulties are the ability t o (1) simplify, (2) control the environment, (3) facilitate measurement, and (4) eliminate or control noise. 5.3 Complexity and Simplificatio-n

The complexity of physiological systems begins a t the molecular level with the basic building blocks. the amino acids, and extends through the levels of cells, individual organs, and organic systems to the complete

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living plant or animal. And at each level, and between levels, there are feedback loops, regulatory mechanisms, and cross-coupling. To attempt t o develop a simulation complete in every detail a t even one of these levels, to say nothing of all of them, would require more knowledge, equipment, and know-how than is available-by orders of magnitude. Fortunately it is neither necessary nor desirable to simulate in complete detail because simulations should be " question-oriented." The model, therefore, should be comprised only of those elements and relationships which bear on the questions of interest. Unnecessary detail makes the model more difficult to develop and to understand, and understanding (or insight) is the ultimate objective of simulation. To gain understanding there is no better way than by attempting to simulate that which would be understood. I n the light of the foregoing we can see what is at once one of the weaknesses and strengths of simulation. The weakness is the amount of talent, of human judgment, that is required. Simulation without human talent can no more answer questions than a scalpel can perform a surgical operation without the knowledge and skill of the surgeon t o guide it. Basing action on results of an improper simulation, or an improper interpretation of results of a valid simulation, can lead to trouble. The strength of simulation is that it can be used as a means of evaluating the importance of elements of the simuland and their functions with respect to the questions to be answered. In case of doubt a test experiment can be designed and run, the function of interest added or deleted, and the experiment run again. Armed with the results, the investigator can judge the relative importance of the function manipulated. 5.4 Adaptability and Its Control

One of the most remarkable characteristics of living organisms is their adaptability: without it the species would have perished from this earth. But it often presents serious difficulties for investigators of physiological phenomena. The time required for an organism to react to the (usually traumatic) investigative techniques is usually very short, so that the investigator will often find at some time during an experiment that he is no longer working with the system with which he started. In a simulation those conditions which all too often affect system parameters can be held constant, or changed only in accordance with the requirements of the investigation. Those reactions of a specific individual to its environment which make it function differently under different circumstances, or under the same circumstances a t different times under apparently identical circumstances, have the same effect as

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though they were random or "noise " in the system. They make it very difficult to distinguish between changes in measured variables resulting from deliberate experimental changes and changes resulting from uncontrollable factors. The primary mechanisms which enable an organism to adapt and make it difficult to perform controlled experiments are feedback and redundancy. Feedback systems contribute to homeostasis, the tendency of an organism to resist change in spite of external stimuli. Redundancy complicates experimental procedures by increasing the number of paths from the point of application of a stimulus to the point where the reaction is measured. As contrasted to a living organism, these feedback and parallel paths in a simulated system are under the complete control of the investigator. If they interfere with his observations but are not germane to the study at hand, he can eliminate them. If, on the other hand, they make a necessary contribution to the validity of the simulation, he can easjly measure their effect.. 5.5 Measurement Faci Iitated It has become a truism that it is impossible to measure anything without disturbing that which is measured. There is no field of endeavor in which this fact leads to more difficulties than in the study of physiological systems. If a cell is punctured by a microelectrode, t o what extent is its normal function altered? If an experimental animal is anesthetized and cannulas inserted, how representative are the measurements of normal physiological functions? It is difficult to say for sure. Consider a simple but important example. I n the study of cardiac function. a parameter of great interest to investigators is cardiac work per ventricular contraction. But to calculate this it is necessary to determine the amount of blood ejected per contraction and the pressure differential across the ventricle. The pressure differential across the left ventricle can be measured with satisfactory accuracy by passing a cannula up a vein in the arm through the superior vena cava, the right atrium, the right ventricle, the pulmonary valve, and the pulmonary artery into the lung and wedging it into a bronchial notch. If it is properly placed and tightly wedged so that the blood flow past the tip is occluded, the pressure measured a t the catheter tip is assumed to be the back pressure from the left atrium and therefore the pressure of the blood flowing into the left ventricle. Then if another catheter is passed through an incision in the neck and down the carotid artery into the aorta, it can be used to measure the pressure of the blood flowing out of the ventricle, which is the pressure that the heart is working against. The instantaneous difference between these two pressures multiplied

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37

by the instantaneous flow rate of the blood ejected from the heart and integrated over one heartbeat will give a reasonably accurate measure of the work performed by that left ventricle during that particular contraction under the existing circumstances. But how can the instantaneous flow out of the ventricle be measured? There are several good blood flow meters, but to measure the flow from a ventricle all of them require thoracotomy, or open-chest surgery, to allow the flow transducer to be placed in or around the aorta. (Or the pulmonary artery, if it is flow from the right ventricle that is of interest.) How much error is introduced by the reaction of the patient (or experimental animal, for that matter) to such a traumatic preparation? It is indeed difficult to say. Given a valid simulation, mensuration presents no problem. All parameters and variables are available in an analog computer, where they can easily be measured. In a digital computer they are probably computed as part of the simulation; if not, it can easily be done. Obviously, the difficulty is that the stress-provoking procedures described (or others which may be less stressful but more indirect and/or more difficult) will have to be used to gather data required to develop the simulation. Thus, if the simulation faithfully reflects the simuland, the result will be a computer model of a stressed animal. But because the simulation can be more readily manipulated than the animal, the stress can be decreased to “ normal.” Or it can be increased beyond the limits that the animal would be able to tolerate, thus allowing a full spectrum of experiments to be run with one “ preparation ” and without sacrificing the animal. The technique of decreasing the stresses until a normal animal is simulated raises the interesting question of how one knows when he gets there. That is obviously a question that the experimenter must answer, but the author is not about to attempt to do so here. However, the implications of the technique are exciting: If a “ normal ” physiological system can be simulated and the effect of stresses on measurable variables duplicated, can the same model be used to identify unrecognized stresses which might be causing abnormal values of measured variables? Closely related to the problem of making measurements without inducing unwanted stress in the subject is that of instrumenting astronauts. The medical team on the ground would like to have continuous measurements of everything. But some measurements are impractical (the cardiac work per ventricular contraction cited, for example) and others are inconvenient or uncomfortable for the astronauts. Furthermore, since the rate at which information can be telemetered from a spacecraft to earth decreases with the distance, the number of physical variables of astronauts in deep-space probes that can be monitored will

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be severely limited. But it is believed that the current state of the simulation art offers a solution. It is believed that it is now possible, and that in the near future it will prove practical, to develop a computer model of a man which will embody the elements, systems, and variables of primary interest to the physiological monitoring team. This model could be tailored to simulate a selected astronaut and tuned ” before the fiight to react to stimuli and stress in the same way that he does. Then during flight the model could be driven by easy-to-measure variables (e.g., respiration, heart rate. and galvanic skin resistance) telemetered from the astronaut it was designed to simulate. Since the value of all parameters and variables in the model would be readily available for measurement and observation, a good idea of the astronaut’s over-all well being could be obtained and the effect of stresses evaluated. In case the foregoing sounds too (‘far out,” it should be remembered that what is proposed is actually only a sophisticated method of on-line data reduction! It differs from systems in actual use only in the degree of complexity of the system simulated. ‘(

5.6 Noise and Its Control

Noise in the sense used here refers to any random or unpredictable variation. Thus included are those changes in physiological systems which cannot be predicted for whatever reason, whether it is because of an incomplete understanding of the system or because the change is truly random. In any case, noise is irksome to the (‘wet lab experimenter. Physiological systems, particularly the more complex ones, differ from subject to subject, and within the same subject from time to time. This makes it difficult to ‘‘ repeat the experiment,” a requisite for the validation of all good research. Though in the past some reservations concerning analog simulations were justified, modern analog equipment and techniques, and certainly digital ones, make it possible to repeat the simulated experiment without the intrusion of unwanted noise. Note the word unwanted-in the simulation of stochastic processes, and in certain other kinds of experiments, noise is necessary. But even then the amount and kind of noise should be under the control of the investigator. The ability to eliminate or control noise not only allows the experimenter to validate his own w-ork by repeating the experiment but also al1ows him t o compare his results with other workers in other locations, a difficult thing to do precisely when different experimental animals (or people) are involved. But through simulation it is possible to develop a “ standard dog ” (or person?). ”

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5.7 A Hybrid Example

Because we have discussed some of the more or less unique difficulties attendant on the simulation of physiological systems, and because we have said that hybrid simulation is best for the tough ones, we will use a hybrid simulation of a physiological system as an example of what has been done. The simulation chosen is not meant to be indicative of what could have been done at the time (and could be done better today), much less that which will be possible and practical tomorrow. It was chosen because the author had followed through on the suggestion that the benchmark concept might be applicable to problems in other fields and had developed PHYsm-a physiological simulation benchmark exconcept [13] periment [12].Experience in implementing the PHYSBE furnished the background necessary for the following discussion. The example chosen is a special-purpose implementation of the PHYSBE concept. It is particularly pertinent to the preceding discussion, and in addition: (1) It illustrates how a basic, simplified, reference simulation can be modified and expanded in a particular area to give the investigator a “ blow-up,’’ or more detailed representation, of the field of interest. (2) It demonstrates how the rest of the reference simulation can be used to “ close the loop ” around the field under investigation and thus give the feedback which is SO often all-important in the study of physiological systems. (3) It emphasizes the fact that to be useful no simulation need be complete in any more detail than that which is required for the study at hand. (4) It shows how typical simulation “chores” may be allocated to the analog and digital equipment, and the signal flow between them. ( 5 ) It underscores an advantage of all simulation: noise, the unpredictable variations that intrude into clinical studies, the inevitable variations from subject t o subject, and in the same subject from time to time, can be controlled.

This modification and refinement of the published version of PHYSBE (by Baker Mitchell and his colleagues in the Department of Mathematics at the University of Texas, Texas Medical Center, Houston) was implemented for the following reasons: ( 1 ) to allow study of effects of hydraulic characteristics and timing of DeBakey-type heart pumps on the over-all circulation; (2) to provide physiologically accurate pressure curves for obtaining

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and testing models of baroreceptor characteristics and their influence on heart rate; and (3) to analyze and simulate tilt-table responses as recorded from astronauts, and to extrapolate these responses to 0-to-6 g space environments. The last two are expected to suggest objective criteria for interpreting the effect of tilts and to point the way for future experiments. In the example case a hybrid rather than an all-analog or all-digital simulation was dictated by the following facts : (1) All-digital simulations using MIMIC and FORTRAN had been tried, but although both yielded satisfactory solutions to the equations, turnaround times of about a half-day precluded effective investigation of the phenomena of interest. (2) The aorta-being a relatively stiff elastic tube-introduced highfrequency effects which made digital running time quite lorig. (3) The analog computer was better for the kind of empirical investigation that was called for, but there was not enough analog equipment to allow an all-analog mechanization of the system in the detail that was necessary.

The EAI 680 analog computer was used to simulate an “ expanded view ’’ of those parts of the circulatory system selected for parametric studies. The additions and refinements which contributed to the expansion were : (1) left atrial pumping (which required the addition of block 23, Fig. l), (2) mass of the blood (the basic simulation considers the blood to be weightless because inertia effects are small). (3) gravity effects, (4)nonlinear elasticity of the capillaries in the blood compartments, (5) the division of the aorta into three segments (blocks 41,42, and 43 of Fig. 3) (discrete-space, continuous-time method of solving partial differential equations), (6) viscoelastic aortic wall effects, and ( 7 ) a carotid baroreceptor/heart-rate control loop.

The simulation of all compartments which did not require parametric “ pumping ’’ functions of both ventricles and the left atrium were assigned to the SDS 930 digital computer. Both FORTRAN and machine language were used to program the 930: FORTRAN for ease of programming and machine language for analog-digital, digital-analog conversions.

‘‘ twiddling,” plus the generation of the

41

ADVANCES IN SIMULATION

Figure 1 is a block diagram of this simulation, Fig, 2 is a one-page sample of the five-page digital computer listing, and Fig. 3 is the analog computer diagram. It is interesting to note that this particular simulation demonstrated the well-recognized limitations of both the analog and digital computers: They ran' out of analog equipment and digital time.

I

I

-_-

i'

U

i

FIG.1. Block diagram of hybrid mechanization of PHYSBE as modified to include the requirements listed in the text.

5.7.1 Signal Flow

The signal flow, insofar as the information concerning the value of problem variables is concerned, can be seen in Fig. 1. But that diagram does not show nearly all of the communication between the analog and digital computers required for hybrid simulation. As an illustration, consider first that part of the circulatory system in the example simulated on the analog computer, as indicated in Figs. 1 and 3. Before starting the simulation (but after all connections have been made and all pots set), the mode control on the analog is switched to

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"Initial Conditioiis." This causes the outputs of all the analog integrators to assume the values set on their respective initial-condition pots. In the example problem the voltages (labeled V 2 3 , V 3 , etc.)represent the volumes of blood in the body compartments that the integrators simulate. These volumes, or voltages, are then divided by 6JBB. &REWIND M T t r . &ASSIC\ S*t'TCkrXl~''TIa. &ASSIS& s l . c ~ r L a = L P I P P = w . &ASSIG$ B ~ J . Y T I ~ * nR1FTDAL.l €38,La. C C

C

C C C C

C

c

C C C C

C C C

C C C

t C C C

2oc 350

700

C C

C C

s s

SET I Y I T l A L C B W I T I r t Y S

5 ceuTIhcuE Few 0 3 1 1 ~ 3

pel

-399

FIG.2. A sample of the listing of the FORTRAN machine language program for the SDS 930 portion of the hybrid PHYSBE simulation.

ADVANCES I N SIMULATION

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(actuaily multiplied by the reciprocal of) the compliance of the respective compartments by electronic multipliers and pots to arrive at the related pressures by mechanizing the relationship

P=

vp.

The resulting pressures are represented by the voltages (P23@,P3, etc.) at the outputs of amplifiers connected to the outputs of the multipliers or pots.

--I%tFIG.3. Computer diagram of the analog portion of the hybrid PHYSBE modulation.

The pressure drops across the simulated body compartments are determined by the summing amplifiers (by adding with the sign of one of the variables reversed), and the voltages (F231, F23@, etc.) representing the flows into and out of the compartments are determined by

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JOHN McLEOO

dividing by (multiplying by the reciprocal of) the resistances to flows between the compartments by means of the associated pots. In other words, the relationship ( P , - P,+I)/Ris mechanized. Note that, appropriately, the resulting voltages are fed to the integrators representing both the upstream and the downstream compartments; that is, the fact that the flow out of the upstream compartment must be equal to the flow into the downstream compartment is assured by letting the same poltage represent both flows. Similar relationships are programmed into the digital computer for the body compartments simulated digitally. But as the physiological system being simulated is a closed circuit, there must be an analog-todigital and a digital-to-analog interface for signals representing the value of variables on both sides of each interface. Typically the interface equipment will include, besides the Analogto-Digital Converters (ADCS) and the Digital-to-Analog Converters ( DACS), sense lines, interrupt lines, and control lines. A patchbay and/or some digital logic is also often included to allow flexibility in the routing of signals. Sense lines allow the digital computer t o interrogate the analog computer to determine some preselected condition of the analog computer or of the simulation. They carry only binary information; that is, they are either low (binary zero) or high (binary one). Thus they can be sampled by the digital computer to determine the mode (pot set, initial conditions, operate, etc.) of the analog computer or the condition (open, closed) of function switches, relays, comparators, etc. Interrupt lines carry commands to the digital computer which cause it to respond in various ways depending on how the computer has been programmed. Typically, interrupt lines are used in hybrid simulation to cause a digital computer working in a " background-foreground " or a time-shared mode to stop work on the current problem; store that program, information and status; call up the simulation program and data; and execute the appropriate commands in support of the hybrid operation. The primary difference between sense lines and control lines is that the digital computer must be programmed to interrogate sense lines, whereas a command on an interrupt line is executed as soon as the digital computer completes the command on which it is working at the time of the interrupt. Therefore, insofar as the digital computer is concerned, sense lines may be considered synchronous in that they are only interrogated at specific times in the digital program, as contrasted to interrupt lines which can interject their commands at any time. Control lines carry commands in the opposite direction, from the digital to the analog computer, and are typically used when a digital

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computer is in command and is controlling the mode and/or other aspects of the analog operation. In the example problem only the sense lines were used. Details of both analog and digital programming are beyond the scope of this article. Sufficeit to say that the digital computer was programmed to go into a fast iterative loop which included a branch point. The branch point required the digital computer to test a mode sense line from the analog computer at each iteration. If the sense line was low (binary zero) it indicated that the analog computer was in some mode other than operate ” and the digital computer continued to “ idle ” in the iterative loop. But when the analog mode control was put into operate (causing all analog integrators to integrate) the sense line would go high (binary one), and after the next interrogation the digital computer would branch into the preprogrammed subroutine to generate the functions 1/C23 and 1/C3 required to cause the left atrium and the left ventricle simulated on the analog computer to “pump.” The instantaneous digital values of llC23 and 1/C3 were converted to an analog voltage by the DACS at the interface and used to drive the multipliers to produce the voltages representing the left atrial and the left ventricular pressures. The voltages representing these pressures in turn caused the voltages representing the flows and volumes in the analog computer to change as functions of time in a way analogous to their counterparts in the physiological system. The analog voltages F231, representing the flow from the lungs into the left atrium, and P43, representing the pressure in the descending aorta, were converted at the interface into binary inputs to drive the digital part of the simulation. The digital computer thus driven generated the pressures, flows, and volumes. associated with the body compartments it simulated. Of these P 2 2 g , the pressure in the pulmonary vein, and F43# (equal to the sum of the flows into the arms, head, trunk, and legs computed digitally) were converted at the interface to analog voltages to close the simulated circulation loop. I<

6. A Look Ahead 6.1 New Fields

Advances in simulation will continue at an even greater rate, proportionately, than advances in computers in general. Problems which have delayed widespread use of simulation in fields other than engineering have been or are being overcome. Workers in other areas of endeavor will find that the equipment and techniques developed by the aerospace industry with government support are applicable to their own problems -and with little or no additional developmental cost.

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6.2 Analog Hardware

Analog elements and components w i l l remain important because of their speed advantages and their compatibility with man. Small generalpurpose analog computers will be used for classroom demonstrations of many dynamic interrelationships in the life sciences and social sciences, as well as in the physical sciences. Larger, more special-purpose analog computers may be more or less permanently wired to produce models of such things as river basins or physiological systems, where it is important to presepe an obvious one-to-one correspondence between elements of the simuland and the simulation. But there will be few of these ‘‘ pure ” analogs. The advantages to be gained by the use of digital elements, or by association with digital computers, will in most cases force hybridization. It is the author’s belief that herein lies the future of analog computers: Analog equipment will survive and flourish indefinitely in the form of special-purpose consoles connected to large central digital processors. These consoles will not only facilitate man-machine interaction by allowing the man to communicate with the computing system in his natural analog fashion, but they will preprocess information for digital computation, post-process computed information for display, and handle all high-frequency computations. 6.3 Analog Software

Analog software, practically unknown today (at least by that name), will take the form of ‘‘ how to ” instructions designed to make possible and encourage the use of analog computers by people with no knowledge of, or interest in, computers per se, but people who could use them to advantage. In the case of the pure analog these will be, for the most part, educators who will find in the small desk-top analog computer a versatile and lucid device for simulating and illustrating the dynamic internal interactions of all kinds of sociological, physiological, mathematical, and physical systems. Such analog software may take the form of paperback supplements to standard texts, showing how analog computers can be set up to demonstrate the phenomena discussed in the text. In stating the case for the future of analog equipment it may seem that the author is implying that hybrid computing systems are, and will become even more so, the best tools for the detailed simulation of moderate to very complex systems. That is exactly what is meant. (Almost any equipment can be used for the quick-and-dirty simulation of simple systems.) But sophisticated digital simulation languages make all-digital simulation an attractive alternative that must be considered.

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6.4 Digital Computers

Digital computers, unlike analogs, will stand alone for a wide variety of uses. Although they can be coerced into serving if no better tool is available, they are definitely not inherently as well suited for the simulation of continuous system as are hybrid systems. Nevertheless, because business applications will support many large time-sharing computer installations, the digital simulation languages under development today will have a profound influence on simulation in the years to come. To use a digital computer for something a hybrid computer could do better and more efficiently will often be justified by the ready availability of the digital computer. And, if it can be time-shared, the operation will in effect be subsidized by the computer working on the payroll or some other worthwhile business chore while the man in the simulation loop is cogitating. 6.5 Toward Greater Hybridization

The current practice of adding a complement of digital logic to otherwise completely analog computers will have its counterpart in the addition of analog components to otherwise all-digital systems. For a time this will continue t o be done by integrating complete analog computers into the system; later analog components will probably be built into otherwise all-digital computers. I n a further step toward total hybridization, the digitally set analog potentiometers which have been with us for years will be replaced by advanced versions of the currently available digitally set step attenuators. The biggest stimulus to hybrid simulation, however, will be the reduction to practice-finally-of digitally programmed (" patched ") analog building blocks. This long-talked-of advance will be brought about not so much by technological breakthroughs, or even by any spectacular advances in the state-of-the-art, but by the sheer pressure of near-necessity. Digital executive programs must be able to call up and alter analog subroutines and even program. To continue to require human intervention to change patch-cords would be ridiculous. This completely digitally controlled analog programming will be made possible by a combination of two things: improved and less expensive digitally controlled reed and/or solid-state analog switches, and through studies to determine how they can most effectively be used. The latter will be accomplished by investigations to determine, for each given complement of analog elements, the probability that each will have to be connected to each other to solve the class of problems of interest. Connections withvery high probability will probably be semipermanently

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connected with conventional patch-cords. Those of intermediate probability will be digitally switched t o give near-complete flexibility under digital control. Low probability connections will probably not warrant automating; human beings can still intervene to take care of unusual requirements. I n the not too distant future hybrid computer systems will dominate the scientific field. These will range widely in both size and configuration, but all w4ll handle both continuous and discrete information and will operate on it in parallel and in series. I n small simulation laboratories the computer may be predominantly analog but with digital setup and control, digital logical elements, and digital memory. Or (depending on the nature of the work load) i t may be predominantly digital with hybrid man-machine interface elements and perhaps with analog integration subroutines. I n any case, most scientific computing-and practically all simulation-will be hybrid. 6.6 The Large Systems Large scientific simulation and computation centers will be designed around a large, digital, time-shared central processor with most, if not all, of the analog equipment in the remote consoles. These consoles will be designed for the particular kind of problems they are expected to handle. If they are for FIDO (figures in, data out) problems, they might consist of a keyboard and a printer only. However, for those problems requiring a high degree of man-machine interaction, there will have to be analog elements. The analog elements in remote consoles may be as simple as those associated with analog-to-digital and digital-to-analog conversion equipment. or the analog subsystem may be as extensive as a modern large-scale general-piirpose analog computer. Though capable of being operated slone, i t will usually be programmed and controlled by the central processor. This will again depend on the nature of the workload. In any case, the man a t the console. whether he be in space or in the next room, \dill not need to know (and probably will not care) what parts of his problem are being handled by analog and what parts by digital elements of the over-all computer system. He will program the computer using a problem-oriented language, and the computer will automatically assign the appropriate analog and digital elements. The majority of today’s high-precision, high-cost analog components will be replaced by solid-state chip amplifiers costing less than one-tenth as much. In hybrid systems the accuracy of these elements will be relatively unimportant because they will be assigned t o subroutines and signal flow paths completely enclosed within digital feedback loops which will keep over-all errors within prescribed limits.

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6.7 The Future of Simulation

The future will see simulation, which has heretofore influenced our way of life almost exclusively as a tool of the physical sciences, influence us even more as its power is recognized and harnessed by the life scientists-and by educators in all lines of endeavor. REFERENCES 1. Account of meeting of Industrial Analysis and Control Council. Simulation Council Newsletter (April 1954). 2. Account of meeting of Industrial Analysis and Control Council. Sirnulation Council Newsletter (October 1954). 3. Brennan, R. D., PACTOLUS, a simulator language which makes a digital computer feel like an analog computer (sorta kinda). Simulation 3, 13-19 (1964). 4. Clymer, A. B., Bibliography on computers in the life sciences (174 items). Simulation 2, 51-58 (1964). 5. Giese, C., Determination of best kinetic coefficients of a dynamic chemical process by on-line digital simulation. Simulation 8, 141-145 (1967). 6 . Korn, G. A., Progress of analog/hybrid computation. Proc. IEEE 54, 1-15 (1966). 7. Kress, R. W., and Fogel, G. D., L. M. Program real-time simulation. Simulation 10, 143-152 (1968). 8. Linebarger, R. N., and Brennan, R. D., A survey of digital simulation: digital analog simulator programs. Simulation 3, 22-36 (1964). 9. McLeod, J., MAC-a simple, reliable, inexpensive, portable extra-corporeal perfusion device. Proc. Symp. Biomed. Eng., Sun Diego, 1961, pp. 46-47. 10. McLeod, J., Ten years of computer simulation. I R E Trans. Electron. Computers 11, 2-6 (1962). 11. McLeod, J.,Computer simulation of the hydrodynamics of the cardiovascular system. Simulation 2, 33-37 (1964). 12. McLeod, J., PHYsBE-a physiological simulation benchmark experiment. Simulation 7, 324-329 (1966). 13. McLeod, J., PHYsBE-a year later. Simulation 10,37-45 (1968). 1 4 . Nesbit, R. A., and Engel, R. D., Example program for the determination of chemical rate coefficients from experimental data. Simulation 8, 133-137 (1967). 15. Ragazzini, J. R., Randall, R. H., and Russell, F. A., Analysis of problems in dynamics by electronic circuits. Simulation 3, 54-65 (1964). 16. Teichroew, D., Lubin, J. F., and Truitt, T. D., Discussion of computer simulation techniques and comparison of languages. Simulation 9, 180-190 (1967) 17. The SCi continuous system simulation language (CSSL). Simulation 9, 2 81-303 (1967).

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Symbol Manipulation Languages PAUL W. ABRAHAMS Courant Institute of Mathematical Sciences New York University New York, New York

. 1. What Is Symbol Manipulation? 1.1 Representation of Lists . 1.2 Language Features . 2. LISP 2 . 2.1 Data . 2.2 Program Structure . 2.3 Implementation of LISP2 . 3. LISP 1.5 . 3.1 Pure LISP . . 3.2 Features Added to Pure Lisp 4. L6 . . 5. PL/I String and List Processing 5.1 String Processing . 5.2 List Processing . 6. SLIP . 6.1 SLIPData . 6.2 SLIPPrograms ; I . 7. SNOBOL 7.1 SNOBOL4 . 8. Other Symbol Manipulation Languages 8.1 IPL-v . 8.2 COMIT . 8.3 EOL . 8.4 A Few More . 9. Concluding Remarks . References

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51 53 56 51 57 61 68 69 70 71 74 18 79 81 84 85 88 92 98 101 102 104 106 108 109 110

1. What I s Symbol Manipulation!

Symbol manipulation is a branch of computing concerned with the manipulation of unpredictably structured data. Most scientific and business data processing is characterized by the manipulation of data of known length and format. Thus, in the numerical solution of a partial differential equation the representations of the input and output parameters and intermediate results (fixed, floating, double-precision, etc.) are fixed at the time the program for solving the equation is written: 51

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PAUL W. ABRAHAMS

the dimensions of the arrays involved are usually also known in advance or a t least do not vary during the running of the program. Similarly, in the preparation of a payroll the exact size and layout of the input and output records and intermediate working storage is given and fixed, and in fact may be stated explicitly in forms such as the data division of COBOL. A little more generally, the length of a payroll may not be known in advance but may be supplied in the course of the problem; or the size of the array of grid points for the differential equation may be changed in accordance with intermediate results of the problem itself. I n all these cases, however, the general format of data is fixed and a t most some parameters related to size are varied from time to time during the computation. I n contrast, the size and format of the data involved in symbol manipulation are not known in advance and vary greatly during the running of a program. These data are in the form of variable-length lists. A list is a sequence of elements, each of which is a data item. A multilevel list is one in which the data items may themselves be lists; the latter are called sublists of the multilevel list. For instance, a verbal text might be represented as a list of the characters in it. An algebraic expression, after suitable insertion of parentheses, might be represented as a multilevel list; the representation would consist of a list whose elements are the main operator and the list representations of the subexpressions to which this operator is to be applied. Thus the elements of one of these lists would consist of a mixture of sublists and elementary items such as operators, variables, and constants. The number of levels of sublists, i.e., of lists within lists, would correspond to the number of levels of nesting of parentheses. Symbol manipulation languages vary in regard to the generality of the lists upon which they operate. List processing languages such as LISP, SLIP, IPL, and L6 process lists in their most general form. String processing languages use one-level lists only; these lists are called strings, and their items are called constituents. The constituents are but they also may be groups of usually single characters, as in SKOBOL; several characters, as in COMITE44. The distinguishing feature of such languages is that a list cannot itself be an item on a list. Algebraic manipulation languages operate on algebraic expressions ; though these expressions are multilevel rather than single-level lists, they are nevertheless a very specialized form. Examples of algebraic manipulation [36] and Formula ALGOL[29, 311; since this languages are FORMAC subject is treated by Sanimet [36],it will not be further discussed here. Both string processing languages and list processing languages have been used for algebraic manipulation. In general, the more specialized languages take advantage of the specialization by utilizing linguistic

SYMBOL MANIPULATION LANGUAGES

53

features and implementation techniques that do not work in the more general cases. A general exposition of symbol manipulation languages, using LISP as an example, was written by this author in 1965 [l].An overview of the state-of-the-art in symbol manipulation about a year later can be gotten by reading the August 1966 issue of the Communications of the ACM [3], which contains selected papers from the ACM Symposium on Symbolic and Algebraic Manipulation that was held in Washington, D.C. in March 1966. Several papers from that symposium are cited in this article. Any programming language for symbol manipulation must meet two major requirements. First, there must be appropriate ways of representing lists both on paper (the external representation) and in the memory of a computer (the internal representation). Second, there must be appropriate functions, statement types, subroutines, and other linguistic devices for specifying operations on lists. 1.IRepresentation of Lists

We first consider the external representation of lists. For specialized lists such as character strings and algebraic expressions, there are natural written representations. Thus a character string may be written by writing down the characters one after another, enclosing the entire group in quote marks to show where it begins and ends. An algebraic expression may be written, for example, in one of the forms used for arithmetic expressions in scientific programming languages. For more general lists, the most freqqently used written representation of a list consists of the elements of the list written in sequence, delimited by blanks and enclosed in parentheses. Thus, (CAT

4 DOG)

represents the list whose three elements are the character string the number 4, and the character string DOG. ((CAT 4) (CENTIPEDE

CAT,

100))

represents a list whose elements are two sublists. Each of these sublists in turn has two elements. In representivg a list within the memory of a computer, we must indicate both what items are on the list and in what sequence they occur. First, consider the sequencing problem. The simplest way to indicate the sequence of items in a list would be to allocate a block of storage words, store one item per word, and then use a special item to indicate the end of the list. But what size block should we use? Since

54

PAUL W. ABRAHAMS

the length of the list is not known in advance, we might allow the maximum length but to do so for every variable would quickly exhaust storage on almost any computer. Even worse, the number of lists needed cannot be predicted in advance, for lists can appear as members of lists, and LISP, new variables and in addition, in systems such as SNOBOL can be created a t run time. So clearly some form of dynanlic storage allocation is needed. We will return to this point shortly. We also have to be able to represent the items on a list. If all of the items are of the same kind-single characters or floating-point numbers, say-that is not much of a problem. But if the contents of a list can be heterogeneous, then a problem can arise with " data puns," i.e., different items that happen to be represented by the same configuration of bits. So we must either associate a tag with each item on a list that says what kind of an item it is, or represent items in such a way that data puns cannot occur. By dynamic storage allocation, we mean that the amount of space allotted to storing the values of variables varies a t run time. Thus we need to have a way of obtaining more space when it is needed; and since we will surely run out of space sooner or later, we need to have a way of recovering space that is no longer needed. Usually, the value of a list variable is stored as a pointer to, i.e., the address of, the machine location where the list actually starts. Some of the possible ways of representing a list in a computer memory are illustrated in Fig. 1. I n Fig. la we see a list represented as an array, with the first cell of the array giving its dimension and the succeeding cells containing the representations of the successive items of the list. -4 list variable whose value was this particular list would contain in its assigned storage location the address of the first cell of the array. This address would thus be a token of the list. (For lists of characters, t,he array might pack several t o a word and give the number of characters

Pro. 1 . Thrw representations of the list and (c) t\vo-way list.

(A B

c

D ) : ((1)

array, ( b ) onc-way list,

SYMBOL MANIPULATION LANGUAGES

55

rather than the number of words in the header.) In Fig. l b we see the representation of the same list as a sequence of linked cells. Each cell contains an item and a pointer to the next cell, i.e., the location of that cell. A token of the list would be the address of the top cell. The last cell has a special indicator for end-of-list, as shown. I n Fig. l c we see the list represented in a doubly linked form with a header cell. Each element of this list occupies two words. The header contains pointers to the first and last elements of the list, and each element of the list contains a pointer to its predecessor and a pointer to its successor. The header is the predecessor of the first element and the successor of the last one. A type code distinguishes the list elements from the header, and also distinguishes different kinds of elements from each other. A token of this list would be the location of the first word of its header. The array representation is convenient in situations where a list, once generated, is never modified directly. I n this situation, a list is modified by making a new copy of it with the wanted modifications. The linked-cell representation is convenient when lists are subject to direct modification. I n either representation, there is always a reservoir of available space, often in the form of a list of available space. As new lists are created or old ones are enlarged, space is taken from this reservoir for the purpose. Of course, the space has to be available in an appropriate form; if we want a block of 300 cells in a row, it does not suffice to have 150 disjoint blocks of 2 cells each. The action of returning storage to the reservoir is known as erasure; the criterion for erasing a block of storage is that the data stored there will never be used by the program in the future. This criterion will be satisfied if the contents of the storage are inaccessible to the program. For example, suppose that a certain list is the value of a variable and is not the value of any other variable, nor is it a sublist of any other list. Then if the value of that variable is changed, the previous value is rendered inaccessible and thus the list can safely be erased. Thus the central issue in storage recovery is the determination of whether or not a given block of storage is inaccessible. Depending on the particular language, this determination may be made by the programmer, by the system, or by a combination of the two. If the determination is left to the programmer, then an erasure subroutine is provided; this subroutine is given the address of a list (or other storage to be erased) and returns the storage occupied by this list to the reservoir. Sublists of the list may or may not be erased also, depending on the system. If the system is the determiner of inaccessibility, then a program called the garbage collector (cf. Section 2.3) is provided. When the reservoir is exhausted, the system will invoke the garbage collector.

56

PAUL W. ABRAHAMS

The invocation will take place without any explicit action on the part of the programmer. The garbage collector will then search out all inaccessible lists and return them to the reservoir. The garbage collector can usually be invoked explicitly as well, and in some cases garbage collection may be performed even though the reservoir is not exhausted. Another approach is the one taken by SLIP,where the system accounts for references to lists as elements of other lists, while the programmer accounts for all other references to lists. I n general, leaving the responsibility for erasure to the p r o g r a m e r requires the programmer t o do more work but leads to a simpler system. A significant disadvantage of leaving erasure t o the programmer is that if a list is erased when it is not yet inaccessible, then the resulting program nusbehavior may be extremely difficult to debug. Furthermore, failure to erase erasable lists may lead to the rapid exhaustion of storage, and this situation also will be difficult to debug. Character strings are a special case of lists because in some internal representations several characters may be packed into a list item. There are a number of possible internal representations for character strings which differ in the density of packing and the extent to which pointers are used. In general, the methods that pack information more densely also increase the cost of insertion and deletion of characters. A useful discussion of the alternative internal representations of character strings is given by Nadnick [26]. Generally speaking, symbol manipulation systems have not had any effective methods for utilizing secondary storage devices. Some facilities of this sort are included in IPL [28],and most systems permit input and output t o and from named files, which may reside on secondary storage. Some ideas on the efficient use of secondary storage have been published by Bobrow and Murphy [a] and by Cohen [ l o ] . 1.2 Language Features

The operations common t o all symbol manipulation languages are those involving the creation and decomposition of lists. At a minimum, it must be possible to create a list by combining existing elements of lists. and to extract a portion of a list. Beyond that, the linguistic treatment of symbol manipulation varies enormously from language to language and is quite difficult t o generalize. Further discussion on this topic is therefore left t o the discussion of the individual symbol manipulation languages. Increasingly, symbol manipulation languages have tended to include more general computational facilities. Some of them, e.g., SLIP,Formula ALGOL.and the PL/I list processing facilities, have been achieved by embedding, that is, by adding list processing to an existing language.

SYMBOL MANIPULATION LANGUAGES

57

For SLIP,there have been several host languages, notably FORTRAN and MAD. Formula ALGOLis an extension of ALGOL,and the list processing features of PL/I were a later addition to that language. On the other hand, LISP and SNOBOL reached the same result via a different path; they started out as pure symbol manipulation languages with only the most rudimentary facilities for anything else, but user requirements pushed them further and further into general computation. LISP 2 and SNOBOL4 are the results. A useful, though now somewhat outdated, comparison of several symbol manipulation languages is given by Bobrow and Raphael [5]. 2. LISP 2

LISP 2 is the most recent version of the list processing language LISP (an acronym for LISt Processing). Its immediate predecessor, LISP 1.5, is described in Section 3 . Although only one implementation of LISP 2 exists at the time of this writing, and furthermore that implementation is on a one-of-a-kind computer, LISP 2 is nevertheless a good starting point because of its resemblance to the well-known language ALGOL. LISP 2 was developed jointly by the System Development Corporation (SDC)and Information International, Inc. ; the present implementation on the Q32 time-sharing system at SDC was completed in 1967. A general description of LISP 2 is given by Abrahams et al. [Z];a more precise definition appears in a series of technical notes issued by SDC [38].The description here is based on those technical notes. LISP 2 was developed in order to correct some of the deficiencies of LISP 1.5, most importantly its inconvenient input language and its gross inefliciency in numerical calculations. In order t o remedy the difficulties with the input language, LISP 2 adopted an ALcoL-like source language (sL); an intermediate language (IL) resembling Lrsp 1.5 was also provided. The difficulties with numerical calculations were remedied through the introduction of type declarations and an optimizing compiler. The advantages of LISP 2 are its symbol manipulating capabilities, its ability to treat programs as data, its flexibility in handling many different types of data, and the ease with which the basic system can be modified. Its disadvantages are its excessive space consumption and the complexity of its specifications; these disadvantages are probably responsible for the difficulties encountered in implementing it. 2.1 Data

LISP 2 data are of two kinds: elements and ntuples. Elements, which we discuss first, consist of numbers, Boolean values, strings, symbols, and

58

PAUL W. ABRAHAMS

functions. Ntuples consist of nodes (a generalized form of list), arrays, and additional programmer-defined data types. There are three kinds of numbers in LISP2: reals, integers, and binary numbers. Integers and binary numbers differ primarily in their external representations. The external representations of real and integer numbers are similar to those of FORTRAN: the external representation of a binary number consists of a sequence of octal digits followed by the letter Q followed by an optional scale factor. The Boolean data consist of TRUE and FALSE. A string is externally represented by a sequence of characters enclosed by the character # ”, e.g., “ #STRING # ”. Within the string, any sequence “ ‘c ”, where c is any character, is equivalent to the character c by itself. Thus it is possible to include the characters # ” and ’ ” within a string. Symbols consist of ident.ifiers, characters, special spellings, and markoperators. The external representation of an identifier consists of a sequence of letters, digits, and periods starting with a letter. The external representation of a character consists of ‘( # ” followed by the desired character, e.g., ‘‘ $4-” or “ #A”. The external representation of a special spelling consists of a string preceded by “%,” e.g., ‘(O 0 # THIS IS AN IDENTIFIER # ”. The external representation of a mark-operator consists of a sequence of operator characters such as + ” or **” I n LISP 2. functions are a kind of datum. The external representation of a function depends upon whether the function is being read in or print,ed out. The external representation of a function to be read in is of the form “[F~-’NCTION name]’’ where name is an identifier that names the function. The actual datum thus denoted is a compiled subroutine. Functions as data are one of the unusual features of LISP.For instance, in LISP 2 it is possible to form an array whose elements are functions; this is not possible in ALGOL,FORTRAN, or PL/I without the use of elaborate artifices. Lists are represented externally in the notation described in Section 1.1, and internally in the form of one-way lists. The identifier NIL is used as the list terminator. The cells that compose a list are called nodes; each node contains the location of an item and the location of the next node in the list. For multilevel lists, the item may itself be a node. Thus a node is really a datum containing the location of two other data. The LISPfunction CAR, when applied to a node, yields the first component of the node, i.e., the list item; the LISP function C D R , ~when ((

((

((

‘1

These namcs originated with the early implementation of LISP on the IBM 704; stands for Contents of Address Register and CDR stands for Contents of Decrement Register. 1

CAR

SYMBOL MANIPULATION LANGUAGES

59

applied to a node, yields the second component of the node, i.e., the remainder of the list. Nodes can be used to represent more general structures than lists, since the CDR component of a node is not restricted to be another node or NIL. These generalized lists are actually binary trees with the restriction that only the end points can be labeled. They are represented externally in a notation utilizing dots; " ( a . ,t?)" represents the node whose CAR component is a and whose CDR component is ,t?. This notation can be generalized; thus " (a1uz . . . u n . ,t?) '' represents a structure obtained from the list (a1a2 . . . an)by replacing the terminating NIL by 8. I n Fig. 2 we see some examples of these generalized lists, together with

c1

I

**=Dl

]NIL

]

( A 1 El (C1 D1)) or

(A1 B l

(Cl D1) . N I L )

or

(A1 81 (CI Dl-NIL).NIL) (0)

(A1

El C l - D l )

or (Ale (El. (C1. D1))) (b)

FIG.2. Examples of node structures.

some (but not all) of their alternative external representations. An ordinary list can be represented externally in the dot notatioii as well as in the notation introduced earlier. It follows, then, that the external representation of a list is not unique. When a node is printed, the external representation used is the one with the minimum number of dots; thus, ordinary lists are printed in the usual way. In Fig. 3 we see another example of a node structure as represented both internally and externally. In Fig. 3b there is one node that is pointed to from two places. This node is used to represent a merge point of the binary tree descending from the top node and corresponds to a repeated part of the external representation. Note that the node structure of Fig. 3a has the same external representation as that of Fig. 3b but uses more storage. An array is represented internally as a sequential block of cells preceded by a header word giving the type of the elements and the

60

PAUL W. ABRAHAMS

dimensionality. Bllof the elements must have the same type. Externally, an array is represented as a sequence of elements enclosed in brackets and preceded by the array type. For multidimensional arrays, several levels of bracketing are used. The programmer may define ntuples in addition t o nodes and arrays. I n general, an ntuple is an ordered collection of data. Associated with each kind of ntuple is a collection of coordinate functions by means of which the individual components of a particular ntuple may be extracted. I n the case of a node, t,he coordinate functions are CAR and CDR.

-

n I I

4iEI

t ] I

I(b!

( a ~

FIG.3. Two representations of and ( h ) common storage.

I

(A.

( ( c. D ) . ( ( c. D ) . x))):( a )no common storage

In the case of an array, there are as many coordinate functions as there are elements in the array; the application of a coordinate function to an array is expressed in the usual subscript notation. I n the case of a programmer-defined ntuple, the coordinate functions are specified by the programmer in much the same way as a data structure is specified in COBOL,PL,'I, or JOVIAL.Since LISP 2 was developed a t SDC, which also developed JOVIAL, the influence of JOVIALdata structure specification on LISP 2 has been strong. For any datum except a function, a number, or a Boolean, the token of the datum is a location. Thus the problem of data puns arises only for functions, numbers, and Booleans. The solution adopted by LISP 2 is somewhat complicated, and is based upon the use of type declarations, both implicit and explieit. We use the case of the integer 479 as a n example. There are two possible internal representations for 479, as shown in Fig. 4. One representation consists of the number itself; the other consists of a pointer to a one-word array whose header indicates that the number is in fact an integer (as distinguished from a real, say). If we wish to add two variables whose values are integers given in the pointer representation, then we must trace down the pointers, locate the actual numbers, and add them. If the resulting value is to be in the same form, then we must create a new array and pass along the pointer to it as the result of the addition. On the other hand, if the variables .in question had their values represented directly, then two fetches, an

SYMBOL MANlPULATlON LANGUAGES

61

add, and a store would suffice. The advantage of the direct representation is that it leads to efficient calculation; the advantage of the indirect representation is that the data are self-descriptive. The type of a data token is a rule for interpreting it, i.e., for determining the datum that the token represents. A field is a location within LISP’Sstorage that is capable of holding a data token; every such field has a type associated with it. Examples of such fields are storage words reserved for variables, the pushdown stack used for temporary storage, the CAR and CDR portions of a node, and the elements of an array. If the type associated with a field is INTEGER, say, then 479 would be stored in that field in its direct representation-but that field could only be

kid Header

FIG.4. Two representations of 479: (a) direct and ( b ) indirect.

(b)

used to hold integers, and could not be used to hold nodes, arrays, functions, etc. If the type associated with a field is GENERAL, then any datum whatsoever can be stored there-but any such datum must be in the form of a pointer. Thus GENERAL is used to describe fields where any kind of datum might be stored. The type of a variable is determined by a type declaration made €or the variable, or by default. The type ofa part of an ntuple is determined by the definition of that kind of ntuple. I? particular, the CAR and CDR portions of a node are always of type GENERAL (and thus cannot be used to hold numbers in their direct representation). For arrays, the type of the elements is determined by the header; the array as a whole is treated as being GENERAL. Thus a datum declared REAL ARRAY will contain elements of type REAL, i.e., actual numbers; an array containing those same numbers in the indirect representation would have type GENERAL ARRAY.

2.2 Program Structure

A LISP program is specified as a sequence of declarations of various kinds. The most important kind of declaration is the function definition, which is equivalent to a procedure declaration in ALGOL. Declarations are made under the aegis of the LISP Supervisor, which recognizes two kinds of actions : declarations and evaluation of expressions. In order to run a program in the usual sense, one first defines a

62

PAUL W. ABRAHAMS

function that carries out the desired operations and then invokes this function by evaluating an expression. Since functions can themselves call functions, one can construct hierarchies of functions in the same way that one constructs hierarchies of procedures or subroutines. Recursion is permitted and indeed (in the L I S P community) encouraged and admired. Although LISP 2 introduces quite a number of extensions to ALGOL in program structure as well as in data structure, remarkably few of these extensions are peculiar to the needs of list processing. Most of these needs are met purely through the introduction of appropriate data types and conversion rules among data types. Therefore, although we will at least mention most of these extensions, we will not dwell upon them in detail. A LISP 2 function definition consists of two parts: the heading and the body. The heading gives the name of the function, the names and types of the formal parameters, and the type of the value returned by the function. The body is (unlike ALGOL)an expression; evaluation of this expression gives the value of the function. A simple example of a LISP 2 function definition (in SL) is the recursive definition of the factorial function FACTORIAL FUNCTION(N) INTEGER; N INTEGER: IF N = 0 THEN

1 ELSE

The corresponding definition in

IL

N * FACTORIAL(N

-

is

(FACTORIAL FITNDEF(FUNCTION (FACTORIAL INTEGER) (IF ( = K

0) 1 (*

N (FACTORIAL

(-

1)

N

( (N

INTEGER))

1))))))

In both of these examples, the first line is the heading and the second line is the body. (Since SL and IL are both written in a free-field format, this arrangement is not required.) This particular function happens to have a recursive definition. In LISP 2 , evaluation of an expression yields a valuation; valuations are characterized by a type and a reference mode. If the reference mode is NOVALUE, then the valuation consists of nonsense information and the expression may only be evaluated for its side effects. If the reference mode is anything else, then the valuation has as part of it a value, which is a data token. The reference mode then determines how the value is to be obtained from the valuation. The UNFIELDED, DIRECT, and INDIRECT reference modes are illustrated in Fig. 5. Evaluation of an UNFIELDED expression yields a value only; the location containing that value is not accessible to the program. Constants always have the UNFIELDED reference mode. Evaluation of a DIRECT expression yields a pointer to a field containing the value. Evaluation of an INDIRECT

SYMBOL MANIPULATION LANGUAGES

63

expression yields a pointer to a field whose contents are in turn a pointer to a field containing the value. The interpretation of this value is, of course, determined by the type of the valuation. The type and reference mode of an expression are determined completely by the expression itself and the context in which it appears; they do not vary from one evaluation of the expression to the next. The actual value and the various pointers involved may very well vary from one evaluation to the next. The rationale behind this particular generalization was to permit assignments to be made to components of list structures and other ntuples as well as to arrays and variables. In both ALGOL and FORTRAN, the left side of an assignment statement must be either an ordinary variable or an array reference; PL/I permits certain more general forms,

Value (0)

m Value (b)

s Value (C)

FIG.5. Reference modes of an expression: (a) unfielded, (b) direct, and (c) indirect.

but does not permit functions to appear on the left side of an assignment statement. In LISP 2, the reference mode of the left side of an assignment must be either DIRECT or INDIRECT. (The default reference mode of a variable is DLRECT.) Expressions with either of these reference modes satisfy the essential requirement for the left side of an assignment, namely, they provide a location where a value can be placed. An expression such as ‘‘ CAR(A) ”, where A is a variable whose value is a node, has the DIRECT reference mode and thus designates the actual field which is the CAR part of A. The introduction of reference modes also permits more general expressions, e.g., conditionals, to appear on the left side of assignments. A block consists of a sequence of statements enclosed in the statement brackets “BEGIN” and “END”, and preceded by some declarations of variables local to the block. The declarations are separated from each other by semicolons, and the last one is followed by a colon. If there are no declarations, ‘‘ DO ” without the colon is used instead of ‘‘ BEGIN: ” to avoid certain syntactic ambiguities. The following kinds of statements are permitted: (1) Expressions. When an expression is encountered in a context where a statement is expected, the expression is evaluated and the

64

PAUL W. ABRAHAMS

resulting valuation is simply discarded. In particular, assignments are accomplished through the evaluation of assignment expressions, described below, rather than through a distinct statement type. (2) Block statements. These are as in ALGOL. (3) Cmpound statements. These are as in ALGOL. (4)Go statements, These are of the form “ GO a ”, where a must be a label. Label variables such as those used in PL/I are not permitted. (5) Conditional statements. These are as in ALGOL. (6) Case statements. These resemble the computed GO TO of FORTRAN and the GO TO statement with a designational expression in ALGOL. (7) Return statements. The statement “RETURN a” has two effects: it causes exit from the block containing it, and it causes that block to have a valuation, namely, the valuation of z. Under certain circumstances, execution of a return statement may cause an exit from surrounding blocks as well. The return statement is one of the more pleasant features of LISP 2, and in fact numerous modifications to ALGOLhave introduced similar facilities. (8) Code statements. These are as in ALGOL. (9) T r y statements. A try statement has the form “TRY v, s1, SZ” where w is a variable and s1 and sz are statements. First the statement s1 is executed. If during the execution of this statement the function EXIT (of one argument) is evaluated, then control reverts through as many levels as necessary to return to the try statement. The value of v becomes the value of the argument of EXIT, and the statement s2 is executed. If no EXIT is encountered during the execution of s1, then cont.ro1simply proceeds to the statement following the try statement. (10) For statements. For statements are similar to those in ALGOL, but include additional special forms appropriate to list processing. For instance. the statement: FOR V IN

1 :S

causes the statement s to be executed once for each element in the list 1 ; during these successive executions, the successive values of v are the successive elements of 1. Assignments are performed by assignment expressions, which are of the form: a+/3

Here a must have reference mode DIRECT or INDIRECT and /3 may have any reference mode except NOVALUE. The valuation of the entire assignment expression is simply the valuation of /3; however, evaluating the assignment expression has the side effect of replacing the value of a by the value of /3, i.e., changing the contents of the field that contains

SYMBOL MANIPULATION LANGUAGES

65

the value of a. Since assignments are expressions, they can be embedded within actual parameters of function calls, for instance. Nested assignment expressions are permitted. Operations on lists are accomplished primarily through the application of appropriate functions rather than through special syntactic devices (the for statement being an exception). The basic operations on lists are performed by the functions CAR and CDR, by the infix operation “ o ” (read as “ cons ” for construct), and by equality testing. The functions CAR and CDR each expect one argument, which must be a node, and return as value respectively the CAR and CDR parts of that node. The expression “ a 0 /3 ” creates a new node whose CAR part is a and whose CDR part is ,!I. Equality testing is accomplished by extending the definition of the equality operator ‘‘ = ” to ntuples; two ntuples are equal if their external representations are equal. (There is a diBrent equality test for actual identity of pointers; this other test will distinguish different copies of the same list with different internal representations but the same external representation.) In addition to these basic facilities, LISP provides a library of other useful functions, e.g., APPEND(X,Y) which expects two lists as arguments and returns a new list whose elements consist of the elements of x followed by the elements of y . In order to use identifiers and nodes as constants within a program, a quotation convention is needed. Otherwise there would be no way to distinguish the identifier “ ABC ”, used as a constant, from the variable “ABC ”. Therefore, any constant may be preceded by a “ ’ ”, and constant identifiers must be preceded by a “ ‘ ”. Thus “ 127 ” and “ ‘127 ” are both the same numerical constant; “ABC ’’ is a variable; and “ ’ABC ” is a constant, as is “ ‘(A B c)”. As we mentioned earlier, functions can be used as data. For example, consider the following sequence of statements : A +FUNCTION(X,Y);

X,Y REAL:

xT2 + ~ 1 ’ 2 X*Y;

x +-~(2,5); A +-FUNCTION(X,Z); Y t

X f

x,z REAL: x f 2

+ z t 2 + x*z;

A(1,2)

Evaluatien of the right side of the first assignment expression yields a function. (Recall the remark earlier that an expression can be used in any context where a statement is expected.) Within this function x and Y are dummy variables and bear no relationship to the x and Y appearing on the left side of the assignment expressions. After the sequence of statements is executed, the value of the variable x is 19 and the value of the variable Y is 26.

66

PAUL W. ABRAHAMS

In Fig. 6 we see a LISP 2 program that computes the longest common segment (i.e., subsequence of elements) of two lists. It uses a version of the for st,atement, governed by ON ”, in which the controlled variable assumes as successive values the initial list, the initial list less its first element, the initial list less its first two elements, etc. In the block I‘

% R LCS F I N D S THE LONGEST COMMON SEGMENT O F TWO LISTS % fi L1 A N C L2

,

LZS FUNCTION(

~1 L Z )

:

B E G I N X, Y, BEST GENERAL; K, N, LX INTEGER; LX t L E N G T H ( L 1 ) ; FOR X ON L 1 W H I L E LX > K: B E G I N I N T E G E R LY; LY

t LENGTH(L2);

F O R Y ON L2 WHLLE LY DO N

>

K:

i COMSEGL(X,Y);

IF N

2 K

K+

N;

THEN GO A;

BEST + COMSEG(X, Y ) ; A:

-

LY t LY

1;

END;

L X t

Lx -1;

END; RETURN B E S T ; END;

%R COMSEGL F I N D S THE LENGTH OF THE LONGEST I N I T I A L COMMON % R SEGMENT O F I W O LISTS X AND Y COMSEGL F U N C T I O N ( X , Y ) ZAR(X)

4

INTEGER:

IF MILz(X)

v

NULL(Y)

CAR(Y) THEN 0 ELSE COMSEGL(CDR(X),

CDR(Y))

+ 1;

% R COlvlSEG FINDS T H E LONGEST I N I T I A L COMMON SEGMENT OF TWO % R LISTS X AND Y COEEG

IF NULL(X)

FUNCTION(X,Y):

THEN N I L E I S E CAR(X)

v

v

NULL(Y)

COMSEG(CDR(X),

V

CAR(X)

CDR(Y));

FIG.6. A LISP 2 program.

i/

CAR(Y)

SYMBOL MANIPULATION LANGUAGES

67

declarations, the assignments are used to specify initial values to be used upon entering the block. The function NULL yields TRUE as value if its argument is the empty list and FALSE otherwise. The function LENGTH(%) has as its value the length of the list x. The types of all formal parameters and of all functions except COMSEGL are assumed to be GENERAL by default. Initial values not specified explicitly are determined by default; in particular, the default initial values for the INTEGER variables are all 0 and for the GENERAL variables are all NIL. The basic concept in LISP 2 input-output is the file. A file is a named data stream agsociated with an input-output device such as tape, a disk, or a printer. Many files may exist at the same time; of these, one is selected to be the input file and one to be the output file. The input file acts as a source of single characters, and the output file acts as a sink of single characters. Input and output are defined in terms of two basic functions: READCH and PRINCH. READCH( ) 2 has as its value the next character. that can be read from the input file; PRINCH(X) writes the character x into the output file, and incidentally has x as its value. The functions READ and PRINT are defined in terms of READCH and PRINCH, respectively, and these read or write the external representation of a single datum. (Since a datum may be a complicated list structure, it may occupy several lines.) There no are input or output statements as such; all input and output is done by means of functions. LISP 2 does not have any formatting in the usual sense. Because of its variable length, symbolic data raise unusual problems in formatting; however, since LISP 2 is also intended for numerical use, the lack of formatting is a serious drawback. LISP 2 does provide for the handling and adjustment of margins. For any file, a left and right margin may be specified, subject to the physical line length limitations of the device associated with the file. The first character on any line is read from or written onto the left margin position, which need not be the first available character position on the line. When the character position moves past the right margin, a user-specified margin overflow function is invoked. Similar functions exist for page position, and there is also a tab function for positioning within a line. These formatting functions are independent for different files, and may be modified dynamically during input or output. There are selection functions, INPUT(!) and OUTPUT(!), that select an input file or an output file, deselecting the previous input or output file. The value of each of these functions is the previously selected file. When a file is deselected, its entire state is preserved, and again restored 2

The ‘‘ ( ) ” notation indicates that

READCR

is a function of zero arguments.

68

PAUL W. ABRAHAMS

when the file is reselected. Thus the appearance of simultaneous input and output on several files can be maintained with no difficulty; the user merely selects the file he wishes to operate upon before performing the operation. The function OPEX associates a file with a physical device; the function SHCT breaks this association. 2.3 implementation of LISP 2 The LISP 2 system provides an environment in which LISP 2 programs can be read in, compiled, and executed. There is no sharp division between these activities, and the user may shift back and forth among them. The principal components of the system are: ( I ) Supervisor-handles

over-all control and processes requests for action. (2) Syntax-directed translator-translates SL to IL. ( 3 ) Compiler-- translates IL to assembly language. (4) Assembler-transla~es assembly language into relocatable binary code. ( 5 ) Input-output functions-handle reading, printing, and file manipulation. (6) Garbage collector-recovers abandoned storage. ( 7 ) Library-provides a collection of useful functions.

Programs may be brought into the system either by typing them in on a terminal device or reading them in from a file. Under user control, programs may then be t,ranslated successively from SL to IL by the syntax-directed translator, from IL to assembly language by the compiler. and from assembly language to code by the assembler. They may be called by giving the function name and a list of arguments. (All of the translators are themselves callable programs.) There are two reasons for the division of the translation process into several stages. First, the various intermediate forms are thenuelves useful languages. In particular, progianis that operate on programs work much more easily with IL than with SL. Second, the task of translating from SL to IL is primarily one of pattern-matching in one-level lists, while the task of translating from IL to assembly language is primarily one of complex structure manipulation. The tools that are appropriate €or one task are not the best for the other. The garbage collector is perhaps one of the most interesting features of the LISP 2 implementation. JIany of the ideas used in it are due to Ross [31. 351. Storage areas are set aside for various kinds of data structures used by LISP. Some of these are arranged in pairs, where one member takes space from the bottom up and the other takes space from

SYMBOL MANIPULATION LANGUAGES

69

the top down. When any area is exhausted, or when the boundaries of two paired areas meet, a garbage collection is necessary. Garbage collection proceeds in four phases: ( 1 ) Marking. All active data structures are traced, and a mark is associated with each. The mark may be placed either directly in the structure or in a bit table. Any data not marked are known to be inaccessible to the program and therefore may be safely erased. (2) Planning. The planning phase is a preparation for the moving phase which follows it. During the moving phase, various data structures are relocated. Pn the planning phase, the new location of each data structure is determined and recorded. (3) Fixup. During the fixup phase, all pointers to data structures are updated to reflect the new location of the data structure. These pointers will occur both in temporary storage areas of the program itself and within data structures. The fixup phase also includes the modification where necessary of executable code. This modification is directed by a bit table associated with the code. (4) Moving. Storage is rearranged in order to pack active data and recovered space into solid blocks.

The garbage collector is actually initiated when one of the basic LISP structure-creating functions cannot obtain the storage that it needs. After the garbage collector is finished, control returns to the function that called it, and this function then proceeds t o create the structure that it could not create previously. Although the garbage collector can be invoked explicitly by the user, it never needs to be; the LISPsystem itself will invoke it when it is needed. 3. LISP1.5

LISP 1.5 is, historically, the programming language that led to LISP2. LISP 1.5 is in turn derived from the original LISP 1 as described by McCarthy [24].LISP 1 was characterized by great elegance, but in practice it turned out to be a language in which it was impossible to write useful programs. This situation led to many additions to LISP1, and the result of these additions has become known as LISP 1.5 (since it was believed to be halfway between LISP1 and LISP 2). The definition of LISP 1.5 is somewhat imprecise, in that there exist a number of implementations of LISP which are considered by both their authors and users to be LISP 1.5 but which differ in many details. The two bestdocumented versions are LISP 1.5 for the IBM 7090 [25],developed a t MIT, and LISP 1.5 for the System Development Corporation timesharing system [39]. A collection of articles describing a number of

70

PAUL W. ABRAHAMS

LISP 1.5 applications, implementations, and improvements has been published by Information International, Inc. [16]and subsequently reprinted by the MIT Press. Unlike LISP 2, LISP 1.5 has been widely implemented and widely used. 3.1 Pure LISP

Pure LISP exists as a language for defining functions of symbolic expressions, known as S-expressions. An S-expression is a particular case of the node structures of LISP 2. These S-expressions are built up from atoms, which are the same as the identifiers of LISP 2; S-expressions are defined as follows: (a) Every atom (i.e., identifier) is an S-expression. (b) If a1 and a2 are S-expressions, then (a1 . az) is an S-expression. In other words, if a1 and a2 are S-expressions, then the node whose CAR component is a1 and whose CDR component is a2 is an S-expression. The various alternative notations for nodes are acceptable, e.g., (a1 a2 . , . a n ) is equivaient to (“1. ( a z .

... . ( a n . NIL)

...))

There are five basic functions in pure LISPthat operate on symbolic expressions: CAR, CDR, CONS, EQ, and ATOM. CAR, CDR, and CONS are as in LISP2. EQ(X,Y) is defined if and only if a t least one of its arguments is an atom. Its value is the atom T (for “ true ”) if x and y are the same S-expression, and F (for “false ”) otherwise; ATOM(Z) has as its value T if x is an atom, and F otherwise. It is defined for all S-expressions. A LISP function is itself represented as an S-expression, in a form quite similar to that of the intermediate language of LISP 2. The form

(fa i

a2

. . . an)

indicates the application of the function f to the arguments a l , a2 . . . a n . The application is carried out by evaluating f,u1, a2 , . . . ,an in sequence and then applying the value off (which must be a function of n arguments) to a 1 , a z , . . . , a n . The form (COND

(PIe l ) (PZe 2 ) * * *

(pn en))

resembles the conditional expression of LISP2. It is evaluated by evaluating the pr in turn until one is found whose value is T. The value of the entire form is then obtained by evaluating the corresponding e i . None of the other eg’s are evaluated, nor are any of the pt following the first true one.

SYMBOL MANIPULATION LANGUAGES

71

A function is represented in the form:

.

(LAMBDA (XIz 2 . . 2),

a)

where the zt are atoms representing dummy variables appearing in the expression u. Application of a function to arguments is carried out by substituting the value of each argument for the corresponding x{ in u and then evaluating the result of this substitution In order to permit recursive functions to be expressed in closed form, an additional device is needed. Evaluation of the form (LABEL f a)

yields the function a (which must be a LAMBDA expression) and in addition associates the function name f (which must be an atom) with a so that during the application of u to arguments, any occurrence o f f evaluates to u. Thus a function may be made recursive by naming it via LABEL and then using this name within the definition, i.e., within the LAMBDA expression. Although the LABEL device is necessary in pure LISP,it has virtually no application in actual programming because of much more convenient mechanisms for defining recursive functions. Given the apparatus just described-the five basic functions, application of functions to arguments, LAMBDA, LABEL, and conditional expressions-it is possible to write an interpreter for LISPin LISP.This interpreter is the analog of a universal Turing machine, in that its input is a LISP function together with arguments, its output is the result of applying that function to the arguments, and the interpreter itself is written in the same language as the program that it is interpreting. Much of the interest in LISPfrom the standpoint of the theory of computation devolves from the fact that LISP is universal in this sense. 3.2 Features Added t o Pure

LISP

While pure LISPwas a thing of beauty to computational theorists, it turned out in practice to be inadequate to the needs of writing programs. At the same time, its simplicity, self-interpretive properties, and symbol manipulating capabilities made it a desirable basis on which to develop a usable language. The main improvements that characterize LISP 1.5 are: (1) DeJinitions and permanent values. It is possible to associate a value with any identifier. In the case of an identifier whose value is a function, the association is created through use of the LISPfunction DEFINE, Normally, a LISP program consists of a sequence of applicetions of functions to arguments. Thus, in order to create it complicated

72

PAUL W. ABRAHAMS

function with many subfunctions, DEFINE is used to associate the definition of each function with its name. Any of these functions may refer to any other function or t o itself by name within its definition. In addition, i t is often useful to assign constant symbolic expressions as values of certain atoms. The function CSET has two arguments: an identifier and a value. Evaluation of CSET causes the value t o be associated with the identifier; any subsequent evaluation of the identifier will yield this associated value. More generally, an identifier has associated with it a property list. Specific properties of an identifier (of which its CsET-assigned value is one) are indicated by placing the name of the property on the property list followed by the associated value. Properties without associated values are also permitted. As an example, in an interpreter-based system one of the properties of a function name will be EXPR. The identifier EXPR will appear as an element of the property list of the function name, and will be followed immediately by the S-expression giving the function definition. (2) Xumbers. LISP 1.5 has a full complement of arithmetic facilities, although their use is still somewhat awkward because of the parenthesized prefix notation, e.g., “ (TIMESA (PLUS B 5))” for “A*(B 5 ) ”. Because of the problem of “ data puns ” alluded t o in Section 1.1, the LISP 1.5 system has needed to adopt an artifice in order to deal with numbers. The most common artifice is the use of indirect storage, sometimes called boxing; a less common artifice is a combination of indirect storage for large numbers and direct storage for numbers whose magnitude is smaller than that of the lowest address usable for list structure storage. Indirect storage is, however, quite costly in both time and space, and one of the major drawbacks of LISP 1.5 has been its inefficiency in arithmetic calculations. (3) Seqzcentinl proqmrns. A major addition was the program feature ” to permit programs to be defined as a sequence of statements rather than in the purely functional form. X program is written in the form (PROG (2’1 v 2 . . . v,) s1 s2 . . . sm) where the v( are local variables and the si are statements. The local variables are assigned storagr when evaluation of the PROG form commences, and this storage is released when evaluation is completed. Each statement is interpreted as an expression to be evaluated. The statements are evaluated in turn, and the values are then thrown away, so that the evaluation is always performed for the sake of its side effects. The expression

+

“

(SETQ 5 a)

evaluates the expression u and assigns this value to the variable x.

SYMBOL MANIPULATION LANGUAGES

73

The expression (RETURN a )

terminates evaluation of the PROG form and causes the value of the PROG form to be the value of a. Labels, in the form of identifiers, may be intermixed with statements; evaluation of the expression (GO

4

causes execution to continue with the statement following the label x. If a conditional expression is evaluated and none of the pi are true, then control proceeds to the next statement, and the fact that the value is undefined does not (in this context) cause an error. (4) Compilation. The original LISP system was interpreter-based. However, compilers have been added to several LISP 1.5 system. I n some cases, the compiler has been used as a replacement for the interpreter; in others, the compiler and the interpreter coexist. Compilation appears to improve the running speed of LISPprograms by a factor of about 50. I n LISP, the interpreter ordinarily exists as a function callable by the programmer. The function E V A L ~is the most useful form of the interpreter; given a symbolic expression, E V A L ~determines its value. Interpretation is required because the functions occurring in the expression to be evaluated must be applied to their arguments in an appropriate manner. In systems with a compiler only, an interesting approach has been taken t o the implementation of E V A L ~ ;namely, the expression to be evaluated is transformed into a function of no arguments, this function is then compiled, the compiled function is applied to its null set of arguments, and the result of this application is the desired value of the expression. The compiled program is then thrown away. ( 5 ) Character manipulation. It was found desirable in many cases to manipulate data in an arbitrary format, For this purpose, character manipulation functions were provided in LISP. These functions permitted input or output of a character at a time, termination of an input or output line, designation of any character as an atom, formation of a sequence of characters into either an identifier or a number, and decomposition of either a n identifier or a number into its component characters. (6) Macros. Macros are included in many (but not all) versions of LISP 1.5. Each macro is associated with a particular identifier and consists of a transformation function. Let m be the name of a macro with transformation function f (which must be a function of one argument). Suppose that during evaluation of an expression a subexpression u is encountered whose first element (i.e., the element in the function posi-

74

PAUL W. ABRAHAMS

tion) is m. Then the entire subexpression a is replaced by the result of applying f to a, and this new expression is then evaluated. Since the new expression may itself contain macro names, macro definitions may effectively be recursive. Figure 7 gives the LISP 1.5 program for LCS that corresponds to the LISP 2 program for the same function as given in Fig. 6. The function OREATERP yields T if its first argument is numerically greater than its second argument, and F otherwise. The function s u s l subtracts 1 from its argument. All the remaining functions and operators have already been explained. 4. L6

A highly machine-oriented (though moderately machine-independent) list processing language developed by Knowlton at Bell Telephone Laboratories in 1966 is L6 (Laboratories Low Level Linked List Language) [19].In contrast to LISP, it gives the programmer very precise control over the allocation of storage, but a t the cost of much more detailed programming. In L6, the representation of data is determined entirely by the programmer. Storage is allocated in units called blocks; a block consists of 2 n machine words. In the 7094 implementation, n ranges from 1 to 7. Part of an L6 program consists of the definition ofjelds; field definitions may be changed dynamically as a program is run. A field is defined by designating its name (a single letter or digit), a word of a block, and a group of bits within that word. Fields may overlap or be contained within one another, and their contents are quite arbitrary. One possible content of a field is a pointer, which is the address of the 0th word of another block. The length of such a field must be greater than or equal to the address size of the machine The programmer has available to him a set of 26 base fields, called bugs. These are designated by the letters of the alphabet, and constitute the explicit variables of L6. These variables may be operated upon by field nanies. Thus the sequence " W ~ W Q A A R'' refers to a field that is obtained by taking the block which is the value of the bug W, then taking the block pointed to by the 9 field within block w, then taking the block pointed to by the w field within block w9, etc. Note that w is used both as a bug and as a field, and these uses are independent. Note also that all the fields in the sequence except for R must be pointers. The xse of blocks, fields, pointers, and bugs is illustrated in Fig. 8. A pointer from a field to a block indicates that the field contains the location of the 0th word of the block. There are two 2-blocks and a 4-block in this diagram, and two bugs: T and R, where T refers to the leftmost

75

SYMBOL MANIPULATION LANGUAGES

block and R refers to the rightmost block. The J field of the rightmost block may be referred to as RJ, TBJ, or TCBCJ (among the many possibilites). Note that the two leftmost blocks have the same division of their first two words into fields, but that the rightmost block has a DEFINE( ( (LCS (LAMBDA ( L 1 L2) (PROG ( X Y BEST K N LX) (SETQ

LX (LENGTH L l ) )

( S E Q T K 0) (SETQ A1

x u)

(COND ( ( O R (NULL X ) (NOT (GREATERP LX K ) ) ) (GO A 4 1 1 1 (SETQ LY (LENGTH L2) ) (SETQ Y L2)

A2

(COND ( (OR (NULL Y ) (NOT (GREATERP LY K ) ) ) (GO A 3 1 1 1

( S m N (COmEGL X Y ) ) (COND ( ( N O T (GREATERP N K ) ) (SEW

(GO A ) ) )

K N)

(SETQ BEST (COMSEG X Y ) ) (SETQ LY

(sum

(SETQ Y

CDR y ) )

LY))

(GO A2) A3

( S E T Q LX (SETQ

x

(GO A l ) A4

(RETURN BEST)

)))

(COMSEGL (LAMBDA ( X Y ) (CONE ( ( O R (WLL X) (NULL Y ) (NOT (EQUAL (CAR X ) (CAR Y ) ) ) ) ( T (ADD1 ( C O W E G L (CDR X ) (CDR Y ) ) ) ) (COKSEG (LAMBDA

(x Y )

0)

)))

(CONE

( ( O R (NULL X) (NULL Y ) (NOT (EQUAL (CAR X) (CAR Y ) ) ) ) N I L ) ( T (CONS (CAR X ) ( C O W E G (CDR X ) (CDR Y ) ) ) )

FIG.7. LISP 1.5 program for LCS.

)))

76

PAUL W. ABRAHAMS

different division. Thus the B field occupies the same space as the J and K fields. An L6 program consists of a sequence of macro calls. A macro call may contain elementary tests, elementary operations, and a label that specifies where control is to go when the operations are completed. A macro call may itself be labeled. The elementary operations of L6 are concerned with setting up storage, defining fields, obtaining blocks of various sizes, freeing blocks that

P FIG.8. A group of linked blocks.

are no longer needed, performing arithmetic and logical operations, doing input-output, pushing down and popping up certain fixed stacks, and calling subroutines. Each elementary operation is expressed as a parenthesized list of elements; the first element of the list ordinarily indicates the field affected by the operation, the second element specifies the operation itself, and the remaining elements are the operands. For example, the operation (5,~~,21,35)

defines field B to consist of bits 21 through 35 of word 5 of a block. The operation ( O,DX,PE,PF) defines field x to consist of a group of bits in word 0. The starting bit is given by the contents of the E field of the block pointed to by bug P ; the ending bit is the contents of the F field of the same block. The operation (CG,GT,O)

causes the storage allocator to get a n 8-word block of storage, store its location in CG (i.e.. the G field of bug c ) ,and store the previous contents of CG in the D field of the newly obtained block. The rest of this block is 0. Had the operation been instead (CG,GT,8)

then the new block would have its initial contents entirely 0. The more

SYMBOL MANIPULATION LANGUAGES

77

elaborate form is useful in the creation of pushdown lists. The operator FR is used in order to free blocks; the decision as to when a block is to be freed must be made entirely by the programmer, and it is his responsibility to handle correctly such matters as the erasure of blocks that are pointed to by several other blocks. An example of an arithmetic operation is (V,-4,5) which adds 5 to the contents of bug v; another example is (RY,M,QY)

which multiplies the contents of field RY by the contents of field leaving the result in field RY. The operation

QY,

(C,XH,XYYZ)

replaces the contents of bug c by the exclusive OR of the old contents of c and the HolIerith literal “ X Y Y Z ” . As an illustration of the input-output operations, the operation (-%IN,6)

brings 6 characters from the system input device into the contents of bug c. The characters are brought in via a left shift, so that existing characters in c are shifted off the left end. The operation (C,PR4

1

prints 4 characters taken from the right end of c. The special character whose octal representation is 77 is used, as an end-of-line signal; on input, no characters are brought in after a 77 is encountered, and on output, the transmission of a 7 7 causes the end of a line and the beginning of a new one. The system provides two pushdown stacks to the programmer: the field contents pushdown and the field definition pushdown. A third stack, not visible to the programmer, is used for storing subroutine entries so that subroutines can be recursive. The operation (S,FC,B)

saves the contents of B on the field contents pushdown (leaving the contents of B undisturbed), and the operation (R,FC,B)

restores these contents. Similar operations exist for the field definition pushdown.

78

PAUL W. ABRAHAMS

There are two kinds of tests: numerical and logical. The test (BG,G,CG)

tests whether the contents of field BG are numerically greater than the contents of field CG. There are also tests for “ less than,” “ equal,” and “not equal.” The test (R,O,T)

tests whether the contents of R has a one bit in every position where the contents of T has a one bit; the command (R,Z,T)

does the same for zero bits. Instructions are made up from tests and operations. For example, the instruction: L1 IFANY (GX,E,GY)(GW,N,CY) THEN (XR,E,3)(XS,SD,5) L 5

has the label ~ 1It. is interpreted to mean that if any of the conditions preceding the ‘‘ THEN ” are satisfied, the operations following the L< THEX ” are t o be carried out, and control is then to go to the instruc. controlgoes to the next instruction. Aninstruction labeled ~ 6Otherwise tion may omit any of the three parts, namely, the tests, the operations, and the go-to. An unconditional instruction thus starts with “ THEN ”. 5. PL/I String and List Processing

The primary design aim of the programming language PL/I was to satisfy the requirements of commercial users, scientific users, and systems programmers simultaneously. Consequently, PL/I has borrowed heavily ALGOL, and COBOL; in addition, i t includes many features from FORTRAX, that are found in none of these languages. Some of these features, such as the ability to specify parallel coniputations, were included in the original design; others, such as the list processing features, were added in subsequent revisions. Originally, P L / I was specified by a joint committee of IBM and SHARE, the IBM users’ organization, and publicly released in March 1964; subsequent responsibility for the specifications was taken over by IBM. As of this writing, no computer manufacturer other than IBM has made PLjI available as a standard software package. The list processing features of PL/I were included primarily to satisfy the needs of compiler writers, particularly those who were interested in “writing PL/I in PL/I.” These features have in fact proved difficult t o implement, and though they are included in the full language specification [ I 7 ] , they are not included in F-level PL/I [18], which is IBM’s

SYMBOL MANIPULATION LANGUAGES

79

present version. A description of PL/I list processing was published by Lawson [ZO]. The essence of the approach is to introduce pointers as a class of data and to provide facilities for referencing the data that they point to. No special functions for list processing are provided; thus, housekeeping responsibilities such as erasure are entirely the programmer's responsibility. 5.1 String Processing

Facilities exist in PL/I for processing both strings of bits and strings of characters; we shall consider here only strings of characters. A character string (henceforth usually referred to merely as a string) consists of a sequence of zero or more characters. Character string constants are written by enclosing them in primes. Primes within the string are indicated by two consecutive primes; repetition of a string can be indicated by a preceding repetition factor in parentheses. Thus, 'ABCDEF'

'IT'

's ME'

(3)'CHA'

are all strings; the last of these is equivalent to 'CHACHACHA'. In PL/I, variables are described by means of the DECLARE statement. Thus, the statement DECLARE A FIXED,

~ ( 1 5 , 1 0 0CHARACTER ) (30), c POINTER;

declares the variable A to represent a single fixed-point number, the variable B to represent a 15 by 100 array of 30-character strings, and the variable c to represent a pointer. A DECLARE statement may specify many different attributes of avariable; thosenot specifiedaredeterminedeither by the context in which the variable is used or by a default assumption. Strings may be declared with either fixed or variable length, e.g. DECLARE A CHARACTER

(25), B

CHARACTER

c CHARACTER( *)

(17) VARYING,

VARYING;

In this case A is a string of exactly 25 characters, B is a variable-length string with a maximum of 17 characters, and c is a string whose length will be determined at the time storage is allocated for it. (Storage might be allocated either by using c as a formal parameter of a procedure or by using the ALLOCATE statement, described below.) A collection of functions is provided for operating on strings. The operator " 1 I " is used to indicate the concatenation of two strings, i.e., the string consisting of all the characters of the first string followed

80

PAUL W. ABRAHAMS

by all the characters of the second string. The function SUBSTR expects three arguments: a string s, an integer i, and an integerj. The value of S ~ B S T Rconsists of a sequence o f j characters extracted from s beginning with the ith one, with appropriate definitions for exceptional cases. j may be omitted, in which case the entire string from the ith character onward is obtained. The function INDEX expects two strings as arguments. If either of the two arguments is a null string, then INDEX returns 0. Otherwise it searches the first argument for an occurrence of the second argument as a substring. If such an occurrence is found, then the value O ~ I N D E X is the starting position within the first string of this substring. If such an occurrence is not found, INDEX returns 0. The function LENGTH expects a string as argument and returns as value the length of that string. The function REPEAT takes a string s and an integer n as arguments; its value is a string consisting of s repeated n times. I n addition to these functions, PL/I provides various methods for converting data of other types to and from character strings. Such conversions may be accomplished through assignments, through the use of an explicit conversion function, or through input-output functions that transmit external representations of data to character strings or take external representations of data from character strings. Rosin [33] has proposed some interesting modifications to the PLiI string processing capability. He replaces SUBSTR(S,I,J) by s( : I , . . J I - l ) , where the " . . . " is actually part of the notation. He uses the following related auxiliary notations :

+

x( : 1 ) - x ( :

I . . . I)

. ..J) = X ( : 1 .. . J) . . .) = x( : I . . . LENGTH(X))

X(:

x( : I X ( A : I)

. . . J ) E SUBSTR(X(A), I, J - I + 1)

(Actually, Rosin proposed the last of these as the basic notation, and defined the others in terms of it.) I n the case where J
. . . I N D E x ( X , Y ) + LENGTH(Y) - 1) x BEFORE Y returns x( : . . . IXDEX(X,Y) - 1 ) x AFTER Y returns x( : INDEX(X,Y) f LENGTH(Y) - 1 . . .) x FRON Y returns x( : INDEX(X,Y) . . .) Y IN x returns x( : INDEX(X,Y) . . . I N D E X ( X , Y ) + LENGTH(Y) - 1 ) X CPTO Y

returns

X( : 1

SYMBOL MANIPULATION LANGUAGES

81

If, in any of these operations, Y does not occur in x, the scan is said to fail and a pseudo-variable is set to indicate this. There is some ambiguity in Rosin’s proposal as to just what happens when a scan fails. He also proposes that the various string operators be permitted to appear on the left side of an assignment and cause modification of the string x when they appear in that context. 5.2 List Processing

The storage class of a PL/I variable determines the mechanism by which storage is assigned to it. There are four possible storage class attributes, as illustrated in the statement DECLARE(A STATIC, B AUTOMATIC,

c

CONTROLLED,

D BASED(P)) FIXED;

The parenthetical notation used here indicates that A, B, c , and D are all fixed-point variables. Storage for A is allocated exactly once, at the time when the program begins execution. Storage for B is allocated upon entrance t o the block or procedure in which B is declared, and released upon exit from that block or procedure. Storage for c is allocated explicitly when the statement ALLOCATE C

is executed, and freed when the statement FREE C

is executed. A, B, and c are nonbased variables; D is a based variable. In this case, P is contextually declared as a pointer (it could, but need not, also be declared as a pointer explicitly); D serves as a prototype for the location that P points to. The expression P->D

represents a fixed-point variable located a t the address given by P. It is the programmer’s responsibility to make sure that P actually points to a fixed-point variable. The symbol >” is read as “ qualifying,” and in this example D is said to be qualijied by the pointer P. If Q is another pointer, then Q - > D would be the fixed-point variable pointed to by Q ; P - > D and Q - > D may both exist at the same time, and may well be different. A reference to D by itself is taken to mean P - > D, since P was the pointer declared with D. If the declaration 6L-

DECLARE D BASED FIXED;

had been used instead, then all references to fied explicitly.

D

would need to be quali-

82

PAUL W. ABRAHAMS

The function ADDR, provided by PL/I, has as its single argument a variable name; its value is a pointer to that variable. Thus, if we write DECLARE ( A AUTOMATIC, B BASED(P)) FIXED; P = ADDR(A);

B=5;

the net effect will be to set the value of A to 5, since B really means the variable pointed to by P. Pointer qualifications may be nested, so that if we write DECLARE P POINTER, Q BASED(R), A FLOAT, B FLOAT CONTROLLED(Q); R = ADDR(P); P = ADDR(A);

R->Q->B

= 5.3;

then the net effect is to set A to 5.3. The rules of PL/I state that R - > Q->B is to be interpreted as ( R - > Q ) - > B . To understand this example, note that R - > Q designates the pointer that is pointed to by R ; that pointer is P. Qualifying B by R - > Q designates the floating variable pointed to by R - > Q, i.e., by P. Since P points to A, it is A that is set to 5.3. A constant pointer NULL is provided, which can be used as a list terminator; NULL does not point to any data. A structure is a hierarchical collection of variables, arrays, and substructures. The term strmcture as used in PL/I has no connection at all with list structures. A typical structure might be created by the statement DECLARE

1 DATE, 2 YEAR FIXED(4), 2 MONTH FIXED (2),

2 DAY, 3 DAY-OF-MONTH

FIXED(2),

3 WEEKDAY CHAR (3);

The integers appearing in this declaration identify level numbers. A substructure of a given structure is indicated through the use of a higher level number. Thus the total structure (which is a variable) is DATE. A date consists of a 4-digit year, a 2-digit month, and a day. The day in turn consists of a 2-digit day of the month and a 3-character day of the week. Suppose now that we wish to oonstruct a one-way one-level list of

SYMBOL MANIPULATION LANGUAGES

83

fixed-point numbers. Such a list can be organized using structures declared as follows: DECLARE 1 ELEMENT BASED(P), 2 NEXT POINTER, 2 CONTENT FIXED; This declaration establishes the format of each list element, which consists of a fixed-point number and a pointer to the next element. A procedure for adding a number to the head of a list L and returning as value a pointer to the next list would be: ADDNUM: PROCEDURE(L, N ) ; DECLARE L POINTER, N FIXED,

2

NEXT POINTER,

2

1 ELEMENT BASED(P),

CONTENT FIXED;

ALLOCATE ELEMENT SET(P);

NEXT = L ; CONTENT = N; RETURN(P) ; END ADDNUM;

Initially, the value of L would be NULL. The ALLOCATE statement causes storage to be set aside to hold the structure ELEMENT, i.e., to hold a pointer and a fixed-point number. The ‘‘SET(P)” clause causes the pointer P to point to the beginning of this newly allocated storage area. The variable used in the SET clause need not be the same as the pointer declared with ELEMENT. Had the SET clause been “ SET(R) ’’ instead, then R would point to the newly allocated element, NEXT would have to be replaced by “ R - > N E X T ”, and ‘‘ CONTENT ” would have to be replaced by “ R - > CONTENT ”. A procedure to erase a list of the kind created by ADDNUM would be ERASE: PROCEDURE(L);

1 ELEMENT

DECLARE L POINTER,

2 NEXT

POINTER,

2

DO WHILE L, = NULL;

M = NEXT; FREE ELEMENT; L=M;

END ERASE;

BASED(L),

CONTENT FIXED, M POINTER;

84

PAUL W. ABRAHAMS

In this example,

and ELEMENT are implicitly qualified by L. The ESD statement ends both the DO and the procedure. The symbol means SOT. The FREE statement has the effect of returning to the system the st’orage allocated for the element pointed to by the current value of L. I t is fairly clear how a tuo-way list could be created instead of a oneway list by using a different structure definition for ELEMENT. It is not quite so clear how a multilevel list or a list with nonhomogeneous elements could be created. I n order t o create such lists, we need to introduce yet another possible attribute of a variable, namely, CELL. CELL is used to specify storage equivalence between different data, and resenibles the EQCIYALENCE statement of FORTRAN. Consider the declaration: DECLARE 1 ELEMENT BASED(P), 2 NEXT POINTER, SEXT

2

COSTEBT CELL,

2

TYPE

“,”

3

S FIXED,

3

Y FLOAT,

3

Z POINTER,

FIXED(^);

By declaring COXTEXT to have the attribute CELL, we specify storage equivalence aniong its substructures, namely, x, Y , and z. I n other words, the storage layout for an ELEMENT will permit the CONTENT part to be either a variable as described by x , a variable as described by Y, or a variable as described by Z. Any particular ELEMENT will have as its COXTEST just one of these alternatives. In this particular list organization TYPE is intended to be a one-digit code indicating which of the alternatives is the one actually present. Thus we can determine the type of a particular list element by testing the integer TYPE. Since CONTENT can be a pointer, we can have a list as an element of a list (the pointer merel~.need point t o another ELESIEST); since CONTENT can also be a number. we can terminate a list at any level with a number. Front these examples it can be seen that PL;l does not impose any particular met hod of list organization upon the programmer; in this sense it resembles L6. I t does, of course, require the programmer to sl)ecify how his lists are to be arranged, and this task is accomplished through the \ arious declarations shown here. 6. SLIP

SLIP (for Syinmctric LIst Processor) is a list processing language developed by \Yeizenbaum in 1963 [ 4 0 ] ; an excellent updated description lias been publishcd by Smith [37]. SLIPis a descendant of a t least four. earlier languages : Gelernter’s FLPL 1131, TPL-V [28], Perlis’s threaded list syst#em L.301, and IVeizenbaum’s earlier KLS system. S L w actually consists of a collection of subroutines to be used by a

85

SYMBOL MANIPULATION LANGUAGES

FORTRAN program; most of these subroutines, being themselves written in FORTRAN, are machine-independent. Thus SLIPprovides to its users several advantages a t the outset. Since SLIPis embedded in FORTRAN, the SLIPuser has the full facilities of FORTRAN, and in particular its numerical and array-handling facilities, available t o him. If he already knows FORTRAN, then the burden of learning SLP is eased. SLIP programs are essentially as transferable from one machine to another as are FORTRAN programs; and from the implementer’s viewpoint, SLIPis quite easy to install on a new machine with a FORTRAN compiler. FORTRAN, by the way, is not the only host language that has been used for SLIP;a MAD version also exists at Yale University. 6.1 SLIP Data

SLIPdata, which are in addition to the usual FORTRAN data, consist of two-way lists. SLIPlists can be traversed either forward (i.e., left to right) or backward (i.e., right to left); hence, the name symmetric lists. The general form of a SLIP cell is shown in Fig. 9. The cell actually

..., 1

Datum

Non-List Datum ID.0

List Doturn. ID= I

I List

ICount

Header

ID.2

I Reoder I D =3

FIG.9. The SLIPcell.

consists of two words in most computers. The first word always contains three fields, called ID, LNKL (link left), and LNKR (link right). If the ID is not 0, the second word is also subdivided in the same way. The name of a list is a word whose ID is zero and whose LNKL and LNKR fields both contain pointers to, i.e., the address of, the list. A FORTRAN variable whose value is a list will normally contain the name of that list. The ID field of the first word of a cell determines how the cell is to be interpreted. A cell representing a list item will have an ID of 1 if the item is a sublist and an ID of 0 otherwise. For sublists, the second word contains the name of the sublist. @verylist has a header that serves as a starting point for the list and also as a way of referring to it; the ID of a header is 2. The ID field of the second word of a header can be used by the user for any purpose; the LNKL field of that word contains a pointer to a description list (of Section 6.2.5) if one is desired, and the

86

PAUL W. ABRAHAMS

field contains a reference count, discussed below. Readers, which are used for traversing lists, have an ID of 3. An example of a SLIPmultilevel list is given in Fig. 10. For each list, the header indicates the first and last cells of the list. The LNKL field o f a list cell points t o the cell to the left of the given one; the LNKR field of a cell points to the cell t o the right of the given one. The header is the left neighbor of the leftmost cell and the right neighbor of the rightmost LNKR

I

FIG.10. SLIPrepresentation of

(A B

(c (D

E ) ) F)

with reader at

D.

cell; for an empty list, the header is its own left and right neighbor, and LNKL and LWKR of the first header word both point back to the header itself. Unlike the languages discussed so far, SLIPdoes not treat segments of lists as lists. In other words. CDH. of a SLIPlist is not a SLIPlist; one would need to copy i t in order to make it into a SLIPlist. This situation is a necessary consequence of SLIP’Stwo-way linkages; if two lists were to share the same CDR, then the left neighbor of the CUR could not be uniquely defined. The main consequence of this restriction is that part of one list cannot appear as a sublist of another list. Readers are a device for traversing lists; their use is discussed in Section 6.2.4. From the storage standpoint, a reader is a list of cells that indicates a particular item embedded within a list (not necessarily on the top level) and the path that leads from the list header to this item. Figure 10 includes a reader of the list shown there. The first cell of the

SYMBOL MANIPULATION LANGUAGES

87

reader points to the item. The successive cells of the reader point to the successive higher level lists that contain the item. A reader cell contains a pointer to a list item in LNKL of its first word and a pointer to the head of the corresponding list in LNKL of its second word; LNKR of the first word contains a pointer to the next higher cell of the reader (0 for the top one) and LNKR of the second word contains the level number (0 for the outermost list, increased by 1 for each level of nesting). It can be seen, then, that if a reader points to an item embedded in a list, then we can trace our way back to the outermost list and can also tell how deep we are within that list. One of the notable and original contributions of SLIPlies in its approach to storage management and recovery. SLIP divides the responsibility for erasure between the user and the system. In general, a list can be erased if and only if there are no references to it either as the value of a variable that will be used later on or as an element of a higher level list. SLIPgives the user responsibility for external references, i.e., those variables, and takes upon itself the that occur as values of FORTRAN responsibility for internal references, i.e., those that occur as parts of other (not erased) lists. Storage management is implemented through the use of a reference count contained in the header of every list. The reference count for a list is either the number of internal references to it or the number of internal references t o it plus one, depending on how the user created it. Whenever a list CL is inserted as a sublist of a list /3, then the reference count of cc is increased by one. Whenever a list is explicitly released by the user, its reference count is decreased by one. When the reference count of a list becomes zero, that list can be erased. A list is erased by appending it to the List of Available Space (LAVS) from which new cells are obtained. References to sublists of an erased list are dealt with by the procedure that makes cells available from LAVS. When a cell is taken from LAVS, a check is made to see if the ID of the cell is 1. If the ID is not 1, the cell is simply made available. If the ID is 1, the second word of the cell must contain the name of a list. The reference count of this list is then decreased by one. If as a result the reference count becomes zero, then this list is in turn added to LAVS. When a new list is created or cells are added to an existing list, the cells required are taken from LAVS according to the procedure just described. The user may, at his option, set the initial reference count of a newly created list to one or zero. If he sets the initial reference count to one, then the list will never be returned to LAVS until he releases it explicitly (by decreasing its reference count by one). If he sets the initial reference count to zero, then the list will be erased as soon as the last internal reference to it is erased.

88

PAUL W. ABRAHAMS

This scheme has several pleasant consequences. The user has responsibility for storage control for those references to lists that are most visible to him, namely, the external ones, while being freed of the responsibility for those reference5 that are much less visible to him, namely, the internal ones. Since appending a list to LAVS at the time of erasure requires examining only the two ends of the list, the time required to erase a list is independent of its length. Also, the bookkeeping for erasing sublists is postponed until the last possible moment. 6.2 SLIP Programs

The SLIPsystem exists in the form of a large number of subroutines. We shall not attempt to describe them all here, but rather we shall discuss t>heirmajor groupings and give some illustrations of the members of each group. The grouping used here follows Smith. 6.2.1 Storage Allocation

The two routines normally used by the programmer are INITAS (space, n ) , which converts the array space of dimension n into the the initial LAvs, and IRALSTQ), which decreases the reference count of the list 1 by one. The routine NUCELL. which obtains a new cell from LAVS, is normally called only by the SLIP subroutines themselves; its main relevance for the user is that if no space is available, it will issue an error complaint and terminate the entire program. 6.2.2 Manipulating Data on Lists

These routines add, delete, change, and reference data on lists. The routine LIST(Z) creates an empty list; if its argument is the literal " 9 ", the reference count is initially zero. Otherwise the reference count is initially one, and the name of the created list is placed in 1. In either case, the value of LIST is the name of the created list. NEwToP(d,z) inserts the datum d as the first element of I , and NEWBOT(d,z) inserts d as the last element of 1. NxTLFT(d,c) inserts the datum d to the left of the cell c. and INLSTL(Z,C) inserts the list 2 to the left of the cell c; NXTRGT and INLSTR, which ins& on the right, are analogous. Lsscpy(Z) creates a new copy of the list 1, and has as its value the name of this new copy. The value of TOP(1) is the datum stored as the first item in the list I: the value of BOT(Z) is the datum stored as the last item of 1. DELETE(C) deletes the item c from the list containing it. Note that since a SLIPcell can be a member of only one list, its left and right neighbors are uniquely defined even if the header of the list is not given.

SYMBOL MANIPULATION LANGUAGES

89

As an example, the following program will create a list whose elements consist of the integers from 1 to 10: CALL LIST(ILIST)

DO

1

The value of

ILIST

1 K = 1,10

CALL

NEWBOT(I,ILIST)

will be the name of this list.

6.2.3 Sequencing through Lists

In order to simplify sequential processing of the items on a list, SLIP provides a collection of sequencing functions. The function SEQRDR(~) has as its value a newly created sequencer for the list 1; the sequencer is initially a pointer to the header of 1. The function SEQLL(S,f) advances the sequencers to the next cell to the left of the current one, i.e., causes the sequencer to point to that cell. Its value is the datum stored in the new cell, and as a side effect it sets f to 1 if the new cell is a header, 0 if the new cell is a list name (i.e., has an ID of l), and - 1 if the new cell is a nonlist datum. The analogous function for sequencing to the right is SEQLR. As an example, assume that the list LL contains a mixture of floating point numbers and sublists. The following program will set SUM to the sum of the floating point numbers:

+

SL = SEQRDR(LL)

SUM = 0

1 x = SEQLL(SL,F) IF (F) 2,1,3

2

SUM=SUM+X

GO TO 1

3 6.2.4

CONTINUE

Tracing through lists Using Readers

By means of readers, the user can operate on or examine the elements of a list (and also those of its sublists) in a more elaborate way than he can using a simple sequencer. We define the progeny of a list to consist of its elements plus the progeny of its sublists. A reader of a list 1 then consists of a pointer to a,one of the progeny of I, together with the path from a t o the header of 1. The internal representation of a reader was discussed in Section 6.1.A reader of A list 1 is created by calling LRDROV(~);

90

PAUL W. ABRAHAMS

the value of this function is the name of the ncwly created reader, which points t o the header of 1. There are 12 functions for advancing readers. X rcladcr may advance to the left or the right; it may advance structiirally (descending into sublists) or linearly (not descending into suhlists): and it may advance to the next element, the next name, or the next word (IShere an elcnierit has an ID of 0. a name has an ID of 1, and a word hasan ha of either Oor 1). Thus AD\’S\YR(T, f ), for instance, will Xl)\‘aiire Structurally IVord Right. Here r is the name of the reader,and f i s a tiag. If the present ccll contains the name of a sublist, then the advance 1% ill take the reader to the rightmost cell of that sublist; otherwise the advance will take the reader to the cell directly to the right of the prrsent one. In this case, since the advance is to the next word, any itrm other than a header will be acceptable: had the advance been hy rlenwnt. then any name found would be skipped (though descent into the siihlist designated by the name would still take place). The flag f is niadr zero if a cell of the given type is found, and nonzero if the search for such a cell encounters the header of 1. As an rsample, assume that the terminal nodrs of the list LT, (i.e., those menhers of the progeny of LL that are not themselves sublists) are all floating-point numbers. Then the following program will compute the sum of the terminal nodes of LL: K = LRDROV(LL)

1 x = ADVSER(K.F) IF (F.NE.0) GO TO

2

SVC’RI = SUM i- x GO TO 1

2

COXTINUE

6.2.5 Description Lists

A description list is a sequence of linked cells that can be attached t o the header of a list and contains information describing that list. The description list is composed of pairs of cells; the first cell of a pair contains an ccttribute and the second contains a i:nlua. Description lists in SLIPare thus like property 1ist.s in LISP. except that property lists are attached to elementary items (i.e., identifiers) while description lists are attached to lists. Attribute-value pairs are added to a description list by means of the function XEWVAL: X E \ V V A L ( d . r d . l ) searches the description list of the list I for the attribute at. If d is found, then the corresponding value is

SYMBOL MANIPULATION LANGUAGES

91

replaced by Val, and the value of NEWVAL is the replaced value. If at is not found, then the (at, vaE) pair is added to the bottom of the description list and the value of NEWVAL is zero. Pairs are removed from a description list by NoATvL(at,l), which removes at and its associated value from the description list of 1. The function ITSVAL(Ut,l) has as its value the value paired with at on the description list of 1. Other functions exist for copying, removing, and performing other manipulations on description lists.

6.2.6 Recursion Since the FORTRAN language as usually defined and implemented does not allow recursion, SLIP has provided special functions to make recursion possible. A recursive function is normally written as a block of code beginning with a statement label rather than as a FORTRAN funcASSIGN statement and a call to tion. The block is entered by a FORTRAN the function VISIT; it is left by a call to the function TERM. For example, executing the statements ASSIGN

60 TO

LOC

x = VISIT(LOC) will cause the recursive function defined by the block of code beginning at statement 60 to be entered; the value of that function will be returned as the value of VISIT and thus will become the value of the variable X. Execution of the block will be terminated by CALL TERM(Z)

which will have the dual effect of returning control to the place from which the corresponding VISIT was called, and setting the value of VISIT to z. It should be noted that the call to VISIT actually causes a transfer of control to LOC, and that control does not return to VISIT until TERM is called. In order to save and restore arguments of recursive functions, SLIP uses an array of 100 public lists, placed in COMMON storage and designated w ( l ) ,. . . , w(100). Upon entrance to a recursive function, these lists are pushed down; upon exit, they are popped up. Pushdown is done by the function PARMTN(P~, p z , . . . ,p,) which expects a variable number of arguments and saves these arguments on the first n public lists. The pushdown for a particular argument is done by placing the argument into the second word of a c,ell obtained from LAVS and adding that cell to the head of the corresponding public list. Popping up is done by REsToR(n),which removes the first cell from each of the public lists, ~ ( 1through ) w(n).

92

PAUL W. ABRAHAMS

In order to simplify saving and restoring of arguments, VISIT and are both permitted to accept a second argument. This argument will be evaluated during the function call, but the value obtained will be discarded. If PARMTN is called as the second argument of VISIT, then statement that enters a recursive function can also save the FORTRAN the arguments of that function; similarly, if RESTOR is called as the second argument of TERM, then the FORTRAN statement that leaves a recursive function can also restore the arguments of that function. I n that do not permit a variable number of thosr. versions of FORTRAN arguments in subroutine calls, the treatment of VISIT, TERM, and PARXTS will be slightly different.

TERN

6.2.7 Input-Output Weizenbaum’s original article on SLIPgave no information on inputoutput, though Weizenbaum’s system does in fact contain functions for that purpose. Smith describes two functions RDLSTA and PRLSTS for reading and printing lists. RDLSTA reads lists in essentially the same format as LISP, except that the dot notation is not meaningful and numbers are treated as character strings. PRLSTS prints lists in quite a different format; no parentheses are used, one item appears on each line, and the beginning and end of a sublist is indicated by indentation and a special message. Thus the list ( A B (c D ) E ) would print as BEGIN LIST A

B BEGIN SUBLIST C

u END SUBLIST E

END LIST

7. SNOBOL

SSOBOL~ is a programming language designed primarily for the manipulation of strings. Historically, SNOBOL was inspired primarily by COhlIT; the first version of SNOBOL was described by Farber et al. in 1964 [ll].There have been several subsequent modifications, of which the best known has been S N O B O L [12], ~ completed in 1966. A more 3

The meaning of the acronym “SSOBOL”has never been explained publicly

SYMBOL MANIPULATION LANGUAGES

93

recent version, S N O B O L [14], ~ is presently being implemented and is gradually replacing SNOBOL~. The description given here is based on S N O B O L ~but , includes a section on the changes introduced by SNOBOL4. It is interesting to observe that although SNOBOL is a string processing language rather than a list processing language, many of its applications are the same as those of list processing languages. For instance, Farber et al. [I21 give three examples of the use of SNOBOL.Of these, two, namely, the Wang algorithm for the propositional calculus and a program for the differentiation of algebraic expressions, are classic examples used to illustrate LISP. (The third example is an editor that does right justification of printed lines.) The structure of a SNOBOLQ program is quite different from that of a program in any of the languages we have discussed so far. A S N O B O L ~ program consists of a sequence of statements, of which there is only one type. Variations are achieved through omission of components of the statement. The statements are executed sequentially until the sequence is altered by a go-to. In general, execution of a statement causes all or a portion of a string to be replaced by a different string. However, many different kinds of side effects can also occur as a result of the execution. The data of S N O B Oare L ~ all strings; a constant string is represented by enclosing it in quotes. Numbers, too, are treated as strings; they also must be enclosed in quotes, though arithmetic is possible. The variables of SNOBOL~ are called names, and they all have strings as values. One of the simplest subcases of a SNOBOL3 rule is a pure assignment such as CAT = “ SIAMESE

”

which causes the value of the narhe CAT to be the string SIAMESE. Concatenation of strings is represented by writing them successively; thus, the two statements PREP = ‘‘ O F ” , SHIP = “ MAN ” PREP

“

WAR

”

will cause the value of SHIP to be the string “MAN OF WAR ”. Note that in this case we have concatenated a constant. a name, and another constant. The statement STRING =

will cause the name STRING to assume the null string as its value. Quotes cannot be written as part of a constant. However, the name QUOTE has as its initial value a single quote. Thus strings containing quotes can be created and manipulated.

94

PAUL W. ABRAHAMS

The most general form of assignment causes just a portion of a string to be replaced. Thus, if the value of STRING is “ CANDY IS DANDY ” and we write STRING “ANDT

then the new value of

STRING

”

= “ HOCOLATE

”

will be

‘‘ CHOCOLATE IS

DANDY ”

The first item on the left side of the assignment (ignoring labels for the moment) is the string reference, which specifies the string to be modified; the remaining items (in this case only one) specify the portion of the string reference that is to be replaced and are called the pattern. If there is no pattern, as in the simple assignment given earlier, then the entire string as specified in the string reference is replaced. Note that only the first instance of the pattern within the string reference is affected. The pattern may or may not be found within the string reference. If it is found, the statement is said to succeed; if it is not found the statement is said to fail. X statement containing all the possible components is L1 STRING S l “ O F ”

S 2 = S2

“FOR”

S3

/S(Ll)F(L5)

Here ~1 is the statement label, which must begin in column 1; if the statement is unlabeled, then column 1 will be blank. The components of the statement are separated by blanks. A period in column 1 indicates a continuation card. STRING is the string reference, sl i‘ OF ” s2 is the pattern, s2 “.FOR” s3 is the replacement, and the material following the slash is the go-to. Execution of this statement proceeds as follows: sl and s2 are both names whose values are specific strings. The pattern being searched for consists of sl (more precisely, the value of s l ) concatenated with “OF” concatenated with s2. If this pattern is found within STRING, then the first occurrence of i t is replaced by s2 concatenated with “ F O R ” concatenated with s3. Assuming the pattern is found, control returns to statement ~ 1 as, specified by the s (success) alternative of the go-to; if the pattern is not found, control goes to statement ~5 as specified by the F (failure) alternative of the go-to. If a statement has no s alternative specified in the go-to, then control will pass to the next statement if execution succeeds; lack of an F alternative is treated analogously. Because the statement in this example loops back t o itself if the pattern is found, the effect of executing it will be to change every occurrence of . the pattern to the replacement and then to transfer control t o ~ 5 Note that in this case both the pattern and the replacement contain names. If a statement does not contain an “=”, then the statement will still

91

SYMBOL MANIPULATION LANGUAGES

succeed or fail according as the pattern is or is not found within the string reference, but no replacement will be done. Statements of this sort are useful for testing. Thus, STRING

((

W

)’/S(L4)

will transfer control to statement ~4 if STRING contains a (‘w )’and will pass control t o the next statement otherwise. though The usual arithmetic operators are available in SNOBOL~, only integer arithmetic is permitted. Numeric constants must be quoted (which is a nuisance), operators must be separated from their operands by blanks, and expressions with more than one operator must be fully parenthesized (also a nuisance). For SNOBOL~, an integer is defined t o be a character string that represents an integer. Parenthesized arithmetic expressions may appear as part of a pattern. Thus, C=A+(B*‘(4”)

multiplies B by 4, adds A, and leaves the result in “21 then

c.

If the value of

N

is

)),

STRING “ W ” ( N - “ 8 ” ) =

(‘Y12”

will replace the first occurrence of ‘(w13 ” in STRING by ‘(~ 1 ”.2 Strings may be searched for patterns that are not entirely known in advance by means of string variables. An arbitrary string variable is designated by surrounding a name by asterisks. It will match any string whatsoever (including the null string). Thus, if we write STRING = “ PETER PIPER PICKED A PECK OF PICKLED PEPPERS ” STRING

‘(PIPER ”

*ACTION* “A PECK )’

then *ACTION* will match “ PICKED ”. Moreover, the name ACTION will be assigned PICKED ” as its value. A name used this way can appear later in the statement, either as part of the pattern or as part of the replacement or both. Thus, if we write ‘I

STRING^ = “ A

ROSE IS A ROSE IS A ROSE

)’

STRING2 = ‘(-A HORSE IS A HOUSE IS A HOSS

STRING^

“A ”

*NOUN*

(‘IS

A

)’NOUN “IS

A

))

’) NOUN

- “ A ” NOUN “ I S SURELY A)’ NOUN STRING2

‘(A ’’ *NOUN* (‘IS - “ A ” NOUN

A ” NOUN

“ IS

A ’)NOUN

‘(IS SURELY A ” NOUN

then replacement will occur for STRING^ but not for STRING2. The value

96

PAUL W. ABRAHAMS

of NOZTN,however, will be “ R O S E ” rather than “HORSE” as a consequence of the failure of the fourth statement. A pattern may contain fixed-length string variables and balanced string variables. A fixed-length string variable is written by following the name by a slash and a string specifying a length in characters. I n the statement STRIXG

‘(A ”

”*

*PART/(‘ 7

the seven characters of STRING following the first “A” will be named PART. The ‘‘ 7 ” could be replaced by any string expression evaluating out to an integer. A balanced string variable is indicated by surrounding the name by parentheses; the variable will only match a string that is balanced in the usual algebraic sense. Thus, if we write EXPR = ( ( A

(R**C)* C

”

c”

EXPR

‘(A ”

EXPR

‘(A ” *STRl* ‘(C ”

*(sTR)*

“

then the value of STR will be “+(B**c)* ”, while the value of STRI will be ‘ ‘ + ( B * * ” . Both system-defined and user-defined functions are available. An example of a system-defined function is SIZE(S), whose value is the number of characters in the string s. 4 function may, instead of rcturning a value, signal failure; the failure signal will cause the statement containing the function call to fail. This feature is useful for testing. For example, the function EQVALS (x,y) returns the null string if x and y are identical character strings. and signals failure otherwise; thus, N = EQUALS(SX, SY) N J-

“1 ”

will increment N by 1 if and only if sx and SY are the same character string. In interpreting an expression containing both concatenation and arithmetic operations, the concatenations are done first. I n this example, if sx and SY are identical, the null string will be concatenated with N, which leaves N unaffected; then 1 will be added t o N . If sx and SY are not identical, EQUALS will signal failure and no replacement will be done. Various arithmetic tests use the same mechanisms. Thus .LT(T, y) returns the null string if x < y and signals failure otherwise. The arithmetic test for equality is not quite the same as EQUALS, since .EQ(“ 0069 ”, “ 69 ”) will succeed while EQCALS (“ 0060 ”, “ 69 ”) will fail. Often it is necessary to match a pattern a t the beginning of a string rather than at some arbitrary place in the middle. Executing the function call MODE(“ANCHOR”)

SYMBOL MANIPULATION LANGUAGES

97

will cause all subsequent pattern matches to start a t the beginning of the string being matched. Executing MODE(“ UNANCHOR

”)

will cause the usual mode of pattern matching to be resumed. The value of both of these function calls is the null string. A user may define a function by a call to DEFINE. The function definition consists of a block of code. Thus, DEFINE(“REVERSE(X) ” , “ R E V ” )

defines a function named REVERSE; its formal parameter is x, and the defining code block begins at the statement labeled REV. The value returned by REVERSE will be the character string x in reverse order. The defining block might be REV

x * c u / l *=

/F(RETURN)

REVERSE = CHAR REVERSE /(REV)

Here the second statement transfers control unconditionally to REV. The special label RETURN is used to indicate return from the function. When the function is entered, the value of the name REVERSE will be the null string. The value returned by the function will be the value of the name REVERSE at the time of the return transfer. Thus

z = REVERSE(“ABCDE

”)

sets the value of z to “EDCBA”. The second argument of DEFINE may be omitted, in which case it is taken to be the same as the name of the function. The character “ $ ” is used to indicate indirect references. Thus if the value of the name AUTHOR is “ MELVILLE ” and the value of the name MELVILLE is “ MOBY DICK ”, then the value of $AUTHOR will be “ MOBY DICK ”. More complicated cases are possible; thus, the statements WORD

*CH/“ 1 ”*

$(“LIST”

CH) = WORD

“ ”

$(“LIST” CH)

willgadd WORD to one of LISTA, LISTB, . . . , LISTZ according to what the first character of WORD is. Indirect references can be used in the go-to as well as in the pattern or replacement. Input and output are accomplished through the use of the special Every time that a value is assigned to names SYSPIT and SYSPOT.~ 4 According to the usage at Bell Laboratories in SNOBOL3 days, SYSPIT stands for System Peripheral Input Tape and SYSPOT stands for System Peripheral Output Tape.

98

PAUL W. ABRAHAMS

SYSI’OT, the ralrie so assigned is printed as a new line in the standard output file. Every tiiiw that SYSPIT is evaluated, a new line is read from thc standard inpiit filv and that line is tht, required value. Thus, SPSPOT -= SYSPIT

will cause a line to be copied from the input file to the output file. The iml’lt.iii~,.ntationof S X O B Oinvolves L~ both a compiler and an intcrprctc~r.Thc compiler translates the original source program into an internal language suitable for the interpreter; the interpreter operates on this internal rc3presentation at run time. Storage recovery is complet (4 y a tit oma t ic. 7.1 SNOBOL4

SSOBOL is ~n significant improvement over SNOBOL~. Xost of the changes have Itcc.n in the direction of gencrslizing existing SNOBOL3 conecpts: the remaining changes arc’ primarily concerned with eliminating nuisances. One niiisance that has been eliminated is the requirement that integers hv enclosed in quotes. Also. sequences of arithmetic operators nck.cl not I)c fully parcnthesized. so S S O R O will L ~ interpret correctly the s t at ( ~ I l l ( ~t t 1 C‘=h-!-B*D

In S s o ~ o r A more . than on(’ statement may be written on a line; suci w statcmcnts are separated Oy semicolons. There are also a number i i m r syntactic changes. 1 hc. concept of a pattern is grratly generalized in S x o n o ~over l what . a pattern is a type of datum, and a name it is i n S S O U O LIn~ SSOBOI,~. can dcsignatc a pattern. Pattrrns may bc composed from simpler ones in a riumhcr of ways. Thus. ()PER = “ _. ” I “ - I (‘ * ” 1 “ 1 ” r /

7’

crcatt.s H pattern (not a string) named OPER: this pattern w i l l he matched by any of t hc arithmetic olwrators. Patterns may be concatenated, so that UOI’ER -= ‘’

. ’*

OPER

n-ould associate with DOPER a pattern con ting of R period followed by an withmc+ic olwrator. The string rarial)lcs of Sso~or,:2arc rtJplaced hy patttm~s.Thus A R B rc1)laccs an arl)itrary string variablc, H A L re1)Iaew a halanccd string varialtlc. and L E S ( I Z )replaces a string v;tri,zble of lcngtli H . For instance, “.\” ARB

‘‘ B ”

99

SYMBOL MANIPULATlON LANGUAGES

is a pattern that will match any string that starts with an with a (‘B ”. Also,

“A”

and ends

‘(SIN ” BAL will match any string that consists of ‘‘ SIN ” followed by a parenthesisbalanced string of characters, and “A” LEN(4)

’(BC

”

will match a string consisting of (‘A” followed by four arbitrary characters followed by ‘(BC ”. Since in SNOBOLQ the matching of a string variable can be used to L~ a corresponding facility. assign a value to a name, S N O B O requires Two operators are used for this purpose: “ . ” and ‘($ ”. If we write STRING^ =

((

STRING^

then

THREE BLIND MICE (I”

ARB

. ADJ ‘(

”

”

will be assigned the value ‘(BLIND’’ since ARB will match and the period will cause the value of ARB to be assigned to ADJ. Any component of a pattern may be named by appending a value assignment to it in this way. Since a component may consist of several subcomponents enclosed in parentheses, groups of components may also be named. If value assignment is done by ‘ I . ”, then the assignment will be made after the entire pattern has been matched and not before. Consequently the “ . ” will not work for back referencing, i.e., for matching a component named earlier in a pattern. Assignment made by $ ”, on the other hand, takes place immediately, whether or not any further matching is successful. Thus, ((

ADJ

BLIND

”

‘(

STRING = STRING

((

x + ALPHA = ALPHA”

‘(X + ” ARB

$ VAR =” VAR ((

will cause VAR t o match ((ALPHA” and the entire pattern to match STRING. Had STRING been “X+ALPHA=BETA”, VAR would still have received the value ALPHA even though the entire pattern match would have failed. A ” used in place of (‘$ ” would cause the pattern match to fail and would leave the previous value of ARB undisturbed. Ordinarily, all Ihe components of a pattern are evaluated before any pattern matching takes place. However, a ‘(* ” may be used preceding a pattern component to indicate that the component is not to be evaluated until it is needed in a match. This means of pattern evaluation I‘.

loo

PAUL W. ABRAHAMS

is known as deferred pattern de$nitim, and it permits the definition in a simple way of recursive patterns. Thus, the pattern p = ‘‘3

”

I “A”

*p

will match any of B AB AAB

.. The ANCHOR and CNASCHOR modes of S N O B Oare L ~replaced by a more general method in S x O B O L 4 . The pattern-valued function pos(n) matches a null string n characters from the beginning of the string being matched. In particular, pos(0) a t the beginning of a pattern will force the rest of that pattern to be matched against the beginning of the target string. -4similar function R P O S ( ~ )matches a null string n characters from the end of the target string. Among the other useful patternl-alued functions are A R B K O ( ~ ) which , matches an arbitrary number (including zero) occurrences of the pattern p; ANY(S), which matches any character in the string s; and BREAK(S), which will match a nonnull sequence of characters containing no character in s but followed by a character in s. SSOBOL.4 includes arrays as a type of datum. An array is created by calling the function ARRAY(^, v), where d specifies the dimensionality of the array and v, which may be omitted, specifies the initial value to be assigned to the array elements. Thus, BOARD = ARRAY(“ 8,!3”,

“x”)

causes the value of BOARD t o be an 8 by 8 array, each element of which is initiallj- the string ‘‘ x ”. An array element is referenced by enclosing the subscripts in angle brackets; e.g., BOARD

< 3,5 >

I n order t o permit more flexible calling sequences, S N O B O L ~includes a name operator. If a name (which in general is anything that denotes an object) is prefixed by the operator “ . ”, then the resulting object indicates the name of the object so prefixed rather than the object itself. With this mechanism, one can for instance write functions that pass results back through their arguments (a frequently used device in FOKTRA~V programming). -4.11 SSOSOLprograms, being character strings, are themselves in the form of SXOBOL data. In s S O S O L 4 , the user can take advantage of this fact, much as he can in LISP, by creating a program and then executing

SYMBOL MANIPULATION LANGUAGES

101

it. The mechanism for accomplishing this is the function CONVERT (p,“ CODE ”) where p is a character string representing a sequence of SNOBOL4 statements. The statements are separated by semicolons within the character string. Evaluation of CONVERT with “ CODE ” as its second argument causes p to be compiled, and returns as value a data object of type CODE that represents the compiled code. This code can then be executed either by transferring to it directly using a special kind of go-to or by transferring to a label within it in the ordinary way. SNOBOL~ uses data types, but not in the way that the other languages discussed here use them. The user can ascertain the data type of any object, but he need not (and indeed cannot) declare that a given name will always have as its value an object of a given type.5 The principal use of the data-type predicates is in writing functions whose behavior depends on the type of their arguments. There is also a facility for creating new data types and then using them; these new data types resemble the ntuples of LISP 2 and the structures of PL/I (sans level numbers). Figure 11 gives a S N O B O L program ~ analogous to the LISP function LCS given previously. Since the operations being performed are essentially linear, this program is somewhat simpler than the LISP program. The program defines the function LCS for computing the longest common substring of two strings, and then applies LCS to two strings on successive cards in the input data stream. The result is then printed out. The LISP functions COMSEG and COMSEGL are combined into a single function COMSEGL(X,Y) that returns a length as value and sets ~3 to the initial common segment of x and y. Note that tests are used in several of the replacements. If such‘a test fails, the corresponding replacement is not done; if such a test succeeds, it generates a null string that can be concatenated with the replaaement without changing it. The system function TRIM removes trailing blanks from its argument. 8. Other Symbol Manipulation Languages

The previous sections have discussed those symbol manipulation languages that in the author’s opinion are the most significant ones at this time. In this section we shall examine briefly a number of other languages, though even the list given here is far from exhaustive and reflects to a great extent the author’s own biases. 5 Compare this situation with LISP2 and PL/I, where all variable names have fixed types associated with them either by explicit or implicit declaration. The lack of declarations adversely affects the efficiency of S N O B O L ~ exactly in the way that it adversely affects the efficiency of LISP 1.5 versus that of LISP2.

I02

PAUL W. ABRAHAMS DEFINE ( "LZS ( L i , L 2 ) " )

DEFIKE( ":OMXGL(X,Y)")

s- = s: =

TRIM(INPUT) TRIM(L~PET)

:( E N D )

CLT?L;T = L:s(cL,s2)

* LX

J O i W T E S T'?i LONGZST 2OMMON SEGMENT OF TWO STRINGS L1

* AXD i2 Ir= 0

A1

x= -_

L1

Y

L :

=

_ -u

,

-(

.: , 1

-_

:F ( RETURN)

DIFFm(Y,"") G T ( S I Z E ( Y ) , K )

A2

N

=

CXEGL(X,Y)

=

:F(A)

N

K = GT(N,K)

L:s

:F(A3)

L?

4

Y POS(O) LEN(^) =

:(A2)

A:

X POS(0) LEN(1)

:( A l )

* ,'OMSEGL(X,Y) *

:OMMOW

=

RETURNS WE LENGTH OF THE LONGEST I N I T I A L

SWZGMENT OF X AND Y AND AS A S I D E E F F E C T S E T S

* L3 TO THAT ZOMMON SUWEGMENT COMSECJL = O

x

a:

LZN(:OMSEGL)

Y LEN(XEEGL) 3GESEGL

=

. xi

:F(RZTURN)

. Y:

:F ( RETURN)

IDENT(X1,Yl)

ZOMSEGL

+

1

:F(RETURN)

: (Bl)

i; = x1

FIG.11. Defiiiitiori of

I,CS

in S N O B O L ~ .

8.1 IPL-V

'I'hc most recent version of IPL" is IPL-V [ZS]. Historically, IPL is of great importance. having pionetred the use of list processing techniques. l'hv origitial IDI, was developed by KeaelI et al. in 1957 [ 271 for use in connwtion with their explorations of problem-solving. It was iniplementcd on the J O H S S M ' computer at, the Rand Corporation and 6

For

I*

Information Procehsng Laripuape.'

SYMBOL MANIPULATION LANGUAGES

I03

also on the IBM 650, and to this day much of the format of the language results from the characteristics of the IBM 650 and its assembly program. Although IPL still has its adherents, it appears to have been superseded by the newer languages. Like L6 programs, IPL programs are heavily oriented toward machine-language programming. An IPL program is divided into routines, each of which consists of a set of instructions. The routines can themselves be expressed as lists of instructions, and the instructions in turn can be expressed as data. Thus, IPL programs are self-descriptive in the same way that LISPand SNOBOL programs are. Symbols are used to designate storage cells. A storage cell is capable of holding a datum such as a list name, a number, or an alphanumeric string; a pushdown stack is implicitly associated with every storage cell. The instructions make implicit use of two special storage cells: HO, the communication cell, and H5, the test cell. The HO cell is used to pass inputs t o routines and to return results from routines7; H5 is used to indicate the results of tests. The contents of a storage cell are considered to be the top item on the stack rather than the whole stack. The IPL storage cells resemble the public lists of SLIP;in fact, the SLIP public lists are derived from the IPL storage cells. An IPL instruction has four parts: the name, the preJixes, the symbol, and the link. The name is simply a label for the instruction, though in addition (as in SNOBOL) it can be used to name a routine. Names in IPL consist of either a letter followed by up to four digits or ( ( 9 - ” followed by up to four digits, e.g., “5521 ”, ~2 ”, “ 9-10 ”.s The prefixes, called p and Q , specify the operation to be performed on the symbol and the degree of indirectness involved. The symbol represents a storage cell, whose contents may be a routine. The link, if specified, names a symbol to which control is to be transferred. Let s designate the storage cell named’by the symbol. Then the actions caused by the various values of P are Execute the routine in s. 0 1 Push down HO and copy s into HO. Copy HO into s and pop up HO. 2 3 Pop u p s . Push down s, leaving the previous contents of s in S. 4 5 Copy s into HO. 6 Copy HO into s. Branch to s if H5 is negative. 7 ((

7 Arguments are passed t o routines by stacking them in HO, so that IPL routines do not have formal parameters in the usual sense. 8 These forms are qulte unmnemonic, though experienced IPL programmers seem to be able t o remember them.

I 04

PAUL W. ABRAHAMS

A copy operation causes neither pushing down nor popping up; since the contents of a storage cell are considered to be the top item on its stack, a copy affects only that item. Externally, I P L data and I P L programs are written in the same form; items in successive lines represent successive items of a list. Sublists must be named explicitly rather than through any parenthetic notation. The internal representation of I P L data resembles that of LISP.with the symbol corresponding t o CAR and the link corresponding to CDR. The prefixes represent additional information not contained in LISPcells and arc used to indicate the type of the datum designated by the symbol. Interestingly, prefixes were used in the very earliest (and unpublished) version of LISP, but were later dropped. Prefixes have been revived in some recent LISP implementations. I P L provides t o its users a large collection of primitive routines called processes; all of these have names starting with " J ". As in L6, the user must handle most of the bookkeeping. Erasure is entirely the responsibility of the programmer; in particular, it is his responsibility to guarantee that an erased list is not part of another list. There are facilities in I P L for utilizing auxiliary storage. Lists (which, of course. may represent programs) can be transferred to and from auxiliary storage fairly easily. The programmer can arrange to have his y-ogram trapped when storage is exhausted and then transfer data and programs to auxiliary storage. The I P L implementation is based on an interpreter rather than on a compiler. Consequently. the system is generally not very efficient. 8.2 COMlT

CONITis a string processing language originally developed by Pngve [ d l ] in 1957 for use in mechanical translation. COMITwas the first major language to introduce pattern-matching statements, and its central ideas have had a strong influence in the whole field of symbol manipulation. Pattern-matching statements are now included in many different languages. several of which are discussed in this article, The primary data depository of COMITis the workspace. The contents of the workspace are a sequence of constituents, each of which is a symbol i.c.. an arbitrary sequence of characters (unlike SNOBOL, where each constituent is a single character). Piotationally, the constituents are separated by plus signs. Characters other than letters, periods, commas, and minus signs are all preceded by " * ", and spaces are replaced by minus signs. An example of a sequence of constituents in a workspace is THE T * 8 * 7 - BIEX - A R E T H E R E i . Constituents may have subscripts attached to them. A numerical sub-

SYMBOL MANIPULATION LANGUAGES

I05

script is an integer. A logical subscript is a name with up to 36 possible associated subscript values, which are also names; any subset .of the values may be present. The order of subscripts is immaterial. An example of a subscripted constituent is MAN/.365,PART-OF-SPEECH NOUN

VERB, CLASS HUMAN

Here the numerical subscript is 365 (not .365), the logical subscripts are PART-OF-SPEECH and CLASS, the values of PART-OF-SPEECH are NOUN and VERB,and the value of CLASS is HUMAN. A COMITprogram consists of a set of rules, each of which in turn consists of a set of subrules. There are two kinds of rules: grammar rules and list rules. Grammar rules are used primarily to detect and transform complex patterns of constituents in the workspace, while list rules are used to operate on a single constituent on the basis of a dictionary lookup. The first subrule of a grammar rule corresponds more or less to a SNOBOL statement. The five parts of the first grammar subrule are the rule name (corresponding to the SNOBOL label), the left half (corresponding to the SNOBOL pattern), the right half (corresponding to the SNOBOL replacement), the routing (which produces side effects not producible in the right half) and the go-to (like SNOBOL). As in SNOBOL, parts of a rule may be omitted. If a rule has more than one subrule, the second and remaining subrules contain alternate right halves, routings, and go-to’s. A grammar rule with only one subrule is executed by matching the left half against the workspace, replacing the matching sequence of constituents as specified by the right half, executing the routing, and transferring to the go-to (or t o the next rule if the match failed). If there is more than one subrule, then each subrule must have a subrule name. An area called the dispatcher will have space set aside correspondii,g to the rule name, with a logical value entered for each subrule. After the left half is matched, the subrule corresponding to the only true value (if there is only one such subrule) will be executed. If there is more than one, a pseudo-random choice is made among the true ones; if there is none, a pseudo-random choice is made among all the possible ones. This choice may, however, be made instead by the go-to of the previously executed rule. Logical subscripts may be used as rule names, and there are ways to use the values of a logical subscript of a constituent in order to select a rule and a subrule. The possible constituents of a left half are full constituents, $n constituents, indefinite constituents, and integers. A full constituent is a symbol that matches an identical symbol in the workspace. A $n constituent matches n arbitrary successive constituents. An indefinite

106

PAUL W. ABRAHAMS

constituent, indicated by " $ ", represents an arbitrarily long sequence of constituents. An integer j represents the constituent or constituents that match the j t h constituent of the left half, and is used for back referencing. Constituents of a left half may be modified by subscripts, thus specifying additional requirements for a match. A right half may contain only full constituents and integers, where the integer jrepresents the j t h constituent of the left half. Again, subscripts may be used in the right half to modify, replace. or delete existing ones and to insert new ones. An example of a pattern match and its result is old workspace:

A 1B

+ A/R + C + D f E + F + G I

U

I

left half: right half:

Y

3

4

Y

5

$+E+$~+G

A/R+

+4/Q v + 5 +T c + D + F/Q v + G + T 2

I-r

new workspace:

V

2

1

rn

-

A list rule consists of two or more list subrules, and corresponds to a dictionary and its entries. The list subrules resemble the first grammar subrule. except that each left half is a single symbol. The subrules are automatically alphabetized by their left halves to facilitate rapid search, and their number is not rest-ricted t o 36. Control can only reach a list rule from the go-to of another rule; the selection of a subrule of the list rule will ordinarily be determined by a constituent of the pattern that was matched by the previously executed rule. Since it is inconvenient to keep all the data in the workspace, COMIT provides a numbered set of temporary storage locations called shelves. The contents of the workspace may replace, be exchanged with, or be added to the contents of a shelf. This operation is performed by the routing of a rule. COMIT has been almost entirely superseded by SNOBOL, though COMIT.like IPL, still has a few adherents. It does have two minor adFirst, for linguistic processing the ability t o have vantages over SNOBOL. constituents of more than one character is often convenient. Second, the dictionary search operations of COMIThave no exact parallel in SNOBOL and therefore cannot be done quite as efficiently in SNOBOL. 8.3 EOL

EOL is a low-level language for manipulating strings of characters.

It was originally designed by Lukaszewicz in Poland and later revised and implemented by Lukaszewicz and Nievergelt [22, 231 a t the Universit,y of Illinois in 1967. Conceptually, an EOL program should be

SYMBOL MANIPULATION LANGUAGES

I07

thought of as a machine-language program running on a hypothetical computer called the EOL machine. An EOL program is built up from machine language through macro definitions and subroutine calls, so that EOL programs are quite hierarchical. The EOL computer is equipped with inputs, outputs, files, and stacks. An input is a source of characters and an output is a sink of characters. I n practice, inputs and outputs correspond to such devices as card readers, line printers, or magnetic tapes. AJile is used t o provide mass storage, and may correspond to core, drum, disk, or tape. Internal processing in the EOL computer is done mostly on the stacks, which are linear lists of constituents. Each constituent in a stack is a string of characters; a special mark preceding each constituent indicates its type: word (i.e., alphanumeric), number, or address. A one-bit register H, similar to HO in IPL, is used to hold the results of tests. An EOL program consists of a sequence of macro definitions followed by a sequence of external procedures. An external procedure may itself contain macro definitions. External procedures together with their required macro definitions may be compiled independently; macro definitions may also be compiled independently. A procedure consists of a sequence of statements, each of which may be a machine-language instruction, a macro-instruction, a procedure definition, a declaration, or a comment. A procedure is external if it is not contained within any other procedure. There are about 50 basic instructions in the EOL machine, and their format is reasonably mnemonic. The stack instructions permit, for instance: Moving a specified number of constituents from the beginning of one stack to either end of a different stack in either the same order or in reverse order. (2) Compressing several words into one word or splitting one word into several words of one character each. (3) Testing whether the initial or the final constituent of a stack is equal to a given word or number. (1)

Instructions may be made conditional on whether their operands start with characters from particular character classes. Input instructions are used for reading, and output instructions for writing; formatted output is possible. Files can be broken down into records, and records can be labeled. Although rather difficult to program in, EOL appears to be a quite flexible language. In particular, the fact that all executable statements are in the format of instructions is a significant handicap; one would very much like to have infix and prefix operators, and to be able t o

I08

PAUL W. ABRAHAMS

compose expressions from them. Also, the macro definition facility does not permit operations on the macro parameters other than direct substitution, so that there is no way to write macros that analyze their arguments. 8.4 A Few More

AMBIT (Algebraic Manipulation By Identity Transform) [a] is a language developed by Christensen at Computer Associates in 1965. The language has been applied to symbolic manipulation problems other than algebraic manipulation. Essentially, AMBIT is a blockstructured language in which the statements consist of replacement rules as in COMIT. A replacement rule has two parts: the citation, corresponding to the left half, and the replacement, corresponding to the right half. -1novel feature is the use of pointers as place markers in matching the workspace. Pointers may appear in both the citation and the replacement. and matching always begins with a pointer. This convention is used as the basis for some interesting implementation techniques [ Y l . COTVEKT[ I S ] . developed by Guzman and McIntosh at the University of Jltsxico. is an augmentation of LISP to include pattern matching facilities. Its two central functions are RESEMBLE, which matches patterns. and REPLACE. which replaces them. Matching can be carried out against segments of lists and against sublists of lists, using patterns similar to those of s S O B O L 4 ; RESEMBLE creates a dictionary associating variables with pattern components, and REPLACE uses this dictionary in the replacement. -1similar augmentation of LISP called FLIP[6] has been developed by Bobrow and Teitelman. FLIPwas intended to lead to pattcrn-matching facilities in LISP 2 , but these facilities of LISP 2 were never fully specified, much less implemented. Lombardi [213 uses list processing as the basis of his approach to incremental computation. His incrementul computer is a simuiated computer in which programs are specified with gaps, using incompletely defined functions. During the evaluation of such a function, any undefined variables or subfunctions that appear can then be provided a t the time they are needed from, say, an on-line terminal. Lombardi’s treatment of list processing is more formal than the one used in this article. YASOS-1 s 273 is a symbol manipulation language developed by Caracciolo and his associates at the University of Pisa. It is based on a particular extension of Jiarkov normal algorithms and consists of a sequence of transformation rules to be applied to an argument string according to appropriate sequencing rules.

SYMBOL MANIPULATION LANGUAGES

I 09

COGENT(Compiler GENerator and Translator) [32] is a programming system designed primarily as a compiler-compiler, i.e., a compiler that produces other compilers. However, it is also applicable to more general symbolic and linguistic applications. Its basic approach is t o describe the data t o be operated on in terms of syntax equations, and then t o specify transformations on this data in terms of these syntax equations. It thus is a pattern-matching language, where the constituents of the match are syntax terms and the matching process may well involve recursive computations. 9. Concluding Remarks

I n reviewing the collection of symbol manipulation languages given here, two divergent approaches become apparent. On the one hand, LISP, SNOBOL,SLIP,and PL/I are higher-level languages that include symbol manipulation facilities. As we pointed out in Section 1.2, such languages may arise either through the embedding of symbol manipulation facilities in a general-purpose language or through the expansion of a symbol manipulation language to include general computation. L6 and EOL, on the other hand, are low-level languages. Their simplicity contrasts sharply with the complexity of the higher-level languages, but this simplicity is obtained at the cost of making the user do more work. Pattern-matching is a recurrent theme in symbol manipulation languages. Pattern-matching provides a nonprocedural method of specifying transformations on symbolic data, and it promises to be one of the dominant features of symbol manipulation languages in the future. Already, pattern-matching facilities have been embedded in LISP, a language that originally lacked these facilities. However, it is not easy t o embed pattern-matching in an arbitrary language. I n PL/I, for instance, the diversity of data types and the use of structures makes it difficult to define a standard data form, comparable to SNOBOL strings and LISP lists, on which matching and replacement could be done. The techniques of symbol manipulation are finding increasing application in such specialized fields as computer graphics and compiler construction. Though the languages discussed here have been applied in these areas to only a limited degree, the concepts and implementation techniques of these languages have been applied extensively. Symbol manipulation is a rapidly expanding branch of computing, but it is still considered somewhat exotic by the mass of computer users. Consequently, there has been relatively little pressure for standardization of symbol manipulation languages, and the “let a hundred flowers bloom )’view has prevailed. New languages continue to appear, and old

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PAUL W. ABRAHAMS

ones are const,antly being revised. It appears likely that symbol manipulation languages will stabilize as their use becomes more widespread, in much the same way as scientific and commercial languages have stabilized. At present, LISP and SXOBOL dominate the field (algebraic manipulation excepted), and LISP 1.5 has been reasonably stable for several years. Although experimentation is sure to continue, the day when symbol manipulation is just another way of massaging data is probably not far off. ~CKSOWLEUGJIENT

The writing of this article \\'as suppoited by the AEC Computing and Applied Mathernat ics ('enter, Courant Inhtitutc of Mathc~niatical Sciences, New York LTiii\-erbitj,uiidrr ('ontract AT (30-1)-1480 u i t h the U.S. Atomic Ericrgy Commissioii. REFERENCES 1. Abrahams. P., List -procesaiiig 1anguagt.s. i n Dzyttal Computer User's Handbook (M.Klerer and G . Korii, eds.), 1-239 1-257. McGrawHill, Ne- York, 1967. 2. Al,rafianis, P.. et al.. The LISP 2 progrnmmirrg laiigiiagr aiid system. Proc. -41'1( ' S Full Joirrt C'ornpciter Cotif.. S(rti Frtrriciato. 29, ti61 -676. 3. A s s o c i ~ t i ~for ~ icolnpiitiiig iniiclriticr>. Corrcm. =1CJI 9, entire ISSW (1966). 4 . 13obrou, I>. t;.. and JIrirphy. D. L., Strrictiirr of B LISPsystem using two1('\t'l st(Jfayr. CO?lOlC. /lC'A\I10. 155-159 (196i7). 5 . Uobrou. I>.. and Raphael. B., A comparison of list processing languages. Ct~m,r/ .-lCJI 7. 231 240 (1964). 6. 13obri)u. I].. inid 'I'c~itclinaii. IY., Format-direeted list processing i n L I ~ P . 'I'cch. f i t b p t . . I M t , Btranrk. mid Stw mail, Tnc.. Cambridge, Massachusetts, 1968. $.

I'irracciolo

di

E'oriiio, -4.. and \Volbmsteni. S., On a class of programming

" J mbol manipulatiori based on c-utcnded Markov algorithms. Cetrtro Sttcrli CrilcolatrLci Elettronzclte tlel C . S . K . 121. 21, (1964). 8. < ?iristc~ir~(m. C.. Esainplta of s j mbol rnaiiiptilattoii i n the AMBITprogramming laiigiia&y. I'roc. AC.11 S n t l . COT?^., 20th. Clerelarirl. Ohm, 19/35, pp. 247 261. Thoinpstrii. \\'.lshiiigt{rn. D.('. 9 . ( ' l i r i s t ( s i i w i i . ('.. 0 1 1 tlrr impleinciitntiorl cpf AXBIT, a language for symbol r r i ~ i i i i ~ ~ i i l ~ ~ t Covtm. ii)li. dCJI 9. 570 572 (1966). 10. ( ' i t l i c ~ i i . J., -4n w o f fast aiid slou iiitmwrie5 i i i list-procrss~ng larigiiages. Coinm. -4c.1110. 82 hCi (1947). 2 2 . J?'artx.i. D. J., ( ~ i i ~ w o l c lI<. . E , aiid Polonsky, I. P., S ~ O B O L a , string ~ i i ~ ~ i i ~ ~ i ~ I . Iaiigiiage i t i i ) i i J . dssoc. C ' o r r ~ p t Jllack. 11, 21-30 (19M). 1 2 . F a r h r . D J , Gri5nold. K. E., aiid Polonsl.y, I. P.. The SNOBOL:< programrniirp Lu~pwige 13eIl S y s t e m Tech. .J. 45, 895-944 (1966). 1 3 . ( ;t+riitcv. H.. A ~ ~ O R T R-compiled A ~ list proresting Ia~ignage.J . Assoc.Comput. Jlach. 7. 87 1 0 1 (1960). I t . (;risnoIcl. K. E., k'oaptb, J . I?., a i d Poloiisky, I. P., Prc~lirnlmryreport 011 the S3ortor-4 programniixig language (IT). Hrpt. S4D4. 13e11 Teleptiorw I A I ~ . , Holmdrl, X e w Jersey. Noxeniber 1967. 15. Guzman, A., and McIntosh, H., C'ONVEHT. C o n ~ r nACM . 9, 694-615 (1966).

laiip\iagw for

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Ill

16. Information International, Inc., The Programming Language LISP: I h Operation and Applications (E. C. Berkeley and D. G. Bobrow, eds.), Inform. Intern., March 1964 [reprinted by M.I.T. Press, Cambridge, Massachusetts, 19661. 17. International Business Machines Corporation, IBM System/360 Operating System: PL/I Language Specifications. Form C28-6571-4. IBM, New York, 1966. 18. International Business Machines Corporation, IBM Systemf360: PL/I Subset Reference Manual. Form C28-8202-0.IBM, New York, 1967. 19. Knowlton, K. C., A programmer’s description of L6. Comm. ACM 9, 616-625 (1966). 20. Lawson, H. W., PL/I list processing. Comm. ACM 10, 358-367 (1967). 21. Lombardi, L. A., Incremental computation. Adwan. Computers 8, 247-333 (1967). 22. Lukaszewicz, L., and Nievergelt, J., EOL programming examples: a primer, Rept. No. 242, Dept. of Computer Sci., Univ. of Illinois, Urbana, Illinois, September 1967. 23. Lukaszewicz, L. and Nievergelt, J., EOL report, Rept. No. 241, Dept. of Computer Sci., Univ. of Illinois, Urbana, Illinois, September 1967. 24. McCarthy, J., Recursive functions of symbolic expressions and their computation by machine, pt. I. Comm. ACM 3, 184-195 (1960). 25. McCarthy, J., et al., L I S P 1.5 Programmer’sManual. M.I.T. Comput. Center and Res. Lab. of Electron., 1963 [reprinted by M.I.T. Press, Cambridge, Massachusetts]. 26. Madnick, S., String processing techniques. Comm. ACM 10, 420-423 (1967). 27. Newell, A., and Shaw, J. C., Programming the logic theory machine. Proc. Western Joint Computer Conf., 1957. 28. Newell, A., et at., Information Processing Language-V Manual, 2nd ed. Prentice-HalI, Englewood Cliffs, New Jersey, 1964. 29. Perlis, A., and Itnrriaga, R., An extension to ALGOLfor manipulating formulae. Comm. ACM 7, 127-130 (1964). 30. Perlis, A., and Thornton, C., Symbol manipulation by threaded lists. Comm. ACM 3, 195-204 (1960). 31. Perlis, A. J., Iturriaga, R., and Standish, T., A definition of Formula ALGOL, Carnegie Inst. of Technol., Pittsburgh, Pennsylvania, August 1966. 32. Reynolds, J. C., COGENTprogramming manual, AEC Ites. and Develop. Rept. ANL-7022, Argonne Natl. Lab., Argonne, Illinois, March 1965. 33. Rosin, R. F., Strings in PL/I, PL/I Bull. No. 4, SICPLAN Notices 2, Assoc. for Comput. Machinery. 34. Ross, D. T., A generalized technique for symbol manipulation and numerical calculation. Comm. ACM 4, 147-150 (1961). 35. Ross, D. T., The AED free storage package. Comm. ACM 10,481-492 (1967). 36. Sammet, J. E., Formula manipulation by computer. Advan. Computers 8, 47-102 (1967). 37. Smith, D. K., An introduction to the list processing language SLIP,in Programming Systems and Languages ( S . Rosen, ed.), pp. 393-418. McGraw-Hi11, NewYork, 1967. 38. System Development Corporation, LISP 2 for the IBM S/360, Doc. Ser. TM-3417, System Develop. Corp., Santa Monica, California, April 1967. 39. Weissman, C., L I S P 1.5 Primer. Dickenson, Belmont, California, 1967. 40. Weizenbaum, J., Symmetric list processor. Comm. ACM 9,524-544 (1963). 41. Yngve, V. H., COMIT Programmer’s Reference Manual. M.I.T. Press, Cambridge, Massachusetts, 1962.

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Legal Information Retrieval*

AVlEZRl S. FRAENKEL Department of Apblied Mathematics The Weizmann lnstitute of Science Rehovot. Israel

and

Department of Mathematics Bar /Ian University Ramat Gon. Israei

To the memory of Itamar Yirmejahu

1. Problems and Concepts . . . 1.1 Introduction 1.2 Basic Thesis . 1.3 Legal Information Explosion . 1.4 Scope . 1.5 Tests of Retrieval Systems . 2. Retrieval with Indexing 2.1 The Ills of Manual Indexing . 2.2 The 111s of Machine Indexing 2.3 To Index or Not to Index? 2.4 Use of Standardized Languages 3. Retrieval without Indexing . 3.1 General Description 3.2 Philosophy of the Method . 3.3 Grammatical Problems 3.4 The Synonym Problem . 3.5 Costs and Possibilities . . 3.6 Tests of Full Text Systems 3.7 The Skeleton Key . 4. Projects . 4.1 Full Text Projects . 4.2 Automatic and Semiautomatic Indexing . 4.3 Manually Indexed Systems Appendix I . Appendix I1 . Appendix I11 . References .

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* Work sponsored, in part, by the U.S. National Bureau of Sbandards. Reproduction in whole or in part is permitted for any purpose of the U.S. Government. I I3

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1. Problems and Concepts 1.IIntroduction

In an address delivered in November 1957, Simon [log,p. 61 stated the following: I n short we now hawe the elements of a theory of heuristic (as contrasted with algorithmic) problem solving; and we can use this theory both to understand human heuristic processes and to simulate such processes with digital computers. Intuition, insight and learning are no longer exclusive possessions of humans: any large high-speed computer can be programmed to exhibit them also .. On the basis of these developments and the speed with which research in this field is progressing, I am willing to make the following predictions, to be realized within the next ten years:

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(1) That within ten years a digital computer will be the world’s chess champion, unless the rules ba.r i t from competition. (2) That within ten years a digit,al computer will discover and prove an important new mat.hematica1 theorem. (3) That. within ten years a digital computer will write music that, will be accepted by critics as possessing considerable aesthetic value. (4) That within ten years most theories in psychology will take the f o m of computer programs, or of qualitative stat.ement,sabout the characteristics of computer programs.

This article was started in November 1967, at the conclusion of the period allowed for realization of these predictions. Regarding chess, a comput,er program which played a poor but legal game on a six-by-six board was written at Los Alamos in 1956. In December 1965, Dreyfus [ZI,p. 101 wrote: “ . . . in the nine years since the Los Alamos program beat a weak player, in spite of a great investment of time, energy and ink, the only improvement seems to be that a machine now plays poorly on an eight-by-eight rather than a six-by-six board.” Greenblatt has recently written a chess program at the Artificial Intelligence Laboratory of Project MAC at M.I.T. “The program wins about 80% of its games against non-tournament players.. . . In the April 1967 amateur (non-master) tournament the program won the class D trophy ” [36].This represents one of the best achievements to date, but it is still very far from a championship, as the nonmaster tournament is the lowest of three tournaments, and class D trophy is the lowest of four grades. The most important arithmetical theorem discovered and proved by a computer to date is probably the following [66]: 275

+ 845 + l l O 5 + 1335 = 1445.

The importance of the theorem lies in that it disproves a conjecture of Euler stating that an nth power is the sum of not less than n nth powers,

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However, this proof only demonstrates the computer’s power in solving well-formed computational problems when directed by skilled men. No power in heuristic problem solving is demonstrated by it. A more modest application of computers to mathematical investigations, which has already demonstrated its usefulness, is checking conjectures, discovering new conjectures, and participating in and completing proofs of theorems formulated by mathematicians. Such use has been made notably by Lehmer and co-workers [75-771, Birch and Swinnerton-Dyer [8a, 1131 (see also Cassels [ I l l ) . Also, with respect to points (3) and (4),the present situation does not live up to the hopes expressed ten years earlier by Simon. 1.2 Basic Thesis I n the area of legal information retrieval-a term which is widely used and hence will also be adopted here, although a more precise term would be legal document retrieval in the sense of Bourne [9] (see also Walston [I201 and Bar-Hillel [8])-the pendulum of opinions between optimists and pessimists is not swinging quite as violently as in the general area of artificial intelligence, the fuzzy boundary of which partly includes some information retrieval activities. But a sober equilibrium has certainly not yet been achieved. In a talk given in February 1967, Simitis [108, p. 51 stated (free translation): Automated processes relieve lawyers and scientists of tedious literature searches. Whether one seeks statutes, regulations, decisions, or written opinions, the automatons always supply the desired documents with utmost precision. One should not think that work in this field is an exclusive activity of universities pursuing their experiments, or of authorities zealously seeking efficiency. Commercial enterprises have long since been active in this area, and, moreover, with astounding success. In sharp contrast, Wiener, a lawyer, expressed his views explicitly as follows [123, p. 10281:

. . . Even in the field of case and statute data retrieval, the user of the machine is still at the mercy of the original indexer’s fallibilities, besides which ~r few hours of personal digging in the digests will give him the feel and the flavor of the decisions in a way that no machine possibly can. In short, members of the Bar will be well advised to stay very far away from computers if they want to remain-or become-lawyers rather than simply attorneys at law. Computers are fine for inertial guidance problems-but the law is neither a missile nor an atomic submarine. Let us be done with the learned nonsense that is baaed on the contrary aasumption. The basic thesis is simple : Present-day computers are potentially very efficient for solving problems which can be formulated well, problems for which a n algorithm has been given; but they are rather

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clumsy in heuristic problem solving. This does not mean that every well-structured problem can be solved efficiently on a computer, nor that every ill-structured problem cannot be handled well by a machine. Problems in combinatorial analysis, for many of which computers are much too slow, illustrate the first type of exceptions. The exceptions in the opposite direction are illustrated-to a lesser degree-by Samuel's checkers programs [106],which achieved a limited measure of success, and by Weizenbaum's patient-psychotherapist interview via ELIZA [121].But exceptions they are. In the context of legal literature searching, this thesis means that the most efficient present-day retrieval systems designed to be operational rather than merely experimental ventures, are those based on man-machine interaction activities. Processes in which neither partner is good should be eliminated as much as possible. The remaining tasks should be divided into two sets, with a clearly marked boundary between them : The machine should handle the well-defined algorithmic processes, while man should handle the ill-structured processes. Skimming through the projects described in Section 4 and in Appendix I11 bears out the fact that the more the two types of tasks are kept separate-the more efficient, competitive, and operational the corresponding projects are. Projects in which the machine is assigned substantial parts of ill-structured processes are all in the research state or extinct. Neither did projects survive in which human beings were assigned tasks that are either easily mechanizable or can be disposed of easily. Although the boundary between the two sets should be clearly marked, i t should not be static in time. Many new developments in computer science and technology manifest themselves by a shift of the boundary line, .i.e.. by the computer conquering over processes previously assigned to man-processes that have come to be understood better and hence have become well structured, or processes that technological developments have helped to mechanize. For example, the development of optical page readers is expected to lead to their taking over a gradually increasing portion of the manual input stage. More fundamental developments in computer science may modify or change the set of tasks t o be performed, and, in particular, impose a new boundary line. For example, the computer era itself brought about the possibility of disposing of the traditional indexing process and making instead the total text available for machine search. 1.3 Legal information Explosion

In a stimulating address delivered before the Association of the Bar of the City of New York in 1922, Salmond [I051 treated a t length the problem of the ever-gropiing size of legal literature. " Law books are no

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longer capable of being read,” hc: said. “ They can be used only as works of reference.” One year earlier the problem was already discussed by Swayze [IIZ].Since then the problem has become more and more acute. It was discussed and lamented by many writers, e.g., by Dickerson [19], and analyzed and documented with charts by Allen et al. [ 5 ] .It is not necessary to discuss the problem here or to drop staggering numbers of rate of growth, since it is already well known. We shall only quote the following passage of Tapper [ I l 4 , p. 1261, writing about British legislation: “For example, Where to Look for your Law lists nearly 2,000 different series of reports, many of them comprising more than 100 volumes. When it is appreciated that one must add to these the much greater profusion of American reports as well as statutes, periodicals, textbooks and a host of miscellaneous sources, the true dimensions of the problem become apparent.” The increasing bulk of material clearly makes the problem of manually retrieving useful information more and more difficult. One of the problems-by no means the only one, but one which is sometimes forgotten -is that an index of a very large volume of material, or any large file for that matter, becomes rapidly unmanageable if organized according to a large number of criteria. These criteria, in addition, have to be fixed a priori, which imposes an inflexible rigidity, inasmuch as the uses to be made of the documents in the file may well change in time. I n an English-French dictionary, for example, information is organized mainly according to two rules only: the lexicographic ordering of English words, and that of French words. Thus it is easy to find in the dictionary all English words starting with the syllable my. But it is considerably harder to find all words ending in my (unless one has a reverse order word list), or to locate and count all three-lettered words. Mechanization, among other things, is an attempt to solve this problem, which, of course, is present only if the file is indeed expected to be searched in such a way that a number of different data organizations are required. Not only is mechanization used for speedily scanning indexes and matching sets of keywords and descriptors related by prescribed logical conditions; or because of the ease of updating or printing out selected portions of files; or for providing remote access to files. It also permits restructuring and reorganizing the data according to a wide class of criteria, which, furthermore, need not be given in advance, but can be specified as the need arises. A new measure of flexibility is thus attained (see also Alt [6, p. 51). 1.4 Scope

The literature dealing with proposed scientific solutions to the legal information explosion problem in particular and with the broad aspects

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AVlEZRl S. FRAENKEL

of applications of logic, modern technology, and computers in the legal profession in general-a subject which has become known as jurimetrics -is already growing more than one might expect. We estimate that over 2000 articles on jurimetrics were published in the last 20 years, most of them in the last ten years. One may well be swamped by too much information in the field, rather than paralyzed by too little The articles deal with an astonishingly wide spectrum of activities, in most of which computers play some role. Among them are: programmed teaching in law schools (a series of six reports on the subject is contained in part VI of [14], a review of a tutor text about practical law [ 9 5 ] ) ;possible applications of decision theory, probability, and statistical analysis to various aspects of law, see part IV of [ l a ] ; court administration [3, 39, 401; court. calendar scheduling [31, 38, 991; juror management and assignment of lawyers to indigent defendants [39, p. 1701; administration of land title records [ S O ] ; searches of patent claims [51, 1041; copyright problems and patent protection for computer programs [53, 79, 1193; mechanization in law libraries [12, 741 (work in this field is also being carried out by Steiner at the Squire Law Library, The Old Schools, Cambridge, England) ; applications of symbolic logic and deontic logic to law [16,64,94,1001;reapportionment and redistricting by computer [43] (see also EDVCOM Bulletin, under " The Computer in Politics [25]); mechanized crime detection and prevention [ I , 26, 32, 52, 69, 89, 98, 1031; admissibility of computer records as legal evidence and invasion of privacy problems [25, 35, 1221; analysis and prediction of judicial behavior [65, 73, 971; and many many others. In some of these activities the computer is supposed to assume a major function, in others the computer is only incidental to the solution of the problem. One example of the latter is the calendar scheduling problem in courts. In large courts, the backlog of both civil and criminal cases assumed monstrous dimensions in recent years. Computerization soon became the slogan for relieving the situation. When people started to sort out and define their problems in preparation for mechanization, it was found that the major cause of delay was that many cases were not ready for trial and had to be adjourned after having come before court. After some deliberation i t was decided to require parties to sign special certificates of readiness within a preassigned period of time, and before scheduling the hearings. This measure alone solved the backlog problem. Computers were than introduced for constructing and updating the master calendar, etc., but the main problem had been solved already in the process of preparation for computer use, before it was actually used. The situation is very much like the well-advertised computer management of the joint Navy-Lockheed research effort in ))

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developing the Polaris missile. No such computerized management was ever implemented for the project, but the fact that a manual network-like system was introduced [7b] so that people had to sit down and define when a job has been terminated, etc., made them understand the processes and the problems they were facing-which, incidentally, brought about the birth of PERT. Of all the activities in jurimetrics, the most important one is undoubtedly that of retrieving legal information. It is reflected by the fact that about 20% of all articles published to date on jurimetrics address themselves to the problem of legal retrieval, with which we are concerned here exclusively. Patent searches, for which there is a literature of its own, are not dealt with here. A very comprehensive bibliography about jurimetrics containing 1742 items of reference was compiled and published by Duggan [22,231. Duggan plans to publish supplements from time to time. It is to be hoped that he will indeed continue to carry out this very useful service (perhaps only adding the corresponding year or volume number to the Computing Reviews references). Thus we could-and did-refrain from recompiling a comprehensive bibliography for this article, and only some of the papers directly connected with the discussion were included in the bibliography. A review of the whole field of jurimetrics written by Lawlor in 1962 [72], a comprehensive review of activities in legal information retrieval and in judicial prediction written five years later by Harris [all, and six volumes [5, 14, 15, 67, 68, 1171 which are devoted entirely to jurimetrics, deserve, nevertheless, special mentioning. A quarterly called M.U.L.L. (Modern Uses of Logic in Law) devoted to jurimetrics was published by the American Bar Association Special Committee on Electronic Data Retrieval, in collaboration with Yale Law School, from 1962 to 1966. Besides articles in the broad field of jurimetrics it carried from time to time bibliographies and reviews of new books and articles, as well as lists of research projects conducted in this area all over the world. After the June 1966 issue, M.U.L.L. changed into Jurimetrics Journal, published by the ABA Special Committee on EDR in cooperation with the Law School and Mental Health Research Institute, University of Michigan. However, only one issue, that of November 1966, was published (in December 1967). The first issue of a new monthly entitled Law and Computer TechnoEogy appeared in January 1968. It is published by the World Peace Through Law Center. I n order to relate this article to the general area of information retrieval and its problems, the interested reader is referred to the excellent review of the field by Stevens [IlOa],which contains 662 references. For reviews of some of the newer activities see Reference [7a].

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1.5 Tests of Retrieval Systems Tests aimed a t comparing manual and machine searches are not easy to conduct. To be meaningful, they should be conducted only after a large and comprehensive chunk of material has been stored in the machine. If only a small amount of material is in the machine, the tests become next to meaningless. This is mostly because of the following two reasons: (1) Suppose first that for the test, the manual searcher is not limited to the small file. That is, he map search a larger file than the machine. Even if all the documents cited by the machine are among those cited by the manual searcher, an extrapolation of the machine’s performance for the case of a larger file-with respect to both the citation of relevant documents and false drops-is very unreliable. For any other test results, the extrapolation will not be easier. If, on the other hand, the manual searcher is limited to the file stored in the machine, the test does not reflect the true state of affairs, since a manual searcher will usually find it much easier to search a limited file, xlth which he may familiarize himself perhaps even to the extent of being able to locate relevant documents in it without resorting to any index. I n other words, in addition to an extrapolation of the machine’s performance, also an extrapolation of the manual searcher’s performance becomes necessary in this case. Such an extrapolation is mostly guesswork. (2) For evaluating test results, the documents are graded, that is, they are classified into categories such as relevant, partly relevant, and irrelevant. This grading is not a well definable task. It is difficult t o perform even when the documents are retrieved out of a large file. If the fiie is small, the difficulties increase. The judgment of a document ceases to be an absolute evaluation of the relevancy of its contents. Rather, its comparative relevancy with respect to the other documents contained in the limited file becomes important. The grader cannot apply his normal judgment about the measure of relevancy. He has to adapt his judgment to the limited universe of the documents that happen t o be in the test file. He has also to weigh simultaneously the relevancy of several documents, which means that he has to apply global judgments, which are more difficult to resort to than local judgments.

The inconclusiveness of the final test of the joint American Bar Foundation (ABF) and IBM project (Section 4.2.1) stems, to a large extent. from the fact that it was run only on some 5000 casw. (The grading instructions that were employed correctly contain some special guidelines because of the small number of cases in the test file.) The

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final test of Project Lawsearch [34],also suffered from the fact that only 1700 motor carrier damagelinjury cases out of a population of 2.5 million such cases could be included in the test files. Because of the inherent difficulties in grading, the scale should be designed to define each grade as clearly as possible, that is, to make the difference between any two grades as distinct and explicit as possible. The grading system of the Pittsburgh group (Section 3.6.1) seems to comply with this requirement slightly better than the ABF/IBM grading system. It is perhaps sad, but the fact has to be faced that normally a retrieval system can be tested effectively only if it contains a sufficiently large amount of material, i.e., only if efforts and funds beyond those required for a mere experimental undertaking have been committed. Those who set out to conduct experimental retrieval systems should first seriously contemplate the type of conclusions they will be able to draw from their experiments. Testing small experimental projects can normally only indicate whether the system works and satisfies certain necessary requirements. This is of course very important. But the ultimate test of the value of the system cannot normally be projected from results of testing small files. 2. Retrieval with Indexing

Indexing, as used here, means the assignment of a set of terms to represent each document, where the assignment depends on global considerations pertaining to the entire document, rather than on local considerations, i.e., considerations depending only on the word currently being examined itself, sometimes including its immediate neighborhood. The assignment can be made by man, machine, or both, but in either case, indexing is an ad hoc assignment for each document. In particular, full text dictionaries, concordances, KWIC(Key-WordsIn-Context) ,or Kwoc (Key-Words-Out-of-Context)indexes are excluded from the present discussion since the exclusion or inclusion of a word in such indexes is decided upon locally, by comparing the word currently examined with an a priori constructed list of words (which might be empty)-either a list of words to be excluded from, or a list of words to be included in the index. Such indexes-which for the sake of clarity should not be called indexes but deserve a new nomenclature-are mentioned briefly in Section 3.5. Also, citation indexes are excluded from the above definition. Incidentally, this type of index has been found to be useful for searching scientific literature in which comprehensive citations are used universally. But this is not universally the case in law (see also [4l,p. 277, 68, p. 40, 216, p. 51). Nevertheless, it is sometimes useful to trace, say, all

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cases that have cited a given case, in the hope that the citing cases are relevant to the given case. Citation indexes are among the proven tools for supplying information of this kind, even though some relevant cases may not cite the given case. Citation indexes have been used in the legal field a t least since 1873 [28b]. For other methods of defining the difference between the two classes of indexes described above, see Stevens [IlOa, p. 131. 2.1 The Ills of Manual Indexing

For manual indexing, the indexer has to go through the following steps: (1) read the document to be indexed;

( 2 ) try to understand it ; (3) separate the essential from the inessential, retaining the former and discarding the latter; and (4)assign a number of index terms to the document, either from a predetermined set of index terms, usually called descriptors, or from the document itself, in which case the selected terms are usually called keywords or uniterms.

It is immediately clear from step (3) that the indexing process is inherently associated with both a loss and a distortion of information. The set of index terms chosen as representatives of the document cannot possibly be identically interchangeable with the document itself. Some information is necessarily lost. The condensation, which is normally the result of step ( 3 ) , may in itself give a distorted picture of the document’s contents. Moreover, in the case of preassigned descriptors, the indexer can only approximate the document’s contents by index terms sincr some terms capable of describing the document more accurately may not be contained in the set of descriptors. This results in loss and distortion of information: loss if the descriptor set does not, include any term similar to the term sought; and distortion if it contains a term similar to but not sufficiently similar to, i.e., not semantically identical uith the sought term in the context. it is embedded in. Thus, even if the indexer is perfect, information must be lost or changcd. One type of loss of information is well illustrated by the following example given by Kayton. He wrote [ 5 7 ] that until 1952 thousands of patent infringement, cases in the United States had treated the patentability of an invention as a mystical, undefinable quantity, termed the levd or standard of invention. I n 1952. Section 103 of the Patent A%ctwas accepted. T t specified. essentially. that the subject mattrr to br patented must be nonobvious to a person having ordinary skills in the art. Almost all patent infringement cases since 1952 cited

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this statute, and a large chunk of legal literature has dealt with it since. Despite this, and 14 years after passage of the Act, no legal index included the terms obvious or nonobvious. A type of loss of a different nature, with rather serious consequences, hinted at above, stems from the condensing aspect of indexing normally implied by step (3). It requires the indexer to exercise judgment as to the possible aims and methods of searching the document. The decisions taken necessarily exclude certain aspects from being represented in the index. However expert the indexer is, he cannot foresee and accommodate in his choice of descriptors all possible searches that might ever be conducted. A case demonstrating this point is discussed by Allen et al. [5, p. 831. As Wilson put it [124, p. 4111: “ . . . the fact that each new decision must be boiled down to fit into a predetermined pigeonhole requires the digester either to leave out those portions of the case for which no pigeonhole exists, or to squeeze them, willy-nilly, into a preconceived mould. In either case, serious distortions may result.” Dickerson [19,p. 4861 added this comment: “For some time, new law has been more likely to come from the legislature or an administrative agency than from the court. And so we must also cope with the problem of searching the rapidly growing fund of statutes and administrative regulations. Consider too, the fact that this greatly increasing volume of material reflects a vastly more complicated system of controls, which, in turn, is addressed to a vastly more complicated society. The ‘ stuff’ of the law, as Llewellyn would say, has become richer and more voluminous. It is not surprising that its individual elements are correspondingly harder to pigeonhole.. . .” In practice, the situation is worse, since indexers are not always perfect. Steps (a), (3), and (4) neither define a well-structured algorithmic process nor an ill-structured process of a type performed reasonably well manually, as, for example, translation. Reporting about the first steps of a British project in legal information retrieval, Tapper [115, p. 1281 wrote the following: The plan .

. . was to index all the materials in a given area for both legal con-

cepts and fact situations. and then to attempt sample searches. The area selected was the law relating to the admissibility in evidence of confessions. It was felt

that this area was well-defined, self-contained, and, in this country at least, of relatively small compass. Some preliminary indexing was carried out on this basis. It proved to be disastrous. For one thing, the legal concepts, so well-defined in the books, proved to be much less so in practice. It was found that the indexers were quite inconsistent in their attempts to index the same document, and that even the same indexer was liable to index a document differently at different times. This was especially true when it was presented in a different context.

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On the one hand, indexing is a difficult and complex job requiring much insight, skill, and experience. On the other hand, it is normally performed by beginners, by the less experienced or less able lawyers (see, e.g., Harris 141, p. 2821, Jones [68, p. 1461). The situation is similar to that of typists or computer operators who do not always live up to the expected standards of performance. If they are able or otherwise gifted, the>- rarelr stay in their job. An attorney using a (manual or automated) retrieval system based on indexing, is thus a priori limited by the amount of ingenuity and insight of the indexer. A deeply rooted difficulty is that indexing imposes a rigid and fixed structure. Later experience with the system will often give rise to rueful reflections about the initial set of descriptors or the initial rules of selecting keywords. Actual changes rapidly become more and more difficult with increasing size of the index. Every change emits shock waves propagating through the entire structure, necessitating changes and reviews of much of the previous work. On top of this, indexing is very tedious, time consuming, and expensive, but usually lacks any information about the factual background of the cases being indexed. A11 these disadvantages are present whether the index is intended for manual or machine use. Indexes intended for manual use, which are normally hierarchical in nature, suffer from additional disadvantages. They are still more rigid. since even the promotion of a descriptor from a lower level t o the level of a major topic, or demotion in the opposite direction, will shake a major portion of the whole structure. It is a closed system which cannot bear the rich expansion in quantity, quality. and variety of statutes, case law, regulations, administrative rules, treaties. and judicial opinions generated in fast-moving modern times (see also Locvinger [84. p. 2711). Here, much more than in indexes intended for machine use---which are linear, in contrast to hierarchical-the indexer’s judgment enters critically. He has to grade the chosen topics and assign them to various levels. thus reflecting a certain legal viewpoint in which some particular aspect is more fundamental than others. A t each level there may be combinations of words-some of which are not necessarily descriptorsrather than single words. This increases the danger of going astray a t any level. The searcher must often spend considerable effort to pursue a particular subject, as the path leading to the last level may be much obstructed. In order to improve this situation. a subject which appears as a certain hierarchy of descriptors should in fact reappear several times, each time with a different arrangement of topics on the various levels.

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This, however, tends to increase the size very quickly beyond reasonable bounds-the growth is roughly factorially proportional to the number of levels-or to impose sharp curtailment of the depth (number of levels) of the index. Wilson [124, p. 4121, commenting about hierarchical indexes, wrote: “. . . there are very practical limitations on the size of the index volumes before they become unwieldy and on the size of the type before it becomes unreadable.’) Dickerson commented as follows [ZO,p. 1941: (‘The limitations inherent in traditional [hierarchical] methods of indexing have created two serious deficiencies: (1) lack of depth, and ( 2 ) limitation of full effectiveness to searches that reflect the same point of view as that reflected in the index.” Recently, linear indexes, rather than hierarchical indexes, have even been constructed for manual use. Such an approach has been used in particular by several U.S. government agencies (see, e.g., Dickerson [ZO]). 2.2 The Ills of Machine Indexing

Automatic indexing and abstracting is less time consuming, and, depending on the method, may be less expensive than human indexing. Also, the constructed index is normally linear, free from the perils of hierarchical indexing methods and controlled vocabularies. Moreover, in contrast to manual methods, the same index will be generated by the machine a t different times. But apart from this, automatic indexing suffers from the same symptoms as manually constructed indexes. In addition, the quality of the index is a t present no better than that of a manually generated index. The reasons for this are discussed extensively elsewhere (see, e.g., Bar-Hillel [S]), and we shall not do so here. For a state-of-the-art report on automatic indexing, see Stevens [110a]. As far as the author knows there was only one legal retrieval project which used fully automatic indexing: the American Bar Foundation and IBM joint project, which was started in December 1961 and lasted for about four years. Its progress was reported upon from time to time in the literature. It was implemented on a limited body of cases, and its results were unfortunately rather inconclusive (see Section 4.2.1). 2.3 T o Index or Not t o Index?

We concur with Wooster who expressed deep skepticism with respect to both manual and automatic indexing, at a symposium on legal information retrieval held in Washington D.C. in November 1963 [13, p. 281. It is interesting to note, however, that even in case of a

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task which is done poorly by both man and machine, a man-machine interaction mode of operation may result at least in a partial improvement i n both the generation and use of a n index. By putting the entire text into a machine, it can be restructured at will, and any keywords can easilv be searched for and located, thus providing a useful aid t o the manual indexer. One interesting new project of J. C. Lyons utilizes such a scheme (sce Section 4.2.2). In use, the machine permits coordinate setirchilzg, i.c., locating documents satisfying a number of requirements simultaneously, like the presence or absence of a set of keywords in the required documents. The set of keywords is chosen by the person conducting the search, but the coordinate search is performed by the machine, which is capable of doing it more efficiently than man-if the number of siniultaneous requirements to be satisfied is large. In conclusion, indexing-being a process depending on global perception-is done badly by machines. It is also done badly by man. Is there any alternative to indexing? If the files are sufficiently large, a “full text system may be more efficient than indexing the file. Such systems are discussed in Section 3. For smaller, or less important files, where a full test system cannot be justified, indexing, with all its ills, is unavoidable even in this computerized second half of the twentieth century. ”

2.4 Use of Standardized Languages

For solving or rather preventing a priori most of the problems in the broad field of information retrieval, it has been suggested time and again to use a standardized and unambiguous language. Such a proposal employing ’‘ precise logical language,” in particular symbolic logic, has been advocated also as a remedy for the problems of legal information retrieval. This approach has special appeal in the legal field since use of symbolic logic is expected to produce additional payoff without additional cost; namely. it is expected to expose ambiguities, inconsistencies, contradictions, and redundancies in law. Allen wrote extensively about this subject. For example, he described [ 4 ] a method to convert legal literature into strings of canonical or *‘ normalized ” logical sentences. Allen points out himself, however, that such treatment cannot be applied t o semantic and syntactic commentaries about, or interpretations of statements of legal consequences. Xlso, the proposed logical language is rather meager; for example, i t does not include quantifiers. In fact, it does not go beyond elenientary propositional calculus. Thus it is not possible, a t present, where the full language of symbolic logic is not being used, to include the details of the factual background of cases, nor even to describe fully the judicial content of all statutes and cases.

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Moreover, the conversion of legal literature into normalized logical language appears t o be even more time consuming than indexing since it requires careful analysis of each elementary statement of the document, together with global awareness of the meaning of the entire document. Here again, the judgment of the ‘‘ indexer ” enters critically. It affects directly and permanently the quality of the finished product. Of course, if legislators and judges would agree to formulate legal literature in standard logical terms, these difficulties would be largely resolved. Such a procedure has occasionally been suggested by the proponents of use of symbolic logic in law, but it is rather questionable whether the legislature will ever submit to such a proposal, particularly in the present state-of-the-art, where the proposed standard languages are not rich enough t o accommodate the breadth and the subtleties of law. A similar view to that of Allen, except for a shift in emphasis, was expressed by Kerimov of Leningrad State University. He expressed his belief [60]that computers can be used successfully in a large number of areas in jurisprudence but that their successful application depends on the creation of a special standardized symbolic language. This language is also expected to help in legal information retrieval. But the retrieval problem per se can be solved, according to Kerimov, even without the special language, by much simpler methods, such as the “full text ” method. The problem of converting an edited version of the original legal text to the symbolic language is disposed of by the statement [60]:“ . . . this problem is being eliminated by the development of special automatic installations for the symbolization of an edited text.” See also Kerimov et al. [61]. For various aspects of automatic translation of natural languages t o symbolic languages see Bohnert and Backer [8b] and Gallizia et al. [35a]. The promotion of use of symbolic logic in law has had some impact on the legal profession. Law schools a t some universities like Yale University, University of Sydney, University of Hamburg, and Polish law schools-Poland has traditionally been a stronghold of pioneering work in mathematical logic-have offered courses in symbolic logic at various times. But the idea of using symbolic logic for solving the retrieval problem, with which we are concerned here, has produced only isolated small-scale research endeavors. We finally remark that the use of standardized logical language is not the only systematic method for exposing contradictions and redundancies in large files. It can be and has been done efficiently by “full text ” methods (see Section 3.5), via man-machine cooperation: relevant passages are retrieved by machine, which are subsequently checked by man for consistency and other qualities.

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3. Retrieval without Indexing

3.1 General Description

I n this approach, which has become known as the full text method, the total text is entered into the machine. Once it is there, no separation of the text into two sets, relevant and irrelevanl, is undertaken by using global considerations as in automatic indexing. Rather, the machine performs such a separation by comparing each text word locally with a list of common words given a priori. A concordance is then constructed and stored internally, giving for each noncommon word, typically, the document number, number of paragraph counted from the beginning of the document, number of sentence counted from the beginning of the document, number of word counted from the beginning of the sentence, and line type; that is, a code number specifying whether the word appears in a line of text, a line of an annotation, a line of a heading, etc. X document here means some predefined logical entity of law, such as a statutory section or a case. A portion of such a hypothetical concordance is given in Fig. 1. Thus the word maternity appears in a line of type 2 as the seventh w-ord of sentence fourteen in the first paragraph of document 183, and elsewhere. I n addition to the concordance. the computer generates a so-called frequency list. Typically, it p i w s for each noncommon word the total number of its occurrences and the number of different documents it occurs in. Figure 2 contains a portion of a frequency list arranged alphabetically, comprising all Pennsylvania statutes [loll. I t was generated by the Pittsburgh group headed by J. F. Horty, who was the first to use full texts for legal retrieval on a large scale. For example, the word accomplice appears Maternity

0183. 01. 014. 07. 2 3210. 01. 008. 11. 3

0231. 03. 179. 11. 3 3210. 01. 017. 02. 3

K%thamtical

0027. 01. 013. 21. 3 1016. 01. 023. 78. 3

0027. 02. 036. 08. 3

&b.thenatically

0791. 01. 01. 03. 1

2732. 03. 108. 13. 3

Ha thematics

0027. 02. 122. 02. 3

XatricuZated

5127. 01. 051. 28. 3

6306. 02. 049. 08. 3

EktricuLation

0029. 04. 112. 08. 3

5129. 01. 012. 05. 3

Matrimonial

0809. 01. 067. 17. 3 2857. 02. 078. 12. 3

2855. 01. 003. 09. 2

Fro. 1. Portion of a (hypotethical) full text concordance.

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five times in three different documents. The frequency list is printed in the form of a booklet and is available to the user as an aid for framing searches. For full text processing and retrieval in fields not limited to the legal profession and the history of the subject, see Stevens [IlOa]. The following is an example of a search conducted by the U.S. Air Force project called LITE(Legal Information Through Electronics) (see Dietemann [20a]). The inquiry, obtained from the Office of the General Counsel of the Department of the Air Force, was concerned witJh retroactive administrative correction of erroneous charges to 93-78

Accompany

1-1

Accomplishes

28-28

125-90

Accanpanying

11-10

Accomplishing

1279-1057

5-3

Accanplice

56-44

Accomplishment

156-151

1-1

Accomplices

1-1

Accomplishments

1-1

Accords

89-83

Accomplish

47-40

Accord

1-1

Accosting

59-47

Accanplished

2712-2123

Accordance

2661-1306

Accorded According Accordingly

Account

FIG.2. Portion of a frequency list of the Pennsylvania statutes.

appropriations. The specific question was whether the decisions of the Comptroller General of the United States contain any relevant material on this subject. The question, as submitted, and the search strategy, are displayed in Fig. 3. The first two lines of Group 1 specify that the word one must follow within two words after the word more. In particular, documents containing the expression more than one will be specified. The last three lines of Group 1 specify documents in which the word multiple appears in the same sentence with either appropriation or appropriations. Thus Group 1specifies, among other documents, all documents which contain either an expression of the form more than one or an expression of the form multiple appropriation, or both. The last line in Group 2 reduces the set of documents to those which contain one of the six words specified in Group 2 within a distance of at most one sentence before or after any expression specified in Group 1. The last line of the search formulation specifies that the output should be the headnotes of the Comptroller General’s decisions, not the complete text, which could have been asked for instead. The computer cited four decisions, whose texts (not necessarily the headnotes) satisfy the search conditions. The four headnotes are contained in Appendix I. It is seen that only 14 Ccmp. Gen. 103 is a relevant decision. It is stated [20a, p. 201 that the search was submitted to LITE because a previously conducted manual search did not provide any relevant document.

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The frequency list is an aid for framing searches, in that it draws attention, a t a glance, to all or most of the grammatical variants of the original search terms-those variants which occur in the documents being searched. At least this is the case for the English language. The frequency list also gives one a notion of the order of magnitude of the number of documents that will be retrieved if one uses only one or two *O.XSIION*. W E R E M E R E ARE Two APPROPKLATIONS B O M *3F WHICH ARE CHARGEABLE OR AVAILABLE FOR M E SAW, OR *SLNILAR PURPOSES CAN THE ONE ALREADY CHRRGED BE f R E T W t T I V E L Y CHANGED OR ARNSTED BY ADEIINIETRATIVE *ACTION TO CHARGE ME O R f E R WHAT HAS ALREADY BEEN *iK4RGED TO THE FIRST

*

*5/16/66

*

mmP

1

LITE

VOL. 1-18

MORE

OR

worn

+2

OR

SENTENCE SENTENCE rp

GRWP 2

CR OR

CHANGE

CHANGED CHANGES ADJUST AANSTED ADJUSTMENT

OR

OR OR OR SENTENCE

*

GRCUP 3

OR

OR

AND OUTKIT

ONE HCLTIPLE APPROPRIATION APPROPRIATIONS

QUNP

+1-1

1

CHARGEABLE CHARGED GRalP 2

CITE

* *END

FIG.3. Original question and associated computer search strategy employed st the LITEproject.

words in a group which is not logically linked to other groupswords that the searcher believes to characterize sharply a certain aspect of the search. One of the most powerful tools of the full text method is the ability to specify that certain words appear within a certain distance from

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other words, by operators such as ((word+ 2 )’,((sentence”, ‘(sentence + 1 - 1 Group 1 ” of Fig. 3. Such operators will be called metric operators. In iterated use, they permit specifying that certain expressions appear within a certain distance from other expressions. For further details about search framing, available search operators, and available outputs see refs. [46-48, 48a, 54, 59, 80, 91, 1071. 3.2 Philosophy of the Method

The most conspicuous feature of the full text method is that indexing with all its ills is completely disposed of. This is as far as the preparation of the material is concerned. I n use, the searcher goes through very similar operations as a uger of an automated system which is indexed. He has to select terms and logical relations among them. The first question is: Does the procedure work at all? Bar-Hillel wrote 18, p. 4161: “. . . any scheme of directly comparing a request formulation with a straightforward one-to-one encoding of the original documents must be regarded as wholly utopian and unsubstantiated.” This conclusion follows a discussion of an example on hand of which the difficulties of the method are explained. The example is: Suppose that the searcher wishes to obtain a list of all documents dealing with corrosion prevention through electroplating, chromium plating excepted. I n addition, he is interested in a list of all documents about copper plating. The following machine search strategy is proposed: Cite all documents in the given collection which contain the expression electroplating at least three times and the expression corrosion prevention a t least twice, but do not contain the word chromium even once. I n addition, cite any document containing the expression copper plating a t least once. (We note, by the way, that this strategy excludes from the set of cited papers a paper which is mainly concerned with corrosion prevention through silver plating, but which also discusses briefly certain aspects of chromium plating. A small change in the search strategy can of course cause inclusion of such papers.) It is contended that the search will not provide satisfactory results. The arguments are as follows: ( 1 ) Documents dealing with the mentioned topic but not written in English will not be caught. ( 2 ) Irrelevant documents such as a document containing the sentence ‘(I n this paper we shall not deal with copper plating ” will be cited. (3) Among the documents written in English and dealing with this topic, an indeterminate number will not be referred to because they do not contain a sufficientnumber of times the expression mentioned in the request formulation.

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(4) Others will not be cited because they contain an expression disallowed by this formulation. This may be because of any number of reasons. The author may be using synonyms, circumscriptions, or even only such (for human beings) trivial deviations as having. “ prevention of corrosion ” or “ prevents corrosion ” or “ corrosion is prevented ” or thousands of other formulations. ( 3 ) The document, while still being highly pertinent to corrosion prevention through electroplating, need not contain expressions which, in whatever estended sense of “ synonymous are synonymous with the espressions occurring in the positive part of the request formulation. It might contain terms like silver plating, brass plating, gilding, anticorrosiw. and innumerable others. (6) In connection with the synonyms problem, it is observed that even if the documents are written in a standardized language, there are synonym problems. The most rigorous symbolic language system for the arithmetic of natural numbers, for instance-surely a part of for each natural number a n every language of science-contains infinite number of synonymous designations. The number 3, for exam?’ can clearly by synonymously designated not only by 2 1, 1 2 . 1 - 1 1, but also by 4 - 1, 5 - 2 . . . . ad infinitum . . . ” [8, p. 4171. ”

-

+

This being so for a standard;--, language. it is certainly the case for everyday language. It’ith respect to argument (1). present-day systems do indeed coinprise a data buse-that is. the totality of words, counted with their multiplicities, contained in the collection of documents being searched -most of whose words belong to a single language. However, one could think of a center in which data bases in different languages are stored side by side. arid where a team of cxpwts in these languages and the substance of the data bases would service a large number of customers who hare remote access to the center. Something along these lines is indeed contemplated by the World Peace Through Law Center in Geneva, which passed a resolution in July 1967 to provide an international computerized law service. Its final plans, if realized, may of course be quite different from the possibility mentioned here. Tapper, chairman of the World Peace Through Law Genter’s Committee of European Experts on the Computerization of Law, expressed his views on the subject as follows [116,p. 81: “For international applications the advantage of a complete text approach is that it does not require a n - translation from original sources. either from language to language. or from one legal system to another. This is just as well, since translation of the selectivity required could not be done by

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machines, and probably not by human beings either, as the fundamental concepts of different legal systems are by no means completely interchangeable. Under this method, each country’s law wonld be stored and searched for its own original language, but would be accessible to searches from any country. It would also allow materials created by any nations to be merged together, with no more difficulty than each nation would experience in adding new information to its own existing store. This is a very significant advantage, particularly for units like the European Economic Community where the structure of the organization promotes multiplicity of languages, and diversity of national legal systems.” See also ref. [102].Incidentally, describing a full text system in the area of patent searching, Magnino [51, p. 2121 commented similarly: ‘(Since normal text is employed, foreign language data may be entered and searched with questions composed in that language.” Meanwhile, the majority of jurists would be quite content with realization of the more modest prospect of having at their disposal an efficient retrieval system comprising unilingual documents only. It should be remarked, incidentally, that the problem of unilinguality arises not only in full text systems but also in automatically indexed systems. The number of irrelevant documents of the type considered in argument (2) is apparently not very large. The few tests that were run on full text systems seem to indicate that the number offalss drops, that is, documents irrelevant to the search at hand, is larger than in manually operated systems using manually prepared indexes (see Secdion 3.6.1). This is not much of a handicap, as irrelevant documents may be disposed of normally at a glance. This is in fact done as a matter of course in manual searching, where the searcher is often scarcely aware of having looked a t and then disposed of an irrelevant document. It should be remarked here also, that the false drops problem is present, to some extent, in automatically indexed systems as well. For example, if the sentence “ I n this paper we shall not deal with copper plating ” is followed by the sentence “Although it does not deal with copper plating, it has its historical roots in copper plating,” the document containing these two sentences will probably be indexed, among other things, under copper plating, since the expression appeared at least three times. Even if the expression copper plating appears only once, it may be picked up by some automatic indexing systems which concentrate on rare words and expressions (see, e.g., Edmundson and Wyllys [ 2 4 ] ) . Moreover, the false drops problem is occasionally very much present in conventional manual hierarchically organized systems. In such systems it is obviously impossible for the indexer to think of and

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accommodate all the detailed requests of future users. For example, there will probably not be any provision by which the searcher could a priori exclude papers dealing with corrosion prevention through chromium plating. He will have to exclude them a posteriori as false drops. On the other hand, it is easy to exclude such papers a priori by full text search techniques. The difficulty expressed in argument (3) results from an improper search strategy. The outcome of a search should not normally depend on the number of timcs an expression appears; rather it should depend on whether i t appears at least once or does not appear at all. Tn automatic indexing methods, frequency thresholds are used to sift out of documents those words that appear a sufficient number of times. Those among them not belonging to a list of common words, are automatically selected as keywords (see, e.g., Luhn [SS]). Later it was realized that more often than not it is the rare word-rare in general use, not necessarily in the document being examined-that carries most of the information (241. But whatever particular criterion is used, the approach is statistical. This is not the method used in a fulI text system. Rather, one tries to define the request as closely as possible in terms of the language that is used in the data base. The presence or absence of defining terms and expressions is the criterion for deciding whether or not a document meets the request definition, not the number of their appearances. I n attempting to refute argument (6), Fels and Jacobs [33, p. 7751 argued that the problem does not arise in the legal profession. Regulations concerning committees with five members are not referred to as committees " comprising two hundred and six minus two hundred and one native-born citizens " or the like. Writing about the same problem, Kayton t.57. p. 321 stated that the problem of an infinite number of synonyms does not exist for any given data base, which is after all, finite. If one is willing to interpret arguments (4),( 5 ) ,and (6) as meaning that there are cases in which a large number of synonyms or variants have to be taken into account, and this is what was apparently meant, the distance between the views of Bar-Hillel, Fels and Jacobs, and Kayton, is perhaps not as large as it appears. First, it is clear that the searcher should indeed take into consideration all grammatical equivalents. synonyms and other variants of words and expressions in which he originally thinks about his problem. It is prccisely here that man enters and puts in his share of work in this joint man-machine interaction mode of operation. Second, the difficulties presented to man do not appear today anymore to be as insurmountable as described by Bar-Hillel in 1962.

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3.3 Grammatical Problems The frequency list of a data base reflects the complete language used in the data base. Among other things, it contains all grammatical variants of every word used in the data base. For example, consider the totality of the Pennsylvania statutes, comprising 61 volumes, which contain a totality of about six and a quarter million words. About 45y4 of this text is composed of 112 common words [as, Chart D]. (This shows, incidentally, that full text systems may comprise as little as 55% of the text or even less. Hence the expression full text systems is rather misleading. But since this expression has been accepted generally, we use it here also.) Excluding these common words, the statutes comprise a surprisingly small number of only 23,159 different words. The frequency list of the Pennsylvania statutes is a booklet of 97 pages, smaller than an ordinary dictionary, which contains these 23,159 different words and their frequencies [loll. (Horty [as, Chart D] gives the total number of different noncommon words as 23,979, but this number also includes misprints which were later corrected. The corrected version of the frequency list [loll contains only 23,159 entries.) Under the root word prevent we find the following entries (the numbers in parentheses give the total number of occurrences of each word and the number of different documents they occur in, respectively): prevent (945-759), preventative (1-1), prevented (75-68), preventing (86-77), prevention (375-271), preventive (14-11), prevents (25-23). Now, on the one hand, this list immediately suggests additional variants of the original formulation of the request topic, like “ preventive maintenance by electroplating ” or electroplating procedures for preventing corrosion,” while it also conveys to us, on the other hand, the no less important information that no other grammatical variant of the word (‘prevent ” appears in any of the documents being searched. This already gives us a much closer grip on those few formulations among the “ thousands of other formulations ” that were actually used by the authors. Using each of the seven variants of the word prevent in conjunction with corrosion and electroplating and their grammatical variants by applying suitable metric operators should yield most if not all of the formulations actually used by the authors. Of course this should be done in parallel also for synonymous expressions, some problems of which are considered in Section 3.4. Some people feel that for any given word in the set of search terms, the computer should also automatically provide all words with the same “root ” or stem, at least for case law. Eldridge and Dennis described this approach [29, p. 891 as follows: ((

Professor Robert Wilson, Research Director of the Southwestern Legal Foundation, has undertaken experiments with the Horty-Pittsburgh system as applied

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to case law. The material for the experimentation consists of all reported cases dealing with arbitration in five southwestern states. Several refinements dictat.ed by the nature of the material have been made on the Keyword-in-Combination system. The most important refinement provides for collecting all the various forms of a given word under a common ‘‘ root ” term. Thus harm,” “harms,” “ harming,” harmed,” and so on, would be assigned a single numerical code. AH words occurring in the riatural text of the selected cases are arranged alphabetically in a list, with each word followed by the ‘‘ root index number ” whichidentifiesits basiccommon root. From thispointon, searching . . . is accomplished by using root index numbers instead of words. This means that in writ,ing a search question one does not have to advert to all the possible suffixes which may appear ina document collection, since all such words will have a common root index number. The operational value of the root index file in the selection of search terms is considerable. A greater degree of compactness of the concordance is achieved, with a consequent reduction in search time. I n order to minimize the pitfalls of subjective decisions about groupings, the task of subsuming words under single code numbers is performed by hand from a complete list of words occurring in the cases. The words are not. looked a t in context; only orthographical similarities are considered in the groupings. ‘I

,4 similar approach has been advocated by Kalikow [56]. We believe that this approach is not much of an improvement. Not only is the work of assigning code numbers to words tedious and time consuming, but it. is also susceptible to all kinds of errors, since words are not looked a t in context, and the notion of “ belonging to the same root ” is not well-defined. (Are root and uproot of the same root?) The use of the method is against the basic thesis expressed in Section 1.2, in that a function performed well by man, namely, the selection of the relevant grammatical variants for the particular search a t hand, out of the totality of variants, is delegated t o the machine, which, in its clumsy way, selects all of these variants, or a t best, a syntactically characterized subset thereof. Consider for example a search aimed a t retrieving all documents dealing with “loitering with intention to steal, but no act of stealing has yet commenced.” One of the search terms would obviously be steal. Under this root term we find the following entries in the Pennsylvania statutes frequency list [loll: steal (13-9),stealing (13-9),steals (11-9), stolen (79-49). While the first t.hree terms should obviously be select.ed for the search, the fourth should probably not, as no “ stolen ” goods were yet received, nor, in fact, was anything yet “stolen.” The w o ~ d“stolen” may of course appear in a document relevant t o this inquiry. For example, t,he document may contain an explanatory sentence of the form “Nothing was as yet stolen.” However, a,relevant document wi11 normally contain, in addition, one of the terms steal, stealing or steals. Inclusion of the term stolen may swamp the output wit’h an unnecessarily large amount of false drops. If the searcher-

LEGAL INFORMATION RETRIEVAL

I37

rather than the computer-would be provided with lists of grammatical variants for each word, and if this could be done economically, it would be of some help, since it would bring all grammatical variants to the searcher’s attention-terms that are prospective candidates for inclusion in the set of search terms. However, for the English language, very much help in this direction is already provided for by the frequency list of the data base. But even if lists of grammatical variants are at our disposal, the final decision as to the inclusion or exclusion of each term should not be irrevocably delegated to the machine, considering, in particular, that the lists of grammatical variants will probably contain erroneous or doubtful entries. Rather it should lie with the searcher, who may, perhaps, in some cases, if he so wishes, surrender this privilege to the machine. 3.4 The Synonym Problem

This problem is considerably more difficult than the grammatical problem, at least as far as the English language is concerned. I n the electroplating problem, the searcher should be aware of all the searchonyms as they became known; i.e., terms considered equivalent for a particular search like silver plating, brass plating, gilding, and anticorrosive that are present in the data base. It should be pointed out, however, that the synonym problem is also very much present in retrieval systems that are based on prior indexing, particularly in conventional hierarchically organized systems. In conventional systems it is in the prepamtory stage that the synonym problem is pressing; in full text systems it is the actual user who has to cope with it. Nevertheless, in conventional systems the user has also to cope with the problem to some extent. For example, the searcher should look for documents dealing with corrosion prevention through electroplating also under “ preventive maintenance,” since there might be documents containing phrases such as “ preventive maintenance through coating and plating,” in which the word corrosion does not appear, and the indexer may not have made the connection to corrosion. It is in general expected from the persons constructing a hierarchical index that they be aware of a large variety of connections. They must be aware that some of the papers including such terms as rust, consumption, gnawing, etching, decomposition, damage, attack, oxidation reaction, and retarding eflect, protect, hinder, avert, keep off, ward off, fend off, repel, guard, preserve, resist, save, spare and gilding, preventive coating, and many others, may have t o be indexed under “corrosion prevention through electroplating.” In addition, they must know that pitting, dezinci$cation, erosion, etc., are special forms of corrosion. Any of these terms and many others may be used in conjunction with

138

AVlEZRl 5. FRAENKEL

“ protective coating ” and synonymous expressions thereof-all to be indexed, among other items, under “ corrosion prevention through electroplating.” They must further know that scaling is a protection resulting from oxidation, that fretting corrosion has nothing to do with corrosion due to chemical reactions, etc., in order to be able to index papers about corrosion protection correctly. ‘We suggest that the searcher, who formulated his problem and is interested in solving it, is normally better equipped to find the suitable synonymous expressions for his request formulation than an obscure indexer, who most probably did not have this particular search in mind when he read and indexed documents which contain sets of terms such as mentioned above. In a full text system, the searcher is not anymore limited a priori by the work of an intermediary indexer whose work was completed many years ago. He is only limited by his own imagination and resourcefulness. Carefully constructed thesauri can increase the efficiency of full text systems, in that they draw the searcher’s attention to prospective search-term candidates. As in the case of lists of grammatical variants, however, it is the searcher, not the computer, who should decide which synonyms to use. Horty pointed out [48, p. 561 that in statutory law, successful searches were run at Pittsburgh without any thesaurus. i’herefore the construction of a thesaurus was continued by the Pittsburgh group only with low priority. (See also Appendix 11,which contains an analysis of failures on the part of the machine to retrieve certain relevant documents during a test conducted at Yittshurgh.) Kayton constructed a thesaurus for 73 appellate cases dealing with automobile litigation, which comprised some 40,000 words 1581. It is claimed [57, p. 321 that the bulk of the work was performed by machine, but the method is not disclosed. It took 135 hours of human contribution and 10 hours computing time on an IBM 7094 computer. The data base which was serviced by this thesaurus was not full text. It contained about 3Oqd of the text comprising “informing ” words only, which were obtained by statistical analysis at the joint ABF/IBM project (see Section 4.2.1). The entries of the thesaurus are of course limited to words actually occurring in the data base. The reduction to a partial text induces curious “ synonyms.” Thus the word away is synonymous to the word immediately (and to other words), since in the full text, the word away is at least once preceded by the word right, producing the expression right away, but the word right belongs to the set of discarded words. Incidentally, it appears that the operation with only 30% of the text,

LEGAL INFORMATION RETRIEVAL

I39

which means a saving in both storage and search time, is paid for dearly by the initial machine time cost of the automatic reduction, and by the man and machine time required for constructing a thesaurus with such special features as create being synonymous to rise. The expensive detour of initially inputting the entire text, then discarding 70% of it by statistical analysis, and finally trying to recapture it by a thesaurus-a process which will necessarily influence search returns negativelydoes not appear to justify the small savings to be gained.

3.5 Costs and Possibilities It has been pointed out that full text systems are expensive both in the initial input and preparatory phase, and in the process of conducting searches, where the computer has to scan the entire set of noncornmon words. It should be remembered, first, that also in any automatic indexing system, the entire text has to be read in. In addition, computer time has to be spent for carrying out the indexing. Thus the preparatory stage is even more costly. Second, a manually indexed system requires skilled indexing manpower, which is reflected in high initial costs. Tapper wrote [ I l 4 , p. 1271: “ ... an input involving preliminary analysis would make so much greater demands on the manpower likely to be available than an input without such analysis, that the latter solution might be preferred, even though the theoretical dificulties were greater. ” However, whether indexed automatically or manually, indexed systems are faster and hence cheaper to search, since the data files are smaller. Optical page readers, whose use was supposed to reduce input costs, are being developed at a slower pace than anticipated a few years ago. There exist today a few multifont page readers designed for special users’ needs, but they are not yet available commercially. Equipment available today on the market requires prior typing with special font. The electric typewriters used for this purpose are cheaper and simpler to run than keypunches or F’lexowriters-and in the United States the unions apparently do not insist that the operators of the former equipment be paid as high a salary as operators of the latter equipment--but their very existence emphasizes the fact that the major objective of eliminating typing and proofreading all input material that the use of page readers was supposed to achieve has not yet been attained. Many people have proposed to use data processing equipment already at the stage of drafting legislative material. Together with the final draft, a punched paper tape, ready for machine input, is obtained. This procedure is attractive and has additional advantages. Changes can be introduced and errors corrected simply by typing over the portions

140

AVlEZRl S. FRAENKEL

that need to be changed or corrected. I n addition to a clean justified and paginated printed output and a paper tape, a magnetic tape output for driving linecasting or photocomposition equipment can be obtained (see, e.g.. Haley 1371). This procedure normally saves time and greatly reduces data base preparation costs. It also expedites wide distribution of legal source material. The RECOMP project (see Section 4.2.2) utilizes ideas of this sort, and other projects are contemplating them, e.g., project LITE (see [81, p. 91 and Sieburg LIOTa, p. 391). It should bc rrwernlered that the promising directions of computer technology . the directions in which developments and improvements can be expected. point clearly toward a reduction of the cost of both full tcst Input and full test searching. In sonic not too distant future, the input of’printed material will not have to be retyped and proofread. Modern disk nicniories have already today reduced the cost of mass memories considerably. In addition. they become larger and larger and can be organized efficientlx in a similar way to the volumes of an encyclopaedia--an organization that permits rapid access, which is, within certain bounds. practically independent of the size of the file. This makes the cost of searching a full test file comparable t o that of searching a n index. 1,argc. amounts of‘ money have becn invested in experimentation with full test hystcms. It is only lately that projects of this sort show the first higiis of standing on their own feet commercially. Horty’s Pittsburgh group has been transformed into Automated Law Searching, whosc coiinections u-ith the Cniversity of Pittsburgh do not seem t o be as close a5 they used to be. During the first seven months of 1967, 470 inquiries were run, and four largc law firms and three large insurance companies have signed contracts with Automated Law Searching. These customers frame their own searches and at present they are charged a flat amount per month, irrespective of‘the number of searches run. At the same time Automated Law Searching advertises for and sells other services; e g . , it publishes thr d utomutcd Stututory Reporter. previously published by the American Bar Foundation (XSF) under the title Current Stute Legislution Service. Thc Autorriatcd Stututory Reporter is a KWIC index of the titles of current legislation of all 50 states of the United States. It is published about every two weeks during the legislative year. Based on this, a profile service called Stcctutes in Point is offered, which provides the crtstonier with current legislation about topics he is interested in.1 1 On F ~ uail N 1 , 1968, the entiir’ I’ittAurgh group tran4errctl out of thc Uniwrsity of Pitt-hiiigh arid foImed the. Aspen System-. C‘urporation, of nhich J. F. Horty 13 prebitlriit. 7 h t a t - n i \ w + i t > 1% o n ~ o f i t - principal zhart,holder\ Automated Law Searching 15 on(’ of i t - divi-ion-. Iriridentall~,one of the first operations of the new corporation t u iai,e the price of the Automuted Stututoiy Reporter from $125 t o $250.

LEGAL INFORMATION RETRIEVAL

141

Full text systems are of course ideal for automatically constructing

KWICindexes, whose wider and wider use in a variety of different fields asserts their usefulness. In the legal field, for example, the ABF used to publish an “ Index to Legal Thesis and Research Projects.” From the ninth issue on, published in June 1962, unt,il the eleventh issue which terminated the series, this index, which has become known as “The Little Green Book,” was published in the form of a KWICindex. Also project LITE makes extensive use of KWICindexes, as a form of output of searches, and as a form of dissemination of information. For example, LITE published KWICindexes of the total text of Titles 10, 32, 37, 50, and 50 Appendices of the U.S. Code a11 of which have particular application to the defense establishment (see, e.g., ref. [63]),and of the scope lines of the decisions of the Comptroller General of the United States (see, e.g., ref [62]).Also complete cross-indexes of the Internal Revenue Code and of other legal texts were constructed [54, p. 281. Other services that full text systems are particularly well suited to supply are studies of very large bodies of law, either for revisions or for checking for possible conflicts and redundancies. For example, the Pittsburgh group carried out a project of searching and collating the welfare laws of Pennsylvania on request of the Department of Justice of the Commonwealth of Pennsylvania [110]. On another occasion, the Pennsylvania Criminal Procedure Rules Committee proposed a set of rules pertaining to trial procedures and bail. The Pittsburgh group was asked to and did use its system to retrieve among all Pennsylvania statutes all those that seemed to conflict with the proposed rules or had some bearing upon them [Ill]. The total investment in project LITE up to July 31, 1967 was $1,300,000 [H,p. 221. The project had about 60 x 106 words stored by that time [81,p. 91. From October 10, 1966 to June 30, 1967, 757 searches were run. In the first eleven months of 1967, a total of 1367 searches were run. There is a complicated government policy regarding use of the system. For example, U.S. government users may conduct searches, but not outside users, who may, on the other hand, lease the data base and program tapes for copying them. They are then free to conduct searches for their own use or for commercial use. Agencies of the Department of Defense are not charged for the service. Other government users are currently charged a flat fee of $35.00 per search. Some changes in policy were recently made [3a,particularly pp. 16-19]. 3.6 Tests of Full Text Systems

Any test requires a considerable amount of human effort and time. These difficulties perhaps partly explain the small number of tests conducted to date. The three tests of full text systems in the legal field,

I 42

AVlEZRl S. FRAENKEL

which the author knows of. were all conducted with relatively large files but a t the initial stages of their respective projects, and thus reflect only their initial behavior. As more experience with the systems is gained and more material is stored in the machine, the tests should reflect comparative performance more realistically. 3.6.1. Test of the Pittsburgh System

I n 1962, Horty reported on a test of 24 inquiries concerning real legal problems, conducted on thc Pennsylvania statutes [ 4 7 ] . For each inquiry, the manual search and thc framing of the computer search were done IIJ- differchiit persons. No time limitation was imposed on the manual searches, which were performed by law students and professors of law. So thesaurus had been constructed for the data base in question at t h e time the tests were conducted. Any set of statutory sections that are both physically close and have a common sul)ject was defined as a statute for the purpose of this test. If the manual searcher retrieved a t h s t one section of such a statute, he was crrditthd with having found the entire statute. Similarly for the machine. Both the sections and statutes headings of Table I, which exhibits the results of the test, are divided into three subcolumns A , R,C. An A section or statute is deemed one which a researcher would wish to read in doing his research, whether it ultimately proved to be of use or not A H section or statute is deemed one which the researcher would wish to wad if certain facts, not clearly stated in the inquiry, were .lit. A c‘ statute is one deemed not relevant t o the inquiry. Most of the machine searches were run more than once. Horty [47. 1). 171 stated: “ I t should be noted that most of tht: searches . . . were run on the computer more than once, in various forms, in order to twt difftwnt methods of framing the most effective computer search. The figures given [in Table I] reflect the results of the best way t o frame these searchts. The general effect of rerunning these searches was to reduce the nuinbei of C statutes. Other results were substantially unchanged and it is felt that the results of the searches as originally run woiild have bcen substantially as useful. ” The computer search of the 24 inquiries retrieved a total of 2442 statutory sections. Upon analysis it was determined that these sections represented 1461 statutes. Of these there were 837 A statutes, 50 B statutes, and 574 C’ statutes. in other words, 61°/, of the statutes were in the A or B category; 57q$ were A statutes. For the same 24 inquiries, the manual searchers retrieved a total of 910 sections, representing 508 statutes. Of these, 439 statutes or S6%,

LEGAL INFORMATION RETRIEVAL

I43

were in the A or B category; 84% were A statutes. We quote from Horty [47, p. 161: “However, it is known that the typical manual searcher will scan and omit without notation many C statutes. Furthermore, the amount of time spent on each hand search indicates that many C provisions were examined but not recorded.” The computer searches produced 442 A statutes and 44 B statutes not found in the manual searches. The manual searches retrieved 34 A statutes and 4 B statutes not retrieved by the machine. Of the 34 A statutes, 11 were not retrieved because of errors in keypunching of the request cards, and because the program was not yet fully checked out at the time the tests were conducted. The number of A and B statutes, each of which was found by both man and machine, was 401. Thus the total number of different statutes retrieved jointly by manual and machine searches amounted to 925. If we assume thaf this number represents the totality of relevant statutes for these searches, only 4.2% were missed by the machine searches, as compared to 52.5% missed by the manual searches. Appendix I1 contains an analysis of the cases where the computer failed to retrieve A and B statutes found by the manual searchers. The analysis is taken verbatim from Horty [47, p. 181. A statistical analysis was performed by Fels [32a]. It is interesting to compare the above numbers with results of a test of a full text system conducted on a set of 100 short articles in the field of nuclear physics, comprising 250,000 words. The articles were studied by specialists in the subject, who rated the relevance of each paper to each of 50 questions, and assigned weighting factors representing the degree of judged relevance. A manual search based on manual indexing of the articles retrieved only 38% of the relevant papers. A machine search employing metrical operators retrieved 68 yo of relevant items. The same type of machine search, but augmented with terms derived from a thesaurus, yielded 86 % of the relevant papers (Swanson [llla], as cited in [lIOa, p. 1341). 3.6.2

Test ofproject LIT€

A test of the LITEsystem was reported by Davis [16a].It was conducted about one year after the inception of the system. Davis wrote: During a six-month period in 1964, after development of a data bast; of approximately 17 million words, a test of the LITESSytem was conducted. This test was conducted using the U.S. Code (all titles) and 23 of the most recent volumes of the Published Decisions of the Comptroller General (Volumes 19 thru 41) as the test file base. Representatives within the Department of Defense and the General Accounting Office were selected to submit test questions and were requested to compare the results of the computer searches against their manual

*-

TABLE I TESTRESULTSOF THE PITTSBIJRGH SYSTEM

Search

Title

Machine

No. 1 Treatment of infant3 2 3 4 5 6 7 8 9 10

11 12

Statutes retrieved only by

Statutes rrtrievrci

Sections tetrieved Manual

Machine

Machine

Manual

Manual

A

U

C

A

L<

C

4

11

C

A

R

C

A

B

A

B

38

0

35

13

0

15

32

0

29

8

0

9

26

0

2

0

5 99 41

2 2

5 73 46

2 0 8

33 5

5 61 24

2 2 1

1 48 23

5 41 19

2 0 0

6 4

3

1

3

1

2

3

1 65 27

5

1

0

0

54 3 3

0 0

18 3

32

0

0 0

14 2

7 15

0 0

5 3

13 1

1

0

0

19 25

0

21

5 5

407

10

309

101

1

-

274

5

118

72

1

-

209

52

4

38

29

1

5

28

4

34

12

1

5

1

51

3

127

31

0

-

45

3

104

29

0

-

28

3

12

0

32

2

25

20

4

13

19

2

20

15

2

9

4

1

0

1

7 3 0

62

6 1 0

8

6 1 5

41

5

4

1

1 1 1

0

0

7

5

3

5

7

0

0

0

in

hoqpitals ('are and treatment of unwed mothers Statutes relating to eyesight Statutov relating to hearing Statutes relating to pests and rodents Illegitimate children Jurisdiction of juztices of the peace, aldcrmen, etc. Control of transient wIler5by Pa. local govt. Right t o counsel in administrative proceedings Powers and duties of DPI, SPI, and SCE over private school= Is a kindergarten or high school program required? May a schoolboard buy liability for employees?

0

2

0

2K

0

E " n

x

5

2

6

8

5

0

2

2

5

0

2

0

0 5

6

0 7

4

2

0 1

0

1

i25 I-

13 Power and duties of State Council on Education 87 14 Powers and duties of Superintendent of Public Institution 243 15 Powers and duties of Dept. of Public Instruction 214 16 Is asst. superintendent of county schools a “ public officer ”? 0 1 7 Statutes relating to immunization 13 18 Statutes relating to shoplifting 1 19 Statutes relating to undersized lobsters 1 20 Must counsel be assigned an indigent murderer? 1 43 21 Statutes relating to gaming 22 Does dealing in real estate constitute “doing business ”? 1 23 Guidance counsellorsteaching or administrative 0 24 May a school district establish a junior college? 0

Total a

1428

2

0

51

0

-

65

2

0

38

0

-

27

2

0

0

6

14

148

0

-

93

1

8

65

0

-

30

1

2

0

12

21

153

0

-

100

8

7

66

0

-

40

8

6

0

0

23

0

0

-

0

0

23

0

0

-

0

O

O

O

K Gl

3 0

18 0

11 1

0 0

-

11

0

1

2 0

4 0

9 1

0 0

0

2 0

2 0

0 0

0 0

g -

0

0

L

O

0

1

0

0

1

0

0

0

o

o

o

f

1 0

2 27

2 28

0 0

1 0

2 7

1 14

0 0

-

0 8

1

0

0

35

-

1 21

0

1

0

-

t

2 P -I

rn

0

3

1

0

0

41

0

0

0

5

0

82

932

768

DPI: Department of Public Instruction; SPI: Superintendent of Public Institution; SCE: State Council on Education.

0

o

o

o

< E

-

0

o

o

o

p

0

-

0

0

0

0

10

69

442

44

34

4

1

0

2

1

0

-

0

0

30

0

0

0

-

0

0

5

0

26

116

837

50

574

429

0

0

146

AVlEZRl S. FRAENKEL

research efforts on thrse questions. During the test period (six months), 216 separate search questions, processed by the LITE System and researched manually, werr evaluated by the test user activities. The results of these evaluations are worthy of senom thought. The over-all analysis revealed: (1) In 16 of these 215 searches (7.5", of the total), the computer was less efficient than human research. LITE retrieved less relevant citations than were discovered by manual research. ( 2 ) In 95 of these 215 searches (44.1°, of the total), the computer equaled human rffort, LITE retrieved tho same number of relevant citations as were discowrcd hy manual research. ( 3 ) In 104 of thew 215 searches (48.4"; of the total), the computer (LITE) was more efficient and retrieved more relevant citations than were discovered manually.

X more detailed analysis, somewhat like the results exhibited in Table I, was not available. 3.6.3 Test of the Oxford System

At the \4'orld Peace Through Law Conference held a t Geneva in July 1967, Tapper exhibited test results obtained from testing his project

at Oxford University, England. Figure 4 illustrates performance of different types of search in terms of the percentage of relevant documents retrieved. It shows a comparison of manual searches conducted by trained lawyers using their tried and familiar techniques, with computer searches conducted on an experimental basis. The computer searches uere conducted on the conventional index terms, abstracts and full text, shown separately. It should be noted that there were no suitable index terms in the industrial injuries decisions.

' T.

L_7__11

Cornp. searches (0)

T

Camp. scorcher

(b)

FIG.4. Diagrams exhibiting initial performance of the Oxford University full text system: (a) all England law reports and (b) industrial injuries decisions.

LEGAL INFORMATION RETRIEVAL

I47

3.7 The Skeleton Key On December 2-4, 1964, a LITEuser evaluation conference was held [81,p. 51. Among other things, it was agreed that: “ Based on a complete understanding of LITE efforts and results, as presented during this conference, the evidence is overwhelming in favour of the potential value and need for LITEin the future.” A colleague of the author recently wrote to him saying that the LITE project proved to be a failure. Between these two extreme views, a large number of people seem to feel that at least for searches of sufficiently large files, where the searches are frequent, important, or complex, the full text approach is the only approach among existing methods which has proved its validity. They feel it worthwhile, a t present, to pursue the method further on an operational basis. Others admit as much, but a bit ruefully. I n an otherwise very interesting article, Hoffman [44,p. 251 wrote: “The natural language approach I consider as representing no real time saving in the selection of indexing terms because of the added difficulty involved in the construction of a thesaurus. Of course it is difficult to argue against success, and the natural language approach has achieved a measure of successful application.” Eldridge and Dennis wrote [29, p. 881: It is quickly apparent that the Pittsburgh system is the first to bring to bear on legal research problems computer capabilities other than speed. In the area of statutory law, where the system has been largely utilized, its effectiveness has been sharply demonstrated. Despite certain ipse dixit pronouncements to the contrary [ 8 ] , Professor Horty and his associates have proved that a completely unindexed body of literature can be searched effectively by a computer. The system is oriented purely toward language, relying solely upon the actual words used by the statute writers. Significance is attached only at the time of searching. This means that there is no necessity for any updating or reorganization routine. This is decidedly an advantage. In fact, the Pittsburgh system meets all our stated requirements. This suggests, since we are not totally satisfied in accepting that system as ‘the ideal,’ that our requirements may need some refinement. Mulling over our intuitive dissatisfaction with the Pittsburgh system, we sense that its chief difficulty is that the questioner must know what it is that he does not know. At least, he must, know the words which will be used to express that which he does not know, which amounts to the same thing. To rationalize our skepticism on this point we are willing to hazard several guesses: (1) The demonstrated effectiveness of the system is due partly to the nature and uses of statutory law. These are such that the searcher usually can identify the gap in his knowledge. This is certainly true of the types of searches which have been used for demonstration purposes. (2) The different nature and uses of decisional law are such that in a large portion of instances the searcher cannot identify adequately the gap in his knowledge. Especially will this be so where the research is aimed at the basic rationales which permeate all sorts of legal relationships.

I 48

AVlEZRl 5. FRAENKEL

(3) Ail adequate selection of search terms ~ 1 1 not 1 be so easy in case law, which not alva>s carefully framed in words chosen for clarity rather than literary quality

IS

.

This mulling over their intuitive dissatisfaction with the Pittsburgh system apparently provided Eldridge and Dennis, a t least in part,, with the motivation for starting their own project, an “ untouched-byhuman-hand ” procedure [29, p. 9.51. This overautomated approach, in which man is a priori excluded from participation, resulted in a project that remained an isolated effort. Incidentally, Eldridge and Dennis are not alone in emphasizing that there exists a basic difference between statutory law and case law regarding full text retrieval. Wilson wrote in 1966 [125, p. 551: “Unfortunately, there has been too little recognition of the fact that substantial differences exist between case law and statutory law insofar as machine searching and indexing methods are concerned.” These considerations apparently motivated Wilsoii into initiating his “ root index ” project mentioned in Section 3.3. Kayton wrote in 1966 [57, p. lo]: “Those who have worked in the field and who have tried to use the techniques developed for retrieving statutory material in a n attempt to retrieve case Iaw soon recognizc the qualitative difference in the technical requirenients between case law and statutory law retrieval systems [29, p. 891.” He concluded, however, that the only instrument required for augmenting existing techniques for retrieval of statutory law is a properly constructed thesaurus. Back in 1962, Dickerson wrote, after having described the Yittsburg full text system [19, p. 4951. So far tills approach has been used only to search thc text of sttttutes and abstracts of case lax\ . )Thy is this not the answer also to the problem of searching the text of caw la%\? Perhaps I t is. Mr. Horty IS no\+ experimenting with attorney general opinions and \\ill later include cases. Others remain bkeptical. In the meantimr. systems such as those developed respecti\ rly by the Patent Office and Robert T. Morgan at Oklahoma State University attempt to store only the text of case abstracts. One problem is that the volume of case law is o\eruhelmingly greater than that of statute la\\. Secondly, judicial opinions are writteii much more loosely and 111 a far more heterogeneous language. A ~ocabiilary list for a large body of case la\\ comparable t o that developed for the hospital statutes would approach the dimensions of a good-sized dictionary. Would this be too unwieldy for the average researcher‘, Only experience can tell. Some of the dtfficulties here can be lessened by ca~efullycon\ ertiiig the \ ocabulary list into a more &electivegeneral thesaurus, v ith helpful cross references t o synonymous or eqtii\ aIent exprrssions arid to higher leiels and lo\\er Iekels of abstraction. 111 the mearitime, Mr. Horty’s approach offers immediate re\\ ards iii the field of statutes.

l\‘hiIe the richer language of case law makes the synonym problem more acute, and a thesaurus more desirable, the fear that full text case

LEGAL INFORMATION RETRIEVAL

I49

law retrieval may be substantially different from full text statutory law retrieval proved to be unfounded. Both in Pittsburgh and in Denver (project LITE), much experience with case law has already been gained, and there is no indication whatsoever that the full text approach needs substantial modification to adapt to case law. Perhaps the most attractive feature of the full text method is its simplicity. It follows the path of least resistance in that it entirely avoids some of the tasks that are performed inefficiently by both man and machine, like indexing, and in that it requires performance of tasks which can be divided, roughly, into two (nonoverlapping) sets: tasks performed well by manual methods and tasks performed well by the machine, the notable exception being the construction of a thesaurus. In discussing the power of abstraction in mathematics, Littlewood wrote [83, p. 91: A locksmith may make fifty locks, each with its own key that will open none but the corresponding lock, but he can make one master key that will open every lock. This is because the opening mechanism is the same for each lock. One small portion of the key operates this mechanism, and this small portion must be present in every key. I n the master key there is that small portion alone, joined by a thin bar to the shaft of the key. There is nothing in the master key that is not essential t o every key, and because there is nothing redundant, there is nothing t o get in the way t o prevent the key from turning, in whichever of the fifty locks i t is used. The principle used in making a skeleton key is thus the concentration on the minimum effective part with the exclusion of everything redundant or nonessential. This austerity brings as a reward a vastly increased power and breadth of application.

A similar idea was expressed in the realm of law by Judge Lee Loevinger, one of the first jurists to apply scientific methods to law. He named such activities jurimetrics-a term which has been accepted universally. He wrote [85, p. 2091: William of Occam was a Franciscan mdnk who taught at Merton College, Oxford University in the early part of the fourteenth century. He was something of a sceptic and philosopher, writing on psychology, metaphysics and theology. He is best remembered today for the maxim attributed t o him, 'Essentia non a n t multiplicanda praeter necessitatena 'Antities should not be multiplied beyond necessity. Among students of philosophy and science this is known as ' Occam's Razor '-for i t serves to shave the surplusage from the concepts of science. It is also called the Principle of Parsimony and has long been one of the fundamental rules of scientific thinking. In more idiomatic language i t commands: Among equally plausible hypotheses, prefer the most simple.

The full text method is the most simple among present-day retrieval systems. It brings with it a new flexibility and breadth of application.

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4. Projects

This section contains very short descriptions of the subset of those projects in legal information retrieval that the author knows of, and that were judged to be beyond the planning stage, i.e., those that were judged to have actually got started. Not all the information given below and in Appendix 111-which includes summaries of the projects as of approximately September 1967 -has been authenticated. It is partly based on personal communications and personal impressions. Many of the projects are still in their infancy, in the sense that they depend on a single man. They stand and fall with the project leader. Only the large projects like those at Pittsburgh and Denver seem t o have grown out of their infancy, and show signs of life of their own, irrespective of the association or disassociation of a particular person. 4.1 Full Text Projects 4.f .f Pittsburgh and Denver

The Pittsburgh and Denver groups between themselves command at present mechanized data bases totaling about 180 million words. The data bases a t Pittsburgh include, among other items, the complete st,atutes of ten states, the U.S. Code, selected health laws, ordinances of cities, judicial decisions, rules and regulations. Table I1 lists the data bases which the Denver group has currently on its tapes [82]. A slightly different list is contained in ref. [81, p. 91. The Pittsburgh group was initially supported by the Council on Library Resources and the Ford Foundation. It started its activities in the fall of 1959 with an IBM 650 computer, in which 2250 Pennsylvania statutory sections were stored. I n September 1960, it obtained access to an IBM 7070 computer. Later an IBM 1410/1301 computer was used. Presently the group has its own IBM 360/40 computer, complete with two data cells, which should be replaced shortly by a 2314 disk pack with a capacity of 233 million bytes and average access time of 7 5 msec. The 360/40 computer is used exclusively for legal retrieval, and so was the 1410/1301 system. Whereas the programs for the first three machines were written essentially in machine language, the present program utilizes a new IBM Document Processing System [as], which handles nonformatted files (including some formatted information). I n the years 1961-63, the Office of the Staff Judge Advocate of the Air Force Accounting and Finance Center in Denver studied activities

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of legal information retrieval. In the second half of 1963, it signed a contract with the Pittsburgh group, which developed the system for LITE,tailored along the lines of the Pittsburgh system (but using for the first time ‘adisk for accommodating the dictionary and vocabulary). The University of Pittsburgh subcontracted IBM for this work. On TABLEI1 DATABASESCURRENTLY STORED BY LITE PROJECT United States Code (1964 ed.) All published decisions of the Comptroller General of the United States (vols. 1-45)

Manuscript (unpublished) decisions of the Comptroller General from 1954 Armed Services Procurement Regulations (ASPR) Fiscal Year 1966 Appropriation Acts Fiscal Year 1967 Appropriation Acts International Law Agreements (unclassified) Defense Contract Audit Manual Air Force Manuals AFM 110-4 Fiscal Law Manual AFM 110-5 Court Martial Instructions Guide AFM 177-102 Commercial Transactions a t Base Level AFM 177-108 Paying and Collecting Transactions at Base Level AFM 177-111 Reports of Survey at Base Level Air Force Regulations AFR 170-4 Funding of Morale, Welfare and Recreational Facilities Military Joint Travel Regulations Civilian Joint Travel Regulations DOD Directives and Instructions DOD Pay and Entitlements Manual Court of Military Appeals Decisions (CMR) Board of Review Decisions (CMR)

July 1, 1967, LITEcame of age, and continued on its own. However, computer support is still being contracted for. Delcos, Inc. is the current contractor, and for an annual cost of $343,000 they have to provide and maintain software, create new data bases, and update existing data bases at the rate of 1,250,000 words monthly [81]. 4.1.2 Other Full Text Projects

J. M. Gradwohl from the University of Nebraska has stored the Nebraska statutes, using Horty’s method, except that the programs are written in COBOL. The tapes are already available. See also refs. [Z,p. 82, 71, p. 1211.

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Another project following Horty’s method is that of Tapper at Oxford University, England, for case law [114, 1151. A set of 148 common words is defined, which reduces the text to one-third. An ICT Atlas computer is used, and a novel programming scheme seems to be employed. An additional project of this sort was conducted a t the University of Nottingham, England by Harris and Kent [42].It appears to have been dormant for some time now. The root index approach of Wilson was already briefly described in Section 3.3. An experimental project based on these ideas was carried out during 1960-63 at the Southwestern Legal Foundation in Dallas, Texas. Since the end of 1963, the project has been dormant [125,p. 571, (see also ref. [ l o ] ,and Wilson [124]). Kerimov of Leningrad State University stated in [60, p. 1611 that he conducted an experiment on a full text retrieval system, without giving further details. S. J. Skelly of the University of Manitoba, Canada, started a full text project which aims to store the full text of all Canadian Federal and Provincial statutes, in English and French. J. F. Triska of Stanford University started to store the full text of 5000 odd United Nations treaties. A full text project for the responsa (Jewish legal cases) is carried out in Israel on an experimental basis. The text of the responsa is printed without vowels-a fact that produces a considerable number of homographs. More seriously, the language of the responsa is a combination of Hebrew and Aramaic, closely intertwined and highly inflected. Several hundred grammatical variants of a single root word may occur in a single volume. Many of these variants differ in their prefixes (headers), others in their suffixes (trailers),and still others in their infixes (kernels). Thus they are difficult to locate in a frequency list. The following solution to this problem is currently being contemplated: Process each inquiry as a two-phase search, using grammatical synthesis. This means the following. In the first search phase, the computer applies rules of conjugation to the initial search terms, thus producing all the valid grammatical variants of each term. All of those which are actually present in the data base are printed out. The searcher then selects those variants that he wishes to include in the search. This produces the final set of search terms, with which the second phase, namely, a normal full text search, is conducted. The test is conducted on a set of 200 responsa. The programs for generating dictionaries and concordances have been written and the first searches were run. The experiment is sponsored by the Council of the Hebrew University’s Institute of Research in Jewish Law, and i t is carried out under the auspices of a Committee for Mechanized Legal

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Retrieval which comprises members from The Weizmann Institute of Science, The Hebrew University, and Bar Ilan University. The Institute of Research in Jewish Law was founded through the efforts of E. Urbach for the purposes of constructing an index for the responsa. The Institute is directed by M. Elon and has been working since its inception in 1962 on the manual construction of a hierarchical index for the responsa. 4.2 Automatic and Semiautomatic Indexing

4.2.1 The ABFIIBM Joint Project

Literature about this project can be found in refs. [?’,13, p. 30, 17,18, 27-30, 1251. The project was started in December 1961 and was terminated in 1965. The final report was not yet available when the manuscript of this article was finished. The project was supported partly by IBM and a $35,000 grant from the Council on Library Resources. One of the major objectives of the project was to design a fully automatic system, to the total exclusion of man. Several automatic indexing and searching techniques were employed. The final test, conducted in 1965, consisted of 40 questions run on a file of 5121 cases from the Northeastern Reporter, Second Series. The 40 questions were partly “donated” by the Fellows of the American Bar Foundation and partly constructed by law students. The grading was performed independently by four lawyers: a law professor, a research lawyer not from the ABF, a retired corporation attorney, and a young attorney with about five years practice. Each of them had to grade about 1200 documents. They were not informed of the methods that were used for obtaining the citations. The following grading instructions were given to them (W. B. Eldridge, private communication): Designate by the letter A-an “ on point ” case: On point does not mean a case factually on all fours. It refers rather to a case which could be used by itself to dispose of the issue raised in the case. It does not mean that this is the best case which might be found. The judgment is, rather, that of those cbses which have been found, this one can be used by itself for disposition. Designate by the letter B-a “relevant” case: Relevant means that the case is not dispositive of the issue, but that it could form a part of the disposition of the issue raised in the question. Again, the decision is to be made in terms of those cases discovered, not in terms of whether there are better cases outside the file and therefore not available for computer searching. Designate by the letter C-a “related” case: Related means only that the citation is for a case in the same general subject matter as the question. Thus, the question may raise a question of the rule against perpetuities in a trust situation. If the case deals with the validity or construction of trusts, though not a t all with the rule, use this designation.

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Designate by thr letter D-an ‘‘ irrelevant” case: Irrelevant means that the nothing t o do v i t h t h r i cluestion raised, vould riot contrihutr t o its rvwliitinn. anti i i not 111 the samr pcweral sribjret mattcbr.

r ~ l j ehas

It is v e r ~difficult to draw any conclusions whatsoever about the systtm’s performance. since the disagrcement among the graders was vcry marked. In several cases all four grades were assigned, and in many caws three out of the four grades were assigned. I t appears that this situation is mainly because of the following two facts: ( 1 ) The data hase was niiich too meager for conducting mcaniiigful trhsts. Eldrkigc~. the director of the project,, remarked [28, p. 1311: l’hc. most serious difficulty in cvaluating the operation of the system is the inadequacy of the basic file on which the experiments were conducted. \I’hile this file represented. at the time i t was created, the largest sample of cases utilized in computer research, it is not adequate for a satisfactory test of the system. Five thousand decisions taken chronologically from the Sorthecrstarn Reporter just do not include enough subjcct niattcr to producc meaningfiil citations in answer to many of the yucstions which were submitted.” ( 2 ) The proc(*ss of grading is not well defined. Whatever grading em is cwployed. human beings may diffvr sharply in their judgment. Expericncc t o this cffect 11 as already amply available when the ABF/ IBM system was tcstcd. For example. Ixecisc4y the same situation arose in a study of the Prnnsylvania Welfare Laws conducted in 1962. The difficulties were rcsolved by joint evaluations and discussions among the panel members l’hc few cases in which no agreement was reached were assigried the hiphrst grade proposed by any of the experts [110]. In contrast, in the XBF/lBJI t*est the experts worked completely independently from on” another (see also Scction 1.5). “

4.2.2 The RECOMP Project This intvrestinp looking project, which is not yet operational, but aims at Iwmming a commercial enterprise. is directed by J . C. Lyons of the Gcwrge Washington University: I ~ E V O M Pstands for Tnformation Itctrievel and Composition. The project plays on the wide distribution and usapc of conventional hierarchical indexes, and it aims at generating various tools which will makc the process of constructing and publishing sueh indexes more c>fficient.One of the main features of t h r system is flexibility and generality. l‘t,xtual mntcial likc full teut,, digchsts. a n d citations can tie entcwd into the niachinr in many ways by diverse input ’output devices. The text stored in the computer or selected I’ortions thrreof can be published in various ways and formats using

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tape driven composition machines. The text can also be restructured in the computer a t will, and keywords, KWICindexes, etc., can be printed out as aids for indexing. Such tasks as updating, merging new cases, and modifying editorial material may be done much more effectively by such a mechanized approach than by conventional manual methods. A company called RECOMP,Inc. was formed for carrying out this project in the area of tax law. It entered into an agreement with a major publishing house which sells annually over 25,000 copies of indexes to tax law. 4.3 Manually Indexed Systems 4.3.1 l a w Research Service

Law Research Service, Inc. is a commercial enterprise with headquarters in New York City. It was described by its president, Hoppenfeld in [ 4 5 ] . It is also described in various advertisements published by the company. The data bases consist currently of indexes of over three million U.S. federal and state court decisions. The manually constructed indexes are stored in the computer. I n order to use the system, special so-called “thesauri ” are required. They are alphabetically ordered, and associate with each elementary judicial concept a ten-digit number. A portion of such a thesaurus is shown in Fig. 5 . Actually, for each state there are eight different thesauri according to the following subject classification: Corporations, Contracts and Business Law; Criminal Law; Domestic Relations; Estates and Wills; Evidence and Procedure; Negligence; Public Law and State Taxation; Real and Personal Property. The federal thesauri are classified into 17 different subject categories. A typical inquiry proceeds as follows. The precedent-seeking attorney characterizes his request by means of a number of keywords. These keywords or synonyms thereof are located in the appropriate state and subject thesaurus (or federal and subject thesaurus). The corresponding ten-digit code numbers are then transmitted via standard Western Union Telex to the New York center. The four “ most relevant ” cases are located and cited by the two HONEYWELL 1200andU~1vac 418 computers in New York, and flashed back onto the requesting teleprinter for a fee of $12-15, depending upon the location. The full text of the cases is also available upon request, for an additional fee. There are a number of regional offices scattered throughout the United States from where such Telex searches can be conducted. Lately the company has been experiencing difficulties in its operations and in its cooperation with Western Union.

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Elevators, Regulation

0017630004

F I E , SPREAD CF Actions

-

Eviderce

0015500037

FIREARMS L i a b i l i t y f o r Injuries Caused by Firearms

0015590095

L i a b i l i t y of Manufacturer, S e l l e r of

0015590096

FIRES Actions-Trial, Judgment, Review AcZs, Constitdting Negligence Dangerous Substances, Machinery

0015520017

0015540006

FIG.5. Portion of a “ computer thesaurus ” which is part of thc system offered by the Law Research Service, Inc.

4.3.2 US. Government Agencies

The following C.S. government agencies in the Washington D.C. area have projects for retrieving legislative material relevant to their respective activities: Department of Justice (Antitrust Division), Internal Revenue Service, Central Intelligence Agency, Federal Trade Commission, Federal Communication Commission, and Federal Aviation Agency. I n addition, J. C. Lyons has recently started a project, at the Department of Labor whose file will contain opinions on unemployment compensation and security. 3 paper by Dickerson [20] contains thoughts and recommendations about the shape of the ideal project for the Federal Aviation Agency, for uhom Dickerson was consulting at the time. It also contains a clear description of the fist four above-named projects. The projects, especially the first, are also described in the literature [Z, p. 82, 55, p. 1127, 70, 78, 87, 881. We shall not describe them here except to say that they use manual indexing. The handling and printing is done partly by machines. The indexes are manually searched, but machine searching is not excluded. That is, machine searching could be implemented if the files would get very large at some time in the future. The full text is stored on microfilm. The main search tools are “thesauri ” of search terms and descriptor indexes. The Federal Trade Commission project

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is somewhat different and is rather similar to the “point of law” approach (Section 4.3.3).For further details the reader is referred to the above-cited literature. The upkeep of the project at the Department of Justice was discontinued. Only a very small number of the decisions concerning the Antitrust Division had been processed before discontinuation of the project. The system that has been established is rarely used. Also the use of the Internal Revenue Service project is not very widespread. 4.3.3 Other Manually Indexed Projects

The Brussels bar sponsored in 1966 formation of a committee of lawyers, judges, and law professors to study legal information retrieval habits and problems. The committee recommended establishment of a national nonprofit organization for analyzing and indexing legal material of interest to Belgian jurists for storage at a national information center. Such an organization, called CREDOC,was formed. It operates in cooperation with the universities of Libge, Louvain, Ghent, and Brussels, and also with the Cour de Cassation, where judges register the case judgment on a card after each case. A data base of about one million documents in French and Flemish is currently contemplated. Manual indexing and machine searching is used. The potential users of the system are the 6000 or so Belgian jurists. An experimental project using a small file is being conducted by the Paris bar. Descriptor indexing is used, which is performed by about 30 part-time lawyers, each working on the average about one hour per day. Both the Brussels and the Pwis bar have signed contracts with L’lnformation Rationelle, a Parisian computer support outfit, which writes all the software for the two projects. P. Rohn of the University of Washington, Seattle, classified all 8641 treaties of the United Nations Treaty Seriesaccording to 15 key variables and put the result of this process on tape. The system answers a variety of questions about patterns and trends regarding the treaties. Details about the project may be found, e.g., in [25a, 104~1. Three other projects that have been terminated and have already been much discussed in the literature should be mentioned: the “point of law ” praject which was started as early as 1957 by R. T. Morgan at Oklahoma State University [29, p. 85, 55, p. 1126, 961, the legal retrieval project at Western Reserve University which used an ultracomplicated manual indexing system [29, p. 90,41, p. 286,92,93],anda nonelectronic project called Project Lawsearch [13, p. 31, 34, 90, 118, 125, p. 571.

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ACKXOWLEDGMENT The author is much indebted to Professor Michael A. Duggan who helped the author i n various \vays to obtain reference material for this article.

Appendix I

The output of the full text search example described in Section 3.1 consists of the headnotes of four Comptroller General decisions. They are the contents of this appendix. A-10137, J C L T 3. 1925, 5 COMP. GEN. 2 CLASSIFIt.4TIOS OF CIVILIAB EMPLOYEES-TRANSFER O F ONE UNIT-POST OFFICE DEPEKSOS I S A C; KADE-APPROPRIATION PARTMEST USDEK ESC'EPTIOSS /2/ AND /3/ TO THE AVERAGE PROVISION, APPEARISG I S T H E ACT O F JANUARY 22, 1925, 43 STAT. 764, AN EMPLOTEE OCCUPYING T H E ONLY POSITION I N A GRADE WHOSE COMPESSXTIOS FVAS F I X E D AT T H E MAXIMUM SALARY RATE OF H I S GRADE. C S D E R RULE 3 O F SECTION 6 O F T H E CLASSIFICATION ACT OF 1923. 3fhT RETAIN SUCH MAXIMUM SALARY RATE ON AND AFTER JCL'I' 1. 1925, LVHERE TRAKSFERRED TO A VACANCY I N T H E SAME GHADE I S A S Y OTHER '' BUREAU, OFFICE, OR OTHER APPROPRIATIOK USIT." T H E AGGREGATE AMOUNT PROVIDED FOR PERSONAL SERVICES I N T H E DISTRICT OF COLUMBIA UNDER THE OFFICE OF THE FOURTH =1SSISTAXT POSTMASTER GENERAL, INCLUDING THE ITEMS '' SALARIES ' ' A X D I' MAIL BAGS AND EQUIPMENT," MADE AVAILABLE FKOM A FIELD SERVICE APPROPHIATION, CONSTITUTES ONE '' B'UHEAU. OFFICE. OR OTHER APPROPRIATION UNIT," WITHIN THE MErlSISC: OF T H E AVERAGE PROVISION MAKING CERTAIN ItESTRICTIOSS lT"p1: THE PAYMENT OF COMPENSATION I N THE DISTRICT OF COLUMBIA 'UNDER THE CLASSIFICATION ACT OF 1923. /MODIFlED €31-5 C'OMP. GEN. 6S.i ~-5txu.x,4cC;r's'r x. 1934, 14 COMP. GEN. 103 FEDERAL EWEKGESCY R E L I E F ADMINISTRATION-VOUCHERSAPPHOPRIATIOS AND ADJUSTMENT THEREOF-OBLIGATIONS C'HAKGEABLE To MULTIPLE APPROPRIATION AND THE VOUCHERING THEREOF. VOGCHEKS SUBMITTED I S SUPPORT O F DISBURSING OFFICERSACCOUSTS MUST SHOW T H E ACTUAL APPROPRIATION OR APPROI'KIATIOSS PROPERLY CHARGEABLE WITH THE EXPENDITURE KEPHESESTED BY T H E VOUCHERS, AND W H E R E T H E WRONG -4PPROPHIATIOS HAS BEEN CHARGED IT I S THE DUTY O F T H E GESERAL ACCOL'XTIXC: OFFICE I N AUDITING T H E ACCOUNTS TO Q'UESTIOS THE E S P E K D I T U R E AKD REQUIRE A SATISFACTORY E x i ' L m x r m r U ' OR ADJUSTMENT OF THE MATTER BEFORE CREDIT MAY B E ALLOiVED THEREFORE. LVHILE T H E GENERAL ACCOUNTING OFFICE MAY EFFECT ADJUSTMENTS BETWEEN APPKOPKIATIONS WHEN, UNDER A MISTAKE O F

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LAW OR FACT, A VOUCHER HAS BEEN CHARGED TO THE WRONG APPROPRIATION AND IT CLEARLY APPEARS THAT ANOTHER APPROPRIATION IS AVAILABLE, AN ADMINISTRATIVE OFFICER MAY NOT, FOR THE SAKE OF AN ADMINISTRATIVE EXPEDIENCY, DELIBERATELY CHARGE THE WRONG APPROPRIATION W I T H THE EXPECTATION O F OBTAINING SUBSEQUENTLY AN ADJUSTMENT T H E R E O F BY TRANSFER OF APPLICABLE APPROPRIATIONS-SUCH PRACTICE RESULTING I N THE RENDITION O F FALSE ACCOUNTS AND BEING VIOLATIVE OF THE PROVISION OF SECTION 3687 REVISED STATUTES. W H E N AN OBLIGATION IS PROPERLY CHARGEABLE TO MORE THAN ONE APPROPRIATION IT IS PROPER TO SHOW ON THE VOUCHER I N THE SPACE PROVIDED THEREFOR, ALL O F THE APPLICABLE APPROPRIATIONS AND TO DRAW ONE CHECK TO THE PAYEE I N PAYMENT O F THE OBLIGATION PRESENTED BY T H E VOUCHER. A-90178, MARCH 18, 1938, 17 COMP. GEN. 748 SAFETY SERVICE, PAMPHLETS AND POSTERS-ADVANCE PAYMENTS AND APPROPRIATION REIMBURSEMENTS ON BASIS O F INTERAGENCY SERVICES SAFETY PAMPHLETS AND POSTERS ARE NOT PERIODICALS WITHIN THE MEANING OF SECTION 5, ACT MARCH 4, 1915, 38 STAT. 1049, AUTHORIZING PAYMENT I N ADVANCE FOR SUBSCRIPTIONS TO PERIODICALS AND PAYMENT THEREFOR I N ADVANCE OF T H E I R DELIVERY I S PROHIBITED BY SECTION 3648 REVISED STATUTES. THE TOTAL COST OF SERVICES AND SUPPLIES PROCURED FROM PRIVATE SOURCES AND PROPERLY CHARGEABLE TO APPROPRIATIONS FOR TWO OR MORE PENAL INSTITUTIONS, MAY NOT BE CHARGED TO ONE OF THE APPROPRIATIONS WITH SUBSEQUENT REIMB’URSEMENT FROM T H E OTHERS UNDER SECTION 601 OF T H E ACT OF J U N E 30, 1932, 47 STAT. 417, THE INSTITUTION WHICH IS TO B E REIMBURSED NOT BEING “ I N A POSITION TO SUPPLY OR EQUIPPED TO R E N D E R ” THE SERVICES OR SUPPLIES INVOLVED AS REQUIRED BY SAID ACT, AND THE PRACTICE BEING VIOLATIVE O F THE PROVISIONS OF SECTION 3678, REVISED STATUTES. A-95599, J U N E 28, 1938, 17. COMP. GEN. 1117 TRAVELING EXPENSES-CIVILIAN OFFICERS AND EMPLOYEESFIELD SERVICE TRANSFERS INVOLVING DIFFERENT APPROPRIATIONS A CHANGE O F STATION I N T H E FIELD SERVICE OF THE WAR DEPARTMENT, UNDER THE SAME BUREAU AND INVOLVING PAYMENT O F COMPENSATION FROM DIFFERENT APPROPRIATIONS UNDER CONTROL O F T H E SAME BUREAU, W H E N MADE I N T H E INTEREST OF T H E GOVERNMENT, AND NOT FOR THE PERSONAL CONVENIENCE OF T H E EMPLOYEE, MAY BE CONSIDERED A TRANSF E R WITHIN T H E MEANING OF T H E ANNUAL STATUTORY PROVISION AUTHORIZING PAYMENT OF TRAVELING EXPENSES OF EMPLOYEES “ON TRANSFER FROM ONE OFFTCIAL STATION TO ANOTHER,” 17 COMP. GEN. 874. AMPLIFIED.

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AVlEZRl S. FRAENKEL

Explanations: The slashes in the above text stand for parentheses, which were not available on the chain of the line printer. The first of the above headnotes, those of 5 Comp. Gen. 2, were retrieved because the full text contains the two consecutive sentences: “ Your statement that there is t o be ‘ no CHANGE in duties ’ incident to the transfer of the employee from the appropriation ‘Mail bags and equipment ’ to the appropriation ‘ Salaries,’ both provided in the act of January 22, 1925, supra, under the office of the Fourth Assistant Postmaster General, would suggest that the proposed transfer involves nothing more than a determination as to which of the two appropriations mentioned is properly CHARGEABLE with the expenditure for this employee’s salary for the fiscal year 1926. A portion of your submission raises the question whether there is MORE than ONE APPROPRIATION unit under the office of the Fourth Assistant Postmaster General.” The words printed in small capitals and their relative position are seen to satisfy the search requirements. The single relevant decision, 14 Comp. Gen. 103, was cited because the last two paragraphs of its headnotes are seen to satisfy the search requirements. The headnotes of 17 Comp. Gen. 748 were retrieved because the full text cites the last two paragraphs of the headnotes of 14 Comp. Gen. 103.

The full text of 17 Comp. Gen. 1117 contains the sentences: “ I f a change in official station of an officer or employee4irected for the benefit of the Government-involves no break in service, no termination of employment by operation of law, no change in the appropriation to be CHARGED with the salary and traveling expenses of the officer or employee. and no change in the department or establishment under which the service is to be performed, such change in station may be regarded as a transfer ’ within the meaning of the statute, regardless of whether, in connection with such transfer, there is involved a change in title of the position or in the grade or salary rate of the officer or employee. . . . It has been recognized that the salary of an employee may be apportioned among MORE than ONE APPROPRIATION available for expenditure by a governmental agency (4 Comp. Gen. 432; 4 id. 703; 5 id. 1036; and decision of June 13, 1938, A-95008, 17 Comp. Gen. 1068). Also the salary of an employee may be paid from different appropriations under the control of the same bureau of the War Department for different portions of the year without otherwise affecting the position of the employee, that is, without the necessity of terminating service under one position and appointment to a new position. Hence, under the circumstances related in paragraphs a and b of your letter, the CHANGE in station in the field service may be regarded as a

LEGAL INFORMATION RETRIEVAL

161

transfer, and not as a new appointment, under the rule stated in decision of April 28, 1938, 17 Comp. Gen. 874, from which you quote.” The decision does not contain any other occurrence where ONE follows MORE within a distance of two words, nor does it contain the word MULTIPLE. Since no word of Group 2 appears within one sentence of MORE than ONE, this decision should not really have been cited. It was cited only because an inherent error in the search program failed to recognize the combination “).” (parenthesis followed by a period), as the end of a sentence. Thus the word CHANGE appeared to the program to be within one sentence of MORE than ONE, and hence the decision was cited erroneously. (Incidentally, C. A. Kelley and D. C. Dietemann informed the author that this error was apparently not detected previously. It was found after the author asked for the full texts of these four decisions and then inquired why the last was retrieved.) Appendix I I

This appendix contains an analysis of machine failures which occurred in a test of the Pittsburgh system discussed in Section 3.6.1. More specifically, it contains an analysis of the cases where the machine failed to retrieve A and B statutes found by manual methods. The analysis is quoted verbatim from Horty [47, p. 181. Search No. 1-Treatment of Infants in Hospitals: Two “A” statutes were not retrieved. One statute not retrieved used the phrase “state institution” in place of “hospital.” The other missed statute dealt with childbirth by an inmate of a penitentiary. The word “ institution ” should have been included in the group of words used to describe “hospital.” It would appear that the word “ penitentiary ” would not normally be thought of as an equivalent word for “hospital.” However, it must be noted that the manual searcher did find the penitentiary statute, showing that good manual indexing will sometimes result in retrieval of the odd statute. Search No. 2--Care and Treatment of Unwed Mothers: One statute was missed because the phrase “ lying-in-hospital ” was omitted by the framer. One “ B ” and two “A” statutes which were not retrieved, dealt with the failure to support an illegitimate child, a concept that the framers of the enquiry completely neglected to consider when thinking of the problem. Search No. 5 : The statute missed would have been retrieved by the search as framed except for a technical malfunction. Search N o . 7-Jurisdiction of Justices of the Peace: Three “A” and one “ B ” statutes were not retrieved due to the omission from the inquiry of grammatical variations of the word “issue.” One other “A” statute used the term “ magistrate ” whereas the framers of the inquiry required the phrase “ police magistrate.” The inquiry was framed too narrowly to retrieve that section. The other four “ A ’ statutes missed would have been retrieved by the search as framed except for a technical malfunction.

162

AVlEZRl S . FRAENKEL

Search s o $-Control of Transient Sellers. The “ B ” statute not retrieved prohibited the sale of certain specified goods arid as applicable generally to all sellcrs. It would riot ha\ e been feasible t y have framed the inquiry to retrieve this srction unless the legal problem required a specific aiis~verinvolviiig one of the specified goods Search S o . 9- Raght to Counael an Admznktrative Proceedtngs. Five “A” statutes r.ould have hem retrieved by the iise of such words as “session. trrbirnal, and inquiry.” These \+ordswere omitted purely by oversight. One “A statute could only have been retrieved if the phrase “appointing authority ‘‘ mere used as an equil alent for “administrative agency.” It is unlikely that ‘appo~ntingauthority ” \tould exci- suggest itself t o the framers without some sort of aid. such as a specially prepared thesaurus. The other six statutes missed mould have been retrieved by the search as framed except for a technical malfunction Search S o . 10-Powers and Dutaes of the Department of Publu: Instructzon: The onc “I3 ’ statute omitted \\astoo broadly phrased to have been retrieved i r y the srarchers =ere aware of its existence prior to b j a well-framrd ~ ~ i q i ~unless framirig the inquiry. Search S o . 14- Powers and Duties of the Superintendent of Publw Instruction: T M O”A‘ provisions \\ere not retrieved. One statute was not retrieved because of the failure to keypunch an amendment to the statute which changed the language used from ‘‘ Superintrndrnt of Common Schools ” to “ Superintendent of Public Instruction.” The other statute was a general statute applicable to the head.; of all go\ ernmental departments without specifying any in particular. Search S o 15-Powers and Dutaea of the Department of Publac Instruction: Six “A’ statutes that dealt ~ i t the h powers of certain specified boards which are located w i t h i n thr framework of the Department of Public Instruction were riot rrtrieved. Honcxcr. the framers of the search were unaware of these boards. Since references %errretrieved \\ hich listed these boards, the searcher would then be am are of them and could run a second search limited solely to these boards, if he so desired. Search A a 21-Statutes Helating to Gaming The statute missed \\ ould have been retrieved by the inquiry as framed except for a technical malfunction.

Appendix 111 SUMMARY OF PROJECTS AS OF

Institution Name or aim of project Year research was started Present status of project Current number of workers Full time equivalents Current annual budget Type of computer used

Current monthly number of computing hours Sponsoring agencies or institutions Project leader@)

Automated Law Searching, The Aspen Systems Corp., Pittsburgh, Pa. Full text project

APPROXIMATELY SEPTEMBER 1967 Dept. of the Air Force, Accounting and Finance Center, 3800 York St., Denver, Col. LITE; full texts of interest to the Dept. of Defense

1959 Active 150 (including 1 1 programmers) 100 $900,000 IBM 360/40; formerly IBM 650, 7070 and 1410/ 1301 computers were used 500

1961 Active 19

?; formerly Counc. Libr.

Resour. and Ford Found. John F. Horty

Univ. of Nebraska, College of Law, Lincoln, Nebr. Full text storage and retrieval of Nebraska statutes 1961 Active? 2?

15? $500,000 RCA Spectra 7 0 Model 45-F; formerly an I B M 1410/1301 was used

IBM 360150

175

About 17

Dept. of Defense, U.S. government Col. Charles A. Kelley, USAF Staff Judge Advocate

Univ. of Nebraska, State of Nebraska John Gradwohl

l? ?

i

Aooendix I I I-Continued Institution Name or aim of project

Year research wasstarted Present status of project Current number of workers Full time equivalents Current annual budget Type of computer used Current monthly number of computing hours Sponsoring agencies or institutions Project leader@)

Magdalcn College, Oxford Univ., Eng. Full text, caae law

1961 Active 6

Dept. of Law, Univ. of Nottingham, Eng. Full text storage and retrieval of treaties

?

Dormant or terminated?

Southwestern Legal Poundat.ion, Dallas, Tex. OGRE(Oil and Gas Reports, Electronic); full text retrieval of case law, using aroot index method 1960 Dormant or terminated?

?

4 25000

ICT Atlas at Harwell 1

Office for Scientific and Technical Information Colin F. H. Tapper

?

D. J. Harris?

Robert A. Wilson (left Southwestern Legal Foundation, present address unknown)

2 K

;P

Institution

Leningrad State Univ., Leningrad, U.S.S.R.

Inst. of Computer Studies, Univ. of Manitoba, Winnipeg, Canada

Name or aim of project

Full text storage and retrieval

Full text storage and retrieval of all Canadian statutory material, in French and English

Inst. of Political Studies, Studies of the Communist System, Stanford Univ., Stanford, Calif. Full text storage and retrieval of about 5000 U.N. treaties

Year research wm started Present status of project Current number of workers Full time equivalents Current annual budget

Before 1964

1966

?

? ?

Active?

Type of computer used Current monthly number of computing hours Sponsoring agencies or institutions Project leader@)

? ?

Active 3 (1 lawyer, 1 programmer, 1 assistant) 3 $11,160 (Canadian).Computer time is supplied by the Univ. of Manitoba. A larger budget for next year is a t present under negotiation IBM 360/65

? ?

?

D. A. Kerimov

?

Canada Council, Univ. of Manitoba Stephen J. Skelly

?

? ?

? ? ?

Jan F. Triske

I-

E9

I-

Arncricmi Httr Ir’ountlati o n , 1155. E. Sixtieth St., (%lcVLpo, 111.

Nunac. o r

itim

I4.11lly arltf>matIcallyIrldrxrd systrm for t hc rctricval of case law,

of project I967 Active 5

1961

Ternmmatctl i n 1965

-

Compu tern -111.Law Inst., Thc National Law Ccntcr, (ioorge Washington Urriv., Washington, D.C. and AUTOCOMP, h c . Handling and retrieving tax law (about 20,000 pages of material) Summer 1966 Active 11 programmers, 3 lawyers

-rnz

: ?

Currcnt monthly number of computing hours Sponsoring agencies or institutions Project leader(s)

14 $250,000 IBM 360/40 at George Washington Univ., Recognition Equipment scanners. Photon 901 and 7 13 photocomposition equipment About 40

3

The Weizmann Inst. of Science, The Hebrew Univ., Bar Ilan Univ. Aviezri S. Fracnkel

IBM, Council on Library Resources William B. Eldridge

Major book publisher. George Washington Univ., AUTOCOMP, Inc. John C . Lyons; George Cozzens

n

P c t

I-

Institution

Name or aim of project

Law Research Service, Inc., Western Union Building, 60, Hudson St., N.Y. Remote case law retrieval on commercial basis

Antitrust Division, Department of Justice, Washington, D.C.

Internal Revenue Service, Washington, D.C.

Retrieval system for Supreme Court decisions, briefs, legal memoranda, opinions of interest to the Antitrust Division 1962 Inactive since 1964 1 programmer, 4 lawyers (formerly) 5 (formerly) IBM 407 (card machine)

RIRA (Reports and Information Retrieval Activity)

Year research was started Present status of project Current number of workers Full time equivalents Current annual budget Type of computer used

1964? Active ?

Current monthly number of computing hours Sponsoring agencies or institutions Project leader(s)

?

25 (formerly)

8

Elias C. Hoppenfeld

John C. Lyons; Michael A. Duggan

Charles Casazza (founder and former leader: David T. Link)

? ? ?

UNIVAC 418 and two Honeywell 1200 computers

1962 Active 2?

l? ?

IBM 7074 (at Detroit)

Appendix IIl--Continued Institution

Central Intelligence Agency

Federal Trade Commission, Washington, D.C.

Name or aim of project

Retrieval system for about 100,000 documents

Retrieval system for Federal Trade Commission decisions, Circuit Court and Supreme Court decisions

Year research wasstarted Present status of project Current number of workers Full time equivalents Current annual budget Type of computer used

? ? ?

Current monthly number of computing hours Sponsoring agencies or institutions Project leader(s)

?

?

munication Commission About 8

?

Paul R. Beath

John C. Lyons; B. Slosberg

Federal Communication Commission, Washington, D.C. Retrieval system for Federal Communications Commission decisions

1963?

1965

Dormant or terminated? ?

Active 2 programmers, 4 lawyers

? ?

? ?

Card and magnetic tape equipment

UNIVAC 3 at Federal Com-

Institution Name or aim of project Year research was started Present status of project Current number of workers Full time equivalents Current annual budget Type of computer used Current monthly number of computing hours Sponsoring agencies or institutions Project leader@)

Federal Aviation Agency, Washington, D.C. Aviation law indexing and retrieval system

Department of Labor, Washington, D.C. Retrieval system on unemployment, compensation and security

CREDOC,Brussels, Belgium Set up retrieval system for all Belgian law, using manual indexing

1964

1966

1966

Active 2 programmers (half-time), 3 lawyers

Active 1 programmer (half-time), 3 lawyers (half-time)

Active

4

2

?

?

?

?

IBM 360/30 at the Federal Aviation Agency

IBM 1401 at Department of Labor

BULLGAMMA115 and XBM 360 system of L’Information Rationelle?

8

Not yet in production

?

John C. Lyons

Brussels bar, Belgian universities Baron Edouard Houtart

John C. Lyons; James Minor

?

Appendix Ill-Continued Institution

Paris bar, 38, ruo Scheffer, Paris

Name or aim of project

Experiment of manually indexed system for companies legislation retrieval 1967 Active? 35?

Year research was started Present status of project Current number of workers Full time equivalents Current annual budget Type of computer used Current monthly number of computing hours Sponsoring agencies or institutions Project leader(s)

7? ?

BULLGamma 115 and IBM 360 system of L'lnformation Rationelle?

Dept. of Political Seienca, Univ. of Washington, Seattle, Wash. U.N. Treaty Series Project 1963 Act,ive Varies with student enrollment

Point of law " retrieval -system for statutory and case law 1957 Terminated "

Varies with student enrollment Varies with student enrollment IBM 7094 and Burroughs B-5500

Paris bar

Varies greatly with uneven demand Univ. of Washington

Claude Lussan

Peter H. Rohn

?

Oklahoma State Univ., Stillwater, Okla.

Robert T. Morgan (deceased)

b

Institution

Western Reserve Univ., Cleveland, Ohio

Name or aim of project

Electronic searching of legal literature

Year research was started Present status of project Current number of workers Full time equivalents Current annual budget Type of computer used Current monthly number of computing hours Sponsoring agencies or institutions Project leader( 8 )

After 1955 Terminated before 1961 -

Michie Co., Bureau of National Affairs, Matthew Bender and Co., Jonker Business Machines, American Asaoc. of Law Libraries Project Lawsearch ; nonelectronic manually operated retrieval system for motor carrier case law 1962?

Terminated before 1967 -

Council on Library Resources Jessica S. Melton; Robert C. Bensing

William H. B. Thomas

c

in c)

?

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AVlEZRl S. FRAENKEL

REFERENCES In this list Modern Usea of h g i C in Law is abbreviated &.U.L.L. 1. A national crime information center. F B I Law Enforcement Bull. 35, pp. 2-6,22-23

(1966).

2. A.B.A. Special Committee on Electronic Data Retrieval-eurrent activities. M.U.L.L., pp. 82-83 (June 1965). 3. Adam, E., EDP aids to the courts.State and Local Gout. Conf., New York, 1964, pp. 18-22. System Development Corp. 3a. Air Force Project LITE. 17th Rept., Committee on Government Operations, 90thCongr., Home Rept. No. 1133 (1968).U.S. Government Printing Office, Washington, D.C., February, 1968. 4. Allen, L. E., Sketch of a proposed semi-automatic, hierarchical, open-ended storage and retrieval system for statute oriented legal literature. Proc. Congr. Intern. Federation Doc., Washington, D.C. October 1965, pp. 189-198. 5. Allen, L. E., Brooks, R. B. S., and James, P. A., Automatic Retrieval of Legal Literature: W h y and Hour.Walter E. Meyer Res. Inst. of Law, Inc., New Haven, Connecticut, 1962. 6. Alt, F . L., Information handling in the National Standard Reference Data System. Natl. Bur. Std. Tech. Note No. 290 (1966). 7. American Bar Foundation to study automated indexing of court decisions. M.U.L.L., p. 147 (September 1963). 7a. Annual Review of Information Science and Technology (C. A. Cuadra, ed.) (Am. Doc. Inst.). Wiley (Interscience),New York, Vol. 1, 1966; Vol. 2, 1967. 7b. Archibald, R. D., and Zilloria, R. L., Network Based Management Systems, p, 14. Wiley, New York, 1967. 8. Bar-Hillel, Y., Theoretical aspects of the mechanization of literature searching. DiqdaJe Informationswandler (W. Hoffman, ed.), pp. 406-443. Vieweg, Braunschweig, 1962. 8a. Birch, B. J., and Swinnerton-Dyer, H. P. F., Notes on elliptic curves, 11. J. Reine Anoew. Math. 218, 79-108 (1965). 8b. Bohnert, H.G., and Backer, P. O., Automatic English-to-logic translation in a simplified model. IBM Research Paper RC-1744, January, 1967. 9. Bourne, C. P., Methods of Information Handling. Wiley, New York, 1963. 10. Case law information retrieval demonstration. M . U.L.L., pp. 145-147 (September 1963). 11. Caasels, J. W. S., Arithmetic on an elliptic curve. Proc. Intern. Congr. Math., Stockholm 1962, pp. 234-246. Almqvist and Wiksells, Uppsala, 1963. 12. Chartrand, R. L., The Library of Congreas Legislative Reference Service; The S y s t e m Asproach: A Tool for the Congeas. The Library of Congress, Washington, D. C., March 1967. 13. Clevinger, F. M., Symposium on legal information retrieval. M . U.L. L. pp. 27-32 (March 1964). 14. Communication Scimcea and the Law: Reflections from the Jurimetrics Conference, Yale Law School, September 1963 (L. E. Allen and M. E. Caldwell, eds.). Bobbs-Merrill, New York, 1965. 15. Computer8 and the Law, a n I n t r o d w h y Handbook (R. P. Bigelow, ed.). Am. Bar. Assoc., New York, 1966. 16. Conte, A. G., Un saggio filosofico sopra la logica deontica. Riv. Intern. Filosof. Diritto, 42, Fasc. 111, 564-577 (1965).

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I73

16a. Davis, R. P., The LITE system. Judge Advocate Gen. Law Rev. 8, 6-10 (Special issue LITE, Legal Information Thru Electronics) (1966). 17. Dennis, S. F., Status of the American Bar Foundation research on automatic indexing-searching computer system. M.U.L.L. pp. 131-132 (September 1965). 18. Dennis, S. F., The design and testing of a fully automatic indexingsearching system for documents consisting of expository text. Information Retrieval, A Critical View (G. Schecter, ed.). Thompson, Washington, D. C., 1967. 19. Dickerson, F. R., Electronic computers and the practical lawyer. J . Legal Educ. 14, 485-497 (1962). 20. Dickerson, F. R., A legal document retrieval system for the Federal Aviation Agency, M.U.L.L., pp. 191-216 (December 1965). 2Oa. Dietemann, D. C., LITE in action. Judge Advocate Gen. Law Rev. 8,20-25 (Special issue LITE, Legal Information Thru Electronics) (1966). 21. Dreyfus, H. L., Alchemy and artificial intelligence. Rand Corp., Paper No. P-3244, December 1965. 22. Duggan, M. A., Law, logic and the computer: bibliography with assorted background material, Bibliography 9. Computing Rev. 7, 95-117 (1966) (reprintsavailable from Assoc. Computing Machinery, 21 1 East 43rd Street, New York). 23. Duggan, M. A., Law, logic and the computer: bibliography with assorted background material, Bibliography 13 (Suppl. A to Bibliography 9). Computing Rev. 8, 171-188 (1967) (reprints available from Assoc. Computing Machinery, 21 1 East 43rd Street, New York). 24. Edmundson, H. P., and Wyllys, R. E., Automatic abstracting and indexing-survey and recommendations. Comm. ASSOC. Computing Machinery 4, 226-234 (1961). 25. EDUCOM, Bull. Interuniu. Commun. Council 2, No. 5 . (October 1967). 25a. Edwards, E. W., Electronic data-processing and international law documentation. Am. J . Intern. Law 61, pp. 81-92 (1967). 26. Edzhubov, L. G . , On automation of fingerprinting expertise. Sovelskaya Krimimlktika na Sluzhbe Sledstviya (Soviet Criminology in the Investigation Service), 4th ed. Gosyurizdat, Moscow, 1961. 27. Eldridge, W. B., Report on the American Bar Foundation project. M.U.L.L. pp. 82-83 (June 1965). 28. Eldridge, W. B., The American Bar Foundation project. M.U.L.L. pp. 129-131 (September 1965). 29. Eldridge, W. B., and Dennis, S. F., The computer as a tool for legal research. Law and Contemporary Problems 28, 78-99 (1963). 30. Eldridge, W. B., and Dennis, S. F., Report of status of the Joint American Bar Foundation-IBM study of electronic methods applied to legal information retrieval. M.U.L.L. pp. 27-34 (March 1963). 31. Ellenbogen, H., Automation in the courts. Am. Bar. Aeeoc. J . 50, 655-658 (1964). 32. Eysmtm, I. I., Certain problems of the theory of investigating material evidence. Voprosy Kriminalktiki (Criminological Problems). Gosyurizdat, Moscow, 1962. 32a. Fels, E. M., Evaluation of the performance of an information-retrieval system by modified Mooers plan, Amer. Documentation 14, 28-34 (1963).

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AVlEZRl S. FRAENKEL

33. Fels, E. M., and Jacobs, J., Linguistic statistics of legal indexing. Univ. of Pittsburgh Law Rev. 24, 771-791 (1963). 34. Fiordalisi, V. E., Jacobstein, J. M., Price, M. O . , and Marke, J. J., Project Lawsearch. Law Library J . 60, 42-63 (1967). 35. Freed, R . N., Evidence and problems of proof in a computerized society. M.C.L.L. pp. 171-184 (December 1963). 35a. Gallizia. A , , Mollame, F.. and Maretti. E.. Towards the automatic analysis of natural language texts (translated from Italian). A G A R D ( A d k o r y Group for Aerospace Research and Development), NATO, Paris, 1966. 36. Greenblatt, R. D., Eastlake, D. E., and Crocker, S. D., The Greenblatt chcss program. Proc. Fall Joint Computer Conj., Los Angeles, November 1967, pp. 801-810. Thompson, Washington, D.C., 1967. 37. Halcy, S. R . , Legislative information system. M.U.L.L. pp. 93-98 (September 1965). 38. Halloran, N. A., Court congestion. Computers and the Law, An Introductory Handbook ( R .P. Bigelow, ed.), pp. 67-72. Am. Bar Assoc., New York, 1966. 39. Halloran, N. A., Modernized court administratron, Appendix E, Task force report: the Courts. The P r d e n t ' s Gornmision on Law Enforcement and ildministrution of Justice, pp. 162-171. U. S. Govt. Printing Office, Washington, D.C., 1967. 40. Harris, A . , Data processing and court administration. M . U .L.L. pp. 17P-175 (Dcccmbcr 1965). 41. Harris, A., Judicial decision making and computers. FiZla.nova Law Rev. 12, 272-312 (1967). 42. Harris, D. J., and Kent, A. K., The computer as an aid to lawyers. Computer J . 10, 22-28 (1967). 43. Hess, S. W., Weaver, J. B., Siegfeldt, H. J., Whelan, J. N., and Zitlau, P. A., Xoiipartisan political redistricting by computer. Oper. Res. 13, 998-1006 (1965). 4 4 . Hoffman, P. S., Lawtomation in legal research: some indexing problems. M . t 7 . L . L .pp. 16-27 (March 1963). 45. Hoppenfeld, E. C., Law Research Service/Inc. M.U.L.L. pp. 46-52 (March 1966). 46. Horty, J. F., Searching statutory law by computer. Interim Rept. No. 1. Health Law Center, Univ. of Pittsburgh, Pittsburgh, Pennsylvania. 47. Horty, J. F., Searching statutory law by computer. Interim Rept. No. 2. Health Law Center, Univ. of Pittsburgh, Pittsburgh, Pennsylvania, May 1962. 48. Horty, J. F., Searching statutory law by computer. Final Rept. Health Law Center, biliiv. of Pittsburgh, Pittsburgh, Pennsylvania, November 1962. 48u. Horty, J . F., A look a t research in legal infcrmation retrieval. Proc. 2nd Intern. Study Conj. C h a i f i m t w n Research, Elsinore, Denmark, September 1964 pp. 382-393. Munksgaard, Copenhagen, 1965. 48b. How to Use Shepard's Citations. Shepard's Citations, Inc., Colorado Springs, Colorado, 1873 and subsequently. 49. IBM System/360, Document Processing System (36OA-CX-l2X), Program Description and Operations Manual H20-0477-0, 1967. Tech. Publ. Dept., White Plains, New York. 50. Improvement of land title records, Reports of the Am. Bar Assoc. Comm.

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51.

52. 53. 54. 55. 56. 57. 58.

59.

60. 61.

62.

63.

64. 65. 66.

67. 68.

69. 70. 71.

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on Improvement of Land Title Records (R. N. Cook, Chairman). Real Property, Probate and T m t J., pp. 191-201, Fall 1966; Fall 1967. Information retrieval among examining patent offices. ICIREPAT Ann. Meeting, 5th, London, 1965 (H. Pfeffer, ed.) Thompson, Washington, D.C., and Academic Press, New York, 1967. Isaacs, H. I., System analysis theory vs. practice-a case study of the Los Angeles Police Dept. Inform. System, Publ. P-102. H. H. Isctacs, Res. and Consulting, Inc., Los Angeles, December 1966. Jacobs, M. C., Commission’s report re: Computer programs. J . Patent Ofice SOC.49, 372-378 (1967). Judge Advocate Qen. Law Rev. 8 (Special issue LITE, Legal Information Thru Electronics) (1966). Jurimetrics: the electronic digital computer and its application in legal research. Iowa Law Rev. 50, 1114-1134 (1965). Kalikow, M., A long-range program for mechanized legal and patent searching centers. M.U.L.L. pp. 78-86 (June 1962). Kayton, I., Retrieving case law by computer: fact, fiction and future. The George Washington Law Rev. 35, 1-49 (1966). Kayton, I., SYNDIG thesaurus of legal terms. SYNDIG, Inc., Washington, D.C., 1966. Kehl, W. B., Horty, J. F., Bacon, C. R. T., and Mitchell, D. S., An information retrieval language for legal studies. Comm. Assoc. Com@ing Machinery 4, 3 8 e 3 8 9 (1961). Kerimov, D. A., Future applicability of cybernetics to jurisprudence in the U.S.S.R. M.U.L.L. pp. 153-162 (December 1963). Kerimov, D. A., Andreev, N. D., Kask, L. I., Edzhubov, L. G., and Lebedev, P. N., The use of cybernetics in law. V’eetn. Leningr. Univ. pp. 141-144 (1962): Foreign Develop. Machinery Transl. Inform. Proc. JRPS: 14967. Office Tech. Service, Washington, D.C., August 1962. Key Word in Context, Index to vol. 41, Decisions of the Comptroller General of the U.S. LITE, Air Force Accounting and Finance Center, Denver, Colorado. Key Word in Context Index, U.S. Code, Titles 10, 32, 37, 50, 50 App. LITE, Vol. I, ABA-COM, Air Force Accounting and Finance Center, Denver, Colorado. Klug, U., Juristkche Logik, 3rd ed. Springer, New York, 1966. Kort, F., Quantitative analysis of fact-patterns in cases and their impact on judicial decisions, Harvard Law Rev. 79, 1595-1603 (1966). Lander, L. J., and Parkin, T. R., Counterexample to Euler’s conjecture on sums of like powers. Bull. A m . Math. SOC.72, 1079 (1966) [see also Math. Qomput. 21, 101-103 (1967)J. Law and Contern?. Probl. 28 (Special issue devoted to Jurimetrics) (1963). Law and Electronics: the challenge of a new era. Proc. Natl. Law Electron. Conj. lst, 1962 (E. A. Jones, Jr., ed.), Bender, New York, 1962. Law Enforcement, Science and Technology ( S . A. Yefsky ed.). Thompson, Washington, D.C., 1967. Law/Fact retrieval at F.T.C. M.U.L.L. p. 43 (March 1963). Law school research projects reported. M.U.L.L. pp. 117-124 (September 1966).

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7 2. Lawlor, R. C., Information technology and the law. Advan. Computers 3, 299-352 (1962). 7 3 . Lawlor, R. C., Analysis and prediction of judicial decisions-informal progress report. M . U . L . L . pp. 132-137 (September 1965). 7 4 . Leboaitz, A. I., Mechanization of the USAEC library; Part I : legislative information, TID-22643. Natl. Bur. of Std., Washington, D.C., November 1966. 75. Lehmer, D. H., The primality of Ramanujan’s Tau-function. Pt. 11: Computers and computing. A m . Math. Monthly 7 2 , 15-18 (1965). 7 6 . Lehmer, D. H., The prime factors of consecutive Integers. Pt. 11: Computers and computing. A m . Math. Monthly 7 2 , 19-20 (1965). 7 7. Lehmer. D. H., Lehmer, E., Mills, W.H., and Selfridge, J. L., Machine proof of a theorem on cubic residues. Math. C o m p t . 16, 407-415 (1962). 7 8 . L E S , LegaZInder, 2nded.AntitrustDiv.Dept. of Justice, Washington,D.C., September 1964. 7 9 . Linden, B. L., The law of copyright and unfair competition: the impact of new technology on the dissemination of information. M . U . L . L . pp. 44-52 (June 1965). 8 0 . LITE. General System Description. Staff Judge Advocate, Air Force Accounting and Finance Center, Denver, Colorado, January 1967. 8 1. LITE, Hearing before a Subcommittee of the Committee on Government Operations, House of Representatives, 90th Congr., U.S. Government Printing Office, Washington, D.C., August 1967. 8 2 . LITE, Sewsletter, No. 1 (1968). Office of Judge Advocate, Air Force Accounting and Finance Center, Denver, Colorado. AFRP 110-3. 8 3 . Littlewood, D. E., The Skeleton K e y of Mathematics, A Simple Account of Complex Algebraic Them&. Harper, New York, 1960. X I . Loevinger, L., Jurimetrics: science and prediction in the field of law. JZinn. Law Rev. 46, 255-275 (1961). 85. Loevinger, L., Occam’s electric razor, A1 . U . L . L . pp. 209-214 (December 1962). 86. Luhn, H. P., The automatic creation of literature abstracts. I B M J . Re. Develop. 2 . 159-165 (1958). 8 7. Lyons, J. C., New frontiers of legal technique. M . U . L . L . pp. 256-267 (December 1962). 8 8. Lyons, J. C., Automation and the administrative process. M . U . L . L . pp. 37-45 (March 1964). 8 9. McCabe, L. B., and Smith, C. P., System analysis in criminal justice information systems, SP-2749. System Develop. Corp., Santa Monica, California. February 1967. 9 0 . Marke, J. J., Progress report on Project Lawsearch. Law Library J . 58, 18-23 (1965). 9 1 . Mattern, C . L., Search Framing Manual (Automated Law Searching). \Vebster Hall, Pittsburgh, Pennsylvania. 9 2 . Melton, J. S., The “semantic coded abstract” approach. M . U . L . L . pp. 48-54 (Narch 1962). 9 3 . Melton, J. S., and Bensing, R. C., Searching legal literature electro~iictllly: results of a test program. Minn. Law Rev. 45, 229-248 (1960). 9 4 . Menne, A., Possibilities for the application of logic in legal science. dI.C’.L.L. pp. 135-138 (December 1964).

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95. Mixon, J., Review of Tutortext practical law: a course in everyday contracts by W. Lehman. M . U . L . L . pp. 226-231 (December 1962). 96. Morgan, R. T., The “point of 1aw”approach. M.U.L.L. pp. 44-48 (March 1962). 97. Nagel, S. S. (Review), Statistical prediction of verdicts and awards. M . U . L . L . pp. 135-139 (September 1963). 98. New York State Identi$mtion Intelligence System against Crime. Bureau of Public Inform. NYSIIS (R. R. J. Gallati, Director), New York, 1967. 99. Nix, L. S., Tomorrow’s techniques today; calender administration in the Superior Court of the State of California. The World Assoc. of Judges, World Conference on World Peace Through Law. Geneva, July 1967. World Peace Through Law Center, Geneva. 100. Paradies, F., Legal norms and the formbook of lawyers. RoZandino, Monit. Notariato 92, (1966). 101. Pennsylvania Statutes Word Frequency List (Automated Law Searching). Webster Hall, Pittsburgh, Pennsylvania, 1967. 102. Proposed plan for the computerization of law internationally (14 p. pamphlet). World Peace Through Law Center, Geneva, July 1967. 103. Ragan, L., Chicago’s police EDP system. Datamation 13, 52-53 (1967). 104. Riddles, A. J., Computer based concept searching of United States patent claims. M . U . L . L . pp. 175-188 (Decemberl965). 104a. Rohn, P. H., The UNTS Project. Geneva World Conference on World Peace Through Law, July 1967. Revised version forthcoming in Intern. Studies Quart. 105. Salmond, J . W., The literature of 1aw.Columbia Law Rev. 22,197-208 (1922). 106. Samuel, A. L., Some studies in machine learning using the game of checkers, 11-recent progress. I B M J . Res. Develop. 11, 601-617 (1967). 107. Searches of law by computer (20 pp. booklet). Univ. of Pittsburgh Health Law Center, Pittsburgh, Pennsylvania. 107a. Sieburg. J., LITE developmental activities Judge Advocate Gen. Law Rev. 8 , 36-41 (Special Issue LITE, Legal Information Thru Electronics) (1966). 108. Simitis, S., Automation in der .Rechtsordnung-Moglichkeiten h d Grenzen. Juristkche Studiengesellschaft Karlsruhe, Schriftenreihe, Heft 78, Miiller, Karlsruhe, 1967. 109. Simon, H. A., and Newell, A., Heuristic program solving: the next advance in operations research. Oper. Res. 6 , 1-10 (1958). 110. Springer, E. W., and Horty, J. F., Searching and collating the welfare laws of Pennsylvania by computer. Res. Rept. Health Law Center, Univ. of Pittsburgh, Pittsburgh, Pennsylvania, September 1962. 110a. Stevens, M. E., Automatic indexing: a state-of-the-art report. Natl. Bur. Std. Monograph 91 (March 1965). 111. Study of the proposed rules of criminal procedure. Final Rept. Health Law Center, Univ. of Pittsburgh, Pittsburgh, Pennsylvania, June 1965. l l l a . Swanson, D. R., An experiment in automatic text searching, word correlation and automatic indexing, Phase 1, F i n d Rept. Report C82-OU4 (April 1960), reprinted November 1960. 112. Swayze, F. J., Can we improve the sources of our law, Lectures on legal topics. Assoc. of the Bar of the City of New York. 3, 145-164 (1921). 113. Swinnerton-Dyer, H. P. F., Applications of computers to pure mathematics. Numerical Anuylsis: A n Introduction (J.Walsh, ed.), pp. 159-164. Thompson, Washington, D.C., 1967.

I78 114. 115.

116.

1lY. 118.

119.

120. 1.21.

122. 1.23. 124, 125.

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Tapper, C., Lawyers and machines. Mod. Law Rev. 26, 121-137 (1963). Tapper, C., British experierice in legal information retrieval. M. U.L.L. pp. 127-134 (December 1964). Tapper, C., World cooperat ion in the mechanization of legal information retrieval, Work paper for the working session on research and legal information by computer. Geneva World Conference on World Peace Through Law. GpncJua.July 1967. World Peace Through Law Center, Geneva. The George Wwhington IAW Rev., 33 (Special issue on law, scionce and technology) (1964). Thomas, ?V, H . R., Project Lawsearch, a non-electricon approach to law searching. M . U . L . L . pp. 49 54 (March 1963). Titus, J. P., Pros and cons of patenting computer programs. Comm. Assoc. Comput. Machinery 10, 12C-127 (1967). M'alston, C. E., Information rrtricval. Advan. Computers 6 , 1-30 (1965). Weizenbaum, J., ELIZA-a computer program for the study of natural language communication between man and machine. Comrn. Asaoc. Comput. Machinery 9, 36-45 (1966). Westin, A. F., Legal safeguards to insure privacy in a computer society. Comm. Assoc. Comput. Machinery 10, 533-537 (1967). Wiencr, F. R., Derision prediction by computers: rionsrnw cubed-and uorse. Am. Rar Assoe. J . 48, 1024-1028 (1962). Wilson, R. A.. Computer retrieval of case law. Southwestern Legal J . 16, 409-4:Ql ( 1 962). Wilson, R . A., Case law searching by machine. Computers a d the Law, an Introductory Handbook (R. P. Bigelou, ed.), pp. 55-59. Am. Bar Assoc.. Xew Pork, 1966.

Large Scale Integration-an

Appraisal

L. M. SPANDORFER Sperry Rand Corporation Univac Division Philadelphia, Pennsylvania

1. 2. 3. 4. 5.

6.

7. 8.

9.

Introduction . Device Fabrication Packaging . Economic Considerations . Interconnection Strategies . 5.1 Fixed Interconnection Patterns . 5.2 Discretionary Wiring 5.3 Special Studies . Bipolar Circuits . 6.1 Saturating Circuits . 6.2 Nonsaturating Circuits . MOS Circuits . LSI Memories 8.1 Bit Organization . 8.2 Word Organization . 8.3 Content-Addressable Memories 8.4 Read-only Memories . 8.5 Reliability . Further System Implications . References .

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179 180 184 190 194 194 197 202 205 206 209 213 218 219 224 228 229 230 231 234

1. Introduction

The last generation of digital computer circuits consisted of discrete components such as transistors and resistors interconnected on printed circuit cards. Present third generation integrated circuit technology is based on the fabrication of one or more entire circuits on an almost microscopically small silicon chip. The action today, denoted LargeScale Integration (LSI), is based on fabricating a plurality of circuits on a single silicon chip roughly equal to or greater than the logic power contained on many third generation cards. More than 100,000 logic circuits can theoretically be batch fabricated on a 2-in. slice of silicon, leading to predictions which soar from vanishingly small processor costs to the era of a computer-on-a-chip. Large-scale integration has been flowering since 1964-1965. No single invention initiated its growth; always theoretically possible since the 179

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development of silicon planar technology, LSI was delayed because of a preoccupation with critical learning problems at the small chip level. No single proposal or publication seems to have sparked the fire and set forth the long-term technical framework. Instead, the LSI concept evolved out of inescapable observations on hypothetical yields of large chips on wafers, coupled with the possibility of improved masking t
The initial procedures followed in fabricating LSI bipolar circuits are typical of those used in high volume integrated circuits, namely: ( 1 ) diffusion of buried n + layer into p-type wafer, ( 2 ) growth of n-type epitaxial layer over entire surface, (3) deep diffusion of p + isolation, (4)diffusion of p-type bases and resistors, ( 5 ) diffusion of n-type emitters and diffused crossunders, and (6) contact and circuit intraconnect metallization.

All but the second step require oxide growing and photomasking. The n-type epitaxial layer on the p substrate is currently the most commonly used starting material. The metallization, known as first level metal, can be used for limited circuit-to-circuit connections. A comprehensive review of processing and device design technology has been presented by Warner and Fordemwalt [88], and by Lathrop [40].

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If additional metal levels are required, an insulation such as low temperature rf sputtered silicon dioxide 1-4 p thick is applied over the wafer. The SiOz is then selectively etched to form vim to the first level metal, followed by deposition of second level metal. A side view of a gate with exaggerated vertical dimensions is shown in Fig. 1. The use of increasingly larger areas of silicon in LSI technology suggests the need for a substantial improvement in yield over conventional Integrated Circuit (IC) processing. Defects because of photomasking, 2nd LAYER METAL

RESISTOR

FIRST LAYER METAL

INSULATION THERMAL OXIDE n EPITAXIAL LAYER

n SUBSTRATE

" ''ITTER p BASE

\

BURIED LAYER

\

I

ISOLATION REGIONS

FIG. 1. Cross section of a bipolar device (exaggerated vertical dimension).

photoresist psocessing, and oxide pinholes constitute major sources of IC failure. The U.S. Air Force is currently sponsoring three major LSI contracts which are an important source of documentation on progress in yield improvement and many other aspects of LSI technology [ 4 l , 33, 131. Petritz has provided a survey of the main directions in these three studies 1631, as well as a significant review of LSI considerations from a technologist's viewpoint [64, 651. Some of the techniques under development consideration in the U.S.Air Force and other programs are the application of an additional and redundant masking oxide to reduce the likelihood of through-pinholes, the use of low temperature deposited oxides, double photoresist coatings, the use of projection rather than contact printing, the use of thick oxides, the use of diffusions from doped oxides rather than gaseous diffusions, and the use of laminar flow rooms within laminar flow rooms. I n addition to bipolar technology, Insulated-Gate Field Effect Transistors (IGFET) are receiving considerable LSI attention. The primary form of IGFET a t present is the p-type MOS transistor shown sectioned in Fig. 2. The basic fabrication requirements (in the newer thick oxide process) are : (1) diffusion of p-type source and drain,

(2) grow thick oxide,

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( 3 ) cut contact holes, regrow thin oxide, (5) cut contact holes for source and drain, and (6) metallize gate, source, drain, and circuit connections. (4)

The comparative fabrication costs between MOS and bipolar has been the subject of considerable controversy. Early estimates which based MOS costs directly on the reduction in the number of processing steps in comparison with bipolar were opt,imistic; the difficulty of certain steps such as (4), gate oxidation, were not adequately taken into account.

rL&-brl

METAL INTERCONNECT

GATE OXIDE

DRAIN

I

SOURCE

FIG.2. Cross section of p-type MOS transistor (exaggerated vertical dimension).

n SUBSTRATE

Recent estimates by Warner have revised the MOS advantage downward to a point where bipolar is about 3004 more difficult; counts of the major process steps required to produce bipolar and MOS wafers are indicated as 32 and 22, respectively [87]. The MOS transistor described thus far is called p type because of the diffused p regions; similarly, an n transistor can be devised (see Fig. 3). Although the n type has better potential speed performance because of its higher mobility, a problem arises because of an inherent layer of positive charge normally present on the silicon-silicon oxide surface which has the effect of shifting tlhe threshold voltage in the negative direction. The shift has the tendency to make n devices normally on rather than normally off, and historically has been the reason for the concentration on p devices. The MOS transistor is a charge-controlled device; i.e., conductive current does not flow into the gate. The p transistor drain is normally operated negative with the source a t a reference voltage, say, ground. Conduction between source and drain occurs when the gate is more negative than a threshold voltage of several volts, and essentially no current, flows when the gate is between ground and the threshold. The polarity relatioris for t h e p and n devices are opposite, or complementary. It was shown by Wanlass and Sah that p and n transistors can be combined into logic gates which dissipate zero power in the quiescent state except for an extremely small leakage component of the order of

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a microwatt or less [86].The complementary pair further provides a low dynamic output impedance for positive- or negative-going voltage transitions, a property necessary for high-speed switching when driving capactive loads. Single polarity MOS circuits can achieve near equivalent low impedances and propagation delays only through the use of moderately complex clocking arrangements; these topics will be discussed later in the section on MOS circuits. Despite the higher switching speeds and lower power dissipation offered by complementary pairs, p-channel MOS technology is currently dominant. This is because of the added problems in fabricating both polarities on a single wafer, the area loss because of the need for essentially twice the number of transistors in comparison with a nonclocked single polarity circuit, and a further area loss because of the p moat surrounding the n transistor. n TYPE

P TYPE

FIG. 3. Complementary pair of MOS transistors (exaggerated vertical dimension).

Prior to 1966 it was difficult if not impossible to consistently obtain reliable fixed-threshold commercial-grade MOS circuits. Major advances have since been made in threshold stabilization by controlling the presence of contaminants such as sodium ions, and in improved understanding of surface phenomena. A t present the technology gives evidence of satisfactory stability although complete acceptance awaits further data from large-scale reliability testing. Excluding laboratory development activities, operational experience on systems with large quantities of MOS devices has been limited. When doubts began to rise about the future of oxide process, workers turned to techniques that might surmount the drift problem such as using a layer which would serve as an effective barrier against impurity migration and which would have a greater chemical stability than silicon oxide. Significant improvements have been reported by Tombs et al. using silicon nitride as a replacement for the oxide [82].Concurrent with the development of the Metal-Nitride-Silicon (MNS) technology, improvements in MOS stability continued; as a result, commercial IGFET practice continues to use the apparently simple oxide process.

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3. Packaging Discrete components comprised the first level of packaging in second generation systems, with the Printed Circuit (PC) card and backpanel serving as the second and third packaging levels, respectively. The logic interconnections were generally formed on the back panel, with the card tending to merely serve as a carrier for the circuits. Integrated circuits form the first level of packaging in systems with third generation circuits. Integrated circuit chip dimensions fall in the 1500-5000 square mil range and production wafers go up to 2 in. in diameter; the larger wafers provide up to 1000 chips, each containing nominally 2-6 circuits and 14 Input/Output (I/o) pads. The spacing of pad centers on the chip is around 10 mils; this distance, however, is transformed via flying wire leads up to a center spacing on leads usually 50 or 100 mils in the final mechanical package. Although a wide range of designs are in use, the typical third generation PC card might be characterized as containing about 6-20 packaged chips. Many of the logic interconnections, however, have been transferred from the back panel to printed wiring on the card. The LSI chip will presumably merge the first two levels of present-day packaging into one. )Thereas arbitrary definitions for LSI such as 100 gates or more have been used, a possibly more appropriate threshold of TSI logic would seem to be roughly the equivalent of the 20-60 circuits that make up the typical third generation card. Integration of circuit groups of even this size poses a serious challenge t o the semiconductor industry in yield and mechanical packaging; two layers of metal are occasionally needed along with 4&60 I/O pads. Multipin extensions of the current 14-pin dual-in-line and flat packages are being proposed for this first wave of LSI chips. The largest known mechanical package from a terminal-count standpoint is a developmental model [all 2 in. square with 156 terminals on each of 4 sides. The terminals are typically 20 mils wide and are on 50 mil centers; the entire package is about 4 in. thick. . 0.25 , mil can provide sufficient component Masking tolerances of , density to realize 50 bipolar (or several hundred MOS) circuits in less than 10,000 square mils. Long-range forecasts [64]suggest the possibility of 3 in. wafers, chip sizes up t o 60,000 square mils, and 0.1 mil tolerances which will enable a factor of 3-4 increase in circuit density and provide the basis for up to 1000 bipolar gates per chip; device and circuit innovations could increase the count by a t least another factor of 5. The projected large number of gates per chip reflects the limitations incurred in wafer processing but does not necessarily take into account potentially critical limiting factors such as wiring space, dissipation (for bipolar circuits), and chip 110 pads.

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The relative dimensions of the circuits and wiring on an LSI chip do not appear to provide the basis for a reduction in the number of wiring layers below that generally found in dense conventional IC-PC board technology. I n the limit, when circuits are closely spaced, the wiring corridors between rows and columns of circuits tend t o become small. In this case the linear distance available for signal wire routing to a first approximation is a function of the ratio of the length of the circuit edge to the wire width, although in any given case the space depends on various parameters such as process tolerances, via diameter. Long-range forecasts predict production bipolar circuits of 10-50 square mils, and yield considerations cause interconnects between circuits to appear to be limited to about 0.2-0.25 mil in width. The resultant ratio of 35 or less is not significantly different from that found in various examples of current close-spaced technology, thereby suggesting an LSI chip will require about as many signal wiring layers as found on IC cards of comparable logic power. Integrated circuit technology has the advantage that circuit density can be tailored to match the wiring space; the LSI chip is area-limited because of yield, and interconnections must be performed either on chip multilayers or off the chip. Multilayers are proving to be difficult in production a t the two-layer level; off-chip wiring would negate some of the attractiveness of LSI. Paradoxically, LSI incurs this practical limitation on internal interconnects at about the integration level where it becomes attractive from a circuit-to-I/o pad ratio standpoint. Power density in high performance applications will range up to several watts per square inch on the substrate. The state of the pilotproduction art in high-speed chips is. around 1.5 nsec and has been realized with current mode logic circuits operating at 40-50 mW. It appears that circuit power in this speed range may eventually be reduced by a factor of two by taking advantage of several techniques which are applicable when the designer can be assured that the source and load circuits are on the same LSI chip. Nevertheless, total dissipation for a 50-gate chip still approaches 2 W, taking into account the necessity for off-chipdrivers. Evenif conventionalsmall chipsare used,thepackageddelay realizable with 1.5-2.0 nsec circuits, namely, 4-5 nsec, requires on the order of 20-40 circuits/sqin. and 1.0-1.5 W/sq in. Althoughseveral watts are comparable to or less than the power density of power transistors, it has not been demonstrated that this level will permit LSI reliability. Heat dissipation does not appear to be a serious limitation for bipolar circuits operating slower than 30 nsec. Metal-oxide semiconductor circuits can be operated at extremely low power levels; whereas clocking power in large MOS circuits can be substantial, the bulkof thedissipation occurs a t the clock source which can be handled on a special chip.

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Two generic methods of replacing flying wire leads with potentially more reliabk and economic bonds, namely, (1) flipchips (face-down mounted chips) with bumps or balls and (2) beam leads, are currently being used in IC production and development and will presumably be considered for use with LSI. Beam leads, and possibly flipchips, will also provide a higher linear pad density than is available with flying wire bonds. A developmental 14-bump chip is shown in Fig. 4. Figure 5 illustrates a facedown chip mounted on a ceramic substrate; the 14 bumps are in contact with screen-printed conductor fingers which in turn are bonded directly to the external leads of the package. Adaptation of bunip or ball ffipchip tcchniques to multipad ICS and LSI chips is not nectlssarily a straightforward extension of earlier efforts with three-ball discrete transistor chips [ 1 5 ] . Whereas three bumps are sufficient to define a mounting plane, reliable bonding a t additional bumps requires greater dimensional control and t8heuse of solder reflow or ultrasonic

FIG.4. A developmental 14-bump flipchip (Sperry Itand Corp.).

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bonding techniques which can, in effect, inherently serve to overcome the remaining small alignment tolerances. The conventional face-up mounted chip with flying leads uses the mounting substrate or carrier as an effective heat sink. Since the thermal conductance of the bumps does not appear to be equal to that of conventional mountings, it appears that new heat-sinking methods will have to be developed before flipchip

FIG.5. Developmental face-down chip mounted on ceramic substrate (Sperry Rand Corp.).

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technology will have widespread applicability to the inherently higher power LSI chips. A type of multichip packaging which is at least applicable to moderate chip power levels is shown in Fig. 6 [a]]. The exploratory assembly, developed by Philco-Ford Xcroelectronics, consists of 10 face-down ~

FIG.6. Multichip packRge with face-down chips (courtesy of Philco-Ford Corporation, Microelectronics Div.).

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chips bonded to a 0.3 x 0.6 in. passive silicon interconnection substrate. The interconnection substrate can be fabricated with the same technology used to fabricate the active silicon chips, including the use of multilayers. The silicon substrate further provides the flipchips with a matched expansion coefficient. The chips shown in Fig. 6 are further described in the section on MOS circuits. Gold beam leads, pioneered by Lepselter a t Bell Telephone Laboratories [42],are relatively thick ( - 12 p ) structures which extend beyond the edges of the silicon chip as shown in Fig. 7. The beams are electroplated on the wafer with precise photomasking and etching techniques; the highly ductile gold structure makes a flexible lead which can readily conform to differential thermal expansion with other materials. The metallurgy involved in the batch fabrication of the beams, including the use of a silicon nitride layer as a barrier against contamination from metallic ions in the atmosphere, provides a highly reliable self-sealing hermetic structure which does not require the usual relatively expensive

FIG.7. Chip with beam leads (courtesy of Bell Telephone Laboratories, Inc.)

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vacuum-tight mechanical package. The precisely formed beams are compatible with precision thin-film substrate interconnections which can provide more than an order of magnitude improvement in surface density over thick film interconnects. The beams can be placed and bonded on extremely close 2.5 mil centers [31]. The gold-gold mating surfaces between the beams and the substrate metal provide highly reliable contacts. One of the earlier arguments against beam leads related to the area wasted by the beams on the silicon wafer. Whereas there is undoubtedly an element of waste, the argument can be partly countered by observing that (1) the percentage of the wafer wasted becomes smaller as the chip becomes larger, and ( 2 )a t the other end of the scale, precision fabrication permits more beanis to be formed on the periphery of a small chip than with other bonding methods. (An example upholding this point is illustrated in the section on LSI memories.) Since the dimensions used in bump or conventional flying wire/pad technology do not appear to permit more leads, i t seems that the apparent wasted area is, in practice, offset by the attributes of fine-line precision fabrication. A second and possibly controversial rationale for ignoring area loss, if any, relates to the notion that the system manufacturer might be willing to pay for the loss if it is accompanied by a new technology that will simplify packaging problems and cost. 4. Economic Considerations

One of the earliest yield models used in integrated circuit cost studies assumed that each circuit component had a given yield loss resulting from defects, and that monolithic circuit yield was accordingly the product of the individual component yields. I n effect this model imposed a uniform defect density over the circuit, the wafer, and from wafer to wafcr. I t proved unduly pessimistic, and more reasonable models with nonuniform defect densities because of random and nonrandom causes were subsequently proposed [54, 711. Roughly speaking, the original model tended to predict negligible yield for a chip of, say, 60 mils square or larger. whersas the later models correctly indicate that large nondefective chips can be found at least somewhere on the wafer. Whereas best yields today are a t the 15-20 mils square discrete transistor chip level, very low cost ICS can be obtained on a 30-35 mil-square die, and 50-60 mil dice with 14 pads and an increased number of gates have already provcd to be economically attractive. Although hard-core yield and chip design data are generally not disclosed by semiconductor organizations, a study by Bilous et al. [4] to determine optimum chip design for high speed-( 2.9 nsec propagation

-

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191

delay) current-mode logic cites yield data and defines a figure of merit as the product of yield, circuits per chip, and chips per wafer. They show that the figure of merit peaks at a chip size of 60 x 60 mils; the yield factor dominates for larger chips, and the area required for pads controls chip size for small chips with less than eight circuits. About 300 square mils is allotted to each circuit, and a minimum tolerance of 0.2 mils is used; a maximum of 12 circuits and 24 terminals is realizable in the optimum chip. Projections that 10,000square mil chips will eventually be competitive with small chips on a cost per function basis appear reasonable. Estimates of this type are based on yield evidence available on currently fabricated wafers, arid on some admittedly hazardous extrapolations of existing economics and technology into the future. : A 2 in. wafer of 3 x 1 0 6 square mils contains roughly two hundred and fifty 10,000 square mil chips. Assuming for illustration a 6% yield, 15 good chips are obtained. Current factory costs for complete wafer processing appear to be around $20; costs per chip prior to testing and packaging are accordingly $1.30. A 150-square-mil gate, somewhat smaller than in current use, IS quite feasible for near-term production; assuming 85% useful gate area per chip, 56 gates per chip are realized. Ignoring the logic design and partitioning difficulties in utilizing all gates 011a chip, the fabrication cost is therefore on the order of 2.5 cents per gate before dicing. Testing and packaging costs are considerably less certain; assuming the two together add another 100-200%, the manufacturing cost would be from five to eight cents per gate, a figure considerably less than present costs. More significant, the manufacturing cost to fabricate the one-chip equivalent of a 56-gate PC card (e.g., $3.00-$4.50 neglecting third level packaging) would be less than current PC card costs: Even more dramatic cost reductions are conceivable within the next decade if the illustrative yield figure proves to be conservative, a notion that becomes plausible with the recognition that even the modern semiconductor plants of today have just scratched the surface of automated processing and production line control techniques.

There are a number of open questions in this simplified picture. On the positive side, there is considerable research and development activity today in yield enhancement programs, and an increase in the level of automation in wafer handling and processing can be expected. On the negative side, there are heavy engineering design costs, volume problems. and part number problems. Regardless whether the system manufacturer supplies his own chips or goes to an external semiconductor supplier, substantial capital and engineering expenses related to the hardware and software aspects of automated design will be incurred and be reflected in the final cost. Mask layout and fabrication costs, if not spread over a sufficiently large volume base, will add appreciably to the $3.00-4.50 chip cost projected above. It is interesting t o note that many if not practically all early versions of LSI chips have been priced by the semiconductor industry to

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be well above those of corresponding inipleiiirntatioiis in conventional chip and packaging technology (several forms of rneiiiory chips appear t o be exceptions). \\’hereas the high prices undoubtedly result from amortization of research and development costs, manufacturing start-up costs. and the usual low early yield which seerns t o characterize many complex processes. it is possible t h a t long-range prices of LSI chips will not gosubstantially under those of conuentioi~altechnology unless major new elements of economic motivation materialize. At the low cost end of the scale, the improbability of reaching a n average cost of eight cchnts per gate should also be noted: Paraphrasing a n observationof L. C. Hoblos, 50.000 computers per year with a n average of 20,000 packaged gates each would onl>- provide the semiconductor industry with a slender rweniie in the order of several hnndred million dollars. The increaw in the level of engineering design does not really confront the systrni manufacturer with a n altogethsr new situation since he is already accnstomccl t o providing automated routines for partitioning, assignment, l a j oat. and simulation currently i w d t o support PC card nianufactnre. On the other hand. assumption of the design role by the independrnt semiconductor supplier might result in substantial new eleriirnts of cost. Regardless of which groul) iint1ertakt.s the LSI chip design. a major increase i n logic simulation activity will h>rcquirtd a t the chip level t o insure correctness of design : this is partic*ularly critical h c a u s e of the chnngc or turnaround problein i n r x . Perhaps the major new clement s of dehigii cost are tliosc related t o thc rather forinidable p r o t h n of specifying chip test and the generall\- nioi~siitvolved interface bet\\ t w i part su1)plier and user. Testing third geiwration cards is a comparatix-cly hiniple matter since all piecc parts a r c iridividually and independently tcsted before assenihlj-. The I)rcictical dctcwiiination of a sintal)ltL tvst for coiiiytles sequential w t n m.lis has thiis fiw proved to be dificiilt and costly in terms of inac~hinetimr. Thf, change 1)rohleni is particularly perplexing. and it is lacking in a suficient nu nil^^ of good proposals for its soliltion. If a changv is requircd in the carly development phase of a n LSI niachine program, redesign costs w i l l be incurrtd; t ~ l i e t h e ror not there will he a schedule s l i p p a p clelwids on thc prograni critical path. H o ~ T ( T ,during thc miwhirit. tt’ht phase. current practice is t o install a temporary fix within iniittttcs. posbihlj. hours. If the need t o niakc a fix occiirs during t m t , both slippage and redesign costs \vill accrue: a htring of repeated fix cyclrs would bc intolerable. -A good discussion of t hc design-redesign cycle has bctw given by Smith arid S o t z [76j. The part number problem can be illustrated with refwerice to the prowssor in a large-scale third generation system. ‘I’hr. logic of a macliirte in this class niight typically require on the order of 18,000 OR-inverter

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(NOR) gates or equivalent. Assuming a maximum 36-gate chip, the average chip might carry about 30 gates, resulting in a total requirement of 600 unique part numbers. As for volume, the expected market potential for the large-scale machine over the next 4-6-year period appears to be numbered in the many hundreds or low thousands. The volume could increase considerably depending upon the growth of new innovations such as file-oriented systems, and various new market areas such as the utility field which are best suited to the large machine. Assuming our hypothetical processor makes a sizable penetration into this market, we see that about 1000 parts of each of 600 part numbers might be required. On the other hand, an equivalent third generation machine might have 10 semiconductor part numbers and an average of 600 parts per part number. I n terms of the traditional high-volume, low unit-cost practices of semiconductor manufacturing, the transition is quite unfavorable. It is too early to assess the degree and manner in which the semiconductor and system industries will adjust to this and other economic aspects of LSI. The example of the hypothetical large-scale machine is particularly significant since this is one of the few areas where LSI offers hope for improving performance. Volume requirements for classes of systems and subsystems other than the processor are more encouraging. Smaller processors have a much larger volume base and more than an order of magnitude fewer part numbers. Terminal equipment is undergoing a very rapid growth; comparatively few part numbers are required. Low [45] has cited the example of a typical airline reservation system: whereas the duplex processors require about 23,000 circuits, the terminals use over 290,000 circuits. Assuming 100 circuit chips, about four part numbers are required for the’latter. Part numbers for I/O controllers are as high as for a small processor but the part volume is growing steadily. Memory part numbers are low; the volume could become very large depending upon the outcome of its formidable competition with magnetics. One technique which should contribute in some measure to the solution of the design, change, and part number problems lies in the use of general-purpose or master chips [60] discussed in the next section; these chips are identical in all stages of fabrication except for the final metallization step in which the required logic function is defined. Hobbs [34], Flynn [ 2 7 ] , and Rice [68] have pointed out that silicon costs comprise only a very small fraction of the cost-of-ownership of digital computers. Rice indicates that the cost of the IBM 360150 installation a t Iowa State University including all auxiliary equipment, manpower, and overhead is $109,600 per month. Programming costs account for $40,000 or 36.50/,, installation operation costs $36,000 or 33%, and

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$33, 600 or 30.5:/, is applied to machine rental. It is further estimated that about one-third of the rental is for hardware and software, one-third is for sales and service, and one-third is for administrative overhead and profit. The fraction of the rental attributable to hardware is about 5.8%, and Rice estimates the silicon portion of the hardware to be 2%. The present writer does not concur with this implicit estimate of the rental attributable to software and believes it should be almost an order of magnitude lower. In any event, i t appears that the logic power of systems could be considerably enhanced without adversely affecting the cost to the user. This point will be briefly discussed in a subsequent section. 5. Interconnection Strategies

Yield considerations give rise to a spectrum of wafer utilization strategies with Fixed Interconnection Pattern ( FIP) and Discretionary Wiring (DW) currently given primary and limited consideration, respectively. Briefly, the FIP strategy involves using the same interconnection masking pattern on all the chips in a wafer, regardless of fault locations. The DW strategy does not make use of a chip structure. Instead, the entire wafer is first analyzed for faults; a specialized masking pattern is then produced which bypasses the faulty gates and implements the required function. 5.1 Fixed Interconnection Patterns

The fixed interconnection pattern is based on two premises: (1) reasonable yields can soon be expected for high device density chips of approximately 60- I 00 mils square. with larger sizes economically feasible within fire years: and ( 2 ) device densities considerably greater than in current use should soon be feasible because of improvements in tolerances and general processing. thus potentially insuring near-term acceptance of the strategy with only a moderate increase in chip size. The fixed interextension of current connection pattern is a corice~~tualJystrai~~itfor~~ard practice: masks are prepared in advance. the wafer is processed and diced. and the chips are operationally tested. The strategy requires that very small geometry devices must be used to attain a high level of circuit complexity. A serious problem arises in testing PIP chips. namely. that tcst data cannot be obtained from the chip prior to final metallization. This is because of inherent high packing efficiency of the PIP strategy which leads to the elimination of pad space for gates within the interior of the

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chip. Thus the test procedure must be deferred until the 110 pads are metallized a t the completion of wafer processing, and a pad-limited functional test must be provided; as noted earlier, fault detection with a limited number of terminals is vastly more complex than the PC card test philosophy used in third generation systems. Fault detection reduces to the problem of finding a manageable sequence of input test patterns that will guarantee to some level of confidence that the chip is nondefective. A fault table can be constructed by providing a column for each conceivable fault, and a number of rows equal to the product of the number of input patterns times the number of internal states. A one is entered in the table if a particular fault can be detected by a specified input and internal pattern; a zero otherwise. I n principle, a minimal test sequence can be determined by selecting a minimal set of rows which cover all ones. Performing this in practice with chips containing, say, 10 or more storage elements and 30 or more input pins is clearly difficult. Much of the published work on testing is on problem formulation rather than on practical results ; several pertinent studies are indicated in the references [Z, 75,481. Testing is further complicated since (1) failures are not limited to gates, and the width of the table must be increased accordingly; (2) dynamic testing with varying load, temperature, etc., is desired; and (3) the chip manufacturer and user must jointly determine a confidence level for the test. The fixed interconnection pattern can be subdivided into muster and custom layout strategies. Master embodies the notion of a generalpurpose chip which is completely prediffused and then inventoried, if desired, without interconnections. A specific function required by a user is implemented merely by fabricating and applying the final interconnect masks. As in most general-purpose schemes, there is a disadvantage; in this case it is moderately inefficient use of silicon area, implying nonoptimization for high volume applications. Custom layouts are tailored precisely for the function a t hand, thereby achieving optimum area utilization a t the expense of generating an efficient and specialized complete mask set for each function. Custom is best suited for high volume applications which can support high engineering layout and mask design costs. An analysis of layout efficiencies by Notz et ul. indicates that custom achieves about twice the area utilization of master a t the 50-100 circuits per chip level, with the ratio increasing at larger integration levels [5Y]. An example of a master chip is the 80-gate 110s chip produced by Fairchild Semiconductor and shown in Fig. S . Figure X u and 8b shows an 80 x 80 mil chip prior to and after mt.talIization, respectively: each of the five major vertical columns contains the equivalent of I6 threeinput gates. The chip uses two-layer metal. The first layer defines the

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gates and provides limited gate-to-gate interconnections; the second level completes the interconnections. Thus, three specialized masks are used: one for insulation cuts and two for the first and second layers of metal. The interconnection widths and via holes are approximately 0.4-0.5 mil; relatively spacious x and y wiring corridors of about 20 wires per cell row and column are used, presumably t o satisfy a wide range of

la) FIG.8. Example o f mastcr 310schip (a) prior t o mctallization; (1)) aftcr mttallization (coiirtrsy of Fairchild Semiconductor, A Division of Fairchild Camera and Irlstrumcllt Corp.).

user applications. For more restricted usage. practice indicates that corridors of about 6-8 wires are able to handle a large fraction of the wiring requirements a t the 80-gate level. An early custom chip designed by the Motorola Semiconductor Products Division is shown in Fig. 9. The 120 x 120 mil chip contains

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16 ultra-high-speed content-addressable memory bits based on current mode circuits with 2 x 0.2 mil emitter geometry. The chip is made up of 2 x 2 arrays of 4 bit cells; each 2 x 2 is 60 mils square and contains 131 devices; the custom layout problems are solved at the bit level and replicated. Four metal layers are used: the first two intraconnect within the 2 x 2’s, and the upper two interconnect between 2 x 2’s.

(b) FIG.8b.

5.2 Discretionary Wiring Since fault patterns vary from wafer to wafer, D W has the drawback that functionally identical arrays will in general require different interconnect mask patterns. The key problem is the critical dependence on data processing for mask layout, albeit off-line, and a host of other production control routines per copy. Further, use of a unique mask implies

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a relatively slow production process for a given capital investment. On the other hand, the inherent suit.ability of conventional device geometries to DW can be construed as an advantage, albeit somewhat ephemeral ; the implication is that DW has the potential for implementing large arrays at an early date. Although advanced techniques for inspecting gates may eventually be developed, the only currently acceptable method involves mechanical probing of each elementary cell, i.e., gate and storage element. As noted,

FIG. 9. Custom chip containing 16 ultra-high-spced content-addressable rnernory (courtesy of Mtitorola Semicoiidiictor Products, Inc.)

probing requires area-consuming pads of the order of 2-3 mils, resulting in a relatively luw circuit density in the array. The area required by the pads sets a lower limit on cell size; a Diode Transistor Logic (DTL) gate currently in high volume production, for example, requires an area ( - 200 square mils) which is not much larger than the area of the pads and leads which service it. Possibly the most serious drawback to DW is that considerable wafer processing is required after the gate probing step, and odds on the creation of at least one post-probe fault appear to be high; no data have vet been presented to refute this self-limiting point. Discretionary wiring techniques have been described by workers a t

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Texas Instruments and International Business Machines [ZS, 411.Texas Instruments has reported studies on a research vehicle involving a several thousand gate general-purpose military computer, the largest known attempt at logic LSI thus far, at least in terms of gate count. Typically, several hundred gates or equivalent are assigned to a 14 in. wafer containing about 1000 gates. The several hundred gate arrays make use of two metal and two insulation masks. High-speed mask-making techniques are required to produce a set of four masks per array and keep up with foreseeable high production rates. One technique under development uses 2:l or 1 : l contact printing generated by a high-resolution Cathode Ray Tube (CRT) with a fiber optic faceplate, and another uses projection printing from a conventional high resolution faceplate; a n additional reduction step is needed if 2 : 1 printing is used to simplify the requirements on the CRT. The coarse line widths of the order of one mil available with CRT 1 : 1 printing are reasonably well matched to upper level metal requirements in DW. An alternate approach to the CRT makes use of a light beam impinging directly on the wafer which in turn is carried on an x-y table positioned by a stepping motor. This method provides very high precision and repeatability and is free from the various distortions found in CRT systems; however, it is several orders of magnitude slower than a CRT (but considerably less expensive). Studies indicate the CRT mask-making portion of the over-all system has the potential of supplying a complete mask set every 40 sec; this is generally longer than the time that might be required by a UNIVACQ 1108, say, to process the placement and wiring algorithms. Clearly, a detailed system analysis covering all bookkeeping and production line aspects must eventually be made before a meaningful DW throughput rate, and hence economic feasibility, can be established. Discretionary wiring may have potential advantages over FIP which seem to have not yet been exploited. One concerns the difficulty of testing sequential circuits already noted. The comparative grossness of the dimensions used in DW suggests the possibility that a considerable simplification in fault detection could be achieved if, at some sacrifice in wiring density, special interior test pads could be carried up to the top layer for subsequent mechanical probing. A second potential advantage is that for many years in the future DW may be capable of providing an optimal approach to the severe problems of nanosecond LSI. Depending on yield statistics and the difficulty posed by the self-limiting effect cited earlier, it may be possible to obtain many hundreds of good gates on a wafer; this is substantially in excess of the most optimistic projections for FIP, and provides the basis for the large-scale partitioning @

Registered trademark of the Sperry Rand Corporation.

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L. M. SPANDORFER

needed at the 1-nsec level. I n addition. the comparatively high part number and low ~-olumeconsideration for a large-scale system with rianosecorid technology are not izecessarily iucorn1)atible with the economics of D W. An example of a DIV layout used by Texas Instruments for exploiting a complete wafer is shoa-n in Figs. 10 and 11. The wafer contains a memory subsysteiii consisting of 38-10 bits a n d 240 word drivers and a second level decoder [19, 871. The organization is flexible and provides TADDRESS INPUTS

2nd LEVEL DECODE GATES AND WORD DRIVES 16 BIT COLUMNS 0

16 BIT COLUMNS

0

16 BIT COLUMNS

16 BIT COLUMNS

-

BIT

MI WORDS

a inaxiniiini of. SRJ . 60 n.ords of 6-k 1)its each on a hypothetically perfect n-afbr. Figure 10 4zon-s the organization of the memory on the wafer, and 121g. I 1 contams a map of the faulty cells on a particular w-afer. The word ciircctioii is divided into four colunzns or .vr-ord groups of 16 bits c3acli. studies 11,3\-(. indicated that a t least 13 of the 16 bits in a group shottld 1)e noiitlcfectiw. thus enabling a. system \\ ord length of 5 2 bits. Bit c e l l size i y a h t i t 1-45 squarc mils \\ hieh is snficiently large to allow 1 i a i t o all pads. coii,scquci>tlJ-.only d sinplt~discretionary mc>tsl layer I \ rt.quirc.tl and i:, uwd t o form tlie bit liiws. If a given bit crll is ckfwtive, it i \ not coiitiwtr.d t o the I)it liiic. Bit rtyistratioii is niaintaiized b y jogotno t h r x othcrn ise straight bit line t o a right or a left iicipliboring hit cc~ll.A typical srray inap slzon-inp good and liad bit cells and a dwc.wtionar:\- m n s k drawing with hit lint, jogging arc sliown in Fig. 11 ;

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the bit lines are horizontally directed. If 13 good bits cannot be found within a 16-bit group, the group is not used and group jogging is employed instead. Alternate approaches to wiring a memorylike array without the need

ACTIVE MEMORY SLICE M A P

CELL YIELD = 87.4 O/o WORD Y I E L D = 6 9 . 5 %

(b)

FIG.1 1 . (a) Illustrative map of wafer yield, and ( b ) discretionary wiring mask (courtesy of Texas Instruments, Inc.).

of topologically jogging the bit line have been examined [77]. Although it has been shown that techniques such as binary erasure error correcting codes and logic deskewing circuits are applicable and permit the use

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of topologically straight bit lines, the trade-off is generally made a t the expense of reduced throughput capability and added circuit complexity.

5.3

Special Studies

Workers in various aspects of switching theory have occasionally turned their attention to certain issues of LSI such as the attributes of simple wiring patterns, wire layer minimization, and universal logic blocks. One activity has involved a study of cellular arrays by Minnick and co-workers [50, 51, 521 and Canaday [7]. An early and primitive form of cellular structure is the two-dimensional array shown in Fig. 12. The FUNCTIONS FOR THE CUTPOINT CELL INDEX1 a b c d

I

2

~~

0

0000

1

1

0001 0010

Y' x'ty'

2 3 4

0011

x' y*

0100

xty

5

0101

XY'

6 7

0110 0111

x + y

F

1101

x'=S,y'=R

0

FIQ.12. Cellular logic array and cutpoint notation.

study of cellular arrays presupposes that simple wiring patterns on an chip will be less costly than conventional irregular patterns; simple wiring patterns are then postulated (the one shown in Fig. 12 is a particularly simple and early prototype), and the logic power of the resultant structures are studied. Each cell can be set to any one of 16 functions of the two input variables 5 and y (six cell functions are LSI

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actually sufficient to implement all combinational switching functions [50] or an R-s asynchronous set-reset flipflop). This structure provides an arbitrary n-variable combinational switching function with an array n 1 cells high and no more than 2n-2 cells wide. A number of elegant synthesis techniques have been devised for specifying the function of each cell and reducing the size of the array, and interconnection patterns somewhat more extensive than the simple rectangular nearest neighbor pattern of Fig. 12 have been introduced [51]. An extensive survey of cdlular logic work has recently appeared [as]. Each cell in the early studies was set to the desired function during the regular masking procedure by appropriate metallization of its so-called cutpoints. Since the chip function thus formed incurs the possible disadvantage of being rigidly and permanently fixed, flexible programmable arrays were subsequently proposed in which the precise chip function need not be fully committed in hard wiring during manufacturing but instead could be specified later by an appropriate set of control signals. An early suggestion for achieving programmability used photo-conductive cutpoint switches, removable photomasks, and a light source. A more recent proposal [77] employs a special 2 0 memorylike control array superimposed on the logic array; the role of the control array is to store the cutpoint data and thus provide a first-step solution to the change or " yellow-wire '' problem. Since speed requirements on the control array are negligible, it could conceivably be implemented with low power MOS devices; the logic array could use higher performance bipolar circuits, if needed. The noncritical loading or input rate imposed on the control array results in a minimal pin requirement for entering control data onto the chip. Although intermixing MOS and bipolar circuits poses problems which have only been partially solved, recent progress by Price [67] and Yu et al. [92] in combining the technologies is encouraging. An important approach to circumventing dependence on a volatile control array lies in the use of a device such as the variable threshold field effect memory element to be described later in the memory section. I n principle, such devices constitute a near-ideal control array element with retpect to minimum area and power requirements. Ignoring the inefficiencies of cellular logic for the moment, the manufacturing advantages which might accrue in its use are not insignificant. The highly regular and simple interconnection patterns called for in cellular arrays are presumably simple to fabricate. The need t o solve wire-routing algorithms and perform complex layouts on silicon is eliniinated. Chip specialization by cutpoints is done at precisely specified interconnect points rather than by irregular interconnect lines. A maximum of two wiring layers is required. The trade-offs for these

+

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features. however, are in gcneral severe; they arc ( 1 ) excess silicon area, possibly with an excessively rectangular or nonsquare form factor, and ( 2 ) an increase in the number of cells through which a signal must propagate in comparison with conventional logic not possessing stringent interconiiect pattern limitations. Both trade-offs arise because of limited ceil fan-in. fan-out, and pattern rclstrictions. The first trade-off might eventuallj- diminish slightl) in importance but will always remain an important competitiw isviie; the second trade-off, involving propagation dclay. and I)ossibly rciliability. appears unlikely to diminish in importanct., although iiianj- applications exist n-htw specLd is not critical. Current practice has sidcstvpped t hc cellular logic precepts and is instead forging ahcad with irrcgirlar intcrconnects and multilayer technol0,a- = Iiich provide minimal area and delay paramc%rrs. Whereas currcmt direct ions will undoultedlj- succeed by some measure becausc of thr heavy investment committmcnt , it should be noted that one of thc important dcxterents to mannfact wing success today, namely, lack of sufficient sntoniat ion. would be considerably Ivsscnedwi t h cellular logic. \\-ark hiis also hwi carried out on varions asp s of the multilayer problcins arising in large-scale integrated circuits. One study showed that given a logic function it is always possible to synthesize iri a way such that no logic line crossovers are requirtad [79]; power lines are not considered to be logic lilies and are treated separately. The result tends to involve a worse case layout restriction in the sense that logic lines in effect are not permitted to cross over or under gates but instclad are morc or less constrained to lie in the intergate corridors. Single lajer logic can bc achieved with no additional input pins; each inpiit and output variable need only make one appearance on thc chip periphery. Similar to cellular logic. however. single layer logic generally requires a hear?; sacrifice of silicon area and logic propagation levels. Other studic,s have concentrated on the nonplanarity of a given implcnientation. For. examlde. an algorithm for detecting whether a given graph is planar has been presented and programmed bj- Fisher and Wing [.XI. 'I'hc algorithni is expressed in terms of a graph incidence matrix; if the graph is nonplanar, thc algorithm identifies a submatrix which is planar. The program can bc iterated thereby generating a sequence of submatrices which include a11 vertices and edges of the graph. The special problems of associating a graph vertex with a chip or a circuit arc' describtd in \I'eindling and Golomb 1901. where the difficiilty in choosing subgraphs rrsulting in a niinimal number of planes is discussed. --Is illustratcd i n the section on packaging. there is little compelling reason to believe that the relative dimensions of the circuits and wiring on N chip will Icad to potentially fexvrr wiring layers for LSI in comparim n with earlier technology.

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Interest in standard or universal logic chips has existed from the beginning. The problem, however, is that universality may not be particularly efficient from a silicon area or I/O pin terminal viewpoint a t a level much above the simple NOR gate. Functional groupings such as decoders, adders, and register cells are useful and can be readily built, but are far from universal. A number of studies on universal logic modules have been carried out; an early paper by Earle [ZU]is particularly worthy of mention. A more recent study has been described by Elspas et al. [Zl];using a model similar to one introduced earlier by Dunham [18, 171, it is desired to attain universal module behavior by being able to implement any function of n variables in a module containing m input terminals, m > n. Function selection is performed by connecting the n variables from the outside to the appropriate subset of the m terminals; some of the unconnected m terminals can be biased to fixed voltages representing constants 0 and 1. In the study by Elspas et al., the complexity of the module is measured by the number of input terminals; the objectives were to develop techniques for the design of the module logic and to minimize the number of required terminals. Several constructive techniques for synthesizing n-variable universal logic modules were reported, along with upper and lower bounds on m as a function of n ; a strategy for searching for universal functions with a minimal or near minimal m was also described. The best result of the search was reported to be the discovery of an eight-input function universal in four variables. Minimization of input terminals was the sole cost criteria and issues such as propagation delay or logic levels encountered in passing through the universal logic module were not examined. 6. Bipolar Circuits

Many basic considerations are involved in comparing integrated versions of various digital circuits used in second and third generation computers. Among these are ( 1 ) speed versus power, (2) required silicon area, (3) current gain, (4)resistor tolerances, (5) fan-in, fan-out capability, (6) noise immunity, and ( 7 ) wired OR operation, i.e., ability to tie outputs directly together to perform a second level of logic. These considerations make generalization within one structure difficult, much less comparison over several circuits. The problem is compounded since each circuit can generally be shown superior to ail other circuits in at least one or more important attributes. Relatively little solid documentation exists in which circuits are carefully compared under the same conditions; several comparative studies have been made [ 4 4 , 4 7 , 781. The ensuing discussion will touch on broad aspects of the various

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circuit t,ypes. Typical propagation delays and dissipations cited are for roughly similar fabrication tolerances and operating conditions; trends rather than precise engineering data are presented. Preoccupation with Current Mode Logic (CML)is because of (1)its emergence as the leader in the speed race, ( 2 ) its recently achieved third generation computer production status with moderate geometries (0.3-0.5 mil) after years of laboratory hiatus, and ( 3 ) its potential as an ultra-high-speed (0.3-2.0 nsec) LSI gate. 6.1 Saturating Circuits

Some of the important second and third generation saturating comput,er circuits are shown in Fig. 13. The transistors in the gates shown are not constrained from entering the saturation region and as a result

.+J--.

iNEGATIVE LOGIC1

I$ *+yfX !3G RTL

(POSITIVE LOGIC1

D

:

c

= DTL

d

Wired OR

+E P

+E

obc

Lou Level TTL High Level T T L

FIG.13. Bipolar saturating logic circuits.

incur the well-known storage-time component of propagation delay. Roughly speaking, a transistor enters saturation when it has ample baseemitter drive but comparatively little collector current. In this condition, the collector voltage falls below the base voltage causing forward conduction of the base collector junction, and excess time is required to

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remove the resultant stored charges in the base when the transistor is eventually turned off. Saturating circuits appear to be limited to a turnoff delay of 3-5 nsec. Practical approaches to minimizing storage include the use of antisaturation feedback diodes and substrate-controlled saturation transistors [73] which limit base overdrive when the collector base junction starts to conduct forward current; gold doping is frequently used to reduce stored carrier lifetime. Resistor Transistor Logic (RTL) provides a simple structure and consequently was one of the earliest integrated circuits in production. It represents a slight modification of the Direct Coupled Transistor Lpgic (DCTL),' the first systematic logic structure devised to capitalize on the iterative switching capability of transistors. Typical speeds obtained with monolithic RTL circuits are in the 15-30 nsec range, with power dissipation on the order of 20 mW. The RTL gate performs the NAND function for negative logic, i.e., where binary 1 is interpreted as a low voltage signal; the NOR function is obtained for positive logic where a high voltage level is taken t o mean binary 0. Since RTL normally operates with gate collectors tied together, the two level AND-OR-NOT or wired OR function cannot be obtained by tying collectors of several gates. Discrete transistor RTL circuits using beam lead technology to reduce parasitic capacitances have been reported which attain propagation delays below 5 nsec at 23 mW for a fan-out of unity [43]. Diode Transistor Logic is another holdover from second generation discrete component circuitry; it provides typically 10-20 nsec propagation delay at 20-30 mW and can be designed to give good noise margins. It performs the NAND function for positive logic. Higher power DTL circuits are in production with propagation delays down to about 5 nsec [22]. Tying together outputs of several gates permits an AND-ORINVERT operation. The symbol for the wired OR outputs is shown in Fig. 13; tying outputs can be used to reduce part numbers and reduce input wiring as well as to provide two levels of logic. Its use in a logic chain, aside from packaging considerations, is a trade-off with the availability of input terminals on the succeeding logic stage. Transistor-Transistor Logic (TTL)is derived from DTL; the multiple emitter device is used as a transistor, replacing the input and voltagetranslation diode functions. It also acts as a NAND gate for positive logic. Transistor-transistor logic appears to embody one of the first really new circuit ideas of the integrated circuit era. With discrete components, designers tended to use relatively inexpensive resistors and diodes wherever possible and minimize transistor count within a gate; early 1 As a historical footnote, it should be noted that one of the editors (MR) was a oo-creatorof DCTL.

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DCTL circuits with one transistor per fan-in were something of an exception, as were the npn and pnp current mode circuits used in earlier computers [GI. integrated circuits upset the earlier economic balance on the use of active and passive elements, and designers began to exploit transistor properties on a large scale. The TTL input circuit is one such example; another is the use of an emitter follower to replace a voltage shift diode in the DTL input network, thereby providing greater circuit gain bandwidth. Low. level TTL uses less silicon area than DTL on a component count basis. However. since TTL was developed as a natural competitor to DTL. a series emitter follower is sometimes used which provides a balanced output which in turn can drive the two transistors in the output or cascode stage. The cascode is used to insure a desirable low output impedance to drive capacitive loads for both positive and negative output transitions. These added components distinguish low level from high level TTL, and caiise the area requirements to be commensurate with DTL. Cascoded output-pair transistors have also been used in DTL configurations. In general, high level TTL provides a speed power improvement over DTL. with 10-15 nsec obtainable a t typically 13 mlV dissipation. Transistor-transistor logic circuits with 30-40 nsec delay and nominally 1 m1V dissipation are also in production. Despite the performance advantage of TTL and the nonsaturating circuits to be described below. it is worth noting that RTL and DTL, through speed'power and other trade-offs, are in use as sub 5-nsec gates in large-scale systems. Both TTL and DTL are currently being designed into LSI arrays. A TTL-compatible memory chip is described in a later section. Nevala [38] has described the elements of a DTL master chip currently in production a t Fairchild Semiconductor. The 80 x 110 niil chip contains 32 four input gates. and two level metal interconnects are provided. The function-defining interconnections and the number of I/o pads can be specified by the user. Fan-in can be increased or AND-OR-INVERT logic provided by borrowing gate diodes from neighboring circuits. Space is available for up to about 40-50 I!O pads. Relative speed 'power performance of the various logic families is dependent on the geometry of the transistors and other devices used. In particular, gain bandwidth is inversely proportional t o the horizontal emitter width and vertical base width. Small geometry devices not only provide high circuit performance but also imply more gates in a given chip area and therefore potentially lower cost per gate down to the point where photomasking resolution and alignment limits with visible light are reached. As an example of the performance improvement possible with more sophisticated device designs, small-geometry TTI, circuits currently in production have propagation delays of 5-6 nsec,

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and even faster saturating ultra-fine 0.1 mil geometry shallow-diffused transistors described by Spiegel [go] provide a n average unloaded delay of 2-3 nsec. 6.2 Nonsaturating Circuits

One approach to nonsaturating logic is through the use of emitter followers. Complementary Transistor Logic (CTL) [?'a]shown in Fig. 14 uses input p n p emitter followers to perform the AND function; the output is connected to the base of an n p n emitter follower which provides the OR. The n p n output can be tied to similar gates t o obtain the wired OR +E ?

I CTL

sum-of-products. Since dc compatability between successive emitter follower stages can be achieved without forward current in the base collector junctions, saturation is avoided, The emitter followers are operated both nonsaturated and class A , thus providing a fast AND-OR. A loss in dc voltage level is incurred going through the emitter followers, and a n inverter must eventually be included in the chain for voltage gain as well as for logic completeness. Although problems have arisen in obtaining high performance p n p and n p n devices on the same chip, the performance of the circuit and the ability to use maximum-duration rise and fall times for a given propagation delay are quite attractive features. Another method of constraining a transistor from entering saturation is through control of the emitter current and thereby control of the collector base voltage. Current mode logic shown in Fig. 15 contains this property as well as an unusual number of other important selfcompatible features [ 5 7 ] . For example, the current switch transistors Q1, Q Z stay out of saturation because their base emitter voltages and emitter currents are closely controlled. Close control comes about because ( 1 ) the base is driven by a low output impedance emitter follower of a preceding stage, and ( 2 ) the emitter current (and voltage) is

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controlled with a sufficiently large resistor R and large voltage E . While QI, say, is turning on, the impedance a t the common emitter node becomes low, thus providing a relatively low impedance loop for the buildup of input current. When Q3 finally turns off, or unclamps, the node impedance reverts to the larger value, preventing overdrive of &I into saturation. The nonsaturating emitter follower further serves as a low impedance output source for posit.ive- or negative-going output

11

-4

VREF

b

a

-E

CML

(NEGATIVE LOGIC)

ab

01

I -E

ab

f

' 6

-E Current Switch

FIG.15.

Currrnt mode logic circuit and current switch circuit.

transitions, and it also conveniently provides the desired voltage shift for interstage dc compatability. The complementary current switching action betw-een QI, Q Z, and Q 3 provides the basis for the NAND and AND functions at, the output. Current mode logic is reasonably independent of resistor tolerances provided ratios are properly maintained, an important factor in the use of diffused resistors. In addition, the low output impedance of the emitter follower makes it relatively difficult to couple capacitive noise into a CML input. The circuit is usually operated with a 0.8-V swing; additional margin against noise and saturation can be

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obtained if needed by placing level shift diodes in, say, the emitter follower base. One of the critical problems in CMI, design is the instability associated with emitter followers under various input and output impedance conditions. The optimum stabilization method for the faster monolithic circuits is not clear a t present; emitter stabilization capacitors have been used in 1.5 nsec discrete hybrid circuits [70]. Current mode logic circuits with 0.1 mil masking tolerances, micron diffusions, and 40-50 mW dissipation provide unloaded stage delays of 1.5-2.0 nsec and are currently in early production phases; reasonable chip yield is believed to exist at the 3-6 gate level. Availability of such chips provides a basis for a new round of high performance processors with unloaded circuit speeds two t o three times greater than in existing third generation systems. State-of-the-art in packaging technology should be able to provide a comparable improvement in the delay attributable to interconnections, resulting in a net stage delay around 3-5 nsec. As noted earlier, an increase in circuit density up to 20-40 circuits per square inch appears to be required, with dissipation in the range of 1-1.5 W per square inch. Dhaka [16]has described an advanced transistor design with 0.075 mil emitter base widths, shallow diffusions which enable collector junction depths of 3300 A, and cutoff frequencies over 6 GHz at a collector current of 10 mA. Transistors of this class have operated in current switch circuits (CML without emitter followers)as low as 220 picoseconds [91];simulation studies indicate that the circuit speed is limited by ft rather than by parasitics. An experimental transistor with 0.05 mil emitters has.been described by Luce [46] which achieves an ft greater than 3 GHz at an unusually low collector current in the 0.5-1.0 mA range. Current mode logic circuits incorporating these devices have shown a delay of about 0.5 nsec at a power dissipation of 10-15 mW. It is not clear a t this time that horizontal line widths less than one-tenth mil will provide sufficient yield without a breakthrough in processing technology. Production yield at even 0.7 nsec is an open question today. Variations on the basic CML structure have been devised to reduce power and area requirements to a level pokentially commensurate with LSI. One approach to power reduction is through the use of the current switch without t,heemitter follower [56,10];operation with small voltage swings ( 0.4 V ) is desirable to keep the transistor out of deep saturation and to provide dc compatability. Removal of complementary emitter followers typically reduces the circuit dissipation by more than 50%. Feedback arrangements which permit a reduction in dissipation have been described [33]. Five-niilliwatt dissipation has been achieved with N

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a low supply voltage (2.4 V), low signal swings ( 200 mV), and reduced speed (10-13 nsec). Nonfeedback reverse-CJIL circuits providing about 7 nsec a t 15 mW and 10 mW for 800 mV and 600 mV swings, respectively, have been reported by the same group. (It is not clear that CML providcs the best speed-power ratio a t these relatively large values of delay.) Reverse CXL involves interchanging input and output termirials such that the emitter follouer becomes the input stage, and the current switching transistor becomes the output. Its primary features, in comparison with conventional CXL, are a smaller input capacity since the Miller effect is reduced, and a reduced component count. I n addition to providing information on the design of low power, small area CML, the project reports describe the special design problems related to the interface circuits used to connect chip to chip. The reports further describe the optimization of area and dissipation on large two level metal CML master chips. Thirty-six gate chips using 288 transistors and requiring 175 x 175 mils have been fabricated and are in an early operational status; 72 gate chips with component packing five times more dense than the 36-gate chip are planned. One of the more advanced developments in 1 nsec LSI has been reported by Chen et al. [9].A three level metal master chip is used which contains up to 12 nsec range circuits in 60 x 60 mils; productionfeasible parameters (0.2mil emitter, 1 GHzft) and relatively high power circuits (50-80 mFY) are used. Seeds [72] suggested the possibility of production circuits a t 100 and 50 square mils in 1970 and 1974, respectively. Murphy and Glinski [Zrecently ] described an exploratory 10 square mil circuit (105 per square inch) which is believed to be the highest density yet reported. The computed value of delay is 4 nsec a t a power of 0.8 mW. The circuit uses a form of TTL with clever circuit and device innovations to keep the output transistor out of saturation and the iriverst slpha of the multiple emitter input gating transistor below a maximum value. Whereas this important development stresses innovations in device technology as an approach to LSI, much (but not all) of the work on basic LSI logic circuits appears to be directed a t the exploitation of a relatively large number of transistors using more-or-less conventional device techniques. Murphy and co-workers (see ref. [36]) also stressed device innovations in an interesting 25 square mil memory cell described in a subsequent section. Alt,hough important signal transmission issues such as cross talk and noise tolerance are apparently still in the open question category, it is worth noting that studies have been reported by Guckel and Brennan [29] that. in the worst case, indicated signal delay on silicon can be as high as 40-50 times the free space value. Experimental verification of this result is awaited.

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7. MOS Circuits

I n contrast with bipolar, MOS has a number of remarkable properties. Assuming equivalent masking tolerances, MOS transistor area requirements are about 3-5 times smaller than for a bipolar transistor, since neither isolation nor nested emitter base diffusions are required. The high input or gate resistance ( 1014-1016) permits voltage controlled operation without the need for input dc current. The high input and high source-to-drain OFF resistances permit the parasitic input node capacitance ( 0.3-0.5 picofarad in close-spaced layouts of the type possible in shift registers) to have important use as a storage element. The two-terminal resistance of the source-to-drain path provides a convenient method of implementing the pull-up resistor function, resulting in an area requirement about 100 times smaller than a diffused bipolar resistor of equal value. Metal-oxide semiconductor sheet resistivity ranges from 25 to 40 kilohms per square, and pull-up resistors of hundreds of thousands of ohms can be readily implemented. Although the pull-up resistor may have a sizable temperature coefficient, it is capable of tracking with the logic transistor. Finally, the transistor can function as a bilateral switch, permitting current flow in either direction. All of these features are advantageously employed in the circuit structures briefly described in t7hissection and in the later section on memory. Transit-time delays are negligible in MOS (1000 MHz operation is possible), and Resistance-Capacitance time constants constitute the primary speed limitation. The transistor is unable to supply a copious amount of current and thus has a particularly low transconductance or Gm (approximately ten t o several hundred micromhos for low level logic devices) which, if coupled with a high threshold voltage, provides a rather large propagation delay in contrast to bipolar transistors. The transconductance is proportional to the ratio of channel width to length; the latter is set by masking tolerances. Present state-of-the-art in clocked p-channel transistor performance (to be discussed below) appears to be in the 5-10 nsec range, with the actual delay being extremely sensitive t o interstage capacitance. To the writer’s knowledge, however, experiments on chain delay in close-spaced clocked or unclocked p-channel circuits have not been reported, leaving some uncertainty on attainable propagation speeds. The actual or potential improvement in p-channel speed is ostensibly due to the use of lower switching voltages, use of a thicker oxide which reduces parasitic interconnect capacitance, and smaller output junction capacitances by means of smaller devices geometries. However, Farina has pointed out that the geometries used in 1965 vintage shift registers which provided 100 kc rates are the same as those used in the more recent 10 Mc designs; he attributes the improveN

N

~

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ment, which includes a seven-fold reduction in circuit area and a twofold reduction in power dissipation, to advances in circuit techniques [23]. (Presumably the 10-JIc designs make use of the thick oxide technology.) Chain delays have been reported for complementary transistor pairs; Klein 1391 has measured 2-4 nsec stage delays for close-spaced pairs with unity fan-out. Unlike the single polarity transistor, complementary pairs can provide high speed in a ripple or dc logic mode, i.e., without clocking. The technology reported by Vadasz et ul. [85] depicted in Fig. 8 uses 0.3-0.4 mil channel lengths and is production feasible; it appears to be capable of providing a nonclocked propagation delay in the 30-50 nsec range on the chip. Threshold voltage V T is the input voltage a t which the transistor begins conduction; V T has been typically of the order of 4-6 V. Improvements in process control offer promise of providing thresholds of around 1.5 V with a stability of &loo,; [39]. In addition to improving the switching speed, a low threshold is functionally important because it permits simple interface with bipolar circuits and permits reductions in power dissipation. Unlike bipolar junction devices where the switching threshold ( 0.75 V in silicon) is fixed by the energy band gap, the MOS threshold can be varied over a wide range by changing factors such as oxide thickness and surface and bulk charges. This apparent flexibility, however, is the very reason that the threshold value has proved difficult to control [53]. Metal-oxide semiconductor gates are generally structured in “ relay contact ” format, similar to early DCTL; both series and parallel stacks are used. The basic MOS gate is shown in Fig. 16; it provides a NOR for

a

-

FIG.16. Basic MOS gat,econfiguration.

negative-going inputs. Transistor Q1 serves as the inverter or logic transistor, and Qz as the pull-up resistor. In order to maintain a suitable “low” or binary 1 output level near ground, the ON resistance of &z is designed to be about 10 times that of &I. As a consequence, when the output voltage is driven to ground through Q1, the ensuing time

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constant is about one-tenth as large as when the output goes to the supply voltage through QZ. Recent circuit work in increasing MOS logic speeds has centered on eliminating the need for charging interstage capacitances through high resistance transistors. The principle usually invoked involves the use of special clocking and gating circuits which both precharge capacitances and provide the necessary low resistance paths. An example of a recently developed circuit which embodies this principle and has important logic implications is the four-phase configuration shown in Fig. 17.

9 1 4

FIG.17. Basic MOS four-phaseclocked

f-2 0,

9 3 4

95

'OUT

circuit.

Clock signals 41+4 are assumed to be a sequence of four nonoverlapping pulses. The stiff clock signal $1 initially charges C toward -E through &I. As soon as the voltage at node A goes sufficiently negative, Q 4 is primed to conduct but is inhibited by nonconducting & a . When C is' sufficiently precharged, clock $2 arrives permitting C to discharge through Q 3 and Q Z and only if the latter has been primed to conduct because of the appearance of a negative input signal. If node A is driven negative, for example, Q 4 is left in a conditionally conducting stage (parasitic capacitance C temporarily retains the voltage). Clock 4 3 then precharges the capacitance in the succeeding stage which is subsequently left charged or discharged. after the occurrence of clock 44, dependng on the state of Q 4 . Note that the nonoverlapping clocking sequence inhibits the establishment of a dc path from the supply voltage t o ground. The lack of dc eliminates the need for the resistance ratio between Q1 and QZ in Fig. 16, thereby providing the basis for the improved switching speed. Since only charging current flows, chip dissipation can be kept particularly low because clock power is not dissipated in the circuit but instead is entirely dissipated in the presumably off-chip clock source. The four-phase circuit is called ratioless since the absence of dc implies the absence of a constraint on the ratio of the conductances of the

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transistors. The new design principles have been extended to two-phase ratioless schemes. and to circuits in which the pull-up resistor is replaced by a capacitor [ 2 4 . Iterated four-phase stages connected as shift registers are currently in production and are operating a t 10 MHz rates with a power dissipation of 1-2 mJT per bit; 100 pi!' dissipation per bit has been reported for a 1 MHz rate [ 2 4 . Progress in circuit and processing technology suggests a t least another factor of two in register speed will be attained. A photograph of a Philco-Ford Microelectronics Division 200 bit register chip is shown in Fig. 18. The 90 x 90 mil single layer metal chip contains 1200 transistors plus several output drivers. The six-transistor cell layout is shown in Fig. 19; the transistors have a channel length of

FIG.18. Photograph of 200 stage 110s shift register (courtesy of Philco-Ford Corporation, Microelectronics Dil-.).

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around 10 p , and the cell size is 25 square mils. The 200-stage register has been demonstrated; studies on state-of-the-art technology suggest that 2000 stages are feasible on the same size chip with 5 p geometry and two-phase ratioless circuit techniques [all. The four-phase circuit of Fig. 17 and other similar clocked stages can be used as clocking stages or pulse formers in a synchronous logic system. Furthermore, transistor &I can be replaced by a complex series-parallel

FIG. 19. Single stage layout of 200 stage register (courtesy of Philco-Ford Corporation, Microelectronics Div.).

p: I :%

2408

94

92

I

stack of transistors; the ensemble can then serve as a general clocked logic block in a multibeatz system. The beat rate will depend on the variation in propagation delay through the general logic block as a function of the topology of the series parallel stack. Cohen et al. [ I I ]have discussed a general synchronous logic block and suggested the feasibility of a 32-high stack [ I l l . Ignoring questions of instability, the greatest drawback t o the use of MOS is the increase in propagation delay incurred when driving off the chip into even moderate size capacitances ( 1 0 picofarads). The degradation implies that an ordinarily desirable design progression from small chips to increasingly large chips may be impractical, but that MOS instead requires a transition directly into full scale LSI. Since most current small commercial processors operate with typical stage delays in the order 30-50 nsec and contain relatively low cost, high-capacitance N

2 The term beat denotes the clock sequence from one timing stage to the next; the term phase denotes the succession of clock signals used to sequence through one timing stage.

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wiring, a serious design transition exists at even the low end of the processor spectrum. \l’hereas the case for MOS in this application area is not hopelcss. it milst first be shown that the functions required in a small processor could be satisfied by a carefully partitioned and packaged array of 310s chips which, a t the same time, would provide economic advantages over conventional or small chip bipolar approaches. The prospects for 310s in commcrcisl areas arc more attractive in memory applications and in slower speed communication terminal or free-standing eqiiiymcnt such as keyboards, tj-peu-riters, desk calcnlators. and various document handling devices. On the other hand, high volume terminal equipment such as CRT displays carrentlp make efficient use of high-speed circuit technology to execute various fine-structure logic decisions. In the military field, arrays of MOS shift registerlike structures appear t o be uniquely suited to the highly parallel type of processing required in problems such as sonar beam forming. Clear applications for complementary pair MOS are particlilarly lacking. In addition to the drawbacks in added processing and area requirements already cited, it should be noted that the speed and low dissipation attributed t o the complementary pair docs not necessarily provide an advantage over single polarity MOS in the important memory area. Specifically, the Yleehko-Tcrman study, albeit with n-channel devices, along with other results dcscribed in the next section tend to point out the sufficiency of single polarity MOS over much of the memory spectrum.

8.

Lst Memories

Large scale integration memories show considerable promise. I n contrast with LSI logic, scratch-pad and main memory configurations are almost ideally suited for exploitation of the% advantages of large chips. The high degree of two-dimensional memory cell replication and wiring regularity results in comparatively simple chip design and, with the availability of selection logic directly on the chip, provides a powerful partitioning flexibility. Trade-off possibilities exist between chip storage capacity, speed, I:O pad requirements, and power dissipation which are simply unavailable in logic technology. Furthermore, major advances in chip complexity can be undertaken in a given development program wit,hout the need for concurrent major advances in chip bonding capability, thus conserving development resources and minimizing program risk. Finally. the severe economic barriers which confront logic LSI such as the part number and volump problems are considerably lower. and the change problem appears no more formidable than in batch fabricated magnetic memories.

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In view of the wide disparity between the natural suitability of memory chips to computer needs on the one hand, and the questionable match between large logic chips and computer needs on the other, one might wonder why there has been so much concentration on logic and so relatively little progress in memory. Whereas the answer to this question is involved, it is worth observing that memory may be the natural bellwether for LSI, with its progress, rather than that of logic, providing the more useful calibration point for the status of the technology. Semiconductor storage elements have already superseded magnetic films in fast scratch pads; the major unresolved question is the likely depth of penetration into main memory applications. All-bipolar scratch pads of several hundred words capacity have undergone considerable development and one version, noted earlier, is currently performing useful work at the system-user ievel. Bipolardriven MOS memory chips, with high storage density and low storage dissipation per chip, are promising for the larger memories. Bipolar-Mos combinations are probably in the strongest position to test the domain of larger film and core memories which operate under 500 nsec, and the lower performance main and buffer core memory areas. Despite the potential of semiconductor memories for the latter applications, relatively little progress is evident in these areas at the end of 1967, suggesting formidability of the design and economic problems. An earlier illustration arrived at a cost projection of$1.30 for a 10,000square-mil 56-gate logic chip; adapting the same figures t o a future 256bit memory chip results in a cost of one-half cent per bit (prior to testing and packaging). It should be remembered that any and all cost improvements in the general semiconductor art will be directly applicable to LSI memories; capital facilities developed for general semiconductor use will be similarly applicable. Likely improvements in yield and reduction in wafer processing costs over the next few years should take the onwafer cost down to a level of one-tenth cent per bit, comparable to the element cost in magnetics. Testing, packaging, peripheral circuitry, power supplies, and other expected elements of cost will undoubtedly take the over-all system cost considerably higher. Since it has become increasingly rare t o be able t o project a potential raw bit cost of the order of one-tenth cent or less for any technology, the prospect of attaining the one-tenth cent figure provides the basic motivation and sufficient condition for the pursuit of large LSI memories.

8.1 Bit Organization Performance considerations and iimitations can be illustrated by several examples of general design. One approach is the bit organization in which coincident read and write selection is used on a chip which

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contains one cell (one bit) of each of, say, M = m2 words. Similar to t,hree-dimensionalcore structures, final selection is executed in the array at the bit level, resulting in a requirement of 2m I/O pads for addressing. The term bit organization as used here actually applies to the chip rather than to the system; a bit-organized chip can be used in either a bit- or word-organized system. As illustrated in Fig. 20, a word line and one or two additional lines for digit control are required; the sense line can be either combined with the digit line(s) or kept conductively independent to minimize digit noise. One approach is to use a series string of

, I

I ONE

1

STORAGE BIT PLUS SELECTION

3

1

FIG.20. Section of

I

BIT-SENSE LINES

chips t o provide multiples of M words, with one string required per bit. Thus an MK-word n-bit memory made up of M-bit chips consists of n strings each containing K chips. Two 16-bit bipolar bit-organized memory chps have been designed and described. The first consists of a 70-mil-squarechip using Solid Logic Technology (SLT)bonding technology and one level of metallization [ I ] . It was developed for exploration of large, high-speed low-cost arrays. Masking alignment tolerances of 0.2 mil were used; although there have been no reports on attainable system performance, the access time from chip input to low level output (
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sense amplifier as depicted in Fig. 21. One pair of emitters of the flip-flop transistors of each cell is directly coupled to the two sense line. When not sensing, the flip-flop current of each cell flows into the select lines. During read time, the voltage on a given select line is raised to a level sufficient to permit the flip-flop current from one transistor in the selected cell to flow in one rail of the sense line pair. As an item of commerce, the chip is particularly significant since the self-contained driving, sensing, and storage circuitry permits optimization of over-all circuit design and silicon area usage while at the same time providing

I

FIG.21. Sixteen-bit chip with self-oon-

xt

I

Y1

I

SELECT LINES

tained sense and write circuits.

I

I

SENSE LINES

1

I I

I I

I CELL 16

x4

y4

the system manufacturer with considerable subsystem flexibility. The access time from chip input to high level output is less than 20 nsec with a 30-picofarad load; access and read cycle times of less than 50 and 100 nsec, respectively, can be achieved with several hundred words. The chip is 5000 square mils, contains one level metal, and nominally dissipates 250 mW. A bit-organized p-channel MOS storage element and selection circuit can be implemented with eight transistors as indicated in Fig. 22. The selection transistors serves as bilateral transmission switches and pass both digit charging current and low level sense signals. Capacitive loading in the sense and selection dimensions plays a particularly important role in the design of large MOS arrays. Each bit contributes typically several tenths of a picofarad or more to tthe bit-sense and selection lines and, as a consequence, bipolar line drivers and sense detectors are practically mandatory to achieve speeds competitive with magnetics. A somewhat more involved problem arises in the sense dimensions where the readout signal must be transmitted through a t

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least one MOS transistor which drives a large capacitive load. One approach under consideration to circumvent the effwt of the large off-chip capacitancc is the use of a special large area MOS transistor output bufier or line driver on the memory chip. The MOS loading problem can be illustrated with reference to a design hy Brewer r t al.. the first and only published example of a bit-organized memory system [ 6 ] .The random access structure, designed as a feasibility vehicle for aerospace applications emphasizing very low power dissipation, has a l024-word capacity with 30 bits per word. Bipolar drivers and sense circuits and p-channel 310smemory elements are used;

BIT-SENSE LINE

BIT-SENSE LINE

PIC.22. Bit-organized xios storage cell arid selection circuits.

read access times of 0.7 p e c and read or write cycle times of 1 psec are achiered at a power level of about 2.5 IT. The memory chips measure 8000 square mils and contain 64 hits each; the 470 chips are arranged in a 3U-row. 16-column matrix. Eight X and eight I' address-select lines enter each chip; a given X or 'I' line connects to 32 storage elements in each bit of the 30-bit word, thereby contacting a total of 120 chips. The total line capacitance is indicated as measuring about 1300 picofarads, with about half contributed by each chip internally and half by external wiring capacity between the 180 "-lead flatpacks plus the capacity attributable to the flat package itself. The storage cell configuration difftm somewhat from that of Fig. 28. Stven transistors are used instead of eight : each of the two selection lines makes only one connection to each cell rather than two, thus reducing the capacity per bit seen by thc selcction lines. Each of 30 bit-sense line-pairs connects to 64 storage elements per chip and 16 chips in a series stack, thereby accumulating about 365 picofarads of capacitance. The large line capacitances, in addition to controlling response time, are responsible for a large fraction of the system power dissipation.

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Higher performance line drivers could be used to charge the lines a t a faster rate but at a sacrifice in power dissipation. It is of interest to note that the charging current level required to drive a 1-psec bit-organized 30K bit MOS memory is somewhat too large ( 200 mA) for conventional monolithic circuits. A portion of the reliability problem in core memories has been generally attributed to the use of high current drivers operating about the same current level; semiconductor memories with conventionally packaged chips will be similarly affected. The key to the attainment of low power dissipation in general lies in the design and method of operation of the storage cell. If the cell dissipation were as large as in the typical currently available MOS shift register cell, the 30,000 cells would dissipate about 30 W. Whereas i t is possible to reduce total cell dissipation to about 3 Wwith careful design, use of a pulse- and capacitor-hold technique can further reduce the array power to as low as 930 mW in the present example. The technique requires that the flip-flop load devices (equivalent t o @ andQ4 in Fig. 22) be normally disconnected from the flip-flop proper by means of a suitable gate control voltage. This has the effect of removing the flip-flop from its power supply; during the disconnect period, the flip-flop state is selfmaintained by the parasitic capacitance (C) across the drain-to-source of the transistor on the nonconducting side of the flip-flop. For illustration, assume Q1 is in the conducting state and Qz nonconducting. During the interval that Q3 and Q 4 are conducting, the parasitic capacitance C acquires a voltage essentially equal to the supply voltage which, in turn, is sufficient to keep Q1 on. When the load transistors are turned off, &I stops condutcing because there is no remaining dc path to sustain conduction but remains primed to turn on owing to the voltage on C, and will do so whenever a restore pulse applied to the gates ofQ3 and Q4 is present. Thus, the array consumes no power when the restore pulse is absent and Q3, Q 4 are off. The charge on C gradually leaks off through the leakage resistances of the &I gate, and the drain or source paths of Q.-, Q? , and Q7 to the substrate. In the subject design, the flip-flops can be safely disconnected for about 0.1 msec; the restore pulse permits charge replenishment in about 1.5 psec. Dissipation, about 30 pW per cell, is thus seen to be a function of the duty cycle of the restore pulse, which in the present instance is 1.5%. The choice of the transconductance parameter Gm for each transistor in the cell involves trade-offs between power dissipation, response time, and silicon area. The current in the conducting transistor of the flip-flop should be as low as possible for low standby power but well into the conduction region of the drain-source current versus gate voltage curve. Since current is proportional to Gm or the ratio of channel width to length, low power is compatible with area limitations but both must be N

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compromised with high Gm or fast response time. The choice of Gm is further affected by the limitations on the sense amplifier and driver designs. The Gm of the various devices in the aerospace memory cell range from 10 t o 400, enabling a cell size of about 100 square mils. The memory chip uses single layer metal and diffused crossunders. The latter are diffused simultaneously with the source and drain regions and have a resistance of about 90 ohms per square or 160 ohms per crossunder. Each of the eight X and Y lines connecting to a chip experience eight crossunders or about 1300 series ohms on the chip; however, the 120 chips served by ;t given X and Y line are not in series with respect t o the line but are instead connected individually between line and ground. Assuming an S or Y driver supplies approximately 200 mA, an average of about 1.6 mi4 will be delivered to each chip. The storage element on the chip furthermost or eighth from the point of entry of the driving line onto the chip thus sees a select signal almost 2 V smaller than seen a t the first storage element on the line. Whereas the drive signal in the aerospace system is made large enough to accommodate such effects, the eventual development and use of low threshold MOS devices to obtain power reductions through lower voltage swings must clearly be accompanied by a reconsideration of the crossover resistance problem. Deployment of two layers of metal appears to be capable of providing a reduction in crossover resistance by more than order of magnitude while a t the same time reducing the chip area by 20-40%. 8.2 Word Organization

A .zrord-organized semiconductor memory, depicted in Fig. 23, corresponds to the familiar magnetic 2 0 or linear select system. Selection is made at the level of a group of bits, or a byte or word, rather than a t the single bit level. X dominant characteristic of the word organization is STORAGE AND SELECTION

lr*o[

LINES

I

\

BIT- SENSE LINES

FIG.23. Section of typical

\\

ord-organized semiconductor memory array.

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that the comparatively short word line reduces the drive requirements in the word direction; this is accomplished as usual at the expense of an increase in the number of switching elements on the array periphery. One approach to a word-organized system was described earlier in connection with the discussion on discretionary wiring. One of the earliest exploratory MOS designs was described by Schmidt [69].It used a relatively large chip (115 x 145 mils) with 64 bits in a 16-word, 4-bit array plus a decoder that translates from a 4-bit binary address to a I-out-of-I6 selection signal. In addition t o the pads required for four conventional address lines, two power lines, four bit-sense lines, and a write " 0 " or clear line, a fifth address line is required for chip selection; the decoding for the latter is executed external t o the chip array. The gates needed to convert from a single external data line per bit to an internal two-rail line pair are implemented in MOS on the chip, in addition to the decoder gates. All driving and sensing circuits off the chip are bipolar. Although the delay resulting from internal MOS gating cannot be ascertained because the device characteristics are not specified, the chip speed is described as 2 p e c for alternate read-write cycles, and about 0.4 psec for read access time. The storage cell configuration is similar to that of Fig. 22. Instead of an X and Y selection transistor pair on each side of the flip-flop, only one is required per side and Q 5 and QS can be eliminated; the gates of Qa and Q7 are tied together and driven in common by the word select line. The high performance potentially attainable in MoS-bipolar designs has been analyzed by Pleshko and Terman [66].The cell uses the same topological configuration as that of Schmidt but employs higher performance n-channel MOS devices. The n-channel transistors provide greater gain bandwidth (in excess of 100 Mc in this design) because of higher mobility. All gating, selection, and sensing functions with the exception of read and write select a t the bit level are executed off the chip with low impedance bipolar circuits. The memory is designed as a 128-word, 64-bit system as far as loading is concerned, although no indication of likely memory chip partitioning is given. Low threshold voltage devices are used, or postulated, for the memory cell, thus permitting reduced power dissipation in the cell and reduced voltage and power requirements on the line drivers. The cell supply voltage is indicated as 4.5 V; this value, coupled with high resistance (200 kilohms) MOS load resistors, enables a cell dissipation of about 0.1 mW. Two-layer metallization is assumed, resulting in a line resistance of about 0.4 ohm per cell, or more than an order-of- * magnitude decrease under that of diffused crossunders required for single layer metal. The cell size using two-layer metallization is indicated as 86 mils

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square, an area decrease of 230i0 under the single layer version. Capacitance per bit is typically 0.7 picofarad for two gates per bit in the word direction, and 0.3 picofarad per bit in the orthogonal direction. I n the single metal layer version, the capacitance per bit is practically doubled for the word lines owing t o the need for a diffused crossunder. Vsing RC' networks to simulate a complete array, the memory is reported to operate a t a 12-nsec access time, 35-nsec read cycle time, and 8 60-nsec m i t e cycle time. These response times were obtained with the use of high performance word and bit line drivers; a total system power dissipation of 43.5 W is indicated. The drivers interface directly with Advanced Solid Logic Technology ( ASLT) logic circuits. It is not clear from the article by Pleshko and Terman [66] whether the cited speeds were obtained with one or two levels of metallization; presumably the added parasitics in the former could be handled with an increase in driver dissipation. if desired. Similarly, the authors did not describe the effects of parasitics because of packaging but limited the analysis to the intrinsic device characteristics. I n view of the vanishingly small additional line capacitance which would be incurred in various modern chip packaging approaches, the omission appears reasonable. The significance of the Pleshko-Terman work is that it appears to indicate an optimal approach for achieving high performance, low-cost systems. Although no studies of comparable thoroughness have been reported for all-bipolar systems, it is worth noting that a bipolar approach employing comparable masking tolerances and providing comparable system speed would probably require over 100 W for the array alone. and the driver power would be considerably increased over the 35 M; required by the Pleshko-Terman drivers. Although the restore technique is pertinent in the aerospace application, the postulated steady-state dissipation of 0.1 mW per cell would be sufficiently low to compete in all conventional main memory applications. One partial exception to the above assertion on power is realized in an elegant bipolar word-organized system described by Iwersen et al. [36] which features moderate power and 100 nsec performance. The exploratory chip contains 16 cells in a 30 x 38 mil area and is mounted uncased on a ceramic or silicon substrate by means of beam lead bonding. The 1040 square mils is inclusive of the complete beam lead structure. The beam leads are spaced on 2.5 mil centers. There are several significant points in their study. One is that it tends to demonstrate that the silicon area loss because of beam leads is rather modest on a small chip. Since the percentage loss because of beam leads normally decreases as the chip is made larger, a lessening of the earlier cited concern over the area-wasting effective of beam leads seems to be justified. A second significant point is that the cell area, although not explicitly stated, is

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approximately 25 square mils, a size considerably smaller than any reported MOS cell. Part of the area reduction results from the formation of the several resistors directly in the normal epitaxial layer rather than in the usual specially diffused areas. The chip is apparently organized with four 4-bit words; since two-rail bit-sense lines are used and power is supplied through the word and bit lines, a total of 12 pads are required, The photograph of the chip, however, shows 24 beam leads; the redundancy is possibly motivated by the desire to tolerate a t least one opencircuit defect anywhere on each drive line bus, or to reduce the effective bus resistance. The sensing arrangement is somewhat similar to that shown in Fig. 2 1. Since a primary goal of the design was to minimize chip area, a significantly different approach is actually used. Selection emitters are not used and each cell continuously delivers current into the sense-line pair. When the word-select line (whichdoubles as the collector supply voltage line) is raised, each cell in the selected word accordingly supplies a larger emitter current to the appropriate sense line; the change in current is detected by the sense amplifier. The latter entails a rather sophisticated design which must be capable of providing a sufficiently low incremental and total impedance to the sense-line pair to permit proper conduction of the cell flip-flops, as well as detecting a small incremental change in current level. The extent to which the system design can be increased beyond 64 words is accordingly dependent upon the margins available in the sense amplifier. The standby power for each cell is 1 mW; the quiescent driver power, although not explicitly given, appears t o be of the order of 50 mW. The specific memory system used to illustrate the potential of the chip is a 64-word, 16-bit system which operates with a 100-nsec read-write cycle time. The bit density in the system array is 9500 bits per square inch [ 2 5 ] ;for comparison, modern magnetic arrays are typically only 1000-1500 bits per square inch. A complete bipolar memory system was described in 1965 [62] by Perkins and Schmidt; although an early design, it represented a large step forward in the competition with magnetics. The system was particularly significant because it became a commercially available product, and a t this writing, it is one of the few known commercially available semiconductor systems. The memory chip contains four words of 9 bits per word, a selection optimized t o fit a standard 16-lead package. The system contains 256 words at 72 bits per word and operates at 150 nsec cycle time, with a slightly smaller read access time. The memory chip power is about 5 mW per bit (92 W for 18,432bits) and 130 W total. The capacity associated with the bit-sense line was estimated at 0.2 picofarad. It should be noted

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that the emitter capacitance is less than the gate capacitance of the earlier cited current technology MOS transistors. All 512 memory chips are packaged on four 8 x 10 in. cards; three additional cards are required for a complete system. Design considerations in an ultra-high-speed scratch-pad system have been described by Catt et al. [8].Using 1-2 nsec current mode logic gates in the storage cell, a system nondestructive read cycle and write cycle of 17 and 10 nsec, respectively, were estimated for a 64-word, %bit nonoverlapped configuration. The memory chip contains two cells and dissipates 275 mW; the technology is similar to that used in the chip shown in Fig. 9. The article contains an interesting description of the packaging and thermal problems involved in an ultra-high-speed system design. 8.3 Content-Addressable Memories

Semiconductor technology has an inherent functional advantage over magnetics in content-addressable applications, namely, that the former can be searched in a bit-parallel as well as a word-parallel mode; i.e., all bits in each word can be interrogated simultaneously. The bit cells within each word are, in effect, OR'ed together on the word-sense line whereby one mismatched bit can be detected. Although the OR function is readily available in magnetic systems, the " shuttle '' noise resulting from imperfect squareness or imperfect cancellation in a two-element per bit configuration, combined with the inherent bit-to-bit variation in output signal, creates an unfavorable signal-to-noise ratio. Specifically, the signal-to-noiseat the mismatch of one bit level is low for search fields of 10 to 12 bits or more. Although coding techniques can be brought t o bear which will provide a strong signal-to-noise improvement at the expense of adding redundant bits and a loss of functional generality, the magnetic Content-AddressableMemory (CAI) is usually designed for the slower bit-serial operation. Much of the current interest in the CAM is for relatively small units which, for example, are embedded in the processor and perform one of several functions in the memory cell sequence. Since such functions, e.g., paging, should have an access time 5-10 times less than main memory. semiconductors dominate by virtue of their bitparallel search capability. Iwersen et al. pointed out that their location-addressable memory can be arranged in a reasonably straightforward way to perform a contentaddressable function; a similar comment applies to the 16-bit chip [30]. Several designs specificallytailored to the search problem have appeared. An article by Igarashi and Faita describes a system [35] containing a 4-cell MOS chip which is designed for a 14-lead package. The cell can be cycled in 100 nsec, dissipates less than 100 pW when quiescent and

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1 mW peak when interrogated; the peripheral circuits are presumably intended to be bipolar. The ultra-high-speed exploratory CAM chip shown in Fig. 9 has an estimated chip speed of about 6 nsec [12]; experimental transistors with 0.1 mil emitters provide about 1 nsec delay and 1 nsec rise and fall. In addition to its cited disadvantages in small fast CAM applications, magnetic technology has also fallen short of providing economical large retrieval-type CAMS in the several thousand word and larger category. Such CAMS are characterized by microsecond search times and multiplematch-resolve and write-on-match capabilities. Large-scale integration memories appear to have all the necessary potential attributes to surpass magnetics and to eventually satisfy typical requirements in this area.

8.4 Read-only Memories MOS devices are highly suited for implementing inexpensive medium speed fixed read-only memories. Since MOS transistors can be spaced on several tenths mil centers, a comparatively inexpensive chip can contain a large number of bits, as well as decoding circuits to minimize pad count. Limitations to this approach are that photomasking and other processing steps for metal removal are required to implement a pattern change, and that the on-chip MOS decoder limits the access time to the microsecond range. With one exception, conventional semiconductor technology does not appear to be particularly suited to the changeable read-only application. Although techniques such as fusing have been presented which would provide the user with a direct means of easily programming his own chips, conventional photomasking is the only currently satisfactory method of implementing the required pattern. A powerful and significantly different approach to a programmable read-only semiconductor memory has been recently described by Wegener et al. [89].Using a modified p-channel IGFET structure, information is stored in a single transistor by setting the threshold voltage to a high or low value. The transistor can then be interrogated by application of a gate voltage intermediate to the two threshold extremes; output current will flow only if the applied pulse is more negative than the threshold voltage. The threshold value can be altered to a high (most negative) or low voltage by application of a plus or minus 50 V pulse, respectively, of about 1 msec duration. Persistence of stored information over periods of at least several months has been demonstrated; retention of data does not require an external power supply. A related phenomena and analysis has recently been described by Kahng and Sze, and Kahng [38,37].Use is made of an IaFET-like device containing a special internal gate which can be charged by a field

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emission mechanism. The charge is retained for a period after the field is removed; holding times longer than one hour have been observed. The holding mechanism in the Kahng device appears to be quite different from the presumably permanent effect in the device of Wegener et al. 1891 and apparently requires a restore procedure. 8.5 Reliability

Since semiconductor memories are still in an early stage of laboratory development, litjtle or no direct reliability data are available. On the other hand. voluminous data have been accumulated on magnetics. Although the reliability of a hypothetical or actual MOS memory cannot readily be extrapolated from other MOS developments, a bipolar memory and bipolar processors have sufficient points in common to permit a useful comparison. For thr sakr of illustration, one such commonality is solder- or welded-type interconnections on the PC board (an oft-cited advantage of magnetic over semiconductor memories is fewer interconnections). \Vhereas an analysis of comparative interconnection reliability should take into account many factors and not be merely a counting exercise, the following observation may nevcrthrless serve as a useful calibration point : Assuming 256 bit memory chips and on-chip decoding to minimize interconnections. a hypothetical 5 x 105 bit memory array would rcquirc on the order of 30.000-50,000 solder-type connections, a value scw*ral timvs smaller t han that found in reliable, high pwfor5 1108. niancc., inttyrated circuit processors with the power of the UNIVM: It should be noted that the volatility of a semiconductor memory appears not to be a particularly serious issue, a t least in commercial systems. lnfrequent memory losses because of volatility can be handled by customary rerun-point procedure [83]. Another aspect of reliability relates to power dissipation in the line drivers. Larger arrays using present-day semiconductor and packaging technology require line currents comparable to those in core; this was particularly evident in the description of the 30K bit nros-bipolar bitorganized system. Although the bipolar driver dissipation is kept low through the use of circuit techiques unique to BIOS arrays, the levels c.itrtf might constitute a lower hound on the value attainable in an alltlm or in a 310s-bipolar system without the resonant line technique. Anticipated advances in the lowering of MOS threshold voltages plus the use of uncased chips strongly indicate the attainability of polver levels less than in core. It is interesting to observe that one of the original reasons behind the push to semiconductor memories. namely, simple and direct compatability between the array and the logic circuits, has proved mildly

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invalid. Special drivers and detectors of rather intricate design are frequently required a t present for both semiconductor and magnetic systems. The real issue pertains to the degree to which these designs can be implemented in low-cost integrated form. The current trend in magnetic film memories is in the development of closed flux-path elements requiring relatively low driver currents which tend to approach values (200 mA word current, 30 mA bit current) obtainable with lowcost semiconductors. Successful implementation of a low-cost magnetic semiconductor interface prior t o solving the many new problems of an all-LsI memory would appear to have the effect of prolonging the entry of the latter into operational systems. 9. Further System Implications

After several years of exploratory development in large chip technology, there is relatively little reason to doubt that the semiconductor industry will eventually be able t o process wafers with large complex chips at reasonable yields. Whereas important technological issues still exist in multilayer fabrication, dissipation in high performance chips, and connections to the chip, economics of LSI logic stands as a problem of the first magnitude. The requirements of small processors, terminals, and certain I/O devices are generally compatible with the characteristics of potentially low-cost bipolar LSI chips. The part number and total volume aspects are sufficiently attractive to suggest that such devices may be among the earliest commercial applications of bipolar LSI logic. Metal-oxide semiconductor logic, while possessing intrinsically adequate characteristics for the lower performance commercial systems, does not readily permit LSI to be approached in gradual steps. To the extent that the momentum of current design philosophy prevails in the system industry, this must be assessed as a self-limiting feature. It is paradoxical that the technology for the application most dependent on the performance attributes of LSI, namely, large-scale systems requiring 1 nsec logic and less, is technically and production-wise the least advanced. Henle and Hill [32] suggested that a rough span of three to four years occurs between advanced development and production announcement (for a given number of components per chip). Since advanced development on 1 nsec logic at the level of 30-50 gates per chip is barely underway, the implication is that production chips would not be available before, say, 1972. It is tempting to speculate that the usual array of technological (and system) development problems will be amplified when pushing the nanosecond art on the large chip, and that production availability will be noticeably delayed beyond 1972.

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The outlook for LSI memory is considerably brighter. Whereas, the chief competition for the large logic chip is the near-invulnerable small chip, the competition for the large memory chip is not a small chip but is instead magnetics. Large-scale integration provides a natural implementation for fast scratch pads and buffers. Conway [ l a ] argues against the use of LSI to build increasingly larger conventionally addressed scratch pads in general-purpose systems and instead proposes the validity of the transparent scratch pad (one whose addressing is not available to the programmer). The argument is based upon (1) the overhead incurred each ,time the conventional scratch pad must be dumped and reloaded because of a program switch, and (2) the poor economics of attempting to eliminate this component of program switch overhead by building a large enough scratch pad to accommodate simultaneously the worst case number of scratch pad words of all programs. Use of a small content-addressable memory to control the transparent scratch pad or direct use of a content-addressable scratch pad, along with an adaptive purge strategy, eliminates the need to make worst case assumptions and correspondingly reduces the aforementioned overhead. Conventional main memories implemented in LSI will be feasible if the conjectures in the last section on cost and reliability do not prove to be overly optimistic. Successful implementation suggests a breakthrough in main memory speed and a possible reassessment of traditional hierarchy arrangements. Large-scale integration memories appear to be compatible with a foreseeable trend in multiprocessor memories where module granularity might become smaller than currently economical for the purpose of permitting additional concurrent accesses. Although it may be too early to seriously consider LSI mass memories, it is not inconceivable that sufficiently inexpensive, reliable arrays of LSI circuits can provide the basis for a storage subsystem with improved access, transfer, and reliability characteristics in comparison with conventional electromechanical equipment. Efforts in logic partitioning have been renewed in order to prevent burdening the LSI chip with excessive I ~ Opads and to exploit the possibility of chips with hundreds of gates. A significant study has been reported by Beelitz et al. [3, 331; separable function execution units which perform various classes of processing are used, and control is divided into ( 1 ) decentralized processing execution within each of the function execution units, and ( 2 ) a centralized information transfer control. The authors cite three to one and five to one improvements in gate-to-r,'o pad ratios at the 100- and 1000-gate levels, respectively. in comparison with data taken from a survey of conventional architecture. The key reason for the improvement appears to be the decentralization into autonomous units which eliminates much of the global irregularity

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of control interconnections, and the use of a request-knowledge bus structure between units. A careful evaluation of the performance and trade-offs of the decentralized control machine with respect to conventional architecture would be a significant contribution. Studies generally show that superior partitions exist with increasing numbers of gates whether or not the logic is restructured. Although this is precisely the goal of the studies, exploitation of the principle to large chips ( 100 gates or more) would appear to have the effect of delaying the entry of LSI into working systems since large chips aggravate all of the problems of LSI. Maximizing gate-to-pad ratios has already been considered in third generation packaging, albeit with a slightly different set of design parameters; it is not at all clear that a further attempt a t partitioning (approximately the same third generation logic) will produce substantially better results for LSI. This observation appears to be particularly true in large-scale high-speed systems where minimization of the number of stages between clocked points has traditionally tended to dominate partitioning considerations. Suggestions for fourth generation systems have been made which incorporate additional control functions in microprograms resident in the logic-control (i.e., read-only) memory a t the expense of both hardware and software. Opler [61],for example, proposes replaceable micro-programs for specializing the particular roles of a computer. Fortunately, a microprogrammed processor may be better suited to an LSI implementation than a conventional processor since incorporating a considerable portion of the controls in a simple memory structure in effect removes irregular control features from the processor [3, l a ] . The control-logic memory is not clearly destined to be implemented in LSI. If the volatility issue persists, use of a permanent semiconductor read-only array raises the usual questions concerning the delay in the redesign cycle; otherwise, use of conventional read-write memories (including LSI) with special write features should be economically justified. An increase in execution speed would probably accrue if portions of system software were converted to logic hardware, although the level of current software maintenance suggests the existence of a formidable obstacle. Procedures such as determination of interrupt source, processing of certain interrupts, polynomial computation, task allocation, and many others can possibly be put into hardware; however, it is not clear that doing so will make the computer more useful or easier to manage. On the other hand, objectives for fourth generation system designers might well be to make computers more flexible and less costly to program. A host of organizational innovations such as flexible hardware stacks and queues, improved memory addressing, and methods of managing and insuring reliability of concurrent processes are under

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consideration and may permit attainment of some of the fourth generation goals. These objectives, however, are not necessarily matched t o the more obvious properties of LSI. I n short, many of the software-systems problems that exist today are, t o a degree, independent of or subtlely related t o the hardware issues, and must be resolved by separate considerations. The promise held by LSI is that in some as-yet-undeveloped manner its exploitation may help in the resolution of the real problems. ACKNOWLEDGMENTS The author v ould like to gratefully acknowledge helpful discussions with

M. E. ('onuay, J . P. Eckerk, R. M. Engluiid, J . B. Schuars, G. B . Strawbridge, and A. 1-3. Toiiik of Univac; D. Chung, Texas Instruments; K. Seeds, Fairchild S~micoriductor;arid C . Thornton, Philco-Ford Microelectronics. Thanks are due Mrs. H . A . Glover for patient typing of text revisions (partly caused by changes in

the state-of-the-art).

REFERENCES I . Agusta, H.. Hardell. P., and Castricci, P., Sixteen-bit monolithic memory chip. I E E E intern. Electron. Develop. Conf., Washington, D.C., 1965. IEEE, Nen Tork. 2. Armstrong. D. B., On finding a nearly minimal set of fault detection tests for combinatioiial logic nets. I E E E Trans. Electron. Computers, 15, 66-73 (1966). 3. Beelitz. H. K.. et al.. System architecture for large scale integration. Proc. i l F I I ' S Fall .Joznt Computer Conf., Los Angeles. 1967, pp. 185-200. Thompw n . Washingtoil, D.C. 4 . Bilous, O., Feiiiberg, I., and Langdoii, J. L.. Design of monolithic cirruit chps. I B N J . Res. Develop. 10, 370-376 (1966). 5 . Rloch, E., The engineering design of the stretch computer. Proc. Eastern Joant Cowiputer Conf., Boston, 1959, pp. 48-58. 6 . BreLtw, D. E., Stssim, S., and Podraza. G. V.,Low poirer computer memory system. Proc. Am Federation Inform. Processang Soc. Conf., November, Los Angeles. 1967, pp. 381-393. Thompson. IVashington, D.C. 7. C'anaday, R. H.. Two-dimensional iterative logic. Proc. A F I P S Fall Joint Computer Conf., Las l'egas. 1965, 27, pp. 343-353. Thompson, Washington, D.C. 8. Catt, I., Garth, E. C., and Murray, D. E., A high-speed integrated circuit scratchpad memory. Proc. A F I P S Fall Joint Computer Conf., Sun Francisco, 1966, pp. 315-331. Spartan Books. W'ashington, D.C. 9. Chen, C. Y., Feinberg, I., and Langdon, J. L., A high-performance master chip for logic circuits. I E E E Intern. Electron. Develop. Conf.. Washington. D.C..1967, p. 18. IEEE, X e u York. 10 C'hung, D. H.. and Palmieri, J. A, , Design of ACP resistor coupled switching circuits. I B J I J . Res. Decdop. 7, 190-198 (1963). 1 1 . Cohen, L., et al.. MTOS four phase clock systems. Record h'ortheast Electron. Rea. Eng. Meeting, Boston, 1967, p. 170. E. E. Witschi. Jr., Newton, Massachuset ts 12. Compatible Semiconductor Thin Film Techniques, Contract No. AF 33 (615) 2629, Third Quart. Rept., Prepared for U. S. Air Force SEG, RTD WPAFB, Ohio, Under contract with Motorola Inc., Semiconductor Prod. Div., Phoenix.

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13. Condon, D., et al., Large scale integrated circuit arrays. Contract No. 33 (615) 3620. Seven reports issued through December, 1967, Santa Clara, California, prepared for WPAFB by Philco-Ford Microelectron. Div. 14. Conway, M. E., and Spandorfer, L. M., A computer system designer’s viewpoint of large scale integration. Proc. Fall Joint Computer Conj., Sun Francisco, 1968. To be published. 15. Davis, E. M. et al., Solid logic technology; versatile, higL performance microelectronics, I B M J . Res. Develop. 8 , 102-1 14 (1964). 16. Dhaka, V. A., Simulation techniques for high frequency transistor design and applications to transistor fabrication. Record Northeast Electron. Res. Eng. Meeting, Boston, 1966, pp. 124-125. E. E. Witsckii, Jr., Newton, Massachusetts. 17. Dunham, B., The multipurpose bias device, Pt. I. I B M J . Res. Develop. 1, 119-129 (1957). 18. Dunham, B., et al., The multipurpose bias device, Pt. 11.I B M J . Res. Develop. 3, 46-53 (1959). 19. Dunn, R. J., and Jeansonne, G. E., Active memory design using discretionary wiring for LSI. Digest Intern. Solid-State Circuits Conf ., Philadelphia, February 1967, pp. 48-49. Lewis Winner, New York. 20. Earle, J., The impact of microelectronics on digital computers. I B M Tech. Rept. TROO. 1236 (1965);Electronic Design (1964). 21. Elspas, B., et al., Properties of Cellular Arrays for Logic and Storage. Contract No. AF (628) 5828, Sci. Rept. 3. Prepared for AFCRL, OAR, USAF, Bedford, Massachusetts, 1967. 22. Fagg, P., et al., IBM system 360 engineering. Proc. A F I P S Fall Joint Computer Conf., Sun Francisco, 1964, pp. 205-321. Spartan Books, Baltimore. 23. Farina, D. E., Advanced MOS circuit techniques for LSI. Lecture notes. Meeting Recent Advan. Solid-State Technol., Univ. of Wisconsin, May 1967. 24. Farina, D. E., and Condon, D. C., MOS-LSI devices and systems. IEEE Intern. Electron. Develop. Conf., 1967, p. 12. IEEE, New York. 25. Finch, R. R., LSI digital electronics. Digest Intern. Solid-State Circuits Conf., Philadelphia, February 1967, p. 32. Lewis Winner, New York. 26. Fisher, G. J., and Wing, O., Computer recognition and extraction of planar graphs from the incidence matrix. IEEE Trans. Circuit Theory 13, 154-163 (1966). 27. Flynn, M. J., A prospectus on integrated electronics and computer architecture. Proc. A F I P S Fall Joint Computer C o i f . . Sun Francisco, 1966. pp. 97-103. Spartan Books, Washington, D.C. 28. Freitag, H., Design automation for large scale integration, I R E WESCOIV Conw. Record Tech. Papers, Ses. 10 (1966). 29. Guckel. H., and Brennan, P. A., Picosecond Pulse Response of Interconnections in a Common Substrate Monolithic System. Proc. IEEE Intern. SolidState Circuits Conf., Philadelphia. 1967, p. 110. Lewis Winner. New York. 30. Hart, T. W., Integrated circuit memory system. Record Northeast Electron. Res. Eng. Meeting, Boston, 1966, p. 216. E. E . Witsch, Jr., Newton, Massachusetts. 31. Heightley, J. D., and Mallery, P., Exploratory study of bonding methods for leads on 2.5 to 50 mil centers. Proc. Electron. Components Conf., pp. 168-177 (1966). 32. Henle, R: A., and Hill, L. D., Integrated computer circuits, past, present, and future. Proc. IEEE 54, 1849-1860 (1966).

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33. Herzog, G., et al., Large scale integrated circuit arrays, Contract No. AF 33 (615) 3491. Seven reports issued through December, 1967, prepared for WPAFB by Radio Corp. of America. 34. Hobbs, L. C., Effects of large arrays on machine organization and hardware/ software tradeoffs. Proc. A F I P S Fall Joint Computer Conf., Sun Francisco, 1966, pp. 89-96. Spartan Books, Washington, D.C. 35. Igarashi, Ryo, R., and Toru, Y., An integrated MOS transistor associative memory syst,em with 100 ns cycle time. Proc. A F I P S Spring Joint Computer Conf., Atlantic City, 1967, pp. 449-506. Thompson, Washington, D.C. 36. Iwersen, J. E., Wuorinen, J. H., Murphy, B. T., and D'Stefan, D. J., New implementation of bipolar semiconductor memory. Digest Intern. Solid-State Circuits Conf., February 1967, p. 74. 37. Kahng, D., Semipermanent memory using capacitor charge storage and IGFET read-out. Bell System Tech. J . 46, 129&1300 (1967). 38. Kahng, D., and Sze, S. M., A floating gate and its applicat,ion to memory devices. Bell System Tech. J . 46, 1288-1295 (1967). 39. Klein, T., Technology and performance of integrated complementary MOS circuits. Record h'wtheaet Electron. Res. Eng. Meeting, Boston,, 1968, p. 168. E. E. Witschi, Jr., Newton, Massachusetts. 40. Lathrop, J. W., Semiconductor network technology-1964. Proc. I E E E 1430-1444 (1964). 41. Lathrop, J., et d . ,Large scale integrated circuit arrays, Contract No. AF 33 (615) 3546. Seven reports issued through December, 1967, prepared for WPAFB by Texas Instruments, Dallas, Texas. 42. Lepselter, M . P., Beam lead sealed-junction technology. Bell Lab. Record 44, 298-303 (1966). 43. Lepselter, M. P., Beam lead technology. Bell System Tech. J . 45, 233 (1966). 44. Lo, A. W., A comprehensive view of digital integrated electronic circuits. Proc. I E E E 52, 1546-1550 (1964). 45. Low, P . R., The impact of large scale integration on small data processing equipment. Digmt I E E E intern. Conv., New York, 1968, p. 81. IEEE, New York. 46. Luce, R. L., Transistor design for application in high-speed complex bipolar arrays. I E E E Intern. Electron. Develop. Conf .. Washington, D.C., 1967. IEEE, New York. 47. Lynn, D. K . , Meyer, C. S., and Hamilton, D. J . (eds.), Anulysis and Design of Integrated Circuits. McGraw-Hill, New York, 1967. 48. Maling, K.,and Allen, E. L., Jr., A computer organization and programming system for automated maintenance. I E E E Trans. Electron. Computers, 12, 887-895, (196:). 39. Minnick, R. C., A survey of microcellular research. J . Assoc. Comput. Mach. 14, 203-241 (1967). 50. Minnick, R. C., Application of cellular logic to the design of monolithic digital systems. Proc. S y m p . Microelectron. and Large Systems, Washington, D.C., 1964, ( S . J . Mathis, Jr., R . E. Wiley, and L. M. Spandorfer, eds.), Spartan Books, Washington, D.C., 1965. 51. Minnick, R . C., Cobweb cellular arrays. Proc. A F I P S Fall Joint Computer Conf., Laa Vegaa, 1965 27, 327--341. Thompson, Washington, D.C. 5 2 . Minnick, R. C., et al., Cellular arrays for logic and storage. Final Rept,., Contract AF 19 (628)4233. Prepared for AFCRL, OAR, USAF, Bedford, Mass., by Stanford Res. Inat., Menlo Park, California, April 1966.

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APPRAISAL

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53. Moore, G . E., The MOS transistor as an individual device and in intergrated arrays. I E E E Intern. Conv. Record pp. 44-52 (1965). 54. Murphy, B. T., Cost-sizeoptima of monolithic integrated circuits. Proc. I E E E 52, 1537-1545 (1964). 55. Murphy, B. T., and Glinski, G. J., Transistor-transistor logic with high packing density and optimum performance a t high inverse gain. Digest Intern. Solid-State Circuits Conf., 1968. 56. Murphy, D. W., High-speed non-saturating switching circuits using a novel coupling technique. Digest Intern. Solid-state Circuits Conf ., Philadelphia, 1962, pp. 48-49. Lewis Winner, New York. 57. Narud, J. A., Seelbach, W. C., and Miller, N., Relative merits of current mode logic microminiaturization. Digest Intern. Solid-state Circuits Conf ., 1963, Philadelphia, p. 104. Lewis Winner, New York. 58. Nevala, R. D., Higher functional complexity using cell oriented bipolar logic. Record Northeast Electronic. Res. and Eng. Meeting, Boston, 1965., pp. 174-175 E. E. Witschi, Jr., Newton, Massachusetts. 59. Notz, W. A., et al., Large scale integration: benefitting the system designer. Electronics 40, 130-141 (1967). 60. Noyce, R. N., A look at future costs of large integrated arrays. Proc. A F I P S Fall Joint Computer Conf., Sun Francisco, 1966, pp. 111-1 14. Spartan Books, Washington, D.C. 61. Opler, A., Fourth generation software. Datamation 13, 22-24 (1967). 62. Perkins, H. A., and Schmidt, J. D., An integrated semiconductor memory system. Proc. A F I P S Fall Joint Computer Conf., Laa Vegm, 1965, pp. 1053-1064. Thompson, Washington, D.C. 63. Petritz, R. L., Current status of large scale integration technology. Proc. A F I P S Fall Joint Computer Conf., Los Angeles, 1967, pp. 65-85. Thompson, Washington, D.C. 64. Petritz, R. L., Large scale integration. Trans. Met. Soc. A I M E 236, 235-249 (1966). 65. Petritz, R. L., Technological foundations and future directions of large scale integrated electronics. Proc. A F I P S Fall Joint Computer Conf., Sun Francisco, 1966, pp. 65-87. Spartan Books, Baltimore. 66. Pleshko, P., Terman, L. M., An investigation of the potential of MOS transistor memories. I E E E Trans. Electron Computers 15, (1966). 67. Price, J. E., A compatible MOS-bipolar device technology for low power integrated circuits. I E E E Intern. Elec. Develop. Conf ., Washington, D.C., 1966. IEEE, New York. 68. Rice, R., Impact arrays on digital systems. Proc. Intern. Solid-state Circuits Conf., Philadelphia, 1967. Lewis Winner, New York. 69. Schmidt, J. D., Integrated MOS transistor random access memory. Solid State Design pp. 21-25 (1965). 70. Sechler, R. F., Strube, A. R., and Turnbull, J. R., ASLT circuit design. I B M J Res. Develop. 11, 74-85 (1967). 71. Seeds, R. B., Yields, economics and logistic models for complex digital arrays. I E E E Intern. Conv. Record 15, 60-61 (1967). 72. Seeds, R. B., Yield and cost analysis of bipolar LSI. I E E E Indern. Electron. Device Conf., Wmhington, D.C., 1967, p. 12. IEEE, New York. 73. Seeds, R. B., and Moyle, K. L., Novel high performance logic circuits. I E E E Intern. Electron. Develop. Conf., Washington, D.C., 1965. IEEE, New York.

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74. Seeds, R. B., Smith, W.R., and Nevala, R . D., Integrated complementary transistor nanosecond logic. Proc. I E E E 52, 1584-1590 (1964). 75. Seshu, S., and Freeman, D. N., The diagnosis of asynchronous sequential switching syst,ems. I R E Trans. Electron. Computers 11, 459-65 (1962). 76. Smith, M. G., and Notz, W.A., Large scale integration from the users point of view. Proc. A F I P S Fall Joint Computer Conf., Los Angeles, 1967, pp. 87-94. Thompson, Washington, D.C. 77. Spandorfer, L. M., Synthesis of Logic Functions on an Array of Integrated Circuit.s, Contract, KO.AF 19 (628) 2907, Final Rept. Prepared for AFCRL, Office of Aerospace Res. USAF, Blue Bell, Pennsylvania. November 1965. 78. Spandorfer, L. M., and Schwarz, J. B., Microelectronic logic circuits. Solid Stute Design 5, 50-66 (1964). 79. Spandorfer, L. M.,and Touik, A. R., Planar interconnection logic. Proc. Synap. Jlicroelectron. and Large Systems, 1965 ( S . J . Mathis, Jr., R. E. Wiley, and L. XI. Spandorfer, eds.). Spartan Books. Washington, D.C., 1965. 80. Spirgcl. P., and LUCY.K. L., A uc\v insulated gate transistor. Digest Intern. Solid-.%te Circuits Conf., of Tech Payes, Philudelphk, 1965, pp. 14-15 (1965). Lebvis \rimier, Kew York. 81. Thoriit on, C . , LS1 subsystems assembled by the silicon wafer-chip technique. Digest Intern. Solid-State Circuits Conf., 1968, pp. 42-43. 82. Tombs, 5 . C., et ul., A new insulat,ed gate transistor. Digest Intern. SolidState Circuits Conf., Philadelphia. February 1966, pp. 58-59. Lewis Winner, Xew York. 83. Tonik, A . R., Development of executive routines, both hardware and soft\varc. l’roc. A FIPS Fall Joint Computer Conf., 1967, pp, 395-408. 8 4 . Triebuasscr, S., Programmable interconnection techniqcio. Digest Intern. Solid.Stute Circuits Conf., Philadelphia, February 1966, pp. 124-125. Lewis bViiiiier, X e w York. 85. Vadasz, L.. el al., X systematic engineering approach to complex arrays. Uigevt Intern. Solid-Stnte Circuits Cqnf., Philudelphia, 1966. pp. 120-121. Le\vis Wirrricr. Sew Tork. 86. Wanlass, F. 31.. and Sah, C. T., Kanoxvatt logic using field-effect metal-oxide semiconductor triodcs. Digest Intern. Solid-Stale Circuits Conf., Philadelphia, February 1963, pp. 32--33. Lewis Winner, Kew York. 87. Warner, H. 31.. Jr., Comparirig MOS and bipolar integrated circuits. IEEE Spectrum 4, 50--59 (1967). 88. Integrated Circuits: Design Principles und Fnbrieuiion. ( R . M. Warner and J . IS.Fordern\valt, eds.). McGraw Hill, New York, 1965. 89. N:egetier, H . A , R., Lincoln, A. J., Pao, H. C., O’Connell, M. It.,and Oleksiak, It. E.. The \-ariat)le threshold traiisistor, a new elecbrically alterable, nondestructive read-wily storage devicc. Z E E E Intern. Electron. Develop. Conf., Wushington, D.C., 1967, p. 70. IEEE, New York. 90. IVeiiidliiig, M. 5 . ,and Golomb, S. bV., Mutilaminar graphs, Douglas Paper So. 3394. Douglas Aircraft Co., Inc., Santa hlonica, California, 1965. 91. bru. B. P. P.,Dhaka, A. X.,and Chcn, C. T., Picosecond silicon monolithic currerit-s\vitchirig circuit using pn junction isolation and diffused resistors. Digest Intern. Solid-State Circuits Conf., Philadelphia, 1967, pp. 66-67. Lewis IVinnrr. KP\Vl-ork. 92. Yu. K. K., Lin, H. C.. aiid Kwong, K . , The MOS-I%Ta moriolithic MOS-bipolar integrated structiirr. I E E E Intern. Elec. Develop. Conf., Washington, D.C. 1967, p. 20. IEEE, New York.

Aerospace Computers A. S. BUCHMAN International Business Machines Corporotion Federol Systems Division Electronics Systems Center Owego, New York

1 . Introduction . 2. Application Requirements 2.1 Performance . 2.2 Reliability . 2.3 Maintainability . 2.4 Physical Requirements 2.5 Cost 3. Technologies . 3.1 Memories. . 3.2 Circuits . 3.3 Second Level Packaging 3.4 Power Conversion . 4. Current State-of-the-Art 4.1 Spacecraft . 4.2 Ballistic Missile . 4.3 Integrated Avionic Systems 5. Aerospace Computers of the Future 5.1 Performance . ' 5.2 Reliability . 5.3 Maintainability . 5.4 Power, Weight, and Volume 5.5 cost . 5.6 Summary . References

.

.

. .

.

239 241 243 252 257 258 261 262 263 265 267 269 269 270 271 272 274 274 277 278 279 280 282 283

1. Introduction

The basic difference between the aerospace computer and its commercial counterpart is that the criteria for establishing the design of the aerospace computer involve not only the considerations of performance and initial cost but also include stringent requirements concerning reliability, maintainability, and physical characteristics. These five primary factors tend to have an orthogonal relationship. An attempt to improve the utility1 of any of these individual factors 1 The term utility has rigorous connotations which are spelled out by Luce and Raiffa [18]. The implication of this term is that the factors discussed can participate in a

meaningful cost-effectiveness analysis.

239

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A. S. BUCHMAN

often changes one or more of the other four factors for the worse. For example. greater performance inay be obtained at the price of increased cost. increased weight and volume, and decreased reliability. Reliability can be improved either through very costly testing and selection of components or by using redundancy techniques which result in increased weight, volume, and cost. In addition to the orthogonal relationship between the factors, they are sometimes neither linear nor continuous. For example, in some applications the computer must fit into a specific space reserved for it. The utility of volume is, therefore, a constant unless the processor exceeds any of the limiting dimensions, in which case the utility of the entire system drops to zero. In simplest terms. the goal of the aerospace computer designer is to maximize the balance among the primary factors in light of the requirements for a specific application, that is, to maximize the utility. Because of the wide variety of application requirements many unusual techniques have been used in the aerospace industry in order to achieve an acceptable processor for a specific application. Historically, early aerospace computers placed strong emphasis on the use of specialpurpose machines which were highly optimized for each application. Too often. users found that each deviation from the initial mission plan required estensive redesign of the processor. The need for storedprogram general-purpose machines was soon apparent even though such machines led to serious compromises in physical characteristics and reliability. The history of aerospace computers has been a battle between the special-purpose and the general-purpose machine. Some very interesting efforts to use general-purpose machines siipplemented by special-purpose techniques have been pursued. and there is a continuing tendency t o use general-purpose machines which have specific features permitting them to operate in a special-purpose fashion for limited parts of the problem. The functions performed by computers in aerospace applications are similar to those of industrial process control applications. The trends in design in these two fields are closelj- related with aerospace processors frequently leading the way. ,Aerospace processors are now facing some of the same problems which confront the design and use of commercial on-line systems. and in this case aerospace processor design is extracting freely from commercial experience. The intent of this article is to review where we have been and t o look forward to the systems which must be designed to meet ever-growing needs for performance and high availability. First, we will provide an in-depth survey of the current application requirements and will relate

AEROSPACE COMPUTERS

24 I

these requirements to the implementation and organizational techniques used by the aerospace computer designer. A number of specific computers will be described in order to provide concrete examples of the application pressures and of the resulting design responses. The nature of the problems to be solved and the task scheduling environment in aerospace applications is becoming less dedicated than it was a few years ago. The problems facing the aerospace computer designer are now closely aligned with those confronting the designers of air traffic control systems and those which will eventually confront the designer of fast-reaction management control systems. The similarities between future aerospace and future ground-based systems wiII be accentuated as the use of high-availability (failsoft) equipment becomes more common. The major problems confronting the next generation of aerospace computers are as much concerned with machine organization as they are with elegant hardware. This area, to be discussed in the last part of this article, is an area of common interest to all computer designers. It is an area where we look to strong developments in handling system interaction inside the processor subsystem and interaction between the processor and the world which places real-time demands on it. In spite of similarities to ground equipment, the aerospace equipment will continue to be characterized by a premium on physical characteristics such as weight, power consumption, and vibration resistancecharacteristics which are of only small concern in ground-based applications. 2. Application Requirements

This section will provide a broad view df the application requirements imposed on aerospace computers. There is no typical or average set of requirements. Even in missions which appear similar, different groups of mission planners may have reached radically different decisions concerning the uses of the processor subsystem. Especially for the nonexpert, it has seemed desirable to impose some order on this situation. This is accomplished in this section by means of simplifying and combining requirements in order to create seven typical missions. We then discuss our five primary factors in light of these synthetic missions. Table I interrelates the primary factors of performance, reliability, maintainability, physical characteristics, and cost for each of a number of missions. The requirements are often a result of what can be obtained rather than representing an ultimate requirement. For example, deep space vehicles could probably make effective use of much higher performance, and could probably afford the added economic cost, if such

TABLEI MISSION REQUIREMENTS Missiona . . . . .-

...

Performance0 .

- ..~

Ballistic missiles Launch vehicles Unmanned short duration Manned orbitalf Unmanned long duration Integrated avionics system Airborne command and controlf

. -. . .. .

2

4 10 20 1 10 40

Reliabilityc

-

1 x 104 1 x 105 1 x 104 1 x 105 1 x 108 1 x 104 1 x 103

- .. .

Matntainabilityd ..

....

2 3 3

3 3 2 1

Physical characteristicse -

Power -

Weight

. . -. . __... - .

1 1 2 2 3 1 1

2 1 2 2 3 2 1

... .

Coste

Volume ......

..

2

3

1 2 2 2 2 1

2

All estimates for missions using 1967 st,ate-of-the-artequipment. Relative scalc-10 approximates computational capability of IBhl 7090. C MTBF (hours) for system performance of critical functions. 1-In-flight repair or reconfiguration needed, 2-repair or replace faulty modules at forward base, and 3-depot-factory acceptable. e 1-Requirements readily satisfied, 2-requirements demanding, and 3-requirements crucial and difficult to meet. I Independent high-reliability guidance system also available.

-

P

1 2 1

v

3 2

5

, W

:

a Q

repair

I < 9

z

AEROSPACE COMPUTERS

243

performance could be obtained within the reliability, power, and weight limitations. As a counter example, integrated avionic systems probably desire higher reliability but find it economical to occasionally abort a mission rather than greatly increasing the initial cost of the equipments. The missions selected include the suborbital ballistic missile, and a large launch vehicle which is used to boost secondary vehicles into space. The three space missions listed in the table axe not well defined; they may be imagined as being a Mars lander, a satellite interceptor/ inspector, and a manned space station. The integrated avionics system is used on board military aircraft to provide functional interrelationships between the various eIectronic and flight control subsystems. Airborne command and control systems are similar to their ground-based counterparts. The airborne center is usually intended for use on board large transport-type aircraft. In spite of the great differences between these missions and the large range of the characteristics required, there are profound similarities. Except for the deep space mission, it is quite possible for a family of computers using similar implementation techniques t o satisfy all of these missions. To emphasize this similarity, aerospace requirements will be discussed from a general point of view rather than concentrating upon a detailed description of each application. 2.1 Performance Requirements

The matrix given in Table I1 classifies a number of application programs which the computer might be required to perform. Each of these programs is characterized in terms of the demands which are placed upon the processor. The mat,rix is also intended to indicate the applicability of these specific tasks to a number of different missions. Across the top of the chart, each program is categorized by its scheduling characteristics, computation, and input/output (110) requirements. Computation is subdivided into arithmetic operations, logical operations (which include bit manipulation and masking functions), and " records processing " which refers to the capability of effectively moving, rearranging, searching and translating large banks of data. Inputloutput capability is characterized by both the number of sources and the I/O data rates which might occur. These characteristics of the I/O system identify only the real-time inputs. The input/output load which is caused by transferring between bulk store and main store is not included in the estimates given. Application programs performed by the processor are infinite in variety. The categories given on the left side of the Table I1 are arbitrarily established. A major distinction is made between those programs

TABLE

11

CLASSIPICATION OF APPLICATION PHO(:RAMS Applicabili tyd

__

Program charactcriuticu

-

Schcdule Compu- I/O cliaracApplication programs control= tationb trristicc . - __ Vehicle Navigation and guidance Intcrtial/nopplrr/Loran 1 A L Stcllar/xurvey update Iklta-minimum guidance Adaptive guidance Flight control Attitude control Adaptive flight control Management Checkout Monitor and alarm Control

Ballistic Launch -

Long duration -

-

-.

Integrrjtcd avionic system .

. _ . . -

- --

.

p F C

P F

A

L

1

A A

L M

P

A A

M M

P

1

2 1 3

AR A A

L L L

P P F

1

__

Short Manned duration orbit

Airborne command and control

(D

2

1

__

_ _ __

-

P

I’

P P

P

F

P F

P F

P

P P F

P

P P F

F

I x 9

Z

P F

n

p

P

F P P F

P P F

Payload Weapon control Map match navigation Target acquisition Penetration aids Weapon release Experiment control Sequence and control Data collection Data analysis Display Command and control Data entry Data analysis Information retrieval Display Communication control

2 2 2 3

ALR

H

A A A

H H -

2

LR R A

L

1

3 3 3 3 3 1 1

R

P F P

P P

L M

R

L

A R R

-

R

F F P

P P P P P P F

H M L

Schedule control: 1-periodic (cyclic), 2-scheduled demand, and 3-real-time demand. Computation: A-arithmetic, Glogical, and R-records processing. c I / O characteristic: L-many sources, low rates; M-multiple sources, moderate rates; and H-few d Applicability: P indicates present and F indicates future. a b

sources, high rates.

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A. S. BUCHMAN

necessary for the vehicle to operate properly and between the programs which are related to the function of the vehicle’s payload. 2.1 .I Vehicle Functions

The vehicle operations are divided into navigation and guidance, flight control, and vehicle management. Navigation and guidance is the sine qua non of aerospace computers. Surprisingly, in terms of modern processors and current requirements, this is not a very demanding operation. I n the future, there may be some growth in navigation requirements resulting from the use of simplified inertial platforms and improved multiple sensor navigation systems. The guidance function has been simple largely because the vehicles are expected to fly known trajectories, and in most cases, the guidance function merely calculates course errors and generates corrective steering signals. Terminal guidance for space rendezvous as well as reentry guidance is somewhat more complex, but even these calculations have been simplified in order t o make them tractable t o existing processors. I n more advanced missions, the need will arise for on-board calculation of optimized trajectories which will economize on fuel usage or accurately determine time of arrival a t destination. Such programs utilize complex mathematical techniques and will require substantially more complex calculations. This future requirement may create an imposing demand upon the computer’s computational capability. The flight control operations are concerned with the attitude of the vehicle in relation to its flight path. This is a function which has traditionally been performed by analog computers because of the requirement for high frequency response with relatively low precision. During the boost phase of large vehicles, the vehicles are subjected to enormous forces because of aerodynamic loads, fuel sloshing, and reactions to steering forces. These forces, acting on the low flexural stiffness of the vehicles and combined with the shifting of the center of mass resulting from fuel usage, make for great complexity in determining the true vehicle flight path and attitude. Future flight control systems may have to analyze and cross-correlate the data from a number of sensors and perform extensive computations before decisions can be made concerning the actual motion which has been imparted to a vehicle. The need for adaptive flight control systems may very well require that the digital computer participate in flight control operations. If this occurs, another demanding computational load will be given the aerospace computer. [a]. Vehicle management has been primarily an “ add on ” feature where residual processor capability has been used for performing checkout of subsystems and for monitoring the vehicle while it is in operation. It is

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247

the author’s opinion that vehicle management will someday become the most important function for many aerospace computers and the primary reason for their utilization. Multistage space vehicles, 400-passenger aircraft, and supersonic aircraft are extremely complex equipments which are, in fact, made up of numerous subsyst,ems each of them with independent control. As the complexity of these vehicles increases, it becomes more and more difficult for the pilot to participate directly in the monitoring and control of the vehicle. Some of us believe that digital computers will assume most of the routine control functions and that the function of the pilot will be that of a decision maker for problems where there is no preplanned decision. While there are widely divergent schools of thought about man’s role and participation in the area of vehicle management, there is almost no disagreement on the need for aids for the man in the form of automatic checkout of facilities before they are put to use, automatic monitoring of facilities while they are being used, and an alarm system to warn the pilot in event of unusual conditions. The processor load for vehicle management is not really predictable a t this time, but some characteristics of the operation are certainly quite clear. The processor must be able to communicate with a n enormous number of external devices. It must scan many devices on a schedule which is controlled by the program. It must be able to modify the programmed scanning schedule to change scanning rates and to change sequences. The individual computation associated with the scan of each point is almost negligible, but the need to store large tables of constants and scaling factors leads to data management problems. The data tables must, of course, be closely related to the scheduling of 110 activity, and the order of accepting these data and using them must be as easily modified as is the order of scanning points. When deviations are found, the processor must be able to correlate results from related sensors and perform logical decision functions in order to identify the cause of the trouble. If automatic control is to be invoked, the processor must locate the program of corrective activities and direct and monitor their enactment [1,61. The computer for a vehicle management system should have good logical and bit manipulation capabilities. It must handle a relatively heavy I/O activity and must have a rapid and effective means of status switching within the processor. There is a clear need for an executive system to control and schedule processor and channel activity. 2.1.2 Payload Functions Aircraft and space vehicles are merely the means of transporting some working system to a destination. I n the military envhonment, the

240

A. S. BUCHMAN

aircraft may be performing reconnaissance, conveying a weapon system to a target area, or protecting targets from enemy attack. I n space, the payload may include various types of reconnaissancc systems (which include meteorological and earth survey) or it may involve the equipment necessary for sampling and testing the strange environment of other celestial bodies. I n any case, one of the functions of the digital computer system becomes that of controlling the payload system throughout the course of the flight and, in particular, utilizing that system with maximum efficiency at the destination. The best explored and best understood area obviously lies in the area of air-launched weapon systems including air-to-airmissiles and air-to-ground weapons The functions performed by the digital computer include those of target identification, launch control, and weapon guidance. The target analysis and correlation requires that many inputs be obtained from the navigation system. from various types of radars, from infrared searching systems, and from the pilot or other observer. Often the target of greatest interest is equipped to take evasive measures or to conceal itself. W'hen such countermeastires are used, the detection and accurate identification of the target is an extremely difficult task, especially when the launch vehicle is moving a t a very high velocity in relation to the targets which it is attempting to analyze. Decision-making times are very short. and the complexity of the problem is very high. When an aircraft is pursuing a target over unfriendly territory, it may suddenly find that it, itself. has become a target. I n such cases, it must not only be seeking its foe, it must also at'tempt to conceal and to defend itself. The facilities for performing these operations are often referred to as penetration aids. Because of obvious military classifications, it is not possible to explore the countermeasure, penetration aid situation in any detail. Nonetheless, the reader can easily envision that masses of data must be gathered rapidly, analyzed almost instantaneously, and complex decisions must be made without hesitation. Whether the final decisiofi is made by the pilot or by the computor has little influence on the computational load on the computer whose main function is that of performing data collection, analysis, corrclation, and calculation of launch parameters for the air-launched missile. Experiment management on board space vehicles has many of the aspects of vehicle management previously discussed. Experiment management also implies the ability to analyze the results of experiments so that the succeeding experiment can be properly planned. Obviously, there is a trade-off between telemetering the raw data t o ground and awaiting results or doing the calculations on board. I n most space missions, experiments are planned to occur when the vehicle is not under powered flight and the decrease in vehicle-oriented

AEROSPACE COMPUTERS

249

computer load usually frees enough processor capacity to make onboard computation attractive [3]. Aerospace command and control functions are essentially duplications of ground-based command and control which are lifted into the aerospace environment for reasons of mobility or protection. The Airborne VCTarningand Command System (AWACS) is typical of the aerospace command and control. I n 1967, this program had not yet achieved the stage of hardware development but it had been under study and public discussion for over five years. The general concept is that of a large aircraft which can hover near or over a field of military operation. The aircraft is equipped with highly capable radars so that it can directly monitor air and battlefield operations. The radar information, combined with inputs telemetered from various ground establishments may be displayed, analyzed, and used by on-board military personnel in order t o give more effective direction to the course of both air and ground operations. The AWACS aircraft will control the operations of interceptor aircraft. It will monitor the users of the air space for a wide range in the vicinity of the battlefield. I n the event that it detects foes, the AWACS aircraft will be able to direct its own aircraft in order that they may intercept the enemy. The AWACS aircraft will also be able to effectively direct its own strike aircraft so that they may invade enemy territory with minimum risk. The AWACS is not the only command and control system being considered. There are several systems concerned with antisubmarine warfare which must collect, analyze, and display large amounts of information while in flight [16]. The command and control computer is very similar to that used on the ground. It requires a large-scale machine with a fairly versatile input/output capability, the ability to handle and manipulate large files of information, and the ability to do both scientific processing and records manipulation with reasonable ease. I n fact, in order to ease some of the programming problems, there have been numerous suggestions that the aerospace computers should have the exact machine language of its ground-based counterpart. The economic and engineering advisability of exact machine compatibility has not been completely explored, but recently there has been a trend to disregard this requirement and to merely require that the aerospace machine and the groundbased machine must be able to compile data from the same high level language inputs. Aerospace command and control will probably, in the coming years, be one of the most demanding, most rapidly growing, and most vital aspects of aerospace computer usage.

250

A. S. BUCHMAN

2.1.3 Program Organization

The aerospace application differs from commercial usage in that each application program is fully defined and debugged before it becomes part of the operational set of programs. In general, these individual application programs are not subject to change nor arc there additions to the total set during an operational mission. \Vhat is subject to change is the set of programs which will be actlive a t any specific time. The active set will contain programs which are scheduled for cyclic use during a specific phase of the mission. These programs may be called by an executive scheduler as they are required. These programs and related data need not be resident in fast storage provided that the system can accommodate the required transfer rate between primary and secondary storage. The storage problem in aerospace processors is no different from that in commercial applications. That is, a balance must be achieved between the size of resident and bulk storage as determined by the capability of the system to effectively transfer information between these two stores. In addition to the scheduled programs, many important programs are called on a demand basis. Such demands may originate from external sources such as manual display requests and limits switches or they may be originated by another program. As an example, a monitor program may scan inputs on a scheduled basis until an alarm condition is found. This may require an immediate call for an analysis program which may call a control program if t,he analysis indicates an emergency condition. Program sequencing under these conditions is best regarded as a fluid situation with demands originating from schedules, from external soiirces. and from other programs. Each demand must have a priority assignment which can be related to the priority of the active program. An executive system is required to resolve conflicts, to schedule activities, and to allocate facilities. Unlike a commcrcial system, the range of programs which may interact is limited because the set of application programs is fixed and the possibility of their interaction is predictable. Because of these circumstances. some interactions between programs such as sharing of subroutines and of data files can be carefully preplanned. The use of physical facilities can also be assigned with greater certainty than in a commercial environment. The supervisory programs for aerospace online environment can take advantage of these rcstrictions and provide rather. sophisticated control without the overhead burden of a fullfledged operating system. Reentrant code can often be avoided, and file protection and keying can be simplified. Many existing aerospace applications have used separate processors

AEROSPACE COMPUTERS

25 I

t o perform certain functions such as navigatisn and guidance. These missions carry several independent and unrelated computers. Usually, there is good justification for decentralized systems based on reliability requirements for critical functions or, in space vehicles, on the desirability of discarding the electronic equipment after it has completed its useful function. Military aircraft are attempting to provide more meaningful centralization through the use of integrated avionics systems and it is hoped that space vehicles will follow suit. Several multiple computer missions will be described in Section 4. 2.1.4 Input/Output Control

The input/output situation can become quite complex in real-time control situations. First, consider a single program which must call inputs (say, for monitoring purposes). Such inputs may require delays of several milliseconds before the data are'accessible. Since such delays are intolerable, the processor must use the wait time for multiprogramming. Now, should a program initiate an I/O request and then be preempted by a priority request, the input is liable to be received into a storage area which is already in use for the superseding program. I n a multiprogram environment, the possibility of such problems is quite real. The waters are further muddied by the requirements for the system to hpndle unsolicited2 inputs. In a conventional situation, the program issues all calls for inputs and then monitors and controls all data sources through a channel command structure. I n the real-time situation, unsolicited inputs may arise from keyboards, from sensors, or from telemetry systems. One way of handling these inputs is to require the programmer (via the executive) to make certain that commands and buffers are reserved for all possible unsolicited input. Better still, if the data source can provide an arming signal, a priority interrupt can be used to establish the commands and buffer. Unsolicited input obviously will compete with solicited I/O for channel facilities, and the resolution of these conflicts must often call on the priority control system. Let us further classify data sources as tolerant, recoverable, and unforgiving. Tolerant sources are fully buffered, and the input will persist until the channel chooses to accept data from it. Recoverable data such as that from tape stations are subject to overrun conditions. If transfer starts and the channel fails to read a message, the data are lost. Fortunately, when data from a tape, drum, disk, or other recoverable source are overrun, the program may command a re-read and obtain the data at the expense of time and some trouble. Unforgiving 2

I am indebted t o Dr. Talmadge [ 2 6 ] for this interesting term.

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A. S. BUCHMAN

sources send their data only once. If the channel fails to acquire it, the data are lost. Obviously, unforgiving sources must be treated with the highest priority. Unfortunately, unforgiving sources are all too often also unsolicited sources. The input/output control provides a situation analogous to program sequencing. There must be priorities assigned which recognize the nature of the source. Such priorities must often be conditioned by the priority structure of the currently active programs. Input/output control represents a significant control problem unless the channel capacity and buffer structure are adequate to handle the maximum possible input /output transfer load withdut conflict. Such overdesign has proved to be the most popular approach to this significant problem. 2.2 Reliability

I n an aerospace application, there must be adequate computing power to do the crucial tasks a t the precise time they need to be done. For many years the search for acceptable reliability has dominated the thinking of the aerospace computer designer. The initial, and perhaps most significant, approach is to manufacture each component, each part, and each subassembly so that it is very unlikely to fail. Because of increased performance requirements and longer mission duration, it is also necessary to devise systems that tolerate failures. The search for better components and manufacturing techniques will be described in Section 3. Here, we will briefly explore the problems of building processor systems which offer high availability through the use of redundancy or recovery techniques. Reliability. as it is conventionally discussed, refers to the catastrophic or hard failure of a component. I n general, aircraft and space vehicles while under powercd flight will h a w a n intermittent failure rate significantly higher than the hard failure rate. Such failures are a particular problem in the aerospace environment because of mechanical vibration which can cause intermittent electrical connections and because of electrical noise resulting from marginal power sources, from electrical interactions between the computer and other equipment, and from the difficult cabling problems which exist in aircraft and space vehicles. Generally, those techniques which provide failure tolerance for hard failures are also effective for intermittent failures. The converse is not true; rollback techniques which serve no useful purpose for hard failures can reestablish proper and complete operation after an intermittent failure. Because of the high ratio of intermittent to hard failures, the use of rollback (possibly in addition to other types of redundancy) is a

subject worthy of independent discussion.

AEROSPACE COMPUTERS

253

2.2.1 Hard Failures

Failure tolerant systems may use algorithmic switching; that is, components and functions inside the computer are switched a t such a level that the program is not aware that a failure has occurred. There are many elegant and interesting approaches to algorithmic switching. They will not be discussed nor compared here because of the extensive literature available [13, 27, 291. Algorithmic switching has numerous drawbacks. First, the size, weight, volume, and cost of the equipment must grow by the factor of a t least three to four. Second, it is usually impossible to protect every element of the system; therefore, the system is still vulnerable to certain single failures. Third, although some failures will be masked, the actual number of failures that occur in a given period of time increases. Simulation studies have clearly shown that the influence of this fact is to maintain the probability of failure at a low level for some period of time but that the probability of failure then increases very rapidly [24]. Finally, the possibility of a component and its " masking ') component both failing at the same time may become quite high if the reason for failure is in any way associated with a design weakness, such as component overstress or with a peculiarity of other equipment to which the processor is connected. A quite different approach to failure tolerance is taken through the use of building tight, effective, and reliable primary units and then running these systems in parallel with efficient cross-coupling and intercommunication so that, in the event of failure of one unit, another unit may assume the activities. The first major problem with this approach is that of failure detection. Detection can be accomplished by hardware error detectors, by subjecting the results of computations to carefully planned reasonableness tests, or by comparing the results from redundant equipment. I n addition, since a hard failure is persistent, special self-test programs may be used to independently (and postfacto) verify proper computer operation. Hardware error detectors such as parity checkers, error detection codes, and adder function tests require hardware which results in an increased failure rate but which does not contribute toward improved availability. These techniques have not proved acceptable in aerospace computers except for memory parity tests. Many computations are not amenable to reasonableness tests, and these tests are usually so time consuming that they have not proved to be useful. Comparing the results from redundant, although not necessarily identical, equipment provides a powerful means of detection errors. While the hardware

254

A. S. BUCHMAN

cost is high, thtx excess computing power provides a means of maintaining availalility. Programmed self-checks can provide, typically, 8s0, assurance of central processor functions. \Vhen the time delay betuwn failure and detection must be small, the self-test program must be run frequently arid may require a significant portion of the computational pon-t~.At a reasonable iteration rate, such as once each smond. it is possible to check a processor with only a 2-3"; interference with normal computation. typical example of a subsystem switching (failsoft) configuration for a large-scalc airborne and command control system is shown in Fig. 1. This configuration cannot handle the failure i n a manner which is completely transparent to the program. Operations must bc stopped, information must be transferred, corrections must be made and, very often, therth is a degradation in performance after a failure has occurred. The e&c.tiveness of subsystem switching is controllrd by the user and the programmer and is deltmdent on ingenious partitioning of the problem and assignnient of facilities. I t is u p to the programmer t o Imrtitioii and preassign parts of the problem to each processor and to each ~~ieiiwry modulr. and it is not within tlic capabilities of t h e system to restructure itself nor to automatically recover inforniatiori froin the defectix-e unit. I n Section 5 , v-e will discuss the necd for a self-restructuring multiprocessing system Xvliich offers automatic information recovery. 1)espite num~~roiis problcnis, cont empomry aerospace planning clearly indicates growth toward the use of subsystem switching. 2.2.2 Intermittent Foilures

-in interinittc~iitfailurc must I t c regardcd as Iwirig ostast,rophic. A bit chanpcd in a data n-ord. address c1iiiilgt.h resulting in incorrect fr.tc1it.s. or spurious alteration of a bit in an instruction all can (and probabl~\I il I ) rcwilt i n complctc*loss of program validity. Error detcrtion techniqucs are similar to those for hard failures except that wlf-test iwograms are not suitable for detection of intermittent errors In a typical installation. 50-73" ~,of the intermittent failurc mtt. is vestcd in the main store. Storage parity tests will detect perhaps X O " ~ , of the atoragc errors or about -iO-60°,, of all intermittent failurw. Thc reniaindcr of the errors require t hc iise of (presently) unecononiic hardware error detectors. Storage parity checks, combined with some programmed reasonableness tcsts, can dctect pcrhaps 7 5 O 0 of all intermittent failurcs. The use of redundant systenls is currently the most attractive approach to effective intermittent error detection. Given that a failure is detected, recovery is possible through rollback techniques which offer a range of possibilities from a " micro-rollback "

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AEROSPACE COMPUTERS

of repeating the last logical operation to the “macro-rollback” of program reinitialization. A systematically satisfactory micro-rollback requires that the state of every significant memory element (flip-flops as well as main store) be

I

-

4

I6k

16k

4-

16k

Keyboard display ( 4 )

16k

Keyboard display ( 4 )

_ _ Channeladapter

16k

I6k

256

A. S. BUCHMAN

preservation of all states until the new state is verified implies extensive hardurare duplication, complex built in test devices, and greatly degraded performance. A more attractive type of rollback consists of preserving the machine state a t the completion of an instruction and then updating that state only after the successful completion of the succeeding instruction. Such an approach has been implemented on several small drum computers where it has proved to be relatively inexpensive (in time or equipment) t o redundantly store the results of the operation and the machine state a t the conclusion of each instruction. When random access memories are used, there is difficulty in preserving the previous state of the machine. If an operation requires that data be written into memory, it is necessary to write that data into a special location to assure that the information formerly in the desired location will not be lost. When the new result has been stored in its special location, the new state of the machine is considered t o be established. I t is then permissible t o overwrite the desired memory location. If a failure occurs during this operation, the new state is preserved in the special location and can be recovered. Certain machine control words such as the instruction counter must be similarly handled. The difficulties of this sort of operation become compounded in machines which are sophisticated to the extent of using look-ahead techniques and look-back loops. The alternative technique is for the programmer to establish significant self-tests and rollback points so that the program can be returned to an earlier level and data reestablished or interpolated. Such program rollback is commonly used although it requires ingenuity and careful planning to be a t all effective. Figure 2 indicates the events which participate in program-rollback recovery. For a particular application, an analysis indicated 45.5% probability of recovery for a processor without buik-in testing of arithmetic operations and 48.5% probability of recovery for an installation uith such facility. The added hardware complexity for built-in test combined with the load on the system designer and programmer do not make rollback an attractive technique in this application. Some current studies have indicated that the intermittent failure rate will probably be between 0.5-4 times the rate for hard failures. If this is the case, it becomes imperative for the computer system designer to consider a means of building machines which can make automatic corrections without requiring the programmer to configure his problem approach around the need for rollback techniques. In summary, continuously increasing performance requirements and mission duration continue to outstrip the increases in Mean Time

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257

Between Failure (MTBF) obtainable through the use of improved technologies. Failure tolerant systems may use some special techniques in coping with intermittent failures but must resort to very costly redundancy (or less costly redundancy and degraded performance) in order to deal with hard failures. The availability problem still dominates the design of aerospace computers.

FIG.2 . Intermittent error strategy concerning probability of: P O intermittent , failure; P I , hardware detection; PZ, program detection; P3, recovery given program detection; Pq , recovery given hardware detection; Pb , degraded performance given no recovery; and P S, system failure given no recovery.

2.3 Maintainability

One of the major costs of ownership of aerospace computers is that associated with stocking of spare parts, acquisition of special test equipment, and training skilled technicians. In commercial practice the uniformity of equipments and their fixed location leads to a consistent maintenance plan. Each aerospace computer usually requires special parts, test facilities, and skills. Further, the mobility of the vehicles makes it difficult to assure availability of spares or test gear. Finally, repair must usually be performed by personnel of limited capability who have had inadequate training. We can define three areas of interest. Repair on board the vehicle, repair at a forward base or area, and repair a t a well-equipped depot or factory. At first, it would seem desirable to perform all repair a t a few depots where spares, equipment, and good technicians could be concen trated. Unfortunately, the madate for rapid time to repair would then dictate

258

A. S. BUCHMAN

that full spare systems be carried a t forward bases or on the vehicle. The cost of maintaining a dead spare a t the forward area is high; the cost of carting spares around on a mission is almost unthinkable. This situation can be approached through a reasoned and compromised sparing plan or through the design of equipment which is easy to repair and which requires few spares. The latter approach is usually based on the use of low cost throwaway modules. If a large machine can be designed from a limited set of such modules, and if it can be designed to indicate which of its modules are faulty, then such a plan becomes feasible. TABLEI11 MODI'LE SIZESTUDY Parameter Signal pins per card Flatpacks per card= Total flatpacks per computer Total cards per computer Card types per computer Computer power Computer cycle timeb Volumeb Weightb a b

A

B

C

D

34 5 4000 800 25 280 1.5 4.8 2.3

68 17 3500 200 33 245 1.2 2.4 1.7

102 33 3000 90 40 210 1.05 1.6 1.2

172 120 2800 28 20 195 1 .0 1 .0 1 .0

All pin limited. Relative.

A st
Power. weight, and volume constraints vary widely from mission to mission. As shown, in Table IV, power consumption is not crucial in aircraft application where large generators are available. It becomes

TABLE

Iv

POWER SOURCE CHARACTERISTICS" Mission Power source ___

Stored power (Wh/lb) Batteries Fuel cells Generated power (W/lb) Solar cells Nuclear cells a

Ballistic missile

Launch vehicle

Unmanned long

Unmanned short

Manned orbit

Integrated avionics

Command and control

150 -

150 -

20 -

150 350

20 350

-

-

-

-

-

10 30

-

-

10 30

-

-

-

-

See Denington and Moss [ 8 ] and Krausz [ 1 5 ] .

260

A. S. BUCHMAN

considerably more important in a booster vehicle, and it is one of the most stringently controlling factors in the design of a computer for deep space application. Secondary power conversion, a t the low voltage levels used by transistors, is limited to about 65?6 efficiency. Thus, 1.5 kWh of energy must be generated for every one used in the computer. Since it may take another 4-1 kWh of energy to provide the equipment cooling required, 2-3 kWh must be generated for each kilowatt-hour required for the electronics. I n short missions, high capacity battery systems may be used. I n longer missions fuel cells become attractive, but for very long missions solar or nuclear cells become most attractive. A computer in a booster may consume 300 U' for a 4-hr mission. This requires the generation of perhaps 3000 Wh of energy or about 20 Ib of extra weight. A similar computer for a manned 30-day mission would require the generation of about 500,000 Wh if the computer were used continuously. If fuel cells were used, almost 1500 Ib would have to be boosted into orbit. Obviously, as mission duration increases, nuclear or solar cells become more attractive. Clearly, power consumption is one of the most crucial factors in selecting a processor for space applications. Not only should the operating power be low but also power conservation should be effected through the use of low-power u-ait-state operation and the use of processor shutdown between periods of active calculation. For deep space applications, even t,hese techniques are not adequate and generalpurpose computers will not be used until there are significant reduction in circuit and memory power consumption. There are current efforts to introduce limited general-purpose machines into deep space [25]. Power goals for one such machine are 3.25 W operating power and 150 mW standby power with an average consumption of 0.5 W. This machine is general-purpose and stored-program only in a most limited sense. Its few instructions and limited facilities are all configured with an eye on the. power consumption problem. Weight follows the trend of power in being important but not critical in aircraft and boosters and of becoming more and more important in missions where payload is limited. Volume considerations are unique in that the selection of electronic equipment often occurs long after a vehicle is completely designed in its physical characteristics. The designer is often required to provide equipment whose maximum dimensions are such that it can be loaded through the hatch of a submarine or can fit into a specific place that happens to have been left available in the electronics bay of an aircraft. While the absolute constraints on volume do not seem terribly important a t first, they are

AEROSPACE COMPUTERS

26 I

often one of the most frustrating problems which confront the computer designer. For example, in a recent case, there was a requirement to package a number of memory modules and a processor in a box of adequate volume but which had a specific form factor and connector location. As a result of these constraints, certain interconnecting lines within a 2-cu f t box became almost 12 ft long. This, in turn, led to serious signal transmission problems which would not have existed at all with moderate relief of a form factor requirement. I n all, power, weight, and volume constraints represent a unique hazard for the designer of aerospace computers. 2.5 Cost

Costs consist of hardware development, production, and maintenance costs and of software development and operational programming costs. Early aerospace computers were developed for specific missions, and the users often had a " damn the torpedoes " attitude toward mundane problems such as cost. The advent of high production quantities, costeffectiveness studies, and competition between manufacturers has forced the users and the aerospace computer manufacturers to thoroughly restructure their attitudes toward cost control. In early applications which required only a few experimental machines, development costs were of most importance. As the quantity of similar machines ordered increased, these costs became less crucial on a per-machine basis but were still very large in absolute value. It is now recognized that one of the largest elements of development cost is the testing and qualification of the technologies used to implement the processors. Several manufacturers are now using the same technologies in a number of different machines in order to reduce the burden of these costs. Production costs are now crucial. The user who will order several hundred to several thousand identical computers cannot afford to be naive about costs, and a number of recent fixed-price awards have been made only after grueling cost-sensitive competitions. The aerospace computer manufacturer is confronted with the problem of maintaining the stringent quality controls which have been traditional in this industry but doing this on an economic and highly repetitive basis. The response to this requirement has been to seek technologies which are less sensitive to the skill of an operator and to use the same technology and manufacturing techniques for 'more than one processor so that the capital costs for production tooling may be amortized over a wide base. In order to meet cost objectives, manufacturers have developed proprietary product lines of aerospace computers and now offer off-the-shelf computers (or at least technologies and production

262

A. S. BUCHMAN

techniques). This is a radical change from the previous role of the aerospace computer manufacturer who represented himself as being technically skilled, uncommitted t o any proprietary ventures, and willing to do or design anything as long as it was on a cost-plus basis. The costs of maintenance vary widely depending on the number of machines to be used, their deployment, and the user’s maintenance philosophy. Costs which are controllable when only a few systems are located a t well-identified sites become immense when systems are deployed widely and when the user no longer desires to send the entire processor back to the factory in order to have it rebuilt if something is a t fault. Several governmental agencies have requested that processors be built with low cost (under 8100) pluggable elements which can be discarded in the field. These agencies would also like to see the number of different plug-in cards held to a minimum. Such requirements are antithetical vjth those for high reliability and low power, weight, and volume (see Section 3.3). It appears that the next area for attitude restructuring lies in the problems of maintenance and logistic philosophy. Because of the quasi-specialized nature of many aerospace computers, and the unusual situation that a single set of operational programs may be used in a large number of identical processors, users have often felt that the initial cost of programming was merely a development cost which would go away as soon as the operational program was written. Machines which are limited in storage capacity, awkward to program, and difficult to simulate, have proved in several instances to have accumulated programming costs several times the hardware cost. Mission planning is not stagnant, and there is a continual redefinition of the functions to be performed by the processor. Thus, even in ballistic missile applications, the programs are frequently revised. Under these circumstances, the need to develop support software such as effective language translators and efficient simulators has been recognized. Three or four manufacturers have announced product lines of processors each of which offer some level of compatibility with existing ground-based equipment. Such compatibility opens the door to using existing software and to reducing program development and verification costs.

3. Technologies The word trchnology here refers t o the physical materials, components, and techniques which are used in construction of a computer. This section will briefly review currently used technologies and will indicate the expected impact of forthcoming developments. New techniques in circuits, memories, power conversion, and pack-

263

AEROSPACE COMPUTERS

aging are often accepted and used in aerospace equipment before they are applied to commercial equipments. The aerospace industry has provided a primary testing grounds for transistors, integrated circuits, thin film memories, nondestructive read and read-only memories, highfrequency power conversion, multilayer interconnection boards, etc. The obvious explanation for such adventures in an essentially conservative industry lies in the improved reliability and reduced size and weight which makes them attractive in spite of the high cost which is always associated with a developmental technique. One of the dominant characteristics of nearly all improved technologies is that the electrical connections between elements tend toward a higher state of integration. This tends to make them more reliable and more compact. The higher density often reduces electrical loading and shortens signal propagation paths thus leading to faster operation. The high rate of change of current associated with these signals requires that careful attention be paid to the transmission line aspects of signal propagation. Tight physical layout aids effective signal propagation, but it leads to high thermal density and to severe problems in heat extraction. The computer designer must not only be able to generate ingenious logic design, he must also understand transmission line characteristics and appreciate the limitations imposed by heat transfer characteristics. Aerospace computers must usually operate over an ambient temperature ranging from -55°C t o f100"C. Since internal heaters and cooling systems have not yet proven economic, this requires that the components and subassemblies function properly over the range from -55°C (component temperature a t cold turn-on) to 125°C (component temperature a t maximum hotspot). A worst case design which considers primary power supply variations, marginal components, and worst case temperature will result in nominal case noise and timing margins ranging from 2 to 5 times those used in good commercial design practice. The stringent specifications which must be imposed on components tend to limit system performance. For example, in 1966, destructive readout (DRO) memories operate a t 2.5 psec cycle in the aerospace environment and a t 2-4 times that speed in commercial equipment. Nonetheless, because of the requirements of wide temperature range, low power, and safe worst case design, the individual specifications on cores, drivers, and sense amplifiers are more demanding for the aerospace design than those of the commercial counterpart.

+

3.1 Memories

Memory systems present the most severe technological challenge.

Rotating and other mechanical memories have been developed to the

264

A. S. BUCHMAN

point of being reliable, but because of access time limitations random access memories must be used. The aerospace environment requires a memory with low power consumption, the ability to operate with safe margins through wide temperature ranges, and insensitivity to external noise. These requirements have led t o a concentration on the USC of NDRO and nonalterable memories. The KDRO memory is attractive because of the reliability inherent in the fact that a readout does not alter the contents of the storage location. Of equally great importance, the read cycle need not be followed by a regenerate operation and the power consumption of NDRO memories is typically only about one-quarter of that for readlregenerate memories. Cnfortunately, there has not been enough demand nor welldirected effort to produce technologies which provide NDRO characteristics a t a reasonable cost. Usually these memories must be wordorganized, and their writing capabilities are often limited by the nmd for high power and slow operation. The data retention characteristic of an SDRO memory is of little value in a system where an auxiliary memory such as a tape unit is available. With such a bulk store, the contents of an ordinary DRO memory can be reloaded if they are inadvertently altered. The most significant advantage of NDRO memories then becomes the reduced power consumption. A surprisingly large number of applications have taken to using wired or read-only stores for storage of microprogram routines and for storage of certain main programs. In the latter case, there is obvious disadvantage that the program cannot be altered once the memory is built. In spite of this, the assurance that the memory is nonvolatile combined with very low power requirements and moderate cost have made these memories attractive enough to be used in numerous coiltemporary computers. Nemory development is a very expensive undertaking, and the size of aerospace requirements has not yet encouraged extensive independent research for storage techniques specifically optimized for aerospace use. The aerospace industry remains dependent upon new technology developments arising from commercially oriented research. Too often, new techniques which appear attractive for commercial use are not suitable for aerospace use because of high power consumption, limited temperature range, strain sensitivity, magnetic field sensitivity, vtc. Ahearly interest in cryogenic techniques for space applications continues to reappear because of the possibility of direct radiation cooling. but the implementation of practical cryogenic memories remains in the distant future The current commerci,zl interest in cylindrical film techniques is also reflected in the aerospace industry [7]. Until

265

AEROSPACE COMPUTERS

such techniques have proved fully acceptable for field use, main store systems will continue to depend on ferrites. 3.2 Circuits Today the circuit designer may safely begin with the assumption that he will use integrated silicon monolithic techniques. The questions which remain are: How far integrated and what circuit configuration? I n 1962, an integrated circuit consisted of a two to four input Diode Transistor Logic (DTL) gate encased in a can or a flatpack. The silicon chip contained about 12 interconnected components and the delaypower product of the circuit was about 420 x 10-12 W-sec. I n 1966, a typical integrated circuit chip contained about 50-70 circuit elements and provided three or four logical gates in DTL, RTL (Resistor-Tranistor Logic), TTL (Transistor-Transistor Logic), or cs (Current Switch) configuration. Typical delay-power products were on the order of 150 x 10-12 W-sec. Circuitswhich communicate onlywith others on the chip have verylight electrical loading. Typically, the power consumption/circuit of circuits on the chip will be only one-third to one-half that for circuit which go off the chip. As the level of the integration increases, the average power/circuit will tend to drop toward the ultimate goal of about onehalf that which would be required if external interconnections were used. As geometries become smaller and isolation techniques improve, delay-power products should soon decrease to 100 x 10-12. The on-thechip logic, because of its light loading, will operate to average delays of about 2 nsec while chip-to-chip delays will become more a function of loading and transmission time than of pure circuit delay. X substantial increase in reliability is directly attributable to the integration of interconnections. Obviously, there are order-of-magnitude differences of reliability between handmade soldered connections, semiautomatic welded joints, and intrinsic connections within a component. Figure 3 shows a typical two input current -switch emitter-follow circuit. The accompanying table estimates the number of connections which must be made to interconnect four such circuits into a functional Connection technique Automated

Manual

Total

Discrete components

One gate per flatpack

Four gates per flatpack

128

48

80

24

18 9

208

72

27

266

A. S. BUCHMAN

FIG.3. Current switch gate (see accompanying table in text).

unit (say, a flip-flop or a 4-bit output gate). Connections such as compression-welded joints which are made by semi-automatic or automatic machines are referred to as automuted connections. Solder or wire wrap joints are called manual. The table clearly shows some of the reasons for the reliability of equipment which uses integrated circuits and further shows the desirability of higher levels of circuit integration. Both computer and component manufacturers are working vigorously on Large-Scale Integration (LsI) which will offer perhaps several hundred circuits on a chip. The yield of chips with every circuit good would be quite low. Therefore, one of the most attractive approaches is to determine which elements on thc chip are good and to use a computer to generate an interconnection scheme for that chip which will provide the desired function but which will use only acceptable elements. Large-scale integration offers the possibility of functional flexibility combined with an extremely high level of integration offering the consequent advantages of controlled interconnectors and low delaypower product. The failure rate of a chip is not constant regardless of the number of elements on the chip, but it does not increase linearly with the number of elements. According to Lowe and Warslow [ I 7 ] , about 35Yb of the total failure rate is independent of the number of elements on the chip, about 30°b varies as the surface area (or a t about the one-half power of the number of elements), about 30% varies as the number of external connections, and only about 50/, of the failure rate increases

AEROSPACE COMPUTERS

267

linearly with the number of circuit elements. Thus, an increase of circuit elements from 50 to 500 should result' in an increase in total failure rate by a factor of about 1.5-1.6. The failure rate per element would decrease by a factor of about 6-7.

3.3 Second Level Packaging The second level package supports the components ; it also provides the electrical interconnection and the paths for removing heat. Too often a package which is satisfactory in its mechanical, electrical, and thermal characteristics does not provide a level of pluggability commensurate with requirements for spares policy (small, identical, pluggable modules), fault isolation (large, functional, pluggable mckages); or size and weight (no plugs). A recent study is summarized in Table 111. This study was based on the use of identical integrated circuits in each case. The goal was to demonstrate the practicability of using small identical modules in order to ease a severe logistics problem It is clear that the problem of creating an effective parts refreshment plan is a serious one for the aerospace computer designer. One of the most important elements of the second level package is the board which supports and interconnects the circuits. Most aerospace computers try to avoid the use of discrete wire because of the high incidence of bad joints and the possibility of wire breakage. Multilayer interconnection boards can easily provide 12-14 layers of copper embedded in a matrix of epoxy-fiber glass. By etching only alternate layers for signal paths and using the remaining layers as ground or voltage planes, a triplate construction is achieved [ I l l . One advantage of this construction is that crosstalk between signals is carefully controlled and predictable except for that occurring through the voltage planes. By careful decoupling (or the use of circuits which draw constant current) effective circuit-to-circuit isolation can be achieved. I n triplate construction, each signal line possesses a characteristic impedance which permits accurate line termination for optimum signal propagation. Usually, practical impedances lie between 30 and 75 ohms. Because of the high power required to terminate such lines, termination is used only when the line length is long in relation to the wavelength of the propagated signal. One intangible advantage of triplate construction is that the designer can accurately anticipate iia situ circuit performance. Generally, aerospace equipment is not designed to be cooled by direct air flow over the components. Because of the variability of coolant supply and because of contamination considerations, conductive cooling

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is provided by the second level package. Heat removed from components is transferred into structure which can be cooled by air, liquid, or even radiation. Figure 4 shows a hypothetical analysis of the thermal characteristic of a computer with pluggable pages consisting of multilayer interconnection boards supported by a metal page frame. Note that a larger chip dissipating, say, 200 mW, would experience a 40OC rise at the first thermal resistance. Here is a clear indication that Chip

(b)

Metol poge frome

1-i ; ii

Structure

Coolant

FIG.4. Sample thermal analysis. (a) 0.05 W x 20OCC/W= 10"C, (b) 0.05 W x lUOT/\V - 5 " C , ( c )5.OW' x 0.5OCjiV = 2.5'C, and (d) 15OW x O.OS°CjW = 7.5"C. Total: 25°C.

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techniques are going to require strong revisions in second level package techniques. The thermal conduction requirement, combined with the need of withstanding severe shock and vibration, leads the designer toward building massive supporting structures. In order to prevent such structural growth, the second level package must provide rigidity and short distances between mechanical supports. Thermal paths must be direct and well connected. Ultimately, circuits which are small in size, weight, and power consumption will lead toward an effective design. However, larger and more dissipative components cause an almost exponential growth of package size and weight. LSI

3.4 Power Conversion Most aerospace computers are powered from 400 Hz alternating or 28 V direct current sources. Usually, the input regulation is poor, and the source is often noisy, especially with switching transients arising from source control or from switching other equipments on or off. Direct regulation of the input source is ruled out because of transformer size and regulation efficiency considerations, The usual technique is to chop the input into a 50-100-kHz signal, providing most of the regulation by means of pulse-width control. After transformation and rectification, fine regulation can be provided using conventional shunt or series techniques. Large current rectification diodes tend to have close to a 1-V forward drop. If the output voltage is, say, 4 V, the power supply efficiency must be under 80%. I n fact, practical supplies at 4.0 V f2% output rarely achieve more than about 65% efficiency. Three means of increasing efficiency appear possible : (1) higher output voltages, ( 2 ) looser regulation, and (3) better rectification diodes.

The tendency toward LSI and to nonsaturated current switch circuitry eliminates the first two options. Here we have a clear case where improved technologies will directly result in a significant improvement in input power requirements and in cooling requirements for aerospace computers. 4. Current State-of-the-Art

I n this section, we will describe several actual aerospace computer applications which are chosen because they typify current usage. These descriptions may also provide a focus to the material of Sections 2 and 3.

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4.1 Spacecraft

The Apollo mission uses the Saturn V booster. The first two stages insert the vchicle in carth orbit and the Saturn 4-B stage injects the manned capsules into an earth-lunar trajectory. After the vehicle has achieved a lrinar orbit, the Lunar Excursion Module (LEM) separates and descends to the moon surface. After exploration, the LEM powers itself into lunar orbit and rendezvous with the Apollo capsule. Finally, this capsule powers itself t o earth and directly performs reentry and landing maneuvers. ‘I’here is a digital computer ill the Saturn V instmment package which performs vehicle monitoring, navigation, and guidance until trans1 iinar injection is complrtc. This computer is supplied by IBM as is the data adapter which provides selection and conversion of all signals lwtween the processor and other rquipments. The computer was designed i n 1062 and is a serial machine operating at a 512-kc bit rate ming glass delay linczs for register storage. The main store module is a %-bit. 4K word DKO core nieniory. Add time is 82 psec and multiply 328 psec. The circuits are implemented in a hybrid technology similar to the Solid Logic Technology used in System/360. The computer architecturc is simple and direct. The unusual feature is that two-out-of-three voting, implemented at the logic gate level, is used throughout the machine. -4s compared to a simples machine, the coniponent count is increased by a factor of 3.5. A11 main store operations are duplicated in two independent stacks, and in the event of a parity error i n one stack the proper information as obtained from the other stack is regenerated in both. For a 2.50-hr mission, the probability of success of the redundant, system is 29,000 hr compared to 1,383 hr for a comparable simplex systeni. The Apollo vehicle is equipped with a general-purpose computer designed in 1961-62 by MIT Instrumentation Laboratory and nianufact wed by Raytheon. This computer performs navigation and guidance functions on tlir journey t o and from the moon and guides the command capsule during earth reentry. The processor has a 14-bit parallel organization and offers double and multiple length precision facilities. The circuits are integrated monolithic mounted in flatpacks with a n average of about two logic gates per flatpack. The 36K words of the 38K word main store are nonalterable wired core-rope. Only a small scratch pad is alterable. The Apollo computer performs the functions of navigation and guidance, flight control, and vehicle monitoring. Its speed is 23.4 psec ADD and 46.8 pscc h i p y . The computer weighs 58 lb, occupies 1.0 cu ft. and consun~es100 R [ 1 2 ] . The LEM vehicle is equipped with a back-up guidance system which

27 I

AEROSPACE COMPUTERS

provides facility for LEM vehicle control in the event of failure of the primary system. The entire system is being built by TRW Systems. The computer offers a parallel organization operating a t a 1-Mc clock rate. The main store consists of 4K words of 18 bits half of which are wired, nonalterable read-only store. The monolithic integrated circuits are mounted in flatpacks. The computer weighs 32.5 lb, occupies about 0.5 cu ft of volume and requires 90 W power [22]. I n summary, in the Apollo mission the need for multiple processors is dictated by the physical separation of the various vehicles. Because of the requirement to achieve a very high probability of success, each machine has resorted to appropriate reliability enhancement techniques. I n the booster where weight, power, and volume were not crucial, hardware redundancy is used. I n the Apollo capsule, a combination of very tight design, careful component quality control and wired memory are used. (At various times during early mission planning, in-flight repair and later a redundant, standby computer were anticipated. By 1966, based on extensive testing, the plan called for only the one processor.) Finally, in the LEM vehicle, two completely different guidance systems are provided in order to avoid the possibility of mission loss because of a design error or a systematic fault. 4.2 Ballistic Missile

The on-board computer for the Minuteman ICBM supplied by the Autonetics Division of North American Aircraft has undergone a major redesign and retrofit since the initial implementation. The first design (D17B) was specifically a navigation, guidance, and flight control computer. It was transistorized and used a flexible disk rotating memory with a capacity for 2985 twenty-seven bit words. Operating in a serial mode a t a clock rate of 345.6 kc, the processor offered an add time of 78 psec and a multiply time of 1017 psec. Organization and architecture were rather conventional, but the instruction set was quite limited. The second version of this machine had a 6912 word memory, a more complete instruction set, and a larger input/output system. The processor assumed many of the checkout and monitoring tasks which

Machine D17B

X (estimated) D37B

Power (W) 350 700 195

Weight (1b) 61 120 36.5

Volume (cu ft)

No. of individual components

1.6 3.2 0.4

15,000 48,000 5,500

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were previously assigned to auxiliary ground computers. The second Minuteman (D37B) design was completed in 1963, and it was the first large-scale commitment to the use of integrated circuits [ 2 4 , 1 9 ] . The accompanying table compares the first and second machines and projects machine X, which is an estimate of the characteristics of a machine built in the D17B technology and offering the D37B performance. While figures are not available, the potential reliability of the expanded D37B was probably greater than that of the original machine. The Xinuteman application clearly shows the rapidity with which computer functions can be expanded if the requirements for reliability and physical characteristics can be met. 4.3 Integrated Avionic Systems

Military aircraft have usually been equipped with two or more independent navigation systems, separate weapon control systems, specialpurpose alarm and monitor systems, and several communication and display systems. Usually, the crew has had t o monitor each system and to coordinate activities between systems. During 1966, three different aircraft made firm commitments t o use integrated avionics systems which provided centralized management of the on-board electronics. The first of these, the Integrated Helicopter Avionics System (IHAS) developed by Teledyne was based on concepts generated in 1962--63a t the U.S. Naval Air Development Center at Johnsville, Pennsylvania. I t will be used in the Marine Corps CH-46A and CH-53A helicopters. The Army is also currently considering IHAS for its CH-47 and UH-1 helicopters. It is also slated for use in the Army AAFSS helicopter [Sl]. The IHAS computer couples together various specially designed avionic equipments which perform the functions of navigation, flight control, station keeping, terrain following or avoidance, and equipment monitoring. The computer uses digital differential analyzers (DDAS) and a general-purpose processor with plug-in memory modules which are prewired to perform specific functions. The entire airborne electronic system and the computer may be modified in function by adding or removing modular elements as required for the specific vehicle or mission on hand. Manual mode controls perniit specific functions to be bypassed and placed back under manual control. Redundancy is used throughout the system. The DDAS are triplicated, and majority rule is invoked. The general-purpose section uses majority logic and core-rope memories. ln the IHBS application, the computer complex will weigh about 62 lb arid occupies about 1 cu f t of space and requires about 250 IfTof power [Sl].

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The IHAS configuration represents a unique and somewhat controversial concept. About SO0/, of the total computer complex consists of DDAS and other modular computing elements. Twenty percent is a small, central, general-purpose computer, and twenty percent a signal conditioning and transfer unit. To some it appears that the DDA functions could easily be incorporated in a slightly more powerful general-purpose machine and that redundant computers could have been used t o achieve the desired reliability. On the side of the IHAS are the strong factors of an appealing logistic system, a simple fault isolation scheme, and a powerful technique for operating in degraded modes. The ILAAS (Integrated Light Attack Avionics System) was also devised by the Navy for application to the A-7A light attack aircraft [9,20]. It is related to IHAS in concept but, in addition to the functions spelled out for IHAS, ILAAS includes a sophisticated fire control system. Not much information is available on the computer complex but it appears that signal conditioning will be moved out to the various avionic systems and that the central processor will be one or more general-purpose machines. I n mid-1966, the Air Force announced a new integrated avionic system for the F111A (originally TFX). This system, known as Mark 11, may also be used in reconnaissance and bomber missions of this aircraft. The system will provide for accurate aircraft navigation, fire control for air-launched missiles, bombing and gunfire control, communications, automatic terrain following, and friend or foe identification (IFF) [23]. The computer system consists of two IBM general-purpose machines with architecture based on the IBM 1800 process control computer. The processors are monolithic integrafed circuits with an average of about 3.5 logical gates in each flatpack. The main stores are DRO operating a t 2.5 psec cycle providing an add time of 5 psec and multiply of 20 psec. Each processor with 8K words of main store weighs 50 lb, occupies 0.8 cu ft, and uses about 250 W. I n the event of failure of one processor, t'he system can be used in a degraded mode with only one processor active. I n the F111A aircraft, the inertial navigation system is equipped with its own digital computer and in some of these aircraft there may be digital preprocessors associated with the radars. The integrated avionic system represents a first attempt a t hierarchical control structures based throughout on digital techniques. They are intended to add coherence to a complex system, to provide continuous system operation in the event of failure of equipments participating in t h e system, and to permit adequate operation of crucial equipments in the event of failure in the control computer.

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5. Aerospace Computers of the Future Throughout this article, we have identified areas of weakness in aerospace computer design. The succeeding generations of computers must provide an orderly attack on these problems in order to devise machines which offer greater utility; that is, increased performance, improved reliability, easy maintenance, and reduced power, weight. and cost. The areas for improvement are as follows: PerformanceHigher program throughput Lou er control program load Reliahili t y Hard failure tolerance Intermittent failure recovery Maintairiabrlity Greater error detection coverage Finer fault isolation resolution cost Development Product ion Field support Software Operat lorial program development Physical Characteristics Pou er IVeigh t Volume

The tools available to the designer include organizational techniques and improved technologies. If these tools are applied independently to each problem area,, the result tends toward improved characteristics in one area a t the expense of others. The utility of the resulting system docs not change, only the balancr changes. The attack upon the problem areas must attempt to find common solutions which, for example, simultaneously improve both performance and reliability. We will discvss some of the approaches applicable t o specific requirements and will then attempt t o cross-correlate the results. First, we will review each area and discuss possible approaches. Finally, we will project a modular multiple processor configuration which does present a unified attack on a number of these problems. 5.1 Performance

5,I . 1 lrnproved Throughput Processors are clearly showing a greater need to be general purpose in their basic organization. This is required both to handle the variety of programs which must be carried as well as to provide flexibility for

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expansion and change. The rjo systems are tending toward greater independence and toward being fully buffered (logically). Both processor and channel are often configured to achieve a useful level of compatibility with ground-based computers. I n many applications, the computer may spend a large portion of its effort in performing a highly repetitive specialized problem. In such instances, the power of the computational system can be increased immensely by means of adding special-purpose facilities for performing the computation of interest. In performing scientific calculations, throughput improvements ranging up to one thousand times have been achieved by means of supplementing a large-scale general-purpose processor with a small special-purpose processor [lo].Improvements by factors of 2-5 have been obtained in aerospace applications using microprogrammed control. I n these instances, sections of the repetitive program were microprogrammed and treated as special-purpose macroinstructions. These special instructions were chosen to make most efficient use of the processor facilities for the specific task required. I n the same way that special-purpose instructions or hardware can increase the power of the system, special-purpose Ijo systems can be extraordinarily powerful. For example, rather than bring raw data in arbitrary format into the processor, special-purpose I/O systems may collect, buffer, reformat, translate, and do preliminary computations on data before moving it to memory. Further, these operations may be done in an independently programmable stand-alone channel which utilizes a memory share facility. I n such cases, the processor need merely inform the channel of the type of transaction required arid it may then continue with its normal operations while the channel proceeds with the I / O operations. When the channel has completed the transfer, i t will inform the processor that the data are available for further processing. An attractive approach to improving throughput would appear to lie in a microprogram-controlled processor with a reloadable control memory. With careful design, a single processor module could act as either a general-purpose or special-purpose processor or channel unit, depending on the control program in use. Such an approach would aid in reducing initial system configuration costs, would lower production costs, would permit dynamic system optimization, and, as we shall soon discuss, could contribute toward a failure tolerant system. 5.1.2 Status Control I n the real-time environment, there is a need to rapidly switch from one program to another in response to external or schedule-demands. Many of the traditional commercial machines have been very weak in

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status switching capability. Although time share systems and process control computers have exhibited some of the characteristics necessary for status control, this remains the most fruitful area for improvement in computer architecture and organization. One aspect of status control is an interrupt' system which should be able to handle large numbers of external sources. Each source should be individually maskable and the priority of individual unmasked sources should be under program control. The interrupt system should compare the priority of the unmasked interrupts with the priority of the current program and create an interrupt request only if the new demand is of higher priority than the existing program. When a request is honored, the processor should quickly and effectively store all of the status related to the current program and staticize all of the information pertinent to the interrupting program. All of the housekeeping operations concerned with interrupt acceptance and program switching should be performed by hardware. Program streaming is a second aspect of status control. I n the on-line environment, some programs must be performed at particular periodic intervals, others must be performed on demand and others may remain stacked waiting for service. Sometimes, when a program is being serviced, the processor must wait for information to be transferred through the I;O system. The processor should be able to work in a multiprogramming environment where it will stream the programs in order to achieve the most effective utilization of the available facilities. By establishing distinct criteria for program streaming, it should be possible to create a hardware-software supervisory system which could effectively control program streaming with a minimum amount of computer time required for supervision. Facilities allocation is another aspect of status control. I n the aerospace environment. the availability of facilities is often limited. The main store may be small and auxiliary storage quite limited. Displays arid terminals may have to be time-shared. Each program stacked awaiting service has its individual requirements for using these facilities. The effective streaming of programs and the effective servicing of interrupts dictate that the requirements for facilities be considered as each program is accepted for servicing. The limitation imposed by the available facilities may require that the order of streaming or servicing programs be revised by the processor t o make most effective use of the 'facilities it does have available. Status control might be approached in a number of ways. One of these would be to carry special tags with the program request which indicates the priority, schedule requirements, and type of facilities needed. A supervisory program would then inspect the request stream

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and the interrupt status to determine the order in which programs should be run. Once selected, the system would be dedicated to performing this task. A quite different approach would be to design the status switching system to be so effective that the time for switching from one stream to another becomes negligible. I n this case, programs may be entered into the stream in an arbitrary order and serviced on a first-in first-serve basis until either the program is completed or else until it is switched out of the stream because of a higher priority demand arising. The real-time control computer need not be optimized for batch processing, for time share, nor for any of the other broad base of functions required of a truly general-purpose system. The computer can therefore afford to have a control system which is highly optimized for handling the type of status control which we have described. 5.2 Reliability

The suggestions that we have brought forth in the section on performance all indicate larger, more complex, and more sophisticated processors. The approach toward providing adequate availability must pursue both the paths of improved technologies and of improved system organization. Further, systems must be designed in such a way that they can recover in an orderly fashion from transient errors. The conventional processor organization must be considered as having failed if any component of the system fails. Such a computer may use internal redundancy to achieve higher reliability. For reasons described in Section 2.2.1, this approach appears less attractive than that of multiprocessing. The term multiprocessing is used here to indicate a system made up of multiple memory, processor and channel elements which are interconnected and configured so that control is distributed and is fully viable regardless of loss of parts of the system. It should be emphasized that the use of a multiprocessing technique is not suggested for the purpose of increasing performance per se but rather for the purpose of increasing machine availability. When failure occurs in a multiprocessor, there is information in memories or in the processor which is lost. If this information is not retrievable through programmed means, then the multiprocessor is little better off than the uniprocessor. An obvious area for further work and improvement lies in the area of automatic hardware rollback. Such a system would periodically (perhaps a t the entrance to each STORE instruction) preserve the entire state of the system in more than one place so that any failure which occurred during the processing of the succeeding instruction could be automatically corrected.

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The goal of achieving high availability and the means of being able to configiirc a system with arbitrarily high reliability appears to be tractable to the use of multiple processors with intercommunication and switching means. The modular reconfigurable processor and the facilities allocation system described earlier provide a means of attacking the reliability problem. Two major problems must be solved: distribution of control functions and recoverj- of data. Obviously, the control function must be viable even though units are lost,. This indicates that control must be distrihuted and redundant. There has been little significant accomplishmcvit in this area except perhaps in the FAX Air Traffic Control System 12, 281. Recovery of data is an equally important problem which seems to be approachable only through the means of redundant storage of nonrecoverable data. Designation of such data (and its subsequent recovery) may well lead to a n extensive programming problem unless a better solution can be found. 5.3 Maintainability

A high availability failsoft system depends upon error detection followed by reconfiguration which switches the faulty module out of the system. Recovery techniques then permit the remaining modules to continue to function although in a degraded mode. The very act of reconfiguration implies that the module containing the fault has been identified and that it can be electrically disconnected from the system. If the faulty module is also physically removable from the systcm, then the maintenance function is inherent in the design. Figure 5 diagrams the strategy involved in error detection, fault isolation. module reconfiguration, recovery, and repair. A detailed analysis of a system consisting of two processor modules, two channel modules. four lGK word memory modules, and four power supplies modules has been analyzed with the results given in the accompanying table.

Tests

Real-time On-line Off-line

Cumulat i \ e probability Cumnlative probability of error detectioii of module isolation (OO)

("0)

70

65 77 92

84

96

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Ll Error

p

real-time tesis

c

0

P

tests

r

-

c 0

L

O 0

..

Yes

N~ -

Isolate by on-line tests

No

Isolate by real-time tests

tests

-

-

T

Yes

-

lsolote by off -line tests Yes

-

Manual isolation

41

T

I

M ()

L

0 0 >

2

\

s

P

Programcontrolled reconfiguration

(SCP) reconfiguration

I

._

0

0

Q

@ I

L

(z

Remove and replace unit

Manual

I

detected

Repair and

Recovery Y

FIG.5 . Availability-serviceability strategy: M indicates manual intervention.

5.4 Power, Weight, and Volume

The continuing pressure for decreased power, weight, and volume for a given performance must be met primarily through improvements in

technologies. Improvements have been occurring a t astonishing rates and probably will continue into the foreseeable future. For example, the reduction in weight and volume between subminiature vacuum tubes and transistors will probably be achieved again through the advent of LSI, multilayer conductor structures, and better thermal and electrical packages. Main stores and power supplies have also drastically decreased in size and weight, and the use of film memories with electronics integrated on the planes will further decrease the weight and volume required.

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Power has been rapidly decreasing. In circuit technologies, power delay products have dccreased by a factor of five from 1960 to 1966 and the use of smaller geometries combined with more circuits on a chip promise further substantial decreases. The power consumption of memories is reduced by means of designing the circuitry so that the st’andby power is low and by decreasing the power needed to access or t o m i t e il bit of information. The typical characteristic for an aerospace memory in 1960 is 21 pW;tllbit accessed and for a comparable memory in 1966. 7 p\Y:bit accessed. The use of NDXO memories which has bwn mentioned as being desirable because of their ability to resist transient errors is also recommended on the basis of the fact that since SDRO memories do not require information regeneration, the power to access a bit is very low. The high 1est.l of integration which is being achieved tends to simplify the signal transmission problem which is one of the most crucial considerations in designing a contemporary computer. Such integration also tends to automatically achieve a much reduced volume. Because of the rapid reductions in size. the pou-erlvolume ratio (power density) is rapidly increasing. Problems of power estraction appear to be almost antithetical to those of signal propagation. Electrical signals require a high degree of isolation from each other and from all other elements. Power extraction requires high conductivity and connectivity between all paths. Presentday integrated circuits tend to move their signal and their power over the same path: that is. in many of the integrated circuits, power is conducted from t hc flatpack into t h o midtilayer signal paths. Thc powcr must then be separated from the electrical signal before it can be mmox-ed through conductive members. It appears that the required ~olut~ion to this problem lies in a circuit where the signal and power are separated at the substrate and that they are moved into different paths. Once this is accomplished. the problems of liquid or evaporative cooling beconic much simplified and may provide adequate solution to the power extraction problems. In suniniary. w i g h t and volume seem to be relatively controllable problvms. but power presents a twofold problem : one in providing significant power reductions for machines intended for space applications. and the other in effectively extracting power from a very dense imckage.

5.5 cost Cost is being recognized as a much more crucial consideration than it has ever been before in the aerospace industry. Development costs are being attacked from the basis that large portions of the cost reside

AEROSPACE COMPUTERS

28 I

in developing and qualifying a technology which is suitable for the aerospace environment. When such a technology has been established, it must be spread over a broad base. This is achieved partially through almost universal acceptance and resulting high usage of components such as integrated circuits and fiberglass-epoxy laminated boards. It is also being attacked by various firms which are attempting to use the same technology for a large number of machines. The hardware production costs are similarly being attacked through the attempt to utilize a given manufacturing technique on a large number of machines in such a way that effective tooling and automated test systems can be amortized. Many of the features appearing in new machines and which are recommended here for future machines tend to provide structures which are denser, more highly integrated, and more difficult to repair. As a result, the need to have machines which can be repaired by unskilled people, parts which can be easily changed and thrown away in the field, appears to be antithetical to the trend of the technologies. The inevitable result is that machines must be replaced as entities in the operational environment and returned to some higher echelon 01 even the factory for repair. The logistics presented by this situation provide untenable expenses in many situations. The maintenance, repair, and replacement policy becomes a major consideration in choosing the level of redundancy, the modularity of structures, and the asynchronous coupling between various parts of the processor system. By juggling these factors, the designer can break the system into modular packages which are removable and field replaceable if the failure can be isolated. Because of the complexity of newer machines, failure isolation cannot depend on highly trained technicians. Automation aids must be supplied which can perform tesh of the machine and can isolate failures t o a specific replaceable part. This requirement has not yet been adequately met by industry. It seems clear that there will not be any significant amount of programming performed on board aerospace vehicles. On the other hand, the number of programs which must be carried in the vehicle is going to continue to increase in quantity and size. Each of these programs must be written and fully debugged in a ground facility. Debugging must assure that the program will work in the object machine with all valid data sets and with the operational storage and input/output configuration. I n the past, such assurance has been provided by means of tedious simulation studies. As the problems become more complex, more time dependent, and more under locally generated control, the realism of such simulation becomes suspect. I n the future, programming

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must he wrified by having a direct correspondence between the host inachinr iisrd for program development and the object machine which is used during the mission. There is a clear indication that there must bc a compatrhilitg hetween these machines. This compatibility should be such that thc machine language tape for use in the object machine can I)(* dirwtly verified on the host machine. This r(quirement will pro1,abIy he compromistld to the extent that the object machine utilizes specializrd processor and channel facilities as drscrilwd al)orv. I t will I)r further compromised by the need for sipnifiritnt iniprovcments i n status control systems. Therc is an obvious area for softwarc tlcvt~lol~ni~nt to derive a new approach to programs which can authcwticatc. object programs using available ground base equipment. Software development and programming costs are being recognized as )wing major elements of cost. and many manufacturers are now attempting to supply a significant software package to support their product. In order to spread the cost of siich a package. several of the manufacturers are attempting to build modular machincs which share architectnrr. at least i n a unilateral if not a full bilatcral direction. The availa1)ility of such software packaging grvtttlv assists the problctn of creating programs. but it does not fully satisfy the need for a really effective means of verifying the object language in a ground-based machine. Thc time-dcpendrnt peculiarities of the aerospace system always result i n the need for the programs to be run under a monitor or quasi-simu1;ttor. \Yhen operating in such a system, program verification is slow. sometimes difficult to interpret. and always has some element of nnctbrtainty .

5.6 Summary Historically, aerospace computers have been venturesome in the use of new technologies and in reliability enhancement. They have been eonservativr and at times backward in matters of architecture, software, and cost control. The most interesting organizational feature of aerospace computers has Gcxm the combination of general-purpose machines which can perform some operations in a spccial purpose mode. X s tht. commt~rcialuse of real-time control increases. there is a greater focus of attention on the aerospace computer in hopes that new ideas with coniniercial-iridastrial applicability will first be explored in thca aerospace industry. I n the areas of technology. there is little doubt this will be true. Large-scale integration is under current exploration, and devclopmental equipment using u p to 500 gates/chip will be available in the late 1960’s. lmprowd second Iercl packages, low-power NDRO

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memories, and alterable control memories will all become available in the next few years. I n spite of these advances, the greatest area for improvement appears to lie in the use of a modular multiple processor system such as that hypothesized in Fig. 6. Storage pool

1 Reconfigurable processor/ channel units

110 devices

FIG.6 . Future aerospace computer system organization. Features: modular system configuration for performance and/or reliability; high performance via reconfigurable processor/channel unit,s; low control load via hardware-software status control system, dynamic optimization of performance via reconfignration; dynamic reconfigiiratioti of facilities to compensate for failure; built-in dat,a recovery control; fault isolation to main store module, processor unit, or device; control of development, production, and field support costs via multiple use of elements; and control of software and programming costs \via conipatibi1it.y with host machine.

The configuration shown presents a, unified approach toward the satisfaction of interacting requirements. It uses the concepts of modularity, cooperating multiple processors, and microprogrammed control to provide improvements in performance, reliability, maintainability, and cost. This example of an advance computer organization highlights the fact that new organizational concepts will be as important as new technologies in the next generation of aerospace computers. REFERENCES 1. Alilyunas, P., Checkout; man’s changing role. SpacelAeron. 44, 66 (1965). 2. An application oriented multiprocessing system. I B N Systems J . 6 78 (1967).

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3 . Bargellini, P. L., Considerations on man versus machine for space probing. Advan. Computers 6 , 195 (1965). 4 . Blair, J., Lovingood, J., and Geissler, E., Advanced control systems for launch vehicles. Astronaut. Aeron. 4, 30 (1966). 5 . Boehm, B. \V., Prospects of a space-based cryogenic computer, Rand. Mem RM-5002-PR (1966). 6 , Buchman, A., Klarman, K., andMatt.hens,C., Digital computer control of an adaptive space \,chicle. USAF Tech. Doc. Rept. AL-TDR-64-62, 1964. 7 . De\velopment of a low-cost medium-speed mass random-access memory. Tech. Rept. So. RADC-TR-66-814,(1967). 8. Denington, R. J., and Moss, T. A., Suclear power supplies. SpacelAeron. R Br D Handbook 44, 115 (1965-1966). 9. England, W. A. , and Stanton, T. S., Advanced aircraft computers. Space/ Aeron. 44,69 (1965). 10. Estrin, G., Bussell, B., and Bibb, J. I., The UCLA variable structure computer system. Proc. Workshop o n Computer Organ., 1962, Spartan Books, Washington, D.C., 1963. 11. Grimmer, R. C., Interconnecting high speed circuits with multilayer boards. Computer Design 6 , 36 (1967). 12. Hopkins. A. L., Inside the Apollo computer. Electronics 40, 109 (1967). 13. IEEE Trans. Reliability 12; 13; 14; 15 (1963-1966). 1 4 . Klass, P. J., Minut,eman guidance built for long life. Aviation Week & Space Technol., November 5, 1962. 15. Krausz, A., Son-Xuclear power supplies. SpacelAeron. R & D Handbook, 44, 113 (1965-1966). 16. Leary, I?., Tactical command and control. SpacelAeron. 45, 95 (1966). 17. Lowe, R. R., and Warslow, M., The Reliability of Ground-Based Digital Computers, Rand Mem. RM 4511--4RPA, June 1965. 18. Luce, R., and Raiffa, H., Game Theory, Wiley, Sew York, 1957. 19. Miller, B., Xicrocircuits boost minuteman capability. Aviation Week & Space Technol., October 28, 1963. 20. Miller, B., Key to future of ILAAS. Aviation Week & Space Technol., February 22, 1965. 21. Miller, B., Integrated helicopter avionics system. Aviation Week & Space Technol., June 21, 1965; June 28, 1965; May 16, 1966; December 4, 1967. 22. Miller, B., Abort backup for LEM. Aviation Week & Space Technol., January 10. 1966. 23. Miller, B., Wide use of F-111-4 Mark I1 advionics. Aviation Week & Spuce Technol., June 6, 1966. 24. Rozenberg, D. P.. and Ergott, H. L., Modular redundancy for spaceborne computers. Proc. Spuceborne Computer Eng. Conf. October 1962. 25. Stabler, E. P.. and Creveling, C. J., Spacecraft computer for scientific information system. Proc. IEEE 54, 1734 (1966). 26. Talmadge, R., IBM SGC, Los Angeles, California. 27. Wilcox, R. H., and Mann, W.C . . ed. Symp. Redundancy Tech. Computer Syatems. Spartan Books, Washington, D.C., 1962. 2 8 . Wood, J. R., The 9020: A modular multiprocessing system for NAS. IBM Syst.ems Develop. Div., Rept. TR 21.187, 1965. 29. Yovit,s, M. C., and Jacobi, G. T., ed., Conf. SeIf-Organizing Systems. Spartan

Books, 1902.

The Distributed Processor Organization*

L. J. KOCZELA Autonetics Division North American Rockwell Corporation Anaheim, California

1. Introduction . 2. Parallelism . 2.1 Introduction and Definitions . 2.2 Assignment and Sequencing of Parallel Operations 2.3 Application of Parallelism Studies 3. Development of the Distributed Processor Organization 3.1 Parallel Computer Organization Development . 3.2 The Distributed Processor . 4. Architecture . 4.1 Cell States . 4.2 Cell Identification . 4.3 Source of Instructions 4.4 Source of Addresses . 4.5 Source of Data . 4.6 Execution of Instructions . 4.7 Input-Output . 5. Failure Detection and Reconfiguration . 5.1 Failure Detection Methods . 5.2 Reconfiguration . . 6. Cell and Group Switch Design 6.1 Processor Features of the Cell . 6.2 Functional Description of the Cell . . 6.3 Group Switch 7. Communication Buses 7.1 Intercell Communications . 7.2 Intergroup Communications . 8. Software Analysis . 8.1 Group Executive . 8.2 System Executive . 8.3 Cell Executive References

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* This work was sponsored by the National Aeronautics and Space Administration under Contract NAS 12-10s. 285

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1. Introduction

Thc purpose of this article is to present the results of a research study of an advanced computer organizational concept entitled ‘‘ distributed processor ” [Y]. This organization evolved from a study of advanced multiprocessor organizational concepts for future space mission applications [Y]. The time frame of application was 1980. Therefore, a representativc futurc space mission was selected as a base for computational reyuireniciits and large-scale integration (LSI) semiconductor technology was txtritpolatrd to the time frame of interest to form a base for the organizational studies. The distributed processor organization was thereby designed to provide general-purpose computing and a very high tolerancc of failures while taking advantage of future large-scale integration trchniques. In addition, an easily expandable or contractable system was desired to readily meet a variety of computational requirements. The organization should have a wide variety of future generalpurpose computational applications even though it was originally designed for a spaceborne application. A brief summary of the requirements and technology investigations is given helow. analysis of a representative future space mission, in particular. a manned Mars Lander mission, was conducted. The major computational requirements considered were storage and speed. Storage capacity requirements in the computer varied as a function of mission phase with a niaximuni of approximately 30,000 words and a minimum of approximatel? 22,000 words. Similarly, the speed requirements range from approximately 1,500,000 t o 300,000 operations (such as add) per second. These requirements were based upon conventional present-day statr-of-the-art aerospace computers and assume a 16-bit word length. The widely varying nature of the computational functions demands a general-purpose computer organization. I n addition, these functions result in a widely varying set of computational requirements as noted above as a function of mission phase. The particular application considered also resulted in two additional computer requirements. The f i s t was a reliability requirement. It was desired to achieve a given probability of success. The second was a reconfiguration time requirement. It was desired to reconfigure in 0.1 sec. Reconfiguration is defined here as the I)rocess of having a computational function mechanized and performed correctly in the computer system after some failure in the computer system. Actually, the capability of meeting the reconfiguration time requirement determines the probability of success. This latter requirement is determined by being able to reconfigure a subset of the total computational functions in the computer system. The subset is a critical portion of the guidance and navigation functions performed during very critical phases of the mission such as atmospheric entry.

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I n addition to defining the requirements, it was necessary t o define the technology to be considered as state-of-the-art for the time period of interest before proceeding with an investigation of the organization. Although the time period of the mission considered was in the 1980’s, it was necessary to have the technology available to hardware designers considerably before the missions are actually flown. Therefore, technology was projected 10 years from the present. The two leading device oriented technologies that lead the developments in LSI today are ( 1 ) bipolar and (2) metal oxide semiconductorfield effect transistors ( M O S - F E T ) . Bipolar devices offer a speed advantage over MOS-FET’S, while MOSFET devices offer the advantages of a simpler manufacturing process, less area for the same function, and lower power dissipation compared to bipolar [ 1 2 , 1 7 ] .Metal oxide semiconductor-field effect transistor technology was selected for investigating the organization. One particular batch fabrication technology presently being developed bearing important implications on future LSI is the heteroepitaxy of thin semiconductor films in which active devices are fabricated. A particular example is the growth (heteroepitaxy) of single crystal silicon-on-sapphire (sos)by chemical vapor deposition. Application of this technology to MOS (MOS-SOS) is presently in the research and development phase. Extrapolation of present results was conducted, and i t was determined that one can reasonably expect large wafers (approximately 1.5 in. in diameter) with 105 or more devices in the technology time frame considered. The development of high density LSI arrays for use in near term and future computation systems will make the processor or arithmetic and control sections of computers increasingly simple in comparison to the memories. This trend is evidenced by the fact that semiconductor memories are being investigated for the main memory in future computation systems [14]. These memories may use many semiconductor chips, whereas a processor may only use one or two such chips. As the processing of semiconductor chips matures, the reliability of the one- or two-chip processors will also be significantly greater than that of the magnetic or semiconductor memory. It is clear that there is a need for new computer organizations which take advantage of LSI technology in order to offer enhanced computation system features. One such organization is the distributed processor discussed here. This organization may be considered an array of semiconductor wafers or chips with a large part of each wafer devoted to memory and a small part of each wafer (less than one-tenth) devoted to processing. The organization thereby integrates processing and memory onto the same wafer or chip and uses a number of these chips to form the organization. Such a structure uses a small hardware increase over a conventional organization in order to offer increased reliability, flexibility, and execution speed for certain

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types of computations. These advantages are explained in later sections of this article. Figure 1 contains a block diagram of the organizational concept. The organization consists of a number of identical cells interconnected in a particular manner. Each cell consists of a general-purpose processor section and a small amount of memory (512 16-bit words) on a single LSI wafer. The cells are divided into groups (four groups of 20 cells each are considered for the spaceborne application), and these groups are connected by an intergroup bus for communication. Within each group, Nelghbor cornrnuncotion

Y

P

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1 - 0connection pone1

Inter

I I

Input output

devices

FIG.1. Distributed processor organization.

the cells communicate with each other by an intercell bus and by neighbor communication lines. Each group has one cell designated as a controller cell. The remaining cells are operated independently of the controller cell. The organizational concept exhibits the capability for computational parallelism since the cells may be operated simultaneously and in parallel. An important distinction between this organization and previously developed highly parallel organizations is that the cells may be operated independently or dependently of the controller cell. This means that there exists the capability for both global control or local control

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of the cells which can result in efficiently mechanizing parallel computations as is developed in Section. 2, This organization achieves high reliability by graceful degradation; i.e., as cells fail, either spare cells simply replace the failures or, if no spares are available, only a small percentage of the computational power is lost. Increased flexibility is inherent since the system easily expands and contracts in small increments to meet requirements. The organization is considered somewhat technologically dependent since it is desirable to have each cell manufactured on a single wafer, thereby resulting in one identical wafer throughout the entire organization. However, this is not a rigid restriction since more than one wafer could be used to construct a cell. Section 2 presents a discussion of parallelism within computations in order to place in proper perspective the parallel computational capability of this organization. The development of this organization and its detailed architecture is given in Sections 3 and 4. Failure detection and reconfiguration procedures are outlined in Section 5. The design of the cells and the communication buses is discussed in Sections 6 and 7. Finally, Section 8 presents some preliminary considerations of the software portions of this organization. 2. Parallelism 2.1 Introduction and Definitions

Definitions of parallelism are given below, followed by a discussion of the methods and procedures to evaluate parallelism within a set of computations. Parallelism is investigat,e'd in order to provide a basis for evaluating various parallel or distributed computer organizations. In particular, the amount of parallelism that may be utilized is evaluated and the methods of making use of parallelism or assigning parallel operations are investigated. The spaceborne application for which the organization was designed was evaluated to determine the parallelism inherent in its computational functions. Results from this evaluation are also presented. Two types of parallelism, applied and natural, are defined as follows. Applied parallelism is the property of a set of computations that enables a number of groups of identical operations within the set t o be processed simultaneously on distinct or the same data bases. Natural parallelism is the property of a set of computations that enables a number of groups of operations within the set t o be processed simultaneously and independently on distinct or the same data bases. Applied parallelism is a special case of natural parallelism since the naturally parallel Operations could be groups of identical operations.

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The distinction between the two types is introduced since it has important implications with regard t o computer orgariization. The two types of parallrlism are illustrated with the simple example in Fig. 2. The example is the computation of the expression

A / X + SIX ACI’

= 2.

Figure 2 illustrates how the expression is computed in a sequential manner. The numbers above each circle indicate the time that might be required to compute each term on a conventional sequential computer ( I S ) . If applied parallelism were capable of being taken advantage of, the computation on such a machine would take place as illustrated in Fig. 3. The term AIS in this figure is the ratio of the time required on the machine with the capability for executing applied parallelism to the time required on the sequential machine. It should also be noted that a degree of applied parallelism of 2 is utilized in Fig. 3 (this occurred during the parallel computation of A / X and B / X ) . If the capability for taking advantage of natural parallelism is now introduced. then the computation may take the form illustrated in Fig. 4 It should be noted that the term C Y may now be computed in parallel with A1.Y and B X. The total computation illustrated by Fig. 4 may be classified as ut lizing natural parallelism ; however, it should be noted that a subset of this may actually be classified as applied parallclism as indicated by thv dashed lines. Therefore, the cornputation may bc said to consist of applied and natural parallelism. This combination map be referred to as total parallelism. Utilization of total parallelism results in the reduction ratio T / S in Fig. 4.With this introduction to the notion of parallelism. some of the problems in attempting to analyze a set of computations to determine the utilization of parallelism will be given next. 0 167

FIG.2. Sequential steps in computation.

FIG.3. Applied parallelism in the computatioii.

29 I

THE DISTRIBUTED PROCESSOR ORGANIZATION

T -I S'2

FIG.4. Applied and natural parallelism in the computation.

2.2 Assignment and Sequencing of Parallel Operations

It can be seen from the above simple example that an important part of any parallelism analysis is the formation of computation graphs to study the degree of parallelism utilized and the inherent reductions in computation time. Unfortunately, the graphs are quite complex to construct for problems of practical interest. It is shown below that the problems encountered in forming the graphs are analogous to those studied in assembly line and job shop scheduling theory. This particular topic is treated first before discussing the over-all problem of analyzing parallelism and applying it to the spaceborne computational problem. An important consideration in the analysis of parallelism is the degree of parallelism utilized and the computation time reduction or effectiveness of the parallelism." I n determining this effectiveness of parallelism one approach used assumes a certain degree of parallelism and then determines the minimum computation time by reordering the computation graph to make use of the parallelism. Following this procedure a curve of the degree of parallelism vs computation reduction ratio is obtained. This problem can be approached another way to arrive a t the same curve. This alternate approach assumes a certain computation reduction ratio and solves for the minimum degree of parallelism required to achieve this reduction ratio. These two approaches of obtaining the ('parallelism curve are analogous to problems proposed and studied in the area of operations research. The first approach, determination of minimum computation time given a degree of parallelism, is analogous to the problem encountered in job shop scheduling or assembly line balancing; namely, given m jobs or tasks to be performed by n men or assembly stations, determine the sequence or assignment of the jobs or tasks that completes them in the shortest time. The second approach is analogous to another job shop scheduling or assembly line balancing problem; namely, given m jobs to be performed, ('

))

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the total time spent by any one man or a t any one assembly station is not to exceed T,what is the sequence or ordering of the jobs to minimize n the number of men or assembly stations required? Considerable research has been carried out in this field of operations research, and several references [2, 3, 5-7, 10, 131 were reviewed to determine if any of it could be extended to this investigation of parallelism. Some significant points from the references are discussed below. The following problem is considered by Hu [ 5 ] :n jobs with partial or total ordering restrictions are to be performed, if all jobs must be completed by time T ,arrange a schedule that completes them with the minimum number of men, or if n men are available, arrange a schedule that completes all jobs a t the earliest time. It is asspmed that all jobs require equal time to complete by any man and that any man can do any job with the capability of immediately starting another after finishing one. Under these assumptions a n analytical expression for the lower bound on the number of men is found. A brief description of how this lower bound can be found is given here. If

+

is true then it is impossible to complete all jobs with y men in a c units of time; where y is the number of men, p ( a 1 -j) is the number of nodes on the graph with ai = a 1 -j,a6 = Xt 1, where X iis the length of the longest path from the node Nt to the final node in the graph (it is assumed that each branch takes an equal unit of time, 1, to complete), a is the maximum X i over the entire graph, c is the non-negative integer, and y* is a positive integer such that

+

j=l

+

+

j=l

Basically, the lower bound (y) is found by labeling all the nodes of the graph with their appropriate p ( a l ) ,determining c from the allotted time T to complete the tasks (c corresponds to a time interval that may be added on to the shortest possible time to complete the tasks, thereby giving the allotted time T to complete the tasks, c units of time greater than the minimum), and then determining y* for Eq. (2.1) by solving Eq. (2.2). Unfortunately in using this algorithm to find the upper bound on the minimum number of men, the ordering restriction that the graph be a tree‘ must be imposed. With this restriction, the minimum is given by 1 A tree may be defined as the ordering restriction that the directed graph has no nodes which contain more than one successor node.

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m, where m is the integer satisfying m - 1< 1 / ( y *

+ c;=Cy’p(cz + 1-j) 5 m j=1

(2-3)

and where the same definitions apply. The restrictions (1) that each job requires an equal amountof time and ( 2 ) that the ordering of the graph be a tree are severe in terms of attempting to extend this work to parallelism studies of computations. It may be possible to reduce computational graphs to the microoperation level where each job takes an equal amount of time. For problems of reasonable complexity, however, this can become a monumental task. The restriction of a tree limits the type of graphs analyzed. Unfortunately, most of the computations of interest do not form trees. This is because the intermediate results are often used at many points within a computation. Nevertheless, this work has been pointed out here since it represents the only pure analytical approach found in the literature to solving the assignment and sequencing problem. If the first restriction (equal lengths of time) can be reckoned with, it does offer a lower bound for any computational graph. Evaluation of the remaining references and others showed that there are no general solutions to the optimum sequencing problem applicable to the study of parallelism here. The only solutions to the problem are generally very lengthy computational programs considering all permutations of the solution space t o find a minimum or computational algorithms to arrive at a suboptimum solution by restricting the solution space. Analytical procedures are nonexistent for general solutions.

2.3 Application of Parallelism Studies Two types of parallelism are of interest as noted above: applied and natural. The goal of these studies is to determine the effectiveness of parallelism on a given set of computations. This “effectiveness ” is determined from a curve of degree of parallelism utilized versus computation time reduction ratio. The detailed procedures to be followed in analyzing a given set of computations were investigated [ 8 ] . The procedures are very complex and only a very brief summary is given here. Solution of the computations on a conventional sequential computer results in a computational graph that consists of a time sequential connection of one task to another task. The tasks are decomposed to the instruction level and then the graph links one instruction to the next instruction. If the computational facility is now given the capability for the execution of applied parallelism, the computational graph assumes a new

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form if computations are executed in parallel when possible. It is first assumrd that the capability for executing any degree of parallelism exists. The computational graph then consists of a time sequential connection of a number of tasks to another number of tasks. The number of tasks varies from one to the maximum degree of parallelism utilized in the computational graph. If the computational facility is now given the capability for the execution of natural parallelism, the computational graph again assumes a new form. It is again assumpd that any degree of parallelism may be executcd. The graph appears similar to that for the utilization of applied parallelism except that the number of tasks a t each point in the graph is greater than or equal to the number for the graph in which applied parallelisin is utilized. hlso the tasks that are executed in parallel may be different, eg., add and multiply. For the graph utilizing applied parallelism, the tasks in parallel must consist of identical operations. 100.

90-

80-

70

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m

X 50Q

P

a

a r

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m m

5

30-

20

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t

0

/

100%utilization curb

/ I

3

5

7

9

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Comoutotian reduction ratio

FIG..5. Applied parallelism speed curve.

13

I5

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THE DISTRIBUTED PROCESSOR ORGANIZATION

Solving for the above two graphs in this manner, the minimum computation time or maximum computation reduction ratio can be obtained. Of course, this assumes that whatever degree of parallelism that is required to achieve this is available. The problem of interest, however, is to find this minimum computation time using the minimum degree of parallelism to achieve it. This requires assigning and sequencing the computations in an optimum manner, and as might be expected, this is not an easy problem to solve because of the large amount of permutations involved. This is particularly true when the computational problem is composed of higher level tasks which are decomposed into lower level tasks within each higher level task. Parallelism between tasks and within tasks must be considered, as the number of levels increase the permutations grow quickly. The problem is even further complicated if as much applied parallelism as possible is to be utilized in addition to natural parallelism.

90 -

80 -

70

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-

60-

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a

B

50 -

al

2

0,

0"

40 -

30-

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3 Computotion reduction rotio

FIG.6. Natural parallelism speed curve.

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The next consideration involved in investigating parallelism requires limiting the degree of parallelism (lower than that degree obtained above) available and determining the maximum computation reduction ratio with this degree. The procedure now is the same as above. However, since there is now a lower degree of parallelism considered, a new set of permutations of the tasks is required. Having gone through the above procedures, effectiveness curves for applied and for natural parallelism are obtained. These give a n indication, for the particular set of computational tasks considered, of the amount of parallelism that is efficiently utilized on a eomputational facility capable of parallel execution of these tasks. The computational tasks for the space mission considered were investigated and the curves in Figs. 5 and 6 were obtained. Figure 5 contains the applied parallelism speed curve, It shows the computation reduction ratio versus the degree of applied parallelism available in the computation system. The 100 utilization curve in the figure is the 1-to-1curve; ix., for a degree of parallelism of 2 the computation reduction ratio is 2 , for 6 it is 5, etc. The actual curve deviates slou-ly from the 1-to-1 curve a t first and then reaches a n asymptotic reduction ratio value of 13.66 for higher degrees of parallelism. The knee of the curve occurs at approximately a degree of 1.5; beyond this degree the curve deviates sharply from the 1-to-1 curve. Figure 6 contains the natural parallelism speed curve. -4higher reduction ratio is achieved, as compared to Fig. 5 , for any degree of parallelism. The curve does not have as sharp B knee as in Fig. 6. However. somewhere in the range of 40-60 in degrec of parallelism, the curve starts to deviate rapidly from the 1-to-1 curve.

3. Development of the Distributed Processor Organization 3.1 Parallel Computer Organization Development

In the past I 0 years, a number of interesting and unique highly parallel computer organizations have evolved [ I I ] . Two particular organizations that properly glace the distributed processor organization in perspective are the Solomon machine and the Holland machine. Prior to discussing these organizations. the relationship of parallelism to computey organization is pointed out. Applied and niiturnl parallelism are of interest. Global control in a computer organization implies common control of a number of processing sections by a central control unit. while local control implies control of a processing section by its own control unit. From the definitions of parallelism, global control is used to efficiently handle applied parallelism since a central control unit provides common instruction and data storage. Local control is

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required to handle naturally parallel (exclusive of any applied parallel) computations since by definition the parallel operations may be different. The Solomon machine is adequately described in the literature [I,41 It consists of a number of processing sections under control of a central control unit. The parallel processing sections operate under global control. Local control may be used in the central control unit. This organization exhibits a high efficiency in the execution of applied parallel operations (this is primarily why it was designed). The significant disadvantage of a global control structure is that it cannot, be efficiently applied to most general-purpose computations. This is primarily because of the inefficiency in executing naturally parallel computations. Such computations must be executed in a sequential manner, with the central IV control unit using only one processing section at a time. The ILLIAC machine presently being implemented by the University of Illinois alleviates some of the problems with the Solomon single global control structure. This is accomplished by providing four global control or central control units, each having a number of processing sections under its control. I n this manner, four naturally parallel computations can be executed at one time, increasing the efficiency of the structure for general-purpose use. The Holland machine is also adequately described in the literature [15, 161. It consists of an array of cells, each with some measure of local control. The cells are connected to their four nearest neighbors for communications. A cell is designed to have a very small amount of storage and logic capability. The computations to be performed are assigned to the cells. Parallel computations (applied or natural) are performed by groups of cells. Theoreticaljy, a local control structure like this could achieve high hardware utilization if many small naturally parallel computations were to be executed. The efficiency of such a structure on applied parallel operations is low. This results from repetitive instruction and data storage, and control. The primary problem with a local control structure such as the Holland machine is its spatial orientation resulting from the neighbor communication system. This results in serious programming problems such as path building. If both local and global control features are efficiently combined into one structure, the advantages of a machine of one type with the advantages of the other type are realized. The disadvantages associated with each type are reduced or eliminated. Such a structure is the distributed processor and is explained below. 3.2 The Distributed Processor The organization of the distributed processor is shown in Fig. 1. The distributed processor structure consists of cells. These cells are inter-

connected to form a group, and a number of groups are interconnected

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to form the organization. X cell may be thought of as a small conventional computer that has a relatively sniall memory. The structure may also be thought of as a number of memory modules, each with its individual processing section. These modules are known as cells (512-16 bit words of memory per cell). Parallel operation may exist between cells in a group and between thc groups in the system. Thereforc, the organization appears as a highly parallel computational facility. The computational tasks to be carried out are divided or assigned to various groups and finally to various cells in the groups. A group of cells may carry out a complete task (such as the navigation and guidance computations), a number of small tasks, or even part of a large function or program. The tasks assigned to a group are subdivided or assigned to individual cclls within the group for actual computational niechanization. An example of a subtask assigned to an individual cell is the computation of position and velocitv from navigation sensor input data. This subtask may bc part of a larger navigational task assigned to the group. Some of the more important considerations in assigning tasks are minimizing communication between cells and groups, and utilizing applied and natural parallvlism wherc possible. The cells in a group and in the entire system are all identical in terms of hardware. However. a t any particular time, some cells are functionally operated differently from other cells. Each group has one cell designated as a controller cell. The reinaining cells in the group are designated as working cells. The controller cell is responsible for controlling the intercell communication bus and providing the executive control of the groups’ operation. X11 of the cells in a group are connected to the intercell communication bus. This bus is a one-half word parallel and serves as the primary means of communication among the cells in a group. The intercell bus is used for communicating data between cells and for thc transmission of global instructions and commands to cells. The cell that has the unique function of the controller cell controls the use of the intercell bus and provides all the global instructions and commands. The working cells in a group either accept and execute the global instructions that are sent on the intercell bus or fetch and execute instructions from their own memory. I n fact, some cells may use the global instructions from the intercell bus, while others use instructions from their own individual memory. Since all of the cells arc physically identical, the cells arc capable of existing in different states functionally. I n this way, both local and global control may be carried out siniultaneously within a group. As a result, both the natural and applied parallelism inherent in a group’s tasks may be efficiently carried out. As noted above, the controller cell controls the intercell bus. The

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functions carried out on the intercell bus include communication of data between cells, sending global instructions and commands, and sending commands to individual cells. As mentioned above, only cells operating under global control use global instructions and commands from the intercell bus. However, all cells in the group respond to commands sent to individual cells via the intercell bus, whether the cell operates under local or global control (these commands are addressed to one particular individual cell). Consequently, the controller cell can command one or more cells operating under global control simultaneously, while cells operating under local control must be commanded or talked to on an individual basis. Global control implies that one or more cells are using this type of control. The controller cell provides all control information sent on the intercell bus. Therefore, cells operated in a global control mode are highly dependent on the controller cell since they receive inst,ructions froin it and are responsive to its global commands. However, the cell operated in a local control mode is considerably more independent of the controller cell, since it fetches its instructions from its own memory and must be talked to or commanded individually. In general, the controller cell has the over-all control of the cells in a group, and the degree of this control can be varied depending on the functional use of each cell. A simplified block diagram of a cell is shown in Fig. 7. The cell consists of a memory and arithmetic and control section in a manner similar to conventional computers. I n addition, the cell contains logic for intercell bus communications and for its own identification. This is the part of the cell that differs significantly from conventional computers. All storage within a cell is directly addressable and is divided into control registers and storage registers. The storage registers hold the program and data to be used by this cell and possibly other cells. The control registers are the general processor registers used in the execution of instructions. Instructions, whether they come from the cell’s own memory or from the intercell bus, are decoded and executed in a manner similar to conventional computers. I n addition to the intercell bus communications path, another means of communication is neighbor communications. Each cell contains a single serial connection to each of its four adjacent neighbors (north, east, south. and west) with wraparound connections at the edges of the array of cells. This communication means is primarily included to facilitate the global programming of a group where sinall amounts of data are required to be communicated between cells. e.g.. a matrix multiply utilizing applied parallelism. The operation of a group was briefly outlined above. The cells are

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capable of operating under either local control or global control. The organization consists of a number of groups interconnected by an intergroup communication bus as shown in Fig. 1. Each of the groups can operate independently of, and simultaneously with, the other groups. Therefore, this introduces another level of parallelism in the organization because it is possible to simultaneously have more than one group in operation where each group is utilizing local and global control t o carry

0 lndentificaiion

Arithmetic ond conirol

Intercell bus CommunicolionS

0 Timing

FIG.7 . General cell block diagram.

out its tasks. Each group is connected to the intergroup bus by a group switch as shown in Fig. 1. The group switch is controlled by the controller cell of the group. One of the groups contains additional functions in its controller cell to operate as the system executive group. This primarily involves coordinating and controlling the communications that take place on the intergroup bus. Since all of the cells are identical, the system executive can be located in any one or more of the groups. Many factors determine the number of cells in a group and the number of groups to be used. From the requirements and the parallelism studies, it was determined to use four groups of 20 cells each (512 words/cell) for the spaceborne application considered. [With more than one group it is possible to simultaneously have in execution more than one computation using applied parallelism (global control) since the groups can each have one global program being executed.]

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Finally, input-output connections are provided directly to each cell and are connected to the appropriate sensors and conditioners (some may not be used if the cell gets 1-0 over the bus). I n addition, 1-0devices can be connected directly to the communication buses in the distributed processor system. 4. Architecture

Architecture means the combining of software and hardware features to make a balanced useful system that meets the requirements set upon the computing system. The distributed processor system consists of groups, which are made up of cells. Because the cells in a group are connected by neighbor communication lines and the controller cell sends global instructions to cells, the group is the fundamental unit of the computing system. This section describes the features desirable to unify the cells into a working group. 4.1 Cell States

Although all the cells are identical in hardware, a cell always exists functionally in one of seven different and mutually exclusive states. These states are listed in Table I. TABLEI

CELL STATES 1. Permanently failed-power off 2. Shut down-power saving state 3. Independent 4. Dependent under global control (global state) 5 . Dependent under local control 6. Dependent in wait state 7. Controller cell

Independent cells are functionally similar to a conventional computer. These cells fetch all instructions and operands from their own memories. The cell in t'he independent state stays in this state until the controller cell sends a command addressed to this cell on the intercell bus to change states. The independent cells can process problems that are not amenable to global processing (i.e., by local control). Dependent cells respond to global instructions and global level commands sent out from the controller cell. A dependent cell exists in one of the states 4, 5 , or 6 depending upon the level of instructions

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being sent from the controller cell and the cell’s level register contents. (The concept of levels is described in Section 4.2). A dependent cell in the global state (also called the active state) receives instructions from the controller cell r i a thc intercell bus. The level of the instructions and the cell’s level register is the same in this state. As mentioned above, the instructions being sent from the controller cell to dependent cells are identified as being at a certain level. A dependent cell that is not at the proper level to receive global instructions can idle and not execute instructions. This is the wait state. Therefore, if tlie controller cell is servicing cc*rtaindependent cells, other dependent cells call wait their turn for service. X dependent ccll, instead of waiting for the controller cell to send the instructions for its Irvt.1, can fetch aiid exccute instructions from its own memory. This is the local control state of a dependent cell. This state appears similar to the independent state of a cell in that both operate in a local control mode. TIM.basic difference between them is that the dependent local control state implies that the cell is dependent, and dependent cells respond to certain global coinniands 011the intercell bus whereas iiidv1)eiidcnt cells do not. The dependent local cells are under niore control of the controller cell than thc independent cells. This is clarified later i n this article. This state has advantages when using a cell partly for glol)al programs (global control) and partly for local programs (local control). The capability of dependent cells t o use local control means that the cell bus is not N asted on sending instructions when the instrnctions could bc twtter stored in the cell’s oivn memory. M’ith this feature, the cells can efticiently use local programs to correct for bad data, handle exceptional eondltions. etc. The cell c i ~ nenter the dependent local control state. do some processing. and later inforin the controllcr cell of the sitnation. E w i i though the cell may us(’ local control ill state 5, it is still a dependmt ccll. It is basically under control of the controller cell and responds to certain global conimands. The seventh statc of a cell is the controller state. In this state, a cell controls the iiitcrcc41 bus and can issutb global instructions. ‘I’hfundaniciital ground rtile of making all the cclls of the same hardwart, allows any cell to I)(~x)nii. it controlIer cell. ’I’his gives the advantage that the controller cell fuiict ions may be sv,itclicd among scvcral cells. 7‘1~1s thcw is no rcqtiirenient that all the cwcutive and controller programs fit i n one eel1 *At any time, there is only one cell in the controller cell state i n a group. ‘ I ’ l i t a rrason for this is the controller ccll controls the intercell hus. aiid t\vo cells cannot be allowed to issue conflicting corniiiands.

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The group switch shown in Fig. 1 is part of the group although it is not a cell. The group switch, like a cell, has an identification (ID) register. The group switch responds to control words containing the proper ID bits and performs the operation given in the control word (cw). The controller cell operates the group switch. 4.2 Cell Identification

The distributed processor computer system has two methods for identifying the individual cells. One method identifies the celIs at one of eight levels. The other method gives each cell a unique identifier known as the cell address. Thus a cell has a common first name (level) and a unique last name (identifier). This concept of having two names is important when discussing the dependent and independent cells. Independent cells use only their identifier or cell address. The level (or f i s t name) is not used and, although present in a level register, has no meaning unless the cell later assumes a dependent state. Dependent cells use both names. The controller cell can send out information using a first name (level number) to all the dependent cells, All the dependent cells at this level respond. If a last name (cell address) is sent, only the cell with this name responds since each cell has a unique last name regardless of state. Consequently the controller cell communicates with independent cells individually. However, the controller cell may communicate with dependent cells individually or to more than one at the same time since the dependent cells respond to levels and more than one cell may have the same level. 4.3 Source of instructions

Unlike a traditional computer that has instructions stored in its memory which are always available to the processor, the distributed processor has different sources of instructions depending upon the state of a cell. 4.3.1. Independent Cells

The independent cell receives all of its instructions from the cell’s memory, like the traditional computer. The program counter is used t o control the fetch of instructions. 4.3.2. Dependent under Global Control

The dependent cell in the global state gets its instructions from the controller cell. These cells receive the instructions from the intercell bus and then execute them. The controller cell precedes the instructions

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with a name. The name (level number) is contained in a control word sent on the intercell bus. This control word is a prefix to a group of instructions. This prefix is the level of all instructions until a new level prefix is sent or another control instruction is sent. A group of global instructions is defined as that information contained between control words on the intercell bus when a certain type of control word precedes the group of instructions. The group of global instructions is variable in length. The cell executes the instructions in a manner quite similar to independent cells. However, the source of the instructions is the intercell bus and not the cell's own memory. A detailed discussion of the intercell bus operation is given later in this article. However, in order to facilitate the discussion here, several items are noted. The bus is a half-word (8 bits) parallel. I n addition, one extra line is used and designated a control line. This line is used to define control words or commands on the bus. The commands or control words utilize levels or addresses (first or last names) to identify which cell or cells the command or control word is intended for. Every dependent cell compares the level prefix sent by the controller cell t o the level register contents contained in the cell. If the prefix and the level register contents are different, the cell ignores all the instructions, data, etc., sent by the controller cell, until a new level prefix (or other control word) is placed on the bus by the controller cell. An example is given in Fig. 8. Note that every cell is required t o examine every control word but will not perform the control word operation if the cell is a t a different level (only the dependent cells examine the level) or has the wrong ID (cell address). When segment 1 in the example occurs, all the cells in the group examine the control byte (cB). Assume the CR is a type that specifies a level. A11 the dependent cells a t this level are ready to receive the cw (segment 2 ) and are automatically placed in the dependent active (global) state. These cells in the global state receive the cw (segment Z), I

I

2

1

3

4

5

6

7

Segment number

FIG.8. N u s operation example: Crosshatching represents control byte. All cells ud1 examine this byte. If the cell(s) matches this CB (either by It.vel or cell address). the eell(s) \ r i l l rccei\ e the control uord. Slanted lines represent control word. This \\ ord iitcltides the C B and defines an operat loti to be performed by the cell. 0ftc.n the ClY consists of only a CB Dashes represent data. In this example, it IS assumed that the CbV specified that instructions are contained hcrc. (The number of instructions can be \ ariable.)

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305

instructions and/or data following (segment 3). No other cells receive any instructions or data (segment 3) from the bus until the next CB occurs (segment 4 in the example). When segment 4 comes on the bus, all the cells again examine the control byte. I n the example it is assumed the CB specifies a different level. The following actions occur: Dependent cells that were active (global state) are set to the dependent wait state by the CB a t a new level. Dependent cells not active and a t the new level indicated in the new CB (segment 4) become active and receive the data (instructions) following (segment 5). All other cells are left unchanged. Thus, many sequences of global instructions may be sent to many sets of cells a t very low overhead cost to switch between sets. The low overhead is advantageous when many cells are a t each level and short sequences of instructions are to be transmitted to each. The bus is used very efficiently. This results from the dependent local and dependent wait state in addition to the dependent global state. Since dependent cells respond to level commands, it is possible to switch many cells quickly and efficiently from one dependent state to another dependent state. To summarize, a dependent active (global) cell is a cell that is receiving global instructions and data. By definition, a global cell is at the same level as the global instructions being sent on the bus. The level is in the prefix CB. There is no level transmitted with each instruction. 4.3.3. Dependent under Local Control

The dependent cell not receiving instructions from the intercell bus can fetch instructions from its own memory. This cell is in the dependent local control state. The fetch of instructions is identical to an independent cell. This cell is constantly examining the bus for a command a t its level as noted in the above example. 4.3.4. Controller Cell

The controller cell always fetches instructions from its own memory. The instructions destined to be executed by the dependent global cells are not executed by the controller cell. All other instructions are executed by the controller cell and are not sent to the global cells. This is explained further in the section describing the controller cell instruction execution (Section 4.6).

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4.4 Source of Addresses

Thc cells in the distributed processor computer have several ways of specifying an address. One way is by adding an instruction displacement and a bank register (also known as a base register). The bank register is 9 bits long since a cell will have 512 words of storage. The displacement is obtained from the instruction. Since the displacement is less than 9 bits, a bank register is always added to the displacement when a full (9 bit) address is required, The sum is called the calculated address. If an index register is specified, it is also added. The bank and index registers used to form a calculated address are always located in the cell itself. Independent cells obtain the displacement from the cell itself. Dependent global cells obtain the displacement from the instruction that was sent on the intercell bus. In addition to the calculated address, a new concept of a given address is used. A given address is an address that is used instead of the calculated address. It is specified by a special instruction preceding a regular instruction. A dependent global cell recognizes a given address by a special control instruction received on the intercell bus, called a global control (GC) instruction. The GC instruction is sent from the controller cell to signal the dependent global cells that a given address, in addition to an instruction, is to be sent on the intercell bus. This particular GC instruction is called a format instruction. There are several types of format instructions, the particular one under discussion here is called a format-given address. The sequence on the bus is as shown in the accompanying tabulation. The normal sequence of instructions below is altered by a format instruction. This instruction is a global control byte and tells the dependent global cells that something new has been added. In this particular case, i t says that an address follows

~~

Time

Contents of intercell bus

I

format (given address) Instruction Given address Subsequent instructions

~

GC

the next instruction. The dependent global cell executes the instruction using the given address instead of the calculated address. Thus, the controller cell can send an address to all the dependent global cells instead of having the cells calculate the address. The independent cell (and t,he dependent cell under local control) may also use a format instruction. I n this case, the format instruction is

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located in the cell’s own memory. After the format instruction is executed, the cell knows the type of data contained in its following memory locations. An example is given below: Location START

+1 +2

Contents Format instruction (address given) Instruction Given address Subsequent instructions

Here, the instruction a t START + 1 is executed using the given address instead of a calculated address. The use of the format instruction is called instruction modification. The modification is usually not a change in the operation of the instruction but rather a respecification of the address. As seen from the above examples, this modification can be done in any cell that executes an instruction. 4.5 Source of Data

All cells have access to data stored in their own memory and may also obtain data from their neighbors (each cell has four neighbor cells). Cells receive data from outside the group via the cells’ 1-0line. Cells may also receive data from outside the group or from other cells in the group via the intercell bus. I n addition to the conventional means of fetching data to be used in executing an instruction (by an address), another means known as “ data follows” is introduced here. This is quite similar to the “given address” concept presented above. I n fact, data follows is specified in the same manner. Dependent global cells recognize this by a special GC format instruction received over the intercell bus, and other cells recognize it by the execution of a special format instruction in a manner similarly described above. The use of the data follows concept is interpreted as meanihg the word following the next instruction is to be used as the data with which to execute the instruction. The address displacement from the instruction is not used in this case. The data follows concept is particularly useful in dependent global cells. Having data sent by the controller cell means individual cells do not have to store constants. To have 20 cells all store pi, e, and other constants is an inefficient use of cell memory, whereas the controller cell stores the constant but once and sends it out when needed. The constants are sent a t the time used, and need not be saved in the individual cells memory.

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There are several other types of format instructions used, one of which is “ Immediate ” instruction. This format instruction specifies that the address displacement from the next instruction is used as the data to execute the instruction. Naturally, the magnitude that may be sent depends upon thP length of the displacement field in the instruction. This format instruction is especially useful when loading registers with small values. Another format instruction called ‘‘ Data String ” specifies that a set of data words is to follow the next instruction. It was designed to rapidly move data from the controller cell to a number of cells or a cell. The format instructions introduced here are called modifiers, as they are used t o modify the address or data specification (or both) of an instruction. 4.6 Execution of Instructions

*4detailed instruction list was derived for the cell. Since the number of instructions is rather lengthy, the instructions were grouped into several general categories as shown in Table 11. The instructions in a category are executed quite similarly in most cases. The differences are pointed out in this section. An explanation of the execution for each of TABLEI1 INSTRUCTION CATEGORIES

1. 2. 3.

LR STR OPR

4. RR

5. 6. 7.

COMP

8.

SKIP

9.

JUMP

R EXEC

10. cc 11. GC

12.

10

Load Register from a memory location Store Register into a memory location An operation is performed between a register and a memory location contents, the results are in a registcr An operation i s performed between one register and another register Single register operation such as shift Execute an instruction in a memory location Compare the contents of a memory location (or register) with a register. The results of the comparison are saved in the COMPARISON flip-flops. Test the contents of a memory location (or register) with a register or implied value. The result is true or false. A new sequence of instructions is begun. The jump may be combined with a test to make a conditional jump. Controller Cell instructions Global Control instructions. These instructions control the states and levels of all cells and dependent cell execution of global instructions. Input-Output instructions. These instructions initiate and control I/O operations.

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the categories is given below for each state o f a cell. I n order to facilitate the discussion in this section, note that the processor section of a; cell sontains the program counter, instruction decoding logic, adder, and several registers as in a conventional machine. The registers are accumulators, index registers, and base registers. The registers may be located in an addressable section of the cell's memory, or they may not, be addressable by the programmer. The cell also contains a cell address register and a level register for purposes of cell identification as discussed in Section 4.2. Two unique instruction categories are Control Cell (CC) instructions and Global Control ( G C ) instructions. Some of the functions of the cc instructions are: (1) control the intercell bus communications section of the cell, (2) generate the GC instructions, (3) generate intercell bus communications control signals, (4) control the transmission/execution of instructions in the controller cell, ( 5 ) specify a format modification, and (6) control the state or level identification of the cell. The cell identified as the controller cell is capable of executing all the cc instructions. Only a very restricted part of the cc instructions can be executed by independent and dependent local cells. TABLEI11

CONTROLLERCELL INSTRUCTIONS 1. Control intercell bus 1-0 logic 2. Generate GC and bus 1-0 commands to be sent over the intercell bus 3. Transmit mode, single 4. Transmit mode, all 5. Execute mode, single 6. Execute mode, all 7. Do not change mode 7.1 No operation 7.2 Format (F) 7.2.1 A -Given address 7.2.2 ~ 1 6-16 bit data word" 7.2.3 ~ 3 2-32 bit data word 7.2.4 A, D16-Given address and 16 bit data 7.2.5 A, ~32-Given address and 32 bit data -Immediate 7.2.6 I 7.2.7 DS -Given address and data stream 7.3 State and level control (SIL) 7.3.1 Controller cell state -Set level 7.3.2 Independent state -Set level 7.3.3 Independent state -No level change 7.3.4 Dependent wait state-Set level 7.3.5 Dependent wait state-No level change a

The basic word length in a cell is 16 bits.

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L. J. KOCZELA

Global Control instructions are actually instructions or commands sent over the intercell bus by the controller cell. They are generated by the execution of a c'c instruction and then sent over the intercell bus. Some of the functions of the GC instructions are: ( 1 ) specify a format TABLEI V

GLOBALCONTROLINSTRGCTIONS 1. Format (P) A.

D 16

D32 A, D l 6

A, D 3 % I

US

E N D DS

Given address follows the next instruction 16 bit date word follows the next instruction 3%bit data word follo\vs the next instruction Both a 16-bit data word and given address follow the next instruction, the address comes first Same as A, ~ 1 only 6 the data word is 32 bits long The displacement field of the inst,ruction is the data X number of 16 bits words preceded by a given address follow the next instruction Indicates the end of DS data words

2. State control of dependent cells on the basis of levels (SL) Level, G All dependent cells at this level go to global state; instructions follo\~-. All dependent cells at this level g o to local control Level, L All dependent cells at this level go to wait state Level, w All dependent cells at this level reply on intercell bus with a Level, R const,ant Level, R , DG A11 dependent global cells at this level reply on intercell bus with a constant Level, I N D All dependent cells at this level go the independent state 3. State and level control of individual cells (SIL) The cell is made independent and level register set t o the value IND, Level specified The cell is made independent with no change in the level register IND The cell is set to the dependent global state and the level register DG, Level set to the value specified The cell is set t o the dependent global state with no change in DG the level register The cell is set to the dependent wait state and the level register DW, Level set to the value specified The cell is set to the dependent wait state with no change in the DW level register The cell is set to the dependent under local control state and the DL, Level level regist,er set to the value specifled The cell is set to the dependent under local control state with no DL change in the level register The cell is made the controller cell CC

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modification, (2) control the state of dependent cells on the basis of level identification, and (3) control the state and/or level of individual cells upon the basis of address identification. Table I11 summarizes the types of cc instructions and Table IV summarizes the types of GC instructions. The term “ instruction ” is used freely here and may not be exactly correct. The cc instructions are conventional-type instructions in that they are stored in the cell’s memory that executes them. However, GC instructions are sent over the intercell bus. Only the controller cell can send out these GC instructions by executing a cc instruction. This area of discussion is quite complex, and the explanation of instruction execution in this section clarifies it. In addition, the types of cc and GC instructions are explained in this section (some of the GC format instructions have been discussed previously in this article). A summary of the GC and cc instruction execution is given in Table V for each of the cell states. This table is explained in detail in this section. In Table V, the communications bus 1-0 commands, c , are listed as GC instructions while not being listed in Table IV. This is done since they are sent out by the controller cell by the execution of a cc instruction therein in much the same manner as those of Table IV. They are not truly GC instructions but rather intercell bus 1-0 commands and are not discussed in this section. Section 7 contains a discussion of these commands and the operation of the intercell bus. TABLEV

GLOBALCONTROL-CONTROLLER CELL INSTRUCTION EXECUTION State

cc

Fetched from own memory (CC instr)a

Received from bus (GC instr)a

ALL^

X

Sent over bus (GC instr)@ F, SIL, SL, C

c

IND

F , SILc

SIL,

DL

F, S I L ~

SIL, SL,

DG

X

F, SIL, SL, C

DW

X

SIL, SL,

X

c

c

X

X

X

@Where x stands for not applicable and c for communication bus 1-0 commands. b Except 7.3.2. through 7.3.5 of Table 111. c For independent cells only a level control is allowed from its own Memory (7.3.2 in Table 111). d For dependent local cells only state control to the dependent wait or independent state is allowed from its own memory (7.3.2 through 7.3.5 in Table I11 are allowed).

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4.6.1 Dependent Global Cell

A dependent cell may receive instructions. data, and commands from the intercell bus. The global cell, or active cell, receives instructions and executes them as they are received. A41though the dependent global cells receive the same instruction from the intercell bus, the registers, addresses, and data are usually from the cell’s memory. Thus several dependent global cells receive the same instructions, but all use different addresses and process different data. The exceptions are indicated by the use of a GC format modifier byte preceding the instruction. This concept was explained in the previous sections. A description of the execution of each instruction category listed in Table I1 is given below. Load Register (LR) instructions are all instructions that fetch a n operand from a memory location and load the contents into a register. The address of the memory location is calculated by adding a base register, index register (if one is specified), and the displacement from the instruction. Only the displacement is received on the intercell bus. The operand is fetched from this cells’ memory and placed in the specified register. The LR instructions may be modified with a GC format byte. This byte. when transmitted by the controller cell just bcfore the LR instruction. is used to modify the address or the source of operand. The Address ( A ) modification forces the cell to use the given address instead of the calculated address. The Data (D) modification forces the cell to load the register with the data word sent on the intercell bus. The lmmediate ( I ) niodification loads the register with the displacement field of the instruction. The Data String (DS) modifier is invalid. Store Register (STR) instructions store registers into memory. The address is calculated. and the contents of the specified register are placed in the addressed memory location. A GC format byte is used to modify the instruction. If an A modification is used, the given address is used instead of the calculated address. d data word. either 16 or 32 bits ( ~ 1 or 6 ~ 3 2 may ) be specified. I n this case, the register contents are ignored and are not used. The data word from the intercell bus is placed in the specified memory location. Thus words may be placed directly in a cells’ memory without changing register contents. Both A and D may be given. In this case the controller cell sends out both the address in which the data is to be placed and the data to be stored. The DS modification, when used with a store instruction, is similar to using a GC format with an A and D. The difference is the instruction and address are not repeated with each data word. They are sent to the cell once. Each time a data word is sent to the cell. the data is stored and the address is incremerited. An ESD DS GC format byte ends the sequence. The I modification cannot be used with STR instructions because the displacement field is needed for an address.

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Operation (OPR) instructions. The contents of the memory location, specified by the calculated address, are obtained and used as the first operand. The second operand is always obtained from a register. The instruction specifies what operation is to be performed with the two operands. The results are always placed in a register or registers. The following GC format modifications are allowed:

A given address is specified which is used instead of the calculated address. A data word is sent on the bus, which becomes the first operand. No address is used. The displacement field from the instruction is specified as the first operand by the format modifier. No address is used. The DS modification is used. The address then is not used. The RR instructions operate exactly as in the independent state. No modifications are possible. Because both registers are in the same cell, no transmission of data on the intercell bus is required. Single register ( R ) instructions are the same in both dependent and independent cells. No modifications are possible with R instructions. EXECUTE instructions can be sent from the controller cell t o the dependent global cells. In this way every dependent global cell can execute a different instruction. The address is calculated, the contents of the specified memory location are obtained and executed as an instruction. The A GC format modification is allowed. In this case, the address of the memory location is sent by the controller cell. No other cc format modifications may be used. comare instructions are executed much differently in dependent cells than in traditional computers. I n the traditional computer, a comparison is made between two values. One is located in a register. The comparison results usually set some flip-flops. In some computers a separate instruction tests the flip-flops and jumps or otherwise modifies the program counter. I n other machines the same instruction actually modifies the program counter. Of course, the instruction may not modify the program counter, depending upon the results of the comparison. The dependent cells in the global state do not use the program counter, thus another means of using the comparison results is needed. The concept adapted here is to change the level register instead. The instruction is received from the intercell bus. The address is calculated and the specified word from the cell’s memory is fetched. This word (operand 1) is compared with the contents of a register (operand 2). The results of the comparison set the comparison flip-flops. Another instruction may be used to test the state of these flip-flops and take some action. Sometimes, the same instruction may compare, set the flip-flops, and take some action. The action to be taken is to continue

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J. KOCZELA

a t this level. or increment the level register by 1 depending on the state of thf. comparison flip-flops. Any Ievc~lregister changc. always discontinues the reception of instructions from the intcwell bus (the cvll changes from tlic dependent global t o the dependent wait state). Since tlie compare iiistrnctioii uses d a t a that ma,v be different in each dependent global cell, soiiie cells niay change lercls and thus discontinue receiving global instructions. I n these cells. d a t a processing may be contilined a t a later time when the controller cell sends out a global command indicating that the new level is uscd on tlie bus. The A , n. I . or 1)s GC format modifications may he used. If the DS modification is used. thc words of memory startiny at the pivm address are compared with the data words sent on the d a t a bus. Tf the comparison changes the level rcgister. the reception of data words is discontinued. SKIP instructions are really test and skip. A test is made Iwtween two operands, and tlie result of this test is alwibvs true or false. The true state increments the level register by 1 in dependent cells. The reception of instructions from the intercell bus discontinues immediately. and the cell is placed in the dependent wait state. The cell remains in this state until a GC' eoniniand is sent indicating instrrictions of the iicw level are being sent on the interctdl hus. The false state does not change the level register. Rcception of instructions continues. If an itddress is rcquired i t is calculated. and the operand is fetched from memory. One operand is iisually from a register. The A . D. I. or DS G C format modifications may be used. If the DS modification is used. the ~ o r d of s memory starting at the given address are tested against the words sent on the intcxrcell bus. If any test is true. the level register is changed and data reception is discontintled. If every test is false, the GC format command which indicates thcb end of the d a t a string is received. The level register is not changed. XMMP instructions are not sent t o dependent global cclls because they have 110 meaning. Controller cell instructions are not sent o w r the intercell bus and are not esccuted by dependent glohal cells. Global control instructions are coniniarids received on the intercell bm. Dependent global cells niay receive any of the GC commands: format. state a n d level control of individual cells, and state control via levels. These commands are listcd in Table 11.. The C;C forinat instructioiis describe what is t o follow on the intercell bus. The other cc' instructions received control thtt levels a n d states. These instructions control the state of cells on thc basis of levels or control the stat(' and or lcvc~lof a n individual ct.11 by cell address identification (recall t h a t each cell has a unique cell address).

THE DISTRIBUTED PROCESSOR ORGANIZATION

The

GC

315

instructions for state control via levels are given below:

GC level G. All dependent cells at this level go to the dependent global state. Instructions for this level normally follow. If the cell is in the dependent global state when this instruction is received, the levels match or do not match. If the levels match the cell continues in the dependent global state, and this is essentially treated as a NO OP. If the cell’s level is diffcrent, the cell will go to the dependent wait state. Essentially, a new set of cells are then made dependent global. GC level, L . All dependent cells at this level go to the dependent under local control state. Dependent global cells whose level matches change state. The others remain dependent global. If the cell goes to the dependent local state, the next instruction for this cell is taken from a fixed location in the cell’s memory. GC level, w. All dependent cells a t this level go to the dependent wait state. The procedure is the same as above except no next instruction is fetched for the dependent global cells that change state here. GC level IND. All dependent cells at this level go to the independent state. This instruction sets all the dependent cells at this level to the independent state. The cell or cells begin by initializing the program counter from a predetermined location in the cell’s memory. The above four GC instructions force all dependent cclls at the given level to change state. Independent cells are not changed. Cells that are at a different level from the level number in the GC instruction sent over the intercell bus are not changed. It was noted above that some dependent cells may change their level register during the course of instruction execution. To efficiently cope with this situation, two special GC instructions are used: GC level, R. All dependent cells at this level respond to this GC instruction. They now return a constant number to the controller cell. Because all cells are setting the intercell bus lines to the same value, the hardware design is simple. This GC instruction is used by the controller cell to determine if one or more dependent cells are at a certain Ievel. The cells may switch levels depending upon the value of the data processed by a cell. With the reply instruction, the controller cell knows only that there is at least one cell at this level. There is no way for the controller cell to know how many cells are a t the level without interrogating each one individually. I n addition, another GC reply instruction is: GC level, R-DG. All dependent global cells a t this level reply as in the above instruction. However, dependent local and wait cells do not respond. This instruction is particularly useful to determine if any dependent cells at a certain level are still in the global state and whether

316

L. J. KOCZELA

the controller cell should continue sending out a global program a t a certain level. The GC instructions for state and/or level control of individual cells are listed in Table IV. The general form is: G C State, Level or GC State, No Level Change The GC command is sent over the intercell bus and is addressed to an individual cell regardless of state. Only the addressed cell picks up the conimand and executes it. The addressed cell changes state as indicated by the command and also changes its level as indicated by the command. If the cell is already a t the indicated state and/or level, no change occurs. Therefore, it is possible, for example, to keep a cell a t the same state and change its level. The procedures for changing states depend on the initial state and the final commanded state in the cell. Since this section is concerned with the execution of instructions in dependent global cells, only this initial state is considered. To enter the dependent local state the cell fetches its next instruction from a location in the cell’s own memory given by a fixed address. Entering the dependent wait state rcsults in the cell cntering an idle mode and siusl)eiision of rcception of instructions over the intercell bus imtil a GC instruction is received forcing it to again change states. If an indelwident state is indicated. the cell places the contents of a location in the cell’s own mtwiory. given by a fixed address, into the program counter. The cell begins fetching instructions from its own memory under control of the program counter. This location may simply be the address saved when the cell was last independent and told to go to the dependent global state, an address placed there by the controller cell, etc. The possibilities of restarting the cell i n an indept>ndentstate are numerous. ‘l‘he controller cell state is entered by having the cell fetch its next instruction from a location in its own memory given by a fixed address. One of the first things the new controller cell does is to change the old controller cell into the independent state. Input-output instructions are not executed by dependent global cells. 4.6.2 Dependent Cells-Local

Control State

The dependent cell may have its level register a t a different value than the instruction and data level that is being sent over the intercell bus. These dependent cells are not receiving global instructions. Instead they can idle or execute instructions from their own memory. The first

case is called the wait state, the second is local control.

THE DISTRIBUTEDPROCESSOR ORGANIZATION

3 I7

The execution of instructions in a local control state continues until one of the following events occurs: (1) A cc instruction from the cell’s own memory is executed, which

puts the cell in the wait state. ( 2 ) A GC instruction is received from the intercell bus which specifies the same level as the cell’s level register and causes a change of state. (3) A GC instruction is received on the intercell bus specifying this cell’s address and causing a change of state. The instruction execution in this state is similar to the dependent global cell state. Only the differences are noted below. Any format instruction modifiers as described previously must be stored in the cell’s own memory, preceding the modified instruction. The sequence of instructions is controlled by the program counter. LR

STR

o m

RR

R EXECUTE

COMP

SKIP

The instruction is fetched from the cell’s onm memory, and the regist,er is loaded from the memory location specified by the address. The calciilat,ed address is used inl less a format modifier instruction is prcsent. The D. A , or I modifier can be used. The instruction is fetched from tlie cell’s own memory, and the register is stored in the memory location specified. The calculated address is used unless a format modifier is present. The D or A modifier can be used. The operation is pcrformed between tlie memory locat,ioiicontents and the register. The format, modifier can specify an A. D. I . or DS modification. These are executed exactly the same way iii all cells. No modifications are possible. The register instructio~isare executrd the same way in all cells. Execute instructions are executed as in an independent cell. The address is calculated and the contents of the specified memory location arc executed as an instruction. A format modifier can specify a given address ( A ) . Compare instruct,ions are executed the same as in a depandeiit global cell, The comparison is made in the same way, only the instruction and all data are obtained from t’his cell. The level register is either changed or will remain the same. If the register is changed, the cell automatically goes to the wait state. If the register is unchanged, the cell continues to execute instructions in the local control state. The A , D, I, or DS modifications are used- as given in the dependent global cell description. These instructions are exccut>edexactly as in a dependent global cell. The results of the test, if true, increment the level register and force the cell into the wait state. The false st,ate does not change the level register and thiis the program continues and fetches the next instruction. The skips may be modified by an A, D, I, or DS format modifier, as described in the dependent global cell description.

318 JUMP

CC

c: C

I0

L. J. KOCZELA

These instructions are executed as in an independent cell. The new \ alue of the program counter IS calculated and replaces the present program counter value. Conditional jumps are also possible. A xery restricted part of these instructions may be executed by the dependent local cells This includes the format modification ( 7 .2 In Table 111) and part of the state and level control instructions (7.3 in Table 111). These cc tnstructions are located In this cell’s own memory. The follo\t ing state and level control instructions can be executed. INL),Le\el IND, KO Le\el Change DEP Watt, Le\ el DEP IVait, No Le\ el Chaiigc Any other cc instrttctions ( 1 through 7.1 i n Tahle 111) are not executed in this state The use of the format instructions is described in the previoiis sections. The format instructions arc specified by certain cc instructions ( 7 . 2 i n Tahle 111). The use of any of the statc and level control cc instructions results in a charigc of state aiid possible a leiel change. The procedures for entering the independent or dependent uait state in this case are the same as those prcseiitcd for entering from the dependent global state. Format c c iirstritctions received over the tiitcrccll hiis are ignored by depexidmt local cells. The G C instriictions that control state on the basts of Ie\cl and those that control state or level on the basis of cell address can be executed by dependent local cells. The GC instructions for state control via l e ~ c l sare executed only if the level register matches that of the GC instrwtioii. These instructions arc executed as iit the dependent global cells. The GC instructions for state and/or level control of tndn idrtal cells are handled quite similarly to that described for depeiidcnt global cells. The differences are brought out below. To go t o the dependent global state, the present instruction is completed, thc program counter sax cd. and the hardware accumulator stored in its memory location. Then the state is set to dcpcndent global and the cell is ready to receive instructions over the intercell bus. The dependent wait state simply results in the cell entering an idle mode as before. The commcnts as to the present tnstriiction, program counter, and accumulator given above apply here also and to every change of state for the depeiident local cell. The same procedure is followed to entcr the itidcpcndcnt and controller cell statos as given for the dependent global cell. These instructions are executed as in an independent cell. They are described i n Section 4.7.

4.6.3 Dependent Cell-Wait

State

This cell is not executing instructions. The dependent cell in the wait state is always examining the intercell bus. When a GC instruction that controls states via levels is received which has the same level number as the contents of the cell’s level register, bhe cell switches to the commanded state. A GC instruction may address this cell individually to

THE DISTRIBUTED PROCESSOR ORGANIZATION

319

change state and/or level. The procedures followed to change state are identical to that described for the dependent global cell. 4.6.4 Independent Cell

The independent cell operation is very similar to traditional computer operation. This cell fetches all instructions and operands from the cell’s own memory. The instruction fetched is located at the address contained in the program counter. The level register, although it is not used by an independent cell, may be set to any value via a cc instruction. An independent cell responds to GC commands received on the intercell bus that specify this cell address (last name). An independent cell does not respond to GC commands based on level. An independent state cell must stay in this state until the controller cell sends a GC command on the intercell bus with a cell address equal to the contents of the cell’s ID register to change states. Thus each independent cell must be addressed individually. The capability for an independent cell to switch itself to a dependent state was not included. This is felt to be of little use since a dependent local cell acts very much like an independent cell, and progr2ms that want t o change states and be performed locally may be done in B dependent local cell. This approach simplifies the executive procedures in the controller cell. LR STR

OPR

RR

R EXECUTE

COMP

These instructions are executed as described for the dependent local cells. The D, A, and I format modifications can be used. These instructions are executed as described for the dependent local cells and are the reverse of the LR. The register contents are stored in the given mcmory location. An A or D format modifier can be used. These instructions are executed as described for the dependent local cells and are similar to LR. Only the present contents of the register are combined with the memory location contents according to the operation. The results of the operation are placed in the register. Operation instructions include ADD, SUBTRACT, MULTIPLY, DIVIDE, AND, OR, etc. An A, D, I, or DS format modifier can be used. These instructions are all instructions that use two registers and place the results in one register. Add accumulator 1 to accumulator 2 is an example. No modifiers can be used. These instructions are all single register operations such as shift and complement accumulator. No modifiers can be used. -This instruction is the traditional computer execute instruction. The specified memory location contents are treated as an instruction. This fetched instruction is executed. The independent cell only executes instructions located within its own memory. A format modifier can be used to specify a given address. These instructions are executedas described for dependent local cells except the results are not used to modify the level register. The compare can be modified as in the previous descriptions; A, D , I, or DS format modifications are possible.

320 SKIP

L. J. KOCZELA

These instructions are always a test and conditional skip. The value tested is in a register or in memory. These instructions are executed as in a dependent local cell except the results of the test affect the program counter as in a traditional computer; the level register is not changed in this state. The A, D, I , or DS modifiers can be used. The independent cell modifies the program counter contents based upon the result~sof a skip test. If the test results are true, P 2 replaces the contents of t.hc program counter P . If the test results are false, P 1 replaces the contents of t>heprogram counter P . In other words, the following instruction is skipped if the test results are true. These instructions are either conditional or unconditional. Additiond operations may take place in addition to the jump, such as storing the program counter in an index register, etc. The jump is implemented in an independent cell by replacing the contents of the program counter with a new value. This new value is the location in the cell’s memory where the next instruction to be executed is located. The calculation of this new value is dependent upon the type of instruction. However, in all cases, a new value replaces the old value. Conditional jump inst~ructionsmake a test, usually on some register. If the test results are true, the program counter contents are replaced. If the test results are false, the program counter is handled in a normal manner, i.e., the program counter is incremented by one. The A, D, I, or DS format modifiers can be used. A very restricted part of these instructions is executed in the independent cell. This includes the format modification (7.2 in Table 111) and one of the state and level control instructions ( 7 . 3 in Table 111). The only state and level control,.instruction that is executed is to change the level in the independent cell: IND, Level. Any other cc instructions are not, executed by an independent cell. The instruction to change level simply results in the level register being set to the nsw value specified. The only GC instructions on the interccll bus that will bc executed by an independent cell are those that control state and/or level on the basis of cell address. If the cell address in the GC command matches the cell’s I D register, the command is executed. The procedure to change states is identical to that given previously for the dependent loctil cell; namely, the present instruction is completed, the accumu:ator stored in its memory location, and the program counter saved in the location used for interrupts. Then the state is changed as described previously. I n this case the procedure in going to the dependent local state is similar to that of going to the independent state for the dependent local cell, namely, t,he next instruction is fetched from a location given by a fixcd address. Input-output instructions are executed normally, as described in Section 4.7.

+

+

JUXP

cc

GC

I0

4.6.5 Controller Cell

As instruction execution is concerned, the controller cell operates in basically two modes, the transmit mode and the execute mode. The controller cell can either send out instructions over the intercell bus or

THE DISTRIBUTED PROCESSOR ORGANIZATION

32 I

execute them internally. The transmit mode is entered by executing a particular cc instruction. This instruction causes the controller cell to place the subsequent memory words on the intercell bus. The program counter controls the fetch of instructions. The execute mode is also entered by executing a particular cc instruction. I n this mode the controller cell fetches and executes instructions like an independent cell. All the instructions except the cc and GC instructions are executed identically to the independent cell. Consequently, only the execution of the cc and GC instructions are discussed below. Control cell instructions are listed in Table IV. There are seven basic types of cc instructions: (1) Control Intercell Bus 1-0Logic-instructions of this type control the logic associated with the intercell bus communications section of a cell. Some instructions of this type are prepare to input from the bus, prepare to output over the bus, etc. ( 2 ) Generate GC and Bus 1-0Commands-cc instructions of this type when executed by the controller cell result in the formation and transmission of control words on the intercell bus. All of the GC commands listed in Table IV are generated by this instruction. This includes the format, state control via levels, and state and/or level control of individual cell commands. In addition, the commands to control local communications (Bus 1-0)between the cells are generated by this instruction. Section 7 will present a discussion of the Bus 1-0 commands formed from this instruction. (3) Transmit Mode, Single-this instruction forces the controller cell to enter the transmit mode until one instruction (including any GC modifiers, given address, etc.) is transmitted and then return to the previous mode. (4) Transmit Mode, All-same as above except the transmit mode is retained until one of the two cc instructions given below is executed. ( 5 ) Execute Mode, Single-this instruction forces the controller cell to execute the instruction (including any format modifiers) that follows in the controller cell. Then the controller cell is to revert to the previous mode. ( 6 ) Execute Mode, All-same as above except the execute mode is retained until one of the cc instructions, (3) or (4)above, is executed. ( 7 ) Do Not Change Mode-these instructions are used to control the execution of instructions in the controller cell and to change its level. The present mode of the controller cell is retained.

(a) No operation. (b) Format-these are the format modifiers previously described (A, D, I, and DS). They are used in the controller cell to modify

322

L. J. KOCZELA

the next instruction it executes (not transmits). These are not sent over the intercell bus. Format niodifiers sent over the bus are generated by the rc instruction of type 2 described ahove. (c) State mtl 1,cvel Control-the only onc of these instructions (Tablt. 111) that the controller cell may execute is “Controller C‘ell Statt-Set Level.” This instruction is used by the controller cell t o change its level register. C:lohal control instructions are sent over the intercell bus by the controller cell. Thertbforc, the controller cell is not normally receiving and exmitirig sny oc‘ commands froin the biis. Thc onc exception occurs when thc. controller cell changes stat(.. This is accomplished by t h r coritrollcr c ~ t l executing l a cc instruction of type ( 2 )above. The particular ~c command generated by the execution of this instruction and sent over the intercell bus is a command for a particular cell to changc its state to the controller cell state. The original controller cell than waits for a command over the intercell bus to tell it to change states. A timer is set so that this command is received in a certain maximum allowable time. The command is a GC command sent by the new controller cell. If this command is not reccivcd in this maximum allowable time, the original controller cell interrupts and enters a software routine t o diagnose the no-response condition. T h two modcs of a contrrollwcell. transmit a n d execute, are only one wag of selecting which coritrollcr cell words are instructions t o be excwitecl in the controller cell or in the dependent global cells. Another method is t o place extra bits on each memory word, telling what the word is. This method requires many extra memory bits in all cells. Anotht.r mc.thod is to store in the controller cell, as input-output data for the interccll h i s . all the instructions and data placed on the bus. This approach is very inefficient since the controller cell must identify control words by setting the control line in the bns. It has no means of distinguishing between plohal instructions a n d GC instructions since they are all stored as 1-0data, Of course. one approach as noted above has extra bits stored with each word with the resultant penalty of increasing the n u m h r of bits used for storage. Xnother method here is to store the count of the number of words between the control words and use these counts to identify the control words. This approach requires storing a number of counts. additional control hardware, and makes program modification difficult. The above are only some alternatives in the design of the architecture. Jiany other possihilities exist. The chosen architecture is believed the most efficient and flexihlc comproinise among many alternatives and possibilities.

323

THE DISTRIBUTED PROCESSOR ORGANIZATION

4.7 Input-Output

Input-output is handled by the hierarchical structure shown in Fig. 9. This figure shows the interface to the computer consisting of serial and parallel digital lines. The conditioners CI through C N each have a number of sensors connected to them. The sensors provide a variety of signals to the conditioners and the conditioners, in turn, accept these signals and provide a standard digital interface to the computer. Some devices contain their own conditioner circuitry and are connected directly into the computer. These devices are generally connected in a byte parallel format. The bulk storage memory unit is one of these devices. Other parallel devices include buffers for video sensor data, etc.

I

I

Bulk store

Parallel devices

The 1-0 structure described above was chosen over a completely centralized 1-0 structure which would absorb the conditioners into the computer and have the sensors interface directly with the computer for the reasons given below: ( 1 ) A completely centralized 1-0 structure is generally used to gain a more efficient hardware utilization by the consolidation of common signal conditioning functions. I n this computer, reconfiguration is possible around a number of failures (down to the cell level). Since some of the 1-0 signals are connected direct'ly into the cells (as will be explained later), reconfiguration around a number of failures makes a completely centralized 1-0 structure inefficient. This is because all the cells would be required to have the capability for interfacing directly with any of the sensors. This approach results in a large amount of redundant hardware and does not provide an over-all hardware savings. (2) The conditioner structure is easily adaptable to a change in sensors, addition of sensors, or improvements in sensor design. All that

324

L. 1. KOCZELA

is necessary is to add a conditioner or replace one that is already there. In the completely centralized 1-0structure there is a need t o redesign

the cells and replace the entire computer with new chips. ( 3 ) The conditioner 1-0 structure also provides ease of adapting the computer system to various vehicles between missions and within missions such as a command module and a lander module of a Mars lander niission. These vehicles mav have significantly different sensors. As a result the conditioner structure provides the ability to use exactly the same basic computer with onlj- the need to change the appropriate conditioners in each vehicle. The conimunication lines to a cell are shown in Fig. 10. Five serial lines are provided for the neighbor communications ( S E , S . S , S s r , S S ) and the 1-0 communications. The connections t o the intercell bus are byte N~ Cell bus

FIG.lo. C'omniunications lincs to a cell.

Nw

( X hits) parallel. The input-output method is shown in Fig. 1. Inputoutput dcvices are connected to the cells directly via a single serial line, to the intercell I)nses (byte parallel). or to the intergroup bus (byte pamllel). &I11 connrctions are made via the 1-0 coiiriection penel. X numbchr of alternative 1-0approaches were considerrd. Most of the othcr approaches utilized separate 1-0 cells in the computer. These approaches have the advantage of eliminating one connection from each ccll. but the system is more prone to failure because of the specialized 1-0cells. The selected approach offers the possibility of using any cell as an 1-0cell. Failure i n 1-0 cells may require the plugging/unplugging of connections to effect a reconfiguration. However, a n entire group or system is not lost because of individual failures with the selected approach. In general. the system is used with onlj- several ( 2 or 3) cells in each group acting as 1-0cc4s. This minimizes changing connections because of reconfigmations. This includes both reconfiguration because of failures and of changes in the computation functions as the mission changes from phase to phase. There are a number of reasons for taking this approach. If one uses many of the cell 1-0lines, then many cells would

325

THE DISTRIBUTED PROCESSOR ORGANIZATION

be associated with particular conditioners or sensors. This places a severe restriction on reconfiguration. Consider reconfiguration because of phase changes, for example, from midcourse cruise to midcourse velocity correction. If the sensors are closely associated with particular cells, one is now constrained as to where new programs may be placed in the system. It would be undesirable to have the 1-0 information coming into many different cells which may not even need this information and then have to be placed on the intercell bus to cells that require it. It may be necessary to unplug/plug sensors to affect a reconfiguration in this manner. Another disadvantage is that the reconfiguration of the system around cell failures is difficult. While the probability of a single cell failing is quite low, there are many cells in the system (approximately 80). Therefore, by using 1-0 connections t o many cells the probability of having a failure now associated with 1-0 signals is increased. If a cell fails that is being used with an 1-0 connection and the conditioner is connected only to this one cell, then this conditioner has to be unplugged/plugged to affect reconfiguration. The reconfiguration cannot be handled by software alone. A design of the 1-0 operation was conducted and some significant points are given here. The 1-0cells are to carry out their communications (both in and out) with the conditioners over a single line connected between the 1-0cell and all conditioners that are to communicate with the cell. The 1-0cell has control over this line and operates under control of an internally stored program. Input-output is performed by executing an 1-0 instruction in the processor section. The instruction format will be presented in Section 6. The basic instruction length is 16 bits with 6 bits used for the operation code. The 1-0 instruction uses a long instruction format. This means that two 16-bit words are used to form the instruction (a 32-bit instruction). The contents of the 1-0instruction are given in the accompanying tabulation. The first word of this instruction identifies the Bits 6

1

9

I

9

Op Code

110

Address

Conditioner/device

Word count

operation as either input or output and also contains the address of the location in the cell’s memory where the first word is either output from or inputted to. The second word identifies the conditioner and device

326

L. J. KOCZELA

with which the 1-0is to be carried out. Seven bits are provided here for identification of the conditioneridevices. This provides the capability of handling up to 128 devices per 1-0 cell. Sine bits are provided for the word count. This results in the capability of inputting-outputting up to 515 words (full memory) with one instruction. Execution of an 1-0 instruction results in a sequence of operations implemented in part by software an'd in part by hardware to carry out the desired 1-0. The assembly and transfer of information from the 1-0 instruction to the proper registers is handled by hardware. A control word is then formed and sent over the 1-0 line to the conditioner under harduarcb control. The actual ini'utting-outputting of data is done under software. control by a n input routine or an output routine. The proper routine is entercd after the control word has been sent to the conditioners. The software routines arc entered by an interrupt system associatcd with a buffer register that is used to shift out/in the data over the 1-0line. 5. Failure Detection and Reconfiguration

The ability to detect failures and reconfigure t h t distributed processor aroiind failures is required for the space application considered in order to meet the probability of mission success and availability goals. This section presrnts the design of this capability. The basic guidelines forming a framework for this section are: ( 1 ) Thc time from the occurrencc of a n error to the time the system is rcvmifigured arid functioning properly should riot exceed 0.1 see for critical computations. ( 2 ) C r w participation can he considered for the following functions: (a) rtw)nfigtiration for noncritical computations, (b) turri-on and requests for check out of idlc standby r~~iiipment, and ( e ) replacement of failed equipment with a spar(', verification of the repair, and insertion of the equipment back into the systeni. 5.1 Failure Detection Methods

There are marly approaches to detecting the failures occurring in the system. It is necessary to detect and isolate failures to the cell level since it is dcsired to reconfigure around individual cell failures. Thc two ?)ask mcthods considered are hardware and software. The selected approach consists of a combination of hardware and software methods. Hardware methods are used where a large percentage of errors are detected for a reasonable increase in hardware complexity. Software

THE DISTRIBUTED PROCESSOR ORGANIZATION

327

methods are used primarily where it is difficult or inefficient to implement hardware detection. They are also used to supplement hardware detection where a small amount of software checks a large percentage of hardware. One approach considered uses a “ floating test-cell ” concept. I n this approach, one cell in each group contains a test program. I n operation, all other cells perform the operational problem while this cell tests itself. After a prescribed number of program steps, the testing task of the successfully tested cell is exchanged with the operating task of another cell within the group. This cell then tests itself during the next program sequence. Thus, the testing is multiplexed, with all cells eventually executing the self-test. A drawback of this method is the storage limitation of an individual cell. It is questionable whether a very comprehensive self-check program can be placed in one cell. However, it should be possible to use a neighbor cell as additional storage to hold the program if this becomes a problem. The most serious drawback is that the geometric properties of the array of cells are disrupted. Neighbor communications assignments change as the operational programs move and secondary connections are required for 1-0 signals since 1-0 programs would have to be reassigned as cells performing 1-0 are tested. Another approach employs time redundancy. A sequence of program steps is performed by the group, the tasks of the cells within the group are interchanged, the program steps are repeated, and the results of the two executions are compared. The obvious disadvantage of this approach is the reduction in operating speed by a factor greater than two. It also requires some overhead in storage of the controller cell to globally control the interchange of programs, the interchange of redundantly computed data, and the programs to detect disagreement. The selected software approach uses a central self-test program executed periodically by the controller cell and sent out to the other cells in the group for simultaneous execution. This program may be fairly lengthy for a comprehensive check and may be contained in a neighboring cell because of storage limitations in the controller cell. The test routine is sent from the controller cell. It is executed by all the cells in a global manner and also by the controller cell itself. The cells of the group execute the test program in the following manner: each cell performs the same instruction at the same time, transmits computed results to each of its four neighbors, checks the data received from each of its four neighbors against its own computed result, and reports to the controller cell over the intercell bus. Assuming that only one failure occurs at any one time, a cell’s failure generally results in each of its four neighbors identifying it as a failed cell and possibly identifying all of its neighbors as failed. The controller cell decodes the failure reports and

328

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performs further tests if necessary to isolate the failed cell. It should be noted here that the “given address” and “ d a t a ” format modifiers presented in Section 4 prove extremely useful in performing the test by the global programming method. With these features there is no need to have the individual cells store data and constants for the test program. Another approach incorporates fault detection hardware into each cell. No special testing mode is required. Checks are performed continually along with the operational problem. Parity checking, special error detecting codes, and feedback checks on decoders are typical of the type of fault detection hardware incorporated. The disadvantage with this approach is the amount of hardware that must be incorporated to achieve a high probability of detection. The selected approach combines the last two approaches discussed abovth. Hardware detection methods are used where they are fairly efficient in terms of the amount of hardware checked compared to the amount required for checking; parity checking is one example. A failure detected by hardware sets an error flip-flop sampled periodically by the software test program. The software detection method supplements the hardware met hods to achieve a very thorough test and a high probability of error detection. The self-test programs are sent out from the controller cell as noted above. All other cells in the group are in the dependent global state when these programs are executed. I n general, a neighbor cell detects a faulty cell since neighbor responses are checked as part of the program. This also checks out the neighbor communication paths. Part of the program tests if the error flip-flop ( F F ) has been set. If it has, this cell does not transmit a certain response to its neighboring cell. Detection of an error causes a cell to change its global level. The controller cell tests to see if any cells changed level at the end of the self-test program. The global command for dependent cells a t a certain level to reply (introduced in Section 4) proves particularly useful in accomplishing the last function. This approach also detects errors in the controller cell since it can also execute the same instructions. However, the controller cell can not be relied on to report its own errors. To resolve this problem, the controller cell is required to report to the group suit ches. The group switches contain timing circuitry, consisting of an out-oftolerancr voltage detector. The setting and resctting of a flip-flop a t a certain rate produces a voltage of a certain value. If the voltage is too high or too low it causes an error signal to be generated. The timing circuitry flip-flop can only be set by a predetermined fixed code word. This is the code word that the controller cell contains and sends to the group switches only after it successfully completes the self-test, program

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(note that if the hardware error detection FF is set, the software self-test program is not completed). The timing circuitry is included primarily for the purpose of reconfiguration during critical mission phases. The controller cell response word may indicate failures of the controller cell only. Failures in the working cells of the group are reported to the controller cell in that group. However, periodically the executive group interrogates the controller cells of the other groups to determine the status of the individual group resources. The present organizational concept uses two intergroup buses and two group switches per group to reduce the possibility of single failures bringing down the entire system. The controller cell response word is reported to two group switches. The executive group checks the group switches to determine if failure is in the group switch or in the controller cell. Conflicting reports from the group switches indicate a failure in one of the group switches. The executive group contains the highest level executive in the system. A backup minimal executive will most likely be contained in another group. This backup executive can monitor the executive group for failures just as the executive group monitors other groups. 5.2 Reconfiguration

This section discusses the task of reconfiguring the distributed processor after a failure has been detected and reported to the space crew. Inherently, this system results in a high probability of mission success and availability because an individual group can continue to operate in the presence of a failed cell@)and because the system can continue to operate in the presence of a failed group(s). There exists a status zone between full available computing power and mission failure for which additional failures may result only in the elimination of lowest priority computing tasks and not in mission failure. This is the degraded performance zone. The actual reconfiguration plans depend upon the particular application that the distributed processor is used for. In order to present the reconfiguration procedures derived for the space mission (Mars Lander) considered, three basic phases by which the mission is classified may be stated as: ( 1 ) Noncritical, (2) Critical, and (3) Mars Orbital. The organzational configurations required for each phase are as follows: 3 groups on, 18 cells per group Noncritical : 4 groups on, 16 cells on per group Critical: 4 groups on, 18 cells on per group Mars Orbital:

The critical phases, as the name implies, are those containing critical computations; the capability for carrying out .these computations

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determines the mission probabi1it;v of success. The reconfiguration plans will be Based on the phase in which the failurtb occurs. Although the plans presented below are for one particular application, they contain many areas of commonality to those of other applications, in particular, other space missions. industrial process control, etc. 5.2.1 Noncritical Phase

Reconfiguration for this phase as well as thc other two phases depends on the type of failure. The types of failures may be classified as follows: ( 1 ) \\'orking cell fails (a) in a manner not affecting other cells or (b) in a manner affecting the other cells, either bringing down the intercell bus or contaminating information in other cells. ( 2 ) Controller cell fails in a manner affecting or not affecting other cells. (3) Group switch fails in a manner affecting only internal operation or bringing down one of the two buses connccted to it. (4)Executive group fails either by the controller cell in this group failing: by a working cell failing, and affecting other cells; or by a group switch failing and bringing down the intercell bus of this group. ( 5 ) C'onditioner;sensor fails. Thth configuration during this phase is to have three groups turned on. The computational functions are distributed among the groups. One of the groups contains the over-all system execut,ive. ( a ) Working Cell Failures Assuming the failure has been detected, the controller cell is informed of the failure and goes into its reconfiguration executive routine. I t scans its cell assignment and status tables to determine what the failed cell was assigned to do. The controller cell does not know at this point uhether the failed cell contaminated data in other cells of the group. This can happen if the celi failed and transmitted data to another cell. Therefore. the controller cell assumes that any data transmissions taking place from the failed cell since its last self-check routine results in the transmission of erroneoils data. As part of the reconfiguration routine the controller cell determines which cells the failed celi has communicated to and informs these cells to ignore these data or any computed results based on these data (if this is not possible t G mechanize, it may be required to reinitialize the entire group). Sext, the controller cell determines if there are an? spare cells available in this group. If there are any spare cells available, the controller cell entfersits full capability assignment routine. This involves assigning

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the failed cell’s program (reloaded from the bulk storage unit) to either a spare cell or moving cell assignments around to maintain certain geometrical relationships between assignments (this occurs when neighbor communication capabilities a,re being used). If there are no spare cells left in this group the controller cell can (1) ask the executive group if this group’s functions or part of the functions can be reassigned to another group or ( 2 ) reduce or eliminate some of the functions being performed in this group according to some degradation procedure. Obviously the executive group must maintain tables of activelspare cells in the various groups and also tables of a certain level of functions assigned within the groups with degradation procedures. Degradation may take place in two forms: (1)lowest priority functions may be completely eliminated from the computations or ( 2 )the computational rate may be reduced on some functions, i.e., the programs may be loaded in periodically from the bulk storage unit and essentially time share storage in the computer with other low priority programs. If a working cell fails in a manner bringing down the intercell bus, the controller cell is unable to respond to the group switch with its status word. The group switch then indicates a failure in this group, and the executive group attempts to isolate the failure following the procedure to be outlined below for a controller cell failure. This type of failure causes the entire group to be rendered useless (unless the bus is not affected when power is turned off to the individual cell). ( b ) Controller Cell failures Failures of the controller cell whether or not they affect other cells are treated in the same manner. The group switches do not receive the proper response word and this is detected by the executive group when it samples the group switches. The executive group upon detecting the failure has no further information as to the specific failure in the group. It must assume that the entire group is down. An example of an entire group being brought down is a failure in the controller cell that results in erroneous global commands to all the cells in the group. As a result the cells may be in totally false states or levels. The executive group does not have the capability to access the working cells in the group. Communications with the failed group are initiated by an external source, similar to that used to initially start up each group. Upon detection of the failure, a light on the display panel is lit indicating which group has failed. A new cell in the group is initialized as the controller cell. This is accomplished by initializing the cell to the controller state via this cell’s 1-0line following the normal start up procedures. This may require the astronaut to plug in a new connection to the computer 1-0 panel. This can be circumvented if an

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alternate connection is initially provided that would be used whenever a group failure is indicated. I n any case a new cell is attempted to be started u p as a controller cell by having the executive group load in a self-test routine to be exercised by this cell. This routine may be contained in the executive group or called in from the bulk storage unit. If the new controller cell is functioning properly it issues the proper response word to the group switches as is required in normal operation. The executive group checks the group switches for the proper response word. If the cell is functioning properly thus far, the executive group may attempt to communicate with the new controller cell to further check out the cell. When the cell is finally determined to be functioning properly, the executive group commands the new controller cell to load up and check out the remaining cells in the group. It also gives the controller cell a list of cells known to have failed prior to the group failure so that the controller cell can avoid testing cells already known to have failed. The controller cell then begins turning on and naming cells via the neighbor lines. I t checks out one cell at a time until all cells, exclusive of those listed by the executive group, have been tested and their status determined. After a fixed period of time the executive group interrogates the controller cell to determine the failure. The executive group working with the controller cell reconfigures the group. First, the reconfiguration routine consists of one similar to that described for the working cell failure where the programs are attempted to be reinstated in the group and, second, in other groups if they cannot be efficiently mechanized in this group. It may be possible that the failed cell that caused the group to indicate a failure transmitted erroneous data to another group. The procedure followed is exactly identical to that followed by the controller cell when a working cell fails. The executive group informs other groups to ignore data received from the failed group or computed results based on such data since the time the last self-check was run by the group that failed. (The executive group always interrogates the controller cell in a group as to the time of its last self-check prior to allowing it to transmit data on the intergroup bus.) The failed cell may bring down the bus when it is turned on. Should this occur the controller cell will turn it off via the neighbor communication lines. This should be accomplished in time for the controller cell to continue its reports to the group switch. If the initial cell identified as the new controller cell fails to respond properly to the group switches, another cell is initialized as the controller cell. This procedure is followed until the executive group attempts to start up some number of cells in the group. If the cells cannot be

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started, the executive group declares the group completely failed. This situation can exist if a cell fails in a mode permanently bringing down the bus. If the group is declared totally failed. the executive group goes into a specific assignment program to reinstate the programs of the failed group. This involves checking t o see if any spare groups are available in the system. If a spare group is available, it is started up using the normal start up procedure. However, if no spare groups are available, an assignment program is entered to allocate the programs to the other groups in the system. This probably results in a degraded mode of performance. The assignment program is quite similar to that used when a working cell fails except that it must contain specific information on all the tasks currently assigned to the system. (c) Group Switch Failures If one of the group switches fails and does not affect any of the buses, it will simply not be used. As long as spare group switches are available the group continues functioning. The executives in all of the groups must be informed of the failed group switch so that they may update their communication routines in order not to use this group switch for communications with this group. If a group switch fails in a manner bringing down the intercell bus of its group, the executive group detects this failure when it samples the group switches for the controller cell response word. The failure appears identical to the controller cell failure. An identical procedure is therefore followed to start up the failed group, One group switch is turned on first to check out the cells in the group. Assuming this is the failed group switch, it will be impossible to get the group initialized with a controller cell. This group switch is then turned off and another one, if available, turned on and the procedure repeated. If this group switch is functioning properly and the failed group switch does not affect the intercell bus when it is turned off, the group will be initialized. The executive group has then isolated the failed group switch and proceeds as discussed in the preceding paragraph. If the failed group switch affects the intercell bus when it is in an off state, the entire group is declarqd faulty. A failure of a group switch that brings down an intergroup bus is detected by the executive group when it tries to communicate to other groups over this intergroup bus. The group switches connected t o this intergroup bus then are turned off one a t a time until the bus is operative once again. The failed group switch is then kept off, and the executive group reconfigures around the failure as described for the previous two cases above. If the failure results in bringing down the intergroup bus when the failed group switch is in an off state, the intergroup bus is

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simply iiot used. Of coursr, if there are no more spare intergroup buses then the systeni has failed. ( d ) Executive Group Fohres A failure in the executive group of the type described in Section 5.2.1 (b) results in the executive group’s group su
( e ) SensorlConditioner Failure It is possible for sensor/conditioners to be connected t o the cells, the intercell buses, and the intergroup buses.

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Assuming the failure has been detected and isolated, the system continues operating in a mode not using 1-0 associated with the failed device until a new one is plugged in to the 1-0panel replacing the failed device. A failure may occur in a sensorlconditioner, bringing down the part of the system it is connected to. One example is bringing down the intercell bus, causing a group failure indication. In such a case, if the group cannot be started up following the procedure discussed above for controller cell failures, the sensorlconditioners are disconnected by the astronaut one a t a time, thereby isolating the failure. The same procedure is followed for failures on intergroup buses and the cells. 5.2.2 Mars Orbital Phase

The configuration during this phase requires four groups to be operating. One group is designated as the executive group with the system computational functions divided up among the groups. The reconfiguration procedures for this phase are identical to those given above for a noncritical phase. The only difference is that this phase requires one more group and thereby results in less likelihood of having a spare group available. 5.2.3 Critical Phase

The configuration during this phase consists of four groups turned on. Groups one through three are considered the primary system; one of these groups is identified as the primary executive group. Group four is considered the secondary system, containing its own executive and the critical mission computations. This also implies that there are redundant connections to the critical sensorlconditioners. ( a ) Working Cell failures The cell that failed or the cells that it affects can be involved with critical or noncritical computations. Failures are detected as before in the other two phases. If the failure is involved in noncritical computations, the controller cell determines if any spare cells are available in the group to assign the failed computations to. They are loaded in from the bulk storage unit. There is no reassigning of programs in the group to affect a certain geometrical reconfiguration of the programs as in the other two phases. If no spare cells are available, the failed cell’s computations are simply suspended. To reassign programs to other groups probably requires plugginglunplugging sensor/conditioners to effect a reconfiguration, and it is doubtful this would be done in a critical phase for noncritical computations.

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X failure associated with critical computations results in the controller cell issuing a faulty response word to the group switches which indicates group failure. The group switches output the group failure signals to switches that control the steering of output signals to the critical sensors as shown in Fig. 11. This results in switching over control to the secondary system as far as the critical sensors are concerned. The executive group in the meantime has also noted the failure. At this point it does nothing. The controller cell attempts to reconfigure within the Critical system outputs

t Crit cond

group

Cflt cond

indicating on-

Secondary group

group so that the critical computation can be reinstated and serve as an additional backup if the remaining system fails. The executive group therefore waits a fixed amount of time to determine if the group has been reconfigured internally. If the group has been reconfigured. it must then be restored to operational status by providing it various computational parameters. This can be done either by using the last known good set of parameters of the failed system which has been continually stored in another cell or group during operation, or by obtaining the latest values from the system which did not fail. If the group is not able to reconfigure itself, the failure is treated as discussed below. Note that the above discussion applies to the primary and secondary systems except that in the secondary case no actual output switching takes place. ( b ) Controller Cell Failures As above, if the failure involves a group with critical computations, the group switches will issue signals to switch control to the secondary system for the critical sensors. The executive group follows a procedure similar to that given for the prior two phases

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as far as attempting to check out and isolate the failures in the failed group. If the failed group is reinitialized, it could be loaded up with critical computations to serve as a backup for further failures. I n the meantime, prior to checking out the failed group, the executive group reloads one of the other groups with a set of the critical computations from the bulk storage unit if the failed group contained critical computations. I n this way another group can serve as a backup to further failures in critical computations. Note that this capability requires redundant 1-0 connections to groups unless the astronaut pluggedlunplugged the connections during the critical phase. (This may not be practical for him to do.) ( c ) Group Switch Failures Same discussion as in prior two phases applies here. The controller cell failure procedures outlined above are followed here in attempting to reinstate the failed group.

( d ) Executive Group Failure If the executive group’s group switches indicate a failure and a minimal backup executive exists as discussed in the prior two phases, the backup executive follows the same procedure as discussed previously. Note that the backup executive can only be located in one specific group since the other two nonfailed groups are associated with critical computations. I n any case, the two groups assigned the critical computations continue operating normally. ( e ) SensorlConditioner Failures Failures associated with noncritical functions result in suspension of the associated computations. However, if they affect a critical function, the controller cell simply indicates a group failure and results in switching over control to the secondary system. Unless redundant connections are provided, the astronaut has to plug/unplug connectors to reinstate another backup system for critical functions. In the above discussion for the critical phase, failures in one group affecting other groups are not mentioned. The reason for this is that the programs in the groups are expected to be well isolated and contain check routines to validate any data received from other groups. They also have routines to validate requests for any control changes or locations that data is read into. In this manner each group essentially locks out other groups except for certain predetermined functions not affecting this group if another group failed that it is communicating with. The group switches also contain logic to inhibit their group from getting on the intergroup bus should they fail to get the proper response word from the controller cell. I n this manner, it is very unlikely that one group’s failure affects the remainder of the system. The organization

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contains many possibilities for sustaining multiple failures during a critical phase. This is particularly true if a number of extra 1-0connections are provided to the system as discussed above. 6. Cell and Group Switch Design

A further description of the cell is given in this section. First the features are presented, and second some detailed aspects of the design are discussed. Finally, some design considerations of the group switch are given. 6.1 Processor Features of the Cell

This section describes the general features of the processor section of each cell and some of the trade-offs in arriving at the features. I n particular, the word length, accumulators, index-bank registers, and the instruction word format are discussed. The primary consideration used in evaluating the features was their ability to save memory storage or total bits of memory. I n general it is desired to minimize the total amount of hardware required. However, it is expected that the memory section of a cell will require approximately nine-tenths of the area of the wafer, whereas the processor section only approximately one-tenth. Therefore, since most of each cell is devoted to memory, it is necessary to consider features that could be added to the processor section t o reduce the amount of memory required. There is also some impetus to minimize the amount of hardware devoted to the processor section. This increases yields of the cell LSI wafers. This may be understood by realizing that the memory section primarily consists of a regular geometric connection structure of gates and registers, whereas the processor section is characterized by an irregular connection structure. Therefore, if discretionary wiring techniques are utilized, yields can be increased on cell wafers by easily incorporating redundant memory logic. It is relatively difficult to incorporate redundant logic in the processor section to increase yields. In general it is necessary to trade off the increase in processor complexity to the amount of memory savings for a given feature.

6.I . 1 Accumulators I n general, it is expected that a cell will be memory limited rather than speed limited. Therefore, there is just one accumulator in the processor section of a cell and any additional accumulators are accessed from a specified area of memory in order to reduce the amount of

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processor hardware. The use of more than one accumulator saves a significant amount of execution speed and, of more importance for this application, storage. The storage saving comes about since intermediate results do not have to be stored in the memory. As intermediate results are obtained they are simply left in the accumulator in use and another accumulator is brought into use. The accumulator to be used in any operation is simply specified in the op code of the instruction. As a result, when the instruction is to be executed, the proper accumulator is pulled out of the memory and exchanged with the accumulator in the hardware location. If the hardware accumulator is the one specified no exchange is necessary. This process takes a longer time than if the accumulators were in the processor hardware itself. However, the main interest is in saving storage and not in increasing the speed capability of the processor. The usefulness for memory savings of a second, third, or more accumulators for intermediate storage has been evaluated. It was found that for guidance and navigation computations in an aerospace system, addition of a second accumulator reduces the instruc,tion count by as much as S%, and the inclusion of six or more accumulators brings this reduction to as much as 12%. The major advantage of multiple accumulators is the addition of the second accumulator; as a result each processor section should have a t least two accumulators. The inclusion of additional accumulators depends on both the availability of instruction bits to specify to which accumulator ai particular op code is being applied and the relative usefulness of additional accumulators versus additional index registers, as is pointed out below. 6.1.2 Indexing

Full word length index and bank registers are used. There is no real distinction between t,he two since they both accomplish address generation and address modification in the same manner. They are referred to as index, bank, or index-bank registers. As above, for the accumulators, these registers are located in memory in order to save processor hardware. For an instruction that requires banking or indexing, the proper index-bank register or registers are accessed from the memory, loaded into the memory buffer register, and added to the memory address register (the memory address register holds the address displacement obtained from the initial instruction word). From this it can be seen that an instruction that needs to be banked and indexed before picking up the operand would require four memory cycles, including the memory cycle to pick up the instruction itself (accumulator may be in memory).

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The advantage of indexing in terms of memory savings has been investigated. It u-as found that the inclusion of a t least three index registers along with one or more bank registers provides significant storage savings (20% or more); however, the addition of more than t h e e index registers provides significantly less storage savings. As a result, a t least three index registers should be included in the processor of each cell. The use of additional index registers depends on the availability of instruction word bits and on a comparison of the value of these additional registers t o the value of additional accumulators. The index registers could also be used for temporary storage. However, use of the index registers in this manner provides no memory saving unless register-to-register instructions are included (instructions carrying out basic operations such as add from one index register to another index register). The reason for this is that an index register used as temporary storage cannot be addressed directly by bits in the op code if the operation is to be carried out between the temporary storage and a memory operand. This results since the index register bits in the instruction word must specify the indexing of the address for the memory operand. Therefore, only operations that address two index registers used as temporary storage and then add or subtract them, etc., provide an instruction saving over the use of memory addressing for intermediate results. Investigation of the usefulness of register-to-register operations versiis the usefulness of providing accumulators that may be used for temporary storage has shown that the register-to-register operations find very little usage in comparison to the accumulators. As a result, using accumulators instead of index registtm for temporary storage provides a much greater storage savings. This trade-off was carried out in conjunction with the word size trade-off and resulted in the decision to provide four accumulators. 6.1.3 Word Size

The desire to save storage (to use the least number of bits in the memory possible) gives a reason for considering small word sizes. If a small instruction word can include enough features, it may provide enough flexibility such that i t would require only a slight increase in the number of words for instructions in the memory over that for a larger instruction word. This may then result in a smaller number of bits in each cell’s memory for instructions. Larger instruction words are generally used to offer more flexibility and increased processing speed. The increased processing speed is not required here, but the amount of storage saved by increased instruction word flexibility is important. It is also necessary to consider the amount of extra data words that would

34 I

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be necessary with a small word size. A small word size may require increased double precision (and possibly some triple precision operations) and results in smaller byte sizes for storage of multiple bytes per word. The following word lengths were given consideration: 12, 14, 16, and 18 bits. Evaluation of 'features obtainable from various instruction formats in each word length resulted in selecting the 16-bit word size. This word size results in an instruction format providing sufficient features, sufficient accuracy for double precision (32 bits) operation with little or no need for triple precision operations, and a flexible word length for bit manipulation capability (16 is a power of 2). The particular 16 bit instruction word format selected is given in the accompanying tabulation. Bits 1

:

6

Op code6

7 : 9

10

BIT3

16

Address displacement'

This format provides for 64 basic op codes for instructions and a 128-word bank from the address displacement. Three bits are provided for the index-bank registers (referred to as B and T registers). The selected use of the three BIT bits is to provide for the specification of one of two B registers in conjunction with one or none of three T registers. This scheme provides five index-bank registers and the oapability of double indexing. (Bit 7 may be thought of as the B bit and bits 8 and 9 as the T bits.) 6.2 Functional Description of the Cell

A general block diagram of the cell was given in Fig. 7. The cell contains hardware that is broken down into six general areas: (1) Memory (2) Identification

(3) Arithmetic and control (4) Intercell bus communications (5) 1-0

(6) Timing

A detailed block diagram of the cell is shown in Fig. 12. This figure contains all the main registers in a cell. Logical gating and some control flip-flops have been omitted for clarity. The drawing ,presents some insight into the detailed operation of a cell. The registers shown have a

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nrinieral in the right-hand corner. This indicates the length (bits) of the register and gives some indication as to its complexity. Each of tho blocks in the figure is explained below: Hard\\arc Upper Accumulator is used to hold one of the memory upper accuniiilators i n any operation that uses them. Lo\\ er accumulator is used primarily in multiply, divide, and double precision operations t o hold the lower half of a data word. This nccuniulatoi. aiid u ha\-e a 1-bit extension onto their 16 bits i i i order to hold thc o\ erflo\\ carries \\ hich may be generated in the multiply operatroil.

FIG.12. Detailed ccll block diagram.

ul,

~

P ,WAR

B l , B2

2 ug ,

, x*4 Blcmiory V p p r r2ccrimulators Program counter Memory Address Register holds the memory address for operand memory cycles. I t is loaded with the address displacement from t h c instruction word. BI or B Z is added t o it arid, if indicated. one of the index (T)registers is also added to it. This register is necessary since the B and T registrrs are in memory and enter the processor through M R . As a resiilt, M B cannot be used t o hold the operand addrcsscs. B Memory Index-Bank Registers hold both index and bank values for address calculation and looping control. One of t.hese two rcgistcrs, indicated by the IJ bit. is added to the address displace;nerit for all operand address calculatioiis. (This is necessary sirico the displacement from the iiistruction is only 7 bits long arid 9 bits are needed to address memory.)

THE DISTRIBUTED PROCESSOR ORGANIZATION Ti

to

T3

343

Memory Index-Bank Registers have the same functions as the registers. However, operand addresses can be generated without adding any T register to B plus the address displacement,. Adder, Logical, and Transfer Unit contains all the circuitry for carrying out arithmetic and logical operations including comparisons. It provides for transfers among all the hardware registers and detection of overflows. Instruction Register holds the 6-bit op code throughout the instruction execution. Tag Register holds the T bits of the instructions. It is necessary so that B plus the address displacement can be gcnerated, stored in MAR, and then added to T prior to an operand cycle. Shift Count Register holds the shift count for shift commands, and for setting up bits in byte manipulation operations. It is counted down to zero by one count for each shift. It provides a temporary storage area for certain control information during several intercell bus communications operations. Length Register is used for byte instructions to specify the length of the byte that is being used. Hardware Accumulator indentifies which of the four accumulators is presently in hardware. Every instruction that specifies an accumulator must compare these 2 bits to that in the instruction. Comparison Flip-Flops hold the results of a comparison; greater than, less than, or equal. They may be tested by an instruction for a conditional jump, skip, etc. Overflow Flip-Flop is set if an overflow results in the ALTU during an arithmetic operation. Like the CFF, it may be tested by an instruction. Failure is set by the hardware failure detection circuitry. It can be sampled by an instruction during software self-test. Interrupt Mask Register is set by the programmer to mask off any interrupts that are not to be allowed. Controller Cell Mode holds the mode of a cell in the controller cell state. It has no meaning in cells in any other state. It will be set to one of the four transmit/execute modes and will control the execution of instructions in the controller cell. Holds the cell address or identification. It is used in the bus 1-0 control section to decode commands over the bus. This register holds the current state of a cell. It will be in one of 5 states: T

B

ALTU

IR TR

SCR

LENR HA

CFF

0

F IMR CCM

Cell

ID

State

Level BCR

000

INDEPENDENT

001

DEPENDENT GLOBAL

010 01 1 100

DEPENDENT LOCAL DEPENDENT WAIT CONTROLLER CELL

Specifies one of eight levels that the cell may use as a means of identification during dependent state operation. Bus Communication Register receives the present byte on the intercell bus. It is used by the Bus 1-0 Control to decode commands and control the bus communications.

344 Bus

L 1-0

ic Biisy Timer 1 , 2

IOSK

Timer 3 Countrr 1-0

RTC' EXT RTC

BTC

35C

J KOCZELA

Holds the identification of the present operation being carried out on thr intercell bus (input. output, etc.). Intercell BUSBus>. This flip flop is used to determine if t h r bus IS presently being used. Used to time certain operations over the intercell bus. Expiration of the timers during these operations results i n an interrupt being lislitd. 1-0 and Seighbor Register. This is a srrial/parallel in and out buffer register used for communications betu een I/O devices and also one of the four neighbor cells. It is 18 bits long because of the need for sync and control bits in addition to the datx bits (16 bits). Is s r t during certain i/o operations such as requesting data from a neighboriiig cell. Its expiration w i l l cause an interrupt. Counts the serial iri/out of the IOXR. It u ill issue interrupts during I 0 operations. This flip-flop is set to either the input or output state during an 1-0 instruction eseciition. I t controls the type of interrupt geneiatrd by the coiinter mentionrd directly above. Acciimulator Flags are set to one of fi1.e states: N, E, S, W, or X. The first four indicate tlir acrrimulator holds data for a neighboriiig cell and thc last one indicates no neighbor data. There is one flag register for each accumulator. Real Time Clock Extension is a simple counter driven by the clock Real Time Clock is a simple counter dri\ e n by the RTC EXT. It is set and read by iristructions and counts dowii to zero. Bit Time Coimter is drittii by the clock and generates two pulses (counts to t u 0 ) . It is used to control the instiuctiori execution and dri\ e thr inrtrnction decoding and control generation logic. Mode Counter is dri\eii by the RTC and generates eight control signals. It drives thr iiirtriictioir decoding arid control generation logic.

6.3 Group Switch -1block diagram of the group switch is given in Fig. 13. The group switch controls tile iiiformation transfer between the intercell bus and the intergroup bus. It is relatively simple in terms of hardware complexity. This offers the possibility of using redundancy techniques to achiew a highly reliable design. functional description of the hardware in the group switch is given 1 ) t ~ l o w : H('R

Group si\itch I r)

13riffrr Coriiiniiiiiedtion Register - t n o half - \ \ ord long registers that rccei\c the preseiit byte o'i-er the bus they are connected to. .I 3 hit register to hold the idoitification or address of the group snitch. This register is nsrd to decide which commands are addressed to the group suitch. I t has a serial load line for initialization purposes. X o t c that this provides the capability for ha\ iiig up t o 32 group snitches or 16 group5 (tmo group snitches used per group) i n the system.

345

THE DISTRIBUTED PROCESSOR ORGANIZATION I-G

Busy

Intergroup Bus Busy Flip-Flop-This flip-flop is set when tho executive group command register is loaded in a group. It is reset when an '' end of transmission " command is sent over the intergroup bus. It is sampled by command over the intercell bus.

w pq inter -group bus

r------

- - -- - - --1

t-I-

BCR

I

I I

Exec group command reg

I '1 '1 Group

I

Cell

Addres~~I-d~Counts~

Group request register

timing circuitry

I Group'I

Cel151AddressSII-dlCountq Output reg

m

Inter-cell control

I

I I

I BCR

"1

I

FIG.13. Group switch block diagram. Executive group Holds a command received over the intergroup bus that was addressed to this group switch. It is sampled by command over command the intercell bus. It is loaded with a command for this group register identifying the cell, address, and number of words to be input or output over the intergroup bus. This register kautomatically reset when it is sampled over the intercell bus.

346

L. J. KOCZELA

Group request register

0

Rite tiiriing circuitry

Intercell aiitl i n twgrou 11 I)US

con t 1.01

Holds a request rcccir-cd over the intrrccll bus by a rommand addrrssrd to the group h u itch to load this register. It is sampled by command over the intergroup b u s and holds the requested I o over the iritergroup bus. Output Register-srt by a command recrived over the intergroup bus. It is sampled by a command over the intercell bus. It synchronizes the start of communicatioiis between two groups. This register is ailtomatically reset when i t is sampled by command over t h r intrrccll bus. Tliis circuitry consists of a flip-flop that is alternately set-reset 1))- t~ ccimmaiid from the iritcrccll bus. The rate at which I t IS x r t determines the voltage geiierated across a circuit. Two out of tolerance le\-el detertors arrow this circuit m i l l check for a high and IOU \slue of voltage. If thc voltage 1s out of tolerance i t failure signal is issued. ('ontain all the control circuitry to decode information received r)\ PI the buses and execute commands addressed to the group s\\ itch. This eontrol circuitry generates intergroup bus commaiids from certain intercell bns comrnaiids. It is responsible for opening up t h e communication path betneeen the two buses.

7. Communication Buses The intercdl and intergroup bus communications are described in this section. Thc basic philosophy behind the design of both buses is that each cell is capable of only addressing directly its own memory. Other cell's memory must be accessed by a request-type scheme over a common bus. 7.1 Intercel I Cornmun ications

Intercell communications within a group are carried out over the groups' intercell biis. The intercell bus is under complcte control of the cell in the group designated as the controller cell. This cell operates the bus by the execution of ccrtain C'C instructions. Communication takes place in basically two types of modes, local and global. Local use is basically communication between two cells with control set up on the basis of cell address identification and not dealing with the control of levels or states of cells. Global use implies communication of the controller cell with one or more of the other cells with control set up on the basis of cell address identification. levels, or states for the purpose of global control of the cells. The intercell bus is used for both instructions and data. Local use of the bus is basically for passing data among cells and among cells and 1-0 devices connected to the bus. Global use of the bus may be for instractions and/or data. In any case the controller cell sets up and controls all information flow over the bus. Software routines are set up in the controller cell to control bus operation.

THE DISTRIBUTED PROCESSOR ORGANIZATION

347

A total of 10 lines are used for the intercell bus. One line is used to denote control or data and is designated the control line. Another line is used for parity. The remaining eight lines are used for control or data words. The two basic control word types are local and global. Local words require a particular cell identification or address to be specified. Global words require the specification of an identification address or certain global levels or modes. The control words are decoded by all the cells and only the appropriate cells partake in or accomplish the desired communication on the intercell bus. All words over the bus are composed of 8-bit bytes whether they are control or data words. The control words are identified as such by use of the control line. The first byte of any control word is identified by the control line set to a one (control) state. The control line will return to a zero after the first byte of a control word. Some control words require more than one byte. The format of the f i s t byte of a control word is given in the accompanying tabulation. This byte provides for addressing Lines

Control/

Command

I

address

control

I

TABLEVI

INTERCELL COMMUNICATIONOPERATIONS 1. Controller cell to send words directly to a cell under controller cell’s command. 2. Controller cell to receive words directly from a cell under controller cell’s command. 3. Controller cell to scan bus usage requests from individual cells and establish communication between two cells based upon reqnests. 4. Controller cell commanding communication between two cells. 5 . Controller cell issuing a command to a cell specifying some changes to the internal control state. 6. Controller cell issuing global commands to one or more cells.

348

L. J. KOCZELA

given above. The first byte is identifird as a command. A list of commands is given in Table VII. TABLEVII INTERCELL

Command S o .

~

s1

000 00 1

X?

010 011 100 101 110 111

Conininncls X U . xi

Description

Code

--

XO

BVS COMJIASDS

~~-

Global mode command Global mode command Report communication request status Input Out put Report status word Control reconfiguration Extended command format

Thew commands are used for global operations. The remaining f i x - ~lines are tiot usrd for cell address purposes. but for Yarious global control fiinctions (format commands, st,ate control via Icvrls. etc.) This command reclwsts a rcspoiisr from a given cell as t o the statiis of its rcclticsts for iisr of the communication bus. This command tells thc ccll t o input thc nest set of data words oir thr bus. (A act of data \\-ords is defined as the words on thc h i s l)rt\vecii control xvords.) This commatid trlls R cell to output a set of data \vords on the bus. a This command rrqiirsts a cell to sciict t o the controller cell a statiis word representing ccrtiiiti control states in the cell. This conmiand forces a cell to perform some change t o the ititcbriinlcontrol state (c.g.. tirrn oti,'off'. ctc.) This command iirirs a n estcndcd forniat. It requires the s;ccond contrul \\orti hytc t o itfcnt ify what thc. command coiisists of. This provitlcs for inor(' t l i a t i tlic cight hasic rommands listed iiwt.. This comrnarid is riscd to rhanpe cells from locnl cotit 1 . 0 1 moctcs to plnhal control inodcs (state coilt ru t I ia wt I a d d w s s iden t ifica t i o i i ) .

The controller cell issues the proper seqitenccs of control words using the cominands given above t o iniplement the operations given in Table VI. 7.2 Intergroup Communications

Intergroup communications are accomplished by using the intercell and the intergroup buses, This communication is somewhat different from that given above for intercell communications.

THE DISTRIBUTED PROCESSOR ORGANIZATION

349

The difference is that the cells in a group are under immediate control of the controller cell and immediately respond to commands over the intercell bus. However, the executive group that is in charge of controlling the intergroup bus use does not have the groups (represented by the group switches) under its immediate control. The groups periodically sample the group switches to see if any commands have been placed in the executive group command register by the executive group. (Any group can do this; however, only the group acting as the executive group will be issuing such commands.) The groups then respond to these commands. There is some delay in getting a response to these commands. The delay is dependent on the rate a t which the group switch is sampled by the controller cell of a group for these commands. Once the controller cell picks up these commands, it immediately responds by commanding the proper cells in its group to begin communications. The groups place requests for intergroup communications in the group switch (in the group request register). These requests are periodcally sampled by the executive group. It is based upon these requests and any individual requests of the executive group that commands are placed in the group switches for intergroup bus control. The following is a list of the communication functions to be carried out over the intergroup bus : (1) Executive group to scan groups €or requests, one group to request to sendlreceive words to/from another group (could be the executive group). (2) Executive group to request to sendlreceive words to/from another group directly. (3) Executive group to command another group switch t o turn off power. To accomplish the communication functions listed above various commands are required over the intercell bus and the intergroup bus. The group switch contains an ID (address register) just as a cell does, It responds to commands addressed to it just as a cell does. However, how it interprets a command may be different from a cell. Eachcommand uses the same format as that given previously, namely, 3 bits for the X (command) code and 5 bits for the address. In general, the commands received by the group switch over the intercell bus are interpreted differently from those received over the intergroup bus. 8. Software Analysis The distributed processor has many levels of control. This results in many levels of control (executive action) in the software to program the

350

L. 1. KOCZELA

computer. The executive programs may be considered at three levels : ( 1 ) the system executive, ( 2 ) the group executive, and (3) the cell executive. 8.1 Group Executive

Basically. the group executive controis a group of cells. Each group must h a w allocated one cell as a controller cell. This cell acts as the group esecntive. Since any cell in a group is identical, any cell can perform as a controller cell. The group executive functions will reside in one or more cells in a group (more than one as required because of storage limitations of an individual cell), and one of these cells will be acting as a controller cell at any one time. Although the different programs that comprise the group executive may be in different cells, this set of cells (which always includes the present cell that is in the controller cell state) is called the “group executive.” The group cxccutivc has inany functions. Basically, it controls the operation of the cells in the group and the intercell communication bus. It reconfigures the group resources rcsulting from changes in processing icquirenients and failures. Finally, it must interface with other groups. The functions are hroken down into six subfunctions: (1) Control system resources

(2) Furnish global programs to dependent cells ( 3 ) Allocate system resources (4) Test system hardware and software, and respond to any malfunctions ( 5 ) Rcconfigure system upon: (a) Xormal phase change (L) Nalfunction (6) Intclrfacc with other groups, including the system executive

Each of thv almve functions of the group executive were considered in detail 181. Some of the niorr important items are noted below. ‘ I ’ h t x computational tasks are performed in the operational cells. These cclis may rcquirr esccutive services such as getting 1-0 data over the intcrccll h i s . getting intermediate coniputational data from other oprwtiunal cells. setting clocks; etc. The group executive provides such services under the subfunction of control system resources. These services are provided in two modes: periodic and background. Periodic services are required at fixed predetermined intervals of time. Background services are fitted in between the periodic according to some priority scheme. The services are provided by command or request. (Jommand services are completely controlled by the controller cell, e.g., the controller cell commanding one cell to send another cell certain data.

THE DISTRIBUTED PROCESSOR ORGANIZATION

35 I

Request services are requested by the operational cells, e.g., an operational cell requesting data from another cell. The function of controlling the system resources may also be considered one of controlling the control and data flow over the intercell bus. The periodic control of system resources is handled by a real time clock interrupt routine. Upon an interrupt from this routine the controller cell services a particular task in one of the cells. This may require the requesting of a communications request word from the cell. The controller cell examines these requests, checks their validity and relative priority, and takes the necessary action to complete the requested service. The background mode of service is quite similar to the periodic except that no real time clock interrupt routine is used. I n this mode, the cells are all serviced according to some priority scheme. The cell or cells that contains the group executive contains all the global instructions that are to be executed by the dependent cells. Because these instructions are sent on the intercell bus and the controller cell controls the intercell bus, the controller cell sends out all the global programs. These global programs may be simply sent out by the controller cell or they may be sent out in response to a request either by the periodic or background service routines mentioned above. To allocate system resources and schedule the use of these resources, there is made available to an executive scheduler program a list of the hardware resources in the group and a list of tasks performed by the group. I n addition, a list of the software requirements of each task is made available. The executive scheduler, using these lists, begins to allocate the resources to the tasks. Periodic tasks are assigned first according to their priority, then the background tasks are assigned. The first assignment primarily consists of deriving the intercell bus usage schedule. The tasks are then physically assigned to cells. The group executive contains the central self-test program to test the group hardware and software. This program is sent from the controller cell to all the other cells in the group by placing these cells in the dependent state. Reconfiguration is required under two conditions. First, there are the normal changes because of phase changes in the mission; e.g., new programs are required during the coast phase which are different from the requirements of the Mars orbital phase. Second, reconfiguration may be required upon a failure or malfunction of a cell, group, bus, etc. Reconfiguration procedures for phase changes are designed to effect a smooth transition for the periodic programs of one phase to those of another. Reconfiguration around failures results in the executive scheduler program being called and given a new hardware resources table. If the tasks cannot be handled by the group, the system executive

352

L. J. KOCZELA

is informed. The system executive then attempts to reschedule and allocate the tasks throughout the entire computer system. The group executive is required to interface with the group that contains the system executive. This interface involves task assignments, communication of backup data, use of the intergroup bus for communications. etc. 8.2 System Executive

In addition to the group executive functions presented in the previous section. one of the group executives also contains additional functions giving it the capability of a system executive. The system executive is designed to coordinate the groups and not really to control them. By this means. the system reliability is increased. The system executive contains a complete up-to-date list of the total hardware resources in the computer system. It is responsible for assigning the tasks throughout the computer system. The system tLxecutive is responsible for control of the intergroup bus in much the same manner as the group executive is responsible for control of the iiiteroell bus. l'he system executive interfaces with the group switches. and essentially this is similar to its acting like the group executive and the group switches' looking like cells. 'l'he system executive follows a routine that is quite similar to the control system resources routine described above. The system executive is forced to handle many cases of reconfiguration: phase changes. faulty assignment of tasks, and failures. The most difficult reconfigurations result from the latter two cases. Both are handled in a similar manner by cntenng the executive scheduler routine and proceeding to reassigri tasks aqong the groups. 8.3 Cell Executive Each cell in a group r e q ~ i r e sa cell executive routine. This routine varies in size and complexity from cell to cell depending on the specific tasks to he performed in each cell. In any cast the cell cxecutive must be a small. minima1 program. Almajor part of the cell executive is that of processing interrupts. Some of tht. types of interrupts are (1)machine errors, ( 2 ) intercell bus 1-0.( 3 ) illegal data such as attempted division by zero, (4)illegal operation, and ( 5 ) real time clock going to zero. ACKSOWLE:DGSIEXTS l'hc author \\ isties to express: his applcciatioii to those individuals who hit\-e assisttd him i i i thr devctlopment of the distributed procrssor orgsnization. Parti-

cular thanks arc drie to Mr. G. \-. K a n g for his iiitcrcst in the project, Mr. P. N. Bogur for his efforts i l l groiip arichtwtiire arid soft,\varc analysis. and Mr. G. J. Burnctt for his efforts in the evaluation of parallel computer organizations.

THE DISTRIBUTED

PROCESSOR ORGANIZATION

353

REFERENCES

1 . Garner, H. L., A study of iterative circuit computers. Univ. of Michigan, Ann Arbor, Mich. Rept. AL-TDR-64-24, April, 1964. 2 . Held, M., and Karp, R., A dynamic programming approach to sequencing problems. SOC.Ind. Appl. Math. 10, 196-210 (1962). 3 . Hcller, J., Sequencing aspects of multiprogramming. J . Assoc. Computing Ma,chinery 8, 426-439 (1961). 4 . Holland, J., A universal computer capable of executing an arbitrary number of sub-programs simultaneously. Proc. Eastern Joint Comp. Conf ., 1959, pp. 108-1 13. 5 . Hu, T. C., Parallel sequencing and assembly line problems. Operations Res. 9, 841-848 (Nov.-Dec., 1961). 6 . Kilbridge, W., A review of analytical systems of line balancing. Operations Res. 10, ,626-638 (Sept.-Oct., 1962). 7. Klein, M., On assembly line balancing. Operations Res. 11, 274-281 (MarchApril, 1963). 8. Koczela, L. J., Study of spaceborne multiprocessing phase I1 final repoft. C6- 1476.22/33, North American Rockwell Corp., Autonetics Div., Anaheim, California, May, 1968. 9. Koczela, L. J., Study of spaceborne .multiprocessing phase I final report. C6-1476.10/33, North American Rockwell Corp., Autonetics Div., Anaheim, California, April, 1967. 10. Martin, D. F., The automatic assignment and sequencing of computations on parallel processor systems. AD628220, Univ. of California, Los Angeles, January, 1966. 11. Murtha, J. C., Highly parallel information processing systems. Advan. Computers, 7 , 2-113 (1966). 12. Petritz, R. L., Technological foundations and future directions of large scale integrated electronics. Proc. Fall Joint Comp. Conf., 1966. 13. Schwartz, E. S., An automatic sequencing procedure with applications to parallel programming. J . Assoc. Computing Machinery 8, 513-537 (1961). 1 4 . Simpkins, Q . W., Fedde, G. A., Dunn, R. S., and Petschauer, R. J., Position papers for main frame memory technorogy debate. Proc. Fall Joint Comp. Conf., Anaheim, California, Nov.,1967. 15. Slotnick, D. L., Unconventional systems. Proc. Spring Joint Comp. Conf., April, 1967. 16. Slotnick, D. L., The Solomon computer. Proc. Fall Joint Cotnp. Conf., 1962, pp. 97-107. 1 7 . Warner, R. M., Jr., Comparing MOS and bipolar integrated circuits. I E E E Spectrum 4, 50-58 (1967).

This Page Intentionally Left Blank

Author Index Numbers in parentheses are reference numbers and indicate that a n author’s work is referred to although his name is not cited in the text. Numbers in italics show t,he pages on which the complete references are listed. A

C

Abrahams, P., 53(1), 57, 110 A d a m , E., 118(3), 172 Afuso, C., 12(9), 18(9), 21 Agusta, B., 220(l), 234 Alilyunas, P., 247(1) 283 Allen, E. L., Jr., 195(48), 236 Allen, L. E., 117, 119(5), 123, 126, 172 Alt, F. L., 117, 172 Andrew, N. D., 127(61), 175 Archibald, R. D., 119(7a), 172 Armstrong, D. B., 195(2), 234 Aspinall, D., 14(6),21

B Backer, P. O., 127(8b), 172 Bacon, C. R. T., 131(59), 175 Bardell, P., 220(1), 234 Bargellini, P. L., 249(3), 284 Bar-Hillel, H., 115, 125,131,132(8), 147(8), 172 Beelitz, H. R., 232, 233(3), 234 Bensing. R. C., 157(93), 176 Bibb, J. I., 275(10), 284 Bilous, O., 190, 234 Birch, B. J., 115, 172 Blair, J., 246(4), 284 Bloch, E., 208(5), 234 Bobrow, D. G., 56, 57, 108, 110 Boehm, B. W., 264(5), 284 Bohnert, H. G., 127, 172 Bourne, C. P., 115, 172 Brennan, P. A., 212, 235 Brennan, R. D., 27(3, 8), 49 Brewer, D. E., 222, 234 Brooks, R. €5. S., 117(5), 119(5), 123(5), 172 Buchman, A., 247(6), 284 Bussell, B., 275(10), 284

Calucci, E., 7( l ) , 20 Canaday, R. H., 202, 234 Caracciolo di Forino, A., 108, 110 Carr, E., lO(S), 21 Cassels, J. W. S., 115, 172 Castricci, P., 220(1), 234 Catt, I., 228, 234 Chartrand, R. L., 118(12), 172 Chen, C. Y . , 211(91), 212, 234, 238 Christensen, C., 108(9), 110 Chung, D. H., 211(10), 234 Clevinger, F. M., 125(13), 153(13), 157(13), 172 Clymer, A. B., 33(4), 49 Cohen, J., 56, 110 Cohen, L., 217, 234 Condon, D. C., 181(13), 216(24), 235 Conte, A. G., 118(16), 172 Conway, M. E., 232, 233(14), 235 Creveling, C. J., 260(25), 284 Crocker, S. D., 114(36), 174

D Davis, E. If., 186(15), 235 Davis, R. P., 143, 173 Denington, R. J., 259, 284 Dennis, S. F., 135, 147, 148(29), 153(17, 18, 29, 30), 157(29), 173 Dhaka, V. A., 211(91), 235, 238 Dickerson, F. R., 117, 123, 125, 148, 156, 173 Dietemann, D. C., 129(20a), 173 Dreyfus, H. L., 114, 173 D’Stefan, D. J., 212(36), 226(36), 236 Duggan, M. A., 119, 173 Dunham, B., 205, 235

355

356

AUTHOR INDEX

Dunn, R. J., 200( 19), 235 Dunn, R. S., 285(14), 3.53

E Earle, J., 205, 25.5 Eastlake,-D. E., 114(36), I74 Edmundbon, H . P., 133. 134(24), 17.3 Eduard5, R. IV., 157(25a), 173 Edzhubov, L. G., 118(26), 127(61), 173, 175 Eldridge, IV. B., 135, 147, 148(29), 153 ( 2 7 , 28, 29, 30), 154, 157(29), IT3 Ellonhogen, H., 118(31), 173 Elspas, B., 205, 23.5 Engel, R. D., 33(14), 49 England, '1V. A., 273(9), 284 Ergott, H . L., 253(24), 284 Esch, J. TV., 12(9), 18(9), 21 Estrin. G., 275( l o ) , 284 Eysman, I. I., 118(32), I 7 3

F Fagg, P., 2 0 7 ( 2 2 ) , 2.3.5 Faiman, A I . , 10(8), 21 Farber, D. J., 92(12), 93, 110 Farina. D. E., 214(23), 216(24). 235 Fetltlr, G. A , . 287(14), 353 Frinberg, I., 190(4). 212(9), 234 Fels. E. ) I . , 134, 143, 174, 174 Finch. I<. R.. .727(25), 235 Fiortlalisi. lT. E., 121(:34), 157(34). 174 Fisher. G. J . , 204, 2S.i Flynil, 31. J., 193, 23.5 Fogel, G. I)., 28(7), 49 Frrctl, K. S . , llS(35). I74 Freeman, D. S . . 195(75), 235 Freitag, H., 199(2Y),2.35

G Gaines, B. R . , 12(3),20 Gallizia, A., 127, I74 Garner, H. L., 196(1), 353 Garth, E. C., 228(8), 234 Geisslw, E., 246(4). 284 Gelernter, H., 84, 110

Giese, C., 33(5), 49 Glinski, G. J., 212, 237 Golomb, S. W., 204, 238 Greenblatt, R. D., 114, 174 Grimmer, R. C., 267(11), 284 Griswold, R. E., 92(11, 12), 93(12, 14), 110 Guckel, H., 212, 235 Gunn, J. B.. 1, 21 Guzman, -4., 108, 110

H Haley, S. R., 140, 174 Halloran, N. A., 118(38, 39), 174 Hamilton, D. J., 205(47), 236 Harris, A , , 118(40), 119, 121(41), 124, 157(41), 174 Harris, D. J., 152, I 7 4 Hart, T. W., 220(30), 228(30), 235 Heightley, J . U., 190(31),235 Held, M., 292(2), 353 Holler, J., 292(3), 353 Henle, R. A., 231, 23.5 Herzog, G., 181(33), 211(33), 232(33), 236 Hess, 8 . W., 118(43), 174 Hill, L. D., 231, 235 Hobbs, L. C., 193, 236 Hoffman, P. S., 147, 174 Holland, J . , 296(4), 353 Hopkin*, A. L., 270( 12), 284 Hoppenfrld, E. C., 155, 174 Horty, J. F . , 131(46, 47, 48, 48a, 59), 135(46), 138, 141(110), 142, 143, 154(110), 161, 174, 175, 177 H u , T. C., 291(5), 333

1

Igaraahi, Ryo, It., 228, 236 Isaacs, H. I., 118(52), 175 Iturriaga, R., 52(29, 31), 111 Iwersen, J. E., 212(36), 226, 236

J Jacobi, G. T., 253(29), 284 Jacobs, J., 134, 174

Jacobs, 31. C . , 118(53), 175

357

AUTHOR INDEX Jacobstein, J. M., 121(34), 157(34), 174 James, P. A., 117(5), 119(5), 123(5), 172 Jeansonne, G. E., 200(19), 235

K Kahng, D., 208(38), 229, 236 Kalikow, M., 136, 175 Karp, R., 292(2), 353 Kask, L. I., 127(61), 175 Kayton, I., 122(57), 134, 138(57), 148, 175 Kehl, W. B., 131(59), 175 Kent, A. K., 152, 174 Kerimov, D. A,, 127(60], 152, 175 Kilbridge, W., 292(6). 353 Klarman, K., 247(6), 284 Klass, P. J., 272(14), 284 Klein, M., 292(7), 353 Klein, T., 214, 236 Klug, U., 118(64), 175 Knowlton, K. C., 74(19), 111 Koczela, L. J., 286(8,9),293(8),350(8),353 Korn, G. A., 26(6), 49 Kort, F., 118(65), 175 Krausz, A., 259, 284 Kress, R. W., 28(7), 49 Kroemer, H., 1(4), 21 Kwong, K., 203(92), 238

L Lander, L. J., 114(66), 175 Langdon, J. L., 190(4), 212(9), 234 Lathrop, J. W . , 180, 181(41), 184(4I), 199(41), 236 Lawlor, R. C., 118(73), 119, 176 Lawsin, H. w., 79, 111 Leary, F., 249(16), 284 Lebedev, P. N., 127(61), 175 Lebowitz, A. I., 118(74), 176 Lehmer, D. H., 115, 176 Lehmer, E., 115, 176 Lepselter, M. P., 189, 207(43), 236 Lin, H. C., 203(92), 238 Lincoln, A. J., 229(89), 230(89), 238 Linden, B. L., 118(79), 176 Linebarger, R. N., 27(8), 49 Littlewood, D. E., 149, 176 Lo, A. W., 205(44), 236

Loevinger, L., 124, 149, 176 Lombardi, L. A., 108, 1.71 Lovingood, J., 246(4), 264 Low, P. R., 193, 236 Lowe, R. R., 266, 284 Lubin, J. F., 27(16), 49 Luce, R., 239, 284 Luce, R. L., 209(80), 211, 236, 238 Luhn, H . P., 134, 176 Lukaszewicz, L., 106, 111 Lynn, D. K . , 205(47), 236 Lyons, J. C., 156(87, 88), 176

M McCabe, L. B., 118(89), 176 McCarthy, J . , 69(25), 111 McIntosh, H., 108, 110 McLeod, J., 24(10), 33(9, l l ) , 39(12, 13), 49 Madnick, S., 56, 111 Maling, K., 195(48), 236 Mallery, P., 190(31), 235 Mann, W. C., 253(27), 284 Maretti, E., 127(35a), 174 Marke, J. J . , 121(34),157(34, go), 174, 176 Martin, D . F., 292(10), 353 Mattern, C. L., 131(91),176 Matthews, C., 247(6), 284 Melton, J. S., 157(92, 93), 176 Menne, A., 118(94), 176 Meyer, C. S., 205(47), 236 Miller, B., 271(22), 272(19, 21), 273(20, 23), 284 Miller, N., 209(57), 237 Mills, W. H . , 115(77), 176 Minnick, R. C., 202, 203(49, 50, 51), 236 Mitchell, D. S., 131(59),175 Mixon, J., 118(95), 177 Mollame, F., 127(35a), 174 Moore, G. E., 214(53), 237 Morgan, R. T., 157, 177 Moss, T. A., 259, 284 Moyle, K. L., 207(73), 237 Murphy, B. T., 190(54), 212, 226(36), 236, 237 Murphy, D. L., 56, 110 Murphy, D. W . , 211(56), 237 Murray, D. E., 22S(S), 234 Murtha, J. C., 292(11), 296(11), 353

358

AUTHOR INDEX

N Sagel. S. S , 118(9i), 177 Narud, ,J. A.. 209(57), 237 Seshit, R. A.. 33(14), 49 h’evala, K. I)., 209(i4), 2.37, 238 Newell, A., 56(28), 84(28), lOZ(ZS), 111 Nievergelt, J., 106, I l l Siiisirn, S., 222(6), 2.34 S i x , L. S., llX(99), 177 S o t z , W.A., 192, 195, 2.37, 2.38 Xoyce, K.S., 193(60), 2.37

0 O’Connrll, Jt. K., 229(89), 230(89), 268 Olekniak, R . E., 239(89), 230(89), 238 Opler, A,, 233, 237 Ovshinsky, S. R., 6(5), 2 l

P T’alniirri, . l . A , , 211[10), 234 Pao. H. C.. 229(89), 23O(S9). 238 Paradics, F., l18(100), 1 7 7 Parkin, T. R., 114(66), 17.1, Perkrnr, H . A , , 227. 237 Prrlie, A. J , , 52(29. 31). 84, 111 f’etritz, R. L.. ISl, 1S4(64), 257, 287(12), 29?( I?). 3.iJ Pctschaurr, H . J., 287 (14). 3.5;l Pleshko. P., 225. 2.76, 2 3 ; €’oap~.J . F.,93( 14). 110 Podraza, G . V., 222tB). 234 Polonsky. 1. P . , 92(11, 12). 93(12. 14). 110 Popprlbaum. \j.. J., l o ( * ) , 11(i). 12(9), I4(6), 18(9),21 l’ricr, J. E., 203. 2.J; Prier. 31. 0.. 121(34), 155(34), 174

R Ragan, L., 118(108), 17; Ragazzini, J . R., 24(15), 4Y Raiffa. H., 239, 284 Randall, K. H., ?4(15). 4!/ Raphael, B., 57. I10 RcynofcL, J. C‘., 109(32), 111 Ribeiro, S. T., 12(1U),21

Rice, R., 193, 237 Riddles, A. J., 118(104), 177 Rohn, P. H., 157(104a), 177 Rosin, R. P., 80, 111 Ross, D. T., 68, I I 1 Rozenherg, D. P., 253(24), 284 Ru.ssell, F. A,, 24(15), 49

S

Sah, C. T., 183(86), 238 Salrnond, J. W., 116, 177 Sammet, J. E., 52(36), 111 Samuel, A. L., 116, I 7 Y Schmidt, J . D., 225, 227, 237 Schwartz, E. R., 292(13), 353 Schwarz, .I. R., 205(78), 2.38 Sechler, R. F . , 211(70), 237 Seeds, R. H., 190(71), 207(73), 209(74), 212, 237, 238 Seelhaeh, M’. C., 209(57), 237 Selfridge, J. L., 115(77), 176 Seshu. S.. 195(75), 2.38 Shaw, J. C . , 102(27), 111 Sieburg, J., 140, 177 Sirgfeldt, H. J., 118(43), 174 Sirnitis, S.. 115, 177 Simon, H. A , , 114, 177 Simpkins, Q . by., 287(14), 3-53 Slotnick, D., 18(11), 21 Slotnick, D. L., 297(15, 16), 3.53 Smith, C . I’., 118(89), 176 Smith, D. K., 84, 111 Smith, 31. G., 192, 2.38 Smith, fV. R., 209(74), 238 Spandorfrr, L. >I., 201(i7), 203(77), 204(79), 205( SH), 232( 14), 233( 14), S 5 , 238

Spirgel, P., 209, 238 Springer, E. IT., 141(110), 154(110), 177 Stabler, E. P., 260(25), 284 Standish, T., 52(31), 111 Stanton, T. S., 273(9), 284 Stevens, 31. E., 119, 122(110a), 125(110a), 129(110a), 143(110a), 177 Strube, A. R., 211(70), 237 Pwanson, D. R., 143, I77 Swaym, X., 117, 1 7 7 Sirinnerton-Dyer, H. P. F., 115, 172, I 7 7 Sze, S. hI., 208(38), 229, 256

359

AUTHOR INDEX

T Talmadge, R., 251, 284 Tapper, C., 117, 121(116), 123, 132, 139, 152, I78 Teichroew, D., 27(16), 49 Teitelman, W., 108, 110 Terman, L. M., 225, 226, 237 Thomas, W. H. B., 157(118), 178 Thornton, C., 84(30),111, 188(81),217(81), 238 Titus, J. P., 118(119), 178 Tombs, N. C., 183, 238 Tonik, A. B., 204(79), 230(83), 238 Toru, G., 228(35), 236 Triebwasser, S., 238 Truitt, T. D., 27( 16), 49 Turnbull, J. R., 211(70), 237

V Vadasz, L., 214, 238 Von Ardenne, M., 7(12), 21 von X’eumann, J., 17, 21

Warslow, M., 266, 284 Weaver, J. B., 118(43), 174 Wegener, H. A. R., 229, 230, 238 Weindling, M. N., 204, 238 Weissman, C., 69(39), 111 Weizenbaum, J., 84, 116, I l l , 178 Westin, A. F., 118(122), 178 Whelan, J. N., 118(43), 174 Wiener, F. B., 115, 178 Wilcox, R. H., 253(27), 284 Wilson, R. A., 123, 125, 148, 152(125), 153(125), 157(125), 178 Wing, O., 204, 235 Wolkenstein, N., 108(7), 110 Wood, J. R., 278(28), 284 Wu, B. P. F., 211(91), 238 Wuorinen, J. H., 212(36), 226(36), 236 Wyllys, R, E., 133, 134(24), 173

Y Yngve, V. H., 52(41), 104, 111 Yovits, M.C., 253(29), 284 Yu, K. K., 203, 238

W

Walston, C. E., 115, 178 Wanlass, F. BI., 183(86), 238 Warner, R. hl., Jr., 182, 200(87), 238, 287(17), 363

L

Zilloria, R. L., 119(7a), 172 Zitlau, P. A., 118(43),174

Subject Index A Acckss time, 220 Accumulator, 338 Adaptability, 35 Address, cell, 303 Aerospace command and control, 249 Aerospace computer, 1 3 9 Algebraic equations, 32 Algebraic manipulation languages, 52 ALGOL,56. 58, 61, 63. 64, 78 AMBIT,108 Analog advantages, 30 Analog-digital communication, 26 Analog-digital converter, 44 Analog hardware, 26, 46 Analog programming, 47 Analog software, 46 Analog storage, 12 Apollo mission. 270 Applied parallelism, 289, 294 Architecture, 301 Ardenne tube. 7 Array computer, 17 Arrays, 59, 100 ARTRIX.11 Assembly line balancing, 291 Assignment of parallel operations, 29 I , 293 Astronaut. 37 Audio information, 1 1 Automatic indexing. see Machine indexing Availability, 329 Avionic systems, 242, 251 .4WACS. 249

B Background tasks, 35 1 B.tchup executive, 334. 337

Balancing, assembly line, 291 Battery system, 260 Beam leads, 186, 189, 226 Bipolar circuits, 180, 184 component density, 184 logic, 206 memory. 2 nonsaturating, 209 saturating, 206 Bipolar transistor, 180, 184, 203, 205, 213 Bit organization, 220 Euffer memory, 232 Bulk storage unit, 334, 337

C Cardiac function, 36 Catastrophic failure, 252 Category of instructions, 308 Cell, 297, 338 Cell address, 303 Cell executive. 352 Cell failure, 325 Cell identification, 303 Cell states. 301 Cell switch, 338 Cellular arrays. 202 Change problem. 192 Circuit density, 184 Citation indexes. 1 2 1 Classroom demonstrations, 3 1 Clocking four-phase. 2 15 two-phase, 2 16 COBOL, 5 2 , 60, 78 COGENT. 109 C'OMIT,5 2 . 92, 104-106, 108 Command and control, 8, 249 Commands, global, 302 Communication buses, 346

360

SUBJECT INDEX

.

Compilers, 73 Complementary pair transistor, 183, 214 Complementary transistor logic, 209, 2 16, 263 Computation reduction ratio, 295 Computational graph, 293 Computational requirements, 286 Conditioner, 323, 325 Content-addressable memory, 196, 228 Continuous system simulation language (CSSL), 28 Control, 295, 299, 315 Control cell instructions, 309 Control line, 44 Control word, 303, 304 Controller cell, 298, 305, 320, 350 Controller state, 302 CONVERT, 108 Cooling, 267 Coordinate searching, 126 Core memory, 2 19 Cost, 191, 261, 280 development, 192 fabrication, I 9 1 layout, 191 programming, 193 silicon, 193 start-up, 192 testing. 191 Counter, 313 Creep vidicon. 8 Crossunder interconnection, 180, 266 Current mode logic. 196-197, 206. 209 Custom interconnection strategy. 195 Cut points. 203 Cycle time, 221. 226

D Data puns, 54, 72 Declarations, 61 Defect, 181 Defect density. 189 Definition of simulation, 24 Degraded performance, 329, 33 I Density circuit, 184 defect, 189 power, 185 Dependent cells, 301

361

Dependent local control state, 305 Description lists, 90, 91 Development cost, 192, 261 Device fabrication, 180 Differential equations, 3 1 Digital advantages, 3 1 Digital-analog converter, 44 Digital software, 27 Diode transistor logic (DTL), 198, 207, 263, 265 Direct coupled transistor logic ( D C T L ) , 207, 263 Discrete systems, 32 Distributed processor, 285, 297

E EAI 680,40 Effectiveness of parallelism, 293 Electrolytic trough, 19 Emitter follower, 209, 212 geometry, 196, 21 1, 212 EOL, 106-109 Equipment cooling, 267 Erasure, 55, 77, 83, 87 Execute mode, 320 Execution of instructions, 308 Executive. backup. 334 Executive group. 300. 329, 331, 334, 349 Executive program. 47, 350 Executive scheduler, 250 Expansion coefficient, 190 Experiment management. 248

F F11 lA, 273 Fabrication cost, 191 Facilities allocation. 276 Failure, 252-157 cell. 315 Failure detection, 326 Failure rate. 266 False drops, 133 Fault, 195 detection, 195 hardware, 328

table, 195 Feedback, 36

SUBJECT INDEX

362

Field effect transistor, 181 First level interconnection, 184, 267 Flight control, 246 FLIP, 108 Flipchips, 186 FLPL, 84 Flying wire leads, 186 FORMAC, 52 Format instruction, 306 Format modifier, 321 Formula ALGOL,52, 56, 57 FORTRAN, 57, 58, 63, 78, 84, 85, 91, 92 Four-phase clock, 2 15 Frequency lists of text words, 128, 130, 135 thresholds, 134 Fuel cell, 260 Full-text retrieval system, 126, 128-149

G Garbage collector, 5 5 , 68 Gate-to-pad ratio, 233 General-purpose, 240, 274 Global commands, 302, 351 Global considerations in indexing, 12 I , 126, 128 Global control, 295, 299, 302, 306 Global instructions, 298, 301, 304, 306, 310, 314, 351 Global state, 302, 303 Grammatical variants of index terms, 130, 134-137, 152 Graphical memory, 11 Group of cells, 297 Group switch, 300, 303, 328, 338, 344 Guidance, 246 Gunn mobility effect, 1

H Hard failure, 252-254 Heart pump, 39 Hierarchical indexes, 124, 125, 137, 154 High accuracy computation, 32 High-current switching, 6 Holland machine, 296 Hologram, 16 Hybrid advantages, 3 1 Hybrid comDuter. 10, 25

I IBM 1800, 273 IHAS, 272 ILAAS, 273 ILLIAC, 18, 295 Ill-structured problems, 116, 123 Incremental computer, 108 Independent cell, 301, 303, 319 Index bank, 338 Indexes citation, 121 hierarchical, 124, 125, 137, 154 linear, 124, 125 Indexing, 339 for information retrieval, 126-127 global, 121, 126, 128 KWIC, KWOC, 121, 141, 155 local, 121, 128 machine, 125, 133, 139, 153, 154 manual, 122-125, 155-157 languages, standardized, 126 Industrial Analysis and Control Council, 29 Information explosion, legal, 116-1 17 Inner loops, 32 Input-output, 323 Instruction modification, 307 Instruction word format, 338 Integrated circuit, 179, 265 Integrated helicopter avionics system, 272 Integrated light attack avionics system, 273 Intelligent display, 20 Interaction, man-machine, 126 Intercell communications, 298, 302, 304, 346, 348 Interconnection, 184 crossunders, 180, 226 first level, 184, 267 layout, 195 metallization, 180, 225 multilayer, 185, 204, 267 nonplanar, 204 patterns, 203 second level, 181, 212, 267 strategies, 194 custom, 195 discretionary wiring, 194 fixed interconnection pattern, 194 master, 195

SUBJECT INDEX three level metal, 212, 267 vias, 181, 196 Interface, 323 Intergroup bus, 300 Intergroup communication, 348 Intermittant failure, 252, 254-257 Interpreters, 71-73 Interrupt, 44, 276, 351 I/O cells, 324 1-0 control, 251 IPL, 52, 84, 102-104, 106 Iteration, 29

J Job shop scheduling, 291 JOVIAL, 60 Jurimetrics, 118, 119, 149

K KDP crystal, 7 KLS, 84 KWIC, KWOC indexes, 121, 141, 155

L L", 52, 74-78, 103, 104, 109 Large-scale integration, 6, 15, 179, 232, 266 Largest common segment of two lists, 62 Lark simulator, 24 Layout cost, 191 LEM, 270 Level, 303, 328 Level register, 302, 304, 3 14, 3 16, 3 18 Linear indexes, 124, 125 LISP, 52, 53, 57-74, 92, 93, 101 List(s), 52 description, 90, 91 multilevel, 52, 86 processing, 8 1-84 languages, 52 property, 72 pushdown, 61, 77,91, 103 representation of, 53-56 symmetric, 85 threaded, 84 Local considerations in indexing, 121, 128

363

Local control, 295, 299, 302 Local control state, 302, 305, 316 Logic, symbolic, applied to law, 118, 119, 126, 127 Logical decisions, 32 Long-term analog storage, 12 LSI, 6, 15, 179, 232, 266, 287 LSI memories, 218, 232 Lunar Excursion Module. 270

M Machine indexing, 125, 133, 139, 153, 154 Macros, 73, 76, 107 MAD, 57,85 Magnetic film memory, 219 Maintainability, 257, 278 Maintenance cost, 261 Man-computer rapport, 32 Man-machine interaction, 126 Manipulation, algebraic, 52 of data on lists, 88, 89 Manual indexing, 122-125, 155-157 Margins (in printing), 67, 93 Mars orbital phase, 335 Masking photomasking, 180 redundant, 181 tolerances, 184, 211, 213, 220, 226 Master interconnection strategy, 195 Measures of relevancy, 120 Memory, 263 analog, 12 buffers, 232 content-addressable, 196, 228 core, 219 graphical, 11 LSI, 232 magnetic film, 219 main, 219 plated-wire, 15 read-only, 229, 233 scratchpad, 180, 232 wave-front, 16 Memotron-vidicon pair, 11 Metallization interconnection, 180, 225 Metal-oxide semiconductor (MOS), 15, 180 component density, 184

364

SUBJECT INDEX

hletal-oxide semiconductor (MOS) (Corzr.) low threshold, 224 threshold stabilization, 183 threshold voltage, 181. 213, 229 variable threshold, 203 Microminiaturize, 4 Microprogram. 233 Microprogrammed control. 275 Minimal backup executive, 334 Minuteman ICBM, 271 hlission success. 329 Mobility effect, 1 Mode control, 41 Modifier, format, 321 instructions. 307 Module, 267 Monsanto Benchmark Problem, 33 MOS. 15. 180. see also Metal-oxide semiconductor MOS transistor. 180, 182. 203, 213, 219, 22 I Multilaver interconnection. 185, 204, 263, 267 hlultilevel lists, 52, 86 Multiple accumulators. 339 Multiprocessor. 277, 286 Multivariable optimization, 26

P

Natural parallelism. 289, 294 Navigation, 246 N D R O memory. 264 Neighbor communication, 297. 299, 324. 327 Noise, 38 Noncritical phase, 330 Nonplanar interconnection. 204 Nonsaturatinp circuits. 209 N-type transistor, 182 Nuclear cell. 260

Packaging. 184, 191 PANON,108 Parallel access, 17 Parallel computer organization, 295 Parallel path. 36 Parallelism, 289. 291, 294, 300 applied. 289. 294 natural, 289, 294 10 PARAMATRIX, Partitioning. 232 Periodic tasks. 351 Phase change, 7 PHASTORstorage cell, 14 PHYSBE,39 Physiological simulation, 33 Pinholes. I8 1 Plated-wire memory, 15 PL/I. 56. 58. 60. 63, 78-84, 101, 109 Pockel's effect chamber. 8 POTENTIOMATRIX, 19 Power. 258-261, 279 conversion, 269 density. 185 Primary system. 337 Print readers. optical, 139 Printed circuit card, 184 Probability of mission success, 329 Production cost. 261 Program counter, 3 13 organization, 250 sequencing, 250 Programming cost, 193 Propagation delay, 183, 185, 206, 211. 212, 214 Property list, 72 P-type transistor. 180, 18 1 Puns. data. 54. 72 Pushdown lists. 61, 77, 91, 103

0

Q

N

Optical print readers. 139 Orbital phase. Mars, 335 Organization, 285 Ovonic threshold $%itch.6 Oxide. 180 thick, 114

QUANTROL. 6

R Read-only memory. 229, 233, 263 Reconfiguration, 325, 329, 35 1 Recursion. 62, 71, 74, 91, 92, 100

SUBJECT INDEX Reduction ratio, 295 Redundant masking, 181 Reference modes, 62, 64, 97 Registers in cell, 341 Relevancy, measures of, 120 Reliability, 223, 230, 252, 265 Reliability requirement, 277, 286 Remote console, 48 Reply instructions, 3 15 Representation of lists, 53-56 of strings, 56 Resistor transistor logic (RTL), 207, 263 Responsa, 152, 153 Rise time, 3 Rollback, 254 Root words, 135, 136, 152 S Saturating bipolar circuits, 206 Saturn, 270 Scheduling, job shop, 291 Scratchpad memory, 180, 232 SDS930, 42 Secondary system, 337 Second level interconnection, 181, 212, 267 Self-check program, 327 Self-test program, 327, 351 Sense amplifier, 221, 227 Sense line, 44 Sensor, 323, 334 Sequencing of parallel operations, 291, 293 through lists, 89 Shallow diffused transistor, 209 Shallow diffusion, 21 1 Shift registers, 216 Signal flow, 41 Silicon, 179 Silicon nitride, 183 Simulation, 23 Simulation Council, 28 Size, 2 SLIP, 52, 54, 56, 84-92, 109 SNOBOL, 52, 54, 57, 92-101, 103, 105, 106, 108, 109 Software, 282 Software analysis, 349

365

Solar cell, 260 Solid-state chip amplifier, 48 Solomon computer, 295 Source of addresses, 306 of data, 307 of instructions, 303 Space mission, 286 Special-purpose, 46, 240, 275 Speed, 2 Standardized indexing languages, 126 Start-up cost, 192 Status control, 275-277 Stochastic computer, 12, 18 Stochastic signal representation, 1 Storage, see also Memory allocation, 76, 87, 88 dynamic, 54 saving, 339 Streaming, 276 String processing, 79-8 I languages, 52 String variables, 95, 96 strings, 58, 79, 93, 94 representation of, 56 Structures, 83, 101 Sublists, 52, 85 Supervisory program, 250 Symbolic logic, see Logic Symmetric lists, 85 Synchronous random pulse sequences, 12 Synonyms, 132, 134, 135, 137-139, 155 System executive, 352 System predesign, 3 1 T Team approach, 34 Technology, 287 Test, 192 cost, 191 Testing of information retrieval systems, 120-121, 141-146 TFX, 273 Thermal conductance, 187 Thesaurus, 138, 155, 156 Threaded lists, 84 Three level metal interconnection, 212, 267 Threshold, 224, 229

SUBJECT INDEX

366

Throw-away modules. 258 Tracing through lists, 89, 90 Transconductance, 21 3, 223 TRANSFORMATRIX, 18 Transistor, 179 bipolar, 180, 184, 203, 205, 213 complementary pair, 183, 214 field effect, 181 MOS, 180, 182,203, 213, 219, 221 n-type, 182 p-type, 180, 181 shallow diffused, 209 Transistor transistor logic (TTL), 207, 263 Transmit mode, 320 Trial-and-error testing Two-phase clock, 2 16

U Ultimate computer limitations, 2 Universal logic, 205 Universal logic blocks, 202

V Valuation, 62, 64 Vehicle management, 246 Vias, 181, 196 Visual information, 1 1 Volatility, 230, 233 Volume, 258-261, 279 W

Wait state, 302, 318 Wave-front storage, 16 Weight, 258-261, 279 Well-structured problems, 116, 123 Wire-routing algorithms, 203 Wiring layers, 185 Word length, 338 Working cell, 298

Y Yield, 190, 194, 211