Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

Analog Circuit Design

Michiel Steyaert • Arthur van Roermund Andrea Baschirotto Editors

Analog Circuit Design Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

123

Editors Michiel Steyaert K.U. Leuven Department of Elektrotechniek ESAT-MICAS Kardinaal Mercierlaan 94 B-3001 Heverlee Belgium [email protected]

Arthur van Roermund Electrical Engineering Technical University Eindhoven Mixed-signal Microelectronics Group Eindhoven Netherlands [email protected]

Andrea Baschirotto Department of Physics University of Milan-Bicocca Milan Italy [email protected]

ISBN 978-94-007-1925-5 e-ISBN 978-94-007-1926-2 DOI 10.1007/978-94-007-1926-2 Springer Dordrecht Heidelberg London New York Library of Congress Control Number: 2011937971 © Springer Science+Business Media B.V. 2012 No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

Preface

This book is part of the Analog Circuit Design series and contains contributions of the speakers of the 20th workshop on Advances in Analog Circuit Design (AACD), which was organized by KULeuven ESAT-MICAS. The workshop was held in Leuven, Belgium, from April 5 to April 7, 2011. I also would like to give my gratitude for the help to organize the workshop to Danielle Vermetten, Chris Mertens, Ben Geeraerts, Valentijn De Smedt and Hans Meyvaert. This book comprises three Parts, covering advanced analog and mixed-signal circuit design fields that are considered as very important by the circuit design community: • Low-Voltage Low-Power Data converters • Short Range Wireless Front-Ends • Power Management and DC-DC Each Part is set up with six papers from experts in the field. The aim of the AACD workshop is to bring together a group of expert designers to discuss new developments and future options. Each workshop is then followed by the publication of a book by Springer in their successful series of Analog Circuit Design. This book is number 20 in this series. The books can be seen as a reference for all people involved in analog and mixed-signal design. The full list of the previous books and topics in the series is given next. We sincerely hope that this 20th book continuous the tradition and provides a valuable contribution to our Analog Design Community. Michiel Steyaert

v

vi

Preface

The topics covered before in this series: 2010

Graz (Austria)

2009

Lund (Sweden)

2008

Pavia (Italy)

2007

Oostende (Belgium)

2006

Maastricht (The Netherlands)

2005

Limerick (Ireland)

2004

Montreux (Swiss)

2003

Graz (Austria)

2002

Spa (Belgium)

2001

Noordwijk (The Netherlands)

2000

Munich (Germany)

1999

Nice (France)

1998

Copenhagen (Denmark)

1997

Como (Italy)

Robust Design Sigma Delta Converters RFID Smart Data Converters Filters on Chip Multimode Transmitters High-speed Clock and Data Recovery High-performance Amplifiers Power Management Sensors, Actuators and Power Drivers for the Automotive and Industrial Environment Integrated PAs from Wireline to RF Very High Frequency Front Ends High-speed AD Converters Automotive Electronics: EMC Issues Ultra Low Power Wireless RF Circuits: Wide Band, Front-Ends, DACs Design Methodology and Verification of RF and Mixed-Signal Systems Low Power and Low Voltage Sensor and Actuator Interface Electronics Integrated High-Voltage Electronics and Power Management Low-Power and High-Resolution ADCs Fractional-N Synthesizers Design for Robustness Line and Bus drivers Structured Mixed-Mode Design Multi-Bit Sigma-Delta Converters Short-Range RF Circuits Scalable Analog Circuits High-Speed D/A Converters RF Power Amplifiers High-Speed A/D Converters Mixed-Signal Design PLLs and Synthesizers XDSL and other Communication Systems RF-MOST Models and Behavioural Modelling Integrated Filters and Oscillators 1-Volt Electronics Mixed-Mode Systems LNAs and RF Power Amps for Telecom RF A/D Converters Sensor and Actuator Interfaces Low-Noise Oscillators, PLLs and Synthesizers (continued)

Preface

vii

(continued) 1996 Lausanne (Swiss)

1995

Villach (Austria)

1994

Eindhoven (Netherlands)

1993

Leuven (Belgium)

1992

Scheveningen (The Netherlands)

RF CMOS Circuit Design Bandpass Sigma Delta and Other Data Converters Translineair Circuits Low-Noise/Power/Voltage Mixed-Mode with CAD tools Voltage, Current and Time References Low-Power Low-Voltage Integrated Filters Smart Power Mixed-Mode A/D Design Sensor Interfaces Communication Circuits OpAmps ADC Analog CAD

The book contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of • Low-Voltage Low-Power Data Converters – Chaired by Prof. Anderea Baschirotto, University of Milan-Bicocca • Short Range Wireless Front-Ends – Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology • Power management and DC-DC – Chaired by Prof. M. Steyaert, Katholieke University Leuven Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

Contents

Part I

Low-Voltage Low-Power Data Converters

1

Power Minimization in ADC Design . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . Willy Sansen

3

2

Low-Power Pipelined A/D Conversion . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . Boris Murmann

19

3

Low-Power Successive Approximation ADCS for Wireless Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . Jan Craninckx

4

Oversampling Converters Beyond Continuous-Time Sigma-Delta for Nanometer CMOS Technologies . .. . . . . . . . . . . . . . . . . . . . A. Di Giandomenico, L. Hernandez, E. Prefasi, S. Paton, A. Wiesbauer, R. Gaggl, and J. Hauptmann

39

59

5

Considerations for Cost-Efficient Calibration of Scaled ADCs . . . . . . . Marian Verhelst, Erkan Alpman, and Hasnain Lakdawala

6

A 12b 2.9 GS/s DAC with IM3 < 60 dBc Beyond 1 GHz in 65 nm CMOS .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 119 K. Bult, C.-H. Lin, F. van der Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, and X. Liu

Part II 7

89

Short-Range Wireless Front-Ends

Short Range Radio Communication – Novel Applications and Their Physical Layer Requirements . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 139 William G. Scanlon

ix

x

Contents

8

Ultra Low-Power Wireless Body-Area Sensor Networks . . . . . . . . . . . . . . 145 G. Dolmans, F. Bouwens, A. Breeschoten, B. Busze, P. Harpe, L. Huang, X. Huang, M. Konijnenburg, V. Pop, M. Vidojkovic, Y. Zhang, C. Zhou, and H. de Groot

9

Low Power RF Power Harvesting Enabling More Active Tag Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 163 Tim Piessens, Yves Geerts, Wim Vanacken, Eldert Geukens, Bram De Muer, Tim Butler, and Bob Hamlin

10 Low Power RF Frontend for Wireless Sensor Networks .. . . . . . . . . . . . . . 175 Frank Henkel, Thomas Leineweber, Mohamed Gamal El-Din, and Ralf Wilke 11 Ultra High Data Rate CMOS Front Ends . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 199 Reza Mahmoudi and Arthur van Roermund 12 Extremely Wideband CMOS Circuits For Future THz Applications Lorenzo Tripodi, Marion K. Matters-Kammerer, Dave van Goor, Xin Hu, and Anders Rydberg Part III

237

Power Management and DC-DC

13 State-of-the-Art of Integrated Switching Power Converters.. . . . . . . . . . 259 Gerard Villar Piqu´e and Henk Jan Bergveld 14 Data Conversion Pulse-Width Modulators for SwitchMode Power Converter Digital Control .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 283 Eduard Alarc´on, Vahid Yousefzadeh, Aleksandar Prodi´c, and Dragan Maksimovi´c 15 Advanced Power Management for Low Power Medical Applications 305 Kristof Quaegebeur and Jan Crols 16 Feedforward Control of Switching Regulators .. . . . .. . . . . . . . . . . . . . . . . . . . 321 Richard Redl 17 Device Optimization to Assess Losses and Ringing Issues in Integrated Synchronous Buck Converters .. . . . . . .. . . . . . . . . . . . . . . . . . . . 339 J. Roig and F. Bauwens 18 Control of Fully Integrated DC-DC Converters in CMOS . . . . . . . . . . . . 357 Tom Van Breussegem, Mike Wens, and Michiel Steyaert

Part I

Low-Voltage Low-Power Data Converters

The first part of the book deals with the design and implementation of “low-voltage low-power data-converters”. The topics have been addressed to the different dataconverter topologies, to the different implementation issues (from topology and system level down to circuit level). Moreover the presented solutions have been always analyzed in consideration of the effects of the CMOS technology scaling that reduces device analog performance but offers efficient digital signal processing for analog performance improvement. In the first paper, Willy Sansen gives an overview of the different ADC topologies, emphasizing the aspects relative the power consumption minimization. This contribution presents a good scenario of the different ADC topologies, like flash (using interpolation & folding), pipeline, SAR and Sigma-Delta, which have been introduced and compared with the data from the implementations most recently reported in literature. The second paper from Boris Murmann reviews recent developments and low-power design techniques for high-speed pipelined ADC. The fundamental operation principles are introduced, and, then, widely used low-power techniques are summarized. Finally some ideas that have been proposed in recent research publications are outlined. In the third paper Jan Craninckx discusses the advancements in SAR ADCs design, in particular for wireless transceivers application. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power ADC efficiency up to levels that are out of reach of the typically used pipeline architecture. Moreover, this paper discusses the chargesharing SAR ADC architecture, which proposes a new signal processing method in the charge domain that removes the often-neglected though requirements for the reference buffer. Antonio Digiandomenico et al. propose in the fourth paper low-power largebandwidth implementations of Continuous-Time Sigma-Delta ADCs, where cascaded architectures and time-encoding signal processing have been successfully applied. Two different implementations, PWM-based and VCO-based, are finally described.

2

I Low-Voltage Low-Power Data Converters

In the fifth paper, Mariam Verhelst et al. discuss digitally-assisted performance enhancement strategies to overcome ADC component mismatch limitation, otherwise addressed by increased component sizes and increased power consumption. Trade-off analysis between mismatch compensation in the analog domain (digitally assisted trimming, possibly in combination with up-scaling) vs. the digital domain (digital post-distortion) is considered. The increasing use of digitally enhanced ADC architectures proves to be the main driver for the observed improvement in area and power with CMOS technology scaling. Finally the sixth paper from Klaas Bult et al. analyzes the aspects relative to power reduction in very high-frequency DAC. The case study of 12b 2.9 Gs/s DAC is proposed as a benchmark. Several design technique limiting the DAC performances are introduced and eventual solutions are developed. Andrea Baschirotto

Chapter 1

Power Minimization in ADC Design Willy Sansen

Abstract An overview is given of the different ADCs, in which power consumption has been minimized. First flash ADCs are examined, in which interpolation and folding is used to reduce the number of comparators. Then pipeline and SAR ADCs are shortly reviewed. Oversampling ADCs are discussed in more detail. The noise shaping is carried out with Switched-capacitor, and with opamp/GmC filters. The text concludes with TDC based ADCs.

1 Introduction Excellent texts exist which give a good introduction on ADCs. Examples are the books by Van de Plassche [1], Razavi [2], Maloberti [3] and Johns and Martin [4]. A summary is given in the slide-based book of Sansen [5]. They all provide details on both system and transistor level. All of them compare ADC performance in terms of a FOM in pJoule per conversion step, which is limited by the effective number of bits resolution (ENOB), the bandwidth and the power consumption. The best overview of the state-of-the art is given on the website of Murmann [6]. It is clear that the minimization of the power consumption is the biggest concern of the designer. This is why this texts tries to highlight a number of design techniques which allow exactly that. Examples are drawn from all major categories of ADCs such as flash ADCs in which interpolation and folding is used to limit the number of comparators. Pipeline and successive-approximation ADCs follow shortly. Considerable attention is then paid to oversampling ADCs in which both switched-capacitor and continuous-time filters are used for noise shaping. Finally the capabilities are discussed of ADCs based on Time-to-Digital converters as they are most promising for nanometer CMOS technologies. W. Sansen () KULeuven, Groenstraat 124, 3001 Heverlee, Belgium e-mail: [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 1, © Springer ScienceCBusiness Media B.V. 2012

3

4

W. Sansen

2 Flash/Interpolation and Folding Only three examples are given. The first one by Verbruggen [7] avoids preamplifiers for lower power consumption. The combination of 1-bit folding and a 4-bit flash ADC, using 15 comparators (see Fig. 1.1), leads to an impressive FOM of 50 fJ/conv.step. The bandwidth is 878 MHz. and is realized in 90 nm CMOS. The ENOB is only 4.7 bit as can be expected for high-speed flash converters. Another example is the 6-bit flash ADC which was realized in 45 nm CMOS [8]. Averaging and folding is realized with 65 dynamic comparators, which are all simple differential pairs. The realization (C045 in Fig. 1.2) is about a factor 8 worse than the simulation because of this averaging and folding circuitry, without calibration. The third flash ADC has been selected because of the low supply voltage [9]. Optimum performance is reached at 0.4 V but it operates down to 0.2 V. At 0.4 V the FOM is about 0.1 pJ/conv.step. It is realized in 0.18 m CMOS. This low supply

Fig. 1.1 A 5-bit folding flash ADC with 50 fJ/conv.step

Fig. 1.2 Five-bit folding flash ADC in 45 nm CMOS

1 Power Minimization in ADC Design

5

Fig. 1.3 Highly-digital flash ADC at minimum 0.2 V supply voltage

voltage is only possible when dynamic CMOS inverters are used as amplifiers and all transistors operate in weak inversion. This is discussed in more detail in the next Chapter (Fig. 1.3).

3 Pipeline ADCs All pipeline ADCs need precision amplification to provide the amplified residue to the next stage. This is easily achieved by switching matched capacitors. The amplifiers however take most of the current. A comparison of the types of amplifiers (for 100 MHz GBW and 2 pF CL) shows that the CMOS inverter is by far the best choice, despite its higher noise and its zero PSRR [5]. Its current consumption ITIOT is lowest and its swing is excellent. Moreover it acts as a simple class-AB stage, which allows power savings beyond to what is given in Fig. 1.4. More and more class-AB amplifiers are used in analog blocks, as they only use power when solicited. Multistage amplifiers provide even higher GBW.CL over ITOT ratios [5] but may not be the best choice if other specifications are taken into account. In nanometer CMOS technologies however, weak-inversion operation becomes evident as shown in Fig. 1.5. It gives the inversion coefficient (which is the ratio of the current to the si-wi crossover current) for a two-stage amplifier with 3 GHz GBW (with GBW D fT/16 [5]). The weak inversion asymptote is given as well. It is clear that important power savings can be achieved in nanometer CMOS, because of its high fT values. Other techniques to save power are opamp sharing, capacitor sharing, removing the S/H input stage, etc. They are summarized in [10].

6

W. Sansen

Fig. 1.4 Comparison of types of amplifiers Fig. 1.5 Nanometer CMOS technologies push weak inversion operation

A good example of an inverter based amplifier for a low-power pipeline ADC is shown in Fig. 1.6 [11]. The inverter schematic is clearly distinguished. Switches are used to set the biasing such that the actual current is much lower than in a conventional CMOS inverter. Cross-coupling is used to enhance the gain. A FOM of 72 fJ/conv. was reached in 90 nm CMOS.

4 SAR ADCs Successive-approximation ADCs are ideally suited for low power consumption as they only consist of a comparator, switches and an array of capacitors (see Fig. 1.7) [12]. It is obvious that a dynamic comparator must be used and that the unit capacitance must be minimized. The one in [12] uses 12 fF but in [15] only 0.5 fF is used (see Fig. 1.8). The resulting SNRD can never be high because of lack of

1 Power Minimization in ADC Design

7 To negative half circuit CNP

Stage1 φ1 : Resel φ2 : Sample φ3 : Compare φ4 : Amplify

Stage2

VBP CBP

VCM

Boot-strapped φ4

φ1 P0

φ2

φ4

φ1,3

φ4

CF

VIN

CF φ4

Cs A

φ2

φ4

CBN

VDAC φ3,4

N0 φ1

φ1

VCM

CS

φ4

φ1 VBN

VCM φ2e

φ4e

CNN

To negative half circuit

CNN

To negative half circuit

To negative half circuit

N0

Fig. 1.6 Pipeline ADC with inverters as class-AB amplifiers

Vcomp

Vref

Vref

Reference Switch

Vcomp

Vref 128C

64C

2C

C

+

–

C Comparator

Capacitor Array

CLK

Vin

Successive Approximation Register and Switching Network

D7

D6 D5

Fig. 1.7 Low-power SAR ADC

D4

D3

D2 D1

Vref GND D0

8

W. Sansen Clock input

Analog input

S&H Switched cap. network

Asynchronous logic

!

1.32 um

Digital output

DAC

0.70 um

0.5 fF Unit capacitance

INP INN

OUTP OUTN Ch

C7

C6 C5

C4

C3 C2

C1

C0

Sample CLK D7 D6

D5 D4 D3

D2

D1

D0

Fig. 1.8 Eight-bit 10 MS/s SAR in 90 nm CMOS [15]

good matching. As a result such low-power ADCs are only used for very low-power applications (portable electronics) and medium SNDR (8 : : : 10 bit). On the other hand their FOMs are impressive. It was 2.6 pJ for the one of [12], but 10 fJ/conv. for [13], 4.4 fJ/conv. for [14] and 12 fJ/conv. for [15].

5 Switched-Capacitor † ADCs Oversampling techniques give rise to higher resolutions than what is possible with matching. Three parameters determine the maximum SNDR, the first one of which is the oversampling ratio. The other ones are the multi-(or single-) bit quantizer and the order of the noise shaping filter [16]. At low supply voltages the switches become a problem. It is then easier to switch the amplifiers rather than the switches, as shown in Fig. 1.9 [17]. If class AB amplifiers are used, then excellent FOMs can be obtained. The amplifier used in [17] is s single VGS C VDSsat amplifier which allows supply voltage down to 0.7 V. It is shown in Fig. 1.10. Indeed transistor M2 acts as a source follower. It imposes vin2 on the source of transistor M1, which thus acts a single-transistor differential amplifier. It has a class-AB output as well which gives rise to low quiescent current consumption. The output current can thus be much larger than biasing current IB. Full feedforward is used now in all Sigma-delta modulators to avoid large signals at the input of the first integrator [18]. An example of a 4th order 1MS/s singlebit converter is shown in Fig. 1.11 [19]. It provides 1 MS/s and its FOM is 0.35 pJ/conv.step. Another low-power realization uses full feedforward as well and cascaded CMOS inverters as amplifiers. The minimum supply voltage is 0.7 V and its FOM is 0.1 pJ/conv.step [20]. Its schematic is shown in Fig. 1.12. The bandwidth is only 20 kHz but its power consumption is correspondingly small.

1 Power Minimization in ADC Design

9

Fig. 1.9 Switched-opamp sigma-delta converter section Fig. 1.10 Class-AB differential V-I converter

x

c1

+ +

c2 + c3 –+

I(z) a1

I(z) a2

I(z) a3

I(z) a4

y

+ c4 DAC

Fig. 1.11 Full-feedforward 4th order single-bit †D ADC

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W. Sansen

0.5 1

–1 / 2

Z

1 + + –

Z 0.2

–1 / 2 –1

1–Z

0.4

Z

–1 / 2

–1 / 2 –1

0.1

1–Z

Z

–1

1–Z

2

–1 / 2

Z

+

DAC

Fig. 1.12 Twenty kilo Hertz †D modulator on 0.7 V

Fig. 1.13 Four-bit †D modulator architecture

Fig. 1.14 0.1–20 MHz SC †D modulator

For higher speed and higher resolution, multibit quantizers are required, which puts severe constraints on linearity of the multibit DAC in the feedback loop. Many techniques have been developed such as DEM, DWA, etc. An example is shown in Fig. 1.13 for a 1.2 MHz input more than 16 bit resolution signal [21]. Better performance has been reached recently [22] with a programmable modulator shown in Fig. 1.14. Its FOM is only 0.62 pJ/conv.

1 Power Minimization in ADC Design

11

Fig. 1.15 Ultra-low power amplifier based on a CMOS inverter

Fig. 1.16 SC modulator (left) and CT modulator (right)

The one with the lowest supply voltage (0.25 V) derives an internal supply voltage of 0.5 V. It reaches 10 kHz with 0.4 pJ/conv. CMOS inverters are used in weak inversion to reach such low power consumption of 7.4 W [23] (Fig. 1.15). For higher frequencies, SC filters cannot be used any more as they suffer from insufficient settling times and charge distribution effects. Continuous-time filters must then be used.

6 Continuous-Time † ADCs In such converters, the sampling is no more done at the input but in the quantizer (see Fig. 1.16). As a result no anti-aliasing filter is required. Moreover the speed of the amplifiers can be lower, saving a factor of 2 : : : 3 in power consumption. On the other hand, jitter occurs between the clocks of the quantizer and the DAC. Also differences between the time constants in the filters must be tuned out. Finally any delay around the feedback loop may cause stability problems [24, 25]. Two important discussions seem to continue. The first one has to do with the kind of filter to be used, an opamp based filter or a GmC filter. The other issue is related to feedforward versus feedback.

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Fig. 1.17 Comparison of filters [5]

– b4fs s + fs Vin

– a1fs s +

– a2fs s + DAC1

– a3fs s + DAC2

Digital Output DAC3

a4

1 bit FF fs = 640 MHz

Fig. 1.18 Architecture of 3-rd order single-bit † modulator

The following realizations will illustrate these points. It is clear from a first-order comparison (in Fig. 1.17) that opamp based filters excel in linearity at low frequencies. GmC filters on the other hand can reach higher frequencies but suffer from distortion. Both are used, sometimes even in the same † modulator ! An example of such CT † modulator using linearized GmC blocks is shown in Fig. 1.18 [26]. It only reaches 10 bit up to 10 MHz (0.22 pJ/conv.step). Local feedback is always used to sharpen the filter response. The CT Sigma Delta modulator with the lowest supply voltage, of only 0.5 V, is shown in Fig. 1.19 [27]. Its BW is 25 kHz and its FOM 1.5 pJ/conv.step. To reach such low voltage is only possible if either the bulk is used as an input or the bulks are slightly forward biased to reduce the threshold voltages.

1 Power Minimization in ADC Design

13

Fig. 1.19 Third-order single-bit † modulator on 0.5 V

Fig. 1.20 Third-order four-bit † modulator up to 20 MHz

Amplifiers biased in weak inversion can be sued provided the bandwidth is small as in [28], which reaches 24 kHz with 0.11 pJ/conv. For higher frequencies, CMOS inverters are used as in [29] with 0.4 pJ/conv. The lowest FOM hitherto has been reached in [30] with 0.12 pJ/conv. It is shown in Fig. 1.20. Three-stage class-AB amplifiers are used! Similar frequencies are obtained in [31, 32], the latter one of which uses an opmap in the input stage, followed by two GmC blocks. Also the DACs use SC techniques to save power. Its FOM is 0.23 pJ/conv.step. The last example reaches 125 MHz and is realized in 45 nm CMOS [33]. Now two operational amplifiers are used followed by a single GmC block as shown in Fig. 1.21. Its FOM is only 0.65 pJ/conv.step.

14

W. Sansen

Fig. 1.21 A 125 MHz CT † modulator in 45 nm CMOS

7 TDC Based ADCs Nanometer CMOS technologies require lower supply voltages, although 0.9 V seems to become the new standard. As a result, maybe it is better to convert the input signal directly into a frequency, rather than to convert the input signal amplitude into a quantized equivalent, which suffers from offset and noise. Such ADCs uses a Pulse-width modulator (PWM) or an oscillator (VCO or ring oscillator). Its most important problem is the linearity of the conversion of the voltage into a frequency [34–36]. An early version of such VCO based ADC is shown in Fig. 1.22 [34]. The supply voltage of the ring oscillator is driven by the input signal, after buffering. Logic is required to output the output bits. As a result of the architecture, first-order noise shaping is realized, leading to excellent results. A bandwidth of 100 kHz was reached with 10 bit resolution, giving rise to a FOM of 3 pJ/conv.step. The same authors realized a version [34, ICECS 2009], with 50 MHz and 9.5 bit in 65 nm CMOS, yielding 20 fF/conv.step, which is impressive indeed. A similar VCO-based ADC was realized for low frequencies (20 kHz) operating at 0.2 V supply voltage [36], which gave 82 fF/conv.step. As linearity of such VCO’s is a problem, a linearization technique is used in Fig. 1.23 [37]. Two oscillators are connected in a differential configuration. The FOM is 25 fJ/conv.step for a 40 nm CMOS technology! The maximum frequency is 10 MHz.

1 Power Minimization in ADC Design

15

Fig. 1.22 VCO based ADC [34]

Fig. 1.23 Linearized VCO based ADC [37]

A higher frequency of 30 MHz is obtained in [38] with a FOM of 143 fJ/conv. A bandwidth of 20 MHz is obtained in [39] with 0.33 pJ/conv. Its configuration is shown in Fig. 1.24. A TEQ (Time Encoding Quantizer) replaces the flash quantizer in Fig. 1.25 [40]. A clock of 2.56 GHz is used for high resolution. Another example of a VCO-based CT † modulator is shown in Fig. 1.25 [41]. Current starved pseudo-differential CMOS inverters are used in the current controlled ring oscillators (ICRO). Non-linear correction improves the linearity. It reaches 18 MHz and its FOM is 0.25 pJ/conv.step. The final one [42] reaches 20 MHz and its FOM is 0.32 pJ/conv.step, in 65 nm CMOS (Fig. 1.26).

16

W. Sansen (N-1)th Order Loop Filter a1

an-2

in(t) –

+

K1(s)

K2(s)

Kn-1(s)

1 s

1 s

1 s

VCO Quantizer Kn(s) –

+

Quantizer

1 s

τD

CLK NRZ DAC

NRZ DAC

Loop Delay

RZ DAC

out[n]

First Order Difference

REG

1–z–1

REG CLKB

CLK

CLK

Fig. 1.24 CT † with VCO quantizer [39]

Fig. 1.25 CT † with TEQ [40]

8 Conclusions An overview is given of the state-of-the art of ADCs. Most attention is paid to oversampling converters with SC or continuous-time filters. Finally TDC based ADCs are discussed as they show great promise for nanometer CMOS technologies. They can all be mapped on the P/fs (in pJoule) versus SNDR (in dB) curve [6], showing which ADC to use for which performance.

1 Power Minimization in ADC Design

n(t)

15-element ICRO

30

15-element ICRO

30

17

30 Ring Sampler

Phase Decoder

5

30 Ring Sampler

Phase Decoder

5

5

Nonlinearity Correction

5

Non14 linearity + – Correction 15

–1

1–z

VII –1

1–z

4-level DAC

14

16

Dither LFSR fs / 8

+ 4-level DAC 15-element ICRO

30

15-element ICRO

30

VII

30 Ring Sampler

Phase Decoder

5

30 Ring Sampler

Phase Decoder

5

–1

5

1–z

–1

1–z

5

Nonlinearity Correction Nonlinearity Correction

14

+ –

14

fz Calibration Unit

Fig. 1.26 Variable-rate CT † with ICRO’s [41]

References 1. R. Van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters (Kluwer Academic Press, Boston, 1994) 2. B. Razavi, Principles of Data Conversion System Design (IEEE Press, New York, 1995) 3. F. Maloberti, Data Converters (Springer, Dordrecht, 2007) 4. D. Johns, K. Martin, Analog Integrated Circuit Design (Wiley, New York, 1997) 5. W. Sansen, Analog Design Essentials (Springer, Dordrecht, 2006) 6. B. Murmann, http://www.stanford.edu/murmann/adcsurvey.html 7. B. Verbruggen,JSSC 44(3), 874–882 (2009) 8. P. Veldhorst,ESSCIRC, Athens, 2009, pp. 464–467 9. D.C. Daly, JSSC 44(11), 3030–3038 (2009) 10. J.W. Nam, ESSCIRC, Athens, 2009, pp. 468–471 11. J. Kim, B. Murmann, ESSCIRC, Sevilla, 2010, pp. 378–380 12. M. Scott, JSSC 38(7), 1123–1129 (2003) 13. G. Van der Plas, JSSC 43(12), 2631–2640 (2008) 14. M. Van Elzakker, ISSCC, San Francisco, 2008, pp. 244–245 15. P. Harpe, ESSCIRC, Sevilla, 2010, pp. 214–217 16. R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters (Wiley, Chichester, 2004) 17. V. Peluso, JSSC 32, 1887–1896 (1998) 18. J. Silva, Electron Lett 37(12), 737–738 (2001) 19. L.B. Yao et al., Low-Power Low-Voltage † Modulators in Nanometer CMOS (Springer, Dordrecht, 2006) 20. M. Chae, ISSCC, San Francisco, 2008, p. 27.2 21. Y. Geerts et al., JSSC 35(12), 1829–1840 (2000) 22. T. Christen, ESSCIRC, Sevilla, 2010, pp. 414–417 23. F. Michel, ISSCC, San Francisco, 2011, pp. 476–477 24. J.A. Cherry, W.M. Snelgrove, CT SD Modulators for High-Speed ADCs (Kluwer Academic Press, Norwell, 2000) 25. S. Paton, JSSC 39(7), 1056–1063 (2004) 26. R. Schoofs, CAS 54(1), 209–217 (2007)

18 27. K.P. Pun, JSSC, 42(3), 496–507 (2007) 28. S. Pavan, JSSC, 45(7), 1365–1379 (2010) 29. R.H.M. van Veldhoven, ISSCC, San Francisco, 2008, pp. 492–493 30. G. Mitteregger, JSSC 41(12), 2641–2649 (2006) 31. L.J. Breems, JSSC 42(12), 2696–2705 (2007) 32. P. Crombez, JSSC 45(6), 1159–1171 (2010) 33. M. Bolatkale, ISSCC, San Francisco, 2011, pp. 470–471 34. T. Watanabe, JSSC 38(1), 120–125 (2003); ICECS, Hammamet, 2009, pp. 271–274 35. D. Hovin, JSSC 32(1), 13–22 (1997) 36. U. Wismar, ESSCIRC, Montreux, 2006, pp. 187–190 37. Op’t Eynde, ISSCC, San Francisco, 2010, pp. 450–451 38. J. Daniels, VLSI Circuits, Honolulu, 2010, pp. 155–156 39. M. Park, M.H. Perrott, JSSC 44(12), 3344–3358 (2009) 40. E. Prefasi, ESSCIRC, Sevilla, 2010, pp. 430–433 41. G. Taylor, I. Galton, JSSC 45(12), 2634–2646 (2010) 42. V. Dhanasekaran, JSSC 46(3), 639–650 (2011)

W. Sansen

Chapter 2

Low-Power Pipelined A/D Conversion Boris Murmann

Abstract This paper reviews recent developments and low-power design techniques for high-speed pipelined A/D converters. The discussion spans a review of the fundamental operation principles, a summary of widely used low-power techniques, and an examination of ideas that have been proposed in recent research publications. As we will show, the best research-level designs reach a power efficiency that lies within an order of magnitude of practically achievable limits in today’s architectures. This corresponds to a 2–3 order of magnitude improvement relative to the first pipelined ADCs designed in the late 1980s and early 1990s.

1 Introduction Pipelined ADCs have been investigated since the late 1980s [1–3] to enable highspeed conversion at moderate-to-high resolutions of approximately 8–14 bits. In the early days of its commercial adoption, the pipelined architecture was used to digitize video signals at approximately 20 MS/s and 10 bits of resolution [4]. At that time, with CMOS feature sizes of several microns, this level of performance was difficult to achieve with competing architectures. Even though more than two decades have passed, the situation hasn’t changed much. Despite the fact that competing architectures (such as successive approximation and oversampling ADCs) have substantially widened their performance space, pipelined converters still enjoy great popularity in high-speed applications. This can be seen from Fig. 2.1, which plots experimental ADC data presented at the IEEE International Solid-State Circuits Conference (ISSCC) and the VLSI Circuit Symposium from 1997 until 2011 [5]. For the range of 50–80 dB signalto-noise-and-distortion ratio (SNDR), the pipelined architecture clearly dominates B. Murmann () Stanford University, 420 Via Palou Mall, Stanford, CA 94305-4070, USA e-mail: [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 2, © Springer ScienceCBusiness Media B.V. 2012

19

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Flash Folding Two-Step Pipeline (Interleaved) Pipeline (1 Channel) SAR ΔΣ Other 100 fsrm s Jitter

1010

BW [Hz]

109

108

107

106 20

30

40

50

60

70

80

90

100

110

120

SNDR [dB]

Fig. 2.1 Experimental data for ADC bandwidth (BW) versus SNDR. Pipelined ADCs dominate the 50–80 dB SNDR range for BW > 10 MHz

the architectural landscape for conversion bandwidths above 10 MHz. Within this range, popular applications include wireless base stations [6], wireless LAN [7, 8], Ethernet transceivers [9], and medical ultrasound imagers [10]. Regardless of the underlying architecture, a general application-driven necessity in the design of modern data converters is the aggressive reduction of power dissipation. According to the analysis described in [11], A/D conversion energy has halved every 2 years over the past decade (on average, across all architectures and performance regimes). While some of these improvements are undoubtedly due to technology scaling, refinements in ADC architectures and circuit design have carried a significant weight in this trajectory. Thus, the purpose of this paper is to review the progression of relevant design techniques for the specific case of highspeed pipelined A/D converters. As a basis for this discussion, Sect. 2 will review pipelined conversion at the conceptual block diagram level. In Sect. 3, common-practice and widely productized techniques applicable to low-power design are reviewed. These include for instance stage scaling, comparator redundancy, and amplifier sharing. In Sect. 4, we will then present ideas that have been evaluated mostly at the level of university research. The topics covered include OpAmp-less stage implementations as well as various digital enhancement techniques. In light of this discussion, Sect. 5 compares the state-of-the art with practical limits on power dissipation and Sect. 6 ends this chapter with a summary.

2 Low-Power Pipelined A/D Conversion

21

2 Review of Pipelined A/D Conversion Figure 2.2 shows a conceptual block diagram of the pipelined A/D converter topology. Several converter stages are cascaded and process the analog input sequentially, similar to flip-flops propagating a bit stream in a digital shift register. Each stage samples and holds its analog input (through S/H circuits implicitly contained in the local A/D block and the summing node) and performs a coarse A/D conversion. The error of this conversion result, often called residue, is computed with the help of a local D/A converter, amplified and fed to the next stage in order to extract additional bits. The last stage contains only a quantizer, since there is no further need to compute a residue. The sub-ADC results are aligned in time (using shift registers) and combined to yield the final digital output word. The principal advantage of this ADC architecture is that due to stage pipelining, its throughput rate is set by the time needed to perform a single sub-A/D and D/A conversion. Similar to workers on a manufacturing line, the stages operate concurrently, i.e. while stage i acquires a new input, stage i C 1 operates on the previous output of stage i. The propagation time through the cascade of pipeline stages merely results in conversion latency, which is tolerable in many applications. In order to understand the operating principle of a pipelined converter in more detail, it is useful to look at a simple two-stage pipeline example as shown in Fig. 2.3. In this diagram, the sub-DAC is ideal and the sub-ADCs are modeled as unity gain elements that introduce an additive quantization error. For an ideal

Align & Combine Bits Dout Vin SHA

Stage 1

Vin1

Stage n-1

Σ

G1 –

ADC

DAC D1

Fig. 2.2 Block diagram of a pipelined ADC

Vres1

Stage n

22

B. Murmann Stage 1

Stage 2

Vin

Σ

G11 G –

Vres1 = –G1εq

Σ εq2

Σ εq1 D2

D1 Dout

Σ

1 / Gd1

Fig. 2.3 Two-stage pipeline ADC example

B-bit quantizer, the quantization error (©q ) is bounded by ˙ ½, where  is the quantizer’s step size. From this model, it is straightforward to show that   ©q2 G1 C Dout D Vin C ©q1 1  Gd1 Gd1

(2.1)

and thus, for Gd1 D G1 Dout D Vin C

©q2 Gd1

(2.2)

From this result, we see that the “digital gain” term that combines the two subconversion results should ideally be set to the reciprocal of the gain used in the analog signal path.1 Under this condition, and assuming that the sub-DAC is ideal and none of the quantizers are driven into overload, it follows that the quantization error of the overall pipeline in this example is equal to the quantization error of the last stage, divided by gain of stage 1. It is straightforward to show that this result extends to an n-stage pipeline, in which case the last stage’s quantization error is divided by the aggregate gain in the analog path. We can therefore summarize the following key results: • In an ideal n-stage pipeline ADC (ideal DACs, quantizers are not overloading and ideal matching of analog and digital gain terms), the quantization error of stages 1 through n  1 does not appear in the output. • The aggregate bit-resolution of a pipeline is given by the resolution of the last quantizer plus the dual logarithm of the aggregate amplifier gain. I.e., for each factor of two in gain, the last stage’s quantization error is cut in half, corresponding one bit improvement in resolution.

1

The reader may notice a similarity to cascade delta-sigma converters: perfect cancellation of the first stage quantization noise requires perfect coefficient matching between the analog and digital domains; any mismatch will “leak” a portion of the coarse quantization error into the output.

2 Low-Power Pipelined A/D Conversion

23

3 Basic Low-Power Design Techniques Given the structural features of a pipelined converter and its underlying circuits, there exist a number of basic opportunities for translating relaxed precision requirements into power savings. We will review the most widely used concepts in this section using a prototypical circuit realization described next. Figure 2.4 shows a conceptual single-ended representation of a conventional pipeline stage. This circuit consists of a flash-type sub-ADC, a capacitive charge redistribution network, and an operational transconductance amplifier (OTA). The switched capacitor network, in combination with the OTA is often called MDAC (multiplying D/A converter). Like most switched capacitor circuits, the stage operates in two main clock phases. During the sampling phase (¥1 ), the stage input signal is acquired. In the redistribution phase (¥2 ), a residual charge packet, controlled by the local conversion result D, is redistributed onto the feedback capacitor CF to produce the amplified stage residue, Vres . In this scheme, the precise matching of capacitors in modern technologies and electronic feedback are leveraged to achieve an accurate realization of the required sub-DAC, subtraction and gain functions.

3.1 Comparator Redundancy The most widely used technique employed to save power in the stage’s flash subADC is comparator redundancy. As we have seen from the analysis of Sect. 2, the errors from the flash ADCs of stage 1 through n  1 do not appear in the converter’s output. Consequently, we should be able to get by with rather imprecise sub-ADCs that utilize near-minimum size transistors and run at very low levels of power. This turns out to be true in practice, provided that proper care is taken to prevent quantizer over-ranging. φ1

CF

. ..

. ..

Vin

Cs[1:m]

... Flash ADC

Switches

D

±Vref

Fig. 2.4 Generic pipeline stage implementation

Vres OTA φ1′

φ2

φ2

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B. Murmann

Fig. 2.5 Overranging due to sub-ADC decision level error

Overranging due to misplaced decision level

Full-scale range

Vres1 4

Vin

As we see from the example in Fig. 2.3, the residue of the first stage is simply a gained-up version of the local quantization error. For the pipeline to work properly, we must ensure that the output does not saturate the following quantizer, i.e. the output must not exceed the next quantizer’s full-scale range (VFS ). Assuming that the local sub-ADC is free of errors in its decision levels, this condition is ensured as long as G1  2B since the quantization error of a B-bit ADC is bounded by VFS /2B and thus G1 VFS /2B  VFS () G1  2B . The limit case of G1 D 2B with B D 2 is illustrated in Fig. 2.5. From this example, it is clear that any error in the sub-ADC decision levels will lead to over-ranging. Thus, it is impractical to design a stage for this limit case; it would require very high precision (and thus high power) in the sub-ADC comparators. There are three ways to ensure that over-ranging is avoided despite large errors in the sub-ADC’s decision levels. The first (and probably most obvious) is to design for a reduced gain less than 2B . This idea, sometimes called “radix <2,” is utilized e.g. in [12], which uses B D 1 and G D 1.93. In order to tolerate relatively large errors and to maintain a radix of 2 (which simplifies the digital logic that combines the bits), another option is to chose G D 2B1 , which was done e.g. in the design of [13]. A particularly elegant and popular variant for a stage that has G D 2 is to employ a sub-ADC with only two decision levels (instead of three), i.e. B D log2 (2 C 1) D 1.589 bits. Such a stage is typically called “1.5-bit” in literature [4]. A third option is to allow the stage to extend the full-scale range of the quantizer that takes the over-ranging residue voltage [14]. With proper redundancy in place, large comparator offsets can be tolerated, often allowing the designer to employ basic dynamic latch comparators without preamplification (unless charge kick-back is a concern). Typically, the power required for such comparators in modern technologies is on the order of 100 W/GHz (100 fJ per comparison) or less [15, 16]. Thus, the overall comparator power in a pipelined ADC tends to be small compared to the power dissipated in the MDAC circuit.

2 Low-Power Pipelined A/D Conversion

Vin

Stage 1

Stage 2

C1 / 2

C1 Vin

25

Stage 3

C2 / 2

C2 Gm

C3 / 2

C3 Gm

Gm

Fig. 2.6 Pipelined ADC model for noise considerations

3.2 Stage Scaling, Per-Stage Resolution and Noise Budgeting Unlike comparator nonidealities, errors in the MDAC circuitry refer directly to the input of the pipeline and there is no inherent architectural suppression mechanism. The most critical implication of this is that the electronic noise of the MDAC circuits must be minimized commensurate with the target resolution of the ADC. Since many stages contribute to the overall input referred noise, a key question is how the input referred noise budget should be distributed across the pipeline to minimize power dissipation. This question was investigated in detail by Cline [17] and later refined by Chiu [18]. In order to understand the first order result, consider the simplified ADC model in Fig. 2.6, using a stage gain of two as an example. Without worrying about the absolute value of the total input referred noise (which would require a more detailed analysis), we begin by expressing the rough proportionalities of the input referred noise, given by 

Ntot

 1 1 1 1 1 1 / kT C C C C1 C2 22 C3 22 22

(2.3)

In words, the noise power of the second stage is divided by 4 when referred to the input, and the third stage noise is divided by 16. If we choose all capacitors the same size, then the first stage will clearly dominate the noise. This is wasteful, since the second and third stage amplifiers are driving large capacitors that are essentially irrelevant to the circuit’s noise performance. Consider now the option of scaling the capacitors such that C2 D C1 /4 and C3 D C1 /16. In this case, each stage will contribute equally to the overall input referred noise. Unfortunately, this choice is also wasteful, since the first stage has a very small noise budget, requiring a very large input sampling capacitance. Further analysis shows that the optimum capacitance scale factor lies approximately midway between the two extremes considered above, i.e. the capacitance should be scaled by the aggregate gain (not gain squared) that precedes each stage. For instance, in the above example, C2 D C1 /2 and C3 D C1 /4 are near optimum

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Fig. 2.7 Pipelined ADC power as a function of stage scaling (from [18]) and for various per-stage resolutions

choices for a practical design. The exact optimum can deviate from these values depending on the speed of the converter and the per-stage resolution. Fortunately, however, the optimum is well-behaved and shallow, as can be seen from Fig. 2.7. For this illustration, the taper factor x is defined such that the capacitor scaling factor is equal to Gx , where G is the stage gain. Thus, x D 1 corresponds to a capacitor scaling by exactly the stage gain. Clearly, deviating by some fraction from x D 1 does not result in a significant change in power dissipation, as long as one does not approach x D 0 or x D 2, which correspond to the extreme (and undesired) scaling scenarios discussed above. In addition to properly distributing the electronic noise budget across stages, the designer must decide upon a split of the overall input noise budget into electronic noise and quantization noise. For an ideal ADC with quantization step , the input referred quantization noise is 2 /12. In general, it is wasteful to make the input referred electronic noise much smaller than the quantization noise; this is because in this case extra amplifier power is invested in diminishing gains in signal-to-noise ratio. For this reason, many designs make the input referred thermal noise at least comparable to the quantization noise. For embedded converters, one can argue that designing toward the other extreme of dominant electronic noise can be beneficial [19]. In an embedded converter, the cost of generating additional bits to reduce quantization noise (and thus allow for a larger electronic noise budget) is relatively low, since there is no I/O power associated with these bits. A quantitative evaluation of the proper sampling capacitor size versus number of bits and overall SNR is plotted in Fig. 9 of reference [20]. A final and equally important architectural parameter that must be considered in the power optimization of a pipelined converter is the per-stage resolution. Qualitatively speaking, the main result here is that the low-to-moderate speed pipelines can benefit from larger state resolutions of up to 4–5 bits (especially

2 Low-Power Pipelined A/D Conversion

27

in the first stage). This is because large per-stage resolutions minimize the OTA count at the expense of extra loading from the flash sub-ADCs. At moderate speeds, this extra loading is not detrimental and can be easily handled. For example, the designs of [21, 22] use only 3 and 5 stages to implement 10- and 14-bit converters, respectively. Recently, very low-power two-stage multi-bit designs were presented in [23, 24]. These ADCs use successive approximation to realize efficient subADCs, and rely on a single residue amplifier. Unfortunately multi-bit designs lose their advantage when the goal is to extract the maximum possible speed from a pipelined converter in a given technology. At the highest possible speeds, the designer will typically opt for a single-bit of effective stage resolution; see e.g. the 500-MS/s design of [25].

3.3 Mitigation of Capacitor Mismatch Since any errors in the first stage’s MDAC refer directly to the input of the converter, the matching precision of the employed capacitors must be commensurate with the overall target resolution of the design. In some cases, this leads to an outcome where the capacitor size is set by matching constraints rather than electronic noise requirements (see e.g. [7]). Thus, one can argue that any technique that addresses capacitor mismatch can translate into power savings. One popular architectural option is to increase the resolution of the pipeline’s first stage. One can show that for each extra bit resolved in the first stage, the converter DNL improves by 1 bit, while the INL improves by 0.5 bits. This was leveraged in the design of [26], which uses a 4-bit (3-bit effective) first stage to achieve no missing codes at 14-bits of resolution without any form of calibration and capacitor sizes set by electronic noise. Due to the limited benefit of increased stage resolution on INL, however, the integral nonlinearity in this design is still several LSBs at the 14-bit level.2 If better INL is desired, a variety of correction techniques are available in the analog or digital domain. In analog domain, it is for instance possible to employ passive error averaging to effectively cancel capacitor mismatch [18]. In the digital domain, there exist a wide range of schemes that are essentially based on adjusting the “digital gain terms” in the logic that combines the stage outputs (e.g. Gd1 in Fig. 2.2). The coefficients are typically measured iteratively, using the existing hardware within the pipeline. For instance, mismatch in stage i can be measured using the backend converter comprising of stages i C 1 : : : n. Self calibration techniques of this kind are described for instance in [12, 27–29]. As far as capacitor mismatch is concerned, it is important to note that the resulting errors do not drift. Consequently, it is sufficient to measure them once, e.g. during production test (or power up), and store the coefficients in fuses (or SRAM).

2

This is tolerable, e.g. in imaging applications.

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3.4 Amplifier Sharing and SHA-Less Frontends Beyond proper budgeting and distribution of electronic noise, trying to reduce the number of OTAs used in the pipeline is the designer’s next best architectural option for additional power savings. In this spirit, the concept of amplifier sharing has been evaluated. The main idea is to leverage the fact that the OTA in Fig. 2.4 is only used during charge redistribution; it is idle (reset) in the phase where the stage acquires its input. During that time, the OTA can potentially be used in the following stage, which performs charge redistribution in this time slot. This idea is used for example in the designs of [21, 30–32]. The key issues that limit the efficacy of inter-stage OTA sharing are: (1) the performance requirements (gain, bandwidth, load capacitance, etc.) are not equal in the two stages that share the same OTA; this leads to overdesign, (2) sharing the OTA requires additional switches that add load capacitance at critical nodes and thus lead to increase the power dissipation of the shared amplifier. The first of these issues can be overcome if the sharing occurs between two identical pipelines that run in parallel, as for instance in the I/Q channels of a radio receiver. An implementation that describes such an approach is found in [33]. In addition to the switch parasitics, a remaining problem in this approach is the channel-to-channel cross-talk that is introduced from switching a non-reset OTA between the two ideally independent signal paths. A more popular option for reducing the number of high-power OTAs in the pipeline is to eliminate the dedicated sample-and-hold amplifier (“SHA” in Fig. 2.1) from the pipeline. This option is attractive since this stage tends to dissipate up to one third of the total power in a high-performance design. One of the first highperformance designs that uses a SHA-less front-end was described by Mehr in 2001 [13]. Today, SHA-less operation is widely used across a wide range of performance specs, even in designs that sample at IF frequencies [34]. The primary issue that must be overcome in a SHA-less design is the clock timing and bandwidth mismatch between signals acquired by the sub-DAC and the main MDAC path. For relatively low-speed designs with a high degree of comparator redundancy in the first stage (e.g. 1.5-bit architecture), the designer can typically rely on the component matching of modern technologies (see e.g. [35]). For designs with wideband inputs, it is conceivable to measure and calibrate the mismatch [36]. Alternatively, it is possible to merge the sampling operation for the two paths into a single circuit [37].

3.5 Flip-Around Charge Redistribution Beyond reducing the number of amplifiers in the pipeline, the next step is to improve the efficiency of the circuit at the transistor level. A widely used idea is to employ “flip-around” charge redistribution [38]. A complete 1.5-bit pipeline stage that uses this technique is shown in Fig. 2.8. The input is sampled on Cs and Cf (nominally

2 Low-Power Pipelined A/D Conversion

29

Fig. 2.8 1.5-bit pipeline stage implementation using flip-around charge redistribution [39]

same size), and Cf is flipped around the amplifier as a feedback capacitor during redistribution. This scheme achieves a closed loop gain of 2 with a feedback factor of 1/2 (neglecting OTA input capacitance). If the generic circuit of Fig. 2.4 is used instead, the feedback factor would be only Cf /(Cf C 2Cs ) D 1/3. Since both the speed and noise performance of the circuit benefit from larger feedback factors, substantial power savings are enabled by flip-around charge redistribution.

3.6 Time Interleaving Time-interleaved architectures [40] exploit time parallelism and trade hardware complexity for an increased aggregate sampling rate. Once a single-channel pipeline has been optimized using the above-discussed techniques, time-interleaving can be employed to increase the achievable sampling rate in a given technology. In addition, interleaving has benefits for power efficiency, since the individual channels can be designed for lower speeds and thus achieve improved power efficiency. Time interleaved pipelined ADCs are currently popular in the 10GBASE-T Ethernet application, which demands sampling rates on the order of 1 GHz and 11 bits of resolution. While it may be possible to achieve this sampling rate by interleaving two channels, it is typically more efficient to work with four or more channels [9, 41]. A numerical justification of this argument is found in [20].

4 Exploratory Low-Power Design Techniques The techniques described in the previous section are widely used and have been in mass production for many years. In this section, we will consider exploratory ideas that have not yet found widespread industry adoption, and are mostly used in

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B. Murmann

experimental converters. Since approximately 50–70% of all power in a pipelined ADC is dissipated in the residue amplifiers, research has focused mainly on this particular building block within the converter.

4.1 Residue Amplification with Low Loop Gain A first and most basic opportunity for power reduction lies in simplifying the OTA circuit shown in Fig. 2.4. Instead of using multiple gain stages to achieve high loop gain (to ensure precise amplification), it has been proposed to work with simplified single-stage amplifiers [42, 43], and to use calibration to overcome the resulting errors. Since the open-loop gain of an OTA varies with temperature, the calibration must run continuously and track changes in the converter’s operating conditions. Unfortunately, this creates overhead in and complexity that takes away from the benefits of the (sometimes minor) OTA simplification. In the realization of [6], a 10mW auxiliary ADC is used to monitor the gain of the first residue amplifier, helping to cut its power in half. This overhead is justifiable in this high-performance ADC that dissipates a total power of 850 mW. In general, when applying this particular or a similar technique, the benefits must be carefully evaluated against the cost of the added calibration. An alternative to handling the low amplifier gain through calibration is to apply some form of double sampling to boost the effective gain of the amplifier. The correlated level shifting technique (CLS) proposed recently [44] shows promise in this direction, as it also increases the available swing, which is highly desired in low-voltage technologies. In the context of designs that use simplified amplifiers, it should also be mentioned that there exist options in the optimization of the process technology. For instance, the design of [45] uses customized “high performance analog transistors” with increased intrinsic gain to achieve sufficient gain for 10-bit precision with a single-stage OTA.

4.2 Class-AB and Comparator-Based Residue Amplification Even in simplified, single-stage OTA realizations, the charge transfer from the power supply to the capacitive load is inherently inefficient, since the amplifier draws a constant current, while it delivers on average only a small fraction of this current to the load. In [46], it was found that the efficiency of a class-A OTA in a switched capacitor circuit is inversely proportional to the number of settling time constants. For the typical case of settling for approximately ten or more time constants, the overall efficiency, i.e. charge drawn from the supply versus charge delivered to the load, is only a few percent. One step toward improving the amplifier efficiency is to employ class-AB amplification [35, 47]. So far, class-AB amplification hasn’t been very popular for

2 Low-Power Pipelined A/D Conversion

31

Fig. 2.9 Comparator-based switched capacitor circuit + –

Vout CL

several reasons. First, a typical class-AB OTA still requires a class-A input stage, which upper bounds the possible savings, especially considering the relatively small load capacitances seen in pipelined ADCs. Furthermore, class-AB operation tends to reduce the achievable bandwidth when compared to a class-A design in the same technology. In [35], a single-stage inverter-based class-AB design was used to achieve good power efficiency at a sampling rate of 30 MS/s. A recent concept that has gained momentum is to replace the OpAmp by a comparator [48, 49], yielding a so-called comparator-based switched capacitor circuit (see Fig. 2.9). In this scheme, the comparator shuts off the capacitor charging current when the final signal value is reached. Thus, no charge is wasted and the efficiency of this topology can approach that of a class-B amplifier.

4.3 OpAmp-Less Residue Amplification A more aggressive approach to reduce the power spent on residue amplification is to eliminate the OTA (or comparator) in the stage entirely, and work with a more simplistic configuration that does not rely on OpAmp-like circuitry. Figure 2.10 shows examples of such circuits. The open-loop circuit of Fig. 2.10a [50] is similar to that of Fig. 2.4, except for the charge redistribution phase. The charge packet on the capacitive array is not re-distributed onto a feedback capacitor, but remains in place to produce a small voltage at node Vx . This residue is amplified by a resistively loaded transconductance stage to produce the desired full-swing residue voltage Vres . Since the high gain requirement in the transconductor is now dropped, a basic differential pair-type stage can be used to replace the complex amplifier in Fig. 2.4. Other variants of this open-loop residue amplification approach have been published; see e.g. [51, 52], and the current mode topology of [53]. The circuit in Fig. 2.10b [54] samples the input on two capacitors connected in parallel. Next, it stacks the capacitors in series to achieve a voltage gain of two. The 1 buffer can be a low-power source follower circuit. In scheme (c) a “bucket brigade” pass transistor is used to move a sampled charge packet (q) from a large sampling capacitor (CS ) to a smaller load capacitor (CL ), thereby achieving voltage gain without drawing a significant amount of energy from the supply [55]. The circuit in Fig. 2.10d uses the gate capacitance of a transistor to acquire a charge

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a

...

...

Vin

b

Cs[1:m] Vx

...

Switches

ADC

±Vref

D

c

Vres

Gm

d

+ – Vout

V

q

VDD

Vin

(large)

(small)

CL

q1

q2

q VBIAS

C

q1 + q2

– V + t q=0

Vout CL

(floating)

e

Fig. 2.10 Examples of OpAmp-less residue amplification schemes

sample (q1 , q2 ). The transistor is then switched into a source-follower configuration, moving all signal charge (q1 C q2 ) to the small capacitance from gate to drain, which also results in voltage amplification [56]. Much like the comparator based circuit of Fig. 2.9, all of the charge drawn from the supply is used to drive the load, thereby enabling high power efficiency. In this same spirit, the dynamic amplifier used in [57] [Fig. 2.10e] turns off once the amplification is complete and thereby achieves very low power dissipation. In this circuit, all nodes are first reset and the load capacitors are charged with a rate that depends on the input (inC, in). The current is shut off via transistors P1 once the stage’s comparator has made a decision. A general concern with most minimalistic design approaches is that they tend to sacrifice robustness, e.g., in terms of power supply rejection, common mode rejection and temperature stability. It remains to be seen if these issues can be handled efficiently in practice. Improving supply rejection, for instance, could be achieved using voltage regulators. This is custom practice in other areas of mixedsignal design, as for example clock generation circuits [58]. Especially when the power of the ADC’s critical core circuitry is lowered significantly, implementing supply regulation should be justifiable.

2 Low-Power Pipelined A/D Conversion

33

Analog Nonlinearity

Vin

Σ

Backend A/D

g –

A/D

Σ

D/A Coefficient Estimation

MOD Dout

Σ

g–1

Digital Inverse

Fig. 2.11 Digital residue amplifier linearization

A second issue with minimalistic designs is the achievable resolution and linearity. OpAmp circuits with large loop gain help linearize transfer functions; this feature is often removed when migrating to simplified circuits. For instance, the amplifier scheme of Fig. 2.10d is linear only to approximately 9-bit resolution. In cases where simplicity sacrifices linearity, it is attractive to consider digital linearization techniques (see Fig. 2.11). In [50], it was demonstrated that a basic open-loop differential pair can be digitally linearized (to 12-bit precision) using only a few 1,000 logic gates. Subsequently, this idea has been refined e.g. in the works of [59–62]. One key issue in most digital linearization schemes is that the correction parameters must track changes in operating conditions relatively quickly; preferably with time constants no larger than 1–10 ms. Unfortunately, most of the basic statistics-based algorithms for coefficient adaptation require much longer time constants at high target resolutions [60, 63]. Additional research is needed to extend the recently proposed “split-ADC” [64, 65] and feedforward noise cancellation techniques [66] for use in nonlinear calibration schemes.

4.4 Dynamic Error Correction Most of the digital correction methods developed in recent years have targeted the compensation of static circuit errors. However, it is conceivable that in the future the correction of dynamic errors will become attractive as well. One opportunity

34

B. Murmann 10–6

[4]

10–8 P / fs [Joules]

[34]

10–10

[24] [49] [56]

100 fJ / conv.-step [57]

10–12

10–14 20

10 fJ / conv.-step

[23]

30

40

50 60 SNDR [dB]

70

80

90

Fig. 2.12 Solid-line: predicted power limits for pipelined ADCs using class-A residue amplification (eq. (27) of [65] for 90 nm technology). The dashed lines represent the figure of merit P/(fs 2ENOB ), for 10 and 100 fJ/conv-step

is the digital correction of errors due to finite slew rate, incomplete settling or incomplete reset of amplifiers [59, 67–69]. With such corrections in place, the speed of the amplifier can be reduced and potentially translated into significant power savings.

5 Limits on Pipelined ADC Power Dissipation Even with the most innovative power saving techniques applied, there exists a practical minimum level of power that must be invested. Such a bound was developed specifically for pipelined ADCs [70] and assuming noise-limited classA residue amplification. The corresponding equation is plotted in Fig. 2.12 along with experimental pipeline ADC data points [5]. As we can see from this plot, the dynamic pipeline by Verbruggen [57] and the comparator based design by Chu and Lee [49] define the state-of the art in power efficiency and lie closest to the predicted limit line. Relative to Lewis’ pipeline from 1992, data point [49] achieves about 2.5 orders of magnitude improvement in power efficiency.

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35

6 Summary The power efficiency of pipelined A/D converters has seen tremendous improvements over the past two decades. While a good portion of the progress can be attributed to process scaling, the design techniques reviewed in this paper have played an equally import role; especially as far as adjusting the architecture for optimization in fine line technology is concerned. Relative to Lewis’ pipeline from 1992, today’s research prototypes boast 2–3 orders of magnitude improvement in power efficiency. However, whether the most aggressive innovation will find their way into products is yet to be determined. Many of the ultra-low power architectures proposed recently tend to sacrifice robustness, either in terms of supply rejection or tolerance to process, voltage and temperature variations. Some of these issues can be addressed using calibration techniques, supply regulation and innovative transistorlevel design. With the continuing application-driven need for high-speed and power efficient pipeline ADCs, it is to be expected that many interesting and transformative answers to these challenges will emerge over the next decade.

References 1. S. Masuda et al., A CMOS pipeline algorithmic A/D converter, in Proceedings of the IEEE Custom Integrated Circuits Conference, Rochester, Sept 1984, pp. 559–562 2. S.H. Lewis, P.R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter. IEEE J. Solid-State Circuits 22(6), 954–961 (1987) 3. S. Sutarja, P.R. Gray, A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter. IEEE J. Solid-State Circuits 23(6), 1316–1323 (1988) 4. S.H. Lewis et al., A 10-b 20-Msample/s analog-to-digital converter. IEEE J. Solid-State Circuits 27(3), 351–358 (1992) 5. B. Murmann, ADC performance survey 1997–2011, [Online]. Available: http://www.stanford. edu/murmann/adcsurvey.html 6. A.M.A. Ali et al., A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration. IEEE J. Solid-State Circuits 45(12), 2602–2612 (2010) 7. J. Arias et al., Low-power pipeline ADC for wireless LANs. IEEE J. Solid-State Circuits 39(8), 1338–1340 (2004) 8. S. Mehta et al., An 802.11 g WLAN SoC, in ISSCC Digest Technical Papers, San Francisco, Feb, 2005, pp. 94–95 9. C.-C. Hsu et al., An 11b 800 MS/s time-interleaved ADC with digital background calibration, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2007, pp. 464–615 10. Texas Instruments, AFE5805 Datasheet. [Online]. Available: http://focus.ti.com/lit/ds/symlink/ afe5805.pdf 11. B. Murmann, A/D converter trends: Power dissipation, scaling and digitally assisted architectures, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, Sept 2008, pp. 105–112 12. A.N. Karanicolas et al., A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. IEEE J. Solid-State Circuits 28(12), 1207–1215 (1993) 13. I. Mehr, L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC. IEEE J. SolidState Circuits 35(3), 318–325 (2000)

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14. I.E. Opris et al., A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter. IEEE J. Solid-State Circuits 33(12), 1898–1903 (1998) 15. D. Schinkel et al., A double-tail latch-type voltage sense amplifier with 18 ps setup C hold time,” in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2007, pp. 314–605 16. T. Sundstrom, A. Alvandpour, A kick-back reduced comparator for a 4-6-Bit 3-GS/s flash ADC in a 90 nm CMOS process, in Proceedings of the MIXDES, Ciechocinek, Poland, 2007, pp. 195–198 17. D.W. Cline, P.R. Gray, A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 m CMOS. IEEE J. Solid-State Circuits 31(3), 294–303 (1996) 18. Y. Chiu et al., A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE J. SolidState Circuits 39(12), 2139–2151 (2004) 19. K. Bult, Embedded analog-to-digital converters, in Proceedings of the ESSCIRC, Athens, 2009, pp. 52–64 20. S. Kawahito, Low-power design of pipeline A/D converters, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2006, pp. 505–512 21. Y.-C. Huang, T,-C. Lee, A 10b 100MS/s 4.5 mW pipelined ADC with a time sharing technique, in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2010, pp. 300–301 22. P. Bogner et al., A 14b 100 MS/s digitally self-calibrated pipelined ADC in 0.13um CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Dec 2006, pp. 832–841 23. M. Furuta et al., A 0.06 mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65 nm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2010, pp. 382–383 24. C.C. Lee, M.P. Flynn, A 12b 50MS/s 3.5 mW SAR assisted 2-stage pipeline ADC, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2010, pp. 239–240 25. A. Verma, B. Razavi, A 10-bit 500-MS/s 55-mW CMOS ADC. IEEE J. Solid-State Circuits 44(11), 3039–3050 (2009) 26. W. Yang et al., A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J. Solid-State Circuits 36(12), 1931–1936 (2001) 27. E.G. Soenen, R.L. Geiger, An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs. IEEE Trans. Circuits Syst. II 42(3), 143–153 (1995) 28. L. Singer et al., A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2000, pp. 38–39 29. S.-Y. Chuang, T.L. Sculley, A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE J. Solid-State Circuits 37(6), 674–683 (2002) 30. Min Byung-Moo et al., A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE J. SolidState Circuits 38(12), 2031–2039 (2003) 31. K. Gulati, Lee Hae-Seung, A low-power reconfigurable analog-to-digital converter. IEEE J. Solid-State Circuits 36(12), 1900–1911 (2001) 32. P.C. Yu, Hae-Seung Lee, A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 1996, pp. 314–315 33. D. Kurose et al., 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. SolidState Circuits 41(7), 1589–1595 (2006) 34. S. Devarajan et al., A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC. IEEE J. Solid-State Circuits 44(12), 3305–3313 (2009) 35. J.K.-R. Kim, B. Murmann, A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration, in Proceedings of the ESSCIRC, Sevilla, Sept 2010, pp. 378–381 36. P. Huang et al., SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration, in Custom Integrated Circuits Conference (CICC), 2010 IEEE, San Jose, CA, USA, 2010, pp. 1–4 37. Byung-Geun Lee et al., A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC. IEEE J. Solid-State Circuits 43(12), 2613–2619 (2008) 38. Bang-Sup Song et al., A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter. IEEE J. Solid-State Circuits 23(6), 1324–1333 (1988)

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39. A.M. Abo, P.R. Gray, A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, 1998, pp. 166–169 40. W.C. Black, D.A. Hodges, Time interleaved converter arrays. IEEE J. Solid-State Circuits 15(6), 1022–1029 (1980) 41. S.K. Gupta et al., A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture. IEEE J. Solid-State Circuits 41(12), 2650– 2657 (2006) 42. J. Ming, S.H. Lewis, An 8b 80MSample/s pipelined ADC with background calibration, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2000, pp. 42–43 43. X. Wang et al., A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. IEEE J. Solid-State Circuits 39(11), 1799–1808 (2004) 44. B.R. Gregoire, Moon Un-Ku, An over-60 dB true rail-to-rail performance using correlated level shifting and an Opamp with only 30 dB loop gain. IEEE J. Solid-State Circuits 43(12), 2620–2630 (2008) 45. M. Boulemnakher et al., A 1.2 V 4.5 mW 10b 100MS/s pipeline ADC in a 65 nm CMOS, in ISSCC Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 250–611 46. B. Murmann, Limits on ADC Power Dissipation, in Analog Circuit Design, ed. by M. Steyaert et al. (Springer, Dordrecht, 2006), pp. 351–368 47. H.-C. Choi et al., A 12b 50MS/s 10.2 mA 0.18 m CMOS Nyquist ADC with a fully differential class-AB switched OP-AMP, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2008, pp. 220–221 48. J.K. Fiorenza et al., Comparator-based switched-capacitor circuits for scaled CMOS technologies. IEEE J. Solid-State Circuits 41(12), 2658–2668 (2006) 49. J. Chu et al., A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2010, pp. 237–238 50. B. Murmann, B.E. Boser, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J. Solid-State Circuits 38(12), 2040–2050 (2003) 51. Ding-Lan Shen and Tai-Cheng Lee, A 6-Bit 800-MS/s pipelined A/D converter with open-loop amplifiers, in Symposium on VLSI Circuits Digest, June 2006, pp. 134–135 52. A. Nazemi et al., A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS, in Symposium on VLSI Circuits Digest, 2008, pp. 18–19 53. K. Poulton et al., A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 m CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2003, pp. 318–496. 54. I. Ahmed et al., A low-power capacitive charge pump based pipelined ADC. IEEE J. SolidState Circuits 45(5), 1016–1027 (2010) 55. M. Anthony et al., A process-scalable low-power charge-domain 13-bit pipeline ADC, in Symposium on VLSI Circuits Dig., Honolulu, HI, USA, 2008, pp. 222–223 56. J. Hu et al., A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic source follower residue amplification. IEEE J. Solid-State Circuits 44(4), 1057–1066 (2009) 57. B. Verbruggen et al., A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm digital CMOS. IEEE J. Solid-State Circuits 45(10), 2080–2090 (2010) 58. T. Toifl et al., A 1.25–5 GHz clock generator with high-bandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS. IEEE J. Solid-State Circuits 44(11), 2901–2910 (2009) 59. C.R. Grace et al., A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration. IEEE J. Solid-State Circuits 40(5), 1038–1046 (2005) 60. A. Panigada, I. Galton, A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction. IEEE J. Solid-State Circuits 44(12), 3314–3328 (2009) 61. B.D. Sahoo, B. Razavi, A 12-bit 200-MHz CMOS ADC. IEEE J. Solid-State Circuits 44(9), 2366–2380 (2009) 62. M. Daito et al., A 14-bit 20-MS/s pipelined ADC with digital distortion calibration. IEEE J. Solid-State Circuits 41(11), 2417–2423 (2006)

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63. B. Murmann, B.E. Boser, Digital domain measurement and cancellation of residue amplifier nonlinearity in pipelined ADCs. IEEE Trans. Instrum. Meas. 56(6), 2504–2514 (2007) 64. J. Li, U.-K. Moon, Background calibration techniques for multistage pipelined ADCs with digital redundancy. IEEE Trans. Circuits Syst. II 50(9), 531–538 (2003) 65. J. McNeill et al., ‘Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. IEEE J. Solid-State Circuits 40(12), 2437–2445 (2005) 66. K.-W. Hsueh et al., A 1 V 11b 200MS/s Pipelined ADC with digital background calibration in 65 nm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, 2008, pp. 546–634 67. J.P. Keane et al., Digital background calibration for memory effects in pipelined analog-todigital converters. IEEE Trans. Circuits Syst. I 53(3), 511–525 (2006) 68. E. Iroaga, B. Murmann, A 12-Bit 75-MS/s pipelined ADC using incomplete settling. IEEE J. Solid-State Circuits 42(4), 748–756 (2007) 69. S. Kawahito et al., A 15b power-efficient pipeline A/D converter using non-slewing closedloop amplifiers, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2008, pp. 117–120 70. T. Sundstrom et al., Power dissipation bounds for high-speed Nyquist analog-to-digital converters. IEEE Trans. Circuits Syst. I 56(3), 509–518 (2009)

Chapter 3

Low-Power Successive Approximation ADCS for Wireless Applications Jan Craninckx

Abstract This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power efficiency of the ADC up to levels that are out of reach of the typically used pipeline architecture. The second part of this paper discusses the charge-sharing SAR ADC architecture, which proposes a new signal processing method in the charge domain that removes the often-neglected though requirements for the reference buffer. An implementation in 40 nm CMOS achieves 9.3ENOB and 60MS/s at a figure of merit of 34 fJ.

1 Introduction When it comes down to achieving low power consumption in A-to-D conversion, the successive approximation (SAR) principle appears to be a very attractive candidate. For an N-bit ADC, only N operations are needed to determine the output word, a process that can be done with little overhead. The use of the SAR architecture has been widely adopted since the original introduction of the charge-redistribution ADC in 1975 [1]. In this technique, illustrated in Fig. 3.1, the input voltage is first sampled on an array of binary scaled capacitors. Then, by sequentially switching the bottom plates of the capacitor to the reference voltage or to ground, this input voltage can be compared with different levels and in a binary-search the exact input level is determined. During this process, charge is indeed ‘redistributed’ between the two sides of a voltage

J. Craninckx () Imec, Kapeldreef 75, 3000 Leuven, Belgium e-mail: [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 3, © Springer ScienceCBusiness Media B.V. 2012

39

40

J. Craninckx QX = –2CVIN VX = 0

VX

+

VC

–

C

C 2

C 8

C 4

C 16

VIN

C 16

VREF

Fig. 3.1 Conceptual 5-bit charge-redistribution SAR ADC [1]

divider constructed between the capacitors. A full conversion cycle thus consists out of 1 C N events (1 input sampling and N comparisons). This conceptual ADC schematic is deceivingly simple: there is only one active element (a comparator) and it further contains just some passive capacitors and a set of switches. An easy conclusion would be that a really low power consumption can be obtained. Still, some techniques have been proposed recently to make this basic structure even more efficient, focusing mostly on reducing the switching energy in the feedback DAC. They will be discussed in the state of the art overview in Sect. 2. An aspect that is often neglected however are the requirements posed on the reference buffers, and Sect. 3 will cover the design of an energy-efficient chargesharing SAR architecture. Finally, some conclusions are presented.

2 State-of-the-Art SAR Techniques 2.1 Split-Capacitor Array When analyzing the energy required to switch the capacitors in the typical binary weighted array, it becomes apparent that during a conversion the charge in the capacitors is not used efficiently [2, 3]. During the first bit decision after sampling, the MSB capacitor is connected to VREF with the remaining capacitors connected to ground. Depending on the output of the first comparison, the SAR will do one of two transitions. For a negative value of VX , an “up” transition must be performed for the MSB/2 capacitor, i.e. it must be switched from ground up to VREF , drawing an energy of EUP D 1=8  CV2REF from the supply. However, for a positive value of VX , more actions must be performed, i.e. besides the switching of the MSB/2 capacitor also the MSB capacitor must be switched from

3 Low-Power Successive Approximation ADCS for Wireless Applications

41

Ssample

VX

Cb-1=2b-2C0

+ Sb–1

Sb––1

C0

C1=C0

+

S1

–

S1

+

S0

–

S0

Ssample

Ssample

Ssample

Cb,b-1=2b-2C0

Cb, 1=C0

Cb,0=C0

VREF VIN

+ Sb,b–1

–

Sb,b–1 Ssample

+ Sb,1

Sb,–1 Ssample

+ Sb,0

– Sb,0

Ssample

Fig. 3.2 Split capacitor array for a b-bit SAR, with the main subarray on top and the MSB subarray below [3]

VREF to ground. In fact they ‘trade places’. Doing these two actions independently would require a much larger energy of EDOWN D 5=8  CV2REF . It takes five times more energy to lower than to raise it; this occurs because all of the charge initially on the MSB capacitor is discharged to ground, and all the charge that ends up on the MSB/2 capacitor must be delivered from the reference voltage supply. From this analysis, it is apparent that energy savings in a SAR ADC are possible if a more efficient switching scheme were devised. The most optimal scheme from [2] splits the MSB capacitor in a number of units as shown in Fig. 3.2, and switches down only the required number of them during the sequence of the SAR algorithm. This technique is expected to have a 37% lower switching energy than the conventional one [3].

2.2 Step-Wise Charging Another method to reduce the energy needed to charge a capacitor from 0 to V is to perform that operation not in one but in several sequential steps [4]. Switching in a

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J. Craninckx

b

a VN

N

V2

2

V

N

RN, CN

2

R2, C2

CT CT V1

R1, C1

1

1 0

CL R0, C0

0

CL

Fig. 3.3 (a) Step-wise charging of a capacitive load; (b) using large ‘tank’ capacitors for the intermediate voltages [4]

2

single step takes an energy of E1step D CV 2 . But because of the quadratic relation to the voltage, switching in N steps would require N units of energy that are each N2 times smaller than that: EN step D N 

C

 V 2 N

2

D

C V2 2N

(3.1)

This configuration is shown in Fig. 3.3, where it is also shown that there is no need for a separate circuit to generate the intermediate voltages. Since during a full up/down switching cycle, no supply except for the top one provides any net charge to the circuits, all intermediate voltages can be sustained by using large tank capacitors. This configuration is even self-stabilizing. This step-wise charging method thus offers the possibility of almost adiabatic switching, without the need for inductors, but of course at the expense of longer switching times, and neglecting the power needed to drive the switches themselves. This technique has been used in a low-speed but ultra-low power 10-bit SAR ADC [5], in combination with the split-capacitor array, to even further reduce the switching energy in the DAC portion of the converter. That design also uses a delayline based controller and a low-power comparator to achieve a power consumption of only 1.9 W at 1 MS/s.

2.3 Monotonic Capacitor Switching Another DAC switching method that allows even further savings was presented in [6, 7].The architecture depicted in Fig. 3.4 looks very similar to the original structure, but in fact operates rather differently because the switching only happens in one direction, e.g. downward.

3 Low-Power Successive Approximation ADCS for Wireless Applications

43

Fig. 3.4 (a) Monotonic capacitor switching architecture; (b) typical waveforms [7]

The input is sampled on the top plates, while at the same time the bottom plates of the capacitors are reset to VREF . Next, the comparator directly performs the first comparison without switching any capacitor. According to the comparator output, the largest capacitor C1 on the higher voltage potential side is switched to ground and the other one (on the lower side) remains unchanged. The ADC repeats the procedure until the LSB is decided. For each bit cycle, there is only one capacitor switch, which reduces both charge transfer in the capacitive DAC network and the transitions of the control circuit and switch buffer, resulting in smaller power dissipation. This results in an 81% reduction of the total switching energy vs the conventional case [7]. On top to that, since the switching only goes in the downward direction and fast-settling NMOS transistors can be used for this, the ADC has a potentially high maximum conversion rate. A disadvantage of this technique is that, because of the fact that the common mode voltage at the input of the comparator lowers during the successive SAR cycles as shown in Fig. 3.4b, the signal-dependent comparator offset can cause a degradation in ADC linearity.

2.4 Discussion It is interesting to note that a lot of recent SAR improvements have focused on this reduction of capacitor switching energy. While in fact, it is often not the most power consuming block in the ADC. The implementation in [5] uses only 20% of the total power budget for this. The most efficient monotonic technique of [7] would have theoretically needed only about 7.5% of the total power, but just because of the digital buffers driving the switches this was increased to 16%. Designs targeting 8-bit resolutions have relaxed matching requirements and can use extremity small capacitor sizes to lower the switching energy [8, 9]. These numbers show that capacitor switching energy is not dominant and a shift in focus is needed for further efficiency improvements.

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An aspect that in reality leads to a larger power consumption in other blocks is the fact that that the total SAR conversion takes 1 C N events, so certainly in highspeed designs only a limited amount of time can be attributed to each action. First, a powerful input voltage buffer is needed in order to make sure that during the (short) input sampling phase the voltage on the (large) capacitor array can settle accurately to the actual value. For the same reason also an accurate and high-speed reference buffer is needed to make sure that a stable reference voltage can be maintained during the charge-redistribution process. Second, the clock generation must be taken into account. Since the SAR algorithm runs at a speed higher than the actual conversion rate, a high-frequency clock is needed. This aspect was also already discussed in [5, 7], where asynchronous controllers are used. Thirdly, the comparator power must also be taken into account. This part is not easily quantified, as it heavily depends on the available or tolerable signal swing. Also the ADC speed requirements play an important role, as the comparator noise/power trade-off becomes more and more disadvantageous when very short evaluation times are needed. Of course, depending on the actual number of bits or conversion rate needed in a specific application, all these effects become more or less important. But they are not always taken into consideration when power consumption numbers are reported, so care must be taken. In the remainder of this paper, a novel charge-sharing SAR architecture will be presented that focuses on these aspect for the realization of lowpower ADCs.

3 Charge-Sharing Successive Approximation ADC Architecture The SAR ADC topology proposed does not need any high-speed buffers. Instead of operating in the voltage-domain, the useful signal is represented by charge. Its operation is explained in the following steps [10, 11].

3.1 Input Sampling An accurate charge proportional to the input signal must be created, and the most obvious way is of course to sample the input voltage on a capacitor. However, to avoid the problems of high-speed settling, a full conversion period must be available for this. If we manage to avoid that the input must be sampled on the binary capacitor array, but instead can be sampled on a separate capacitor, a time-interleaved Sample & Hold (S/H) can be used.

3 Low-Power Successive Approximation ADCS for Wireless Applications

45

Ψ1 Φ2

CTH1

CLK

Φ1 TG1

Ψ1

BM1 CTL1 VQP

INP

rst

Φ2 Ψ2

0 0 1

1 1 1

0

1

0

1

CTL2 TG1

Φ1

1

0 1 0

Ψ2

rst BM1

1

Φ1 Φ2

CTH2

VQP INP VCM

Fig. 3.5 Single ended schematic of the time-interleaved S/H and relevant waveforms

The time-interleaved sampling circuit, shown in Fig. 3.5, processes a largeswing single-ended input signal with common mode level VCM typically around half of the supply voltage. The circuit is based on bootstrapped NMOS switches at the input (BM1) [12], offering a low, signal-independent on-resistance, and passgates at the output (TG1). When phase ˆ2 is active, the input signal is tracked on capacitors CTL1 C CTH1 while the charge previously sampled on CTL2 C CTH2 is already available for conversion. So after sampling, the capacitors CT hold a charge proportional to the input: Qin D CT  Vin

(3.2)

An extension to the basic operation is the fact that, after the MSB will have been determined and the maximum differential voltage on the nodes VQP;N becomes smaller, the common mode voltage VCM can be lowered without the risk clipping the signal to ground. To create this CM shift, the connection of the capacitors CTH is switched from VDD to ground by the signal ‰ 1;2 . With this lower common mode, the on-resistance of NMOS switches that will be connected to the sampling nodes will significantly decrease, an effect that will show its benefit once the core of the SAR operation is explained.

3.2 Successive Approximation Operation After sampling, the analog-to-digital conversion can start. The most significant bit is determined first by using the comparator to check if the differential voltage on CT

46

J. Craninckx VQP c0n

CTP

c0p

c0p

CTN VQN

Precharge CMSB

Precharge

c0n

S/H Compare c0p c0n VQN

VQP

Fig. 3.6 Comparison and charge sharing action for MSB detection

is positive or negative. Depending on that decision, a signal proportional to half of the input range must be subtracted or added to the input signal. In order to avoid tough specs on the voltage settling time with opamps, we will not add a certain voltage to the signal, but instead add a charge. This operation can be done by passive charge sharing and happens very fast without taking any power. As shown in Fig. 3.6, this charge is taken from a capacitor of a certain size that has been pre-charged previously to a fixed reference voltage. If the comparator input voltage is positive (VQP > VQN ), the switches controlled by c0p are closed, after which the charges on the three capacitors (CTP , CTN and CMSB ) equalizes. The voltage VQN will rise and VQP will fall. Likewise, if the comparator input voltage is negative (VQP < VQN ) as in the figure, the switches controlled by c0n are closed, after which voltage VQN will fall and VQP will rise. The total charge on the capacitor set is now given by Q0 D CS  Vin C S0  C0  Vref

(3.3)

where S0 represents the output of the comparator (C1 for positive,1 for negative signal). The time needed for this charge-sharing process is of course proportional

3 Low-Power Successive Approximation ADCS for Wireless Applications

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to the time constant given by the product of the switches on-resistance and the capacitor size. Since nmos switches are used for this, the on-resistance is improved by lowering the common-mode voltage as described earlier, and hence the ADC speed increases. It is crucial to note here that the reference voltage itself is not loaded by this action. During the pre-charge phase, that reference voltage was sampled on the capacitor CMSB , and it is that reference charge that is now used to provide the feedback DAC action required in the SAR ADC. The reference is thus independent on the input voltage, and the constraints posed on the reference buffer are almost negligible. Even if an error would have been made during the reference sampling, because of its independency on the input that would only result in a gain error of the ADC, which is not important. The following bit is determined in the same way, but now a precharged capacitor of size CMSB1 D CMSB /2 will be used, since in the binary search for the correct digital output code the range is now reduced by a factor 2. The sign of the voltage on the capacitor set formed by CT and CMSB represents the sign of the current signal Q0 , so the comparator can be used again to determine it. Depending on the comparator output, the switches c1p or c1n are closed, and the following charge sharing action between CTP , CTN , CMSB and the newly connected CMSB1 will cause the voltages VQP and VQN to rise or fall. Intuitively one can see that the SAR algorithm at each step uses these pre-charged capacitors to add or subtract a binary scaled-down charge to the initial charge (that represented the sampled input voltage) until the results converges to zero. If too much charge was added during a certain step, the next comparison returns the opposite sign, and in the next step the charge will be subtracted. The actual value of the voltage on the nodes (VQp,VQn) is not needed, just the sign is used to determine if the next binary scaled down capacitor (and hence, charge) must be connected positively of negatively.

3.3 First Block Diagram The block diagram of this initial charge-sharing SAR ADC architecture is shown in Fig. 3.7. As already explained, it consists of • a passive time-interleaved Sample&Hold with capacitors and switches • a binary scaled array of unit capacitors that are pre-charged to the reference voltage (e.g. the power supply) and afterwards connected positively or negatively to the sampling capacitor, depending on the outcome of the comparator • a comparator that returns the sign of the differential voltage on the sampling capacitors (VQP VQN ) • a control block that implements the SAR algorithm, i.e. – generate the control signals for the S&H switches – generate the signal precharge

48

J. Craninckx VQP

INP

4

2

1

N–1

M=2

CU

INN cn

cp

VQN cp[0..N–2] cn [0..N–2]

Sample & Hold

Precharge Comp

CLK Control block @FS

Result

B[0..N–1]

Fig. 3.7 Block diagram of initial charge-sharing SAR architecture

– go through a loop that for every bit of the ADC • activate the comparator • interprete the result and close one of the switches cp or cn – output the digital code that represents the digitized value of the input voltage.

3.4 Asynchronous Operation The synchronous operation of the control block described above would need a highfrequency clock, which has to be generated externally and hence also results in a power consumption penalty. Moreover, the maximum speed possible with the circuit is not exploited, as this way of working requires the control block to e.g. wait until the falling edge of the clock to close one of the switches cp or cn, although the comparator result S is already available earlier. All blocks (comparator speed, settling time for charge sharing) must be designed fast enough to certainly finish within the available clock period.

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INp

INn

OUTp

Comp

49

OUTn

OUTp OUTn

Valid

Fig. 3.8 Comparator for asynchronous operation

An asynchronous operation must be implemented that removes the need for an extra high-frequency clock, and allows analog-to-digital conversion at the highest possible speed. The timing of this asynchronous controller is fairly simple, as a straightforward sequential list of actions must be taken during the binary search algorithm. It is further aided by the use of a comparator that also provides a ‘valid’ signal, as shown in Fig. 3.8. The comparator is based on [13]. The ‘valid’ signal goes high after the two crosscoupled inverters leave their metastable operating point, meaning one of the two sides has gone high. This means the comparison results is ready. This comparator circuit also has the nice feature that it is a fully dynamic implementation that does not consume any power when inactive, and thus enables for the whole ADC the feature that its power consumption scales linearly with the sampling frequency.

3.5 Binary Scaled Capacitor Array The linearity (INL/DNL) performance of a SAR ADC is determined by the INL/DNL performance of the feedback DAC, and thus by the matching of the capacitors in the binary scaled reference array. From [14] it can be derived that e.g. for 99.7% yield, the units of a 9bit DAC need a standard deviation less than 0.7%, which is the key number in determining the size of the reference capacitor array. With some margin, the total size is set at 2 pF, such that CMSB D 1 pF, CMSB1 D 0.5 pF, etc.

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J. Craninckx VREF

Share1

16C

8C

4C

2C

C

C

Share2

C

Share3

C

C

Charge Ground Charge Ground Share1 Share2 Share3

Fig. 3.9 Example of the capacitor array for a 9-bit ADC with a 3 upscaled unit capacitor

The resulting LSB capacitor size now equals about 8 fF, which is obviously too small to be used. The parasitics from the connections will be too large w.r.t. the actual capacitance, and since the units can be positively or negatively connected to the sampling capacitor, any difference or mismatch in these parasitics deteriorates the INL/DNL behavior. An alternative for the most significant bits is certainly to use a bigger unit, e.g. eight times bigger. The capacitor controlled by c0p;n can now consist of 16 units of 60 fF, which is a value that can be practically used. The following one has 8 units, and so on until the one controlled by c4p;n which has 1 unit. For the next charge sharing, a 30 fF unit could be used, but this will not match correctly with a ‘half’ unit of 60 fF. Instead, since we only care about the amount of charge that we will connect to the sampling capacitors CT , a 60 fF capacitor can also be charged to half of the reference voltage. This is done by taking 2 units, keep one of them empty and charge the other one to VREF . If then a switch between them is closed, the charge redistributes evenly and on each one a charge of 60 fFVREF /2 remains. This one can be used for the charge sharing by switches c5p;n . Also the next bits can be done similarly. If we close a switch between the other unit with half of the charge and an empty one, on each of them we have one quarter of charge for the next bit, and so on. With this structure a practical size unit capacitor can be used, and an example of this capacitor array is depicted in Fig. 3.9. The effect of parasitics in the capacitor array must of course be evaluated carefully. In first order, the parasitics to the substrate of the unit capacitors do not pose a problem. They behave just as useful capacitors, i.e. they have a certain charge on them which will be connected to the positive or negative sampling capacitor and this way help to perform the DAC operation of the SAR ADC. Some constraints do apply however. First of all, the parasitics on both sides of the capacitor must be balanced. If not, connecting the units positively or negatively to the sampling capacitor will have a

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different result. Therefore, the use of symmetric MoM capacitors that use lateral capacitance between a large number of closely space metal fingers is necessary. Capacitor structures that use vertical capacitance have obviously different parasitics on the top and the bottom plate. Mismatch of the parasitics will also result in missing the INL spec of the ADC, but since often no process data is available to estimate these mismatches, the only solution is to keep the parasitics small. An important part of the parasitics is caused by the switching transistors as well. Their drain-bulk and source-bulk junction constitute a non-linear capacitance. Their gate capacitance varies from very large to very small when the transistor switches from on to off. At first sight, this could be a performance-degrading effect, but to a first degree this nonlinearity is not important. The signal is represented by charge, and the fact that this charge is present on a nonlinear capacitance is of no importance. Besides matching, also sampling noise is an item that determines the minimum input capacitance of the ADC, and hence also the size of the reference array as these two are proportional. Each time a sampling switch closes, a noise power (given by the integrated noise voltage kT/C) remains on the capacitor. However, with capacitor sizes in the picoFarad range as dictated by matching requirements, kT/C noise is often negligible.

3.6 Comparator Noise Although also not obvious from the basic architecture of Fig. 3.8, care must be taken when designing the comparator. During the SAR algorithm, sometimes the input signal to the comparator is very small, and when this value becomes comparable to the inherent noise of the comparator, an error can be made. An elaborate analysis of the noise sources in a comparator falls out of the scope of this text, more details on this can be found in [15]. Comparator noise was the reason why the first prototype of the charge-sharing SAR that was implemented [10] had a measured performance that was worse than originally estimated. Reducing comparator noise by increasing its power consumption quickly has a detrimental effect on the overall energy efficiency, since for a 6 dB (2) noise reduction, a quadratic increase (4) in power is needed. To resolve this issue, a noise robust design approach to fully dynamic SAR ADCs was developed by leveraging redundancy in the search algorithm [11]. The strategy behind the proposed correction technique is the fact that during the SAR operation, at most two out of N comparisons are critical, i.e. the one when the signal is right below the threshold and the one when it is right above. All other comparisons will be done on a relatively large input signal, and hence can use a low-power but noisy comparator. A low-noise (higher-power) comparator is only needed for the critical decisions, but of course it is unknown when they will appear. However, one of them will certainly be the last one: an error in this decision can be avoided by using the comparator in its low-noise/high-power state. The other one can be any of the

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a

High Noise Comp b0

b1

b2

Low Noise Comp b3

b4

b+ Vout = 11011 = 27

V QP

OK! Vout = 11011(0)

YES

NO

b4 == b+

Truth table

VQN

b

1

1

0

1

1

b0

b1

b2

b3

b4

VQP

Nth 0 1 1 0

0 b+

OR!

ERR

(N+1)th 1 0 1 0

Correction No No +1 –1

Vout = 11100–1 = 27 Vout = 11100(0) –1

b4 == b+

YES

NO 0 or 1

0 1 +1

VQN 1

1

1

0

0

0

Fig. 3.10 Correction algorithm for comparator noise (5b example) in case no error is made (a) and in case of error (b)

previous (N1) comparisons, and avoiding it by always employing a low-noise comparator is not power efficient. As shown in Fig. 3.10 for a 5b example, the SAR algorithm in the proposed redundant search algorithm uses the comparator in its high-noise state during the first (N1) iterations, thus allowing errors in these cycles. However, if  H , the input comparator RMS noise in that mode, is less than one half of the LSB value, only one error can be made. The ADC then switches into its low-noise mode (with comparator input noise  L   H /2) to avoid errors for the Nth comparison, and an extra (N C 1)th iteration is added to correct for the error possibly made in the first phase. As shown in Fig. 3.10a, if the last two comparisons give different results, no error was made and no action has to be taken. On the other hand, in case the last two bits are equal, then a digital addition or subtraction needs to be performed on the final N-bit result. Being pipelined to the SAR conversion, the simple digital adder needed to correct does not work at the internal SAR frequency (N times the sampling frequency), thus limiting its power consumption. Importantly, the correction is effective not only for thermal noise, but also for other error sources, including static non-linearities, as far as they are not bigger than one LSB.

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3.7 Comparator Offset In contract with classical charge-redistribution SARs, in the charge-sharing SAR offset of the comparator does have an effect on the INL/DNL performance. The reason for this is that the signal is represented by charge and the offset in the comparator is always a certain voltage. During the successive approximation process, the capacitance size is changing and hence the relationship between charge and voltage is not fixed. To make the comparator offset small enough not to have an effect, the same offset calibration technique as in [13] was again used, as already indicated by the varicaps shown in Fig. 3.8. At startup or at regular time intervals, the two inputs of the ADC must be shorted and the correct digital value must be searched that results in equal probability of a positive/negative comparator decision.

4 Implementation The ADC prototype that was designed to show the performance of the proposed techniques was implemented in a 90 nm 1 V 1P9M digital CMOS process [11]. The die photo is shown in Fig. 3.11. Only regular transistors and MoM-caps are used in the whole design, making it ideally suited for implementation in digital CMOS. Figure 3.12a shows the static INL/DNL performance when the correction is active. The peaks in DNL and INL are due to incomplete settling during the common mode switching, a small design mistake that could easily be corrected. The actual

Fig. 3.11 Nine-bit 40MS/s charge-sharing SAR ADC photograph

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J. Craninckx

a

b 9

ENOB

1.5 1 0.5 0 –0.5 –1 –1.5 0

255

8.5 8

7.5

510

0

0.5

–20

[dBFS]

1

0 –0.5

1

21

ENOB = 8.23 Bit SNDR = 51.31 dB THD = 52.76 d B fln = 18.8821MHz N = 16384

–40 2nd

–60

–1

11

Freq [MHz]

7th

5th

3rd

–80 0

255

510

0

2

4

6

8

10

12

14

16

18

20

Freq [MHz]

Fig. 3.12 (a) Measured INL/DNL plot; (b) ENOB vs. frequency and near-Nyquist FFT at 40MS/s

error caused by this effect is even worse (uncorrected INL/DNL is worse than C/1LSB), but as already stated the correction algorithm does not only detect errors cause by noise, but also this static nonlinearity. The peak resulting DNL and INL are 0.7/0.45 and 0.56/0.65 respectively. As shown in Fig. 3.12b, when the input signal is sampled at 40Ms/s, the measured ENOB is 8.56 (53.3 dB SNDR) at low frequencies, mainly limited by static distortion, and lowers to 8.23 at Nyquist. The effective resolution bandwidth extends up to 32 MHz. At 40Ms/s the ADC consumes 820 A from a 1 V supply voltage of which 290 A are drawn by the asynchronous controller, and 530 A are shared between the S/H, the pre-charging phase of the capacitor array, and the flexible comparator. Because of the dynamic architecture, power scales linearly with the sampling frequency. The resulting FoM is only 54 fJ per conversion step. Since this SAR ADC only contains digital gates, capacitors, switches and one comparator, it lends itself easily to further scaling in more advanced technology nodes. With decreasing CMOS features, the performance is expected to improve, since controller will become more power efficient and on top of that the capacitor sizes could be chosen smaller because of the improved matching characteristics. A new implementation of the charge-sharing SAR ADC in 40 nm CMOS as part of a full SDR transceiver [16] targets a resolution of 10 bit. This extra bit would normally require a 4 increase in the capacitors for matching, but because of the more advanced process node the total reference array size could be kept at 2 pF. Most of the building blocks (boosted input switch, capacitor array with 3 upscaled unit, controller, : : : ) have been simply ported into the new technology, the only serious effort needed for the new design was on the only analog block of the

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55

Fig. 3.13 Low-noise comparator schematic

Fig. 3.14 Ten-bit 60MS/s SAR ADC in 40 nm CMOS

converter, i.e. the comparator. As the comparator noise becomes the limiting factor in the achievable ADC resolution, the new design uses a dynamic preamp and an improved latch timing of the second stage that uses internal signals instead of the external clock [17] (Fig. 3.13). A die photo of a separate test chip to evaluate the ADC performance is shown in Fig. 3.14 and the measurements are reported in Fig. 3.15. The maximal sampling speed is 60 MS/s, with a power consumption of 1.2 mW. At lower speeds, the power decreases proportionally. The maximum DNL and INL are 1.4 and 0.8 LSB, respectively. An SNDR of 54 dB (9.3 ENOB) is obtained, which results in a figure-of-merit of 34 fJ per conversion step.

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a

b

c

Fig. 3.15 Measured ADC performance. (a) INL/DNL; (b) near-Nyquist FFT; (c) SNDR vs input frequency

5 Conclusions As has been shown by many publications in the last years, SAR ADCs have replaced the typical pipeline design in the application range of 8–10 bit accuracy and sampling speeds up to several 10’s of MHz. The simplicity of the SAR architecture

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makes it very well suited for implementation in nanoscale CMOS, and several improvements in capacitor switching strategy, asynchronous controller implementation and low-power comparator design has improved the power efficiency by an order of magnitude. Furthermore, the charge-sharing architecture is proposed which makes the load of the reference buffer signal-independent, thereby removing all constraints posed on the reference buffer by a high-speed ADC. With continuous scaling of CMOS technology nodes, and probably with some more architectural improvements, ADCs with a figure of merit of a few femtoJoules per conversion step will be just around the corner! Acknowledgment The work presented here is the result of the research on ADCs performed in imec’s wireless research group in the past years, and the author would like to acknowledge the contributions of all team members, an especially Vito Giannini, Geert van der Plas, Bob Verbruggen, and Takaya Yamamoto.

References 1. J. McCreary, P. Gray, All-MOS charge redistribution analog-to-digital conversion techniques – Part I. IEEE J. Solid-State Circuits 10(6), 371–379 (1975) 2. B. Ginsburg, A. Chandrakasan, An energy-efficient charge recycling approach for a SAR converter with capacitive DAC, in Proceedings of IEEE International Symposium Circuits and Systems, 2005, pp. 184–187 3. B. Ginsburg, A. Chandrakasan, 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC. IEEE J. Solid-State Circuits 42(4), 739–747 (2007) 4. L.J. Svensson, J.G. Koller, Driving a capacitive load without dissipating fCV2, in IEEE Symposium on Low Power Electronics, 1994, pp. 100–101 5. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E.A.M. Klumperink, B. Nauta, A 10-bit charge-redistribution ADC consuming 1.9 W at 1 MS/s. IEEE J. Solid State Circuits 45(5), 1007–1015 (2010) 6. C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 m CMOS process, in IEEE Symposium on VLSI Circuits Digest, June 2009, pp. 236–237 7. C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, A 10-bit 50-MS/s SAR ADC With a monotonic capacitor switching procedure. IEEE J. Solid State Circuits 45(4), 731–740 (2010) 8. P. Harpe, C. Zhou, X. Wang, G. Dolmans, H. de Groot, A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90 nm CMOS, in ISSCC Digest of Technical Papers, Feb 2010, pp. 388–389 9. P. Harpe, C. Zhou, X. Wang, G. Dolmans, H. de Groot, A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios, in Proceedings of European Solid-State Circuits Conference, Sept 2010, pp. 214–217 10. J. Craninckx, G. Van der Plas, A 65fJ/conversion-step 0-to-50Ms/s 0-to-0.7 mW 9b Charge sharing SAR ADC in 90 nm digital CMOS, in ISSCC Digest of Technical Papers, Feb 2007, pp. 246–247 11. V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, J. Craninckx, A 820 W 9b 40MS/s noise tolerant dynamic SAR ADC in 90 nm digital CMOS, in ISSCC Digest of Technical Papers, Feb 2008, pp. 238–239 12. M. Abo, P. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid State Circuits 34(5), 599–606 (1999)

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13. G. Van der Plas, S. Decoutere, S. Donnay, A 0.16 pF/conversion-step 2.5 mW 1.25GS/s 4b ADC in a 90 nm digital CMOS process, in ISSCC Digest of Technical Papers, Feb 2006, pp. 566–567 14. A. Van den Bosch, Static and Dynamic Performance Limitations for High Speed D/A Converters (Springer, New York, 2004). ISBN 9781402077616 15. P. Nuzzo et al., Noise analysis of regenerative comparators for reconfigurable ADC Architectures. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 55(6), 1441–1454 (2008) 16. M. Ingels et al., A 5 mm2 40nm LP CMOS transceiver for a software-defined radio platform. IEEE J. Solid-State Circuits 45(12), 2794–2806 (2010) 17. M. Miyahara, et al., A low-noise self-calibrating dynamic comparator for high-speed ADCs, in Proceedings of IEEE Asian Solid-State Circuits Conference, Nov 2008, pp. 269–272

Chapter 4

Oversampling Converters Beyond Continuous-Time Sigma-Delta for Nanometer CMOS Technologies A. Di Giandomenico, L. Hernandez, E. Prefasi, S. Paton, A. Wiesbauer, R. Gaggl, and J. Hauptmann

Abstract This paper describes first the properties of Continuous-Time SigmaDelta ADCs which make this type of converters attractive for low-power and high-bandwidth applications. Cascaded architectures are analyzed as a possible way to further improve the analog bandwidth. The limits towards nanometer technology integration are then described, showing how the time-encoding theory can be successfully applied to overcome them. Two different implementations are introduced (PWM-based and VCO-based), and some case-studies are given to support the theories. Conclusions are drawn, with emphasis on possible future development steps.

1 Introduction Sigma-Delta ADCs are a valid and attractive solution to build converters with either a very high resolution (above 20-bits [8]) or a very high analog bandwidth (above 100 MHz [14]) while consuming a lower power if compared to other A/D types, such as SAR (for high resolution) or pipeline (for high bandwidth). Discrete-Time (DT) types are preferred when a high resolution in a narrow-band is required, due to the very good matching achievable between integrators gain and system

A. Di Giandomenico () • R. Gaggl • J. Hauptmann Lantiq, Villach, Austria L. Hernandez • E. Prefasi • S. Paton UCIIIM, Madrid, Spain A. Wiesbauer Infineon Technologies, Villach, Austria M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 4, © Springer ScienceCBusiness Media B.V. 2012

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a

b fs =

Amp[H(s)]

1

poles

Ts

u(t)

y(n)

zeros

H(s) DAC

UGF ADC Phase[H(s)] –180º PM

Fig. 4.1 (a) A classical CTSD converter and (b) Amplitude and phase of the open-loop transfer function

coefficients. On the other hand, Continuous-Time (CT) implementation presents someadvantages, when the target resolution is not very high (below 14-bits): • Built-in anti-alias filter: since the sampler is moved just before the internal ADC (see Fig. 4.1), the loop filter H(s) can be designed such that the signal transfer function (STF) has a low-pass characteristic. This can be realized efficiently by using multi-feedback architectures, although an interesting structure was proposed which uses explicit-filtering to provide high immunity to interferers [6]. This property can be used in the system where the CTSD is embedded, to simplify the receive chain, saving area and power. • High-impedance input stage: the input network of a CTSD is usually a simple resistor connected to the virtual-ground of the first integrator (Opamp-RC filter implementation) or a simple differential-pair of a transconductor (Gm-C filter implementation); this simplifies the design of the preceding filter, since it doesn’t need to drive a big switching load (like the one presented from other types of converters such as DT-SD, SAR or pipeline). Moreover, the input network can be made programmable quite easily (for instance with a programmable resistor), realizing in this way also a built-in PGA functionality [6]. The system design of the loop filter is done by placing first the poles to optimize the bandwidth and then by finding the zeros to recover stability. For a given loopfilter, the architecture of the CTSD can be chosen to target high analog bandwidth (BW) and low power consumption, by tuning some system parameters such as OverSampling-Ratio (OSR), loop-filter order or number of levels of the internal quantizer [3]. The physical limit towards BW increase is the maximum sampling frequency achievable in a given technology, while the limit towards power reduction is the current consumption of the active elements used. This paper aims to present two architectural strategies to push the CTSD beyond their limits: • Cascaded (MASH) architectures: increasing the OSR allows increasing the analog BW. When the clock frequency can’t be made higher, then the only option

4 Oversampling Converters Beyond Continuous-Time Sigma-Delta...

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to further increase the analog BW is reducing the OSR. Since high-order loops become unstable for low OSR, the architecture must be split into a cascade of low-order single-loop SD, still maintaining the overall high-order noise-shaping. • Time-Encoded quantizers: exchanging amplitude-quantization with timequantization allows replacing the power-hungry quantizer with structures simpler which consume less current and occupy less area. This exchange can be done at a price of a higher time resolution (which often means also a higher sampling rate), making these architectures particularly attractive for nanometer technologies. This paper is organized as follows: Chap. 2 gives an overview of the most important challenges for designing efficient CTSD converters; Chap. 3 describes how to extend the analog BW by using MASH topologies; Chap. 4 shows how the time-encoding theory can be effectively applied to the design for low-power and low-voltage applications; in Chap. 5 the conclusions are presented.

2 Challenges and Limitations of Classical CTSD One of the most important challenges for designing an efficient CTSD is to keep the modulator stable even with all the impairments imposed by the non idealities of the analog and digital building blocks. Another limitation of this type of converters – which must be considered in the noise budget since the beginning of the system design phase – is the high sensitivity to clock-jitter. This chapter describes all these challenges and shows the most common ways to reduce their undesired effects.

2.1 Modulator Stability and Excess Loop Delay As described in Fig. 4.1, the phase margin of the open-loop transfer function mainly depends on the location of the compensation zeros with respect to the in-band poles. If the OSR of the modulator is high enough, then the compensation is easy and a high phase margin can be achieved. On the other hand when the OSR becomes too low (typically below 16), then the order of the modulator must be increased to still achieve the target SNR: this leads to a loop filter design very aggressive, with reduced phase-margin and high sensitivity to coefficient deviation. Hence, when trying to increase the BW by reducing the OSR, all non-idealities leading to a phase-loss in the loop must be considered, and primarily two among all: the parasitic effects in the integrators and the digital latency in the feedback path.

2.1.1 Parasitic Effects in a Real Integrator The most severe non-idealities in a real integrator are the finite GBW of the OpAmp and the parasitic capacitance at the virtual-ground node, as shown in Fig. 4.2.

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a

b

CINT RINT

RZ

CINT

RINT –

CPAR

–

+

CPAR

GBW

+

–

+ GBW + –

OpAmp Transfer Func Ideal Integrator Transfer Func

Real Integrator Transfer Func With compensation

FREAL FINT

Real Integrator Transfer Func

GBW

FLP

Fig. 4.2 A real integrator without (a) and with (b) zero-compensation

Given a first-order approximation of the OpAmp (considering the finite DC gain Av1), then the real transfer function of an ideal integrator with ¨int D 1/Rint Cint angular frequency, can be written as: Hint;real .s/ D GE  Hint;ideal .s/  Hlp .s/ D GE 

Tclk 1  s s  Rint Cint 1 C 2F LP

(4.1)

The real transfer function is therefore affected by a gain-error GE and by a phaseloss equivalent to having a high-frequency pole FLP : GE D

1 1C

!int 2GBW

FLP D

 ! Cint int C GBW  Cint C CPAR 2

(4.2)

From (4.2), one can see that both effects are proportional to the GBW of the OpAmp (which changes under different PVT conditions); the gain error mainly depends on how far is the GBW with respect to the integration frequency, while the parasitic pole mainly depends on how big is the parasitic capacitance with respect to the integrating capacitance. The gain error can only be compensated by re-tuning the integration frequency, though particular care must be taken to ensure that the GBW doesn’t change too much with the operative conditions. On the other hand, the phase-loss due to the parasitic pole can be compensated by adding one resistor in the feedback network to realize a pole-zero cancelation [46], such that:

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2

u(t) H(s) DAC 4

3 DEM ?

FADC u(t) –

ADC-out

H(s)

A

τ = ELD, [0..1] e

–sττ

DAC Ideal delay-free subsystem

PMLOSS

Φ –180° PM

Fig. 4.3 (a) Excess loop delay and its effect in a CTSD converter

  1 1 2  GBW D  1C RZ RINT C RZ !int

(4.3)

The compensating resistor Rz is usually very small (in the range of some hundreds of Ohms) and hence can’t be tuned. As a result, from (4.3), one can see that the cancelation works well only if the gain-bandwidth product of the OpAmp doesn’t vary too much with the operative conditions.

2.1.2 Analog and Digital Latencies in the Feedback Path In an ideal CT sigma-delta converter the digital data in the feedback loop is instantaneously generated in the quantizer when the clock edge arrives, is then instantaneously propagated via the feedback network down to the main DAC and is finally instantaneously converted into an analog signal at the summing node of the loop-filter. In real life, however, all these processes require some finite time to happen as in practice (see Fig. 4.3): 1. The comparators need some time to decide, depending on the input level 2. The digital buffers needed to drive the long feedback lines introduce a digital latency 3. If a DEM block is necessary to linearize the main DAC, then its latency must also taken into account (this is often the dominant delay source) 4. The response time of the main DAC is always finite

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b

a +

Hsd(s)

+

–

Hsd(s)

–

+

+

–

fbe

D/A

c

D/A

d

Loop Filter H(s) x(t)

Loop Filter H(s)

Analog Adder

+

+

y(t)

x (t) A/D

+

–

y(t)

+ –

fbe

cint / s

A/D

Last Integrator

fbe¢ u(n)

v(n)

D/A

D/A

Inner D / A converter

Digital Differentiator

u(n)

Inner D / A converter

Fig. 4.4 (a, b) Excess loop delay compensation at system level and (c, d) some implementations

The latency introduced by the DEM block can be avoided by using different techniques to linearize the main DAC, such as background self-calibration [47]. To understand the effects of all these delays in the loop, one can build a simple model, using a single delay element in the feedback path to take into account the four non-idealities listed above. The phase loss introduced by this delay element is then proportional to the relative delay Td (compared to the clock period) and to the analog bandwidth (compared to the clock frequency): P MLOSS

1  / 2OSR



2  Td Tclk

 (4.4)

Expression (4.4) tells that the effect is higher for low-oversampling converters, while it can be negligible if the OSR is high enough. Since in Low-OSR converter the loop filter is usually designed to be quite aggressive, any additional phase-loss can’t be tolerated and compensation techniques become unavoidable. One of the most used ELD-compensation consists in adding a high-frequency zero in the openloop transfer function, by a dedicated feedback loop just before the quantizer (see Fig. 4.4b) [1, 5]. One way to realize this loop is to build an additional D/A converter and an analog adder (see Fig. 4.4c); however, this solution is not really efficient, since it requires extra-hardware which costs area and power (the analog-adder should have also very high bandwidth, in order to maintain the high-frequency zero). An alternative and more efficient solution [9, 14] is to make use of the last integrator of the loop-filter (see Fig. 4.4d): in this case, the digital signal must

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Fig. 4.5 A sensitive (a) and a less sensitive (b) Noise transfer function

be differentiated before the inner D/A converter, in order to compensate for the following integration. If the architecture of the modulator is multi-feedback, then the inner D/A converter can be also re-used by taking a digital adder to combine the normal digital signal to the ELD-compensation signal coming from the digital differentiator.

2.1.3 Effects of Clock Jitter The biggest drawback of CT sigma-delta modulation is the high sensitivity to clock jitter [1]. This is basically due to the fact that if the width of the pulse sent back in the loop by the main DAC varies randomly at each sampling process, it generates an error which is at least integrated once in the loop filter. If the spectral density of the clock jitter (assumed to be a random process uncorrelated with the input signal) surpasses the quantization noise density, it can limit the overall SNR. The only way to reduce the effects of clock jitter is to reduce the average-step-size (ASZ) of the modulator, and this can be achieved either by increasing the levels of the quantizer (using multi-bit D/A converters) or by reducing the oversampling ratio. However, in [4] a jitter-model was presented, which could be used to link the jitter-sensitivity to the spectral shape of the noise-transfer-function (NTF), hence finding a design criterion to minimize the variance  2dy of the ASZ: 2 Š dy

2 Q

2

Z

2



ˇ ˇ  ˇ 1  e j!  NTF.e j! /ˇ2 d!

(4.5)

0

Where  2Q is the variance of the jitter noise introduced at the quantizer, assumed white. From (4.5), one can see that the effect of the NTF are shaped by the weighting function Hw(¨)(1  ej¨ ), which gives more emphasis to the higher frequencies of the NTF (see Fig. 4.5).

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3 MASH Topologies One way to look at a cascaded CTSD architecture is to describe the system like a 2-step sigma-delta, where (see Fig. 4.6): • The first stage produces a quantization error ©Q • The quantization error is sensed and sent to the second stage • The second stage amplifies the error to fit into the full-scale range and quantizes it again • A digital filter takes the two digital signals from the single-stages and combines them to cancel out the quantization error of the first stage This concept can be of course extended to N-step converters, with more than two stages. The biggest advantage of this architecture is that the order of the overall modulator is given by the sum of the order of the single stages, allowing for higher stability and lower achievable OSR. On the other side, the digital coefficients must have a perfect matching with the analog coefficients in order to guarantee a perfect cancellation of the quantization noise of the first stage, avoiding noise leakage which could degrade the overall SNR. The biggest challenge in CT MASH topologies is that the quantization error is usually not available in the circuit as it is in Discrete-Time SD-ADCs, because most of the designs use a continuous-time quantizer which does not provide the sampled information before quantization [11, 12]. In such architectures, the estimated quantization error transferred from one SD-stage to the next has a peakpeak value much higher than the actual sampled quantization error. The inter-stage gain must thus be reduced to avoid overloading of the succeeding stages, reducing the efficiency of the cascaded principle by the same factor.

Q1 x(t)

1 st Stage Sigma-Delta

Q

Digital Cancelation Filters NCF1 = STF2

y1(n)

+

Q2

– G

2 nd Stage Sigma-Delta

y2(n)

1/G

NCF2 = NTF1

Y = STF1·X-1 / G· NTF1·NTF2·Q2

Fig. 4.6 A cascaded CTSD

y(n)

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67

Fig. 4.7 Block diagram of the 2–2 MASH converter

3.1 A Design Example In this chapter we present a MASH converter using a novel and simple inter-stage network, which does not overload the succeeding stages, thereby increasing the maximum stable amplitude and the dynamic range at the same time. The proposed architecture is shown in Fig. 4.7. The quantizers have been replaced with linear models. Each stage is implemented as a second order multiple feedback CTSD, so that the implicit anti-alias filter has a second order slope in each stage and a fourth order slope at the output of the cascaded CTSD. The quantization error is estimated by a simple linear combination of the two state variables of the first stage, removing the need of an extra DAC as is usually done [11, 12]. The values of the two coefficients K1 and K2 are chosen imposing that (1) the input of the second stage is a band-limited signal, (2) the transfer function from the first quantization noise to the output of the second stage is all-pass in-band, and that (3) the transfer function from the input signal to the input of the second stage is high-pass in-band. The removal of the extra DAC in the inter-stage network gives the advantage of power and area saving. The integrators are realized with OpAmp-RC cells, where the capacitors are tuned to compensate for process deviation. The feedback DAC connected to the first integrator of the first MASH-stage is self-calibrated. No mismatch-shaping logic is therefore needed in the digital feedback loop. This reduces the Excess-Loop-Delay of the modulator, which is fixed in this converter to ½ of the clock period. The Loop-Filter of the second stage is designed to be equal to the one used in the first stage.

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Analog Bandwidth

40 MHz

30 MHz

Clock-Frequency

800 MHz

600 MHz

Dynamic-Range

63 dB

70 dB

Peak-SNR

60 dB

68 dB

Peak-SNDR

60 dB

68 dB

SFDR Total Power

79 dB

85 dB

110 mW, 1.5 V

100 mW, 1.5 V 1.2 mm

Area

2

0.13 μm CMOS

Technology

FFT @ VIN = –2dBFS / 2.8320 MHz 0 SNDR vs AIN

SNR = 58.8 dB SNDR = 58.8 dB DR = 60.6 dB

–20

70

SNDR [dB]]

50 40 30 SNDR (40MHz)

20

SFDR = 79 dB

–40 –60 –80

10 0

SNDR (30MHz)

–10 –20 –80

PSD [dB]

60

–60

–40 AIN [dBFS]

–20

0

HD2 = 92.2 dBc HD3 = 78.9 dBc HD4 = 90.4 dBc HD5 = 83.3 dBc

–100 –120

0

5

10

15

20 25 freq [MHz]

30

35

40

Fig. 4.8 Layout of the MASH prototype and measurement results

This prototype CTSD modulator has been fabricated in a digital 0.13 m CMOS process. The two digital cancellation filters are designed as FIR types (2-TAPs and 5-TAPs respectively) and emulated in a software platform off-line. The loop-filter coefficients and the sampling frequency are programmable to work in two modes. In the 40-MHz analog bandwidth (ABW) mode, the modulator is clocked at 800MHz; it achieves a DR of 63-dB and a peak-SNDR of 60-dB consuming 110-mW from a single 1.5 V supply. In the 30-MHz ABW-mode, the modulator is clocked at 600-MHz and achieves a peak-SNDR of 68-dB. Figure 4.8 shows a measured output spectrum and the SNR as a function of the input signal. An FFT-plot of the output is also included for the 40-MHz mode, and the in-band zoom reveals a 79-dB SFDR for a -2dBFS sine (FS D 1.5 Vpp-diff).

4 New CTSD Architectures Towards Nanometer Technologies Integrating CTSD converters in nanometer technologies would allow for achieving higher bandwidths without power consumption penalty; however, the integration of these converters is limited by the growing difficulty of implementing circuits with high amplitude accuracy. Many problems concur to make this difficult: the implementation of the embedded multi-bit A/D and D/A converters. The main problem is the limited dynamic range of the comparators in a low voltage technology, which degrades the linearity of the quantizer.

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As CMOS technology scales towards smaller feature sizes, it is getting more difficult to design circuits with high amplitude accuracy. This is due to several problems: the threshold voltages of the transistor keep almost constant, while the supply voltages decrease; the intrinsic gain of the transistor reduces, requiring more and more cascading topologies to achieve same linearity; current sources and current mirrors have lower output impedance and a higher leakage current, requesting trimming and calibration procedures. On the other hand, nanometer technologies offer digital operations at a speed faster and faster and at an area-cost smaller and smaller. It becomes then advantageous trying to port some power-hungry operations in the CTSD modulator from the analog-domain to the digital-domain, and the most interesting area for improvements seems to be the embedded Flash A/D in the CTSD loop: here the main problem is the limited dynamic range of the comparators in a low voltage technology, which degrades the linearity of the quantizer. The “tracking-quantizer” [7] has been one of the first attempts to reduce the analog complexity of this block at a cost of more sophisticated digital circuits. However it suffers from a limited slew-rate, which can become a problem if high immunity to out-of-band interferers must be guaranteed (especially in feed-forward CTSD structures with no anti-alias built-in function). To leverage the hardware possibilities opened up by the increased maximum clock frequency of the digital circuits, one more efficient solution has been explored in the recent past: turning the amplitude-quantization into time-quantization thereby focusing on time-based analog signal processing instead of voltage- (current-) based analog signal processing, as explained in Fig. 4.9. The background of this idea is that the analog signal v(t) coming from the feedback-path is being processed by a Continuous-Time integrator (the first CTSD stage); hence, the most important information which v(t) brings in the loop is the area of the DAC pulse, which is proportional to the quantized amplitude of the DAC-output. The same information (i.e. the same area of the DAC pulse) can indeed be propagated if the amplitude of the DAC-output keeps constant, while the pulse duration becomes quantized in time. To make this idea possible, two building blocks can be defined to realize a Single-Bit Time-Encoded ADC equivalent to the standard multi-bit FLASH ADC: a Time-Encoder and a high-speed sampler. The Time-Encoder converts the amplitude of the input signal into a sequence of continuous-time pulses having the same amplitude but different duration and/or period. Such a block has the following characteristics: • It oscillates at rest (i.e. when the input signal u(t) is null) at a free-running frequency Fo, providing a well defined pulse width and period. • The duration of the pulse (referred to the instantaneous oscillation period) is modulated by the amplitude of the input signal u(t), providing a phase and/or frequency variation of the generated signal p(t). • The free-running oscillation Fo is in the same order of the sampling frequency Fs of the equivalent multi-bit FLASH ADC.

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a

b u(t)

y(n)

p(t)

u(t)

p(t)

x(n)

Fs

TDC Single-Bit TE-ADC

FLASH ADC u(t)

p(t)

y(n)

u(t)

Time Encoder

Fc x(n)

p(t)

Time Decoder

Sampler

v(t)

v(t) D/A

D/A N-bit @ Fs

1-bit @ Fc

Ts = 1 / Fs

To = 1 / Fo ROSR = To / Tc

v(t)

v(t) ~ y(n)

COSR = Ts / To

v(t)

Tc = 1 / Fc

Fig. 4.9 (a) Classical multi-bit quantizer within a CTSD loop and (b) an alternative equivalent Single-Bit Time-Encoding-ADC

The high speed sampler must run at a frequency Fc much higher than the free-running oscillation Fo of the Time-Encoder; the Ratio-Over-Sampling-Ratio (ROSR D Fc/Fo) is a measure of the ability of the sampler to digitize the timedomain information contained in the time-encoded analog signal (it’s equivalent to the number of digital levels that a quantizer is able to resolve in a FLASH ADC). In some implementations there is not a physical high speed sampler, as it is embedded in a Time-to-Digital-Converter (TDC) block, where multiple phases of the lowfrequency Fs clock are derived and distributed to a bank of latches, which sample the time-encoded continuous-time signal on different time edges. Although this idea looks simple, many system aspects must be considered, such as the relative position of the free-running oscillation frequency of the TimeEncoder with respect to the system clock Fs of the equivalent CTSD (defined by the ratio COSR D Fo/Fs) and such as the stability of the main CTSD loop. Also the Time-Encoder type plays a significant role, and in some cases additional analog or digital filtering is required in the feedback loop, as better explained in the next section. In general, the implementation of the architecture proposed in Fig. 4.9b looks quite attractive for many reasons: • The multi-bit FLASH ADC can be replaced by a simpler single-bit structure, with a big area and power saving potential: the simpler structure can be either a single comparator or a VCO, as it will be explained in the next section.

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• The multi-bit DAC is replaced by a single-bit DAC, which is an inherently linearblock: no DEM block is needed any more in the feedback path, reducing in this way the ELD and making the loop-filter design much easier. In opposite to these positive aspects, the biggest drawbacks of Single-Bit TimeEncoding CT sigma-delta are mainly some toughest requirements on the clock generation and distribution to the modulator. This architecture suffers indeed of: • An increased sensitivity to clock-jitter, which can be considered to be half-way between a standard multi-bit CTSD and a standard single-bit one. • A high sensitivity to deterministic mismatch between time-edges (for those implementations using multi-phase TDC) which can be turned into signal distortion. Indeed, the architecture proposed in Fig. 4.9b is completely different from a standard single-bit CTSD running at clock frequency Fc (i.e. the same structure shown, where only the Time-Encoder is removed). In the latter case, the loop filter would be designed for an OSR much higher, and the average-step-size [4] during normal operation would be also much higher. For this reason the sensitivity to clock-jitter of the single-bit Time-Encoded CTSD is much lower than the standard single-bit CTSD. However, since the height of the pulse at the output of the feedback DAC is always higher than the height of the equivalent multi-bit CTSD in Fig. 4.9a, this latter architecture will still result in a lower sensitivity to clock-jitter. The exact influence of clock-jitter to modulator noise strictly depends on the way the highspeed clock Fc is generated: • In some implementations, this high-frequency clock is directly derived from the main clock source (PLL): in this case the jitter requirement is directly One way to overcome this limitation and to reduce the sensitivity to clock-jitter of TE-based CTSD is to convert the single-bit stream back into a multi-bit stream by using an additional Time Decoder in the feedback loop, between the ADC and the DAC, as shown in Fig. 4.10. This alternative architecture has now only half of the benefits of the Single-Bit one, since the DAC is again multi-bit and for highresolution converters DEM logic is again necessary. However, the implementation of the Time-Decoder which follows the sampler depends on the particular type of the Time-Encoder. Although in some cases it is not possible to achieve the low-latency required by the SD loop to maintain the ELD below the stability-limit, in some other cases it can be realized by means of compact Time-to-Digital-Converters (TDC), which are able to reconstruct the multibit stream at the original sampling rate Fs. As these TDC blocks are built with purely digital cells, their area and power penalty will become more and more negligible with the scaling of the technology. The implementation of the Time-Decoder which follows the sampler clearly depends on the particular type of the Time-Encoder; in some cases it is not possible to achieve the low-latency required by the SD loop to maintain the ELD below the stability-limit, making this multi-bit approach practically unfeasible. In some other

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u(t)

p(t)

y(n)

Fs

Fc

x(n)

Tc = 1 / Fc

Ts = 1 / Fs

Multi-Bit TE-ADC u(t)

Time Encoder

p(t)

y(n)

Time Decoder

x(n)

Sampler

TDC v(t) D/A N-bit @ Fs

Fig. 4.10 A Multi-Bit Time-Encoding-ADC within a CTSD loop

cases, the sampler and the decoder can be realized by means of Time-to-DigitalConverters (TDC), which are able to reconstruct the multi-bit stream at a lower rate (usually the original sampling frequency Fs of the equivalent CTSD).

4.1 Basics of Time-Encoding ADC: Theory and Examples For a structured analysis of the Time-Encoded CTSD systems described in Figs. 4.9b and 4.10, it helps the classifications based on the specific Time-Encoder which makes the Amplitude-to-Time mapping [22]: 1. PWM-based TE-ADC: a Pulse-Width-Modulator (PWM) is used as TimeEncoder, and the way the modulation is produced leads to the two following sub-categories: (a) Synchronous PWM [24]: the pulse-width modulated waveform is generated by comparing the input signal with a periodical waveform (usually a saw-tooth or a triangular-shape) synchronous with the master clock. (b) Asynchronous PWM [18, 19, 26, 30]: the pulse-width modulated waveform is generated with a self-oscillating loop fulfilling the Barkhaussen phase criterion. The main difference between the two subcategories here above defined, is that the self-oscillation frequency is fixed and constant in the synchronous

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systems, while it depends on the input signal (amplitude and frequency) in the asynchronous ones. 2. VCO-based TE-ADC [21, 28]: in such systems a Voltage-Controlled-Oscillator is used as Time-Encoder to generate the oscillation at rest; the VCO output can then be perturbed (in frequency and/or phase) by the input signal to the TE-ADC, thereby mapping the amplitude-to-time information.

4.2 PWM-Based CTSD ADCs There are two types of Time-Encoded ADCs [22] (synchronous and asynchronous) based on Pulse Width Modulators (PWM) and their most common implementations are shown in Fig. 4.4. In the former category a fixed frequency square pulse stream is produced, where the width of each pulse is proportional to the amplitude of the sampled continuous time input signal. A saw-tooth signal generator and a comparator are used, and it has been shown that different type of triangular waveforms can lead to different results [20]. When closed in the Sigma-Delta loop, the non-linearity of the ramp generator is attenuated by the loop-gain, so its implementation is normally easy and very efficient. In an Asynchronous PWM Time-Encoded ADC, the oscillation is induced by a positive feedback fulfilling the Barkhaussen phase criterion. The input signal is then added to the feedback signal, perturbing the phase and frequency of the oscillation itself. Figure 4.11b shows the block diagram of a typical implementation, composed of a comparator, a loop filter H(s) and a delay element. Since the loop-filter (usually one integrator) is not sufficient to reach the required 180ı phase, to induce a stable oscillation, the phase of the loop is increased by a delay-block in the feedback path or by introducing hysteresis in the comparator. The oscillation frequency (so called limit-cycle) at rest and the dynamics of the system are nontrivial and need to be established in approximately [19]. One of the biggest challenge of these systems is to control (via tuning or tracking) the limit-cycle frequency over PVT variations (process, voltage, temperature) and also over the whole variety of input signals (amplitudes and frequencies). It can be proven [19] that both of the PWM time-encoding architectures do realize ideal signal coders that do not introduce any error, given that the input signal is band limited and the self-oscillation frequency is sufficiently high. In both cases, to implement a practical decoder with digital logic running with a synchronous clock, the PWM signal must be sampled first. The decoder performs the Time-toDigital-Conversion, i.e. measures the pulse width within a discrete set of values, thereby introducing a time-quantization noise. For this reason, the resolution of a TE-ADC built with this principle is directly proportional to the sampling frequency Fc, which determines the number of discrete-time values resolvable by the TDC (or, in turn, by the achievable time-resolution of the TDC when implemented with multiple-phases of the low-speed Fs clock). When used in combination with a CTSD, then it is convenient placing the TDC decoder within the SD loop, such

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a

Fs TDC Fc

u(t)

+

From Loop Filter

y(n)

–

T&H

Time Decoder

Sampler

Ramp Gen

To Main DAC

Time-Encoder

b

PWM sampled signal

TDC Fc

u(t) From Loop Filter

y(n)

+

–

H(s)

Time Decoder

Sampler Td Delay

Time-Encoder

To Main DAC

PWM sampled signal

Fig. 4.11 (a) Synchronous PWM, (b) Asynchronous PWM

that the time-quantization error gets shaped by the NTF of the Sigma Delta itself, allowing for easier implementation. Is worthwhile to mention that for asynchronous modulators, a perfect recovery algorithm also exists, although it is quite complicated [17] and would require a very sophisticated digital reconstruction filter.

4.2.1 Synchronous PWM CTSD – Case Studies One recent example of a Single-Bit Synchronous PWM Sigma-Delta ADC is given in [24, 26, 29] and the block diagram of such a system is given in Fig. 4.12. The CTSD modulator implements a third order feed-forward architecture, with an active-RC inv-chebyshev filter. An additional feedback loop realizes the ELD compensation by placing a high-frequency zero in the NTF [1]. The triangular waveform used in the PWM generator is realized by integrating the master clock square-wave with a simple active integrator (switched-current sources driving a capacitive load [24]). Double sampled PWM [16] is used to eliminate the harmonics of the input signal (minimize the distortion) as compared with single sampled PWM. The high-speed sampler working at 12.5 GHz does not exist as a unique block in the circuit, being this embedded in a compact time-to-digital converter. The TDC decoder is realized by using 50 different latches, each one triggered by a different phase of the master clock (Fs D 250 MHz), achieving an equivalent sampling of the

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Fs = 250 MHz

75

Fc = 12.5 GHz Single-Bit TE-ADC

Fs = 250 MHz

PWM-mod +

H(s) –

+

+ –

Time Decoder

–

Loop Filter

y(n) [50 lev @ 250MS / s]

Sampler TDC fbe pq(t) D/A 1

D/A 1

Fig. 4.12 The Synchronous PWM CTSD presented in [24]

PWM signal of 12.5 GHz. The re-sampled single-bit feedback signal is then sent back in the CTSD loop, using different DAC types for the two loops: • a differential-pair as the “main-DAC” for high PSRR requirement • a CMOS digital driver (connected to the supplies) as the “fbe-DAC” for power reduction The sensitivity to the jitter of the master-clock Fs of this converter is very low [24], since the TDC architecture generates a DAC pulse with one rise-edge and one fall-edge in each clock period Ts. The resulting waveform can be therefore considered a Return-to-Zero code with very low pulse-width jitter ı£2 and very high delay clock jitter ıtd 2 , resulting therefore quite robust [33]. The pulse-width jitter depends mainly on the size of the delay line used for the multi-phase clock generation: this implies that jitter sensitivity can be exchanged with area and power of the TDC. Increasing the size of the unity elements composing the delay line helps also to reduce the distortion due to static mismatch between them. The time-quantization noise generated in the TDC is similar to the amplitudequantization of the equivalent quantizer, but for the same sampling frequency Fs and for the same number of levels, the noise floor of the time-quantizer results higher (8 dB in this example); this is due to the aliasing of the high-frequency tones of the PWM continuous-time signal (harmonics of the free-running frequency and intermodulation products with the input signal) which are folded in band.

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A. Di Giandomenico et al. FFT Spectrum of pq(t)

FFT Spectrum of y(n)

0 NTF peak Magnitude (dBFs)

Magnitude (dBFs)

0 NTF peak

–20 –40 –60 –80

–20 –40 –60 –80

–100

–100 10

6

107

107

106

109

108

108

Frequency (Hz)

Frequency (Hz) Fs = 250 MHz Fc / 2 = 6.25 GHz

Fs / 2 = 125 MHz

SNR, SNDR (dB)

Limited DR

70 60 50 40 30 20 10 0 –10

SNR SNDR

–80

–60

–40

Amplitude (dBFs)

–20

0

Analog Bandwidth

20 MHz

Clock-Frequency Fc

12.5 GHz (equivalent)

Clock-Frequency Fs

250 MHz

Dynamic Range

68 dB

Peak-SNR

62 dB

Peak-SNDR

60 dB

Total Power

10.5 mW @ 1.2 V

Technology

CMOS 65 nm

Fig. 4.13 Some measurement results of the Synchronous PWM CTSD presented in [24]

Figure 4.13 shows some measurement results, where the FFT of the signal before decoding and after decoding are shown. The FFT plot of the PWM signal pq(t) clearly shows a high out-of-band (OOB) energy due to the oscillation tone and its multiples. The NTF-peak contributes to the OOB power which is sent back into the loop-filter and reveals a design closed to the instability margin, despite the help of the compensation fbe-DAC. The OOB high-energy constrains the first Op-Amp of the loop filter to have a high gain-bandwidth product and limits also the dynamic range of the modulator, as it can be seen in the SNR versus input amplitude plot.

4.2.2 Single-Bit Asynchronous PWM CTSD – Case Studies When the asynchronous Time-Encoding ADC shown in Fig. 4.11b is embedded into a CT Sigma-Delta converter, the resulting structure is shown in Fig. 4.14a. The architecture can be further improved, by moving the sampler inside the PWM loop (see Fig. 4.14b) and then by moving the PWM-filter H(s) in the feedback path (see Fig. 4.14c), realizing in this way a Single-Bit Time-Encoding-Quantizer (TEQ, [25]). Due to the nature of the limit-cycle generated by the asynchronous modulation (it is not constant, but depends on amplitude and frequency of the input signal), the exact time-decoder filter would require a very high hardware complexity [17,

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a

77

Fc v(t)

x(t) +

–

w(t) +

Hsd(s)

–

p(m)

Time Decoder

H(s)

y(n)

Sampler Td PWM sampled signal

Delay

Time-Encoder u(t) D/A

b

Fc w(t)

v(t)

x(t) +

+

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–

–

p(m)

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H(s)

y(n)

Sampler u(t) Td

D/A

Delay

Time-Encoder

c

Fc v(t)

x(t) +

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– u(t)

Loop-2

w(t) +

p(m)

u(m) H(z)

– Loop-1 H(s)

Sampler p(t) D/A

Time-Encoding-Quantizer

Td Delay

Equalizer

y(m) S(z)

y(n) ROSR

Oscillation Removal (Sync) Time-Decoder

Fig. 4.14 The Asynchronous PWM CTSD architecture

19]. Instead, a simple time-decoder can be built as a cascade of an equalization filter H(z) – the digital equivalent of the PWM filter H(s) – and an oscillationremoval filter S(z) – a sync-filter is sufficient for the purpose – which decimates also the digital stream down to the equivalent sampling frequency Fs. Since this modified system present two loops, the dynamics of the signals involved depend on the design of the two filters H(s) and Hsd(s): by proper placement of poles and zeros, it can be guaranteed that at low-frequencies the outer loop (Loop-2 in Fig. 4.14c) dominates, while at high-frequencies the inner PWM-loop (Loop-1 in Fig. 4.14c) becomes dominant. By doing so, one can virtually split the feedback signal path in a way that most of the OOB energy circulates mainly in the inner loop (providing the oscillation at the limit-cycle) and that most of the in-band power circulates in the outer loop (giving to the SD the optimal signal to be cancelled on the input adder). As a result, this modified architecture presents multiple advantages: • Since the PWM filter H(s) has usually a high-frequency low-pass characteristic (can be also a high-frequency integrator), it attenuates the high OOB energy of the signal p(t), it helps to increase the dynamic range of the CTSD modulator, as more dynamic is then available in the loop filter Hsd(s) for the input signal x(t). • As the inner loop (Loop-1 in Fig. 4.14c) provides already a first order shaping to the time-quantization error of the sampler in the TEQ, the intrinsic SNR of the TEQ stand-alone is increased (also thanks to the high OSR). • If the clock Fc is affected by jitter, then the jitter-error-signal at the output of the D/A (which is a stream of very narrow pulses produced every time p(t) changes

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+

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+– – +

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FFT plot of feedback signals in Loop-2 Fc

+

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–60 –80 –100 –120

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D/A

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6

10

7

10

8

10

9

Freq (Hz.)

Fig. 4.15 The Asynchronous PWM CTSD presented in [30]

polarity and which has a high OOB frequency content) is also attenuated by the low-pass filter H(s) before it’s subtracted from the input signal x(t); this clearly reduces the jitter sensitivity of the modulator. As the derivation of the limit-cycle frequency is not easy, the design methodology of such converters is more complex and has been in details explained in [19, 25]. In short, three important parameters must be determined, to make the PWM-based oversampled converter shown in Fig. 4.15c equivalent to the standard CTSD shown in Fig. 4.8a: 1. PWM loop gain: although the oscillation can be easily guaranteed at rest, the dynamics of the loop may be perturbed when an input signal v(t) is applied to the TEQ. The filtered signal u(t) can be considered to be a triangular signal, if the filter H(s) is an integrator or a low-pass filter with very low cut-off frequency as compared to the limit-cycle frequency. When the slope of the input signal v(t) becomes comparable with the slope of the ramp-signal u(t), then the oscillation could be lost, leading the modulator into overload condition. To avoid that this occurs, a sufficiently high gain kg must be chosen in the feedback DAC of the inner loop. The minimum value of the gain kg depends mainly onto the ratio between the oscillation tone ¨O and the maximum input frequency and amplitude, ¨B and A [19] (the maximum amplitude A can be seen also as the full-scale input voltage of the Time-Encoded-Quantizer shownin Fig. 4.14c):

4 Oversampling Converters Beyond Continuous-Time Sigma-Delta... Table 4.1 System parameters of the PWM CTSD presented in [30]

79

Parameter

Value

Analog BW CTSD OSR/Fs Kg COSR/Fosc ROSR/Fc TEQ resolution

20 MHz 16/640 MHz 6.7 0.5/320 MHz 8/2.56 GHz 4.7 bits

ˇ  ˇ ˇ  ˇ ˇ ˇ ˇ ˇ j !S ˇ  ˇH j !S ˇ kg  A  j1 C H.j !B /j  jH.j !O /j D A  ˇˇ1 C H ˇ ˇ 2  OSR COSR ˇ (4.6) 2. Relation between ¨S and ¨O : due to the sampling error, the time when the digitized signal p(m) changes polarity will be always delayed as compared to its analog representation w(t). This introduces a time-varying delay which, in average, will be always smaller that TO (the oscillation period itself). Since this delay may cause the sigma-delta loop to become unstable, it must be kept always below the maximum tolerable excess loop delay EMAX (expressed as a portion of the sampling period Ts). As a rule of thumb, one can assume that the oscillation period must be always smaller than twice the maximum tolerable ELD [19], yielding to: COSR D

!O TS 1 > D !S 2  .EMAX /  TS 2  EMAX

(4.7)

3. Relation between the quantizer resolution and the sampler frequency Fc: the time-quantization error introduced by the uniform sampler can be reduced by increasing the sampling frequency Fc. The minimum value of the Ratio-Oversampling-Ratio (ROSR) required to obtain an error lower than the quantization error of an equivalent classical amplitude quantizer with N LEV levels can be estimated to be [19]: ROSRmin D

!C 2NLEV > 2P  !O kg

(4.8)

Where P is the amplitude of the PWM signal before quantization (usually it’s 1). Once these three parameters are computed, the Single-Bit Time-EncodedQuantizer (TEQ) is ready for integration into a CT Sigma-Delta converter. Many designs have been proposed to implement system in Fig. 4.14c [25, 27] and the most efficient one, presented in [30], is described in Fig. 4.15. The most important system parameters are listed in Table 4.1.

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FFT Spectrum of p(m) for a big signal

0

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NTF not peaking

Limit Cycle moving

–20 PSD [dBFS]

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70 SNR SNDR

SNR/SNDR [dB]

60 50 40 30 20 10 0 –70

–60

–50 –40 –30 –20 Relative input leve [dBFS]

–10

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20 MHz

Clock-Frequency Fc

2.56 GHz

Clock-Frequency Fs Dynamic Range

640 MHz (equivalent) 63 dB

Peak-SNR

63 dB

Peak-SNDR Total Power Technology

61 dB 7.0 mW @ 1.0 V CMOS 65 nm

Fig. 4.16 Some measurement results of the Asynchronous PWM CTSD presented in [30]

The loop filter realizes a multiple feed-forward architecture where the last integrator is used also as capacitive adder of all state-variables. The two feedback loops are split for a different optimization of the D/A converters: • DAC1 in the inner loop: uses as reference voltages the supply rails, with more noise and more gain • DAC2 in the outer loop: uses low-noise reference buffers The analog filters in the feedback path are realized with a passive implementation, boosting the efficiency of the overall modulator. A programmable high frequency pole is used in the filter H1(s) of the inner loop to tune the limit-cycle frequency over process deviation. A low-frequency pole is used in the filter H2(s) of the outer loop to dump the OOB energy in the loop filter, enhancing in this way the Dynamic Range of the modulator. Figure 4.16 shows some measurement results, where the FFT of the singlebit output is compared for different values of the input amplitude. It can be seen that the peak of the limit-cycle (and its harmonics) is very dominant for lowamplitudes, while it becomes more flattened (and moves to lower frequency) for higher values. The NTF does not peak significantly, revealing a robust design with enough stability-margin, despite there’s no use of any ELD compensation technique.

4 Oversampling Converters Beyond Continuous-Time Sigma-Delta...

a

81

Fc v(t)

x(t) +

–

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w(t) +

u(m)

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Loop-1

u(t)

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b p ( t)

α

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Fc Loop-1

w (t) +

–

a1/s

+

–

a1/s

+

–

–d

a1/s

z

Fs

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Time Decoder

y(n)

Edge detect

u(m)

–1

z

1–z

–1

Digital Integrator

Fig. 4.17 A multi-bit Asynchronous PWM CTSD architecture proposed in [17]

The OOB high-energy is attenuated by the filter H2(s) (see Fig. 4.15); hence the design of the first Op-Amp of the loop filter is more relaxed and the dynamic range of the modulator is extended, as it can be seen in the SNR versus input amplitude plot.

4.2.3 Towards Multi-Bit Asynchronous PWM CTSD If the clock speed is already at the edge of the technology, getting more resolution from the Asynchronous PWM CTSD converters can be achieved by increasing the number of levels of the time-encoding quantizer [19] as shown in Fig. 4.17a. This can be accomplished by moving the Equalization filter H(z) inside the outer loop (Loop-2) which will act as the previous analog filter H(s) for the outer loop. The two loops are now independent one from each other, being the inner one still realized with Single-Bit D/A converter. The design procedure of such a converter is the same as the one described in the next section. If the parameter ROSR has been chosen to be the minimum, according to (4.8), then the number of levels for the multi-bit DAC in Loop-2 will be the same as the levels of the quantizer of the equivalent standard CTSD system:  NDAC2 D log2

kg  ROSR 2

 (4.9)

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One interesting design example is also presented in [19] (see Fig. 4.17b), presenting the following characteristics: • The equalizer H(z) is realized with an integrator, which can be implemented as an up/down counter running with the high-frequency clock Fc (the same as the comparator) • The sampling and interpolation operations can be implemented with a row of two M-bit registers running at the low-speed clock Fs • One DEM module might be needed before the multi-bit DAC, in case its static non-linearity does not meet the distortion requirement • The last integrator of the loop-filter can be reused also within the inner loop, to realize the pulse-width modulation If the implementation of the digital integrator is unfeasible due the tough latency requirement (to meet the maximum ELD target), then a hybrid solution has been also proposed, by combining the digital filter in the feedback with the D/A converter, employing a single-bit FIR-DAC [23].

4.3 VCO-Based CTSD ADCs Time encoders using a VCO can also be used to directly implement an ADC. Its principle relies in a very simple fact. If we periodically sample the number of complete cycles of an oscillator that fit within a given sampling time, we will have an estimate of the frequency of the oscillator. Due to the fact that the phase state of the oscillator may not be an integer number of periods within the sampling period, the phase error is accumulated for the next estimation, which results in a first order noise shaping of the quantization error. To implement a data converter we only need to control the oscillator frequency by a voltage such that input voltage maps directly into a digital code. Strictly speaking, such data converter is not a sigma delta modulator, because there is no feedback loop. Instead, is may be seen as a quantizer whose quantization noise exhibits noise shaping. An in depth mathematical analysis of VCO based ADCs can be found for example in [34]. Figure 4.18a shows the basic building block of a VCO based ADC, where the input is directly connected with the VCO frequency control input. The VCO signal clocks a digital counter that is dumped and reset periodically at a sampling frequency fs . This scheme can be refined by using several of the intermediate phases of a VCO implemented with a ring oscillator. The system of Fig. 4.18a produces first-order shaped quantization noise only, and as a consequence, it requires oversampling to achieve a sufficient SNR. As there is no feedback loop, all distortion components introduced in the VCO are coupled to the output. For this reason, the system of Fig. 4.18 can only be used for limited resolutions, although it permits achieving a remarkable FoM and low area. For instance, [35] shows an exemplary circuit implemented with digital inverters which exhibits very low area and FoM, but whose linearity is strongly limited by the VCO.

4 Oversampling Converters Beyond Continuous-Time Sigma-Delta...

a

fs

VCO Input signal

reset COUNTER

Clk LATCH

Digital out

fs

b

Digital out VCO

Input signal

83

reset

Clk

COUNTER

LATCH

Look-up Table

Fig. 4.18 A VCO based oversampling converter

Calibration has been proposed as an option to improve the linearity. In this case, the ADC core resorts to the building block of Fig. 4.18b and first order is maintained. However, the output data is linearized by use of a look up table after the counter. The look up table contents is calculated at power up by a calibration system which may require dedicated calibration hardware. In [37] this approach is employed to achieve a low FoM and very small size converter. Although this approach can be very adequate for low resolution ADCs (below 11-bits), increasing the resolution above that value by means of calibration seems not so efficient. Moreover, concerns have been raised about the possibility of maintaining the calibration with power supply and temperature variations. Apart from these two alternatives, some others have been developed [38], based in similar principles. VCO based oversampled converters have been there for more than 15 years [39], however, this topic cannot be considered already closed and more architectures based on oscillators will likely be seen in the future.

4.3.1 Sigma-Delta Employing VCO-Based ADCs VCO based ADC converters have been the subject of many research works for its promising advantages, namely simplicity and low power. However, the hardware cost of the proposed solutions to their inherent drawbacks has placed them as an option similar to the PWM based converters. Using the VCO as the quantizer of a higher order conventional continuous time sigma delta modulator is an approach which combines several advantages: • The order can be increased arbitrarily; it’s just a matter of increasing the complexity of the analog filter. Moreover, one needs one integrator less than the modulator order, because the VCO already provides first order noise shaping

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fs

Analog input Hsd

ring oscillator

register

1–z–1

Digital multibit output

ΦN 5b DAC Analog feedback

Fig. 4.19 A VCO as time quantizer of a CT-SDM [33]

• If the VCO is implemented with a particular ring oscillator topology, the feedback DAC may incorporate a Data Weighted Averaging (DWA) effect without the need of a dedicated DWA hardware. Finally, VCO nonlinearity is spectrally shaped by the analog loop filter. In [36], a polyphase VCO is implemented using a ring oscillator as shown in Fig. 4.19. Each output phase, (ˆ0 : : : ˆN) is sampled in a register by a flip-flop and thus, time quantized with a single bit. This way, a multilevel code is generated. After a digital differentiator, this code is both used as digital output and to drive a conventional unit element current-DAC. The rotating effect of the ring oscillator eases the equiprobable use of the DAC elements, resulting in a built-in DWA kind of nonlinearity compensation. In spite of all these advantages, one still needs high performance analog integrators and a multi-bit D/A converter which end up in a real improvement over a standard continuous time sigma delta but with similar limitations, especially the linearity of the first integrator, which dominates the overall performance.

5 Conclusions As many other research topics with an industrial application, Sigma Delta converters have been a fashion item that many semiconductor companies wanted to display in its portfolio. Recently its effectiveness has been questioned in favor of classical Nyquist architectures such as SAR and pipeline converters. As a difference to Nyquist ADC architectures, they have been surrounded by a myth of complicated mathematics and connections with chaos theory and other exotic disciplines. While this is true, their design resorts to a deep analog circuit design knowledge (same a Nyquist converters) combined with a clear understanding of classical linear systems and filter theory (same as the anti-aliasing filters that precede a Nyquist converter). In spite of these arguments, Sigma Delta converters are typically the solution in the industry “after” pipelines and SAR fail to deliver the power or performance that differences a product from its competitors.

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The historical steps taken in sigma delta converter evolution go from the ideal model of a sigma delta, embodied as a switched capacitor circuit to continuous time sigma deltas and lately to time encoding designs. This evolution has been forced by starvation of analog performance as feature sizes decreased. The way to exploit the extra digital MHz allowed by shrinking technologies could not come from higher bandwidth opamps or better matched current sources. Hence, researchers have been forced to dig a bit more in unconventional engineering knowledge. Time encoding techniques will represent in the near future one of the main escapes to this low performance of analog electronics associated with nanometer CMOS. The attempts to implement time encoding converters with direct sampling in 65 nm and 45 nm have shown to date that the paradigm of excellence of digital versus analog circuitry is still not enough accomplished. High order continuous time Sigma delta converters implemented with time encoded quantizers [30], VCOs [36] are bridging the gap momentarily, but still require high performance operational amplifiers. It can be envisioned that a definitive solution must benefit from the advantages of time encoding in the whole analog signal processing chain, and not only at the quantizer. This way, time encoding could be applied to filtering, amplification and other building blocks made mostly of digital logic but realizing analog operations. Opamps and integrators implemented with charge pumps and logic inverters [40] are one of the early examples of the changes that will arrive. Other uses of time encoding to implement analog to digital conversion are a mix of traditional frequency synthesis techniques with VCO oversampled converters [41, 42]. A classical time encoding converter was the dual slope ADC. In [43, 44], it is shown how to implement a multi-bit oversampled converter using the dual slope principle by means of time encoding. Continuous time digital signal processing [45] shows that the real barrier is not the speed and performance of CMOS technology but the way engineers see real world signals and signal processing, linked to the classical theory of sampled data systems with a fixed sampling rate.

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40. L. Brooks, H.-S. Lee, A zero-crossing-based 8b 200MS/s pipelined ADC, in IEEE International Solid-State Circuits Conference, 2007, ISSCC 2007, San Francisco, 11–15 Feb 2007, pp. 460–615 41. L. Hernandez, E. Prefasi, Continuous time † modulator based on digital delay loop and time quantisation. Electron. Lett. 46(25), 1655–1656 (2010) 42. B. Young, P.K. Hanumolu, Phase-locked loop based -† ADC. Electron. Lett. 46(6), 403–404 (2010) 43. E. Prefasi, E. Pun, L. Hernandez, S. Paton, Second-order multi-bit † ADC using a pulsewidth modulated DAC and an integrating quantizer, in 16th IEEE International Conference on Electronics, Circuits, and Systems, 2009. ICECS 2009, Hammamet, 13–16 Dec 2009, pp. 37–40 44. L. Hernandez, E. Pun, E. Prefasi, S. Paton, Continuous time sigma-delta modulator based on binary weighted charge balance. Electron. Lett. 45(9), 458–460 (2009) 45. M. Kurchuk, Y. Tsividis, Signal-dependent variable-resolution clockless A/D conversion with application to continuous-time digital signal processing. IEEE Trans. Circuits Syst. I Regul. Pap. 57(5), 982–991 (2010) 46. A.M. Soliman, M. Ismail, Phase correction in two-integrator loop-filters using a single compensating resistor. Electron Lett 14(12), 375–376 (1978) 47. S. Paton, T. P¨otscher, A. Di Giandomenico, K. Kolhaupt, L. Hernandez, A. Wiesbauer, M. Clara, R. Frutos, Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators, in Proceedings of the Custom Integrated Circuits Conference (CICC), San Jose, IEEE, 2004

Chapter 5

Considerations for Cost-Efficient Calibration of Scaled ADCs Marian Verhelst, Erkan Alpman, and Hasnain Lakdawala

Abstract Observed ADC area and power scaling do not seem to follow the trends predicted using pure technology scaling arguments. A cubic improvement in area and power with gate length is observed in literature, which has been enabled by migration towards more and more capacitor-based ADC architectures, and the introduction of digitally-assisted performance enhancement strategies to overcome component mismatch. This paper assesses these trends, and discusses the most relevant enhancement strategies for mismatch-limited ADCs. Trade-off analysis between mismatch compensation in the analog domain (digitally assisted trimming, possibly in combination with up-scaling) vs. the digital domain (digital postdistortion) is required. The increasing use of digitally enhanced ADC architectures proves to be the main driver for the observed improvement in area and power with scaling.

1 Introduction The need for increased mobility and portability of computing devices and ever increasing data rate requirements puts more and more stress on the ADC’s performance. At the same time cost and battery life issues demand continuous scaling of the ADC area and power consumption and require designs in smaller and smaller (CMOS) technologies. Furthermore increased dynamic range required for modern communication standards also pushes the required dynamic range of the ADCs with scaling. This causes significant noise and matching issues in several key ADC building blocks, as traditional scaling studies predict a power and area flattening or even increase.Nevertheless, a survey of published data indicates that

M. Verhelst () • E. Alpman • H. Lakdawala Intel Labs – Radio Integration Research, 2111 NW 25th Ave, Hillsboro, OR, USA e-mail: [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 5, © Springer ScienceCBusiness Media B.V. 2012

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ADC performance does improve significantly over technology. This contradiction is explained by new architecture and design innovations in ADC design that exploit the inherent improvements provided by CMOS technology scaling. These improvements include: 1. Metal finger capacitor (MFC) density as well as MFC matching per pF improved significantly over the last technology generations. 2. The speed of digital gates increases, while their power and area reduce. Analysis of performance enhancement techniques that exploit these advantages of scaling is necessary to understand the improved performance of ADC implementations and to extrapolate these learnings towards future scaled ADC designs. This paper starts by deriving the expected ADC area and power consumption trends from pure technology scaling in Sect. 2. Section 3 makes the comparison with observed trends from survey data on state-of-the-art ADCs of the last decade. Next, Sect. 4 focuses on several digital enhancement techniques to explain the inconsistency between the theoretical and observed trends. Section 5 finally derives the strategies to incorporate these calibrations in a cost-aware way into ADC design and illustrates this with a design example.

2 Theoretical Performance Trends in Scaled ADCs 2.1 ADC Performance Limiters Noise and distortion impose fundamental limits on ADC performance. Their impact on ADC area and power consumption has been covered extensively in literature [1–4]. This section summarizes these dependencies, which will be used in Sect. 2.2 to evaluate the impact of scaling. The conversion accuracy of ADCs is typically expressed in ENOB (effective number of bits), or SNDR (signal-to-noise-and-distortion power ratio): SNDR.dB/  1:76 ; 6:02

(5.1)

S Nnoise C Nmismatch C Nnonlin

(5.2)

ENOB D SNDR D Where:

S: signal power at the ADC input, or Vsig; rms 2 . Nnoise : input referred noise power. Noise appearing in the ADC output signal is caused by a combination of quantization noise, thermal noise, flicker noise and input sampling jitter. Quantization noise, caused by the finite resolution quantization intervals, sets the limit for the maximum achievable SNDR. Practical ADC designs

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are also limited by thermal noise, which can be characterized by the total integrated noise: Nnoise D

kB :T ; C

(5.3)

With kB the Boltzmann constant, temperature T and effective input referred noise capacitance C. Nmismatch : distortion due to mismatch. As shown in [2, 5] matching rather than thermal noise dictates the performance of low resolution ADCs. Mismatch of critical circuit elements has different effects depending on the ADC architecture. In Flash converters the random mismatch among the comparators’ (or pre-amplifiers’) offset degrades performance, while in a SAR ADCs, the comparator offset is un-important, but the sensitivity to capacitor (and hence radix) mismatch is large. Pipelined ADCs need carefully matched opamps and capacitors to maintain good ENOB, while finally time-interleaved ADCs heavily suffer from mismatch among gain, offset, skew or bandwidth of the time interleaved channels. This mismatch causes non-linear distortion, affecting dynamic and static ADC metrics, like SNDR, INL and DNL. The latter have to be reduced to a fraction of the LSB to avoid ADC performance degradation. One way to reduce circuit mismatch, is by increasing circuit area. This linear relationship is demonstrated in Eqs. 5.4 and 5.5 for amplifier differential offset voltage matching (Vgs ) [5–7], as well as capacitor matching (C ): # " A2ˇ  2 1 2 AVT C  .Vgs / D Vgs  VT W:L 4 2

 

2

C C

 D

A2C N  Cunit

(5.4)

(5.5)

with AVT t , Aˇ and AC technology constants, W.L the transistor area and N the unit capacitor multiplier. However, due to the deterministic nature of mismatch (unlike thermal noise), opportunities for smarter correction exist. They are the primary focus of this paper and will be covered extensively in Sect. 4. Nnon  lin : device non-linearity. The linearity of an ADC is further degraded by device non-linearity. A well know example of this is the input sampling stage, which

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a

b

VDD

VDD

vbias2

i2

vo1 vid1 / 2

iod1

W1, L1

–vid1 / 2

W1, L1

vo2 Cpassive1 vi2

W2, L2 (M2)

Cpassive2

IB1

Fig. 5.1 Representative circuit model of ADC input stage (a) and output stage (b)

is affected due to charge injection and a varying input resistance [8]. The input resistance Ron heavily depends on the sampled input voltage Vin : Ron D dV in =dI D

2 WL

1 Cox .Vin  VT /

(5.6)

To limit the non-linear distortion, the difference in Ron over the signal swing (Ron) has to be kept small. Assuming a transmission gate: max Ron D

2k  2 Vdd  VT Ronmax D D Vdd Ronmin k=2 1 . 2  VT /=2

(5.7)

This parameter however significantly degrades with process scaling, as the ratio k D Vdd=V th decreases rapidly with technology (trending < 2.5 for some low leakage <45 nm CMOS). Luckily, gain boosting and bootstrapping resolve most of this signal dependency, but at the cost of input bandwidth, area and power [9]. Again, due to the deterministic nature of the impairment, post-distortion techniques have proven to provide additional improvement [8]. Amplifying stages can also be a source of non-linear distortion. Although even order harmonics are typically cancelled out by employing differential circuits, odd order distortion does affect the ADC performance. For the differential pair of Fig. 5.1a, and assuming ideal square law devices, it can be shown that [10]: iod Dx IB

r 1

x2 ; 4

with x D

vid .Vgs1  VT /

(5.8)

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and hence by approximation: gm IB D 8:.Vgs1  VT /2 : Š8 gm3 2:Kn :W1 =L1

(5.9)

with gm being the transconductance, gm3 D ı 3 iod =ıVgs3 (third harmonic of the transconductance) and Kn D 2n Cox .

2.2 Fixed Performance ADC Scaling The noise and distortion formulae of previous section allow assessing the impact of scaling on ADC performance. More specifically this section derives trends in ADC area and power consumption with iso-performance technology scaling. Broader studies of scaling effects in analog and mixed signal circuits can be found in [6, 7, 11–14]. The circuits shown in Fig. 5.1 will be used as a representative circuit for an ADC input stage (Fig. 5.1a), respectively output stage (Fig. 5.1b), driving a passive capacitor Cpassive . These circuits are relevant for a multitude of recent ADCs based on open loop amplifiers and passive capacitors, like pipelined, sigma-delta or SAR ADCs. While noise and matching constraints mainly impact the input stage, device linearity has to be addressed for both input- and output stage. Throughout this study, following assumptions are made: • The square law MOSFET model is used, with the understanding that short channel effects limit the accuracy of this model in scaled technologies. However this assumption allows a first order calculation to reveal trends. • L scales with technology. Design rules of deep submicron technologies do not allow long channel devices without severe area and leakage penalties. The scaling factor of L per technology generation will be denoted sL (0.7). • Voltage scaling is pursued less aggressively in latest technology generations. Leakage concerns cause the threshold voltage to be almost flat. As a result VDD scales at a slower pace to keep sufficient voltage overdrive. Therefore, a voltage scaling factor sV , different from sL , is used. Recently this factor has been trending p towards sL or even less when different supply voltages are used for analog and digital blocks. • Gate tox , and as a result Cox has not been keeping up with feature scaling due to gate leakage concerns. Survey data [15] shows Cox scaling of 1=sL (towards 1=sL for high-k gate). Interconnect tox scales with 1=sL . • Absolute matching coefficients AVT and AC (Eqs. 5.4 and 5.5) improve with every new technology generation. Lately this improvement rate has been trending p around sL [15, 16]. Aˇ , which does not see similar improvements, has not been taken into account in this study, resulting in a slightly optimistic (smaller area, power) outcome.

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• A passive metal finger capacitor (MFC) capacitor is assumed. MFC capacitor density scales with technology as 1=sL [16]. • The input stage operates in Class A, or IB1 =iod1 D constant. This implies that .Vgs  VT / cannot scale faster than the input signal swing, or sV . • Iso-bandwidth (conversion rate) scaling is pursued in all scenarios (unless other iso-performance requirements force the bandwidth to be larger). This poses the following constraints for the representative circuits: Input stage: (linear settling): gm1 D constant Cload1

(5.10)

Output stage: (slew rate limited): Cload2 :.vo /max D constant i2

(5.11)

Table 5.1 shows the effect on the most important circuit parameters when scaling device length (sL ) and supply voltage (sV ) under different scenarios.

2.2.1 Iso-(device-)linearity Scaling In a first scenario, an iso-linearity scaling of the input stage is pursued, assuming a constant load capacitor Cpassive1 . Only the intrinsic non-linearity of the transistor device is considered. Non-linearity due to mismatch will be covered later (isomatching). As can be derived from Eq. 5.9, this linearity is maintained as long as the overdrive voltage Vov D .Vgs1  VT / scales proportional to vid . This is realized by scaling both voltages with sV , resulting in a device width scaling: W 

I L Cox  .Vgs  VT /2



p sI  sL : sL : sV 2

(5.12)

Iso-(device-)linearity scaling of the output driver stage (Fig. 5.1b) requires both .Vgs  VT / of M2, as well as the voltage drop over the output stage bias transistor to scale with sV . Assuming constant bandwidth, bias current can be decreased according to Eq. 5.11. As a result, iso-linearity enforces similar scaling to the output driver stages as derived for the input stage (Eq. 5.12). As can be seen from Table 5.1, iso-(device-)linearity scaling (without other noise or matching requirements) results in an almost perfect scaling with technology, p where both area and power scale down with a factor sL to sL 2 (using sV  sL ). From this observation, linearity does not seem to be affected by scaling if the input swing range is allowed to be reduced with the input supply, predicting ever

sL sV sV 1 sV sL 3=2  sV 1 sV 2 sL sL 5=2  sV 1 sL2 sL p Green formulaeassuming sV  sL

L Vdd (vo ), (vi )max Cpassive I W Power Area (active) Area (passives)

sL sV sV sV 2 sV 1 sL 3=2  sV 3 1 sL 5=2  sV 3 sL sL  sV 2 1

sL sV sV sL sL 3=2 .passive load/ sV 2 .offset/ sL 3=2  sV sL1 sL  sV 2 1 sL 2

sL sV sV sV 2 .noise/ sL 3=2 .linearity/ sV 2 .matching/ sL 3=2  sV sL1 sL  sV 2 1 sL  sV 2 1

Table 5.1 Effect on design parameters, area and power consumption of the input stage reference circuit of Fig. 5.1a under iso-performance scaling Parameter Iso-linearity Iso-noise Iso-matching Iso-SNDR

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decreasing area and power numbers for scaled technologies. However, system, noise and matching requirements will make it harder and harder to scale the input swing with sV , which will be reflected in an area and power penalty as seen in the following scenarios. 2.2.2 Iso-thermal Noise Scaling To keep the signal-to-thermal-noise-ratio constant in a scaled technology, assuming the input swing scales proportional to the supply, circuit noise has to be suppressed with sV 2 . As a result, the passive capacitive load Cpassive has to be scaled up with the same factor. To account for the larger gm requirement due to this load under iso-bandwidth constraints and only allowing limited overdrive voltage scaling to maintain Class-A operation, this requires approximately flat device width scaling. Table 5.1 shows the impact on area and power consumption. It has to be noted that flicker noise, important for low frequency ADC designs has been neglected here. Flicker noise limited designs can use architectural solutions like correlated double sampling or need to keep input device sizes large to limit the flicker noise. 2.2.3 Iso-matching Scaling In an iso-matching scenario the amount with which active and passive circuits can scale is limited, and directly tied to the improvement over technology of AVT and AC (Eqs. 5.4 and 5.5). Additionally, the scaled supply voltage and input swing increases the threshold voltage matching requirement for the active devices with sV . The decrease in required gm (smaller load) does however not allow significant power savings due to the Class A operating requirement. The design is no longer iso-bandwidth, but is forced to increase bandwidth with ‘sL 3 ’ at a larger power cost. As shown in Table 5.1, area is flat for active devices, passive area decreases due to improved capacitor density and matching. Note that a purely passive load is assumed. An active load (with matching requirements, like in current steering DACs, or CT † ADCs) scales slower, 3=2 resulting in a 1=sL times higher power consumption. 2.2.4 Iso-SNDR A good ADC implementation will always use all excess margin in terms of every performance limiter: device non-linearity, noise and matching. As result, when such a design has to scale down, performance across all three has to be improved simultaneously. The last column in Table 5.1 shows the result on the circuit’s area and power consumption for such an iso-SNDR scaling (iso-linearity C iso-noise C iso-matching). The size of the passives will typically be determined by

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noise, and of the actives in many designs (e.g. flash) by threshold voltage matching, while the current is set based on the linearity constraint of Eqs. 5.9, taking the p increased W due to matching into account. Assuming sV  sL , this scenario results in iso-bandwidth scaling as well.

2.3 Conclusion An interesting observation from Table 5.1 is the difference in scaling between active and passive devices. While active devices seem to suffer less from scaling in a noise-limited scenario, passive devices scale better under matching constraints. This relates to the ongoing shift of ADC designs towards oversampling implementations (relying more on active devices) for noise limited designs, while more passive capacitor based designs (like SAR ADCs) gain popularity for low SNDR requirements (matching limited [17]). However, as can be concluded from Table 5.1, no significant overall area or power improvements can be expected from pure technology scaling alone under fixed performance constraints. The ADC area and power seems solely dependent on and tied to its SNDR requirement. Due to the p slowed down voltage scaling sV 6 sL both are more or less flat, or slightly increasing over generations. If sV would have maintained his old trend sL , power would have scaled better at the cost of additional area. The increasingly common trend of using of dual supplies for the ADC, with the analog supply being higher and scaling slower than the digital supply helps in terms of area scaling. Next section will compare these trends with survey data from recent ADC implementations.

3 ADC Area and Power Survey Based on the survey data from [18] an assessment can be made about the actual trend of area and power consumption of iso-SNDR ADC implementations over the past decade. The power consumption scaling per calendar year is studied extensively in [17]. The study reveals a significant scaling divergence between high SNDR ADCs (>75 dB SNDR), limited by thermal noise (technology), and lower SNDR ADCs, which are mismatch limited. The remainder of this paper will focus on trends for mismatch limited ADCs, as they contain the majority of recent ADC designs. This section will investigate the trend in area scaling, as well as quantify the area and power scaling over technology generations. Figure 5.2 shows an analysis of all ADC implementations presented at the IEEE International Solid-State Circuits Conference (ISSCC) and the VLSI Circuit Symposium during the last decade [18]. In this plot, the area efficiency (area divided by the Nyquist sampling rate fnyquist ) is plotted in function of the achieved SNDR.

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ISSCC, VLSI data 10–4

2000-2001 2010

area / fnyquist [mm2 / Hz]

fit all fit 2000-2001

10–6

fit 2010

10–8

10–10

10–12 20

40

60 SNDR [dB]

80

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Fig. 5.2 ADC performance data (ISSCC 2000–2010, VLSI Circuit Symposium 2000–2010). Area efficiency plotted in function of SNDR

The oldest (2000–2001) and most recent (2010) implementations are highlighted. A first observation is the large spread of the data around their best linear fit, which can be explained by different performance metrics targeted by the various ADC designs, not all reflected in this drawing: area, power, bandwidth, or a combination of them. However, due to the abundance of data, interesting conclusions can still be drawn from averaged data through linear regression models. Figure 5.2 shows linear fits constructed based on all mismatch limited ADCs (SNDR < 75 dB) of different publication years. Based on these lines, a clear improvement of area efficiency from 2000 to 2010 can be identified. This trend is also observed in three generations of similar sigma-delta ADCs at Intel in scaled technologies (Fig. 5.3) [19]. This observation is contradictory to the theoretical area scaling effect derived in previous section. One partial explanation is a shift toward passive capacitor-based ADC designs, which rely on passive, rather than active device matching. As shown in Table 5.1, these devices still scale quite well over technology. Figure 5.4 confirms this trend: The fraction of SAR ADC implementations significantly increased over the past years. Also, sigma-delta (SD) and pipeline ADCs, relying heavily on passive capacitors as well, remain popular.

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MASH 2-2 90 nm CMOS 1X

99

MASH 2-0 45 nm CMOS ~ 0.2X

MASH 2-2-0 32 nm CMOS ~ 0.1X

Fig. 5.3 Three generations of similar delta-sigma ADC implementations, demonstrating the ongoing area improvement over technology generations

1

other SAR SD(SC+CT) flash pipeline

fraction of ISSCC +VLSI paper

0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 year

Fig. 5.4 Fraction of ADC architectures published in ISSCC and VLSI in different calendar years

However, as derived in Table 5.1, this design shift can only (partially) explain an improvement in area efficiency. Improvements in power efficiency (power consumption divided by the Nyquist sampling rate fnyquist ) are not expected from the scaling study of Sect. 2. Figure 5.5 however shows that the power efficiency of ADC designs demonstrates a similar decrease over the last decade. This scatter plot visualizes the power versus area FOM (figure-of-merit): power FOM D

P ; fnyquist :2ENOB

area FOM D

A fnyquist :2ENOB

(5.13)

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power FOM

10–11

2000-2001 2010

10–12

10–13

10–14

10–15 10–14

10–12

10–10 area FOM

10–8

10–6

Fig. 5.5 Power figure-of-merit vs. area figure-of-merit (FOM)

The scattered data can again be attributed to different design optimization metrics pursued. A clear power-area trade-off locus can be observed, which steadily improves over the years for both area and power. A similar trend can be observed when computing the expected area and power consumption of a iso-SNDR ADC in different technology generations: Based on a linear fit of both area and power in function of SNDR over the ISSCC/VLSI survey data for every different CMOS technology generation between 600 and 65 nm (not enough data points available for 45 nm), the area and power consumption of a typical comms ADC, targeting 60 dB SNDR, is predicted. Figure 5.6 plots the result: a perfect scaling with sL 2 for both metrics : : : To understand why this perfect scaling with technology is possible, despite the contradictory theoretical derivation of Table 5.1, let’s look at two interesting data points in Fig. 5.5: the most power efficient and most area efficient design up to date, indicated with the ‘stars’: The most power efficient ADC design, described in [20] is a 4.4fJ/conversion step charge redistribution (SAR) ADC, heavily relying on metal-plate capacitor matching. The most area efficient ADC design, described in [21] is a 0.01 mm2 flash ADC using minimum-size input devices in 65 nm. To compensate for resulting non-linearities and offsets in the comparator and track-and-hold, the ADC employs digital compensation techniques, both calibrated during startup.

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fitted area / fs, resp. power / fs for 60 dB ADC

100

10–1

10–2 mean area scaling mean power scaling scaling with L sL2 10–3

65

90

130

180

250 technology

350

500

650

Fig. 5.6 Predicted power consumption and area for 60 dB SNDR ADC over technology generation (normalized to the 650 nm data point (1 m2 /Hz, 9.5nW/Hz))

These two examples beautifully illustrate the two most important strategies followed in many of the ISSCC/VLSI survey designs to overcome mismatch limitations and maintain aggressive area and power scaling over technology: 1. Rely on metal-plate capacitor matching instead of device matching whenever possible (see also Fig. 5.4). 2. Add digital enhancements to the ADC to boost performance. Although a majority of the recent ISSCC/VLSI ADC implementations heavily relied on digital enhancements, only few of them demonstrated these in actual silicon. As a result, their true power and area cost is often not taken into account in the reported performance metrics. The remainder of this paper will focus on various digital enhancement strategies for ADCs, as well as quantify their benefits and penalties. This information helps the ADC designer to make smart design choices to optimize overall area and power of analog plus digital.

4 ADC Performance Through Digital Enhancements Designers have been using digital enhancements for many decades to boost the ADC performance at a reduced power/area cost compared to traditional up-scaling

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Fig. 5.7 (b–f) Enhancement techniques to improve matching performance over the minimum size, thermal noise-limited, baseline design (a)

[22, 23]. Analog power/area is saved, at the expense of more digital gates. Finding the best trade-off between the two is not straightforward and requires thorough understanding of the impact of these enhancements. This section will revise different digital enhancement techniques and their influence on both analog and digital performance metrics. This data can be used to understand the sL 2 scaling trends seen for ADC area and power consumption, and to investigate whether this trends is expected to continue in the future. A well-known and thoroughly studied digital enhancement technique for overcoming SNDR limitations for thermal noise limited ADCs is oversampling [24]. This section will therefore solely focus on enhancements for mismatch limited ADCs.

4.1 Non-digital Enhancements Figure 5.7 gives a classification of various strategies to improve matching performance of circuit components, and by extension of ADCs.

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The baseline, reference design which has to be improved is drawn in Fig. 5.7a. It consists of a set of N mismatched circuit components, which can be either active or passive devices, depending on the ADC under study. Example in a Flash ADC, these could be N pre-amplifiers which require careful voltage offset matching; While in a SAR ADC these could be N capacitors. In this reference design of Fig. 5.7a these N components have the minimal size required to meet the signal-to-thermal-noiseratio constraint (target SNDR). We denote this size as ‘1’. As shown in Table 5.2, such an ADC would consume a reference (D‘1’) analog area Aanalog and power Panalog , and does not need any digital area Adigital , power Pdigital or calibration time Tcal . Its performance is limited by mismatch, having a component variation of .a/ and the resulting SNDR is again normalized to ‘1’. A first way to improve matching between the fundamental circuit components of the reference design of Fig. 5.7a in a fixed silicon technology is by up-sizing the individual circuit components. Up-scaling every device area with a factor U, as shown in Fig. 5.7b improves the component matching and reduces their variance p with U (Eqs. 5.4 and 5.5). As a result, the ‘voltage accuracy’ improves by U , or an SNDR (power ratio) improvement of a factor ‘U’ is achieved at the cost of a ‘U’ times analog area and power increase (See Table 5.2). From the discussions earlier in this paper, it is clear that this is not the way mismatch and non-linearity are overcome in modern ADCs. The oldest calibration techniques to improve ADC matching and linearity are based on analog feedback (e.g. Opamps). Drawback of these analog feedback loops are however the requirement for the circuit to remain active during the whole circuit operation, as well as the very stringent gain-bandwidth (GBW) and linearity requirements for the feedback opamps and reproducibility and yield concerns. Designing under these requirements becomes problematic in scaled technologies and has a detrimental impact on system power consumption and area. This trend, together with the ever decreasing cost of digital gates over technology [2], pushes designers towards digital performance enhancements to improve performance will a smaller area/power penalty. Three techniques will be described: digitally assisted analog selection (including analog redundancy), digitally assisted analog trimming and digital post-distortion.

4.2 Analog Redundancy and Digitally Assisted Analog Selection A straightforward approach to avoid designing accurate analog components is to create analog redundancy, and average the outcome of the redundant, inaccurate (min-size) elements in the digital domain (shown in Fig. 5.7c) to enhance performance. This is e.g. used in Flash convertors to reduce sensitivity to offset voltage, by having several comparators evaluate the same input voltage and use their output in a voting mechanism [25]. By statistically averaging, the designer can get away with small devices.

Component trimming Digital postdistortion

1 C Z/2.ftrim (Š1 C 3. a ) 1 (e.g. 1.2)

Minimal (at startup) Significant (e.g. LUT)

1 1 C 6:a 1 (e.g. 1.2)

log2(Z) 0 (if ran in background)

Minimal Significant (e.g. LUT)

"" ,depends on impairment, f(an. redund., LUT size)

6. a /ftrim (DZ)

sL 2 ; sL 2 (Eq. (5.16)) sL 3=2 ; sL 2 (digital scaling)

Table p 5.2 Costs and SNDR improvement of enhancement techniques. Last column shows the effect of technology scaling on every enhanced ADC (assuming sV  sL ) SNDR (defined Technology Aanalog Adigital Panalog Pdigital Tcal by Eq. (5.2)) effect on (P ; A) Min size design 1 / 1 / 0 1 sL 1 ; 1 (Table 5.1) Upscaled U / U / 0 U sL 1 ; 1 (Table 5.1) design Analog X Small, log2(X) X Small, 0 X sL 1 ; 1 (Table 5.1) redundancy log2(X) erfcinv.erfc.3/1=Y / sL 1 ; 1 Component Y Minimal >1 Minimal Y 3 (Table 5.1) selection (at startup)

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Fig. 5.8 Area and SNR impact of different performance enhancement techniques, normalized to the thermal noise-sized design (1,0). Assumptions for baseline design: 7% mismatch, ftrim;min D 1/10, trimming overhead D 1/10

As shown in Table 5.2, increasing the number of redundant devices bypa factor of X, will only reduce equivalent device mismatch standard deviation by X , hence improving SNDR by X. A small area and power penalty in the digital domain is paid, to implement the averaging. As a result, analog redundancy shows a similar, or even slightly worse performance cost compared to classical up-scaling. Similarly, Fig. 5.8, which plots the SNDR improvement in function of area increase, shows an identical SNDR-area relationship for device up-scaling and analog redundancy, which both linearly reduce the component variation with increasing area (see distribution histograms in Fig. 5.8). Pure analog redundancy is hence not a good strategy to enhance ADC performance. It can however be extended with digitally assisted analog component selection, which is much more interesting [26]. This technique (Fig. 5.7d) aims at digitally selecting the best devices out of the pool of redundant analog components. It has been applied to Flash converters to reduce input offset voltages, where for an N- bit converter, all 2N comparator (Cpreamplifier) stages are replaced by Y identical copies of the same component. During a training phase, the best matching comparator (smallest offset) is selected out of every pool of Y comparators [26, 27]. This “selection step” reduces the variation of the remaining components much more effectively than adding redundancy. It can be derived that the 3:.d / spread

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(determining SNDR) after component selection in scheme (d) is reduced from the spread 3:.a/ of the reference design of scheme (a) as: 3:.d / D erfcinv .erfc.3/1=Y /:.a/

(5.14)

with erfc and erfcinv the (inverse) error function. The resulting “peaking” distribution is depicted in Fig. 5.8. Power savings are more significant, than area savings, since power is saved due to smartly shutting down the non-selected components. However, depending on how the non-selected components are gated, they might still load the input stage, resulting in some additional power consumption compared to the baseline design. The overhead of the off-line calibration required to implement this approach can have significant impact on the system and should not be neglected. Contrary to previous solutions (Fig. 5.7), calibration time (Tcal) will have to be foreseen in the manufacturing environment or when powering up the device to run the selection procedure. Depending on the configuration stability, this could however be a onetime tune-and-store process.

4.3 Digitally Assisted Analog Trimming While analog component selection allows reducing ADC power consumption for a fixed SNDR drastically, it does not come with a significant area breakthrough. Even more importantly though, as shown in the last column of Table 5.2: it does not allow to break with the traditional scaling laws presented in Table 5.1 and hence does not explain the observed scaling of Fig. 5.6. The enhanced designs (b)–(d) don’t scale any better than the reference case (a)! More interesting it is however to trim, instead of selecting components [28–30]. In component trimming (Fig. 5.7e), component variation is reduced by postmanufacturing inserting or removing small fractions of the component. A wellknown example is trimming capacitor values by connecting or disconnecting small capacitor to the main capacitor [30]. Similar trimming can be done to match current sources, gm, etc. [28, 29]. As shown in Fig. 5.8, this kind of trimming reduces the spread of the component drastically, since it cuts the tails of the component variation distribution. Both the amount of trimming steps Z, as well as the size of every trim step required depends on the original variation of the baseline device (.a/ 2 ) and the target SNDR. All trim steps together should cover the 6:.a/ spread of the original component. Or, defining ftrim as the fraction of the trim step size to the original component size: .Z C 1/:ftrim D 6:.a/

(5.15)

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Fundamental unit of digital trimming Vout Ctrim Corig Cp

select Rp

Fig. 5.9 Fundamental unit of digital trimming

The resulting SNDR will then show an improvement with approximately a factor Z (6:.a/ =ftrim ) over the baseline design. This of course comes at a small area cost due to the component selection switches and interconnect overhead. The power cost is often negligible, since the extra load of the switches can be incorporated in the design. Certainly the most important observation is that digitally controlled trimming decouples device sizing from the target SNDR, since it is tuned post-manufacturing to the required SNDR. As a result the area and power cost is nearly independent of SNDR, as seen in Fig. 5.8 by the steep increase in SNDR at almost no area cost. This would lead to the conclusion that minimum sized components (thermal noise limited) can in theory be used as trimmable devices. This however does not hold in practice due to two reasons: 1. The size of a trim component cannot be made arbitrarily small. Technology limits the trim step ftrim . As a result, the maximally achievable SNDR improvement for a design depends on the original mismatch 6:.a/ and the best achievable trim ratio ftrim . 2. The component selection area and power overhead is not negligible for close to minimum size devices. To assess this, let’s look into a representative circuit, which can be used as a “fundamental unit of digital trimming”: a digitally controlled switch, plus a passive element (Rtrim or Ctrim ) (Fig. 5.9). The overhead of using this passive element as a trim component are the parasitics of the switch, which load the component under trim, consume area and power and diminish the effect of the trim impact. In order to keep the overhead marginal and ensure a predictable impact of the trim, the value of the passive trim component should be significantly (e.g. 5X) larger than the parasitic of the switch.

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As a result, these switch parasitics (Cp or Rp ) determine the maximal achievable SNDR improvement and hence the sizing and power consumption of the original component under trim. Since switch parasitics, and hence ftrim;min  Cp ; Rp , heavily depend on technology, this directly links the design cost to achieve a certain SNDR to the silicon technology used. Parasitics are moreover characterized by following scaling rules [31]: Cp;switch  W:L  sL 2

(5.16)

Rp;switch  L=W  1

(5.17)

Interconnect parasitics follow different scaling rules [31]: Cp;interc 

W:L  sL ! .local interconnect/ tox

 1 ! .constant length interconnect/

(5.18)

Rp;interc  L=.W:H /  1=sL 1=2 ! .local interconnect/  1=sL 3=2 ! .constant length interconnect/

(5.19)

The relationship between ftrim;min and Cp together with Eq. 5.16 justifies a scaling of the ADC design cost (area and power) with sL 2 over technology: The intrinsic accuracy with which components can be trimmed in a certain technology improves by sL 2 , which does explain the observed trends of Sect. 3. This conclusion holds for C-based trimming, and as long as interconnect parasitics do not dominate. Since interconnect parasitics start to become more and more relevant relative to device parasitics, a slowdown of this area and power scaling trend is to be expected. It is also clear that R-based trimming is not favorable in advanced silicon technologies. Once the trimming accuracy limit of a certain technology is reached, the only way to increase SNDR further in the analog domain is to increase original device sizes. This up-scaling results in a relative decrease of ftrim . It however again has a linear effect on area and power consumption. An alternative to stick with minimal size devices is to increase SNDR in the digital domain by using digital post-distortion when technology prevents further trimming.

4.4 Digital Post-processing Due to the decreasing cost of digital gates over technology generations, digital postdistortion (Fig. 5.7f) to boost ADC performance becomes less and less costly [2]. A multitude of digital post-distortion techniques for ADCs have been developed and published over the past decade and are all very diverse in nature. The two most common, but very distinct, classes of digital post-processing are “look-up-table

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Table 5.3 Analog overhead required for digital impairment correction Impairment type Offset Gain error Radix mismatch (e.g. in SAR) Linearity correction

Required analog overhead ADC dynamic range C max offset ADC dynamic range * max gain error Use nominal radix <2, to ensure max radix 2. Typically radix Š 1.7 Ensure worst case DNL still within spec (smaller nominal DNL)

(LUT)”-based [32] and filter-based [8]. The former corrects analog impairments by using the bare ADC output as the index to a table look-up containing the corrected sample data. This approach is very straightforward and easy to implement, but only suitable for low SNDR (small number of bits) ADCs. It is also not well suited for on-line calibration. Filter based correction eliminates impairments by sending the bare ADC output data through a digital filter. The filter coefficients are adapted (on-line or offline) based on the detected actual ADC impairments. The type of filter required (linear vs. non-linear, order, length, etc.) is heavily dependent on the nature of the impairment(s) under correction. E.g. offset and gain mismatches between channels in a time interleaved ADC can simply be corrected with a linear, single-tap ‘filter’, while skew or non-linearity correction of the same ADC needs complex higher order implementations [8, 33]. These types of adaptive filters are especially attractive in medium to high SNDR ADCs, where LUT approaches become infeasible and where the cost of extra digital gates is relatively low compared to the analog power. Moreover, these filters lend themselves perfectly to on-line training and background adaptation, hence eliminating the need for (and cost of) startup calibration time Tcal , but only if initial settling transients are acceptable before achieving full performance. While very distinct in nature, digital post-distortion techniques have several key characteristics in common: They are all able of achieving very large SNDR improvements, and allow close-to-minimum size ADC front-end designs. Like in the case of digitally assisted trimming, this partly decouples component sizing, area and power requirements from the target SNDR, explaining the observed improvement over technology. However, unlike in the case of digitally assisted trimming, this comes at a significant (digital) area and power penalty. Additionally, a penalty in the analog domain has to be paid as well: Almost all forms of digital post-distortion require analog overhead to allow correction in the digital domain. This overhead is necessary to ensure that no unrecoverable information gets lost when digitizing the data. Table 5.3 lists the required overhead for common digitally corrected ADC impairments. The amount of analog overhead area and power consumption due to this depends on the (3- value of the) expected impairment, but can typically be estimated to be between 10% and 20%. It finally has to be noted that sometimes digital power and area are non-existent if leveraged from other DSP blocks already present in the system [34].

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5 Cost-Aware Calibration Design 5.1 Cost-Aware Enhancement Selection Previous section gave an overview of strategies for digital ADC enhancement. The effect of every strategy on the area, power consumption, the calibration time, as well as the SNDR was discussed. As shown, the various strategies improve component matching, which in its turn allows to scale down analog component sizes, and hence area and power consumption. However, often a penalty on either the digital area, power or the calibration time has to be paid. As a result, the selection of the optimal strategy for a particular ADC design is not straightforward. It requires a careful analysis of the expected analog savings due to the enhancement compared to its cost. Depending on the relative importance ˛ i of area vs. power vs. calibration time in the overall cost factor K of the particular design a different solution will be preferred. K D ˛1 :.Aanalog C Adigital / C ˛2 :.Panalog C Pdigital / C ˛3 :Tcal

(5.20)

Often a combination of different strategies offers the best trade-off. This “strategy selection/combination” problem can be treated as an optimization problem. Starting from a minimum sized design, without any enhancements, the overall cost factor K has to be minimized under an SNDR constraint by successively applying several enhancement strategies (Fig. 5.10). At every point in this optimization process, the enhancement strategy x with the highest SNDR vs. cost sensitivity SSNDR; K; x should be applied first until the target SNDR is achieved: SSNDR;K;x D

SNDR=x ; applying enhancement strategy x K=x

Fig. 5.10 Optimizing K under SNDR constraint by successively applying performance enhancement with largest sensitivity

(5.21)

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This sensitivity is a measure of the expected cost investment to achieve SNDR improvement with this strategy. As can be seen from Fig. 5.8 and Table 5.2, up-scaling and analog redundancy have and equal SNDR-cost sensitivity of ‘1’. Analog selection demonstrates a larger sensitivity, which is however still far off from the sensitivity of digitally assisted trimming, being 2/ftrim considering area cost and even larger when taking power cost into account. However, the benefit of this large SNDR sensitivity to trimming is only limited, since technology restricts achievable ftrim . When more SNDR improvement is needed, additional up-scaling can however be combined with trimming, resulting in a joint SNDR-cost sensitivity of: SupscaleCtrim

p p 6:.a/ = U =ftrim :U p  6:.a/ = U =ftrim .for large U / (5.22) D .U  1/ C 3.a/ = U

with .a/ and ftrim , resp. the component standard deviation and trim-ratio of the minimum size baseline design. This sensitivity decreases when U gets larger. The SNDR-cost sensitivity of digital post-distortion cannot be put into formulae that easily, as it heavily depends on the type (LUT vs. filter) and complexity of the implemented enhancement. Moreover, the sensitivity will in general be larger for complex, high resolution ADCs, since the area and cost adder will be relatively smaller compared to the overall ADC area and power consumption [2]. This sensitivity should be compared to the (decreasing) SupscaleCtrim , to determine at what point in the design it no longer makes sense to add additional trimming (in combination with up-scaling) and post-distortion should be deployed instead due to its larger sensitivity.

5.2 Practical Example: TI SAR ADC Calibrations In this section, the cost K of a time interleaved (TI) successive approximation (SAR) ADC will be optimized by applying different enhancement strategies. The performance of the 7-bit, 2.5 GHz 45 nm TI SAR ADC [35] (architecture in Fig. 5.11), is severely impacted by mismatch of the following parameters: • Capacitor values within every ADC: The linearity of a SAR ADC depends on the ADC’s capacitor ratios, which have to be equal to 2. • Offset and gain mismatch: Different (comparator) offset voltages and gains for the different TI channels also cause spurious tones. • Sampling skew mismatch between the different TI channels. 5.2.1 Capacitor Value Mismatch As depicted in Fig. 5.11, the SAR ADC under study does not rely on a binary weighted DAC, but uses a C-2C DAC instead [36]. This has the advantage that the

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Fig. 5.11 Architecture of the TI SAR ADC (* D parasitic capacitor)

DAC size only increases linearly with the resolution and small, fixed capacitor sizes can be used. However, a C-2C DAC suffers heavily from the parasitic capacitances at the intermediated nodes, which distort the capacitor ratios and can serve as a resolution limit [36]. The proposed SAR however incorporates these parasitic capacitors into the design: The ‘Cu /2’ capacitors in this design (Fig. 5.11) represent the total parasitic capacitances at the intermediate nodes but are also included as an integral part of the DAC [35]. Their nominal (parasitic) value is around 40 fF, which sets the limit of the minimum size design of this ADC, which is hence not thermal noise limited. The values of these parasitic capacitors will be severely mismatched and have to be corrected by calibration. When assessing the SNDR-cost sensitivity of both capacitor trimming and digital post-distortion, capacitor trimming is to be preferred here due to the achievable ftrim being: ftrim D

Ctrim D 0:125; 40f F

with Ctrim D 5:Cp;switch D 5fF in 45 nm CMOS design

(5.23)

As shown in Fig. 5.11, a slightly (2.2X) smaller effective ftrim can even be achieved by placing several trim capacitors in series. The trimming structure is able to compensate the range of 6. mismatch with a Z D 6, assuming a mismatch of  D 5% on the nominally 40 fF parasitic capacitors. The resulting measured performance improvement can be seen in Fig. 5.12.

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Fig. 5.12 INL improvement after capacitor trimming of individual SAR ADC

Fig. 5.13 Automated offset calibration loop in TI SAR ADCs [35]

The remaining capacitors ‘Cu ’ and ‘2Cu ’ are formed by metal finger capacitors (MFC). In the technology (45 nm LPCMOS ) used, their matching is more than sufficient to achieve 7-bit resolution without the need for additional calibration.

5.2.2 Offset and Gain Mismatch Once mismatch within the individual ADCs is calibrated, the mismatch across ADCs has to be addressed. In this design, an un-calibrated offset mismatch up to ˙85 mV is expected, while un-calibrated gain mismatch is typically limited to less than 5%. Both offset, as well as gain mismatches can easily be detected in the digital domain. Also the circuitry to correct for them does not require a lot of digital gates. However, due to the large offset mismatch (3- spread typically equals ˙85 mV D 34% of comparator input range) the analog cost adder of the required extra analog redundancy to allow digital post-distortion is very large. As a result, the SNDR-cost sensitivity of digital post-distortion will be poor for offset mismatch correction, while it is good for gain mismatch correction. As a result, the ADC gain is calibrated in the digital domain using a multiplier, while an automated offset calibration loop is implemented in the analog domain (Fig. 5.13).

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0 SNDR = 31.4 dB SFDR = 42.8 dB

–20

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Fig. 5.14 Performance of full ADC before (left) and after (right) TI channel mismatch correction

5.2.3 Sampling Skew Mismatch Sampling skew mismatch affects the maximum ADC performance by [37]:  SNRmax D 20 log

1 skew fsignal =fsample





 .M  1/ 2 4 dB  10 log M

(5.24)

with skew the sampling error standard deviation and M the number of time interleaved ADC channels. The original sampling skew mismatch in our design is estimated have a skew  1:5% of the sampling period. This sampling skew mismatch between different ADCs is much harder to detect than gain or offset mismatch, and has attracted a lot of attention from the research community. The most common estimation approach is a digitally implemented LMS optimization loop [33]. While implemented in the digital domain, the correction can both be executed digitally (digital post-distortion) or in the analog domain by using digitally assisted trimming. The required compensation step resolution is found from Eq. 5.24 to be about 0.2% of the total ADC sampling period, or 1 psec. Digital post-distortion involves the implementation of a time-varying fractional delay filter, often realized with a (poly-phase) Farrow filter [38]. The instantiation of this, typically at least 30-tap [33], digital filter comes with a large area and power penalty, as it is always on and runs at the full rate. The digitally assisted trimming counterpart consists of a digitally tuned delay line. This can be realized by cascaded inverters, loaded by a programmable capacitor bank (16 2.5 fF capacitors). Both the area (45 um2 /channel) and power cost (50uW/channel) of this are negligible on the total ADC design. The realized performance enhancement of the full TI SAR ADC under the described channel mismatch correction (offset, gain, timing) can be derived from Fig. 5.14.

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6 Conclusions Theoretical analysis of ADC scaling over technology predicts a flat to increasing trend on the ADC’s area and power consumption. A study over survey data of all published state-of-the-art ADC designs over the last decade however shows a cubic area and power improvement with technology gate length. The same survey data seems to indicate that this improvement is realized by heavily relying on capacitorbased ADC architectures, as well as by exploiting digitally assisted performance enhancement techniques. Several digitally assisted techniques to improve performance of mismatchlimited ADCs are evaluated. Digitally assisted trimming, as well as digital postdistortion do not only show the largest SNDR-cost sensitivity, but also demonstrate the same cubic improvement relationship with the technology gate length, which explains the observed ADC scaling. A practical design example is used to describe the ADC enhancement selection for different mismatch parameters. More work is required on system level techniques for fast, but low complexity background mismatch estimation techniques, to limit the calibration time penalty of both digitally assisted trimming and post-distortion.

References 1.P. Scholtens, D. Smola, M. Vertregt, Systematic power reduction and performance analysis of mismatch limited ADC designs, in Proceedings of ISPED, Bordeaux, Aug 2005, pp. 78–83 2.B. Murmann, Limits on ADC power dissipation, in Analog Circuit Design, ed. by A.H.M. van Roermund, H. Casier, M. Steyaert (Springer, Dordrecht, 2006), pp. 351–367 3. Y. Chiu, B. Nikolic, P.R. Gray, Scaling of analog-to-digital converters into ultra-deepsubmicron CMOS, in Proceedings of IEEE CICC, San Jose, 2005, pp. 375–382 4.K. Uyttenhove, M. Steyaert, Speed–power–accuracy tradeoff in high-speed CMOS ADCs. IEEE Trans. Circuits Syst. (CAS-II) 49(4), 280–287 (2002) 5. P. Kinget, M. Steyaert, Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits, in Proceedings of IEEE CICC, Rochester, 1988, pp. 333–336 6. M. Pelgrom, A. Duinmaijer, A. Welbers, Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24(5), 1433–1440 (1989) 7. P. Kinget, Device mismatch and tradeoffs in the design of analog circuits. IEEE J. Solid-State Circuits 40(6), 1212–1224 (2005) 8. P. Nikaeen, B. Murmann, Digital compensation of dynamic acquisition errors at the front-end of high-performance A/D converters. IEEE J. Sel. Top. Signal Process. 3(3), 499–508 (2009) 9. A. Abo, P. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits 34(4), 599–606 (1999) 10.K. Laker, W. Sansen, Design of Analog Integrated Circuits and Systems (McGraw-Hill, New York, 1994) 11. P. Woerlee, M. Knitel, R. van Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Zegersvan Duijnhoven, RF-CMOS performance trends. IEEE Trans. Electron. Devices 48(8), 1776– 1782 (2001) 12. C. Diaz, D. Tang, J. Sun, CMOS technology for MS/RF SoC. IEEE Trans. Electron. Devices 50(3), 557–566 (2003)

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13. Q. Huang, F. Piazza, P. Orsatti, T. Ohguro, The impact of scaling down to deep submicron on CMOS RF circuits. IEEE J. Solid-State Circuits 33(7), 1023–1036 (1998) 14. M. Vertregt, P. Scholtens, Scalable high-speed analog circuit design, in Analog Circuit Design, ed. by M. Steyaert, J.H. Huijsing, A.H.M. van Roermund (Kluwer, Boston, 2003), pp. 3–21 15. C.-H. Jan et al., RF CMOS technology scaling in high-k/metal gate era for RF SoC (Systemon-chip) applications, in Proceedings of IEEE IEDM, 2010, San Francisco, 2010, pp. 27.2.1 16. International Technology Roadmap for Semiconductors, 2009 edition: www.16.net/Links/ 200916/Home2009.htm 17. B. Murmann, A/D converter trends: power dissipation, scaling and digitally assisted architectures, in Proceedings of IEEE CICC, 2008, San Jose, 2008, pp. 105–112 18. B. Murmann, ADC performance survey 1997–2010, [Online]. Available: www.stanford.edu/ murmann/adcsurvey.html 19. P. Malla, H. Lakdawala, K. Kornegay, K. Soumyanath, A 28 mW spectrum-sensing reconfigurable 20 MHz 72 dB-SNR 70 dB-SNDR DT † ADC for 802.11n/WiMAX receivers, in Proceedings of IEEE ISSCC, 2008, San Francisco, 2008, pp. 496–497 20. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, A 1.9 W 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC, in IEEE ISSCC, 2008, San Francisco, 2008, pp. 244–245 21. H. Chung, A. Rylyakov, Z. Toprak Deniz, J. Bulzacchelli, G.-Y. Wei, D. Friedman, A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65 nm CMOS, in Proceedings of Symposium on VLSI Circuits, 2009, Kyoto, 2009, pp. 268–269 22. B. Murmann, Digitally assisted analog circuits. IEEE Micro 26(2), 38–47 (2006) 23. B. Murmann, C. Vogel, H. Koeppl, Digitally enhanced analog circuits: system aspects, in Proceedings of ISCAS, 2008, Seattle, 2008, pp. 560–563 24. R. van de Plassche, A sigma-delta modulator as an A/D converter. IEEE TCAS 25(7), 510–514 (1978) 25. S. Weaver, B. Hershberg, D. Knierim, U. Moon, A 6b stochastic flash analog-to-digital converter without calibration or reference ladder, in IEEE ASSCC, 2008, Fukuoka, 2008, pp. 373–376 26. L. Pileggi, G. Keskin, X. Li, K. Mai, J. Proesel, Mismatch analysis and statistical design at 65 nm and below, in IEEE CICC 2008, San Jose, 2008, pp. 9–12 27. M. Flynn, C. Donovan, L. Sattler, Digital calibration incorporating redundancy of flash ADCs. IEEE Trans. Circuits Syst. CAS-II 50(5), 205–213 (2003) 28. B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, G.V. der Plas, A 2.2 mW 1.75 GS/s 5 bit folding flash ADC in 90 nm digital CMOS. IEEE J. Solid-State Circuits 44(3), 874–882 (2009) 29. D.C. Daly, A.P. Chandrakasan, A 6-bit, 0.2 V to 0.9 V highly digital flash ADC With comparator redundancy. IEEE J. Solid-State Circuits 44(11), 3030–3038 (2009) 30. G.V. der Plas, S. Decoutere, S. Donnay, A 0.16pJ/conversion-Step 2.5 mW 1.25GS/s 4b ADC in a 90 nm digital CMOS process, in IEEE ISSCC, 2006, San Francisco, 2008, p. 2310 31. J. Rabaey, A. Chandrakasan, B. Nikolic (eds.), Digital Integrated Circuits, 2nd edn. (Prentice Hall, Upper Saddle River, 2003) 32. C. Grace, P. Hurst, S. Lewis, A 12b 80MS/s pipelined ADC with bootstrapped digital calibration, in IEEE ISSCC, 2004, San Francisco, 2004, p. 460 33. C. Vogel, S. Saleem, S. Mendel, Adaptive blind compensation of gain and timing mismatches in M-channel time-interleaved ADCs, in Proceedings of IEEE ICECS, Malta, Sept 2008, pp. 49–52 34. Y. Oh, B. Murmann, System embedded ADC calibration for OFDM receivers. IEEE Trans. Circuits Syst. CAS-I 53(8), 1693–1703 (2006) 35. E. Alpman, H. Lakdawala, R. Carley, K. Soumyanath, A 1.1 V 50 mW 2.5GS/s 7b timeinterleaved C-2C SAR ADC in 45 nm LP digital CMOS, in IEEE ISSCC, 2009, San Francisco, 2009, pp. 76–77 36. S. Iyer et al., A 0.5 mm2 integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floor, in IEEE CICC, 2005, San Jose, 2005, pp. 93–96

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Chapter 6

A 12b 2.9 GS/s DAC with IM3 < 60 dBc Beyond 1 GHz in 65 nm CMOS K. Bult, C.-H. Lin, F. van der Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, and X. Liu

Abstract A 12b 2.9GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < 60dBc beyond 1 GHz while driving a 50  load with an output swing of 2.5Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at highfrequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with “always-ON” biasing.

1 Introduction In large Systems-on-Chips (SoC), Data Converters are critical for connecting signals to the real world, often limiting the accuracy and speed of the overall system. The clear trend towards digital signal processing of traditional analog functions, reducing the Analog Front-End (AFE) and Analog Back-End (ABE) to a bare minimum, by connecting the Data Converter directly to the terminals, requires very high bandwidth and sampling speeds. As an example, 10GBASE-T Ethernet requires a Transmit DAC sampling at 1.6 GS/s with at least 70 dB IM3 up to a frequency of 400 MHz, while supporting an amplitude of 2.5 Vppd driven in to a 50  load. In recent years many papers have been published on high-speed DAC design [1–9]. Most of these designs concentrate on obtaining good low-frequency

K. Bult () • F. van der Goes • J. Westra • J. Mulder • Y. Lin • E. Arslan • E. Ayranci • X. Liu Broadcom Netherlands BV, Bunnik, The Netherlands e-mail: [email protected] C.-H. Lin Broadcom Corporation, Irvine, CA, USA

M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 6, © IEEE. Reprinted, with permission, from K. Bult, C.-H. Lin, F. van der Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, and X. Liu, A 12b 2.9 GS/s DAC with IM3 < 60 dBc Beyond 1 GHz in 65 nm CMOS, Journal of Solid State Circuit, December 2009

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performance and use techniques like calibration [1] or Dynamic Element Matching [10]. However, these techniques do not help the performance at higher frequencies since at those frequencies matching problems are not the limiting factor anymore. The goal of this paper is to design a DAC which achieves a minimum of 70 dB IM3 at low frequencies, maintains that performance up to a minimum of 400 MHz and achieves at least 60 dB IM3 at 800 MHz, as is shown in Fig. 6.1. Currently, no published designs meet these requirements. Section 2 introduces the chosen architecture. Sections 3 and 4 deal with various distortion mechanisms that are dominant at low- and high-frequencies respectively. In Sect. 5 the DAC-Cell for the thermometer-coded Coarse-DAC is shown and the implemented techniques are discussed in detail. The test-chip and set-up are discussed in Sect. 6 and the results of measurements along with a comparisons with the theory (as discussed in Sect. 5) as well as with previously published data are shown in Sect. 7. Finally, Sect. 8 summarizes the conclusions.

2 Architecture For fast-sampling applications the Current-Steering architecture is the architecture of choice [1–9]. Because of the obvious advantages of thermometer-coded DACs with respect to DNL, glitch-energy, monotonicity and linearity on the one hand and on the other hand the advantages of binary-coded DACs with respect to compactness and simplicity, a segmented design was chosen (Fig. 6.2). Using the approach outlined in [2] the optimal segmentation ratio was determined and a 6b thermometercoded DAC was combined with a 6b binary-coded DAC. A transformer connects the DAC to the load. For proper termination reasons, on each side of the transformer the impedance equals 100  and the total effective impedance to the DAC equals 50 .

6 A 12b 2.9 GS/s DAC with IM3 < 60 dBc Beyond 1 GHz in 65 nm CMOS

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row

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Fig. 6.3 Thermometer-coded Coarse DAC

The Thermometer-coded MSB section (Coarse-DAC) determines the overall performance with respect to linearity and most of the design effort was focused on that block. The architecture is shown in Fig. 6.3. Although the final layout was not done in a matrix-style layout but rather in a single-line layout, the cells are driven by row and column decoders as this turns out to be area efficient. Latches are placed at the input of the DAC, after the column and row-decoding and inside the cells.

3 Low Frequency Performance This section deals with error-mechanisms that are frequency-independent and as such will dominate the accuracy at low frequencies.

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Vss Isupply IR

Fig. 6.4 IR-drop in the supply-line causes DNL

3.1 Matching Transistor-mismatch in the current source of the DAC-cell is a source of nonlinearity, especially in the coarse-DAC. Care has to be taken to obtain good matching by using sufficient gate-area [11], short distances between the transistors and equal environments through the use of dummy-transistors. Many papers have been written about various techniques to improve matching between current sources, like calibration techniques [1] or Dynamic Element Matching (DEM) [10]. Although there are ample examples of papers that show that for low-frequencies this does indeed improve the linearity of the DAC, for high-frequencies these techniques in general do not help and often even degrade the performance. This is mostly because both techniques complicate the design significantly, including the layout, whereas high-frequency performance mostly benefits from simplicity and low parasitic capacitances. As a result no matching improvement techniques were used other than proper layout and proper transistor-sizing.

3.2 IR-Drops on the Supply Routing of the supply-lines to the DAC current sources is a critical step. As the supply-lines carry current, any resistance will cause voltage drops (“IR”, see Fig. 6.4) on the supply line, which in turn can cause the individual gate-source voltages to be unequal [12]. As a result the value of the currents will become smaller (or bigger) along the supply-line (Fig. 6.4), causing not only a DNL problem, but, without any randomization, could also cause significant INL problems. Solutions can be found in using wide power supply lines and binary trees for the supply-grid.

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RL

123

RL Vout

2Zo (N+n)

(N+n) Io 2

(N–n) Io 2

2Zo (N–n)

Fig. 6.5 The effect of finite current source output impedance on DAC linearity

3.3 Finite Output Impedance Finite output impedance of DAC current sources leads to distortion, as has been pointed out by several authors [4, 8, 9]. Figure 6.5 shows a thermometer-coded DAC with ideal current sources, but with finite current source output impedance Ro . In this graph, N equals the total number of current sources, Io is the value of one current source and n equals the digital input code (N  n  N). Depending on the digital input code, more or less current sources are connected to the left and the right output nodes. Along with that also more or less output impedances are connected in parallel with the load impedance RL . This means that the total effective load impedance becomes signal-dependent. Since the output voltage is a simple multiplication of the current and the output impedance, a signal-dependent load impedance leads to distortion. A straightforward calculation of the transfer-function from the digital input word (n) to the output voltage Vout in Fig. 6.5 leads to the following expression: h i Vout D RL NIo .n=N/ C .n=N/3 ŒRL N=2Ro 2

(6.1)

For full swing conditions (n D N) the expression for third order distortion becomes: HD3 D ŒRL N=4Ro 2

(6.2)

As Eq. 6.2 shows, low third-order distortion (due to this mechanism only) requires a high output impedance from each current source: Ro  NRL . This can be fairly easily achieved at low frequencies by cascoding and if necessary double or active cascoding. For high frequencies this is not a sufficient solution as will be shown in Sect. 4.

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4 High Frequency Performance High frequency performance is quite a different problem from its low frequency counterpart and special measures have to be taken.

4.1 Switch Gate Driving It is well-known that it is important to keep the voltage across the current sources as stable as possible during the output current transition from one side to the other [2, 8]. Special gate-driving circuits have been developed for that purpose [8]. However, it is also important that the transition itself is as short as possible. The main reasons for that are to reduce the effects of switch driver mismatch, clock jitter, decoding feed through and, to some extent, device noise. CML-drivers are often used to obtain maximum possible clock speed (because of the reduced swing), but the steepest transitions are obtained using regular CMOS logic. In this design the latch of Fig. 6.6 is used for two reasons, it creates the steepest transition [2] and has the shortest clock-to-Q delay known to the authors [8]. Inherently, this circuit has a low crossing of the Q and QB signals. If followed by inverters for Q and QB, the signals become high-crossing and can be used to drive the switch gates directly. It was found that the rapid transitions exhibited by this circuit have more benefits than any reduced swing circuit known to the authors.

4.2 Decoding Feedthrough Since decoding signals contain information about the input signal, any feedthrough from the decoding to the DAC output can lead to distortion. In [8] Data-Dependent Clock Loading is discussed and a solution is presented. Another error mechanism is non-symmetrical decoding. In the design presented here, decoding is done as if the current source cells were distributed in a matrix-style layout, using column and

clk D QB

Q

Fig. 6.6 Fast latch

DB

6 A 12b 2.9 GS/s DAC with IM3 < 60 dBc Beyond 1 GHz in 65 nm CMOS col

125

row clk QB

col+1

row Q

col

col+1

Fig. 6.7 Latch with symmetrical decoding

row signals [2]. A cell can get activated either because the next column signal is active or the current column and the current row are active. The circuit in Fig. 6.7 has been used to make sure that in all cases the cell gets activated with the same signal strength [3]. At high speed the transition of digital signals can still have a finite settling effect at the end of the clock-period and a difference can emerge between the values of those signals that had to transition and those that already transitioned in a previous clock-period. Adding an extra latch reduces this effect considerably.

4.3 Switch Driver Mismatch Mismatch in switch driver transistors can lead to small differences in the speed of the transition and therefore also the exact switching moment. Deviations in switching moments are more important at higher signal speeds and therefore a degradation proportional to frequency is to be expected. For good high-frequency performance, care should be taken to obtain good matching of the driver transistors. However, since any spread in switching moment is proportional to the switching time, the absolute transition of the driving signal should be as fast as possible. Both good matching as well as a fast transition requires the driver transistors to be fairly large. The latch or logic preceding the driver is less sensitive and can be scaled down in size, leading to a tapered design in logic, latches and driver. Also the supply-line needs to be low-Ohmic and routed in such a way that the actual driving strength for all drivers is matching well.

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4.4 Output Current Tree Equal delays are not only relevant in the clock-tree but just as much in the signal path. For that reason it is crucial to design the paths from the cells to the outputnodes as well-matched as possible. A binary output-current tree is used in an effort to keep all possible delays in the signal path the same.

4.5 Output Impedance at Higher Frequencies As discussed in section III.C, finite current source output impedance causes distortion in current-steering DACs. Equation 6.2 shows the expression for third harmonic distortion (HD3) at low frequencies. In the analysis it was assumed that the output impedance was purely real and equal to Ro . At higher frequencies this assumption is no longer valid. A better assumption would be that the output impedance can be modeled by the parallel connection of a resistor and a capacitor: Zo D Ro == .1=j!Co / :

(6.3)

An expression for HD3 valid for all frequencies is found by substituting Ro in (6.2) by jZo j: HD3 D ŒRL N=4 jZo j2

(6.4)

As the impedance Zo shows a first-order roll-off with frequency, it can be expected that for higher frequencies (! > 1/Ro Co ) HD3 degrades quadratically with frequency and this will become the dominant distortion mechanism. The effective output capacitance Co being switched back and forth between the positive and negative output, will be referred to as the “switching capacitor” in the remainder of this paper and should be kept small. A numerical example may make the above more clear. A 12b DAC is built from a 6b Fine-DAC and a 6b Coarse-DAC and the Coarse-DAC is thermometer coded. The number of current sources in the Coarse-DAC is 64 (DN). Using Eq. 6.4 with a load resistance of 50  (DRL ) and HD3  67.5 dB (D IM3  70 dB) yields jZo j  39k, which seems reasonable and could be achieved through cascoding. However, if this level of HD3 also is required at an output frequency of 600 MHz, the maximum capacitance in this impedance can be no more than 6.8fF. This is very difficult to achieve indeed.

5 The DAC-Cell After discussing various error mechanisms in Sects. 3 and 4, this section deals with the solution proposed here. The DAC-Cell designed to combat these issues is shown in Fig. 6.8.

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2.5 V supply

DAC-CELL M5

1.75V

M6

3 Decoding + Latches

4

M4

M3

M13 1.0 V supply

1.0 V supply

BIASING

2 M12

M9

M8

M2

M11

0.75 V

M7

M1

M10

0.41 V

Fig. 6.8 DAC-Cell

5.1 Low Frequency Issues To obtain good matching between the Coarse-DAC currents, it is of key importance that transistor M1 is well matched to its counterparts in the other DAC-cells. For this reason M1 is sized large enough to support the required matching [11] and is placed in a large array of transistors with ample dummies placed at each end of the array. Triple cascoding (M2, M3/M4 and M5/M6) is used to prevent finite outputimpedance of the current sources dominating the low frequency distortion.

5.2 High-Frequency Output Impedance The goal of this paper is to obtain good harmonic performance even at high frequencies. As pointed out in Sect. 4.5, it is crucial to keep the effective “switching” capacitance Co as small as possible. Therefore M2 is sized as small as possible to reduce the parasitic capacitance at the sources of switches M3 and M4, which themselves are also sized minimally. Since the switches operate with a large Vgs ,

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their sizes are close to the minimum allowed in the technology. The device sizes in the DAC-cell are therefore large at the bottom (for good accuracy), getting smaller in the middle (just large enough to support the current) and close to the minimum at the switches. As discussed in Sect. 5.1, M5 and M6 are added in each cell to reduce the effect of finite output-impedance at low frequencies. Unfortunately, at higher frequencies this techniques does not work that well. M5 and M6 do reduce the effect of parasitic capacitances from M1 to M4, but also add their own parasitic capacitances, primarily their own Cgs ’s [9]. When M3 and M4 are switching, so are the Cgs ’s of M5 and M6 and they become the dominant limitation of the switching output impedance of the current source.

5.3 The “Switching Impedance” It is important at this point, to realize that the part of the output impedance that is hurting the distortion performance is only that part which is actually switching. Any impedances (like parasitic capacitances) which are not switching, but are rather fixed at each side of the output, are not contributing to distortion. This observation leads to one of the key contributions of this paper. In the remainder of this paper the term “switching impedance” is used for that part of the output impedance that is actually switching, equivalent to Zo in Eqs. 6.3 and 6.4. At higher frequencies Zo is dominated by the “switching capacitance” Co .

5.4 The Proposed Solution Adding small current sources (M7–M9 and M10–M12) to the sources of cascodes M5–M6 prevents the cascodes from being fully switched off. That means that even if the current from the current source M1/M2 is not routed through a particular cascode, that cascode remains active. In turn this means that the parasitic capacitances associated with nodes 3 and 4 can still be observed from the DACcell output, irrespective of the status of the switches M3–M4. Therefore these capacitors will not contribute to distortion degradation. Now, the first switching capacitors that can be observed are the Cgs ’s of M3 and M4, but their effect on finite output impedance is reduced by the intrinsic gain (gm .rout ) of the cascode transistors M5–M6. The use of the cascode transistors M5–M6 together with the small current sources M7–M9 and M10–M12 achieves a reduction of the switching output-impedance, and therefore also the distortion, by an order of magnitude. To make the solution proposed here more clear, the effect discussed above is illustrated in Fig. 6.9, where both the circuits of the “on”-impedance Zo (on) as well as the “off”-impedance Zo (off) are shown. The “switching-impedance” Zo can be obtained mathematically through:

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Zo(off)

Zo(on)

M5

129

Zo

M6

M3

M5

M3

1 / Zo = 1 / Zo(on) – 1 / Zo(off)

Fig. 6.9 Subtracting the “off ”-impedance Zo (off ) from the “on”-impedance Zo (on). The resulting “switching-impedance” Zo is shown on the right

1=Zo D 1=Zo .on/  1=Zo .off/ ;

(6.5)

as is shown in Fig. 6.9. By “subtracting” the two circuits, as a result of which all the capacitances associated with M5/M6 are cancelled, the first capacitor seen from the output becomes the Cgs of M3/M4. However, this capacitance is reduced by the intrinsic gain of both M3/M4 as well as M5/M6, improving the performance by a factor (gm .rout 2 ). In order to keep the power dissipation as low as possible, the additional current sources should be kept as small as possible. Their purpose is to keep M5–M6 “on” in order to keep the parasitic capacitances associated with node 3 and 4 observable at all times. However, if the additional current source values are too small, the switching of the DAC-cell will vary the Cgs ’s of M5–M6 too much and a finite effect on distortion will be the result. Simulations have shown that a relative small value of 1–2% of the main current source is sufficient to keep the Cgs ’s of M5–M6 fairly constant.

6 Test-Chip The 12b DAC was built from a 6b Thermometer-coded Coarse-DAC and a 6b Binary-coded Fine-DAC (as shown in Fig. 6.2). The Coarse-DAC uses 63 DACCells as depicted in Fig. 6.8. As mentioned before, although the layout of the coarse-DAC was implemented with all the current sources in a straight line (as opposed to a matrix style layout), the decoding was implemented using column and row decoding using the circuit of Fig. 6.7, as this results in a very effective decoding structure.

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A transformer was used (as depicted in Figs. 6.2 and 6.8) to connect to the loadimpedance. As the total effective load-impedance is 50  and a 2.5 Vppd swing is required by the application, the total available current for driving the load is 50 mA. As a result of that large signal-swing the center-tap of the transformer is biased at 2.5 V, which necessitates the use of thick-oxide devices for M5 and M6. Two Direct Digital Frequency Synthesizers (DDFS) were integrated along with the DAC to enable two-tone testing. This avoids the problem of having to bring highfrequency digital signals onto the chip for test purposes. In the real application that is of course also not necessary because the digital signals to drive the DAC come from a dedicated Digital Signal Processor (DSP).

7 Measurements The design was implemented in 65 nm CMOS technology and measures 0.31 mm2 . The layout is shown in Fig. 6.10. The power-dissipation was 188 mW, combined from a 1.0 and 2.5 V supply. The measured INL and DNL were 0.5lsb and 0.3lsb respectively on a 12b level. All dynamic measurements were performed using the two on-board DDFS’s. Although the circuit was designed for a 1.6 GS/s application, it ran with good performance up to 2.9 GS/s. Many of the measurements were performed at 2.9 GS/s, others at the speed of the application, 1.6 GS/s.

7.1 IM3 Measurements Figure 6.11 shows a spectrum of the output signal of a two-tone test centered at 1 GHz and sampling at 2.9 GS/s. As can been seen the IM3 is better than 62 dB.

Biasing

Tail Current Sources Switches + Cascodes Decoding + Registers

Fig. 6.10 DAC layout

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Fig. 6.11 Two-Tone measurement centered around 1 GHz while sampling at 2.9 GS/s 100

[6] @ 0.4 GS / s

90

IM3 [dB]

Theory 80 This work @ 2.9 GS / s

70 60 [4] @ 1.0 GS / s 50

[5] @ 1.4 GS / s 400

800 Frequency [MHz]

1200

Fig. 6.12 Measured IM3 versus signal-frequency. Note the differences in output swing and sampling-frequency

Many of those measurements were taken and Fig. 6.12 shows the measured IM3 results versus signal frequency, sampling at 2.9 GS/s. The figure shows a 70 dB IM3 bandwidth of 550 MHz and a 60 dB IM3 bandwidth of more than 1 GHz.

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Zo [Ohm]

1M

Zo

Zo(on)

10 K

100

100 K

1M

10 M 100 M Frequency [MHz]

1G

10 G

Fig. 6.13 Simulated output impedances Zo (ON) and Zo (OFF) versus frequency. The switching impedance Zo is calculated using (6.5)

7.2 Comparison with Theory In order to show the validity of the simple high-frequency distortion model discussed in Sect. 4.5, the output-impedance of the DAC-cell, as shown in Fig. 6.8, was simulated, both for the output that is ON as well as for the output that is OFF. The results are shown in Fig. 6.13 as Zo (ON) and Zo (OFF). An effective switchingimpedance Zo was extracted using Eq. 6.5. By taking the imaginary part of Zo we can make an estimate of the “switching-capacitance”. Both the imaginary part of Zo as well as the switching-capacitance is shown in Fig. 6.14. For frequencies up to about 200 MHz the estimated switching capacitance is about 5fF, after which the capacitance increases and peaks around 1.5 GHz at 9.5fF. At a frequency of 600 MHz the value is about 6.5fF, very close to what was needed for our goal of 70 dB IM3 at that frequency. Using the data from Fig. 6.14 in Eq. 6.5, with RL D 50  and N D 64, an estimate was made of the IM3 for higher frequencies. This is shown in Fig. 6.12 as the curve labeled “Theory”. As can be seen, for higher frequencies (>400 MHz) a very close match is obtained with the measured data, showing the validity of the theory. The IM3 at lower frequencies is clearly dominated by other effects, most likely a combination of matching errors, IR-drops and transformer-effects. The peaking observed around 400 MHz can be explained by a cancellation effect. The lowfrequency distortion mechanism (mismatch, IR-drops, transformer) cancels with the high-frequency mechanism (finite output impedance).

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10

Co

1 / jωCo

8

1M

6

10K

4

100K

1M

10M 100M

1G

10G

Co [fF]

Zo [Ohm]

100M

100

133

2

Frequency [MHz]

Fig. 6.14 Simulated imaginary part of the switching output impedance and the associated output capacitance Co versus frequency

7.3 SFDR Measurements SFDR was measured at 1.6 GS/s and 2.9 GS/s. A spectrum of the output signal measured at 1.6 GS/s and producing an output tone of 125 MHz is shown in Fig. 6.15. Many of those measurements were performed and Fig. 6.16 shows the results. It shows a 70 dB SFDR bandwidth of 225 MHz and a 60 dB SFDR bandwidth of 550 MHz. The SFDR-results clearly show a lower bandwidth than the IM3 results. This is to be expected and can be explained as follows. In the first place, IM3 measurements only look at close-in third-order components, while SFDR measurements look at all the tones. Secondly, and more importantly, all measurements have been performed through a transformer (see Figs. 6.2 and 6.8), which has a bandwidth of about 300 MHz. This means that if the signal frequency is higher it gets attenuated. However, if spurious tones are generated and folded back to lower frequencies (below the transformer bandwidth), they do not get attenuated. This mechanism degrades the measured SFDR performance results significantly. The same mechanism has no effect on IM3 measurements, since the signal tones and the close-in tones are approximately at the same frequency and get the same attenuation.

7.4 Comparison with Literature Table 6.1 shows a comparison with published data [4–7]. Although all designs are driving a 50  load, the available current varies significantly, from 15 [7] to 50 mA (this work). This results in equally significantly different signal swings.

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Fig. 6.15 SFDR measurement producing a tone at 125-MHz while sampling at 1.6 G-S/s

90 [6] @ 0.4 GS / s

80 SFDR [dB]

[5] @ 1.4 GS / s

70

[4] @ 1.0 GS / s

This work @1.6 GS / s

60 [7] @0.5 GS / s

50

This work @ 2.9 GS / s

200

400 Frequency [MHz]

600

800

Fig. 6.16 Measured SFDR versus signal-frequency. Note the differences in output swing and sampling-frequency

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Table 6.1 Comparison with published data Reference

Tech [nm]

Fclk [GHz]

Iload [mA]

Swing [Vppd ]

Power [mW]

NPE [%]

This work [4] [5] [6] [7]

65 350 180 250 180

2.9 1.0 1.4 0.4 0.5

50 16 30 20 15

2.5 0.8 1.5 1.0 0.75

188 110 200 400 216

66 12 23 5 5

When comparingpower dissipation, the available power for the load, P(Rload ) should be considered as well. A comparison of absolute power dissipation would make no sense. Here we use a Normalized Power Efficiency (NPE) defined as: NPE D Ppeak .Rload / =0:25Psupply

(6.6)

The factor 0.25 is used to allow the theoretical maximum of the Normalized Power Efficiency to be 100%. Note that the NPE is varying significantly from design to design (5–66%) and this work achieves the highest NPE. The vast differences in maximum signal swing also have a strong influence on distortion performance. As is generally known, third-order distortion is proportional to the square of the signal amplitude. Figure 6.12 also shows the results presented by [4–6]. Although the results presented here outperform the previously published results for frequencies above 300 MHz, the real difference is, as a result of the vast differences in signal amplitude, much more pronounced. For IM3, the best results to compare to are presented by [6] which are produced at an output swing of 1.5 Vppd , compared to 2.5 Vppd presented here. This results in an additional (2.5/1.5)2 D 9 dB difference in IM3 compared to [6], on top of the (approximately) 9 dB shown in the graph. Note that the results presented here are produced at a sampling speed of 2.9 GS/s, more than twice the sampling speed of the second best in Table 6.1. Figure 6.16 shows the results of SFDR measurements of [4–7] and the results of this work. In this case the best results to compare to are presented by [4], but at an amplitude of 0.8 Vppd , compared to 2.5 Vppd presented here. The difference in amplitude is equivalent to an additional (2.5/0.8)2 D 20 dB in SFDR. Table 6.2 gives an overview of the measured performance of this work.

8 Conclusions A 12b 2.9 GS/s Current-Steering CMOS DAC was presented with a 70 dB IM3 bandwidth of 550 MHz and a 60 dB IM3 bandwidth of 1.0 GHz. These results were obtained while driving a 50  load with 2.5 Vppd swing. The DAC presented combines the highest clock frequency (2.9 GS/s) with the highest output swing

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CMOS NOB Fclk Iload Swing Power NPE INL DNL 70 dB IM3 Bandwidth 60 dB IM3 Bandwidth 70 dB SFDR Bandwidth 60 dB SFDR Bandwidth

65 nm 12 2.9 GS/s 50 mA 2.5 Vppd 188 mW 66% 0.5 lsb 0.3 lsb 550 MHz 1,020 MHz 225 MHz 550 MHz

(2.5 Vppd ) at the best power efficiency (66%), while simultaneously achieving the highest 60 dB and 70 dB IM3 bandwidth. The increase in performance at highfrequencies compared to previously published results is mainly obtained by adding “always-ON” cascodes on top of the current-switches.

References 1. H.J. Schouwenaars et al., An oversampled multibit CMOS D/A converter for digital audio with 115-dB dynamic range. IEEE J. Solid-State Circuits 26, 1775–1780 (1991) 2. C.-H. Lin, K. Bult, A 10-b 500-MSample/s CMOS DAC in 0.6-mm2 . IEEE J. Solid-State Circuits 33, 1948–1958 (1998) 3. K. Bult, C.-H. Lin, U.S. Patent 6,191,719, Digital to analog converter with reduced ringing, Feb 2001 4. A. Van den Bosch et al., A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J. Solid-State Circuits 36(3), 315–324 (2001) 5. B. Schafferer, R.Adams, A 3V CMOS 400mW 14b 1.4GS/s DAC for Multi-Carrier Applications, in ISSCC Digest Technical Papers 2004, Feb 2004, pp. 360–361 6. W. Schofield et al., A 16b 400MS/s DAC with <80dBc IMD to 300MHz and <160dBm/Hz noise power spectral density, in ISSCC Digest Technical Papers, 2003, San Francisco, Feb 2003, pp. 126–127 7. K. Doris et al., A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18um CMOS, in ISSCC Digest Technical Papers 2005, San Francisco, Feb 2005, pp. 116–117 8. D.A. Mercer, Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-m CMOS. IEEE J. Solid-State Circuits 42, 1688–1698 (2007) 9. P. Palmers, M. Steyeart, A 11mW 68dB SFDR 100 MHz bandwidth SD-DAC based on a 5-bit 1GS/s core in 130nm, in ESSCIRC Digest Technical Papers 2008, Sept 2008, pp. 214–217 10. K.L. Chan,J. Zhu, I. Galton, Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs. IEEE J. Solid-State Circuits 43, 2067–2078 (2008) 11. M. Pelgrom, A. Duinmaijer, A. Welbers, Matching properties of MOS transistors. IEEE J. Solid-State Circuits SC-24, 1433–1439 (1989) 12. T. Miki et al., An 80-MHz 8-bit CMOS D/A converter. IEEE J. Solid-State Circuits SC-21, 983–988 (1986)

Part II

Short-Range Wireless Front-Ends

This second part of the book is on ‘short-range wireless front-ends’, which, as the name suggests, refers to wireless communication of data over short, or relatively (with respect to the application) short, distances. Six chapters will focus on this, from different angles of view. The first papers start from the application view: three of them discuss various forms of sensor networks, and one focuses on RFID. In most of the applications, low power, or ultra low power, plays a dominant role, whereas the data rates are relatively low. In case power dissipation can be kept low enough, energy scavenging comes into play, making the use of batteries even obsolete. The first paper, of William Scanlon, addresses sensor networks from a high level, with system and network implications, focusing on the free-space channel, and on the consequences, in the sense of requirements, for the physical layer. The second paper, of Guido Dolmans, addresses the field of ultra-low-power wireless body-area networks for medical applications, like EEG measurements. The ultra-low-power requirement requires cross-layer optimization, including MAC, PHY, protocols, standardization, architecture, and final circuit design. The design of a specific ultra-low-power transmitter and a super-regenerative receiver is shown. Tim Piessens then addresses low-power RF energy harvesting in the context of RFID tags, and Frank Henkel finally addresses sensor network frontends for military, agriculture, and industrial applications. The last two papers approach the field from a different angle of view: they focus on very-high-frequency technology, for future short-range communication. Reza Mahmoudi discusses microelectronic frontend design for 60 GHz and higher, for very-high data-rate applications. Here, microwave design, Maxwell equations, 2.5 and 3D simulation, parasitics, and high-frequency measurement techniques play a dominant role. Lorenzo Tripodi, finally, approaches the terahertz field: he discusses a transmitter and a receiver operating at very wide bandwidths, of about 200 GHz, for spectroscopy applications. This work is showing that the so-called ‘terahertz gap’ between electronics and photonics is entered now, which promises a successful future for a complete new field of terahertz electronics and a lot of new applications. Arthur van Roermund

Chapter 7

Short Range Radio Communication – Novel Applications and Their Physical Layer Requirements William G. Scanlon

Abstract Technologies and applications based on short range radio communication links have pervaded almost all aspects of modern life. From wireless doorbells through Bluetooth headsets and WiFi browsing to streaming high definition multimedia, we have never been so dependent on short range links. This paper outlines some of the physical layer requirements for short range radio systems and gives an overview of some of the novel applications and future trends for this area of technology.

1 Introduction Since its discovery, wireless communication has always captivated mankind with its air of ‘magic’ and obvious application. However, it is not just the ability to travel over long distances that made wireless communication so attractive, particularly in terms of personal communication it was the ability to bring freedom from the restrictions and limitations of cabling that made wire-less so popular. And in the latter age of electronics, such tether-less operation brought about ‘freedom’ through unobtrusiveness and mobility. Short range radio can be defined as those radio systems bringing wireless communication with links covering modest distances or over distances that are short relative to the scope of the application. Common and familiar examples include wireless LAN systems, children’s toys, home automation (garage door opener, heating thermostat), DECT home telephones or any Bluetooth application. However, as suggested above, many of the challenges facing short-distance links

W.G. Scanlon () Wireless Communications Research Group, Queen’s University, Belfast, UK Telecommunication Engineering, University of Twente, Enschede, The Netherlands e-mail: [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 7, © Springer ScienceCBusiness Media B.V. 2012

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are also applicable to longer range links which are relatively short in the context of their application. For example, km-scale communication between an array of micro satellites forming a low-frequency radio telescope could be considered a short-range radio application. This paper discusses some of the challenges and requirements of short range radio systems in Sect. 2. An example novel emerging application is described in Sect. 3.

2 Short Range Radio Physical Layer Requirements Regardless of the application, it is the nature of the radio channel itself that determines every other aspect of short range radio communications. For example, communication through anything more than a few 100 m of sea water is almost impossible, except at very low frequencies due to the dielectric losses of the medium. In many cases it is the application itself that determines the defining features of the channel – for example, in body area networks (BANs), the movements of the human body perturb the radio channel in a way that is quasi-repetitive for regular movements yet is uncontrolled in that the user can move around as much as they like. Interestingly, the radio channel characteristics might themselves lead to novel applications. A good example of this is the regular changes in impedance that a wearable antenna might see as the user respires with many research groups currently trying to build respiration based physiological monitors around that particular feature. It is the channel then that sets some of the key parameters for the short range radio system including expected received power level, dynamic range and levels of inter-symbol interference or, in narrowband systems, multipath fading. However, the peculiar nature of the channel in some applications can also have unexpected effects in terms of other radio system parameters such as co-channel and adjacent channel interference. This is discussed further in Sect. 3. One of the driving forces behind the popularity of short range radio systems, particularly at UHF frequencies, is the unlicensed use of the spectrum with most high volume short range radio applications operating in the Industrial Scientific and Medical (ISM) bands. Unlicensed use requires careful consideration of effective radiated power (ERP) and spectral characteristics to reduce interference, increase re-use and promote efficient use of the radio spectrum. However, while many low data rate applications operate quite well under existing regulation in the popular ISM bands such as 868 MHz and 2.45 GHz, there is a desire for higher bandwidth services. This has led to renewed interest in short range links operating at 60 GHz and higher millimetre wave frequencies. In all but the most ‘open’ of line of sight (LOS) applications, the poor channel characteristics at these frequencies at first glance appear to be a major concern. However, sometimes the ease of blocking at these frequencies can lead to useful advantages such as frequency re-use and security as demonstrated in the soldier to soldier system outlined in [1].

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Energy consumption, while only indirectly related to the propagation channel, is another extremely important aspect of short range radio systems. As portable or wearable devices get smaller due to chip integration developments, the relative size and weight of any battery becomes more significant. Recent advances in low power circuit design have helped to improve the situation but reducing energy consumption at all stages, from RF circuitry upwards is a major requirement. Even the choice of power supply circuit is important, particularly in low-duty cycle designs. For example, consider an active RFID transceiver based on the Texas Instruments CC1110 system on chip (low power 868 MHz transceiver with integrated 8051 microcontroller) with an active time of 10 ms every 2 s (0.5% duty cycle). Assuming an idle current of 0.02 mA including regulator losses, the average current for this duty cycle is 0.12 mA, given an active current of 20 mA. If the duty cycle is reduced further (Fig. 7.1), for this configuration the idle current becomes dominant after an active interval time of around 60 s. For this reason, many low cost wireless sensor node systems, notable for their long life requirements and extremely low duty cycle, operate without any voltage regulation. Often short range radio devices need to wake regularly to listen for commands. In ultra low power systems one way to avoid this cost is to utilise “wake on radio” techniques. For example, the Zarlink medical implant communications ZL70102 chip has an integrated 2.45 GHz wake on radio circuit. Other important requirements for short range radio applications include the need for active antenna tuning in ultra low power medical implants and wearable body sensor nodes. These devices will often use electrically small antennas which because of their high Q factor (stronger near field) are subject to detuning effects caused by the proximity of human body tissue.

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3 BAN to BAN Application Example As the demand for BANs increases in medical, military, sport and entertainment application, the issue of inter-body interference will become an important concern for protocol design and quality of service for the end user. In a BAN communication is intended to be over the surface of the user’s body, for example from distributed biomedical sensors to a “controller” node for further processing or storage. However, it is widely recognised that since wave propagation over the human body is subject to increased losses compared to free-space propagation, that there is a potential major problem with multiple co-located BANs. Since wave propagation “off” the human body suffers from much less path loss, then a wearable receiver node will experience high levels of either co-channel or adjacent channel interference depending on the channel allocations in a particular situation. This issue was investigated through a series of “live” channel measurements using off the shelf 2.45 GHz wireless transceivers. A total of 12 nodes were used, 6 on each body, and the path loss between each node in the mesh was determined 17 times a second. Figure 7.2 shows the two BANs. Details for the experimental setup can be found in [2]. Wearing the jackets and nodes shown in Fig. 7.2, the test users initially sat in a common room environment and then moved away from each other heading in different directions along a corridor until they were both at opposite ends. Here the users waited for approximately 45 s, before returning back down the corridor to the common room area to finish the experiment by sitting once again. The entire test lasted about 215 s. To get a full understanding of the channel, received signal strength (RSSI) time-series for the full mesh needs to be studied to reveal how body movements affect this balance between on-body and off-body channels. Due to space limitations, only a subset of results including both LOS and non-LOS (NLOS) cases are shown.

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The RSSI time-series results in Fig. 7.3 show that for the LOS on-body link (H–I), channel fading is greatly increased when the user is mobile (see dynamic range, Table 7.1). Figure 7.4, however, shows a combination of fading and distance related path loss as BAN2 moved away to the far end of the corridor from BAN1. The key result from these RSSI time series and Table 7.1 is that while the potential interference from nearby BANs is unpredictable and extremely variable, that the average levels (Table 7.1) are significantly high. The relative user movements only serve to complicate the situation. In practical deployments, BAN systems will have to employ interference mitigation techniques such as dynamic channel assignment.

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Nonetheless, given that these are low cost, low power devices their RF front ends need to be carefully designed to cope with the expected large dynamic range and high levels of co- and adjacent channel interference.

4 Conclusions A short overview of short range radio requirements and challenges has been presented. While the applications for short range radio systems continues to grow there will be increased need for innovation in a number of areas, particularly at the physical layer.

References 1. S.L. Cotton, W.G. Scanlon, B.K. Madahar, Millimeter-wave soldier-to-soldier communications for covert battlefield operations. IEEE Commun. Mag. 47(10), 72–81 (2009) 2. S.F. Heaney, E. Garcia-Palacios, W.G. Scanlon, Context-aware body area networks (CABAN) for interactive smart environments: interference characterization, in 5th International Conference Body Area Networks (Bodynets), Corfu, Greece, Sept 2010

Chapter 8

Ultra Low-Power Wireless Body-Area Sensor Networks G. Dolmans, F. Bouwens, A. Breeschoten, B. Busze, P. Harpe, L. Huang, X. Huang, M. Konijnenburg, V. Pop, M. Vidojkovic, Y. Zhang, C. Zhou, and H. de Groot

Abstract In wireless body area network (WBAN) applications, wireless sensors are used to collect, monitor and transmit vital signs and other medical information. In such scenarios, it is critical to maximize the autonomy, while satisfying application performance. A unique platform for introduction of such ultra-low power technology components is an electrocardiography (ECG) patch for BAN applications, and is taken in this work as an example to illustrate the development of an ultra low-power transceiver.

1 Introduction The rapid growth in physiological sensors, low power integrated circuits and wireless communication has enabled a new generation of wireless sensor networks. Ultra-low power design and architectural level thinking is driving game-changing circuit and system innovation in wireless sensor networks. A number of intelligent comfortable physiological sensors can be integrated into wearable wireless body area networks, which can be used for personalized, predictive, preventive and participatory health care. The sensor information will be transmitted wirelessly to an external processing unit. The unit instantly transmits all information to the backbone in real time to the doctors throughout the world. If an emergency is detected, the physicians can inform the patient by sending appropriate messages or alarms. Currently the level of information provided and energy resources capable of powering the sensors are limiting. The technology is still in its primitive stage

G. Dolmans () • F. Bouwens • A. Breeschoten • B. Busze • P. Harpe • L. Huang • X. Huang • M. Konijnenburg • V. Pop • M. Vidojkovic • Y. Zhang • C. Zhou • H. de Groot Holst Centre/Imec, HTC31, P.O. Box 8550, 5605 KN, Eindhoven, The Netherlands e-mail: [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 8, © Springer ScienceCBusiness Media B.V. 2012

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Fig. 8.1 Short-range WPAN standardization from 1998 to 2011

and it is being widely researched. Once adopted, it is expected to be a breakthrough invention in healthcare for ubiquitous monitoring, real-time diagnostics, and patientcentric therapy.

2 WBAN 2.1 What Is a WBAN? A Wireless Body Area Network (WBAN) enables wireless communication between several miniaturized body sensor nodes and a single central unit. The development of WBAN technology can be seen as an extension of wireless personal area network (WPAN) technologies for communications on, near and around the human body. A WBAN system can use WPAN wireless technologies as gateways to reach longer ranges. WPAN systems have been standardized in IEEE 802.15.1 (Bluetooth) and IEEE 802.15.4 (Zigbee). The evolution of these 802.15 standards is shown in Fig. 8.1. The draft standard IEEE 802.15.6 [1] is a WBAN standard for short range, wireless communication in the vicinity of, or inside, a human body (but not limited to humans). It uses existing ISM bands as well as frequency bands approved

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Fig. 8.2 WBAN communication paths: on-body to central unit, on-body to on-body, on-body to implant, implant to implant

by national medical and/or regulatory authorities. Support for quality of service, extremely low power, and data rates up to 10 Mbps is required. The study group Medical Body Area Network (MBAN) has recently being transformed in task group 802.15.4j. The purpose is to define a physical layer for IEEE 802.15.4 in the 2,360–2,400 MHz band that complies with Federal Communications Commission (FCC) MBAN rules. This 4j taskgroup may also define modifications to the MAC needed to support the new physical layer. The purpose of an international standard for WBAN and MBAN is to facilitate low-power and highly reliable wireless communication for use in close proximity to, or inside, a human body. Body area wireless communications scenarios are shown in Fig. 8.2. Standard radio solutions will co-exist in the market with proprietary solutions optimized for required performance in healthcare networks at the lowest possible power. A proprietary ultra low-power radio solution is the focus of this paper. Key elements of the upcoming standards such as anticipated use in medical licensed bands close to ISM bands are taken into account in the radio design.

2.2 The Need for a New PHY and MAC The state-of-the-art Bluetooth (LE) and Zigbee standardized radio’s for WPAN consume up to 100 times more than what is allowed for advanced health care applications. Their power consumption is at the level of 50–100 nJ/bit. The transceiver design in this paper has a target of 1 nJ/bit efficiency. Furthermore, the standardized radios do not meet the medical (proximity to human tissue) regulation. Neither do they support the combination of reliability, Quality of Service (QoS), low power, data rate and noninterference, which is required to address the broad class of body area network applications. There is a need for a PHY optimized for ultra-low power devices to operate on, in or around the human body for a variety of applications including medical and personal entertainment. A WBAN has a typical operation distance of 3 m within the boy area, and the power budget is stricter compared to WPAN (Fig. 8.3). The PHY should be of low complexity, in support of ISM bands as well of 2.36– 2.4 GHz MBAN for FCC, and the 2.485–2.5 GHz band for ETSI. To support the broad class of applications, a variable data rate is preferred.

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Fig. 8.3 Operational power of WBAN, WPAN, and WLAN systems Beacon CFP1

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There is also a need for a MAC optimized for WBAN operation. To satisfy both medical and consumer electronics (CE) applications with a uniform medium access control (MAC) protocol becomes a challenge. We propose a priority-guaranteed (PG) MAC protocol [2, 3]. With this protocol, data channels are separated from control channels to support collision-free high data rate communication for CE applications. Priority-specific control channels are adopted to provide priority guarantee to life-critical medical applications. Traffic-specific data channels are deployed to improve resource efficiency and latency performance. The frame format is shown in Fig. 8.4. As compared with the IEEE 802.15.4 MAC and its improved versions, the PG-MAC demonstrates significant improvement on throughput, energy efficiency, scalability, reliability, and co-existence with other networks, with a tolerable penalty on latency performance of bursty traffic in CE applications. The energy consumption per bit of data transmission is saved up to 60% as compared to IEEE 802.15.4. Most important of all, it can minimize the access latency of medical applications of higher priority, which is crucial for life-critical applications. Another proposal is to use dynamic channel selection by spectrum sensing and adaptive channel search. This would reduce the impact of interference in a crowded ISM band.

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Fig. 8.5 A schematic sketch of a wireless body area network node

2.3 Why Needs a WBAN a Low Power Radio? A WBAN node typically consists of sensor & read-out, actuators, analog-digital interface, microcontroller, power management unit, and a wireless transceiver. The complete system is powered by a small sized energy source. The sensor and read-out module is used to sense and convert the signals from the body, such as skin temperature, electroencephalography (EEG), electrocardiography (ECG), and electromyography (EMG) to the continuous analog signals. These analog signals are then sampled by the analog-to-digital converter (ADC) module. The microcontroller module carries out low level processing of the sampled signals, and manages the wireless transceiver module to transmit and receive the signals in accordance with the communication protocols being used. The power management module is used to regulate and distribute the power for all the consisting modules. The micropower module is the power source that supplies the sensor node. A sketch of a WBAN node is illustrated in Fig. 8.5. Low-power optimized designs at the block level can be indicated, but the success of these is largely dependent on their power optimization ability at the architecturallevel. This strengthens the role of architectural-level thinking and of in-depth interactions during the electronics design to avoid wasting time on sub-optimal system solutions. The ECG BAN application is taken further as an example to illustrate a power optimized architecture. A streaming ECG with commercial stateof-the-art components would consume 1.3 mW, which results in a 2-week lifetime. The target is 60 days lifetime, and therefore a 300 W power consumption of the total system for streaming ECG systems. With a duty cycling less than 30%, the transceiver in this paper is being designed with a continuous power consumption below 1 mW. For non-streaming ECG application, such as beat-detection only, stateof-the-art low power solutions exist. However, there are two trends in vital body signals monitoring that justify the development of new low-power modules. One is the tendency to ask for more bandwidth by measuring multiple complex signals at once. Another is the shrinking size of the nodes, such that only small thin-film batteries can be implemented. The storage capacity of these batteries is small, and can only be connected to body area nodes with ultra low-power consumption.

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2.4 WBAN Radio Market The Body Area Network field is an interdisciplinary area which could allow inexpensive and continuous health monitoring with real-time updates of medical records via Internet. Examples of applications are: EEG, ECG, EMG, vital signals monitoring (temperature (wearable thermometer), respiratory, wearable heart rate monitor, wearable pulse oximeter, wearable blood pressure monitor, oxygen, pH value, wearable glucose sensor, implanted glucose sensor, cardiac arrhythmia), wireless capsule endoscope (gastrointestinal), wireless capsule for drug delivery, deep brain stimulator, cortical stimulator (visual neuro-stimulator, audio neuro stimulator, Parkinson’s disease, etc. : : : ), remote control of medical devices such as pacemaker, actuators, insulin pump, hearing aid (wearable and implanted), retina implants, disability assistance, such as muscle tension sensing and stimulation, wearable weighing scale, fall detection, aiding sport training. These health applicaions are based on body-centric solutions for future wearable intelligent computer nodes. The same technology can provide effective solutions for personal entertainment as well, such as video streaming, audio streaming for headsets, surround sound streaming, data file transfer, image file transfer, small data transfer for remote controls, body motion captures, PC control signals, smart keys, identification, gaming. The existence of a body area network standard will provide opportunities to expand these product features, better healthcare and wellbeing for the users. It will therefore result in economic opportunity for technology component suppliers and equipment manufacturers.

3 Design Considerations of WBAN Radios 3.1 Requirements As indicated earlier, the use of a commercial low power radio would limit the lifetime of an ECG WBAN sensor to 14 days. An ultra low-power radio is needed with continuous power consumption below 1 mW. The use of the world-wide available 2.4–2.485 GHz ISM band is proposed, with an extension to the 2.36– 2.4 GHz FCC medical band and the 2.485–2.5 GHz ETSI medical band. The data rate should be programmable, to serve the diverse application space of a WBAN. A scalable data rate of 64 kbps to 1 Mbps has been chosen.

3.2 Duty Cycling and Data Rates One of the widely known solutions to minimize power consumption is duty cycling, which allows switching on the transceiver only for the instants where signals must

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be transmitted or received. Thus, the average power consumption is significantly lower than the continuous peak power. The duty cycling can be made more aggressive when the data rate is much higher than the sensor information rate. Duty cycle indicates how long the portion of time that the device is in the active mode. It is desirable that the node is awake mainly for active communication by keeping the overhead of control signaling small. Beacon listening takes a significant part of power consumption, especially for nodes with sporadic data communication. Regular beacon listening is used for synchronization and to get information about the control channel and the resource allocation. In a proper designed system, beacon listening per superframe should be avoided.

3.3 Tx Architectures Compared to transmitters in WPAN standards, the WBAN transmitter output level is lower. As the output power scales down, it becomes more difficult to maintain good overall power efficiency. A Tx frontend can be separated into a power amplifier (PA) stage and pre-PA stages. The pre-PA power consumption has to scale down proportionally with the output power to maintain a constant overall efficiency.

3.4 Rx Architectures Superheterodyne, low-IF, and direct conversion architectures are not the best candidates, because of complexity and power consumption. A subsampling receiver is promising, but is very challenging for narrowband systems due to noise folding and sampling jitter. A wideband FSK system is also promising, but high data rates are difficult to achieve. The proposed Rx architecture is based on a super-regenerative receiver and an envelope detector. This results in a design with a low complexity and low power consumption. The core block is an RF oscillator, which is periodically started and stopped by a quench oscillator.

3.5 Signal Processing A frame consists of a synchronization preamble (SHR and SFD), a physical layer header (PHR), and a data field. A preamble based timing acquisition algorithm has to be used, to compensate the unknown timing information between transmitter and receiver. The timing information is used to determine the start frame delimiter (SFD). A five-step

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acquisition algorithm is proposed using noise power estimation, signal detection, confirmation, two timing parameters estimation, and SFD detection. A scalable data rate is used by direct-sequence spread spectrum (DSSS) and/or duty cycling.

4 Analog BAN Radio IC Design 4.1 Receiver Frontend Known superregenerative receivers support only low date rate that can only accomodate a very limited number of WBAN applications. To overcome this limitation, we designed a high date rate frontend (up to 5 MHz) that enables much wider WBAN applications [4]. A basic sketch of a superregenerative receiver is shown in Fig. 8.6. The receiver frontend consists of the following parts: • Low-Noise Amplifier (LNA) &Voltage-Controlled Oscillator (VCO), providing selectivity and super-regenerative amplification • Differential Single-ended Converter (DSC) suppresses the VCO common-mode variations • Envelope detector (ED) detects baseband bit-stream • Quench wave generator (QWG) generates Iquench for the VCO The receiver front-end is shown in Fig. 8.7. A low power consumption is achieved by a high Q external inductor, and the use of a complementary cross-coupled VCO with bond-wire inductance. There are two operational modes: 1. for Iquench < Icritical selectivity mode 2. for Iquench > Icritical super-regeneration (amplification) mode The critical current floor is programmed by a DAC and the saw-tooth waveform is made by an analog block (Fig. 8.8).

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4.2 Receiver Analog Baseband The RX analog baseband (BB) is composed of three blocks: a variable gain amplifier (VGA), an ADC and a bias current generator (BCG). The VGA [5] includes an analog integration function. It can be used either as an amplifier or as an integrator. The BCG generates the various bias currents required for the baseband of the receiver to reduce the number of external bias currents. The VGA has an open-loop first stage to save power. The second stage has a programmable gain and bandwidth (Fig. 8.9). The ADC is designed for a 5 MHz analog bandwidth (10 Msps Nyquist). An 8 bit resolution has been chosen. The ADC architecture is based on asynchronous successive approximation, where the power consumption is proportional to the sample rate [6, 7]. There are three control components in the system: main control, comparator control and DAC control. The choice has been made to use start/ready flags (instead of delay lines) and to use custom logic (instead of standard CMOS cells). Timing and schematic are shown in Fig. 8.10.

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4.3 Transmitter Choice The transmitter (TX) consists of a VCO, a power amplifier (PA), buffers as well as biasing circuitry [8]. It supports amplitude modulation in the form of amplitudeshift keying (ASK) and on-off keying (OOK) with pulse-shaping, and its 10 Mbps data rate makes it capable of handling data intensive applications such as different WBAN waveform transmission or high quality personal audio/video streaming (Fig. 8.11).

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Fig. 8.11 Transmitter architecture

Fig. 8.12 Circuit details of the WBAN transmitter

The 2.4 GHz carrier is generated by a VCO. The amplitude modulation (on/off) is directly applied at the PA, which results in faster start-up and no spectral artifacts. A swing detector adjusts driving level for optimal power efficiency. A digital pulseshaping technique is being used to improve spectral efficiency. More circuit details are shown in Fig. 8.12. The VCO is a complementary cross-coupled oscillator, with on-chip integrated inductor, a switched varactor bank and varactor analog tuning. The PA is made of 15 pseudo-differential parallel NMOS pairs in class-AB operation.

4.4 SoC The system-on-chip is based on analog Tx and Rx, a phase-locked-loop system, and digital baseband [9]. The digital baseband is designed to support a maximum date rate of 1 Mbps with an oversampling factor of 3. The phase-locked loop is shown in Fig. 8.13. The digital baseband part includes the blocks of pulse shaping for data transmission, data spreading and despreading to achieve scalable data rates, reliable timing synchronization and data detection algorithms, and CRC-16-CCITT encoding and decoding for packet validation. The digital baseband generates accurate RF Tx

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Fig. 8.13 Phase-locked-loop to tune the radio channel in Tx and Rx mode

Fig. 8.14 Clock generation part implemented in the digital baseband section

and Rx timing (by delay lines), autonomous DC offset correction, automatic gain control, and receive timing tracing. The clock generation part is shown in Fig. 8.14. It is based on two delay lines with a 750 ps phase and duty cycle resolution. The SoC diagram is shown in Fig. 8.15. The transceiver chip photograph is shown in Fig. 8.16. This chip is implemented on an application-specific integrated circuit (ASIC) using a standard 90 nm complementary metal–oxide–semiconductor (CMOS) technology.

4.5 Measurements The power consumption of the WBAN radio is more than one order of magnitude lower than commercially available transceivers. The measured power consumption at 1.2 V when transmitting an OOK packet at 0 dBm is 2.5 mW. For a 10 dBm

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Fig. 8.16 Chip photograph of WBAN transceiver

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Fig. 8.17 Power breakdown of the WBAN transceiver

Fig. 8.18 WBAN Transceiver comparison with state-of-the-art

output level, the transmitter power consumption is 900 W. For Rx, the PLL, RF frontend, analog and digital baseband blocks consume 1,100,468,48 and 199 W, see Fig.8.17. The measured performance of the transceiver is compared to state-of-the art in Fig. 8.18. In a wireless transmit-receive link we verified that there were no received packet errors (i.e. below 0.002) within 14 m of transmission distance at a data rate of 256 kbps. At a 64 kbps mode, the maximum distance is up to 30 m. It is sufficient to satisfy the required communication range of WBAN, which is typically within a few meters.

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5 ECG Example Cardiac monitoring is one of the earliest adopters of wearable healthcare technology and the impact of technology on the efficiency of care and reduction of hospitalization has been shown in various studies. Our first system is based on an ECG necklace node, [10, 11, 12]. The node transmits/receives to a basestation or to a smart phone (Fig. 8.19). The ECG node can be used for 24/7 connectivity to the public network. The second system will be based on a thin, comfortable patch ECG node (Fig. 8.20). The starting point was a necklace node with commercial state-of-the art components. The power consumption breakdown for such a sensor node is shown in Fig. 8.21. The current necklace system uses the WBAN transceiver and it consumes 362 W. The power breakdown of the ECG necklace based on Imec WBAN transceiver is shown in Fig. 8.22. The RF transceiver is not the dominant part anymore. In an ECG application, the signal could be processed locally to detect the R-peak. RR interval information is sent wirelessly at each detected beat. Power optimization at architectural-level has been carried-out during integration without affecting system functionality. The estimated power consumption results are illustrated in Fig. 8.23. It follows that the total power consumption for the ECG application equals 96 W

Fig. 8.19 ECG necklace node and smart phone basestation

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Fig. 8.22 Imec WBAN necklace. The total power consumption equals 362 W

Fig. 8.23 Relative power consumption estimated for the ECG beat-detection application; 37% of the power is attributed to the DSP, radio (RF) and analog-to-digital converter (ADC) blocks; the total power consumption equals 96 W

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6 Conclusions An ECG patch worn on the body will have difficulty to be on the air frequently with the power consumption of state-of-the-art transceivers. An ultra low-power WBAN transceiver is designed with optimized sensitivity for high data rates. The 1 nJ/bit solution is a single chip OOK transceiver fully optimized for on- and off- body communication operating in the 2.36–2.5 GHz medical BAN and ISM band. The transceiver is integrated in ECG necklace and patch monitoring systems. The transceiver is implemented in 90 nm CMOS and occupies 2.4  1.85 mm2 .

References 1. IEEE P802.15.6/D02, Draft trial-use standard; Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Wireless Personal Area Networks (WPANs) used in or around a body, Dec 2010, http://grouper.ieee.org/groups/802/15/pub/LB66/LB66.html 2. Y. Zhang, G. Dolmans, A new priority-guaranteed MAC protocol for emerging body area networks, in Fifth International Conference on Wireless and Mobile Communications, ICWMC 2009, Cannes/La Bocca, France, 23–29 Aug 2009, pp 140–145 3. Y. Zhang, G. Dolmans, Priority-guaranteed MAC protocol for emerging body area networks. Ann. Telecommun., special issue on Body Area Networks applications and technologies (2010). doi:10.1007/s12243-010-0232-9 4. M. Vidojkovic et al., A 500 W 5 Mbps super-regenerative RF front-end, in European SolidState Circuits Conference (ESSCIRC), Seville, Sept 2010 5. C. Zhou et al., A 56uW VGA with 5MHz bandwidth and 47dB gain-range in 90nm CMOS, in VLSI-DAT, Hsinchu, 26–29 Apr 2010 6. P. Harpe et al., A 12fJ/conversion-step 8bit 10Ms/s asynchronous SAR ADC for low energy radios, in European Solid-State Circuits Conference (ESSCIRC), Seville, Sept 2010 7. P. Harpe et al., A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS, in ISSCC 2010, San Francisco, 6–11 Feb 2010 8. X. Huang, P. Harpe, X. Wang, G. Dolmans, H. de Groot, A 0dBm 10Mbps 2.4GHz ultra-low power ASK/OOK transmitter with digital pulse-shaping, in RFIC 2010, Anaheim, 23–25 May 2010 9. M. Vidojkovic et al., A 2.4GHz ULP OOK single-chip transceiver for healthcare applications, in ISSCC 2011, San Francisco, 20–24 Feb 2011 10. V. Pop et al., Improving power diagnosis by architectural modeling in wireless autonomous transducer solutions, in Globecom 2010, Miami, Dec 2010 11. L. Huang et al., Ultra low power wireless and energy harvesting technologies – an ideal combination, in Proceedings IEEE International Conference on Communication Systems (ICCS), Singapore, Nov 2010 12. L. Huang et al., Performance evaluation of an ultra-low power receiver for Body Area Networks (BAN), in Personal, Indoor and Mobile Radio Conference (PIMRC), Istanbul, Sept 2010

Chapter 9

Low Power RF Power Harvesting Enabling More Active Tag Functionality Tim Piessens, Yves Geerts, Wim Vanacken, Eldert Geukens, Bram De Muer, Tim Butler, and Bob Hamlin

Abstract This paper presents the analog part of a production integrated circuit (IC) for EPC Gen2 UHF RFID applications in the 900 MHz band. The tag is unique for its on chip 32 kB non-volatile memory (NVM) I2C functionality and its large reading and writing distance. To achieve these goal a power oriented architectural and block level design approach has been followed. The main considerations concerning energy harvesting and RFID communication are presented in this paper and some specific building blocks are more elaborated like a 2.5% accurate clock reference consuming only 0.3 A and a 6.25 s TARI ASK demodulator. The chip is currently in production and is going to be used in aviation for airplane parts logging.

1 Introduction 1.1 RFID Tag Classification Although Radio-Frequency IDentification (RFID) technology is available since the second world-war [1], it took until recent developments in semiconductor and telecommunication technologies for RFID to become ubiquitous. Currently the term RFID is a flag covering a broad range of applications from cheap anti-theft systems in retail to expensive and complicated long-life logbook type applications. A first classification can be made between active and passive devices based on the presence of a battery on the tag or not. Table 9.1 shows a comparison between active

T. Piessens () • Y. Geerts • W. Vanacken • E. Geukens • B. De Muer ICsense, Gaston Geenslaan 9, 3001 Heverlee, Belgium e-mail: [email protected] T. Butler • B. Hamlin TEGOinc, 375 Totten Pond Road, Waltham, MA, 02451 USA M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 9, © Springer ScienceCBusiness Media B.V. 2012

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Table 9.1 Passive versus active RFID tags

Power Frequency

Passive None 135 kHz or 13.56 MHz

Read range Tag life Tag costs Readers

Few meters Up to 10 years $.05 Higher cost

Active Battery ISM Bands 433 MHz, 900 MHz, 2.45 GHz Tens of meters 3–8 years $15–50 Lower cost

EPCglobal Gen-2 Passive None 860 MHz–960 MHz >Few meters 10 years and longer $0.1–4 Higher cost

and passive tags [2]. Classic passive tags are using near-field coupling to transmit power and data. Due to the d13 attenuation in this frequency range, the operating distance and functionality of these type of tags is very limited. Communication is performed by load modulation of the incoming wave. They are mostly used in retail and inventory management and in animal husbandry. When higher security, environmental sensoring or read/write functionality is needed, the active tag comes into the picture. Since power is not a real issue for the tag, higher frequencies and thus far field communication can be used, reducing the attenuation by d1 and thus drastically increasing the reader distance.

1.2 EPCglobal Gen-2 Passive Tags This paper focusses on tags made for the EPC Gen2 standard [3] which was approved in December 2004. By its use of ultra-high frequencies (UHF), more energy can be harvested from the incoming radio wave. However to ensure better power efficiencies in practical implementations, the frequency needs to be limited. For instance power losses due to substrate capacitance are given by (9.1) [4] Ploss D

Rsub 1 2 1 v 2  v2 .!Csub /2 Rsub 2 Rsub 2 C .!Csub /2

(9.1)

However, with the EPC Gen2 tags, with a clever architectural and circuit implementation, sufficient energy can be harvested to provide active tag functionality in a passive device. Due to the absence of a battery, the passive tags provide much longer lifetimes without sacrifying the possibility to go beyond identification: the possibility to integrate sensors [5], higher memory ([6, 7] and This Work), more digital processing and I2C communication, including powering of external devices (This Work). All this extra functionality opens up plethora of new applications like decentralized logbook management in e.g., aviation [7], transportation, active monitoring in healthcare, better control of goods in logistics, anti-theft control, : : :

9 Low Power RF Power Harvesting Enabling More Active Tag Functionality Fig. 9.1 Basic ASK (a) and PSK (b) modulation implementation

a

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b

This all leads to harsh specifications in the design of the tag. The front-end not only needs to be tailored for optimal energy harvesting but also for minimal power consumption at all levels, analog and digital. A thorough design methodology aimed for minimizing the power consumption is a must for successful design.

1.3 Backscattering Since the tag does not have a power source, its most efficient communication mechanism is to backscatter the incoming wave. By modulating the reflection coefficient of the antenna, the reflected wave is changed and detected by the reader. Since the reflection coefficient is modulated by modulating the impedance as illustrated in Fig. 9.1, two basic modulation types are possible: Amplitude Shift Keying (ASK) and Phase Shift Keying (PSK). In low frequent applications, with low bitrates, one state is much more active as the other. An optimal choice for communication is than to use ASK with the most active state perfectly matched and the other state maximally unmatched, with a short or open chain at the antenna. This gives optimal power transfer in the most frequent state and optimal communication. For Gen-2 tags, with high bitrates, this would lead to half of the power being wasted. A more optimal modulation is to use a symmetrical mismatch in both states, giving a modulation indec of ˙ m for ASK and ˙ jm in PSK [4]. Both modulation schemes will provide the same reflected power: Pbs D m2

Pavail Lant

(9.2)

with Lant the antenna loss factor and Pavail the available power at the antenna. For the PSK case, the remaining power can be harvested for the ASIC:   (9.3) PRF;in D 1  m2 Pavail

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However, to create the needed modulation index in the ASK case, a considerable amount of power will be dissipated in the resistor that modulates the index. This series resistor can be calculated as: Rseries D

4m Rantenna 1  m2

(9.4)

Resulting in the following available power: PRF;in D

1  m4 .m C 1/2

Pavail

(9.5)

For this work a PSK implementation has been chosen.

2 Chip Architecture Figure 9.2 shows the architecture of the proposed tag. Key feature of this ASIC the high amount of NVM memory present. While passive tags in general have a limited memory between 196 and 512 bits [8], this ASIC has a non-volatile memory of 262,144 bit or 32 kB. This high memory tag opens up a world of possibilities since the memory allows retention of e.g., • Total life history information and usage profile of a tagged item which is important in logistics and expedition. • Original creation record, maintenance & repair events of tagged parts for e.g., aviation parts. • Access all stored information without dependency of a network, which adds reliability to the log like e.g., in healthcare. • Storing of security certificates and encrypted data for e.g., ID cards and Medicare. The digital controller is doing the communication protocols according the EPCglobal Gen-2 standard [5] and has an I2C interface to connect the tag to other external components like sensors, memory, displays : : : and even provide sufficient power to feed these components. The analog part consists of the PSK modulator

PSK modulator

Data decoder

Power Management Command processor

ASK demodulator

Data encoder

Memory Manager

Regulators Rectifier

NVM Memory Charge pump

Fig. 9.2 Architecture of the proposed ASIC

I2C

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and an ASK demodulator for communication between tag and reader and a power management block which generates several voltages from the incoming rectified voltage. To save power, the digital is running on the lowest possible voltage for the technology. Also a specific reading supply is generated to communicate with the NVM macro. A charge pump with integrated high frequency oscillator is included to create the higher supply voltage needed for a write operation. Other general analog building blocks on the tag are an accurate 3 MHz clock generator to drive the digital, a persistance block and a random number generator for unique addressing of the tag.

3 Analog Building Blocks 3.1 RF Rectifier To generate the internal DC supply voltage a Dickson’s charge pump, modified for UHF multi-stage rectification has been used as depicted in Fig. 9.3. The rectifier is constructed with MiM capacitors and RF Schottky diodes available in the technology. The available DC voltage at the output of the rectifier can be calculated [9] as follows: VDC D

p Pavail :RANT :8  GAIN RECT  VDIODEDROP  ZOUT :ILOAD

GAIN RECT D

(9.6)

N:˛ 1C

N:GSUB GANT

(9.7)

BVDD

RFIN

GND

Fig. 9.3 4-stage Dickson’s rectifier schematic

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VDIODEDROP

ZOUT D 

:ILOAD D nVT :N:ln IS

N 2 :2:RANT :˛ 2 : 1C

N:GSUB GANT

 D



CC C CPAR CC



N .CC C CPARA/:f

(9.8)

(9.9)

2 (9.10)

1 the antenna resistance, N the number of diodes used in the With: RANT D GANT charge pump, GSUB the substrate conductance, ˛ the capacitive division between CC and the parasitic capacitance at the pumping node,  the coupling capacitor impedance transformation and  an averaging factor to compensate the true current profile. As calculated in (9.6), the incoming energy is converted into an output voltage. Several effects contribute to the loss in output voltage. For the rectifier the coupling capacitor and number of diodes are the most important parameters. The tag presented in this work has a low antenna resistance of 12˝, to be able to use Q-boosting of the coupling. The number of diodes has been determined to be able to deliver a minimum needed output power for the maximal writing distance, maintaining a high efficiency. For smaller reading distances the output voltage of the rectifier can become too high for the safe operating region of the process technology. Therefor a smart limiter has been designed as depicted in Fig. 9.4. The limiter needs to combine a fast turn on time, to be able to limit instantaneously a closeby incoming wave, with little variation on the limiting level, cause this would reduce the maximum writing distance. Typical solution use thresholds based on MOS VT ’s [10] and thus need to take sufficient safety margin with respect to process variations, leakage and temperature. To overcome this limitation, the architecture starts up with a fast and inaccurate reference, limiting the supply voltage low enough. When the system’s bandgap has started up, the limiter switches over references. Since the bandgap provides a much more stable reference the output voltage can be set to a higher value, increasing the amount of stored energy (CV2 ). In the same time the bandwidth of the limiter set pushed further, since due to a more stable bias current, loop stability can be guaranteed for higher bandwidths. By extending the limiters bandwidth, the voltage can be set even higher, since the limiter can react on the transients imposed by the ASK modulation.

3.2 Clock In a Gen-2 communication system, the clock generator is one of the most important building blocks due to the high accuracy needed to enable communication [5, 11].

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Vdd

+ − VBG

Fig. 9.4 Schematic of the voltage limiter at the rectifiers output

On the other hand, since the clock is during communication always on, its power consumption is largely limiting the maximum distance on which the tag still can operate. Figure 9.5 shows the schematic of the current starved oscillator used to provide a stable clock frequency of 2.75 MHz. By synthesizing the clocks bias current for a specific temperature coefficient in the band gap, the frequency only has a 0. 5% variation over the full temperature range from  40 ı C to 125 ı C. Over temperature and supply variations, the clock frequency is kept within 2. 5%. The duty cycle varies from 37 to 60% over PVT. The total power consumption of the clock is 0.3 A. The clock does not to be trimmed for production to meet the EPC Gen2 specification.

3.3 ASK Demodulator Figure 9.6 shows the schematic of the integrated ASK demodulator. The ASK demodulation needs to respond as quickly as possible to an incoming wave without unwanted togglings due to the ramping up of the power and reference signals. This is solved by adding a fixed offset in the biasing chain of the comparator following the envelope demodulator.

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Duty cycle restorating level shifter

Fig. 9.5 Schematic of the current starved oscillator Vdd

− +

Fig. 9.6 Schematic of the implemented ASK demodulator

The communication frequency goes up till 160 kHz. This corresponds with a Type A Reference Interval (TARI) of 6.25 s. The ASK demodulator complies with all specified TARI’s and ASK modulation types set in the EPC Gen2 specification. Its current consumption is only 200 nA.

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3.4 Random Number Generator The Gen2 specification allows an infinite number of tags to be in the field of the reader. The protocol is designed to be able to handle this and several anti-collision algorythms have been developed for Gen2 UHF RFID tags. These algorithms require a unique identifier for each tag in the field. Since a hard coded unique identifier is logistically hard to achieve in a disposable like a RFID tag. For this reason an analog random number generator (RNG) is implemented in this work. During the tag start-up a random number is generated and used as a unique identifier for the tag. Due to its true randomness, the probability of having two identical identifiers within the range of one reader is very small. Since digital random number generators require quite some computational power, we have opted to implement an analog random number generator. The RNG consists of four uncoupled noisy clock generators. Their outputs are XOR’ed to form a random bit stream sampled by the digital. The RNG starts up as soon that there is sufficient analog power. Once the digital has started up, it samples the random stream and shuts down the RNG. Only during this limited time a 1.8  A current is needed to generate a true random number. Since the total start-up time of the digital is dependent on the incoming power, this gives another level of randomness next to the randomness due to the high clock jitter. The random number generator has been measured and compared with the Mersene Twister algorithm [12] and shows at least equal randomness.

4 Tag Asic and Prototype Figure 9.7 shows a chip photograph of the implemented RFID tag. The 32 kB of memory can be clearly seen in the middle of the ASIC. Left and right, two rectifier structures can be observed. In this way the tag can operate on two differently

Fig. 9.7 Chip photograph of the RFID tag

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Fig. 9.8 Prototype (a) and product version (b) of the RFID tag

orientated antennas for increasing the energy harvesting or the rectifier can be connected as a Greinacher full wave rectifier. Figure 9.8 shows the measurement prototype of the presented tag and an application production example. The tag is fully compliant with the EPC Gen2 specification. The production samples are available in several forms with antenna on foil. The tag can perform read operation from a distance above 5 m and write operations from a distance higher than 1 m. Even with small antenna structures and attached to metal, reading distances of a few meters can be obtained. Currently tags are in full production in different series for a wide variety of antenna structures.

5 Conclusion In this paper a selection of analog building blocks from a production high memory Gen2 RFID tag have been presented. Starting form the design consideration on a high level based on the EPC Gen2 specification, the analog blocks have been designed aiming at a maximum reading and writing distance. Therefor not only very careful and power oriented state-of-the-art building block design was needed but a constant system and architectural consideration with feedback between RF, analog and digital design. The building blocks touched in this paper are the power harvesting stage, the high accuracy clock, the ASK demodulator and the random number generator. The RF rectifier has been designed for an optimal power efficiency. For high incoming powers a voltage limiter has been implemented to protect the circuitry. By switching the references of this block a high accuracy with a high speed could be combined with a low power consumption. The communication protocol requires a very stable clock oscillator. The presented clock achieves a 2.5% accuracy over temperature and supply variation by carefully designing the temperature coefficient of the bias current. The tag is currently in production and used in amongst others airplane part tracking applications.

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Acknowledgements The authors wish to thank Tim Morlion and Ramses Valvekens of EASICS for their contribution to this chip development.

References 1. M. Roberti, “The history of RFID technology.” [Online]. Available: http://www.rfidjournal. com/article/view/1338 2. J.-P. Curty, M. Declerq, C. Dehollain, and N. Joehl, Design and Optimization of Passive UHF RFID Systems. Springer, 2007. 3. EPCglobal, “Epc radio-frequency identify protocols class-1 generation-2 UHF RFID protocol for communications at 860-MHz - 960 MHz version 1.2.0.” [Online]. Available: http://www. gs1.org/sites/default/files/docs/uhfc1g2/uhfc1g2 1 2 0-st%andard-20080511.pdf 4. U. Karthaus and M. Fischer, “Fully integrated passive UHF RFID transponder IC with 16.7-w minimum RF input power,” IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1602– 1608, Oct. 2003. 5. J. Yin, J. Yi, M. K. Law, Y. Ling, M. C. Lee, K. P. Ng, B. Gao, H. C. Luong, A. Bermak, M. Chan, W.-H. Ki, C.-Y. Tsui, and M. Yuen, “A system-on-chip EPC gen-2 passive UHF RFID tag with embedded temperature sensor,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2404–2420, Nov. 2010. 6. H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. Mukaida, T. Ninomiya, T. Ohkawa, S. Masui, and K. Gotoh, “A passive UHF RF identification CMOS tag IC using ferroelectric RAM in 0.35-m technology,” IEEE Journal of Solid-State Circuits, vol. 42, no. 1, Jan. 2007. 7. B. Hamlin, “Beyond identification - high memory RFID in aviation,” in SAE AeroTech Congress, Nov. 2009. 8. C. Swedberg, “Nxp boosts epc gen 2 tag memory, performance.” [Online]. Available: http:// www.rfidjournal.com/article/view/3637 9. R. E. Barnett, J. Liu, and S. Lazar, “A RF to DC voltage conversion model for multi-stage rectifiers in UHF RFID transponders,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, Feb. 2009. 10. N. D. C. D. M. J. Curty, J. P. Joehl, “Remotely powered addressable UHF RFID integrated system,” IEEE Journal of Solid-State Circuits, vol. 40, no. 11, Nov. 2005. 11. C. Dorio, “Watching the clock,” Jan. 2006. [Online]. Available: http://www.rfidjournal.com/ article/view/2040/1 12. Nishimura and Matsumoto, “The mersenne twister homepage.” [Online]. Available: http:// www.math.sci.hiroshima-u.ac.jp/‘m-mat/MT/emt.html

Chapter 10

Low Power RF Frontend for Wireless Sensor Networks Frank Henkel, Thomas Leineweber, Mohamed Gamal El-Din, and Ralf Wilke

Abstract An essential requirement for Wireless Sensor Networks (WSN) is the low power consumption, so that the maximum time of operation can be achieved with the available energy. Particular the RF Frontend has an important role, since most of the energy is consumed here. After a short introduction the different RF Frontend Architectures are discussed in Chap. 2. Chapters 3 and 4 give details about the frontend circuit implementations for the RX and the TX path with the focus on low power consumption, respectively.

1 Introduction to Wireless Sensor Networks Wireless sensor networks (WSNs) have become popular for monitoring functions used in military, agriculture/farming, or industrial applications. The network consists of several single nodes whose number can range from at least two to over a thousand. Each of these nodes is connected to at least one sensor which can in general measure dimensions of any kind; common examples include temperature, light, pressure, humidity, sound, speed etc. [1]. The values of the measured data are digitized and transmitted through the network to a dedicated base station. In a star network configuration the nodes communicate directly to the base station while in a more advanced application the nodes communicate with each other to finally pass the data to the base station. This multi-hop network allows extending the network range, but each node must be capable of also receiving data. For transmitting and receiving each node is equipped with a wireless transceiver radio and antenna. A microcontroller and energy source complete the WSN node. The energy source might be a simple battery but with the goal for maintenance free

F. Henkel () • T. Leineweber • M.G. El-Din • R. Wilke IMST GmbH, Carl-Friedrich-Gauss-Str. 2, 47475 Kamp-Lintfort, Germany e-mail: [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 10, © Springer ScienceCBusiness Media B.V. 2012

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sensors more advanced concepts such as energy harvesting need to be applied. In any case the available energy is limited which leads to the demand for low power devices. One popular standard used for WSNs is the IEEE 802.15.4 which operates in unlicensed ISM bands.

2 RF Frontend Architectures The RF frontend can be split in a receiver (RX) and a transmitter (TX) path. On the RX side the signal is amplified by a Low Noise Amplifier (LNA) followed by a mixer as downconverter. On the TX side there is the Power Amplifier (PA) driven by the upconverter mixer if e.g. not a direct PLL modulation approach is applied. The RF interface of the frontend may be either differential or single ended. A fully differential structure will benefit from higher immunity against common mode distortion but will require an external balun if the antenna is single-ended. It might be possible to share a common RF IO for LNA input and PA output because frontend does not receive and transmit at the same time but this will require integration of the antenna switch or power-down of the unused path. For a low-power application there are two main configurations: direct-conversion (also known as zero-IF) and low-IF architecture each with its own advantages and disadvantages. The direct-conversion architecture is known for its simplicity since the absence of the image frequency eases the base band signal filtering. However, its major drawbacks are DC offsets due to LO-self mixing, spurious near DC due to second order intermodulation and flicker noise which may severely degrade the bit error rate [2]. According to [2] high-pass filtering is possible to circumvent this if the flicker noise corner is low enough. To achieve this some approaches suggest passive mixers [3, 4] which indeed minimizes the flicker noise but also suffers from reduced RF gain (higher noise floor) and the need for a strong LO amplitude and hence higher power consumption. Furthermore the above mentioned DC offsets and intermodulation products in direct conversion receivers need high effort in calibration techniques [5] which may compensate the benefits of the simple signal path architecture. As summarized in [6] the zero-IF approach may indeed lead to higher chip area. The alternative to direct-conversion is the Low-IF approach [2, 7] which overcomes the problems of LO-self-mixing and flicker noise by converting the RF frequencies to a base band a few MHz apart from DC. This enables high-pass filtering without losing signal information. Since the TX PA will draw a significant amount of the total supply current budget the efficiency of the PA should be maximized for low power applications. It is well known that nonlinear PAs achieve better efficiency than linear versions but their use is only possible with constant envelope modulation.

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The classical transmitter requires a mixer as part of the TX frontend to convert the analog baseband frequencies to RF. However, some approaches suggest direct modulation of the VCO [6, 7] which is very effective because it eliminates the need for the analog TX base band path including the upconverter.

3 RX RF Frontend Circuits The main building blocks of the RX RF frontend circuits, LNA and downconverter mixer will be discussed in this section.

3.1 LNA The low noise amplifier is an essential building block in wireless sensor networks transceivers. Its function is to amplify the received signal with minimum added noise. In [8] the noise generation mechanisms in CMOS transistors were discussed and the optimum source impedance for minimum noise generation was driven. If we consider the transistor as a two port network the noise figure can be written in terms of equivalent resistances and conductance as F D Fmin C

2  2 i Rn h Gs C Gopt C Bs C Bopt Gs "s

Fmin D 1 C 2Rn

Gu C Gc2 C Gc Rn

(10.1)

# (10.2)

where Gopt and Bopt are the source optimum conductance and susceptance [8]. An essential problem in designing a low noise amplifier (LNA) is that the optimum impedance for minimum noise generation is not necessarily the optimum impedance needed for input matching. Using MOS devices to implement the LNA adds another problem which is that the input impedance is mostly capacitive. Several amplifier topologies were presented to address this problem and theoretically there are clear differences in their noise, gain and power consumption characteristics. Nevertheless, as these structures are investigated the differences in the realized noise figures become smaller and the main retention is the loss associated with the passive elements used to realize the input matching. In this section two well known LNA structures namely shunt-series feedback LNA and inductively degenerated common source LNA will be discussed and compared regarding their noise figure, gain and power consumption characteristics. The target specifications for the LNA input stage are summarized in Table 10.1, special emphasis was placed on lowering the power consumption making this LNA suitable for operation in wireless sensor nodes.

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Table 10.1 LNA target specification

Noise figure Gain Power consumption Output referred IP3 Frequency Technology

<3 dB >10 dB 6 mW 10 dBm 2.4–2.5 G 150 nm CMOS

Fig. 10.1 Shunt-series feedback LNA

3.1.1 Shunt-Series Feedback LNA Using shunt-series feedback as shown in Fig. 10.1, an input impedance with a real part can be realized over a relatively wide bandwidth. Since the IEEE 802.15.4 frequency bands extends from below 1 GHz to above 2 GHz [9], this topology represents an attractive LNA candidate for multiband operation. An approximation of the input impedance, gain, and noise figure of this amplifier is given by Eqs. 10.3–10.5 [10]. Zin 

RL C RF 1 C jAj

(10.3)

jAj  gm .RL k RF / 2 1  NF  1 C 3 gm Rs



1 1 C 2 Rs RF Rs



 C

f fT

(10.4) 2

2 Rs  gm Rs C 3 RF

(10.5)

Based on the same concept the current reuse shunt-series feedback LNA Fig. 10.2 was introduced in [10]. Through stacking a P-MOS with an N-MOS the transconductance is increased for the same bias current, thus giving the designer a higher degree of freedom in choosing the feedback resistance Rf and load resistance RL . Another advantage is that the two transistors are kept in the saturation region during

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Fig. 10.2 Shunt-series feedback LNA with current reuse

Fig. 10.3 NF, Gain and input/output matching of the shunt-series feedback LNA

their operation. To compensate for the gate capacitance an additional inductor Lg is needed in front of the gate terminal. In this work this inductor is inserted in series with the feedback resistance; through this way the input as well as the output capacitance can be compensated. Using Eqs. 10.3–10.5 an LNA for operation in the 2.4–2.5 GHz band was designed using 150 nm CMOS technology with thick metal for inductors. Figure 10.3 shows the small signal performance of the shunt-series LNA, the input matching and output matching is better than 10 dB over the band from 1 to 3 GHz and the gain is higher than 9 dB. Most importantly the noise figure is below 3.1 dB in the same band. In the band from 2.4 to 2.5 GHz the noise figure is 2.8 dB. This high noise figure can be attributed to the thermal noise of the resistive feedback network. Another drawback of this topology is the high current consumption, in our case the amplifier draws 11.7 mA from the 1.8 V supply voltage. The current can be reduced through reducing the transistors gm , but as a result the gain is reduced and the noise figure increases. Figure 10.4 shows the input referred IP3 to be 8 dBm for two-tone signals of 2.399 and 2.401 GHz. Another problem with this LNA is that it has poor reverse isolation, due to the feedback path.

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Fig. 10.4 Two tone linearity test of the shunt-series feedback LNA

Fig. 10.5 Inductively degenerated common source LNA

3.1.2 Inductively Degenerated Common Source LNA The inductively degenerated common source amplifier shown in Fig. 10.5 (which is a series-series feedback amplifier) is another way to match the input of the LNA to the 50  source impedance. In contrast to the shunt-series feedback LNA no resistance with its associated thermal noise is needed.

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Fig. 10.6 NF, Gain and input/output matching of the common source LNA

Using the small signal model of the transistor T1 and neglecting the gate-drain capacitance Cgd , the input impedance can be written as Zin D s.Lg C Ls / C

1 gm C Ls sCgs Cgs

(10.6)

The inductance Lg plays a helping role in compensating the gate capacitance since the main role of Ls is to tune the real part of the input impedance through the m term Cggs Ls . The cascoding transistor T2 is intended to isolate the input from the output and thus improving the reverse isolation, also it helps to reduce the effect of transistors T1 Cgd . The design process as shown in [8] starts by determining the optimum device width Wopt D 3!LC1ox Rs . Since the allowed drain current is known (from power requirements) the device bias can be determined. Knowing the source impedance (Rs ) and the device transconductance gm , the degeneration inductance Ls can be calculated using the Eq. 10.6. The inductance Lg can be calculated such that together with Ls they resonate the gate capacitance Cgs . The size of the cascading transistor is initially chosen to be equal to the size of the transistor T1, this size is latter optimized to achieve the linearity goals. The Inductance Ld is chosen to resonate the output capacitance of the cascading transistor T2 . These guidelines were used to design an LNA for operation in the 2.4–2.5 GHz band for wireless sensor applications using a digital 150 nm CMOS process. The small signal performance of the designed LNA can be seen in Fig. 10.6. In the band of interest (2.4–2.5 GHz) the amplifier has a gain of 12 dB and input and output return loss greater than 14 and 11 dB, respectively. The noise figure in the target band is smaller than 2.4 dB with current consumption of 2.8 mA, which is significantly smaller than that of the shunt-series feedback LNA. Although

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Fig. 10.7 Two tone linearity test of the shunt-series feedback LNA

Fig. 10.8 NF variation with bias current using different technology options

the inductively degenerated common source LNA has a theoretical noise figure which is superior to the shunt–series feedback LNA, the difference in noise figure performance is not as expected (Fig. 10.6). In the commonsource LNA a large inductor is used to resonate the small gate source capacitance. This large inductance is difficult to realize with low loss (high quality factor) due to the loss in the conductive silicon substrate used in conventional digital CMOS processes. For realizing high quality passives some CMOS processes offer the possibility of back etching the substrate under the inductance and replacing it with a dielectric, this option was investigated together with the option of using external components for the gate inductance Lg . Figures 10.8 and 10.9 show the effect of the supply

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Fig. 10.9 S21 variation with bias current using different technology options Table 10.2 Comparison of LNA key parameters Ref [11] This work This work This work

Tech CMOS 150 nm CMOS 150 nm CMOS 150 nm CMOS 150 nm

Freq (GHz) 2.46

Pdc (mw) 4.65

S21 (dB) 14

NF (dB) 2.36

2.5

5.04

12.3

2.303

2.5

5.04

13.6

1.5

2.5

5.04

14.1

1.1

FOM 34.7 External matching 31.9 Integrated inductor 36.2 High Q integration 38.9 External matching

current (and eventually the transistor transconductance) on the noise figure and gain (S21 ) using different technology options for realizing Lg . It can be seen that the losses in the gate inductor plays a crucial role in determining the noise figure and the gain of the LNA and thus the NF of the whole receiver. To be able to compare this LNA to other results the figure of merit below is used [11] (Table 10.2)   FOM D 10log 100

S21.lin/ f02 .F  1/ Pdc .mW /



OIP3.mW / Pdc .mW /

 (10.7)

3.1.3 Passive Elements Options (Full Integration, High Quality Integrated Passives, External Components) Securing the necessary energy for powering the wireless nodes and its costs is an important aspect which should be regarded during the design of the whole network [12]. The use of external components for input matching offers the lowest noise figure and power consumption, nevertheless the economical side of this choice

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Fig. 10.10 Operation cost vs time using different passive technology options

should also be considered. Although both options, using external components or reverting to the total integration solution is a question of costs, it is important to differentiate between two kinds of costs, fixed costs and variable costs. The fixed costs are the costs of the external components and PCB area needed, while the variable costs are the costs per unit time of the energy source used to power the wireless node. The operation cost of the node can be simply defined as OC D FC C VC  t

(10.8)

where OC is the operation cost, FC is the fixed cost, VC is the variable cost and t is time. Figure 10.8 shows the noise figure with respect to supply current. In case of using external components for input matching, lower supply current and noisier active elements can be tolerated. In case of using the total integration solution, higher supply current is needed to minimize the noise generated by the active devices. Using external components means higher fixed costs but lower maintenance costs due to lower power consumption for the same noise figure, while using the total integration solution means lower fixed costs but higher maintenance costs. To make this point clear, Fig. 10.10 shows the operation costs of three possible solutions over time. The fixed costs for using external components was assumed to be 1$ and the other costs are 0.5$ and 0.25$, the same principle was applied to the variable costs. The time t is also a normalized variable it can be weeks, months or years. Two breakeven points can be identified B1 and B2. The breakeven point B1 where the operation costs of the high quality integrated passives solution is equal to the operation costs of the total integration solution. If the wireless node is intended to be used beyond the point B1 it is better to use the high quality integrated passives solution. If the wireless node lifetime is beyond B2 using external matching with its higher costs can be justified.

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Fig. 10.11 Simplified schematic of standard Gilbert-cell

3.2 Mixer Introduction In RF Transceivers the mixer is one of the key building block and often the limiting part, because mixer properties determine the system linearity. There are mainly two types of mixers, passive and active mixers. The linearity is described by the compression point P1dB and the third order input interception point IIP3. Generally, passive mixers have a high linearity and low power consumption, but show conversion loss and high noise figure [13]. Active mixers on the other hand, provide an acceptable gain, lower noise figure and high port-to-port isolation. However, they have higher power consumption and reduced linearity. In accordance with the requirements for low power, low noise, high gain and high linearity, the most commonly used topology is the Gilbert-cell. A double balanced Gilbert-cell mixer is shown in Fig. 10.11. Transistor T1 is the tail current source. Transistors T2 and T3 form the radio frequency (RF) input and act as a transconductance stage, which converts the RF input voltage into a current. The transistors T4–T7 act as switches and steer the current depending on the local oscillator (LO) signal. The load resistors R1 and R2 form the current to voltage transformation and providing the differential output of the intermediate frequency (IF). Unfortunately, not all the mixer specifications can be fulfill the requirements needed for the target Wireless System Network transceiver. To improve gain and linearity the current through the mixer should be increased, which leads to higher power consumption. Additionally, a higher current through the switching quads and

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using of resistive load can cause headroom problems. On the other hand, the use of active loads increases the noise figure. Furthermore, the larger current through the switching quads increases the flicker noise and also needs larger LO drive current which increases the DC power consumption of the LO signal generation block. It is necessary to find a solution that offers a compromise for low supply voltage, low power consumption, high linearity and low noise.

3.3 Down-Conversion Mixer In the receiver path a mixer translates the 2.4 GHz RF signal down to a lower IF signal or baseband. For low power applications the Gilbert-cell has some disadvantages. To keep the three stacked transistors in the saturation region a high supply voltage is needed. Similarly, a strong LO voltage is needed, which is a serious disadvantage in terms of power consumption. But a reduction of supply voltage will result in a poor conversion gain and linearity performance. Furthermore, the working range of Gilbert-cell MOS transistors is limited to the saturation region and limits the linearity. For low power applications the structure of the Gilbert-cell has to be modified. When the RF input transistors operate in the saturation region and the LO switch transistors operate in the perfect switching situation, the conversion gain (CG) and IIP3 can be approximated expressed as [14]: CG 

p 2 2 RL  gm  RL KN  IdsRF  

(10.9)

s IIP3  4

2 IdsRF 3 KN

(10.10)

W L

(10.11)

KN D 2N COX

Equation 10.9 shows the relationship between the transconductance gm and the conversion gain as a function of the load resistance RL . In Eq. 10.10 the IIP3 is shown in dependence of the drain current of the RF input IdsRF . For a better mixer performance gm and IdsRF should be increased. A possible solution is described in the following sections (Fig. 10.12). 3.3.1 Modified Transconductance Stage The linearity of the Gilbert-cell mixer mainly depends on the linearity of the transconductance stage. To improve linearity of the transconductance stage in the last years several new approaches were presented. In [15, 16] a modified Gilbert-cell

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Fig. 10.12 Simplified schematic of proposed down-conversion mixer Fig. 10.13 IDS .VGS / for large-size and normal-size transistors around thresholdvoltage VT : same slope of current in two different curves means the same transconductance gm [17]

was presented without tail current transistor to increase linearity, voltage headroom, and allow low voltage operation. A proposal for a RF CMOS subthreshold active mixer design, based on subthreshold biasing of MOS transistors is made in [17]. The improvement in [17] made it possible to reach a high transconductance gm with large sized transistors, biased in subthreshold, similar to the case of normally sized transistors biased in superthreshold as shown in Fig. 10.13.

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RL1

RL2 IF +

IF – IBLD

LO +

LO –

MSW2

MSW1 ID1

ID2 Ibias

RF

MRF

Fig. 10.14 Single-balanced mixer with bleeding current source IBLD [19]

This reduces the power consumption of the mixer. Similarly with the same drain current a higher transconductance can be reached. Combining these techniques, the mixer transconductance stage operates in a kind of class AB configuration, i.e. the typical current consumption is low but for high input voltages the differential pair transistors are alternatively pushed into saturation and draw more current. This improves the linearity of the transconductance stage and increases the linearity of the whole mixer. In this case the high current causes a high voltage drop over the load transistors. To prevent the LO switches going into the ohmic region the load stage could be implemented with active PMOS loads. This is controlled by a common mode feedback circuitry (CMFB) which additionally improves the linearity by allowing the maximum range of output voltage swing.

3.3.2 Current Bleeding In addition to the active loads the current bleeding technique [18] is used. The bleeding source transistor reduces the current through the LO switches and loads. For a given current through the transconductance stage, gain decreases in dependence on the current through the bleeding source transistor, and the flicker noise caused by the LO switches and active loads can be reduced. Further increase of gain and lowering of the noise figure can be achieved through higher power consumption (Fig. 10.14).

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Fig. 10.15 IDC .RFpower/

Fig. 10.16 Compression points for standard and proposed mixer

3.3.3 Simulation Results As test conditions a radio frequency of 2.4 GHz and a LO frequency of 2.41 GHz resulting in an IF of 10 MHz have been assumed. The mixer is fed with a LO power of 12 dBm from a differential 100 Ohm source. This corresponds to an amplitude for LO C and LO-of about 220 mVpp. Figure 10.15 illustrates the DC current dependence on RF power for the proposed mixer and a standard Gilbert-cell. The operating voltage is 1.8 V. The current consumption of the presented mixer depends directly on the input voltage at the RF input. As described, the current for small input signals is relatively low (IDC < 600 A for RF power <20 dBm). Above a certain input power (around 20 dBm) the available current is not sufficient to substantially increase the input signals. This limits the linearity and affects on the compression point, shown in Fig. 10.16. The proposed structure has a 11 dB higher linearity.

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Fig. 10.17 Noise figure(f), improved noise figure with current bleeding

Table 10.3 Simulation results of down-conversion mixers Gilbert-cell Parameter Proposed with modified results mixer transcond. stage

Standard Gilbert-cell

Conversion gain Noise figure @ 10 MHz P1dB IIP3 DC current (mixer core)

9.4 dB 10 dB 19 dBm 10 dBm 580 A @prf D 20 dBm

10.4 dB 14.3 dB 7.9 dBm 5.4 dBm 580 A @prf D 20 dBm

10.8 dB 14.5 dB 8.9 dBm 6 dBm 560 A @prf D 20 dBm

For small input signals the current is the same. The gain reaches up to 10.4 dB. Depending on the input signal strength more current is available for amplification which is a form of adaptive biasing. In Fig. 10.17, the influence of the current bleeding technique is shown on the noise figure. For an intermediate frequency lower than 1 MHz the noise figure is reduced by 2 dB. For a higher bleeding current ratio the noise figure can be further reduced, but the power consumption increases. The simulation results of the different structures are shown in Table 10.3.

4 TX RF Frontend Circuits In this chapter the main building blocks of the TX RF frontend circuits, PA and upconverter mixer are discussed.

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4.1 Power Amplifier At the transmitter side of the transceiver another kind of amplifier is needed, which is the power amplifier. The most important characteristics of the power amplifier are linearity, gain, and efficiency. For low power applications high efficiency power amplifiers are of great importance, since high efficiency means lower power consumption and longer battery life. At this point it is important to discuss how power amplifier efficiency is defined. The simplest definition is D

PRF PDC

(10.12)

where PRF is the output RF power and PDC is the DC power. This definition is most suitable when the input of the amplifier is a signal with a constant envelope (like FM signals), since the output RF power is constant with time. To increase the spectral efficiency modern communication systems use complex modulated signals with variable envelope. These signals have high peak to average power ratio (PAPR). To amplify such signal with acceptable linearity, the amplifier is operated at backoff, such that it can accommodate the occasional high power peaks. Since the output power varies with time, the efficiency is also varying with time. In this case the average efficiency would deliver a more accurate measurement of how efficiently the amplifier converts the DC power to RF power. Since communication signals have a stochastic (non-deterministic) nature, the probability density function of the output signal should be known to be able to calculate the average efficiency. For this reason the power amplifier should be designed with the modulation scheme which the transmitter is targeted for in mind. In the last section it will be shown how the average efficiency can be calculated. Several techniques are proposed to efficiently amplify signals with high dynamic range, like envelope elimination and restoration (ERR) and Doherty amplifier systems. Nevertheless these techniques are costly and justifiable only at high power levels. Wireless sensor networks are intended to be low cost and very low power systems, for this reason another approach is used. In wireless sensor networks O-QPSK can be applied; in this modulation scheme only one bit is changed at a time and thus the signal has no zero crossing. In this way the signal dynamic range is minimized. Another optimization factor is the pulse shaping filter used to limit the spectrum of the digital signal and avoid inter-symbol interference. In this work a class B power amplifier shown in Fig. 10.18 was designed for a wireless sensor network node. Table 10.4 shows the required specifications. It is important to point out that although high efficiency operation is required, the final efficiency will partially depend on the form of the input signal as mentioned previously. The design process starts with determining the maximum drain current, after that the optimum load impedance can be calculated using the load line method [20].

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Fig. 10.18 Cascode class-B power amplifier

Table 10.4 Power amplifier target specification

Output P1dB Gain Efficiency Output referred IP3 Frequency Technology

13 dBm >15 dB >40% 15 dBm 2.4–2.5 G 150 nm CMOS

Since the output power and supply voltage are known, the DC current (for class B operation) can be calculated using the following formula: PRF D

 IDC VDC 4

(10.13)

Imax 

(10.14)

For class B operation: IDC D

Knowing Imax the size of the transistor T1 can be determined. Since the output voltage swing is double the DC supply voltage the optimum load can be calculated as follows Ropt D

2 .VDC  Vk / Imax

(10.15)

where VDC is the supply voltage and Vk is the knee voltage. Since in sub-micron CMOS process the knee voltage can be as large as 50% of the supply voltage, the optimum load which will be used will be larger than the calculated value and the transistor will be pushed into the ohmic region during operation.

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Fig. 10.19 Simulated S11 and S22

The cascoding transistor T2 has two functions, first it isolates the input from the output and reduces the effect of the drain gate capacitance and thus increases stability. The second function can be understood if we observe that the output voltage swing which is 2 .VDC / is applied to two stacked transistors, and in this way the drain gate voltage of each transistor can be kept within the safe limits of the technology. The resonant circuit built of the LD and CD is open circuit at the fundamental and short at all harmonics, additionally the output capacitance of the amplifier can be absorbed in the capacitance CD . At this point it is important to test the stability of the amplifier and determine the regions of stable operation in the smith chart. The input matching circuit made of Cin and Lg is designed to match the large signal input impedance to 50 . Although the loss in the gate inductor Lg affects the gain and efficiency negatively, it increases the stability of the amplifier and can replace the stabilization resistors if needed. Figure 10.19 shows the simulated S11 and S21 of the designed amplifier, it can be seen that the input matching is better than 10 dB in the band of operation and the small signal gain is 17.34 dB at 2.5 GHz. Figures 10.20 and 10.21 show the single tone tests for the amplifier. It can be seen that the power gain is 17.25 dB and the output 1 dB compression point is at 13.15 dBm. The efficiency at this point is 43%; nevertheless the maximum efficiency is 48% at 3 dB compression as shown in Fig. 10.21. The OIP3 of the amplifier is 15 dBm as shown in Fig. 10.22. As mentioned before the average efficiency of the amplifier will depend on the probability distribution function of the input signal. To calculate the average efficiency under realistic conditions the amplifier was excited with 4 O-QPSK signals with a root raised cosine filter for pulse shaping with a roll of factor of 1. To get an estimation of the power variation with the time and the effect on efficiency,

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Fig. 10.20 Gain and Pout at 2.5 GHz

Fig. 10.21 Efficiency at 2.5 GHz

the histogram of the output envelope power was calculated and plotted together with the efficiency curves. Figure 10.23 shows the case of using a root raised cosine filter with alpha D 1. It can be seen that the signal has a peak power of 13.57 dBm and a dynamic range of 3 dB. Most importantly the output signal is at its peak only 1% of the time where the efficiency is 45.4%, and at a lower level (12.89 dBm) 14% of the time where the efficiency is 42.6%. The average efficiency can be calculated by summing the product of the two curves, in this case the average efficiency is 41.6%. At this point it is instructive to change the filter parameters and see its effect on the signal dynamic range and thus the average efficiency. Changing the value of alpha to 0.33 the signal dynamic range increases as shown in Fig. 10.24.

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Fig. 10.22 Two tones linearity test

Fig. 10.23 Envelope power distribution for ’ D 1

The signal has peak power of 14.12 dBm and a dynamic range of around 7 dB. In this case the average efficiency drops to 40%. It can be seen that the pulse shaping filter has an effect on the amplifier final efficiency. In this case the efficiency drop was not large but it showed the importance of considering the performance of other system block in calculation the amplifier final efficiency.

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Fig. 10.24 Envelope power distribution for ’ D 0.33

4.2 Up-Conversion Mixer In the RF transmitter front end the up-conversion mixer is one of the essential parts. It converts the incoming intermediate frequency to radio frequency. Compared to the down-conversion mixer the linearity requirements of an up-conversion mixer will be higher, when driving the preamplifier or directly connecting to the power amplifier. For high linearity, a large DC current through the transconductance stage is required which increases the power consumption of the mixer. Accordingly a larger current is flowing through the LO switches. The higher current flow requires larger sizes for the transistors in order to preserve the voltage headroom.

4.2.1 Circuit Description A modified transconductance stage with current reuse bleeding technique is used in [19]. In addition, the tail current source is removed [15, 16]. This can ensure a high linearity and sufficient gain. Figure 10.25 shows the proposed up-conversion mixer. The NMOS transistors T1 and T2 and the PMOS transistors P1 and P2 are the transconductance stage. P1 and P2 act as bleeding current sources. The transistors T3 and T6 form the LO switches, R1 and R2 are the load elements.

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Fig. 10.25 Simplified schematic of proposed up-conversion mixer

Table 10.5 Simulation results for up-conversion mixer

Parameter

Results

Conversion gain Noise figure @ 10 MHz input P1dB IIP3 DC current (mixer core)

1.3 dB 12.5 dB 0.4 dBm 2.5 dBm 400 A

4.2.2 Simulation Results The conversion gain of the up-conversion mixer is 1.3 dB for an LO power of 0 dBm and a supply voltage of 1.8 V. In this case the current consumption of the mixer core is 400 A. The linearity is simulated at an RF output of 2.4 GHz and input frequency of 10 MHz (and 10.1 MHz for IP3). The resulting IIP3 and P1dB were 2.5 and 0.4 dBm, respectively. The simulation results of the proposed upconversion mixer were summarized in Table 10.5.

5 Conclusion Details about RF frontend circuit implementations for different topologies have been presented which show the potential use in integrated radio transceivers for low power applications.

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References 1. E. Estrin, R. Govindan, J. Heidemann, S. Kumar, Next century challenges: scalable coordination in sensor networks, in ACM MobiCom ’99, Washington, DC, USA, 1999, pp. 263–270 2. N. Scolari, C.C. Enz, Digital receiver architectures for the IEEE 802.15.4 standard, in Proceedings of the 2004 International Symposium on Circuits and Systems ISCAS ’04, vol. 4, Vancouver, 23–26 May 2004, IV – 345–348 3. G. Cornetta, A. Touhafi, D.J. Santos, J.M. Vazquez, A direct down-conversion receiver for lowpower wireless sensor networks, in World Academy of Science, Engineering and Technology, Issue 51 March 2009 4. S. Chang, J. Park, K. Won, H. Shin, Design of a 2.4-GHz fully differential zero-IF CMOS receiver employing a novel hybrid balun for wireless sensor network. J. Semiconductor Technol. Sci. 8(2), 143–149 (2008) 5. L. G¨opfert, F. Hofmann, G. Jacobasch, A 900 MHz CMOS RF transceiver including digital baseband and hardware-MAC for IEEE 802.15.4/ZigBee applications. Eur. Trans. Telecommun. Spec. Issue on IST Summit 2005. 17(2), 283–292 (2006) 6. J. Notor, A. Caviglia, G. Levy, CMOS RFIC Architectures for IEEE 802.15.4 networks, Whitepaper, http://www.cadence.com/whitepapers/cmosrficarchforieee80215.pdf 7. W. Kluge, F. Poegel, H. Roller, M. Lange, T. Ferchland, L. Dathe, D. Eggert, A fully integrated 2.4-GHz IEEE 802.15.4-compliant transceiver for ZigBee applications. JSSC 41(12), 2767–2775 (2006) 8. T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn. (Cambridge University Press, New York, 2004) 9. IEEE standard 802.15.4d-2009 10. T. Taris, J.B. Begueret, Y. Deval, A low voltage current reuse LNA in a 130-nm CMOS technology for UWB applications, in European Microwave Conference, Munich, 9–12 Oct. 2007, pp. 1105–1108 11. V. Chandrasekhar, C.M. Hung, Y.C. Ho, K. Mayaram, A packaged 2.4 GHz LNA in a 0.15um CMOS process with 2 kV HBM ESD protection, in Proceedings of the 28th European SolidState Circuits Conference, ESSCIRC, Sept. 2002, pp. 347–350 12. H. Long, Y. Liu, Y. Wang, R.P. Dick, H. Yang, Battery allocation for wireless sensor network lifetime maximization under cost constraints, in Proceedings of the International Conference on Computer-Aided Design, San Jose, California, USA. Nov. 2009, pp. 705–712 13. S.K. Alam, J. Degroat, A 2 GHz highly linear downconversion mixer in 0.18- m CMOS, in 12th Nasa Symposium on VLSI Design, Coeur d’Alene, 4–5 Oct. 2005 14. Q. Wan and C. Wang, “A 0.18-m CMOS High-Performance Up-Conversion Mixer for 2.4-GHz Transmitter Application”, Frequenz, Journal of RF-Engineering and Telecommunications, 1-2/2010 Volume 64 January/February 2010, pp. 14–18 15. G. Yao, B. Chi, C. Zhang, Z. Wang, A low-power monolithic reconfigurable direct-conversion receiver RF front-end for 802.11a/b/g applications, Institute of Microelectronics, Tsinghua University, 100084, Beijing 16. T. Elesseily, T. Ali, K. Sharaf, “A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver”, Analog Integrated Circuits and Signal Processing, (2010) 63(2), 143–159 17. H. Lee, S. Mohammadi, A 500 W 2.4 GHz CMOS subtreshold mixer for ultra low power applications, School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, U.S.A. 18. R. Hedayati, S. Haddadian, H. Nabovati, A low voltage high linearity CMOS Gilbert cell using charge injection method, World Academy of Science, Engineering and Technology 38, 2008 19. S. Douss, F. Touati, M. Loulou, Design optimization methodology of CMOS active mixers for multi-standard receivers. Int. J. Electr. Comput. Eng. 2(9), 571–579 (2007) 20. S.C. Cripps, RF Power Amplifiers for Wireless Communications (Artech House, Norwood, 1999)

Chapter 11

Ultra High Data Rate CMOS Front Ends Reza Mahmoudi and Arthur van Roermund

Abstract The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using onwafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology.

1 Introduction Driven by customer demands, the last two decades have experienced unprecedented progress in wireless portable devices capable of supporting multi-standard applications. The allure of “being connected” at anytime anywhere and desire for untethered access toinformation and entertainment “on the go” has set the ever increasing demand for higher data rates. As shown in Fig. 11.1, contemporary

R. Mahmoudi () • A. van Roermund Department of Electrical Engineering, Eindhoven University of Technology, Den Doleh 2 E. H. 5. 26, 5600 MB Eindhoven, The Netherlands e-mail: [email protected]; [email protected] M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 11, © Springer ScienceCBusiness Media B.V. 2012

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Fig. 11.1 Left: data rate and distance comparison for different WPAN and WLAN technologies. Right increasing data rate trend according to Edholm’s law [2]

systems are capable of supporting light or moderate levels of wireless data traffic, as in Bluetooth and wireless local area networks (WLANs). However, they are unable to deliver data rates comparable to wired standards like gigabit Ethernet and highdefinition multimedia interface (HDMI) [1]. Furthermore, as predicted by Edholm’s law [2], the required data rates (and associated bandwidths) have doubled every 18 months over the last decade. This trend is shown in Fig. 11.1 for cellular, wireless local area networks and wireless personal area networks for last 15 years. In 2001, spurred by the increasing demand of high data rate applications and limitations of current wireless technologies, a 7 GHz contiguous bandwidth was allocated world-wide by the FCC. The regional regulatory bodies allocated local frequency bands with slight shift and defined the maximum effective isotropic radiated power (EIRP). The maximum allowed EIRP at 60 GHz is much higher than other existing WLANs and WPANs. This is essential to overcome the higher space path loss (according to classic Friis formula) and oxygen absorption of 10– 15 dB/km as shown in Fig. 11.2. These two loss mechanisms dictate the use of 60 GHz for short range multi-gigabit per second transmission. The attenuation also means that the system provides inherent security, as radiation from one particular 60 GHz radio link is quickly reduced to a level that does not interfere with other 60 GHz links operating in the same vicinity. Using the 60 GHz band for high data rate and indoor wireless transmission, a multitude of potential applications can be envisioned. The high definition multimedia interface (HDMI) cable could be replaced by a wireless system, transmitting uncompressed video streams from DVD players, set-top boxes, PC’s to a TV or monitor. Current wireless HDMI products utilize the 2.5 and 5 GHz unlicensed spectrum where bandwidth is limited. As a result, these systems implement either lossy or lossless compression, significantly adding component and design cost, digital processing complexity and product size. Typical distance between these gadgets is 5–10 m and this communication can be point-to-point or point–multipoint. The span of the potential services and applications in conjunction with the maturity of the main stream CMOS technology have stimulated the large activity for the realization the required corner blocks and systems in the cheap main stream CMOS process technology at 60 GHz.

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40 15 dB / km @ 60 GHz

20 ATTENUATION dB / km

10 4 2 1 .4 .2 0.1 .04

H2O A O2

.02 .01

O2 B H2O

.004 .002 .001 10

H2O

15

20

25 30

A: Sea Level T = 20 °C P = 760 mm 3 ′H2O = 7.5 gr / m

4 5 6 7 8 9 100 FREQUENCY GHZ

150

B: 4 km T = 0 °C ′H2O = 1 gr / m3

200 250 300

400

Fig. 11.2 Gaseous absorption at 60 GHz

Designing at 60 GHz requires dealing with multiple challenges which might be irrelevant or negligible at low frequency designs. One of the most important challenges of 60 GHz circuit design occurs in the transition between schematic and layout. Modeling the performance of circuits after doing the layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. The pronounced impact of parasitics at such high frequencies makes it more difficult to obtain the desired level of performance from the circuits. In addition, the necessity of accurate modeling of the parasitic effects brings about another design complexity. In fact, these complexities lead to the necessity of an iterative shift of the design focus from the schematic to the layout and vice versa, rendering the design a more time consuming process. The electromagnetic modeling of complex structures including the skin effect, substrate loss and the coupling impact of adjacent components is another issue which is sometimes impractical with the currently available simulation software, as they may require immense computational power. Therefore, the question facing the designers is whether the currently available software and tools are computationally capable of including all the layout impacts in their prediction of the performance of the circuits and how such predictions can be accurate regarding all the aforementioned limitations and the accentuated impact of layout-level issues. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the

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interfaces. Especially to perform on-wafer measurements one must pay utmost attention to the rigidity of the interfaces connected to the probes to keep all the connection lengths and orientations constant during the whole period of the measurement and calibration. Also special care must be taken to preserve the position of the probes on the bondpads and impedance standard substrates, since the measurement accuracy can be very much dependent on the positioning and landing of the probes. Another difficulty of mm-wave measurements arises from the overwhelming cost of equipment needed for instrumentation.

2 A Noise and S-Parameter Measurement Setup In this section, measurement setups are introduced which use waveguide interfaces to provide the required rigidity in the vicinity of the probes and utilize magic-T single-ended-to-differential converters to facilitate the measurement of differential circuits. The noise measurement of a 60 GHz double-balanced zero-IF mixer (see Sect. 4) and the noise and s-parameter measurement of a differential 60 GHz LNA (see Sect. 3), using the introduced setup, are explained in the following sections.

2.1 Noise Measurement of a Double-Balanced Mixer The waveguide setup used for on-wafer measurement of the differential circuits is illustrated in Fig. 11.3. In the case of the zero-IF mixer, four probes are needed. The probe on the top of the picture is an eye-pass probe used for biasing. The probe at the bottom of the picture is a GSGSG microprobe suitable for up to 50 GHz measurements and used here at the IF output of the DUT mixer. The other

Fig. 11.3 Left: the waveguide-based setup including two magic-Ts for measuring a doublebalanced mixer. Right: noise measurement setup for the mixer

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two probes on the left and right side are infinity GSGSG probes suitable for mmwave signals and used here at the RF and LO differential inputs of the mixer. The waveguide structures are mounted on metal plates which are screwed to the probe station, preventing all kinds of unintentional movements in the setup. Figure 11.3 shows the block diagram of the setup used for the noise measurement using the Y-factor method [3]. The network analyzer is used as a signal generator to produce the LO signal. The 60 GHz noise source is connected via an isolator and a waveguide to the magic-T and then to the RF port of the mixer. The differential IF output of the mixer is converted to single-ended via a hybrid and then connected to the spectrum analyzer via a low-frequency amplifier which covers 30 MHz to 4 GHz. The spectrum analyzer is set to Noise Figure mode and DUT is specified as a downconverter with a 60 GHz LO. The RF frequency range is set to 30 MHz to 2 GHz. The 60 GHz noise source generates noise only in the range of 60–75 GHz. Therefore, another noise source, capable of generating noise in the IF range, is needed for calibration of the output path and the spectrum analyzer. Figure 11.3 shows the block diagram of the noise calibration setup. The low-frequency amplifier is essential for obtaining good calibration results by amplifying the noise. Since two different noise sources are used, the ENR (excess noise ratio) list of the two noise sources must be manually entered in the ENR table of the spectrum analyzer. Both noise sources are controlled by the spectrum analyzer. The effect of the low-frequency amplifier and the cable, connecting the IF balun to the low-frequency amplifier, is automatically taken into account during the measurement, because they are in the calibration setup. However, the impact of the IF balun and the RF interfaces between the 60 GHz noise source and the input of the DUT must be manually calculated after the measurement. The loss of the combination of the magic-T, waveguide structure, and the infinity probe can be measured via two methods. The first employs a delta measurement and utilizing the network analyzer as a signal generator, the amplitude of the 60 GHz signal is measured by the spectrum analyzer. Since the spectrum analyzer does not support 60 GHz measurement, a preselected millimeter mixer is used to downconvert the 60 GHz signal to the range of the spectrum analyzer. Keeping the same amplitude for the signal generated by the network analyzer, the magic-T and the probes are introduced into the setup. A through of an impedance standard substrate is used between the probes. The difference in the readings of the two steps gives the loss of the introduced interface. Assuming a negligible loss for the through and equal loss for the two probes and magic-Ts, the loss of the RF interface, used between the noise source and the mixer input, can be calculated by dividing this number by two. In the second method, two one-port calibrations are performed using the network analyzer. First a cable, used in the next step for connecting the network analyzer to the magic-T and probe, is calibrated and the calibration dataset is saved. Then an onwafer one-port calibration is performed using an impedance standard substrate and including the magic-T and the probe in the setup. Again the calibration dataset is saved. Having the two datasets, the magic-T and probe combination is characterized.

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Measurement Simulation

NF (dB)

17 16.5 16 15.5 15 14.5 0.5

1

1.5

2

IF Frequency (GHz)

Fig. 11.4 Measured and simulated noise figure of the mixer

The results are the same as the first method (delta measurement). After calculating the impact of the IF Balun, the magic-T and waveguides, and the infinity probe, the final noise measurement results are obtained as shown in Fig. 11.4. The measurement results are close to the simulations.

2.2 Noise Measurement of a Differential LNA The noise measurement of the 60 GHz LNA is impeded by the fact that the output of the LNA is at a higher frequency than supported by the spectrum analyzer. Even the preselected mixer of previous section cannot be used here because the Noise Figure mode of the spectrum analyzer does not support it and it cannot be used with an external LO either. Therefore a passive mm-wave mixer is used in the noise measurement setup, as shown in Fig. 11.5, to down-convert the output of the LNA to the range of the spectrum analyzer. The passive mixer can be included in the calibration setup as shown in Fig. 11.5, making the post-measurement calculations much easier. The measured noise is in close agreement with the simulated values as shown in Fig. 11.6.

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LNA (DUT)

Probe + Magic T

LowFrequency Amplifier

60 GHz Amplifier

LowFrequency Amplifier

60 GHz Amplifier

Spectrum Analyzer

Network Analyzer

60 GHz Noise Source

Magic T + Probe

60 GHz Amplifier

60 GHz Noise Source

205

60 GHz Amplifier

Spectrum Analyzer

Network Analyzer

Fig. 11.5 Left: LNA noise measurement setup. Right: noise calibration for the LNA

During measurement: LNA (DUT)

12 11

During calibration: Impedance standard substrate

10

Magic T + Probe

Magic T + Probe

dB

9

Network Analyzer

8 7 6 5 4 3

Simulated Gt Measured Gt Simulated NF Measured NF

56

58

60

62

64

66

Frequency (GHz)

Fig. 11.6 Left: S-parameter measurement and calibration setup of a differential two-port circuit. Right: measured and simulated noise figure and transducer gain of the 60 GHz LNA

2.3 S-Parameter Measurement Performing s-parameter measurements on differential circuits with a two-port network analyzer is also facilitated by utilizing the magic-Ts. As shown in Fig. 11.8, each port of the network analyzer is connected to a magic-T and then to the probes. SOLT (Short-Open-Load-Through) calibrations are performed on a standard impedance substrate, suitable for GSGSG probes. Then the impedance standard substrate is replaced by the DUT and the measurement is done. The measured transducer gain of the 60 GHz LNA, using this setup, is compared with simulation results in Fig. 11.6. Conforming to the following considerations can promote the accuracy of the measurements and calibrations: • Accurate definition of the impedance standard substrate in the network analyzer or the software which controls the network analyzer • Precise positioning of the probes on the bondpads or on the impedance standard substrate

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• Repeating the calibration after some period due to invalidity of the calibration results after a certain period • Using undamaged samples of impedance standard substrate Employing waveguide-based measurement setup enabled performing accurate and repeatable measurements on 60 GHz receiver components. The fixed waveguide structures, specially provided for the probe station, serve for the robustness of the setup as they circumvent the need for cables, which are by nature difficult to rigidify, in the vicinity of the probes. Taking advantage of magic-Ts, it is possible to measure differential mm-wave circuits with a two-port network analyzer rather than using a much more expensive four-port one. Furthermore, the differential circuit can be driven by a single-ended noise source necessary for the noise measurement. The noise and s-parameter measurements performed on a 60 GHz mixer and LNA yield consistent results with the simulations.

3 Fully Balanced 60 GHz LNA The market demand for RF transceivers providing communication links of several Gb/s data rate motivates the use of the broadband WPAN ISM band at 60 GHz. These systems require receivers with a low noise figure (NF) and flat band response because of the complex modulation scheme. Combination of low NF, sufficient bandwidth, high gain and low voltage operation are important properties of LNAs. The design of mm-wave LNAs in CMOS causes many challenges because of lossy passives and the Miller capacitance. Several LNAs have been reported in recent years [4]. This section describes a fully differential 60 GHz LNA (Fig. 11.7) in bulk CMOS employing transformer feedback resulting in a flat and broadband response. The Miller effect is defeated using gate-drain capacitance neutralization [5], which is achieved when the following equation is satisfied (n is the transformer turn ratio and k is its coupling). s Cgs n  ;n D k Cgd

Ld Ls

(11.1)

3.1 Design Procedure Main design goal for the LNA is low NF combined with a high gain. Both are a function of MOS transistor bias and width, passives choices, and source impedance Zsrc. The MOS transistor bias was chosen as a compromise between noise and gain performance. The small signal circuit is shown in Fig. 11.7.

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Fig. 11.7 Left: circuit of the V-V transformer FB LNA as discussed in [5]. The coupling is indicated by the symbols next to the coils. Right: small signal circuit of the V-V transformer feedback LNA. For reasons of clarity the single ended circuit is shown

3.2 Transformer Specifications and Voltage Gain To achieve Cgd neutralization, the transformer turn ratio n divided by the coupling factor k should be equal to the ratio between Cgs and Cgd with a negative sign (11.1), which is approximately 2.3 in the used technology. To maximize gain, the turn ratio should be as high as possible and Ls should resonate with (n2Cgd C Cgs ) to tune out these parasitic capacitances. The former leads along with (11.1) to a high jkj (which is ˙1 at maximum), and the latter sets the inductance value for the inductors used in the transformer. The resulting voltage gain then converges to n. Given a certain MOS transistor width at the chosen bias the transformer properties are thereby known.

3.3 Transformer Design The transformer used in the LNA was constructed using EM simulation software (ADS Momentum). The resulting structure is shown in Fig. 11.8. The transformer has been optimized to have high jkj and high Q-factor inductors [6]. To satisfy Eq. 11.1 a turn ratio n of 1.8 has been chosen along with a coupling factor k of – 0.76. The simulated Q-factors of the inductors are higher than 10 at the frequency of interest. Simulated values for Ld and Ls are respectively 137pH and 42pH. A patterned shield has been placed underneath the transformers to reduce substrate coupling.

3.4 Layout Consideration In Fig. 11.8 the layout of the core of the LNA is shown. At the left the differential input of the first stage is shown and at the right the differential output of the second

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Fig. 11.8 Left: used transformer structure. For reasons of clarity the vias connecting the two bottom metals are only shown at the beginning and at the end of the metal strips. In reality many vias are distributed along the metal lines. The top inductor (Ls ) connects two metal lines in parallel to lower the inductance and increase the Q-factor. The lower inductor (Ld ) has two turns. The two inductors are placed exactly on top of each other to achieve the highest possible coupling (kj  1). The width of the metal lines is chosen to be 3 m. Right: the schematic of the realized two stages LNA

Fig. 11.9 Left: layout of the LNA (330  170 m2 ). Shown are only the top metal layers to clarify the structure. Patterned shields are used underneath the inductors, transformers and coplanar waveguides (not shown). In and output reference planes are indicated by the dashed lines. Right: Total LNA chip with bondpads and one de-embedding structure. Size die D 960  980 m, size LNA D 330  170 m2

stage. The two stages are connected to each other with a DCblocking capacitor between the output of TF1 and the input of Lg2 . All RF interconnects longer than 10 m used were simulated in ADS Momentum and Cadence RCextraction was used for all other structures. Lg1 and Lg2 are approximately 110pH and 150pH respectively. The transistors are indicated in Fig. 11.9 and are situated underneath the metal lines connecting the transformer structures. Transistor width stage 1 is 35 m and stage 2 is 25 m. The vertical lines surrounding the transformers are the DC power lines and biasing of the LNA. Coplanar waveguides with shielding have been used to connect the different components to each other. This results in low coupling to the substrate and between components. The input and output of the LNA are connected to bondpads using CPWs (see Fig. 11.9). This results in losses

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and an impedance shift. The resulting source and load impedance of the circuit at the input and output indicated in Fig. 11.9 is approximately 37 C j10. Open-shortload structures are added to de-embed the circuit. A lot of effort has been put into making the design as symmetrical as possible to reduce common mode.

3.5 Simulation Results The design consisted of an iterative process between circuit simulations, EM simulations and RC-extraction. After the first circuit simulation a Gt of 13 dB with a NF of 3.1 dB was simulated at 61 GHz. The IIP3 of the LNA was approximately 2.6 dBm with a 1 dBc of 11.8 dBm. After EM-simulation and RC-extraction the performance changed due to the parasitic effects. Gt decreased by 2.3–10.7 dB and the NF increased by 0.5–3.6 dB. These simulation results are shown in Fig. 11.6. The IIP3 increased to 4 dBm and the 1 dB compression point increased to 9.8 dBm. The simulated Gt variation in the band of interest is smaller than ˙0.15 dB and the 3 dB bandwidth is approximately 50–73 GHz which is approximately 37% of the center frequency at 61 GHz. The simulated power consumption is 35 mW at 1.2 V supply and 0.8 V gate bias. All simulations were performed using a source impedance of 30 , which was chosen as a compromise between NF and Gt. This is not equal to the conventional 100  for a differential topology. This is because the antenna could be connected directly to the LNA, allowing a different antenna (source) impedance.

3.6 Measurements and Verifications To verify the behavior of the LNA a number of measurements were performed using a differential measurement setup. DC power consumption is seen to be equal to the simulated value of 35 mW. The NF and sparameters are verified independently by the Eindhoven University of Technology and NXP Research. The S-parameters were measured using Agilent E8361A PNA. Calibration was verified using WinCal XE software. After de-embedding the measured Gt with Zsrc D 30  is 10 dB at 61 GHz (Fig. 11.6). The measured in-band deviation is ˙0.25 dB. The s12-parameter is below 47 dB over the entire measured band of 55–67 GHz and the group delay is 20 ps and behaves constant over the band of interest. The differential stability factor (K-factor) stays above 30 in the measured band. In common mode, the maximum transducer gain is equal to 2 dB resulting in a CMRR of 12 dB. The s12- parameter is below 42 dB, and K-factor stays above 70 in this case. NF was measured in the band 59.5–66 GHz (Fig. 11.6). Zsrc during this measurement is equal to 37 C j10 , while the input reflection coefficient for the noise source stays below 15 dB. The average measured value in this band is equal to 3.8 dB. To the author’s knowledge this is the lowest value found in literature

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around 60 GHz. NFmin of the circuit is found to be 3.7 dB using a load-pull setup in NXP. During this measurement the source impedance for NFmin was also verified with the simulated value. 13BC. The measured IIP3 is equal to 5 dBm at 57.5 GHz and 4 dBm at 60 GHz which is in close agreement with the simulation. Measured 1 dBc is 4.6 dBm and deviates from the simulated value because in simulation a Zload of 100  was used.

3.7 Benchmarking The performance of existing 60 GHz LNAs is compared with this work in Table 11.1. The LNAs presented in [7–9] are single ended, and [10] has a differential output. It is seen the work presented in this section shows the lowest NF along with the highest bandwidth. The relative low gain is because only 2 CS stages are used. The use of feedback results in a high IIP3.

4 60 GHz Zero-IF Mixer Utilized with a Three Dimensional Tuning The zero-IF receiver architecture is a promising candidate for mm-wave high data rate communication. While offering the possibility of low-cost and compact solutions for receivers operating in the license-free band around 60 GHz, the zero-IF architecture suffers from problems such as dc offset, flicker noise, and second order intermodulation distortions. In this section the wideband minimization of second order intermodulation distortion (IMD2 ) in a 60 GHz mixer is investigated. MultiGBps applications envisioned for the 60 GHz band require the zero-IF mixer to provide around 1 GHz of IF bandwidth. Therefore, any IMD2 cancelation mechanism applied to such a mixer must be functional across a wide frequency range. Thus, narrowband IMD2 cancelation techniques are not beneficial in this case. However, conventional single-parameter and double-parameter tuning techniques appear to be ineffective for high IF bandwidth applications. Therefore, in this section a three-parameter tuning method is proposed and is shown both in theory and measurement to be effective in wideband cancelation of IMD2 .

4.1 Second Order Intermodulation Mechanisms The downconversion mixer is normally the main contributor to second order nonlinearity distortions in a zero-IF receiver. The low-frequency second-order distortions generated in the RF path preceding the mixer can easily be filtered by RF coupling

Reference [7] [8] [9] [10] [4] (LNA C mixer, HG) This work

Table 11.1 Benchmarking

Process (nm) 90 65 (SOI) 90 65 45 65

Topology 3 stage CS 2 stage casc. 2 stage casc. 2 casc. C 1 CS 2 stage casc. 2 stage CS

Gt (dB) 15 12 14.6 22.3 (Av ) 26 10

NF (dB) 4.4 8 <5.5 6.1 6 3.8

3 dB BW (%) 10 22 25 13 N/A 37

IIP3 (dBm) N/A N/A 6.8 N/A 12 4

Vdd (V) 1.3 2.2 1.5 1.2 1.1 1.2

PDC (mW) 4 36 24 35 23 35

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R. Mahmoudi and A. van Roermund VDD RL

RL

VR1

VOUT

VR2

VC1

VC2

VLO– VLO+

M3

M4

M5

VG2

VG1

VRF+

VG1

VLO+

M6

VG2

VRF–

l1

l2

Fig. 11.10 Left: circuit schematic of the Gilbert-cell-like mixer with tunable output impedance and tunable gate biasing. Right: die photo of the mixer

or band-pass filtering. Figure 11.10 shows a typical Gilbert-cell-like mixer used in this article [11]. The input RF voltage is applied via two RF-coupling capacitors to the switching stage. The transistors M1–M4 are responsible for switching and downconverting the RF signal. At the output, the downconverted signal is converted from the current domain to voltage domain by means of the resistors (RL ). The CL capacitors represent the input capacitance of the following stage as well as the parasitics of the switching transistors at the output node. The differential output IMD2 voltage (Vimd2;out ), comes from two sources: (1) the common-mode output IMD2 current combined with output load mismatch and (2) the differential-mode output IMD2 current, as defined in (11.2). Iimd 2CM D

Iimd 2;1 C Iimd 2;2 ; Iimd 2Diff D Iimd 2;1  Iimd 2;2 2

(11.2)

where, Iimd2;1 and Iimd2;2 are as shown in Fig. 11.10. The differential output IMD2 voltage is described as a function of these currents in (11.3): Vimd 2out D Iimd 2;1 ZL;1  Iimd 2;2 ZL;2

(11.3)

where, ZL;1 and ZL;2 are the impedances seen from Vout C and Vout  nodes to the RF ground respectively as shown in (11.4), where, Rout is the resistance seen from the output node. ZLi D

Routi 1 C Routi CLi j!

(11.4)

Defining a nominal value for output impedance as in (11.5), the differential output IMD2 voltage can be rewritten as a function of common-mode and differential-mode output IMD currents as depicted in (11.6).

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ZL;1 D ZL .1 C •zL / ZL;2 D ZL .1  •zL /

(11.5)

Vimd 2out D 2Iimd 2CM ZL •zL C Iimd 2Diff ZL

(11.6)

Iimd2CM is a function of the input-stage and switching stage even-order nonlinearities and is present at the output current even if there is no mismatch in the circuit. However, it can be vanished in the differential output voltage by a perfect matching between ZL1 and ZL2 . Three mechanisms are responsible for generation of Iimd2DIF : self-mixing, input stage nonlinearity combined with switching pair mismatches, and switching pair nonlinearity combined with its mismatches [12]. Self-mixing is a result of the leakage of RF signal to the LO and vice versa. This mechanism is in general a function of the layout parameters and its contribution is zero in an ideally matched fully balanced downconverter. However, in practice any kind of mismatch in the LO or RF paths can activate this mechanism. The contribution of second and third mechanisms is determined by the mismatch between transistors in the switching pair [13]. The mismatch between the two transistors in a differential pair can be represented by an equivalent voltage offset at the gate of one of them [14]: @f @f ˇ C  @ˇ @ 0 1 s  2ˇ A C VT f D IDS @1 C 1 C 2 ˇ  IDS Voff D VT C

(11.7)

(11.8)

where, IDS is the biasing current of the transistor, “D n Cox W/L, ™ is the factor taking into account the velocity saturation effect, and VT is the threshold voltage. Therefore, these mechanisms can only be activated if there is mismatch between the switching stage transistors and the effective mismatch between transistors can be controlled by modifying the threshold voltage or biasing voltage of the gates of transistors. The latter approach, as a circuit-level parameter tuning, is considered in this work to avoid the requirement for very accurate tuning of the threshold voltage in the process.

4.2 Wideband IMD2 Cancellation Vimd2out can be minimized by tuning different parameters. Single-parameter tuning methods can adjust Voff to vary Iimd2DIF [15]. They can also adjust output resistance mismatches (•Rout ) or output capacitance mismatches (•CL ) to vary •zL

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[16, 17]. To make the two terms in (11.6) cancel out each other by tuning only one parameter, the following should be satisfied: •zL D

•Rout  Rout CL •CL j !b Iimd 2Diff D .1 C Rout CL j !b / 2IimdCM

(11.9)

where, ¨b is the IMD2 frequency at the output of the mixer. Higher powers of •Rout and •CL are neglected in this approximation of •zL . However, choosing only one parameter to tune, can only satisfy (11.9) at one single frequency point, because for each frequency the tunable parameter has a different optimum. Even a two-dimensional tuning involving •Rout and •CL is not sufficient [17], because it can only set (11.6) to zero at a single frequency point. Of course one might suggest using higher order filters as ZL which can annul (11.6) at multiple frequency points, but that would complicate the baseband filter design and the parameters needed to be tuned increase with the required flatness of IMD2 over the IF band. The approach chosen in this work is tuning all three parameters at the same time. This will result in simultaneous nullification of both terms in (11.6) as shown in (11.10). Since both •Rout and •CL are set to zero in this approach, nullification of •zL is (ideally) frequency-independent. Due to the narrowband assumption of the interferer at RF, Voff can be chosen in a way that all three mechanisms responsible for Iimd2Diff can cancel out each other. •zL D

  •Rout  Rout CL •CL j !b D 0; Iimd 2Diff Voff D 0 .1 C Rout CL j !b /

(11.10)

4.3 Circuit Design Variable resistors and varactors are added to the output, to provide tunability of the output impedance as required by (11.10). Variable resistors are in the simple form of series transistors biased in the triode region. The biasing of the gates of the switching pair transistors, can be adjusted separately for each half-circuit as required by (11.10). The circuit is designed and fabricated in CMOS 45 nm technology and the die photo is shown in Fig. 11.10. The supply voltage (VDD) is 1.1 V. VR1 and VR2, which control the value of the variable resistors, are differentially tuned around 100 mV. VC1 and VC2 control the varactors to tune the output capacitance and are differentially tuned around 500 mV. VG1 and VG2 tune the biasing voltage of the gate of switching pair transistors and are differentially tuned around 0.9 V. IBias draws 300 A and with a current mirror translates approximately the same current to I1 and I2 in Fig. 11.10. Therefore the circuit in Fig. 11.10 draws less than 600 A from VDD. The complete chip includes the mixer core shown in Fig. 11.10 as well as two active baluns and matching networks at RF and LO inputs. In addition, an IF

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–40

–20

–45 –25 Power@IF (dBm)

IMD2 (dBm)

–50 –55 –60 –65

–75 –60

–40

–20

0

–35 –40

IMD2@970MHz IMD2@60MHz

–70

–30

20

–45 –20

–10

VR (mV)

0

10

20

VG (mV)

Fig. 11.11 Left: IMD2 vs. (a) variable resistance control voltage (b) varactor control voltage. Right: IMD3 and fundamental term versus VG, varied in a range twice bigger than needed

buffer is used at the IF output to drive the 50  load of the measurement equipment. Four inductors are used in the design. Two of them are used in the input matching networks and the other two are the loads of active baluns.

4.4 Measurement and Experimental Results To test the capability of IMD2 cancelation across a wide IF frequency range, a 3-tone out-of-band signal is applied to the RF input of the mixer to emulate an out-of-band interferer. The 3 tones are at 61.07 GHz, 61.130 GHz, and 62.1 GHz. The LO signal is at 60 GHz. Therefore, the resulting IMD2 terms are at 60 MHz and 970 MHz which are measured as a function of the tuning parameters. There is another IMD2 term at 1,030 MHz which is considered as out-of-band and is not measured. The closest fundamental term of the downconverted interferer is at 1,070 MHz which is also measured as a function of tuning parameters to see how much the conversion gain can be affected by IMD2 cancellation. One of the IMD3 terms is also measured to observe the variation of IMD3 due to IMD2 cancelation. First of all, the single-parameter tuning is examined. Figure 11.12 shows the variation of IMD2 as a function of the control voltage of the variable resistors. This voltage is varied differentially around a common value of 100 mV. IMD2 at 60 MHz is minimized to around 5 mV whereas IMD2 at 970 MHz is minimized to around 20 mV. In fact, when IMD2 at 970 MHz is minimized, IMD2 at 60 MHz is significantly degraded. The same problem is observed when only one of the other two parameters, VG or VC, is tuned. Figure 11.11 shows the variation of IMD2 when VR and VC are changed simultaneously while keeping VG equal to zero. VR is swept from 40 to 40 mV in steps of 0.5 mV and in each step VC is swept from 300 to 300 mV in steps of 5 mV. According to Fig. 11.12 IMD2 at 60 and 970 MHz are never at the lowest points simultaneously, proving the inefficiency of two-dimensional tuning in this case.

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Fig. 11.12 Left: IMD2 tuning by simultaneous variation of VC and VR while keeping VG constant at 0. IMD2 tuning by simultaneous variation of VC and VR while keeping VG constant at 10 mV

However, as shown in Fig. 11.12, when VG is also tuned, an optimum point can be found where both 60 and 970 MHz IMD2 terms can be reduced to 70 dBm. In this case three-dimensional tuning improves the IMD2 components at 60 and 970 MHz by 10 and 20 dBm respectively. These results demonstrate both in theory and measurement that a threedimensional tuning is beneficial for wideband cancelation of second order intermodulation distortions (IMD2 ) in a zero-IF downconverter. The resistance and capacitance at the output of the mixer as well as the gate biasing of the switching pairs are tuned together to suppress IMD2 across a wide bandwidth. A 60 GHz zero-IF mixer is designed and measured on wafer to show that the proposed tuning mechanism can simultaneously suppress two IMD2 tones with a frequency difference of 910 MHz while having minor effect on conversion gain and third order intermodulation distortions.

5 A 40-GHz Phase-Locked Loop for 60-GHz Sliding-IF Transceivers Figure 11.13a illustrates a generalized two step down-conversion, sometimes also referred to as sliding-IF architecture. The incoming RF signal fRF is first downconverted by mixing with the RF local oscillator signal fRFLO producing a difference component at fRF – fRFLO . The second down-conversion to baseband is achieved by using the output of the prescaler fIFLO . The factor ‘M’ is an integer frequency multiplier which usually has a range between 1 and 3. The value of 1 implies a direct connection between the oscillator and the mixer, whereas the values 2 and 3 imply a frequency doubler and tripler, respectively. The factor ‘P’ is the division ratio of the prescaler and can also have a value between 1 and 3. The overall division ratio of the synthesizer is separated into ‘P’ and ‘N’ as the prescaler requirements and utilization in mm-wave synthesizers is distinct from the lower

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a

217

b

fRF

Baseband fRF–LO

60 GHz

Baseband

20 GHz

fIF–LO

40 GHz

20 GHz I-Q

×M

÷2 fOSC

÷P LPF, PFD, CP

LPF, PFD, CP

÷N

÷N

Fig. 11.13 Generalized PLL architecture for 60 GHz transceivers

frequency divider chain. The frequency conversion to baseband is carried out as: fosc ; fRF  fosc  M D P

 fosc D fRF

P MP C 1

 (11.11)

Using different values for M and P between 1 and 3 in (11.11) yields synthesizers operating at different frequencies. For instance, for M D 1, P D 1 the synthesizer operates at 30 GHz and provides both the RF-LO and IF-LO signals. This architecture is termed as “half-RF” and offers the lowest possible LO without doublers or triplers. However, it has two major drawbacks: third harmonic image and LO-IF feed-through. Other demonstrated combinations include M D 3, P D 2 and M D 2, P D 2. The former operates the synthesizer at 17 GHz and using a frequency tripler to down-convert the RF signal to 8.5 GHz. The conversion to baseband is by using the outputs of the prescaler [18]. The latter uses a 24 GHz PLL and 48 and 12 GHz as the first and second down-conversion steps. In this paper, a fully integrated 40 GHz PLL is presented (using M D 1, P D 2) as shown in Figs. 11.13b and 11.14. The required quadrature IF-LO is provided by the prescaler to down-convert the 20 GHz IF signal to baseband. This architecture prevents the need for doubler or tripler circuits as they tend to be lossy at these frequencies and typically do not provide quadrature outputs. Furthermore, it provides a good trade-off between tuning range and phase noise requirements and enables to satisfy the IEEE 802.15.3c channelization requirements.

5.1 Circuit Design Frequency synthesizers operating below 10 GHz can utilize broadband static prescalers, so there is no issue of synchronization between the VCO and the prescaler (together termed as PLL front-end) as the latter can easily cover the complete tuning range of the VCO. In contrast, mm-wave synthesizers generally

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R. Mahmoudi and A. van Roermund VbiasCP To bond-pad fref

Iout PFD

fdiv_out

fdiv

fRF-LO

Vtune

CP 74.2 pF

5.74pF

2 kΩ

CML-toCMOS

÷2I-Q ILFD

Selector fIF-LO

Divide-by64

fext

Fig. 11.14 Forty giga hertz PLL block diagram

use LC based VCOs and prescalers, and their frequency selectivity necessitates careful alignment of their respective working ranges. Any frequency mismatch due to design inaccuracy or layout parasitic can reduce the effective operation range of the synthesizer or, in worse case, make it completely devoid of locking. The complete schematic of the PLL front-end is shown in Fig. 11.16. The 40 GHz VCO shown on the left hand side is based on an NMOS-only cross coupled topology and the tank is formed by a top metal single-turn inductor and a varactor setup. The maximum and minimum capacitances are 106 and 30 fF resulting in a Cmax /Cmin ratio of 3.53. The Q-factor of the varactor setup is between 6 and 20, for a tuning voltage of 0–1.2 V. The post-layout simulation of the VCO yields a frequency tuning range (FTR) from 38 to 45 GHz (16%). The VCO consumes 5 mA from a 1.2 V supply and the peak-to-peak amplitude is about 1.5 V. The quadrature injection locked frequency divider is also shown in Fig. 11.15. The differential outputs of the VCO are injected to the input transistors M3 and M6 present in the two separate stages of the ILFD which are coupled in anti-phase to generate 90ı spaced outputs. As the output swing of the VCO is sufficiently large, buffers are not required between the ILFD and VCO, which greatly simplifies the routing during layout and decreases the power consumption of the overall system. The divide-by-64 block consists of six cascaded divide-by-2 stages which are optimized individually for low power consumption and required output power. Each divide-by-2 stage is based on current-mode-logic (CML) D-latches in negative feedback. The differential small-swing output from the last stage is converted to rail-to-rail square pulses for comparison in the PFD by means of a differential to single-ended converter followed by a pair of inverters.

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VDD VDD

Vtune

fref

VDD

VDD

VDD

Buffer M3

Q+

VDD

Q– UP

l+

Vtune

UP

l–

VCO+

VDD

M10

M11

M7

M8

M1

M3

Reset delay

VCO–

IoutLoop filter Vtune

VDD Vtune

VDD

l+

M6

C1

Icp

Buffer

M9

M4

C2 R1

l– M5

Q–

M6

M12

DN

M2

DN fdiv

Fig. 11.15 Left: PLL frontend including LC-VCO and quadrature ILFD. Middle: PLL backend components, PFD. Right: charge pump

G

G

fout+

G

fout–

G

Loop filter

fext+ G

÷64

PFD f CP div

buffer

ILFD fext–

~3.5 MHz synthesizer loop bandwidth

fdiv_out G fref

G VD ILFD

Ground meshing

G

VCO Vt

VDD VDD

Vt VDD VDD VDD OUT

Vb VDD SLCT G CP

G

Fig. 11.16 Left: die micrograph of 40 GHz PLL. Right: Fig. 11.6. Close-in spectrum of a locked PLL frequency

5.2 Layout and Technology The PLL is fabricated (Fig. 11.16) in TSMC bulk CMOS 65 nm LP (low-power) process having six metallization layers. The process offers MIM capacitors and poly-silicon resistors. The measured fT of NMOS and PMOS transistors is 140 and 80 GHz, respectively. The layout is done compactly to avoid parasitics, especially in the PLL front-end. Due to bond-pad limitation, only the ILFD output is measured. Transmission lines are used for all RF inputs and outputs. These TL’s are coplanar waveguide based with lateral ground plane consisting of all metal layers. The width of the TL is 5 m and spacing from the ground plane is 4.22 m. The total chip-area of the synthesizer including bond-pads is 1.67  0.745 mm2 .

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Fig. 11.17 Measured phase noise of the PLL

5.3 Measurement Results The PLL is measured on wafer using Agilent PSA (E4446A) and LeCroy real-time oscilloscope (Wave Master 830Zi). The free-running center frequency of the PLL is observed at 20.2 GHz and the VCO and ILFD consume 5 and 9 mA from a 1.2 V supply, respectively. The divide-by-64 block is included in the circuit by keeping the selector voltage HIGH and the divided frequency of 315 MHz is observed on the oscilloscope. The divide-by-64 circuit consumes 6 mW and the corresponding output buffer which is a cascade of four inverter stages consumes 2 mW. Both, the divided signal and the reference signal are observed on the oscilloscope. The reference signal is varied in steps from 290 to 344 MHz, which corresponds to an output frequency of 18.5–22 GHz (or 37–44 GHz at the VCO output). From these values, the ILFD output of the synthesizer locks between 19.1 and 21.8 GHz. The corresponding locked frequency range at the VCO output is 38.2–43.6 GHz. Thus, the PLL can down-covert a 60 GHz signal within a range of 57.3–65.4 GHz, thus covering all the four high-rate PHY (HRP) channels of the IEEE 802.15.3c standard. A locked spectrum for a reference frequency of 306.2 MHz is shown in Fig. 11.16. In a typical PLL, the sideband spectrum noise is cleaned-up within the loop bandwidth which is evident by the highlighted area in Fig. 11.16. The loop bandwidth estimated from the screenshot is about 3.5 MHz as opposed to the calculated value of 4 MHz. The output power of 8.55 dBm also includes the 1.5 dB of cable and other measurement related losses. The phase noise of the synthesizer is measured by the spectrum analyzer at the ILFD output and reflects its loop performance. Figure 11.17 shows one typical plot for a locked frequency of 20.12 GHz from 100 to 10 MHz. The value at 1, 4 and 10 MHz offset from the carrier is 95.7, 100 and 118 dBc/Hz, respectively. The first of the above values is the in-band phase noise (within the loop bandwidth),

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the second at the calculated loop bandwidth (forming the “knee”) and the third corresponds to the out-of-band phase noise. The variation of phase noise over the synthesizer operation range is C2.5 dB. The phase noise at the VCO output (at double the frequency, i.e. 42.24 GHz) can be estimated by adding 6 dB to the above mentioned values, resulting in 89.7, 94 and 112 dBc/Hz at 1, 4 and 10 MHz offsets from the carrier, respectively. The presented PLL is compared with published works in Table 11.2. It is the only design which covers all four HRP channels of the IEEE 802.15.3c standard. It demonstrates the lowest power consumption with the second highest locking range.

6 A Dual-Mode mm-Wave Injection-Locked Frequency Divider The proposed ILFD shown in Fig. 11.18 achieves dual-mode operation by preserving both even and odd harmonics, and features an increased locking range by improving both injection efficiency and varactor tunability. The former is achieved by direct differential injection via M3–M4, at the same time enhancing noise immunity as well as symmetric loading for a differential VCO. De-tuning of the Miller capacitances, introduced for the first time in an ILFD, improves the input– output transfer of the injection signal and cancels out the fixed tank capacitance, thus widening the locking range. This is achieved by a transformer feedback, which further accomplishes input matching without need for extra components. In addition, the over-drive voltage of the injection transistors M3–M4 is increased resulting in an enhancement of their effective transconductance. AC and transient simulations were used to determine the optimum transformer and injection-transistor parameters for achieving a wide locking range with minimum input power. The center-tap inductor of the LC-tank is a 9 m wide single-turn top-metal coil having an inductance of 192pH and a Q-factor of 28 around 20 GHz. The varactors provide a capacitance tuning of 150–39 fF and a Q-factor of 8 20,for a tuning voltage of 0–1.2 V. Operating at 0.8 V, the circuit is also suitable for future CMOS processes. The RF-input is AC coupled on-chip and the

VDD

VDD

Vout–@ finj / 2 or finj / 3

VDD Ltank

M6

Vinj+@ finj M1

M3 k

G

OUT+

G

OUT–

G G

G

Divider core & Buffers Vtune

Transformer

M5

VDD

Vtune

Vinj–@ finj

Vout+@ finj / 2 or finj / 3

Vbias

M4 k

VDD Ltank

M2

G

G G

IN+

G

IN–

G

Fig. 11.18 Left: dual-mode ILFD circuit schematic and output buffer. Right: chip micrograph of DM-ILFD

b

a

Supply for PFD and CP is 1.8 V Excluding buffers

80 1.6  1.9

65 CMOS 1.2a 17.5–20.94 (17.9%) 35–41.88 (17.9%) 100 (at 20 GHz)

Tech. [nm] Supply [V] VCO range [GHz]

Phase Noise [dBc/Hz] Fref [MHz] Ref. spurs [dBc] Power [mW] Area [mm2 ]

ISSCC 10 [31]

Reference 130 CMOS 1.5 45.85–50.6 (9.8%) 72 (@1 MHz) 45.1 40 to 27 45.8b 1.16  0.75

90 (@ 1 MHz) 50 54 64b 1.77  0.87

JSSC 07 [33]

90 CMOS 1.2 39.1–41.6 (6.2%)

ISSCC 08 [32]

Table 11.2 Performance summary and comparison of PLL

85.1 (@1 MHz) 234.1 50.4 80 0.95  1

90 CMOS 1.2 58–60.4 (4.1%)

ISSCC 07 [34]

89.7 (@ 1 MHz) 300 42 22.8* 1.67  0.745

65 CMOS 1.2 38.2–43.6 (13.2%)

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output employs a 50  matched differential common-source buffer (M5–M6) for measurement purposes. The basic purpose of the transformer, as mentioned, is to transfer the injection signal without loss to the drain and source of M3–M4 for signal-mixing. As the required inductance is below 100pH, a small structure with high self-resonance frequency could be chosen. In order to achieve high coupling and Q-factor, the top two metal layers (Me6, Me5) are used and placed exactly on top of other (Fig. 11.18). Me1 is placed below the transformer to improve substrate isolation and reduce capacitive coupling to the substrate.

6.1 Layout and Technology Figure 11.18 shows the micrograph of the 65 nm bulk-CMOS DM-ILFD IC. A separate transformer along with de-embedding structures (open, short, load) is also fabricated. Coplanar transmission lines, wideband 50  matched including the bond-pads, are used at input and output. The core DM-ILFD circuit occupies 200  150 m2 and the total chip area is 800  500 m2 . The transformer is smaller than a ‘ground’ bond-pad and only occupies 54  52 m2 .

6.2 Measurement Results The measured inductances of the primary and secondary coils of the transformer are 70 and 88pH at 60 GHz, and 62 and 80pH at 35 GHz. At 60 GHz, the measured values differ by 3 and 14pH compared to the corresponding EM-simulated (in Momentum and Sonnet V12) values. The measured coupling factor at the two frequencies is 0.69 and 0.67, respectively. The input sensitivity curves of the DM-ILFD are shown in Fig. 11.19. The free-running frequency of the DM-ILFD lies between 16.8 and 19.2 GHz for a tuning voltage (Vtune in Fig. 11.18) of 0–1.2 V while consuming 4 mW from a 0.8 V supply. A shift in center frequency due to an estimated 50 fF interconnect capacitance is observed. In divide-by-2 mode, with an input power less than 2 dBm, the locking range for each Vtune is about 3 GHz (8.27%) and total operating range is 33–39.5 GHz (17.93%). In divide-by-3 mode, the required input power is less than C1 dBm whereas the locking range for each Vtune is about 4 GHz (7.4%), and the total operating range is 48.5–59.5 GHz (20.4%). Figure 11.19 shows an example of the locking operation. A maximum variation of C3 and C1.15 dB is observed in the de-embedded output power and phase noise over the complete operating range as shown in Fig. 11.19 for different tuning voltages in the two division modes. The phase noise at a locked output of 19.05 and 16.6 GHz in divide-by-2 and divide-by-3 mode is 130.6 and 13 dBc/Hz at 1 MHz offset, respectively. These values are within C0.2 dB to the theoretical 6 and 9.5 dB difference (due to frequency division) from the generator phase noise.

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Fig. 11.19 Left: measured input sensitivity of DM-ILFD in divide-by-2 and divide-by-3 mode. Middle and Right: measured output power and phase noise variation in the two division modes for different tuning voltages

Fig. 11.20 Left: Figure-of-merit principle and definitions. Middle and Right: measured locking operation in the two division modes

6.3 ILFD Figure-of-Merit For proper comparison to state-of-the-art ILFDs, two new figure-of-merits (FOMs) are introduced here. Varactor tuning is widely adopted to increase the operating range of ILFDs [19–21]. It is noticed, however, that two different definitions are used for locking ranges obtained with [22] or without [20] varactor tuning. Therefore, an appropriate comparison demands a FOM incorporating the number of required varactor tunings to cover the complete operating range. Furthermore, input injection power and DC power consumption are important benchmarks that should be reflected in the FOMs. To this end, the total locking range is divided (Fig. 11.20) into p parts f1 , f2 , : : : , fp , related to tuning voltages Vtune1 , Vtune2 , : : : , Vtunep and minimum input powers Pmin1 , Pmin2 , : : : , Pminp . Averaging both locking range and minimum input power leads to favg D (f1 C f2 C : : : C fp )/p and Pminavg D (Pmin1 C Pmin2 C : : : C Pminp )/p. The total locking range (flock) thus equals n x favg . FOMP-in , also shown in Fig. 11.20, reflects the injection efficiency by assessing the average injection power Pminavg (in watts) required for an average relative tuning range (favg /fcenter ), and FOMPdc reflects the tuning efficiency by assessing the DC power consumption needed for the same average relative tuning range. Both FOMs comprise n and clearly, a lower value of n is preferred. It should be noted that without varactor tuning n equals 1. A higher FOM value indicates

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a better ILFD. A comparison with reported designs using the proposed FOMs and underlying parameters is shown in Table 11.3. The FOMPin of the presented DM-ILFD, in divide-by-2 and 3 mode, is 28 and 34.5 dB better than the dual-mode ILFD in [21] (ISSCC 2009), reflecting a considerable improvement in injection efficiency whereas the FOMPdc is comparable. Compared to the single-mode dividers, the 20.4% operating range of the DM-ILFD in divide-by-3 mode is better than [19, 20], resulting in a better or comparable FOMPin . The FOMPdc , on the other hand, is lower than single-mode ILFDs in [23, 24]. Finally, the operating range of 11 and 6.5 GHz at 60 and 35 GHz can easily cover the respective mm-wave bands of a multi-mode synthesizer.

7 Fully Integrated 60 GHz Distributed Transformer Power Amplifier Realization of high speed short-range wireless communication systems has motivated the employment of the available 6 GHz bandwidth around 60 GHz. Cost effective solutions for those applications can be achieved through the realization of fully integrated transceivers comprising the digital circuits in the main stream CMOS technology. However the low breakdown voltage of the active devices and the poor quality factor of passive components in CMOS technology have complicated the realization of power amplifiers capable of achieving the required output power and decent efficiency. The achievement of high power levels demands the realization of high ratio trans-impedance matching networks which declines the efficiency. As an alternative, one may use of distributed transformer power amplifier [25] which enables simultaneous power combining and impedance matching. The inequality of transformers’ input impedances engenders common-mode and unequal differential voltage-swings which might prevent the achievement of maximum output power. To surmount these problems we present two universal methods by adding auxiliary tuning components and introducing different device size for each combining stage, instead of complicating the transformer design [26, 27].

7.1 DAT Topologies DAT topology is composed of two sets of magnetically coupled inductors from which the secondary is connected to the output and the set of primaries are connected to amplifiers, creating power combining stages. Since DAT topologies accumulate the voltages of all combining stages, proper performance of DAT demands the achievement of maximum voltage swings of each stage and processing negligible common-mode component. A literature survey reveals the existence of different DAT topologies [25, 28], shown in Fig. 11.21, which share a common

This work

Reference [19] ASSCC 07 [20] MWCL 09 [23] WITS 08 [24] MWCL 08 [21] ISSCC 09

3 3

2

2 2 3 2 3

130 65

90

130 130

65

Division ratio

CMOS Tech. (nm)

25–31.2 35.6–39.3 53.8–57.8 33–39.5 48.5–59.5

35.7–54.9

66–72 48.8–54.6

Op. Fteq (Gliz)

Table 11.3 Comparison with published results of ILFD

22 9:8 7:1 17:9 20:4

42:3

9:1 11:2

LR. (%) 2 3 0.8

1.86 3.12

13 55:2 26

39 18 12 45:3 45 4 4

Pdc (mW)

Pmin-avg (dBm)

130 133:7 131:5 130:6 132

118:4

120:8 115

Ph. Noise (dBc/Hz @ 1 MHz)

1 1.57 2 2.29 2.86

1

1.63 5

Factor ‘n’

62.4 35.9 28.9 64.2 63.5

52.2

30.4 69.7

FOMPin

20:7 13:0 12:0 12:9 12:5

27:2

12:6 8:7

FOMPdc

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Fig. 11.21 Left: DAT topologies. (a) Inline non-alternating topology with center output [28]. (b) Inline alternating topology with side output [28]. (c) Ring topology [25]. Primary inductors are in red and secondary inductors are in blue. Right: simplified equivalent half-circuit diagram of Fig. 11.18a

problem regarding the inequality of input impedances. This inequality can occur between the values of differential input ports (ZinIi ) as well as between the individual nodes of those ports (ZnodIi ). The latter engenders unbalanced voltage swings at the output of differential amplifier stages (common-mode component), while the former imposes unequal voltage swings among those differential amplifier stages due to unequal loadline terminations [29]. This inequality might occur due to a combination of three mechanisms; different physical distances of power combining stages towards the output port (see Fig. 11.21), asymmetric physical position of input nodes with respect to the virtual AC grounding and asymmetric interwinding capacitances (see Fig. 11.21). Notice here that the AC grounding results from the differential output. Without loss of generality, Fig. 11.21 illustrates the half-circuit diagram of Fig. 11.21. Different voltage levels can be noticed at nodes V5 and Vx with respect to the virtual AC ground. These differences in combination with the asymmetric values of interwinding capacitances create common mode voltages and unequal differential voltage swings.

7.1.1 Compensating Common-Mode Effect In order to alleviate the impact of the common-mode effect, one can use the biasing connection at the center tap of the primary inductors. However the impact of this method is depending on the DAT topology and its contribution could

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R. Mahmoudi and A. van Roermund Table 11.4 Results examples common-mode compensation Fig. 11.21 U .a/ C U .c/ C

Znod,1 9.2 C j7.8 11.3 C j5.7 12.7 C j1.5 10.9 C j1.4

Znod,2 17.9  j3.4 12.5 – j5.1 8.8  j1.3 9.2  j0.1

Znod,3 17.4 C j3 19.6 j0.3 7.7 C j0.6 8.7  j0.9

Znod,4 25.2  j5 19.6 – j7.8 10.2  j0.2 8.9 – j0.3

Fig. 11.22 RF-voltages at nodes 3, 4 related to Fig. 11.21c. (a) before CM-compensation. (b) after CM-compensation. The dashed line indicates VRF; max

be turn to be positive or negative. Furthermore, one can adjust the transformer layout for a reduction of common mode effect. However these methods impose complex and iterative design procedure. To surmount the common mode effect, we propose the insertion of auxiliary components, e.g. capacitances and resistances, for equalization of node impedances. Employing mixed-mode parameters facilitates the determination of the common and differential components of each input port. A general analyzing procedure targeting zero common-mode voltages leads to a set of required conditions. As an example the required conditions in relation to Fig. 11.21a with use of Fig. 11.21 can be formulated as: Zcd11 C Zcd12 D 0; Zcd22 C Zcd21 D 0

(11.12)

In which ZcdIij represents the differential to common impedance-parameters of the transformer. Employing the equivalent circuit, presented in Fig. 11.21, enables the determination of the values and the location of auxiliary components. The result of this example is presented alongside another example regarding an implemented ring variant ([30], Fig. 11.21c) in TSMC 65 nm CMOS technology at Table 11.4 with the location of auxiliary components shown in Fig. 11.21. In Table 11.4 ’U’ denotes the uncompensated node impedances and ’C’ denotes the compensated node impedances. For the latter example the RF voltages at nodes 3, 4 are shown in Fig. 11.22 before (a) and after (b) compensation.

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Table 11.5 Results example load-line adjustment by device scaling W1 D W4 (m) 293 293

W2 D W3 (m) 293 258

Zin,1 D Zin,4 23.6 C j0.5 21.9 C j0.1

Zin,2 D Zin,3 17.3 C j0.6 18.5 C j0. 15

7.1.2 Compensating Unequal Differential Voltage-Swings Assuming the negligible effect of common mode, one may compensate the inequality of voltage swings between different combining stages. This goal can be achieved by combining currents and voltages as is suggested in [27]. However, this method complicates the design procedure for achievement of a higher output level where a larger transimpedance ratio is necessary. In conventional amplifier design, the required relation between the voltage and current swing is dictated by the impedance value of the output termination. However the existing magnetic and capacitive coupling between different stages of DAT topology facilitates the implementation of a new approach. This property enables adjusting the voltage swing of one stage by means of altering the amplitude and phase of current flows at the other amplifier stages. Taking benefit of this distinguishing property, an equalization of the voltage swings can be achieved by conscious introduction of inequality in the physical dimension (e.g. width) of the implemented amplifiers which in turn alters the required loadlines for achievement of maximum output swing for each stage. Table 11.5 represents the optimized transistor sizes with resulting load-line values of the ring variant, mentioned in the previous section. After applying compensation the voltage swings become approximately equal.

7.2 Circuit Design Due to the restriction on the layout size, a compact two stage inline alternating structure has been implemented in TSMC 45 nm CMOS technology. Cascoded differential pair topology forms the core of the combining stages. These amplifiers are operating in Class A, providing maximum gain and linearity. Minimizing interconnection loss has been achieved by an appropriate arrangement of the transistors. Transistors’ width of the first and the second combining stage are respectively 150¹m and 160¹m and they are biased according to the 0.29 mA/m guideline for achievement of optimal linearity. Fulfilling the DC-electro-migration design rules has imposed a larger line-width of the primary (red) windings. An optimal transformer design has been carried out in Momentum and it has led to an achievement of 76% efficiency, primary inductors of 70pH and a secondary inductor of 157pH. A T-junction power divider delivers the required power level to each amplifier stage and has angles of 45ı to reduce the length and losses. A pair of LC-matching networks together with the power divider transforms the 4.6–j8.7 

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RFin

Rin,1

Rin,2

RFout

Fig. 11.23 Left: two-stage inline alternating transformer. Right: chip photograph of two-stage DAT PA. The core is shown within the dashed box

amplifiers input impedances into 100 . The large ratio of the required transimpedance matching networks reduces the overall bandwidth. This affect might be alleviated by adding pre-amplifiers which will raise the impedance level of the amplifier input ports. The required passive and distributed components have been designed in Agilent Momentum and in Fig. 11.23 the chip photograph of the realized PA is shown with a core-size of 210 m  270 m.

7.3 Measurement Results 7.3.1 Small-Signal Measurements On-wafer small signal measurements are carried out using a 67 GHz Agilent PNA and Cascade Microtech infinity probes with integrated baluns with a supply voltage of 1.8 V and a total bias-current of 178 mA. Figure 11.24 shows the simulated results alongside the measured results in which a maximum measured gain of 7.8 dB can be observed at 56 GHz. Noticeable is a discrepancy at peak and notch frequency of jS21j and jS11j, respectively. Measurement results reveal a 1 dB-bandwidth of 5.5 GHz (from 53.6 to 59.1 GHz).

7.3.2 Large-Signal Measurements Due the inaccuracy involved with the modeling of passive components, a small discrepancy has been observed between the simulated and the measured load-line terminations. A proper measurement of the output power level has then been carried out by employing a 60 GHz Focus MPT load-pull system. Verification between the simulated and measured optimum load reflection coefficients reveal a discrepancy only in the phase component of 45ı . The measured value of the 1 dB compression

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Fig. 11.24 Left: S-parameters at Vdd D 1.8 V and Idc D 178 mA. Right: output power, power gain and PAE at 60 GHz for Vdd D 1.8 V and Idc D 178 mA

output power at the reference plane directly after the transformers’ output shows only a 0.7 dB discrepancy between load-pull system and nominal 100-termination. The large signal measurement has resulted in a 1 dB compression point of 13.2 dBm, a saturated power level of 16.3 dBm and a maximum PAE of 8.7% which are illustrated in Fig. 11.24. In the definition of the latter the power gain is taken into account. Employing 60 GHz Agilent signal generator, 67 GHz Agilent PNA and Agilent Spectrum Analyzer in combination with the 60 GHz Focus MPT load-pull system has facilitated the realization of an accurate 2 tone measurement setup. The 2 tone measurement results reveal an 18.7 dBm of OIP3 for a center frequency of 60.02 GHz and a tone-spacing of 40 MHz. Table 11.6 summarizes the performance of the presented differential DAT power amplifier alongside the latest reported CMOS power amplifiers at 60 GHz. This table shows that the presented work has a good output power level and a moderate efficiency in respect to the reported amplifiers.

8 Conclusion The parasitic effects due to layout, which are more influential at high frequencies, are taken into account by performing automatic RC extraction and manual L extraction. The long signal lines are modeled with distributed RLC networks. The problem of substrate losses is addressed by using patterned ground shields in inductors and transmission lines. It is observed that accurate simulation of all these parasitic effects is sometimes very time consuming or even infeasible. For instance electromagnetic simulation of a transformer in the presence of all the dummy metals is beyond the computational capability of existing EM-simulators. The on-wafer measurements on the 60 GHz circuits designed in this work are performed using a waveguide-based measurement setup. The fixed waveguide structures, specially provided for the probe station, serve for the robustness of

Description

3-Stage DAT cascode 2-Stage cascode 3-Stage differential CS 3-Stage DAT cascode 3-Stage CS 2-Stage push pull 2-Stage single-ended cascode 2-Stage differential cascode 1-Stage DAT differential cascode

Reference

[29] [35] [36] [37] [38] [39] [40] [41] This work

Bandwidth ldB/3 dB (GHz) 55–71/NA 55–65/NA NA/57–62 NA/53–68 NA/51–61 50–67/NA 50–60/47–60 55–65/NA 53–59/NA

Gain 26 16 15:8 15:5 19 6 16 20 6

Table 11.6 Comparison with reported pas in literature

14.5/18 12.7/14.5 2.5/11.5 11.5/18 NA/7.9 11/13.8 7.6/12 11.2/14.5 13.2/163

Output power 1 dB/sat (dBm) 12:2 25 11 3:6 19:4 7 12:3 14:4 8:7

PAE max (%)

90 SOI 65 65 65 45 45 45 45 45

Technology (nm)

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the setup as they circumvent the need for cables, which are by nature difficult to rigidify, in the vicinity of the probes. Taking advantage of magic- Ts, it is possible to measure differential mm-wave circuits with a two-port network analyzer rather than using a much more expensive four-port one. Noise, s-parameter, and phase noise measurements are performed using the mentioned setups. However, in practice, we have succeed to realize different 60 GHz corner blocks with excellent performance. These results have proven the capability of the main stream CMOS technology combined with proper and time consuming design procedure for the realization of 60 GHz RF corner blocks. Acknowledgement The author would like to thank Hammad M. Cheema, Jaap Essing, Pooyan Sakian, Erwin Janssen from Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands; Anton de Graauw and Edwin van der Heijden from NXP Semiconductors, the Netherlands; and Paul T.M. van Zeijl from Philips Research, The Netherlands, for contribution to this work, NXP Semiconductors and Philips research for giving access to the CMOS technologies and STW for the financial support.

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Chapter 12

Extremely Wideband CMOS Circuits For Future THz Applications Lorenzo Tripodi, Marion K. Matters-Kammerer, Dave van Goor, Xin Hu, and Anders Rydberg

Abstract Recent results in IC design have demonstrated the possibility to realize CMOS circuits working in the 100 GHz-1 THz band. In this chapter the design and measurements of a CMOS nonlinear transmission line and a CMOS Schottky diode sampling bridge are presented. Large-signal measurements of the nonlinear transmission lines from 6 to 168 GHz are shown. Time-domain measurements showing the possibility to sample ultrafast signals with fall time of 4.6 ps are described too. These two extremely wide band devices will be used as essential building blocks for the future implementation of a CMOS-based coherent THz spectrometer and imager.

1 Introduction Technologies and devices able to produce, detect and guide radiation in the band 100 GHz-1 THz have attracted for long time the attention of the scientific and industrial community [1]. Applications related to space exploration have been the major driver for the development of new devices for decennia, but in recent years, and especially since the invention of the terahertz time-domain spectroscopy technique [2], new commercial applications in multiple fields including biology and medicine have appeared [1, 3]. Today, femtosecond lasers are the core components of many state-of-the-art optical THz systems. Such devices have paved the way L. Tripodi () • D. van Goor Philips Research, High Tech Campus 37, 5656AE Eindhoven, The Netherlands e-mail: [email protected] M.K. Matters-Kammerer Electrical Engineering, TU Eindhoven, 5600MB Eindhoven, The Netherlands e-mail: [email protected] X. Hu • A. Rydberg Uppsala University, Uppsala, Sweden M. Steyaert et al. (eds.), Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, DOI 10.1007/978-94-007-1926-2 12, © Springer ScienceCBusiness Media B.V. 2012

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towards modern THz applications and, in some cases, have been transformed into successful products [4]. An alternative approach to produce and detect THz radiation is based on solid state electronics. The compactness, the lower cost and the large commercial success of solid state devices is definitely an attractive solution to allow a more widespread use of THz radiation. Devices based on advanced material band gap engineering such as the Quantum Cascade Lasers (QCLs) [5, 6] have demonstrated to be powerful THz sources. To produce and detect THz radiation, another mechanism based on plasma waves in a transistor channel [7] is also currently being explored. With this technique room-temperature THz emission [8] and detection have been achieved [9]. Apart from these solid-state approaches based on new devices, recent publications also show an effort to exploit standard CMOS technology for THz radiation detection and generation. The use of an already available and standard commercial technology such as CMOS would allow implementing innovative miniaturized THz devices that will open novel commercial opportunities in the field of THz imaging and spectroscopy. In this work we show some recent advances in this direction. Design and measurements of two essential building blocks of a future THz imager and spectrometer are presented. Such a miniaturized device is planned to have an overall size small enough so that it can be also used for handheld applications. This chapter is organized as follows. Section 2 gives some background information on the architecture of the THz imager and spectrometer. A short summary of some current research carried out in the world on THz CMOS electronics is given in Sect. 3. The design and measurements of an extremely wide band THz signal generator are reported in Sect. 4. Section 5 focuses on the receiving part of the overall THz system. Conclusions are drawn in Sect. 6.

2 CMOS-Based THz Imager and Spectrometer Systems based on GaAs technology able to carry out THz imaging and spectroscopy have been demonstrated in the 1990s [10, 11]. Those pioneering experiments were using integrated nonlinear transmission lines and Schottky diode sampling bridges to generate and detect THz radiation. The THz electronics was usually integrated on GaAs technology while the low frequency part was implemented with external instruments such as signal generators and oscilloscopes. In this work a further step towards the transformation of those devices into actual commercial products is taken. CMOS technology is chosen instead of GaAs be