Bio-Inspired and Nanoscale Integrated Computing (Nature-Inspired Computing Series)

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BIO-INSPIRED AND NANOSCALE INTEGRATED COMPUTING

BIO-INSPIRED AND NANOSCALE INTEGRATED COMPUTING EDITED BY Mary Mehrnoosh Eshaghian-Wilner

A JOHN WILEY & SONS, INC., PUBLICATION

Copyright r 2009 John Wiley & Sons, Inc. All rights reserved. Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and speciﬁcally disclaim any implied warranties of merchantability or ﬁtness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of proﬁt or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data: Bio-inspired and nanoscale integrated computing / edited by Mary Mehrnoosh Eshaghian-Wilner. p. cm. – (Nature-inspired and nanoscale integrated computing) Includes bibliographical references and index. ISBN 978-0-470-11659-3 (cloth) 1. Molecular computers. 2. Biologically-inspired computing. 3. Nanotechnology. 4. Nanomedicine. I. Eshaghian-Wilner, Mary Mehrnoosh. QA76.887.B56 2009 004.1–dc22 2009013331

Printed in the United States of America 10 9 8 7 6

5 4 3 2

1

CONTENTS Foreword

vii

Preface

ix

Contributors

xiii

1

AN INTRODUCTION TO NANOCOMPUTING 1 Elaine Ann Ebreo Cara, Stephen Chu, Mary Mehrnoosh Eshaghian-Wilner, Eric Mlinar, Alireza Nojeh, Fady Rofail, Michael M. Safaee, Shawn Singh, Daniel Wu, and Chun Wing Yip

2

NANOSCALE DEVICES: APPLICATIONS AND MODELING Alireza Nojeh

31

3

QUANTUM COMPUTING John H. Reif

67

4

COMPUTING WITH QUANTUM-DOT CELLULAR AUTOMATA Konrad Walus and Graham A. Jullien

5

DIELECTROPHORETIC ARCHITECTURES Alexander D. Wissner-Gross

6

MULTILEVEL AND THREE-DIMENSIONAL NANOMAGNETIC RECORDING S. Khizroev, R. Chomko, I. Dumer, and D. Litvinov

111 155

175

7

SPIN-WAVE ARCHITECTURES Mary Mehrnoosh Eshaghian-Wilner, Alex Khitun, Shiva Navab, and Kang L. Wang

203

8

PARALLEL COMPUTING WITH SPIN WAVES Mary Mehrnoosh Eshaghian-Wilner and Shiva Navab

225

9

NANOSCALE STANDARD DIGITAL MODULES Shiva Navab

243

vi

10

11 12

CONTENTS

FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING Sumit Ahuja, Gaurav Singh, Debayan Bhaduri, and Sandeep Shukla

263

MOLECULAR COMPUTING: INTEGRATION OF MOLECULES FOR NANOCOMPUTING James M. Tour and Lin Zhong

295

SELF-ASSEMBLY OF SUPRAMOLECULAR NANOSTRUCTURES: ORDERED ARRAYS OF METAL IONS AND CARBON NANOTUBES Mario Ruben

327

13

DNA NANOTECHNOLOGY AND ITS BIOLOGICAL APPLICATIONS John H. Reif and Thomas H. LaBean

349

14

DNA SEQUENCE MATCHING AT NANOSCALE LEVEL Mary Mehrnoosh Eshaghian-Wilner, Ling Lau, Shiva Navab, and David D. Shen

377

15

COMPUTATIONAL TASKS IN MEDICAL NANOROBOTICS Robert A. Freitas, Jr.

391

16

HETEROGENEOUS NANOSTRUCTURES FOR BIOMEDICAL DIAGNOSTICS Hongyu Yu, Mahsa Rouhanizadeh, Lisong Ai, and Tzung K. Hsiai

429

17

BIOMIMETIC CORTICAL NANOCIRCUITS Alice C. Parker, Aaron K. Friesz, and Ko-Chung Tseng

455

18

BIOMEDICAL AND BIOMEDICINE APPLICATIONS OF CNTs Tulin Mangir

483

19

NANOSCALE IMAGE PROCESSING Mary Mehrnoosh Eshaghian-Wilner and Shiva Navab

515

20

CONCLUDING REMARKS AT THE BEGINNING OF A NEW COMPUTING ERA Varun Bhojwani, Stephen Chu, Mary Mehrnoosh Eshaghian-Wilner, Shawn Singh, and Chun Wing Yip

Index

535

547

FOREWORD Bio-inspired and Nanoscale Integrated Computing (edited by Professor Mary Mehrnoosh Eshaghian-Wilner) is the ﬁrst book in a new and exciting Wiley book series, the Nature-Inspired Computing Series. The proliferation of computing devices in every aspect of our lives increases the demand for better understanding of emerging computing paradigms. The new book series seeks to provide an opportunity for researchers to explore the new computational paradigms and their impact on computing in the new millennium. The series is quite timely since the ﬁeld of computing as a whole is undergoing many changes. A vast literature exists today on such new paradigms and their implications on a wide range of applications—a number of studies have reported on the success of such techniques in solving difﬁcult problems in all key areas of computing. The list of topics covered by the series is by no means exhaustive but it serves as a guide to the diversity of the topics covered here. It is also hoped that the topics covered will get the readers to think of the implications of such new ideas on the developments in their own ﬁelds. These ﬁelds are: Quantum Computing, DNA Computing, Genetic Algorithms, Evolutionary Paradigms, Cellular Automata, Neural Networks, Swarm Algorithms, Fuzzy Logic, Computational Synthesis, Machine Learning Techniques, Computational Methods for Biological Systems. The series will also publish books related to technologies that are relevant to nature-inspired computing: Silicon Neuron Processing, Molecular Scale Computers and NanoTech, Optics, Evolvable Hardware, Quantum Hardware, Reconﬁgurable Hardware, and others. Bio-inspired and Nanoscale Integrated Computing is a solid inaugural contribution that overviews some of the recent developments in the area of nanocomputing. This is an important emergent discipline which is facilitated by scientiﬁc advances in the ﬁeld of nanotechnology. This book, through a number of chapters covering a wide range of topics, increases the awareness of the potential of nanocomputing as a new paradigm that holds great promise. It is well-positioned to generate more interest and concerted effort in studying the different facets of nanocomputing and applying it to a wider range of problems in science and engineering. Bio-Inspired and Nanoscale Integrated Computing can be used by scientists, engineers, graduate students, senior undergraduate students, researchers, instructors, and practitioners, who want to learn more about nanocomputing. It is deﬁnitely an excellent reference on this topic. ALBERT Y. ZOMAYA The University of Sydney Sydney, New South Wales, Australia

PREFACE The word ‘‘bionics’’ is often described as a compound of ‘‘biology’’ and ‘‘electronics.’’ Some say it was coined in the 1950s and that it originates from the Greek word ‘‘bı´ on,’’ meaning ‘‘unit of life,’’ and the sufﬁx ‘‘-ic,’’ meaning ‘‘like’’ or ‘‘in the manner of’’–hence ‘‘like life.’’ But just like many people of a certain age, I ﬁrst came to know the term when I was a child (in my case growing up in Tehran) watching the then-famous duo of American TV series, ‘‘The Six Million Dollar Man’’ and ‘‘The Bionic Woman.’’ Back then, I had no idea how much of those programs was just fantasy. Not only was I too young to know better, but I was also under the impression that America was so much more advanced than where I lived, and therefore everything must have already been possible in the United States. As I grew older and eventually moved to the United States during my early teen years, I began to realize more and more just how far removed the bionic fantasy was. The absence of those advancements I had expected to see was certainly a big disappointment, yet it motivated me to begin my undergraduate studies in biomedical and electrical engineering at the University of Southern California (USC). As part of my studies, it became apparent that computer science and engineering were key disciplines that would make the bionic fantasy a reality. I therefore majored in Computer Engineering in the USC graduate school and received a Master s degree and a Ph.D. My ultimate dream was to make an actual bionic eye. To move one step closer to that dream, I concentrated on designing ultra-dense multiprocessor VLSI chips that had the capability of massive electrooptical intercommunications. I also designed a large number of algorithms that could be mapped onto those chips for image processing and computer vision. Before long, my career took off and my work received recognition in the area of parallel processing. I published, gave talks, taught courses, and organized conferences in various areas within parallel processing. Over time, my bionic dream was diminished to a small side issue. About two decades later, while employed as a professor and department head at the Rochester Institute of Technology, I learned about the intriguing advancements that were rapidly taking place in the new ﬁelds of nanotechnology and bioinformatics. I applied for and received a fellowship at the National Science Foundation’s Institute of Pure and Applied Mathematics at the University of California Los Angeles (UCLA). There, I interacted with an interdisciplinary group of scientists who were all interested in the applications of nanotechnology to their ﬁelds of expertise. Among them were biologists, chemists, physicists, mathematicians, electrical engineers, mechanical engineers, computer scientists,

x

PREFACE

and so forth. I knew that if I could somehow get all of them to understand each other, we could then also sit and design some of the world’s most challenging devices, e.g., those that were part of my ‘‘bionic dream.’’ Towards that goal, I began working with a small group of interdisciplinary scientists, and together we wrote a joint article about various ways computing could be done at a nanoscale level. The collaboration also led to the production of some very interesting breakthrough results that were widely disseminated and publicized through various news media. Shortly after that, I was contacted by an editor for the publisher, John Wiley & Sons, who told me Wiley would be interested in a book on the type of collaborative multidisciplinary work in which I was engaged. ‘‘Bio-inspired and Nanoscale Integrated Computing (BioNIC),’’ the name I had given to my research team at UCLA, was the title that I proposed to Wiley. I proposed a collection of the latest ﬁndings of leading scientists who were working in the proposed topic area, with the intent to get one step closer to the creation of actual bionic parts. Paul Petralia, the Wiley Editor, liked my proposal, then sent it for external review for which it received very positive and high peer ratings. I began working on the book immediately; and after about three years, it is now complete. The quality of the work presented in this book is all to the credit of the outstanding group of scientists with whom I had the distinct privilege and honor to collaborate. I must mention here that this book was initially planned to contain signiﬁcantly fewer chapters than what you see before you. Only through the remarkable dedication and contributions of the co-authors did this book evolve to its current size. I am immensely thankful and indebted to all of them. I invite all of you to begin reading with a special emphasis on Chapter 1. That chapter was produced primarily by a group of amazing interdisciplinary UCLA students who took a seminar course on nanocomputing that I taught. Each student studied the application of nanocomputing to their prospective ﬁelds and, based on those, they all got together and wrote the chapter. The chapter not only contains a brief but comprehensive background, but it also serves as a guide to various chapters within the book where additional information can be found. Special credit goes to Shawn Singh, who took a superb leading role among all the students that were involved. I also thank Professor Alireza Nojeh for his ﬁnal review of their work. There are many additional people to whom I am grateful. First and foremost, I thank Paul Petralia of Wiley, who had the foresight, leadership, and vision to help me produce this book from a simple idea to what it is now. He is also responsible for creating the Nature-Inspired Computing Series that I am coediting with my dear colleague, Professor Albert Zomaya. This book will serve as the ﬁrst in the new series and it will be followed by several other interesting titles, some of which are currently in progress. I am extremely grateful and pleased for the opportunity to be working with the renowned Professor Zomaya on this important series.

PREFACE

xi

My undying gratitude also extends to the numerous other wonderful people at Wiley and UCLA who have worked with me nonstop on this book. At Wiley, a special shout-out goes to Lisa Morano Van Horn for her outstanding production work, to George Telecki for seamlessly transitioning into Paul Petralia’s role, and to Michael Christian for his routine help with all diverse tasks. Over at UCLA, I would like to thank my administrative assistant, Rose Weaver, and all of my research assistants, including Dr. Shiva Navab, David Shen, Jon Lau, Mike Yip, and Stephen Chu, and Eric Mlinar. Finally, I don’t think this book would have been possible without the various contributions of my family. My parents, Mehdi and Molly, my brothers, Michael and Mark, and my sister, Maggie, have always supported me throughout the various stages of my life and career. I am forever indebted to them. My husband, Arthur, who is an excellent writer himself, has been a great adviser to me. I thank him with all my heart for all his valuable feedback. But most of all, I owe the most credit to my beautiful daughter, Ariana, who has been so patient and understanding about Mommy’s crazy schedule. I love her more than words can describe, and I dedicate this book to her and our family. Thank you for reading this book. Enjoy! MARY MEHRNOOSH ESHAGHIAN-WILNER Los Angeles, California March 2009

CONTRIBUTORS Sumit Ahuja, Research Assistant, Fermat Lab, Virginia Polytechnic and State University, Blacksburg, Virginia Lisong Ai, Department of Biomedical Engineering and Division of Cardiovascular Medicine, University of Southern California, Los Angeles, California Debayan Bhaduri, Research Assistant, Fermat Lab, Virginia Polytechnic and State University, Blacksburg, Virginia Varun Bhojwani, Analyst, Wachovia Securities, Los Angeles, California Elaine Ann Ebreo Cara, Department of Electrical Engineering, University of California, Los Angeles, California R. Chomko, Assistant Research Professor, Department of Electrical Engineering, University of California, Riverside, California Stephen Chu, Department of Electrical Engineering, University of California, Los Angeles, California Dr. I. Dumer, Professor, Department of Electrical Engineering, University of California, Riverside, California Dr. Mary Mehrnoosh Eshaghian-Wilner, Adjunct Professor, Department of Electrical Engineering, University of California, Los Angeles, California Dr. Robert A. Freitas Jr., Senior Research Fellow, Institute for Molecular Manufacturing, Palo Alto, California Aaron K. Friesz, Department of Electrical Engineering, University of California, Los Angeles, California Tzung K. Hsiai, Department of Biomedical Engineering and Cardiovascular Medicine, University of Southern California, Los Angeles, California Dr. Graham A. Jullien, Professor, Department of Computer and Electrical Engineering, University of Calgary, Calgary, Alberta, Canada Alex Khitun, Research Engineer, Department of Electrical Engineering, University of California, Los Angeles, California Dr. Sakhrat Khizroev, Professor, Department of Electrical Engineering, University of California, Riverside, California Dr. Thomas H. LaBean, Professor, Department of Chemistry and Department of Computer Science, Duke University, Durham, North Carolina Ling Lau, Hardware Engineer, Cisco Systems, San Jose, California

xiv

CONTRIBUTORS

Dr. Dimitri Litvinov, Director, Center for Nanomagnetic Systems, Associate Professor, Electrical and Computer Engineering and Chemical and Biomolecular Engineering Departments, University of Houston, Houston, Texas Dr. Tulin Mangir, Professor, Electrical Engineering Department, College of Engineering, Director, Nano Technology Lab, and Director, Wireless and Mobile Security Lab, California State University, Long Beach, California Dr. Shiva Navab, Staff Scientist, Broadcom Corporation, Irvine, California Dr. Alireza Nojeh, Assistant Professor, Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, Canada Dr. Alice C. Parker, Professor, Department of Electrical Engineering, University of California, Los Angeles, California Dr. John H. Reif, A. Hollis Edens Distinguished Professor of Computer Science, Duke University, Durham, North Carolina Fady Rofail, Department of Electrical Engineering, University of California, Los Angeles, California Mahsa Rouhanizadeh, Department of Biomedical Engineering, University of Southern California, Los Angeles, California Dr. Mario Ruben, Institut fur Nanotechnologie, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany Michael M. Safaee, David Geffen School of Medicine, University of California, Los Angeles, California David D. Shen, School of Law, University of California, Davis, California Sandeep Shukla, Associate Professor, Department of Electrical and Computer Engineering, Virginia Polytechnic and State University, Blacksburg, Virginia Gaurav Singh, Fermat Lab, Virginia Polytechnic and State University, Blacksburg, Virginia Shawn Singh, Department of Electrical Engineering, University of California, Los Angeles, California Dr. James M. Tour, Chao Professor of Chemistry, Professor of Computer Science, and Professor of Mechanical Engineering and Materials Science, Rice University, Houston, Texas Ko-Chung Tseng, Department of Electrical Engineering, University of California, Los Angeles, California Dr. Konrad Walus, Associate Professor, Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, Canada Dr. Kang L.Wang, Raytheon Chair Professor of Physical Electronics, Director, Marco Focus Center on Functional Engineered Nano Architectonics (FENA), and Director, Western Institute of Nanoelectronics (WIN), University of California, Los Angeles, California

CONTRIBUTORS

xv

Alexander D. Wissner-Gross, Environmental Fellow, Harvard University, Cambridge, Massachusetts Daniel Wu, Department of Electrical Engineering, University of California, Los Angeles, California Chun Wing Mike Yip, Department of Electrical Engineering, University of California, Los Angeles, California Dr. Hongyu Yu, Assistant Professor, School of Earth and Space Exploration, Department of Electrical Engineering, Arizona State University, Tempe, Arizona Dr. Lin Zhong, Professor, Department of Electrical and Computer Engineering, Rice University, Houston, Texas

1 AN INTRODUCTION TO NANOCOMPUTING Elaine Ann Ebreo Cara, Stephen Chu, Mary Mehrnoosh Eshaghian-Wilner, Eric Mlinar, Alireza Nojeh, Fady Rofail, Michael M. Safaee, Shawn Singh, Daniel Wu, and Chun Wing Yip The continuous shrinking of transistors has made it possible to do amazing feats with computers, and a major theme of the microelectronics era has been ‘‘smaller is better.’’ Today, technology has already shrunk to the nanometer scale, causing many practical challenges and motivating the search for new nanoscale materials and designs. In this chapter, we present a brief introduction to the concept of nanocomputing and provide a high level overview of nanocomputing devices and paradigms. We also discuss some applications of nanocomputing such as biomedical engineering and neuroscience.

1.1. INTRODUCTION In 1959, Nobel laureate Richard Feynman posed this question to his fellow physicists: ‘‘Why cannot we write the entire 24 volumes of the Encyclopedia Britannica on the head of a pin?’’ In that lecture, aptly named ‘‘There’s Plenty of Room at the Bottom,’’ Feynman challenged scientists and engineers to imagine what could be possible using nanoscale structures. He used computing as a prime example, suggesting that wires and circuits could be shrunk to only hundreds of angstroms in size [1], making it possible to combine billions of devices to perform amazing tasks. The transistor, today’s most prevalent modern computing device, can already be manufactured as small as hundreds of atoms across. This could mark the Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

2

CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

end of the microcomputing era and the beginning of the nanocomputing era. Nanocomputing could be fundamentally different from microcomputing: individual particles could play a signiﬁcant role; quantum effects enter the game much more directly. Even though Feynman’s vision has been partially realized with such tiny transistors, researchers are only beginning to explore the fundamental questions: How small can we make computers? How would such computers work? How can we embrace quantum mechanics for computation? What applications are possible with nanocomputing that were not possible with microcomputing? We will explore these questions throughout the book. In this introductory chapter, we will give a brief overview of devices, paradigms, and applications of nanocomputing. Of course, we cannot include all existing ideas about nanocomputing in the introduction, or even in the entire book. Instead, we aim to inspire the reader with a variety of ideas that appear commonly in nanocomputing research. We will ﬁrst deﬁne computing and nanocomputing and provide some historical context of the microcomputing era. The limitations of today’s microcomputers motivate a discussion of nanoscale devices and paradigms, many of which are detailed in later chapters. We then consider two major ﬁelds that can greatly beneﬁt from nanocomputing: biology and neurology.

1.2. WHAT IS NANOCOMPUTING? Computing is the representation and manipulation of information. Computer games, surﬁng the Internet, solving complex math equations, and even verbal communication are examples of computing. While we certainly compute using our own thinking power, it is often more useful to create a machine that computes on its own so we can use it to enhance our daily lives. Indeed, our world has become dependent on machines that automatically compute for us. These ‘‘computers’’ are used for entertainment, education, safety, and a vast number of other applications, all of which require manipulation of abstract information. To build a computing machine, abstract data must eventually be represented by something that physically exists. For example, digital states (such as 1’s and 0’s) can be represented as high and low voltages on a wire. Similarly, manipulations of abstract data, such as adding two numbers, must eventually be performed by a physical phenomenon that affects the data. Therefore, to explore the world of computing, we must ask the most fundamental question: How can we use physics to represent and manipulate abstract information? Directly or indirectly, researchers from all over the world are exploring this fundamental question. This endeavor spans across several disciplines, including mathematics, computer science, physics, chemistry, and biology. Throughout this book, there are many examples of how physics can be used for computation; some of these ideas may eventually lead to more powerful computers. Nanocomputing can be interpreted literally as computing at the nanometer scale. It is generally agreed that the terms nanotechnology, nanocomputing, and

1.2. WHAT IS NANOCOMPUTING?

3

nanoscale are used when considering devices that are at least one dimension smaller than 100 nanometers (nm). Today, devices such as transistors have channels that are well below 100 nanometers in length. Eventually the size of entire computers may also be measured in nanometers. Just how small is a nanometer? A nanometer is one-billionth of a meter (109 m). Figure 1.1 shows the approximate size of various physical entities at the nanometer scale. If it were possible to arrange 10 hydrogen atoms side by side, their combined width would measure approximately 1 nanometer. A typical processor found in a modern desktop computer is roughly 10 millimeters wide and 10 millimeters long—in terms of nanometers, this is nearly 10 million nanometers in width and length! Other computers are commonly much smaller; embedded processors used today in cell phones, cars, and many other devices are as small as a fraction of a millimeter squared. Nanocomputers will be even smaller; electrons, atoms, DNA, and proteins are all nanometer scale or smaller and offer a huge variety of ways to represent and manipulate data. At ﬁrst this description may seem to be simply a matter of size. For more than 50 years, computers have continued to get smaller and faster, and so it may not be obvious that nanocomputing is drastically different than microcomputing. Looking deeper, however, the nanometer size opens a new world of possibilities. Nanocomputers will be able to ﬁt anywhere, even inside our own bodies. They may be nearly undetectable, certainly invisible to the naked eye. Millions of such computers could work together and intelligently collect data about the world. Quantum physics makes it difﬁcult to continue using old microcomputing techniques, but it also gives us inﬁnitely more possibilities. With all this in mind, nanocomputing can be deﬁned as the study of devices, paradigms, and applications that surpass the domain of traditional microcomputers by using physical phenomena and objects measuring 100 nm or less. This deﬁnition clariﬁes that nanocomputing encompasses a large variety of challenges, ranging from effectively fabricating nanoscale devices to creating revolutionary applications for nanocomputers. In the nanoscale world, it is unlikely that computers will work the same way they work today. Figure 1.2 lists some of the novel paradigms that can be realized with nanoscale physics, roughly estimating how they may be compared to each other given today’s understanding of nanocomputing. As the ﬁgure shows, there is a vast amount of untapped potential computational power beyond CMOS logic, today’s dominant technology. Another important aspect of nanocomputing is the new set of applications that will be possible with such tiny, powerful computers. In turn, the plethora of applications raises ethical, social, and economic questions that are also of great interest. The applications and impact of nanocomputing will be discussed later in this chapter, but let us ﬁrst turn our attention to the fundamental question stated above, that is, exploring how physics can be used for computation. Over the next several sections we will discuss this idea, providing a historical context and generic taxonomy of nanocomputing topics that are detailed in the rest of this book.

4

CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

1000 nm

400−700 nm Wavelength of visible light

100−300 nm Typical virus

100 nm

Human hair (50,000 nm)

45−120 nm Modem CMOS fabrication process 700x 2−100 nm Quantum dot 3−15 nm A protein

10 nm

Virus

2−10 nm Diameter of a carbon nanotube 100x

1 nm

2 nm Thickness of a DNA strand

0.01−10 nm Wavelength of X−rays

0.1 nm

0.1 nm Hydrogen atom

DNA strand

10x

Hydrogen atom (computer visualization)

Less than 0.1 nm Wavelength of an electron 0.01 nm

Figure 1.1. Left: Size of various objects, measured on a logarithmic scale. Right: Visual depiction of some of these objects, to compare relative size. Permissions obtained for the DNA strand from CalTech. The human hair and the virus pictures were taken from the Wikipedia public domain.

5

1.3. THE MICROCOMPUTING ERA: THE TRANSISTOR AS A SWITCH

Modern CMOS circuits

Analog circuits Wave-based communication and logic

Switch-based logic

Size

Cellular and neural logic DNA and protein computing

Quantum Computing

Estimated computational power

Figure 1.2. Visualization of how future paradigms in nanocomputing may compare to today’s CMOS technology.

1.3. THE MICROCOMPUTING ERA: THE TRANSISTOR AS A SWITCH Traditionally, the most common way to use physics for computation is to cleverly control electricity. Figure 1.3 shows a simpliﬁed transistor. We can add or remove electrons from the gate. When there is no charge in the gate, the wire can easily transmit its own electrons. If there are electrons in the gate, an electric ﬁeld of negative charge is created, and this repelling force makes it difﬁcult for electrons to ﬂow through the wire. In a sense, we can control how much current ﬂows through the wire by controlling how much charge we put into the gate. With this physical device, an abstract 0 or 1 is represented as a low or high current on the wire. This is known as the digital abstraction. The transistor’s

Gate Insulating barrier

− − − − − − − − − − − − − − − − − − − − − − Current flowing through channel

Gate − − − − − − − − − − − − − − −

− − − − − − Channel blocked

Figure 1.3. A simpliﬁed ﬁeld-effect transistor. Ideally, the gate can ‘‘switch’’ current on or off.

6

CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

behavior represents a simple switch: the gate can allow or prevent current from ﬂowing through the wire. This is the switch abstraction. In practice, there are many more abstractions placed on top of these two (for example, representing integers in binary form with a series of 0’s and 1’s). However, the digital and switch abstractions are particularly signiﬁcant because they bridge between a physical phenomenon, moving electrons and electric ﬁelds, to an entirely abstract world, manipulating 0’s and 1’s with switches. This use of transistors is the cornerstone of modern computing. One particularly interesting achievement occurred in 1959, when both Robert Noyce and Jack Kilby independently developed the integrated circuit. With integrated circuits, one fabrication process simultaneously creates many transistors, all of them integrated on a single crystalline structure such as silicon. As fabrication techniques began to improve, it became possible to pack more transistors together. By 1965 Gordon Moore, the co-founder of Intel, predicted that the number of transistors that ﬁt into a given area would double every 18 months due to continued improvements in the fabrication process. Following this prediction known as Moore’s Law, transistor size, speed, and power consumption have exponentially improved for almost 50 years. Today it is possible to construct hundreds of millions, even billions, of tiny transistors on a small piece of silicon the size of a thumbnail (Fig. 1.4). In turn, it has become practical to create abstract computers that use millions or billions of switches. Because the fabrication process produces all transistors simultaneously, the cost of fabricating these computers is largely independent of the number of transistors. There is typically a large initial cost, and this initial cost can be amortized over thousands or millions of processors, which can be produced cheaply. The economics of this situation is staggering—with a smaller transistor, performance improves, power consumption decreases, more abstract computation ﬁts onto a single processor, and all this happens as the price of each transistor decreases! With this persistent exponential improvement, it is very easy to manipulate large amounts of abstract information, and computers are used for a proliﬁc number of applications today. All of this has hinged on the fact that transistors continue to get smaller, and this has led to the general trend that ‘‘smaller is better.’’

1.3.1. Difﬁculties with Transistors at the Nanometer Scale Transistor sizes are already at the nanometer scale, and this causes many practical difﬁculties. At the time of publication of this book, many consumer products are using a 45 nm fabrication process, and 32 nm technology has already been demonstrated. At these small sizes, fundamental limitations have to be considered. Entire books have been written on the subject, and here we describe only a few such challenges. One primary example of these difﬁculties is a quantum phenomenon known as tunneling, visualized in Figure 1.5. Due to the wave nature of particles, electrons can ‘‘jump,’’ or tunnel, through barriers with some nonzero probability. This probability increases exponentially as the size of the barrier decreases. The size of

7

1.3. THE MICROCOMPUTING ERA: THE TRANSISTOR AS A SWITCH

1,000,000,000

100,000,000

Number of Transistors

10,000,000

1,000,000

100,000

10,000

1,000

100 1970

1975

1980

1985

1990

1995

2000

2005

Year

Figure 1.4. The number of transistors found in commercial processors. Note that the y-axis is logarithmic. This exponential trend is mostly due to the decreasing size of transistors. It is expected that very soon transistors will become as small as physically possible, which motivates the exploration of other devices that may be smaller and more powerful. Data acquired from [2].

transistors has decreased so much that in today’s tiny transistors, electrons regularly tunnel between the gate and the wire. (Fig. 1.6). Since electrons and charge cannot be controlled as easily at the nanometer scale, the transistor behaves less and less like an ideal switch. Tunneling has become part of a larger tradeoff between performance and power consumption. The size of transistors has reached the point where traditional models of transistors cannot be applied without a detailed understanding of nonideal characteristics [3]. There are many reasons that electrons can unintentionally leak across the wire, even when the gate tries to block current. Furthermore, the smaller the wires become, the more difﬁcult it becomes for electrons to move through wires; that is, thinner wires have greater resistance. Because of this, even more power is required to push electrons through the wires quickly. Most processors today are limited to about 4 GHz, largely because power requirements beyond this speed are too costly and generate too much heat for a processor to function properly. Many creative solutions have kept transistors useful despite these limitations. For example, by placing the appropriate stress or strain on the crystalline

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CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

An electron wave becomes a decaying signal as it tries to penetrate a barrier.

If the barrier is thin enough, the wave can continue on the other side.

Figure 1.5. Visualization of the tunneling phenomenon. Mathematically, the wave changes into an exponential decay when it enters a region of ‘‘high potential’’—the barrier—and resumes as a wave after it exits. The probability that an electron will tunnel across the barrier is related to how much amplitude the wave has left once it exits the barrier.

structure of silicon, electrons can move through a transistor more easily. This can be done by adding materials on top of transistors that naturally want to bend, thus pulling or pushing on the silicon. The so-called strained silicon [4] has quickly become a standard technique to improve the performance of transistors at 90 nm or less. Another example is the development of better insulating materials, known as high-K dielectrics [5]. The right combination of conducting and insulating materials can reduce the amount of undesirable tunneling between the gate and channel, even when the barrier is only a few layers of molecules thick. This advancement has been the key towards 45-nm technology. In the future, it may be necessary to use multiple gates to reliably control the current along a wire. FinFETs [6] or trigate transistors [7] are two multigate variations of transistors that may take us beyond 45 nm. There are several more limitations when using tiny transistors that motivate the nanocomputing ideas presented in this book. First, the wiring that interconnects transistors is becoming a very signﬁcant limitation for performance, power, and size of devices. There are even theoretical limitations about how much

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Figure 1.6. One of many nonideal effects in a transistor is that electrons in the gate may tunnel into the wire. This occurs more often as the thickness of the insulating barrier decreases.

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1.4. BEYOND THE TRANSISTOR: NANOSCALE DEVICES

− − − − − − − − −

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Figure 1.7. When transistors become very tiny, electrons can tunnel across the channel when the gate tries to block current ﬂow. If the channel length is small enough, electrons will regularly tunnel in this way, and the gate would no longer effectively control current ﬂowing through the wire.

area interconnections require as long as we connect transistors with traditional wires [8]. As we will see in the next few sections, there are many ideas in this book that reduce the limitations of wiring. Second, variations during fabrication are now becoming a very signiﬁcant problem. Relative to such tiny transistors, variations in geometry or chemical concentrations can easily change or break the behavior of the transistor. This variability decreases the yield and reliability of devices. Fault-tolerant methodology (Chapter 10) is desired for computing under unreliable conditions, and new fabrication methods, such as self-assembly (Chapter 12), may be better for reliable fabrication at the nanometer scale. Furthermore, reconﬁgurability (Chapter 5) offers a way to keep a device useful by updating or ﬁxing its functionality. Finally, when transistors become very small (below 5 to 15 nm approximately), electrons will be able to tunnel in a different, much more challenging way: electrons would be able to tunnel through the channel itself, even when the gate tries to block current, defeating the purpose of a gate entirely (Fig. 1.7). It is currently not clear how to overcome this upcoming problem, except to ﬁnd a better nanoscale device that can behave like a switch [9].

1.4. BEYOND THE TRANSISTOR: NANOSCALE DEVICES In practice, the use of transistors has been so successful that so far it remains unchallenged as the ‘‘best way’’ to use physics for computation. However, as mentioned above, it is not clear that the transistor will continue to be the best device to use as a switch at the nanometer scale. One major facet of nanocomputing research is ﬁnding new devices that exhibit switching or other behaviors that are useful for computing. Unlike the classical transistor, these

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CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

devices very directly embrace the properties of quantum physics to serve their function. In this section, we brieﬂy describe various nanoscale device technologies, referring to the speciﬁc chapters where topics are discussed in more detail. It should be noted that this introductory material is not intended to be a comprehensive list of nanoscale devices; such information can be found in later chapters. In fact, this section only describes a mere fraction of the devices that are being explored at the nanometer scale. Instead, the purpose of this section is to give an intuitive understanding for several common aspects of nanoscale devices.

1.4.1. Molecular Devices In general, there are a huge variety of molecules and structures that can be explored (for example DNA, proteins, rotaxanes, nanotubes, and more) [10]. In some sense, atoms and molecules are just highly complicated toy blocks: there are an inﬁnite number of ways to assemble molecules into something useful, limited only by the creativity of future research. Molecular structures can be used to create very tiny switches, ranging from 1 to 10 nm in size. One possible approach is to control how easily electrons can ﬂow through the molecule, very much like a transistor, but with different underlying physics (e.g., [11]). Another possible approach is to control how light is absorbed or scattered by the molecules (e.g., [12]). These interactions with molecules can be controlled in many different ways, for example, by applying a nearby voltage or by changing the structure of molecules. Molecular switches and molecular computing are discussed further in Chapter 11. A big challenge with molecular switches—and many nanoscale devices—is to effectively fabricate and interconnect them to perform complex logic functions. In an attempt to circumvent these problems, one proposed molecular device is the NanoCell [13]. The NanoCell tolerates defects and variability that occur during self-assembly fabrication. To provide reliability, the NanoCell depends on postfabrication ‘‘training’’ to create the desired logic function. This approach is interesting for two reasons. First, the logic function of the NanoCell can (ideally) be reconﬁgured instead of permanently ﬁxed; second, it allows the use of larger and fewer wires to connect between different cells. The function implemented by a single cell would be equivalent to using many transistors, thus simplifying the arrangement of large-scale computations.

1.4.2. Nanotubes One interesting class of molecular devices is nanotubes, particularly carbon nanotubes. Recall that pure carbon has two common crystalline forms: diamond, where carbon atoms form a three-dimensional structure; and graphite, where carbon atoms form ﬂat sheets that can easily slide and peel from each other. A single-wall carbon nanotube (Fig. 1.8) can be visualized as a single sheet of graphite rolled into a tube (though it is not created in this way), with a diameter of only a few nanometers.

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11

Figure 1.8. Visualization of carbon nanotubes (CNT), an exciting class of molecular devices. CNTs can be visualized as a sheet of graphene (top) rolled into a tube, though they are not created this way. Note that these two nanotubes have slightly different conﬁgurations. Various conﬁgurations of nanotubes can result in drastically different physical properties. Images created by Gabriele Nateneli.

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CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

Carbon nanotubes have very interesting mechanical and electrical properties. Mechanically, they are extremely strong and versatile. The tensile strength and stiffness of carbon nanotubes are extremely high, especially relative to their weight. Also, two tubes arranged with one inside the other can have a very low friction interface, similar to the way two ﬂat sheets of graphite can very easily slide over each other. Therefore, two nanotubes can have very efﬁcient telescoping and rotation motions, useful for nanomachines [14]. Electrically, a nanotube can potentially behave as a ballistic conductor. This means that an electron travels through the tube with small, quantized levels of resistance. The typical levels of resistance are much lower than traditional conductors. Nanotubes can exhibit properties of a metal or a semiconductor, depending on how the sheet of graphite is rolled into a tube. It has even been suggested that nanotubes can behave like a waveguide, guiding the wave-like properties of an electron similar to the way electromagnetic (optical) waves are guided through a ﬁber-optic cable [15]. All of these properties are being investigated for future switches and wires. In fact, switches, wires, and support structures have all been demonstrated with carbon nanotubes, but, as with many nanoscale devices, the ability to fabricate a practical nanoscale device with nanotubes and nanowires is still an open challenge. Carbon nanotubes are discussed further in several chapters in this book. See Chapter 2, Chapter 12, and Chapter 18.

1.4.3. Quantum Dots and Tunneling Devices Many quantum phenomena occur when conﬁning electrons to a very small space, such as the nanoscale range. For example, an electron conﬁned to a small area can only have a select few discrete levels of energy, similar to the discrete levels of energy that an electron may have as part of an atom. When a group of electrons is conﬁned in all axes of movement (i.e., in three dimensions), a quantum dot is formed. Similarly, a quantum wire is a group of electrons conﬁned along a 1-dimensional line, and a quantum well restricts electrons to a 2-dimensional plane. These structures can exhibit properties similar to electrons in atoms or molecules, even if there is no nucleus of protons and neutrons. Their properties can be ﬁne-tuned with more freedom than atoms or molecules, making them very interesting structures to use for computing. Often, the phenomenon of tunneling, described previously, is combined with quantum dots, wires, and wells to create useful devices. This is in contrast to traditional transistors, where tunneling is very undesirable. Three such nanoscale devices are the resonant tunneling diode (RTD), the single electron transistor (SET), and quantum-dot cellular automata (QCA). An RTD is a device that has a quantum well where electrons can be conﬁned; therefore, electrons in this region can assume only a few possible discrete energy states. When the energy of an incoming electron is close to one of these ‘‘resonant’’ discrete energy states, the electron can tunnel through with high probability. This device can emit extremely high frequencies, in the hundreds of GHz, making it interesting for

13

1.4. BEYOND THE TRANSISTOR: NANOSCALE DEVICES

high-speed applications. RTDs can also be arranged to perform logic functions, digital or otherwise. For example, RTDs have been used to implement cellular automata and cellular nonlinear networks [16, 17], two paradigms described below. A single-electron transistor, or SET [18], operates on a principle similar to a conventional transistor: a gate can control the ﬂow of electrons through a channel. However, unlike the classical transistor, in a SET the ﬂow of a precise number of electrons is controlled. The device consists of a quantum dot between two barriers. When the gate has a negative electric ﬁeld, the properties of the quantum dot are changed, effectively preventing electrons from entering (Fig. 1.9). When the gate does not block the ﬂow of electrons, the space between two barriers accepts only a few electrons, typically allowing single electrons to tunnel through one at a time. In addition to quantum phenomena, an important mechanism that is generally dominant in SETs is the so-called coulomb blockade, which is essentially a classical effect, arising from the fact that charge is not continuous, but comes in packets of one electron each. The mutual repulsion of individual electrons, when conﬁned to very small regions, leads to this effect. Currently, the smallest SETs are just as large as transistors, but it is expected that SETs will be able to shrink well beyond the limits of classical transistors. RTDs, SETs, quantum dots, and many other related devices are discussed further in Chapter 2. Another interesting use of quantum dots is in quantum-dot cellular automata (QCA) [19]. A single QCA cell is a container that has several quantum dots. Electrons in this container tunnel between the dots in order to try and ﬁnd the ‘‘ground state,’’ that is, the state where the cell is at its lowest energy. A QCA cell has only two stable states, as shown in Figure 1.10. With two states, a QCA cell can realize the digital abstraction (i.e., logic 0’s and 1’s). However, there is no switching behavior in this concept. Instead, QCA are based on the property that adjacent cells prefer to have the same ground state. At the inputs, the cells can be constrained. Depending on how cells are arranged, the constrained inputs will propagate in

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Figure 1.9. Conceptual illustration of a single-electron transistor (SET). A quantum dot (small conﬁned space containing electrons) exists between two tunneling barriers, and electrons can tunnel in and out of the dot, one at a time. When the gate has electrons, the quantum dot changes and no electrons can ﬂow from one side to the other.

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CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

0

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Figure 1.10. Depiction of quantum-dot cellular automata (QCA). Each cell has several quantum dots (in this case ﬁve). A cell can have two possible states, where electrons are diagonally oriented. When the input value is changed, the change propagates over time, this particular arrangement of cells represents a logic function that inverts the input.

different ways, allowing for many interesting logic functions. Since there are no wires interconnecting various cells, they can be arranged very compactly, in turn allowing for compact logic functions. Note that quantum dots are only one of serveral ways to implement QCA cells. QCA are discussed in Chapter 4.

1.4.4. Spin Devices Electron spin is another interesting quantum effect that can be used to create nanoscale switching devices. Various particles can have different types of spin, but electrons in particular can have only two types: spin up and spin down. This is a natural way to introduce the digital abstraction. Furthermore, electron spin is a main nanoscale property that results in macroscopic magnetic ﬁelds. For example, if most of the electrons in a metal object assume a polarized spin state (either all spin up or all spin down), the metal object will be magnetic. One interesting phenomenon that is a result of the relationship between magnetism and electron spin is the magnetoresistive effect: the resistance of some materials can change depending on the surrounding magnetic ﬁeld. Magnetoresistance is already widely used as the mechanism to read data from a disk drive that stores information magnetically. Manufacturers are also considering the possibility of magnetic random-access memory (MRAM), which would use magnetoresistance to implement nanoscale memory cells. MRAM may have a number of advantages over other types of memory storage. It is expected to have the high storage density of today’s dynamic RAM technology, while providing the high speed and power savings of today’s static RAM technology. Magnetoresistance can also be used to create a switching device. This sort of switch is called a spin transistor, or transpinnor [20]. Recall that a classical transistor uses an electric ﬁeld to make it difﬁcult for electrons to travel across the wire. Similarly, a spin transistor uses magnetoresistance to drastically increase the resistance of the wire, effectively blocking current like a switch. Magnetic storage is discussed in Chapter 6, and spin devices are discussed further in Chapters 7 and 9.

1.5. BEYOND THE SWITCH ABSTRACTION: NANOSCALE PARADIGMS

15

1.5. BEYOND THE SWITCH ABSTRACTION: NANOSCALE PARADIGMS The use of switches has fundamental limits. At some point, researchers may achieve a switch that is plainly as small as possible. This would mean that the exponential decrease in size of transistors would stop—the end of Moore’s Law. It would be desirable to ﬁnd a new way of continuing Moore’s Law, not in the literal sense that transistors could get smaller, but rather that technology could continue to exponentially improve. Furthermore, the complexity of interconnecting switches is a fundamental limitation; even today, the wires are becoming the limiting factor when making high performance nanoscale transistors. In fact, there is no indication that switches, binary logic, or transistors are the best way to compute. This motivates the search for entirely new paradigms of computing that could eventually replace the digital and switch abstractions. Of course, the common thread in the ideas we consider is that they can be realized at the nanoscale level. Here we brieﬂy describe some of the major paradigms of computing that are part of nanocomputing research, as well as mention the corresponding chapters where they are discussed further. As before, this section is not intended to be comprehensive; instead it aims to inspire the reader by illustrating some novel approaches to computing and how drastically different they are than today’s computing technology.

1.5.1. Cellular and Neural Logic One paradigm is the use of emergent properties. The idea is to use a large number of extremely simple processors. Alone, each processing element can be extremely small, and it can do only a limited number of trivial functions. However, powerful computers ‘‘emerge’’ from a group of such processors. Cellular automata, cellular nonlinear networks, and artiﬁcial neural networks are major examples of this paradigm. Cellular automata (CA) [21, 22] can be understood as a regular grid of identical cells, where each cell changes its state depending on its own state and the state of its neighbors (Fig. 1.11). Cellular nonlinear networks (CNN) [23] are similar to cellular automata, the main difference being that each cell in a CNN is an analog processor. Neural networks [24], unlike CA or CNN, use simple units that simulate the behavior of biological neurons. Figure 1.11 shows an example of how a behavior can emerge from a cellular automaton. At each step, every cell changes depending on the previous state of its neighboring cells. The pattern shown in this ﬁgure repeats every four steps, but gradually moves diagonally as well. This diagonal movement is a property that emerges from the group of cells. The rules that deﬁne how all cells behave are very simple, but the result is a rich, complex world of emergent properties that are being studied by many mathematicians and scientists and can be used for computation. In nanocomputing, the idea of having a huge number of very simple nanoscale structures is appealing for many reasons. The challenge of how to fabricate such

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CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

Figure 1.11. Example of a simple cellular automaton. Each cell can be ‘‘on’’ (black) or ‘‘off’’ (white). Depending on its neighbors, a cell may turn on or off in the next time-step. This speciﬁc example shows a ‘‘glider,’’ a structure that emerges from rules deﬁned by the famous ‘‘Game of Life’’ by John Conway [25]. As time goes forward, the glider moves diagonally. More complex cellular automata can compute anything that a traditional computer can, and possibly more.

a computer becomes much easier because the same nanoscale structure can be repeated in a regular pattern. Most of the ideas in this paradigm are also faulttolerant, that is, able to handle a few defective cells or neurons. This alleviates the problem of variability when fabricating nanoscale devices. Their regular structure usually implies that they can perform different functions depending on the context, instead of being permanently hard coded with a ﬁxed function; in other words, such computers are highly reconﬁgurable. Most importantly the potential computing power that is available with emergent properties is immense and only beginning to be explored. Even with the limited understanding of emergent properties, this paradigm already has many applications. Cellular automata and cellular nonlinear networks have been mostly used for image processing applications due to the highly parallel nature and intuitive correspondence between each simple processor and pixels on an image. Neural networks have been extensively studied for their applications in artiﬁcial intelligence and are useful practically anywhere uncertainty is encountered in computation. It has also been shown theoretically that cellular automata and neural networks can do anything that today’s computers can do [26, 27]. With all this in mind, one of the main challenges of this paradigm is to ﬁnd a way to harness emergent properties for a wider variety of applications. Nanoscale devices that implement cellular automata, cellular nonlinear networks, and neural networks are actively being researched. NanoCells, quantumdot cellular automata (QCA), and RTDs, described in the previous section, are just a few possible ways to realize this paradigm. Quantom-dot cellular automata are discussed in Chapter 4, and nanoscale neural networks are discussed in Chapter 17.

1.5.2. Wave Computing Waves are an elegant but complicated way to communicate and manipulate abstract data. One of the most powerful features of waves is the phenomenon of diffraction, or the behavior of light as it propagates around objects or through a nonuniform medium. Perhaps the best known example of the power of diffraction

1.5. BEYOND THE SWITCH ABSTRACTION: NANOSCALE PARADIGMS

17

is seen—literally—in holography. To display a hologram, light waves are diffracted through patterns that were previously recorded. The diffraction of light actually reproduces all the waves of light that were originally recorded. Because of this, visual holograms are well known to have accurate details and amazing realism. Holography has found many other important engineering applications because diffraction can manipulate light waves in a ﬂexible, powerful way. Equally important is the superposition of waves. Consider two waves that are traveling in opposite directions (Fig. 1.12). The waves continue with the same direction and speed, unaffected by each other. However, if desired, one could measure the intensity of the point where both waves cross. The propagation of the waves remains unaffected, but the intensity measured at a point where two waves overlap would be the sum of both waves, a result of constructive or destructive interference. This provides a convenient way to overcome the signiﬁcant limitation of wiring: use waves for communication instead of particles. Because of superposition, waves can cross over each other without destroying the information being carried. In addition to guided waves, one could also use waves in free space, removing dependence on wiring. This may seem like a small matter at ﬁrst, but as shown later in this book, it allows for signiﬁcant improvements in theoretical algorithmic performance of computations. Note that improving algorithmic performance is usually more beneﬁcial than simply making a processor ‘‘smaller and faster.’’

Figure 1.12. Visualization of how two waves cross. Unlike wires carrying an electrical signal, waves can occupy the same space while propagating. However, even though propagation over time remains unaffected, as they cross, the waves do interfere.

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CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

In addition to being used for communication, waves can also be used for computation by using interference. For example, constructive and destructive interference can result in either a high intensity or low intensity—introducing the digital abstraction without any switches. Furthermore, several waves can be combined at a single point, an occurence that can be advantageous over traditional logic that requires many transistors to handle many inputs. By combining the beneﬁts of waves over wires with the functionality of waves over transistors, many limitations, theoretical and practical, can be overcome. The visual portion of the electromagnetic spectrum has wavelengths on the order of hundreds of nanometers, slightly larger than the nanoscale level. The principles of diffraction and interference, however, apply to any type of wave, including X-rays and electrons that have nanoscale or smaller wavelengths (recall from Fig. 1.1). Another useful nanoscale wave, known as a spin wave, occurs when the spin state of previous electrons affects the spin state of nearby electrons, causing a propagation of the change in magnetic ﬁeld (recall that magnetism is the macroscopic property of spin). In addition to the many beneﬁts of wave computing described above, a key beneﬁt of spin waves is that they can conveniently communicate with electronic devices as well. Spin waves for computation are described in Chapters 7, 8, 9, 14, and 19.

1.5.3. DNA and Protein Computing DNA and protein are nanoscale molecular structures found in almost all existing biological life that we know. Recall that DNA is essentially a sequence of four primitive molecular structures: adenine (A), cytosine (C), guanine (G), and thymine (T), attached to a molecular ‘‘backbone.’’ The main property that can be exploited for computing is that adenine bonds only to thymine, and cytosine bonds only to guanine. This means that a sequence of these base pairs has exactly one complementary sequence that will bond to it. By setting up speciﬁc sequences of DNA, many clever interlocking ‘‘tiles’’ can be created, and the way these tiles interact is used for computation. Proteins are complex molecules comprised of a string of amino acids. Biologically, the sequence of amino acids that create a protein is deﬁned by a sequence of DNA. Various proteins can interact to perform useful computations, for example, by exploiting the way a protein structure folds. Proteins are much more complex than DNA, and their use for computation has so far only been simulated [28]. The power of this paradigm is the principle of constraint satisfaction. Here, instead of representing abstract operations as physical phenomena, abstract rules are enforced (in this case with molecular structure), and physical phenomena (in this case, bonding between structures) do their best to ﬁnd the lowest state of energy within the constraints. Performing constraint satisfaction in this way makes it possible to compute many things that are otherwise very difﬁcult. The best example is a demonstration of DNA computing to solve the Hamiltonian Path Problem [29]. This is a well known problem in theoretical computer science

1.5. BEYOND THE SWITCH ABSTRACTION: NANOSCALE PARADIGMS

19

for which the best known solutions currently take exponential amounts of time. Because of this high complexity, only very small, trivial inputs can be solved by a traditional computer. To solve a large exponential problem on a traditional computer can take years, or even decades, even with all the computing power available in the world! Many real world problems are also exponentially difﬁcult, and being able to quickly solve these problems would profoundly impact the world. While DNA computing still performs an exponential amount of computation, by using constraint satisfaction of nanoscale physics, this paradigm can quietly bypass many of the limitations of traditional computers, allowing the solution of the Hamiltonian Path Problem to be computed in a tractable amount of time. Note that constraint satisfaction is implicit in all physical phenomena used for computing. For example, a QCA cell in Figure 1.10 had two stable states because of the way electrons were constrained within quantum dots. The difference here is that the constraint itself is used for computation, rather than to make devices that can be used for computation. Another place that constraint satisfaction is useful is for self-assembly. By specifying tiles of DNA to connect in certain ways, the DNA can automatically assemble itself into structures that satisfy the constraints. DNA self-assembly has been demonstrated as a way to fabricate nanoscale structures [30, 31], which can then be used for other purposes (e.g., as a template to fabricate other integrated devices at the nanometer scale). The challenge with DNA and protein computing is to manage these complex molecules. Even though DNA computing solves the Hamiltonian Path Problem, extracting the computation from the reactions takes many hours of manual effort, and the constraints to set up do not scale well. For proteins, it is not yet fully understood how they fold to develop complex structures. The number of permutations with sequences of base pairs or amino acids can be astronomical, and ﬁnding sequences that result in useful structures is like trying to ﬁnd a needle in a haystack. As future research overcomes these challenges, DNA and protein computing may become an essential paradigm to solving very difﬁcult problems. Such topics are discussed further in Chapters 13 and 14.

1.5.4. Quantum Computing Further on the horizon of nanocomputing is the very powerful yet challenging ﬁeld of quantum computing [32]. Recall that the fundamental question we have been discussing is how physics can be used for computation. All the ideas discussed above, even though they use properties of quantum physics, are only used to represent intuitive, essentially ‘‘classical’’ abstractions, such as digital 1’s and 0’s. Quantum computing, on the other hand, uses the general principles and mathematics of quantum mechanics as the abstraction itself. In this paradigm, the leap from physics into an abstract world is accomplished by a qubit: the quantum analogy to the digital abstraction. Recall that a classical bit can have one of two possible states, usually denoted as 0 and 1. A qubit also has two such states, often denoted as |0S and |1S, but in this case the qubit

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CHAPTER 1: AN INTRODUCTION TO NANOCOMPUTING

actually is a combination of both states simultaneously! This combination of two states, however, is something that cannot be measured directly. When trying to observe the state of a qubit, we receive a |0S or |1S with some probability. This probability is the actual information contained by a qubit, and it is almost as if nature teases us by making this information impossible to measure. One of the key tasks of quantum computing is to manipulate this hidden information in such a way that it is meaningful to measure the qubit as only a |0S or |1S. The states |0S and |1S are actually just one ‘‘frame of reference’’ in understanding the actual underlying quantum system. One of the interesting powers of quantum computing is that we can freely decide which frame of reference we want in which to manipulate the qubit. For example, we could view the same qubit as a combination of |+S and |S, two other states that give us a different way of looking at the same qubits. Even more peculiar, two or more qubits may be completely unrelated in one frame of reference, but in another frame of reference, the qubits become entangled. This means that a change in one qubit will unavoidably affect the other qubit, and even though this complicates matters, it allows a powerful way to manipulate multiple qubits. Often, a useful quantum circuit ﬁrst manipulates qubits in one frame of reference, where they are entangled, and then uses another frame of reference where the state of the qubits can be observed. Perhaps the best known example of the power of quantum computing is its use in ﬁnding the prime factors of a given number. Traditional algorithms can take extremely long for large numbers. A quantum algorithm known as Shor’s Algorithm [33] uses quantum computing to factor prime numbers. A physical implementation of this algorithm has been demonstrated using 7 qubits, triumphantly factoring the number 15 into the prime numbers 5 and 3 [34]. While the number 15 is not large and it seems like a trivial task that could have been done with any other computer, the real landmark of this result is to demonstrate that quantum computers can indeed work as theoretically proposed. With every next qubit, the amount of hidden information in a quantum system effectively doubles. With 7 qubits, there are 128 hidden ‘‘numbers’’ that represent a combination of 128 different states. With 20 qubits, there are more than a million such hidden numbers. It might take 30–40 qubits to represent computations that exceed the potential of traditional computers, and each qubit could possibly be represented by a single nanoscale particle! While this is currently a distant dream, the foundations towards realizing this dream are being studied extensively today. Despite this awe inspiring amount of power that seems possible with quantum computation, there are many daunting challenges to be addressed before quantum computing becomes more practical. First, physically implementing a quantum computer is a tricky task. While it would be ideal to isolate a single quantum system in reality as we can do mathematically, in practice a quantum system also interacts with the rest of the world. Therefore, it is difﬁcult to keep the coherence of a quantum system, where coherence is a measure of how long the quantum system can stay intact before it gets disrupted by the surrounding environment. On the other hand, quantum phenomena such as photons of light

1.6. BIOMEDICAL APPLICATIONS

21

have a good coherence, but then it becomes difﬁcult to get the photons to interact at all. Another problem is the difﬁculty of understanding how to develop algorithms for quantum computation. Some algorithms have been proposed that use quantum computation, and a few general computing framework are being proposed for using qubits in a practical setting. Chapter 3 gives a detailed history of the contributions in quantum computing as well as a discussion of its theoretical and practical limitations.

1.6. BIOMEDICAL APPLICATIONS Recent developments in the ﬁeld of nanocomputing have laid the groundwork for technology that will revolutionize modern medicine. The most important biomedical research in the latter half of the twentieth century, which culminated in the publication of the human genome, was driven by an understanding of DNA, our genetic code. Similarly, nanotechnology has the potential to usher in an age of nanomedicine, creating a paradigm shift in the way we study and treat disease. This technology will not come without a heavy price. There are obvious ﬁnancial impediments and technical challenges, but moral and ethical concerns will also play an important role in the development of this ﬁeld. An excellent comparison can be drawn with genetically modiﬁed foods. A signiﬁcant amount of the produce and livestock grown in the United States has been subject to genetic engineering. While many consider these modiﬁcations to be safe, some are still skeptical. Various nations, particularly some in the European Union, are hesitant to embrace such technology because of a fear that genetically modiﬁed foods are inherently unsafe and may damage local ecosystems. Some say nanomedicine may suffer a similar fate. Will governments and health care professionals trust and endorse this technology? Will individuals be comfortable with nanoscale devices circulating through their bodies? Regardless of the public’s willingness to accept nanomedicine, few will dispute its potential to revolutionize the biomedical research. By providing scientists with new techniques for targeting and attacking virtually every human ailment, nanocomputing will usher in an age of medicine in which physicians and scientists can treat disease at a molecular level and attack it in a way never thought possible. As nanotechnology provides more versatile tools, the rules of engagement for diseases will change. Physicians and scientists will no longer be hindered by the small size and tremendous complexity of the human cell, but rather utilize these features to develop therapies that are more speciﬁc and effective, producing better outcomes with fewer side effects.

1.6.1. Vaults The future of nanocomputing knows no bounds and its merger with biomedical research provides unlimited pathways to discovery. It is difﬁcult to imagine an area in which there is more promise and a greater potential to revolutionize the

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scientiﬁc ﬁeld. It is also important to emphasize the importance of cooperation between scientists, physicians, and engineers to ensure the success of biomedical and nanotechnology related research. Perhaps the most intriguing development in this ﬁeld was the discovery of nanoparticles called vaults. Groundbreaking work on vaults was performed at the University of California, Los Angeles, where these nanocapsulses have fascinated scientists since their discovery [35]. Current studies have shown that vaults are found in all eukaryotic cells and are composed of protein and RNA [36]. Through precise genetic manipulation, scientists predict that vaults may be used as structural support for nanomachines as well as integral parts of nanocircuits. Perhaps most appealing is the potential of vaults to serve as vehicles for drug delivery. These nanocapsulses may one day deliver precise amounts of drug to speciﬁc cells in the body, increasing their efﬁcacy and eliminating the potential for certain adverse reactions. While this type of technology seems to be straight out of a science ﬁction ﬁlm, it is indeed very real and has a tremendous potential to usher in the age of nanomedicine. Vaults may also be used as biological sensors, detoxiﬁcation centers, and aid in environmental restoration [36]. Equally important will be their contributions to biomedical research as a whole. It is impossible to predict the full potential of vaults but they may revolutionize drug delivery, treatment of disease, and fundamentally change the way we practice medicine. Imagine for a moment a day in which vital signs, blood chemistries, and even disease progression can be monitored remotely by nanomachines. These safe and affordable nanorobots would be capable of transmitting data to a local physician and may even calculate complete blood counts, cholesterol levels, and search for invading pathogens. Some speculate that such robots could also be used to treat heart attacks and strokes by analyzing and neutralizing blood clots that pose a threat to the patient. Nanotechnology can provide physicians with more accurate and less invasive techniques for treating everything from the common cold to the most severe and debilitating diseases. Medicine would never be the same.

1.6.2. Molecular Motors In analyzing the problem of providing power for future nanocomputing devices, researchers are exploring the use of molecular motors. These motors, instrumental in the functioning of biological systems such as muscle contraction, will allow for the movement of nanorobots within organisms. All motors consume a form of energy to perform work; in the case of molecular motors, it is some form of chemical energy, such as ATP [37]. Molecular motors are attractive because they are smaller and more efﬁcient than any other man-made motor [37]. Numerous molecular motors exist, the most well-known being the proteins myosin and kinesin. Myosin lies along actin ﬁlaments in muscle cells and utilize a single ATP molecule per cycle to perform a power stroke [38]. Kinesin carries cargo in the intercellular space and uses 1 ATP to move 8 nm. The development of effective and reliable molecular motors will be essential for the utilization of nanorobots in biomedical applications.

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23

A focal point of such research is treating motor neuron diseases, such as Amyotrophic Lateral Sclerosis (Lou Gehrig’s Disease) and other types of atrophy [38]. Motor neuron diseases typically result in the degradation of neurons that control voluntary muscle, which are critical in performing tasks such as speaking and swallowing. Researchers have discovered a mutation in a molecular motor gene that leads to the buildup of improperly folded proteins in the cell. Many hypothesize that nanorobots and molecular motors may prove useful in preventing such degradation by restoring normal function to the cell and preventing the buildup of protein [37]. Scientists are currently attempting to construct nanoscale devices for this application, but they face many challenges. By studying molecular motors, they hope to discover ways for powering and mobilizing future nanodevices.

1.6.3. Nanorobots Based on the existence of vaults, it is clear that nature has created its own nanoparticles. But what about man-made nanomachines? As nanocomputing advances, the ﬁeld of nanorobotics is sure to progress as well. Approximately 10 years ago, the ﬁrst theoretical design of a nanorobot for medicinal purposes was presented to the scientiﬁc community. The device utilized 18 billion precisely arranged atoms to form a diamonoid vessel with active pumping capabilities [41]. This has the potential to deliver over 200 times more oxygen to tissues than red blood cells. Theoretical designs also exist for synthetic white blood cells that are able to digest blood-borne pathogens. These nanorobots would have the ability to operate faster and more reliably than naturally occurring white blood cells. Other designs include nanorobots with platelet functions that will allow hemostasis in as little as a single second. This complex machine would be invaluable in treating patients with severe hemorrhaging, especially in traumatic injuries. Perhaps most intriguing is the idea of a chromallocyte, a hypothetical mobile repair nanorobot capable of performing chromosome replacement therapy (CRT) [41]. This process involves the replacement of the entire chromatin content of a living cell with a prefabricated set of error-free chromosomes. This may allow for the treatment of entire organs such as the liver or heart and will without a doubt revolutionize the way we treat disease. These nanomachines will be the core of nanocomputing and nanotechnology’s biomedical applications; they represent a fundamental change in the way engineers and doctors will communicate. Indeed, it is essential for researchers on both sides of this fascinating technology to exchange ideas and strategies if they are to fully utilize the potential of nanotechnology. Nanorobotics is discussed in detail in Chapter 15.

1.6.4. Pharmaceuticals Pharmaceuticals are a multibillion dollar a year industry, evolving daily with the discovery and patenting of new drugs. Developers are constantly seeking stronger and more effective medicines that will also reduce side effects. Nanotechnology and

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nanocomputing stand as beacons of hope for fulﬁlling these goals as they encompass several areas of pharmaceuticals, including ‘‘discovery, development, delivery and even post-delivery’’ [39]. Currently, several short- and long-term projects are underway to revolutionize the industry, as well as talks with large pharmaceutical corporations [39]. The National Cancer Institute has also created a nanotechnology branch to allow companies to expedite the processing of their drugs. Presently, many of the beneﬁts achieved by this technology are decreased toxicity and reduction of side effects [39]. Two anti-cancer drugs, Doxil and Abraxane, have had their adverse effects reduced nanoformulation. Other applications include improved targeting of drugs by both oral and parenteral means [40]. These present developments are minuscule compared to the limitless longterm applications of nanocomputing and nanotechnology. Three crucial applications are in the areas of design, delivery, and drug monitoring [40]. Monitoring the efﬁciency of pharmaceuticals remains an persistent obstacle to both pharmaceutical corporations as well as medical practitioners. The use of nanorobots composed of ‘‘diamondoid nanometer-scale nanosensors’’ may allow imaging after drug delivery [41]. This would enable physicians to consistently monitor patients and evaluate the efﬁcacy of certain medicines over a broad spectrum of individuals. Additionally, by using recently pioneered nanodelivery systems, several drugs may be combined into a single ‘‘package.’’ [42].

1.6.5. The Future of Biomedical Nanotechnology The future of nanotechnology is bright and every day new and important advancements are made in the ﬁeld of nanocomputing. The merger with biomedical research will bring in a new age of scientiﬁc development unlike anything we have ever seen. Like the biotechnology revolution of the 1960s and 1970s, biomedical nanotechnology will revolutionize research and provide an almost inﬁnite supply of techniques for treating the most challenging ailments. Even the simplest tasks may be delegated to nanomachines, which make fewer mistakes and will monitor parts of the human body not possible by physicians. The brain, heart, liver, kidneys, and other vital organs may be under the constant watch of millions of nanorobots that can take precise and accurate measurements in real time. This data can be sent to a local computer where it is processed and transmitted to a healthcare professional for analysis. Doctors will change their approach to treating disease, and computing in nanotechnology will make diagnoses more accurate, treatments more effective, and lives more fulﬁlling. The technology is real. The potential is real. All we need is time. Chapters 15, 16, and 18 provide additional information.

1.7. NANOCOMPUTING AND NEUROSCIENCE Nanotech applications in biology and medicine now allow for surgeons to induce desired physiological responses in the human body throughout the central nervous

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25

system (CNS). Pioneer work being done in this novel ﬁeld may one day bring us numerous new therapeutic choices that hold much less risk for patients, as well as prove a more convenient means for surgeons to handle molecular machinery. According to Dr. Gabriel A. Silva, technological advancements must occur alongside clinical neuroscience advancements [43, 44] simply because of the highly interdisciplinary nature. An emerging ﬁeld of neuroscience nanocomputing is the production of materials and devices designed to interact with neurons at the molecular level. The developing platform technology of nanowires that is to be discussed in this section may prove to have broad applications in neuroscience and, of greater importance, possess the potential to save lives much sooner than expected.

1.7.1. Nanomachinery: Opportunities and Challenges Imagine wires that were hundreds or thousands of times thinner than the human hair, utilizing blood vessels in the body as conduits towards adjacent individual neurons. These are what we would call nanowires [45]. Dr. Charles M. Leiber, an interested researcher at Harvard University in the ﬁeld of nanocomputing, invented a nanowire transistor that can detect, stimulate, and inhibit neuronal signals [46]. This gives rise to the question of what a nanowire is. In simple terms, a nanowire is a wire of dimensions in the order of a nanometer. These range in makeup, being either metallic, semiconducting, or insulating. Some previous technology was available in this area but was too large in size. Micropipette electrodes were previously available but were harmful to cells in that they destructively poked cells. By contrast, the tiny nanowire transistors developed by Lieber and colleagues gently touch a neuronal projection to form a hybrid synapse, making them noninvasive and thousands of times smaller than the electronics now used to measure brain activity [46]. In addition to being nonintrusive, nanowires can be biodegradable, biocompatible, and capable of producing diagnostic test results in minutes instead of days. A great effort has already been invested in this nanomachinery, and a series of promising results have thus been revealed. One such opportunity is the silicon nanowires’ precision in its detection of bioterrorism threats. When discussing neuropathological disease processes at a molecular level, scientists can observe that there is potential in a nanowire’s ability to limit such disease processes with early detection. Unlike conventional DNA sensors, such nanowire techniques provide much more detailed information on the scale of neurons, as well as give a sharper focus of disease markers in perhaps any bodily ﬂuid in humans [47]. Likewise with degenerative diseases such as Parkinson’s and Alzheimer’s, nanowires provide hope for treatment rid of damaging side effects (brain tissue scars) by stimulating the affected area of the brain with wires tinier than capillaries themselves. Many researchers envision nanowires connected to a catheter tube and able to be guided throughout the circulatory system to the brain, where nerveto-nerve interactions will allow neuroscientists to make earlier diagnoses and provide earlier treatment without the cost of time consuming procedures.

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Through electrophysiological measurements of brain activity, made possible by nanowires, important signal propagation through individual neurons and neural networks can be understood. Sophisticated networks between the brain and external prosthetic technology can be produced through this revolutionary manipulative technique. Much of this technology has great potential in the ﬁeld because it can be used to monitor signaling among larger networks of nerve cells, thereby allowing doctors to detect electrical activity going on between neurons, tumors, and brain abnormalities; to localize seizures; and to pinpoint damage caused by injuries and stroke [47]. Eventually, the technology will be used to detect the diverse kinds of neurotransmitters that leap synapses from neuron to neuron. The mystery behind many neural system disabilities such as mental illnesses and certain paralysis diseases could be unraveled with this amazing invention in the scientiﬁc community. Working at the molecular level with nanowires still has its shortcomings and is an incredible challenge in the ﬁeld of neuroscience and nanocomputing. The extremely intricate composition of the CNS poses obvious challenges to nanocomputing’s applications in neuroscience. Speciﬁcally, these include cellular heterogeneity and multi-dimensional cellular interactions which explain the basis of its extremely complex information processing [43]. There is also the challenge of guiding nanowire probes to a predetermined location among the thousands of capillary branches in the human brain that reside in the brain’s vascular system. And because it is considerably more difﬁcult to manipulate materials on the nanoscale level, it is also difﬁcult to measure the electrical and mechanical properties of the nanomaterials themselves. Along with developing the functions of engineered machinery to carry out neural regeneration, neuroprotection, and other tasks of the sort, there is an evident need for precise and proper synthesis of such machinery. These ‘‘tailored nanotechnologies’’ cannot provide any solution to neurobiological complications unless they are designed by the most skilled and competent specialists, which in this case is not the role of the neuroscientist [44]. We know that materials scientists, chemists, and specialists of other similar disciplines have, unlike neuroscientists, devoted their careers to the synthesis of such technologies. Neuroscientists in turn contribute to this interdisciplinary science through their wealth of knowledge in neurobiology, neuropathology, and other areas. In this book, an implementation of neural network with nanotechnology is studied in Chapter 17. Evidently, these challenges have the potential to improve what may have otherwise been overlooked in synthesizing machinery. Often such obstacles help us to be more focused on the safety behind clinical neuroscience advancements.

1.7.2. Current Work and Research Functional nanotechnology, including nanocomputing, is still at its infancy stages, with numerous institutions of various scientiﬁc ﬁelds ﬁnding ways to make nanotechnology as safe and effective as can be. The government has given research grants to scientists from different universities such as Brown, Stanford,

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MIT, and CIT in order to facilitate research in such a promising ﬁeld. Leading researchers such as Dr. Charles M. Lieber of Harvard University have contributed greatly to the advancement of nanocomputing. Dr. Lieber, along with his associate Jong-in Hahm, Ph.D., recently helped start a company called NanoSys, Inc., which is currently in the process of developing nanowire technology and other nanotech products. Other researchers include neuroscientist Rodolfo R. Llinas of the New York University School of Medicine and Masayuki Nakao of the University of Tokyo [45, 47]. As the general public can see, the advent of nanotechnology is one that will affect the lives of people worldwide and not simply arrive to us as a packaged fad whose hype is short lived. The great deal of research that is currently being done on the neurological applications of nanotechnology was bolstered when six scientists at Brown University were awarded $4.25 million to begin research on such interactions in the mammalian nervous system. Along with many professionals from an array of different ﬁelds—surgery, chemistry, physics, and others—these brilliant minds are collaborating to help advance knowledge and further discovery of nanotechnology and nanocomputing. This commitment to research, coupled with a great amount of popular sentiment towards nanotechnology and nanocomputing, may further our own knowledge as observers and students and accelerate the progress of this exciting phenomenon. For more information on funding and patenting issues, see Chapter 20.

1.8. CONCLUSIONS For the past 50 years, transistors have been shrinking consistently, and we have entered the era of nanocomputing. In this new era, transistors are only a small portion of the technologies that are available at nanoscale. There is a vast landscape of nano devices and paradigms that are currently being studied. In this chapter, we gave a brief introduction to nanocomputing and presented a high level overview of nanocomputing devices and paradigms. Nanocomputing has a potential to provide a remedy for some traditional problems in microelectronics. We also discussed some applications of nanocomputing such as bio medical engineering and neuroscience. The rest of this book will take the reader on a journey from low level device physics to architecture-level, bio-inspired architectures, all of which have the potential to be used for implementing various devices, such as biomedical and biomimetic nanoscale integrated circuits.

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3. N. Weste and D. Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Reading, MA: Addison Wesley, 2004. 4. C. K. Maiti, N. B. Chakrabarti, and S. K. Ray. Strained Silicon Heterostructures: Materials and Devices. Piscataway, NJ: IEEE, 2001. 5. M. Houssa. High k Gate Dielectrics. New York: AIP, 2004. 6. X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, and C. Hu. Sub 50-nm ﬁnFET: PMOS. Electron Devices Meeting, 1999. IEDM Technical Digest International: pp 67–70, 1999. 7. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau. High performance fully depleted tri-gate CMOS transistors. IEEE Electron Device Letters, 24(4): pp 263–265, Apr 2003. 8. Harold Abelson and Peter Andreae. Information transfer and area-time tradeoffs for VLSI multiplication. Communications of the ACM, 23(1): pp 20–23, 1980. 9. J. Wang and M. Lundstrom. Electron Devices Meeting, 2002. Does source-to-drain tunneling limit the ultimate scaling of MOSFETs? In: IEDM ‘02 Digest. International: pp 707–710, 2002. 10. V. Balzani, A. Credi, and M. Venturi. Molecular Devices and Machines: A Journey into the Nanoworld. Weinheim: Wiley-VCH, 2003. 11. Y. Chen, G. Y. Jung, D. A. A. Ohlberg, X. Li, D. R Stewart, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, and R. S. Williams. Nanoscale molecular-switch crossbar circuits. Nanotechnology, 14(4): pp 462–468, 2003. 12. B. L. Feringa. Molecular Switches. Weinheim: Wiley-VCH, 2001. 13. J. M. Tour, W. L. Van Zandt, C. P. Husband, S. M. Husband, L. S. Wilson, P. D. Franzon, and D. P. Nackashi. Nanocell logic gates for molecular vomputing. Nanotechnology, 1(2): pp 100–109, Jun 2002. 14. J. Cumings, A. Zettl. Low-friction nanoscale linear bearing realized from multiwall carbon nanotubes. Science, 289(5479): pp 602–604, 2000. 15. W. Liang, M. Bockrath, D. Bozovic, J. H. Hafner, M. Tinkham, and H. Park. Fabry– Perot interference in a nanotube electron waveguide. Nature, 411: pp 665–669, June 2001. 16. A. Khitun and K. L. Wang. Multifunctional edge driven nanoscale cellular automata based on semiconductor tunneling nanostructure with a self-assembled quantum dot layer. Superlattices and Microstructures, 37(1): pp 55–76, 2005. 17. A. Khitun and K. L. Wang. Cellular nonlinear network based on semiconductor tunneling nanostructure. IEEE Transactions on Electron Devices, 52(2): pp 183–189, Feb 2005. 18. M. A. Kastner. The single electron transistor and articial atoms. Annalen der Physik, 9: pp 885–894, Nov 2000. 19. C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernstein. Quantum cellular automata. Nanotechnology, 4(1): pp 49–57, 1993. 20. M. Johnson. Bipolar spin switch. Science, 260(5106): pp 320–323, 1993. 21. S. Wolfram. A New Kind of Science. Wolfram Media, 2002. 22. A. Ilachinski. Cellular Automata: A Discrete Universe. Singapore: World Scientiﬁc, 2002. 23. L. O. Chua and L. Yang. Cellular Neural Networks. Circuits and Systems, 1988.

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24. C. M. Bishop. Neural Networks for Pattern Recognition. Oxford, UK: Oxford University Press, 1994. 25. M. Gardner. Mathematical games: the fantastic combinations of john conway’s new solitaire game ‘life.’ Scientiﬁc American, 223(4): pp 120–123, 1970. 26. M. Cook. Universality in elementary cellular automata. Complex Systems, 15(1): pp 1–40, 2004. 27. T. Roska and L. O. Chua. The CNN universal machine: an analogic array computer. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 40(3): pp 163–173, Mar 1993. 28. C. N. Eichelberger and K. Najarian. Simulating protein computing: character recognition via probabilistic transition trees. IEEE International Conference on Granular Computing, 2006. pp 101–105, May 2006. 29. L. M. Adleman. Molecular computation of solutions to combinatorial problems. Science, 266(11). 30. P. W. Rothemund, N. Papadakis, and E. Winfree. Algorithmic self-assembly of DNA sierpinski triangles. PLoS Biology, 2(12): Dec 2004. 31. P. W. Rothemund. Folding DNA to create nanoscale shapes and patterns. Nature, 440: pp 297–302, 2006. 32. M. A. Nielsen and Isaac L. Chuang. Quantum Computation and Quantum Information. Cambridge: Cambridge University Press, 2000. 33. P. W. Shor. Algorithms for Quantum Computation: Discrete Logarithms and Factoring. IEEE Symposium on Foundations of Computer Science: pp 124–134, 1994. 34. L. M. Vandersypen, M. Steffen, G. Breyta, C. S. Yannoni, M. H. Sherwood, and I. L. Chuang. Experimental realization of Shor’s quantum factoring algorithm using nuclear magnetic resonance. Nature, 414: pp 883–887, Dec 2001. 35. N. L. Kedersha, D. F. Hill, K. E. Kronquist, L. H. Rome. L.H. Subpopulations of liver coated vesicles resolved by preparative agarose gel electrophoresis. Journal of Cell Biology, 103: pp 287–297, 1986. 36. National Science Foundation. ‘‘Vaults: From Biological Mystery to Nanotech Workhorse?’’ Biological Sciences, Arlington, VA: The National Science Foundation. http:// www.nsf.gov/discoveries/disc_summ.jsp?cntn_id=104106&org=MCB, 2007. 37. Regents of the University of Michigan. Molecular Motors. http://www.umich.edu/ news/MT/04/Fall04/story.html?molecular. Jan 16, 2007. 38. Y. E. Goldman. Functional studies of individual myosin moleculares. Annals of the New York Academy of Sciences, 1(18): 2006. 39. C. McCarthy, Nano Science and Technology Institute. Pharma Explores Business Opportunities for Nanotech. http://www.nsti.org/news/item.html?id=. Mar 13, 2007. 40. Cirrus Pharmaceuticals. Pharmaceutical Nanotechnology. http://www.cirruspharm. com/pdf/brochures/Nanotechnology.pdf. Mar 13, 2007. 41. R. A. Freitas. Computational Tasks in Medical Nanorobotics. Insitute for Molecular Manufacturing, 2007. 42. P. Chapman. Nanotechnology in the pharmaceutical industry. Expert Opinion on Theraperutic Patients. 15(3): pp. 249–255, 2005. 43. G. A. Silva. Introduction to nanotechnology and its applications to medicine: applying nanotechnology to medicine. Surgical Neurology, 61: pp 216–220, 2004.

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44. G. A. Silva. Neurosicence nanotechnology: progress, opportunities, and challenges. Nature Reviews Neuroscience, 7: pp 65–74, 2006. 45. National Science Foundation. Nanowires in blood vessels may help monitor,sStimulate neurons in the brain. http://www.nsf.gov/news/newssumm.jsp?cntnid=104288&org= ENG. July 7, 2005. 46. F. Patolsky, B. P. Timko, G. Yu, Y. Fang, A. B. Greytak, G. Zheng, and C. M. Lieber. Detection, stimulation, and inhibition of neuronal signals with high-density nanowire transistor arrays. Science, 313: pp 1100–1104, 2006. 47. Tiny Nanowire Could be Next Big Diangostic Tool for Doctors. Science Daily: Dec. 18, 2003.

2 NANOSCALE DEVICES: APPLICATIONS AND MODELING Alireza Nojeh This chapter starts with a discussion of the roots of nanotechnology, the distinguishing aspects of the nanoscale, and the deﬁnition of nanoscale devices. Some of the common materials and techniques used to fabricate such devices are brieﬂy reviewed. The physics of the operation of nanoscale devices is the subject of the next part. Quantum dots, resonant tunneling diodes, and single-electron transistors, which can be made using traditional fabrication methods, are ﬁrst studied. Then a number of devices based on newer materials such as carbon nanotubes are introduced, and how the properties of these materials provide opportunities for innovative device design is discussed. The last part of the chapter deals with the theoretical study, modeling, and simulation of nanoscale devices. The challenge of the many-body problem and the difference between ﬁrstprinciples and semi-empirical approaches are highlighted. A brief introduction to some of the simulation methods, such as the Hartree–Fock approximation, density functional theory, molecular dynamics, tight-binding, and Monte Carlo, concludes the chapter.

2.1. INTRODUCTION 2.1.1. The Roots of Nanotechnology Although one can easily think of many milestones, such as the invention of the scanning tunneling and atomic force microscopes or the discovery of fullerenes in the 1980s, that have pushed us more and more into the nano era, it is not easy to deﬁne a single point in time when it all started. For instance, many of the imaging tools relevant to the nanoscale, such as electron microscopes, have been around Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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for a long time. But as we see, they have been called microscopes and not nanoscopes. One tends to think that at least one aspect of what we consider nanotechnology is the extension of microtechnology to smaller sizes, and it is hard to separate the roots of these two, although some clear distinctions can be drawn between them. As discussed in Chapter 1, a particularly interesting early reference to small scale devices and technologies was made by physicist Richard Feynman in a lecture he gave in 1959 [1]. Feynman did not make speciﬁc claims about what would happen in future, but rather gave a tour of what could very logically and naturally be available at small scales from a purely scientiﬁc point of view (i.e., without contradicting the laws of physics as we know them). After almost half a century, that lecture can be an insightful introduction for newcomers to the ﬁeld of nanotechnology and a great inspiration to seasoned nanotechnologists.

2.1.2. Two Ways to Reach the Nanoscale It could be argued that one of the most dramatic changes in our lifestyles has been brought about by the rapid advance of the microelectronics industry over the last few decades. The steady decrease in the size of transistors, the fundamental building blocks of microelectronic circuits, has lead to today’s low cost and high performance computer chips. For instance, the transistors in your computer are about a tenth of a micrometer in size, or maybe even about a twentieth of a micrometer if you have recently bought a new one—that is about 50 nanometers (nm). Thus, for those who work in this industry, nanoelectronics is a completely natural continuation of microelectronics. In fact, many tend to deﬁne a device as being a nanodevice if one of its dimensions is smaller than 100 nm. In that sense, the semiconductor industry has already entered the era of nanoelectronics—without really calling itself nanotechnology! Pushing our traditional microfabrication techniques to make devices much smaller than a micrometer is one way of approaching the nanoscale. One could think of this as the art of ‘‘carving’’ ultra-small objects. However, there are objects that are very small by their nature, such as molecules. They provide another approach to nanotechnology: use small objects already available to us through nature and try to add some level of control to where and how they are arranged so that they can perform the functions we are interested in.

2.1.3. The ‘‘Nano’’ Difference As pointed out in Chapter 1, there is more to the nanoscale than just the ability to pack a large number of devices in a small area or to manipulate very small objects. There is a fundamental reason that makes ‘‘nano’’ attractive from a scientist’s point of view but a nonexpert might have a little more difﬁculty appreciating it. Let us see what that is. We know that objects are made of individual units called atoms that are extremely small. This book you are reading, for example, contains on the order of one hundred trillion trillion atoms—that is a 1 with 26 zeros in front of it! When

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such a large collection of atoms is put together, the general behavior of the ensemble in everyday life experiences does not directly reﬂect the atomistic nature of the system. It looks like a solid, bulky material for which the behavior can be explained relatively easily: You can describe it in terms of its macroscopic properties, i.e., weight, dimensions, color, etc. You can also use the laws of classical physics, such as Newtonian mechanics, to describe its motion if a force is applied to it. In fact, atoms behave according to laws discovered much later than Sir Isaac Newton’s classical mechanics. The laws of quantum mechanics, developed mainly in the ﬁrst half of the twentieth century, are rather nonintuitive for someone who is used to everyday phenomena with large objects, but they constitute the best description we have so far for the world of small particles such as atoms. Let us continue with the example of the book. When such a huge collection of atoms is put together, the overall behavior will be a statistical average of the behavior of the individual atoms, subject to external forces and the constraints that keep them together. This average behavior can be explained well with classical physics. The result is that we do not really need quantum mechanics to be able to handle a book! Now, imagine a microelectronic device, such as a transistor, with dimensions on the order of a micrometer. Such a device would contain about one trillion atoms (a 1 with 12 zeros in front of it). That is still a very large number and so, even in such a small device, most of the characteristics are determined by the statistical averages of many interactions and phenomena. Thus, although in order to properly understand these phenomena and the resulting average behaviors one needs to apply quantum mechanics, more phenomenological laws can be derived using statistical analysis that explain the device behavior accurately enough for most engineering purposes. In fact, quantum mechanics is still somewhat masked and its effects are only indirectly visible at the microscale. In other words, you do not need to resort to quantum mechanics every time you want to study or use a microscale transistor. In this sense, even microdevices could be considered somewhat classical. Now let us imagine devices that have dimensions on the order of only a few nanometers. In matter, atoms are spaced apart by a few angstroms. An angstrom is 10 times smaller than a nanometer. Thus, in the volume of our nanoscale device, there would be only a few hundred or thousand atoms. It turns out that in such small collections of atoms, statistical averages are not always very meaningful. But the individual character of each atom—its quantum mechanical nature—is much more visible. Therefore, when working with nanodevices one observes quantum mechanics very directly and, by the same token, can take advantage of the laws of quantum mechanics to design devices and systems that are not achievable at larger scales (that is, where quantum effects have averaged out to give way to more classical behavior). This direct access to quantum mechanics at the nanoscale makes a fundamental difference that involves more than manipulating small objects or squeezing a large number of devices into a small area. A whole new world of functionalities and possibilities previously unimaginable is opened up. One is tempted to argue that this is the most important aspect of the nano

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CHAPTER 2: NANOSCALE DEVICES: APPLICATIONS AND MODELING

world, but that remains to be determined by the course of progress of this ﬁeld in the future. In addition, the surface-to-volume ratio of objects increases as the objects become smaller. For instance, the surface of a cube with side x is 6x2 and its volume is x3, so the surface-to-volume ratio, 6/x, increases as x decreases. Usually, the surfaces of materials act differently from their bulk in terms of physical properties. As one goes to smaller and smaller scales, surface phenomena become a more important part of device behavior, and this could have very practical implications.

2.1.4. What is a Nanodevice? The exact deﬁnition of what a nanodevice is remains somewhat fuzzy and subjective. There seems to be a general consensus that any device with at least one dimension below 100 nm is a nanodevice. In many cases, depending on how a particular device is made and its principle of operation, some may choose to call it a nanodevice and some may not. What seems to be clear is that, regardless of how we reach the nanoscale and whether or not we manage to make sophisticated nanorobots at some point in future, many interesting phenomena happen at the nanoscale that are worth studying and could be used for new device ideas. This chapter hopes to reach out to a large audience. For the nontechnical who are intrigued by the word ‘‘nano,’’ the chapter provides a general insight. For the nonexpert technical person or those wishing to enter the ﬁeld of nanodevice research (such as advanced undergraduate or fresh graduate students in science and engineering), it provides an introduction and perspective. The main focus of the chapter is on the electronics aspects of nanodevices, but there exist many other aspects to these devices, as well as different approaches to understanding them and creating new ones. Obviously none of the devices or methods discussed here can be reviewed in full detail in the context of a one-chapter overview, nor can all the valuable references in the ﬁeld be cited. However, the author hopes that the references provided here will be a good starting point for those interested in learning more about each subject.

2.2. MATERIALS OF NANOTECHNOLOGY The ﬁrst question that might come to mind when thinking about materials for nanodevices is such: Can one take any material (even a piece of wood), carve a nanoscale object out of it (assuming one has the means, such as an ultra-sharp carving tip to make something that small!), and hope that it would exhibit some interesting nanodevice characteristics? The answer, in principle, is yes. In practice, however, just as is the case in the microscopic or macroscopic worlds, different materials have different properties at the nanoscale level; depending on the particular application the nanodevice is intended for, one has to spend some effort to ﬁnd the right material for it.

2.2. MATERIALS OF NANOTECHNOLOGY

35

The well established materials of the microelectronics industry, such as silicon, dielectrics, and metal layers, also represent a very important category of materials necessary in nanodevices. Not only can many nanoscale devices be made using only these materials and standard microfabrication processes, but in many other cases at least part of the structure of a nanodevice involves these materials and processes. We will talk more about this later in the chapter, but for now let us focus on objects that are more ‘‘nano’’ by nature.

2.2.1. Molecules We know that a molecule is a collection of atoms of either one element or several different elements. Most of the molecules we are familiar with (for example from our high school chemistry) are made of a relatively small number of atoms. Consider the water molecule. It has one oxygen and two hydrogen atoms. However, there is no reason why we could not have much bigger molecules that include hundreds or even thousands of atoms—as a matter of fact, we do! Let us go back and think about our nanodevices for a moment. We estimated that a typical nanodevice would have hundreds or thousands of atoms in it. Can we say a nanodevice is a molecule? In reality, many nanodevices could be considered molecules. Many would be a system of several molecules put together or with other structures in a certain fashion. The term molecular electronics is quite commonly used these days. One difference between these molecules and the more ‘‘traditional’’ molecules that we remember from good old high school chemistry is that there the molecule was a concept describing the smallest building blocks of a much larger substance. When we say a nanodevice can be thought of as a molecule, we are really only emphasizing the fact that it is a stable collection of a number of atoms, and not necessarily a unit that is going to be used to build a macroscopic substance. Also, when one thinks of a molecule, the ﬁrst examples that usually come to mind are rather small ones that contain only a few atoms (such as the hydrogen or benzene molecules), although much larger molecules are also commonplace (such as many polymer molecules or the DNA that can reach macroscopic length scales). Nanodevices, if one wants to call them molecules, are usually very large molecules.

2.2.2. Nanoparticles One important set of ‘‘objects’’ that are very useful to the world of nanotechnology is nanoparticles. As the name implies, a nanoparticle is a particle that has dimensions on the order of a few nanometers. This typically includes a few thousands of atoms. Nanoparticles can be made from various materials. Many metals, for instance, form good nanoparticles. Nanoparticles containing more than one element can also be formed. Again, what is really important about a nanoparticle is the fact that it is small enough such that the quantum effects and large surface-to-volume ratio effect discussed before are dominant in it, to the extent that its properties can no longer be described by the same general properties

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describing a microscopic or macroscopic piece of the same material. In this sense, nanoparticles are at the intermediate level between bulk materials and the atomic world.

2.2.3. Nanowires We recall from geometry that an object can be zero-dimensional (0D: a point), one-dimensional (1D: a line), two-dimensional (2D: a plane) or three-dimensional (3D: a volume). In analogy, nanoparticles are like points. One important category of nanomaterials is 1D objects or ‘‘lines’’ at the nanoscale, namely nanowires. A typical nanowire has a thickness of a few nanometers to a few tens of nanometers; its length is much more than a nanometer, giving it a very high aspect ratio (like a line). Nanowires have been made of many materials, such as silicon, germanium, zinc oxide, and gallium nitride [2–5]. Nanowires are extremely important due to their one-dimensionality. In particular, the electronic properties in these 1D materials can be drastically different from their bulk counterparts due to the fact that charge carriers (electrons) are conﬁned to a small space (only a few nanometers) in the lateral dimensions. This leads to very strong quantum mechanical effects and can result in outstanding electronic transport characteristics for devices such as transistors and switches needed in ultra-high-performance electronic circuits and chips.

2.2.4. Nanotubes One particularly important form of nanowires is what we call a nanotube. The name explains it all: It is a hollow cylinder with a diameter on the order of 1 nm. The most common nanotubes are those made of carbon, i.e., carbon nanotubes. Graphite is a well known form of carbon. Pencil lead is made out of graphite. Graphite has an interesting structure, in that it is composed of one-atom-thick layers stacked on top of each other. Each layer, called graphene, is a sheet of carbon atoms arranged in a hexagonal lattice structure, like a chicken wire. A carbon nanotube can be thought of as a single graphene sheet rolled along a certain direction into a nanometer-diameter tube that is hollow inside. Carbon nanotubes can be extremely long, up to several centimeters, and that means they have aspect ratios on the order of 107. Thus, they represent highly 1D systems. They can be single-walled (Fig. 2.1), i.e., composed of only one layer, or multiwalled, composed of several co-axial, single-walled nanotubes. Carbon nanotubes were discovered in 1991 by Sumio Iijima [6] and have since attracted much attention in the world of nanotechnology due to characteristics such as outstanding electronic properties arising from their 1D nature, as well as extreme mechanical strength due to the strong carbon-carbon SP2 bond. One fundamental difference between nanotubes and other forms of nanowires is that a nanotube is by itself a perfect structure. In other words, most nanowires can be thought of as a very thin wire carved out of a 3D bulk. As such, there could be many unsatisﬁed and dangling bonds on the surface of these structures. They

2.3. WORKING AT THE NANOSCALE

37

Figure 2.1. 3D view of a section of a single-walled carbon nanotube.

could also be rather brittle. A nanotube is, on the other hand, one of the natural, stable forms of its material. For example, a carbon nanotube is an allotrope of carbon, the same way graphite and diamond are. A nanotube surface does not have dangling bonds and all atoms are in a perfect crystalline structure, contributing to the stability of the overall system. A carbon nanotube is, in fact, a giant molecule. For a detailed study of carbon nanotubes the reader is referred to [7].

2.3. WORKING AT THE NANOSCALE Nanofabrication, at least so far, has been heavily reliant on the processes used to fabricate microelectronic circuits or micro electro mechanical systems (MEMS). In fact, many of the processes used for nanodevice fabrication are simply microfabrication processes. In most cases, the term ‘‘nanofabrication’’ only implies that we are using them to make nanodevices. For a detailed study of microfabrication and MEMS techniques references [8, 9] can be used. A typical nanodevice fabrication process involves several microfabrication steps, with the addition of one or two new steps to the process. Let us consider a device consisting of a nanotube attached to two metal electrodes lying on an insulating surface (Fig. 2.2). The fabrication of this device starts with thermal oxidation of silicon to create a thin dielectric layer on a silicon wafer. Then lithography and metal deposition are used to create the contact electrodes. Another lithography step helps pattern catalyst islands that will later be used to grow carbon nanotubes. So far everything is standard microfabrication. The last step, i.e., the growth of the nanotube, can be done using chemical vapor deposition (CVD) [10]. Although CVD has long been around for various fabrication purposes,

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Catalyst island Nanotube

Drain

Source (thickness: 50 nm)

Silicon dioxide (thickness: 100 nm) Back gate Silicon wafer 5 μm

Figure 2.2. Schematic representation of a device including a nanotube attached to two metal electrodes.

nanotube CVD is a relatively recent process that is not standard to the microelectronics or MEMS industry, and can be qualiﬁed exclusively as a nanofabrication step. In general, CVD leads to nanotubes growing randomly in all directions; the task of locating the nanotubes in desired locations and orientations after CVD can be quite time consuming and, more importantly, cannot be relied upon for mass production of devices. It has been demonstrated, however, that the direction of the nanotubes grown by CVD can be controlled to a large extent by the application of an electric ﬁeld [11, 12] or by using the direction of the laminar ﬂow of gases [13, 14] during CVD. Just as in the case of fabrication, many of the inspection and imaging techniques appropriate for nanotechnology have also existed for a long time. Some of the most commonly used imaging methods with nanoscale (or even subnanoscale) resolution include scanning and transmission electron microscopy (SEM and TEM). These work on principles very similar to optical microscopes; the basic difference is that instead of photons (light particles) they use electrons to obtain an image. The reason is that electrons generated in typical laboratory equipment can easily have associated wavelengths much smaller than photons and thus be focused to a much smaller spot, leading to higher resolution. Another group of techniques for imaging and manipulating nanoscale objects is scanning probe microscopy (SPM). The idea behind these is to have a very small and sharp tip brought in contact with a sample (although the term contact should be used loosely in this context), scan the surface, and record the proﬁle. Based on whether the sample is conductive or insulating and other requirements, various types of SPM methods can be used. Scanning tunneling microscopy (STM) and atomic force microscopy (AFM) are two of the most popular techniques of this kind. After a device has been fabricated and imaged, various measurements and experiments are performed on it. There are two big challenges. The ﬁrst is reaching

2.4. NANODEVICE APPLICATIONS

39

such small devices to perform, say, electrical measurements on them. Usually this can be done by making ‘‘interface’’ structures to connect the nano world to our macroscopic world. For instance, in the case of the device in Figure 2.2, the metal electrodes on the sides can be connected to large pads that one can use for wire bonding to the outside world. Another option is to use high resolution motion probes, such as in an SPM tool, to move, manipulate, and contact objects at the nanoscale. The second challenge is determining whether a measurement or perceived effect is really due to the nanodevice and not other surrounding structures, noise, inaccuracies, etc. This is true in any experiment in general, but it becomes particularly important at the nanoscale since one is dealing with very small signals. Creative techniques need to be developed constantly for such experiments. This is an ongoing challenge in nanotechnology.

2.4. NANODEVICE APPLICATIONS Although nanotechnology is still very much in a research phase, many applications have been suggested and even demonstrated at the laboratory level for nanoscale devices. It should be noted that many of the more traditional microdevices have also found their way into nanotechnology. Their scaled down versions could well be considered nanodevices, especially since the reduction in scale results in major differences in characteristics and operation, such as the operating temperature. In this section we will ﬁrst review some of the more established devices in this category, and then present some of the less traditional nanodevice ideas.

2.4.1. ‘‘Traditional’’ Nanodevices The fundamental building blocks of our computers are ﬁeld-effect transistors (FETs), which act as switches to perform logic operations. In parallel with efforts to shrink those devices in the well-established silicon technology, as well as in new types of materials (discussed later in this chapter), there have also been many efforts in making alternative devices that could perform such operations. Here we will look at some of the most common devices in this category, namely resonant tunneling diodes (RTDs), single-electron transistors (SETs), and quantum dots (QDs). An interesting overview of these devices can be found in [15]. As discussed, a fundamental aspect of nanodevices is that quantum effects are directly visible in them. We will take a closer look at this here. 2.4.1.1. Resonant Tunneling Diodes. Consider the problem of a ‘‘particle in a box.’’ By this we mean a particle, say an electron, conﬁned to a small region in space by a potential energy distribution such as the one shown in Figure 2.3. This represents what is called an inﬁnite potential ‘‘well’’—namely, a region where the electron is trapped by two barriers on the sides.

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CHAPTER 2: NANOSCALE DEVICES: APPLICATIONS AND MODELING

4

3 2 1 d

Figure 2.3. A potential well where electrons are conﬁned in space due to energy barriers on the sides. Electrons in such a ‘‘box’’ can only take on discrete energy levels as shown. The horizontal axis is location and vertical axis is energy of the electron.

As will be discussed in more detail later in this chapter, the fundamental equation that governs the behavior of quantum mechanical particles, such as electrons, is the Schro¨dinger equation. The energy levels that an electron is allowed to have in this one-dimensional potential well can be easily obtained by an analytical solution of the Schro¨dinger equation. The result is EN ¼

_2 p 2 N 2 ; 2md 2

N ¼ 1; 2; . . .

Here _ is Planck’s constant and d is the width of the well. In other words, the electron in the well cannot have just any energy, but must take one of the discrete values given by the above formula. In general, such ‘‘quantization’’ of energy levels also happens in the 3D case. This idea is at the heart of some of the quantum devices that we will discuss in this section. Now consider a region in space where a potential well is connected to two metal electrodes through barriers with ﬁnite heights and widths on the sides, such as in Figure 2.4. This is an RTD. An electron can enter this region from outside, leave the region by overcoming the barrier heights (by, for instance, acquiring thermal energy and going to higher energy levels), or move through the barriers by a process called quantum mechanical tunneling. What is interesting is that in the transport characteristics of this device, the effect of these discrete energy levels becomes completely visible. Now imagine a voltage bias is applied to the structure that leads to a relative shift in the chemical potentials of the two contact electrodes, such as in Figure 2.5. An electron will be able to tunnel through the device from one side to the other only if the biases on the two sides are such that there is an energy level in the well in the range where electrons exist on the left and empty states exist on the right, i.e., when there is a level lower than m1 but higher than m2. (Remember that in the electrodes all energy states up to the chemical potentials are ﬁlled with electrons.)

41

2.4. NANODEVICE APPLICATIONS

μ1

μ2

Figure 2.4. The double-barrier structure of an RTD. The gray areas on the sides represent metal contacts or reservoirs of electrons with chemical potentials m1 and m2. The horizontal axis is location and vertical axis is energy of the electron.

Thus, as the applied bias is increased, every time a new energy level enters the range between the two side chemical potentials, there will be a peak in the device’s current versus voltage curve (Fig. 2.6). If a ‘‘gate’’ electrode is placed below the device to enable us to move the energy levels up and down, then we can use this gate to control which level lies between the side chemical potentials, and therefore we can control the conductance of the device. This is the basis of a three-terminal switching device or resonant tunneling transistor. Note that the conductance through this device cannot be modeled by simply considering two single barriers in series. In fact, what is essential here is the wave nature of the electrons and the resonance phenomenon in the well that leads to a high transmission probability of electrons from one side to the other, giving rise to the peaks in conductance. This is analogous to the transmission of light through a multilayer structure with layer thicknesses on the order of the wavelength of the incident light or smaller. Resonance phenomena there can lead to high transmission for a given set of layer properties (thicknesses and refractive indices) and incident wavelength. In general, this is the problem of a resonant cavity, which in the case of the RTD is a cavity for electrons.

μ1 μ2

Figure 2.5. A double-barrier under applied bias, which creates a difference between the chemical potentials on the two sides.

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CHAPTER 2: NANOSCALE DEVICES: APPLICATIONS AND MODELING

I

Resonant peaks

V

Figure 2.6. Conceptual representation of the current-voltage characteristics of an RTD.

2.4.1.2. Single-Electron Transistors. In the operation of the RTD, we looked at the problem as if there were only one electron in the system. In other words, we neglected electron-electron interactions. Electrons repel each other through Coulomb forces; if an electron is put inside the device, it will be harder for a second one to enter since it will have to face the repulsive force of the ﬁrst one. This is called Coulomb blockade. In other words, if multiple electrons are to enter the device at a time, each subsequent electron will have to be put at an energy not only determined by the level quantization shown in Figure 2.3, but also by the charging energy of the device due to its capacitance. As a consequence, the difference between the energy of the electrons will be approximately the sum of the two contributions. One effect may be more dominant than the other based on the actual device size and material. In RTDs the device has a relatively large capacitance such that the charging energy e2/C is much smaller than the level quantization energy discussed above. In an SET, however, the structure is such that the charging energy is much larger than the level quantization energy. Note that although the end result of both effects (resonant tunneling and Coulomb blockade) is that transport happens through discrete energy states and gives rise to unusual device characteristics, the two effects are fundamentally different: one effect is due to the wave nature of particles (quantum mechanical), and the other one due to the fact that the value of charge is quantized (which could be regarded as a somewhat more classical effect). A review of single-electron transistor devices can be found in [16]. Such structures could also be operated under an alternating voltage, and the frequency and amplitude of this signal is such that only one electron is transferred per cycle through the device. Such a device is called a singleelectron turnstile [17]. 2.4.1.3. Quantum Dots. There seems to be some degree of ambiguity in the literature as to the exact deﬁnition of a QD. In particular, the terms SET and QD often seem to be used one instead of the other. A QD could be thought of as a conﬁned region between two potential barriers such as in Figure 2.4, although conﬁnement in all three dimensions is typically assumed. In a sense, RTDs and SETs can be considered special forms of QDs. Both energy level quantization

43

2.4. NANODEVICE APPLICATIONS

I

V

Figure 2.7. The staircase-like current-voltage characteristics of a QD. The width of the plateaus is deﬁned by the separation of the energy levels due to quantum conﬁnement and/or Coulomb blockade.

(due to the wave or quantum mechanical nature of electrons) and Coulomb blockade (due to the discrete nature of charge) are present in the electronic characteristics of a QD. The authors in [15] present the clear distinction that if these two effects are on the same order of strength and signiﬁcance, the device is a QD; otherwise it is an RTD or SET depending on which effect is dominant. In so doing, they correlate these effects to the number of ‘‘small’’ or conﬁned dimensions in each device. What is really important in any case is the clear understanding of both these effects and their fundamental difference. Also, note that typically the structure of an RTD is such that as the bias is increased, only one level at a time is in the energy ranges where there are available electrons for transport, giving rise to the peaks in the conductance characteristics of the device and the negative differential conductance after each peak (Fig. 2.6). However, in what we usually think of as QDs or SETs, often a wider energy range can be available for the incoming electrons (compared to the level spacing inside the well); as the bias is increased, ﬁrst one level enters that range, then a second one, a third one, and so on, without the previous levels leaving that range. Thus, instead of a number of peaks in the current–voltage characteristics, one can have a staircase-like proﬁle: every time a new level enters the allowable energy ranges of the contacts, the current goes up by a ﬁnite amount (Fig. 2.7). Because electron energy is quantized in a QD (like the energy levels in an atom) quantum dots are sometimes referred to as artiﬁcial atoms. For more detail on the operation of QDs the reader can consult [18, 19]. The above quantum devices can be realized in various ways. One popular method is to create a so called two-dimensional electron gas (2DEG) in the interface region of a heterojunction of III-V semiconductors with different band gaps. A set of electrodes is patterned on top of this 2DEG, and by the application of proper bias to these electrodes, some regions of this 2DEG can be depleted (Fig. 2.8). As a result, an ‘‘island’’ of electrons is created that is connected to the reservoirs on the sides through potential barriers (the depleted regions).

2.4.1.4. Temperature Dependence. Table 2.1 shows the ﬁrst few allowed energy levels in a potential well with different widths calculated using the formula

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CHAPTER 2: NANOSCALE DEVICES: APPLICATIONS AND MODELING

Figure 2.8. Schematic top view of a QD created in a 2DEG.

presented earlier. As can be seen, going from 100 to 1 nm changes the energy level separations signiﬁcantly. Note that the thermal energy of electrons at room temperature is kT=25.9 meV (k is Boltzmann’s constant and T is temperature on the absolute or Kelvin scale). If the separation of levels is smaller than this value, the thermal energy of the electrons will be enough to allow them to freely move between these levels; subsequently, the quantization of levels becomes masked at room temperature. Table 2.1 shows that one can hope to see room temperature operation only if the device size is on the order of 10 nm or less. This is in fact the case, and most experiments on QD-type devices are performed at very low temperatures (cryogenic temperatures such as liquid helium temperature). A similar effect also exists with regards to the Coulomb blockade energy e2/C. This energy will be large enough to have an effect at room temperature only if the device dimensions, and therefore its capacitance, are small enough. This typically happens at the nanoscale. An example of room temperature operation can be seen in [20].

2.4.2. Less Traditional Nanodevices By making the ‘‘island’’ of electrons smaller and smaller in the devices discussed in the previous section, one goes from the world of microdevices to that of nanodevices. This could be accomplished, for instance, by using lithography TA B L E 2 . 1 . The First Four Energy Levels in an Inﬁnite Potential Well with Various Widths N

eN (meV) for W=100 nm

eN (meV) for W=10 nm

eN (meV) for W=1 nm

1 2 3 4

0.038 0.151 0.339 0.603

3.8 15.1 33.9 60.3

380 1510 3390 6030

45

2.4. NANODEVICE APPLICATIONS

Source

Gate

Drain

N

N Channel

P

Figure 2.9. Schematic representation (side view) of an MOS FET (N-channel type).

with higher resolution or new methods of fabrication. But there are other types of nanodevices that are ‘‘nano’’ by nature without the need for us to try to make them smaller. This section reviews some of these devices. 2.4.2.1. Nanoscale Field-Effect Transistors. Let us recall from Chapter 1 the operation of a metal-oxide-semiconductor ﬁeld-effect transistor (MOS FET), shown schematically in Figure 2.9. Conduction in this device happens between source and drain in a channel below the gate. The properties of this channel can be modulated by the voltage applied to the gate (by attracting more charge carriers to the channel or pushing them away from it), and this is the basis of the switching action of the transistor. Now let us focus more on the channel itself. We introduced nanowires and nanotubes earlier in this chapter. The basic idea behind nanoscale FETs is the use of a nanowire or nanotube as the conducting channel of the transistor. This wire or tube is connected between two electrodes (source and drain), and a third electrode placed in close proximity (above, below, or even on its side) acts as gate (Fig. 2.10). The difference with traditional MOS devices is that here transport does not happen in a 3D bulk material, but rather in a 1D structure, which is radically different. As a result, these nanoscale FETs can have major differences in characteristics from their traditional counterparts, including several advantages. In these 1D structures or quantum wires, charge carriers are conﬁned in the two lateral directions and behave completely differently compared to 3D materials: not only do they experience strong energy quantization effects, but their movements are strongly correlated with each other. In particular, carriers in these

Gate Source

Drain Nanotube channel

Silicon substrate

Figure 2.10. Schematic representation (side view) of a nanotube FET.

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CHAPTER 2: NANOSCALE DEVICES: APPLICATIONS AND MODELING

wires can have very high mean free paths (the average distance they travel before being scattered), and even ballistic transport (collision free transport) can happen over lengths of up to several micrometers. This could lead to very high operation speed. Transistor action in these devices can happen as a result of both direct modulation of the channel due to the gate or the modulation of the tunnel barriers at the source and drain contacts. These nano transistors are currently the subject of active research, both experimentally and theoretically. For instance, silicon nanowire transistors have been reported to have higher on–off ratios and smaller subthreshold slope (approaching the theoretical limit) than planar silicon-oninsulator FETs [21]. FETs based on other types of nanowires, including germanium, zinc oxide, and gallium nitride, have also been investigated [3, 22, 23]. Similarly, high performance FETs based on carbon nanotubes, including ballistic transport devices, have been demonstrated [24–26]. Applications for logic circuits and high frequency operation (GHz range) have also been investigated [27, 28]. For a theoretical study and modeling of nanowire and nanotube transistors, the reader is invited to consult [29–32]. 2.4.2.2. Exploiting the Hidden Offerings of Nanomaterials. If the length of the channel in a nanowire or nanotube transistor is made very short, the device will naturally become a quantum dot or single electron transistor. Obviously this can be achieved if high resolution patterning is possible, and it is one way of making nanoelectronic devices with new materials [33, 34]. Note that in this approach we are using only the fact that these materials are one-dimensional or quantum wires, i.e., conﬁnement in two directions is already in place. However, the size of the quantum dot achieved in this way is still determined by our ability to pattern electrodes on the nanotube with very high spatial resolution. Therefore, this kind of quantum dot typically has a length on the order of 100 nm and, as discussed before, room temperature operation is not easy. Here we will discuss brieﬂy how some of the less obvious properties of these nanomaterials can be exploited to make new types of devices that are less dependent on traditional patterning techniques. Consider a single-walled carbon nanotube. It is a quantum wire and can be made into a quantum dot by creating only one additional degree of conﬁnement in it. Using ﬁrst-principles calculations, the authors in [35] predict that if the cross section of a nanotube is deformed from circular to elliptical, its electronic structure (both valence and conduction bands) can be altered signiﬁcantly, changing the nanotube from semiconducting to metallic and vice versa. This property was used in [36] and two kinks were created in a nanotube using AFM manipulation (Fig. 2.11) to induce potential barriers and isolate a dot as small as 20 nm, which exhibited room temperature operation. The device was also studied theoretically in [37]. Another device suggested in [38] is based on the geometrical idea that a dot can be deﬁned by crossing two lines. Here the induced mechanical deformation at the intersection of two nanotubes crossing each other (Fig. 2.12) creates a local potential well with a width of about 1.5 nm, potentially enabling room temperature operation.

47

2.4. NANODEVICE APPLICATIONS

(a)

(b)

Figure 2.11. (a) Nanotube QD fabricated by creating two kinks in the nanotube shank using AFM manipulation. Scale bar indicates 20 nm.(From [36]. Reprinted with permission from AAAS.) (b) Simulation of the structure Reprinted with permission from [37] (r 2005 American Institute of Physics)

The advantage here is that once the two nanotubes are made to cross one another, the quantum dot is formed by the natural relaxed conﬁguration of the system and its size is deﬁned automatically to be about 1.5 nm, which would be impossible to achieve using the established patterning techniques. The effect of this deformation on the local density of states in a similar structure was also investigated experimentally in [39]. Thus, as can be seen, there are properties in nanomaterials that can be capitalized on for the creation of novel devices. The author believes that this is one of the major advantages of the world of nanoscale devices and that many unexplored opportunities in this regard still exist.

2.4.3. Other Nanodevice Applications 2.4.3.1. Electron Emitters. Electron emitters have long been in use in vacuum tubes and applications such as electron microscopy and electron beam lithography. With the advances in electron optics in these systems, the electron emitter or source remains the performance bottleneck. Parameters such as the brightness, energy spread, and shot noise of the electron beam directly affect resolution, signal-to-noise ratio, and throughput in such applications. Electron emission is the phenomenon of extracting electrons from inside a metal or semiconductor into a vacuum. An electron emitter could be as simple as a tungsten hairpin with a sharp point. Figure 2.13 summarizes various well established electron emission mechanisms including emission by heating the sample to provide the necessary kinetic energy for the electrons to overcome the

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(a)

(b)

Figure 2.12. Nanotube cross QD. (a) AFM image of structure. (b) Simulated structure using molecular dynamics. Reprinted with permission from [38]. (r 2003 American Chemical Society)

workfunction barrier (thermionic emission), by applying a large external electric ﬁeld to extract electrons by quantum mechanical tunneling through the potential barrier (ﬁeld-emission), or by a combination of heat and external ﬁeld (Schottky emission). Another way to provide the necessary escape energy to the electrons is by using light (photo-emission). A sharp object enhances an externally applied electric ﬁeld and makes electron emission easier. With the advent of nanotechnology and the possibility of fabricating very small and sharp tips with high aspect ratios, electron emission research has reached new dimensions and become a very popular subject in the world of nanodevice applications (Fig. 2.14). In particular, carbon nanotubes, with their extremely strong mechanical structure, high current carrying capacity (109 A/cm2—orders of magnitude higher than copper and silver), and high aspect ratios, seem like ideal candidates for ﬁeld-electron emitters [40–44]. Moreover, their unique structure could lead to interesting electron emission characteristics or be used to make more controllable electron emitters. In one experiment, electron

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2.4. NANODEVICE APPLICATIONS

Vacuum level Thermionic emission

e e

Schottky emission

Work function

Fermi level

e

Field-emission

Metal

Vacuum

Figure 2.13. Various electron emission mechanisms.

emission from the tip of a nanotube was triggered by a combination of an external ﬁeld and another electron beam hitting the nanotube with a very high multiplication factor (ratio of emitted electrons to the incoming ones) [45]. This could have many applications in nanoscale vacuum transistors and electron detectors. Other nanowires have also been investigated for electron emitter applications, including silicon, zinc oxide, and tungsten nanowires [46–48]. Controllable nanoscale electron emitters are in demand not only in electron beam lithography and microscopy, but also in vacuum nanoelectronics, ﬂat panel display technologies [49, 50], free-electron analog to digital conversion [51], time-resolved electron holography, and synchrotrons. 2.4.3.2. Sensors and Actuators. In order to sense a molecule or particle, one needs a device that shows a measurable change in characteristics as the result of the proximity or adsorption of that particle. In nanostructures, due to the large surface-to-volume ratio, even a single particle sitting on the nanostructure could potentially have a large effect on the nanostructure properties such as electronic transport characteristics. Sensor applications have, therefore, been investigated in nanotubes and nanowires. The advantages of these sensors include very high sensitivity, low-voltage operation, low power consumption, and portability. Examples include gas sensors [52, 53], biosensors [54–56], and chemical sensors

e

Cathode structure

e

e

e

Nanotube tip

Figure 2.14. Schematic representation of a nanoelectron source for vacuum nanoelectronic applications.

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[57, 58]. Similarly, the actuation mechanism in nanostructures is being studied actively. For instance, electromechanical actuation in carbon nanotubes has been demonstrated [59, 60] for applications such as artiﬁcial muscles. 2.4.3.3. Interconnect. One of the big challenges facing the integrated circuit industry is the issue of interconnect. As devices shrink and are packed more densely, routing the connections between them becomes more complicated; the interconnect lines themselves can severely affect the operation speed and power consumption of the circuit, to the point of becoming a limiting factor. Various approaches are being pursued to address this problem. One solution is to make 3D integrated circuits (as opposed to current planar or 2D circuits), which would create more ways of connecting devices and make shorter paths possible [61]. So far in this chapter we have been discussing the usage of nanomaterials to make devices. It is noteworthy that several research groups are also working on the possibility of using materials such as carbon nanotubes for interconnecting the devices on a circuit [62, 63]. Since these materials can carry large current densities and operate in the ballistic transport regime, this could lead to potentially faster interconnects with less power consumption. 2.4.3.4. Hydrogen Storage. Alternative energy sources are becoming increasingly important and research in this ﬁeld is very active. Hydrogen-based energy requires the storage of hydrogen in a safe and efﬁcient manner. Carbon nanotubes are being investigated for their potential in storing hydrogen in high densities [64]. 2.4.3.5. Optical Properties of Nanostructures. The focus of this chapter has been mainly on the electronic properties of nanodevices. However, optical properties are closely related to electronic properties; microscale optoelectronic devices are in widespread use. Nanoscale optoelectronic devices are the subject of active research. Examples include lasers based on nanowires [65] and optical emitters [66, 67], detectors [68, 69], and antennas [70] based on carbon nanotubes.

2.5. MODELING AND SIMULATING NANODEVICES 2.5.1. The Art of Modeling In the world of natural sciences and engineering, the art of modeling consists of describing a physical system in terms of parts and phenomena that we can understand based on our knowledge of nature, in the simplest possible manner, in such a way that none of the fundamental aspects of its operation are lost, and that we can use the model to predict/explain the results of experiments on the system. The model often involves a number of mathematical equations that can be solved to explain or to predict experimental outcomes. As a matter of fact, it could be argued that the most fundamental laws of nature, as we know them, are

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51

themselves models at the most basic and general level, and they attempt to describe all of nature and its phenomena in one shot. But as long as these models are not derived from more general models and are at the root of our modeling hierarchy, we call them fundamental laws. Before the advent of fast calculating machines and computers, researchers had to rely mainly on solving these equations analytically (as much as possible) before attempting to plug in numbers. In the recent times, modeling is often accompanied by heavy numerical simulations; that is, once a good model is chosen for a given system, predictions on the behavior of the system under various circumstances are done by numerically solving the equations using fast computers. One may ask that if we know the fundamental laws of nature, and if we have a fast computer to solve equations, why can we not always start from those fundamental laws (whether classical or quantum mechanical) and solve the relevant equations for any system in the most general sense? The answer is that this ‘‘ﬁrstprinciples’’ approach usually leads to a complex system of interrelated equations that even the most advanced supercomputers cannot handle numerically for a simple physical system. As a consequence, regardless of how good our computers have become, modeling has remained an integral part of studying natural systems. For example, think about an inert gas. The sciences of statistical mechanics and thermodynamics have provided us with an elegant model that describes an ‘‘ideal’’ gas that results in a very simple equation relating its pressure, volume, and temperature. For many a practical application, this model provides a description that is accurate enough to ﬁnd those parameters, without the need for heavy calculations. In contrast, imagine the practically impossible task of solving the equations of motion for all the atoms in a given volume of gas (trillions of trillions of atoms) every time one needs to study the gas’ expansion as a function of temperature. With the introduction of every new branch of science and engineering, models start being developed (and gradually improved) to describe systems relevant to the discipline. There are well established models for gases, solids, and ﬂuids that engineers use every day to design new devices and systems. We have been very successful so far in coming up with good physical models to describe systems ranging from giant spacecraft all the way down to microelectronic devices. In other words, when designing a spacecraft, an engineer does not start with the behavior of the individual atoms in it, but rather uses the much more high level models of mechanical engineering that describe the system containing a very large number of atoms. Similarly, even in microelectronic devices, a designer/engineer does not look at individual atoms or electrons, but uses the well established equations of microscopic electronic transport in a system containing a large number of atoms and electrons. These cases (spacecraft and microelectronic device) have in common the fact that in both systems there exists such a large collection of atoms that the details of the exact behavior of each individual atom is of little signiﬁcance to the overall system, and it is the statistical averages of these behaviors that determine what happens. Thus, the fact that there is a large number of atoms to be accounted for is not only not a threat to modeling, but is actually the very reason why such successful macroscopic models can be developed and used.

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2.5.2. The Challenge of Nanoscale Modeling If you have two planets interacting with each other through gravitational forces, you can use Newtonian mechanics to trace their motion analytically. Add one more planet to the system (the so called three-body problem) and a closed-form analytical solution will generally not exist. This is also true for interacting electrons and protons. There is no analytical solution to the interacting manybody problem and one will need to resort to numerical methods to study such systems. Although simple in theory, the practical difﬁculty arises from the fact that with the addition of every new particle to the system, the amount of calculations needed grows considerably. Now let us imagine that we want to study a system that includes only a few electrons. As discussed, we know the fundamental laws that describe the system— that is quantum mechanics. One tends to think that it should not be too hard to analyze such systems with a reasonably good computer. In fact, that might be the case when there are only a few particles involved. However, if there are hundreds or thousands of interacting atoms in the system, such as in nanoscale devices, then the exact solution of the equations of quantum mechanics for the entire system is absurdly out of reach for even the most advanced supercomputers of the modern day. At the same time, hundreds or thousands of atoms do not represent a large enough system where we could neglect the individual character of each atom and simply describe the system in terms of statistical averages. Thus, nanoscale devices present a regime of physical systems—in terms of their size—where we can neither neglect the atomic nature of the structure, nor treat it exactly using numerical methods and fast computers. It is noteworthy that this book focuses on new approaches to making computers with signiﬁcantly more power than our traditional computers. When such efforts eventually become successful, our method of dealing with nanoscale devices from a modeling and simulation perspective could also change in major ways.

2.5.3. Smart Physical Modeling So how do we deal with nanoscale devices? The solution lies in a smart approach to modeling. Often, a hybrid, multiscale approach is necessary to treat the system: more classical methods for aspects of the system that are less affected by the atomic nature, and more fundamental, quantum mechanical calculations where needed. Another important factor is that often a given property or experimental outcome could be explained based on a small part of the overall device. The art of modeling nanostructures consists of seeing what is essential to retain in a minimal subsystem (that we can handle with our available computing power in reasonable time) in order to study a certain subject relevant to the nanodevice in question. Nanodevices constitute a very new ﬁeld and there is not, at least not yet, a general approach to modeling all nanodevices (such as is the case for larger devices like microelectronic transistors). Therefore, every researcher working in the ﬁeld will, at some point, have to deal with modeling the speciﬁc system he/she is studying.

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53

Nonetheless, there are many different levels of theory that have been developed over the years that could be applied based on the level/depth of the model itself. These include methods ranging from semi-classical treatments of atoms to single-electron methods to lower level methods directly relying on the solution of the fundamental equations of quantum mechanics for all the atoms. In the next few sections we shall brieﬂy introduce some of the common methods in this context.

2.5.4. The Methods Generally speaking, the methods of modeling and simulating nanodevices could be divided into two major categories: the so called ab initio (from the beginning) or ﬁrst-principles approaches, and methods that have more of a phenomenological or empirical aspect to them. In ﬁrst-principles methods, as the name suggests, the idea is to start with the basic physical equations for the entire system, such as the Schro¨dinger and Poisson equations, and solve them to ﬁnd all the desired characteristics like electronic structure or transport properties. The Hartree– Fock theory is one such method that provides a framework for treating the quantum many-body problem by solving the Schro¨dinger equation. As discussed before, this could be a remarkably difﬁcult task to accomplish (in terms of computational complexity) for a reasonably large system such as a nanodevice with hundreds of atoms. Therefore, other methods have been developed that rely on approximations and ﬁtting parameters that, although not as accurate as ﬁrstprinciples approaches, depending on the problem at hand could still capture most of the underlying physics and handle much larger systems in a practical manner. Molecular dynamics and tight-binding approximations are some important examples in this category. 2.5.4.1. Ab Initio (First-Principles) Approaches. Quantum mechanics and relativity are the theories that describe the world around us (the best theories we have so far, though not necessarily the absolute truth!). In everyday experiences, quantum mechanical and relativistic effects are often masked and simpler theories, such as Newtonian mechanics, provide an accurate enough description. At very small scales, such as the nanoscale, quantum mechanical effects are dominant (although relativistic effects can be negligible in many nanodevice applications). We will begin our discussion here with a quick look at what is at the heart of quantum mechanics. In one common approach to quantum mechanics, the behavior of a particle can be described by the Schro¨dinger equation: HC ¼ eC: Here, H is the so called Hamiltonian operator of the system, including both potential and kinetic energy terms and e represents the allowed energies in the system. Particles are described in terms of waves (C). The amplitude of the wave

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represents the probability of the particle being at a given location. (You cannot know for sure where a particle is; rather, you have a probability distribution for its existence in various locations in space. To the best of our knowledge so far, this is the reality, but it might sound counterintuitive because this reality reveals itself only at small scales, and so we are not used to it in everyday life.) Note that the Schro¨dinger equation is, in general, a time-dependent differential equation. Here we have shown the time-independent case just for the sake of introduction. At the root of modeling a nanoscale device is the problem of writing the above equation for the system by including the proper terms in the Hamiltonian and solving it to ﬁnd C and e. From C and e one can proceed to ﬁnding other parameters of interest in the system. Thus, for nanoscale modeling, learning quantum mechanics, at least at an introductory level, is the ﬁrst necessary step. The reader is referred to [71, 72] as good examples of quantum mechanics textbooks. Finding a solution to the above equation without invoking empirical parameters is what ab initio approaches try to accomplish. SLATER DETERMINANTS AND THE HARTREE–FOCK METHOD. In one simpliﬁcation, exact instantaneous electron–electron interactions are neglected in studying a system of atoms. The problem is reduced to that of a single electron moving in the ‘‘average’’ ﬁeld created by the rest of the system. This approximation is very useful in many practical cases and captures the basic physics of the problem while greatly simplifying the computational complexity. When trying to solve the Schro¨dinger equation in this case, one can represent the overall wave function C of the system as products of individual wave functions for electrons; this is basically the technique of separation of variables in solving differential equations. In addition, Pauli’s exclusion principle that no two electrons with the same spin can reside in the same state must be satisﬁed. This, together with the fact that electrons are indistinguishable particles from one another, requires that the system wave function be antisymmetric with respect to simultaneous change of spin and space coordinates of electrons. A general form for the many-body wave function that satisﬁes this condition is the so called Slater determinant [73, 74]: f1 ð1Þ f1 ð2Þ f1 ðN Þ f2 ð1Þ f2 ð2Þ f2 ðN Þ C/ . .. .. .. .. . . . f N ð 1 Þ f N ð 2Þ f N ð N Þ In the above each f represents a single-electron wave function (including the spin part). Since swapping two rows or columns in a determinant changes the sign, this form satisﬁes the antisymmetry condition. In the Hartree–Fock method, the wave function of the system is obtained in the form of a Slater determinant. More on this method can be found in [74, 75]. Although this method neglects electron–electron correlation (i.e., the instantaneous nature of electron–electron

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interactions as they move in their complex orbitals), it can often provide a good insight into the physics of a problem and even make relatively good quantitative predictions as well. For instance, this method has shown to be quite effective in ﬁnding the occupied orbitals of carbon nanotubes and ionization energies of several molecular systems [76, 77]. THE DENSITY FUNCTIONAL THEORY. The density functional theory (DFT) is perhaps the most celebrated of approaches to solving the quantum many-body problem and has become increasingly popular in modeling and simulating solid materials including nanostructures. DFT provides a framework to accurately treat the quantum many-body problem. So, in principle it could be classiﬁed as a ﬁrstprinciples approach. However, later we will see that in practical implementations of DFT one needs to use approximate descriptions for the so called exchange– correlation energy. Therefore, DFT is not always necessarily considered an ab initio technique. Nonetheless, due to the fact that it does not essentially rely on empirical data, it is included in this section. A paper published by Hohenberg and Kohn in 1964 [78] demonstrates that in treating an N-body problem, instead of working with the coordinates of all individual particles (electrons and nuclei), one can use a particle density distribution in space. This remarkably simpliﬁes the problem and brings it to a much more manageable level. This is accomplished on the basis of the two following theorems, proven in that seminal paper [75, 78]: 1. The external potential acting on a fully interacting many-particle system in the ground state is determined uniquely by its electron density distribution in space. (Obviously we can add a constant to the potential everywhere without any real effect). 2. The ground state energy of the system (with the correct density) is smaller than the energy in any other conﬁguration (with any other trial density). The ﬁrst theorem enables one to transform the many-body Schro¨dinger equation to an equation for the particle density functional. The second theorem provides a variational principle to solve the equation by ﬁnding the density distribution that minimizes the resulting energy for the system, which will be its ground state. A formal approach to ﬁnding the solution was proposed by Kohn and Sham in 1965 [79]. The key to this approach is that, using the introduction of an effective potential, the equation for the interacting many-body system is rewritten in such a way that it looks like the equation for a system of noninteracting particles. Then this equation is solved in a self-consistent manner as follows: one makes a guess for the density distribution, uses it to ﬁnd the effective potential, uses the effective potential to ﬁnd the orbitals (which is feasible since the equation looks like the one for noninteracting particles), and then calculates the electron density again from these orbitals. This process is continued until the density converges, and then one will have the ground state energy,

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orbitals and density. This cycle of iterations to ﬁnd the solution is common to many methods including DFT and Hartree–Fock and therefore these methods are referred to as Self-Consistent Field (SCF) methods. It should be noted that no miracle is performed in DFT. In following the Kohn–Sham method, a term called the exchange–correlation energy appears in the equations, due to both the quantum mechanical nature of particles and the fact that they are interacting. But this term is not known exactly. Therefore, the ﬁnal solution will be approximate. There is indeed ongoing work on ﬁnding improved descriptions for the exchange–correlation energy in various systems [75]. One of the most widely established methods is the so called local density approximation (LDA). Here, the exchange–correlation energy for the system at each point in space is taken to be equal to that of a system with a uniform density that is the density in the actual system at that location. Despite the fact that the lack of an exact exchange–correlation energy makes the results obtained by DFT approximate (like other methods), it is important to note that DFT is, in principle, a rigorous approach and is not based on a simpliﬁed model for the system. As such, it provides a way not only to understand what approximations one is making (when choosing the exchange–correlation functional) but also to improve those approximations in a systematic manner. In this regard, it also helps to put some of the other methods (that are based on simpliﬁed models of the real problem) into perspective and to provide a means of analyzing how accurate they are. For a very well written summary on DFT the reader is encouraged to consult [75]. For more detail [80–82] can be used. 2.5.4.2. Semi-Empirical Methods. As pointed out before, starting from ﬁrst principles and solving the many-body quantum mechanical problem can often be a formidable task even for the most advanced computers. Therefore, methods have been developed that, in addition to theory, use empirical data to provide simpliﬁed descriptions of many-particle systems. Molecular dynamics, tight-binding, and Monte Carlo approaches are some of the popular methods of this genre. CLASSICAL MOLECULAR DYNAMICS. The basic idea in molecular dynamics is to represent the interaction between each two atoms as a mean ﬁeld arising from the interaction of all individual electrons and nuclei. For example, in the case of two carbon atoms instead of trying to calculate the force between them as the sum of the attractive and repulsive forces between all the individual electrons and protons (6 protons and 6 electrons in each atom, resulting in a total of 12*12=144 complex interactions), a semi-empirical model for the force between the two atoms would be used. This force would be expressed as a function of the relative positioning of the two atoms with a number of parameters that are obtained by ﬁtting the predictions of the model to available experimental data. In very simple terms, the potential energy resulting from the interaction of two atoms could be something like the curve in Figure 2.15. Since force is the negative of the derivative of potential energy with respect to position, it can be seen that if

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Potential energy Equilibrium point

d

Interatomic distance

Figure 2.15. A simple representation of the interaction potential energy of two atoms.

the two atoms are a distance d apart, they are in equilibrium. If they are pushed closer, the force between them will be repulsive. If they are pulled farther, the force between them will be attractive. Both cases would lead to the atoms going back to their equilibrium distance. Here is how molecular dynamics works in principle: consider a system of a number of atoms. We place them in close proximity and would like to ﬁnd what the equilibrium position of each atom in the ‘‘relaxed’’ structure would be. We can start by calculating the force on each atom resulting from the rest of the atoms, using curves such as the one in Figure 2.15. Then, using Newton’s equation of motion F=ma, we can calculate the acceleration on each atom due to this force. Now we let all the atoms move under these accelerations for a very small duration of time—a duration short enough that we can assume the force (and, as a result, acceleration) on each atom does not change signiﬁcantly during that time. After this very short time, we have the new locations of the atoms and their new velocities. From the new locations we can calculate the new accelerations each will be feeling, and then move in time one more short step. If we repeat this process for a large enough number of time steps, at some point we will see that the atoms will not move signiﬁcantly any longer as time passes. This will be the equilibrium or relaxed conﬁguration of the system. One way to see this is to plot the total potential energy (the sum of all atom–atom interactions) of the system as a function of time. Eventually, this curve will saturate and asymptotically go toward the relaxed energy of the system. One important issue to consider is that the system could converge to the metastable state closest to where we started from (in terms of initial choice of atomic positions). Therefore, in order to ﬁnd the global minimum energy conﬁguration of the structure, one may need to repeat the simulation with various choices of initial conﬁgurations and compare the end results in terms of total energy, or incorporate mechanisms to ‘‘kick’’ the system out of metastable conﬁgurations (using parameters such as thermal energy) with the hope that it will ﬁnd its global minimum. Many variations of molecular dynamics are in use today and they can handle systems of relatively large numbers of atoms (thousands or tens of thousands of atoms) in reasonable time on present day

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computers. There have also been many valuable attempts at modeling the interatomic interactions for use in molecular dynamics simulations. One good example is the Brenner–Tersoff potentials that are well established for describing hydrocarbon systems [83, 84]. For a detailed review of molecular dynamics the reader is referred to [85]. TIGHT-BINDING. One way to approach a problem involving multiple atoms is to try to solve the Schro¨dinger equation by ﬁnding an expanded form for the expected solution. It is customary to write the solution in the form of a linear combination of atomic orbitals (LCAO), that is, as a weighted sum of wave functions that have been found for individual, isolated atoms. The parameters involved could be derived from ﬁrst-principles methods. In many cases, however, these can be found from elsewhere, such as using experimental data. For instance, the core of an atom could be represented by a pseudopotential, instead of explicitly including all the individual electron contributions, just like in molecular dynamics. Thus, as opposed to exact, real orbitals, the atom will be represented by parameters derived by ﬁtting to other available data. In such cases, especially when interactions with close neighbors are considered only, the LCAO method would typically be referred to as the tight-binding (TB) approximation. TB has the advantage of being computationally much less expensive than ab initio methods and therefore capable of providing, at least, a qualitative description of the behavior of a relatively large system quickly. For more on LCAO methods and TB, [86–88] can be studied. MONTE CARLO. Monte Carlo methods are in place in many disciplines. The basic idea is to start from a known point and trace the behavior of a system by following a random-walk process. In each state, the system has the possibility of going to several of subsequent states with different probabilities. The choice of which one of those states the system will go into at each step is decided by a random process that is weighted by those different probabilities. For instance, consider the movement of an atom sitting on a crystalline surface through a loose bond. This atom moves around due to its thermal, kinetic energy. At each point, there exists several sites around it for it to move to. There would be a potential barrier in front of the atom to cross in order to make the transition to any of these sites, but the barriers have different heights and widths for the different sites, which correspond to different transition probabilities. The random walk of this atom could be traced using the Monte Carlo approach. Both semiclassical and quantum Monte Carlo methods are widely in use in nanoscale modeling [89, 90]. 2.5.4.3. Use of Green’s Functions. Green’s functions are powerful tools in solving differential equations. Since the goal in nanosale modeling is to ﬁnd the solution to the Schro¨dinger equation, which is a differential equation, Green’s functions often come in very handy. In particular, they provide a useful way of dealing with problems involving open boundary systems. Consider, for example, a QD or SET connected to two large metal contacts on the sides. Although the

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device itself is small (nanoscale), the contacts are usually very large (microscale) and could be treated as semi-inﬁnite systems for the purposes of the analysis. The use of Green’s functions greatly simpliﬁes the problem in such cases. In particular, problems involving electronic transport usually have contacts playing a crucial role and thus the so called nonequilibrium Green’s function (NEGF) formalism is commonly used. Moreover, Green’s functions provide a way of dealing with interparticle interactions in electronic transport modeling. For a study of Green’s functions with application to transport problems in nanostructures the reader is referred to [91–93]. 2.5.4.4. System-Level Modeling. Although most of the research in the ﬁeld of nanodevices is currently focused on the device itself, it is noteworthy that valuable efforts are being made on system-level issues, such as designing circuits based on these novel nanodevices and analyzing such systems. Researchers have worked on circuit design paradigms for future computers based on QD-type devices such as quantum dot cellular automata (QCA) [94]. Although this research is very new, even compared to the ﬁeld of nanodevices itself, there are already examples of computer-aided design (CAD) tools that have been developed for circuit design applications. An example is the software called QCADesigner [95].

2.6. CONCLUSIONS There are various methods that could be used for the analysis of a given device depending on the aspects being studied. For instance, classical molecular dynamics usually gives an accurate enough result for the mechanical structure of the system, but does not provide much in the way of electronic structure. DFT gives very accurate results for electronic structure and can be used to relax the mechanical structure of the system, although it is extremely expensive computationally. To illustrate how these various methods could be used in practice, let us consider the example of a carbon nanotube with a length of 10 nm connected between two metal electrodes to form a quantum dot. One way to approach the problem of electronic transport in this device is the following: the coordinates of the carbon atoms as well as those of the metal atoms in the contact electrodes are generated based on the lattice structures of the nanotube and the electrode. However, we know that once a short section (10 nm) of the nanotube is cut and put in contact with the electrodes, the atoms, especially at the edges, rearrange themselves slightly. A molecular dynamics simulation is run to determine the exact location of all the atoms in the metal-nanotube-metal structure. Then both DFT and TB are used to determine the electronic structure (orbitals or band structure), while using the NEGF approach to study the transport characteristics. If the current as a function of applied voltage is to be found, it would mean a series of electronic structure calculations with different system Hamiltonians (each reﬂecting a single bias point). This is very time consuming with DFT. So, one could use TB for this, and at the same time use DFT for some of the bias

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points to have a benchmark for comparison in order to evaluate the accuracy of the TB results. The objective of this chapter was to provide an introduction to the world of nanodevices. We brieﬂy reviewed the motivations behind making devices at the small scale, the process of how they are made, some of their applications, and some of the common methods of studying and simulating them. Entering any level of detail in those subjects is obviously beyond the scope of this single chapter, but the author hopes that the chapter shows the big picture of what to expect in this area and how to pursue a given direction of interest.

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3 QUANTUM COMPUTING John H. Reif Quantum computation (QC) is a type of computation where unitary and measurement operations are executed on linear superpositions of basis states. This chapter provides a brief introduction to QC. We begin with a discussion of basic models for QC such as quantum TMs, quantum gates, and circuits and related complexity results. We then discuss a number of topics in quantum information theory including bounds for quantum communication and I/O complexity, methods for quantum data compression and quantum error correction (that is, techniques for decreasing decoherence errors in QC), Furthermore, we enumerate a number of methodologies and technologies for doing QC. Finally, we discuss resource bounds for QC including bonds for processing time, energy, and volume, particularly emphasizing challenges in determining volume bounds for observation apparatus.

3.1. INTRODUCTION 3.1.1. Reversible Computations Reversible computations are computations where each state transformation is a reversible function, so that any computation can be reversed without loss of information. Landauer [1] showed that irreversible computations must generate heat in the computing process, and that reversible computations have the property that if executed slowly enough, they (in the limit) can consume no energy in an adiabatic computation. Bennett [2] (also see Bennett, Landauer [3], Landauer [4], Toffoli [5]) showed that any computing machine (e.g., an abstract machine such as

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a Turing Machine) can be transformed to do reversible computations. Bennett’s reversibility construction required extra space to store information to insure reversibility; Li Vitanyi [6] give tradeoffs between time and space in the resulting reversible machine. An innovative technique due to Bennett [2, 7] can be used to make reversible functions bijective, as required for quantum computations. Given a bijective function f, suppose we can reversibly compute in time T(x) a bijective function f and it’s inverse f1 using auxiliary registers for storage of the input. He proves in time O(T(n)) we can also reversibly compute the bijective mapping, ðx; 0; 0Þ ! ð f ðxÞ; 0; 0Þ, without use of auxiliary registers for storage of the input.

3.1.2. An Introduction to Quantum Computation Computations and methods that do not make use of quantum mechanics will be termed classical. In contrast, quantum computation (QC) applies quantum mechanics to do computation. A single molecule (or collection of particles and/or atoms) may have a number n of degrees of freedom known as qubits. Associated with each ﬁxed setting X of the n qubits to Boolean values is a basis state denoted 7aS. Quantum mechanics allows for a linear superposition (also termed an entangled quantum state) of these basis states to exist simultaneously. Each basis state 7aS of the superposition is assigned a given complex amplitude a; this is denoted a 7aS. Unitary transformations are reversible operations on the superpositions which can be represented by unitary matrices A (e.g., permutation matrices, rotation matrices, and the matrices of Fourier transforms) where AAT=I. The sum of the squares of the magnitudes of the amplitudes of all basis states is 1. This sum remains invariant due to the application of a unitary transformations. The Hilbert space Hn is the set of all possible such linear superpositions. QC is a method of computation where various operations can be executed on these superpositions: unitary operations, and observation operations, which allow for the (strong) measurement of each qubit, providing a mapping from the current superposition to a superposition where the measured qubit is assigned a Boolean value with probability given by the square of the amplitude of the qubit in its original superposition. Elementary unitary operations that sufﬁce for any quantum computation over qubits (see [8] and [9]) include a conditional form of the conditional XOR operation , the Boolean operation NOT, and a constant Boolean operation yielding 0. The time bound for a quantum computations is deﬁned to be the number of such elementary unitary operations.

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3.1.3. Surveys of QC The following are reviews and surveys have been made of QC: Bennett [10], Barenco [11], Benio [12], Brassard [13, 14], Haroche, Raimond [15], Brassard [16], Preskill [17], Scarani [18], Steane [19], and Vedral, Plenio [20]. Also, Taubes [21] and Gershenfeld, Chuang [22] give popular press descriptions of QC. The following are texts on quantum computing.

Overviews: [23–26] Quantum information processing: [27–34] Quantum cryptography: [35–37] Quantum coding theory: [38, 39] Quantum algorithms: [40] Experimental implementation of quantum computation: [41–45]

3.1.4. Initial Work in QC Feynman [46, 47] and Benioff [48] were the ﬁrst to suggest the use of quantum mechanical principles for doing computation. Deutsch and Jozsa [49] give the ﬁrst example of a quantum algorithm that gave a rapid solution of an example problem, where the problem (for a given a black box function) is not quickly solvable by any deterministic conventional computing machine. But their problem could be quickly solved using randomization. Bernstein and Vazirani [50] then provided the ﬁrst example of a fast quantum algorithm for a problem that could not be quickly solved by conventional computing machines even using randomization. (See also Costantini, Smeraldi [51] for a generalization of Deutsch’s example and see Collins et al. [52] for a simpliﬁed Deutsch–Jozsa algorithm, and Jozsa [53–55] for further work in quantum computation and complexity.)

3.1.5. Organization of this Chapter In Section 3.1 we introduced QC. In Section 3.2 we introduce formal quantum computing models and in Section 3.3 we discuss quantum complexity classes. Next we overview key topics concerning quantum information processing: Section 3.4 discusses bounds for quantum communication; Section 3.5 discusses methods for quantum errorless compression; Section 3.6 discusses methods for quantum error coding; and Section 3.7 describes methods for quantum cryptography. In Section 3.8 we discuss further algorithmic applications of QC. In Section 3.9 we enumerate various technologies for doing QC. In Section 3.10 we review of the resource bounds of quantum computing as compared with the resources required by classical methods for computation. In Section 3.11 we conclude the chapter. In Appendix 3.12 we discuss the challenge of providing volume bounds for observation apparatus when doing QC.

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3.2. QUANTUM COMPUTING MODELS Quantum TMs and other Automata. Deutsch [56] gave the ﬁrst formal description of a quantum computer, known as a quantum TM. The tape contents of the TM are qubits. Quantum conﬁgurations of the QTM are superpositions of (classical) TM conﬁgurations. A transition of the QTM is a unitary mapping on quantum conﬁgurations of the QTM. Thus, a computation of the QTM is a unitary mapping from the initial quantum conﬁguration to the ﬁnal quantum conﬁguration. Various papers generalize machines and automata to the quantum case. Moore, Crutchﬁeld [57] propose quantum ﬁnite-state and push-down automata, and regular and context-free grammars; they generalize several formal language and automata theorems, e.g., pumping lemmas, closure properties, rational and algebraic generating functions, and Greibach normal form. Kondacs and Watrous [58] partially characterize the power of quantum ﬁnite state automata. Dunlavey [59] gives a space efﬁcient simulation of a deterministic ﬁnite state machine (FSM) on a quantum computer (using Grover’s search algorithm discussed below). Watrous [60] investigates quantum cellular automata and Du¨rr et al. [61, 62] give decision procedures for unitary linear (one dimensional) quantum cellular automata. Quantum Gates. A set of Boolean gates are universal if any Boolean operation on arbitrarily many bits can be expressed as compositions of these gates. Toffoli [5] deﬁned an extended XOR 3-bit gate (which is an XOR gate condition on one of the inputs and is known as the Toffoli gate) and showed that this gate, in combination with certain 1-bit gates, is universal. A set of quantum qubit gates are universal for Boolean computations for QC if any unitary operation on arbitrarily many qubits can be expressed as compositions of these gates. Deutsch deﬁned the extended quantum XOR 3-qubit gate (known as the Deutsch–Toffoli gate) and proved this gate, in combination with certain one qubit gates, is universal. Barenco [63], Sleator et al. [64], Barenco et al. [65], and DiVincenzo [66] proved the 2-qubit XOR gates with certain 1-qubit gates can implement the Deutsch–Toffoli gate, so are universal for QC (also see Smolin and DiVincenzo [67], DiVincenzo et al. [68], Poyatos et al. [69], and Mozyrsky et al. [70, 71]). Lloyd [72] then proved that almost any 2-qubit quantum logic gate (with certain 1-qubit gates) is universal for QC. Monroe et al. [73], DiVincenz et al. [74] gave experimental demonstrations of quantum gates [75]. Deﬁned a quantum computing model known as a quantum gate array, which allows execution of a (possibly cyclic) sequence of quantum gates, each input is a qubit, and each gate computes a unitary transformation. Quantum Circuits. Yao [76] restricted the concept to (acyclic) quantum circuits, which are a generalization of Boolean logic circuits for quantum gates. It sufﬁces that a quantum circuit use only these universal gates. Yao [76] proved that QTM computations are equivalent to uniform quantum

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circuit families. Bernstein and Vazirani [50] showed that quantum gates of only logarithmic accuracy sufﬁce for polynomial time quantum circuits. Aharonov et al. [77] discusses a generalization of quantum circuits to allow mixed states, where measurements can be done in the middle of the computation, and showed that such quantum circuits are equivalent in computational power to standard quantum circuits. This generalized an earlier result of Bernstein and Vazirani [50] that showed that all observation operations can be pushed to the end of the computation by repeated use of a quantum XOR gate construction. Aharonov et al. [78] considered an adiabatic model of quantum computation and showed it is equivalent to standard quantum computation. Computer Simulations of QC. Obenland, Despain [79–81] have given efﬁcient computer simulations of QC, including errors and decoherence, and Cerf, Koonin [82] have given Monte Carlo simulations of QC.

3.3. COMPLEXITY BOUNDS FOR QC 3.3.1. Quantum Complexity Classes and Structural Complexity Berthiaume, Brassard [83] survey open QC structural complexity problems (also see Berthiaume [84]). QC can clearly execute deterministic and randomized computations with no slow down. P (NP, QP, respectively) are the class of problems solved by deterministic (nondeterministic, quantum, respectively) polynomial time computations. Thus QP is the quantum analog of the time efﬁcient class P. It is not known if QP contains NP, that is, if QC can solve NP search problems in polynomial time. It is also not known whether QP is a superset of P, nor if there are any problems QC can solve in polynomial time that are not in P (but this is true given quantum oracles; see Berthiaume, Brassard [85, 86], Machta [87], and van Dam [88, 89] for complexity bounds for computing with quantum oracles).

3.3.2. Bounded Precision QC Let BQP be the class of polynomial time quantum computations that are computed within bounded error. Most of the algorithms we will mention (such as Shor’s) are in the class BQP [50]. Showed that BQP computations can be done using unitary operations with a ﬁxed irrational rotation. Adleman et al. [90] improved this to show that BQP can be computed using only unitary operations with rational rotations, and that BQP is in the class PSPACE of polynomial space computations of (classical) TMs. Practical implementations of QC most likely will need to be done via unitary transitions within some modest amplitude precision. Bernstein, Vazirani [50] proved that BQP computations running in time T can be done with unitary operations speciﬁed by only O(log T) bits of precision.

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3.3.3. Quantum Parallel Complexity Classes Let NC (QNC, respectively) be the class of (quantum, respectively) circuits with polynomial size and polylogorithmic depth. Thus QNC is the quantum analog of the processor efﬁcient parallel class NC. Moore, Nilsson [91] deﬁne QNC and show various problems are in QNC; for example, they show that the quantum Fourier transform can be parallelized to linear depth and polynomial size.

3.4. BOUNDS ON MEASUREMENT, SENSING, AND COMMUNICATION 3.4.1. Lower Bounds on Quantum Communication Cleve et al. [92] prove linear lower bounds for the quantum communication complexity of the inner product function and give a reduction from the quantum information theory problem to the problem of quantum computation of the inner product. Knill, Laﬂamme [93] characterize the communication complexity of one qubit.

3.4.2. Interaction-Free Quantum Measurement A method for (nearly) interaction-free measurement (IFM) speciﬁes the design of a quantum optical sensing system that is able to determine with arbitrarily high likelihood if an obstructing body has been inserted into the system, without moving or modifying its optical components; moreover, in the case that the obstructing body is present, IFM uses at most an arbitrarily small multiplicative factor of the input intensity to do the sensing. Kwiat et al. [94] (also see [95]) have given a method for IFM which does repeated rounds of measurement to affect small phase changes that eventually determine (via the quantum Zeno effect) whether an obstructing body has been inserted. Kwiat et al. [95] assert their method can be applied to sensing tasks such as photography, but the use of their method for IMF has major practical limitations (i.e., if the obstructing body has not been inserted, then the amount of sensing can be quite large).

3.4.3. Interaction-Free Quantum Sensing Reif [96] deﬁnes (nearly) interaction-free sensing (IFS) similarly to IFM, except an upper bound is imposed on both the intensity to do the sensing (which again is an arbitrarily small multiplicative factor of the input intensity) whether or not the obstructing body is present. A quantum optical method for IFS (but not IFM) may be used to do I/O with bandwidth reduced by an arbitrarily small multiplicative factor of the bandwidth required for classical (e.g., conventional optical or electronic) I/O methods. Reif [96] proves there is no method for IFS with

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unitary transformations and so concludes that I/O bandwidth cannot be signiﬁcantly reduced by such quantum methods for sensing. (Also see Holevo [97], Fuchs and Caves [98] for proof that quantum methods cannot increase the bandwidth for transmission of classical information.)

3.5. QUANTUM COMPRESSION As noted above, quantum methods cannot increase the bandwidth for transmission of classical information; still, in certain cases, entangled states can be compressed to fewer qubits. This quantum compression could have important applications in practice, where the number of usable qubits is very limited. Schumacher [99] considered compression and decompression of a noiseless source of n quantum bits (qubits), each sampled independently from a given mixed state quantum ensemble. For such a quantum source, the compression factor obtainable by classical information theory is limited by the Shannon entropy, which in general (except in the case where the quantum ensemble has only orthogonal states) is less than the quantum compression factor given by the von Neumann entropy. In particular, Schumacher [99] proved a quantum noiseless coding theorem that states that the source’s von Neumann entropy is the number of qubits per source state which is necessary and sufﬁcient to asymptotically (in the limit of large code-block size) encode the output of the source with arbitrarily high ﬁdelity. The quantum noiseless coding of Schumacher has asymptotically optimal ﬁdelity and size; the resulting compressed number of qubits can be far fewer than in the classical case. SHANNON ENTROPY AND THE LIMITATIONS OF CLASSICAL METHODS FOR NOISELESS COMPRESSION. Suppose n characters from a ﬁnite alphabet S are each sampled independently over some probability distribution p. In classical information theory, the Shannon entropy of each character is HS ðpÞ ¼ P 1a2S pðaÞ log pðaÞ. A string of these n bits may be compressed without loss to a bit string of mean length HS (p)n. THE VON NEUMANN ENTROPY AND QUANTUM NOISELESS COMPRESSION. Following Schumacher [99], we assume there is a ﬁnite quantum state ensemble (S, p) which is a mixed state consisting of a ﬁnite number of qubit states S ¼ fja0 i; . . . ; jajSj1 ig, where each jai i 2 S has probability pi. The compressor is assumed to act on blocks of n qubits (so is a block compressor), and is assumed to know thisP underlying ensemble (S, p). The density matrix of (S, p) is an jSj jSj jSj1 matrix r ¼ i¼0 pi jai ihai j: The von Neumann entropy (see [99, 100]) corresponding to (S, p) is HVN ðrÞ ¼ Trðr log rÞ: In general, the Shannon entropy HS (p) is greater than or equal to the von Neumann entropy. These entropies are equal only when the states in S are mutually orthogonal.

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An Example: Consider a slightly more complex example of a source consisting of a sequence of n photons polarized randomly, with equal probability of phase 0 or phase angle y (e.g., As a very simple example of a source with low von Neumann entropy, consider N photons polarized randomly, equiprobably at 0 or 1.) In this case, the states are S ¼ fja0 i; ja1 ig; where the ﬁrst state ja0 i ¼ j0i; corresponds to phase 0, and the other state ja1 i ¼ cos yj0i þ sin yj1i corresponds to phase angle y, and the probabilities are both pð0Þ ¼ pð1Þ ¼ 12. The density matrix is r ¼ 12 ja0 iha0 j þ 12 ja1 iha1 j ¼ 12 ðj0ih0j þ ðcos yj0i þ sin yj1iÞðcos yh0j þ sin yh1j ÞÞ ¼ 2 1 2 2 ðð1 þ cos yÞj0ih0j þ cos y sin yj0ih1j þ cos y sin yj1ih0j þ sin yj1ih1j Þ which has 2 2 matrix form

2 1 1þcos y 2 cos y sin y

cos y sin y sin2 y

over the basis vector

j0i j1i

: Then we can

ﬁnd an appropriate b which gives a change of basis with new basis states j00 i ¼ j0i 0 r0 ¼ and j1 i ¼ cos bj0i þ sin bj1i; providing a diagonal density matrix 1 2

ð1þcos2 yÞþcos y sin y tan b

0

0

cos y sin yþsin2 y tan b

over the basis vector

j00 i

: Although

j10 i

this source has high Shannon entropy HS(p), it will have low von Neumann entropy HVN (r) in the case of a small magnitude phase angle y However, note that the entropies are the same in the special case where y=p/2, so the states ja0 i ¼ j0i, ja1 i ¼ j1i are orthogonal and the density matrix is simply the diagonal matrix r ¼ 12 ðj0ih0j þ j1ih1jÞwhich has a diagonal density matrix r ¼ j0i basis vector j1i .

1 2

0

0

1 2

over the

For technical reasons, the unitary compression and decompression mappings need to preserve the number of bits (some of which are ignored). An n-to-n0 quantum compressor is a unitary transformation that maps n-qubit strings to n-qubit strings; the ﬁrst n0 qubits that are output by the compressor are taken as the compressed version of its input, and the remaining nn0 qubits are discarded. An n0 -to-n decompressor is a unitary transformation that maps n-qubit strings to n-qubit strings; the ﬁrst n0 qubits input to the decompressor are the compressed version of the uncompressed n qubits, and the remaining nn0 qubits are all 0. The source to the compression scheme is assumed to be a sequence of n qubits sampled independently from (S, p). The observed output is the result of ﬁrst compressing the input qubits, then decompressing them, and measuring the result (over a basis containing the n inputs). The compression rate is n/n0 and the compression factor is n0 /n. The ﬁdelity of the compression scheme is the probability that the observed output is equal to the original input (that is, the probability that the original qubits are correctly recovered from the compressed qubits). The goal here is a quantum compression with both a high ﬁdelity and a high compression rate. Example (Continued): Consider again the example of a source consisting of a sequence of n photons polarized randomly, with equal probability of phase 0 or phase angle y. If y has small magnitude, then a quantum encoder can compress these photons into an entangled state using just a few photons. Furthermore, a

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quantum decoder can the recover n photons with the original distribution (with arbitrarily high ﬁdelity for large n) from these compressed photons. SCHUMACHER QUANTUM NOISELESS COMPRESSION. Schumacher [99] gave a quantum noiseless coding theorem which provided asymptotically optimal noiseless compression of a sequence of qubits independently sampled from a ﬁnite quantum state ensemble (S, p). The quantum noiseless coding theorem states that for any e,dW0 and sufﬁciently large n, (i) there is an n-to-n0 quantum compression scheme with ﬁdelity at least 1e and compression to length n0 nðHVN ðrÞ þ dÞ, and (ii) any n-to-n00 quantum compression scheme which gives compression to length n00 nðHVN ðrÞ dÞ, has ﬁdelity o1e. That is, in the limit of large code-block size, the source’s von Neumann entropy HVN (r) is asymptotically the number of qubits per source state which is necessary and sufﬁcient to encode the output of the source with arbitrarily high ﬁdelity. Given a known ﬁnite quantum state ensemble (S, p), Schumacher’s compression scheme assumes a known basis for which the density matrix r is diagonal, with nonincreasing values along the diagonal. The proof of the Schumacher quantum noiseless coding theorem and its reﬁnements by Jozsa and Schumacher [101] and H. Szeto [102] make use of the existence of a typical subspace L (see [101]) within a Hilbert space of n qubits over a source of von Neumann entropy HVN (r). The typical subspace L has dimension 2nHVN ðrÞ and with high probability, a sample of n qubits has an almost unit projection onto L. The Schumacher compressor simply transposes (via a permutation mapping) the subspace L into the Hilbert space of a smaller block of nHVN (r) qubits. These proofs are not completely constructive. Bennett [103] gave a constructive presentation of the Schumacher compression. He observes that the Schumacher compression can be done by a unitary mapping to a basis for which the density matrix r is diagonal (in certain simple cases the density matrix r is already diagonal, e.g., when the input is a set of n identical qubits) followed by certain combinatorial computation which we will call the Schumacher compression function SCHUMACHER. The Schumacher compression function SCHUMACHER simply orders the basis states ﬁrst by the number of ones (from smallest to largest) that are in the binary expansion of the bits and then reﬁnes this order by a lexical sort of the the binary expansion of the bits. That is, all strings with i ones are mapped before all strings with i+1 ones, and those strings with the same number of ones are lexically ordered. Note that for any given value X of the qubits, this transformation SCHUMACHER (X ) is simply a deterministic mapping from an n bit sequence to a n0 bit sequence deﬁned by a combinatorial computation. In particular, given an n bit binary string X, the transformation SCHUMACHER (X) is the number of n bit strings so ordered before X. It is easy to show that SCHUMACHER(X ) is a permutation. Since it is a permutation, it is a bijective function which is uniquely reversible; it is also a unitary transformation. To insure that the overall transformation (for all the states) is a quantum computation, it is essential that the transformation SCHUMACHER (X ) be done using only reversible, quantum-coherent elementary operations. (Bennett et al. [104] gave a

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polynomial time quantum algorithm for the related problem of extraction of only classical information from a quantum noiseless coding.) Cleve, DiVincenzo [105] then developed the ﬁrst polynomial time algorithm for Schumacher noiseless compression of n qubits. In particular, they explicitly computed the bijective function SCHUMACHER (X) and it’s reverse using O(n3) reversible, elementary unitary operations. This was previously the fastest previous algorithm for the Schumacher encoding and decoding functions. Recently, Reif and Chakraborty [108] gave a time efﬁcient algorithm for asymptotically optimal noiseless quantum compression and decompression, costing only Oðnðlog4 nÞlog log nÞ elementary quantum operations. This modiﬁed Schumacher encoding requires the evaluation of various combinatorial sums, for which Reif and Chakraborty provide efﬁcient recursive, reversible quantum algorithms. The coding of [106] employed a modiﬁed Schumacher encoding that was still asymptotically optimal in ﬁdelity and size. The Schumacher quantum noiseless coding theorem assumes the compressor knows the source. Jozsa et al. [107] recently gave a generalization of the Schumacher compression, that is, the compressor does not know the source, and thus provides the ﬁrst asymptotically optimal universal algorithm for quantum compression. Also, Braustein et al. [108] have recently given a fast algorithm for an quantum analog of Huffman coding, but do not provide a proof that this coding gives asymptotically optimal noiseless quantum compression (that is, reaches the von Neumann entropy), as provided by Schumacher compression. ([102] assumes the compressor knows the source, but can be extended using the techniques of Jozsa et al. [107] to a asymptotically optimal universal algorithm for quantum compression where the compressor does not know the source.)

3.6. QUANTUM ERROR-CORRECTING CODES 3.6.1. Quantum Coding Theory The qubit can be deﬁned in quantum information theory as the amount of information that can be carried in a quantum system with two basis states, e.g., the internal degree of freedom of a polarized photon. The qubit is thus a fundamental unit of quantum channel capacity. Nielsen [109] (Svozil [110, 111], Holevo [112], Knill, Laﬂamme [113, 114], and Ohya [115] develop a theory of quantum errorcorrecting codes and quantum information theory, e.g., they give the deﬁnition of quantum mutual entropy for an entangled state. Buhrman et al. [116], and Adami, Cerf [117] contrast quantum information theory with classical information theory. Quantum channel capacity has been investigated for noisy channels (DiVincenzo, et al. [118], Holevo [119], Barnum et al. [120]), very noisy channels (Shor, Smolin [121]), and quantum erasure channels (Bennett et al. [122]). Fuchs [123] showed that nonorthogonal quantum states maximize classical information capacity. (Also, Helstrom [124, 125] deﬁnes a quantum theory of information detection, and Fuchs [126] deﬁnes a related quantum theory of information distinguishability.)

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3.6.2. Decoherence Errors in QC Quantum decoherence is the gradual introduction of errors of amplitude in the quantum superposition of basis states. All known experimental implementations of QC suffer from the gradual decoherence of entangled states. The rate of decoherence per step of QC depends on the speciﬁc technology implementing QC. A signiﬁcant property of Shor’s algorithm is that the precision of the amplitudes in the superpositions need be only a polynomial number of bits. Although the addition of decoherence errors in the amplitudes may at ﬁrst not have a major effect on the QC, the effect of the errors may accumulate over time and completely destroy the computation. Researchers have dealt with decoherence errors by extending classical error correction techniques to quantum analogs. Generally, there is assumed a decoherence error model where the errors introduced are assumed to be uniform random with bounded magnitude, independently for each qubit.

3.6.3. Quantum Codes Shor [127] and Steane [128] gave the ﬁrst techniques for reducing quantum decoherence by the addition of extra qubits which are then projected via observation operations to eliminate errors in the superposition. Calderbank, Shor [129], and Steane [130] then proved that QC can be done with bounded decoherence error, assuming the error correction mechanism is without error itself. Bennett et al. [131], and Laﬂamme [132] gave the ﬁrst optimal 5-qubit codes, leading to asymptotically optimal (for large code blocks) quantum error correction codes. Shor [133] and Kitaev [134, 135] extended these techniques to do fault tolerant quantum computation on quantum networks, in the presence of bounded decoherence error, even if the error correction mechanism also suffers from error decoherence errors. A ﬁnal innovation (Aharonov, Ben-O [136], and Knill et al. [137, 138]) was concatenated versions of the above quantum codes that allow for arbitrarily long QC in the presence of arbitrary (i.e., not necessarily random) decoherence error below a ﬁxed constant threshold. Current bounds on this threshold are very small, and it seems likely (although it is not yet known) that they can be increased to above the decoherance error bounds of experimental techniques for QC. Also see the texts [38, 39] on quantum coding theory.

3.7. QUANTUM CRYPTOGRAPHY Here we overview quantum cryptography; also see the following texts: [35–37].

3.7.1. Quantum Keys Bennett et al. [139] and Bennett and Brassard [140] gave the ﬁrst methods for quantum cryptography using qubits as keys, which were proved to be secure

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against certain types of attacks. (However, see the remarks at the end of this subsection.) Surveys of quantum cryptography are given in Bennett, Brassard, Ekert [141], Brassard [142], Bennett, Brassard [143], Brassard [144], and Gisin [145]. Ozhigov [146] gives a protocol for security of information in quantum databases. Hruby [147] discusses further methods for quantum cryptography. Bennett et al. [148], Hughes et al. [149] describes experiments of quantum cryptography, including optical ﬁbers. Bennett et al. [150] gave a protocol for quantum oblivious transfer. Mayers [151] gives quantum oblivious transfer and key distribution protocols and Mayers [152] extends the protocols to noisy channels. Lo, Chau [153] give a quantum key distribution protocol which is unconditionally secure over arbitrarily long distance. Brassard, Crpeau [154] gave quantum bit commitment and quantum coin tossing protocols. Brassard et al. [155] gives a quantum bit commitment scheme provably unbreakable by both parties. Yao [156] proved quantum protocols secure against coherent measurements. Brassard et al. [157] shows how to defeat classical bit commitments with a quantum computer. Chau, Lo [158] gives further methods for qubit commitment. Crpeau et al. [159] gives protocols for quantum oblivious mutual identiﬁcation. IS QUANTUM CRYPTOGRAPHY ACTUALLY UNBREAKABLE? Unfortunately, some of the methods for quantum cryptography that claim to be unbreakable can in fact be broken by sidestepping assumptions assumed in the proofs of their security. For example, to break the well known quantum cryptography method of Bennett and Brassard [140], Brandt [160] provided a method (experimentally demonstrated by Kim et al. [161]) that exploited entanglement of momentum with the phase of photons, making observations of the momentum portions to infer transmitted phases. It is not clear what other prior results in quantum cryptography could be broken by similar techniques, which places the ﬁeld of quantum cryptography in some doubt. (Also, Lo, Chau [162] have recently argued that quantum bit commitment and ideal quantum coin tossing are impossible in certain cases that are not covered in the preceeding results.)

3.7.2. Distributed Quantum Networks Future hardware will have to be fast, scalable, and highly parallelizable. A quantum network is a network of QCs executing over a spatially distributed network, where quantum entanglement is distributed among distant nodes in the quantum network. Thus, using distributed entanglement, a quantum network distributes the parts of an entangled state to various processors, which can act on the parts independently. Pellizzari [163] proposes quantum networks using optical ﬁbers; Cirac, Zoller et al. [164] and Bose, Vedral [165] show state transfer distribution can be done among distant nodes. For example, [164] uses a cavity QED device that traps atoms in multiple cavities and exchanges photons between

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79

the cavities to establish the distributed entanglement. Various basic difﬁculties were overcome. They are explained below. How can one do state transfer distribution? Bennett et al. [166, 167] and Brassard [168] developed a technique known as teleportation to transmit arbitrary input states with perfect ﬁdelity. It does this by separating the input state into classical and quantum components. The input can then be reconstructed from these components with perfect ﬁdelity. How can one cope with communication errors and attenuation in a quantum network? Wootters, Zurek [169] proved that a single quantum cannot be cloned. (Note: Buzek, Hillery [170] recently claimed a universal optimal cloning of qubits and quantum registers in a distributed quantum network, but this seems inconsistent with the no-cloning theorem.) That no-cloning theorem implies that once a signal becomes attenuated in an optical ﬁber communication channel, then it cannot (generally) be ampliﬁed. It would at ﬁrst appear that communication and quantum network links may be limited to distances of the order of the attenuation length in the ﬁber. However, the range of quantum communication could be extended using quantum repeaters that do quantum error correction, restoring the quantum signal without reading the quantum information. Ekert, Huelga et al. [171] extend the techniques of distributed quantum computation to noisy channels, and showed that for quantum memories and quantum communication, a state can be transmitted over arbitrary distances with bounded error, provided a minimum gate accuracy can be achieved—a constant factor of this error.

3.8. OTHER ALGORITHMIC APPLICATIONS OF QC The early literature in QC provided some examples of QC algorithms for problems constructed for the reasonable purpose of showing that QC can solve some problems more efﬁciently than conventional sequential computing models. Later, quantum algorithms were developed for variety of useful applications. See the texts on quantum algorithms: [27–34, 40]. Quantum Fourier Transforms. Drutsch, Jozsa [49] gave an O(n) time quantum algorithm for creating a uniform superposition of all possible values of n bits, which is a quantum Fourier transform over the ﬁnite ﬁeld of size 2. Simon [172] used this quantum Fourier transform to give an efﬁcient time quantum algorithm for determining whether a function over a ﬁnite domain is invariant under some XOR-mask. This provided one of the ﬁrst examples of a quantum algorithm which efﬁciently solves an interesting problem that is costly for classical computation. Brassard, Hoyer [173] gave improvements to Simon’s algorithm. There have been a number of

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efﬁcient quantum algorithms for extensions of the quantum Fourier transform: to the approximate quantum Fourier transform (Coppersmith [174]), over various domains (Grifﬁths, Niu [175], Hoyer [176]), over symmetric groups (Beals [177]), and over certain nonabelian groups (Pueschel, Roetteler, Bet [178]). Vedral, Barenco, Ekert [179] give efﬁcient quantum networks for elementary arithmetic operations using the quantum Fourier transform. Grigoriev [180] used the quantum Fourier transform to test shift-equivalence of polynomials. Quantum Factoring. The most notable algorithmic result in QC to date is the quantum algorithm of Shor [181, 182] for discrete logarithm and integer factorization in polynomial time (with modest amplitude precision). (Also see a review of the algorithm by Ekert and Jozsa [183].) Shor’s algorithm uses an efﬁcient reduction (due to Miller [184]) from integer factoring to the problem of approximately computing the period (length of a orbit) within an integer ring. Shor approximates the period by repeated use of a quantum Fourier transform over an integer ring and greatest common divisor computations. There has been further considerable work on Shor’s quantum factoring algorithm: Zalka [185] improved the time complexity; Beckman et al. [186] describe its execution on quantum networks with small size and depth; Obenland, Despain [187], Plenio, Knight [188] consider the feasibility of executing Shor’s quantum factoring algorithm on various quantum computer architectures. (The latter provide somewhat pessimistic lower bounds for the factorization time of large numbers on a quantum computer in the presence of decoherance errors.) [189] describes a 7-qubit demonstration of Shor’s factorization algorithm using nuclear magnetic resonance. Kitaev [190] gave an independent derivation of Shor’s factoring result using a reduction to ﬁnd an abelian stabilizer. Quantum Search. Another signiﬁcant efﬁcient QC algorithmic result is the algorithm pﬃﬃﬃﬃ of Grover [191], which searches within a database of size N in time N . (An interesting property of Grover’s algorithm for search is its similarity to the quantum Zeno affect technique for p quantum measurement ﬃﬃﬃﬃ [94, 95]. In particular, the algorithm also uses Oð N Þ stages of unitary operations, each quite similar to a stage of the quantum Zeno sensing method.) Grover reﬁned his result to require only a single query [192] and to use almost any unitary transformation [193]; Zalka [194] showed Grover’s algorithm cannot be further asymptotically sped up and so is optimal for database search; and Pati [195] gave further improvements to the bounds. Biron et al. [196] extended Grover’s algorithm to arbitrary initial amplitude distribution. Cockshott [197] gave fast quantum algorithms for executing more general operations on relational databases, and Benjamin, Johnson [198] discuss the use of Grover’s algorithm and related quantum algorithms for other data processing problems. Farhi et al. [199] showed that Grover’s algorithm could not be extend to quickly determine

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parity of N bits; in particular, they showed that any quantum algorithm for parity takes at least N/2 steps. Meyer [200] and Terhal, Smolin [201] propose quantum search algorithms that do not to require entanglement. Brassard et al. [202, 203] combine the algorithmic techniques of Grover and Shor to give a fast quantum algorithm for approximately counting (i.e., ﬁnding the number of matches in a database). While Grover’s algorithm is clearly an improvement over linear sequential search in a database, it appears less impressive in the case of an explicitly deﬁned database which needs to be stored in volume N. Parallel computation can do search in a database of size N in time at most polylogarithmic with N (that is, in time OðlogOð1Þ NÞ) by relatively straightforward use of parallel search Moreover, Grover’s algorithm may not have a clear advantage even in the case of an implicitly deﬁned database, which does not need to be stored, but instead can be constructed on the ﬂy (e.g., that arising from NP search methods). In this case, Grover’s search algorithm can be used to speed up combinatorial search within a pﬃﬃﬃﬃ domain of size N to a time bound of Oð N Þ. (Hogg [204], and Hogg, Yanik [205] investigate similar quantum search techniques for local and other combinatorial search problems.) In this case Grover’s algorithm appears to require only volume logarithmic in the search space size N. In contrast, parallel computation takes volume linear in the combinatorial search space, but takes just time polylogorithmic in the search space. Quantum Simulations in Physics. The ﬁrst application proposed for QC (Feynman [46]) was for simulating quantum physics. In principle, quantum computers provide universal quantum simulation of any quantum mechanical physical system (Lloyd [206], Zalka [207], Boghosian [208])). Proposed QC simulations of quantum mechanical systems include many-body systems (Wiesner [209]); many-body Fermi systems (Abrams, Lloyd [210]); multiparticle (ballistic) evolution (Benioff [211]); quantum latticegas models (Boghosian, Taylor [212]), Meyer [213, 214]); Ising spin glasses (Lidar, Biham [215]); the thermal rate constant (Lidar, Wang [216]; and quantum chaos (Schack [217]). Quantum Learning. QC may have some interesting applications in learning theory and related problems. Bshouty, Jackson [218] describe learning Boolean formulas in disjunctive normal form (DNF) over the uniform distribution of inputs, using a quantum example oracle; Ventura, Martinez [219] describe a QC learning algorithm for learning DNF using a classical example oracle. Also, Yu, Vlasov [220] describe image recognition using QC, Tucci [221] investigates quantum Bayesian networks, and Ventura, Martinez [222] describe a quantum associative memory, Quantum Robotics. Benioff [223] considers a distributed QC system with mobile quantum robots that can carry out carrying out measurements and physical experiments on the environment; as an example, Benioff gives an

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algorithm for the problem of measuring the distance between a quantum robot and a particle on a 1D space lattice. Hogg [207] proposes the use of distributed QC to allow small-scale sensors and actuators to be controlled in a distributed manner. Further discussion of the applications of QC are given by Landauer [224, 225]. Winding Up Quantum Clocks. The precision of atomic clocks are limited by the spontaneous decay lifetimes of excited atomic states. An interesting application of QC proposed by Huelga [226] (also see Bollinger et al. [227]) is to extend these lifetimes by using quantum error correcting codes to inhibit the spontaneous decay. A similar idea can be used for improving the precision of frequency standards and interferometers. Quantum Strategies. Meyer [228, 229] has proposed a class of generalized games that allow for quantum strategies and he proves that they provide an improvement over conventional mixed (randomized) strategies for certain games.

3.9. POSSIBLE TECHNOLOGIES FOR DOING QC Here we provide an overview of various experimental implementations of quantum computation; also see the texts [41–45]. As noted previously, any QC can be realized by a universal set of gates consisting of the 2-qubit XOR operation along with some 1-qubit operations. There are two basic approaches known to do QC. (A) Micromolecular QC. Here QC on n qubits is executed using n individual atoms, ions, or photons, and each qubit is generally encoded using the quantized states of each individual atom, ion, or photon. The readout (observation operation) is by measurement of the (eigen) state of each individual atom, ion, or photon. We enumerate a number of proposed micromolecular QC methods as follows: Quantum Dots. Burkard et al. [230], Loss, Di Vincenzo. [231], and Meekhof et al. [232] describe the use of coupled quantum dots to do QC. ( [78] proposes quantum computation using Cooper pairs.) Ion Trap QC. Cirac, Zoller [233], Pellizzari et al. [234], and James [235] proposed using a linear array of cold trapped ions (the ions are trapped by electromagnetic ﬁelds) whose energy states are used to store the qubits; vibrational modes between consecutive ions also can be used to store states of qubits. The coupling of the qubits is by electrostatic repulsion between the ions. Unitary transitions on superpositions can be executed via an associated array of lasers, each of which pulses a distinct ion; these induce electric dipole moments that determine the transitions. A group at the National Institute of Standards at Boulder, Colorado (Wineland et al.

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[236, 237] King et al. [238], and Turchette et al. [239]) and a group at Los Alamos (Hughes [240], Hughes et al. [241], and James [242]) have experimentally demonstrated trapped ion QC. These and other researchers have addressed various key issues associated with quantum computation with trapped ions. Deterministic entanglement of two trapped ions (Turchette et al. [239]) Decoherence bounds (Hughes et al. [240] and Plenio, Knight [244]) Measurement and state preparation, i.e., initialization of the collective motion of the trapped ions (Schneider et al. [245] and King et al. [238]), Coherent quantum-state manipulation of trapped atomic ions (Wineland et al. [236, 237]), Heating of the quantum ground state of trapped ions (James [246]) and quantum computation with ‘‘hot’’ trapped ions (Schneider et al. [247]). Cavity QED. A group at Cal Tech (Turchette [248]) have experimentally demonstrated the use of trapped photons in a cavity QED system to execute 2-qubit XOR gates and thus in principle can do universal QC. The qubits are encoded by the circular polarization of photons interacting. The XOR unitary transitions on superpositions can be executed by resonance between interacting photons in the cavity; the coupling of qubits is via resonance between interacting photons using a Cesium atom also in the cavity, and the coupling is tuned by the spacing of mirrors in the cavity. Photonics. Various groups (i.e., Chuang et al. [249, 250] and Torma, Stenholm [251]) have experimentally demonstrated QC using optical systems where qubits are encoded by photon phases, and universal quantum gates are implemented by optical components consisting of beamsplitters and phase shifters as well as nonlinear media (also see the linear optics QC proposed by Adami, Cerf [252]). Heteropolymer. This is a polymer consisting of a linear array of atoms, each of which can be either in a ground or excited energy state. Teich et al. [253] ﬁrst proposed classical (without quantium superpositions) molecular computations using heteropolymer. Later Lloyd [254] extended the use of heteropolymers to QC using the energy states to store the state of the qubits. The coupling of qubits may be via electric dipole moments that cause energy shifts on adjacent atoms. Unitary transitions on superpositions can be executed via pulses of a laser at particular frequencies; these induce electric dipole moments that determine the transitions. Nuclear Spin. DiVincenzo [255] and Wei et al. [256, 257] proposed the use of nuclear spin to do QC; see the remarks following the discussion of bulk QC. Quantum Propagation Delays. Castagnoli [258] proposed a way to do QC using retarded and advanced propagation of particles through various media.

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Of these, ion trap QC, cavity QED QC, and photonics have been experimentally demonstrated up to a very small number of qubits (about three bits). The apparent intention of such micromolecular methods for QC is to have an apparatus for storing qubits and executing unitary operations (but not necessarily executing observation operations) which requires only volume linear in the number of qubits. One difﬁculty (addressed by Kak [259], and Murao et al. [260]) is puriﬁcation of the initial state: If the state of a QC is initially in an entangled state, and each of the quantum gate transformations introduces phase uncertainty during the QC, then the effect of these perturbations may accumulate to make the output to the QC incorrect. A more basic difﬁculty for these micromolecular methods is that they all use experimental technology that is not well established; in particular, their approaches each involve containment of atomic size objects (such as individual atoms, ions, or photons) and manipulations of their states. A further difﬁculty of the micromolecular methods for QC is that apparatus for the observation operation—even if observation is approximated— seems to require volume growing exponential with the number of qubits, as described earlier in this paper. (B) Bulk (or NMR) QC. Nuclear magnetic resonance (NMR) spectroscopy is an imaging technology using the spin of the nuclei of a large collection of atoms. Bulk QC is executed on a macroscopic volume containing a large number of identical molecules in solution, each of which encodes all the qubits. The molecule can be chosen so that it has n distinct quantized spins modes (e.g., each of the n nuclei may have a distinct quantized spins). Each of the n qubits is encoded by one of these spin modes of the molecule. The coupling of qubits is via spin-spin coupling between pairs of distinct nuclei. Unitary operations such as XOR can be executed by radio frequency (RF) pulses at resonance frequencies determined in part by this spin-spin coupling between pairs of nuclei (and also by the chemical structure of the molecule). Bulk QC was independently proposed by Cory, Fahmy, Havel [261] and Gershenfeld, Chuang [22, 262]. Also see Berman et al. [266] and the proposal of Wei et al. [257] for doing NMR QC on doped crystals rather than in solutions, and see Kane [264] for another solid state NMR architecture for quantum computing using silicon. Bulk QC. was experimentally tested (Jones et al. [265, 266]) and applied to demonstrate the following tasks: quantum search (Jones [267]), approximate quantum counting (Jones, Mosca [268]), Deutsch’s problem (Jones, Mosca [269]), and the Deutsch–Jozsa algorithm on 3 qubits (Linden, Barjat, Freeman [270]). Advantages of Bulk QC. (i) it can use well established NMR technology and in particular macroscopic devices, The main advantages are (ii) the long time duration until decoherence (due to a low coupling with the environment) and (iii) scaling to more qubits than other proposed technologies for QC.

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Disadvantages of Bulk QC. A possible disadvantage of bulk QC is that it appears to allow only a weak measurement of the ensemble average that does not provide a quantum state reduction; that is, the weak measurement does not alter (at least by much) the superposition of states. Another disadvantage of bulk QC is that it may require (for a variety of reasons) macroscopic volumes and volumes which grow exponentially with the number of qubits. Macroscopic volumes may be required for measurement via conventional means. However, known quantum algorithms can still be executed even in this case (e.g., see Gershenfeld, Chuang [22, 262]). So the lack of strong measurement is not a major disadvantage. Also, bulk QC requires the initialization close to a pure state. If bulk QC is done at room temperature, the initialization methods of Cory, Fahmy, Havel [261] (using logical labeling) and Gershenfeld, Chuang [22, 262] (using spatial averaging) yield a pseudo-pure state, where the number of molecules actually in the pure state drops exponentially as 1/cn with the number n of qubits, for some constant c (as noted by Warren [271]). If we approximate the resulting measurement error by a normal distribution, the measurement pﬃﬃﬃﬃ error is (with high 0 , for likelihood) at least a multiplicative factor of 1 c0 = Np ﬃﬃﬃﬃ some constant c . n 0 To overcome this measurement error, we need 1=c 4c = N ; and so we require that the volume be at least N4ðcn =c0 Þ2 : Hence, for the output of the bulk QC to be (weakly) measured, the volume (the number N molecules) of bulk QC needs to grow exponentially with the number n of qubits. Recently, there have been various other proposed methods for initialization to a pure state: Barnes [272] proposes the use of very low temperatures. Gershenfeld, Chuang [22, 262] suggest the use of gradient ﬁelds. Knill et al. [273] suggest a randomization technique they call temporal averaging. Recent work of Schulman, Vazirani [274] provides polynomial volume for initialization, with the assumption of an exponential decrease in spin-spin correlations with the distance between the nuclei located within a molecule. (In particular, they assume that the statistical correlation between and two bits on a molecule falls of exponentially with the distance between these bits). Although their methods may provide a solution in practice, known inter-atomic interactions such as the spin-spin correlations are generally considered to be governed by potential force laws which decrease by inverse polynomial powers rather than by an exponential decrease. It has not yet been experimentally established which of these pure state initialization methods scale to a large number of qubits without large volume. (Note: Some physicists feel that it has not been clearly established whether (a) NMR is actually a quantum phenomenon with quantum superposition of basis states, or (b) if NMR just mimics a quantum phenomenon and is actually just

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classical parallelism, where the quantum superposition of basis states is encoded using multiple molecules where each molecule is in a distinct basis state. If the latter is true (each molecule is in a distinct basis state) then the volume may grow grow exponentially with the number n of qubits, since each basis state may need to be stored by at least one molecule, and the number of basis states can be 2n. (See Williams, Clearwater [23]) Also, even if each molecule is in some partially mixed quantum state (see Zyczkowski et al. [275]), the volume may still need to grow very large.) In summary, some possible disadvantages of bulk QC that may make it difﬁcult to scale are (i) the inability to do observation (strong measurement with quantum state reduction); (ii) the difﬁculty to do even a weak measurement without the use of exponential volume; (iii) difﬁculty (possibly now resolved) to obtain pure initial states without the use of exponential volume; and (iv) the possibility that bulk QC is not a quantum phenomena at all (an unresolved controversy within physics), and so may require use of exponential volume. It is interesting to consider whether NNR can be scaled down from the macroscopic to molecular level. DiVincenzo [255] and Wei et al. [256, 257] propose doing QC using the nuclear spins of atoms or electrons in a single molecule. The main advantages are (i) small volume and (ii) the long time duration until decoherence (an advantage shared with NMR). The key difﬁculty of this approach is the measurement of the state of each spin, which does not appear to be feasible by the mechanical techniques for detection of magnetic resonance usually used in NMR (which can only do detection of the spin for large ensembles of atoms).

3.10. RESOURCE BOUNDS In this chapter, we have discussed many applications of quantum computation that provide advantages over classical methods of computation. Certain applications of QC (e.g., quantum cryptography) require only a small or constant number of qubits, whereas other applications (e.g., factoring and database search) require a large number of qubits and moreover require an observation operation at least as the ﬁnal step of the QC. For these advantages to be practical, we need to determine that there are no unfeasible, large resources required by QC. Hence we complete the chapter with a review of the resource bounds of quantum computing compared to the resources required by classical methods for computation. In particular, we will conclude that for the advantages of QC (with a large number of qubits) to be practical for applications requiring a large number of qubits, there needs to be determined (theoretical and practically) bounds on the volume required of observation operations. This seems to us a major missing element in the ﬁeld of QC. The energy consumption, processing rate, and volume are all important resources to consider in computing devices. Conventional (classical) electronic supercomputers of the size of a work station operate in the range of 109 Joules

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per operation, at up to about 50 giga-ops per second, with memory of about 10 to 100 giga-bytes, and in a volume of about 10 cm2. The volume scales as the number of bits of storage. Energy Bounds for QC. The conventional linear model of QC allows only unitary state transformations and so by deﬁnition is reversible (with the possible exception of the observation operation that does quantum state reduction). Benioff [48] noted that as a consequence of the reversibility of the unitary state transformations of QC, these transformations dissipate no energy. But this does not consider (i) the precision of the amplitudes to be preserved nor (ii) the expected time duration required to drive the operation to completion. Gea-Banacloche [276] and Ozawa [277] independently derived lower bounds on the energy needed to execute within a given precision of the amplitudes and in a given time, an elementary qubit logical operation on a quantum computer. They derived energy lower bounds depending inversely on the time duration for the operation and on the precision of the amplitudes to be preserved. Hence, for polynomial time quantum computations requiring polynomial relative precision, the lower bounds on energy are polynomial, though the constant factors could be a limitation for practical implementations. (Recall that Bernstein, Vazirani [50] proved that BQP computations can be done with unitary operations speciﬁed by only logarithmic bits of precision, which corresponds to relative precision e where e41=nOð1Þ :) These energy lower bound results were stated to be independent of the nature of the physical system encoding the qubits and under what the authors claimed normal circumstances in a wide variety of conditions for implementations of quantum computers. Nevertheless, the matter still appears to not be completely resolved, since there may be physical implementations of quantum computers that do not abide by their assumptions. Energy bounds for the quantum qubit logical operations require better understanding and study, particularly with respect to their dependence on the technology used. Processing Rate of QC. In QC, the rate of execution unitary operations largely depends on the implementation technology (see Section 3.9); certain techniques can execute unitary operations in microseconds (e.g., bulk NMR) and some might execute at microsecond or even picosecond rates (e.g., photonic techniques for NMR). The time duration to do observation can also be very short, but it may be highly dependent on the size of the measuring apparatus and the required precision. (See the following discussion on the observation operation and its volume). Volume Bounds for QC. We now consider (perhaps more closely than usual in the quantum literature) the volume bounds of QC. Potentially, the modest volume bounds of QC may be the one signiﬁcant advantage over classical methods for computation. Due to the quantum parallelism (i.e., the superposition of the basis states allows each basis state to exist in parallel),

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the volume would appear to be no more that the number of qubits. This may be true, but there are a number of substantial issues that need to be carefully considered. Recall the observation operation both provides a measurement of a qubit with a resulting state reduction. However, the QC literature has not yet carefully considered the volume bounds for the observation operation and as we shall see, it is not yet at all clear what the volume required. In spite of major works on the mathematical and physical foundations of quantum observation, the precise nature of quantum state reduction via a strong quantum measurement remains somewhat of a mystery. Two distinct approaches to the mathematical and physical foundations of observation have been developed: (a) the Copenhagen Formulation, where the observation is simply an assumed basic operation and is considered to be done by a macroscopic measuring device, and (b) the von Neumann Formulation [100, Chapter 4: Macroscopic Measurement], which views the measuring apparatus as well as the quantum system measured as both part of a quantum system. Hence the evolution of the system (and resulting experimental predictions) can be distinct from that predicted by the Copenhagen formulation of observation (which does not take this into account since the measuring apparatus is assumed in their formulation to be very large). See Cerf and Adami [18] for a comparison the Copenhagen and von Neumann formulations and see Hay, Peres [278] for an example of this difference. In summary, the Copenhagen and the von Neumann formulations for observation differ in the assumed context (macroscopic or microscopic measurement apparatus). (Note: Attempts to rectify the difference between the Copenhagen and the von Neumann formulation for observation are given in Hay, Peres [278] and in Zurek [279], but it appears not yet resolved.) The Copenhagen formulation for observation is generally used in the context of quantum physics experiments which use macroscopic measurement apparatus. However, the Copenhagen formulation does not seem to be applicable in the context of a microscopic measurement apparatus, which is so small that it is subject to quantum effects (and thus is within a unitary quantum system). So the Copenhagen formulation for observation may not appropriate for molecular size QC. Although the von Neumann formulation of observation is not relevant to the vast majority of physics experiments (since their experiments generally use large measuring apparatus and small number of degrees of freedom (qubits)), it appears to be appropriate for molecular size QC. It is possible that the volume for quantum observation apparatus grows very quickly with the number of qubits in the von Neumann formulation. In particular, no one has proved a upper bound on the volume for quantum observation (as a function of the number of qubits) assuming the von Neumann formulation. See the Appendix for a further discussion of the problem of determining volume bounds for the observation operation in QC.

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3.11. SUMMARY AND ACKNOWLEDGMENTS We have have provided an overview of the ﬁeld of quantum computing and surveyed its major algorithmic results and applications as well as physical implementations and their limitations. Some issues such as energy costs as well as volume of observation apparatus for quantum computing are still unresolved, and the later are further addressed in the Appendix. We would like to thank G. Brassard for his clear explanation of numerous results in the ﬁeld of QC. Also, I would like to thank P. Shor and U. Vazirani for references and for illuminating discussions on quantum computation, particularly on the issue of volume bounds for quantum observation.

3.12. APPENDIX: VOLUME OF OBSERVATION APPARATUS FOR QUANTUM COMPUTING Here we discuss the challenge of providing volume bounds for observation apparatus when doing QC.

3.12.1. A Potentially Fallacious Proof of Small Volume First we note that one might be tempted to give a constructive proof that observation can be done on n qubits in small volume, along the following lines: (i) Basis Step. We begin with a simple, well established experimental method for observation of a single qubit in small quantum system with say n0 qubits for a constant n0. There are many other examples of experimentally veriﬁed methods for observation using macroscopic measurement apparatus. (For example, a number of proposed QC architectures (e.g., the Cirac and Zoller [233] 3, and Pellizzari et al. [234] proposed ion trap QC and Kane’s [264] silicon-based NMR QC) give speciﬁc descriptions of measuring apparatus that have been experimentally veriﬁed for observation of a single qubit within a quantum computing systems with a constant number of qubits. While their measuring apparatus is macroscopic, it still must have just some ﬁnite volume. (ii) Inductive Step. However, then we just scale up by using the same experimental apparatus to do observation on each of n qubits (that is, repeating the observation for each of the other qubits). This seems to result in a small volume (perhaps even linear size) apparatus for observation. The potential fallacy of this line of argument is: (a) In the basis step, the experiments of [230, 260] did not provide bounds on the errors (or ﬁdelity) of the measurement as a function of the volume of the measuring apparatus. (b) The inductive step fails to take into account quantum effects involving both the measuring apparatus and the n qubits, as might be predicted by

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the von Neumann formulation of quantum measurement in the case where the measuring apparatus is so small that it is subject to quantum effects. That is, there needs to be given, in addition to the experimental description (which is only established for n0 qubits): (iii) A mathematical analysis of the quantum effects (in the context of a closed unitary system) involving the measuring apparatus as the number n of qubits grows large. In particular, bounds on the errors (or ﬁdelity) of the measurement need to be determined as a function of the size of the measuring apparatus. Without this crucial ﬁnal element, the proof is certainly not complete. Since the observation operation is not reversible, such a proof (in the context of a closed unitary system) seem unlikely to be obtainable.

3.12.2. Possible Experimental Demonstrations of Measurement Another approach would be to test a proposed small-volume apparatus for observation on n qubits for moderate size n (say, in the range of a few hundred, which is required for a nontrivial factoring computation). But the experimental evidence of the volume bounds for observation is unclear, since the QC experiments have not yet been scaled to large or even moderate numbers (say dozens) of qubits, and there are few if any physics experiments for this case. (Shnirman, Schoen [120] describe the use of a single-electron transistor to perform quantum measurements; D’Helon, Milburn [280] describe quantum measurements with quantum computers; and Ozawa [281] describes methods for nondestructive (known as nondemolition) quantum measurements of certain quantum computations.) Hence, at this time that there appears to be neither a mathematical proof nor an experimental demonstration (for even a moderately large number of qubits n) that observation can be done in small volume (in a closed quantum system). Thus there is no evidence (either mathematical or experimental) at this time that QC using measurement scales to large numbers of qubits with small volume. We ﬁrst consider a number of related questions concerning measurement and quantum state reduction:

3.12.3. Is a Quantum Observation Instantaneous? It appears not. Brune et al. [282] describe the progressive decoherence of the meter in a quantum measurement.

3.12.4. Is an Observation Always Reversible? It appears the answer is no (in a narrow mathematical sense of a state reduction), yes (for small closed state spaces), and no (in a practical sense for entanglements in a large state space).

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By the strict mathematical deﬁnition of the state reduction due to observation, an observation is not reversible in general. Under what conditions is a measurement reversible in the strict mathematical sense? That is, when can we measure classical information from a quantum source (yielding a set of pure states with their probabilities with a reduction of quantum entropy), but later be able to reverse this process to regenerate the entangled source state? Bennett et al. [104] show that this is possible in the very special case where the source states can be partitioned into two or more mutually orthogonal subsets. (Other necessary and sufﬁcient conditions for measurements to be reversible have been proved in Bennett et al. [104]; Chuang, Yamamoto [283] describe how to regenerate a qubit if it has observable error.) There is experimental evidence that the physical execution of some reductions via measurement are in fact reversible (at least in very small closed systems). Mabuchi, Zoller [284] have observed inversions of quantum jumps in very small quantum-optical systems under continuous observation, and Ueda [285] compares the notions of mathematical and physical reversibility. On the other hand, in the case of entanglements in a large state space, even if a measurement is in principle reversible in a closed system due the reversible nature of the diffusion process, the likelihood of such a reverse to the original state, within a moderate (say polynomial in n) time duration, appears to drop exponentially with the number of qubits n. Gottﬁeld [286] and Diosi, Lukacs [287] explain quantum state vector reduction via strong measurement as a physical process, e.g, state diffusion into the atoms of the measurement apparatus. (Also see Pearle [288, 289].) This diffusion due to reduction may be modeled by a system similar to a rapidly mixing Markov system in probability theory, which seems to provide a very low (dropping exponentially with n) likelihood for reversibility within a polynomial time duration. (Others have modeled measurement by a nonlinear interactions with the environment, which are irreversible.)

3.12.5. Should You Avoid Observation Operations? An alternative approach is to completely avoid observation operations on the basis that the observation operation is not actually essential to many quantum computations. (This seems somewhat surprising, given the extensive use of the observation operation in the QC literature for both algorithms and quantum error correction.) Bernstein, Vazirani [50] (by showing that any given observation operation can be delayed to future steps by use of the using XOR operation) proved that all observation operations can be delayed to the ﬁnal step of a quantum computation. For a small eW0, let some particular qubit (of the linear superposition of basis states) be e-near classic if had the qubit been observed, the measured value would be a ﬁxed value (either be 0 or 1) with e probability. Suppose the output of a QC consists of the observation of a subset S of the qubits; the resulting reduced superposition will be termed the output superposition.

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Bernstein and Vazirani [50] and Brassard et al. [173, 202] observe that any QC can be repeated to insure the output qubits are e-near classic in the ﬁnal output superposition after the repetitions. Note that if a QC with bounded amplitude precision is reduced by an observation, the output qubits yield the correct value with high likelihood. Hence we may consider simply not doing the observation reduction to a basis state in the ﬁnal step; in place of this (reduced) output superposition we simply output the nonreduced quantum state superposition of the QC that exists just prior to the ﬁnal observation step. This alternative approach can eliminate entirely the observation operation from many quantum computations, and so provides small volume, but has the drawback of providing a nonclassic output consisting of a nonreduced quantum state superposition. The potential difﬁculty with this approach is as follows: If this (nonreduced quantum state superposition) output is then processed by a classical computing machine, it may propagate unwanted quantum effects to the classical computing machine.

3.12.6. What about Approximate Observation Operations? An approach to this difﬁculty is to only do the observation operation approximately within accuracy e; this may sufﬁce for many QC applications. However, even if the observation operation is done e-approximately by unitary operations, it appears to require a number of additional qubits n0 growing exponentially with the n, the original number of qubits of the QC. In fact, we know of no upper bound on n0 better than 2n log (1/e).

3.12.7. Why May the Volume Required by Observation Apparatus Not Be Small? We next consider whether it is reasonable to expect that a mathematical proof (or such experimental demonstrations) of small volume quantum observation will ever be done. We provide an informal argument that even an e-approximate observation cannot be done in polynomial time using small volume, where e is the inverse of a polynomial. (It should be emphasized that the following is not a formal proof in any sense.) Since for n qubits, the size of the basis state space grows as 2n in the general case, it seems reasonable to assume (e.g., where the physics of the strong measurement is modeled by a diffusion process [286–288] that is rapidly mixing) that the likelihood of reversibility within polynomial time bounds drops exponentially with the number n of qubits. Thus, in the context of polynomial time computations, the e-approximate observation is assumed irreversible with high likelihood. The argument will hinge on the assumption, made by conventional formulations of quantum computation, that quantum computation (including both unitary qubit operations as well as the nonunitary observation (or projection) operation) can be exectuted for any given number n qubits, which makes an implicit assumption that both unitary and nonunitary operations can be executed at any scale.

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Let us also assume that the number of qubits n is small (at most a few hundreds). For sake of contradiction, let us for the moment suppose that (i) quantum computing scales to at least moderate size (say a few tens of thousands of qubits), and (ii) an e-approximate observation operation can be done on one of n qubits by a microscopic measuring device of size n0 =nc, for a constant c, and operating within time polynomial in n. Since n is small, the measuring device is surely of sufﬁciently small size so that its physics is consistent with established quantum physics. (Observe that if quantum computing is to scale to at least moderate size n0 , then surely quantum effects need to hold for molecules of size n0 ). This implies that we need to view the apparatus for the observation as executing polynomial time unitary quantum computation, which is reversible, so the reverse of the observation also executes in quantum polynomial time. Hence we have an apparent contradiction, since we have assumed the e-approximate observation is not reversible in polynomial time. (Note: This argument does not require that the governing physical laws shift at some deﬁnite size from a quantum-mechanical paradigm to a classical paradigm; instead, the argument requires that if the quantum-mechanical paradigm is valid at size n then it also is valid at some what larger size n0 =nc.) Due to informal nature of this argument, it only provides partial evidence that (with the above assumption), QC with the observation operation does not scale to a large number of qubits within small volumes, and in particular that a polynomial time e-approximate observation operation requires very large volume and cannot be done at the micromolecular scale for moderate large n. We feel our above argument is far too informal to provide a resolution of the issue. It remains a major open problem in QC to provide a formal proof that either (i) there is large volume required for observation or (ii) there is not.

3.13. CONCLUSIONS This chapter provided an overview of the ﬁeld of QC, including abstract models for QC. We have surveyed major potential applications of QC, for example, cryptography, speeding up combinatorial search and integer factorization were surveyed. Major technologies for experimental implementation of QC have been enumerated. Even after two decades of major research efforts, all prior QC demonstrations to date have been limited to very small number of qubits. Various key technical challenges and fundamental resource bounds for scaling QC to larger problem sizes have been reviewed. It remains to be demonstrated if these challenges can be overcome to allow QC to scale to problem instances of practical importance to combinatorial search and integer factorization.

REFERENCES Note: QCQC 98 is an acronym for Proceedings of 1st NASA Workshop on Quantum Computation and Quantum Communication (QCQC 98), Springer-Verlag, Feb 1998.

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261. D. G. Cory, A. F. Fahmy, and T. F. Havel. Nuclear magnetic resonance spectroscopy: an experimentally accessible paradigm for quantum computing. In: Proceedings of the 4th Workshop on Physics and Computation. Boston: New England Complex Systems Institute, 1996. 262. N. Gershenfeld and I. Chuang. Bulk spin resonance quantum computation. Science, 275: p 350, 1997. 263. G. P. Berman, G. D. Doolen, G. V. Lopez, and V. I. Tsifrinovich. Quantum entangled states and quasiclassical dynamics in macroscopic spin systems. 1998. (Online preprint quant-ph/9802015) 264. B. E. Kane. A silicon-based nuclear spin quantum computer. Nature, 393: 133–137, 1998. 265. J. A. Jones, R. H. Hansen and M. Mosca. Logic gates and nuclear magnetic resonance pulse sequences. 1998. Submitted to Journal of Magnetic Resonance. (Online preprint quant-ph/9805070) 266. J. A. Jones, M. Mosca, and R. H. Hansen. Implementation of a quantum search algorithm on a nuclear magnetic resonance quantum computer. Nature, 393: pp 344– 346, 1998. (Online preprint quant-ph/9805069) 267. J. A. Jones. Fast Searches with nuclear magnetic resonance computers. Science, 280: Apr 1998 p 229. 268. J. A. Jones and M. Mosca. Approximate quantum counting on an NMR ensemble quantum computer. Submitted to Physical Review Letters, 1998. 269. J. A. Jones and M. Mosca. Implementation of a quantum algorithm to solve Deutsch’s problem on a nuclear magnetic resonance quantum computer. Journal of Chemical Physics: in press, Aug 1998. (Online preprint quant-ph/9801027) 270. N. Linden, H. Barjat, and R. Freeman. An implementation of the Deutsch–Jozsa algorithm on a three-qubit NMR quantum computer. 1998. (Online preprint quantph/9808039) 271. W. S. Warren. The usefulness if NMR quantum computing. Science, 277: pp 1688– 1689. (See also response by N. Gerenfeld and I. Chuang, ibid, pp 1689–90, 1997) 272. S. E. Barnes. Efﬁcient quantum computing on low temperature spin ensembles. 1998. (Online preprint quant-ph/9804065) 273. E. Knill, I. Chuang, and R. Laﬂamme. Effective pure states for bulk quantum computation. 1997. (Online preprint quant-ph/9706053) 274. L. J. Schulman and U. Vazirani. Scalable NMR quantum computation. 1998. (Online preprint quant-ph/9804060) 275. Zyczkowski, Horodecki, Sanpera, Lewenstein. On the volume of the set of mixed entangled states. 1998. (Online preprint quant-ph/9804024) 276. J. Gea-Banacloche. Minimum energy requirements for quantum computation. The American Physical Society, 89(12): Nov 18, 2002 pp 217901-1–217901-4. 277. M. Ozawa. Conservative Quantum Computing. Physical Review Letters, 89: 057902, 2002. 278. O. Hay and A. Peres. Quantum and classical descriptions of a measuring apparatus. 1997. (Online preprint quant-ph/9712044) 279. W. H. Zurek. Decoherence and the transition from quantum to classical. Physics Today, 44: pp 36–44, 1991.

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4 COMPUTING WITH QUANTUMDOT CELLULAR AUTOMATA Konrad Walus and Graham A. Jullien This chapter describes a promising emerging technology for nanoscale computing based on cellular automata. Rather than relying on the on/off state of a current switch to encode information, this paradigm, called quantum-dot cellular automata (QCA), represents binary information in the electronic conﬁguration of a set of coupled quantum dots, molecules, or magnetic nanoparticles. QCA logic and circuits are implemented by connecting various logic gates using arrays of QCA cells, which also make up the interconnect network. Control over information ﬂow and synchronization, as well as true power gain, is possible by clocking the cells. Using the available building blocks, several circuit examples are provided, together with a description of available computer-aided design tools. This chapter also presents a description of recent experiments and several promising implementations of QCA.

4.1. INTRODUCTION The seemingly endless progress of microelectronics is the result of the ability of the semiconductor industry to continuously scale down the transistor. However, there are challenges to this scaling as the lateral dimensions of transistors approach a few tens of nanometers, and the gate oxides are reduced to just a handful of atoms. These challenges include leakage currents through the gate oxide, the discreteness of impurities, low on/off ratios due to drain induced barrier lowering (DIBL), and very high power dissipation. When scaled down to the level of single molecules, several additional problems emerge. A molecular transistor would require a channel, implemented with a single molecule, and three contacts, most likely implemented with metal. Given the signiﬁcant size difference between the metallic Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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contacts and the molecular channel, it is very difﬁcult to achieve high coupling from the three contacts to the molecular channel. If the source and drain are tightly coupled to the molecule, the gate remains very weakly coupled. As a result, the on/off ratio of the device is very poor. Remember that the current success of the metal-oxide-semiconductor transistor has been due to its nearly ideal properties, which have been maintained in a succession of highly controllable silicon technology advances. Finding a replacement that has all of these features and is also faster and/or cheaper is a formidable task. There has been great research interest in ﬁnding the ‘‘next switch’’ that will replace the current transistor [1], but there have also been alternative proposals to replace the underlying paradigm on which computers operate. One of these paradigms was introduced to the research community in 1993 by C. S. Lent; he published the ﬁrst work on a novel paradigm for computing at the nanoscale that is based on cellular automata, which he called quantum-dot cellular automata (QCA) [2]. Rather than encoding information in the on/off state of a current switch, the QCA paradigm encodes information in the electronic conﬁguration of coupled quantum dots [3–5], metallic islands [6–26], molecules [27–41], or alternatively the magnetization in anisotropic nanomagnets [42, 43]. Information is transmitted and processed via the electrostatic or magnetic exchange interaction between individual QCA cells [44]. The potential advantages of QCA include high device density, high operating speed, and low power dissipation; the degree to which these advantages can be realized depends on the particular choice of physical implementation. The lack of physical connection (at the molecular scale) to each molecule and the fact that no current passes through each molecule makes the paradigm more suitable as a molecular implementation of the switch [27]. The cellular automata computing architecture paradigm has been studied for many years; in fact, John von Neumann, who is credited with inventing the stored program concept for building computers—the concept on which most of today’s computer processors are still based—conceived the ﬁrst cellular automaton in the late 1940s [45]. Cellular automata (CA) are essentially discrete dynamic systems whose behavior is completely speciﬁed in terms of local interactions with adjacent cells. The cell is usually assumed to be a ﬁnite-state machine driven by a central clock that synchronously advances time in all cells in the automata array. The outputs of neighboring cells at a given clock pulse are used, by each cell, to compute the cell’s state following the next clock pulse. Most research has looked at fairly simple cells that can be implemented with little hardware cost. The QCA cell originally introduced by Professor Lent and his colleagues has a very simple structure with only two states provided by the two energetically low-lying electronic conﬁgurations of non-bonding electrons; the process by which electrons move about in the cell is quantum mechanical tunneling. The cell is designed such that these two states are energetically degenerate in the absence of any external inﬂuence. The conﬁguration becomes deterministic under the perturbing inﬂuence of the electronic conﬁguration of adjacent cells. A major feature of the technology (besides having to be built at nanometer scales) is that the logic state of the cell is determined by the position of extra charge in a ﬁxed location on the substrate or

4.3. THE QCA CELL

113

molecule, rather than by the ﬂow of charge in and out of the cell, which is how logic states are changed in standard CMOS-based logic. Since the movement of charge during logic state switching gives rise to most of the power dissipation in modern CMOS logic, QCA technology promises very low power dissipation.

4.2. THE CAD TOOL: QCADesigner When commercial fabrication processes have reached a stage of advancement where any emerging technology is an economic reality, the potential of that technology should already have been explored and uses for the technology found. In fact, this vertical approach may even change the amount of effort spent on developing a technology based on, for example, the uses (or lack of them) found and the fabrication tolerances required. The best way to evaluate a technology is to provide tools for design and simulation and then to make these available to a large group of future designers within that technology. These tools, with sufﬁciently accurate simulation models and computational techniques, are able to predict the level of success of nanocircuit designs, even though such nanotechnology is not available. Throughout this chapter we will be illustrating the design concepts and showing simulation results using the QCA CAD tool, QCADesigner [46]. QCADesigner provides a comprehensive design and layout tool, along with a simulation engines that uses two different quantum mechanical approximations. The tool is currently available as a free download from http://www.qcadesigner.ca/ and provides an excellent vehicle for exploring the concepts discussed here. The various elements of QCADesigner will be introduced, where required, later in the chapter.

4.3. THE QCA CELL QCA computing involves the interaction of many QCA cells, each constructed from a square pattern arrangement of four quantum dots. It is important to note that although initial work on QCA focused on semiconductor quantum dots, recent research has included cells implemented from single molecules [27–41] as well as magnetic nanoparticles [42, 43]. The electronic QCA cell is charged with two mobile nonbonding electrons that repel each other as a result of their mutual Coulombic repulsion, and, occupy one of the two diagonals of the cell in the ground state. These two states are referred to as the ‘‘ACTIVE’’ states and are used to encode binary information as depicted in Figure 4.1. Other higher energy states can be ignored if the energy of those states is sufﬁciently high. The quantum dots can be coupled through a quantum mechanical tunneling barrier that enables the controlled transfer of electrons from one site to another. The cells are typically illustrated in the literature as having a bounding box (shown in Fig. 4.1). This bounding box does not necessarily have a physical structure; it is, rather, used for illustration and design purposes to isolate one cell from the next. Some implementations are based on double dots, two of which are required to

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Polarization = −1 Binary value = 0

Polarization = 1 Binary value = 1

Figure 4.1. QCA cell is constructed from four quantum dots arranged in a square pattern. The two mobile electrons in the cell tend to repel each other and occupy the diagonal sites of the cell. The electronic conﬁguration of the cell is used to encode binary information.

make a single cell, while others employ the cell in its entirety. Figure 4.2 illustrates the numeric indexing normally used to refer to individual dots in a cell. Using this indexing convention, cell polarization is deﬁned as P¼

ðr1 þ r3 Þ ðr2 þ r4 Þ ; r1 þ r2 þ r3 þ r4

where ri is the charge density at dot i. The value of ri represents the average number of electrons occupying dot i [44]. In an isolated cell, the two ACTIVE states will be energetically equivalent and, quantum mechanically, the state of this isolated cell can form a superposition of the two diagonal states. In such a superimposed state, the cell will have no net polarization. An unpolarized cell is said to be in a ‘‘NULL’’ state and the inﬂuence of such a cell does break the energy degeneracy in the neighboring cells; essentially the cell is said to be ‘‘off’’. However, in a four-dot cell such superimposed states only exist if the cell is maintained in coherent isolation; real devices will naturally drop to a random ACTIVE state due to the loss of quantum mechanical coherence to the environment. Therefore, maintaining a stable NULL state in four-dot cells is a difﬁcult technical challenge. In order to overcome the challenges associated with coherent NULL states, recent proposals have included two additional sites that introduce a

4

1

3

2

Figure 4.2. Cell indexing used throughout this chapter.

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Polarization = −1 Binary value = 0

Polarization = 0 Binary value = Null

Polarization = 1 Binary value = 1

Figure 4.3. In the six-dot cell, the two center dots enable a third electronic conﬁguration. In this third conﬁguration, the cell is said to be in the NULL state, in which the cell does not drive adjacent cells to any particular polarization.

third low-lying electronic conﬁguration with no net cell polarization [28, 32], as shown in Figure 4.3. To force the cell into this NULL state, the potential energy of these two sites can be controlled using coupled electrodes, and this ability provides a convenient and potentially more robust mechanism for clocking QCA circuits [22, 28, 32, 47]. Adjacent cells interact via electrostatic coupling—a quadrupole moment established from the nonuniform distribution of cell charge in each ACTIVE cell lowers the energy of one of the two ACTIVE states in neighboring cells, forcing those cells to relax preferentially to one state. The resulting cell-to-cell interaction function is highly nonlinear as shown in Figure 4.4, and the

1

Cell−cell response function

0.8 0.6

Cell polarization

0.4 0.2 0

−1 −0.8 −0.6 −0.4 −0.2 0

0.2

0.4

0.6

0.8

1

−0.2 −0.4 −0.6 −0.8 −1

Driver cell polarization

Figure 4.4. Nonlinear cell–cell response function. The output cell is almost completely polarized for a small polarization of the input cell (bold outline).

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nonlinearity of this response function provides a noise margin, which is essential for signal restoration along lengthy arrays. Because of this interaction, neighboring cells will tend to synchronize their polarization and, as a result, ‘‘wires’’ can be implemented from a linear array of cells.

4.3.1. Kink Energy A full quantum mechanical model of a QCA circuit is computationally intractable. The size of the Hamiltonian matrix grows exponentially and leads to extremely large matrices for even small circuits. Assuming a two-state basis, the size of the Hamiltonian matrix is 2N 2N, where N is the number of cells in the circuit. Various approximations can be made in order to reduce the size of the problem such that it can be solved on a standard computer. The most basic of these approximations is the Hartree approximation, in which the cells are quantum mechanically decoupled, and their interactions are modeled classically through a mean ﬁeld approach. The dynamics of each individual cell are modeled quantum mechanically, but the correlations between cells are ignored and the cell is evolved in the ﬁeld of all other cells, which remain stationary. When modeling the QCA cells in a two-state basis, an important parameter is the interaction coupling between two cells. The Coulombic coupling between two cells can be described by the so called kink energy, Ekink, associated with the energetic cost of two neighboring cells having opposite polarization [44]. The electrostatic interaction between charges in two four-dot cells, m and n, is Em;n ¼

n 4 X 4 qm 1 X i qj n ; 4pe i¼1 j¼1 jrm i rj j

m where qm i is the charge in dot i of cell m, and ri is the position of dot i in cell m. The kink energy is the difference in energy between two cells that have opposite polarization and those same two cells having the same polarization; i.e., kink opposite polarization same polarization ¼ Em;n Em;n : Em;n

Although not shown in Figure 4.1 and Figure 4.3, there are two positive background charges distributed throughout the cell in order to ensure charge neutrality and must also be included in the expression for kink energy. It can be shown that the kink energy decays as the ﬁfth power of the distance between cells. This property is useful in designing circuits that do not suffer from crosstalk. Table 4.1 shows the kink energy for four different cell sizes. The reader should note that the listed dimensions represent the width and height of the cell bounding box within which the cell dots are located (in the center of the four quadrants of the box).

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4.4. GROUND STATE COMPUTING

TAB LE 4 .1 . Kink Energy Between Adjacent Cells Cell Type

Cell Size

Kink Energy

Molecular QCA (er=1) Self-assembled (er=12.9) Lithographically deﬁned (er=12.9) Lithographically deﬁned (er=12.9)

o 2 nm 5 nm 10 nm 20 nm

W0.3 eV 9.13 meV 4.56 meV 2.28 meV

4.3.2. Cell Switching Cell switching involves the change of electronic conﬁguration (polarization) of the cell, as illustrated in Figure 4.5. Switching is driven by the clock and the ﬁnal state is determined by the neighboring cells or possibly unwanted space charges [48]. Depending on the level of kink energy, a cell can be excited into one of the other low lying states by unwanted thermal ﬂuctuations [49, 50]. For this possibility to be avoided, the kink energy should be much larger than the thermal ambient energy, kBT. The attainable switching speed of a QCA circuit depends primarily on the particular choice of implementation. If the system is strongly coupled to the substrate, inelastic processes will dominate and the switching speed will be determined by the strength of the coupling between the cell and the substrate. However, if elastic processes dominate the switching, the switching speed can be determined by modeling the system using the Schro¨dinger equation. Tougaw et al. showed that the standard cell has a switching time as low as 2 ps [51] when operating in this coherent regime. Table 4.2 lists the order of the theoretical cell switching frequencies for different cell implementations reported in the literature.

4.4. GROUND STATE COMPUTING QCA computing has often been referred to as ground state computation since the design of QCA circuits involves ﬁnding a layout of cells where the ground state of the layout for a particular set of boundary conditions provided by the inputs is the solution to the designed logical function. When a suitable environment is

P=1

P=0.5

P=0

P=−0.5

P=−1

Time

Figure 4.5. Cell switching from P=1 to P=1.

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TAB LE 4 .2 . Theoretic Orders of QCA Cell Switching Frequencies. Implementation

Frequency

Molecular [44] Semiconductor [51] Metallic-Island [25] Magnetic [42]

THz THz GHz MHz

provided, the cell will relax to the correct ground state. Changes in the boundary conditions (input values) raise the system energy and cause the system to relax to a new ground state and a new output. Original work on QCA focused on an edgedriven approach where the QCA circuit was provided inputs at the edge of a computational array, thus raising the system energy by introducing kinks at these inputs and allowing the system to relax to the correct ground state [2, 52, 53]. However, this approach limits the size of the circuit, since larger circuits will have a tendency to stick in one of many unwanted metastable states, as illustrated in Figure 4.6. The ability of the circuit to ﬁnd the correct ground state can be enhanced with the application of adiabatic clocking [44].

4.5. CLOCKING As with standard technologies, QCA clocking provides a mechanism for synchronizing information ﬂow through the circuit. However, unlike standard

Application of new input

Energy

Metastable state

Ground state

Correct ground state Time

Figure 4.6. In the edge-driven computation approach, inputs are applied to one side of the circuit and the circuit is allowed to relax. Correct operation requires that the circuit settles to the correct ground state and does not get stuck in a metastable state.

4.5. CLOCKING

119

technologies, which have a set input/output that provides a built-in directionality for information ﬂow, the clock also controls the direction of information ﬂow in a QCA circuit. In addition to this, the clock provides the power gain required for proper circuit operation [54]. By clocking the cells quasi-adiabatically, problematic metastable states can be minimized. Clocking three-state QCA cells (six-dot cells) can be accomplished by modulating the potential of the two central dots of the cell. This applied potential modiﬁes the potential energy of the NULL state. When the NULL state has the lowest energy, the cell will tend to relax to this state. When the clock potential is increased, the energy of the NULL state will be higher than that of the two ACTIVE states and the cell will tend to the ACTIVE state with the lowest potential energy, determined by the perturbation provided by neighboring cells. A mechanism for clocking has also been proposed for a four-dot cell that involves a controlled ability to raise and lower the quantum mechanical tunneling barriers between the dots of the cell, thus forcing the cell into and out of a quantum mechanical superposition of the two ACTIVE states. When the tunneling barriers are high, charges in the cell become localized in one particular electronic conﬁguration; as a result, the cell is said to be latched and the cell will not switch regardless of the inﬂuence of neighboring cells. When the tunneling barriers are low, the electronic wave function becomes delocalized (P=0) and the cell is said to be in the NULL polarization state. There are advantages to building QCA circuit design tools around this particular approach to clocking because the Hamiltonian for each cell can be reduced from three-states (3 3 matrix) to two-states (2 2 matrix). This reduction signiﬁcantly lowers the computational requirements for large circuits. QCADesigner is designed around this model and is therefore capable of simulating fairly large circuits [46].

4.5.1. Zone Clocking With zone clocking, all the cells in a design are grouped into one of four available clocking zones; that is, all the cells in a particular clocking zone are connected to one of the four available phases of the QCA clock, as shown in Figure 4.7 [55]. The successive latching and unlatching of cells connected to the different clock phases acts to pump information throughout the circuit. For example, a wire, which is clocked from left to right with increasing clocking zones, will propagate information in the same direction. As a result, QCA circuits are pipelined at the clocking zone level. This also permits more than one bit of information to be present on a particular wire. QCADesigner has been developed around this particular approach to clocking, and the example circuits presented in this chapter are based on results using this method. Within the zone clocking scheme, each group of cells connected to a particular phase of the clock can be modeled as a D-latch [56]. As each group of cells in a particular clocking zone becomes latched, they retain their information until the clock is relaxed, independent of changes in the polarization of neighboring cells.

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Clock zone 0

Clock zone 1

Clock zone 2

Clock zone 3

Figure 4.7. The four phases of the QCA clock used to control information ﬂow in the QCA circuit.

A length of QCA wire can be represented schematically, as shown in Figure 4.8, where each clock zone is identiﬁed in the layout with a unique shade of gray. This deep (or ﬁne-grained) pipelining has a major effect on the design cost function. Schematics of QCA circuits should include these D-latches to represent the clocking zones, as also shown in Figure 4.8. The deep pipeline inherent in QCA circuits forces us to evaluate our designs differently than we would if we were designing with traditional technologies. Even in heavily pipelined transistor based logic architectures, there will normally be many gates in a combinational structure between each latch in the pipeline. In QCA, the latency is determined completely by the largest number of clocking zones between input and output, with each gate and wire connection being connected to a clocking zone. The original concept of QCA, as a quantum level implementation of classical cellular automata (CA) [2], is evident from the

Information flow

In

In

Out C0

C1

C2

C3

C0

C1

C2

C3

D0

D1

D2

D3

D0

D1

D2

D3

Out

Figure 4.8. QCA wire shown with cells and schematic representation. C0, C1, C2, C3 are the four phases of the clock. Each of the clocking zones maps to a numbered D-latch in the circuit representation and is represented in the layout with a unique shade of grey. Notice that only one clocking zone is latched.

121

4.6. INPUT/OUTPUT INTERFACING

Information flow E

φ1

φ2

φ3

φ4

Figure 4.9. Submerged electrodes can be used to clock QCA cells by applying a forward moving electric ﬁeld at the level of the cells. The ﬁgure is not shown to scale, as many cells can be placed between adjacent electrodes.

inherent clocked operation at the device level. Although CA architectures are not normally implemented in most synchronous digital systems, we can look at structures that have similar properties as being target candidates for QCA implementation. Examples are bit-serial architectures and systolic arrays. Interestingly, parallel designs, which require large fan-outs to the parallel logic components, will introduce more latency because of the very nature of QCA interconnects; thus, we will need to change our computing paradigms to match the different cost functions inherent with using future QCA technology. Signiﬁcant work in these areas remains to be done.

4.5.2. Continuous Clocking A method of clocking molecular QCA using a continuous clocking wave, realized by generating a moving electric ﬁeld by a network of submerged electrodes, has been proposed in references [28, 31, 32]. Clocking networks using carbon nanotubes have been investigated in [57]. The design of three-dimensional molecular QCA cells enables a ﬁeld in the vertical direction to modulate the potential energy between the NULL state and the two ACTIVE states. By applying phase-shifted sinusoidal potentials to each of the electrodes, a forward moving wave can be generated at the level of the cells. Cells are latched at the wavefront of this forward moving wave as illustrated in Figure 4.9. This enables the cells to be clocked without inﬂuencing the cell–cell interactions. This method is also valuable because there is no physical connection between the clocking network and the QCA devices. The number of cells between any two electrodes can be large, allowing the electrodes to be quite large when compared to the individual cells.

4.6. INPUT/OUTPUT INTERFACING Interfacing to QCA circuits requires a technology that can set and detect the electronic conﬁguration, or magnetization in the case of magnetic QCA, of single

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cells. I/O for molecular implementations of QCA is signiﬁcantly more difﬁcult, and there is currently no established method for I/O in these future molecular scale devices. In the case of metallic island and semiconductor QCA, the I/O mechanism is already established using single electron transistors (SETs) for reading the output and electrodes for setting the input [13, 25, 26]. The SET is a highly sensitive electrometer capable of detecting a fraction of the elementary charge present at its gate electrode. SETs operate in the Coulomb blockade regime and generally have to be cooled to extremely low temperatures. Signiﬁcant research has been invested in developing techniques to realize room temperature [58] and high frequency [59] SETs since their application extends beyond sensitive electrometers. Although magnetic QCA is still in the early stages of development, it appears that the I/O mechanism for this implementation is relatively simple to construct. At the input stage, a single wire element, through which a current is passed, provides sufﬁcient magnetization to cause its neighboring MQCA cell to relax to one of the two polarizations [42]. At the output of the circuit a magnetization sensor, based on the giant magnetoresistance (GMR) effect, or a magnetic tunnel junction can be used to detect the magnetization of output cells.

4.7. QCA LOGIC 4.7.1. Inverter The most common inverter design is shown in Figure 4.10. The kink energy between two cells changes sign when the cells are oriented at 451 with respect to each other. The output wire and the two legs of the inverter have this sign-change coupling and the ground state of this device has complementary input and output.

4.7.2. Majority Gate The fundamental logic primitive available with QCA technology is the majority gate. This gate performs the following Boolean function: MajðA; B; CÞ ¼ AB þ AC þ BC:

1

0

Figure 4.10. Layout of a fork inverter. The two arms of the fork reinforce the inverter function by doubling the coupling to the output cells.

123

4.8. FIXED POLARIZATION CELLS

A

A B

M(A,B,C)

B

M(A,B,C)

M

C

C

Figure 4.11. The three-input majority gate is the fundamental logic primitive available with QCA. It is created from a cross pattern of ﬁve cells. At least two of the cells must be logic ‘1’ before the output is logic ‘1.’

At least two of the inputs to the gate must be of the same polarization before the output attains that polarization. This gate is a member of the higher class of threshold gates where the sum of weighted inputs must exceed the threshold before the output switches state [60]. The three-input majority gate is implemented with the layout shown in Figure 4.11. The majority gate can be programmed to perform the standard two-input AND as well as two-input OR operations by ﬁxing the polarization of one of the three available inputs as illustrated in Figure 4.12.

4.8. FIXED POLARIZATION CELLS Fixed polarization cells are required to implement AND and OR functions, as discussed in the previous section. There are two possible methods for realizing B

AB

A

B

A

B

A

A+B

−1

1 B

AB

A

A+B

Figure 4.12. The majority gate as a programmable AND and OR gate. Fixing one of the inputs to logic ‘0’ creates a two-input AND gate. Alternatively, if we ﬁx one of the inputs to logic ‘1’ we obtain a two-input OR gate.

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these cells. The ﬁrst involves a QCA network that distributes a constant polarization to all the AND and OR gates, inverting where necessary. In this case, the ﬁxed polarization is provided as a separate input to the circuit. Only one such input is required. The second approach involves a dot-level manipulation of cells within the circuit or the controlled placement of ﬁxed charges. It is theoretically possible to implement a ﬁxed polarization cell by simply removing two quantum dots from the cell, leaving only the two dots associated with the desired diagonal. The use of ﬁxed polarization rather than a distribution network results in circuits that consume far less area and are not prone to errors associated with the large network required by the ﬁrst approach. Signiﬁcant work remains to be done in this area.

4.9. WIRE CROSSING The majority gate, inverter, and wire are insufﬁcient to design and build a complex QCA circuit. Two other building blocks are required: the fanout and a method of wire crossing. The fanout can be implemented by joining two QCA wires to the same node. The wire crossing represents a far more difﬁcult problem and is still being investigated. In standard technologies, wire crossings are implemented with several layers of metallic interconnects. The situation is quite different for QCA circuits, where such metal layers are will probably not be available and converting between the electronic conﬁguration of QCA cells and voltages in wire interconnects is not practical.

4.9.1. Coplanar Crossover In earlier research, Tougaw et al. proposed an additional type of cell to create a coplanar crossover [61]. The cell is the same size as the standard cell except the dots are rotated by 451 as shown in Figure 4.13, where we also show the information encoding in these rotated cells. As a result of the geometry of these cells, each cell in a wire will relax to the opposite polarization of its nearest neighbors. When placed directly adjacent to one another, rotated and nonrotated cells do not interact with each other, as shown in Figure 4.14a. This lack of interaction is a result of the symmetry between

Binary value = 1 Polarization = 1

Binary value = 0 Polarization = −1

Figure 4.13. 451-rotated QCA cells, showing the deﬁnition of polarization and binary encoding.

125

4.9. WIRE CROSSING

Niether polarization is preferred

0

1

1

0

1

(a)

(b)

Figure 4.14. (a) Because of symmetry, when rotated and nonrotated cells are placed adjacent to one another, they do not interact. (b) Recovering a digital signal from the inverting chain is done by placing regular cells in between two of the rotated cells. We recover either the signal or its inverse, depending on where we tap off the inversion chain.

the two cells; the effect of one cell on the other does not break the energy degeneracy between the polarization of the two cells. To convert a signal from rotated to nonrotated wires the position of nonrotated cells has to be offset by a half-cell, as illustrated in Figure 4.14b. This effect can be exploited to implement wire crossovers. Consider two standard, nonrotated cells placed at a separation of one cell. It is reasonable to assume that the polarization effect of one cell is able to traverse this gap and effectively break the energy degeneracy of the second cell. If we place a wire of rotated cells in between these two cells, this interaction will not be disrupted because of the geometric considerations discussed above. This property allows the coplanar crossover to transmit information independently along the two different cell wires: one wire comprised of regular cells and the other comprised of rotated cells, as illustrated in Figure 4.15. If there is no crosstalk between the two interconnects, a signal is able to propagate across the gap. However, this building block is very sensitive to fabrication variations [62, 63]. Variations in the position of cells or dots in cells of this building block introduce crosstalk between the two interconnects, which quickly dominate its operation. The problem stems from the cell gap between input and output in the non-rotated cell wire. The coupling between the two wires is 1/32 that of adjacent cells and the output wire is essentially ﬂoating.

4.9.2. Coplanar Crossover with Continuous Clocking Blair et al. proposed a new approach to the coplanar crossover that does not involve the use of rotated cells [30]. By using an eight-phase clocking scheme and generating ACTIVE domains that were shorter than the NULL domains, Blair

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1

0

0

1

Figure 4.15. Wires created with rotated and nonrotated cells do not interact. We can exploit this to create coplanar crossovers, if the effect of one cell onto another of the same orientation is able to traverse the gap.

et al. were able to show that the progress of these domains through the junction could be interlaced, as shown in Figure 4.16. Although this building block resolves the problems associated with the previous coplanar crossover and represents the most promising approach to wire crossing, it comes at a signiﬁcant cost associated with the additional area overhead; the requirement for four additional clocking phases; and the extra complexity associated with the clock timing.

4.9.3. Multilayer Crossover Previous work has examined the possibility of building multilayer QCA [64]. The use of multilayer QCA is quite attractive as a means of wire crossing but it also introduces the possibility of a 3D computer since it is quite reasonable to assume that the additional layers could perform logical functions. The application of multilayer networks as a means of signal crossing was ﬁrst explored in [62]. Many of the circuits presented later in this chapter use this approach to achieve signal crossing. Using these multilayer QCA cells, we can effectively cross signals over on another layer; such a technique has been simulated to show signiﬁcantly less sensitivity to cell displacements [63]. Using this method, multilayer QCA circuits can potentially consume much less area than planar circuits (Figure 4.17). This building block has area and displacement tolerance advantages. However, the physical realization of this building block is technically very challenging and it is difﬁcult to predict whether such a multilayer QCA technology will be feasible in the future.

127

(b)

(a)

0

x (nm)

−100

x(nm)

−500 −500 −400 −300 −200

500

−500 −500 −400 −300 −200 −100 400

−400

−400 300

−300

−300

0

100

200

−200

200

1

−200

100

0.5 1/T

300

400

500

−100

0

−1 0

0

Clock waveform

−100

0

100

200

300

400

1

Figure 4.16. Using an eight-phase clocking network, coplanar crossover is possible by timing the information ﬂow across a crossover point [30]. Reprinted with permission from E.P. Blair.

y(nm)

500

y (nm)

100

200

300

400 500

128

CHAPTER 4: COMPUTING WITH QUANTUM- DOT CELLULAR AUTOMATA

Normal input

Crossover input

Crossover output

Normal output

Figure 4.17. A multilayer crossover. Cells shown with an ‘‘X’’ are located on higher layers; cells shown with ‘‘O’’ are vertically stacked to produce a via.

4.10. QCADesigner: SIMULATION ENGINES Simulation engines within QCADesigner model the static and dynamic behavior of QCA operation. Although two simulation engines are currently included with the tool, other groups are free to incorporate their own simulation engines since the source code for the tool is made available. Work on a new simulation engine tailored for continuously clocked molecular QCA has been started [65]. However, much work remains to be completed. Models that described the static and dynamic behavior of electronic QCA have been reported in [47, 51, 54, 67, 68]. In general, quantum mechanical systems are not suitable for efﬁcient simulation on a classical computer, and the models are approximations of the full quantum mechanical behavior of the system. Included in the current version of QCADesigner are two different simulation engines: the bistable and the coherence vector engines. The bistable engine is based on the simplest model and is very fast. There are several key assumptions made by this model. The ﬁrst is the two-state approximation, which ignores higher energy conﬁgurations of the cell. The second is the Hartree approximation, which quantum mechanically decouples the cells, ignoring the intercellular correlations and reducing the size of the matrices involved. The last is that the cells remain at the ground state, no time-dependant dynamics are considered. The second simulation engine is based on the coherence vector formalism, a model that is able to model the dynamics of the cells in the presence of coupling to the substrate. This engine is also based on the two-state cell and uses the Hartree approximation to decouple the correlations between cells. The main challenge in implementing physically accurate simulations is the lack of experimental data for the various QCA implementations. Even though several small QCA systems have been developed as proof-of-concept experiments [9, 10, 12, 20–22], these early devices do not necessarily represent scalable QCA

129

4.11. EXAMPLE CIRCUIT DESIGNS

technology. As a result, one of the main objectives of this effort is to provide motivation for further research into the implementation of such devices and development of a continued dialog between circuit designers and researchers investigating these implementations.

4.11. EXAMPLE CIRCUIT DESIGNS The following sections describe a relatively small subset of the many circuit designs that have been already been reported in the literature. The design and layout of these example circuits has been done manually. Early work on the automatic placement and routing of QCA circuits has also been reported [69–71], as well as early work on minimizing the overall hardware requirements through majority minimization techniques [60, 72, 73].

4.11.1. QCA Addition Of the variety of information processing tasks that computers perform, the most basic is certainly the addition of two single digit binary numbers. References [56, 74] investigate the design and layout of a QCA full adder, using QCADesigner, in more detail. The schematic and layout for the full adder are shown in Figure 4.18. It should be noted that these layouts represent a snapshot of the circuit in operation, which is why only one of the clocking phases has cells that are latched. The apparent underutilization of space in this layout is a result of design requirements that attempt to minimize the crosstalk between different parts of the QCA circuit. The simulation results for this adder are shown in Figure 4.19. The delay between the application of the input and the appearance of the associated output is due to the inherent delay in the circuit. Figure 4.18 shows the four clocking zones (1 clock cycle) between the input and output. A QCA ripple-carry adder is implemented by cascading n 1-bit QCA full adders. The schematic for a 4-bit adder is shown in Figure 4.20. As the inputs

M

D1

D2

D1

D2

M

D3

Sum Sum

M

D1

D2

D3

Carry Carry

D0

D0

D0

Cin

A

B

Cin

A

B

Figure 4.18. Schematic and layout of a majority-based full adder.

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Simulation results Sum

1

0

1

1

0

1

0

0

1

Cout

0

0

0

0

1

0

1

1

1

B

A

Cin

0

1

0

0

1

0

1

1

0

0

1

1

1

0

0

0

0

Figure 4.19. Simulation results for the full adder.

increase in signiﬁcance, a larger number of clock cycles are introduced in order to synchronize the arrival of the input with the carry of the preceding adder. The layout of the 4-bit adder is shown in Figure 4.21. The overall latency can be obtained by considering the critical path from one of the inputs of the 1st adder to the carry output of the nth adder. Since the carry output of a QCA full adder requires 1 clock cycle to complete, the overall latency for the n-bit adder will be n clock cycles. The advantage of the QCA adder is that it is inherently pipelined. As a result, we can feed new inputs into the adder every clock cycle. When the pipeline is full, a new output will be available every clock cycle independent of the depth of the pipeline. An n-bit QCA carry-look-ahead adder can be expressed as Ci ¼ Gi þ Pi Gi1 þ Pi Pi1 Gi2 þ þ Pi P1 C0 ¼ Gi þ Pi ðGi1 þ Pi1 ð þ ðG1 þ P1 C0 ÞÞÞ Si ¼ Ci1 Pi Ci1 Pi þ Ci1 Pi ; where Gi ¼ Ai Bi ; Pi ¼ Ai Bi ¼ Ai Bi þ Ai Bi : Due to the limitation of QCA to two-input AND and OR gates, the critical path of a 4-bit carry-look-ahead adder consists of 10 majority gates as shown in Figure 4.22. Therefore, the best case latency of this architecture is estimated at ﬁve clock cycles.

131

D1

D2

D3

D0

D2

D1

D1

D0

D0

D0

D0

D0

D3

D3

D3

D3

D3

A2

B2

A3

B3

D2

D2

D1

D1

D3

D3

D3

D3

D3 D3

D2 D2 D2 D2

D1 D1 D1 D1

D0 D0 D0 D0

M

M

D1

D1

D1 D2

D0

D0

D2

D2 M

D3

D1

D1

D3

D0

D2

D2

D3 D3

D0 D0

D1

D0

D3

D2

D1 D1

D0 D0

D3

D2

Figure 4.20. Schematic of a 4-bit QCA ripple-carry adder.

D2

D1

D2

D2

D1

D0

D3

D3 D3

M

D3 D3

D0

D3

D3 D3

D3

M

D1

D0

D0 D0

D2

D2

D1

D0

D0 D0

D1

M

D2

D3

D0 D0

M

D3 D1

M

D2

B1

D0

D1

D2

D1

D1

D2

A1

B0

A0

−1

M

D1

D0

M

M

D2

D1

D1

D1

D2

D2

D2

D2

D2

M

D3

D3

D3

D3

D3

Sum0

Carry

Sum3

D0

Sum2 D0

Sum1 D0

D0

D0

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CHAPTER 4: COMPUTING WITH QUANTUM- DOT CELLULAR AUTOMATA

Sum0 Sum1 Sum2 Sum3 −1.00

Cout

A0 B0 A1 B1 A2 B2 A3 B3

Figure 4.21. Layout of a 4-bit QCA ripple-carry adder.

In an actual layout, the latency may be larger because the long interconnects associated with the most signiﬁcant carries would have to be divided into more than one clocking zone. The advantages of carry-look-ahead adders are dependent on the ability to realize AND and OR gates with more than two inputs. A ripplecarry adder is considered the slowest bit-parallel adder design in CMOS circuits. However, the QCA ripple-carry adder has better performance when compared to both the QCA carry-look-ahead and carry-select adder designs because of the inherent pipelining associated with QCA technology.

4.11.2. QCA Multiplication A constant coefﬁcient multiplier has been implemented using the adders described above [56]. The block schematic for a 2-bit multiplier is shown in Figure 4.23. The

A1 B1 A1 B1

P1 C0

Critical path P4 G1

P2

G2

P3

G3

P4

S4

G4

C4

Figure 4.22. Critical path of a 4-bit QCA carry-lookahead adder from the input of the ﬁrst bit to the carry output C4 or the sum output S4.

133

4.11. EXAMPLE CIRCUIT DESIGNS

D

D

D

FA

0

Pi

FA

Ai B1

B0

Figure 4.23. Block schematic of bit-serial multiplier.

D-latches in this schematic are required for the proper operation of the device and are not QCA zone latches. In order to map this design into a QCA circuit, we have to realize that many more D-latches are introduced from the very nature of the QCA circuit. The D-latch between the two adder blocks in the original schematic (Fig. 4.23), is implemented in QCA by adding four additional clocking zones (one clock cycle) along that path. One of the inputs to the multiplier is serially connected across the multiplier circuit; the other is constant and implemented using ﬁxed polarization cells. The schematic for this multiplier is shown in Figure 4.24. The overall latency for the

D3

D3

D0

M

D1

D2

M

D1

D2

M

D0

D3

M

D1

D2

M

D1

D2

D1

D2

D0 D1 D0

Ai

D1 D2

D3

D0

D0

D3 M

D3 M

−1

D2

D0

D2 −1 D2

D2 −1 D2

D1

D2

D3

D0

D1

D1

D1

B1

B0

Figure 4.24. Schematic of QCA bit-serial multiplier.

M

D3

Pi

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CHAPTER 4: COMPUTING WITH QUANTUM- DOT CELLULAR AUTOMATA

Pi Output is LSB first −1.00

−1.00

−1.00

Ai Input is LSB first B1

B0

Figure 4.25. Layout of QCA bit-serial multiplier.

multiplier is three clock cycles: one clock cycle inherent to each adder and one to implement the latch between them. The QCA layout for the multiplier is shown in Figure 4.25. The schematic is drawn to match the layout as much as possible, and the multiplier can be easily scaled by adding full adder blocks and partial product generators. We have experimented with designs as large as 32-bit using this layout. The size of the multiplier grows linearly with the number of bits, making it efﬁcient in area. The latency also increases according to L ¼ 2n 1; where the latency, L, is measured in clock cycles, and n is the size of the multiplier in input bits.

4.11.3. Memory Zone clocking creates a shift register with each wire of clocked cells. However, each cell is connected to a clock signal that will clear the cell contents once every clock cycle. To correct for this loss of data, small loops can be used to retain information and implement memory. The simplest memory loop consists of all four clocking zones, enabling the information to continuously circulate in the loop. A similar approach using continuous clocking has been proposed by Blair et al. [30]. Figure 4.26 shows a QCA memory loop without any mechanism for reading or writing information.

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D1

D2

Memory

D0

Memory

D3

Figure 4.26. The most basic memory element in QCA is the loop. As each of the clocks latch and unlatch they circulate information around the loop.

4.11.4. Memory Cell Extra control can be added to the memory loop to create a memory cell. The memory cell is a building block of random access memory (RAM) and implements a bit-level read/write function [75]. The QCA memory is volatile, and all stored information will be lost when the power to the circuit is disconnected. In order to control the function of this memory cell, we introduce two controls and one input. The ﬁrst control wire, called the Row Select, serves to enable the memory cell to be used in a larger memory grid. The second control, called the Read/Write, selects the present operation to be performed on the memory. A schematic representation of the loop memory cell is shown in Figure 4.27. The associated QCA circuit layout is shown in Figure 4.28. This layout attempts to maximize the application of the memory cell to larger memories, by running the Row Select and Read/Write control wires through the entire length of the cell. In this way, a row of memory can be created by simply laying out these cells in a linear array and extending the control wires to each of the cells.

Row select

D0 D1 −1

D1 D0

Input

D0

D1

D2

−1

D2

M

D3

D1

D1

D2

M −1

−1

1 D3

M Read/write

M

M

−1

D2

M

D2

D0

Figure 4.27. Schematic of the 1-bit memory cell.

D3

Output

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Memory loop Row select

mem

−1.00

−1.00 1.00

−1.00

Input

Output

−1.00

−1.00

Read/write

Figure 4.28. QCA layout of the memory cell.

The stored memory value is constantly circulated inside the memory loop until the Read/Write and Row Select wires are polarized to logic ‘1’, at which time the incoming input is fed into the memory loop and circulated. If the Row Select is polarized to logic ‘1’, and the ‘Write/Read’ is polarized to ‘0’, the current memory value inside the loop is fed to the output. If the Row Select is polarized to logic ‘0’, then the memory cell will always polarize the output cell to logic ‘0’. Simulation results for the memory cells are shown in Figure 4.29. Interestingly, the use of

Simulation results Mem

0

Output

0

0

Input

0

0

0

1

0

0

1

Read/write

0

1

Row select

0

1

0

1

0

0

0

0

0

1

1

Write 1

Figure 4.29. Simulation results for the memory cell.

0

0 Read 1

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circulating memory storage is not a new concept and can be traced back to at least the mercury delay lines that were used to implement storage in the commercial tube computers of the 1950s.

4.11.5. 4-bit Processor A simple 4-bit processor, designed using QCADesigner, has been reported in [76]. This processor was designed mainly as a proof-of-concept to demonstrate that reasonably complex architectures are possible to build using QCA technology, as well as to create a platform for investigating the inherent zone level pipelining. This circuit is intended to demonstrate the level of complexity that can be handled by QCADesigner, not as a demonstration of the ideal architecture for computing using QCA technology. Such architectures are still being developed. The processor is limited to operate on instructions fed into the circuit directly at the inputs; no program memory is used. The design incorporates a 4 4 random access memory (RAM) to provide temporary storage. The design is based on a simple accumulator architecture shown in Figure 4.30. Basic arithmetic and logic operations are implemented in the arithmetic logic unit (ALU). This ALU is built by extending the 4-bit adder. The ALU layout can be seen in Figure 4.31. An input to the ALU requires 11 clock cycles (44 consecutive clock zones) to propagate through the entire unit. Due to the natural pipelining introduced by the clocking, a new input can be applied to the ALU in each consecutive clock cycle, allowing 11 operations to be in the pipeline at any one time. 4 4

0 1

B

Ins [8-5]

A ALU

Dataout Ins [4] 4

4x4-bit memory

4 Ins [9] ALUOp (Ins [3-1])

Accumulator

Ins [8-7]

Acc

R/W Address Datain

10 4

Instruction [9-0]

Figure 4.30. Processor architecture.

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Figure 4.31. The 4-bit QCA ALU. The inputs arrive at the lower left corner, and the outputs are read at the upper right.

In order to provide the processor with data loading and storing capabilities, four 4-bit registers act as physical memory. Instructions are available to store the current accumulator value into any register, and similarly load the contents of any register into the accumulator for computations using the ALU. Figure 4.32 shows the memory layout. It takes four clock cycles for data to be stored in a register, and ﬁve clock cycles for data to be available at the output. However, as discussed above, this reduces to one read or write operation per clock cycle in the steady state. The feed-through path, i.e., write then immediately read, consumes only six clock cycles since the read operation is not required to wait for the write to complete.

Figure 4.32. The 4 4-bit memory block. Data enters the block at the lower left, along with the register address and read/write signal. The data is then made available at the upper right.

4.11. EXAMPLE CIRCUIT DESIGNS

139

Figure 4.33. QCA layout of the 4-bit processor.

The accumulator is implemented using a 2:1 multiplexer with outputs fed back into one of the two input channels. The Select control enables the accumulation of the present ALU output. The propagation path in the feedback loop has a two clock cycle pipeline allowing for the accumulation of two values. These two values, however, are accessible every second clock cycle. Figure 4.33 shows the layout of the complete QCA processor. Each component of the processor, including the interconnect between components, has some latency associated with it, creating a systemwide pipeline. The number of pipeline stages for each component of the processor is shown in Figure 4.34. In order to eliminate the controller logic for this simple design, we have taken advantage of this inherent pipelining. Our instructions contain control bits that determine how each of the processor components handles the arguments associated with that instruction. The control data is distributed to each of the processor components through a set of interconnects, which are clocked such that the control signals arrive synchronously, with the associated argument, to each of the processor blocks. This design was successfully simulated using QCADesigner running on an Intel Pentium 4 computer system with 2GB of RAM. The simulation performed

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1 2 11 1 6 1

3 1

2

Figure 4.34. Number of clock cycles through each stage of the processor.

the addition of two pieces of data, where the result of the addition was written back to the internal memory. The total simulation time to perform this operation was approximately ﬁve hours on the Pentium computer using a time-independent simulation engine. In order to improve simulation performance, signiﬁcant effort is being invested in optimizing the available simulation engines, including the use of multiprocessor computing clusters.

4.12. QCA FABRICATION To date, QCA is a commercially unrealized technology. However, several experimental devices have been fabricated and are described in more detail in this section. The different proposed implementations attempt to realize the required bistable and locally interacting behavior required by the QCA paradigm. Of all the implementations, four distinct classes of QCA implementations have emerged and are listed below.

Semiconductor [3–5, 77–79] Metal-Island [6, 7, 9–14, 16–26, 55] Magnetic [42, 43, 80] Molecular [27–35, 37–41, 81]

4.12.1. Semiconductor QCA Room temperature QCA requires cells that are approximately 1–5 nm. Semiclassical modeling of QCA cells shows that cells made any larger would be limited to temperatures in the mK range [49, 50, 82]. Self-assembly of the quantum dots offers a promising route to fabricating room temperature QCA; however, the required homogeneity in quantum dot size and placement accuracy is not yet at a

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141

level that would support QCA technology [79]. As a result, very limited experimental results are available for this particular implementation of QCA. One of the advantages of using semiconductor QCA is that it is based on materials that are well understood and many fabrication techniques have been created to work with them. As well, there is a large economic beneﬁt to using a material system for which signiﬁcant infrastructure already exists. Gardelis et al. demonstrated polarization transfer into and out of a QCA cell deﬁned with metallic gates patterned on top of a 2-dimensional electron gas (2DEG) in AlGaAs/GaAs [78]. The experiment was performed in a dilution refrigerator operating at 100 mK. The use of 2DEG for implementing QCA is limited and a scalable implementation using this method is most likely not possible. In addition, the tolerance to fabrication variations appears to be too sensitive for any practical application. However, such devices can be fabricated using available techniques and are providing a valuable experimental platform to study the fundamental physics of QCA operation.

4.12.2. Magnetic QCA Recently, signiﬁcant research effort has been put into the implementation of magnetic QCA (MQCA) based on the interactions of magnetic nanoparticles [42, 43, 80]. The magnetization vector of these nanoparticles is analogous to the polarization vector in electronic QCA, and information is propagated via magnetic exchange interactions as opposed to electrostatic coupling in all other reported implementations. Although this technology is referred to as magnetic quantum-dot cellular automata, the term quantum in this case represents the quantum mechanical nature of the exchange interaction. One of the immediate advantages of considering such a technology is that MQCA cells can operate at room temperature, even for large device features on the order of a few hundred nanometers. A potential application of such a technology would be to implement processing-in-memory where the QCA circuit can be used to implement both the information processing and storage elements, potentially eliminating the need for a read/write head, as required by conventional hard disk drives, or the interconnects required by MRAM devices. The read/write operation would be performed at the edges of a MQCA array and the information would be processed and propagated inwards by the coupled magnetic ﬁeld exchange interactions. Contrary to the layout pattern of magnetic storage elements of an MRAM, where the elements are created such that there is very little interaction between them, the MQCA cells are designed to interact in order to enable information processing. Because these exchange interactions are similar to electronic QCA, the MQCA cells would also be able to perform computational tasks using majority functions. One of the drawbacks to using MQCA as a general computing platform is the low operating speed; studies report switching frequency estimates at around 100 MHz [43]. However, it is expected that the MQCA circuits will operate with a much higher tolerance to displacement and rotational defects than the electronic QCA. The QCA wires fabricated in [43] operated properly for

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wires of lengths between 10 and 20 cells long. It is indicated that the number of nanomagnets that can be clocked with a single phase is limited and that a multiphase clocking scheme similar to that used in electronic QCA will be required for a large-scale implementation of MQCA circuits.

4.12.3. Metallic-Island QCA The metallic-island implementation was the ﬁrst experimental realization of QCA [6, 7, 9–14, 16–26, 55]. In all these prototypical devices, the metal islands are used to replace the semiconductor quantum dots. These experiments demonstrated that single-electron tunneling between two Al metallic islands coupled with tunnel junctions would encourage single-electron tunneling in the opposite direction in two adjacent coupled metal islands, realizing this bistable behavior. This idea has been extended to majority gates and short shift registers. The advantage of this implementation is that quantized electron tunneling between metal islands could be observed for large device sizes that are relatively easily fabricated using established electron beam lithography (EBL) techniques. The schematic representation of a metal island QCA cell is shown in Figure 4.35. The cell consists of four metallic islands grouped into two sets of double-dots. The two metallic islands that make up a single double-dot are coupled to each other through tunneling junctions. The two double-dots are then coupled to each other with capacitors increasing the interactions between the two double-dots in order to enhance the bistable behavior of the cell. The devices operate in the so called Coulomb Blockade regime. The island capacitance C is a parameter that determines the device operating temperature and is dominated by the capacitance of the tunnel junctions connecting the metallic island to the external electrodes and adjacent islands. Due to the relatively

Coupling capacitor

−

−

+

+

Previous cell

Tunneling junction

Next cell

+

+

−

−

Metal island

Figure 4.35. Schematic representation of a metal-island QCA cell. The two vertically stacked metal islands are coupled through tunnel junctions, which enable the quantum mechanical switching of the cell.

4.12. QCA FABRICATION

143

large area of the tunnel junctions, the devices require operating temperatures lower than 15 mK. To achieve such low temperatures in the experiments, the devices required cooling via a dilution refrigerator. At these temperatures the charging energy is much higher than the thermal ambient energy kBT facilitating the precise control over single electron charging of the metal island. Under the appropriate bias, a small change in the input can cause single electron transfer between islands, and this change in charge will cause a similar effect in the neighboring double-dot. However, due to the precise biasing requirements, each cell has several external connections and it is therefore difﬁcult to scale this implementation of QCA to much more complex circuits. The metal islands that make up the quantum dots are tightly coupled to the substrate or heat bath. As a result, the time evolution of the cell is not quantum mechanically coherent and can be modeled using semiclassical descriptions. Unlike the semiconductor implementation, the metal islands are ﬁlled with many conduction band electrons, and QCA operation is veriﬁed by observing the change of charge rather than the total charge at a particular site. Electron tunneling is the only nonclassical phenomenon in the metal-island implementation.

4.12.4. Molecular QCA Developing cells using molecules represents a very promising approach to implementing QCA. Molecular QCA has the potential for room temperature operation, high device density, and high operating speed [27]. Room temperature operation is possible as a result of the high kink energies of molecular cells [53]. In theory, molecular implementations could also be fabricated with much higher uniformity than those achievable with semiconductor or metallic-island implementations [31]. Estimates using 1 nm2 QCA cells indicate that molecular QCA could reach densities of 1014 devices/cm2 [29]. However, one has to be careful when making a direct comparison of the functional capability of a QCA circuit with this density to a transistor circuit of the same density since the contribution of each QCA cell to the overall functionality is far lower than that of a transistor circuit as a majority of the cells are consumed in the interconnect network between logic gates. Although the cell density can be very high, recent research on QCA clocking is progressing towards relatively low density circuits as a result of the large area consumed in the crossovers [31]. Quantum mechanical analysis of QCA dynamics has predicted cell switching times as low as 2 ps per cell resulting in the possibility of THz operation [51]. It is not clear if the clocking network itself could operate at such high speeds and the limits to QCA operating speed could end up being determined by the clocking implementation rather than the cell dynamics. Initial research into molecular QCA has focused on bistable mixed valence compounds similar to those ﬁrst developed by Aviram [83] and Hush et al. [84]. These molecules consist of multiple redox centers, where each center can be reduced (gain an electron) or can be oxidized (lose an electron) [32]. The Aviram molecule consists of two allyl groups connected by a butyl bridging ligand. One of the allyl groups is a neutral radical, while the other is a cation. The unpaired

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electron forming the neutral radical can be transferred from one end group to the other without signiﬁcant change to the molecular geometry. The sigma bridge separating the allyl groups provides a potential barrier and enables the measurable bistability of the molecule. The application of an electric ﬁeld will cause the molecule to exhibit a change in the electronic conﬁguration from donor-bridgeacceptor to acceptor-bridge-donor. The change in conﬁguration can result from either electron or hole transfer in the molecule. In order to construct a molecular implementation of a QCA cell, a molecule that exhibits bistability and charge localization is required. Lent et al. [33] analyzed the performance of the Aviram molecule (1,4-diallyl butane radical cation shown in Fig. 4.36) as a test bed for molecular QCA. Ab initio calculations were performed with Gaussian 98 and the unrestricted Hartree–Fock theory (UHF) and the Slater Type Orbitals simulated by the 3 Gaussians (STO-3G) basis set. Figure 4.36 shows the highest occupied molecular orbitals (HOMOs) and the isopotential surfaces for two neighboring molecules. Lent et al. also demonstrated that these molecules could be used to implement majority gates and wires. Although the molecule was found to exhibit nonlinear bistability, charge localization, and molecule–molecule interactions necessary for information transmission, other necessary features such as a mechanism for I/O and a functional group for attachment to a substrate were not designed into this molecule. Molecular QCA was also shown to exhibit a second level of nonlinearity as a result of the coupling between electronic and nuclear degrees of freedom. This

Figure 4.36. The HOMO levels (a) and (c) and isopotential sufraces (b) and (d) for the two stable states of a pair of QCA molecules studied in [33]. Reprinted with permission from [33]. (r 2003 American Chemical Society)

4.12. QCA FABRICATION

145

coupling acts to stabilize the molecule in a particular polarization and ensure that once the cell is polarized it will require an outside inﬂuence to force a change [33]. This second level of nonlinearity is not present in the other implementations. Lent et al. also point out that the kink energy in a molecular cell can be reasonably approximated with simple electrostatic calculations. For the molecular system described here, the kink energy was calculated to be 646 meV. In order to enable the molecular QCA cells to be clocked, a third stable state is required. The molecular geometry described above was extended to include an additional allyl group and permits the molecule to have a third stable state [32]. In this molecule, alkyl bridges in a ‘‘V’’ shaped molecule connect 3-allyl groups (the dots). This ‘‘V’’ shape permits the use of a vertically aligned electric ﬁeld to induce a potential difference between the upper sites (the two ends of the V) and the lower site (the vertex of the V). This potential difference can be used to clock the cell— when the potential of the lower dot is lower than the potential of the upper dots, the cell will go into the NULL state. The group is considered a molecular cation, with two neutral allyl groups and one positive allyl group. In this case it is the positive charge that is transferred between the different dots. The molecule in the three stable conﬁgurations is shown in Figure 4.37.

Figure 4.37. Three stable conﬁgurations of ‘‘V’’-shaped QCA molecule [32]. Isopotential surfaces are shown on the left hand side and a schematic representation of the cell on the right. Reprinted with permission from [32]. (r 2003 IEEE)

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The molecule requires a vertical ﬁeld of 1.3 V/nm to switch from the NULL state (molecule is normally off) on one of the two active states. The state to which it is switched depends on the presence of perturbing ﬁelds (in this case, produced by a point charge a single cell distance away from the two molecules). The molecule was found to have the necessary nonlinear response function to enable QCA computing. As with the initial work, this molecule was also used as a test bed and does not have the necessary structure required for attachment to the substrate. Signiﬁcant work has also been completed with synthesized molecular QCA. Lieberman et al. have experimented with the application of the Creutz–Taube ion as a QCA cell [29]. This mixed valence compound was reported to have the necessary properties to implement a QCA cell; however, there were signiﬁcant challenges with associated counterions binding to the substrate. Earlier research has shown that QCA is highly sensitive to space charges [48]; counterions on the surface close to cells can cause the cells to latch to a ﬁxed polarization, preventing any signal propagation along that particular path. Additional work to demonstrate a surface bound QCA cell with vertical alignment was reported by Qi et al. [34]. In this work, they successfully demonstrated a vertically aligned dinuclear Ru-Fe mixed-valence compound that has been functionalized for attachment onto Si. The change of electronic conﬁguration from RuIII-FeII to RuII-FeIII, resulting from an applied vertical electric ﬁeld, was measured using an AC capacitance technique. A control experiment using the inactive RuII-FeII compound showed no measurable change in the capacitance. The transition from one conﬁguration to the other was detected as a peak in the measured AC capacitance at 1 MHz, which occurred when there was energy level alignment between the Ru and Fe centers. As these levels become aligned, the induced dipole is able to be ﬂipped with an applied AC ﬁeld; this results in an increase in AC capacitance. The ﬂipping is a result of electron transfer between the metal centers and is representative of double-dot QCA action. The capacitance of the ﬁlm was measured using a mercury probe. It is also signiﬁcant that this molecule was bound to the silicon surface; this is a key step toward a ﬁnal implementation of molecular QCA. To do this the mixedvalence compound was functionalized with an amine group that was subsequently bonded to the Si. The process involved termination of a Si(111) surface with chlorine. A reaction between the Si-Cl surface and the NH2 functional group results in a strong covalent Si-N bond. The group also showed that the addition of the amine functional group did not signiﬁcantly alter the properties of the mixed valence compound. First attempts to attach and pattern molecular QCA circuits were reported by Lieberman et al. [29]. A self-assembled monolayer (SAM) of octadecyl trichlorosilane (OTS) was grown on SiO2. When exposed to a high-energy electron beam, the OTS was shown to become more hydrophilic (contact angle changed from 1101 to 801). Using the electron beam system, the group was able to pattern lines 30 nm wide in the OTS SAM structure. Three functionally terminated SAMs were used to test the binding of their test QCA molecule onto the SAM. The ﬁrst was a phosphonateterminated surface (contact angle o301), the second a hydroxyl-terminated surface

4.13. CONCLUSIONS

147

(contact angle 35–521), and the third a methyl-terminated surface (contact angle 105–1101). It was found that the test molecule formed a self-limiting monolayer on the phosphonate and hydroxyl-terminated surface, but no such layer formed on the methyl-terminated surface; this suggests that patterned changes in the hydrophobicity of a SAM could be used to create patterns of molecular QCA. One of the challenges with this approach is the resolution limits associated with using the EBL process (around 10 nm), as well as the challenges to using such a serial patterning approach for mass production of such devices. Line widths of 30 nm would create QCA wires that are many cells wide; interestingly, however, wide QCA wires have been suggested as a way of increasing the fault tolerance of QCA circuits [85]. Recent work by Hu et al. has developed the use of DNA rafts self-assembled on an e-beam patterned PMMA surface [36]. This combination of lithography and self-assembly appears to be very promising; however, much more work remains to be done. Many exciting results have been achieved toward an implementation of molecular QCA, but many challenges to the implementation of a molecular QCA technology still remain. The placement and patterning of individual molecules is a very difﬁcult challenge; in addition, the implementation of a mechanism to measure the electronic conﬁguration of individual molecules, to provide a means of implementing I/O, still remains to be solved.

4.13. CONCLUSIONS Emerging nanotechnologies that are being explored as additions to and replacements of current FET-based fabrication technologies may allow us to continue along the Moore’s Law exponential path and provide the anticipated increases in circuit density that drive many advancements of our technological society. Several promising emerging technologies have already been identiﬁed and others will undoubtedly appear over the next decade or so. Whichever technologies prove to be successful replacements, and there may be several that are ﬁnally used in a mixed technology scenario, will need to be explored thoroughly in a sophisticated design and simulation environment. This chapter has focused on the promising nanotechnology of quantum cellular automata (QCA). Our exploration has covered the basic theory of QCA including a variety of cellular architectures, logic elements, memory cells, and processor structures that have been designed and simulated using the QCADesigner tool. We have covered the proposed approaches to clocking QCA cells and circuits and provided the advantages and disadvantages of each approach. We have also provided a round up of the most promising approaches to QCA implementation including semiconductor, magnetic, metal-island, and molecular QCA. QCA remains an uncommercialized technology; this is primarily due to the challenges with realizing a scalable implementation. However, advantages such as low power dissipation, high device density, and the lack of required connection to each device make QCA a more suitable paradigm for computing at the molecular

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scale. As technology limits are being reached, it may be such disruptive technologies that enable us to build the future generations of computer technology.

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5 DIELECTROPHORETIC ARCHITECTURES Alexander D. Wissner-Gross Electric programmability has been the basis for decades of advances in integrated computer component performance. However, once fabricated or assembled, such components—whether blade servers in a data center or microprocessors on a circuit board—are typically stuck in place and require human intervention for reconﬁguration, removal, or replacement. For continued advances at the architectural level, mechanical programmability of components may also be needed. One generally promising approach for electromechanical manipulation at the nanoscale and microscale is dielectrophoresis, or the net force experienced by a neutral dielectric object in a nonuniform electric ﬁeld. In this chapter, we review recent advances in dielectrophoretic architectures for computation, focusing particularly on the experimental demonstration of fully reconﬁgurable nanowire interconnects. Programmability in electronic systems originates from the ability to form and reform nonvolatile connections. Devices in modern programmable architectures typically derive this ability from controlled internal changes in material composition or charge distribution [1]. However, for ‘‘bottom-up’’ nanoelectronic systems it may be advantageous to derive programmability not only from internal state, but also from the mechanical manipulation of mobile components. Proposed applications that require component mobility include neuromorphic networks of nanostructure-based artiﬁcial synapses [2], breadboards for rapid prototyping of nanodevice circuits [3, 4], and fault-tolerant logic in which broken subsystems are replaced automatically from a reservoir [5]. In this chapter, we review recent advances in dielectrophoretic architectures for enabling such computational component mobility, focusing particularly on the experimental demonstration of fully reconﬁgurable nanowire interconnects—the simplest nanoelectronic components.

Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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5.1. INTRODUCTION TO DIELECTROPHORESIS Let us ﬁrst begin with a discussion of the phenomenon of dielectrophoresis itself. Following Pohl’s seminal work on the subject [6], we ﬁrst calculate the strength of the dielectrophoretic force on a particle and then consider the consequences of dielectrophoresis in media with different electromagnetic responses.

5.1.1. The Dielectrophoretic Effect Dielectrophoresis is the net force experienced by a dielectric object in a nonuniform electric ﬁeld. This effect exists because the dipole charges 7q induced at characteristic locations r7 are subject to different values of the electric ﬁeld Ee(r), as shown in Figure 5.1. There is no net force in a homogeneous electric ﬁeld, so we can expand, *

*

*

*

*

E e ðrþ Þ ¼ E e ðr Þ þ ðL rÞE e ðr Þ þ OðL2 Þ: For particles that are small relative to the characteristic length of a ﬁeld gradient, the net force is given by *

*

*

*

*

*

*

*

*

*

*

*

*

F ¼ F þ F þ ¼ qðE e ðr þ Þ E e ðr ÞÞ ¼ ðqL rÞE e ¼ ðp rÞE e : Under vector transformation, *

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

F ¼ ðp rÞE e ¼ rðp E e Þ ðE e rÞp p ðr E e Þ E e ðr pÞ: *

*

Since r E e ¼ 0, and for a *dielectric that is isotropically, linearly, and homo* aE e for body volume v and tensor polarizability ^a, the geneously polarizable, p ¼ v^ force reduces to * * * * * * * * * * 1 * * 2 aðE e rÞE e ¼ v^arE e : F ¼ rðp E e Þ ðE rÞp ¼ v^ 2 Notably, the above dielectrophoretic force is invariant under ﬁeld inversion. Ee(r )

−q

L = r+ − r−

+q

Figure 5.1. Schematic of dielectric particle in inhomogeneous ﬁeld.

157

5.1. INTRODUCTION TO DIELECTROPHORESIS

5.1.2. Dielectrophoresis in Media For a particle with complex dielectric permittivity ep in a medium em , the internal electric displacement is the sum of the particle polarization and the external displacement: *

*

*

*

Di ¼ ep E i ¼ P þ em E i : Therefore, the polarization scales with the internal electric ﬁeld as * * P ¼ ep em E i : This polarization generates an additional surface charge dQ on each surface element dF: *

*

dQ ¼ spol dF ¼ P dF : So, applying Coulomb’s Law and combining this result with the unperturbed ﬁeld, we ﬁnd that ZZ * * * * E i ðr 1 Þ ¼E e ðr 1 Þ

ZZ * i * * r 12 r 12 h * * * dQ ¼E ðr Þ P ðr Þ dF 2 e 1 2 2 4pem r312 4pem r312 ZZ *r h* i * * * * 12 ¼E e ðr 1 Þ ep em E ðr Þ dF : i 2 2 4pem r312 *

Since we assumed that the particle is linearly polarizable and, for approximation purposes, considering only the polarization parallel to the electric ﬁeld, it follows that: * * * P ¼ aE e ¼ ep em E i (ZZ * ) i * * * a r 12 h * * * * E e ðr 1 Þ ﬃ E e ðr 1 Þ a Proj* * ! E e ðr 2 Þ dF 2 Ee ð r 1 Þ 4pem r312 e e p

m

"* * # * * ZZ * * * a r 12 Ee ðr 1 Þ E e ðr 2 Þ dF 2 * E e ðr 1 Þ ﬃ E e ðr 1 Þ ! Ee ðr 1 Þ *2 * 4pem r312 ep em Ee ðr 1 Þ ep em ! a ﬃ em "* * # * * ZZ * * e r E ðr Þ E ðr Þ dF e 12 e e 2 2 1 em þ p4p m *2 * r312 Ee ðr 1 Þ a

*

*

*

*

The above expression for a=em is termed the Clausius–Mossotti factor and is denoted by the frequency-dependent function K(o).

158

CHAPTER 5: DIELECTROPHORETIC ARCHITECTURES

(K±)

Ee

(KII)

Ee

L R

Figure 5.2. Clausius–Mossotti deﬁnitions for orientations of a cylindrical particle.

This factor, in both sign and magnitude, is essential to characterizing the dielectrophoretic behavior of a particle in a medium. When the factor is positive, the particle moves toward stronger electric ﬁelds; when the factor is negative, the particle moves toward weaker electric ﬁelds. For rotationally asymmetric particles, the magnitude can depend strongly on particle orientation relative to the ﬁeld direction and, in particular, roughly corresponds to the elongation of the particle along the ﬁeld axis. The nanodevices we focus on in this chapter are cylindrical, so we now present approximate Clausius-Mossotti expressions for cylindrical particles parallel and perpendicular to a ﬁeld, as shown in Figure 5.2: Kjj ðf Þ ﬃ

ep em em þ ðep em Þð1 ð1 þ R2 =L2 Þ1=2 Þ

and K? ðf Þ ¼

em

ep em ep em : 3 ep þ 2em 1 p8 þ ep p8

5.2. DIELECTROPHORETIC ASSEMBLY AND TRANSPORT OF NANODEVICES Having completed our discussion of the theory of dielectrophoresis, we are now ready to explore its practical applications to nanocomputation. Let us ﬁrst consider the problem of assembling individual nanodevices. Various approaches for manipulating electronic nanostructures have been developed, including mechanical [7], optical [8, 9], electrostatic [10, 11], and dielectrophoretic [6] methods. Dielectrophoresis is particularly attractive for inexpensive and massively parallel manipulation [12] of neutral microscale and nanoscale objects using only standard semiconductor fabrication technologies. It has been used to trap a variety of structures from suspensions, including NiSi nanowires [13], CdS nanowires [14], GaN nanowires [15], carbon nanotubes [16], silicon microblocks [17], ZnO

159

5.3. DIELECTROPHORETIC RECONFIGURATION OF NANODEVICES

R = 1.2 kΩ

10 VPP

7.5 VPP

R

R

5 VPP

R

2.5 VPP

Figure 5.3. Dark-ﬁeld microscope image demonstrating the trapping of large numbers of nanostructures, which are visible as lines perpendicular to the electrode faces, at relatively low voltages.

nanorods and nanobelts [18, 19], and gold nanowires [20]. An example of the ability of dielectrophoresis to trap nanostructures with relatively low voltages is shown in Figure 5.3. Previous electrical transport measurements of dielectrophoretically trapped structures have been performed either after immobilizing the structures through drying [15–19] or chemical binding [20], or performed over large ﬁlms of parallel interconnects [16]. In this work we demonstrate for the ﬁrst time that dielectrophoresis may also be used to reconﬁgure and disassemble nanowire interconnects and that our process is compatible with the assembly and electronic characterization of individual nanowire devices.

5.3. DIELECTROPHORETIC RECONFIGURATION OF NANODEVICES Assembly of nanodevices is itself worthy of scientiﬁc interest, but the beauty of dielectrophoretic architectures lies in their versatility, since they enable not just the assembly but the reconﬁguration of nanodevices as well. We now proceed to discussion of the recent experimental demonstration of reconﬁgurable nanowire interconnects [21], which exempliﬁes that versatility.

5.3.1. Fabrication of a Nanowire Trapping Architecture For interconnects, p-type silicon nanowires were grown by the vapor-liquid-solid method [22], using 20-nm Au nanocluster catalysts (Ted Pella), and SiH4 reactant

160

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(99.7%) and B2H6 dopant (0.3%) in He carrier gas (100 ppm) at 450 torr and 450 1C. Growth was performed for 10–60 min to achieve nanowire lengths of 10–60 mm. The nanowire growth wafer was sonicated lightly in isopropanol for 1 min. The suspension was vacuum ﬁltered using a 12-mm mesh (Millipore Isopore) in order to remove unnucleated Au catalyst particles and short nanowires. The ﬁlter mesh was sonicated in isopropanol, and the suspension was again ﬁltered. The second ﬁlter mesh was sonicated in benzyl alcohol for 2 min and the suspension was used for trapping experiments. Benzyl alcohol was selected as a viscous, low-vapor-pressure solvent [23] for reconﬁguration in order to damp Brownian motion, minimize toxicity [24], and allow ambient operation. Additionally, its static relative permittivity is slightly smaller than that of bulk Si (11.9 versus 12.1, respectively) [23], reducing van der Waals interactions at low frequencies and favouring dielectrophoretic trapping of conductive structures [6]. Heavily doped silicon nanowires were selected as interconnects to demonstrate potential compatibility of our technique with the assembly of more complex semiconducting nanostructures, such as axial heterostructures [25]. Trapping experiments were performed with 100-nm Au electrodes (5 nm Cr wetting layer) to avoid oxidative damage, on a Si wafer with a 200-nm oxide to prevent shorts. Thicker electrodes, with reduced fringing ﬁelds, were found to better allow nanowires to migrate along their edges toward the trapping region. Thinner electrodes tended to permanently pin nanowires to the top electrode faces wherever they were ﬁrst trapped. The electrodes were deﬁned by e-beam lithography with a 101 taper angle and a 1-mm tip radius of curvature. The nanowire suspension was pipetted onto the electrode chip to form a 250-mm-thick reservoir, as shown schematically in Figure 5.4a. For trapping, electrode pairs were biased at 10 kHz to minimize both solvent electrolysis and parasitic capacitance. The bias was modulated into 10-ms bursts at 110 VRMS with a period of 100 ms, which allowed migration of nanowires toward the trapping region in controlled steps. The time between bursts was manually increased to 1000 ms as nanowires approached the inter-electrode region, and the bursts were halted when the desired number of nanowires had been trapped. Movies of nanowire motion were recorded at 4 fps.

Figure 5.4. Dielectrophoretically trapped nanowires. (a) Schematic illustration of nanowire trapping process. (b) Light microscope image of multiple nanowires stably trapped between electrodes separated by 40 mm. Scale bar is 40 mm.

161

5.3. DIELECTROPHORETIC RECONFIGURATION OF NANODEVICES

Electrical characterization was performed by manually switching the electrodes from the trapping voltage source to a measurement apparatus (Agilent 4156C). A 10-V sawtooth bias at 10 Hz was used and the measured currents were binned by voltage and averaged to remove hysteresis. Nanowire movement in the plane of the chip during transport measurement was minimal, since transport voltages were an order of magnitude smaller than trapping voltages.

5.3.2. Trapping Nanowire Interconnects Nanowires up to 55 mm in length were stably trapped, as shown in Figure 5.4b, with noticeable bending due to the trapping ﬁeld inhomogeneity. The longest previously reported one-dimensional nanostructures to be trapped by dielectrophoresis at both ends were less than 15 mm long and showed minimal bending [14]. For larger electrode gaps, nanowires at either tip appeared not to experience signiﬁcant bending toward the opposite electrode, while shorter gaps caused signiﬁcant accumulations of wires, as shown in Figure 5.5. Conﬁrmation that the trapping voltage was not substantially attenuated was provided by observation of a single scattering fringe around the electrodes in darkﬁeld mode, as shown in Figure 5.6, which was consistent with the DC Kerr effect [6] at 155-V peak bias across a 10-mm gap. The burst method was also delicate enough to enable trapping of individual nanowires when the reservoir was diluted below 2 1013 M, as shown in Figure 5.7a. Before nanowire interconnects were assembled, DC transport between electrode pairs was nearly ohmic, as shown in Figure 5.7b. The measured current of 0.3 mA at 1-V bias and 40-V/s sweep rate was consistent with electrooxidation of benzyl alcohol [26, 27] at 1-mm-radius electrode tips. However, after a 50-mm-long nanowire was trapped, the conductance became nonlinear and showed a 50% enhancement at 10-V bias, as shown in Figure 5.7c. Treating the device as an electrooxidative resistance in parallel with a series nanowire resistance and Schottky contacts [28], a nanowire transport curve was calculated, as shown in Figure 5.7d. The nanowire exhibited a calculated linear 10 μm

20 μm

30 μm

40 μm

60 μm

80 μm

Figure 5.5. Nanowires trapped by electrodes separated by various distances.

162

CHAPTER 5: DIELECTROPHORETIC ARCHITECTURES

Figure 5.6. Scattering fringes about active electrodes as viewed in dark-ﬁeld mode, attributed to the DC Kerr effect.

4 3 2 1 0 (d) −1 −2 (b) (c) −3 −4 −10 −5

(e)

6 Current (μA)

Current (μA)

(a)

(g)

4 2

(f) 0 −2

0 Voltage (V)

5

10

−15

−10

0 5 −5 Voltage (V)

10

15

Figure 5.7. Electrical transport in trapped nanowires. (a) Dark-ﬁeld microscope image of a single nanowire trapped by an electrode pair under solvent with electrical transport (b) measured with solvent, (c) measured with trapped nanowire in solvent, and (d) calculated for nanowire alone. (e) Dark-ﬁeld microscope image of two trapped nanowires on dried substrate with electrical transport measured (f) immediately after drying and (g) after several voltage sweeps. Scale bars are 10 mm.

5.3. DIELECTROPHORETIC RECONFIGURATION OF NANODEVICES

163

response resistivity of 3.8 103 O cm (6.0-MO resistance), consistent with a B doping ratio of 2000:1, and an estimated barrier potential of 2.0 V. The barrier potential was higher than the 0.34 V measured in evaporated Au/p-Si junctions [29], and is attributed to incomplete contact of the nanowire with the electrodes. Further conﬁrmation that dielectrophoretically trapped nanowires acted as interconnects was provided by substituting ethanol as a solvent and permitting the substrate to dry after trapping. A pair of nanowires thus trapped, as shown in Figure 5.7e, appeared to rest on both electrode faces but initial voltage sweeps yielded a 30-MO resistance, as shown in Figure 5.7f. After several sweeps, however, a sharp current turn-on was observed at 6.8–7.8 V, as shown in Figure 5.7g, which may indicate electrostatically induced bending of the nanowires to better contact the electrodes. Above the turn-on bias, the nanowires exhibited a 1.7-MO combined resistance, which is compatible with the solvent-based result.

5.3.3. Reconﬁguring Nanowire Interconnects The reported method for trapping nanowire interconnects furthermore enabled reconﬁguration, since nanowires were maximally polarized when aligned between a pair of electrode tips. Reconﬁguration of a nanowire bundle was achieved using ‘‘source’’ and ‘‘drain’’ electrodes with opposite phase and a ‘‘latch’’ electrode with variable phase. Several nanowires were independently trapped between the source and latch electrodes with 100-ms-period bursts, as shown in Figure 5.8a, and then bundled with 250-ms-period bursts, as shown in Figure 5.8b. The phase of the latch electrode was then inverted, with the same burst period, causing the nanowire bundle to experience a dielectrophoretic force toward the drain electrode. Because the electrode tips were arranged in an isosceles right triangle formation, the torque about the latch electrode was higher than that about the source electrode, and the nanowire remained in contact with the latch electrode during the motion, as shown in Figure 5.8c. The reconﬁguration was completed 0.25–0.75 s after the phase inversion, as shown in Figure 5.8d, and could be reversed by restoring the original phase of the latch electrode, as shown in Figure 5.8e. Similarly, parallel reconﬁguration of a pair of nanowire interconnects was achieved with four electrodes in a 10-mm square, as shown in Figure 5.9. To accomplish this, the relative phases between diagonally opposite electrodes were ﬁxed and the relative phase of the diagonal pairs was inverted. Dielectric breakdown of some nanowires occurred and short fragments were visible around the connecting nanowires. For theoretical comparison, we now calculate how rapidly a nanowire might be dielectrophoretically reconﬁgured. The dielectrophoretic force per unit length on a cylindrical nanowire with length lwire and diameter dwire is given by n* o * * * 1 2 2 ^ 2Þ Fdep ¼ esolv pdwire Re K ð f Þ rðE Þ rðE 8 *

where esolv is the solvent permittivity and K ð f Þ is the frequency-dependent Clausius–Mossotti factor [6].

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Figure 5.8. Microscope images of 3-electrode serial reconﬁguration of nanowires. The relative phase between the left (source) and middle (latch) electrodes is modulated from (a,b) 1801 to (c,d) 01 to (e) 1801. Scale bars are 15 mm.

For lwire >> dwire , the Clausius–Mossotti component perpendicular to the nanowire axis is approximately K? ¼

~esolv

~ewire ~esolv p ; p 1 þ ~ewire 8 8

where ~eX eX isX =ð2pf Þ are the complex permittivities of nanowire and solvent (the solvent is assumed to be nonconductive at trapping frequencies). Approximating the gradient of the ﬁeld energy density in the inter-electrode space as *2

2 =L3 , where L is the distance between electrode tips. uniform, rðE ÞV~sd The dielectrophoretic force is opposed by Stokes drag. The drag coefﬁcient for an inﬁnitely long, cylindrical nanowire [30] is given by

CD

Fdrag 8p

; 1 Reð2:002 ln ReÞ rwire u2 d 2

5.3. DIELECTROPHORETIC RECONFIGURATION OF NANODEVICES

165

Figure 5.9. Microscope images of 4-electrode parallel reconﬁguration of nanowires. Each pair of diagonally opposite electrodes is held at a constant relative phase of 1801, while the relative phase between the upper-left and upper-right electrodes is modulated from (a) 01 to (b) 1801 to (c) 01. Scale bars are 20 mm.

where Fdrag is the drag force per unit length, rwire is the nanowire density, u is the nanowire velocity, and Redrsolv u=m is the Reynolds number for solvent density rsolv and dynamic viscosity m. Assuming bulk mechanical properties of silicon and benzyl alcohol [23] and matching drag and dielectrophoretic forces, the terminal velocity during switching perpendicular to the nanowire axis is calculated to be u>E30 mm/s, implying a 0.3-s reconﬁguration time. This time is consistent with the serial reconﬁgurations observed, validating our model.

5.3.4. Disassembling Nanowire Interconnects Finally, it should be mentioned that electrically driven nanowire disassembly was also found to occur. In an example of this effect, a single nanowire that was initially trapped on one electrode, as shown in Figure 5.10a, was pulled into the inter-electrode region and a gas bubble immediately formed there, as shown in Figure 5.10b. After the bubble dispersed, only short nanowire fragments remained, as shown in Figure 5.10c. This effect was observed for about 1/3 of

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Figure 5.10. Disassembly of nanowire interconnects by thermal detonation. (a) Stably trapped nanowire before detonating voltage pulse. (b) Vapor bubble resulting from thermal detonation. (c) Only submicron fragments remain. Scale bars are 20 mm.

the nanowires trapped in inter-electrode regions and might be explained by variation in the nanowire conductivities and/or the formation of exceptionally good contacts, which could lead to current densities as high as 5 1010 A m2 and thermal detonation. After the original nanowires were destroyed, the interelectrode regions were typically able to trap new interconnects, so this effect might prove useful in fault-tolerant applications for severing connections to nonfunctioning components.

5.3.5. Summary of Implementation The ﬁrst assembly, reconﬁguration, and disassembly of nanowire interconnects through dielectrophoresis has been presented. Silicon nanowires up to 55 mm long were trapped, and solvent-based transport studies show a 50% conductivity enhancement in the presence of the nanowires. Once assembled, these nanowire interconnects could then be reconﬁgured and disassembled using periodic voltage bursts. These results open up the possibility of colloidal, nanostructured connection architectures for computation.

167

5.4. LARGER- SCALE ARCHITECTURES

5.4. LARGER-SCALE ARCHITECTURES With our discussion of individual component reconﬁgurability concluded, we now advance to an exploration of the feasibility of larger-scale dielectrophoretic architectures. For dielectrophoresis to ﬁnd real-world applications to nanocomputation, logic—at least at the gate level—must be demonstrated.

5.4.1. 1 3 1 Crossed Interconnects In Section 5.3 we experimentally demonstrated the reconﬁguration of interconnects geometrically occupying single sides or pairs of sides of a square. As a next step toward larger-scale architectures, we should also consider interconnects that do not lie on the circumference of the trapping region, but instead span it. In particular, we may estimate the value of the term rE2, which is crucial to the dielectrophoretic strength, for either type of conﬁguration, as shown schematically in Figure 5.11. Recall that we may approximate the trapping force by assuming a uniform electric ﬁeld gradient near the energy minimum. Therefore, for the geometry shown in Figure 5.11, for the noncircumferential interconnect (I), pﬃﬃﬃ 1 V2 rE 2 ðV Þ2 =ðd 2Þ3 ¼ 3=2 3 ; d 2 and for the circumferential interconnect (II), rE 2 ðV=2Þ2 =ðdÞ3 ¼

1 V2 : 22 d 3

+V/2

d 0

II

I

0

−V/2

Figure 5.11. Schematic diagram for circumferential (II) versus noncircumferential (I) interconnects in a 1 1 crossbar.

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Since the value is larger for the noncircumferential case, stable trapping of diagonal interconnects should be possible. (There is suggestive experimental data that stable diagonal interconnects can indeed be achieved [14], although the substrate in that case was dried before imaging.) Moreover, since K? Kjj , a short ﬁeld burst perpendicular to an existing wire should not disrupt it.

5.4.2. 2 3 2 Crossbar We can perform a similar, albeit more entailed, analysis to determine the feasibility of stable noncircumferential interconnects in larger crossbars, such as the 2 2 geometry we now consider. For the speciﬁc octagonal electrode tip geometry and voltages shown in Figure 5.12, we can calculate all force values (F rE2):

2

2 1 1 a þ a F2 F3 ð2aÞ2 F4 2 2 ¼ ¼ 3 ; ¼ "rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ#3 ; 3 : F1 F p F 1 1 1 1 p2 pﬃﬃﬃ ð1 pÞ þ 2 2 2

2 1 þa F4 F5 ð2aÞ2 2 ¼ "rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ#3 ; ¼ hpﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃi3 ; F1 F1 1 p2 p2 þ 1 þ 2 2 In order to estimate the proper conditions for trapping of non-circumferential interconnects, particularly the interconnect at F1, we are most interested in the

+V/2

+V/2

F2 L aV

F1 aV

F4

F3 −aV

−aV

F5

pL −V/2

−V/2

Figure 5.12. Schematic diagram for dielectrophoretic force constants for various interconnects in a 2 2 crossbar geometry. Circles indicate electrode tips.

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5.4. LARGER- SCALE ARCHITECTURES

0.1 0.2 0.8 0.15 0.6 p

p 0.1

0.4 0.05 0.2 0

0

0.01 0.02 0.03 0.04 0.05 a

0 0

0.1

0.2

a

0.3

0.4

0.5

Figure 5.13. Phase diagram of dielectrophoretic forces (F2, F3, F4, F5)/F1 in the space of dimensionless electrode voltages (a) versus electrode spacings (p) in a 2 2 crossbar geometry. Darker regions indicate that more of F2, F3, F4, F5 are less than F1.

parameters 0oao1/2, 0opo1 that cause all of these ratios to fall below 1. We survey this phase space in Figure 5.13, and ﬁnd that—at least by this prediction method—long crossbar-style interconnects should be possible as long as the parallel electrode pitch is 10–20 times smaller than the interconnect length (0.05opo0.1) and electrodes uninvolved in the trapping are kept grounded (a=0).

5.4.3. Field-Programmable Gates In addition to interconnect architectures, it should also be possible to more directly build logic based on dielectrophoretic reconﬁguration of nanodevices. In particular, with the proper arrangement of pairs of the latching electrodes shown in Figure 5.8, digital logic gates can be reproduced. In these gates, as depicted in Figure 5.14, the relative phase of two electrodes determines the position of interconnects which can then carry or block a current path speciﬁc to the logical operation required.

5.4.4. Packaging In order to enable the vision of dielectrophoretic architectures for self-repairing computer components, development of stable colloidal reservoirs of components will be crucial. Fortunately, many dielectric solvents, such as the benzyl alcohol used in the reconﬁgurable nanowire work discussed above, have low vapor pressures. This property may enable colloidal reservoirs of replacement components to be stably sealed into a chip carrier package, as shown in Figure 5.15.

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CHAPTER 5: DIELECTROPHORETIC ARCHITECTURES

Example (AND):

+ AND:

A

B −

+V/2

− +

OR:

A −

lsd V/2*(−1)A

V/2*(−1)B

B − −

NOR:

A

B +

+ − −V/2

−V/2

NAND:

A

B +

+

Figure 5.14. Field programmable gates in which short voltage pulses on two electrodes serve as input (phase indicated by sign), and current indicated by arrows serves as output.

Figure 5.15. Packaged nanowire reservoir.

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171

In preliminary tests, sealed reservoirs of benzyl alcohol for dielectrophoretic manipulation remained stable, in the sense that nanowires remained suspended and there was no visible leakage of solvent, for more than a week under refrigeration.

5.5. CONCLUSIONS We have reviewed recent progress toward the development of dielectrophoretic architectures for integrated nanoelectronic computation. Focusing on the demonstration of reconﬁgurable nanowire interconnects, we also derived general strategies for scaling, integrating, and packaging such dielectrophoretic systems.

ACKNOWLEDGEMENTS The author is especially grateful to C. M. Lieber for his generous guidance and support, and for use of his laboratory, and to F. Patolsky for very helpful discussions. The author also thanks the Fannie and John Hertz Foundation for doctoral funding, and T. M. Sullivan for his editing. This work made use of Harvard Center for Nanoscale Systems and NSF/NNIN facilities. This material was supported in part by the United States Air Force and DARPA under Contract No. FA8750-05-C-0011. Any opinions expressed are those of the author and do not necessarily reﬂect the views of the United States Air Force or DARPA.

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7. Y. Huang, X. Duan, Q. Wei, and C. M. Lieber. Directed assembly of one-dimensional nanostructures into functional networks. Science, 291: p 630–633, 2001. 8. R. Agarwal, K. Ladavac, Y. Roichman, G. Yu, C. M. Lieber, and D. G. Grier. Manipulation and assembly of nanowires with holographic optical traps. Optics Express, 13(22): p 8906–8912, 2005. 9. P. J. Pauzauskie, A. Radenovic, E. Trepagnier, H. Shroff, P. Yang, and J. Liphardt. Optical trapping and integration of semiconductor nanowire assemblies in water. Nature Materials, 5: pp 97–101, 2006. 10. J. E. Jang, S. N. Cha, Y. Choi, G. A. J. Amaratunga, D. J. Kang, D. G. Hasko, J. E. Jung, and J. M. Kim. Nanoelectromechanical switches with vertically aligned carbon nanotubes. Applied Physics Letters, 87: p 163114, 2005. 11. T. Rueckes, K. Kim, E. Joselevich, G. Y. Tseng, C. L. Cheung, and C. M. Lieber. Carbon nanotube-based nonvolatile random access memory for molecular computing. Science, 289(5476): p 94–97, 2000. 12. P. Y. Chiou, A. T. Ohta, and M. C. Wu. Massively parallel manipulation of single cells and microparticles using optical images. Nature, 436: p 370–372, 2005. 13. L. F. Dong, J. Bush, V. Chirayos, R. Solanki, J. Jiao, Y. Ono, J. F. Conley Jr., and B. R. Ulrich. Dielectrophoretic controlled fabrication of single crystal nickel silicide nanowire interconnects and the investigation of their formation mechanism. Nano Letters, 5(10): p 2112–2115, 2005. 14. X. Duan, Y. Huang, Y. Cui, J. Wang, and C. M. Lieber. Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices. Nature, 409: p 66–69, 2001. 15. T. H. Kim, S. Y. Lee, N. K. Cho, H. K. Seong, H. J. Choi, S. W. Jung, and S. K. Lee. Dielectrophoretic alignment of gallium nitride nanowires (GaN NWs) for use in device applications. Nanotechnology, 17(14): p 3394–3399, 2006. 16. Z. Chen, Y. Yang, F. Chen, Q. Qing, Z. Wu, and Z. Liu. Controllable interconnection of single-walled carbon nanotubes under AC electric ﬁeld. Journal of Physical Chemistry B, 109(23): p 11420–11423, 2005. 17. S. W. Lee and R. Bashir. Dielectrophoresis and electrohydrodynamics-mediated ﬂuidic assembly of silicon resistors. Applied Physics Letters, 83(18): p 3833–3835, 2003. 18. O. Harnack, C. Pacholski, H. Weller, A. Yasuda, and J. M. Wessels. Rectifying behavior of electrically aligned ZnO nanorods. Nano Letters, 3(8): p 1097–1101, 2003. 19. C. S. Lao, J. Liu, P. Gao, L. Zhang, D. Davidovic, R. Tummala, and Z. L. Wang. ZnO nanobelt/nanowire Schottky diodes formed by dielectrophoresis alignment across Au electrodes. Nano Letters, 6(2): p 263–266, 2006. 20. L. Shang, T. L. Clare, M. A. Eriksson, M. S. Marcus, K. M. Metz, and R. J. Hamers. Electrical characterization of nanowire bridges incorporating biomolecular recognition elements. Nanotechnology, 16: p 2846–2851, 2005. 21. A. D. Wissner-Gross. Dielectrophoretic reconﬁguration of nanowire interconnects. Nanotechnology, 17: p 4986–4990, 2006. 22. Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber. Diameter-controlled synthesis of single-crystal silicon nanowires. Applied Physics Letters, 78(15): p 2214–2216, 2001. 23. D. R. Lide, editor. CRC Handbook of Chemistry and Physics, 82nd ed., New York: CRC Press, pp 3–52, 6–163; 12–59, 2001.

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6 MULTILEVEL AND THREEDIMENSIONAL NANOMAGNETIC RECORDING S. Khizroev, R. Chomko, I. Dumer, and D. Litvinov This chapter outlines a study of multilevel (ML) and three-dimensional (3D) magnetic recording—a nanomagnetic recording technology suitable for information storage densities above 10 Tbit/in2. To comply with the multilevel signal conﬁguration, ML magnetic recording exploits a 3D head/media system powered with next-generation data coding methods. It is believed, when that combined with novel information processing techniques, relatively cost effective ML systems could be scaled down to a single-grain spin level, thus enabling memory with effective areal densities above 100 Tbit/in2.

6.1. INTRODUCTION 6.1.1. Information Industries in Need of Alternative Storage Technologies Demand for larger areal density of storage and memory devices is growing exponentially with the emergence of the Internet, explosive growth of broadband communication, increasingly complex multimedia mobile devices, and the rapid expansion of on-demand databases serving multinational businesses. Magnetic recording has been the mainstream data storage technology for more than four decades [1, 2]. After aggressive attempts to extend the life of longitudinal magnetic recording, the data storage industry is ﬁnally coming to terms with reality [3, 4]. Researchers, indeed, witness that the recorded data become highly unstable as the areal density increases beyond approximately 200 Gbit/in2. A number of technologies have been proposed by research teams all over the world to address the fundamental (superparamagnetic) limit. The closest alternatives are believed to be Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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perpendicular magnetic recording (already commercialized) [5, 6], patterned medium [7–9], and heat-assisted magnetic recording (HAMR) [10–13]. It is expected that these technologies can defer the superparamagnetic limit somewhat above 1 TbitT/in2. However, there are other alternatives which the industry might not seriously consider due to the lack of similarity to the conventional technology. This somewhat conservative approach (to avoid ‘‘high risk’’ projects) is often dictated by economical reasons. Despite the fact that the high risk, unconventional technologies often have strong potential to revolutionize the industry, they might not be considered cost effective according to the current standards of the industry. The university environment, on the other hand, may favor high risk technologies because of their scientiﬁc values and far-future potential. In this chapter, multilevel (ML) three-dimensional (3D) magnetic recording will be discussed as one of such high risk data storage systems. To comply with the multilevel signal conﬁguration, ML magnetic recording exploits a 3D head/media system powered with next-generation data coding methods. It is believed, when that combined with novel information processing techniques, cost effective ML systems could be scaled down to a single-grain spin level, thus enabling memory with effective areal densities above 100 Tbit/in2. In summary, the purpose of this chapter is to diversify from the mainstream magnetic technologies and explore a novel nanoscale system suitable for unprecedented data storage densities and rates.

6.2. MULTILEVEL MAGNETIC RECORDING 6.2.1. Introduction In this section, an unconventional approach to increase the effective areal densities is discussed. The feasibility of using more than two signal levels to code recorded information is explored. This is in contrast to conventional recording schemes in which binary coding is used methods, meaning that the signal recorded into or read back from magnetic media has only two states: presence or absence of the magnetization reversal in a bit transition. For example, Figure 6.1a and b illustrate so called frequency modulation (FM) encoding form, probably the most trivial encoding scheme, as it could be used in longitudinal and perpendicular recording, respectively. The only difference between the two recording modes is in the orientation of the magnetization, along or perpendicular to the plane of the disk, respectively. In both cases, encoding has a simple one-to-one correspondence between the bit to be encoded and the magnetization reversal pattern. ML magnetic recording refers to the use of multiple signal values to encode data onto a magnetic disk. By using more than two levels, more information could be put in the minimum feature size. Figure 6.1c illustrates how a multilevel code could be used in a system with a 3D media with a perpendicular orientation of the magnetization. This is a simpliﬁed case; in general, the magnetization could be oriented along or at some arbitrary angle to the plane of the disk. As described

177

6.2. MULTILEVEL MAGNETIC RECORDING

Signal

1 0 0 0 0

1 0 1 0 1 0 0 0

M (a)

(b) Signal

0

1

2

3

4 5 dBm

Adjacent levels

(c)

Figure 6.1. A binary signal representation with a trivial FM encoding in (a) longitudinal and (b) perpendicular recording modes. (c) A trivial example of a system with multilevel data encoding.

below in more detail, the main concern is to engineer a magnetic recording system which could maintain signal-to-noise ratio (SNR) between any two adjacent levels sufﬁcient for a data encoding channel to maintain a certain data bit error rate. The novel multilevel data coding methods discussed in this chapter are designed to deal with SNR of approximately 5 dB. Therefore, it is clear that with the goal to develop a practical ML recording system with as many levels as possible, it is necessary to engineer a magnetic recording system with as many signal levels as possible and at least 5 dB SNR between any two adjacent levels. It is expected that the magnetic system discussed in this chapter could use at least twenty ‘‘distinguishable’’ signal levels. Finally, it should be mentioned that the ML approach could be applied ideally to any of the above mentioned alternative technologies to further increase the data capacity.

6.2.2. History of Multilevel Optical Recording Before exploring the feasibility of ML magnetic recording, it may be helpful to learn from the experience of other industries with regard to ML data coding. For example, in 2004, LSI Logic, one of the electronics giants, acquired Calimetrics, the ﬁrst company to focus on the development of a multilevel optical recording system for CD or DVD technologies. Though Calimetrics ceased to exist mostly because of the sudden increase in popularity of writable DVD technology, it was successful in introducing a multilevel signal standard to the world of information related technologies, especially overseas. Today, it is becoming normal for new

178 CHAPTER 6: MULTILEVEL AND THREE- DIMENSIONAL NANOMAGNETIC RECORDING

technologies to start to prosper ﬁrst overseas, as it is often easier to launch new standards because of the lack of a well established traditional technology infrastructure. It could be noted that though the ML technology by Calimetrics offered only eight signal levels and was not rewritable, it still appeared successful, especially for its tremendous impact on modern DVD technologies.

6.2.3. Apparent Differences Between ML Magnetic Versus ML Optical Technology First, the ML technology developed by Calimetrics competed in the market of DVD/CD technologies, while the analyzed ML magnetic technology, at least at this early stage, targets the market of hard drives. Second, the Calimetrics technology was optics-based, while the currently proposed technology is magnetics-based. Consequently, the magnetic technology would be rewritable, is in contrast with the read-only Calimetrics technology. Finally, the optical technology used only eight signal levels while the ML magnetic technology has the potential for many more levels.

6.2.4. Magnetics of Multilevel 3D Recording The concept of three-dimensional (3D) magnetic recording was proposed over 10 years ago [14, 15]. 6.2.4.1. Background. Traditionally, scaling laws have been followed to advance magnetic data storage industry to a next level/generation. Scaling implies that with each next generation, all dimensions of a recording system have been respectively reduced, as schematically illustrated in Figure 6.2. Such a straightforward approach (of scaling) has been applied since the inception of the data storage industry more than ﬁve decades ago.

Magnetizing coil

MR reader

Inductive “ring” writer

Scaling S

N N

S S

Write field

N N

S S

N N

S

Recording media

Figure 6.2. Schematic diagram illustrating how scaling has been applied to advance a technology to a next generation for the last ﬁve decades.

179

6.2. MULTILEVEL MAGNETIC RECORDING

6.2.4.2. Superparamagnetic Limit. For the ﬁrst time since the inception of the data storage, the traditional technology cannot be improved further. The reason is the superparamagnetic limit [16]. This fundamental limit is caused by thermal instabilities in the recording media when physical bit dimensions are reduced below certain fundamental values. Each bit in the recording media consists of over 100 grains. Though the grains are magnetostatically coupled, the separation between adjacent grains is large enough (B1 nm) to ensure the grains are ‘‘exchange’’ decoupled. The ‘‘exchange’’ coupling is a quantum mechanical coupling that exists at a separation of less than approximately a few nanometers [17]. In this case and, to some degree of approximation, the law of large number would prevail if the number of grains is maintained approximately greater than 100 [18, 19]. In other words, to maintain a certain value for the signalto-noise ratio (SNR), e.g., 20 dB, in a recording system, it is important to have the number of grains be greater than approximately 100. Therefore, when with each next generation bit dimensions are reduced, each grain dimension also must be reduced to maintain the number of grains and thus SNR value required for adequate signal processing. A transmission electron microscopy (TEM) image of a patch of a longitudinal recording media suitable for areal densities above 100 Gbit/in2 is shown in Figure 6.3a [20, 21]. The characteristic diameter of an average grain is approximately 6 nm. Figure 6.3b shows a schematic illustrating how a transition between two adjacent bits would be written. Now, according to the scaling law, to further increase areal density by a factor of four, i.e., up to 400 Gbit/in2, the characteristic diameter of an average grain should be reduced by a factor of two, i.e., it should be reduced to 3 nm. Unfortunately, here also lies a problem. The problem is the superparamagnetic limit. As the grain size is reduced (with each generation), the anisotropy energy, equal to the product of the grain volume

TEM

Magnetic grains

Bit transition (a)

(b)

Figure 6.3. (a) A transmission electron microscopy (TEM) image of a micropatch of a typical CoCr-based longitudinal magnetic recording media. (b) A schematic illustrating how a transition between two adjacent bits of information is deﬁned by the granular structure of the recording media.

180 CHAPTER 6: MULTILEVEL AND THREE- DIMENSIONAL NANOMAGNETIC RECORDING

and the anisotropy energy density, becomes comparable to the energy of thermal activations, i.e., kT (which is approximately 25 meV at room temperature). Professor Stanley Charap and his graduate students at Carnegie Mellon University were the ﬁrst to use Monte Carlo-based numerical simulations to estimate that the superparamagnetic limit becomes noticeable as the ratio of the anisotropy energy and the thermal energy is reduced (approximately) below the value of 40 [22]. For example, it was found that for the ratio value to increase from 40 to 60, the relaxation time changes from 72 seconds to over 3.6 109 years, respectively. In other words, to avoid the superparamagnetic limit, the following condition should be satisﬁed: Ku V > 40 60 kB T

ð6:1Þ

where Ku and V are the anisotropy energy density and the volume of an average grain, respectively. For this condition to be satisﬁed for typical CoCr-based longitudinal media, the characteristic diameter of an average grain should be greater than approximately 3 nm. Of course, one way to increase the ratio without reducing the average grain size could be to increase the anisotropy energy density. In fact, there are ultra-high anisotropy magnetic materials, such as L10 and others, that could be used to achieve the goal [23]. However, there is another fundamental limit that makes it difﬁcult to use these ultra-high anisotropy materials [24, 25]. A recording head is made of a soft magnetic material, and the maximum recording ﬁeld generated by the head is limited by the saturation magnetization of the material. Unfortunately, the saturation magnetization in practical soft materials, namely the 3D transition metals (Fe, Co, and Ni), is fundamentally limited by approximately 26 kemu/cc, as described by the so called generalized Slater– Pauling curve [26]. The curve shows that the magnetic moment per atom in ferromagnetic alloys of the 3D transition metals could generally be predicated as m=9.6Nd, where Nd is the average number of d electrons per atom. This curve works because it is energetically favorable to keep the majority-spin d-band full, independent of alloy composition. Therefore, to further extend the areal density, it is necessary to further reduce the grain size and thus further reduce the ratio in Expression 1; this implies stepping in the superparamagnetic limit. The modern laboratory demonstrations indeed indicate that the information becomes highly unstable as the areal density is increased above approximately 200 Gbit/in2 [27]. That is why the multibillion data storage industry is currently searching for an alternative technology that could extend scaling and thus areal data density much beyond the current limits. 6.2.4.3. Temporary Solution/Patch in Layman’s Terms. So called perpendicular recording promises to defer the fundamental superparamagnetic limit for several more years [28–32]. Ideally, this could bring the areal densities in demonstration data storage systems to one Tbit-per-square-inch. Figure 6.4 illustrates the difference between the conventional technology (longitudinal

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Background:

Magnetizing coil

Today, perpendicular recording is forcing longitudinal recording out of the market

MR reader

Perpendicular

Inductive “ring” writer Magnetizing coil

S

N N

SS

Write field

N N

S S

N N

Recording media

Longitudinal Bit sizes: 13 x 52 nm2

Inductive “SPH” writer

MR reader

S

Write field Recording layer SUL

Figure 6.4. A schematic diagram to compare conventional longitudinal magnetic recording and perpendicular magnetic recording systems. In these two cases, magnetization in the recording media are directed along the plane and perpendicular to the plane of the disk, respectively. (Image from Perpendicular Magnetic Recording by S. Khizroev and D. Litvinov r 2004 Kluwer Academic Publishers.)

magnetic recording) and perpendicular recording. In the case of perpendicular recording, the magnetization in the disk is polarized perpendicular to the disk. This is in contrast to the conventional system in which the magnetization is polarized along the disk. According to a model in layman’s terms, each bit of information is presented as a permanent magnet. Depending on the direction of the magnetic moment inside the magnet, the recorded information is ‘‘0’’ or ‘‘1.’’ According to this model, one could pack more permanent magnets per unit surface area in the conﬁguration when the magnet’s axis is directed perpendicular to the disk rather than in the plane of the disk. Unlike many other alternatives to the conventional recording (such as heatassisted magnetic recording (HAMR) and patterned media), perpendicular recording has been quickly adopted by the industry because of its similarity to the conventional technology [33–36]. In fact, this adoption is happening today. During the last two years, most leading companies in the industry have transitioned to perpendicular recording. Such a drastic change is quite unprecedented for the industry that has been following one technology for over ﬁve decades now! However, as mentioned earlier, perpendicular recording in its current form is only a temporary solution/patch. The solution it offers is more quantitative than qualitative and thus the expected progress is quite incremental (for only the next ﬁve years or so).

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Transducer flying direction

Transducer flying direction

Recording transducer

Recording transducer N -layer media

Conventional media 10−20

~2 nm

Magnetization “up” and “down”

Figure 6.5. Comparison between a conventional recording system with recording on a surface (left) and a proposed 3D or/and multilevel system with recording across the thickness of the recording media.

6.2.4.4. Multilevel 3D Recording in Layman’s Terms. The proposed technology differs from the traditional approach because it deals with one surface (of a magnetic recording media) only. It is proposed to use a third vertical dimension to store information not only on the surface but also in the volume of the recording media. In other words, the information is packed across the thickness, as shown in Figure 6.5. As a result, more than one signal level would be exploited to record, store, and retrieve information from the same unit surface area of the recording media. This opens a new window of opportunities to develop not only the most superior near-future data storage device (multilevel 3D (m3d) drive) but also for a long future to exploit groundbreaking advantages of an entirely new dimension. 6.2.4.5. Advantages a. Simplicity One of the advantages of this technology, at least at this early stage of development, is its relative simplicity. This is due to the fact that the proposed multilevel 3D magnetic recording has similarity with perpendicular recording. Similar to perpendicular recording, the information, at least at the initial stage, will be recorded perpendicular to the disk. However, other media conﬁgurations should not be disregarded. For example, longitudinally oriented media or media with the magnetization tilted at some arbitrary angle may have some advantages perpendicular media do not have. As the complexity of multilevel 3D recording system increases with each next generation, it might become beneﬁcial to switch to one of the nonperpendicular modes. b. Technological Superiority As mentioned above, this is the only magnetic technology that relies on the use of a third dimension to record, retrieve, and store information in a device. In other words, the information will be recorded not only on a surface but also across the thickness or in the volume of the recording media. As a result,

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183

substantially more information could be recorded per unit area and thus the fundamental data density limit could be extended substantially further. This means that this technology has strong potential to revive the current, relatively slow progress in the multibillion-dollar data storage industry. c. Long-term Potential For the reason mentioned above (exploiting not only a surface but the volume of a device), the technology has potential to be extended much further into the future compared to any other alternative data storage technology. d. Multilevel Signal The exploitation of multilevel signals will substantially loosen fabrication requirement. In other words, unlike conventional magnetic and silicon technologies, this effort will not be limited by the many problems that arise during fabrication of sub-100-nm devices. In this context, multilevel implies the ability to record more information per unit surface area. As mentioned above, previous research has identiﬁed the multilevel mode as a likely form of 3D recording to impact the future world of memory and storage applications [37–39]. In this mode, a varying recording ﬁeld was used to sequentially record across the media thickness, as illustrated in Figure 6.6a. The research effort has triggered industry-wide interest in the new topic [40]. The current study is aimed at bringing the research to the next level. The chapter studies the feasibility of multilevel magnetic recording and attempts to consider the physical limitations of the technology designed to function at densities above 10 Tbit/in2. Previously, the authors developed 3D media similar to the popular perpendicular media conﬁguration (with the magnetization perpendicular to the plane of the disk) [41]. A recording system with a single pole head and a recording media with a soft underlayer (SUL) (Fig. 6.6b [42]) was used to generate adequate perpendicular ﬁeld. SUL was used to force the magnetic ﬂux to ﬂow in the perpendicular direction. Typical FIB-modiﬁed write head with a 80-nm trackwidth and a magnetic force microscopy (MFM) nanoprobe used to write and read information from 3D media, respectively, are shown in Figure 6.6c and d. The write head was in the form of a single pole [43], while the MFM nanoprobe was designed to read a certain component of the magnetization [44, 45]. A schematic illustrating the concept of 3D recording is shown in Figure 6.7a. For simplicity, only two magnetic layers across the thickness are discussed. The layers can be deposited via regular sputtering systems. Continuous and patterned versions of 3D media could be used. For illustration purposes and prototype development, a focused ion beam (FIB) was used to further pattern 3D media within the plane of the disk, as illustrated in Figure 6.7a. A straightforward MFM experiment can be performed to demonstrate the presence of more than one signal level. In this example, a CoCrPt-based 2-layer 3D media was sputter-deposited and then patterned via FIB into a square periodic arrays with a linear period of 80 nm [46]. Then, the media was demagnetized using an alternating external magnetic ﬁeld. AFM (left) and MFM images of the surface of the fabricated

184 CHAPTER 6: MULTILEVEL AND THREE- DIMENSIONAL NANOMAGNETIC RECORDING

Inductive “SPH” head

Magnetizing coils Reader (GMR sensor)

head H = Hc

Magnetic bits

Write field Magnetization up and down (a) SUL (b)

Nanoprobe

Writer (single pole)

FIB−etched regions GMR reader

(c)

(d)

Figure 6.6. (a) Schematic illustrating recording across the thickness via continuous variation of the recording ﬁeld. The boundary curve is the ﬁeld proﬁle when H = Hc, where Hc is the coercivity. (b) A diagram of a perpendicular recording system. FIB images of FIB-fabricated (a) single pole writer with a 80-nm trackwidth and (b) a MFM nanoprobe for reading a component of the stray magnetic ﬁeld.

media are shown in Figure 6.7b. A digitized sectional proﬁle of the signal along the highlighted line going through a track of bits is shown above the AFM and MFM images. Clearly, over three different signal levels could be detected, as shown in Figure 6.7b (top). This experiment illustrates that the 3D media could be partially polarized across the thickness, resulting in a multilevel signal conﬁguration. On the contrary, it is known that in conventional recording the magnetization remains in one of the two saturated states and no partial polarization is feasible. To further perfect the concept of generating a multilevel signal, various types of media have to be developed and explored. However, media development is not the main subject of this chapter. Instead, the focus is placed on the system integration.

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185

Figure 6.7. (a) A schematic illustrating a two-layer 3D media. (b) A MFM image of a patch on the surface of FIB-fabricated CoCrPt-based two-layer 3D media. A digitized sectional proﬁle of the signal along the highlighted line is shown above the AFM/MFM images.

6.2.5. Design of a New Multilevel Magnetic System The general task is maximizing the number of signal levels while maintaining SNR between the signal values in each pair of adjacent levels above approximately 5 dB. The 5 dB value is dictated by the requirements of the novel data encoding methods, as described below. The magnetic system probably would be further modiﬁed and optimized with the goal to maximize the number of ‘‘distinguishable’’ signal levels.

6.2.5.1. Modiﬁcation of a Magnetic System. As mentioned earlier, it is assumed that the material science underlying the new media type has been studied in the prior related work. To formulate the approach in one expression, it is necessary to develop media in which each magnetic grain could be recorded independently (without a chain clustering effect). In fact, a conventional CoCrbased composition (as used in conventional longitudinal recording media) could be used for this purpose, and the media could be made even thicker to fully maximize the effective number of individual Co grains participating in the process. The focus of this chapter is directed towards engineering a new system to address the above described requirements on multilevel recording. In other words, the chapter is aimed at designing a system with substantially increased recording and sensitivity ﬁelds (used for writing and reading information, respectively), thus enabling adequate SNR to accommodate as many signal levels as possible, with 5 dB difference between any two adjacent levels. The data encoding methods proposed in the chapter are aimed at providing sufﬁcient bit error rates for maintaining SNR of the order of 5 dB.

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6.2.5.2. Patterned Soft Underlayers and Interlayers. The main motivation underlying the system modiﬁcation described below is to substantially increase the maximum recording ﬁeld, Hmax, so that the range of the ﬁeld, Hmax to +Hmax, controlled via the variation of the drive current could also be substantially increased. Traditionally, SUL has a ﬂat surface boundary with the recording layer. The image model could be used to describe the effect of SUL on the recording ﬁeld within the recording layer (Fig. 6.8a) [47, 48]. Ideally a factor-of-two increase in the ﬁeld is expected, although from the same image model one could observe that the image is located further away from the center of the recording layer as compared to the real head. The difference between the separations of the real and image heads from the center of the recording layer (the spacing loss) is B equal to the thickness of the recording layer. The closer to the recording media the head is placed, the stronger and more localized the recording ﬁeld would be in the media. Because the image head is located further away compared to the real head, the net effect will result in a deteriorated signal compared to the signal, due to two equally separated heads. The reciprocity principle states that the detrimental effect exists for both write and read processes [49]. The following concept is proposed to resolve the spacing loss issue. One could recall that magnetic imaging is very much like regular mirror imaging [50]. Therefore, exactly as in the case of a convex mirror, one could use a SUL with a convex boundary to move the image closer to the ‘‘mirror’s’’ (SUL’s) boundary with the recording layer [51]. To illustrate this effect, a diagram comparing the positions of the images in the two cases is shown in Figure 6.8b. Using a convex SUL instead of a ﬂat SUL could make the image head ‘‘be closer’’ to the recording layer and thus increase the areal density. Based on the above described concept, it is proposed to use a patterned SUL with each patterned island having a convex shape. Patterning is necessary to implement the novel concept on the physical scale of one bit. The cross-sectional dimensions of each patterned island correspond to the cross-sectional dimensions of the targeted bit cell. For example, for an areal density of 1 Tbit/in2, assuming a square symmetry in the plane, each of the (x and y) period values T should be approximately 26 nm. Via numerical simulations, it has been discovered that this favorable effect exists not only for patterns with convex islands but also for patterns with rectangular islands (Fig. 2.8c) [52]. This is attributed to the combined effect of patterning and periodicity. Both continuous (conventional) and patterned recording layers could be integrated with a patterned SUL, as shown in Figure 6.9a and b, respectively. Patterning in the latter case combines the described below advantages of patterned SULs with the well known advantages of patterned recording layers [53]. The key practical advantages due to the use of a convex patterned SUL are the following and described below in detail: SNR drastically increases, as demonstrated below. Patterning of SUL increases both the recording and sensitivity ﬁeld gradients. The latter is critical for maximizing the areal density during writing and reading, respectively.

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6.2. MULTILEVEL MAGNETIC RECORDING

Real head Recording layer Sreal

Central plane of the recording layer

Simage ‘Image’ head

SUL boundary

δ

SUL Note: Spacing loss due to the SUL is Simage − Sreal = δ. (a) Real head SUL boundary Recording layer

H

H>

Image head

SUL

SUL

(b) Disk substrate Pattern

Rotation direction (c)

Figure 6.8. (a) A diagram of an image model to illustrate the spacing loss due to the offset in the separation between the real and image heads with respect to the central plane of the recording layer. (b) A schematic illustrating the ‘‘move’’ of the image closer to the recording layer if a convex SUL boundary is used. (c) Patterned SUL with rectangular islands.

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Continuous recording layer Recording head Recording layer Patterned SUL (a)

Patterned recording layer Recording head Recording layer Patterned SUL (b)

L P

T (period)

x-direction

(side band)

(c)

Figure 6.9. Drawings illustrating integration of a patterned SUL with (a) a continuous recording layer and (b) a patterned recording layer. (c) A schematic diagram of the cross-section of a convex patterned SUL in X-direction.

The recording and sensitivity ﬁelds remain well localized across the entire thickness to generate a multitude of signal levels. The period of the grid T in each direction corresponds to the bit cell dimension in this direction and thus deﬁnes the effective areal density D as 1/T2 (bit/in2) (Fig. 6.9c). Below, it is shown that at a given grid period, the thickness of the island, L, could relatively and sensitively control the advantageous effects of the patterned SUL. To simplify the description, below the ratio of the grid period to the island thickness L/T is arbitrarily deﬁned as the pattern ‘‘curvature.’’ Increased SNR: Figure 6.10a illustrates the simulated perpendicular recording ﬁeld versus the distance along the line from the top surface of the patterned SUL to the ABS of the head (from point s to point e in Fig. 6.10b) at saturation for three ‘‘curvature’’ values of the patterned SUL. The three sets of three parameters, T, P, and L, are 1) 98, 2, and 200 nm, 2) 98, 2, and 100 nm, and 3) 98, 2, and 25 nm, for curvature values of 1, 2, and 4, respectively. Curvature values 1 and 4 correspond to the sharpest and ﬂattest surfaces of the island, respectively. In all these cases, the head is centered with respect to an island in the patterned SUL, as shown in Figure 6.10b. For comparison, the solid black line in the ﬁgure shows an equivalent ﬁeld line for the case of a conventional ﬂat-surface continuous SUL. A pronounced increase of the recording ﬁeld near the top SUL boundary could be observed, especially for a curvature of 1. While in the case of a conventionally ﬂat SUL, the ﬁeld reaches its maximum at the air bearing surface of the head, in the case of a patterned SUL, the ﬁeld reaches its maximum in the vicinity of SUL. The recording ﬁeld at SUL exceeds 30000 Oe, while at the air bearing surface of the head it barely reaches 15000 Oe. For the conventionally ﬂat SUL, the ﬁeld is less than approximately 12500 Oe when it reaches the surface of SUL. Such an increase (by a more than a factor of two) of the recording ﬁeld in the region of the recording layer means that a recording media with substantially higher anisotropy could be used and thus substantially higher recording densities could be achieved. The fact that the ﬁeld reaches its maximum at the side of the recording layer farthest away from the ABS is especially favorable for 3D recording. As described above, the most trivial form of recording across the thickness of 3D media could

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6.2. MULTILEVEL MAGNETIC RECORDING

Hz (Oe) 50000

Bottom and top surfaces of the recording layer

Curv 1

45000 40000

Head

Recording

SUL layer

35000

ABS surface of the recording head

Curv 2

30000

Curv 3

25000

Flat

20000 15000 10000

−2

0

2

4

6

8

10 12 14 16

Distance across the thickness (nm) (a)

Z-axis

Recording head Recording layer

Field profile line L

Recording head

Offset

b a SUL T (period)

P (side band)

(b)

X-axis

Field profile line

b a

L

X-axis SUL

T (period)

P (side band)

(c)

Figure 6.10. (a) The perpendicular recording ﬁeld versus the distance along the line from the top surface of the SUL to the air bearing surface of the head for three different values of the curvature of the semispherical island in the SUL type under study. For comparison, an equivalent dependence for a regular ﬂat SUL is also shown. Diagrams showing the location of the recording head with respect to an island in the convex patterned SUL (b) with the head and the island perfectly centered and (c) with a half-period offset line between the head and the island.

be achieved via sequential recording from the bottom up via continuous variation of the current in the drive coil. Patterning of SUL provides another knob to control the recording ﬁeld. As seen in Figure 6.10a, at a given value of the current, the ﬁeld maximum could be shifted from the bottom to the top side of the recording layer via variation of the softness of SUL. Moreover, the investigators propose to use soft interlayers (SIL) to separate magnetic layers across the thickness. As illustrated below, the use of SILs is expected to facilitate recording across the thickness substantially, thus further increasing the number of distinguishable signal levels. Proﬁles of the simulated recording ﬁeld along a track line in the recording layer 2.5 nm away from the top surface of SUL (Figure 6.10b, c) for a patterned

190 CHAPTER 6: MULTILEVEL AND THREE- DIMENSIONAL NANOMAGNETIC RECORDING

Patterned SUL 15000

Flat SUL 10000

10000

5000

5000

0

0 −80 −60 −40 −20 0

20 40 60 80

Hz (Oe)

15000

Hz (Oe)

SUL and a conventional (ﬂat) SUL are shown in Figure 6.11a. Although for the patterned SUL the recording ﬁeld drops with the distance away from SUL, it is still larger compared to the ﬁeld in the conventional case. The graphs also indicate that patterning of SUL would result in a more localized ﬁeld. The latter effect is discussed below in more detail. Study of the Localization of Recording and Sensitivity Field: Patterning of SUL is fundamentally different from patterning of the recording layer with respect to addressing information during writing and reading. Here, it could be reminded that SUL is an indispensable part not only of the media but also of the head [54]. The latter is not true for the recording layer. This major difference is due to the fact that SUL is made of a ‘‘soft’’ magnetic material. This is in contrast with the recording layer, which is made of a ‘‘hard’’ magnetic material. As a result, patterning of SUL effectively also ‘‘patterns’’ the ﬁeld generated by the head. This ﬁeld is the recording magnetic ﬁeld or the sensitivity ﬁeld depending on the writing or reading processes, respectively. To illustrate ‘‘patterning’’ of the recording ﬁeld because of patterning of SUL, two different locations of the recording head with respect to the patterned SUL are considered, as shown in Figure 6.10b and 6.10c, respectively. In the ﬁrst case,

Centered head Half-period offset head

−80 −60 −40 −20 0

20 40 60 80

Distance across track (nm)

Distance across track (nm)

(a)

(b)

Head

Field pattern

Head

Field pattern

Recording layer

Patterned SUL

(d)

(c)

Figure 6.11. (a) Field proﬁles inside the recording layer for the cases of patterned and conventional SUL. (b) The ﬁeld proﬁles along same line, 5 nm away from the surface of SUL, along a patterned direction along or across the track. The recording ﬁeld proﬁles for two systems, (c) with a patterned SUL and (d) without a SUL, respectively.

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6.2. MULTILEVEL MAGNETIC RECORDING

the recording head is centered with respect to an island of the patterned SUL. In the second case, the recording head is centered with respect to a groove between two adjacent islands. In other words, in the second case, the head is a half-period offset with respect to an island. The respective ﬁeld proﬁles along same line, 5 nm away from the surface of SUL, along a patterned direction are shown in Figure 6.11b. The fact that the ﬁeld proﬁles are so different from each other clearly indicates the above mentioned process of ‘‘patterning’’ the recording ﬁeld. One can observe the ﬁeld in the centered case is larger (by more than a factor of two) and substantially more localized compared to the ﬁeld in the off-centered case. This means that the head itself is going to substantially improve its recording quality when it is recording information in the favorite positions (compared to any off-centered positions). This is in contrast to the conventional recording process in which the recording ﬁeld proﬁle does not depend on the location of the head with respect to the media, regardless of whether the media being patterned or not. Improved Localization of Recording and Sensitivity Field across the Thickness: Furthermore, the effective ﬁeld patterning, as described above, takes place across the entire thickness of the recording media. In other words, the recording and sensitivity ﬁelds could be strongly localized not only at the air bearing surface of the head but also across the entire thickness of the recording layer. Figure 6.11c and d illustrate the recording ﬁeld proﬁles for the two cases of a recording system with a patterned soft underlayer and without a SUL, respectively. In the latter case, one could notice the great divergence of the ﬁeld away from the air bearing surface of the head. As described below, this concept can be extended to further increase the effective number of active layers by introducing so called soft interlayers (SIL) between adjacent layers. How Patterned SUL Would Help Read Across the Media Thickness: As a simulation input, two types of information were prerecorded into the top and bottom layers of 3D recording media with a net thickness of 50 nm (Figure 6.12a). The ‘‘softness’’ of a patterned SUL was controlled via continous variation of SUL’s bias current, as deﬁned above. The respective signal proﬁles, read back at biasing current values of 5.85 and 1.56 A-turn, respectively, (Figure 6.12b) indeed

Top layer

Bottom layer

(a)

Parallel set of signals read back at Ibias = 5.85 and 1.56 (A turn)

(b)

Figure 6.12. (a) Prerecorded magnetization in the top and bottom layers of a 20-layer recording media. (b) Sets of signals read back at a SUL’s biasing current of 5.85 and 1.56 A-turn.

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Transducer location Recording layers SILS

SUL Line cross thickness (a)

Hz (a.u.)

Soft Interlayers

Distance across the thickness (a.u.) Transducer location (b)

Figure 6.13. (a) Diagram and (b) simulations to illustrate how the ﬁeld could be ‘‘discontinued’’ in the region of SILs. (c) Diagrams of various bit conﬁgurations to illustrate the effect of the stray ﬁeld on the intersymbol interference.

strongly remind the prerecorded patterns. One notices here that various deconvolution based signal encoding techniques could be implemented to further optimize SNR of a multilevel system [55]. How Soft Interlayers Could Be Used to Further Separate Individual Layers across Thickness: The purpose of SILs is to create ﬁeld ‘‘discontinuities’’ to facilitate information access not only in the top and bottom layers but also in the intermediate layers. Each SIL is patterned with a pattern reﬂecting the pattern of SUL (Figure 6.13a). Numerical simulations showed that a thickness (of SIL) of smaller than 2 nm is sufﬁcient to create a detectable ‘‘discontinuity’’; at the same time it is not too thick to totally shield the ﬁeld from penetrating across the thickness. A typical ﬁeld proﬁle across the thickness of the media with adjacent magnetic layers separated from each other with a 2-nm thick SIL is shown in Figure 6.13b. The thickness of the magnetic layers and SILs could be optimized to maximize the effective number of layers.

6.3. MULTILEVEL DATA ENCODING Before going into details of the new multilevel coding method, it may help to recall how conventional coding works.

6.3.1. Summary of Conventional Encoding Methods FM encoding has a simple one-to-one correspondence between the bit to be encoded and the ﬂux reversal pattern. One needs only to know the value of the current bit. So called modiﬁed frequency modulation (MFM) improves encoding efﬁciency over FM by controlling more intelligently where clock transitions are added into the data stream; this is enabled by considering not just the current bit but also the one before it. This ‘‘looking backwards’’ allows improved efﬁciency by letting the controller consider more data in deciding when to add clock

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193

reversals. Run limited length (RLL) encoding takes this technique one step further. It considers groups of several bits instead of encoding one bit at a time. The idea is to mix clock and data ﬂux reversals to allow for even denser packing of encoded data and thus improve efﬁciency. The two parameters that deﬁne RLL are the run length and the run limit (and hence the name). The word ‘‘run’’ here refers to a sequence of spaces in the output data stream without ﬂux reversals. The run length is the minimum spacing between ﬂux reversals, and the run limit is the maximum spacing between them. As mentioned before, the amount of time between reversals cannot be too large or the read head can get out of sync and lose track of which bit is where. Finally, the so called partial-response maximum likelihood (PRML) sequence detection is even more advanced and is today’s most common method. Partial-response means controlled inter-symbol interference (ISI). That is, the data represented by the received waveform are packed so closely together that they overlap (interfere). The ‘‘controlled’’ part means that there is some identiﬁable structure to the overlapping. This structure is ‘‘taught’’ to a sophisticated sequence detector that looks only for the possible controlled patterns of ISI in the received waveform. This provides a much more robust detection method in the presence of noise. This type of detection is often used with trellis coding to further improve detection. Trellis coding encodes the data such that the possible received sequences that are most similar are not used. This provides extra capability to distinguish between received waveforms in the presence of noise and distortion.

6.3.2. New Error-Correcting Techniques for Multilevel Magnetic Recording In the previous sections, it is shown that multilevel recording can substantially increase the capacity of storage systems versus its conventional two-level counterpart. On the other hand, multilevel recording reduces the separation between different amplitude levels (given the same power constraints), which can make the entire system more error-prone as more data becomes incorrectly recorded or retrieved in the ‘‘read–write’’ channel. To address this problem, in this chapter, we intend to employ powerful error-correcting codes. In general, efﬁcient error correction can reduce the overall error rates by a few orders of magnitude, and this can also lead to higher recording densities in the entire storage system. Thus, error correction becomes an efﬁcient tool that can greatly reduce the errors caused by multilevel recording and higher densities. The main overhead caused by many error-correcting algorithms is their excessive complexity or—equivalently—prohibitively slow data processing. Therefore, our main goal in this part of this chapter is to design the error-correcting techniques that combine powerful error-correcting performance with fast, feasible processing. Namely, we intend to design the algorithms that approach optimum, maximum likelihood (ML) decoding without signiﬁcant degradation of the data transmission rate in the overall system.

194 CHAPTER 6: MULTILEVEL AND THREE- DIMENSIONAL NANOMAGNETIC RECORDING

The existing methods of code design can be divided into three different categories. In the ﬁrst group of graph-based techniques, a linear code is associated with some bipartite graph, with code symbols on the one side and their parity checks on the other. Iterative decoding is then used similar to belief propagation in neural networks. This method combines relatively simple processing and powerful performance; however, it becomes efﬁcient only on the relatively long blocks of thousand bits. The lack of analytical tools required to estimate low output error rates (of 1012 and less) is another drawback of iterative techniques. The second group employs algebraic methods. Here a code consists of a set of polynomials of some limited degree taken over a Galois ﬁeld; a string of all values of a speciﬁc polynomial is called a codeword. This technique is especially efﬁcient for large (nonbinary) alphabets and leads to the optimum Reed–Solomon (RS) codes, which are currently designed into most storage systems. However, RS codes have relatively high complexity in correcting multiple errors. This excessive complexity combined with long operations in Galois ﬁelds can slow down the overall performance, especially in multilevel signaling, which requires multiple error correction. Finally, the third group consists of various concatenated techniques, which combine good short codes into the longer ones. Invented by Forney over 40 years ago, this technique still manifests itself as one of the most efﬁcient, thanks to simple decoding procedures of multiple error correction. To further reduce decoding complexity, we intend to design new concatenated techniques using simple constituent codes.

6.3.3. Reed–Muller Codes and Their Recursive Decoding The technique that will be used in the project has some similarities with general concatenated design. The main new feature will employ constituent codes that can be considered as ‘‘self-contained’’ recursive constructions. Such constructions— already known in coding theory—preserve all the properties of the shorter, building codes. These recursive techniques result in a simple, low complexity decoding, which repeatedly employs the same code properties multiple times on increasing lengths. Reed–Muller (RM) codes represent the most notable example of recursive constructions and have been explored for ﬁve decades. These codes also yield a simple recursive decoding, which has been recently designed and analyzed in papers [56–59]. Namely, any RM code (m, r) of length n=2m and distance d=2mr can be obtained from the two RM codes (m1, r1) and (m1, r) 1 of length n/2. The decoding process can be relegated further using four RM codes of length n/4. After a few steps, the decoder ﬁnally arrives at the trivial end codes RM(mr, 0) or RM(r, r), which are either fully redundant (repetition codes) or nonredundant (full codes). For both types, it is easy to use powerful ML decoding. On the other hand, the received channel symbols are only recalculated in all intermediate recursive steps without any decoding. Due to this, decoding

195

6.3. MULTILEVEL DATA ENCODING

100 Uncoded k = 37, I(Δ) = 64 k = 93, I(Δ) = 128 k = 163, I(Δ) = 128 k = 219, I(Δ) = 16

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Figure 6.14. (a) Exact bounds on word error rates (WER) for ML decoding of RM codes of orders 2 to 5 on the length 256. The legend includes the list sizes l(D), for which recursive permutation algorithm performs within D = 0.25 dB from ML decoding. (b) Word error rates (WER) for the (512, 101)-subcode of the (512, 130) RM code of order 3. Different curves represent WER for recursive list decoding for varying lists L.

196 CHAPTER 6: MULTILEVEL AND THREE- DIMENSIONAL NANOMAGNETIC RECORDING

100 Uncoded 32x64, k = 592, L = 1 32x64, k = 592, L = 16 32x64, k = 592, L = 64 32x64, k = 592, L = 256

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Figure 6.15. (a) Concatenated (n, k) code of length n = n1 n2 = 2048, with variable lists of size L. (b) Concatenated (n, k) codes of length n = n1 n2 = 4096, with variable lists of size L.

6.4. CONCLUSIONS

197

complexity has a low order of n log n or even a linear order n if incomplete hard decision decoding is concerned. This combination of powerful end decoding and fast intermediate processing outperforms all other nonexponential algorithms known for RM codes. In particular, it turns out that the algorithms of [56–58] substantially outperform the two conventional techniques of bounded distance decoding and majority decoding. Namely, new recursive techniques increase 1n d times the number of errors d/2 corrected by bounded-distance decoding (for most error patterns); double the number of errors (d 1n d )/4 corrected (with high probability) by conventional majority decoding; for the moderate lengths of 128 to 512, these techniques were enhanced in [4] with list decoding, which gives near-optimum performance (within 0.25 dB of ML decoding) with feasible complexity; outperforms all other decoding algorithms currently known for all existing codes. Some results are given below in Figure 6.14a and b for different RM codes of lengths 256 and 512, respectively. An important conclusion is that RM codes yield near-optimum performance and fast processing with complexity of order n log n. Then in Figure 6.15a and b, also the results for longer blocks obtained by concatenating different RM codes are plotted. In summary, these data illustrate that concatenated RM codes combine fast feasible processing and very low SNR of 2 to 3 dB on the Gaussian channels for various block lengths of 256 to 4000 bits. These algorithms could be further enhanced in the future to correct speciﬁc (nonGaussian) error models that pertain to magnetic recording channels.

6.4. CONCLUSIONS This chapter outlines multidisciplinary research to develop a multilevel mode of next-generation magnetic recording, a promising and challenging solution to increasing the capacity of electronic and computer devices. The study is conducted from the system perspective. It is anticipated that through marrying the expertise in magnetic recording and state-of-the-art data encoding, the proposed multilevel magnetic recording approach could be applied to any alternative magnetic data storage technology to further increase its data capacity by several factors. The key to the multilevel system is exploitation of the recently proposed concept of threedimensional media optionally with patterned soft magnetic underlayer and interlayers. Among the unique properties are the substantially increased (compared with conventional technologies) recording and sensitivity ﬁelds used for writing and reading information, respectively. This ﬁeld increase results in adequate signal to noise ratio (SNR) to accommodate over 40 signal levels with 5 dB difference

198 CHAPTER 6: MULTILEVEL AND THREE- DIMENSIONAL NANOMAGNETIC RECORDING

between any two adjacent levels. The proposed data encoding methods are aimed at providing sufﬁcient bit error rates for a system with a SNR of the order of 5 dB.

ACKNOWLEDGMENTS The authors would like to aknowledge the insighful discussions with Dr. Michael Alex of Hitachi Research and the continous support by the research groups led by Song Xue of Seagate Technology, Steve Lambert of Hitachi Global Storage Technologies, and Robert Haddon of Center for Nanoscience Innovation for Defence (CNID), University of California, Riverside. This work is partially supported by four grants from the National Science Foundation (NSF): ECS0401297, ECS-0508218, ECS-0404308, and IIP-0712445, respectively; two grants from the U.S. Air Force Ofﬁce of Scientiﬁc Research (AFOSR): FA9550-04-10446 and FA9550-05-1-0232, respectively; and one grant co-sponsored by Defence MicroElectronics Activity (DMEA) and Defence Advanced Research Project Agency (DARPA): DOD/DMEA-H94003-06-2-0608.

REFERENCES 1. D. A. Thompson and J. S. Best. The Extendibility of Magnetic Recording for Data Storage. IBM executive brieﬁng: Jan 1998. 2. M. H. Kryder. Data storage technologies for advanced computing. Scientiﬁc American, 117 p 72, 1987. 3. S. H. Charap, P. L. Lu, and Y. He. Thermal stability of recorded information at high densities. IEEE Transactions on Magnetics, 33(1): pp 978–983, 1997. 4. N. H. Bertram and M. Williams. SNR and density limit estimates: a comparison of longitudinal and perpendicular recording. IEEE Transactions on Magnetics, 36(1): p 4, 1999. 5. S. Iwasaki and Y. Nakamura. An analysis for the magnetization mode for high density magnetic recording. IEEE Transactions on Magnetics, 13 p 1272, 1977. 6. S. Khizroev, M. H. Kryder, Y. Ikeda, K. Rubin, P. Arnett, M. Best, and D. A. Thompson. Recording heads with trackwidths suitable for 100 Gbit/in2 density. IEEE Transactions on Magnetics, 35(5): pp 2544–2546, 1999. 7. M. Albrecht, C. T. Rettner, A. Moser, M. E. Best, and B. D. Terris. Recording performance of high-density patterned perpendicular media. Applied Physics Letters, 81(15): pp 2875–2877, 2002. 8. C. Chappert, H. Bernas, J. Ferre´, V. Kottler, J. P. Jamet, Y. Chen, E. Cambril, T. Devolder, F. Rousseaux, V. Mathet, and H. Launois. Science, 280 p 1919, 1998. 9. D. Weller and A. Moser, IEEE Transactions on Magnetics, 35 p 4423, 1999. 10. H. F. Hamann, Y. C. Martin, and H. K. Wickramasighe. Thermally assisted recording beyond traditional limits. Applied Physics Letters, 84(5): p 810, 2004. 11. P. C. Arnett, D. C. Cheng, S. Khizroev, and D. A. Thompson, inventors; IBM Almaden Research Center, assignee. Track width control of readback elements via ion

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30. D. A. Thompson. The role of perpendicular recording in the future of hard disk storage. Journal of the Magnetics Society of Japan, 21(S2): p 9, 1997. 31. F. Liu, K. Stoev, P. Luo, Y. Liu, Y. Chen, J. Chen, J. Wang, F. G. Shan, K. T. Kung, M. Lederman, M. Krounbi, M. Re, A. Otsuki, and S. Hong. Perpendicular recording heads for extremely high-density recording. IEEE Transactions on Magnetics, 39(4): pp 1942–1948, 2003. 32. S. Khizroev and D. Litvinov. Perpendicular Magnetic Recording. Amserterdam: Kluwer, 2004. 33. T. McDaniel and W. Challener. Issues in heat-assisted perpendicular recording. IEEE Transactions on Magnetics, 39(4): pp 1972–1979, 2003. 34. F. Chen, A. Itagi, J. A. Bain, D. D. Stancil, and T. E. Schlesinger. Imaging of optical ﬁeld conﬁnement in ridge waveguides fabricated on very-small-aperture laser. Applied Physics Letters, 83(16): p 3245, 2003. 35. J. Wong, A. Scherer, M. Todorovic, and S. Schultz. Farbrication and characterization of high aspect ratio perpendicular patterned information storage media in an Al2O3/ GaAs substrates. Journal of Applied Physics, 85 p 5489, 1999. 36. E. D. Boerner, H. N. Bertram, and G. F. Hughes. Writing on perpendicular patterned media at high density and data rate. Journal of Applied Physics, 85 p 5318, 1999. 37. S. Khizroev, Y. Hijazi, N. Amos, D. Doria, A. Lavrenov, R. Chomko, T. M. Lu, and D. Litvinov. Three-dimensional magnetic recording: an emerging nanoelectronic technology. Journal of Nanoelectronics and Optoelectronics, 1 pp 1–18, 2006. 38. S. Khizroev, R. Chomko, Y. Hijazi, and N. Amos. Three-dimensional magnetic recording devices. Pentagon report: Report # A752434, 2005. 39. M. Albrecht, G. Hu, A. Moser, O. Hellwig, and B. D. Terris. Magnetic dot arrays with multiple storage layers. Journal of Applied Physics, 97 p 103910, 2005. 40. M. Albrecht, G. Hu, A. Moser, O. Hellwig, and B. D. Terris. Magnetic dot arrays with multiple storage layers. Journal of Applied Physics, 97 p 103910, 2005. 41. S. Khizroev and D. Litvinov. Perpendicular Magnetic Recording. Amsterdam: Kluwer, 2005. 42. D. Litvinov, M. Kryder, and S. Khizroev. Recording physics of perpendicular media: soft underlayers. Journal of Magnetism and Magnetic Materials, 232(1–2): pp 84–90, 2001. 43. S. Khizroev, M. H. Kryder, Y. Ikeda, K. Rubin, P. Arnett, M. Best, and D. A. Thompson. Recording heads with trackwidths suitable for 100 Gbit/in2 density. IEEE Transactions on Magnetics, 35(5): pp 2544–2546, 1999. 44. D. Litvinov and S. Khizroev. Orientation-sensitive magnetic force microscopy in future probe storage applications. Applied Physics Letters, 81(10): p 1878, 2002. 45. F. Candocia, E. Svedberg, D. Litvinov, and S. Khizroev. Deconvolution processing for increasing the resolution of magnetic force microscopy measurements. Nanotechnology, 15: p S575–584, 2004. 46. D. Litvinov, M. Kryder, and S. Khizroev. Recording physics of perpendicular media: recording layers. Journal of Magnetism and Magnetic Materials, 241(2–3): pp 453–465, 2002. 47. B. D. Cullity. Introduction to Magnetic Materials. Reading, MA: Addison-Wesley, 1972. 48. Yu. B. Sidorov, M. B. Fedoryuk, and M. I. Shabunin. Lectures on Theory of Functions of Complex Variables. 1989. Need publisher.

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7 SPIN-WAVE ARCHITECTURES Mary Mehrnoosh Eshaghian-Wilner, Alex Khitun, Shiva Navab, and Kang L. Wang In this chapter, we present three nanoscale architectures: the reconﬁgurable mesh, crossbar, and fully interconnected cluster. In these architectures, both communication and computation are performed using spin waves. These architectures are capable of simultaneously transmitting multiple waves over different frequencies. In addition, they can use the superposition property of the waves and allow for concurrent writes. In these architectures, computation can be done in both analog and digital modes. On the other hand, one shortcoming of the spin-wave architectures is the limitation on the attenuation length of spin waves, about 50 microns. To address this issue, a hierarchical multiscale design is proposed that is an integration of the spin-wave modules within a MEMS architecture.

7.1. INTRODUCTION Spinwaves have been attracting scientiﬁc interest for a long time, but only recently several experimental types of projects have been devoted to the problem of spinwave detection using the inductive voltage measurement technique [1, 2]. The results indicate that spin-wave packets propagating in a 100 nm thick ferromagnetic ﬁlms may produce an inductive voltage in the order of several mV, suitable for experimental detection [1]. The inductive voltage measurement technique appears to be one of the most convenient physical methods for spin-wave detection and integration in a semiconductor platform. The authors of this chapter are listed alphabetically. Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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The use of spin waves for computation is an entirely new idea. The ﬁrst computational architecture utilizing spin waves was for massive entanglement of distant spin-based qubits in a quantum computer as described in [3, 4]. In this research, spin waves are used for both information transmission and information processing. Moreover, the classical type of computing is employed as opposed to quantum, and the architectures are operable at room temperature. In the following section, we present three spin-wave architectures: crossbar, reconﬁgurable mesh, and fully interconnected cluster. Afterward, we explain our experimental results.

7.2. SPIN-WAVE ARCHITECTURES In the following section, after a brief introduction to spin waves, we present three nanoscale spin-wave architectures: nanoscale crossbar, spin-wave reconﬁgurable mesh, and spin-wave fully interconnected cluster. Then, to address the size limitation of spin-wave architectures, we propose a multiscale hierarchical architecture. Spin wave is a collective oscillation of spins in an ordered spin lattice around the direction of magnetization. The phenomenon is similar to the lattice vibration, where atoms perform oscillation around its equilibrium position. In other words, a collection of electron spin precessions about the magnetic ﬁeld is a spin wave [5], as shown in Figure 7.1. The magnitude of the spin wave is determined by precession angle. A propagating spin wave changes the local polarization of spins in the ferromagnetic material. In turn, the change in magnetic ﬁeld results in an inductive voltage. Recently published experimental results indicate that an inductive voltage signal of the order of mV produced by spin waves propagating through a nanometer thin ferromagnetic ﬁlm are detectable at the distances of up to 50 microns at room temperature. Our idea is to use the phase of the spin wave for both information exchange and information processing [6]. Typically, the speed of the spin wave is 104 m/s. In the current experimental results, the switching frequency is in the order of GHz, but up to the order of THz is possible. As mentioned above, the attenuation of spin waves is around 50 microns, which makes it a suitable candidate for nanoscale communication. In the following section, we show how spin waves can be used in implementing nanoscale architectures.

7.3. SPIN-WAVE CROSSBAR In this section, a nanoscale crossbar architecture that is interconnected with ferromagnetic spin-wave buses is introduced [7, 8]. The power consumption of

Figure 7.1. Spin wave: a collective oscillation of spins.

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these proposed modules is relatively low, and the classical type of computing, as opposed to quantum, is employed. By using phase logic, simple operations such as AND/OR/NOT can be performed efﬁciently on the transmitted waves. Signal detection is accomplished by the time-resolved inductive voltage measurement technique. In this structure, the sphere of interactions is limited by the spin-wave attenuation length; therefore, it is suitable to be used as nanoscale computing modules that can be ported or integrated onto higher-scale chips or devices. The architecture described here, while requiring the same number of switches as a standard crossbar, is capable of simultaneously transmitting N waves on each of the spin-wave paths. As compared to the known molecular crossbars, this design is fault tolerant: In case there is a failure in one of the N channels, any of the other channels can be reconﬁgured to transmit the data. This is possible since all the channels are accessible by all the ports and each channel can handle multiple data. Crossbars are attractive architectures because they can realize any permutations of N inputs to N outputs. However, their main shortcoming is due to the fact that N2 switches are used to transmit only N pairs of data. As mentioned earlier, each spin-wave bus is capable of carrying multiple waves at any point of time. Therefore, each of the N inputs can broadcast its data to all of the N outputs in parallel. Using this type of architecture, it would be possible to efﬁciently realize highly connected types of computations such as the Hopﬁeld Neural Network model, as shown in [9]. An example of the proposed spin-wave crossbar architecture is shown in Figure 7.2. A set of column spin-wave buses on the bottom and a set of row spin-wave buses on the top are connected via the vertical spin wave switches. An important element required for the spin-wave crossbar is the spin-wave switch. We deﬁne a spin-wave switch as a device that has an externally controllable magnetic phase. In the ‘‘On’’ state, the switch transmits spin waves;

Spin-wave crossbar architecture

VI+1 VI Insulator F(VI,VI)

p-dopedDMS Insulator

VI−1

VI

VI+1

VI+2

Figure 7.2. Spin-wave crossbar architecture.

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in the ‘‘Off’’ state, it reﬂects any incoming spin wave. A possible structure of the spin-wave switch is shown in Figure 7.3. A ferromagnetic ﬁlm is divided by a region of diluted magnetic semiconductor (DMS) used as a magnetic channel; the magnetic phase is controlled by the applied electric ﬁeld via the effect of hole-mediated ferromagnetism [10]. Figure 7.3a shows the cross-section of a metal-insulator-diluted magnetic semiconductor structure that is used for experimental study of the effect of hole-mediated ferromagnetism in [10]. A negative gate bias increases the hole concentration in the DMS region, resulting in the paramagnetic-to-ferromagnetic transition, whereas a positive bias has an opposite effect (as shown in Fig. 7.3b). The cross-section of the spin-wave switch is shown in Figure 7.3c. The ferromagnetic ﬁlm is divided by the DMS cell. Spin waves can propagate through the DMS cell only if it is in the ferromagnetic phase. While in the paramagnetic phase, the DMS cell reﬂects all incoming spin waves. As it is shown, there is a common p-doped DMS layer for the whole structure. The magnetic phase in every region is controlled by the hole concentration. Using conducting ferromagnetic ﬁlms (NiFe, for example), it is possible to control the hole distribution along the structure by the applied electric ﬁeld. The hole concentration is high when both the top and the bottom ferromagnetic ﬁlms are

M VG MS Metal gate insulator

Ferromagnetic

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VG < 0

DMS

VS Magnetic ion

Hole

0 (b)

VG

(a) VG

Insulator DMS Spin wave

Ferromagnetic film S.I. Substrate (c)

Figure 7.3. DMS cells and ferromagnetic ﬁlm forming a spin-wave switch.

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biased by a negative voltage. There is a self-alignment mechanism that makes the proposed structure tolerant to structure imperfections. The detailed analysis of the spin wave switch can be done on the base of the Heisenberg model, treating the ferromagnetic ﬁlm and the DMS cell as two media having different exchange integrals J. The Hamiltonian for the system ferromagnetic ﬁlm plus DMS cell can be expressed as follows: H¼

X

~i S ~j ; Jij ½S

i;j

where J is the exchange integral for the nearest spins in the lattice. The propagation/reﬂection of spin waves through the interface between the DMS cell and the ferromagnetic ﬁlm depends on the ratio JDMS/Jﬁlm, where JDMS and Jﬁlm are the exchange integrals for the DMS cell and the ferromagnetic ﬁlm, respectively. The exchange integral in the ferromagnetic ﬁlm is constant, while the exchange integral in the DMS cell is a function of the gate voltage JDMS JDMS(VG). In the two ultimate limits JDMS/Jﬁlm = 1 and JDMS/Jﬁlm = 0, we have complete transmission and complete reﬂection, respectively. The same structure of the spin-wave switch based on the effect of holemediated ferromagnetism may be used for the vertical integration of the spin-wave buses. In Figure 7.4 we have schematically shown two vertically separated ferromagnetic ﬁlms with a spin-wave switch in between. The switch serves as a connector between two spin-wave busses in this structure. At the negative applied bias (ferromagnetic phase), the switch allows spin wave propagate from one ﬁlm to another. At the positive bias (paramagnetic ﬁlm), spin waves can not propagate through. The use of the spin-wave switches for vertical integration makes possible array-based architectures similar to the one proposed for the array of nanowires [11]. The advantage of the proposed architecture is that signal information can be encoded in the phase of the propagating spin wave rather than in the number of electrons to be transmitted via conducting wires.

Feromagnetic buses

VG

Switch

Figure 7.4. Spin-wave crossbar with spin-wave switches.

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7.4. SPIN-WAVE RECONFIGURABLE MESH A nanoscale spin-wave reconﬁgurable mesh of size N2 consists of an N N array of processors connected to a reconﬁgurable spin-wave bus grid, where each processor has a locally controllable bus switch [12], as shown in Figure 7.5. In the proposed spin-wave reconﬁgurable mesh architecture with spin-wave buses, a set of column spin-wave buses on the bottom and a set of row spin-wave buses on the top are connected via the spin-wave switches. Each switch is placed at the grid point of the mesh, as shown in Figure 7.6. Basically, the nanoscale spinweave reconﬁgurable mesh is similar to the standard reconﬁgurable mesh, except for the spin-wave buses and switches. It is worth noting that, similar to the standard reconﬁgurable mesh, the nanoscale reconﬁgurable mesh of size N occupies N N area, under the assumption that processors, switches, and the link between adjacent switches occupy unit area. However, the main difference in terms of area here is that the unit of area is at nanoscale level as opposed to the standard reconﬁgurable meshes that are at microscale level of integration. Each of the spin-based devices serves as a one-bit input/output port. One spinwave packet excited by one port can be superposed with many packets generated by the nearby ports. The length of interaction among the spin-based devices is limited by the spin-wave attenuation caused mainly by the scattering on phonons. The length of interaction is deﬁned by the material properties of the ferromagnetic ﬁlm, ﬁlm size, and the operation temperature. According to our experimental data it can be as high as tens of microns.

i −1, j +1

i +1, j +1

i, j +1 “On”

Spin wave switch

i −1, j

i, j

“Off”

i +1, j

100 nm Spin-based device 100 nm i −1, j −1

i, j −1

i +1, j −1

Spin wave bus

Figure 7.5. Reconﬁgurable mesh architecture.

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7.5. SPIN- WAVE FULLY INTERCONNECTED CLUSTER

VG-W

N

W

VG-N E

VG-S S

VG-E

Figure 7.6. Reconﬁgurable spin-wave switches at the grid points of the mesh.

In Figure 7.7, the cross-section of the reconﬁgurable spin-wave switch is shown. A ferromagnetic ﬁlm is divided by regions of diluted magnetic semiconductor (DMS). The reconﬁgurable switches work based on the same mechanism as a regular spin-wave switch used in a crossbar architecture. The difference is that the reconﬁgurable switches are controlled by four different control signals to form 15 possible interconnections, as shown in Figure 7.8.

7.5. SPIN-WAVE FULLY INTERCONNECTED CLUSTER The architecture presented in this section is a nanoscale fully interconnected architecture [13]. In this architecture, each node can broadcast using spin waves to all other nodes simultaneously, and similarly, each node via spin waves can receive and process multiple data in parallel. The signiﬁcance of this design is that the communication between the nodes can be done in constant time. This is

Cross-plane view

Top view N VG - N

VG - W

W

VG - W

VG - S

E Ferromagnetic film

VG - S S

VG - E

Silicon substrate P + DMS duster

Figure 7.7. Reconﬁgurable spin-wave switches.

VG - E

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CHAPTER 7: SPIN- WAVE ARCHITECTURES

Figure 7.8. Reconﬁgurable spin-wave switch possible connections.

a signiﬁcant improvement considering the O(log N) lower-bound on the time delay for implementing such networks in VLSI using traditional electrical interconnects. Another key advantage is that the spin-wave fully interconnected network can be laid out in O(N2) area as opposed to O(N 4). Of course, the unit of area is in order of nanometer as opposed to the standard micron technology. In this architecture, information is encoded into the phase of spin waves, and no charge is transmitted. As a result of this, power consumption can be signiﬁcantly reduced in this architecture (compared to other nanoscale architectures). Figure 7.9 shows the top view of the architecture in which the N computing nodes are placed around a circle on a magnetic ﬁlm. Each node is an asymmetric coplanar strip (ACPS) line (described later in Section 7.7), which can be used as a sender or receiver at each point of time. Figure 7.10 shows the cross view of the layout of this architecture on a semiconductor chip. The area requirement of this architecture is O(N2), as opposed to the O(N 4) area requirement if electrical interconnects were to be used. We should also note that in this architecture all the distances are in nanoscale. Also unlike the network with electrical interconnections,

A B

L

K

C

J

D

E

I

F

H G

Figure 7.9. The top view of the architecture with full spin-wave interconnectivity.

211

7.6. MULTISCALE HIERARCHICAL ARCHITECTURE

Cross-section view ACPS line L

Ferromagnetic film A

B

K

C

Spine wave

Figure 7.10. Cross-section view of spin-wave fully interconnected cluster.

in which only one transmission can be done at a time, in this architecture, multiple simultaneous permutations are possible. This can be done by transmitting the spin waves over different frequencies. The information is coded into the phase of the spin waves in the sender and is detected by the receivers. In addition, within each frequency, data can be sent to one or more other nodes from each node. In the following we present a brief discussion on the placement of nodes and their intercommunication mechanism. Normally, in architectures where the phases of the waves are the means of information transmission, the exact location of the nodes with respect to the size of topology is an important design issue. The distance between the sender and receiver has to be a multiple of the wavelength; otherwise, the receiver might receive the wave at a different phase. For instance, if the wave is received with a p radian phase-shift, a ‘‘0’’ is received instead of a ‘‘1’’ or vice versa. In our design, however, this is not an issue since the wavelength of spin waves is considerably larger than the distance between the nodes. The speed of spin waves is around 105m/s. Assuming the input frequency range of 1–10 GHz, the wavelength will be in the order of 104 to 105 m, while the distances are at the nanoscale, or 109 m. In other words, the wavelengths of the spin waves are orders of magnitude greater than the distances between the nodes. Therefore, all the nodes receive the same phase regardless of their location, and there is no need to place the nodes at speciﬁc distance relative to the other ones.

7.6. MULTISCALE HIERARCHICAL ARCHITECTURE As mentioned earlier, the attenuation of a spin wave is about 50 microns, which dictates the maximum size of spin-wave architectures. In order to overcome this

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CHAPTER 7: SPIN- WAVE ARCHITECTURES

Reconfigurable mirror

Fixed mirror

RM

FM

Control unit

Transmitters

Reconfigurable switch

Receiver

Figure 7.11. The deﬂection unit in hierarchical multiscale architecture.

size limitation, we propose using a hierarchical multiscale architecture, which will embody the spin-wave modules described above. The proposed multiscale architecture is based on the optical reconﬁgurable mesh (ORM) architecture [14], which consists of two layers: the deﬂection layer and the processing layer. In this architecture, similar to ORM, the deﬂection layer consists of N2 deﬂecting units, while the processing layer consists of N2 processing units. In this architecture, in addition to the standard processing layer of ORM at microscale level, there is another processing layer at nanoscale level which consists of a set of spin-wave modules. These modules can be spin-wave crossbars, reconﬁgurable meshes, or fully interconnected clusters. Each deﬂecting unit consists of a ﬁxed mirror, a reconﬁgurable mirror, and a unit to control the direction of the reconﬁgurable mirror, as shown in Figure 7.11. Each processing unit at the microscale has an optical receiver, optical transmitters, and a regular reconﬁgurable electrical switch. These processing units are interconnected as a standard reconﬁgurable mesh and can also intercommunicate optically using the deﬂection layer. Data at the processing module level can be routed in three different ways: electrical routing through electrical buses, optical routing via free-space optical interconnections, and electro-optical routing that uses electrical and optical freespace connections to allow a complete connection among N processors [14]. Each of these routing mechanisms is described below, assuming we index the processing unit in the ith row and the jth column of the mesh as P(i, j) and the mirror above it as M(i, j), in which 1 r i, j r N.

7.6.1. Electrical Routing The electrical routing in ORM is similar to the routing in the standard reconﬁgurable meshes. This type of routing uses the electrical buses in the reconﬁgurable mesh for one-to-one routing or broadcasting. This type of communication is suitable for providing arbitrary conﬁguration of the buses in the processing layer.

7.6. MULTISCALE HIERARCHICAL ARCHITECTURE

213

7.6.2. Optical Routing The optical routing in ORM is the routing through optical free-space interconnections. The data transfer does not use any electrical bus in the system. All N2 processors can communicate in unit time delay as long as there is only one read or write from or to each location. In the following, we describe how such an optical connection is established between two processors through the RM. A connection phase consists of two cycles. In the ﬁrst cycle, each processor sends the address of its desired destination processor to the arithmetic control unit of its associated mirror using its dedicated laser. The arithmetic control unit of the mirror computes a rotation degree such that both the source and the destination processors have equal angle with the line perpendicular to the surface of the mirror in the plane formed by the mirror, the source processor, and the destination processor. Once the angle is computed, the mirror is rotated to point to the desired destination. In the second cycle, the connection is established by the laser beam, carrying the data from the source to the mirror and then from the reﬂected mirror towards the destination. The read operation has two phases. In the ﬁrst phase, the read requirement and the reader’s address are sent to the processor which stores the desired data. In the second phase, the data is sent back to the reader, depending on the reader’s address. Both phases use the two-cycle write routing method.

7.6.3. Electro-Optical Routing This communication mechanism establishes an efﬁcient full connectivity among only the N processors situated diagonally in the processing layer on the N2 processors in the ORM (i.e., for processors P(j, j) where 1 r j r N). This routing technique uses electrical buses on the processing layer and ﬁxed mirrors on the deﬂection layer. The connection for electro-optical routing is implemented as follows. Each processor P(j, j) is associated with the jth row of the deﬂection unit, where the row contains N ﬁxed mirrors. The ith ﬁxed mirror in that row for 1 r i r N is directed to the processing unit P(i, i). In an exclusive read exclusive write (EREW) scenario, any processing element P(i, i) sends data to P(k, k) in the following way: First, P(i, i) sends the data to P(i, k) through the electrical row bus; then, P(i, k) sends data to P(k, k) through the transmitter and its deﬂector M(i, k). The variety of techniques available in this architecture makes ORM a very powerful computing model [15]. In our proposed hierarchical multiscale architectures, the processing elements are interconnected using spin waves at the nanoscale level, and via ORM’s electrical, optical, or electro-optical routing at the microlevel [16]. Figure 7.12 shows this organization. As an example, an electro-optical routing is shown in Figure 7.12. In this routing, as mentioned previously no reconﬁguration of mirrors is necessary, and only ﬁxed mirrors are used. The data communication in each row is through

214

CHAPTER 7: SPIN- WAVE ARCHITECTURES

Deflection layer with microelectro mechanical mirrors Electro-optical Interconnects Microscale processing layer Nanoscale processing layer

Figure 7.12. The hierarchical multiscale architecture.

electrical interconnections, while the ﬁxed mirrors provide vertical paths among processors. Since only electrical switches and ﬁxed mirrors are used, this architecture has a switching time of nanoseconds. In the example shown in Figure 7.12, the electrical connection between P(4,1) and P(4,4) has been highlighted, and the electro-optical routing from processor P(1,1) to processor P(3,3) is shown. P(1,1) makes an electrical connection to P(1,3) while P(1,3) is connected to P(3,3) using M(1,3) ﬁxed mirror.

7.7. PRELIMINARY IMPLEMENTATIONS While the architectures presented in the previous section have not yet been fully implemented, we have some preliminary experimental results based on a simple prototype that is built and tested by our collaborators. The signiﬁcant point about these experimental results is that the architectures are operable at room temperature and currently have GHz switching speed. In the following, we ﬁrst show some numerical simulations that illustrate the functionality of a simple logic device. Next, our prototype and experimental results are presented, along with a theoretical discussion explaining the operation of the prototype.

7.7.1. Spin-Wave-Based Logic Devices Spin waves can be used to provide an ‘‘LC’’ coupling of devices, without dissipative resistance. With the spin-wave concept, the spin rotates as a propagating wave and there is no particle (electron/hole) transport. In Figure 7.13 we have schematically shown a prototype structure for spin-wave bus demonstration. The core of the structure consists of a ferromagnetic ﬁlm (NiFe, for example) grown on a semi-insulating substrate. The ﬁlm is polarized, along with the x axis. There are three asymmetric co-planar strip (ACPS) transmission lines on the top of the

215

7.7. PRELIMINARY IMPLEMENTATIONS

ACPS line

ACPS line

10m

10m

ACPS line

Z Y X

SiO2

50m

2m

Ni at Fe to ferromagnetic film

100 nm

S.I. substrate (a) Cross-plane view ACPS line ACPS line ACPS line to excite spin wave to detect the inductive voltage to excite spin wave Z Y

X

SiO2

Ferromagnetic film

Spin wave

S.I. substrate

(b)

Figure 7.13. Prototype of a spin-wave logic device.

structure. The lines and the ferromagnetic layer are isolated by the silicon oxide layer. The thickness of the ferromagnetic layer can be as thin as tens of nanometers, and the thickness of the oxide layer is several hundreds of nanometers. The dimensions of the ACPS lines are deﬁned by the frequency of the transmitting signal. Each of the ACPS lines can be used for spin-wave excitation and detection. A voltage pulse applied to the ACPS line produces magnetic ﬁeld perpendicular to the polarization of the ferromagnetic ﬁlm, and, thus, generates a spin wave (spinwave packet). Being excited, the spin wave propagates through the ferromagnetic ﬁlm. As it reaches the nearest ACPS line, the amplitude and the phase of the spin wave is detected by the inductive voltage measurements. For example, the edge ACPS lines can be considered as the input ports, and the ACPS in the middle as the output port. The middle ACPS line detects the inductive voltage produced by the superposition of two waves. Depending on the relative phase of the spin waves, the amplitude of the inductive voltage may be enhanced (when two waves are in phase) or decreased (when two waves are out of phase) in comparison to the

216

CHAPTER 7: SPIN- WAVE ARCHITECTURES

inductive voltage produced by a single spin wave. As we will show below, it is possible to realize different logic gates AND, OR, and NOT controlling the relative phase of the spin waves.

7.7.2. Logic Functionality The utilization of spin waves provides an opportunity to perform different logic operations in a single device by controlling the initial phases of spin waves. The set of logic gates, i.e., the two-bit gates, AND, OR, and the one-bit NOT gate can be demonstrated on the prototype three-terminal device as shown in Figure 7.13. The edge ACPS lines are considered as the input terminals, and the ACPS line shown in the middle is the output port. The input information is coded into the polarity of the voltage pulse applied to the edge ACPS lines (for example, Vinput = +10 V corresponds to the logic state 1W, and Vinput = 10 V corresponds to the logic state 0W). We assume the input terminals are placed equidistantly from the output one. In order to detect the output signal Vind we use the time-resolved inductive voltage measurement. To recognize the output logic state we introduce a reference voltage Vref. We assign the output logic state 1W if VindWVref, and logic state 0W otherwise. The measurement is performed at the moment of spin-wave packet arrival to the detecting ACPS line, tm. The exact choice of tm depends on the logic function one needs to realize. The one-bit NOT gate (inverter) can be obtained measuring the inductive voltage produced by spin waves excited by one of the input lines. Taking tm = pg/vph (where g is the distance between the contacts and vph is the spin-wave phase velocity), and Vref = 0 V, we achieve the required logic correlation. Next, the twobit AND gate can be realized when tm = 2pg/vph, and Vref = 0.5 mV. Two spinwave packets coming in phase enhance the amplitude of the produced inductive voltage, and cancel each other when coming out of phase. The nonzero reference voltage is needed to avoid the effect caused by the ﬁnite size of the detecting ACPS line. The OR gate can be realized by analogy, taking tm = 2pg/vph, and Vref = 0.5 mV. In Table 7.1, we have summarized the input/output correlations into the truth tables for different logic gates. TA B L E 7 . 1 . Truth Tables for AND and OR Gates

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

AND

OR

Vref = 0.5 mV

Vref = 0.5 mV

Logic state 1 1 0 0

1 0 1 0

Output Logic voltage state +27 mV 0 mV 0 mV 27 mV

1 0 0 0

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

Logic state 1 1 0 0

1 0 1 0

Output Logic voltage state +27 mV 0 mV 0 mV 27 mV

1 1 1 0o

217

7.8. EXPERIMENTAL RESULTS

7.8. EXPERIMENTAL RESULTS In Figure 7.14, we have schematically shown the prototype of the spin-wave logic device structure. The core of the structure consists of a 100 nm-thick CoFe ﬁlm deposited on a silicon substrate. There are two asymmetric co-planar strip (ACPS) transmission lines on the top of the structure. The distance between the lines is 8 mm. The lines and the ferromagnetic layer are isolated by a 300 nm silicon oxide layer. The dimensions of the ACPS lines are adjusted to match 50 O of the external coaxial cable. One of the ACPS lines (shown on the right) is used for spin-wave excitation. Hereafter, we will refer to this ACPS line as the ‘‘excitation’’ line. A voltage pulse applied to the excitation line produces a magnetic ﬁeld and excites a spin wave (spin-wave packet) in the ferromagnetic layer. Being excited, the spinwave propagates through the ferromagnetic ﬁlm. The other ACPS line (shown on the left) is used to detect the inductive voltage signal produced by the propagating spin wave. Hereafter, we will refer to this line as the ‘‘detection’’ line. Figure 7.15 shows the experiment setup, where an input voltage pulse with an amplitude of 24.5 V, rising time of 1.2 ns, and pulse length of 20 ns is applied to the

ACPS line

ACPS line Z 8 m

Y X

SiO2 Ferromagnetic film

(CoFe)

100 nm

S.I. substrate (a) ACPS line to detect spin

Z Y X

ACPS line to excite spin wave SiO2

Ferromagnetic film

Spine wave

S.I. substrate

(b)

Figure 7.14. Prototype of spin-wave device used in the experiments.

218

CHAPTER 7: SPIN- WAVE ARCHITECTURES

Figure 7.15. Spin-wave voltage detection set-up.

input port. In Figure 7.16, we present our experimental results on spin-wave detection by the time-resolved inductive voltage measurement technique [1]. The dashed line depicts the voltage pulse applied to the excitation line. One can see the inductive voltage oscillation at the detection line, which is caused by the inductive coupling via the spin waves. The output voltage signal has maximum pulse amplitude of 26 mV, and the period of oscillation is 9 ns. These experimental data illustrate the possibility of signal transmission by spin waves over micrometer range distances. The attenuation time is about 20 ns, and the signal-to-noise ratio is satisfactory (at least for 8 mm propagation distance). We would like to stress that the utilization of spin waves is prominent for short-range on-chip communication. There are two important issues that require additional consideration: (i) power dissipation in spin-wave bus and (ii) signal gain. In principle, the energy per spin wave can be scaled down to several kT, just above the thermal noise level. On the other hand, in order to

20

Input (V)

30

Input Output

20

10

10

0

0

−10

−10

−20

−20

−30

−30 60

80

100 120 140 Time (ns)

160

Output (mV)

30

180

Figure 7.16. Experimental data on spin-wave detection.

7.9. THE PRINCIPLE OF OPERATION

219

compensate the damping of spin waves, one needs to include an ampliﬁcation mechanism (gain). One of the possible gain mechanisms may be parametric spinwave ampliﬁcation, which has been experimentally demonstrated [17].

7.9. THE PRINCIPLE OF OPERATION In order to illustrate the principle of operation, we consider the propagation of a spin wave excited by an ACPS transmission line. The spin dynamics can be described using the Landau–Lifshitz’s equation as follows: h i ~ dm g ~eff þ a~ ~eff ; ~ m H m H ¼ dt 1 þ a2

ð7:1Þ

~ ~ ¼ M=M where m s is the unit magnetization vector, Ms is the saturation magnetization, g is the gyro-magnetic ratio, and a is the phenomenological Gilbert damping coefﬁcient. The ﬁrst term of Equation 7.1 describes the precession of magnetization about the effective ﬁeld and the second term describes its dissipa~eff is the effective ﬁeld that consists of the superposition of the external ﬁeld tion. H and contributions from anisotropy, and exchange ﬁelds. 2K ~pulse ; ~eff ¼ r2 F þ 2A r2 m ~þ ð~ m ~ eÞ~ eþH H Ms Ms

ð7:2Þ

~, A is the exchange constant, K is the uniaxial anisotropy wherer2 F ¼ 4pMs r m ~pulse is the constant, and ~ e is the unit vector along with the uniaxial direction, H pulse ﬁeld produced by the source-drain current. The ﬁrst terms in Equation 7.2 are deﬁned by the material properties of the ferromagnetic sample, while the last term, the excitation pulse ﬁeld, can be artiﬁcially controlled. Theoretically, by adjusting the form of the external ﬁeld pulse, it is possible to excite a spin wave of any desired frequency and amplitude. To be realistic, we use experimental data and an analytical model developed in [2], where spin wave excitation in NiFe ﬁlm by applying current pulses has been investigated in detail. It was found that a short current pulse (o100 ps) through a conducting strip placed close to the NiFe ﬁlm (0.54 mm oxide thickness) excites a spin-wave packet, which is a linear superposition of spin waves. An analytical solution to Equation 7.1 was found, and it describes the propagation of the wave packet through the ferromagnetic ﬁlm. The results of the numerical simulations demonstrated a good agreement with experimental data [2]. In Figure 7.14, we have show two ACPS lines, one as input and one output. If we add another ACPS line, it can be used as a second input port. Each of the input devices (ASPC lines) excites a spin-wave packet consisting of a Gaussian distribution of wave vectors that is 2/d in width and centered about k0. The wave packet propagates along with the y direction and can be described with one

220

CHAPTER 7: SPIN- WAVE ARCHITECTURES

magnetization component My as follows: " # C expðt=tÞ d2 ðy ntÞ2 My ¼ 4 cosðk0 y ot þ fÞ; exp 4ðd4 þ b2 t2 Þ d þ b 2 t2

ð7:3Þ

where C is a constant proportional to the amplitude, t is the decay time, f is the initial phase, n = qo/qk (k = k0) and b = (1/2)q2o/qk2 (k = k0) are the coefﬁcients of the ﬁrst and second order terms, respectively, in the Taylor expansion of the nonlinear dispersion, o(k). The dispersion relation for spin waves propagating orthogonally to the magnetization is given by n o1=2 ; o ¼ g 8pK þ ð2pMs Þ2 ½1 expð2kdÞ

ð7:4Þ

where d is the thickness of the ﬁlm. In numerical simulations, we used NiFe material characteristics: A = 1.6 106 erg.cm1, 4pMs = 10 kG, 2K/Ms = 4 Oe, g = 19.91 106 rad/s Oe, a = 0.0097, known from the literature [1, 18]. Taking the ﬁtting parameters for the wave packet obtained in [2], we use t = 0.6 ns, k0 = 0.25 mm1 and d = 5.7 mm for d = 27 nm. In Figure 7.17, we have show the results of numerical simulations illustrating spin-wave packet propagation. The distance between the excitation point and the point of observation is 50 mm. The spin waves produce perturbation in spin orientation perpendicular to the direction of magnetization, whose amplitude is much less than the saturation magnetization My =Ms 1.

50 μm

Inductive voltage (mV)

2

0

−2

0

1

2

3

4

5

Time (ns)

Figure 7.17. Numerical simulations results: propagation of a spin-wave packet.

221

7.9. THE PRINCIPLE OF OPERATION

Next, we consider the combined effect of spin-wave packets produced by two input devices. We assume that each of the input devices generates a spin-wave packet, which is described by Equation 7.3. The amplitudes of the input signals are the same, while the relative phase between the signals can be controlled, for example, by the polarity of the applied current pulses. The current pulses having the same polarity produce local magnetic ﬁelds oriented in the same direction, so the generated spin-wave packets have the same initial phase (f1 = f2). In the other case, when the current pulses have different polarity, the produced spinwave packets have relative phase difference. (f1 = f2 = p) In order to ﬁnd the magnetization change caused by two spin-wave packets, we calculated the resultant magnetization as a superposition of waves of the same frequency from each packet. y ¼ 1 M w

Zw=2 Z h i 2 2 M1y ðoÞ þ M2y ðoÞ þ 2M1y ðoÞM2y ðoÞcosðf1 f2 Þ dody ð7:5Þ w=2 o

In above equation, w is the width of the detecting device along the Y axis (the gap between the strips), and the subscripts depict the magnetization components of the ﬁrst and the second packets, respectively. We made integration over the ﬁnite length (w = 200 nm) to take into account the effect of dephasing. Then, we calculated the inductive voltage according to [1]:

d My m0 ldf ðz; wÞ Z ; ð7:6Þ Vind ¼ dt 4 Z þ 0:5Rdc where m0 is the magnetic constant, l is the length of the sample, f(z,w) is the spacing loss function, Z is the strip line resistance, and Rdc is the total ACPS line Relative phase (1 −2) = 0

30

Voltage (mV)

20 Relative phase (1 −2) =

10 0 −10 −20 0

1

2

Time (ns)

Figure 7.18. Numerical simulations results: output of two spin-wave packets.

222

CHAPTER 7: SPIN- WAVE ARCHITECTURES

dc resistance. In our calculation, we neglected the additional losses due to the ACPS line resistance. In Figure 7.18, we present the results of numerical simulations showing the inductive voltage as a function of time obtained in two cases: Spinwave packets are excited in phase (the solid line) and out of phase (the dashed line). The results of simulations illustrate the output of the prototype logic device described above. As shown in Figure 7.18, the amplitude of the inductive voltage is maximum when the spin-wave packets are coming in phase. In the other case, the waves from two packets compensate each other and produce inductive voltage of much less amplitude.

7.10. CONCLUSIONS In this chapter, three nanoscale architectures were presented: the reconﬁgurable mesh, crossbar, and fully interconnected cluster. In these architectures, both communication and computation are performed using spin waves. Furthermore, computation is done in both analog and digital modes. A hierarchical multiscale architecture was also presented that is an efﬁcient integration of the spin-wave modules within a MEMS architecture.

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9. M. M. Eshaghian-Wilner, A. Friesz, A. Khitun, A. C. Parker, S. Navab, and K. L. Wang. Emulation of neural networks on a nanoscale architecture. Journal of Physics: Conference Series, pp 288–292, 2007. 10. Y. Ohno et al. Electrical spin injection in a ferromagnetic semiconductor heterostructure. Nature, 402(6763): pp 790–792, 1999. 11. A. Dehon. Array-based architecture for FET-based, nanoscale electronics. IEEE Transactions on Nanotechnology, 2(1): pp 23–32, 2003. 12. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. A nanoscale reconﬁgurable mesh with spin waves. Proceeding of the ACM International Conference on Computing Frontiers, Italy: pp 65–70, May 2006. 13. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. Nanoscale modules with spin-wave inter-communications for integrated circuits. Proceedings of NSTI Nanotech 2006, Boston: pp 320–323, 2006. 14. M. M. Eshaghian-Wilner and L. Hai. Application-speciﬁc design of the optical communication topology in ORM. Proceedings of Supercomputing Applications in the Transportation Industries, International Symposium on Automotive Technology and Automation, Florence, Italy: June 1997. 15. L. Hai. Efﬁcient parallel computing with optical interconnects. Ph.D. Thesis, New Jersey Institute of Technology: 1997. 16. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. Wang. Hierarchical multiscale architectures with spin waves. Proceedings of the 2006 International Conference on Computer Design CDES 2006, Las Vegas, Nevada: pp 220–226, June 2006. 17. B. A. Kalinikos, et al. Parametric frequency conversion with ampliﬁcation of a weak spin-wave in a ferrite ﬁlm. IEEE Transactions on Magnetics, 34(4, pt.1): pp 1393–1395. 18. W. K. Hiebert, A. Stankiewicz, and M. R. Freeman. Direct observation of magnetic relaxation in a small permalloy disk by time-resolved scanning Kerr microscopy. Physical Review Letters, 79(6): pp 1134–1137, 1997.

8 PARALLEL COMPUTING WITH SPIN WAVES Mary Mehrnoosh Eshaghian-Wilner and Shiva Navab In this chapter, we study the algorithm design aspects of three newly developed spin-wave architectures. The three nanoscale architectures, the spin-wave reconﬁgurable mesh, spin-wave crossbars, and spin-wave fully interconnected clusters, are capable of simultaneously transmitting multiple signals using different frequencies, and allow for concurrent read/write operations. Exploiting such parallel features, we introduce a set of generic parallel processing techniques that can be used for routing and design of fast algorithms on these spin-wave architectures. We also present a set of application examples to illustrate the operation of the proposed generic parallel techniques on these new spin-wave models.

8.1. INTRODUCTION When mapping parallel algorithms onto parallel architectures, the performance of the algorithms highly depends on the underlying interconnectivity. In the past decades, various architectures with different types of interconnectivity were introduced; their aim was to produce fast algorithms. The major shortcoming in most of bus-based designs has been due to the fact that the use of bus was restricted to one pair of processors at any given time. Here, we deal with architectures with spin-wave buses that allow multiple pairs of processors to intercommunicate over each bus at any given time. In the following chapter, we study the algorithm design aspect of the three spin-wave architectures presented in Chapter 7. Exploiting the highly parallel features of these architectures, we introduce a set of generic parallel processing The authors of this chapter are listed alphabetically. Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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techniques that can be used for routing and design of fast algorithms on these spin-wave architectures. We also present a set of application examples to illustrate the operation of the proposed generic parallel techniques on these new spin-wave models.

8.2. PARALLEL ALGORITHM DESIGN TECHNIQUES In this section, we present three generic parallel processing techniques that are mainly designed for spin-wave reconﬁgurable meshes. The implementation of some of these techniques using spin-wave crossbar and fully interconnected clusters is also brieﬂy discussed. When using these architectures, one should take into consideration the fact that two different types of data detections are possible at the nodes. Once the spin waves are detected by the receiver, the transmitted data can either be digitized or left as analog. In analog detection mode, the receiver detects a voltage that is the superposition of multiple waves. For example, if ten waves are sending a ‘‘1,’’ then their analog sum through their cumulative amplitude is computed instantly as 10. Also, this property can be used to compute logical functions as described previously. In digital detection mode, this value is digitized to just a ‘‘1,’’ and then the computations are continued digitally. In the following section, the generic parallel techniques are presented [1, 2].

8.2.1. Find the Maximum/Minimum To ﬁnd the maximum or minimum of O(N2) inputs (with a maximum value of 2N) on a reconﬁgurable mesh, we ﬁrst assign each value to a processing node on the grid points of the reconﬁgurable mesh. Next, each node checks its most signiﬁcant bit (MSB). If MSB is 1, the node broadcasts a ‘‘1’’ to all the other processing nodes. If the MSB is 0, on the other hand, the processing node listens to the channel and gets disabled if it detects a 1 on the bus. At the next step, the nodes check their next most signiﬁcant bit. This procedure is repeated for all the bits. Since the maximum value of the inputs is N, this procedure takes O(log N) time [3]. If the number of inputs is at most N, the minimum and maximum numbers can be found in O(1) as presented in [4]. Finding the minimum is similar to ﬁnding the maximum except that in the case of MSB=1, the node broadcasts a ‘‘1’’ and at the same time listens to the channel. If there is a 1 on the bus, that node becomes disabled. The same implementation technique applies when using one single column of a spin-wave crossbar. In that case, the max/min of at most N inputs can be found using the N processing units. One of the columns would be used as the shared medium, where nodes broadcast their MSB. All the switches on that column must be turned on to connect the processing units to the shared bus. This algorithm can also be implemented on a fully interconnected cluster in a similar fashion, except that in the fully interconnected cluster, there are no

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switches to be set. The nodes are all connected to the shared medium, where they can broadcast their MSB or receive signals from other nodes. Note that on all of the spin-wave architectures, this whole routine can be performed simultaneously on disjoint sets of input, using different frequencies for each set. This cannot be done on a standard VLSI reconﬁgurable mesh due to the conﬂicts on the buses. Finding the maximum/minimum routine is used in several applications. For instance, it is used in the labeling algorithm and ﬁnding the nearest neighbor, explained in Chapter 19.

8.2.2. Find the First/Last in the List In many applications, we need to ﬁnd the ﬁrst or last element of a list. In geometric algorithms, for instance, this operation is useful where we ﬁnd the extreme points of a ﬁgure. The convex hull algorithm presented in Chapter 19 and the graph formation for multiple sequence alignment algorithms, presented in Chapter 14, are application examples that use this routine. To ﬁnd the ﬁrst or last element of at most N inputs, the ﬁrst step is to store the inputs in the processing elements in a column. We ﬁnd the local topmost nodes on that column by making each node send a signal downward. This procedure begins by turning off all the switches above each node (disconnect the channel) to force the signal sent by each node downwards. Then all nodes simultaneously send out a signal downward and turn on all switches (reconnecting the channel), thereby lettings all signals pass through the bus. Each node that receives a signal will become disabled. As the result, the only active nodes are the local topmost nodes that have not received a signal. This procedure is performed in O(1) time. An example is shown in Figure 8.1, where the ﬁrst A in the list is found by disabling the rest of the As. If different sets exist among the inputs, it is possible to ﬁnd the ﬁrst element of each set using frequency division multiplexing. For instance, in the above example, there are two sets (As and Bs). As shown in Figure 8.2, we ﬁnd the ﬁrst A and B in the list simultaneously by performing the routine on two different frequencies for A and B. Unlike a reconﬁgurable switch that can be controlled in four different directions, a crossbar switch has just two possible statuses: ‘‘on’’ or ‘‘off.’’ Therefore, it is not possible to force the wave in only one direction. As a result, the ﬁrst/last routine cannot be implemented on a crossbar in a similar fashion as a reconﬁgurable mesh. A

A

A

B

B

B

A

A

A

A

A

A

Figure 8.1. Finding the ﬁrst element of a list.

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Freq Freq A B

A B

A

A

Figure 8.2. Finding the ﬁrst element of different sets.

This implementation does not apply to a fully interconnected network either, since in that symmetric architecture, there is no notion of ﬁrst or last.

8.2.3. Find the All Preﬁx Sum To ﬁnd the all preﬁx, one should compute the sum of the ﬁrst j elements in an array and store the sum in the jth element. Using this algorithm, the sum of all the input values will be computed and stored in the last element. Here we show how this operation is performed in O(1) time on spin-wave architectures. To perform the all preﬁx sum routine for most N inputs, ﬁrst we map the inputs to the processing nodes on one column of the spin-wave reconﬁgurable mesh. At the beginning, all of the switches are turned on. Then, each node sends a signal with an amplitude equal to the value it has stored and immediately turns off the switch above it, directing the generated wave downwards. Note that for synchronization purpose, each node generates its spin-wave signal after a short period of time to compensate the spin-wave propagation delay in the ferromagnetic channel. This short period of time has to be greater than or equal to the distance between adjacent nodes divided by the speed of spin waves, which is in the order of 109/104=1013. Considering the fact that the frequency is in the order of GHz or even THz, this whole process is considered as constant time. The sum of previous values can be found at each element by using the superposition property of spin-waves. The main idea behind superposition is that when nodes transmit signals on the same frequency, the signals will superpose in amplitude when they meet. The amplitude of the superposed wave received by each node will be the preﬁx sum on that node. This routine is used in the graph formation algorithm for partial-order multiple sequence alignment, presented in Chapter 14. A special case of ﬁnding all preﬁx sum routine is counting the number of elements preceding a certain element in the list. To solve this problem, all the nodes transmit a signal downwards with an amplitude of 1. In each node, the total

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amplitude of all the superposed signals sent by the nodes above shows the number of its preceding elements in the list. Another special case of ﬁnding the all preﬁx sum routine would be the summation routine, where the summation of all nodes is found and stored in constant time. This is equivalent of all the preﬁx sum routine when performed at the very last node in the list. All the processing elements send downwards a signal with an amplitude equal to the value they have stored. Utilizing the superposition property of spin-waves, the last node receives the ‘‘sum’’ of the input values in constant time. This routine has been used in implementing the graph formation of the POMSA algorithm [5] described in Chapter 14. Note that the all preﬁx sum routine can be performed on at most N inputs, on a single column of the reconﬁgurable mesh. However, the summation routine can have as many as N2 inputs, mapped to all the nodes of the reconﬁgurable mesh. In that case, all the nodes send out their signals and the superposed signal or the ‘‘sum’’ received by all the nodes in O(1) time. Since it is not possible to send signals downwards in a crossbar or in a fully interconnected cluster, the all preﬁx sum routine can not be implemented on these two architectures. However, the special case of ﬁnding the summation of all inputs, for at most N inputs, can be implemented on one single column of a crossbar and on a fully interconnected cluster. As another application example, consider the problem of creating a histogram of input values where all such values are in the range of 1. N and each value represents a type. We show that this problem can be solved in O(1) time on a spinwave reconﬁgurable mesh. Assuming that the number of inputs is at most N2, the inputs can be mapped to processing nodes. There are two approaches to store the result of the histogram. The ﬁrst one is to choose one node of each type to be the representatives of that type. We can ﬁnd the ﬁrst of each type in the list to represent its type, using the routine explained in the previous section. The second approach, which we choose, is to let each node keep track of the number of nodes from its type. The next step is to count the number of times each value has been repeated in the list and store the sum at each (or the representative) node. As explained above, this problem is a subset of ﬁnding the all preﬁx sum routine. In this case all the nodes send a value of ‘‘1’’ and the result would be the number of inputs in that category. Note that this routine should be performed on each type of input; however, using different frequencies, these separate routines can be done simultaneously. In other words, each type’s sender and receiver are tuned on a distinct frequency. Due to superposition characteristic of the waves, each node receives the sum of 1 s sent on its tuned frequency, which is the number of nodes of that type.

8.2.4. Shifting the Elements of a List In several applications, the elements of a list needed to be shifted. The shifting operation can be implemented on a row or a column of a spin-wave reconﬁgurable

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mesh. We explain two methods for implementing the shifting operation on one row of the spin-wave reconﬁgurable mesh. In both methods, ﬁrst the elements of the list are mapped to the processing nodes. In the ﬁrst method, the shift operation is performed by using the spin-wave switches. As explained in the previous section, spin waves can be forced in one direction by using the spin-wave switches. To implement shifting to the right, all the nodes ﬁrst turn off their left switch and send out a spin-wave with an amplitude equal to their data while their right switch is open. This forces the waves to be directed to the right. As soon as the nodes send their waves, they immediately open their left switch and close their right switch. This allows each node to receive the spin wave from its left neighbor, while blocking the channel and preventing this received wave to go through to the next node on the right hand side. Similarly, shifting to the left can be implemented by forcing the waves to the left and not letting the wave pass through the immediate neighboring node. This method can not be used in a crossbar or fully interconnected cluster, since there are no switches between two adjacent nodes. No spin-wave switches are used as the second method for implementing the shift operation. The nodes are required to dynamically tune their frequency. In this method a distinct frequency is assigned to each node as its receiving frequency. In addition, each node’s sending frequency is tuned on its right neighbor’s assigned frequency. For instance, the sending frequency of node xi is tuned on fi1. Since these data transmissions between adjacent nodes are done at different frequencies, all can be performed simultaneously. This method can be used in implementing the shift operation on the reconﬁgurable mesh, as well as the crossbar and fully interconnected cluster. One of the applications of the shifting operation is in implementing a spinwave ﬁnite impulse response (FIR) ﬁlter module. An FIR ﬁlter is one of the primary types of ﬁlters used in digital signal processing [6]. An FIR ﬁlter works by multiplying an array of the most recent n data samples by an array of constants (called the tap coefﬁcients), and summing up the elements of the resulting array. The ﬁlter then inputs another sample of data, which causes the oldest piece of data to be discarded, and repeats the process [7]. FIR ﬁlters are implemented using a ﬁnite number M delay taps on a delay line and M computation coefﬁcients to compute the algorithm (ﬁlter) function. Figure 8.3 illustrates the block diagram of an FIR ﬁlter with M taps [8]. In the FIR ﬁlter, the output at time n, y(n), is computed as the summation of inputs multiplied by the tap coefﬁcient as illustrated by the following equation: yðnÞ ¼ b0 xðnÞ þ b1 xðn 1Þ þ þ bM xðn MÞ: To implement a spin-wave FIR ﬁlter, we use the superposition property of the waves to realize the summation function and we employ spin-wave switches to implement the shifting operation. First, each coefﬁcient is stored in the nodes with respect to the node’s index. In the next step, each processing node computes the multiplication of its ﬁxed coefﬁcient and the input mapped to it. All the processing

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x(n)

z−1

z−1 b0

b1

z−1

z−1 b2

b3

bM y(n)

Figure 8.3. Block diagram of an FIR ﬁlter.

nodes then broadcast a spin wave on the bus with an amplitude equal to their data. These values, which are sent at the same frequency, are superposed and form a wave with amplitude equal to the summation of all. The output node’s receiving frequency is tuned on the sending frequency of all the input nodes; therefore, it receives the result of this summation. At this stage, all the previous inputs are shifted right by one position, the new data is inputted to the leftmost node, and the summation process is repeated. The structure of a spin-wave FIR ﬁlter module is shown in Figure 8.4. This structure includes M+1 input node, where M is the number of taps. In this implementation, the shift operation is performed by using the spinwave switches as explained previously. (These switches are all on in the summation step.) As mentioned, it is possible to use another method for implementing the shift operation in which distinct frequencies are assigned to different nodes. Note that in implementing the FIR ﬁlter, after each shifting operation, all the nodes’ sending and receiving frequencies must be tuned on a common frequency to perform the summation. Therefore, in each step the nodes are required to dynamically tune their frequencies. Having explained some of the parallel techniques for algorithm design on spin-wave architectures, in the next section we describe some of their parallel routing schemes.

Inputs

Output

Xn

Xn-1

Xn-2

Xi

Xn-M

b0

b1

b2

bi

bM

Shifting step Summation step Spin-wave switch

Figure 8.4. Structure of a nanoscale spin-wave FIR ﬁlter.

y

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8.3. PARALLEL ROUTING AND BROADCASTING In the following section, we illustrate the routing features of our three spin-wave architectures. We focus primarily on the routing on a spin-wave crossbar, and we explain how the routing on the other two architectures differs from the routing on the crossbar. We also discuss the enhanced multiple multicasting feature on the fully interconnected cluster.

8.3.1. On Spin-Wave Crossbar Our spin-wave crossbar has several parallel and fault tolerant routing features [9]. We concentrate the routing features of this architecture in three different scenarios. These techniques are then compared to those for the reconﬁgurable spin-wave architecture and the fully connected spin-wave architecture. It is well known that all crossbars are capable of realizing any arbitrary oneto-one permutation. In a standard VLSI crossbar, however, unless there are broadcasting buses on each row, at any single point in time, only one switch is turned on in each row and each column. Spin-wave crossbars, on the other hand support additional features such as broadcasting and concurrent receiving as described below. ARBITRARY PERMUTATIONS. Similar to any standard crossbar, a spin-wave crossbar realizes arbitrary permutations. As described in the previous section, in the crossbar architecture the signals are directed in each row and each column through spin-wave buses. As an example of a one-to-one permutation realization, assume that input 3 needs to send a message to output 6. In that case, the switch in row 3 and column 6, represented as s(3,6) should be set to on. In addition, the receiver’s frequency of node 6 should be tuned to sender’s frequency of node 3. The switches can be set to on according to the following mechanism: A ﬁxed frequency is assigned to each column, and on top of each switch there is a receiver that is tuned to the frequency assigned to its column. As soon as the switch receives a signal on its frequency, it is activated and can route the data. For instance, switch s(3,6) is tuned onto the frequency assigned to column 6, f6. Input node 3 sends a signal on frequency f6 on row 3, which turns on s(3,6). Now, the third row is connected to the sixth column, and permutation (3,6) is realized. Figure 8.5 shows this communication on a crossbar of size 6. Note that there is a switch located on each of the grid points, but here we are just showing the activated one. CONCURRENT RECEIVE FEATURE. Realizing concurrent receive feature is very similar to realizing the one-to-one permutation described above. A ﬁxed frequency is assigned to each column (each receiver), and the senders tune their sending frequency to that frequency. As explained in the previous section, one of the important features of a spin-wave crossbar is allowing concurrent write. For instance node 2, 3, and 4 can all send a message to node 5, as shown in Figure 8.6.

8.3. PARALLEL ROUTING AND BROADCASTING

233

Figure 8.5. Arbitrary permutation.

Due to the superposition property of waves, output 5 receives a signal which is the sum of these three waves. In a standard VLSI crossbar, it is not possible to perform these three communications simultaneously because such a situation will cause a conﬂict on column 5.

Figure 8.6. Concurrent receive feature.

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BROADCASTING FEATURE. Broadcasting at a node happens when that node sends a single message to multiple receivers. Realizing broadcasting in a spin-wave crossbar is slightly different from realizing concurrent receive. In this case, a ﬁxed frequency is assigned to each row (each sender), and the receivers tune their receiving frequency to that ﬁxed frequency. As explained earlier, one of the most important advantages of a spin-wave crossbar is that one input can broadcast to multiple outputs simultaneously. For instance, node 3 can broadcast a message to output 2, 4, 5, and 6 at the same time, as shown in Figure 8.7. The only constraint is that the receivers should be tuned on the sender’s frequency. Note that different senders can broadcast to different sets of inputs on different frequencies. However, the sets must be disjoint since the receivers in different sets need to be tuned on different frequencies respectively. FAULT-TOLERANT ROUTING. Fault tolerance is one of the most important requirements for nanoscale devices and architecture because these devices suffer from dramatically increased permanent and transient failure rates. These failures are mainly due to the quantum nature (and hence probabilistic behavior) of the devices as well as the fundamental limitations of the fabrication processes [10]. The achievable degree of fault-tolerance to the defects present in the nanoscale devices will be the main concern in the adoption of new approaches in nanotechnology. One well known approach for developing reliable architectures to address both types of manufacturing and transient defects in nanoscale devices is to incorporate spatial and/or temporal redundancy [11]. In recent years, different tools have been developed to evaluate certain design trade offs in the nanoscale architectures. The

Figure 8.7. Broadcasting feature.

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235

most important trade offs are between granularity and reliability [12] and between redundancy and reliability [13]. It is shown that to make nanoscale systems reliable, different degrees of redundancy need to be applied at different granularity levels (i.e., gate and reconﬁgurable logic block levels) [13]. Several designs and techniques have been studied to increase the tolerance of nanoscale architectures to both transient and fabrication defects [14–31]. For instance, a number of redundancy schemes, including von Neumann’s multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic, have been presented in [20]. In addition, a new fault-tolerant design approach based on coding theory has recently been proposed at HP Labs [21]. In this approach, by using a crossbar architecture and adding 50% more wires, nanoelectronic circuits with nearly perfect yields can be fabricated even though the probability of broken components is high. To implement fault-tolerant quantum computers, quantum error correcting codes are being developed and elementary quantum gates are being constructed to form the basic building block of these computers [22]. Furthermore, three logic mapping algorithms with defect avoidance have been presented in [23] to circumvent clustered defective crosspoints in nanowire reconﬁgurable crossbar architectures. Fault tolerance is achieved in all these architectures by adding some level of redundancy. While redundancy is needed for reliable computation, economic constraints also need to be considered in choosing the redundancy factor [11]. The advantage of the fault-tolerant scheme presented in this chapter as compared to the other methods mentioned previously is in its smaller degree of required redundancy. In this section, we concentrate on the fault-tolerance features of a spin-wave nanoscale crossbar architecture. We show that by employing the parallel features of this architecture the amount of the spatial redundancy required for a fault-tolerant design is signiﬁcantly reduced [9]. In the following section, we brieﬂy talk about fault diagnosis for our spin-wave crossbar and then present a simple fault recovery scheme. FAULT DIAGNOSIS. There are many different ways in literature to detect a defective switch [24–28]. Here we choose a very simple method, in which an acknowledgment is sent from the receiver back to the sender for each transmission. If the sender does not receive an acknowledgment from the receiver after a ﬁxed amount of time, existence of a fault has been determined. The sender then tries to resend the message through another route. FAULT RECOVERY. In the example presented earlier where input 3 was sending to output 6, assume that the switch s(3,6) is defective. So now after node 3 sends a message to node 6, it does not receive the acknowledgement. Therefore, sender 3 will attempt to resend the message to node 6 through a new path. There are several schemes to reroute the message. The method we employ to reroute the path is simple. It is basically performed by adding an extra column of switches to the crossbar. In case of a fault on any of the switches on row i, the input, using the extra column, connects with the spin-wave bus path on row i+1 (or row i 1 if in

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Figure 8.8. Fault recovery example.

the last row) and then from there goes to its destination, as shown in the example below. We refer to the switches in the extra routing column as switches in column 0. In our example, node 3 connects to row 4 via this switch and reroutes the path through s(4,6), as shown in Figure 8.8. The signiﬁcant advantage of a spin-wave crossbar over a standard VLSI crossbar is that this simple scheme for rerouting does not collide with other intercommunications along the same row or column. For instance, as shown in Figure 8.9, in the same example, node 4 can still send a message to node 5 while 3 sends a message to 6 via s(4,6) in row 4. Although the rerouted path passes through row 4, these communications can be done in parallel with no conﬂict. This is due to the fact that nodes 3 and 4 use different frequencies, so their signal waves pass through each other without interference. Note that in this example, the two signals from input 3 and 4 go through row 4, as well as both columns 5 and 6. So the two input messages reach both outputs 5 and 6; however, output 5 detects the message from input 4 on its tuned frequency, while output 6 receives the signal from input 3.

8.3.2. On Spin-Wave Reconﬁgurable Mesh The routing on a reconﬁgurable mesh is similar to a crossbar. However, this routing can be from any of the N2 processing elements to any other one, so there can exist up to N2 N2 different routing schemes. The routing mechanism in a spin-wave reconﬁgurable mesh is as follows: To send information from Pi,j to Pk,l, the sender, Pi,j sends the signal to switch s(i,l) to be routed to Pk,l as shown in Figure 8.10.

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Figure 8.9. Parallel communications on spin-wave bus.

As mentioned in the previous section, the signiﬁcance of spin-wave architectures is that multiple waves on different frequencies can pass through the same bus without any conﬂict. For instance P3,2 can send a signal to P6,5, while P3,3 is sending a signal, on the same row and column, to P5,5.

Pi,j

(i,l)

Pk,l

Figure 8.10. Routing in reconﬁgurable mesh.

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8.3.3. On Spin-Wave Fully Interconnected Cluster The routing on a fully interconnected cluster is quite similar to the routing on a spin-wave crossbar, except the fact that there are no switches on this architecture. In addition, the fully interconnected cluster has an extra feature (which we explain later in this section). Similar to a crossbar, the concurrent receive feature applies here as well. At a given frequency, a node can listen to multiple waves simultaneously. Using the superposition property of waves, it receives the sum of all waves destined to it. Consider the scenario where multiple senders send data to a node, for instance G, at the same time. G receives the sum of those signals, providing that all the nodes transmit on the frequency at which G’s receiver is tuned. Multiple broadcasting is possible here too. To distinguish the data being transmitted to different nodes, transmissions are done at distinct frequencies, using frequency division multiplexing. In a way, this is similar to having various radio stations, each broadcasting at a different frequency. To listen to a speciﬁc station, one tunes to the corresponding frequency. Figure 8.11 shows an example, where node A is sending to a set of nodes, while C is sending to another set. Note that since different senders broadcast to different sets on different frequencies, the sets must be disjoint. However, as pointed out earlier, the fully interconnected network has an additional feature that is different than the other two

A L

f1 B

K

f2

C

J

D

I

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F G

Figure 8.11. Multiple broadcasting on disjoint sets of receivers.

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A L

B

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F G

Figure 8.12. Multiple broadcasting on disjoint sets of receivers.

architectures. This feature allows multiple braodcasting to sets which are not disjoint. This is basically the combination of concurrent receive and multiple broadcasting. Assume the scenario shown in the Figure 8.12 where one of the A’s and C’s destinations is the same (node H). This requires the sending frequency of A and C to be the same as the receiving frequency of H. However, if the sending frequency of these two nodes are the same, the receiving frequency of K, J, G, and F has to be the same too, which causes each of these nodes to receive the superposition of the signals sent by A and C. One approach to solve this problem, is using phased array techniques explained in [32] to direct the waves to speciﬁc locations. It is also possible to combine the phased array technique with multiple frequencies. As a result, for each frequency, some of the waves are only transmitted to desirable directions and are received by the intended sources.

8.4. CONCLUSIONS In this chapter, the algorithm design aspects of the spin-wave reconﬁgurable mesh, spin-wave crossbars, and spin-wave fully interconnected were studied. The architectures simultaneously transmit multiple signals using different frequencies,

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and allow for concurrent read/write operations. Exploiting such parallel features, a set of generic and fast parallel processing techniques were introduced.

REFERENCES 1. M. M. Eshaghian-Wilner and S. Navab. Generic parallel processing techniques for nanoscale spin-wave architectures. 2007 World Congress in Computer Science, Computer Engineering, and Applied Computing WORLDCOMP’07. In: Proceedings of the 2007 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’07): pp 221–227. 2. M. M. Eshaghian-Wilner and S. Navab. Efﬁcient parallel processing with spin-wave nanoarchitectures. Journal of Supercomputing; October 2008. 3. M. M. Eshaghian-Wilner, S. Navab, A. Khitun, and K. L. Wang. The Spin-wave Reconﬁgurable Mesh and Labeling Problem. ACM Journal on Emerging Technologies in Computing Systems, 3(2, no. 5): July 2007. 4. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. A nanoscale architecture for constant time image processing. Physica Status Solidi A, 204(6): pp 1931–1936, June 2007. 5. M. M. Eshaghian-Wilner, L. Lau, S. Navab, and D. Shen. Parallel graph formations of partial-order multiple-sequence alignments using nano-, micro-, and multi-scale reconﬁgurable meshes. Submitted to IEEE Transactions on NanoBioScience: 2008. 6. A. V. Oppenheim, R. W. Schafer, and J. R. Buck. Discrete-Time Signal Processing. Upper Saddle River, NJ: Prentice Hall, 1999. 7. http://www.bores.com/courses/intro/ﬁlters/4_ﬁr.htm. 8. http://www.freqdev.com/guide/DgtlFltrDsgnGd.pdf. 9. M. M. Eshaghian-Wilner and S. Navab. Parallel and fault-tolerant routing in the nanoscale spin-wave architectures. 2007 World Congress in Computer Science, Computer Engineering, and Applied Computing WORLDCOMP’07. In: Proceedings of the 2007 International Conference on Computer Design (CDES’07): pp 3–9. 10. C. Constantinescu. Trends and challenges in VLSI circuit reliability. IEEE Microwaves, 23: pp. 14–19, Jul–Aug 2003. 11. S. Roy and V. Beiu. Majority multiplexing—Economical redundant fault-tolerant design for nano architectures. IEEE Transactions on Nanotechnology, 4(4): pp 441–451, Jul 2005. 12. D. Bhaduri, S. K. Shukla, and Nanoprism. A tool for evaluating granularity vs. reliability trade-offs in nano architectures. GLSVLSI, ACM, Boston, Apr 2004. 13. S. K. Shukla, G. Norman, D. Parker, and M. Kwiatkowska. Evaluating the reliability of defect-tolerant architectures for nanotechnology with probabilistic model checking. Proceedings of the International Conference on VLSI Design 2004. 14. P. T. Gauehan, B. V. Dao, S. Yalamanchili, and D. E. Schimmet. Distributed, deadlock-free routing in faulty, pipelined direct interconnection networks. IEEE Transactions on Computers, 6: pp 651–665, 1996. 15. B. Almohammand and B. Bose. Fault-tolerant communication algorithms in toroidal networks. IEEE Transactions on Parallel and Distributed Systems, 10: pp 976–983, 1999.

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16. V. P. Roychowdhury, D. B. Janes, S. Bandyopadhyay, and X. Wang. Collective computational activity in self-assembled arrays of quantum dots: a novel neuromorphic architecture for nanoelectronics. IEEE Transactions on Electron Devices, 43: 1996. 17. R. M. P. Rad and M. Tehranipoor. A reconﬁguration-based defect tolerance method for nanoscale devices. 21st IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT’06): pp 107–118, 2006. 18. K. Nikolic, A. Sadek, and M. Forshaw. Fault-tolerant techniques for nanocomputers. Nanotechnology, 13(3), pp 357–362(6), 2002. 19. J. Byunghyun, Y. Kim, and F. Lombardi. Error tolerance of DNA self-assembly by monomer concentration control. 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06): pp 89–97, 2006. 20. J. Han, J. Gao, Y. Qi, P. Jonker, and J. A. B. Fortes. Toward hardware-redundant, fault-tolerant logic for nanoelectronics. IEEE Design and Test of Computers, 22(4): pp 328–339, July 2005. 21. http://www.extremetech.com/article2/0,1558,1826021,00.asp. 22. D. P. Vasudevan, P. K. Lala, and J. P. Parkerson. Fault tolerant quantum computation with new reversible gate. Proceedings of the NSTI Nanotechnology Conference: pp 744–747, 2005. 23. Y. Yellambalase, M. Choi, and Y. Kim. Inherited redundancy and conﬁgurability utilization for repairing nanowire crossbars with clustered defects. Proceedings of the 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06): pp. 98–106, 2006. 24. B. Almohammand and B. Bose. Fault-tolerant communication algorithms in toroidal networks. IEEE Transactions on Parallel and Distributed System, 10: pp 976–983, 1999. 25. J. Zhou and F. Lau. Adaptive fault-tolerant wormhole routing with two virtual channels in 2D meshes. International Symposium on Parallel Architectures, Algorithms and Networks: p 142, 2004. 26. G. Wang and J. Chen. A new fault-tolerant routing scheme for 2-dimensional mesh networks. Proceedings of the Fourth International Conference on Parallel and Distributed Computing: 2003. 27. X. Fan, W. Moore, C. Hora, M. Konijnenburg, G. Gronthoud. A gate-level method for transistor-level bridging fault diagnosis. 24th IEEE Proceedings of VLSI Test Symposium: 2006. 28. J. Zhou and F. Lau. Adaptive fault-tolerant wormhole routing with two virtual channels in 2D meshes. International Symposium on Parallel Architectures, Algorithms and Networks: p 142, 2004. 29. G. Wang and J. Chen. A new fault-tolerant routing scheme for 2-dimensional mesh networks. Proceedings of the Fourth International Conference on Parallel and Distributed Computing: 2003. 30. X. Fan, W. Moore, C. Hora, M. Konijnenburg, and G. Gronthoud. A gate-level method for transistor-level bridging fault diagnosis. 24th IEEE Proceedings of VLSI Test Symposium: 2006. 31. M. B. Tahoori and S. Mitra. Fault detection and diagnosis techniques for molecular computing. NanoTech Conference: 2004. 32. R. C. Hansen editor. Signiﬁcant Phased Array Papers. Norwood, MA: Artech House, 1973.

9 NANOSCALE STANDARD DIGITAL MODULES Shiva Navab In this chapter on employing the computing features of spin waves, we present several nanoscale standard combinational modules. We show that a number of these widely used arithmetic and logic modules, including full adders, multipliers, decoders, encoders, multiplexers, and demultiplexers, can be implemented by employing the concurrent write feature and superposition property of the spin waves. In addition, we demonstrate how to implement more complex modules, such as priority encoders and shifters, by using spin-wave switches. The universality of the presented digital architectures ensures the possibility of realizing any logic switching functions. Moreover, these nanoscale modules can be integrated by adding latches to implement sequential systems.

9.1. INTRODUCTION The signiﬁcance of efﬁciently implementing standard combinational arithmetic and logic modules is due to the fact that they are the basic blocks of any digital system. All the sequential systems can be implemented by just adding latches to the combinational circuit. The universality of the combinational modules ensures the possibility of realizing any logic switching function. A set of combinational modules are said to be universal if any combinational system can be implemented using the elements from just that set. In addition to logic gates such as {NAND} and {NOR}, standard combinational modules can generate universal sets as well. For instance, a network of multiplexers can implement any switching function according to Shannon’s decomposition [1]; therefore the set {MUX} is universal. {Decoder, OR} is another example of a universal set. We show how each of these modules can be implemented using spin waves. Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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The architectures presented here use spin waves for information transmission and data processing. Spin wave is a collective oscillation of spins in an ordered spin lattice around the direction of magnetization [2]. A propagating spin wave changes the local polarization of spins in ferromagnetic material. In turn, the change in magnetic ﬁeld results in an inductive voltage. Recent published experimental results indicate that an inductive voltage signal of the order of mV produced by spin waves propagating through a nanometer thin ferromagnetic ﬁlm are detectable at the distances of up to 50 microns at room temperature [3, 4]. A number of spin-wave architectures have been recently proposed, namely, logic gates [5–7], a crossbar [8, 9], a reconﬁgurable mesh [10, 11], and a fully interconnected cluster [12]. Similar to those architectures, in the spin-wave digital modules presented here, information is encoded into the phase of the spin waves. Moreover, all these architectures are capable of transmitting multiple waves simultaneously. In this chapter, we present a set of widely used digital architectures and demonstrate how they can be implemented at the nanoscale [13]. A number of these standard and combinational arithmetic and logic modules, including full adders, multipliers, logic gates, decoders, encoders, multiplexers, and demultiplexers can be implemented by employing the concurrent write and superposition property of the spin waves. To implement more complex modules such as priority encoders and shifters, spin-wave switches [8] are used as well. The rest of this chapter is organized as follows: In Section 9.2, we present our proposed spin-wave combinational arithmetic modules. We then describe the proposed spin-wave standard combinational logic modules in Section 9.3. We present more complex digital modules in Section 9.4, followed by our conclusion and future work in Section 9.5.

9.2. NANOSCALE SPIN-WAVE STANDARD ARITHMETIC MODULES In this section, we ﬁrst present a digital to analog module that is used in the design of several other arithmetic and logic modules. Afterwards, we show how to implement spin-wave full adders and multipliers.

9.2.1. Nanoscale Spin-Wave Digital to Analog Converter As mentioned in Chapter 7, the computation using spin waves can be done in both digital and analog forms. We assume that upon receiving an analog signal, analog to digital conversion is performed in each processing node by comparing the signal value to several threshold voltages. In this section, we illustrate a simple method for converting a digital value to an analog signal to be transmitted via the spinwave bus. The analog value is computed as the weighted sum of input bits, where the weight of the ith value is 2i. Analog value ¼

N 1 X i¼0

i 2i

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9.2. NANOSCALE SPIN- WAVE STANDARD ARITHMETIC MODULES

···

xi xk−1

D/A

x0

···

Inputs

Y

xk−1

xk−2

2K−1

2K−2

···

x1

x0

2

1

Output Y

fadc

Figure 9.1. Structure of a nanoscale spin-wave digital to analog converter.

To implement an N-bit digital to analog converter (D/A), we use N nodes as inputs and one node as the output, all connected to the spin-wave bus. Assuming that the output is the rightmost node, the N-bit digital value gets mapped to the N input nodes such that the most signiﬁcant bit (MSB) is mapped to the leftmost node, and the least signiﬁcant node (LSB) to the rightmost node. The index of these nodes starts at zero for the rightmost node and continues to N1 for the leftmost node. A ﬁxed value equal to 2index is assigned to each of these nodes. To compute the analog value, each node checks its input value; if equal to ‘‘1,’’ it sends a spin wave on the bus with an amplitude equal to its assigned ﬁxed value. Note that all the senders’ frequencies are the same as the frequency at which the output is tuned. The output node receives the superposition of all the waves, which is equal to the analog value represented by the N input bits. Figure 9.1 illustrates the structure of a spin-wave digital to analog converter. The digital to analog converter module has several applications. For instance, it is used in the design of decoders, multiplexers, and demultiplexers as shown in the next sections.

9.2.2. Nanoscale Spin-Wave Full Adder A k-input full adder is a device that adds the two k-bit input values and a carry-in value and generates a k-bit sum and a 1-bit carry-out [1]. The structure of a spinwave k-bit full adder is shown in Figure 9.2. It consists of k nodes representing input x, k nodes representing input y, one node for cin, and one node for analog value of the output, z. These nodes intercommunicate via the spin-wave bus. All the input nodes’ sending frequency is tuned on the receiving frequency of the z. The inputs x and y are converted to analog value using two digital to analog converters (D/A). The cin node broadcasts its value on the spin-wave bus at the same time as all the other input nodes broadcast 2i xi and 2i yi , for i = 0 k1, explained in Section 9.2. All these waves get superposed and the output node z receives the analog value of this summation. Similar to a spin-wave encoder, the internal A/D converts this value to k+1 bit binary value. The most signiﬁcant bit (MSB) of this binary value is the cout, while the rest of the bits represent the sum value.

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cout

···

yn−1 Cin

···

Y0

S0

Full adder

x0 xn−1

···

Binary input x xk−1 xk−2

x0

yk−1 yk−2

1

2K−1 2K−2 ···

Sn−1

cin

y0 1

X Digital to analog converter

Cout

zk zk−1 z0 ··· A/D z

Binary input y

2K−1 2K−2 ···

Sum

cin

Y Digital to analog converter

Figure 9.2. Structure of a nanoscale spin-wave full adder.

9.2.3. Nanoscale Spin-Wave Multiplier A k-input multiplier is a device that multiplies two k-bit input values and generates a 2k-bit product. A spin-wave multiplier consists of k nodes representing input x, k nodes representing input y, 2i intermediate nodes, t, and one node for analog value of the output, P. These nodes intercommunicate via the spin-wave bus, as shown in Figure 9.3. The multiplication is implemented as x number of times adding the value of y. This process is performed in three steps. Similar to a spin-wave adder, both binary input values are converted to analog using digital to analog converters: First Step. First the receiving frequency of t0 tN1 (t nodes) is tuned on the sending frequency of x nodes. Each xi node (which has a value 1) sends a spin-wave on the bust with its assigned amplitude, 2k, to implement the digital to analog conversion. Therefore, all the t nodes receive the analog value of x. Second Step. In the next step, the receiving frequency of t nodes is tuned on the sending frequency of y nodes. Step 1 is repeated for y and the analog value of y is received by t nodes. Third Step. Each t node compares its index to value of x. If its index is less than x, the t node broadcasts a spin-wave with an amplitude equal to the value of y.

Binary input x

Binary input y

N=

···

x0

···

y0 yk−1

···

Multiplier

xk−1

P0

xk−1

xk−2

2 K−1

2 K−2

···

x0

yk−1

yk−2

1

2 K−1

2 K−2

y0

···

Digital to analog converter

Intermediate Nodes

2

P2k−1

tN−2

t0

··· Y

P0

P2k ··· A/D

tN −1

1

1 X

P2k−1

2K

3

P

Digital to analog converter

Figure 9.3. Structure of a nanoscale spin-wave multiplier.

P

247

9.3. NANOSCALE SPIN- WAVE STANDARD LOGIC

TA B L E 9 . 1 . Frequency Assignments in the Multiplier Implementation Node Binary x input nodes (step 1) Intermediate nodes t (step 1) Binary y input nodes (step 2) Intermediate nodes t (step 2) Intermediate nodes t (step 3) Output node (step 3)

Sending frequency

Receiving frequency

fadc – fadc – fout –

– fadc – fadc – fout

The output node’s receiving frequency is tuned on the t nodes’ sending frequency, so that it receives the superposition of these waves. In this fashion, x number of y is accumulated to generate the multiplication operation. Note that 2k nodes are required as t since maximum value of x is 2k. Table 9.1 shows the frequency assignments for implementing a spin-wave multiplier.

9.3. NANOSCALE SPIN-WAVE STANDARD LOGIC In this section we demonstrate how standard combinational logic modules can be implemented at the nanoscale. We employ parallel features of spin waves for implementing these logic modules: logic gates, decoders, encoders, multiplexers, and demultiplexers.

9.3.1. Logic Gates The utilization of spin waves provides an opportunity to perform different logic functions in one device controlling the initial phases of spin waves and the voltage threshold to which the output voltage is compared. As explained in Chapter 7, Khitun and Wang showed how the two-bit gates, AND, OR, and the one-bit NOT can be implemented on the simple spin-wave prototype device [5, 6]. In this section we ﬁrst brieﬂy explain how they have implemented these logic gates, and next, we show how to extend their design to implement other logic functions such as NAND, NOR, XOR, and XNOR. As explained in Chapter 7, the input information is coded into the polarity of the voltage pulse applied to the input ACPS lines and is detected at the output port [5]. The output logic state is determined by comparing the detected voltage to a reference voltage, Vref. Assume that the measured inductive voltage produced by a single spin wave at the output port is V1. The reference voltage Vref can be a function of V1 as shown below. The measurement is performed at the moment two spin wave packets arrive at the detecting ACPS line tm. The exact choice of tm depends on the logic function one needs to realize.

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Excitation

Detection

+1V

−1V

Figure 9.4. Encoding the information in the phase of the spin-wave.

The one-bit NOT gate can be obtained measuring the inductive voltage, Vout, at the output line produced by spin waves excited by the input line. Taking tm = pg/vph (where g is the distance between the contacts and vph is the spin-wave phase velocity), and Vref = 0 V, we achieve the required logic correlation [7]. At this tm, the spin waves are detected with 1801 phase difference comparing to the original phase as shown in Figure 9.4. Next, the two-bit AND gate can be realized when tm = 2pg/vph, and Vref = V1 (in Table 9.2, V1 = 10 mV). Two spin-wave packets coming in phase enhance the amplitude of the produced inductive voltage, and cancel each other when coming out of phase. The nonzero reference voltage is needed to avoid the effect caused by the ﬁnite size of the detecting ACPS line. The OR gate can be realized by analogy, taking tm = 2pg/vph and Vref = V1. In Table 9.2, the input/output correlations are summarized for different NOT, AND, and OR logic gates as shown in [8]. Extending the same idea, a two-bit NAND gate can be implemented when tm = pg/vph and Vref = V1. Similarly a two-bit NOR gate can be realized when tm = pg/vph and Vref = V1. Table 9.3 shows the input/output correlations for NAND and NOR gates. To realize XOR and XNOR gates, we need two reference voltages, Vref1 and Vref2. In these two gates, we deﬁne the output to be in state ‘‘1’’ if the detected output voltage is between Vref1 and Vref2 and in state ‘‘0’’ if it is greater than Vref1 or less than Vref2. For both gates, Vref1 = V1 and Vref2 = V1. For an XOR gate

TA B L E 9 . 2 . Truth Table for AND and OR Gates [6]

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

AND

OR

Vref = 0.5 mV

Vref = 0.5 mV

Logic state

Output Logic voltage state

1 1 0 0

+27 mV 0 mV 0 mV 27 mV

1 0 1 0

1 0 0 0

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

Logic state

Output Logic voltage state

1 1 0 0

+27 mV 0 mV 0 mV 27 mV

1 0 1 0

1 1 1 0

249

9.3. NANOSCALE SPIN- WAVE STANDARD LOGIC

TA B L E 9 . 3 . Truth Table for NAND and NOR Gates

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

NAND

NOR

Vref = 0.5 mV

Vref = 0.5 mV

Logic state

Output Logic voltage state

1 1 0 0

+27 mV 0 mV 0 mV 27 mV

1 0 1 0

0 1 1 1

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

Logic state

Output Logic voltage state

1 1 0 0

+27 mV 0 mV 0 mV 27 mV

1 0 1 0

0 0 0 1

tm = 2pg/vph, while in an XNOR gate tm = pg/vph. Table 9.4 summarizes the input/output correlations for XOR and XNOR gates.

9.3.2. Nanoscale Spin-Wave Binary Encoder A binary encoder is used when an occurrence of one of several disjoint events needs to be represented by an integer identifying the event [1]. A 2k-input binary encoder is a combinational system that has 2k binary inputs and k binary outputs. Note that at any given time only one of the encoder’s inputs can be 1, and all the others have to be 0. The structure of a spin-wave encoder is shown in Figure 9.5. To implement an encoder with N = 2k input bits, we use N nodes for the inputs and one node as the output. These nodes intercommunicate via the spin-wave bus to which they are connected. The sending frequency of all nodes is tuned at the same frequency, namely fT. The output’s receiving frequency is tuned on fT as well. As soon as the input value of a node becomes 1, it broadcasts a spin wave with amplitude equal to its index; the output node receives this broadcasted value. In this architecture, the output node will contain the ‘‘analog’’ value equal to the index of the input containing a 1. As mentioned previously, we assume that this analog value can be digitized at

TA B L E 9 . 4 . Truth Table for XOR and XNOR Gates XOR

XNOR

Vref1 = 0.5 mV, Vref2 = 0.5 mV

Vref1 = 0.5 mV, Vref2 = 0.5 mV

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

Logic state

Output Logic voltage state

1 1 0 0

+27 mV 0 mV 0 mV 27 mV

1 0 1 0

0 1 1 0

Input voltage +1 V +1 V 1 V 1 V

+1 V 1 V +1 V 1 V

Logic state

Output Logic voltage state

1 1 0 0

+27 mV 0 mV 0 mV 27 mV

1 0 1 0

1 0 0 1

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CHAPTER 9: NANOSCALE STANDARD DIGITAL MODULES

Binary outputs yk−1 y0

... N = 2K

A/D

Input

y0

...

...

x0

yi

x1

xi

...

...

...

xi

Binary encoder

x0

yk−1

Analog out

xN−1

... i

xN−1 Binary encoder

Figure 9.5. Structure of a nanoscale spin-wave binary encoder.

the output node based on several reference voltage thresholds. The digitized value will be k = log N bits which are the outputs of the binary encoder.

9.3.3. Nanoscale Spin-Wave Binary Decoder A k-input binary decoder is a combinational system that has k binary inputs and 2k binary outputs. The inputs represent an integer in the range of 0y2k1 [1]. In other words, assuming N = 2k, the binary decoder has N outputs and k = log N inputs. A spin-wave binary decoder consists of k input and N output nodes connected to a spin-wave bus. We show two different methods for implementing a nanoscale binary decoder using spin waves. The structure of a spin-wave decoder that has been implemented based on these two methods is shown in Figure 9.6. In both designs, the binary input value is ﬁrst converted to analog using a digital to analog converter. An additional node, which is in fact the output of the digital to analog converter, stores the analog value of the input represented by the log N bit inputs. To ﬁnd this analog value, the binary input nodes send their value (i 2i) on frequency fadc. The analog input node’s receiving frequency is tuned on fadc and it receives the index value. At the next step, the sending Analog input

Inputs xk−1

xk−2

...

yN−1

x0

y0

X

1

yi

2

...

... xN−1

y0

...

... xi

Binary decoder

x0

Digital to analog converter

N=2K

Outputs y1

y2

...

fsel fi Decoder

Figure 9.6. Structure of a nanoscale spin-wave binary decoder.

yN −1

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9.3. NANOSCALE SPIN- WAVE STANDARD LOGIC

TAB LE 9 .5 . Frequency Assignments in the First Method of Binary Decoder Implementation Node Binary inputs Analog input Outputs

Sending frequency

Receiving frequency

fadc fsel –

– fadc fsel

frequency of this analog input node is determined depending on the method we choose for implementing the decoder. In the ﬁrst method, the input node broadcasts the index of the output it is selecting on a common frequency, fsel, at which all the output nodes are tuned. In this implementation, all the output nodes are required to know their index. They receive the broadcasted value, compare it to their index, and the one whose index has been broadcasted outputs 1. Table 9.5 shows the sending and receiving frequencies the nodes have to be tuned on. In the second method, the output nodes do not need to have any information regarding their indices. Instead, a distinct frequency is assigned to each output node. For instance, output i is tuned on fi. The input node, which contains the index of the output node, sends a signal on the speciﬁc frequency assigned to that output. The output node that receives this signal outputs 1. Since the output nodes are tuned on distinct frequencies, only one output node receives this signal. Table 9.6 shows the frequency assignments for the second method of implementing a spin-wave binary decoder. Binary decoders are widely used in different logic systems. One of their most important applications is in decoding the address when accessing memory cells.

9.3.4. Nanoscale Spin-Wave Multiplexer A multiplexer is a device that selects one of many data sources and outputs that source into a single channel. In other words, multiplexers function as multipleinput, single-output switches. A 2k-input multiplexer is a combinational system that has 2k binary inputs, k binary control (select), and one data output. The output of the multiplexer is equal to the data input selected by the control input [1]. TAB LE 9 .6 . Frequency Assignments in the Second Method of Binary Decoder Implementation Node Binary inputs Analog input Output i

Sending frequency

Receiving frequency

fadc Variable (fi ) –

– fadc fi

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CHAPTER 9: NANOSCALE STANDARD DIGITAL MODULES

Analog select input

Select inputs

... xi

...

Multiplexer

x0

sk−1

sk−2

2K−1

2K−2

s0

...

Digital to analog converter

xN−1

x0

S

x1

x2

1

fadc

y

Output

Data inputs

1

fsel

2

fi

xN−1

...

Y

fout

Multiplexer

... Sk−1 S0

Figure 9.7. Structure of a nanoscale spin-wave multiplexer.

We present two different methods for implementing a nanoscale spin-wave multiplexer, in which input and output nodes intercommunicate via a spin-wave bus, as shown in Figure 9.7. Similar to the implementation of the binary decoder, in both designs, the binary select-inputs value is ﬁrst converted to analog using a digital to analog converter. In the ﬁrst method of implementing a multiplexer, the analog-select-input node broadcasts on frequency fsel, the index number of the input it is selecting. The data-input nodes, which are tuned on fsel, receive the broadcasted value, compare it to their indices, and check if they have been selected. The selected data-input node sends its data on fout that is the frequency the output node’s receiver is tuned on. Table 9.7 shows the sending and receiving frequency assignment of the nodes. In the second method, a distinct frequency is assigned to each data-input node. In other words, data input i is tuned on fi. Assuming that the analog-selectinput node contains the index i, it broadcasts a signal on fi to be received by the ith data-input node. Upon receiving a signal, this node sends its data on the frequency at which the output node is tuned. Thus, the output node receives the data sent by the selected data-input node. Table 9.8 shows the frequency assignments for the second method of implementing a spin-wave multiplexer. Multiplexers are widely used in various digital circuits. As an example, we mention one of their applications in digital signal processing. The multiplexer takes several separate digital data streams and combines them together into one data stream of a higher data rate. This allows multiple data streams to be carried from one place to another over one physical link. TAB LE 9 .7 . Frequency Assignments in the First Method of Multiplexer Implementation Node Binary select inputs Analog select input Data inputs Output

Sending frequency

Receiving frequency

fadc fsel fout –

– fadc fsel fout

253

9.3. NANOSCALE SPIN- WAVE STANDARD LOGIC

TAB LE 9 .8 . Frequency Assignments in the Second Multiplexer Implementation Node Binary select inputs Analog select input Data inputs Output

Sending frequency

Receiving frequency

fadc Variable (fi ) fout –

– fadc fi fout

9.3.5. Nanoscale Spin-Wave Demultiplexer A demultiplexer is a device that takes a single input which selects one of many data-output-lines and connects the single input to the selected output line. A demultiplexer is often used in the receiver with a complimentary multiplexer on the sender end. A 2k-output demultiplexer is a combinational system that has one binary input, k binary control (select), and 2k data output. This module routes the input data to the output selected by the control input; all other outputs are zero [1]. The structure of a spin-wave demultiplexer consists of k select-input, one data input, and N = 2k output nodes that are connected to a spin-wave bus, as shown in Figure 9.8. The implementation of the spin-wave demultiplexer is quite similar to the spin-wave multiplexer (second method) implementation in which a distinct frequency is assigned to each of the output nodes. In the ﬁrst step the binary select-input value is converted to analog value using a digital to analog converter. Note that unlike the decoder and multiplexer, the implementation of the demultiplexer requires no additional node to keep the analog select value, since this value is received by the data-input node. The data-input node, which has received the index of the output node, sends a signal with an amplitude equal to its data on the speciﬁc frequency assigned to the output node. The output nodes are tuned on distinct frequencies, therefore only the selected output node receives the

Data input

Select inputs

...

x

Demultiplexer

y0

yi

sk−1

sk−2

2K−1

2K−2

...

fadc

s0

x

N=2K

Outputs y0

y1

1

y2

...

yN−1

fi x-value

... yN−1

Digital to analog converter

Demultiplexer

... Sk−1 S0

Figure 9.8. Structure of a nanoscale spin-wave demultiplexer.

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CHAPTER 9: NANOSCALE STANDARD DIGITAL MODULES

TAB LE 9 .9 . Frequency Assignments in the First Method of Demultiplexer Implementation Node Binary select inputs Data input Output i

Sending frequency

Receiving frequency

fadc Variable (fi ) –

– fadc fi

data sent by the data-input node. Table 9.9 shows the frequency assignments for the ﬁrst method of implementing a spin-wave demultiplexer. The other possible implementation would require the demultiplexing to be performed in two steps. In the ﬁrst step, all the output nodes’ receiving frequencies are tuned on a common frequency fadc so that all the nodes receive the analog value of select-input. All the output nodes compare the select value to their own index to see which output is selected. In the second step, the selected output node tunes its frequency on the input node’s sending frequency. The data-input node broadcasts a spin-wave with an amplitude equal to its data, and the selected output receives and outputs it. Table 9.10 shows the frequency assignments for the second method of implementing a spin-wave demultiplexer.

9.4. MORE COMPLEX NANOSCALE SPIN-WAVE DIGITAL MODULES In this section, we demonstrate how to implement more complex modules such as priority encoders and shifters. We present two implementations for a simple shifter and show how to extend one to design a spin-wave p-shifter. Next, we show how to implement a regular and also programmable priority encoder by using spin-wave switches.

9.4.1. Nanoscale Spin-Wave Shifter In this section we ﬁrst present two methods for implementing a simple shifter. In the ﬁrst method, we use assigned frequencies for parallel intercommunications between adjacent nodes. In the second method, we use spin-wave switches to TAB LE 9 .1 0 . Frequency Assignments in the Second Method of Demultiplexer Implementation Node Binary select inputs Outputs (step 1) Data input Output i (step 2)

Sending frequency

Receiving frequency

fadc – fout –

– fadc – fout

255

9.4. MORE COMPLEX NANOSCALE SPIN- WAVE DIGITAL MODULES

implement the shifting operation [14]. Afterwards, we show how to extend the ﬁrst implementation if a simple shifter to design a p-shifter. A SPIN-WAVE SIMPLE SHIFTER. A simple shifter is a combinational system having (N+2)-bit data-input, N-bit data output, and two one-bit control inputs: d (shifter direction) and s (shift or no shift). This system shifts the input data by one bit either to the right or to the left (depending on the value of d ), or delivers the input data unchanged [1]. In implementing a simple shifter, we need N+2 processing nodes. Except the ﬁrst and last nodes which are just input nodes, The nodes act as both inputs and outputs, except the ﬁrst and last nodes that are just inputs. We present two methods for implementing a simple shifter. In the ﬁrst method, a single frequency is assigned to each of the nodes. The receiving frequencies of all nodes are tuned on these distinct frequencies. In addition, each node is aware of the frequency of its neighboring nodes. Each node determines its sending frequency based on the control signals. If control signal s shows ‘‘no shift,’’ no node sends out any signal. On the other hand, if s commands to ‘‘shift,’’ each node’s sending frequency will be tuned on its right or left neighbor’s frequency depending on the direction shown by control signal d. For instance, node xi sends its data on frequency fi+1 if d indicates shift to the left and on fi1 for shift to the right. Since these data transmissions are done on different frequencies, all can be performed simultaneously. The structure of this shifter (except s and d) is shown in Figure 9.9. In the second method, all the nodes are tuned on the same frequency, and the shifting operation is performed by using spin-wave switches. The structure of this shifter is shown in Figure 9.10. If s indicated ‘‘no shift,’’ all the nodes keep their switches off and no wave is transmitted; otherwise, the shifting operation is performed by using the spin-wave switches. Note that spin-waves propagate in both directions in the ferromagnetic bus; however, they can be forced in one direction by using the spin-wave switches. The structure of spin-wave switches were described in Chapter 7. To implement shifting to the right, all the nodes turn off their left switch and send out a spin-wave with an amplitude equal to their data while their right switch is open. This forces the waves to be directed to the right. As soon as the nodes send their waves, they immediately open their left switch and close their right switch.

xn xn−1

s

S/N-S

d

L/R

...

xi

...

Shifter

yn−1

...

yi

...

Outputs: Inputs:

x0 x−1

Shift right Shift left

yn−1 yn−2 xn

xn−1 xn−2

fn−1

fn−2 fn−1

...

...

yi xi

...

y0 x0

...

x−1

f0

fi fi

f1

f0

y0

Figure 9.9. Structure of a nanoscale spin-wave shifter using multiple frequency assignments.

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CHAPTER 9: NANOSCALE STANDARD DIGITAL MODULES

xn xn−1

...

s

S/N-S

d

L/R

xi

...

Shifter

... yn−1

xn

xn−1 xn−2

...

yi xi

...

y0 x0

...

x−1

Shift right

... yi

...

yn−1 yn−2

Outputs: Inputs:

x0 x−1

Shift left y0 Spin-wave switch

Figure 9.10. Structure of a nanoscale spin-wave shifter using spin-wave switches.

This allows each node to receive the spin wave from its left neighbor, while blocking the channel and preventing this received wave to go through to the next node on the right hand side. Similarly, shifting to the left can be implemented by forcing the waves to the left and blocking them at the immediate neighboring node. A SPIN-WAVE P-SHIFTER. A p-shifter is a generalization of the simple shifter, which has a (N+2p)-bit data-input, N-bit data output, a one-bit control inputs d (for shifter direction), and a (log p)-bit control signal s (shift distance). In this system, the data-input is shifted 0, 1,y, p positions (according to s) to either the right or left (according to d) [1]. The structure of a p-shifter is shown in Figure 9.11. This structure contains log p nodes that represent the binary value of p, N+2p input nodes, and N output nodes. All the input nodes’ receiving frequency is tuned on a common frequency fadc, and the output nodes’ receiving frequencies on distinct frequencies. First the binary value of p is converted to analog as explained in Section 9.2.1. No additional node is required to keep this analog value, since all

xn+p−1

...

s

S/N_S

d

L/R

xn xn−1

xi

x0x−p x−1

... ...

...

x−p

P-Shifter

... ... yn−1 Shift register control pk−1 pk−2

y0

Inputs xn+p−1

p0

...

yi

...

1 P

xn

xn−1

...

xi fi+p fi−p

...

Outputs x0

x−1

...

x−p

yn−1

... ...

(Shift right) (Shift left)

Digital to analog converter

Figure 9.11. Structure of a nanoscale spin-wave p-shifter.

yi

... ...

y0

257

9.4. MORE COMPLEX NANOSCALE SPIN- WAVE DIGITAL MODULES

TAB LE 9 .1 1 . Frequency Assignments in the First Method of p-shifter Implementation Node Binary p inputs Input nodes Output node i

Sending frequency

Receiving frequency

fadc Variable (fi ) –

– fadc fi

the input nodes receive the analog value of p. Each input node knows its own index i and has received the value p. Depending on the shift direction d, each input node ﬁnds the index of the output node to which its data should be sent. If the shifter is in ‘‘shift to the right’’ status, each node xi should send its data to the output node with index i p; if it is in ‘‘shift to the left’’ status, the data is sent to the node with index i+p. Therefore node xi sends its data on frequency fip if d indicates shift to the right and on fi+p for shift to the left. Table 9.11 shows the frequency assignments for implementing a spin-wave p-shifter. Note that in order to use the same nodes as both input and output similar to a simple shifter, the shifting operation will have two main steps. In the ﬁrst step, all the nodes’ receiving frequency is tuned on a common frequency fadc so that all receive the analog value of p. In the second step, the nodes’ receiving frequencies are dynamically tuned on distinct frequencies to receive the data as explained in the previous method. Table 9.12 shows the frequency assignments for implementing a spin-wave p-shifter. This structure is shown in Figure 9.12.

9.4.2. Nanoscale Spin-Wave Priority Encoder A priority encoder is used to select, according to a predeﬁned priority, one of the several events that can occur simultaneously; the selected event is represented by an integer [1]. In this section we ﬁrst explain the design of a standard priority encoder with ﬁxed priority order, and afterwards, the implementation of a programmable priority encoder. SPIN-WAVE PRIORITY ENCODER. A standard priority encoder has N-bit inputs and k-bit outputs, where N = 2k. Unlike the binary encoder that can have one

TAB LE 9 .1 2 . Frequency Assignments in the Second Method of p-shifter Implementation Node Binary p inputs Input/output nodes (step 1) Input/output node i (step 2)

Sending frequency

Receiving frequency

fadc Variable (fi ) –

– fadc fi

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CHAPTER 9: NANOSCALE STANDARD DIGITAL MODULES

Inputs Outputs Shift register control pk−1 pk−2

...

yn−1 xn+p−1

p0 1

Shift right

...

xn

xn−1

...

yi xi

...

... ...

P

fi+d

Shift left

y0 x0

x−1

...

x−p

fi−d

Digital to analog converter

Figure 9.12. Structure of a nanoscale spin-wave p-shifter with overlapping input/ output nodes.

input with value 1, the priority encoder may have several 1-valued inputs. The output represents the index of the highest priority input having the value 1. The priority is a ﬁxed ordering implemented by the encoder; usually, xN1 has the highest priority, whereas x0 has the lowest [1]. The general way to implement a priority encoder is to have a module called ‘‘priority resolution’’ which keeps the highest priority 1 and sets all the other inputs to 0. These data will be the input to a standard binary encoder which gives the index of the only input with value 1. In implementing the spin-wave priority encoder, however, we do not use a ‘‘priority resolution’’ module to reset the lower priority 1-valued inputs to 0. Instead, we use spin-wave switches to force the waves in the desired direction and arrange the nodes in a fashion that the output node receives the index of the highest priority 1-valued input. The structure of a spin-wave priority encoder is shown in Figure 9.13. In this design, the highest priority node, xN1, is placed closest to the output node, while the lowest priority node, x0, the farthest. Note that in the structure shown in yk−1 Binary outputs: N = 2K

x0

x1

yi

...

xi

...

xN−1

...

i

yk−1

xN−1 Spin-wave switch

y0

A/D

Input

y0

... ...

... xi

Priority encoder

x0

...

Spin-wave bus

Figure 9.13. Structure of a nanoscale spin-wave priority encoder.

Analog out

259

9.4. MORE COMPLEX NANOSCALE SPIN- WAVE DIGITAL MODULES

Figure 9.13, the output node is placed on the right hand side of the inputs, so all the nodes should direct their waves to the right. First each node that has a value 1 turns off its left switch to direct the wave to the right. Next, it sends out a spin wave with an amplitude equal to its index and immediately turns off its right switch to block the wave coming from its left hand side. As a result, the output node will just receive the spin wave sent by the highest priority 1-valued node. This analog value is converted to digital at the output node. One application of priority encoder can the control of interrupt requests to a processor in a computer system. Since several interrupts might occur at the same time, a mechanism is required to determine which request should be handled. In such a scenario, a priority encoder can be used to identify the interrupting signal with the highest priority. SPIN-WAVE PROGRAMMABLE PRIORITY ENCODER. Similar to a priority encoder, a programmable priority encoder is used to select one of the several events that can occur simultaneously; however, in a programmable priority encoder, this selection is not according to a predeﬁned order, but at an order deﬁned at run-time. The output represents the index of the highest priority 1-valued input. The structure of a spin-wave programmable priority encoder is shown in Figure 9.14. This design includes a digital to analog converter, a shifter, and a priority encoder. First, the analog value of p, which shows the highest priority node’s index, is found by the digital to analog converter on frequency fadc. At this step, the receiving frequency of all the nodes, including the input and the output nodes, is tuned on fadc, so all receive p. In the next step, the data is rotated p times, so that the highest priority node is mapped to the closest node to the output. For rotating the data, each input node computes the sum of p and its index and ﬁnds the frequency of the destination node to which it should sent its data. For node xi, the index of the destination would be (i+p) mod N. After the rotation is done, the next step will be ﬁnding the index of the highest priority node that contains a 1. This step is performed as discussed in the implementation of a priority encoder. The spin-wave switches let the index of

yk−1

... xN−1

...

y0

... ...

... xi

Programmable priority encoder

x0

yi

yk−1

Binary priority input pk−1 pk−2

...

N = 2k

1

P Digital to analog converter

xi

... 1

y0

A/D

Input x0

p0

...

... findex

xindex

...

xN−1

y

2 index

Index = (i+p) mod N

pk−1 p0

Figure 9.14. Structure of a nanoscale spin-wave programmable priority encoder.

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CHAPTER 9: NANOSCALE STANDARD DIGITAL MODULES

TAB LE 9 .1 3 . Frequency Assignments in the Programmable Priority Encoder Implementation Node Binary p inputs Input nodes (step 1) Output node (step 1) Input nodes (step 2) Output node i (step 2)

Sending frequency Receiving frequency fadc – – Variable (fi ) –

– fadc fadc – fi

the highest priority node reach the output node. Note that this index is the index of the highest priority node when the data has been shifted p times. Therefore, as the last step, the output node ﬁnds [(received index-p) mod N] as the ﬁnal output of the programmable priority encoder. Table 9.13 shows the frequency assignments for implementing a spin-wave programmable priority encoder. The programmable priority encoder can be used to determine which interrupt request should be handled in the case that the priority order of the interrupts is not ﬁxed. For instance, a programmable priority encoder can be used in designing a ‘‘fair’’ system. In a fair system, whenever an interrupt request is handled, its priority becomes the lowest priority for the next interrupt handling cycle. By using a programmable priority encoder the winning interrupt node will determine the next priority order.

9.5. CONCLUSIONS In this chapter, we presented a set of nanoscale, standard combinational modules by exploiting the computing features of spin waves. We showed that a number of these widely used, standard arithmetic and logic digital modules including full adders, multipliers, decoders, encoders, multiplexers, and demultiplexers can be implemented by employing the concurrent write feature and superposition property of the spin waves. In addition, we demonstrated how to implement more complex modules such as priority encoders and shifters by using spin-wave switches. The universality of these modules ensures the possibility of realizing any logic switching functions. Sequential systems can be implemented by adding latches to the combinational circuit. The latches or D ﬂip-ﬂops can be easily simulated by the processing nodes. One possible extension of this research could the investigation of how nanoscale latches can be implemented using the nanoscale memory technology.

REFERENCES 1. M. Ercegovac, T. Lang, and J. Moreno. Introduction to Digital Systems. New York: Wiley, 1999.

REFERENCES

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2. C. Kittel. Introduction to Solid State Physics. New York: Wiley, 1986. 3. T. J Silva, et al. Inductive measurement of ultrafast magnetization dynamics in thinﬁlm permalloy. Journal of Applied Physics, 85(11): pp 7849–7862, 1999. 4. M. Covington, T. M. Crawford, and G. J. Parker. Time-resolved measurement of propagating spin-waves in ferromagnetic thin ﬁlms. Physical Review Letters, 89(23): p 237202-1-4.l, 2002. 5. A. Khitun and K. L. Wang. Nanoscale computational architectures with spin-wave bus. Superlattices and Microstructures, 38(3): pp 184–200, Sep. 2005. 6. A. Khitun and K. L. Wang. Nanologic circuits with spin wave bus. In: Proceedings of the Third International Conference on Information Technology: New Generations (ITNG’06). 7. A. Khitun, M. Bao, J. Y. Lee, K. L. Wang, D. W. Lee, S. Wang, and I. Roshchin. Inductively coupled circuits with spin wave bus for information processing. Submitted for publication in IEEE Transactions on Electron Devices, 2006. 8. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. A nanoscale architecture with spin-wave crossbar. In: Proceeding of the 6th IEEE Conference on Nanotechnology: pp 326–329, July 2006. 9. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. Nano-scale modules with full spin-wave interconnectivity. Journal of Experimental Nanoscience, 2(1–2): pp 73–86, Mar 2007. 10. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. A nanoscale reconﬁgurable mesh with spin-waves. In: Proceeding of the ACM International Conference on Computing Frontiers: pp 65–70, May 2006. 11. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. The spin-wave reconﬁgurable mesh and labeling problem. ACM Journal on Emerging Technologies in Computing Systems, 3(2, no. 5): July 2007. 12. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. Nanoscale modules with spin-wave intercommunications for integrated circuits. In: Proceeding of the NSTI Nanotech 2006, Boston: pp 320–323, May 2006. 13. S. Navab. Nanoscale standard combinational modules. 2007 World Congress in Computer Science, Computer Engineering, and Applied Computing WORLDCOMP’07. In: Proceedings of the 2007 International Conference on Computer Design (CDES’07): pp 10–16. 14. M. M. Eshaghian-Wilner and S. Navab. Efﬁcient parallel processing with spin-wave nanoarchitectures. Journal of Supercomputing, October 2008.

10 FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING Sumit Ahuja, Gaurav Singh, Debayan Bhaduri, and Sandeep Shukla In the recent past, CMOS manufacturing technology has been successfully downscaled to create feature sizes below 100 nm; it is predicted to reach the 22 nm mark very soon. But with the predicted demise of Moore’s law, continued success of the electronic industry will increasingly depend on emerging nanotechnologies. These emerging nanotechnologies have inﬂuenced the rapid development of nonsilicon nanodevices such as carbon nanotubes and molecular switches. CMOS or not, affordable manufacturing of defect-free nanosystems seems unlikely. Besides manufacturing defects, various transient faults will affect these systems. Therefore, there is a need for developing computing architectures that are tolerant to defects and faults and that may be one of the ways to avoid an industrial meltdown. This chapter provides a survey of techniques and architectures for providing defect- and fault-tolerance to nanocomputing.

10.1. INTRODUCTION 10.1.1. The Micro to Nano Trend For four decades, the rapid pace of improvement in microelectronics has been based on the ability to decrease the minimum feature sizes used to fabricate integrated circuits. The different parameters associated with integrated circuits that have improved due to such feature scaling are outlined in Table 10.1. One of the improvements that is frequently cited is the improvement in integration level; this is expressed as Moore’s law—the number of components per chip doubles every 24 months. Bio-Inspired and Nanoscale Integrated Computing. Edited by Mary Mehrnoosh Eshaghian-Wilner Copyright r 2009 John Wiley & Sons, Inc.

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TA B L E 1 0 . 1 . Parameters that have Improved Due to feature Scaling [1] Parameter

Example

Integration Level Cost Speed Power Compactness Functionality

Components/chip, Moore’s law Cost per function Microprocessor clock rate, GHz Laptop or cell phone battery life Small and light-weight products Nonvolatile memory, imager

The scaling of CMOS technology has faced many barriers, but clever engineering solutions and new device architectures have thus far broken through such barriers. However, the size of a silicon atom will be an indisputable barrier in CMOS scaling [2]. Since 2001, the ITRS Roadmap has challenged the practicality of CMOS scaling projections beyond MOSFET channel lengths of 9 nm and has addressed the need for non-CMOS technologies. In the recent past, a number of novel non-CMOS nanotechnologies have emerged that have shown potential in enhancing the CMOS platform; they have also demonstrated promise developing fundamentally new approaches to information processing. Chemical self-assembly of molecular devices is one such nanotechnology that has been proposed for the development of reconﬁgurable molecular nanofabrics. Some of these nanotechnologies have led to the development of exciting memory and logic nanodevices. Engineered tunnel barrier memory, polymer memory, and molecular memory are some of the novel nanomemories under research, whereas CNTs, RTDs, molecular and spin devices are some of the non-CMOS logic devices that have matured signiﬁcantly. These logic devices are predicted to have high switching speed, low power consumption, and good demonstrations of scaling potential. These nanodevices represent charge-based logic and their scaling is limited by the minimum switching energy per binary operation, also called the thermodynamic limit [3]. Beyond this limit, the challenge is to invent and develop nanotechnologies based on something other than electronic charge. Ferromagnetic logic and spin gain devices have been identiﬁed as some of the ﬁrst potential non-charge-based devices.

10.1.2. Challenges Nanoelectronics has advanced appreciably in the recent past, and it has shown potential for large scales of integration, speciﬁcally on the order of a trillion (1012) devices in a square centimeter. But at the same time, some of the characteristics of these nanodevices and their fabrication methods pose prominent limitations to such ultra-scale integration. Some of these characteristics are manufacturing defects, unreliable device performance, interconnect limitations, and thermal

10.2. FAULT TOLERANCE THROUGH REDUNDANCY

265

power dissipation [1, 4, 5]. The two major categories of defects occur because of interconnections and power dissipation. The unreliability of nanoscale devices is a consequence of the inherent variability in fabrication processes and the physical principles that govern their operation. Self-assembly methods may have to be used at dimensions below those for which conventional lithographic-deﬁned subtractive processing methods are used. Since variability and imprecision are inherent in such self-assembly processes, it is estimated that a signiﬁcant number of devices, up to many percent, may suffer from manufacturing defects. The other source of unreliability is due to the physical principles of these devices that cause reduced noise tolerance and higher susceptibility to external inﬂuences, such as electromagnetic interference, thermal perturbations, and terrestrial radiation, resulting in in-service transient faults. The problem of interconnects is due to a number of fundamental challenges. These are (i) the geometrical challenge of interconnecting devices at the nanoscale dimensions at high speed and bandwidth; (ii) the process of interfacing these devices with the macroscopic world; and (iii) the challenge of transforming longdistance communications to short-distance communications for nanodevices that have low drive capabilities. To tackle some of these challenges, fabrication processes for producing aligned wires and highly regular, homogeneous and locally connected parallel architectures have been proposed. The other challenge is thermal power dissipation that comes from device switching energy and the energy needed for driving signals. Due to this, there is a trade off between clock speed and device density—clock speeds need to be decreased for high device densities, and densities need to be lowered for high clock speeds. The problem of power dissipation sets a general limit to the operational speed of any charge-based nanodevice. To solve these problems, researchers are looking at approaches like charge recovery [6], reversible computing [7], and adiabatic computing [8].

10.2. FAULT TOLERANCE THROUGH REDUNDANCY For the management of defective and error-prone devices, several fault- and defect-tolerant nanoarchitectures have been proposed in order to aid the reliable integration of nanodevices, hence allowing the demonstration of their full potential [9]. Techniques such as redundancy and reconﬁguration are used in such architectures to achieve defect and fault tolerance. Here we discuss various redundancy techniques commonly used to achieve fault tolerance.

10.2.1. Structural Redundancy Redundancy has been widely used for fault tolerance in hardware. A structurally redundant architecture is one which mitigates the effects of faults in the devices and interconnects that make up the architecture and guarantees a given level of

266

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reliability. Various structural redundancy-based techniques such as triple modular redundancy (TMR), Cascaded triple modular redundancy (CTMR), von Neumann multiplexing and their variations have been proposed to provide fault tolerance in hardware. As opposed to structural redundancy, temporal redundancy entails repetition of the same computation if the computation fails to compute correctly. A classical temporal redundancy mechanism used in hardware is based on checkpoints and roll-back recovery [10, 11]. This chapter focuses on fault tolerance techniques based on structural redundancy. 10.2.1.1. Triple Modular Redundancy (TMR). The concept of TMR [12] is to have three functionally identical units working in parallel and comparing their outputs with a majority (MAJ) gate to produce the ﬁnal output. The units could be gates, logic blocks, logic functions, or functional units. TMR provides a functionality similar to one of the three parallel units but provides a better probability of working [12]. The MAJ gate is a single failure point and three of these can be used instead of just one to improve the reliability of the system further. The main drawback of simple, modular level TMR technique is that it does not provide robust error recovery mechanisms [13]. For example, if the triplicated units in TMR architectures have random logic with sequential elements and any one of the units are in error, there is no mechanism by which such an error can be detected until it manifests at the output of the modular unit. At that point in the execution of the system, the internal states of the erroneous and nonerroneous redundant modules will be inconsistent; Ref. 13 discusses the signiﬁcance of feeding back the voted result to all the voted sequential elements to resynchronize all the redundant modules and avoid error build up. This implies that a Boolean network needs to be apportioned into combinational and sequential parts; then, redundancy may be inserted. This is shown in Figure 10.1 where triple MAJ gates are used along with feedback.

Sequential logic

Combinatorial logic

MG

MG

Combinatorial logic

MG

MG

10.2.1.2. Cascaded Triple Modular Redundancy (CTMR). CTMR [12] is similar to TMR, wherein the units working in parallel are TMR units combined

Sequential logic

Sequential logic MG = Majority gate

Figure 10.1. TMR for sequential and combinational logic.

267

10.2. FAULT TOLERANCE THROUGH REDUNDANCY

x1 y1 x1 y1 x1 y1

x2 y2 x2 y2 x2 y2

x3 y3 x3 y3 x3 y3

1 bM MG

MG

Y1

MG

Z1

MG

X2

MG

Y2

MG

Z2

MG

X3

MG

Y3

MG

Z3

MG

Z

1 bM MG

X1

MG 1 bM

1 bM

MG = Majority gate

MG

MG = Majority gate

(a)

(b)

Figure 10.2. Different CTMR conﬁgurations. (a) Generic CTMR: multilayer voting; (b) CTMR with triple voters: smaller granularity.

with a MAJ gate. Figure 10.2a shows a ﬁrst-order CTMR conﬁguration where the parallel processing units in each of the three TMR units are NAND gates. Due to the area and latency overheads associated with this technique, the triplicated units in the CTMR with a multilayer voting scheme are normally functional units or logic blocks, not single gates as shown in Figure 10.2a. Since the triplicated functional units or logic blocks may consist of a large number of gates, their failure probability is more than individual gates. Hence, the multilevel CTMR with triple voters as shown in Figure 10.2b may be used to apportion the system into optimally sized functional units or logic blocks to effectively allow the architecture to withstand more errors across the triplicated units [14]. 10.2.1.3. Triple Interwoven Redundancy (TIR). The idea of TIR is based on von Neumann’s multiplexing techniques and interwoven redundant logic [15]. A TIR architectural conﬁguration has three times as many gates and interconnects as compared to the nonredundant network. The interconnections are arranged in random patterns. Such inherent randomness in the interconnections makes this structural redundancy technique favorable for the integration of molecular devices, since the manufacturing method for such devices is most likely to be stochastic chemical assembly. Figure 10.3 shows a nonredundant half adder and its corresponding TIR implementation. For a particular interconnect pattern, [16] shows that the TIR actually works as a TMR conﬁguration, implying that TMR is a speciﬁc implementation of TIR. 10.2.1.4. Multiplexing Techniques. Structural redundancy-based architectures that can circumvent transient faults can affect both the computation and communication in nanosystems. Interestingly, von Neumann addressed this issue

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Set A a1

A1

D1

A2

D2

a2 a3

A3

a b1

A

B1

b2

b D

E

E1 E2

B2

b3 B

D3 Set D

Set B

B3

E3

CS1 CS2 CS3

Set E

C1 C2 C C3

CC1 CC2 CC3

Set C

Figure 10.3. Nonredundant and TIR implementation of half adder.

in 1952 and developed a technique called multiplexing. He introduced multiplexing as a technique for constructing a system whose malfunction cannot be caused by the failure of a single device or a small set of devices. It has been identiﬁed as one of the most effective techniques for transient fault mitigation. Von Neumann proposed multiplexing architectures based on two universal logic functions—NAND and MAJ—which will be discussed in detail later in the chapter.

10.2.2. Information Redundancy Information redundancy, i.e., providing more information, is used in applications for error detection and correction to make systems more reliable. Below, some basic information redundancy techniques are discussed. 10.2.2.1. Parity. A parity bit is a binary digit that indicates whether the number of bits with value of 1 in a given set of bits is even or odd. There are two types of parity bits: even and odd. An even parity bit is set to 1 if the number of ones in a given set of bits is odd (thus making the total number of ones even). An odd parity bit is set to 1 if the number of ones in a given set of bits is even (thus making the total number of ones odd). If an odd number of bits (including the parity bit) are changed in transmission of a set of bits then parity bit will be incorrect and will thus indicate that an error during transmission has occurred. Therefore, parity bit is used as an error-detecting code. Note that it is not an errorcorrecting code as there is no way to determine which particular bit is corrupted. If an error occurred during transmission, then the entire data must be discarded, and retransmitted from scratch.

10.3. DEFECT TOLERANCE THROUGH RECONFIGURATION

269

10.2.2.2. Cyclic Redundancy Check (CRC). The CRC is a very powerful and easily implemented technique to obtain data reliability. CRC is a type of hash function used to produce a checksum, a small ﬁxed number of bits against a block of data. The checksum holds redundant information about the block of data that helps the recipient detect errors. A CRC is computed and appended before transmission or storage, and veriﬁed afterwards by the recipient to conﬁrm that no changes occurred during transmission. It is one of the most widely used techniques for error detection in data communications. The technique is popular because CRCs have extreme error detection capabilities, have little overhead and are easy to implement. Moreover, they are simple to implement in binary hardware and are easy to analyze mathematically. Even parity is actually a special case of a CRC, where the 1-bit CRC is generated by the polynomial x+1. 10.2.2.3. Error-Correcting Code (ECC). An error-correcting code is an algorithm for expressing a data signal such that any errors which are introduced can be detected and corrected, within certain limitations, based on the other parts of the signal. In an ECC, each data signal conforms to speciﬁc rules of construction so that departures from this construction in the received signal can generally be automatically detected and corrected. It is used in computer data storage and transmission. The simplest error-correcting codes can correct singlebit errors and detect double-bit errors. There are other codes which can detect or correct multi-bit errors. Some of the examples of ECC are Hamming code, BCH code, Reed-Muller code, Binary Golay code, and convolutional code. ECC-based computer memory provides greater data accuracy and system uptime by protecting against soft errors.

10.3. DEFECT TOLERANCE THROUGH RECONFIGURATION Chemically self-assembled molecular nanofabrics are by nature very regular and homogeneous, hence, well-suited for reconﬁgurability [17–19]. It is reported that the reconﬁguration is the most effective technique to cope with manufacturing defects in nanodevices. Reconﬁgurable fabrics are composed of programmable logic elements [like conﬁgurable logic blocks (CLBs)] and interconnects which can be conﬁgured to implement any logic circuit. It is expected that reconﬁgurable fabrics made from next generation fabrication processes will go through a postfabrication defect mapping phase during which these fabrics are conﬁgured for self-diagnosis [20, 21]. Thus, defect tolerance in such fabrics can be achieved by detecting faulty components during an initial defect map phase and excluding them during actual conﬁguration. In other words, design of reliable digital logic and architectures on unreliable nanofabrics will require defect mapping followed by defect avoidance to circumvent hard faults. Defect mapping is the process of ﬁnding defect locations in a nanofabric, and defect avoidance is the process of mapping a computing logic on a faulty nanofabric knowing its defect-maps.

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While such reconﬁgurable architectures may aid in circumventing manufacturing defects at the nanoscale, they will not provide tolerance to natural external transient faults. The addition of structural redundancy a priori may enhance the reliability of such systems in the presence of transient faults. There are two general classes of defect mapping and avoidance techniques: (i) techniques that use test circuits to ﬁnd the location and number of defects on a reconﬁgurable nanofabric [19, 21], and (ii) broadcast-based methods that ﬂood test packets through the whole nanofabric to locate nonreachable nodes [22]. The test circuits or packets placed on the fabric during the self-diagnosis phase utilize resources that are available later for normal logic mapping. Although such defect mapping techniques can be performed with massive parallelism, they have been reported to be expensive in terms of cost and time. In [23–25], a defect-mapping and hierarchical redundancy insertion methodology is presented which is discussed below in detail. First, we present the target nanofabric and fault models for this methodology followed by the details of the methodology and a proposed automation framework.

10.3.1. Nanofabric and Fault Models 10.3.1.1. Nanofabric Model. The target nanofabric model is composed of processing elements (PEs) built from crossbars. Figure 10.4 shows a nanofabric composed of a grid of PEs connected together. This model is a combination of the nanofabric models used in [22] and [26]. The PEs are modeled to function as simple single-bit arithmetic logic units (ALUs), 8-bit adders or 8-bit combinational multipliers depending on the application being targeted. In this model, each PE has 4 transceivers that are connected to the 4 asynchronous bidirectional interconnects. Figure 10.4 also shows vias that are used to interface the nanofabric with external circuitry. The nanofabric model has three levels of hierarchy: regions, mapping units (MUs) and components (defect-mapping technique discussed in [22] uses a monolithic model). 10.3.1.2. Fault Model. The fault model considers the effects of both manufacturing defects and transient faults. Since the proposed work focuses on crossbar-based nanofabrics, the faults relevant to such nanofabrics are discussed. The manufacturing defects in the crossbar cause stuck-open and stuck-closed faults at the junctions and wires. Since the yield of the crossbar is very low in the presence of stuck-closed faults, it is possible to bias the chemical self-assembly process to decrease the probability of such faults [19]. Hence, only stuck-open faults at the junctions and wires are considered. The methodology [23–25] models these faults as the probability of failure to program the molecular diodes or latches to the appropriate logic value. Also, the faults at the interconnects are modeled as Gaussian failure distributions that quantify the effect of signal noise. It is also assumed that the faults at the junctions and interconnects are independent, identical and uniformly distributed (i.i.u). This fault model can be changed in the proposed toolset discussed below and the

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10.3. DEFECT TOLERANCE THROUGH RECONFIGURATION

Via2

Via1

Via5

Via3

20x10 Grid

Via4

Figure 10.4. Molecular Nanofabric.

current model is used to represent the fault classes that have the highest probability of occurrence in chemical self-assembly fabrication processes.

10.3.2. Methodology The instance-based methodology proposed in [23–25] can be used to design and analyze molecular logic systems. The methodology entails (i) developing a script to translate speciﬁcations of molecular nanofabric instances in terms of number of PEs, size of crossbar for each PE, etc. into probabilistic transition models, (ii) determining the exact failure probability of each junction by running test circuits physically on the nanofabrics and using these values on the nanofabric models to generate probabilistic defect maps, (iii) developing a script to insert behavioral redundancy in the designs and/or structural redundancy at the different structural hierarchies of the nanofabrics and (iv) developing Markovian and state space traversal techniques to analyze redundant instances of different designs that are mapped onto the nanofabrics. Many speciﬁc design instances have to be analyzed by this methodology to predict general performance trends of general structurally redundant architectures, a drawback that is common for instance-based methodologies. This issue is addressed by hierarchical modeling and state space partitioning techniques discussed later in this section. 10.3.2.1. Test Circuits. The probabilistic defect mapping technique is based on limited on-line testing of nanofabrics. Simple test circuits are conﬁgured on the nanofabrics to get a notion of the probability of the crossbar-based PEs being

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defective. One of the easiest test circuits proposed for such purposes is a counter circuit [21]. Counter circuits with thresholds of t can indicate 0,1,2,y,t or more than t defects. Since the lowest element of the structural hierarchy are regions (composed of 8 PEs), the threshold of such a test circuit may be set to 8. Another set of simple circuits that can be used for this purpose are linear feedback shift registers (LFSRs). LFSRs are used widely in built-in self test (BIST) of RAMs. These can be conﬁgured on MUs and run autonomously with sets of inputs. parallel signal analyzers (PSAs) are also conﬁgured on the MUs. These PSAs are used as parallel-to-serial compression circuits to avoid testing large number of pseudo-random vectors generated by the LFSRs. The compression of a number of patterns using a PSA is called a signature. If there are signature mismatches, the LFSRs may be split into smaller units and conﬁgured on each region of the speciﬁc MU instance. Note that even then if there are no signature mismatches, it does not mean that the constituent nodes are defect free. This is due to a non-zero probability of aliasing. A way to minimize this aliasing problem is to use maximal-length PSAs and to frequently compare the signatures with the expected values [27]. The test circuits discussed here are just a small subset of the different test circuits that can be used to compute the probability of PEs being defective. The crossbar junction failure probability can be computed using these probabilities. Note that determining the junction failure probability is required for both the defect mapping and structural redundancy insertion methodologies, since logic functions need to be mapped to the crossbar-based PEs in both the cases. 10.3.2.2. Defect-Mapping Technique. The proposed nondeterministic defect-mapping technique [23–25] is based on a variant of the RPF broadcast scheme [22] and on the defect-mapping methodology proposed in [21]. Simple test circuits from [21] are conﬁgured physically on the nanofabrics to determine the probability of the crossbar junctions being defective. These defect rates are used in determining the probability of successfully conﬁguring all the PEs with the same broadcasting functionality. Once this conﬁguration probability is computed, probabilistic models representing such PE-based nanofabrics are constructed and the broadcast-based algorithm is used to determine the reachability graph of each PE from the vias. The broadcast-based algorithm used is a modiﬁcation of the deterministic algorithm proposed in [22]. The algorithm has been modiﬁed such that defect maps represented by probabilistic broadcast trees can be generated, hence reﬂecting the non-deterministic defects in molecular nanofabrics. In this algorithm, the probability of a PE being reached depends on the probability of the packet reaching the previous PE that forwarded the packet and the probability of the interconnect on which the packet was transmitted being defect free. The methodology also stores the via number from which a PE is reachable with highest probability, since this facilitates the physical logic conﬁguration of the fabric at a later stage if there is more than one available via. Since the methodology applies this modiﬁed broadcasting algorithm on a nanofabric model, the dynamics of the

10.3. DEFECT TOLERANCE THROUGH RECONFIGURATION

273

physical broadcast are mimicked in the model. Note that the broadcast-based part of the defect-mapping technique is executed off-line, i.e., on an external system. The methodology also partitions the nanofabric models to decrease the computational complexity of the off-line probabilistic broadcasting algorithm. A molecular nanofabric is partitioned into equal-sized smaller units such that the algorithm can be run simultaneously on all the units. This implies that in certain cases some of the PEs may be a part of more than one unit and hence can be reached from more than one via. The defect-mapping mechanism pin-points the via from which a speciﬁc PE can be reached with the highest probability. If the highest probability value of reaching a PE from any of the vias is lower than a user-speciﬁed threshold, that PE is marked defective. In summary, the methodology combines the good features of test circuitbased and broadcast-based defect mapping techniques. The differences between this methodology [234–25] and the methodologies in [21, 22] are as follows: [21] uses extensive on-line testing to improve the recovery metric whereas this methodology only uses limited on-line testing. [22] proposes a deterministic broadcast algorithm that has been extensively modiﬁed to a non-deterministic broadcast algorithm. [23] generates on-line defect maps by physically broadcasting test packets in the nanofabrics whereas in the methodology discussed such broadcasts are mimicked in the nanofabric models. The discussed methodology uses state space partitioning techniques on the nanofabric models to improve off-line computational complexity. This was not considered in both [21, 22]. 10.3.2.3. Hierarchical Redundancy Insertion Methodology. The problem of mapping logic onto ultra-dense nanofabrics has been handled well in [26]. In this methodology, the same procedure is used to map covers of different designs onto the structural hierarchy of the nanofabric models. Note that a cover is the decomposition of a monolithic data ﬂow graph (DFG) of a design, where a DFG of a design represents the behavior of a design. Since there can be more than one way of decomposing a DFG for a system into a cover, the DFG of a system may have more than one cover. Figure 10.5 shows one of the possible covers for an auto regression (AR) ﬁlter design. This procedure is extended so that behaviorally redundant systems can be mapped onto structurally redundant molecular nanofabrics. Redundancy can be added to the covers by replicating the nodes. Figure 10.6a shows how a nonredundant cover with a single ﬂow changes to a cover with two ﬂows when an operation (Node 1) is triplicated. Similarly, structural redundancy can be inserted either at the crossbar level; by adding columns or at any of the three tiers of the nanofabric hierarchy. Figure 10.6b shows TMR conﬁgurations for the different structural hierarchies. The TMR conﬁgurations are representative examples of structurally redundant fault-tolerant conﬁgurations. The discussed hierarchical

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Flow 0

Flow 1

Flow 2

Flow 0

Flow 2

Flow 1

Figure 10.5. Cover for AR ﬁlter design.

A0

B0

A1

B1 PE

A

PE

PE

B B2

A2

Node 1 is triplicated

1

PE Voter

Region Voter

TMR at the PE level 2 Flow 3

TMR at the region level 3

4 2 Flow 5 3

4 Flow 2 Mapping unit

(a) Voter

TMR at the MU level

(b)

Figure 10.6. Behavioral and structural redundancy.

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10.3. DEFECT TOLERANCE THROUGH RECONFIGURATION

redundancy insertion methodology maps the non-redundant or redundant covers of the systems onto the structurally redundant nanofabrics by generating pseudorandom maps. These pseudo-random maps (i) avoid defective components if and only if a defect map is available for the nanofabric, since a designer can opt not to generate a defect map, (ii) introduce redundant structural units at the different hierarchies of the nanofabrics, and (iii) attempt to reduce routing latencies while inserting structural redundancy. As part of this work, scripts are developed that use these maps to hierarchically translate each primitive ﬂow of the covers onto the structurally redundant nanofabric models. The stress is on hierarchy, since the computational time required for steady state probability analysis of hierarchically mapped designs is less as compared to ﬂat models [28]. Such a speciﬁc behavioralstructural mapping of a design is called a cover-map. 10.3.2.4. Design Flow. Figure 10.7 shows the design ﬂow of the proposed design and analysis methodology. Below, the different steps are outlined in detail. 1. Test circuits are run physically on the nanofabric to compute the approximate junction defect rate. A model of the speciﬁc molecular

Molecular nanofabric

1. Build model in SMART Probability of each PE being reachable

Broadcast mechanism

3. Analyze broadcast coverage and network connectivity

2. Probabilisitic defect map

4. Inject signal noise on interconnects

7. Granularitybased redundancy insertion Generate configuration bits

Hierarchical mapping

No

5. Translate systems onto nanofabric

6. Meets specification? Reliability, area, cost, delay Yes

Figure 10.7. Design Flow.

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2. 3.

4.

5.

6.

7.

nanofabric is built in SMART [29] (SMART is probabilistic model checking tool which can be used to model and analyze complex probabilistic systems) by creating an array of PEs and interconnects. Since each PE needs to have some functionalities to support the proposed broadcastbased algorithm, the nanofabric model enforces that each PE must at least have logic functionalities to support 4 transceivers, a simple single bit ALU and control circuitry for routing. The junction defect rate is used to compute the probability of the PEs being successfully conﬁgured to achieve such minimal functional capabilities. The nondeterministic broadcast-based algorithm (Section 3.2.2) is used to generate a defect map, if the designer opts to generate one. If a defect map is generated, the designer can analyze the performance of the defect mapping scheme in terms of the broadcast coverage and recovery. A transient fault injection library is developed to model signal noise at the interconnects. This library can be used to model noise as Gaussian distributions with different means and variances. The hierarchical logic mapping scheme proposed in [26] and the pseudorandom maps are used to translate a nonredundant or redundant cover (Fig. 10.6) onto the nanofabric model composed of regions, MUs, and components. The mapped design is analyzed to check conformance to required speciﬁcations in terms of reliability, cost, latency and area. If the speciﬁcations are met, the system is physically conﬁgured on the nanofabric. If the speciﬁcations are not met, structural redundancy is added at the different hierarchies of the nanofabric by using the redundancy insertion methodology discussed above.

This methodology can be applied for the design and analysis of missioncritical systems and systems that can tolerate certain degrees of failure as shown in Figure 10.8. If the system is mission-critical and needs a reliability guarantee that is arbitrarily close to 100%, the probabilistic defect mapping mechanism can be used with high reachability threshold values—implying that each PE needs to be accessed from one of the vias with very high probability. PEs that are not reachable are marked defective and are not considered while mapping the system onto the nanofabric. The nondefective nodes are partitioned into regions, MUs and components, and the DFG of the system is mapped to the defect mapped nanofabric model with suitable redundancy. If the system can tolerate low but nonzero failure probabilities, it may not be required to generate defect maps for the nanofabric. Instead, such a system can be mapped onto the defective nanofabric with suitable redundancy. These will allow the system to be tolerant to transient faults, achieve the required reliability guarantee and entail less computational complexity for its design. In both the system types, the value of R and architectural level for redundancy insertion is dependent on the system and

10.4. RELIABILITY EVALUATION OF DEFECT/FAULT- TOLERANT NANOCOMPUTING

Direct mapping

Non-mission critical systems

Defect prone reconfigurable nanofabric

Defect mapping

System tolerant to transient errors

Computationally less expensive and time-consuming

Design

Mission critical systems

Structural redundancy

277

Defect mapped reconfigurable nanofabric

Structural redundancy

System tolerant to both permanent and transient errors

Figure 10.8. Application of our methodology.

its operational environment, hence, determining these parameters is experimental. The toolset is used to determine whether these parameters provide the necessary reliability without causing unacceptable delay, area and cost penalties.

10.4. RELIABILITY EVALUATION OF DEFECT/FAULT-TOLERANT NANOCOMPUTING As discussed earlier, due to increased defects in nanoscale devices, designing reliable digital circuits with such devices is a major challenge. Development of accurate reliability estimation methodologies is critical in analyzing the robustness of circuits designed from unreliable nanoscale devices. Recently, a number of methodologies have been developed to evaluate circuit reliability, methodologies that analyze the reliability independent of the technology used to fabricate nanoscale devices. Methodologies based on probabilistic model checking (PMC) have been developed to evaluate circuit architecture reliability and demonstrated its applicability at the logic gate and logic block levels. [30, 31] developed matrix-based gate-level models called probabilistic transfer matrices (PTM) that are used for circuit reliability analysis. Concurrently, but independently [32], proposed a technique to develop probabilistic models called probabilistic gate models (PGM) for unreliable logic gates and used these models to analyze the circuit reliability.

10.4.1. Probabilistic Model Checking (PMC) PMC is an algorithmic procedure for ascertaining whether a given probabilistic system satisﬁes probabilistic speciﬁcations such as the probability of logical correctness at the output of a logic network must be at least 90% given that each

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gate has a failure probability of 0.001. The system is usually modeled as a state transition system with probability values attached to the transitions. Examples of such transition systems are discrete time Markov chains (DTMCs), continuous time Markov chains (CTMCs) and Markov decision processes (MDPs). The speciﬁcations or properties to be veriﬁed are speciﬁed typically in probabilistic extensions of temporal logic. A probabilistic model checker applies algorithmic techniques [33] to analyze the state space of the input model to verify the probabilistic properties. The two most common temporal logics used for specifying properties of probabilistic systems are PCTL [34, 35] and CSL [36, 37], both extensions of the logic CTL. PCTL is used to specify properties for DTMCs and MDPs and CSL is used for CTMCs. One common feature of the two logics is the probabilistic P operator. For example, the formula P1 ½} terminate states that the system will eventually terminate with probability 1. On the other hand, the formula P0:95 ½:repair U 200 terminate asserts that the system should terminate within 200 time steps without requiring any repairs with a probability 0.95 or greater. In addition to the P operator, CSL also provides the S that helps in specifying steady-state behavior. For instance, So0:01½queue size ¼ max states that the probability that a queue is full is strictly less than 0.01 in the long run. Further properties can be analyzed by introducing the notion of costs (or, conversely, rewards). If each state of the probabilistic model is assigned a real-valued cost, one can compute properties such as the expected cost to reach speciﬁc states, the expected accumulated cost over some time period, or, the expected cost at a particular time instant. Methodologies based on PMC techniques can be applied to evaluate the reliability of nanoarchitectures. PMC-based tools like PRISM [38] and SMART [29] can be used for such analysis. PRISM [38, 39] is an example of model checker that supports the analysis of three types of probabilistic models: DTMCs, CTMCs and MDPs. DTMCs can be used to model conventional digital circuits since DTMCs are suitable for such modeling [12]. The DTMC model of computation speciﬁes the probability of transitions between states such that the probabilities of performing a transition from any given state sums up to 1. Modeling of faulttolerant architectures can be done as templatized DTMCs with probabilistic assumptions about the occurrence of noise at the gates and interconnects and using Markov analysis techniques to evaluate different properties of the architectures. In [40, 41] PMC is used to evaluate the reliability of small circuits assuming that each gate fails independently. Circuits are speciﬁed as DTMCs, due to their suitability for modeling digital systems [12]. The reliability of a circuit is evaluated by computing the probability of reaching speciﬁc DTMC states, states that represent the correct Boolean values at the circuit outputs for a certain probability distribution at the inputs. Below, we discuss this PMC-based reliability estimation methodology with an illustrative example. Figure 10.9 shows the DTMC for a NAND gate with inputs A0 and B0, and output out. The DTMC has 15 states and 22 transitions. The state variables are s, A0, B0 and out, where s is used to represent the level in the DTMC. Formally, each

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10.4. RELIABILITY EVALUATION OF DEFECT/FAULT- TOLERANT NANOCOMPUTING

A0 Out

B0 s=0

0 0.9

0.1 1

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7

s=2, B0=0

4 0.99

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9

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s=3, s=3, s=3, s=3, Out=A0B0 Out=1−A0B0 Out=A0B0 Out=1−A0B0

s=2, B0=1

5 0.99

0.01 1.0

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s=3, s=3, s=3, s=3, Out=A0B0 Out=1−A0B0 Out=1−A0B0 Out=A0B0

Each state is encoded as (s, A0, B0, out) DTMC states = 15, DTMC transitions = 22, MTBDD nodes = 52, terminals = 6

Figure 10.9. DTMC of a NAND gate.

DTMC state is encoded as a quadruple ðs; A0; B0; outÞ, where s 2 f0; 1; 2; 3g and A0, B0 and out are Boolean variables. The transitions in Figure 10.9 have probability values attached to them. For instance, the probability of 0.9 for transitioning from state 0 (encoded as (0,0,0,0)) to state 2 (encoded as (1,1,0,0)) implies that input A0 has a 0.9 probability of being stimulated, i.e., being in logic ‘‘1’’ state. Similarly, a 0.01 probability of moving from state 6 (2,1,1,0) to state 14 (3,1,1,1) implies that the NAND gate can fail independently with a 0.01 probability. Figure 10.10 is a one step transition probability matrix of the DTMC in Figure 10.9. Each row of the matrix represents the transition ﬂow out of the corresponding state. For instance, the ﬁrst row of the matrix shows that there is a probability of 0.1 for transitioning from DTMC state 0 to DTMC state 1, and a probability of 0.9 of moving from state 0 to state 2. Since the accumulative transition ﬂow out of each state must be 1 in a DTMC, the rows of the matrix must sum to 1. Usually these probability matrices are sparse, and can hence be represented compactly. PRISM uses multiterminal binary decision diagrams (MTBDDs) to represent these matrices. MTBDDs were introduced in [42] as a generalization of binary decision diagrams (BDD) [43]. Like BDDs, they are rooted directed acyclic graphs whose non-terminal nodes are labeled with Boolean variables from an ordered set. However, unlike BDDs, the terminal nodes are labeled with values from a ﬁnite set M, where usually M P, not just 0 and 1. An MTBDD with n Boolean variables and terminals from M can be considered as a map f : f0; 1gn ! M.

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0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0

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0:0 0:0 0:0 0.99 0:0 0:0 0:0 0:0 1:0 0:0 0:0 0:0 0:0 0:0 0:0

0:0 0:0 0:0 0.0 0:01 0:0 0:0 0:0 0:0 1:0 0:0 0:0 0:0 0:0 0:0

0:0 0:0 0:0 0.0 0:99 0:0 0:0 0:0 0:0 0:0 1:0 0:0 0:0 0:0 0:0

0:0 0:0 0:0 0.0 0:0 0:01 0:0 0:0 0:0 0:0 0:0 1:0 0:0 0:0 0:0

0:0 0:0 0:0 0.0 0:0 0:99 0:0 0:0 0:0 0:0 0:0 0:0 1:0 0:0 0:0

0:0 0:0 0:0 0.0 0:0 0:0 0:99 0:0 0:0 0:0 0:0 0:0 0:0 1:0 0:0

0:0 0:0 0:0 0.0 0:0 0:0 0:01 0:0 0:0 0:0 0:0 0:0 0:0 0:0 1:0

Figure 10.10. Transition probability matrix for NAND DTMC.

[42] shows how to represent probability matrices as MTBDDs. Consider a square 2m 2m matrix A (non-square matrices can be padded) with elements from M. Its elements aij may be viewed as values of a function fA : f1; ; 2m g f1; ; 2m g ! M, where fA ði; jÞ ¼ aij . Using the Boolean encoding c : f0; 1gm ! f1; ; 2m g, fA may be interpreted as a Boolean function f : f0; 1g2m ! M, where f ðx; yÞ ¼ fA ðcðxÞ; cðyÞÞ for x ¼ ðx1 ; ; xm Þ and y ¼ ðy1 ; ; ym Þ. The variables for the rows and columns are interleaved, implying that the MTBDD interpreted from the function f ðx1 ; y1 ; ; xm ; ym Þ can be used to represent the matrix A. This interleaving imposes a recursive structure from which efﬁcient recursive algorithms for all matrix operations are derived [42]. For instance, the transition probability matrix of Figure 10.10 can be represented as a MTBDD with Boolean row variables s0 ; s1 ; A0 ; B0 ; out and column variables s00 ; s01 ; A00 ; B00 ; out0 . Note that since s 2 f0; 1; 2; 3g, it is encoded as f0; 1g2 ! f0; 1; 2; 3g. f ðs0 ; s00 ; s1 ; s01 ; A0 ; A00 ; B0 ; B00 ; out; out0 Þ is the interleaved function from which the MTBDD is interpreted in this case. Figure 10.9 indicates that only 52 MTBDD nodes are required to represent the 15 15 probability matrix. Thus, the PMC-based methodology entails modeling circuits as DTMCs and the PRISM tool uses compact MTBDDs to represent and analyze the DTMCs. 10.4.1.1. Evaluating Multiplexing Architectures. The effect of noisy communication on computing systems has been theoretically analyzed in terms of information theoretic entropy, and bounds have been established on the noise levels that can be tolerated during transmission [44]. Error-correcting codes have been used extensively to abate transient faults at interconnections [45, 46]. The theory to treat the effect of noise on gates was ﬁrst developed by von Neumann [47], and later extended in [3, 48–54]. In his seminal work [47], von Neumann proposed a gate-level fault tolerance technique called multiplexing (MUX) for both the majority (MAJ) and NAND

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gates. He also showed analytically how a NAND MUX architecture can be used to enhance the reliability of a system in the presence of limited computation noise and large bundle size (N). Bundle size (N) is deﬁned as the number of replicated transmission lines and redundancy factor (R) is deﬁned as the ratio of the circuit sizes of the redundant and nonredundant designs for a nanosystem. Note that R is dependent on the value of N. Reliability evaluation of multiplexing (MUX) architectures is based on PMC technique discussed earlier in this chapter. Von Neumann addressed a fundamental problem in his seminal work [47], the problem that the probability (d) of malfunction of a system cannot be less than probability (e) of failure of the last device in the design. He proposed multiplexing (MUX) as a technique to achieve doe. The main trick behind MUX is in replacing a single transmission line by a bundle of N parallel transmission lines. Since a signal bundle is used to carry messages, a single logic gate is replaced by N copies. The N devices process the signals in parallel to give N outputs. Each element of the output set will be identical and equal to the original output of the logic gate, if all the copies of the inputs and devices are reliable. However, if the inputs or devices are in error, the outputs will not be identical. To tackle such an error-prone scenario, von Neumann deﬁned a critical level D 2 ð0; 0:5Þ. The output of the MUX unit is considered stimulated (taking logical value true) if at least ð1 DÞ N of the outputs are stimulated and non-stimulated (taking logical value false) if no more than D N outputs are stimulated. Any other number of stimulated lines is interpreted as a malfunction. The MUX unit formed by the signal bundles and logic gates is known as the executive stage since this performs the basic logic function. In Figure 10.11, the executive stage of the NAND and MAJ MUX consist of N NAND and MAJ gates, respectively. The advantage of implementing this technique at the gate level is to increase the reliability of the basic building blocks of a logic network, hence, enhancing the reliability of more complex units built from these. In [47], von Neumann observed that for MAJ MUX whose outputs are governed by a two-to-one majority of the input bundles (two inputs are either stimulated or non-stimulated while the third one represents a different logic state), the error at the output bundle is the sum of errors in two governing input bundles.

(K1)

(K0)

(K2)

(K3)

X

M M

Y (K1) Y U

Executive stage

U

Restorative stage (a)

Z

M

M Random permutation (U)

X

X

M

M

M

M

M

Y

M

Z

Executive stage Restorative stage

M

Executive stage (b)

Figure 10.11. Original von Neumann MUX schemes.

M U

Restorative stage

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Similarly, the output bundle error for a NAND MUX system is the sum of the errors at the two input bundles, if both the input bundles are prevalently stimulated. This implies that certain worst-case input conﬁgurations may produce outputs lying in the intermediate region of uncertain information. Thus, von Neumann proposed that a logical stage is required to transform an input bundle with a stimulation level close to zero or one into an output bundle with stimulation level closer to the corresponding extremes [47]. Hence, the von Neumann multiplexed systems must contain a signal restoration stage that reduces the degradation caused by the executive stage for certain input bundle conﬁgurations. The signal carried by each input bundle of an executive stage can be thought of as a probability wave that deviates from the prevalent logic values due to signal noise at the executive stage gates. The purpose of a restorative stage is to counteract this deviation and increase the probability of the output bundle being in a valid stimulated or non-stimulated state. Figure 10.11 shows the restorative stages for the NAND and MAJ MUX schemes. Correlation between the input bundles will destroy the signal restoration process, hence, the logic circuit U (see Fig. 10.11) provides a randomizing effect to provide statistical independence between the output bundle of the executive stage and the input to the parallel NAND or MAJ gates that form the restorative stage. The number of restorative stages can be increased arbitrarily, but it has been shown in [41, 55] that the output distributions of the MUX systems stabilize very quickly as the number of restorative stages increases while causing degradation in speed and increase in the redundancy factor R. It can be observed from Figure 10.11, that R for a MUX system is computed as a function of the bundle size (number of replicated gates in each MUX stage) and the number of MUX stages. For NAND MUX, R is computed as Bundle Size (1+2 Number of Restorative Stages), whereas, for MAJ MUX, R is evaluated as Bundle Size (1+Number of Restorative Stages). For instance, a NAND MUX system with a bundle size of 10 and 2 restorative stages (5 MUX stages) has a R of 50, and a MAJ MUX system with a similar conﬁguration has a R of 30 (3 MUX stages). Although von Neumann had proposed both NAND and MAJ MUX systems in [47], most researchers extended his analysis of the NAND MUX architecture. von Neumann had analyzed the NAND MUX system for NW1000 by exploiting the Gaussian nature of the output distribution. This theory was extended to No1000 in [55], and it was proved that the output distribution is binomial for smaller values of N. [56] introduces a modiﬁcation of the von Neumann NAND MUX technique called parallel restitution. Parallel restitution is simply a methodology to apply the NAND MUX scheme to a large system to make it fault-tolerant to noise. [57] was probably the ﬁrst theoretical attempt at analyzing the reliability of MAJ MUX. In that work, the authors analyzed the reliability of MAJ MUX architectures theoretically for small R and extended this scheme by eliminating unnecessary restorative stages. The integration of reconﬁgurable architectures and NAND MUX has also been evaluated in [16] to circumvent both permanent and transient faults. In [58–60], different fault-tolerant techniques including NAND MUX were used on a chip

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composed of 1012 devices to compare their fault mitigation potential. It was shown that a NAND MUX based architecture on such a chip could be reliable 90% of the time if the devices had a failure probability r0.01, however, the R required to achieve this was E106. Reference [28] provides a comparative study of the von Neumann NAND and MAJ MUX architectures. These comparisons have been made in the presence of (i) only noisy gates and (ii) noisy gates and interconnects, for different values of R. Some of the results are discussed below. The ﬁrst ﬁve results are obtained in the presence of only noisy gates while the rest of them are determined in the presence of both noisy gates and interconnects. For large gate failure probabilities, the performance of the MAJ MUX architecture is substantially better than the NAND MUX system. As the gate failure probability increases beyond a certain threshold, increasing N degrades the performance of the NAND MUX system. But for MAJ MUX, increasing N results in marginal improvement of performance. For small gate failure probabilities, the performance of the MAJ MUX architecture is better than NAND MUX at lower R. But both MUX architectures tend to reach similar steady state reliability values at higher R. For small gate failure probabilities, the increase in N results in a higher probability of malfunction. This is because the chance of error introduction due to more noisy gates may be counterproductive [57]. Hence a higher R is required to improve the performance of the architecture. This is true for both MUX schemes. The individual device failure probabilities that can be tolerated by incorporating a MAJ MUX scheme with 50rRr100 on a chip are determined and compared to theoretical results. MAJ MUX has a higher reliability than NAND MUX in the presence of small and large noise spikes at the inputs and interconnects. In the presence of signal noise at the inputs and interconnects, a MUX system with a large bundle size N must have higher R to provide better reliability than a MUX system with small N.

10.4.2. Probabilistic Transfer Matrices (PTMs) PTMs have been used in [61] to model defective logic gates using matrix representations, an idea that dates back to [62]. The PTM for a NAND gate with a failure probability of e is given by 2 6 6 PTMNAND ¼ 6 4

e e e 1e

3 1e 1 e7 7 7; 1 e5 e

ð10:1Þ

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and its output probability is given by ½p0 p1 ¼ ½p00 p01 p10 p11 PTMNAND . The PTM representation encompasses all the input combinations of the NAND gate and hence is very similar to logic compatibility functions (Section 4.4) or DTMC models (Section 4.1) for NAND logic. A PTM for a speciﬁc circuit is formulated by composition of the gate PTMs, the composition being dependent on the logic dependency of the circuit. The authors propose a framework in [31] based on PTMs that can be used for computing the output probabilities for combinational circuits. This involves the composition of gate PTMs in terms of the logic dependency of a circuit. This composition technique takes into account signal dependencies between gates by considering the underlying joint probabilities; it also considers the effects of logical masking. The authors in [31] use algebraic decision diagrams (ADDs) to alleviate a potential memory bottleneck for PTMs representing large circuits. The ADD representations result in elimination of identical information and compression of the PTMs. PTM operations such as probability value extraction are performed on the ADDs. There are a number of similarities between the PMC and PTM approaches. First, instead of specifying the initial probabilities as a tuple (½p00 p01 p10 p11 ), if PTMNAND is modiﬁed to encode them, the modiﬁed PTM becomes the transition probability matrix shown in Figure 10.10. Second, both the PMC and PTM approaches require a matrix of the order of O(2m+n) entries to evaluate a circuit with m inputs and n outputs. Therefore, the PMC and PTM methodologies use compact MTBDD and ADD (another name for MTBDDs [63, 64]) matrix representations, respectively. Third, even the usage of these compression techniques does not help these two reliability evaluation methodologies to scale for large circuits.

10.4.3. Probabilistic Gate Models (PGMs) The PGM-based methodology [32] entails the formulation of a PGM for each logic gate type. For instance, the PGM for the NAND gate in Figure 10.9 with a failure probability of e is pðoutÞ ¼ ½1 pðA0ÞpðB0Þ pðA0ÞpðB0Þ

1e ; e

ð10:2Þ

where p(A0) and p(B0) are the probabilities of inputs A0 and B0 being stimulated. Hence, p(out) is the probability of the faulty NAND output being logic high. This formulation can be applied iteratively to compute circuit reliability. This shows that the PGM approach requires computation of the output distribution, given the input probability distributions and logic function (truth table) performed by the gate. The DTMC model of a gate in the PMC methodology can be interpreted as a representation of the input probability distribution and the logic function; hence,

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the PMC and PGM approaches are similar. At the core, these methodologies construct probabilistic models that can be derived from one another; assume that if each gate fails independently, the scalability problem affects them equally.

10.4.4. Markov Random Fields (MRFs) Reference [65] proposed a probabilistic approach based on Markov Random Fields (MRFs) for analyzing nanocircuits. An MRF is deﬁned as a ﬁnite set of random variables, L ¼ fl1 ; l2 ; . . . . . . ; lk g. Each variable li has a neighborhood Ni which has variables from {Lli}. The probability distribution of a given variable depends only on a typically small neighborhood of other variables that is called a clique. As per the Hammersley–Clifford theorem [66], P 1 1 KT c2C Uc ðlÞ : ð10:3Þ Pðli jfL li gÞ ¼ e Z The conditional probability in Equation 10.3 is the Gibbs distribution. Z is the normalizing constant and for a given node i, C is the set of cliques. Uc is the clique energy function [65] and depends only on the neighborhood of the node whose energy state probability is being calculated. The idea of this model of computation is to use such a Gibbs distributionbased technique to characterize the logic functionality of each gate and maximize probability of being in valid energy conﬁgurations at the gate outputs. The logic functionality of each gate is represented by a logic compatibility function which is similar to a truth table. But instead of only considering the valid logic combinations, i.e., for given logic values at the inputs, the corresponding logic value at the gate output is correct; the logic compatibility function considers the invalid logic logic operation scenarios as well (output value is invalid for a given logic combination at the inputs). Such a function is used to represent the logic or clique energy for each Boolean function, and hence formulate energy-based transformation for the Boolean function. Due to such a formulation of the logic compatibility function, this computational scheme implicitly considers structural defects during the circuit formulation and eliminates the need for defect mapping followed by defect avoidance. The reliability of Boolean networks can be evaluated by representing circuits as MRFbased formulations of logic gates, applying Belief Propagation to the output energy distributions of each logic gate, and computing the probabilities of the signals at the prime outputs. These output distributions are evaluated for speciﬁc probability distributions at the primary inputs and signal noise at the interconnects. Note that this model of computation encodes signals over a continuous energy distribution, unlike conventional computational models where signals are bimodal (logic low or high). Let us take a speciﬁc NAND gate example to walk through the methodology in [65]. For a two-input NAND gate, there are three nodes in the assumed MRF: the inputs x0 and x1, and the output x2. Figure 10.12 shows x0 and its

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x1

Neighborhood of x0

x0

x2 2nd

order clique

Figure 10.12. NAND gate depicted as an MRF.

neighborhood, since the energy state of this node depends on its neighboring nodes. The edges in Figure 10.12 depict the conditional probabilities with respect to the other input x1 and the output x2 (nodes in the same clique). The operation of the gate is designated by the logic compatibility function j (x0,x1,x2) shown as a truth table in Table 10.2. j ¼ 1 when (x2 ¼ ðx0 ^ x1 Þ0 (valid logic operations). Such a function takes all valid and invalid logic functionality scenarios into account so as to represent a Gibb’s energy-based transformation of the NAND logic. Entropy has been deﬁned in many different yet equivalent ways. In this discussion, we deﬁne entropy as a measure of the disorder of a system. It is considered to have high values when the system under consideration is very disordered. The concept of entropy originated from classical thermodynamics, but has found widespread application in dynamical systems theory, communication theory, information theory, etc. Considerable work has been done on statistical thermodynamics [67], which be