Contemporary Computing: Third International Conference, IC3 2010 Noida, India, August 9-11, 2010 Proceedings, Part II (Communications in Computer and Information Science 95)

Communications in Computer and Information Science 95 Sanjay Ranka Arunava Banerjee Kanad Kishore Biswas Sumeet Dua ...

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Communications in Computer and Information Science

95

Sanjay Ranka Arunava Banerjee Kanad Kishore Biswas Sumeet Dua Prabhat Mishra Rajat Moona Sheung-Hung Poon Cho-Li Wang (Eds.)

Contemporary Computing Third International Conference, IC3 2010 Noida, India, August 9-11, 2010 Proceedings, Part II

13

Volume Editors Sanjay Ranka University of Florida, Gainesville, FL, USA E-mail: [email protected] Arunava Banerjee University of Florida, Gainesville, FL, USA E-mail: [email protected] Kanad Kishore Biswas Indian Institute of Technology, New Delhi, India E-mail: [email protected] Sumeet Dua Louisiana Tech University, Ruston, LA, USA E-mail: [email protected] Prabhat Mishra University of Florida, Gainesville, FL, USA E-mail: [email protected] Rajat Moona Indian Institute of Technology, Kanpur, India E-mail: [email protected] Sheung-Hung Poon National Tsing Hua University, Hsin-Chu, Taiwan, R.O.C. E-mail: [email protected] Cho-Li Wang The University of Hong Kong, China E-mail: [email protected]

Library of Congress Control Number: 2010931449 CR Subject Classification (1998): I.4, I.2, I.5, H.4, C.2, F.1 ISSN ISBN-10 ISBN-13

1865-0929 3-642-14824-7 Springer Berlin Heidelberg New York 978-3-642-14824-8 Springer Berlin Heidelberg New York

This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting, reproduction on microfilms or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer. Violations are liable to prosecution under the German Copyright Law. springer.com © Springer-Verlag Berlin Heidelberg 2010 Printed in Germany Typesetting: Camera-ready by author, data conversion by Scientific Publishing Services, Chennai, India Printed on acid-free paper 06/3180 543210

Preface

Welcome to the proceedings of the Third International Conference on Contemporary Computing, which was held in Noida (outskirts of New Delhi), India. Computing is an exciting and evolving area. This conference, which was jointly organized by the Jaypee Institute of Information Technology, Noida, India and the University of Florida, Gainesville, USA, focused on topics that are of contemporary interest to computer and computational scientists and engineers. The conference had an exciting technical program of 79 papers submitted by researchers and practitioners from academia, industry, and government to advance the algorithmic, systems, applications, and educational aspects of contemporary computing. These papers were selected from 350 submissions (with an overall acceptance rate of around 23%). The technical program was put together by a distinguished international Program Committee consisting of more than 150 members. The Program Committee was led by the following Track Chairs: Arunava Banerjee, Kanad Kishore Biswas, Summet Dua, Prabhat Mishra, Rajat Moona, Sheung-Hung Poon, and Cho-Li Wang. I would like to thank the Program Committee and the Track Chairs for their tremendous effort. I would like to thank the General Chairs, Prof. Sartaj Sahni and Prof. Sanjay Goel, for giving me the opportunity to lead the technical program.

Sanjay Ranka

Organization

Chief Patron Shri Jaiprakash Gaur

Patron Shri Manoj Gaur

Advisory Committee S.K. Khanna M.N. Farruqui Y. Medury J.P. Gupta T.R. Kakkar S.L. Maskara

Jaypee Institute of Information Technology, India Jaypee Institute of Information Technology, India Jaypee Institute of Information Technology, India Jaypee Institute of Information Technology, India Jaypee Institute of Information Technology, India Jaypee Institute of Information Technology, India

General Co-chairs Sartaj Sahni Sanjay Goel

University of Florida, USA Jaypee Institute of Information Technology, India

Program Chair Sanjay Ranka

University of Florida, USA

Track Co-chairs Algorithms Arunava Banerjee Sheung-Hung POON

University of Florida, Gainesville, USA National Tsing Hua University, Taiwan ROC

Applications Sumeet Dua K.K. Biswas

Louisiana Tech, USA IIT Delhi, India

VIII

Organization

Systems Prabhat Mishra Rajat Moona Cho-Li Wang

University of Florida, USA Indian Institute of Technology, Kanpur, India University of Hong Kong, Hong Kong

Technical Program Committee Aaron Striegel Alan Chiu Amitabha Bagchi Ananth Kalyanaraman Anil Tiwari Animesh Pathak Anirban Mondal Ankush Mittal Annamalai Annamalai Ansuman Banerjee Antoine Vigneron Arijit Ghosh Ashish Sureka Ashok Srinivasan Bertil Schmidt Bharat Madan Che-Rung Lee Chien-Liang Chen Chin-Laung Lei Chris Gentle Christian Duncan Christie Fuller Chuan Wu Chun-Cheng Lin Chung-Shou Liao Connor Johnson Costas Bekas D. J. Guan Devesh Kumar Bhatnagar Bhatnagar Dhiren Patel Eun-Sung Jung Francisco Massetto G. S. Lehal Gaurav Gupta George Varsamopoulos

University of Notre Dame, Indiana, USA Louisiana Tech University, USA Indian Institute of Technology, Delhi, India Washington State University, USA The LNM IIT, Rajasthan, India INRIA, Rocquencourt, Paris, France IIIT Delhi, India IIT Roorkee, India Prairie View A&M University,Texas, USA National University of Singapore, Singapore INRA, France CDNetworks, USA IIIT Delhi, India Florida State University, USA Nanyang Technological University, Singapore Applied Research Laboratory - Penn State University, USA National Tsing Hua University, Taiwan Aletheia University, Taiwan National Taiwan University, Taipei, Taiwan Avaya Australia, Australia Louisiana Tech University, USA Louisiana Tech University, USA The University of Hong Kong, Hong Kong Taipei Municipal University of Education, Taipei, Taiwan National Tsing Hua University, Taiwan Louisiana Tech University, USA IBM Zurich Research Laboratory, USA National Sun Yat-Sen University, Taiwan Landis&Gyr, Noida, India National Institute of Technology, Surat, India University of Florida, USA University of São Paulo, Brazil Punjabi University, Patiala, India IIIT Delhi, India School of Computing and Informatics, Bloomington, USA

Organization

Ghassan Alkadi Goutam Sanyal Hans-Christoph Wirth Harpreet Singh Heon-mo Koo Herman Haverkort Hilary Thompson Howie Huang Hsin-Hao Lai Hung-Chang Hsiao Hung-Min Sun Ian Rogers Iris Reinbacher Ishfaq Ahmad Ivona Brandic Jan-Jan Wu Jaya Deva Jean Gourd Jemal Abawajy Jiannong Cao Jinyuan Jia Jun Luo Ka-Lok Man Kamal Bharadwaj Kanav Kahol Kiran Rami Kuan-Ching Li Kuan-Chou Lai Leonard Brown Lihua Xu Li-Wei Ko Maarten Löffler Magdalini Eirinaki Mahesh Mamidipaka Mainak Chaudhuri Manas Somaiya Manoj Gaur Mayank Vatsa Michael Dessauer Mingsong Chen Mohammad Abdullah Al Faruque

IX

Southeastern Louisiana University, USA National Institute of Technology, Durgapur, India University of Würzburg, Germany Louisiana Tech University, USA Intel, Santa Clara, USA Eindhoven University of Technology, The Netherlands LSU Health Science Center, USA George Washington University, USA National Kaohsiung Normal University, Taiwan National Cheng Kung University, Taiwan National Tsing Hua University, Taiwan Azul Systems, USA Pohang University of Science and Technology, Korea University of Texas, Arlington, USA Vienna University of Technology, Austria Academia Sinica, Taiwan IIT Delhi, India Louisiana Tech University, USA Deakin University, Australia Hong Kong Polytechnic University, Hong Kong Tongji University, China Shenzhen Institutes of Advanced Technology, China Xi'an Jiaotong-Liverpool University, China Jawaharlal Nehru University, Delhi, India Arizona State University, USA Marvell Semiconductor, USA Providence University, Taiwan National Taichung University, Taiwan The University of Texas, USA Rochester Institute of Technology, USA National Chiao Tung University, Taiwan University of California, Irvine, USA San Jose State University, USA Intel, Austin, USA Indian Institute of Technology, Kanpur, India University of Florida, USA Malaviya National Institute of Technology, Jaipur, India IIIT Delhi, India Louisiana Tech University, USA University of Florida, USA University of Karlsruhe, Germany

X

Organization

Mohammad Ali Abam Mohammad Farshi Namrata Shekhar Naveen Kandiraju Naveen Kumar Ng Yin Kwee Nigel Gwee Nirmalya Bandyopadhyay P. Pandey Pabitra Mitra Paolo Bellavista Parbati Manna Patrick Mcdowell Per Kjeldaas Peter Rockett Philippe O.A. Navaux Piyush Kumar Ponnurangam Kumaraguru Prabhakar T.V. Prabir Kumar Biswas Pradeep Chowriappa Pramod Singh Prerna Sethi Prerna Sethi Prof. Merchant Prudence Wong Pushpendra Singh Rajeev Kumar Rajendra Acharya Richa Singh Robert Hsu Roberto Rojas-Cessa Rodrigo Mello Roop Jain Ruppa Thulasiram S. Hong Saeed Moghaddam Sandeep Gupta Sandip Aine Sanjay Chaudhary Saroj Kaushik S.C. Gupta Seetharama Satyanarayana-Jois

Dortmund University, Germany Yazd University, Iran Synopsys, California, USA Yahoo Inc., Sunnyvale, California Delhi University, India Nanyang Technological University, Singapore Southern University, Los Angeles, USA UFL IIT Bombay, India Indian Institute of Technology, Kharagpur, India University of Bologna, Italy University of Florida, USA South Eastern Louisiana University, USA Louisiana Tech University, USA University of Sheffield, UK Universidade Federal do Rio Grande do Sul, Brazil Florida State University, USA Indian Institute of Information Technology, Delhi, India IIT Kanpur, India Indian Institute of Technology Kharagpur Louisiana Tech University, USA ABV-IIITM, Gwalior, India Louisiana Tech University, USA Louisiana Tech University, USA IIT Bombay, India University of Liverpool, U.K. IIIT Delhi, India Indian Institute of Technology Kharagpur, India Ngee Ann Polytechnic, Singapore IIIT Delhi, India Chung Hua University, Taiwan New Jersey Institute of Technology, USA Universidade de Sao Paulo, Brazil JIIT, Noida, India University of Manitoba, Canada University of Sydney, Australia University of Florida, USA Arizona State University, USA Mentor Graphics, India Dhirubhai Ambani Institute of Information and Communication Technology, India IIT Delhi, India National Informatics Centre, India College of Pharmacy, Los Angeles, USA

Organization

Shankar Lall Maskara Sheetal Saini Shih Yu Chang Shireesh Verma Shripad Thite Shyam Gupta Siu Ming Yiu Siu-Wing Cheng Somitra Sandhya Somnath Sengupta Sonajharia Minz Song Fu Sridhar Hariharaputran Stanley P.Y. Fung Sudip Seal Sumantra Dutta Roy Suresh Chandra Teng Moh Tianzhou Chen Tien-Ching Lin Ton Kloks Travis Atkison Tridib Mukherjee Tyng-Yeu Liang Tzung-Shi Chen Vikram Goyal Vinayak Naik Vir Phoha Wang Yinfeng Wen-Chieh Lin Xian Du Xiaofeng Song Xiaoyu Yang Xuerong Yong Yajun Wang Yeh-Ching Chung Yenumula Reddy Yong-Kee Jun Yo-Sub Han Young Choon Lee Yu-Chee Tseng Yuting Zhao

XI

JIIT, Noida, India Louisiana Tech University, USA National Tsing Hua University of Taiwan Conexant, California, USA Google Inc., USA IIT Delhi The University of Hong Kong Hong Kong University of Science and Technology, Hong Kong IIIT Delhi, India Indian Institute of Technology, Kharagpur, India Jawaharlal Nehru University, India New Mexico Institute of Mining and Technology, USA Bielefeld University, Germany University of Leicester, UK Oak Ridge National Laboratory, USA Indian Institute of Technology, Delhi, India IIT Delhi, India San Jose State University, Canada Zhejiang University, P. R. China Academia Sinica, Taiwan National Chung Cheng University, Taiwan Lousiana Tech University, USA Arizona State University, USA National Kaohsiung University of Applied Science, Taiwan National University of Tainan, Taiwan IIIT Delhi, India IIIT Delhi, India Louisiana Tech University, USA School of Electronics and Information Engineering, Xi'an Jiaotong University, P.R. China National Chiao Tung University, Taiwan Louisiana Tech University, USA Nanjing University of Aeronautics and Astronautics, P.R. China University of Southampton, UK University of Puerto Rico at Mayaguez, USA Microsoft Research Asia, P.R. China National Tsing Hua University, Taiwan Grambling State University, Los Angeles, USA Gyeongsang National University, South Korea Yonsei University, Korea University of Sydney, Australia National Chiao-Tung University, Taiwan University of Aberdeen, UK

XII

Organization

Zhe Wang Zhihui Du Zili Shao

University of Florida, USA Tsinghua University, P.R. China Polytechnic University, Hong Kong

Publicity Co-chairs Bhardwaj Veeravalli Divakar Yadav Koji Nakano Masoud Sadjadi Paolo Bellavista Rajkumar Buyya

University of Singapore, Singapore JIIT Noida, India Hiroshima University, Japan Florida International University, USA University of Bologna, Italy University of Melbourne, Australia

Publications Committee Vikas Saxena Abhishek Swaroo Alok Aggarwal Mukta Goel Pawan Kumar Upadhyay Rakhi Hemani

JIIT Noida, India (Publication Chair) JIIT, India JIIT, India JIIT Noida, India JIIT Noida, India JIIT Noida, India

Web Administration Sandeep K. Singh Shikha Mehta

JIIT Noida, India JIIT, Noida, India

Graphic Design Sangeeta Malik

JIIT Noida, India

Registration Committee Krishna Asawa Anshul Gakhar Archana Purwar Indu Chawla Manisha Rathi Purtee Kohli

JIIT Noida, India (Chair ) JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India

Finance Chair Bharat Gupta

JIIT, Noida, India

Organization

XIII

Poster Session Committee Hima Bindu Antariksh De Jolly Shah Kumar Lomash Nikhil Wason Priyank Singh Rakhi Himani Sangeeta Mittal Siddarth Batra

JIIT, Noida, India (Chair ) Xerox, USA JIIT, Noida, India Adobe Systems, India Orangut (Co-Chair) Firmware Developer at Marvell Semiconductor, India JIIT, Noida, India JIIT, Noida, India Co-Founder & CEO at Zunavision, USA

Student Project Exhibition Chair Alok Aggarwal

JIIT, India

Student Volunteers Coordinator Manish Thakur

JIIT, Noida, India

Local Arrangements Committee Prakash Kumar Adarsh Kumar Akhilesh Sachan Anuja Arora Arti Gupta Bharat Gupta Gagandeep Kaur Hema N. Indu Chawla K. Raj Lakshmi Kavita Pandey Manoj Bharadwaj Meenakshi Gujral Mukta Goel O. N. Singh Parmeet Kaur Pawan Kumar Upadhyay Prakash Kumar Prashant Kaushik S. Bhaseen S.J.S. Soni

JIIT, Noida, India (Chair ) JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT, Noida, India JIIT Noida, India JIIT Noida, India JIIT, Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT, Noida, India

XIV

Organization

Sangeeta Mittal Sanjay Kataria Shikha Jain Suma Dawn Tribhuvan K Tiwari Vimal Kumar Vivek Mishra

JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India JIIT Noida, India

Table of Contents – Part II

Technical Session-12: System-1 (S-1) Automatic Test Data Generation for Data Flow Testing Using Particle Swarm Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Narmada Nayak and Durga Prasad Mohapatra Eﬃcient Storage of Massive Biological Sequences in Compact Form . . . . . Ashutosh Gupta, Vinay Rishiwal, and Suneeta Agarwal

1 13

Maximum Utility Meta-Scheduling Algorithm for Economy Based Scheduling under Grid Computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hemant Kumar Mehta, Priyesh Kanungo, and Manohar Chandwani

23

An Accelerated MJPEG 2000 Encoder Using Compute Uniﬁed Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Datla Sanketh and Rajdeep Niyogi

34

Event-Based Metric for Computing System Complexity . . . . . . . . . . . . . . . Sandeep Kumar Singh, Sangeeta Sabharwal, and J.P. Gupta

46

Technical Session-13: System-2 (S-2) Load Balancing in Xen Virtual Machine Monitor . . . . . . . . . . . . . . . . . . . . . Gaurav Somani and Sanjay Chaudhary Aerial Vehicle Based Sensing Framework for Structural Health Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ashish Tanwer, Muzahid Hussain, and Parminder Singh Reel A Cross Layer Seamless Handover Scheme in IEEE 802.11p Based Vehicular Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arun Prakash, Sarsij Tripathi, Rajesh Verma, Neeraj Tyagi, Rajeev Tripathi, and Kshirasagar Naik

62

71

84

Modeling and Simulation of Eﬃcient March Algorithm for Memory Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Balwinder Singh, Sukhleen Bindra Narang, and Arun Khosla

96

A New Approach for Detecting Design Patterns by Graph Decomposition and Graph Isomorphism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Akshara Pande, Manjari Gupta, and A.K. Tripathi

108

XVI

Table of Contents – Part II

Technical Session-14: System-3 (S-3) Detection of Polymorphic Viruses in Windows Executables . . . . . . . . . . . . Abhiram Kasina, Amit Suthar, and Rajeev Kumar Sensitivity Measurement of Neural Hardware: A Simulation Based Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amit Prakash Singh, Pravin Chandra, and Chandra Shekhar Rai An Approach to Identify and Manage Interoperability of Class Diagrams in Visual Paradigm and MagicDraw Tools . . . . . . . . . . . . . . . . . . Gaurav Bansal, Deepak Vijayvargiya, Siddhant Garg, and Sandeep Kumar Singh A Novel Approach to Generate Test Cases Using Class and Sequence Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shireesh Asthana, Saurabh Tripathi, and Sandeep Kumar Singh

120

131

142

155

Technical Session-15: System-4 (S-4) Arrogyam: Arrhythmia Detection for Ambulatory Patient Monitoring . . . Dheerendra Singh Gangwar and Davinder Singh Saini

168

Test Process Model with Enhanced Approach of State Variable . . . . . . . . Praveen Ranjan Srivastava

181

Re-engineering Machine Translation Systems through Symbiotic Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pawan Kumar, Rashid Ahmad, A.K. Rathaur, Mukul K. Sinha, and R. Sangal

193

Analysis for Power Control and Security Architecture for Wireless Ad-Hoc Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bharat Singh, Akash Bansal, Sunil Kumar, and Anshu Garg

205

Extension of Superblock Technique to Hyperblock Using Predicate Hierarchy Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sweta Verma, Ranjit Biswas, and J.B. Singh

217

Technical Session-16: System-6 (S-6) Vehicular Ad Hoc Network Mobility Models Applied for Reinforcement Learning Routing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shrirang Ambaji Kulkarni and G. Raghavendra Rao Hardware and Software Co-Design for Robot Arm . . . . . . . . . . . . . . . . . . . . Urmila Meshram, R.R. Harkare, and Devendra Meshram

230 241

Table of Contents – Part II

XVII

Security Vulnerabilities of a Novel Remote User Authentication Scheme Using Smart Card based on ECDLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manoj Kumar and Aayushi Balyan

252

Multiple Polymorphic Arguments in Single Dispatch Object Oriented Languages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sanchit Bansal

260

Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

273

Table of Contents – Part I

Technical Session-1: Algorithm-1 (A-1) A PDE-Based Nonlinear Filter Adapted to Rayleigh’s Speckle Noise for De-Speckling 2D Ultrasound Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rajeev Srivastava and J.R.P. Gupta

1

Face Recognition Using Kernel Fisher Linear Discriminant Analysis and RBF Neural Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Thakur, J.K. Sing, D.K. Basu, and M. Nasipuri

13

Parallel Enumeration Sort on OTIS-Hypercube . . . . . . . . . . . . . . . . . . . . . . Keny T. Lucas

21

A Robust Trust Mechanism Algorithm for Secure Power Aware AODV Routing in Mobile Ad Hoc Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Naga Sathish Gidijala, Sanketh Datla, and Ramesh C. Joshi

32

A Heuristic Algorithm for Constrained Redundancy Optimization in Complex Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sudhanshu Aggarwal

42

Technical Session-2: Algorithm-2 (A-2) A Hybrid Genetic Algorithm Based Test Case Generation Using Sequence Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mahesh Shirole and Rajeev Kumar

53

LACAIS: Learning Automata Based Cooperative Artiﬁcial Immune System for Function Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alireza Rezvanian and Mohammad Reza Meybodi

64

Image Reconstruction from Projection under Periodicity Constraints Using Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Narender Kumar and Tanuja Srivastava

76

A Robust Watermarking Algorithm for Audio Signals Using SVD . . . . . . Malay Kishore Dutta, Vinay K. Pathak, and Phalguni Gupta

84

Diﬀerential Evolution Using Interpolated Local Search . . . . . . . . . . . . . . . . Musrrat Ali, Millie Pant, and V.P. Singh

94

XX

Table of Contents – Part I

Technical Session-3: Algorithm-3 (A-3) A New SVD Based Watermarking Framework in Fractional Fourier Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gaurav Bhatnagar and Balasubramanian Raman

107

Mining Frequent and Associated Gene Expression Patterns from Spatial Gene Expression Data: A Proposed Approach . . . . . . . . . . . . . . . . . M. Anandhavalli, M.K. Ghose, and K. Gauthaman

119

Minimization of Lennard-Jones Potential Using Parallel Particle Swarm Optimization Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Kusum Deep and Madhuri Arya

131

An Artiﬁcial Bee Colony Algorithm for the 0–1 Multidimensional Knapsack Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shyam Sundar, Alok Singh, and Andr´e Rossi

141

Automatic Summary Generation from Single Document Using Information Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chandra Prakash and Anupam Shukla

152

Technical Session-4: Algorithm-4 (A-4) An Alternate Approach to Compute the Reliability of a Computer Communication Network Using Binary Decision Diagrams . . . . . . . . . . . . Manoj Singhal, R.K. Chauhan, and Girish Sharma A Multi-Level Blocks Scrambling Based Chaotic Image Cipher . . . . . . . . . Musheer Ahmad and Omar Farooq Maxillofacial Surgery Using X-Ray Based Face Recognition by Elastic Bunch Graph Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manish Madhav Tripathi, Mohd Haroon, Minsa Jafar, and Mansi Jain

160 171

183

A Phenomic Approach to Genetic Algorithms for Reconstruction of Gene Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rio G.L. D’Souza, K. Chandra Sekaran, and A. Kandasamy

194

An Algorithm to Determine Minimum Velocity-Based Stable Connected Dominating Sets for Ad Hoc Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Natarajan Meghanathan

206

Technical Session-5: Algorithm-5 (A-5) An Eﬃcient Intrusion Detection System Using Clustering Combined with Fuzzy Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ajanta Konar and R.C. Joshi

218

Table of Contents – Part I

Assessing the Performance of Bi-objective MST for Euclidean and Non- Euclidean Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soma Saha, Mohammad Aslam, and Rajeev Kumar

XXI

229

PSO - SVM Based Classiﬁers: A Comparative Approach . . . . . . . . . . . . . . Yamuna Prasad and K.K. Biswas

241

Eﬃcient Job Division for Grids Running SIMD Algorithms . . . . . . . . . . . . Ashish Kurmi and Srinivasan Iyer

253

A Novel Algorithm for Achieving a Light-Weight Tracking System . . . . . Sanketh Datla, Abhinav Agarwal, and Rajdeep Niyogi

265

Technical Session-6: Application-1 (P-1) Computer Simulation Studies of Drug-DNA Interactions: Neothramycin B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rajeshwer Shukla and Sugriva Nath Tiwari

277

Eﬀect of Speech Coding on Recognition of Consonant-Vowel (CV) Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anil Kumar Vuppala, Saswat Chakrabarti, and K. Sreenivasa Rao

284

Cloudbank: A Secure Anonymous Banking Cloud . . . . . . . . . . . . . . . . . . . . Ridhi Sood and Meenakshi Kalia Alignment Model and Training Technique in SMT from English to Malayalam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sebastian Mary Priya, K. Sheena Kurian, and G. Santhosh Kumar Emotion Classiﬁcation Based on Speaking Rate . . . . . . . . . . . . . . . . . . . . . . Shashidhar G. Koolagudi, Sudhin Ray, and K. Sreenivasa Rao

295

305 316

Technical Session-7: Application-2 (P-2) A Vulnerability Metric for the Design Phase of Object Oriented Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Agrawal and R.A. Khan A Framework for Synthesis of Human Gait Oscillation Using Intelligent Gait Oscillation Detector (IGOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soumik Mondal, Anup Nandy, Anirban Chakrabarti, Pavan Chakraborty, and G.C. Nandi Detection of Signiﬁcant Opinionated Sentence for Mining Web Users’ Opinion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . K.M. Anil Kumar and Suresha

328

340

350

XXII

Table of Contents – Part I

Hyperspectral Data Compression Model Using SPCA (Segmented Principal Component Analysis) and Classiﬁcation of Rice Crop Varieties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shwetank, Kamal Jain, and Karamjit Bhatia Impulse Noise Removal from Color Images Using Adaptive Neuro–fuzzy Impulse Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Umesh Ghanekar, Awadhesh Kumar Singh, and Rajoo Pandey

360

373

Technical Session-8: Application-3 (P-3) Measuring of Time-Frequency Representation(TFR) Content - Using the Kapurs Entropies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Priti Gupta and Vijay Kumar

381

An Ontology Based Framework for Domain Analysis of Interactive System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shrutilipi Bhattacharjee, Imon Banerjee, and Animesh Datta

391

Entropy Based Clustering to Determine Discriminatory Genes for Microarray Dataset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rajni Bala and R.K. Agrawal

403

A Framework for Incremental Domain-Speciﬁc Hidden Web Crawler . . . . Rosy Madaan, Ashutosh Dixit, A.K. Sharma, and Komal Kumar Bhatia Impact of K-Means on the Performance of Classiﬁers for Labeled Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.M. Patil, R.C. Joshi, and Durga Toshniwal

412

423

Technical Session-9: Application-4 (P-4) Digital Watermarking Based Stereo Image Coding . . . . . . . . . . . . . . . . . . . Sanjay Rawat, Gaurav Gupta, R. Balasubramanian, and M.S. Rawat Content Based Multimodal Retrieval for Databases of Indian Monuments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aman Agarwal and Vikas Saxena Evolutionary Based Automated Coverage Analysis for GUI Testing . . . . . Abdul Rauf, Sajid Anwar, Naveed Kazim, and Arshad Ali Shahid

435

446 456

Online Signature Classiﬁcation Using Modiﬁed Fuzzy Min-Max Neural Network with Compensatory Neuron Topology . . . . . . . . . . . . . . . . . . . . . . B.M. Chaudhari, Rupal S. Patil, K.P. Rane, and Ulhas B. Shinde

467

Multifaceted Classiﬁcation of Websites for Goal Oriented Requirement Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sangeeta Srivastava and Shailey Chawla

479

Table of Contents – Part I

XXIII

Technical Session-10: Application-5 (P-5) A Simpliﬁed and Corroborative Approach towards Formalization of Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ram Chatterjee and Kalpana Johari Robust Multiple Watermarking Using Entropy Based Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sushila Kamble, Vikas Maheshkar, Suneeta Agarwal, and Vinay Shrivastava Application of Adaptive Learning in Generalized Neuron Model for Short Term Load Forecasting under Error Gradient Functions . . . . . . . . . Chandragiri Radha Charan and Manmohan Intelligent Schemes for Indexing Digital Movies . . . . . . . . . . . . . . . . . . . . . . R.S. Jadon and Sanjay Jain Fuzzy Reasoning Boolean Petri Nets Based Method for Modeling and Analysing Genetic Regulatory Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raed I. Hamed, S.I. Ahson, and R. Parveen

486

497

508 518

530

Technical Session-11: Application-6 (P-6) Mining the Blogosphere for Sociological Inferences . . . . . . . . . . . . . . . . . . . Vivek Kumar Singh

547

Modeling for Evaluation of Signiﬁcant Features in siRNA Design . . . . . . . Chakresh Kumar Jain and Yamuna Prasad

559

A Fast Progressive Image Transmission Algorithm Using Linear Bivariate Splines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rohit Verma, Ravikant Verma, P. Syamala Jaya Sree, Pradeep Kumar, Rajesh Siddavatam, and S.P. Ghrera Building Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rekha Bhowmik and Pradeep Sharma

568

579

Adaptive Bacterial Foraging Optimization Based Tuning of Optimal PI Speed Controller for PMSM Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ravi Kumar Jatoth and A. Rajasekhar

588

Missing Value Imputation Based on K-mean Clustering with Weighted Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bankat M. Patil, Ramesh C. Joshi, and Durga Toshniwal

600

Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

611

Automatic Test Data Generation for Data Flow Testing Using Particle Swarm Optimization Narmada Nayak and Durga Prasad Mohapatra Department of Computer Science and Engineering National Institute of Technology Rourkela, Orissa-769008, India [email protected] http://www.nitrkl.ac.in

Abstract. Automatic test case generation is a major problem in software testing. Evolutionary structural testing is an approach to automatically generate test cases that uses a Genetic Algorithm (GA) which is guided by the data flow dependencies in the program to search for test data to cover the def-use association. The Particle Swarm Optimization (PSO) approach is a swarm intelligence technique which can be used to generate test data automatically. We have proposed an algorithm to generate test cases using PSO for data flow testing. We have simulated both the evolutionary and swarm intelligence techniques. From the experiments it has been observed that PSO outperforms GA in 100% def-use coverage percentage. Keywords: Software testing, Data flow testing, Genetic algorithm, Particle swarm optimization.

1

Introduction

Software testing has two main aspects: test data generation and application of a test data adequacy criterion. A test data generation technique is an algorithm that generates test cases. The test data adequacy criterion is a predicate that determines whether the testing process is ﬁnished. Several test data adequacy criteria have been proposed, such as control ﬂow-based and data ﬂow-based criteria. An automated test data generator is a tool that assists the tester in creating test data. Test data generators can be categorized into three classes: random test data generators, structural-oriented test data generators and data speciﬁcation generators. Random test data generators select random test data from the domain of input variables. Structural-oriented test data generators are based on path coverage, branch coverage, def-use coverage etc. Data speciﬁcation generators select test data from program speciﬁcation, in order to exercise features of the speciﬁcation.

Corresponding author.

S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 1–12, 2010. c Springer-Verlag Berlin Heidelberg 2010

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N. Nayak and D.P. Mohapatra

Evolutionary structural testing is a search based technique that uses GA [1] which is guided by the data ﬂow dependencies in the program, to search for test data to fulﬁll data ﬂow path selection criteria namely the all-uses criterion. However, GA [2,3,4,5,6,7] has started getting competition from other heuristic search techniques, such as the particle swarm optimization. Various works [8,9,10,11,12] show that particle swarm optimization is equally well suited or even better than genetic algorithms for solving a number of test problems. At the same time, a particle swarm algorithm is much simpler, easier to implement and has a fewer number of parameters that the user has to adjust than a genetic algorithm.

2

The Data Flow Analysis Technique

This section describes the all-uses criterion and the data ﬂow analysis technique used to implement it. Firstly, some deﬁnitions used in describing this technique are presented. The control ﬂow of a program can be represented by a directed graph with a set of nodes and a set of edges. Each node represents a group of consecutive statements, which together constitute a basic block. The edges of the graph are then possible transfers of control ﬂow between the nodes. A path is a ﬁnite sequence of nodes connected by edges. A complete path is a path whose ﬁrst node is the start node and whose last node is an exit node. A path is defclear with respect to a variable if it contains no new deﬁnition of that variable. Fig. 2 presents the ﬂow graph of the example program, shown in Fig. 1, which determines the middle value of three given integers A, B and C. Data ﬂow analysis [13] focuses on the interactions between variable deﬁnitions (defs) and references (uses) in a program. Variable uses can be split into ’c-uses’ and ’p-uses’ according to whether the variable use occurs in a computation or a predicate. Defs and c-uses are associated with nodes, but p-uses are associated with edges. The purpose of the data ﬂow analysis is to determine the defs of every variable in the program and the uses that might be aﬀected by these defs, i.e. the def-use associations. Such data ﬂow relationships can be represented by the following two sets: dcu(i), the set of all variable defs for which there are def-clear paths to their cuses at node i; and dpu(i,j), the set of all variable defs for which there are def-clear paths to their p-uses at edge (i,j). Using information concerning the location of variable defs and uses, together with the basic static reach algorithm [14] the sets dcu(i) and dpu(i, j) can be determined . The basic static reach algorithm is used to determine two sets called reach(i) and avail(i). The set reach (i) is the set of all variable defs that ”reach” node i. (A def of a variable x in node k is said to reach node i if there is a defclear path w.r.t. x from node k to node i). The set avail (i) is the set of all ”available” variable defs at node i. It is the union of the set of global defs at node i together with the set of all defs that reach this node and are preserved through it. (Clearly any def of a variable in node i will not preserve any other def of the same variable). Using these two sets, the sets dcu(i) and dpu(i,j) are constructed from the formulae:

Automatic Test Data Generation for Data Flow Testing Using PSO

3

Fig. 1. Example Program (The 1st column represents statement numbers, and the 2nd one represents block numbers)

dcu(i) := reach(i) ∩ c use(i), and dpu(i, j) := avail(i) ∩ p use(i, j) where c-use(i) is the set of variables for which node i contains a global c-use, and p-use(i,j) is the set of variables for which edge (i,j) contains a p-use. The all-uses criterion requires a def-clear path from each def of a variable to each use (c-use and p-use) of that variable to be traversed. It should be noted that, the all uses criterion includes all the members of the family of the data ﬂow criteria, except the all-du-paths criterion. In other words, any complete path satisfying the all-uses criterion also satisﬁes the others. In order to determine the set of paths that satisfy the all-uses criterion, it is necessary to determine the def-use associations of program variables. As described above, such data ﬂow relationships can be represented by the dcu and dpu sets. The def-clear paths required to fulﬁl the all-uses criterion are constructed from the dcu and dpu sets. These paths are divided into two groups: dcu-paths and dpu-paths. In the dcu-paths list, each dcu-path is represented by: a def-node

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N. Nayak and D.P. Mohapatra

Fig. 2. Flow Graph for the Example Program given in Fig. 1

(a node containing a def of a variable), a c-use-node (a node containing a c-use of that variable), and the set of nodes that must not be included in that path (nodes containing other defs of that variable). These nodes are called killing nodes. In the dpu-paths list, each dpu-path is represented by: a def-node (node containing a def of a variable), p-use-edge (an edge having a p-use of that variable), and the set of killing nodes. Henceforth, the term ’def-use paths’ will be used to mean the set of dcu-paths and dpu-paths together. Table 1 and 2 show the lists of the def-use paths of the example program.

Table 1. List of the DCU-paths of the Example Program given in Fig. 1 DCU Path No. Variable Def Node C use Node Killing Nodes 1 B 1 3 None 2 A 1 5 None 3 B 1 9 None 4 A 1 11 None 5 MID 1 14 3,5,9,11 6 MID 3 14 1,5,9,11 7 MID 5 14 1,3,9,11 8 MID 9 14 1,3,5,11 9 MID 11 14 1,3,5,9

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Table 2. List of the DPU-paths of the Example Program given in Fig. 1 DPU Path No. Variable Def Node P-Use Node Killing Nodes 1 B 1 1-2 None 2 C 1 1-2 None 3 B 1 1-8 None 4 C 1 1-8 None 5 A 1 2-3 None 6 B 1 2-3 None 7 A 1 2-4 None 8 B 1 2-4 None 9 A 1 4-5 None 10 C 1 4-5 None 11 A 1 4-6 None 12 C 1 4-6 None 13 A 1 8-9 None 14 B 1 8-9 None 15 A 1 8-10 None 16 B 1 8-10 None 17 A 1 10-11 None 18 C 1 10-11 None 19 A 1 10-12 None 20 C 1 10-12 None

3

Proposed Work

The Genetic algorithm has been a signiﬁcant milestone in automatic test data generation for dataﬂow testing, but the algorithm takes more generation to get the def-use coverage percentage. The Particle swarm optimization algorithm takes less generation to get the result. This paper thus presents a comparative study and intends to ﬁnd the eﬃcient algorithm for automatic test data generation by performing simulations. 3.1

The Principles of Genetic Algorithm(GA)

Genetic algorithm is a meta-heuristic optimization technique that mimics the principles of the Darwinian theory of biological evolution. Its adequacy for solving non-linear, multi-modal, and discontinuous optimization problems has drawn the attention of many researchers and practitioners during the last decades. GAs generates a sequence of populations by using a selection mechanism and use crossover and mutation as search mechanisms. The principle behind GAs is that they create and maintain a population of individuals represented by chromosomes (essentially a character string analogous to the chromosomes appearing in DNA). These chromosomes are typically encoded solutions to a problem. The chromosomes then undergo a process of evolution according to rules of selection, mutation and reproduction.

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N. Nayak and D.P. Mohapatra

The Genetic Algorithm to automatically generate test cases for the given program deﬁnes: Step 1: generation = 0. Step 2: Generate the initial population Pi of binary coded chromosomes Ci each representing a variables of the program. Step 3: while (coverage percent = 100 and N o of Generation ≤ M ax Gen) Step 4: Generate Accumulated Def-Use coverage for each Ci using the evaluation Eq. (1) Step 5: Get the mating pool ready by eliminating worst ﬁt individuals and duplicating high ﬁt individuals; using reproduction operator(cross over operator and mutation operator) reproduce oﬀspring from the parent chromosomes and the new population is formed which will be current population Pi . Step 6: generation = generation + 1. Step 7: Extract a set of def-use paths covered by each test case. Step 8: Calculate Accumulated Def-Use coverage for each Ci using the evaluation Eq. (1). Step 9: If condition is not satisﬁed then go to step 3. Evaluation Function The algorithm evaluates each test case by executing the program with it as input, and recording the def-use paths in the program that are covered by this test case. (A test case is said to cover a def-use path, if it causes the program to traverse a path that has a sub path, which starts at the def-node and ends at the c-use node/p-use edge of the def-use path and does not pass through its killing nodes.) The ﬁtness value evalCi for each chromosome Ci = (i = 1, · · · , pop size) is calculated as follows: N umber of Def U se paths covered by Ci (1) T otal number of Def U se paths The ﬁtness value is the only feedback from the problem for the GA. A test case which is represented by the chromosome Ci is considered eﬀective if its ﬁtness value eval (Ci ) > 0. eval(Ci ) =

Reproduction Operators Crossover: The main purpose of crossover is to exchange information between two parent chromosomes to produce oﬀspring for the next generation. Mutation: The main aim of mutation is to introduce genetic diversity into the population 3.2

Particle Swarm Optimization(PSO)

Particle Swarm Optimization is an algorithm developed by Kennedy and Eberhart [8] that simulates the social behaviors of bird ﬂocking or ﬁsh schooling and the methods by which they ﬁnd roosting places, foods sources or other suitable habitat.

Automatic Test Data Generation for Data Flow Testing Using PSO

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In the basic PSO technique, suppose that the search space is d-dimensional, 1. Each member is called particle, and each particle (i-th particle) is represented by d dimensional vector and described as Xi = [Xi1 , Xi2 ,...,Xid ]. 2. The set of n particle in the swarm are called population and described as pop=[X1 , X2 ,...,Xd ]. 3. The best previous position for each particle (the position giving the best ﬁtness value) is called particle best and described as P Bi = [P Bi1 , P Bi2 ,...,P Bid ]. 4. The best position among all of the particle best position achieved so far is called global best and described as GBi = [GBi1 , GBi2 ,...,GBid ]. 5. The rate of position change for each particle is called the particle velocity and described as Vi = [Vi1 , Vi2 ,...,Vid ]. At iteration k the velocity for d-dimension of i-particle is updated by: Vidk+1 = wVidk + c1 r1 (pbkid − xkid ) + c2 r2 (gbkid − xkid )

(2)

Where i= 1,2,..,n and n is the size of population, w is the inertia weight, c1 and c2 are the acceleration constants, and r1 and r2 are two random values in range [0,1]. 6. The i-particle position is updated by: xk+1 = xkid + Vidk+1 id

(3)

PSO Algorithm to automatically generate test cases for the given program defines: Step 1: (Initialization): Set the iteration number k=0. Generate randomly n particles, Xi , i = 1, 2,..., n, where Xi = [Xi1 , Xi2 ,...,Xid ]. and their initial velocities Vi = [Vi1 , Vi2 ,...,Vid ]. Evaluate the evaluation function for each particle eval (Xi ) using Eq. (1). If the constraints are satisﬁed, then set the particle best P Bi = Xi , and set the particle best which give the best objective function among all the particle bests to global best GB. Else, repeat the initialization. Step 2: Update iteration counter k=k+1. Step 3: Update velocity using Eq. (2). Step 4: Update position using Eq. (3). Step 5: Update particle best: If evali (Xik ) > evali (P Bik−1 ) then P Bik = Xik Else P Bik = P Bik−1 Step 6: Update global best: eval(GB k ) = max(evali (P Bik−1 )) If eval(GB k ) > eval(GB k−1 ) then GB k = GB k Else GB k = GB k−1

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Step 7: (Stopping criterion): If the number of iteration exceeds the maximum number iteration or accumulated coverage is 100% then stop, otherwise go to step 2.

4

Comparison between GA and PSO

The Genetic Algorithm (GA) is an evolutionary optimizer that takes a sample of possible solutions (individuals) and employs mutation, crossover, and selection as the primary operators for optimization. Most of evolutionary techniques have the following procedure: 1. 2. 3. 4.

Random generation of an initial population. Reckoning of a ﬁtness value for each subject. Reproduction of the population based on ﬁtness values. If requirements are met, then stop. Otherwise go back to 2.

From this procedure, we can learn that PSO shares many common points with GA. Both algorithms start with a group of randomly generated population and both algorithms have ﬁtness values to evaluate the population. Both algorithms update the population and search for the optimum with random techniques. Compared with genetic algorithms (GAs), PSO does not have genetic operators like crossover and mutation. Particles update themselves with the internal velocity. They also have memory, which is important to the algorithm. Also, the information sharing mechanism in PSO is signiﬁcantly diﬀerent: In GAs, chromosomes share information with each other. So the whole population moves like one group towards an optimal area even if this move is slow. In PSO, only GB gives out the information to others. It is one-way information sharing mechanism. The evolution only looks for the best solution. Compared with GA, all the particles tend to converge to the best solution quickly in most cases. When comparing the run-time complexity of the two algorithms, we should exclude the similar operations (initialization, ﬁtness evaluation, and termination) from our comparison because similar operations give same run time complexity. We exclude also the number of generations, as it depends on the problem complexity and termination criteria (experimentally, PSO has lower number of generations). Therefore, we will make our calculations for the main loop of the two algorithms. We consider the most time-consuming processes (recombination in GA as well as velocity and position update in PSO). For GA, if the new generation replaces the older one, the recombination complexity is O(q), where q is group size for tournament selection. In our case, q equals the Selection rate*n, where n is the size of population. But if the replacement strategy depends on to the ﬁtness of the individual, a sorting process is needed to determine which individuals to be replaced by which new individuals. This sorting is important to guarantee the solution quality. Another sorting process is needed any way to update the rank of the individual at the end of each generation. Therefore, as the quick sort complexity ranges from O(n2 ) to O(n log2 n) the recombination complexity is O(n2 ) to O(n log2 n).

Automatic Test Data Generation for Data Flow Testing Using PSO

9

For PSO, the velocity and position update processes complexity is O (n) as there is no need for sorting. The algorithm operates according to equations (2) and (3) on each individual (particle). From the above discussion, GA’s complexity is larger than that of PSO. Therefore, PSO is simpler and faster than GA.

5

Simulation Results

MATLAB is used as simulation tool.Input to the PSO algorithm is instrumented version of the program, list of def-use path to be covered, number of program input variables, population size, and maximum number of iteration.Output is the set of test cases for program and the set of def-use path covered by each test case. The eﬀectiveness of the proposed PSO is compared with GA. A set of 14 small FORTRAN programs is used in the experiments. Table 3. Comparison between GA technique and PSO Technique

Program No. No.of 1 2 3 4 5 6 7 8 9 10 11 12 13 14

No.of Generation DEf-Use Coverage % Variable Population size GA PSO GA PSO 3 6 17 2 100 100 3 8 10 3 100 100 4 8 19 6 100 100 3 6 21 17 100 100 5 10 9 3 100 100 4 6 17 9 100 100 4 8 13 7 100 100 3 8 12 5 85 90 4 8 14 10 90 96 4 6 19 12 100 100 3 8 21 15 82 95 4 6 18 10 100 100 3 8 24 18 81 92 3 6 19 10 100 100

Table 3 shows the result of applying the GA technique and PSO technique to 10 programs. As can be seen PSO technique outperformed the GA technique in all programs. In these programs, the PSO technique required less number of generations than GA technique to achieve same def-use coverage percentage. In each iteration of PSO, we ﬁnd the GB (gbest), which gives the single optimal solution. The PSO moves towards the near global optimal solution in each iteration. Thereby, PSO takes less iterations whereas in GA, in each generation the three basic opertions namely selection, crossover and mutation are performed. So GA takes more generations to reach towards the solution in comparison to PSO.

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N. Nayak and D.P. Mohapatra

Fig. 3. (a)The graphs showing plot between Def-Use Coverage Percentage vs. No. of Generations of GA technique of 1st Program (b) The graphs showing plot between Def-Use Coverage Percentage vs. No. of Generations of PSO technique of 1st Program

It should be noted that, in the cases where less than 100% coverage is achieved, the program included some def-use paths that cannot be covered by any test case due to the existence of infeasible paths. In Fig. 3(a) shows the graph between the Def-Use Coverage percentage vs. No.of Generations of GA technique of 1st program. Fig. 3(b) shows the graph between the Def-Use Coverage percentage vs. No.of Generations of PSO technique of 1st program. In the graph it is viewed that GA technique has taken 17 generations to get 100% def-use coverage but PSO technique has taken 2 iterations to get the same result. This improvement in PSO occurs due to the reasons mentioned above.

6

Comparison with Related Work

Li et al. [11] applied particle swarm optimization to all path test data generation. They constructed a new ﬁtness function for all path test data generation. In the process of all path test data generation, the execution frequencies of all paths are registered to apply to further tests. If the frequency is equal to zero, this indicates that the path is not traveled in this generation. In this situation they used the single path test data automatic generation to generate test data for the path. If it is not found then the path is probably unreachable. If frequency data is relatively small, the situation shows that this path is infrequent one. If the frequency data is relatively big, then the situation is considered as normal. Khushboo et al. [10] described the application of the discrete quantum particle swarm optimization (QPSO) to the problem of automated test data generation. A discrete quantum particle swarm optimization algorithm based on the concept of quantum computing. They had studied the role of the critical QPSO

Automatic Test Data Generation for Data Flow Testing Using PSO

11

parameters on test data generation performance and based on the observation an adaptive version (AQPSO) had been designed. Its performance compared with QPSO. They used the branch coverage as their test adequacy criteria. Andreas et al. [9] described the application of Comprehensive Learning Particle Swarm Optimizer (CL-PSO). They applied a new learning strategy, where each particle learns from diﬀerent neighbors for each dimension separately which dependent on its assigned learning rate. This happenes until the particle does not achieve any further improvements for a speciﬁc number of iterations called the refreshing gap. Finally it yields a reassignment of particles. They described the design of the test system that was used to carry out experiments with 25 artiﬁcial and 13 industrial test objects that exhibit diﬀerent search space properties. Both particle swarm optimization and genetic algorithms were used to automatically generate test cases for the same set of test objects. They used the branch coverage as their test adequacy criteria. The results of the experiments showed that particle swarm optimization is competitive with genetic algorithms and even outperforms them for complex cases. Andreas et al. [9] and Khushboo et al. [10] used the branch coverage as their test adequacy criteria. Once such a criterion has been chosen, test data must be selected to fulﬁll the criterion. One way to accomplish this is to select paths through the program whose elements fulﬁll the chosen criterion, and then to ﬁnd the input data which would cause each of the chosen paths to be selected. Li et al. [11] used the all-paths selection criterion, which require all program paths to be selected. Using such path selection criteria as the basis for test data selection criteria presents two distinct problems. The ﬁrst problem is that traversing all paths does not guarantee that all errors will be detected. The second problem is that programs with loops may have an inﬁnite number of paths, and thus, the all-paths criterion must be replaced by a weaker one which selects only a subset of the paths. But in our approach, we are using all-uses as test adequacy criterion which focuses on how the variables are bound to values, and how these variables are used. Rather than selecting program paths based solely on the control structure of a program, the data ﬂow all-uses criteria keep track of input variables through a program, following them as they are modiﬁed, until they are ultimately used to produce output values.

7

Conclusion and Future Work

We have developed an algorithm for generating test cases using PSO. The PSO technique accepts an instrumented version of the program to be tested,the list of def-use paths to be covered, the number of input variables. Also, it accepts the the population size, maximum number of iterations, values of inertia factor, self conﬁdence and swarm conﬁdence. The algorithm produces a set of test cases and the set of def-use paths covered by each test case. Experiments have been carried out to evaluate the eﬀectiveness of the proposed PSO compared to the GA technique. The results of these experiments

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show that the PSO technique outperforms the GA technique in all 14 programs used in the experiment. In four programs, the PSO reached higher coverage percentage in fewer generation than the GA technique. Our future work will be to study the test case generation using ant colony optimization technique for data ﬂow testing.

References 1. Girgis, M.R.: Automatic test data generation for data flow testing using genetic algorithm. Journal of Universal Computer Science 11(6), 898–915 (2005) 2. Pargas, R.P., Horrold, M.J., Peck, R.R.: Test data generation using genetic algorithm. The Journal of Software Testing,Verification and Reliability (1999) 3. Michael, C.C., McGraw, G., Schatz, M.A.: Generating software test data by evolution. IEEE Transactions on Software Engineering 27(12), 1085–1110 (2001) 4. Pei, M., Goodman, E.D., Gao, Z., Zhong, K.: Automated software test data generation using genetic algorithm. Technical report, GARGE of Michigan State University (1994) 5. Jones, B.F., Sthamer, H.H., Eyres, D.E.: Automatic structural testing using genetic algorithms. Software Engineering Journal 8(9), 299–306 (1996) 6. Roper, M., Maclean, I., Brooks, A., Miller, J., Wood, M.: Genetic algorithm and the automatic generation of test data. Technical report, University of Strathelyde (1995) 7. Watkins, A.E.L.: A tool for automatic generation of test data using genetic algorithm. In: Software Quality Conference, Dundee, Scotland (1995) 8. Kennedy, J., Eberhart, R.: Particle swarm optimization. In: IEEE International Conference on Neural Networks, pp. 1942–1948. IEEE Press, Los Alamitos (1995) 9. Windisch, A., Wappler, S., Wegener, J.: Applying paricle swarm optimization to software testing. In: GECCO, London, England, United Kingdom. ACM, New York (2007) 10. Agrawal, K., Srivastava, G.: Towards software test data generation using discrete quantum particle swarm optimization. In: ISEC, Mysore, India (February 2010) 11. Li, A., Zhang, Y.: Automatic generating all-path test data of a program based on pso. In: World Congress on Software Engineering. IEEE, Los Alamitos (2009) 12. Eberhart, R.C., Kennedy, J.: A new optimizer using particle swarm theory. In: 6th International Symposium on Micromachine Human Science, pp. 39–43 (1995) 13. Rapps, S., Weyuker, E.J.: Selecting software test data using data flow information. IEEE Transactions on Software Enggineering 11(4), 367–375 (1985) 14. Allen, F.E., Cocke, J.: A program data flow analysis procedure. Communication of the ACM 19(3), 137–147 (1976)

Efficient Storage of Massive Biological Sequences in Compact Form Ashutosh Gupta1 , Vinay Rishiwal2, and Suneeta Agarwal3 1,2

Institute of Engineering & Technology, M.J.P. Rohilkhand University Bareilly, UP, India 3 Motilal Nehru National Institute of Technology Allahabad, UP 211004, India [email protected], [email protected], [email protected]

Abstract. This paper introduces a novel algorithm for DNA sequence compression that makes use of a transformation and statistical properties within the transformed sequence. The designed compression algorithm is efficient and effective for DNA sequence compression. As a statistical compression method, it is able to search the pattern inside the compressed text which is useful in knowledge discovery. Experiments show that our algorithm is shown to outperform existing compressors on typical DNA sequence datasets. Keywords: Biological sequences and Compression.

1 Introduction There are plethora of particular types of data which should be compressed, for ease of storage and communication. Amongst them are texts (natural language, programs, etc.), images, sounds, etc. In this paper, we spotlight the compression of a definite kind of texts only, namely DNA sequences. Some important molecular biology databases (ERIBL, GenRank. DDJB) are developed around the world to accumulate nucleotide sequences (DNA, RNA) and amino-acid sequences of proteins. It is well acknowledged that their size increases nowadays exponentially fast. Not as big yet as some other scientific databases, their size is in hundreds of GB [27]. The compression of genetic information as a result constitutes a very important job. A DNA sequence is composed of nucleotides of four types: adenine (abbreviated A), cytosine (C), guanine (G) and thymine (T). With escalating number of genome sequences being made available, the difficulty of storing and using databases has to be addressed. The importance of mutual compressibility for discovering patterns of interest from genomes is recognized by Stern et al. [21]. Powell et al. [19] show that compressibility is a fine dimension of relatedness among sequences and can be effectively used in sequence alignment and evolutionary tree construction. Conventional text compression schemes are not competent when DNA sequences are concerned. Since DNA sequence contain only 4 bases A, G, T, C, each base can be represented by 2 bits. Though standard compression tools like compress, gzip and bzip2 have S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 13–22, 2010. © Springer-Verlag Berlin Heidelberg 2010

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more than 2 bits per base when compressing DNA data. Consequently, DNA compression has become a challenge. Algorithms like GenCompress [6], Biocompress [11], Biocompress-2 [12], that use the characteristics of DNA like point mutation or reverse complement achieve a compression rate about 1.76 bits per base. Many compression methods have been exposed to compress DNA sequences. We refer to e.g., [1,5,6] and references therein for a sampler of rich literature existing on these subjects. Invariably, all the methods initiate so far take advantage of the fact that DNA sequences are made of only 4 alphabets, together with techniques to exploit the repetitive nature of DNA [20]. In this paper, we present a two pass algorithm for biological sequence compression. Our compressor works in two phases. In first phase, the 4 base symbols are transformed into 256 ASCII character set. In second phase, actual encoding is performed with Word Based Tagged Code [17]. The compression algorithm achieves around 1.49 bits per symbol. The results show that our algorithm is shown to outperform existing compressors on typical DNA sequence datasets. This paper is organized as follows. Section 2 reviews existing research on biological compression. Our algorithm is described in section 3. Section 4 describes encoding and decoding algorithm. Experimental results are presented in section 5. Finally, section 6 concludes our work.

2 Related Work The information in DNA sequences is represented by four alphabets (A,C,G,T), if the sequences were to be completely arbitrary (that is, completely uneven or incompressible [28], then, we need two bits to code each nucleotide base pair. Biological sequences are however known to utter important determined information between different generations of organisms. Moreover, from the analysis point of compression and sequence understanding, the repetitions inherent in biological sequences involve redundancies which can provide a path for a momentous compaction. The credit of such dependencies is the starting point for biological sequence compression. 2.1 Standard Text Compression There are three common classes of lossless compression methods: substitution, dictionary based and context-based methods [29,30]. In substitution methods [26], each character is replaced with a new codeword, such that characters that arise more frequently are replaced with shorter codewords, thus achieving an overall compression. In dictionary-based methods, a dictionary of frequently occurring characters or group of characters is constructed from the input sequence. Compression is achieved by replacing the positions of the characters with a pointer to their positions in the dictionary. The dictionary could be off-line [25] or on-line. In on-line dictionary methods [31], the text itself is used as the dictionary, and characters that have formerly been observed in the sequence are replaced with pointers to the positions of their previous occurrence. The popular LZ-family of algorithms is based on on-line dictionaries[31,32]. Off-line dictionary methods compress the input sequence in two passes: first to build the dictionary by identifying the repeating sequences, and the second to

Efficient Storage of Massive Biological Sequences in Compact Form

15

encode the repeats with pointers into the dictionary. Rubin [33], and Wolff [34] describe various issues in dictionary-based schemes, including dictionary management. Storer and Szymanski [35] provide a general framework to describe different substitution-based schemes. The context-based compression schemes make use of the information that the probability of a character could be affected by the nearby characters. The contexts are generally articulated in terms of character neighborhoods in the sequence. The PPM (prediction by partial match) family of compression schemes [36] uses contexts of dissimilar sizes. Characters are encoded by taking into account the previous occurrences of their current context and then selecting the longest matching contexts. Block sorting methods also make use of contexts, but here the contexts are characters permuted in such a manner that the contexts appear to be sorted - that is, characters in lexicographically similar contexts will be clustered together. This clustering can thus be exploited to code the symbols in a compact way. The block sorting approach is called the Burrows-Wheeler Transform or BWT for short [37, 38]. The LZ-based algorithms are the most well-liked due to their availability on most commercial computing platforms (utilities such as GZIP, WINZIP, PKZIP, GIF, and PNG are LZbased schemes). However, in terms of compression performance, the PPM schemes provide the best compaction, although they are slower. The BWT is second to the PPM in compaction performance, but faster than the PPM schemes. They are, however, generally slower than the LZ-family. This middle position presentation has made the BWT an important addition to the long list of text compression algorithms. 2.2 DNA Compression The initial special purpose DNA compression algorithm found in the literature is BioCompress developed by [11]. BioCompress detects a precise repeat in DNA using an automaton, and uses Fibonacci coding to encode the length and position of its previous location. If a subsequence is not a repeat, it is encoded by the naive 2 bits per symbol technique. The enhanced version, BioCompress-2 [12] uses a Markov model of order 2 to encode non-repeat regions. The Cfact DNA compressor developed by Rivals et al. [20] also searches for the longest exact repeats but is a two-pass algorithm. It builds the suffix tree of the sequence in the first pass, and does the real encoding in the second pass. Regions not repeated are also encoded by 2 bits per symbol. The Off-line approach by Apostolico and Lonardi [3] iteratively selects repeated substrings for which encoding would gain maximum compression. An analogous substitution approach is used in GenCompress by Chen et al. [6] except that approximate repeats are exploited. An inexact repeat subsequence is encoded by a pair of integers, as for BioCompress-2, and a list of edit operations for mutations, insertions and deletions. Since almost all repeats in DNA are approximate, GenCompress obtains better compression ratios than BioCompress-2 and Cfact. The similar compression technique is used in the DNACompress algorithm by Chen et al. [7], which finds significant inexact repeats in one pass and encodes these in another pass. A good number of other compression algorithms employ similar techniques to GenCompress to encode approximate repeats. They differ only in the encoding of non-repeat regions and in detecting repeats. The CTW+LZ algorithm developed by Matsumoto et al. [16] encodes significantly long repeats by the substitution method,

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A. Gupta, V. Rishiwal, and S. Agarwal

and encodes short repeats and non repeat areas by context tree weighting [23]. At the cost of time complexity, DNAPack Behzadi and Fessant [4] employs a dynamic programming approach to find repeats. Non-repeat regions are encoded by the best choice from an order 2 Markov model, context tree weighting, and naive 2 bits per symbol methods. Several DNA compression algorithms join substitution and statistical styles. An inexact repeat is encoded using (i) a pointer to a previous occurrence and (ii) the probabilities of symbols being copied, changed, inserted or deleted. In the MNL algorithm by Tabus et al. [22] and its improvement, GeMNL by Korodi and Tabus [14], the DNA sequence is split into fixed size blocks. To encode a block, the algorithm searches the history for a regressor, which is a subsequence having the minimum Hamming distance from the current block, and represents it by a pointer to the match as well as a bit mask for the differences between the block and the regressor. The bit mask is encoded using a probability distribution estimated by the normalized maximum likelihood of similarity between the regressor and the block. The two pure statistical DNA compressors published so far are CDNA by Loewenstern and Yianilos [15] and ARM by Allison et al. [2]. In the former algorithm, the probability distribution of each symbol is obtained by approximate partial matches from history. Each approximate match is with a previous subsequence having a small Hamming distance to the context preceding the symbol to be encoded. Predictions are combined using a set of weights, which are learnt adaptively. The latter ARM algorithm forms the probability of a subsequence by summing the probabilities over all explanations of how the subsequence is generated. Both these approaches yield significantly better compression ratios than those in the substitutional class and can also produce information content sequences. CDNA has many parameters which do not have biological interpretations. Both are very computationally intensive. The algorithm named DNAZip presented in this paper is a statistical algorithm. The method works in two phases. Firstly, a transformation is applied to original sequence and then encoding is performed in second phase. The compressor is designed with the aim that it also does searching in compressed sequence. This approach comes from the fact that it is better to keep sequences compressed all the time and searching is done to reduce CPU I/O time. This is a purpose of our compressibility research.

3 Overview of the Method A DNA sequence is composed of 4 base symbols: A, T, C and G. The method named DNAZip works in two phases. In first (transformation) phase, the original DNA sequence consisting of 4 base symbols are transformed into 256 ASCII symbol sequence. Let the sequence be S1. In second (encoding) phase, sequence S1 is encoded by Word based Tagged Code (WBTC) method [17]. In the following sections, the two phases of the method is described. 3.1 Transformation Phase The first phase of the method transforms the original DNA sequence consist of 4 base symbols into 256 ASCII symbol sequence. The working of transformer is as follows:

Efficient Storage of Massive Biological Sequences in Compact Form

17

In first round, the transformer reads two bytes of the original sequence and converts into one byte. As DNA sequence is consist of 4 symbols, 42 i.e. 16 possible combinations are there. These combinations are represented as symbol 0 to 15. The resulting sequence is consist of 16 symbols and store in a temporary buffer. In this way, we reduce the size of original sequence by 50%. In next second round, these 16 symbols (i.e. 0 to 15 symbols) are again transformed into 162=256 ASCII symbols. This time, the resulting sequence S1 is reduced to 25% as compared to original sequence. Now the sequence S1 is ready for encoding purpose. 3.2 Encoding Phase The reduced sequence S1 obtains from the transformation phase contains ASCII symbols. The sequence S1 is seen as an alternating sequence of words and separators, where a word is a maximal sequence of alphanumeric characters and a separator is a maximal sequence of non-alphanumeric characters. As the base symbols (only four symbols) have repetitive property in DNA sequence, many symbols in the S1 are transformed into separator symbol. Since the text is not only composed of word but also of separators, a model must also be chosen for them. In [29] two different alphabets are used: one for words and other for separators. Since a strict alternating property holds, there is no confusion about which alphabet to use once it is known that the text starts with word or separator. In [40] a new idea of spaceless words is presented. If a word is followed by a space, we just encode the word. If not, we encode the word and then the separator. At decoding time, we decode a word and assume that a space follows, except if the next symbol corresponds to a separator. In this case the alternating property does not hold, and a single alphabet is used. Our idea is to use a spaceless model for sequence S1. Thus sequence S1 is consisting of word followed by a space. The statistics of number of words in sequence S1 for different test data are given in section 5. Recall that S1 is itself reduced to 25% of original sequence. Now, the WBTC coding scheme is applied to this transformed sequence S1. Next, WBTC scheme and how it is applied to S1 is explained. 3.3 Word Based Tagged Code The code generated by this technique always ends with either 01 or 10 bits. This implies that the bit combination 01 or 10 act as a flag to indicate the end of code. The coding procedure of Word based Tagged Code is simple. First, source text is parsed and all the statistics of vocabulary in the sequence S1 is gathered. Here, the source text is transformed sequence S1. The vocabulary is sorted with non increasing frequency. Each codeword in WBTC will be generated with the help of 2 bit patterns (00, 11, 01, 10). Following procedure is used for the assignment of codes to the vocabulary. 1. 2. 3.

At the very first level l=1, the first 2l words (rank: 0 to 20 of the vocabulary are assigned codes as 01 and 10 respectively. For the next level l=2, 2l words in positions from 21 + 0 to 22 +20 are encoded using four bits by adding 00 and 11 as prefix to all the codes of previous level. In general, for any value of level l, next 2l words present in the positions from 2l-1 +2l-2 + ...+0) to 2l +2l-1 +...+20) of vocabulary are assigned codes using 2 x l

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A. Gupta, V. Rishiwal, and S. Agarwal

4.

bits, by adding 00 and 11 as prefix to all the codes generated at preceding level. The above procedure is repeated until all the N words in the sequence S1 are encoded.

In this coding scheme, we neither to store the frequencies nor the codewords are required to store along with compressed file. This makes vocabulary very small. The coding technique is a prefix code, no codeword is a proper prefix for any other code, and hence it is instantaneously decodable.

4 Encoding and Decoding Algorithm 4.1 Encoding Algorithm The encoding algorithm computes the codewords for all the words of the sorted vocabulary and stores them in a data structure that we call CodeVector. In this way, the first pass generates codes for all the vocabulary words of the input text. In second pass, we read the words and assign their codes from the CodeVector generated in first pass. Thus, compressed file is generated. The vocabulary is stored along with the compressed text in order to decompress it later. There is no need to store either the codewords (in any form such as a tree) or the frequencies in the compressed file. It is enough to store the plain words sorted by frequency. Therefore, the vocabulary will be slightly smaller because no extra information other than the words alone is here. Now we describe the complete encoding algorithm with the help of an example. Example 1 Let the original sequence be T = AA CT CG CA AT AT. The size of T is 12 bytes. The space between symbols are just for readability purpose. Transformation Phase Round 1 produces sequence in the form of 0 7 6 4 3 12 Round 2 produces sequence S1 = 7 100 60 The round 1 and 2 transformed sequences are generated according to the implementation. Due to the limitation of pages we exclude to illustrate this point here. WBTC coding phase The S1 is encoded with the help of WBTC coding scheme. As there are only 3 symbols with frequencies 1, the vocabulary is small and contains only three symbols 7, 100 and 60 with codes 01, 10, 0001 respectively. The complete compressed file (F) is represented as sequence of binary string "01100001". The size of F is 1 byte. In this way we achieve around 8% compression ratio (0.5 bpc). 4.2 Decoding Algorithm The first step to decompress the compressed text is to load the words that compose the vocabulary in a separate data structure. Since these words were stored in sorted form (with respect to frequency) along with the compressed text during compression, the

Efficient Storage of Massive Biological Sequences in Compact Form

19

vocabulary which is retrieved is sorted by frequency. Once the sorted vocabulary is obtained the decoding of codewords can begin immediately. At any step i, i=1 to ......, the decoder reads a codeword from compressed file till it ends with 01 or 10. Let the read codeword be ci$ and its length be bi bits. Next the level of ci is computed and decoder finds the range of words with in the level i. Then, binary search is used at level i to find out the exact rank r of word wi corresponding to the codeword ci by checking the decimal value of code ci. The above decoding algorithm is applied to compressed file F to recover the original sequence T.

5 Empirical Results We implemented the encoder and decoder of DNAZip in C and ran experiments on a machine with Pentium IV 2.8Ghz CPU and 1GB of RAM, using the Fedora Core 2 Linux. The compression results are calculated from the size of real encoded files. The Table 1 shows the statistics of original sequences when transformation is applied on them. The transformation process converts the original sequences into words and separators. The total number of words in the transformed sequence is represented by N. The number of distinct words is represented by n. The first and second column showed the name of test files and their respective size in bytes. The values of N and n are shown in column three and four. For comparison, we applied our algorithm on a standard dataset of DNA sequences that has been used in most other DNA compression publications. The dataset contains 7 sequences including chloroplast genomes (CHMPXX), five human genes (HUMDYSTR, HUMGHCSA, HUMHBB, HUMHDAB and HUMHPRTB) and mitochondria genome (MTPACG). Table 2 compares the compression results, in bits per symbol (bps), of DNAZip to that of other standard and DNA compressors on the dataset. The compression algorithms includes gzip, bzip2, gzip-4, bzip-4, ac, dna2, Offline, CTW + LZ, Bio Compress-2 (BioC) , GenCompress (GenC) , DNACompress (DNAC), DNAPack (DNAP) , CDNA [15], GeMNL [14] and XM. The result of CDNA compressor for CHMPXX is not available. The GeMNL results are also reported without the sequence HUMHBB and in two decimal place precision. We include the average compression results of each algorithm in the last row of Table 2. Table 1. Details of Test data Filename CHMPXX HUMDYSTR HUMGHCSA HUMHBB HUMHDAB HUMHPRTB MTPACGA

Size (bytes) 121024 38770 66495 73308 58864 56737 100314

N 7869 2810 5384 5269 4802 4187 6706

n 4052 1595 2593 2728 2529 2232 3484

20

A. Gupta, V. Rishiwal, and S. Agarwal Table 2. Comparison of DNA compression Sequence

CHMP XX

HUM DYSTR

HUM GHCSA

HUMHB B

HUMH DAB

HUM HPRTB

MTPACG A

Average

Length Gzip Bzip Ac-o2 Ac-o3 gzip-4 bzip-4 dna2 O_-line BioComp ress GenComp ress CTW+LZ DNACom press DnaPack CDNA GeMNL Expert Model DNAZip

121024 2.2818 2.1218 1.8364 1.8425 1.8635 1.9667 1.6733 1.9022 1.6848

33770 2.3618 2.1802 1.9235 1.9446 1.9473 2.0678 1.9326 2.0682 1.9262

66495 2.0648 1.7289 1.9377 1.9416 1.7372 1.8697 1.3668 1.5993 1.3074

73308 2.245 2.1481 1.9176 1.9305 1.8963 1.9957 1.8677 1.9697 1.88

58864 2.2389 2.0678 1.9422 1.9466 1.9141 1.9921 1.9036 1.974 1.877

56737 2.2662 2.0944 1.9283 1.9352 1.9207 2.0045 1.9104 1.9836 1.9066

100314 2.2919 2.1225 1.8723 1.8761 1.8827 1.9847 1.8696 1.9155 1.8752

2.2721 2.0983 1.9205 1.9267 1.9038 1.9875 1.7891 1.9383 1.7837

1.673

1.9231

1.0969

1.8204

1.8192

1.8466

1.8624

1.7428

1.669 1.6716

1.9175 1.9116

1.0972 1.0272

1.8082 1.7897

1.8218 1.7951

1.8433 1.8165

1.8555 1.8556

1.7389 1.7254

1.6602 1.6617 1.6575

1.9088 1.93 1.9085 1.9031

1.039 0.95 1.0089 0.9845

1.7771 1.77 1.7524 1.5544

1.7394 1.67 1.7059 1.6696

1.7886 1.72 1.7639 1.7378

1.8535 1.85 1.844 1.8466

1.7148 1.6483 1.6488 1.6946

1.4867

1.5602

1.034

73308

1.771

1.565

1.5058

1.4967

DNAZip outperforms all other algorithms in most sequences from the standard dataset. The average compression ratio is also significantly better than other compressors. Since due to missing compression results of several sequences for CDNA and GeMNL, we are not able to compute the same average. For comparison purpose, we compare the average of the only available results. The average compression ratio of six sequences reported for CDNA is 1.6483 bps, while DNAZip's average performance on the same set is 1.4984 bps. On the six sequences excluding HUMHBB, GeMNL averages 1.6488 bps, compared to DNAZip's 1.4984 bps. The above results shows that DNAZip achieves better compression ratio (in terms of bps) compared to other DNA compressor.

6 Conclusions We have presented a simple and statistical compressor DNAZip for DNA sequences. The designed compression algorithm is efficient and helpful for DNA sequence compression. The algorithm works in two phases and uses statistical properties of the biological sequence for compression. Our algorithm is shown to outperform all published DNA compressors to date while maintaining a practical running time.

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3. Apostolico, A., Lonardi, S.: Compression of biological sequences by greedy off-line textual substitution. In: DCC, pp. 143–152 (2000) 4. Behzadi, B., Fessant, F.L.: DNA compression challenge revisited: A dynamic programming approach. In: Apostolico, A., Crochemore, M., Park, K. (eds.) CPM 2005. LNCS, vol. 3537, pp. 190–200. Springer, Heidelberg (2005) 5. Boulton, D.M., Wallace, C.S.: The information content of a multistate distribution. Theoretical Biology 23(2), 269–278 (1969) 6. Chen, X., Kwong, S., Li, M.: A compression algorithm for DNA sequences and its applications in genome comparison. In: RECOMB, p. 107 (2000) 7. Chen, X., Li, M., Ma, B., John, T.: DNA Compress: Fast and effective DNA sequence compression. Bioinformatics 18(2), 1696–1698 (2002) 8. Cleary, J.G., Witten, I.H.: Data compression using adaptive coding and partial string matching. IEEE Trans. Comm. COM-32(4), 396–402 (1984) 9. Dix, et al.: Exploring long DNA sequences by information content. In: Probabilistic Modeling and Machine Learning in Structural and Systems Biology Workshop Proc., pp. 97– 102 (2006) 10. Dix, et al.: Comparative analysis of long DNA sequences by per element information content using different contexts. BMC Bioinformatics (to appear, 2007) 11. Grumbach, S., Tahi, F.: Compression of DNA sequences. In: DCC, pp. 340–350 (1993) 12. Grumbach, S., Tahi, F.: A new challenge for compression algorithms: Genetic sequences. Inf. Process. Manage. 30(6), 875–886 (1994) 13. Hategan, A., Tabus, I.: Protein is compressible. In: NORSIG, pp. 192–195 (2004) 14. Korodi, G., Tabus, I.: An efficient normalized maximum likelihood algorithm for DNA sequence compression. ACM Trans. Inf. Syst. 23(1), 3–34 (2005) 15. Loewenstern, D., Yianilos, P.N.: Significantly lower entropy estimates for natural DNA sequences. Computational Biology 6(1), 125–142 (1999) 16. Loewenstern, D., Yianilos, P.N.: Biological sequence compression algorithms. Genome Informatics 11, 43–52 (2000) 17. Gupta, A., Agarwal, S.: Partial retrieval of compressed semi-structured documents. Int. J. Computer Applications in Technology (IJCAT) (to appear) 18. Nevill-Manning, C.G., Witten, I.H.: Protein is incompressible. In: DCC 1999, pp. 257–266 (1999) 19. Powell, D.R., Allison, L., Dix, T.I.: Modelling-alignment for non-random sequences. In: Advances in Artificial Intelligence, pp. 203–214 (2004) 20. Rivals, et al.: A guaranteed compression scheme for repetitive DNA sequences. In: DCC, p. 453 (1996) 21. Stern, et al.: Discovering patterns in plasmodium falciparum genomic DNA. Molecular & Biochemical Parasitology 118, 175–186 (2001) 22. Tabus, I., Korodi, G., Rissanen, J.: DNA sequence compression using the normalized maximum likelihood model for discrete regression. In: DCC, p. 253 (2003) 23. Willems, F.M.J., Shtarkov, Y.M., Tjalkens, T.J.: The context-tree weighting method: Basic properties. IEEE Trans. Info. Theory, 653–664 (1995) 24. Witten, I.H., Neal, R.M., Cleary, J.G.: Arithmetic coding for data compression. Comm. ACM 30(6), 520–540 (1987) 25. Gupta, A., Agarwal, S.: A Novel Approach of Data Compression for Dynamic Data. In: Proc. of IEEE third International Conference on System of Systems Engineering, California, USA, June 2-4 (2008)

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Maximum Utility Meta-Scheduling Algorithm for Economy Based Scheduling under Grid Computing Hemant Kumar Mehta1, Priyesh Kanungo2, and Manohar Chandwani3 1

School of Computer Science, Devi Ahilya University, Indore, India 2 Patel College of Science & Technology, Indore, India 3 Department of Computer Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, India [email protected], [email protected], [email protected]

Abstract. In this paper, an economy-based Grid algorithm named as maximum utility (MU) has been presented. The algorithm maximizes the utility for all of the users. The maximum utility for the resource provider indicates the higher profit and for the resource consumers the maximum utility indicates successful execution of users processes with the lower cost of execution. Thus the utility results in the better incentives to the users. The algorithm uses the market based parameters to determine the utility value for both the resource consumers and the resource providers. Two parameters, loss factor and net savings, have been used to characterize the utility values for resource providers and resource consumers. Besides cost of execution, the algorithm uses the past performance of resource providers before allocating a new process. The algorithm uses a parameter called reputation point that will be credited to the resource provider’s account after successful completion of a process. A hierarchical decentralized scheduling framework is also proposed for better performance of scheduling algorithms. Keywords: Economy-based scheduling, market-based scheduling, grid computing, meta-scheduler, utility value.

1 Introduction Grids are attractive platforms for deploying large scale parallel and distributed applications with high performance requirements. Scheduling applications on grid platforms pose a number of challenges. The decision process, by which application components are allocated to available resources for optimizing some metric of performance, is the key issue for Grid scheduling algorithms. After getting strong attraction from researchers, grid computing has also been of interest for the IT enabled commercial applications. To get proper return on investment on the technology in an enterprise, its resources must not only be utilized effectively but their profitability should also be considered. Economy-based grid scheduling has been an area of interest for a number of grid researchers. This paper presents a new economy-based scheduling algorithm. We call this algorithm as maximum utility (MU) algorithm which optimizes the utility for all type of S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 23–33, 2010. © Springer-Verlag Berlin Heidelberg 2010

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users in the grid. There are three types of user in the grid environment, the resource consumers (consumers), service providers (providers) and the users acting as both; the resource consumers as well as service providers. The meaning of utility is different for the different users. For the consumers the utility means the cost of execution of their processes on the grid therefore, the utility will be higher if this cost is less. For the service providers the utility is their profit, therefore, the most profitable situation for service providers is the maximum utility for them. Main aim of the meta-scheduler is to increase the profit of providers. The metascheduler also aims at the fair allocation of processes among the resources. By fair allocation, we mean each of the resources must have equal opportunity to participate in the scheduling process. It also tries to minimize the cost of execution of the consumer’s processes. This paper is organized as follows. Section 2 examines related work. Section 3 describes the maximum utility algorithm. The simulator used for experimentation, the experimental setup and analysis of the results are described in Section 4. Section 5 presents a hierarchical decentralized framework for the implementation of the algorithm. Finally, Section 6 concludes our research and development effort.

2 Related Work Literature in the field of grid scheduling contains a large body of research work. Buyya et al. and Broberg et al. have given detailed survey of economy based grid scheduling algorithm along with high successful rate [2, 3]. Major emphasis of these surveys is economy based grid scheduling. Recently, several works have been reported in the economy based scheduling, that are not covered by these survey. Patil et al. proposed a reward based model for creating economy based computing environment. The model uses the concept of grid points instead of currency. Initially, consumer and resource provider are credited with some points. On the successful completion of a process, the grid points required by the process are debited from the consumer’s account and credited to the resource provider’s account. This is simple model which do not even consider the deadlines. Each task allotted to a resource must be completed whatever may be the required time [8]. Altmann and Routzounis presented an economy based modeling of grid services. They have proposed a service oriented market based grid architecture. In this architecture, several web services are proposed including the service for resource request, resource booking, broker, accounting and charging. These services are proposed over the existing grid middleware. However, this model is a conceptual model. Implementation details to support the model have not been provided [1]. Xiao et al. have proposed an incentive-based scheduling algorithm (IB) for market based grid computing environment. This algorithm uses a peer-to-peer scheduling framework to decentralize the algorithm. They have suggested that both resource providers and consumers must be given the autonomy regarding the scheduling decisions. They have also recommended that both the players in the market must have sufficient incentive to participate and stay in the market. Since the interest of resource providers and consumers are different, they have suggested different performance metric for both of them. According to them, as the user is mainly interested in the

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successful execution of its processes, for the resource consumers they choose a performance metric called the successful-execution rate. By successful-execution rate they mean the number of processes successfully completed their execution without missing the deadline. Similarly, for the resource providers the main incentive is that they must have equal opportunity of participation in the market and the fair allocation of the profit among the providers based on their capacity. They defined job announcement, competition degree (CD) and price as the mechanisms to implement market model in the computational grid. Furthermore, they developed four heuristic algorithms to utilize these market implementation mechanisms and optimize the incentives for each of the users [10]. In addition, two types of competition attitude of providers are defined aggressive and conservative. The aggressive providers do not consider the unconfirmed processes while estimating whether they will be able to meet the deadline. With such an attitude, there are fair chances of deadline missing but this type of attitude results into increased profit. On the other hand, the conservative providers take into account the unconfirmed processes for some time. With this type of attitude there is no chance of missing deadline but these types of providers will loose several probable chances of winning the bid. They have implemented four algorithms for resource providers. The first algorithm named as job competing, is used for submitting the bid for the announced jobs. The second algorithm called as heuristic local scheduling, is used for placement and maintenance of the order of the processes in the job queue of the provider. The concept of penalty is implemented in the heuristic local scheduling. If any process failed to meet its deadline, then penalty must be applied to that node. The price-adjusting algorithm dynamically adjusts the price of the resource as per its participation in the market. Similarly the competition-degree-adjusting algorithms dynamically adjust the CD according to the market situations. Each time the penalty increase the, the value of CD tends towards the aggressive attitude (CD=1) or conservative attitude (CD=0) depending on the ratio of penalty to profit is greater than or less than the threshold value. Garg et al. presented a market-oriented meta-scheduler for grids. The metascheduler is a trade-off between the market-oriented and traditional scheduling algorithms. To achieve this trade-off, they have defined two valuation metrics, one for resource consumer’s application and the other for the resource of the providers. The meta-scheduler uses the Continuous Double Action (CDA) to find suitable nodes for the processes. They have created five components for the grid-market. These components include grid Information service and Resource Catalog, Reservation service, Pricing System, Meta-Scheduler and Accounting System [4]. To the best of our knowledge, besides the research work of the Xiao et al., no other research explore the market based scheduling that is beneficial for both the resource provider and resource consumers. The incentive-based scheduling algorithm introduced by Xiao et al. uses non economy based performance metrics. However, in order to properly implement the market based scheduling, economy based performance metrics must be used. There must be direct concept of the cost, profit and penalty in the market based model. Moreover, the algorithm developed by Xiao et al. is a decentralized peer-to-peer based algorithm that broadcast the job announcements to all the providers.

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3 Maximum Utility Meta-Scheduling Fig. 1 shows the architecture of the meta-scheduler and the grid. The economy-based grid can have three types of users: (a) Consumers, (b) Providers and (c) Users working as both, the consumers as well as the providers. The consumers are the users having the processes to execute on the grid. While the providers are having the various resources, that can be utilized by the processes of consumers. Providers publish their billboard on the media (information directory in the Fig. 1). The billboard contains a variety of information regarding the facilities or the resources rendered by the providers. The media directory provides resource matching algorithm for mapping the consumers’ requirement specification with the capable providers. In order to process a new task, the consumer searches the clusters for the appropriate node having capability necessary to execute the task. The best suited cluster is selected based on the details of the task. These details include Process-id, execution time, input file size, start date, deadline date, budget, deadline miss limit, optimization, negotiable property and negotiation factor. Analogues to the concept of “yellow pages” in real world, the providers publish details regarding their resources and services in the media directory. Presently, the database of media directory is a flat file. The service providers publish their details in the database. The information written in the database contains the details about the cluster and nodes in the cluster such as Cluster-id, number of nodes in the cluster, node-ids, speed of the processor in the node, memory-size, hard disk capacity, weekday-load and holiday-load of the node, weekday-price and holiday-price of the node, special offers at the node, weight of the node (currently determined by the CPU speed),list of the holidays in the area where the node is situated and the booking status of the node.

USERS

Providers

Consumers

Clusters Nodes

Processes

Publishes

Publishes

Information tory

Direc-

Computing Nodes

Process

Fetches Meta-Scheduler Scheduling Accounting

Fig. 1. The utility grid and meta-scheduler

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The billboard will be updated at fixed intervals, say hourly or with the change in the status of the resource. The update time can be optimized depending on the resource usage. The price of the resource varies with the type of resource and the required timeslot. The price may also vary according to the usage history. The slots having high demand will have higher price and the slots with low demand will have lower price. The advance reservation concept is implemented here so that the deadline of the processes is not missed due to unavailability of the systems. The matching algorithm performs several other tasks besides matching the suitable service providers. To begin with, it will select the most appropriate service provider according to the optimization criterion of the process and the availability of the resource. The resource is marked as available if it is having free time slot before the deadline of the process. Resource booking request is then sent to the selected service provider that gives the final acceptance. Before receiving a request, if the resources are already booked by some other consumer, the subsequent resource booking requests will be denied. If resource booking request is accepted by the service provider, the process and its data will be sent to the service provider for the execution on the requested time slot. If the process is not accepted by the selected provider or no suitable provider could be found, the budget or deadline may be changed according to the preferences of the process. The matching process starts again using one of the two techniques. First option is to include all the grid units and each node from the grid unit in the matching process. The other technique involves only those service providers who have missed the range due to cost or time constraints as these constraints are now relaxed. We have chosen the second option as it will reject the nodes which are not capable of executing the process, thereby increasing the efficiency of the searching process. If suitable cluster is not found, process can relax the deadline and/ or increase the budget depending on the configuration of the negotiation parameters. This new information is also published in the media directory. Again, the matching process starts to find best suitable service provider clusters. If still the process couldn’t find suitable node, the process is declared to be rejected by the grid. The media directory service can be implemented on a group of servers for improved efficiency. Moreover, it can be made payable service and can also be hosted by any of the grid units to improve its profit. The media directory also performs the role of accounting unit as it is the trusted unit between the resource provided and resource consumer. The media directory can act as a broker and keep the margin money as its profit. The margin money is calculated as: M =B – P where, M is margin money, B is budget of process and P is price of selected system. The accounting is done based on the execution status of the processes at various computing nodes. The maximum utility for the resource provider is the maximum profit earned from each of the resource. In order to have maximum profit, the difference between the expected earning and actual earning must be minimal if not zero. We call this difference as loss factor. Loss Factor =EE–AE where, the EE is the expected earning and AE is the actual earning.

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The EE is calculated as

Where, n is the number of days, i is the index for particular day and j is the index for the hours. cij is the cost of jth hour of ith day. Similarly the maximum utility for the consumers is the lower cost of execution of its process. The cost will be lower if the difference of actual cost to the budgeted cost is small. This difference is called net savings and defined as: Net Saving=AC – BC Where the AC is the actual cost charged by providers and the BC is the budgeted cost as decided by the consumers. The actual cost is calculated by per unit cost of resource usage multiplied by total execution time unit taken by the process. Each process is created with some bonus reputation points that can be awarded to the resource provider on the successful completion before the process deadline. These reputation points are checked before submitting a process to a computing node for execution along with the price of that computing node. In this way, the history of the resource providers will help them to attract more customers. We define the reputation as a two-tuple Rp=(T, R), where T is the total reputation points earned and the R is the ratio of the total reputation points earned to the total reputation points offered by the allocated processes. Human economies are very different and quite difficult to model on computer because of several characteristics of human decision making [9]. Human decisions are based on the diverse information from various media and this diversity can not be implemented on the computer. To cope up with this problem, we provided the option of manual setting of prices of the resources to reflect the mind of the resource providers.

4 Experimental Results The MU algorithm is implemented and tested on a Java based simulator called EcoGrid [7]. EcoGrid provides support for the creation of the cluster and grid as well as execution of the processes on it. EcoGrid provides an interface GridScheduler which is inherited in the classes which are defined for the scheduling algorithms. We have developed this grid simulator as a test-bed for grid scheduling algorithms that are based on dynamic load balancing. EcoGrid is dynamically configurable and supports simulation of the economy-based as well as non-economy based scheduling algorithms. 4.1 Architecture of EcoGrid The grid environment supported in EcoGrid contains various components required in the grid. The architecture of EcoGrid is shown in Fig. 2. Different components of EcoGrid are: Configuration Manager (CM), Random Number Generator (RNG), Load Generator (LG), Resource Calendar (RC), Computer Node (CN), Computer Cluster (CC), Media Directory (MD), Grid Process (GP), Grid (G), Grid Scheduler (GS),

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Statistical Analyzer (SA) and the Grid Data Provider (GDP). The DB & FS represents database and file system. Components of the EcoGrid are being described below: a) Configuration Manager (CM): The simulator is dynamically configurable. Configuration manager is responsible for dynamically configuring the grid simulator. Several methods have been included to read and update the values of the parameters. b) Random Number Generator (RNG): This component provides the methods for random number generation that are based on the various statistical distributions namely Poisson distribution, Exponential distribution, Normal distribution and Uniform distribution. c) Resource Calendar (RC): The resource calendar element of the simulator is used by the computer node to define its basic properties. It stores the details regarding the load, price, booking status, list of holidays of the time zone etc. for the resource. The load and price are having different values for weekdays and for holidays. d) Load Generator (LG): This module generates the processing load for the system. We can also configure the parameters of the load generator for varying work load situations. e) Computer Cluster (CC): The computer cluster is the collection of the computer nodes to represent the processing unit of the grid. cluster will publish its details in the media directory to facilitate the resource consumers. f) Grid Data Provider (GDP): This component is designed to separate the data access functionality from the core grid functionality. The class will be used to facilitate data access from various sources. Data can be stored in flat files, database software or XML files.

Fig. 2. Architecture of EcoGrid

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g) Statistical Analyzer (SA): The statistics generated by the system is analyzed by this component. This module provides the facility to perform statistical computations. h) Computer Node (CN): The basic resource in the grid is represented by the computer node component. This component consists of the hard disk, main memory and the processor. Based on the speed of the processor, a weight is assigned to the computer node, so that it can represent higher class of the processing unit as compare to the computer nodes with normal weight (=1). i) Media Directory (MD): As the name suggests, this component acts as the media service to store the details of the service providing clusters, which can be accessed by the resource consumers. It also provides resource matching algorithm to determine most suitable cluster and most suitable node. Media directory contains two databases: mediaFileProvider containing the details of the service providing cluster and the mediaFileProcess containing the details of the negotiated processes. j) Grid Process (GP): Grid process represents a task to be executed on grid. The arrival time for the process follows the Poisson distribution. The details required regarding the process are: execution time (executionTime), input data file size (inputFileSize), starting date (arrivalDate), deadline date (deadlineDate), deadline miss limit (deadlineMissLimit) budget, optimization factor (optimizationFactor) and negotiation factor for time & cost (timeNegotiationFactor & costNegotiationFactor). k) Grid Scheduler (GS): Grid scheduler represents the set of algorithms to schedule the processes on the clusters and the nodes. We have designed the Grid scheduler in such a manner that the users can dynamically plug their own scheduling algorithms into the system. l) Grid (G): The Grid represents a set of cluster to perform the task. It initializes the clusters, nodes in the cluster and the various resources on a node. 4.2 Experimental Setup and Analysis of Results We have evaluated MU algorithm through extensive simulations using synthetic as well as real workload traces. The real workload traces are taken from the Grid Workload Archive [5]. Iosup et al. created a generic workload format for the grid [6]. However, we have synthetically added few attributes to the workload traces as they do not contain several attributes required by economy based scheduling. Moreover, the synthetic workload is generated with the help of a load generator. This load generator generates the load using the suitable statistical distributions. A grid is created with five clusters and each cluster is having around fifty computing nodes. The workload is created to keep the nodes busy for 15 days. Total around 550 processes are created. These results are verified with the expected values. Fig. 3 and Fig. 4 show the comparison of the results. We observe that the computing nodes are getting the price demanded by them. The actual earning for some clusters is less than the expected earnings because there may be some slots remain vacant. The reason is the cost of that slot may be higher than the budget of any processes. As the grid is usually under full load condition, we verified the earnings from the price of working days and holidays

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between these fifteen days of simulation period. We kept different price of same node for different period to reflect the workload at different timestamp. Similarly, the consumers’ processes are getting the computing nodes on the cost that is less than their budget. The budget of the processes is uniformly distributed between the minimum and maximum possible price of execution of the process under this grid. The minimum price will be the price if the process is scheduled at the cheapest node in the grid. The maximum price is the cost of execution of the process at the highest price node. Moreover, the algorithm selects the computing node with minimum cost among the suitable computing nodes.

Fig. 3. Actual cost (AC) and budgeted cost (BC) for various processes

Fig. 4. Actual earning (AE) and expected earnings (EE) for computing nodes

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5 A Hierarchical Decentralized Scheduling Framework The grid computing environment contains a larger number of resources (may be thousands). The centralized scheduler is unable to scale up to the requirement of such a large number of resources. Deploying centralized scheduler in such environments will results into performance issues and can cause single point failure. In the hierarchical scheduler a central scheduler receive all requests and each node is having a local scheduler. However as the request is received by a single server, this environment again can be considered as a central scheduler. If we deploy decentralized scheduler than different nodes will interact with each other using message broadcasting resulting into the flooding of messages on the network [11]. The flooding may consume the available network bandwidth. To cope up with these problems a hierarchical decentralized scheduling framework is proposed for the implementation of the scheduling algorithm as depicted in Fig. 5. This framework can be utilized to avoid the scalability and single point failure issues in case of centralized scheduler and the message broadcasting issue of decentralized scheduler. In the proposed framework each cluster is having a master node that keeps track of its local nodes in the cluster. Each cluster is having backup option for its local scheduler so that the failures at local scheduler can be recovered. The message broadcasting will be limited between the master node level and the master node will respond to the message on behalf of the nodes in the cluster. Master Node

Cluster n

Cluster n-1

Cluster 1

Cluster 6

Cluster 5

Cluster 2 Cluster 3

Cluster 4

Fig. 5. A hierarchical decentralized framework for scheduler

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This approach is a tradeoff of the centralized and decentralized scheduling policy. The approach is generic and can be used to implement any scheduler to be implemented on the grid.

6 Conclusion In this paper, we have proposed an economy-based algorithm that tries to maximize utility value for both the resource providers and resource consumers. Proposed method uses market based tools to determine the utility value. These two features make the proposed method unique from the other similar methods. Simulations are conducted under synthetic and real workload traces to validate our method. The resource provider’s profit is inversely proportional to the loss factor. The resource consumer’s utility value is directly proportional to the net saving. From the results we conclude that using the maximum utility algorithm the computing nodes are getting the desired price. Moreover, the consumers’ processes are getting the computing nodes on the cost within their budgetary limit. A generalized hierarchical decentralized framework is also proposed for implementation of scheduling algorithms under grid computing.

References 1. Altmann, J., Routzounis, S.: Economic Modeling of Grid Services. In: e-Challenges 2006, Barcelona, Spain (2006) 2. Broberg, J., Venugopal, S., Buyya, R.: Market-oriented Grids and Utility Computing: The state-of-the-art and future directions. Journal of Grid Computing 6(3), 255–276 (2008) 3. Buyya, R., Abramson, D., Venugopal, S.: The Grid Economy. Journal of Proceedings of IEEE 93(3), 698–714 (2005) 4. Garg, S.K., Venugopal, S., Buyya, R.: Market-Oriented Meta-Scheduling for Utility Grid. In: 15th IEEE International Conference on High Performance Computing, HiPC, Bangalore, India (2008) 5. The Grid Workload Archive, http://gwa.ewi.tudelft.nl/pmwiki/ 6. Iosup, A., Li, H., Dumitrescu, C., Wolters, L., Epema, D.H.J.: The Grid Workload Format (2006), http://gwa.ewi.tudelft.nl/TheGridWorkloadFormat_v001.pdf 7. Mehta, H., Kanungo, P., Chandwani, M.: EcoGrid: a dynamically configurable object oriented simulation environment for economy-based grid scheduling algorithms. Under Communication 8. Patil, A., Power, D.A., Morrison, J.P.: Economy-Based Computing with WebCom. International Journal of Computer and Information Science and Engineering 1(1) (2007) 9. Waldspurger, C.A., Hogg, T., Huberman, B.A., Kephart, J.O., Stornetta, S.: Spawn: A Distributed Computational Economy. IEEE Transaction of Software Engineering 18(2), 103–177 (1992) 10. Xiao, L., Zhu, Y., Ni, L.M., Xu, Z.: Incentive-Based Scheduling for Market-Like Computational Grids. IEEE Transactions on Parallel and Distributed Systems 19(7) (2008) 11. Hamscher, V., Schwiegelshohn, U., Streit, A., Yahyapour, Y.: Evaluation of JobScheduling Strategies for Grid Computing. In: 1st IEEE/ACM International Workshop on Grid Computing, pp. 191–202 (2000)

An Accelerated MJPEG 2000 Encoder Using Compute Unified Device Architecture Datla Sanketh and Rajdeep Niyogi Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee {sankipec,rajdpfec}@iitr.ernet.in

Abstract. With the recent tremendous increase in Graphics Processing Unit's computing capability, using it as a co-processor of the CPU has become fundamental for achieving high overall throughput. Nvidia’s Compute Device Unified Architecture (CUDA) can greatly benefit single instruction multiple thread styled, computationally expensive programs. Video encoding, to an extent, is an excellent example of such an application which can see impressive performance gains from CUDA optimization. This paper presents a portable, fault-tolerant and a novel parallelized software implementation of Motion JPEG 2000 (MJPEG 2000) reference encoder using CUDA. Each major structural/computational unit of JPEG 2000 is discussed in CUDA framework and the results are provided wherever required. Our experimental results demonstrate that GPU based implementation works 49 times faster than the original implementation on the CPU. For the standard frame resolution of 2048 × 1080, this new fast encoder can encode up to 11 frames/second. Keywords: Graphics Processing Unit (GPU), Compute Unified Device Architecture (CUDA), Parallelization, Motion JPEG 2000, performance.

1 Introduction Many applications often require high quality video encoding and transmission. Even in modern desktop computers which are equipped with four cores, the time required to encode or transcode video is very high. Video encoding users, these days, often use higher end graphic cards, such as Nvidia’s GeForce 200 and 100 series. Graphical Processing Units (GPUs) have been originally developed for handling computations only on computer graphics. But recently, with the advent of CUDA technology, it is now possible to perform general-purpose computation on GPU [1]. Nvidia’s CUDA platform allures programmers with the promise of thousands of stream processors available in GPU capable of providing amazing parallel speedup returns that dominate the prospects of CPU cores countable on one hand. The lure of such incredible efficiency gains available on price-conscious customer-level hardware is certainly powerful. However, the actual act of coding for such architecture and obtaining the theoretical gains is a much less abstract exercise, especially when considering parallelizing existing applications for CUDA, even when they appear at first to be well suited for its paradigm. With both the real-world desire for faster video encoders and S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 34–45, 2010. © Springer-Verlag Berlin Heidelberg 2010

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the mystical-appearing power of CUDA in mind, we set out to explore the feasibility of converting a well-established video compression Program to Nvidia’s architecture. Our targeted application is the Motion JPEG 2000 reference encoder, provided freely by the JPEG Software Simulation Group. Motion JPEG 2000 [2] is one of the ISO standard video formats that was published in Part 3 of the JPEG 2000 [3] ISO standard. Because of its superior compression performance and support for easy editing of image content, It has proved to be a mastering video encoding format for digital cinema solutions. Each video frame in Motion JPEG 2000 is encoded as a JPEG 2000 data stream. JPEG 2000 supports both lossy and lossless compression and is superior to the existing standard, especially JPEG, in terms of subjective image quality and rate distortion with a number of additional features [4]. This standard adopts Embedded Block Coding with Optimized Truncation (EBCOT)[5] and Discrete Wavelet Transform(DWT)[6] as key algorithms. However, JPEG 2000’s computation load is greater than the DCT-based JPEG. The digital cinema application profile defines two standard resolutions of 2048 × 1080 and 4096 × 2160. To encode one of the lower resolution (2048 × 1080) video frames, it takes more than two seconds per frame on a current-generation PC. In this paper, we detail the experience of porting the motion JPEG 2000 reference encoder to the CUDA architecture. We applied the combined computational power of 3.2GHz Xeon X5482 (CPU) and GeForce GTX 280 (NVIDIA GPU) to the processing of Motion JPEG 2000. This paper is organized into 5 sections. The reminder of this paper is organized as follows. Section 2 briefs the related work on parallelization of MJPEG 2000 . In Section 3, we give an overview of our encoder system hardware, software and the communication overhead involved in it. In Section 4, we show the performance profiling results of our single thread base code. In Section 5, we show our parallelization techniques for different processes in JPEG 2K encoding. Section 6 shows the results of our parallelization and section 7 concludes the paper.

2 Related Research In [7], Meerwald et al. parallelized Jasper, a software based JPEG 2000 codec implementation [14] on shared memory multiprocessors using openMP. In [8], Muta et al. implemented MJPEG 2000 encoder on Cell/B.E-based cluster system, and described parallelization techniques at various system levels and its encoding performance.In [9], S. Kang and David A. Bader further optimized the computationally expensive algorithmic kernels of JPEG 2000 for the CELL/B.E and introduced a novel data decomposition scheme to achieve high performance. Using CUDA architecture, other video encoding algorithms like MPEG-4[10] and AVC/H.264 [11] were parallelized.

3 System Overview 3.1 Encoder Workload The JPEG 2000 encoder is composed of 4 processes: (1) DC level shift and ICT (Inter Component Transform) for lossless conversion, (2) Wavelet transform [6],

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(3) Quantization, which is necessary only for lossy conversion, and (4) EBCOT (Embedded Block Coding with Optimized Truncation) including bit modelling, arithmetic coding, and tag tree, as shown in Figure 1. Our program was executed in the lossless conversion mode, and therefore the quantization process was not needed. We have written the program from scratch in Matlab as per the standard JPEG 2000 specification. The output data stream of our program exactly matched the output from an existing implementation of a JPEG 2000 encoder. After that, we have identified which parts of the program were taking most of the execution time to optimize them. We have used the MEX files to perform computations on GPU using CUDA [19, 23]. MATLAB provides a script, called mex, to compile a MEX file to a shared object or dll that can be loaded and executed on GPUs.ïThe single threaded profiling results are shown in section 4.

Fig. 1. JPEG 2000 encoding process

3.2 Introduction to CUDA Hardware Architecture Each CUDA-compliant device is a set of multiprocessor cores (see Fig. 2), capable of executing a very high number of threads concurrently, and that operates as a coprocessor to the main CPU or host. In turn, each multiprocessor has SIMD architecture, that is, each processor of the multiprocessor executes a different thread but all the threads run the same instruction, operating on different data based on its thread Id, at any given clock cycle. The NVIDIA GTX 280 has thirty multiprocessors with eight processors each. Both the host and the device maintain their own DRAM, referred to as host memory and device memory (on-board memory). Device memory can be of three different types namely global memory, constant memory and texture memory. They all can be

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Fig. 2. CUDA Hardware model

read from or written to by the host and are persistent through the life of the application. Nevertheless, global, constant and texture memory spaces are optimized for different memory usages. Multiprocessors have on-chip memory that can be of the four following types: registers, shared memory, constant cache and texture cache (see Fig. 2). Each processor in a multiprocessor has one set of local 32-bit read-write registers per processor. A parallel data cache of shared memory is shared by all the processors. A read-only constant cache is shared by all the processors and speeds up reads from the constant memory. A read-only texture cache is shared by all multiprocessor and has one set of local 32-bit read-write registers per processor. A parallel data cache of shared memory is shared by all the processors. The local and global memory spaces are implemented as read-write regions of device memory and are not cached. The NVIDIA GTX 280 has 16,384 registers and 16 KB of shared memory per multiprocessor. The main drawback to CUDA performance is the cost of transferring data from host memory to device memory. All CUDA functions need to access and operate on device memory when running. This means that before CUDA code can execute, we need to transfer all the data to the device, and then, when the CUDA code is complete, you need to transfer it back.

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4 Single Threaded Profiling We used the matlab profiler to measure the relative times taken by each process block. Table 1 shows the results of the performance measurement when we encoded one of the digital cinema standard 2048 × 1080 video frames with our single thread encoder. Total time taken for JPEG 2K encoding: 4129 [ms]. Therefore, the time taken to encode 25 frames of size 2048 × 1080 is 103,225[ms] which corresponds to .242 frames/second. Our performance measurements show that EBCOT and wavelet transform are the computational expensive blocks. As the EBCOT process is split into Bit modelling, Arithmetic coding, and Tagtree building, we further did profiling inside the EBCOT to know the time consuming blocks. These results are shown in table 2. Table 1. Single Threaded Performance of JPEG 2000 on 3.2 GHz Xeon X5482 DC shift, ICT and Wavelet Transform 1164 [ms]

EBCOT

Others

2903 [ms]

62 [ms]

Table 2. Profiling of EBCOT Bit modeling

1771 [ms]

Arithmetic coding

871 [ms]

Tag tree building

261[ms]

In addition, the profiler also gives the time consumption ratio in detail that can list each function and the program execution time it used. After the above performance analysis, we have decided to port wavelet transform and, bit modeling and arithmetic coding in EBCOT on to the GPU and parallelize them.

5 Parallelization In Motion JPEG 2000 encoder, temporal information is not encoded, i.e. information from the previous frames is not encoded. Therefore, any number of frames can be processed in parallel. Further, the algorithm for JPEG 2000 encoding has a natural pipeline organization to it as each frame is sent through a series of stages that perform some computation on it. This design lent itself to a modular breakdown for CUDA analysis. For each of the major components, we did some analysis and implanted the kernels using CUDA.

An Accelerated MJPEG 2000 Encoder Using Compute Unified Device Architecture

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5.1 Wavelet Transform We group N video frames into one superblock (N= 30 in our case since GTX 80 has 30 multiprocessors) and these N frames will be processed in parallel (shown in figure 3(a)). For this purpose, we create N threads on the host which perform computations on these frames and further are responsible for communication of frame information between host (CPU) and device (GPU). The first step of encoding is a DC level shift transformation and inter- component transform (ICT). The DC level shift and ICT are pixel independent operations and hence can be fully parallelized using the GPU. For a video frame size of 2048 × 1080, we have used a tile size of 256 × 135 with an intention to get 8 × 8 tiles per video frame (as shown by the marked tile in Figure 3(a)). Each tile is mapped to a thread and each thread is given a two dimensional thread Id. Eight such tiles are grouped into one block and N such blocks per video frame are grouped into one kernel grid. Thus one block has information about one frame and one kernel grid has information about super block (which contains N frames). When the program on the host CPU invokes this kernel grid, the blocks of the grid are enumerated and distributed to multiprocessors. The multiprocessor further maps each thread in the block to one of the scalar processor cores (SP) on it, and each scalar thread executes independently with its own instruction address and register state. Each processor core process tiles which are cut from a source data frame as shown in Fig. 3. Each thread computes DC level shift and ICT on the tile followed by the wavelet transform operation. The tiling is done on the CPU and the wavelet transform of each tile is computed by one of the scalar processor cores on the GPU as shown in Fig. 3(b). The results are stored in the shared memory of the corresponding multiprocessor and are later copied to the main memory by the host thread. 5.2 EBCOT After the wavelet transform operation is completed on the whole super block, then EBCOT processing is performed on it. Embedded Block Coding with Optimized Truncation (EBCOT) involves bit modelling, arithmetic coding, and tag tree building. Both the bit modelling and the arithmetic coding are time consuming processes, as shown by the profiling results in Table 2. The results of the wavelet transform process are the sub-band parameter arrays of LL, HL, LH, and HH. EBCOT divides these sub-band parameter arrays into small code blocks and then does bit modelling and arithmetic coding for each code block. When all the code blocks for one of the four sub-bands have been completely processed, a tag tree is built from these compressed code blocks. Hence, arithmetic coding and bit modelling has to be completed before tag tree building is started. For each code block, we process the bit modelling and arithmetic coding in parallel by using multiple cores which are present on each multiprocessor on the device. For this, each code block is treated as a logical CUDA block and is given a two dimensional block Id. The threads inside this block perform bit modelling and arithmetic coding on the code block. We have grouped code blocks of one sub-band parameter array into one kernel grid and are scheduled to run on the device (GPU). When the CPU program invokes this kernel, the blocks of the grid are distributed to multiprocessors.

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Fig. 3. Parallelization of wavelet transform. (a) Tiling on CPU, (b) Wavelet transform of one tile computed on one of the stream processors on GPU.

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The multiprocessor schedules each thread inside the code block to one of its eight scalar processor cores (SP) with zero scheduling overhead. After the bit modelling and arithmetic coding for this code block is completed, it transfers the resultant output data stream to host’s main memory. Note that the multiprocessor is not idle at this time as it executes another block from the kernel grid as scheduled. When the host receives all the code blocks for a sub-band parameter array, it begins to build the tag

Fig. 4. Diagram showing the different states of host (CPU) and the device (GPU) at different times during EBCOT processing

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tree. Once the tagtree is built, the host divides the next sub-band parameter array into code blocks and the above procedure repeats for the remaining sub-band parameter arrays. When the tagtree is built for all the parameter arrays, the EBCOT processing is completed. In the above implementation, we found that the stream processors on the GPU were idle when the tagtree on the host is being built. To overcome this problem, we have slightly modified our approach. When the device is computing the bit modelling and arithmetic coding on code blocks of one parameter array, the host at the same time divides the next sub-band parameter array into code blocks (see Fig. 4). These are again grouped into one kernel grid. Once the host receives all the code blocks for one parameter array, it invokes this kernel which transfers the code blocks of the next parameter array to the device. The host now builds the tagtree for the parameter array for which compressed code blocks are received, while the device computes the bit modelling and the arithmetic encoding on the received code blocks. In this way the host and the device work in parallel. This approach was highly successful as the utilization of the device has increased and further speed up was achieved during EBCOT processing. The above procedure continues until the EBCOT processing for all the frames in the super block is computed. The whole process of DC level shift, ICT, Wavelet transform and EBCOT repeats with the next super block on N frames.

6 Results We developed all of the code from scratch as per the JPEG 2000 specification for effective parallelization. As described in above section, several parallelization techniques at various levels are proposed. The total time taken to encode 25 video frames of resolution 2048 × 1080 is 2097.25 [ms] which corresponds to 11.92 frames/second. Thus, the encoder works up to 49.22 times faster than the existing sequential one. The time taken to encode one frame is 83.89 [ms] .The time taken to encode different blocks is shown in Table 3. The performance comparison of wavelet transform, EBCOT and the overall encoding is shown in the figure 5.

Table 3. Parallel Performance of JPEG 2000 encoder on NVIDIA GTX 280(GPU) and 3.2 GHz Xeon X5482 (CPU)

DC shift, ICT and Wavelet Transform 29.46 [ms]

EBCOT

Others

35.42 [ms]

19 [ms]

An Accelerated MJPEG 2000 Encoder Using Compute Unified Device Architecture

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Execution time in ms CPU

CPU + GPU 4129

2903

1164 29.46 Wavelet transform

35.42 EBCOT

83.89 Overall Encoding

Fig. 5. Performance comparison of the parallelized version of JPEG 2000 with respect to the single threaded one

7 Conclusion In this paper, we presented our experience of porting JPEG 2000 and MJPEG 2000 on to CUDA architecture. We gave an overview of our encoder system hardware, software and the overhead involved in it. We analyzed the underlying parallelism in MJPEG 2000 and described our parallelization techniques at various frame levels, system levels, and discussed the results in detail wherever required. The bottleneck for CUDA programming lies in the user’s ability to strictly minimize any communication between host and device code. In many applications, such as our Motion JPEG 2000 encoder, this restriction can become highly burdensome, to the point that the original sequential version would require a complete rewrite for the CUDA framework. This is in order to realize performance improvements which lead to optimized results.

References 1. Owens, J.D., Luebke, D., Govindaraju, N., Harris, M., Kruger, J., Lefohn, A.E., Purcell, T.J.: A survey of general-purpose computation on graphics hardware. In: Eurographics 2005, State of the Art Reports, August 2005, pp. 21–51 (2005) 2. Information technology - JPEG 2000 image coding system - Part3: Motion JPEG 2000, ISO/IEC 15444-3 (2000) 3. Information technology - JPEG 2000 image coding system - Part1: Core coding system, ISO/IEC 15444-1 (2000)

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4. Christopoulos, C., Skodras, A., Ebrahimi, T.: The JPEG 2000 still image coding systemAn overview. Proc. IEEE Transactions on Consumer Electronics 46(4), 1103–1127 (2000) 5. Taubman, D.: High performance scalable image compression with EBCOT. IEEE Trans. Image Processing 9(7), 1158–1170 (2000) 6. Antonini, M., Barlaud, M.: Image coding using wavelet transform. IEEE Transactions on Image Processing 1(2), 205–220 (1992) 7. Meerwald, P., Norcen, R., Uhl, A.: Parallel JPEG 2000 image coding on multiprocessors. In: Proc. of Int’l. Parallel and Distributed Processing Symp., USA, April 2002, pp. 2–7 (2002) 8. Muta, H., Doi, M., Nakano, H., Mori., Y.: Multilevel parallelization on the Cell/B.E for a Motion JPEG 2000 encoding server. In: Proc. ACM Multimedia Conf. (ACM-MM 2007), Augsburg, Germany (September 2007) 9. Kang, S., Bader, D.A.: Optimizing JPEG 2000 Still Image Encoding on the Cell Broadband Engine. In: Proc. of 37th International Conference on Parallel Processing, pp. 83–90 (2000) 10. Dishant, A., Kumar, M.M., Mittal, A.: Frame based parallelization of MPEG-4 on Compute unified device architecture (CUDA). In: Proc. IEEE International Advance Computing Conference (2010) 11. Chen, W., Hang, H.: H.264/AVC motion estimation implementation on compute device unified architecture (CUDA). In: Proc. IEEE International conference on Multimedia and Expo. (2008) 12. Franco, J., Bernabe, G., Fernandez, J., Acacio, M.E.: A parallel implementation of the 2D wavelet transform using CUDA. In: Proc. Euromicro International Conference on Parallel, Distributed and Network-based processing, pp. 111–118 (2009) 13. Zhong, H., Lieberman, S.A., Mahlke, S.A.: Extending multi-core architectures to exploit hybrid parallelism in single-thread applications. In: International Symp. on HighPerformance Computer Architecture, Phoenix, Arizona (February 2007) 14. Michael, D.A., Kossentini, F.: JasPer-a software-based JPEG-2000 codec implementation. In: IEEE International Conference on Image Processing 2000, pp. 53–56 (2000) 15. Tenllado, C., Setoain, J., Prieto, M., Pinuel, L., Tirado, F.: Parallel Implementation of the 2D Discrete Wavelet Transform on Graphics Processing Units-Filter Bank versus Lifting. IEEE Transactions on Parallel and Distributed Sytems 19(2), 299–310 (2008) 16. Bernabe, G., Garcia, J.M., Gonzalez, J.: Reducing 3D Wavelet Transform Excecution Time Using Blocing and the Streaming SIMD Extensions. Journal of VLSI Signal Processing 41(2), 209–223 (2005) 17. Garcia, A., Shen, H.: GPU-Based 3D Wavelet Reconstruction with Tileboarding. The Visual Computer 21(8-10), 755–763 (2005) 18. Moreland, K., Angel, E.: The FFT on a GPU. In: Graphics Hardware, July 2003, pp. 112–119 (2003) 19. NVIDIA Corporation. Accelerating MATLAB with CUDA using MEX Files (September 2007) 20. Misra, D., Yang, Y.: Coarse-grained parallel algorithms for multi-dimensional wavelet transforms. J. Supercomputing 12(1-2), 99–118 (1998) 21. Lian, C.J., Chen, K.F., Chen, H., Chen, L.G.: Analysis and architecture design of blockcoding engine for EBCOT in JPEG 2000. IEEE Trans. Circuits and Systems 13(3), 219–230 (2003) 22. Burt, P.J., Anderson, H.: The Laplacian pyramid as a compact image code. IEEE Trans. Commun. 31(4), 532–540 (1983)

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23. NVIDIA Corporation. NVIDIA Compute Unified Device Architecture (CUDA) Programming Guide Version 2 (April 2009) 24. Parakh, N., Mittal, A., Niyogi, R.: Optimization of MPEG 2 Encoder on Cell B. E. Processor. In: IEEE International Advance Computing Conference, IACC 2009, March 6-7, pp. 423–427 (2009) 25. Lin, D., Xiaohuang, H., Nguyen, Q., Blackburn, J., Rodrigues, C., Huang, T., Do, M.N., Patel, S.J., Hwu, W.-M.W.: The parallelization of video processing I 26(6), 103–112 (2009)

Event-Based Metric for Computing System Complexity Sandeep Kumar Singh1, Sangeeta Sabharwal2, and J.P. Gupta1 1

Jaypee Institute of Information Technology, Noida, India Netaji Subhash Institute of Technology, Dwarka, India {sandeepk.singh,jp.gupta}@jiit.ac.in, [email protected]

2

Abstract. In order to increase quality and productivity of software, weaknesses must be identified in the software development process. Software metrics play a central role in identifying such weaknesses. High complexity of software is also one of the weaknesses. Identifying it in the early analysis stage can reduce cost, time and efforts. In this paper, a model-based approach is proposed to derive software metrics for measuring system complexity. The proposed metric measures the complexity of system on the basis of event flows and their interdependencies. Events taking place in the system are represented using Event Templates. An Event-Flow Model is then constructed from Event Templates and is represented as Event-Flow Graph. The proposed Event-Flow Complexity metric for analysis model is derived from Event-Flow Graph. The metric has also been evaluated in terms of Weyuker’s properties. Results of evaluation show that it satisfies 8 out of 9 Weyuker’s properties. Keywords: Events, Event Meta Model, Complexity metrics, Event based systems, Software engineering.

1 Introduction Complexity is an important attribute of any system. As the complexity of a system increases, it can lead to poor quality and becomes difficult to reengineer. High complexity in a system may also result in limited understandability, more errors, defects and exceptions, making it difficult to develop, test and maintain. For example, in software engineering, it has been found that program modules with high-complexity indices have a higher frequency of failures [1]. Also, life critical systems in which failure can result in the loss of human life require a unique approach to development, implementation and management. For these types of systems, typically found in healthcare applications [2], the consequences of failure are severe. Therefore, excessive complexity should be avoided. Thus measuring complexity of systems is a vital issue. Several technical soft-ware metrics have already been proposed to measure complexity for analysis model, design model, source code, testing and maintenance. Software complexity has been defined using different perspective by different authors. Author in [3] states that complexity is a characteristic of the software interface that influences the resources, another system will expend or commit, while interacting with the software. Authors in [4] define relative system complexity as the sum of S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 46–61, 2010. © Springer-Verlag Berlin Heidelberg 2010

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structural complexity and data complexity divided by the number of modules changed. Author in [5] defines complexity as the amount of resources required for a problem’s solution. This paper defines complexity of software system based on events. In any system, especially in real time systems, there is plethora of events happening. Event-Flows in a system give information about the behavior of a system. Analyst can use events effectively for requirement elicitation, validation and design of conceptual models based on events. Events have been used in past to generate DFD’s, ERD’s for structured analysis and also for identifying Use Cases in Object-oriented analysis (OOA) [6, 7, 8, 9, 10]. This paper uses Event-Flows and their interdependencies for deriving a metric to compute the complexity of software systems. In terms of an event, complexity is determined by number of events triggered from an event as well as number of events that are causative for an event. Events taking place in the system are represented using Event Templates. An Event-Flow Model is then constructed from Event Templates and is represented as Event-Flow Graph. The proposed Event-Flow Complexity metric for analysis model is derived from EventFlow Graph. The metric has also been evaluated in terms of Weyuker’s 9 properties and has been applied on a case study from a real time system. The organization of paper is as follows: Section 2 briefly discusses the related work in the software metrics and also briefly gives an event based approach of OOA of requirements. Section 3 discusses the proposed Event-Flow Model. Section 4 explains the entire process to derive software metric from the proposed Event-Flow Model. Section 5 shows the application of the proposed software metric on a case study from real time system and Section 6 describes the conclusion and the future work.

2 Related Work First step in software engineering begins with the creation of analysis model. This model is a foundation of design. Therefore, those metrics that provide insight into the quality of the analysis model are highly desirable. Relatively few analysis and specification metrics have appeared in the literature to predict the size of the resultant system. In the last 30 years, efforts have been made to capture the notions of software complexity. Most basic measure based on analysis of software code is count of the number of Lines of Code (LOC). Despite being widely criticized as a measure of complexity, it continues to have widespread popularity, mainly due to its simplicity [11]. Among others are Halstead’s measure [12], McCabe’s measure [13], the COCOMO model [14], and the Function-Point method [15]. In this paper, unlike the above approaches, a metric is proposed to measure the complexity of systems on the basis of event flows and their interdependencies. The proposed work integrates and expands the previous work on event based OOA of requirements [6, 7, 8]. These paper shows that Events can also be a starting point in OOA of requirements for generating class diagrams. In the earlier work [6, 7, 8], events have been defined as an occurrence at a specific time and place that can be described and recorded in the system. Three types of events have been considered as described in [10, 16] i.e. External or Data oriented events, Temporal or Time oriented events and State or Control oriented events. Elementary events are extracted and categorized as external, temporal or control events and formalized and documented in

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Event Templates [8]. An Event Template models every single interaction detail of events occurring in the system. Degree of the complexity of a system is defined on basis of event interdependencies among causative events and triggered events extracted from Event Templates. These interdependencies among events are captured in an Event-Flow Graphs using which, metric value is computed.

3 Proposed Event-Flow Model 3.1 Modeling Events In the event based OOA [6, 7, 8], events are modeled using Event Templates. A sample Event Template is shown in Table 1 and its details can be referred from [8]. In construction of Event-Flow Model, we have used two components of an Event Template (a) Causative Events and (b) Trigger Vector. Table 1. Event Template for event “Sensor 1 sense the package at start place” 1 2. 3. 4. 5. 6. 7. 8.

Event ID Event Name (verb phrase) Description

9. 10.

Initiator Facilitator Affecter Timestamp Causative Events (Preconditions) Inputs Trigger Vector

11.

Change-event

EA05 Sense package at the start place Sensor 1 sense the package at start place (State/Control Event) Sensor 1 Count n ALCS / Belt 1(Start place) Count n Package Count n TA1 EA01

Sensor 1 generate no-detect signal at start place Sensor 1 generate detect signal at start place Connection between Sensor 1 and Package

3.2 Modeling Event Interactions Using Event Operators Events in a system do not occur in isolation but as a chain of events. So, identification of an event in turn identifies other events. This relationship among events is described as Event-Flow Interdependency. Event- Flow Interdependency is captured from the Causative events and Trigger vector section of Event Templates. Event Interdependency is assigned a numerical value to indicate strength of dependency based on its complexity. This section presents description of modeling event interactions in Causative and Triggered events using event operators. (a)Causative events can be a single event or a set of events related using Event-join operators. We have defined three types of Event-join operators: (i) Event-or join (ii) Event-xor join (iii) Event-and join. An event following event-and join operator starts its execution when all its incoming events are executed. Irrespective of the fan-in (i.e. number of causative events), no decision making is involved to select causative events

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at event-and join operator. So, it is the most simple event interdependency and is assigned lowest interdependency strength. Strength given to event interdependency with event-and operator is 1. An event following event-or join operator starts its execution when a subset of its causative events are executed. One, more than one or all incoming events at event—or join operator can be causative. So, it is the most complex dependency and is assigned highest interdependency strength. Strength given to event interdependency with event-or join operator is 2F-1, where F is the fan-in (i.e. number of causative events). An event following event-xor join operator is executed as soon as exactly one of its causative events is executed. Exactly one of the incoming events at event-xor join operator can be causative. So, complexity of this interdependency lies between complexity of event-and join and event-or join operators. Strength given to event interdependency with event-xor join operator is F, where F is the fan-in (i.e. number of causative events). (b)Events triggered in a trigger vector are related with triggering event using Event-split operators. We have defined three types of event-split operators: (i) eventor split (ii) event-and split (iii) event-xor split. Event-and split indicate that all events have to be triggered in parallel. Irrespective of the fan-out (i.e. number of events in trigger vector), no decision making is involved at event-and split operator to select events to be triggered. So, it the most simple interdependency and is assigned lowest interdependency strength. Strength given to event interdependency with event-and split operator is 1. Event-or split indicates one, more than one or all events can be triggered at event-or split operator in the trigger vector. So, it the most complex interdependency and is assigned highest dependency strength. Strength given to event interdependency with event-or split operator is 2F-1, where F is the fan-out (i.e. number of events in a trigger vector). Event-xor split indicates exactly one event can be triggered at event-xor split operator. So, complexity of this dependency lies between complexity of event-and split and event-or split operators. Strength given to event interdependency with event-xor split is F, where F is the fan-out (i.e. number of events in a trigger vector). Fig 1 , depicts all the possible event flow interdependencies in a system. Simple Event Interdependency with and without negation as shown in Fig. 1(a) and Fig. 1(b) is a special case of Event-or and Event-xor with fan-out 1. Event-and split / join as shown in Fig. 1(e) and Fig. 1(f) is one of the possible cases of Event-or split / join respectively, when all events are triggered or when all are causative and hence given event interdependency value 1. Thus basic Event-Flow Interdependencies in a system are classified in three broad categories (a) Event-or split & join (b) Event-xor split & join (c) Event-and split & join with strength ranging from 1 to 2F-1, where F is the maximum of the number of causative events or events in a trigger vector whichever is higher. 3.3 Formal Definition of Event-Flow Model In any system, especially in real time systems, there is plethora of events happening, so event interdependency of all the events happening in the system is represented collectively using Event-Flow Model. In much the same way as a control-flow model represents all possible execution paths in a program [17] and a data-flow model represents all possible definitions and uses of a memory location [18] the Event-Flow

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Fig. 1. Basic Event-Flow Interdependencies in a system

Model represents all possible sequences of events that can be executed in a system. The event flow model contains two parts. The first part refers to events that are causes in terms of causative events and the second part refers to events that are triggered after an event has been executed. Both these parts play an important role in constructing Event-Flow Model. Our Event-Flow Model is represented as Event-Flow Graph.

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Event-Flow Graph represents events, their interaction in terms of causative events and trigger vector. It has one event designated as start event and another designated as exit event. Start event indicates the initialization of the system i.e. once a system is turned on all other events can get executed. Exit event indicates the completion of functionality. In Event-Flow graph, events are represented using circles, and dependencies between activities are represented using arrows. Our Event-Flow Graph is different from the one used in GUI testing [19,20]. Event-Flow Graph used in Graphical User Interface (GUI) testing represents all possible interactions among the events in a GUI component whereas our Event-Flow Graph depicts all possible event interdependencies among the interacting events of the system. Formally, Event-Flow Graph is defined as: An EFG is a 3-tuple where •

•

•

V is a nonempty finite set of vertices representing all the events in a system with two events designated as Start (S) and Exit (E) to indicate the system startup and exit events. T is a nonempty finite set of transitions. T ⊆ V * V . We say that event ei causes event ej iff ei is a causative event of ej. Similarly event ei triggers event ej iff event ei triggers event ej. An edge (vx,vy) ∈ T iff the events vx and vy are interdependent either due to causes or triggers relationship. C is a finite set of vertices representing connector nodes {OR , XOR, FORK, JOIN, NOT}

A connector node with more than one outgoing transition is classified as an Event-and split (fork), Event-or split, Event-xor split. A connector node with more than one incoming transitions is classified as an Event-and join (join), Event-or join and Eventxor join. OR and XOR-splits and joins are non-deterministic while AND-splits and joins are deterministic. In the Event-Flow Graph, Event-and split operator is represented with a ‘fork’, Event-and join operator is represented with a ‘join’, OR-split/join operator is represented with an ‘or’ and XOR-split/join operator is represented with a ‘xor’. The construction of the Event-Flow Graph is based on the identification of causative events and trigger vector of all event templates and hence the identification of causes and triggers relationships among events is essential. A set of causes and triggers relationship for each event is analyzed. These sets are then used to create the edges and vertexes of the Event-Flow Graph.

4 Generating Event-Flow Complexity Metric from Event-Flow Model This section explains the definition and measurement of Event-Flow Complexity metric. The metric is computed from Event-Flow Model using two Event Interdependency Matrices. In the end of the section, utility of Event-Flow Complexity metric is explained.

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4.1 Event Interdependency Matrices Complexity of an event is determined on basis of events that are triggered by it and the events that are causes for its occurrence. Dependencies extracted from the event templates by analysis of causative events and trigger vector are shown in a tabular form in Event interdependency matrices similar to ‘Dependency Structure Matrix’ (DSM) [21, 22, 23, 24, 25, 26]. We have chosen a matrix form as it can easily reflect the architecture of the system based on event interdependencies. Before explaining Event Interdependency Matrix, DSM is briefly described. Design Structure Matrix- also known as the dependency structure matrix, dependency source matrix, or dependency structure method is a square matrix that shows relationships between elements in a system. DSM has been used in [21, 22, 23, 24] for analysing software design tradeoffs, in the study of aspect-oriented modularization, modularity in architecture and managing complex software architecture. Our approach however, seems to be the first application of DSM for analyzing the event dependencies in event based systems. We have used Numerical DSMs (NDSM) in our approach that provides a detailed information on the relationships between the different system elements [36]. In our approach, two NDSM are constructed from the Event-Flow Graph namely Trigger events Matrix (Mtv) and Causative events Matrix (Mcv). Causative events matrix (Mcv) is an n-by-n matrix of order n where n represents the number of events in a system. It is a means of representing which events of a system are causative events for a given event. A non-diagonal entry aij in Mcv is the dependency value which indicate that event j is the causative event of event i. The value of aij corresponds to the strength assigned to the event interdependency that exist between events i and j, as discussed in section 2.3. Trigger events matrix (Mtv) is an n-by-n matrix of order n where n represents the number of events in a system. It is a means of representing which events of a system are triggered by a given event. A non-diagonal entry aij in Mtv is the dependency value which indicate that event j is the triggered event of event i. The value of aij corresponds to the strength assigned to the event interdependency that exist between events i and j, as discussed in section 2.3. The rows and columns in these NDSM are marked by event id of events (taken from Event Template) occurring in the system. Values in NDSM indicate the three possible types of event-flow interdependencies Event-or split & join, Event-xor split & join and Event-and split & join. These values are only assigned to differentiate among three types of event interdependency. A cell is assigned value of 1, in the Mtv and Mcv, if there is an ‘event-or split/ join’ relationship among two or more events either as causative events or as events in the trigger vector. A cell is assigned value of 2, in the Mtv and Mcv, if there is an ‘event-xor split/ join’ relationship among two or more events either as causative events or as events in the trigger vector. A cell is assigned value of 3, in the Mtv and Mcv, if there is an ‘event-and split/ join’ relationship among two or more events either as causative events or as events in the trigger vector.

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4.2 Computing Event-Flow Complexity Metric We propose following steps to compute Event-Flow Complexity metric of the system. 1. 2.

3.

Document all the events in the event templates as discussed in [6, 7, 8]. Draw Event-Flow Graph from Event Templates by using information from the causative events and trigger vector section of each template. Event-flow graph represents the interdependencies of events. Draw the Event Interdependency matrices (Trigger events Matrix and Causative events Matrix) from the event flow diagram and compute the system complexity from these matrices.

4.3 Definitions and Measurement of Event-Flow Complexity Metric Event-flow is determined by connector nodes in the Event-Flow Graph. These connector nodes are either splits or joins. Splits allow defining the possible events that are triggered from a given event. Joins express the synchronization of causative events at a specific point in the event flows to trigger events. We now introduce several definitions that will constitute the basis for computing the Event-Flow Complexity metric: Cumulative causative effect (Cce(i)): It is a combined effect of all event interdependencies on an ith event due to its causative events. Cce(i) of an event is computed from the interdependency strength of all causative events of an event in the Mcv. Three possible cases exist for Cce(i) calculation. When causative events are set of events through OR-join event operator as shown in Fig 1(g) in Event-Flow Graph and as indicated by strength value 1 in Mcv, value added to Cce is 2F -1, where F is the fan-in (i.e. number of causative events). When causative events are set of events through XOR-join event operator as shown in Fig 1(h) in Event-Flow Graph and as indicated by strength value 2 in Mcv, value added to Cce is F, where F is the fan-in (i.e. number of causative events). When causative events are set of events through AND-join event operator as shown in Fig 1(f) in Event-Flow Graph and as indicated by strength value 3 in Mcv, value added to Cce is 1. n

Cce(i) =

∑ [(2

no of cells (i , j) in a row of Mcv with 1 as value

− 1) + (no of cells (i , j) in a

i=0

row of Mcv with 2 as value) + ( no of cells (i , j) in a row of Mcv with 3 as value) 0 ] where n is the Total number of events in the system.

Cumulative trigger effect (Ctv(i)): It is the combined effect of all event interdependencies on an ith event due to events triggered by it. Ctv(i) of an event is computed from the dependency strength of all triggered events of an event in the Trigger event Matrix. Three possible cases exist for Ctv(i) calculation. When events are triggered from an event through OR event dependency as shown in Fig 1(d) in Event-Flow Graph and as indicated by strength value 1 in Mtv, value added to Ctv is is 2F -1, where F is the fan-out (i.e. number of events in trigger vector).

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When events are triggered from an event through XOR event operator as shown in Fig 1(c) in Event-Flow Graph and as indicated by strength value 2 in Mtv, value added to Ctv is F, where F is the fan-out (i.e. number of events in trigger vector). When events are triggered from an event through AND event dependency as shown in Fig 1(e) in Event-Flow Graph and as indicated by strength value 3 in Mtv, value added to Ctv is 1. n

Ctv(i) =

∑ [(2

no of cells (i , j) in a row of Mtv with 1 as value

− 1) + (no of cells (i , j) in a

i=0

row of Mtv with 2 as value) + ( no of cells (i , j) in a row of Mtv with 3 as value) 0 ] where n is the Total number of events in the system.

Complexity of an event: It is the arithmetic summation of cumulative causative effect (Cce) and cumulative trigger effect (Ctv) that all other events make on that event. n

Ce(k) =

∑ [Ctv(k) + Cce(k) ] where n is the Total number of events in the system. k =0

Complexity of a system: It is defined on the basis of event flows and interdependencies of all the events occurring in the system. Complexity of system is measured either as an absolute value or as relative value. Absolute complexity (Csystemabs): It is the summation of the event complexity of all events. n

Csystemabs =

∑ [ Ce(k) ] where n is the Total number of events in the system. k =0

Relative complexity (Csystemrel): It is the ratio of absolute complexity of the system to count of all types of event interdependencies. Csystemrel = Csystemabs / [Count of simple event interdependency + Count of Eventnot operator + Count of event- xor join operator + Count of event- or join operator + Count of event- and join operator + Count of event- xor split operator + Count of event- or split operator + Count of event- and split operator ] 4.4 Utility of Event-Flow Complexity Metric

Application and Utility of Event-Flow Complexity Metric is derived from the value of Csystemabs (P) and Csystemrel (P). Metric can be used to identify need to reengineer or redesign systems. A high complexity may be the sign of a brittle, nonflexible, or highrisk event flows. If high complexity is identified, the system may need to be redesigned to reduce its complexity. Redesign may involve breaking the event flows, reducing the event interdependencies or simplifying the way events are related to one another. Metric can also help analysts to identify need to improve event interdependencies, thus

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reducing the time spent in reading and understanding event-based systems, in order to remove faults or adapt them to changed requirements. The higher the value of Csystemabs (P) and Csystemrel (P), the more complex is Event-Flow of system due to more complex type of event interdependencies among events. A low value of Csystemabs (P) and Csystemrel (P) of a system or event-flow indicates a low complexity, so implementation of such event-flows represents low risk. Event-Flows of two system designs can be compared on the basis of absolute and relative complexity of systems in order to decide on the risk of their implementation. Events with a high complexity i.e. higher Ce value can be marked as the critical events. More focus can be given on testing such events or the paths in event-flow graph involving those events. Limits for the value of Csystemabs (P) and Csystemrel (P) can be decided on the basis of empirical results obtained after organizations successfully implement the proposed complexity metric as part of their development projects. We expect that limits for the proposed event-flow complexity metric will be obtained and set using empirical and practical results from research and from realworld implementation. In future, more metrics can be developed and Event-flow complexity metric can be used in conjunction with other metrics in order to increase the correctness of complexity analysis of a system. The actual complexity of implementing individual events can also be calculated and used in conjunction with Event-Flow Complexity metric. Design rules can also be framed to analyze and evaluate architecture of eventbased system on the basis of event-Flow Graph and the complexity value of the system calculated from the metric.

5 Application and Validation of Event-Based Complexity Metric This section describes application of steps to compute Event-Flow Complexity Metric on a case study. A Case study named ‘Automatic Production Environment (APE)’ on a real time system is taken from Real-Time Lab of Embry-Riddle Aeronautical University [27]. In this case study, after applying the proposed steps of Event based OOA as described in [6, 7, 8], we extracted 34 events along with their types. Some of these events are listed in the Table 2 below. Table 2. Some Events from APE Case Study User places package at the start place of the Belt 1 (External Event). User places package at the scanner place of the Belt 1 (External Event). User places package at the transition place of the Belt 2 (External Event). User places package at the end place of the Belt 2 (External Event). Sensor 1 sense the package at start place (State/Control Event)

5.1 Event Templates

All the events identified are documented in the proposed Event Templates [8]. Due to space constraint, Event Templates corresponding to two of the event listed in Table 2 are shown in Table 3 and Table 4.

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S.K. Singh, S. Sabharwal, and J.P. Gupta Table 3. Event Template for event “Sensor 1 sense the package at start place” 1 2.

9. 10.

Event ID Event Name (verb phrase) Description Initiator Facilitator Affecter Timestamp Causative Events (Preconditions) Inputs Trigger Vector

11.

Change-event

3. 4. 5. 6. 7. 8.

EA05 Sense package at the start place Sensor 1 sense the package at start place (State/Control Event) Sensor 1 Count ALCS / Belt 1(Start place) Count Package Count EA01 or Independent

Sensor 1 generate no-detect signal at start place Sensor 1 generate detect signal at start place Connection between Sensor 1 and Package

Table 4. Event Template for event “Sensor 1 generate no-detect signal at start place” 1 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

Event ID Event Name (verb phrase) Description Initiator Facilitator Affecter Timestamp Causative Events (Preconditions) Inputs Trigger Vector Change-event

EA06 Generate no-detect signal Sensor 1 generate no-detect signal at start place (State/Control Event) Sensor 1 Count ALCS / Belt 1(Start place) Count Signal Count EA05 Signal type NULL Connection between Sensor 1 and Signal

5.2 Event-Flow Graph

All the event templates are analysed and using information from the causative events and trigger vector section, an Event- Flow Graph is drawn as shown in Fig 2. 5.3 Event-Interdependency Matrix

Causative events and Trigger Vectors of every event are represented in the Causative events Matrix (Mcv) and Trigger events Matrix (Mtv) respectively. These matrices for APE Case Study are computed from the Event-Flow diagram (Fig 2) and Trigger Vector matrix is shown in Fig 3 whereas Causative Events matrix is shown in Fig 4. Value 0 in the matrix cell indicates there is no dependency between two events. Based on the formula for computation of various measures described earlier, value of cumulative causative effect and cumulative trigger effect of all other events on an event is calculated and is shown in Table 5. Result presented in Table 4 shows that basic

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Fig. 2. Event-Flow Graph of APE Case Study

Event-Flow Interdependency in a system ranges from 1 to 2F-1, where F is the number of causative events or events in a trigger vector based on the event operator used. Event with event id 0 is the most critical event as it has the highest event complexity value of 127. This event is the system startup event. Similarly, end event is also critical with event complexity i.e. 15. Event ids 5, 8, 11, 14 have next higher value of event complexity value of 3, all of which indicate event-xor spilt / join. Value of other event ids is either 1 or 2. Thus range of value lies between 1 to 127 (2F-1 where F is 7 in this case). 5.4 Validation of Event-Flow Complexity Metric

The proposed complexity measure is acceptable only when its usefulness has been proved by a validation process. Validation process increases the acceptance and confidence in the measurement. In existing literature, there are several proposals [28, 29, 30, 31] for validation process of complexity metrics. Among these, Weyuker’s properties [28] play an important role in validating software complexity measures. Weyuker’s properties have been suggested as a guiding tool in identification of a good and comprehensive complexity measure by several researchers [32,33,34,35]. They are a widely known formal analytical approach and so we have chosen them for analysis of our event-flow complexity metric. Weyuker proposed nine properties to evaluate complexity measure for traditional programming [28]. However, they are extensively used for evaluating object-oriented (OO) metrics. These properties lead to the definition of good notions of software complexity. For using these properties for validating

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Fig. 3. Trigger Event Matrix of APE Case Study

Fig. 4. Causative Event Matrix of APE Case Study

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Table 5. Table showing Ctv,Cce,Ce,Csystem values for APE Case Study Event id 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Ctv 127 1 1 1 1 2 0 1 2 0 1 2 0 1 2 1 1 1

Cce 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Ce 127 2 2 2 2 3 1 2 3 1 2 3 1 2 3 2 2 2

Event id Ctv Cce Ce 18 1 1 2 19 1 1 2 20 1 1 2 21 1 1 2 22 1 1 2 23 1 0 1 24 1 1 2 25 1 1 2 26 1 1 2 27 1 1 2 28 1 1 2 29 1 1 2 30 1 1 2 31 1 1 2 32 0 1 1 33 0 1 1 34 0 1 1 35 0 15 15 Csystemabs =207 Csystemrel =5.30

our proposed complexity metric, a system event-flow is considered as a basic unit instead of program bodies. Weyuker introduced the concatenation operation (P1;P2) of program blocks. Since our approach measures system complexity on the basis of events and their interdependencies, we have defined concatenation operation on event-flows of two systems (sub-systems). Results of validation show that out of 9 properties our proposed metric satisfies 8 properties hence the metric qualifies as good and comprehensive. Entire process of validation can not be shown in this paper due to space constraints.

6

Conclusion

Complexity is one of the important aspects of any system. In any system, specially in real time systems, there is plethora of events happening. These events play an important role to give information about the behavior of a system. This paper has shown that Event-Flow in a system also forms the basis for computing metrics to find the complexity of a system. A metric is proposed to measure the complexity of systems on the basis of Event-Flows and their interdependencies. The proposed work discusses the complexity of systems from an event-flow perspective. These interdependencies among events are captured in an Event-Flow Graphs using which, metric value is computed. The proposed metric has been theoretically validated in terms of Weyuker’s properties in order to guarantee that it qualifies as good and comprehensive. Since our complexity metric happens to fully satisfy eight of the Weyuker’s nine properties, it can be considered to have passed a significant part of the theoretical validation process. Therefore, it can be categorized as good, structured, and comprehensive. A control experiment is also under conduction to empirically validate the proposed metric. A prototype tool is also being

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developed to automatically (a) generate Event-Flow Graph and both the Event Interdependency Matrices (b) compute absolute and relative complexity of the entire system. In future, we are also working on framing design rules to analyze and evaluate the architecture of event based systems on the basis of event interdependencies. These design rules can then be applied to identify acceptable event interdependency.

References [1] Lanning, D.L., Khoshgoftaar, T.M.: Modeling the relationship between source code complexity and maintenance difficulty. Computer 27(9), 35–41 (1994) [2] Anyanwu, K., Sheth, A., Cardoso, J., Miller, J.A., Kochut, K.J.: Healthcare enterprise process development and integration. Journal of Research and Practice in Information Technology, Special Issue in Health Knowledge Management 35(2), 83–98 (2003) [3] Curtis, B.: Measurement and experimentation in software engineering. Proceedings of the IEEE 68(9), 1144–1157 (1980) [4] Card, D., Agresti, W.: Measuring software design complexity. Journal of Systems and Software 8, 185–197 (1988) [5] Fenton, N.: Software measurement: A necessary scientific basis. IEEE Transactions on Software Engineering 20(3), 199–206 (1994) [6] Singh, S.K., Sabharwal, S., Gupta, J.P.: Object Oriented Analysis using Event Patterns. In: Proceedings of International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CIS2E 2007), USA, pp. 438–442 (2007) [7] Singh, S.K., Sabharwal, S., Gupta, J.P.: Event Patterns for Object Oriented Requirement Analysis. In: Proceedings of IASTED International Conferences on Advances in Computer Science and Technology, Malaysia, pp. 115–120 (2008) [8] Singh, S.K., Sabharwal, S., Gupta, J.P.: Events - An Alternative to Use Case as Starting Point in Object-Oriented Analysis. In: Proceedings of ICETET, India, pp. 1004–1010 (2009) [9] McMenamin, S.M., Palmer, J.F.: Essential Systems Analysis. Prentice-Hall, Englewood Cliffs (1984) [10] Yourdon, E.: Modern structured analysis. Prentice-Hall, India (2003) [11] Azuma, M., Mole, D.: Software management practice and metrics in the European community and Japan: Some results of a survey. Journal of Systems and Software 26(1), 5–18 (1994) [12] Halstead, M.H.: Elements of software science, operating, and programming systems series, vol. 7, p. 128. Elsevier, Amsterdam (1977) [13] McCabe, T.J.: A complexity measure. Transactions on Software Engineering 13(10), 308–320 (1977) [14] Boehm, B.: Software engineering economics. Prentice Hall, Englewood Cliffs (1981) [15] Garmus, D., Herron, D.: Function point analysis: Measurement practices for successful software projects. Addison Wesley, Boston (2000) [16] Ward, P.T., Mellor, S.J.: Structured Development for Real-Time Systems. Essential Modeling Techniques, vol. 2. Prentice-Hall, Englewood Cliffs (1989) [17] Allen, F.E.: Control flow analysis. In: Proceedings of a Symposium on Compiler Optimization, pp. 1–19. ACM Press, New York (1970) [18] Rosen, B.K.: Data flow analysis for procedural languages. Journal of the ACM 26(2), 322–344 (1979)

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[19] Memon, A.M., Soffa, M.L., Pollack, M.E.: Coverage criteria for GUI testing. In: Proceedings of the 8th European Software Engineering Conference (ESEC) and 9th ACM SIGSOFT International Symposium on the Foundations of Software Engineering (FSE9), pp. 256–267. ACM Press, New York (2001) [20] Memon, A.M.: An event-flow model of GUI-based applications for testing. Software Testing, Verification and Reliability 17, 137–157 (2007) [21] Sullivan, K., Cai, Y., Hallen, B., Griswold, W.: The Structure and Value of Modularity in Software Design. In: Proceedings of the 8th European Software Engineering Conference held jointly with 9th ACM SIGSOFT International Symposium on Foundations of Software Engineering (2001) [22] Lopes, C.V., Bajracharya, S.: An Analysis of Modularity in Aspect-Oriented Design. In: Proc. Aspect-Oriented Software Development (AOSD 2005), Chicago (2005) [23] MacCormack, A., Rusnak, J., Baldwin, C.: Exploring the Structure of Complex Software Designs: An Empirical Study of Open Source and Proprietary Code. Harvard Business School Working Paper Number 05-016 [24] Sangal, N., Jordan, Ev., Sinha, V., Jackson, D.: Using Dependency Models to Manage Complex Software Architecture. In: Proceedings of the 20thACM/SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA), San Diego, CA (October 2005) ISBN 1-59593-031-0 [25] Browning, T.R.: Applying the Design Structure Matrix to System Decomposition and Integration Problems: A Review and New Directions. IEEE Transactions on Engineering Management 48(3), 292–306 (2001) [26] Browning, T.R., Eppinger, S.D.: Modeling Impacts of Process Architecture on Cost and Schedule Risk in Product Development. IEEE Transactions on Engineering Management 49(4), 428–442 (2002) [27] APE, http://www.rt.db.erau.edu/BLUE/02%20SE545_FA07_TEAM_BLUE_SRS _version2.pdf [28] Weyuker, E.J.: Evaluating software complexity measures. IEEE Transactions on Software Eng. 14(9), 1357–1365 (1988) [29] Mouchawrab, S., Briand, L.C., Labiche, Y.: A Measurement Framework for ObjectOriented Software Testability. Information and Software Technology 47, 979–997 (2005) [30] Poels, G., Dedene, G.: Distance-based Software Measurement: Necessary and Sufficient Properties for Software Measures. Information and Software Technology 42(1), 35–46 (2000) [31] Stockhome, S.G., Todd, A.R., Robinson, G.A.: A Framework for Software Quality Measurement. IEEE Journal on Selected Areas in Communications 8(2), 224–233 (1990) [32] Misra, S.: Weyuker’s Properties, Language Independency and Object Oriented Metric. In: Gervasi, O., Taniar, D., Murgante, B., Laganà, A., Mun, Y., Gavrilova, M.L. (eds.) Computational Science and Its Applications – ICCSA 2009. LNCS, vol. 5593, pp. 70–81. Springer, Heidelberg (2009) [33] Misra, S., Akman, I.: Applicability of Weyuker’s Properties on OO Metrics: Some Misunderstandings. ComSIS 5(1) (2008) [34] Misra, S., Akman, I.: Weighted Class Complexity: A Measure of Complexity for Object Oriented Systems. Journal of Information Science and Engineering 24, 1689–1708 (2008) [35] Misra, S., Akman, I.: Applicability of Weyuker’s Properties on OO Metrics: Some Misunderstandings. Journal of Computer and Information Sciences 15(1), 17–24 (2008) [36] Design Structure Matrix, http://www.dsmweb.org

Load Balancing in Xen Virtual Machine Monitor Gaurav Somani1 and Sanjay Chaudhary2 1 2

Laxmi Niwas Mittal Institute of Information Technology, Jaipur, India Dhirubhai Ambani Institute of Information & Communication Technology, Gandhinagar, India

Abstract. Global load balancing across all the available physical processors is an important characteristic of a virtual machine scheduler. Xen’s Simple Earliest Deadline First Scheduler (SEDF) serves the purpose for interactive applications and low latency applications. SEDF scheduler can not be used in multiprocessor environments due to unavailability of load balancing. This paper investigates requirement of this feature and discusses algorithmic design and implementation of an user space load balancing program. Experiment results show a balance among number of physical processors with better utilization of resources in multiprocessor systems. Keywords: Virtualization, Xen, Virtual machine scheduling and Global load balancing.

1

Introduction

Modern data centers host diﬀerent applications ranging from web servers, database servers and high performance computing nodes to simple user desktops. Virtual Machine based data center implementation provides numerous advantages like resource isolation, hardware utilization, security and easy management. The concept of virtualizing resources is old [16] but it is gaining popularity after the term on-demand computing or cloud computing arose. Virtual Machine Monitor (VMM) or hyper-visor is a piece of software which manages these virtual machines. Data centers which host these virtual machines on their physical machines follow Service Level Agreements (SLAs), which speciﬁes the service requirements with diﬀerent constraints and parameters to be fulﬁlled by service providers or cloud providers[4]. Running more virtual machines on a single physical machine results into better hardware utilization. Xen is a popular open source virtual machine monitor. Credit scheduler in Xen uses weight and cap values to allocate CPU time. Simple Earliest Deadline First Scheduler (SEDF) gives time period and a slice to every virtual machine. Credit scheduler uses a global load balancing feature[5] in which every runnable VCPU will get a physical CPU if there is one. SEDF scheduler gives comparatively fair scheduling for interactive applications than credit scheduler [17]. SEDF scheduler does not have feature to dynamically balance the load among the physical server. This paper investigates the need of this kind of feature and proposes an implementation of Global Load Balancing S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 62–70, 2010. c Springer-Verlag Berlin Heidelberg 2010

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(GLB) algorithm. Section 2 describes Xen virtual machine monitor architecture. Section 3 elaborates scheduling internals in Xen and its two schedulers. Requirements, design and implementation of the new algorithm are discussed in section 4. Experiments and results are discussed in section 5. Related work, conclusion and future work have been given in last consecutive sections.

2

Virtual Machine Scheduling

Virtualization is mostly targeted towards wide-spread x86 architectures. Xen uses paravirtualization strategy to create virtual machines and run operating systems on it [2]. Guest Operating systems running on top of Xen are known as domains in Xen’s terminology. Xen designates host operating system (domain 0) as isolated driver domain (IDD) to provide device driver support to guest operating systems. In Xen architecture the device drivers in host operating system will serve all co hosted guest operating systems. Guest Domain, also known as domainU can access drivers via back end drivers provided by domain 0. Scheduling in Xen has ported some concepts from operating systems. Virtual machine scheduling is compared with process scheduling in [6]. An Operating system kernel that provides an N:M threading library schedules N threads (typically one per physical context) which a user space library multiplexes into M user space threads [6]. In Xen, kernel threads are analogous to VCPUs (Virtual Central Processing Unit) and the user space threads represent processes within the domain. in Xen system, there can even be another tier, because the guest domains can also be running user space threads in it. So there comes a role of three tiers of schedulers [6]. 1. User space threads to kernel threads in guest. 2. Guest kernel mapping threads to VCPU. 3. VMM mapping VCPUs to Physical CPUs (PCPUs). The hypervisor scheduler, sitting at the bottom of this three tier architecture, needs to be predictable. The layers above it will make assumption on the behavior of the underlying scheduling, and will make the decisions. So the Xen’s scheduler is one of the the most important part for achieving overall performance(Figure 1). 2.1

Simple Earliest Deadline First Scheduler (SEDF)

SEDF scheduler is an extension to the classical Earliest Deadline First (EDF) scheduler. This scheduler provides weighted CPU sharing in an intuitive way and uses real-time algorithms to ensure time guarantees. It is a soft real time scheduler which operates on the deadlines of the domains. Applications with least deadline will be scheduled ﬁrst to meet their goals on time. Xen operates on SEDF scheduler with two parameters decided by system administrator i.e. Time Period Pk and Time slice Sk , k designates a task in total number of tasks which is n. So each and every runnable domain will run for at least Sk time in a period of Pk time. So this kind of scheduler will give soft real time guarantees

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Fig. 1. Virtual Machine Scheduling in Xen [6]

to domains. Soft real time schedulers are those in which some of the tasks can tolerate the lateness or a deadline miss. SEDF maintains a per CPU queue to schedule domains according to their deadlines [5][15]. The deadline of each domain is calculated by the time at which the domain’s period is ending. SEDF is a preemptive scheduler whose fairness is decided by the parameters chosen by user. SEDF can be a good choice for the application with latency intensive tasks. Domains which host an I/O intensive application require very less CPU time but that time is critical in such applications [20]. It is a preemptive policy in which tasks are prioritized in reverse order of impending deadlines. The task with the highest priority is that one that is run. If we assume that the deadlines of our tasks occur at the ends of their periods, although it is not required by EDF [13]. Given a system of n independent periodic tasks, all the tasks will meet their deadlines if and only if n Sk U (n) = ≤1 (1) Pk k=1

That is, EDF can guarantee that all deadlines are met if total CPU utilization is not more that 100%. If above condition does not meet then one or more tasks will miss their deadlines. To understand above equation we will take an example : Consider 3 periodic processes scheduled using EDF. Below are the required time slices in given period of time is given for all the three tasks. Scheduler should be able to provide at least Sk time to task k in each time period Pk . 1. P1 =8 and S1 =1. 2. P2 =5 and S2 =2. 3. P3 =10 and S3 =4. Here the value of U (utilization) will be 4 1 2 = 0.925 ≤ 1 U (n) = + + 8 5 10

(2)

So in above set of task, a schedule can be made to meet all the deadlines. Xen’s SEDF scheduler can be used in both Work Conserving (WC) and Non-work Conserving(NWC) modes. In work conserving mode, shares are guaranteed. The tasks in work conserving mode can use idle CPU if they are runnable. CPUs will

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not become idle if there is some runnable task in the system. So if there is only one task and all other tasks are idle or blocking than that single task can consume the whole CPU. On the other hand a task in a scheduler in NWC mode will not be given a share other than its share even if CPU is free. Xen provides these two modes in both of the current schedulers. Credit scheduler use “cap” values to choose between those two modes. SEDF scheduler has a extra time option to allow a VM to use extra time. By enabling this ﬁeld a domain is able to get extra CPU time other than its slice if physical CPU is idle. SEDF scheduler has a serious drawback when it is used for multiprocessor systems. It can not do load balancing among processors for the available VCPUs. It just maintains per physical CPU queues and schedule the queues on individual processors. Xen’s credit scheduler provides a great advantage of global load balancing among the number of physical CPUs available. If there is any runnable VCPU in the system than it will get a CPU if one is available. In other way, there will be no idle CPU if any runnable VCPU is there. It provides a great advantage to choose Credit as a scheduler. On the other hand Xen’s SEDF scheduler provides per CPU queues, so it does not support Global Load Balancing. Manual pinning can be done to ﬁx a VCPU on a physical CPU (PCPU). The multicore or multiprocessor hardware is important target for virtualization due to their more CPU capacity to share within a virtualization environment. A Global Load Balancing strategy like Credit scheduler, re-assigns VCPUs to dynamically balance the load among available CPUs. A good example is given in [5]. Let us consider a 2-CPU machine. By assigning equal weights and a single VCPU to each of the three VMs, one would expect to get around 66.6% of the total CPU per VM. However it can only be achieved when the scheduler has Global Load Balancing features. When we use same conﬁguration on server running under SEDF scheduler, it will assign all the VMs to the ﬁrst processor. SEDF maintains per CPU queues, so each VM will be getting only 33.3% share on average of the ﬁrst CPU and it results into Maximum 50% utilization of the whole system. The other CPU will not be used at all. If we deﬁne aﬃnity rules by pinning mechanism provided by Xen. Then we will have at most 100%, 50% and 50% shares respectively for these three VMs.

3

Requirement of Global Load Balancing

Some points in favor of requirements of load balancing. 1. SEDF’s present allocation If there is a dual CPU system (There are two CPUs, CPU0 and CPU1) with ﬁve VCPUs to run. Domain 0 has two VCPUs and domain 1 has three VCPUs. SEDF assigns VCPU0 and VCPU1 of domain 0 to CPU0 and in case of domain 1, VCPU0 and VCPU1 are assigned to CPU0 and VCPU2 will be assigned to CPU1. So if there are 2 VCPUs in a VM it will assign both the VCPUs to the 0th processor. Any VM having 4 VCPUs will only able to get a single VCPU on 1st processor. This allocation is quite static and imbalanced in nature.

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2. Why VCPU balancing and why not domain balancing? VCPUs are ﬁner abstractions for the hypervisor scheduler to allocate CPU. A domain can only be assigned using deﬁning aﬃnity or mapping rules between its each VCPU and physical processors or PCPUs. We use the pinning mechanism provided by Xen hypervisor to achieve Global Load Balancing among available physical CPUs. Pinning a VCPU assigns it to a particular CPU. Xen gives a facility to assign CPU aﬃnity by using virsh interface of libvirt virtualization library. Before the algorithm start working, the utilization of each VCPU is calculated using the command line interface given by xm vcpulist. xm gives the total elapsed time for each VCPU on a CPU at any instance of time. This elapsed time E0 is noted as initial elapsed time for each VCPU. Again, after time=T the reading ET is taken for each VCPU. The utilization of each VCPU will be calculated as. U (V CP U ) =

3.1

ET − E0 T

(3)

Description

Based upon equation 3, we propose an algorithm for load balancing strategy. Equation 3 gives utilization of each VCPU in time duration T. This utilization is the basis for sorting the VCPUs in decreasing order. Modiﬁed Worst Fit Bin packing algorithm is used to assure the balancing [11][19]. Bin packing algorithm is a classical problem to ﬁll n number of objects of size ci (real value between 0 and 1) into minimum number of bins of unit size. Its goal is to pack a collection of objects into the minimum number of ﬁxed sized “bins”. Our aim is slightly diﬀerent from this algorithm, Global Load Balancing aims to balance the load among the number of available processors. Number of bins (PCPUs) is Npcpus and the sum of sizes of all the objects is also less than the sum of bin capacities. That can be achieved by Worst Fit Bin Packing algorithm by ﬁlling largest elements in emptiest bins or processors in the present case [11][19]. Formally, we can deﬁne the problem as follows. If the number of VCPUs is Nvcpus with Utilization Ui , where i=1 to Nvcpus . There are Npcpus available with capacity 100 each and their present utilization denoted by U Pj , where j=1 to Npcpus . The aim is to place total VCPUs among all the PCPUs available such that, Utilization U Pj , where j=1 to Npcpus , is almost similar for all the available Npcpus with all the Nvcpus placed. The overall ﬂow can be seen in example given in Figure 2. Here, Npcpus =2 and Nvcpus =5. According to their mapping and utilization Ui , where i=1 to 5, the utilization of PCPUs is U P1 =93% and U P2 =25%. In the next step, the whole VCPU list has been sorted in decreasing order with respect to utilization. In the ﬁnal stage when the new mapping has been applied using algorithm shown in 3.2, the balanced utilization will be U P1 =60% and U P2 =58%. The algorithm shown in section 3.2 uses current VCPU mapping as input in the form of a matrix. The total number of rows in this input mapping matrix A will

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Fig. 2. Global Load Balancing Flow

be equal to the number of VCPUs available in the system. Each row of this matrix will corresponds to a mapping like “domain-VCPU-CPU”’. Forth coloumn of each matrix will be the Utilization Ui , where i=1 to Nvcpus . This matrix will be sorted in the order of decreased utilization. A new mapping will be recorded using worst case bin packing algorithm to ﬁll all the physical processors. The output matrix B will contain the ﬁnal mapping to be applied to balance the load. 3.2

Algorithm

OBJECTIVEThis algorithm assigns the number of VCPUs among number of physical processors to balance the total load. INPUTNo. of PCPUs : N_pcpus No. of VCPUs : N_vcpus Affinity Matrix : A(4 x N_vcpus) matrix. First three columns corresponds to the mapping of a domain’s VCPU to a PCPU. Fourth column corresponds to the utilization. OUTPUTBalanced Affinity matrix : B(3 x N_vcpus) matrix. Each row corresponds to the new mapping of a domain’s VCPU to a PCPU. ALGORITHM [GLOBAL-LOAD-BALANCE] 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12)

Sort the matrix A with Utilization in decreasing order for each row in A do Pick the VCPU in order of Utilization Create a new mapping by adding this VCPU to the emptiest PCPU Add this mapping in matrix B done for each row in B do Apply the new mapping done Return Balanced Affinity matrix B

END [GLOBAL-LOAD-BALANCE]

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4

Experiments and Results

The description given in previous section is elaborated version of the algorithm in section 3.2. The algorithm has been implemented as a user space program in C with use of shell and awk scripts to process utilization data. To show the eﬃciency of the Global Load Balancing algorithm, experiment shown in Figure 3 was conducted. There are four virtual machines with 1 VCPU each. All VMs started running a CPU intensive program at time t=0. This CPU intensive program comprises integer and ﬂoating point instruction in an inﬁnite loop. The physical machine has two processors. SEDF will assign all these VCPUs on processor 0 by default. Each domain will be able to complete the whole execution of the CPU test program in around 237 seconds. The ﬁrst plot in Figure 3 shows the behavior of SEDF. In the next plot, we started with the same conditions. At time t=10 seconds, we triggered our Global Load Balancing algorithm. The test duration parameter T was set to 5 seconds. After calculating the utilization’s and getting the ﬁnal mapping and applying them took around 5 seconds. After that the overall utilization of the whole system raised up to 100%. The increase in each VMs utilization is also increased by double due to the Global Load Balancing on two processors. The total time taken by these VMs to complete the test was reduced to 135 seconds only.

Fig. 3. Experiment : Global Load Balancing Activity

4.1

Load Balancing Parameters

1. Time duration for the tests : It purely depends upon the utilization data of each VCPUs. Figure 3 shows that it reacts in few seconds after gathering data. The above graph shows the activity with T= 5 seconds. 2. When to run? : It can be run any time and as soon as possible after VMs has been started. Running it as a daemon and checking for current balancing after each ﬁxed interval of some seconds and changing the essential mapping is useful in getting continuous balancing.

Load Balancing in Xen Virtual Machine Monitor

5

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Related Work

Global Load balancing among number of nodes in a distributed computing environment has been seen in [3][8][10]. Distributed shared memry architecture and load balancing among peers have been analysed in [1][12]. Load balancing of tasks in a multiprocessor environment is done in [14][9]. Load balancing among number of physical servers is implemented in virtualization environment with migration support in [7][18]. Virtualization environment are diﬀerent from native architecture due to their three tier scheduling features discussed in section(2) and [6]. Global Load balancing of virtual processors among number of physical processors on a physical machine is done in credit scheduler of Xen virtual machine monitor. Our work automates the aﬃnity rules for the VCPUs among number of PCPUs using proposed Global Load Balancing (GLB) algorithm.

6

Conclusion and Future Work

A novel approach has been proposed and developed to facilitate balancing VCPUs according to their utilization among the available physical processors. The algorithm supports Global load balancing for Xen’s SEDF scheduler. The experiment results shows a performance and utilization increase of physical machine and running domains.The developed program for the global load balancing for the SEDF scheduler provides a crucial way to implement the load balancing among the physical processors and dynamic aﬃnity gives higher utilization. Load balancing strategy can be extended by getting utilization at more ﬁne time scales with the analysis of multiprocessor scheduling in guest operating system and use of predictive models.

References 1. Ahrens, J.P., Hansen, C.D.: Cost eﬂective data-parallel load balancing. Technical Report 95-04-02, University of Washington (1995) 2. Barham, P., Dragovic, B., Fraser, K., Hand, S., Harris, T., Ho, A., Neugebauer, R., Pratt, I., Warﬁeld, A.: Xen and the art of virtualization. In: SOSP 2003: Proceedings of the nineteenth ACM symposium on Operating systems principles, pp. 164–177. ACM, New York (2003) 3. Biagioni, E.S., Prins, J.F.: Scan directed load balancing for highly parallel meshconnected parallel computers. Unstructured Scientiﬁc Computation on Scalable Multiprocessors 10, 371–395 (1990) 4. Chen, Y., Iyer, S., Liu, X., Milojicic, D., Sahai, A.: Translating Service Level Objectives to lower level policies for multi-tier services. Cluster Computing 11(3), 299–311 (2008) 5. Cherkasova, L., Gupta, D., Vahdat, A.: Comparison of the three CPU schedulers in Xen. SIGMETRICS Perform. Eval. Rev. 35(2), 42–51 (2007) 6. Chisnall, D.: The Deﬁnitive Guide to the Xen Hypervisor. Prentice Hall Open Source Software Development Series. Prentice Hall PTR, Upper Saddle River, NJ, USA (2007)

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7. Padala, P., et al.: Automated Control of Multiple Virtualized Resources. Technical Report HPL-2008-123R1, HP Laboratories (2008) 8. Gates, K.E., Peterson, W.P.: A technical description of some parallel computers. International Journal High Speed Computing 6(3), 399–449 (1994) 9. Hajek, B.E.: Performance of global load balancing of local adjustment. IEEE Transactions on Information Theory 36(6), 1398–1414 (1990) 10. Hwang, K.: Advanced Computer Architecture: Parallelism, Scalability, Programmability. MIT Press and McGraw-Hill Inc. (1993) 11. Johnson, D.S.: Fast algorithms for Bin packing. Journal of Computer and System Sciences 8, 256–278 (1974) 12. Lenoski, D.E., Weber, W.D.: Scale Shared Memory Multiprocessing. Morgan Kaufmann Publishers Inc., San Francisco (1995) 13. Lin, B., Dinda, P.A.: VSched: Mixing Batch And Interactive Virtual Machines Using Periodic Real-time Scheduling. In: SC 2005: Proceedings of the 2005 ACM/IEEE conference on Supercomputing, Washington, DC, USA, p. 8. IEEE Computer Society, Los Alamitos (2005) 14. Nicol, D.M.: Communication eﬃcient global load balancing. In: Proceedings of the Scalable High Performance Computing Conference, April 1992, pp. 292–299 (1992) 15. Ongaro, D., Cox, A.L., Rixner, S.: Scheduling I/O in virtual machine monitors. In: VEE 2008: Proceedings of the fourth ACM SIGPLAN/SIGOPS international conference on Virtual execution environments, pp. 1–10. ACM, New York (2008) 16. Popek, G.J., Goldberg, R.P.: Formal requirements for virtualizable third generation architectures. Commun. ACM 17(7), 412–421 (1974) 17. Somani, G., Chaudhary, S.: Application performance isolation in virtualization. In: International Conference on Cloud Computing, pp. 41–48. IEEE, Los Alamitos (2009) 18. VMware. VMware Infrastructure: Resource Management with VMware DRS. Technical report (2008) 19. Weisstein, E.W.: Bin-Packing Problem, From MathWorld–A Wolfram Web Resource, http://mathworld.wolfram.com/Bin-PackingProblem.html 20. A Xen wiki page. Scheduling-PrgmrWiki, book.xen.prgmr.com/mediawiki/index.php/Scheduling

Aerial Vehicle Based Sensing Framework for Structural Health Monitoring Ashish Tanwer, Muzahid Hussain, and Parminder Singh Reel Electronics and Communication Engineering Department Thapar University, Patiala – 147001, India {Ashishtanwer,parminder.reel}@gmail.com, [email protected]

Abstract. A novel approach to implement wireless active sensing framework for Structural Health Monitoring is presented using an Unmanned Aerial Vehicle as a Mobile Agent. This approach has unique features of critical activity detection, wireless power delivery and measurement and data collection options from the sensor nodes through Zigbee. The active sensing is initiated by wirelessly triggering the sensor node from UAV. UAV provides unrestricted accessibility in various applications for SHM. It carries Beagle Board payload for real-time calculations to check the health of structures. The onboard video camera provides improved analysis of Critical activities like abnormal vibration and structure tilt. It captures video of the area of interest and data measured by any sensor node network. This paper is intended to give sufficient details of the implementation of our approach. Keywords: Structural Health Monitoring, Wireless Sensing Framework, Wireless Energy Transmission, Mobile Agent, UAV, Mulle Platform.

1 Introduction Structural health monitoring (SHM) is the process of detecting damages in civil, military, aerospace structures such as bridges, buildings, aerial vehicles, oil and water tanks etc. before it reaches critical stage. It is a field of public interest aiming to improve the safety and reliability of costly infrastructure by detecting damage at early stage of its evolution. Wireless Sensor Networks (WSN) are employed for monitoring process of these structures in which the dynamic response of the deployed sensors are measured and damage sensitive features of the signals are analyzed. WSN provide an agile and effective solution over the convectional wired sensors system in terms of multipath transfer, distributive computing and lack of extensive wiring for every individual sensor node. However, wireless sensor nodes have energy constraints which require periodic replacement of battery in sensor nodes. In order to overcome these constraints, an energy harvesting system such as that of use of solar cells in sensor node is developed. Wireless sensor nodes having energy harvesting feature are already been developed for SHM applications [1] [2]. In an alternative approach, mobile agent is used for wireless powering and triggering of sensor nodes on as needed basis [3]. This approach involves the use of an unmanned S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 71–83, 2010. © Springer-Verlag Berlin Heidelberg 2010

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mobile agent which collaborates the concept of wireless energy transmission along with the distant monitoring platform. The previous work in this context includes a lot of theoretical investigations but a hardheaded demonstration of mobile agent based approach is done. The use of the Unmanned Ground Robot (UGV) as a mobile agent node is proposed but it severely restricts the application of mobile agent in the remote areas like huge buildings, containers and military structures [4]. In this paper, a new approach of using UAV as mobile agent node is presented and implemented. The UAV here is a mobile WSN member providing wireless power delivery and data collection options from the sensor nodes. The UAV node provides a radio-frequency (RF) signal to the receiving antenna of the sensor node that has been deployed on the structure. The sensors measure the desired response at critical areas on the structure and transmit the signal back to the mobile-agent again via the wireless communication.

2 Previous Work WSN have been thoroughly inquired for the structural health monitoring applications. The current wireless sensing system used for SHM varies from decentralized processing hopping protocol based sensors system to that of mobile based sensing networks. Various researchers have proposed collaborating robots/UAVs as mobile agents in WSN. Tong [3] and Tirta [5] did a significant work in this regard. Tong investigated the use of mobile sensor node for executing computational activities and come to the conclusion that the energy required by an ad-hoc network exponentially increases as the density of the deployment of WSNs increases. Tirta proposed the concept of mobile agent as data collector which collects the data from the local data storage nodes in the group of various small subnets. A very few illustrations of mobile agent based WSN used for SHM are found. Esser [6], Huston [7] and Ma [8] have proposed their research dealing with the use of mobile agents for inspecting structural integrity as well as performing power line inspections respectively. The hardheaded demonstration of the mobile based WSN used for structural health monitoring rarely exists. The use of unmanned ground robot as mobile agent in WSNs for providing wireless energy transmission and data collection have been thoroughly investigated and practically demonstrated in the work of Taylor [4]. However, to the author best knowledge, the use of UAV as mobile agent and its field demonstrations does not exist up to this date.

3 System Architecture The system used for SHM is 3-tier architecture consisting of WSN, UAV as mobile agent and the base station. There are 4 mode of communication between Mobile Agent, WSN and UAV as follow: Mode I: Data Communication between Gateway Node of WSN and UAV for data transfer through Zigbee (IEEE 802.15.4) @ 2.4 GHz.

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Mode II: Data Communication between UAV and Base station at RF of 1.2 GHz Mode III: RC Control of UAV from the Base Station Mode IV: Energy Transfer from UAV to Sensor nodes by reflector grid antenna of 5.8 GHz

Mobile Agent (UAV)

Wireless Data Transfer @ 1.2 Ghz

Wireless Energy Transfer

Zigbee Communication

Gateway RC Control

Base Station

Sensor Network

Fig. 1. Tier Architecture of SHM System

4 Wireless Sensor Network-Tier I Performance of WSN is primarily dependent on the performance of sensor node.SHM through WSN is critical task. For SHM the sensor node must have following characteristics: • Long range communication (range>100m) so that less number of sensor node can cover whole structure. • Low power consumption so that the battery replacement period is large • Wireless power transfer to remote nodes in case batteries are down • High precision 3- degree accelerometers • High data rate communication protocols like IEEE 802.15.4 Zigbee standard • Large data storing capacity on sensor nodes like ROM or flash memory • Time stamp. The system should be capable to time stamp events in real time A number of commercial wireless sensor platforms are capable to perform SHM. For testing, improved Mulle Platform, an open-source wireless sensor platform was adopted. Mulle EIS (Embedded Internet System) is based on the Renesas M16C/62P

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CPU having Core clock frequency of 24 MHz. The size of the Mulle platform is only 26 x 24 x 5 mm3. The Mulle platform is a complete standalone sensor node aimed at adhoc sensor. It has 10-bit A/D Converter consisting of 26 channels for sensor interface. The node has 3-axis accelerometer ADXLxxx (v5.2) with. Zigbee range 150 m. This enables the same sister nodes to be used on 10/100 m. The platform is equipped with AT86RF230, a low-power 2.4 GHz transceiver specially designed for IEEE 802.15.4, ZigBee and 6LoWPAN applications and high data rate 2.4 GHz ISM band applications. Node battery is single Lishen Lithium polymer (25x25 x 5 mm) rechargeable battery with life of 2 years and capacity of 130 mAh.

Renesas M16C/62P

ZigBee Module

Main Connector

Fig. 2. Mulle Embedded Internet System

The operating system running on sensor nodes is TinyOS. Renesas M16C/62P CPU has 31K CPU RAM, 384K CPU Flash and 2 MB serial flash (sufficient for TinyOS and data storage). Piezoelectric (PZT) sensors along with the impedance convertor chip of AD5933 is used .The change in the mechanical impedance shows the degree of damage done in the structure which is measured by the PZT sensor. The equivalent electric impedance signal is converted into digital signal by AD5933 chip embedded on the node which further fed its digitalized output to the microprocessor of the node. Each sensor node records data into local flash memory. Bonjour Service Discovery Protocol and Mulle Public Server (MPS) are used for application level communication. Mulle has open Application Programming Interface (API) in the C programming language that simplifies code reuse and improves performance. All programming work is done in nesC (subset of C) using GCC compiler. Table 1. Overview of Mulle Architecture Purpose Processor Tran-receiver Sensors Battery OS Programming

Component Renesas M16C/62P @ 24 MHz AT86RF230 @ 2.4 GHz for IEEE 802.15.4, Zigbee, 6LoWPAN 3-axis accelerometer (ADXLxxx), Piezoelectric Sensor with AD5933 Impedance chip Lishen Lithium polymer (25x25x5 mm) rechargeable battery TinyOS nesC using GCC Compiler

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The Mulle power Management Architecture (PMA) consists of a number of components that allow the Mulle to monitor and control its power supply. Various power saving modes adopted are • Passive mode: Transceiver on in listening mode. MCU is in stop mode and unused components are powered down in order to conserve energy. • Active mode: Mulle initiates outgoing connections. Once a connection is established, the Mulle starts to stream sensor data to a user or database server. The power consumption usually depends on the specific type of sensor(s) attached to the Mulle • Time-synchronous mode: Combines the two previous modes using an activation schedule, is a form of distributed duty-cycling and allows the Mulle to conserve a considerate amount of energy. The activation schedule can be modified dynamically, and allows users to make trade-offs between system life-time and end to-end delay. The Mulle spends most of its time, typically 95-99 %, in sleep mode where it consumes less than 10μW. Periodically it wakes up to either: listen for incoming connections or establish its own outgoing connections. The energy consumption is calculated as:

E =T ×(Psleep+ facq × Eacq + fcon× Econ)

(1)

where Psleep is Power Consumption while sleeping, Eacq is Energy Consumption while acquiring data, Econ is Energy Consumption for a connection, facq Frequency of acquisition, and fcon is Frequency of connection. An implementation of the wireless energy transfer system using mobile agent has been demonstrated. The system is designed in such a way that sensor nodes accept the wireless energy from the UAV (mobile agent). The energy received from the rectenna at receiver end is fed to a 0.1 F capacitor for storage shown in Fig 3. There is a provision of voltage trigger switch which provides regulated voltage to the processor. The sensor node acquires the data from accelerometer and piezo-electric sensors when triggered by UAV.

Fig. 3. Working Diagram of Sensor Node

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When the data from the sensors has been acquired, sensor node sends back this data to the computational load of the UAV with the help of its on-board Zigbee module. The mobile agent then stores the data, move to the next node if required performing the similar operation and send the stored data back to the base station.

5 The Mobile Agent (UAV)-Tier II The mobile-agent used for testing purpose is RC (radio controlled) unmanned aerial vehicle (UAV). The UAV weighs approximately 8 kg and carries components needed to implement the mobile-agent based SHM process as shown in Fig 4. Payloads are RC receiver for motion control, High frequency Radiator to make Nodes harness energy, Zigbee receiver for WSN access, Data transmitter unit, Seagull Telemetry system and EagleTree GPS. Data transmitter unit operates 500 mW, 1.2 GHz and delivers data received from WSN to the base station. 5.8 GHz reflector grid antenna for energy transmission

Wireless antenna

Data Recorder, Data Transmitter, GPS Receiver, Camera

Fig. 4. UAV developed at Thapar University in assistance of DRDO

5.1 Telemetry System The payloads seagull telemetry system has 3 main components: Seagull dashboard telemetry receiver with USB interface (displays telemetry data and sounds alarms when problems occur), onboard data recorder (collects and logs the data/sessions) and onboard telemetry transmitter (sends the data from the recorder to the dashboard).

Fig. 5. Dashboard, data recorder and GPS expander

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The basic building blocks of Video Transmitter unit are Modulator, Oscillator, Multiplier and RF Amplifier.

Fig. 6. Block Diagram of Video Transmitting Unit

5.2 Beagle Board Payload Beagle Board payload provides wireless interface platform with 2.4 GHz Zigbee devices through a dynamic mapping framework. It communicates and downloads data from Gateway Sensor Node through Zigbee link. Beagle board has POP Processor TI OMAP3530 (600MHz ARM Cortex-A8 core, HD capable' TMS320C64x+ core (75MHz up to 720p @30fps), Imagination Technologies PowerVR SGX 2D/3D graphics processor, 256MB LPDDR RAM memory and 256MB NAND Flash memory. Angstrom Linux is installed on SD/MMC card which boots from NAND memory. Zigbee USB Dongle is attached to Beagle Board via USB hug plugged in Enhanced Host Controller Interface (EHCI) port [Refer Fig 7].

Fig. 7. Interfacing of Beagle Board’s EHCI port with USB hub and Zigbee Bluetooth Dongle

5.3 Wireless Energy Transfer A Mobile Agent based wireless energy transmission to the sensor nodes is one of the major challenging problem since microwave transmission is always associated with some sort of attenuation which is governed by the Friis equation, all symbols having their usual meaning:

PR =

GTG Rλ2 PT (4π R )2

(2)

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Mobile agent acts as data storage and processing unit, transmits energy to the node when needed and triggers it for data extraction from the nodes. An antenna with rectification circuit called rectenna is used which have the capability to provide an efficiency up to 80% for DC conversion. An antenna at the receiver end captures the transmitted microwave energy and converts it into DC power with the help of rectifying circuit used and finally stored it in a storage medium (capacitors/battery). From the experiments, it was concluded that grid antenna of 5.8 GHz was used as transmitting antenna and rectenna was used at receiver end. Table 2 shows the power requirements of a sensor node when the circuit is operated on 3.3 V. Table 2. Power Requirements of Sensor Node Sensor Node Component Renesas M16C/62P Processor AT86RF230 Trans-receiver AD5933 Impedance chip

Voltage (V) 3.3 3.3 3.3 Total

Current (mA) 14 16.5 15 45.5

Power (mW) 46.2 54.45 49.5 150.15

6 The Base Station-Tier III The radio controller used here is Futaba 6ex-pcm model kit. It works on 72 MHz frequency. The kit consists of the transmitter T6exap, receiver 136hp and servos s3004 and s3151. T6exap transmits in both FM (PPM) and PCM by selecting modulation/cycling. It requires receiver of proper modulation. The LCD on the face of the compact transmitter enables easy reading and allows rapid data input. The system also holds independent memories for six different models. It has landing gear, trainer cord and buddy box capabilities. It also includes servo reversing, dual rates, exponentials and programmable mixing.

Fig. 8. Futuba Transmitter

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6.1 Video Receiver Video Receiver is used to receive the video signals transmitted by transmitter place in the aircraft. It works at 1.2GHz frequency. When the critical activity is detected by any of the sensor node the on board video camera captures the detailed pictures of the critical area and GPS locates the location of that area and return back these data to base station.

Fig. 9. Block Diagram of Video Receiver

The block diagram of typical video receiver is shown above. It is super- heterodyne receiver. It is less prone to noise and gives better quality of images. The different blocks of video receiver are: 1. Antenna: High gain directional 1.2GHz patch antenna is used to receive signal transmitted by the video transmitter placed in the aircraft. 2. RF Amplifier: It is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically for driving the antenna of a transmitter. It is usually optimized to have high efficiency, high output Power (P1dB) compression, good return loss on the input and output, good gain, and optimum heat dissipation. It receives the low power signal from the antenna and selects the desired frequency and amplifies it. It gives at the output frequency component fs. 3. Mixer: Mixer is a nonlinear or time-varying circuit or device that accepts as its input two different frequencies and produces four frequencies at the output fo, fs, fo- fs, fo+fs out of these four frequency fo- fs is the desired one and is fed to the IF amplifier. 4. Local Oscillator: A local oscillator is an electronic device used to generate a signal normally for the purpose of converting a signal of interest to a different frequency using a mixer. This process of frequency conversion also referred to as heterodyning, produces the sum and difference frequencies of the frequency of the local oscillator and frequency of the input signal of interest. These are the beat frequencies. Normally the beat frequency is associated with the lower sideband, the difference between the two. The frequency component produced by it is denoted by fo. The local oscillator frequency is always greater than signal frequency. 5. IF Amplifier: It selects the intermediate frequency from the mixer output and amplifies it. The IF frequency used here is 480MHz. It removes the image frequency i.e. improves the image frequency rejection. It plays very important role in removing noise or unwanted signal from the received signal.

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6. Demodulator: Demodulation is the act of extracting the original informationbearing signal from a modulated carrier wave. A demodulator is an electronic circuit used to recover the information content from the modulated carrier wave. It receives the signal from the IF amplifier and demodulates it i.e. converts the modulated signal into the original signal and fed it to the modulating amplifier. 7. Amplifier: It amplifies the weak demodulated signal received from the demodulator. It provides enough strength to the signal that it can be derive USB video card effectively. The USB video input to the laptop is used for further processing (such as object detection). 6.2 Computing Platform The base station consists of laptop computer running windows XP. The SHM software is installed on this computer to make a real-time assessment on the structural Condition. Data received from the sensor node via Zigbee attached to Beagle Board is send to the base station. The UAV trigger the sensor node wirelessly using a low Frequency RF triggering antenna installed on the side of the vehicle.

7 Simulation Results The planning of WSN implant and positioning of sensor nodes for the proper functioning of WSN and optimization planning are done with WSN simulator. The sensor nodes are shown as yellow dots, gateway nodes as red dots and sinks as small receiver towers.

Fig. 10. WSN Analysis with WSNSim

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The simulation and optimization of WSN is done by Prowler, a MATLAB based Probabilistic Wireless Network Simulator is used to simulate the communication scheme: local OS services including the network protocol stack, and also the radio transmission phenomena (signal power vs. distance, fading, collision, disturbances). The figure shows results radio-channel simulation of span tree application on Prowler GUI.

Fig. 11. Simulation results of WSN on Prowler

The critical activity detection of a structure is done by measuring the vibrations for different buildings in the mentioned places (mentioned in the table 3) for the frequency range 1-80 Hz. The values in the block represent critical ones for a vibration of a building. Table 3. Intermittent vibrations values of a building

Place Residences Offices Critical areas

Intermittent vibrations(m/s2 ) .0072 .0063 .0013 .013 .0036 .0028

.0058 .014 .009

.030 .021 .0031

Table 4 and 5 shows the maximum values of impedance measured from various sensor sub-networks integrated on the bridge. Table 5 reveals the damage identified in the structure.

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Table 4. Impedance (Max) Values –No Damage

Sensor sub-nets

S1 S2 S3

Impedance(max)

1356.04 1319.80 1322.30

Table 5. Impedance (max) values-damage identified Sensor sub-nets

A1 A2 A3

Impedance(max)

1340.3 2234.67 1234.8

8 Conclusion The work of this paper represents the first hardheaded demonstration of using an Unmanned Aerial Vehicle (UAV) as a mobile agent for WSN in SHM applications. It is so designed to overcome the limitations of existing mobile agent based sensing techniques in WSN based SHM applications. The system developed consists of a group of structural monitoring sensors, wireless sensor nodes and an AUV mobile agent which delivers the wireless energy for the node for active sensing. The system measures the structure monitoring parameters like mechanical strain to analyze the degree of on effectiveness of the structure. UAV is capable of associating itself with any node and wirelessly collects the data from the node. The performance of the system has been verified. This work gives the feasibility and applicability of UAV in WSNs based applications. The future work may includes the development of power receiving efficient sensors system improving the efficiency of wireless energy delivery and further investigate the methods of developing the agility of WSNs using mobile agent based approach. The work should also be done on investigating the applications of UAV based WSNs in emergency situations like earthquakes, terrorist attacks etc.

References 1. Mascarenas, D.L., Todd, M.D., Park, G., Farrar, C.R.: A miniaturized electromechanical impedance-based node for the wireless interrogation of structural health. In: Proceedings of SPIE -Health Monitoring and Smart Non-destructive Evaluation of Structural and Biological Systems (March 2006) 2. Pakzad, S., Kim, S., Fenves, G., Glaser, S., Culler, D., Demmel, J.: Multi-purpose wireless accelerometers for civil infrastructure monitoring. In: Proceedings of the 5th International Workshop on Structural Health Monitoring (2005) 3. Tong, L., Zhao, Q., Adireddy, S.: Sensor networks with mobile agents. MILCOM 1, 688– 693 (2003) 4. Taylor, S.G., Farinholt, K.M., Flynn, E.B., Figueiredo, E., Mascarenas, D.L., Moro, E.A., Park, G., Todd, M.D., Farrar, C.R.: A mobile-agent based wireless sensing network for structural monitoring applications. LA-UR-08-06545, Material Science and Technology Material Science and Technology (accepted for publication) 5. Tirta, Y., Li, Z., Lu, Y.-H., Bagchi, S.: Efficient collection of sensor data in remote fields using mobile collectors. In: Proc. 13th Int. Conf. Comput. Commun. Networks, October 2004, pp. 515–519 (2004)

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6. Esser, B., Pelczarski, N., Huston, D.: Wireless inductive robotic inspection of structures. In: Proc. IASTED Int. Conf. Robot. Appl., Honolulu, HI, August 14-16 (2000) 7. Huston, D., Esser, B., Gaida, G., Arms, S., Townsend, C., Chase, S.B., Aktan, A.E. (eds.): Wireless inspection of structures aided by robots. In: Proc. SPIE Health Monitoring and Management of Civil Infrastructure Syst., August 2001, vol. 4337, pp. 147–154 (2001) 8. Ma, L., Chen, Y.: Aerial Surveillance system for overhead power line inspection. Center for Self-Organizing and Intelligent Systems (CSOIS), Utah State Univ., Logan, Tech. Rep. USU-CSOIS-TR-04-08 (September 2000)

A Cross Layer Seamless Handover Scheme in IEEE 802.11p Based Vehicular Networks Arun Prakash1 , Sarsij Tripathi1 , Rajesh Verma1 , Neeraj Tyagi1 , Rajeev Tripathi1 , and Kshirasagar Naik2 1

Motilal Nehru National Institute of Technology, Allahabad-211004, India 2 University of Waterloo, Waterloo-N2L 3G1, Canada [email protected]

Abstract. In this paper, we propose a seamless handover scheme for Network Mobility (NEMO) in vehicular scenario assisted by IEEE 802.11p based ad hoc communications among vehicles. The proposed scheme reduces handover latency and minimizes packet loss during handover by utilizing cross layer information available from other vehicles in the ad hoc manner. The role of neighboring vehicles assistance to the handover vehicle is twofold. First is to get the router advertisement of the next access point in advance to actual handover, resulting in considerable reduction in handover latency. Second is to receive packets destined for handover vehicle, thus minimizing packet loss during handover period. The extensive simulation study reveals that the proposed handover scheme provides seamless network mobility handover in vehicular communication scenario. Keywords: 802.11p, Cross layer, handover, NEMO, VANET.

1

Introduction

As a prospective Intelligent Transportation Sysyem (ITS) technology, Vehicular Ad hoc Networks (VANETs) have recently been attracting an increasing attraction from both research and industry communities[1]. Other than the unique characteristics of VANETs, the popularity of Global Positioning System (GPS) and availability of traﬃc data make it suitable for a wide range of ITS applications. ITS applications ranges from collision warning, hazardous location warning, lane change warning to electronic toll collection, multimedia downloading, and map downloading[2]. These applications demand both Vehicle-to-Vehicle (V2V) communications and Vehicle-to-Infrastructure (V2I) communications. The motivation stems from recent advances in the area of ITS with the advent of Dedicated Short Range Communications (DSRC)[3], which is designed to support high speed, low latency V2V and V2I communications using IEEE 802.11p standard[4]. VANETs involve both V2V and V2I communications. In V2V, direct or multihop communications take place between vehicles. It has advantage of short range bandwidth and ad hoc nature. IEEE 802.11p is an extension of IEEE 802.11 for S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 84–95, 2010. c Springer-Verlag Berlin Heidelberg 2010

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V2V communications being developed by IEEE working group. V2I involves communications between vehicles and infrastructure, e.g. an Access Point (AP) connected with Internet can be used for Internet connectivity of vehicles. In a V2I communication scenario, some ITS applications rely mostly on infrastructure based communications and mandate Internet access in vehicles[2,5]. In this scenario, the IETF NEMO working group proposed NEMO Basic Support Protocol (NEMO BS)[6] for mobility management of mobile networks. By introducing an entity named Mobile Router (MR), NEMO BS enabled mobile networks preserve communication with other nodes while changing the point of attachment to the Internet. However, multihop communication is not supported in NEMO BS as it is designed for mobile networks (vehicles) having direct communication link with an AP. MRs in vehicles may form VANETs. To guarantee the consistent reachability to Internet from vehicles via both direct (single hop) and indirect links (multihop), it is necessary to integrate VANETs with NEMO, referred to as VANEMO[7]. VANEMO allows to achieve V2V and V2I communications simultaneously[8]. One of the important components of mobility management is handover management. It aims to maintain the active connections when a mobile network changes its point of attachment. From vehicular perspective, the two most important requirements for handover management are as follows[9,10]: 1. Seamless connectivity should be assured regardless of vehicle’s location and speed. 2. Fast handover is needed for delay sensitive ITS applications. The vehicles in the ad hoc region can communicate with each other and with the infrastructure (AP). Thus the vehicles can assist the vehicle which is undergoing handover process in reducing handover latency as well as in minimizing packet loss during handover period. In this paper, we propose a Cross layer Seamless Handover Scheme (CSHS ) in IEEE 802.11p based Vehicular Networks that is based on cross layer information from PHY and MAC with the assistance of other vehicles in the ad hoc region. The rest of the paper is organized as follows: Section 2 discusses the related work on NEMO handover. Section 3 presents the system model and Section 4 describes the proposed handover scheme. Section 5 presents a comparative performance evaluation with NEMO BS and, ﬁnally, Section 6 concludes the paper.

2

Related Work

There are several proposals in literature that address NEMO handover and claim to reduce the latency and packet loss due to handover[11,12,13,14,15]. However, to the best of our knowledge, no previous works have used VANET, namely the communication among vehicles using ad hoc infrastructure based on IEEE 802.11p, to assist NEMO handover (that is, network layer handover in VANEMO model). Chiu et al.[16] present a vehicle-aided cross layer design for fast handover support in VANETs by using WiMAX Mobile Multihop Relay (MMR) technique.

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The proposed scheme provides an interaction between PHY and MAC layer and uses inter-vehicle communications to reduce the handover delay. The proposed scheme uses WiMAX MMR as a framework and allows some pubic transportation vehicles to act as Relay Vehicles (RVs) to provide Internet access to passenger vehicles. However, the standard handover procedure of MMR WiMAX suﬀers long delay (about 11 seconds) due to the lack of information about next RV. Even after applying the proposed Vehicular Fast Handover Scheme (VFHS), the handover latency is reduced by about 75 %. Whereas, in the case of using NEMO BS as framework to provide Internet access, the standard handover procedure takes about 1 second. The handover scheme developed in this paper uses NEMO BS as framework and provides seamless handover by further reducing handover latency and minimizing packet loss.

3

System Model for Proposed Handover Scheme (CSHS )

In this section, we present a system model for VANEMO scenario and explain diﬀerent priority levels that we introduced in to 802.11p MAC to assist NEMO handover. To demonstrate the eﬀectiveness of the proposed handover scheme, we take a simple highway scenario as shown in Fig. 2. The typical VANEMO scenario is a vehicular network with the vehicles moving on two-lane highway, i.e. all the vehicles in each lane move in same direction. All vehicles are equipped with a MR that has three interfaces and all interfaces are conﬁgured with diﬀerent radio channels and radio frequency to prevent interference[17]: 1. One egress interface to support infrastructure communications (NEMO interface). 2. One egress interface to form ad hoc network among vehicles (Ad-hoc interface). 3. One ingress interface for delivering data to the nodes inside a vehicle (In-vehicle interface). The nodes inside a vehicle communicate with the nodes in the ﬁxed infrastructure using NEMO BS (NEMO route). The nodes inside a vehicle communicate with the nodes inside another vehicle using ad hoc communications (Ad hoc route), and they can communicate up to 1000 m in single hop using 802.11p protocol. Moreover, each and every vehicle is equipped with GPS facility. GPS data is used to know the relative position and distance of other vehicles within the ad hoc region. For demonstrating our handover case scenario, we consider the vehicles moving from left to right direction, i.e. the upper lane of the road in Fig. 1. The circular areas represent the coverage range of AP1 and AP2 respectively, and the oval area represents the ad hoc communication range. Vehicles VA through VH are connected with AP1 and vehicles VG through VM are in the coverage range of AP2. The dotted arrow represents a threshold value that is set to initiate the procedure (as explained below) that a vehicle has to complete before actual handover starts, and the solid arrow represents the actual handover point.

CSHS in Vehicular Networks CN

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AR

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V B V D V F VH VA VC VE

VI VL VG VJ VK VM

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Fig. 1. System model for handover in VANEMO scenario

As soon as vehicle VH (which is connected with AP1 and receiving packets from the Correspondent Node (CN)) reaches its threshold value, it initiates two processes to reduce handover latency and to minimize packet loss during handover respectively: 1. Getting Router Advertisement (Rt Adv) information from a candidate vehicle which is in the range of its ad hoc region and connected with AP2. This allows VH to conﬁgure its new Care of Address (CoA) on the ﬂy (before actual handover starts), thereby, reducing handover latency. 2. Establishing connection with a candidate vehicle which is in the range of its ad hoc region and connected with AP1. This allows VH to receive packets destined to it via another vehicle during handover period, thereby, minimizing packet loss. The threshold value to initiate these two steps has to play a critical role in achieving seamless Make-Before-Break (MBB) kind of handover. The threshold is deﬁned as the minimum signal power level received from an AP at which the Handover Vehicle (VH ) should start the above two processes and completes before actual handover starts. Now, before explaining the above two steps in detail, we ﬁrst describe the creation and maintenance of priority table at MAC layer. Priority Table. All vehicles within the ad hoc domain create and maintain a priority table using GPS information. Using GPS, each vehicle periodically

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receives the information of other vehicles in terms of distance and relative position. On the basis of this information, the relative speed of other vehicles can be calculated. The table contains information about its nearby vehicles and the information is updated periodically. Based on the received information, the priority table assists the Handover Vehicle (VH ) in taking decisions and selecting a suitable candidate vehicle with respect to relative positions (front as well as rear) in order to complete the above deﬁned two processes. In our case scenario, VH considers the candidate vehicles falling into 500 m range in front and 500 m range in rear relative to VH , moving in same direction. Although 802.11p provides 1000 m range, we consider 500 m range to minimize the size and complexity of priority table. Moreover, this increases the reliability of the system. The priority of the candidate vehicle is decided on the basis of proximity of those vehicles to VH . Table 1 shows the priority levels assigned according to diﬀerent ranges of distance. Table 1. Priority levels Priority level Range 0 0-100 m 1 101-200 m 2 201-300 m 3 301-400 m 4 401-500 m

In our case scenario, the highest priority is assigned to the most distant vehicle from VH due to following reasons: (a) In front side, the vehicle which is farthest from VH , will have maximum probability that it is connected with AP2 and receiving Rt Adv from AP2. (b) In rear side, the vehicle which is farthest from VH , will have maximum probability that it will remain connected to AP1 for the longest time among other vehicles. Thus the highest priority (4) is assigned to the vehicles which are in the range of 401-500 m. Now, if VH has to decide between the two vehicles of same priority, then relative speed of vehicles comes into the picture. Lesser the speed, higher will be the priority because the low speed vehicles will have higher probability to satisfy the conditions imposed in (a) and (b). The speed of a vehicle can be calculated dynamically by receiving GPS information periodically. Table 2 shows the priority table of VH based on the GPS data received. Each vehicle maintains priority table in two parts. One part covers those vehicles which are in front of VH and moving in the same direction. Another part covers those vehicles which are in rear of VH and moving in the same direction. For the sake of simplicity, we are showing only one table covering rear vehicles.

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Table 2. Priority table of VH Vehicle Priority level Distance Speed Relative position VA 4 480 m 70 Kmph Rear VB 4 410 m 80 Kmph Rear VC 3 320 m 110 Kmph Rear VD 2 260 m 85 Kmph Rear VE 1 180 m 95 Kmph Rear VF 0 70 m 60 Kmph Rear

It is clear that with respect to the speed of VH (assuming the speed of VH as 60 Kmph), the relative speed of VA is less as compared to VB . Thus, if there are two or more vehicles with the same priority based on distance, the tie will be broken on the basis of speed of vehicle. The vehicle having less relative speed among the same priority level vehicles will be chosen for communication, i.e. VA will be assigned highest priority.

4

Proposed Handover Scheme (CSHS )

In this section, we describe the proposed ’Cross layer Seamless Handover Scheme in IEEE 802.11p based Vehicular Networks’ (CSHS ), by elaborating the two steps to reduce handover latency and to minimize packet loss during handover respectively. Step 1. To reduce handover latency, the objective of the proposed scheme is to conﬁgure new CoA of the handover vehicle in advance to the actual handover moment. First step is to get Rt Adv from the vehicle which is part of the ad hoc region and connected with AP2. In our case scenario, VH being the vehicle which is about to go into handover region. After reaching the threshold level, VH broadcasts a tone signal on control channel. The tone signal is out of frequency band used for data transmission and informs other nearby vehicles in ad hoc region to defer their communications (analogous to the safety messages in 802.11p networks)[18,19]. Thus, the tone signal allows VH to acquire highest priority to transmit data. VH senses the channel for AIFS time, if channel is free, it starts transmitting data (Rt Adv request) immediately to the chosen vehicle (Let VM is the chosen vehicle based on the priority table). If the channel is not found free, it defers its transmission for a random backoﬀ time with the following formula: Backof f time = [ rand+(1−i) ] × CW , where; 2 rand = uniformly distributed random number between [0,1] i = [0,1] is the priority level of the transmission with i=1 being the highest priority (tone signal) and i=0 for others CW = size of the contention window

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After receiving Rt Adv message, the candidate vehicle (VM ) sends the Rt Adv to VH . Finally, VH sends an Acknowledgement (Ack) to VM to terminate the communication session. By getting Rt Adv, VH can conﬁgure its new CoA for AP2 while it is still connected and receiving data from AP1. This reduces handover latency considerably because after reaching actual handover state, VH does not have to wait for Rt Adv and new CoA conﬁguration. By simply sending a Binding Update (BU) and receiving an Ack from Home Agent (HA), VH starts receiving packets destined to it via AP2. Step 2. To minimize packet loss, the objective of the proposed scheme is to redirect the traﬃc ﬂow of the vehicles via one another during handover period. Second step is to establish a communication with the vehicle which is part of the ad hoc region and connected with AP1. To minimize packet loss, VH takes assistance of one of the rear vehicles chosen on the basis of priority table (Let VA is chosen). During handover period, the packets destined to VH are received by VA , i.e. VA receives packets on behalf of VH and relays them to VH on its ad hoc interface. For doing so: 1. After completing ﬁrst step, VH again senses the channel for Arbitration Inter Frame Space (AIFS) time, if channel is free, it immediately starts transmission (requesting CoA of VA ) to VA . 2. VA replies to VH with its CoA. 3. VH sends BU message to the HA on NEMO interface. The home-address destination option ﬁeld and alternate CoA option ﬁeld of the binding update message contains VH ’s CoA and VA ’s CoA respectively. On receiving BU message, HA creates a mapping between both CoAs which is used to tunnel packets addressed to VH ’s CoA through AP1. All the packets routed to VH are intercepted by HA and the packets are encapsulated and forwarded to VA ’s CoA. The encapsulated packets all routed to VA ’s NEMO interface are then decapsulated to take VA ’s CoA oﬀ. The destined address is VH ’s CoA which is what the CN sends. 4. Finally, VA sends the decapsulated packets to VH on its ad hoc interface. VH receives packets via VA until it completes the handover process. As soon as VH gets Binding Acknowledgement (BAck) from HA after completing its handover, the HA tunnels packets to VH through AP2 and the communication session with VA is terminated. Thus, the cooperative reception of packets by vehicles via one another signiﬁcantly minimizes packet loss during handover.

5

Performance Evaluation

This section presents the performance evaluation in which our proposed handover scheme (CSHS ) is investigated and compared with standard NEMO BS with respect to handover latency and packet loss during handover period. Network Simulator ns-2.29[20] is used to perform simulations by extending MOBIWAN[21]. We adopted two-lane highway scenario with vehicles moving in same direction in

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each lane. In simulations, we consider only one lane just for the sake of simplicity. We assume that the vehicles are moving at constant speed with in a range of 60 Kmph to 150 Kmph and the arrival of vehicles is modeled as Poisson process. In simulations, we have taken three diﬀerent threshold values that are 10, 20, and 30 percent more than the signal strength at handover point respectively. We use IEEE 802.11p protocol for V2V communications in single hop ad hoc region. The tone signal is broadcasted on control channel and all the data transmission with in the ad hoc region takes place on data channel. In our scenario, the Handover Vehicle (VH ) has been given higher priority for transmitting data over other vehicles within the ad hoc region. As per our formula for random backoﬀ time, the highest priority is being given to VH with AIFS value of 34 µ s and CW range of 3 to 511. For other data transmission, the values of AIFS and CW range are shown in Table 3. Three set of parameters has been taken to assist diﬀerent type of messages for diﬀerent services such as traﬃc information and multimedia applications. Table 4 summarizes the parameters used in our simulation. Fig. 2 compares the handover latency experienced during the simulation of CSHS for diﬀerent threshold values with NEMO BS. The simulation was carried out for single hop distance from MR to the HA. It can be observed that at lower speeds (60-80 Kmph), CSHS has almost similar handover latency for diﬀerent thresholds. However, as the speed increases, CSHS with threshold set to 30 % has lower handover latency because it has suﬃcient time to complete step 1 of CSHS. When threshold is set to 10 %, the vehicle moving at the speed of 150 Kmph has very less time to perform step 1 before their handover point due to

Table 3. Parameters for AIFS and CW Parameter Priority 1 (ﬁxed) Priority 0 (varying) AIFS 34 µ s 34 µ s, 43 µ s, 79 µ s CWm in 3 7, 15, 15 CWm ax 511 1023, 1023, 1023

Table 4. Simulation Parameters Parameter Value Simulation area 10100 * 50 m Simulation time 150 s AP coverage 5000 m Gap between AP’s range 100 m Rt. Adv. interval 1s Number of vehicles 50 Vehicle Speed 60 Kmph to 150 Kmph Ad hoc Data transfer rate 3Mbps Packet size 500 bytes Ad hoc coverage 1000 m

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900 800

s) 700 m ( 600 cyn tea 500 lr ev 400 od 300 na H 200

P=4 Th 10% Th 20% Th 30% NEMO BS

100 0 60

80

100

120

150

Speed of vehicles (km/h)

Fig. 2. Handover latency Vs vehicle speed for diﬀerent threshold values

900 800

P=4

700

ss 600 o l 500 te kc 400 a P 300

Th 10% Th 20% Th 30%

200

NEMO BS

100 0 60

80

100

120

150

Speed of vehicles (km/h)

Fig. 3. Packet loss Vs vehicle speed for diﬀerent threshold values

the non-availability of channel in CSMA. Thus maximum handover latency is experienced. It is observed that even if threshold is set to 10 %, our approach performs better than NEMO at higher speeds. This is because the handover vehicle receives Rt Adv from front vehicle instead of AP. Fig. 3 shows the packet loss during the completion of two steps of CSHS. It is clear from the graph that at speed of 60 Kmph, the packet loss is almost same for all the threshold values. It is because the vehicle has enough time to process step 2. The packet loss experienced at this speed accounts only for the time required to send BU to the HA. As the speed increases, the time available to complete both steps becomes shorter, and when the threshold is 10 %, more packet loss will be experienced. The performance is aﬀected by the inherent nature of CSMA which is contention based channel access. Thus it may be possible that VH will not get access over the channel immediately after sending the tone signal and will go for backoﬀ. At lower speeds, this backoﬀ time will have very small eﬀect, but at higher speeds it will result in packet loss. At higher values of threshold, it may be possible that even if the speed is high, packet loss will be small as compared to other schemes, because it has more (enough) time to complete the two steps.

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1200 1000 s) m ( 800 cyn tea 600 lr ev od 400 na H 200

Speed = 60 P=4 Th 10% Th 20% Th 30% NEMO BS

0 1

2

3

4

5

6

7

8

Number of hops between MR and HA

Fig. 4. Handover latency Vs number of hops between MR and HA for vehicle speed 60 Kmph

1400 1200

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ss o L 800 te kc 600 a P 400

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200 0 1

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3

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Number of hops between MR and HA

Fig. 5. Packet loss Vs number of hops between MR and HA for vehicle speed 60 Kmph

Fig. 4 exhibits handover latency with respect to number of hops between MR and HA for diﬀerent threshold values. The handover latency is signiﬁcantly aﬀected by the number of hops encountered by a packet coming from HA to the MR. When number of hop count is 1, the handover latency is minimum in our simulation, As the number of hops increases, handover latency also increases. Up to number of hops = 3, the handover latency is observed less than 200 ms for all the threshold values. When number of hops is increased, the overall time required to complete handover process increases. Thus, in our case, the handover latency is aﬀected by the number of hops between MR and HA. Fig. 5 shows the packet loss observed for diﬀerent threshold values at constant speed of 60 Kmph. At speed of 60 Kmph, the vehicle has enough time to perform step 2. This means that packet loss occur only for the period it takes to complete the BU procedure with the HA. Thus as the number of hops increases, the packet loss increases in proportion to delay experienced by the BU packet to reach its HA.

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Conclusion

In this paper, we have proposed a Cross layer Seamless Handover Scheme in IEEE 802.11p based Vehicular Networks’ (CSHS ). CSHS makes use of ad hoc communications between vehicles to assist NEMO handover in vehicular scenario. The main contribution of this paper is to optimize handover latency and minimize packet loss based on the uses of mixed ad hoc and infrastructure communications, thus enabling V-2-I communications to be improved. The eﬃciency of CSHS is veriﬁed through extensive simulations. CSHS is evaluated for diﬀerent vehicle speeds and MR-HA latency under diﬀerent threshold values and priority levels. The simulation results reveal that CSHS achieves seamless handover in VANEMO scenario by signiﬁcantly reducing handover latency and minimizing packet loss in comparison to NEMO Basic Support protocol.

References 1. Hartenstein, H., Laberteaux, K.P.: A Tutorial Survey on Vehicular Ad Hoc Networks. IEEE Communications Magazine 46(6), 164–171 (2008) 2. Papadimitratos, P., de La Fortelle, A., Evenssen, K., Brignolo, R., Cosenza, S.: Vehicular Communication Systems: Enabling Technologies, Applications, and Future Outllok on Intelligent Transportation. IEEE Communication Magazine 47(11), 84– 95 (2009) 3. Standard Speciﬁcation for Telecommunications and Information Exchange Between Roadside and Vehicle Systems - 5 GHz Band Dedicated Short Range Communications (DSRC) Medium Access Control (MAC) and Physical Layer (PHY) Speciﬁcations, ASTM DSRC STD E2313-02 (2002) 4. IEEEP802.11p/D3.0, Draft Amendment for Wireless Access in Vehicular Environment (WAVE) (2007) 5. Ernst, T.: The Information Technology Era of the Vehicular Industry. ACM SIGCOMM Computer Communication Review 36(2), 49–52 (2006) 6. Devarapalli, V., Wakikawa, R., Petrescu, A., Thubert, P.: Network Mobility (NEMO) Basic Support Protocol. Internet RFC: RFC3963 (2005) 7. Baldessari, R., Festag, A., Abeille, J.: NEMO meets VANET: A Deployability Analysis of Network Mobility in Vehicular Communication. In: 7th International Conference on ITS Telecommunications (ITST 2007), pp. 375–380 (2007) 8. Tsukada, M., Mehani, O., Ernst, T.: Simultaneous Usage of NEMO and MANET for Vehicular Communication. In: Proceedings of TridentCom, Innsbruck, Austria, pp. 1–8 (2008) 9. Bechler, M., Wolf, L.: Mobility Management for Vehicular Ad Hoc Networks. In: Proceedings of VTC 2005-Spring, pp. 2294–2298 (2005) 10. Ernst, T., Uehara, K.: Connecting Automobiles to the Internet. In: Proceedings of ITST: 3rd International Workshop on ITS Telecommunications (2002) 11. Park, H.-D., Lee, K.-W., Lee, S.-H., Cho, Y.-Z., An, Y.-Y., Kim, D.-H.: Fast IP Handover for Multimedia Services in Wireless Train Networks. In: Chong, I., Kawahara, K. (eds.) ICOIN 2006. LNCS, vol. 3961, pp. 102–111. Springer, Heidelberg (2006) 12. Han, Y.H., Choi, J.H., Hwang, S.H.: Reactive Handover Optimization in IPv6based Mobile Network. IEEE Journal on Selected Areas in Communications 24(9), 1758–1772 (2006)

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13. Petander, H., Perera, E., Lan, K.C., Seneviratne, A.: Measuring and Improving the Performance of Network Mobility Management in IPv6 networks. IEEE Journal on Selected Areas in Communications 24(9), 1671–1681 (2006) 14. Prakash, A., Verma, R., Tripathi, R., Naik, K.: Multiple Mobile Routers based Seamless Handover Scheme for Next Generation Heterogeneous Networks. In: Proceedings of First International Conference on Networks and Communications, IEEE Netcom 2009, Chennai, India, pp. 72–77 (2009) 15. Prakash, A., Verma, R., Tripathi, R., Naik, K.: A Seamless handover Scheme for Vehicles across Heterogeneous Networks. International Journal of Communication Networks and Distributed Systems (accepted for Publication) 16. Chiu, K.L., Hwang, R.H., Chen, Y.S.: Cross-Layer Design Vehicle-Aided Handover Scheme in VANETs. Wireless Communications and Mobile Computing (2009) 17. Okada, K., Wakikawa, R., Murai, J.: MANET and NEMO Converged Communication. In: Cho, K., Jacquet, P. (eds.) AINTEC 2006. LNCS, vol. 4311, pp. 235–251. Springer, Heidelberg (2006) 18. Yang, S., Refai, H.H., Ma, X.: CSMA based Inter-Vehicle Communication Using Distributed and Polling Coordination. In: Proceedings of 8th International IEEE Conference on Intelligent Transportation Systems, Vienna, Austria, pp. 167–171 (2005) 19. Bilstrup, K., Uhlemann, E., Strom, E.G., Bilstrup, U.: On the Ability of the 802.11p MACMethod and STDMA to Support Real-Time Vehicle-to-Vehicle Communication. EURASIP Journal on Wireless Communications and Networking, 1–13 (2009) 20. The Network Simulator - ns-2 Home page, http://www.isi.edu/nsnam/ns 21. MobiWan: ns-2 Extensions to Study Mobility in Wide-Area IPv6 Networks, http://www.inrialpes.fr/planete/pub/mobiwan/

Modeling and Simulation of Efficient March Algorithm for Memory Testing Balwinder Singh1, Sukhleen Bindra Narang2, and Arun Khosla3 1 Centre for Development of Advanced Computing (CDAC), Mohali (A scientific Society of Ministry of Comm. &Information Technology, Govt. of India) 2 Electronics Department Guru Nanak Dev University, Amritsar, India 3 ECE Department Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, India [email protected]

Abstract. Semiconductor memories are considered one of the most important aspects of modern microelectronics. Memories are the most important universal components in SoC (System on Chip) today. Almost all SoC’s contain some type of embedded memories, such as ROM, RAM, DRAM and flash memory. Testing them becomes a challenge as these devices become more complex. The modeling and simulation of Memory BIST is presented in this paper. The architecture is implemented using Hardware Description Language and an area overhead is analyzed. The LR algorithm is implemented on to test the SRAM faults like stuck at faults, inversion coupling faults, linked faults etc. Keywords: Memory Built In Self-Test, March Algorithms, VLSI Testing.

1 Introduction Memories also are the most sensitive components to process defects. Memory stores data and instructions used in almost all-modern technology devices such as computers, telecommunications and consumer electronics. Memory is either volatile; loses data when power is removed or non-volatile; stores data indefinitely. Volatile memory can be SRAM or DRAM stores data using a flip-flop and a capacitor respectively. ROM, EPROM, EEPROM and flash memories are examples of non-volatile memories where the data can be permanent or reprogrammable, depending on the fabrication technology used. Embedded memory cores are the densest components within SOCs. According to the International Technology Roadmap for Semiconductors 2007, the percentage of memory in the CPU cores ranges from 65% to 75% and 83% to 86% in consumer cores. [1] For example, the Compaq Alpha EV7 chip employs 135 million transistors for RAM cores alone, while the entire chip has 152 million transistors. Memories may have faults that are related to the structure of circuit. For these faults detections various test algorithms are used to test these memories with the help of modern memory BIST circuitries. These test algorithms are divided into two categories: Classical tests and March-based tests. Classical test algorithms [3][16] are Checkerboard, Walking, GALPAT, Sliding Diagonal, Butterfly, MOVI, etc. Each S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 96–107, 2010. © Springer-Verlag Berlin Heidelberg 2010

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algorithm has its own advantages and disadvantages like Checkerboard algorithms are simple, fast but have poor fault coverage others have good fault coverage but are complex and slow. The popularity of these algorithms is decreased due to their imbalanced conflicting traits, so March-based Test Algorithms comes into existence, March-based test algorithm has finite sequence which specified by an address order and a number of reads and writes. Examples of some March-based tests are MATS, MATS+, March C-, March Y, March A, March B, march LR etc. these all are simple and have good fault coverage, specific algorithms have been developed and analyzed in detail. [4] In this paper section 2 gives the review of the previous work , Section 3 gives an overview of commonly used memory BIST methods and their comparision. Then the section 4 describes fault modeling, various test algorithms and comparison with LR algorithms and . Last, section 5 gives the synthesis of LR algorithm for SRAM and simulation results summary and paper is concluded in Chapter section 6. References are appended in the last.

2 Prior Work Many researchers have been studying the faulty behavior of memory devices and defining functional fault models (FFMs) to describe the detected faulty behavior, and develop tests, which target these FFMs. Many functional fault models (FFMs) for memories have been introduced. G.Harutunyan[5]introduces minimal March test algorithm March SS of complexity 18N for detection of all realistic simple static faults in Random Access Memories Benso et al[6] proposed that March AB and March AB1 have the same fault coverage of already published algorithms (March RAW and March RAW1) addressing the same fault list but they reduce the complexity of 4 and 2 operations respectively. In addition, the comparison between March AB and the well-known March SS for static fault shows that March AB has the same length of March SS but it improves the fault coverage by detecting both static and dynamic faults. Harutunyan et al. [8] proposed Two March test algorithms of complexity 11N and 22N; N is the number of memory cells, for subclasses of twooperation single-cell and two-cell dynamic faults respectively. In this paper the previously known March test algorithm for detection of two-operation two-cell dynamic faults is improved by 30N.Hamdioui et al[9] introduces a new test (March SS), with a test length of 22n that detects all realistic simple static faults in RAMs. Haron proposed a micro coded memory BIST architecture that is modeled and synthesized using RTL abstraction level and five March algorithms are implemented to test faulty memories. [10]

3 Memory Built in Self Test The design for testability (DFT) circuits (like Built In Self Test) is embedded in a system to reduce the test complexity and cost. The testing benefit is high due to expensive memory testers and a significant reduction in memory tester time. As a result, MBIST is beneficial for medium- to high-volume products [11] BIST consists of address generator, test pattern generator, and BIST control logic as shown in Figure 1.

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Fig. 1. Basic Memory BIST architecture

Address Generator: The main purpose of the address generator is to generate the test patterns. Linear Feedback Shift Registers (LFSRs) are often used to generate the test pattern. LFSRs are called so because they are shift registers with feedback paths that are linearly combined via the XOR gates. Read/Write Controller: The read/write controller provides the location on the memory where data will be written during the write operation or from where date will be read during the read operation. The read/write controller determines how many cycles a given address is maintained before the address counter is incremented. Data Generator: Data generator interacts with address counter and read/write control logic. It is used to provide the correct data to the memory corresponding to the particular element of the particular test pattern. Address counter: Address counter interacts with address limiter and address comparator, identifying the proper start and stop address points. The address counter indicates if an even or odd address is being exercised, so that appropriate data can be generated. This counter needs to able to be increment or decrement. Comparison of Memory Bist Techniques Different memory BIST implementation schemes are described and compared in this section. Memory The BIST controller can be implemented by either micro code, hardwired logic, or processor-based. Table 1 gives the summary of this comparison of the three implementations. Table 1. Trade-offs: Memory BIST Schemes [12]

Scheme

Test Time

Area OH

Routing OH

Flexibility

Hardwired Micro code

Short Average

Low High

High Low

Zero Low

Processor

Long

Zero

Zero

High

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Hardwired Based BIST: Finite state machine is used for hardware realization of the selected test algorithms. This scheme is compact, fast, incur the most design efforts and possesses the least flexibility. This technique is still much used by the DFT designers. Processor based BIST: In this processor of the system is used to test the memory of the system .It is done by executing a assembly language program on the on chip microprocessor to generate patterns, including address sequence data patterns and control signals. The memory outputs are then compared with the expected correct data. This method is the most flexible, zero area overhead and routing overhead but incurs long test time. So processor become busy for much time for testing, it may delay the normal mode operations.[13] Micro code based BIST: In this type of BIST instruction set is defined for the BIST process. A selected test algorithm program can be written with the use of instruction set. This program is stored in the BIST controller to test the memory. This method is somewhere in between the two methods according to the tradeoff’s as mentioned above.

4 Fault models and Memory Test Algorithms Fault Models Fault modeling is the translation of physical defects to a mathematical construct that can be operated upon algorithmically and understood by a software simulator to provide a quality measurement. New fault models should be established in order to deal with the new defects introduced by today and future (deep-sub micron) technologies. Fault models are classified as static and dynamic faults: Memory faults sensitized by performing at the most one operation are called static faults such as state fault (SF),Transition fault (TF), stuck-at fault (SAF), Stuck-open fault (SOF) and address decoder fault (ADF). Where as dynamic faults can take place in the absence of static faults and require more than one operation to be performed sequentially in time in order to be sensitized. For example, a write ‘1 ‘operation followed immediately by a read 1 operation will cause the cell to flip to ‘0’; however, if only a single write ‘1’ or a single read ‘1’, or a read ‘1’ which is not immediately applied after write ‘1’ operation is performed, then the cell will not flip. For test purpose, faults in memories are usually modeled as functional faults. A Functional Fault Model (FFM) is a deviation of memory behavior from the expected one under a set of performed operation (Al-Ars et al., 2001). The functional fault model can be of two types Static fault model and Dynamic fault model. In the last years Static faults (e.g., stuck-at faults, coupling faults) have been the predominant fault type. They are characterized by being sensitized by the execution of just a single memory operation. New faulty behaviors occur in latest technologies. These behaviors require more than one operation to be sensitized, and are referred to as Dynamic Faults .[6]

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Dynamic Fault Model Dynamic faults are the faults, which require more than one operation to be performed sequentially in time in order for the faults to be sensitized. For example write ‘1’ operation followed immediately by a read ‘1’ operation may cause a cell to flip (invert its values) from ‘1’ to ‘0’; however, if only a single write 1 or a single read 1or a read ‘1’ which is not immediately applied after write ‘1’ operation is performed, then the cell will not flip. Dynamic fault model can appear in both in cell array, the R/W circuitry and address decoder circuitry. Dynamic Faults in array cell Dynamic read destructive faults (dRDF): it occurs when a write operation is immediately followed by read operation and it changes the logic value stored in the memory cell and returns incorrect value at the output. Dynamic data retention faults (dDRF): it occurs when a memory cell loses its previously stored logic value after a certain period of time during which it has not been accessed. Leakage Read fault (LRF): it occurs when in a memory column most of the cells store the same value x ε {0, 1}, the leakage current, through the pass transistor of the unselected cells may affect the read operations of the cells storing the value y = not (x) is expected whereas x is read. Dynamic Faults in Address Decoder Address Decoder Open Fault (ADOF) and Resistive- ADOF: A decoder is said to have an ADOF/R-ADOF if changing only one bit on its address results in selecting this new address but also the previous one. Consequently, two core-cells are selected at the same time for a read or a write operation Dynamic Fault in the R/W Circuitry Dynamic Incorrect Read Fault (dIRF). A sense amplifier is said to have a dIRF if it is not able to read any value. So, the read data value at the output is the one previously stored in the data output circuitry. Slow Write Driver Fault (SWDF): a write driver is said to have a SWDF if it cannot act a w0 (w1) when this operation is preceded by a w1 (w0). This results in a core cell that does not change its data content. Static Fault Model Most of the work published on memory testing focuses on faults sensitized by performing at most one operation; e.g., a write operation sensitizes a fault. These FFMs are called static faults. Static fault model can appear in both in cell array, and in address decoder circuitry as discussed below.

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Address Decoder Faults These concern faults in address decoder. Functional faults can result in four AFs: Fault 1: with a certain address, no cell can be accessed Fault 2: there is no address with which a particular cell can be accessed. Fault 3: multiple cells can be accessed with a particular address. Fault 4: a certain cell can be accessed with multiple addresses. Simple Memory Cell Array Faults Stuck-at Faults: The stuck-at fault (SAF) considers that the logic value of a cell or line is always 0 (stuck-at 0 or SA0) or always 1 (stuck-at 1 or SA1). Stuck open faults: An Stuck open faults (SOF) in a memory cell means that cell cannot be accessed e.g due to open word line [15]. When the sense amplifier contains a latch, then upon a read operation the previous read value may be produced. Transition Faults: The transition fault (TF) is a special case of the SAF. A cell or line that fails to undergo a 0! 1 transition after a write operation is said to contain an up transition fault. Similarly, a down transition fault indicates the failure of making a 1! 0 transitions. Faults between Memory Cells Coupling Faults: Coupling fault (CF) between two cells causes a transition in one cell to force the content of another cell to change. Inversion coupling fault (CFin): A “1 Æ 0” “or “0 Æ1” transition in one cell (coupling cell) inverts the contents of a second cell (coupled cell). It is sensitized by transition write operation. Idempotent coupling fault (CFid): A “1 Æ 0” or “0 Æ1” transition in one cell (coupling cell) forces the contents of a second cell (coupled cell) to a certain value, 0 or 1. State coupling fault (CFsts): A coupled cell is forced to a certain state only when the coupling cell is in a given state. It is not sensitized by a transition write operation in the coupling cell but by the logical state of the cells or lines. Disturb fault (CFdst): It is a fault whereby the coupled cell is disturbed (i.e. makes 0Æ1 or 1Æ0 transition) due to a readY or writeY operation (where Y can be 0 or 1) applied to the coupling cell. Incorrect Read Coupling Fault (CFir): A read operation applied to the coupled cell returns an incorrect value if the coupling cell is in a certain state. Note that in this case, the state of the coupled cell is not changed. Random Read Coupling Fault (CFrr): A read operation applied to the coupled cell returns a random value if the cell is in a certain state.

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Neighborhood pattern sensitive fault (NPSF): The contents of a cell or the ability to change the contents are influenced by the contents of its neighboring memory cells. NPSF is a subset of PSF (Pattern sensitive fault) wherein the cell can be influenced by the contents of all other cells in the memory. The cell under test is the base cell. The neighborhood with the base cell excluded is called the deleted neighborhood. Three types of NPSF are there: Active NPSF: The base cell changes its contents due to change in the deleted neighborhood pattern. The test to detect this fault should ensure that “each base cell is read in state 0 and state 1, for all the possible changes in the deleted neighborhood pattern.” Passive NPSF: The contents of the base cell can’t be changed (it can’t make a transition) due to a certain deleted neighborhood pattern. The test to detect this fault should ensure that “each base cell is written and read in state 0 and state 1, for all permutations of the deleted neighborhood pattern.” Static NPSF: The content of the base cell is forced to a certain state due to a certain deleted neighborhood pattern. The test to detect this fault should ensure that “each base cell is read in state 0 and state 1, for all permutations of the deleted neighborhood pattern. Memory Test Algorithms A March test consists of a finite sequence of March elements. A March element is a finite sequence of operations applied to each cell in the memory before proceeding to the next cell, according to a specified address order; i.e., ascending, descending, or irrelevant. An operation can consist of writing a 0 into a cell (w0), writing a 1 into a cell (w1), reading an expected 0 from a cell (r0), and reading an expected 1 from a cell (r1). Some of the most popular notations for MARCH tests which will be used through out the explanation are below.

March LR algorithm March LR algorithm is one of the most efficient RAM test algorithms currently in use, in terms of test time and fault detection capability. This algorithm has a test time

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on the order of 16N, where N is the number of address locations. The holy wish of any test algorithm designer is to get maximum fault coverage with minimum test time. So a new test for realistic linked faults, March LR is produced. The March LR pattern covers stuck-at and transition faults along with even more coupling and address decoder faults. It requires test time of 16N operations and able to detect the following faults: {↕(w0); ↓(r0,w1); ↑(r1,w0,r0,w1); ↑(r1,w0); ↑(r0,w1,r1,w0); ↑(r0)} SOFs: by the March element M2 and M4 SAFs and linked TFs: by the March element M2 and M4 CFs: by March element M2 through M5 Linked CFs consisting of two simple CFs: by March element M2 together with M3 and by M4 together with M5 AFs: by March element M1 together with M1 through M3 AF#TF and AF#CF. March LR is more superior to the existing March tests because it is able to detect linked faults consisting of an arbitrary number of simple faults, which may be of type CFin or CFid as shown in table 2. Table 2. Fault coverage of linked faults

5 Simulation Result The March element of Memory BIST architecture is designed using HDL then the Write operation that is used to insert the faults in the memory programmatically. In this way the faults are inserted in the memory locations in the memory as shown in the table 3. Synthesis process has been performed using Xilinx 9.1i tools [17] for synthesizing the complied HDL design codes into gate level schematics and the technology mapping has chosen in this paper was spartran3E (XC3s1600) with FG484 package and speed grade of –4.

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The faults are detected in the simulation results as March LR algorithm first March element does the w0 and r0 down operation. During read ‘0’ operation following faults are detected at specified addresses: as shown in table 4 and simulation results with help of Mentor graphics ModelSim 6.2 tool as shown in figure 3. After that the second March element does w1 down and read ‘1’up operation. During read ‘1’ operation following faults are detected at specified addresses as shown in the table 5 and simulation results shown in figure 4. Table 3. List of faults inserted in various memory locations

Location 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110

Fault inserted No fault Stuck at fault 0 (SA0) Stuck at fault 1 (SA1) No fault Inversion Coupling fault (with address 0011) No fault No fault Linked fault (linked with upper cell) Address Decoder Fault (address decoder fault 4 with 0010 address) Linked fault (linked with lower cell) No fault Dynamic Coupling fault(with address 0011) No fault No fault Address Decoder Fault (address decoder fault 3 with addresses 1111, 0000 and 0001 in this case)

According to March LR algorithm first March element does the w0 and r0 down operation. During read ‘0’ operation, following faults are detected at specified addresses. Table 4. Faults detected in memory addresses

Fault type Address Decoder Fault Linked fault Dynamic Coupling fault Linked fault at Stuck at fault 1 (SA1) Inversion coupling fault at

Fault detected at memory locations Address 1000 Address 1001 (linked with lower cell i.e 1000) 1011 (with address 0011) Address 0111 (linked with upper cell i.e 1000) Address 0010 Address 0100 (with address 0011)

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Fig. 3. Simulation results for detected faults at memory locations

Then the second March element does w1 down and read ‘1’up operation. During read ‘1’ operation following faults are detected at specified addresses: Table 5. Faults detected in memory addresses

Fault type Inversion coupling fault Stuck at fault 0 (SA0) Address Decoder Fault Dynamic Coupling fault

Fault detected at memory locations Address 0100 (with address 0011) Address 0001 Address 1110. (Address decoder fault 3 with addresses 1111, 0000 and 0001 in this case) 1011 (with address 0011)

Fig. 4. Simulation results for detected faults at memory locations

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Second, the March C, March X, and March LR are simulated on the same platform. The comparison of these algorithms on the basis of device utilization reports is given in table 6. The March LR detects all the faults listed in Table 2 except DRF faults. it costs with increased gate count then March X . But gate count for March LR is less than March C. Delays are also more due to more time taken to detect more faults. Table 6. Comparison of Area overhead and delay for different march algorithms

Components Number of Slices Number of LUT Number of IOBs Total Gate count Delay (ns)

Comparison of Area overhead and delay March C March X March LR 42 33 86 84 62 280 8 29 4 8499 559 2500 12.3 14.45 15.884

6 Conclusion In this paper a classification of memory faults have been made. Here, various March test algorithms are proposed for detection of different static and dynamic faults and it is surveyed that march LR is superior to the existing March tests because it is able to detect all realistic faults and have a shorter length than comparable other tests. We have implemented the LR march algorithm and modeled the faults in the fault free memory with HDL and faults are detected from the injected locations with 100% fault coverage and in second part of simulation March C, March X and March LR algorithms are implemented in HDL and hardware overhead is calculated which will helpful to select the March algorithms for Memory Testing.

References [1] International Technology Roadmap for Semiconductors, ITRS (2007), http://public.itrs.net [2] Hamdioui, S., Gaydadjiev, G., van de Goor, A.J.: The state-of-art and future trends in testing embedded memories. In: International Workshop on Memory Technology, Design and Testing, pp. 54–59 (2004) [3] Grout Ian, A.: Integrated circuit test engineering: modern techniques. Springer, Berlin (2006) [4] Riedel, M., Rajski, J.: Fault coverage analysis of RAM test algorithms. In: Proceedings of the 13th IEEE VLSI Test Symposium, pp. 227–234 (1995) [5] Harutunyan, G., Vardanian, V.A., Zorian, Y.: Minimal March Tests for Unlinked Static Faults in Random Access Memories. In: Proceeding of VLSI Test Symposium, pp. 53–59 (2005) [6] Benso, A., Bosio, A., Di Carlo, S., Di Natale, G., Prinetto, P.: March AB, March AB1: New March Tests for Unlinked Dynamic Memory Faults. In: Proceeding of International Test Conference, pp. 841–848 (2005)

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[7] Hamdioui, S., Al-Ars, Z., van de Goor, A.J.: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Transactions on Computers 55(12), 1630–1639 (2006) [8] Harutunyan, G., Vardanian, V.A., Zorian, Y.: Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. In: Proceeding. of VLSI Test Symposium, pp. 120–127 (2006) [9] Hamdioui, S., van de Goor, A.J., Rodgers, M.: March SS: A Test or All Static Simple RAM Faults. In: Proc. of MTDT, pp. 95–100 (2002) [10] Haron, N.Z., Yunus, S.A.M., Aziz, A.S.A.: Modeling and simulation of microcode Memory Built In Self Test architecture for embedded memories. In: International Symposium on Communications and Information Technologies, pp. 136–139 (2007) [11] Lu, J.-M., Wu, C.-W.: Cost and benefit models for logic and memory BIST Design. In: Proceedings of Automation and Test in Europe Conference, pp. 27–30 (2000) [12] Cheng Allen, C.: Comprehensive Study on designing Memory BIST: Algorithms, implementations and Trade-offs. In: EECS 579, 48109–2122. University of Michigan, Ann Arbor (2002) [13] Zarrineh, K., Upadhyaya, S.J.: On programmable memory built-in self test architectures, Design, Automation and Test. In: Proceedings Europe Conference and Exhibition, pp. 708–713 (1999) [14] Al-Ars, Z., van de Goor, A.J.: Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs. In: Proceedings of DATE, pp. 401–406 (2001) [15] Van de Goor, A.J., Gayadadjiev, G.N., Yarmolik, V.N., Mikitjuk, V.G.: March LR: A Test for Realistic Linked Faults. In: 16th IEEE VLSI ISE 9.2i Software Test Symposium, pp. 272–280 (1996) [16] Rochit, R.: System-on-a-Chip: Design and Test, pp. 155–177. Artech house. Inc., Norwood (2000) [17] Xilinx Manuals, http://www.xilinx.com/itp/xilinx92/books/manuals.pdf

A New Approach for Detecting Design Patterns by Graph Decomposition and Graph Isomorphism Akshara Pande, Manjari Gupta, and A.K. Tripathi DST- Centre for Interdisciplinary Mathematical Sciences, Banaras Hindu University, Varanasi-221005, India [email protected] ,[email protected], [email protected]

Abstract. Design Pattern Detection is a part of many solutions to Software Engineering difficulties. It is a part of reengineering process and thus gives important information to the designer. Design Pattern existence improve the program understanding and software maintenance. With the help of these patterns specific design problem can be solved and object oriented design become more flexible and reusable. Hence a reliable design pattern mining is required. Here we are applying graph decomposition followed by graph isomorphism technique for design pattern detection. Keywords: design pattern, graph decomposition, UML, adjacency matrix, graph isomorphism.

1 Introduction In many object oriented software, there are recurring patterns of classes. Design Patterns are defined as explanation of corresponding classes that forms a common solution to frequent design problem. To reuse expert design experiences, the design patterns [1] have been extensively used by software industry. When patterns are implemented in a system, the pattern-related information is generally no longer available. It is tough to trace out such design information. To understand the systems and to modifications in them it is necessary to recover pattern instances. There are number of pattern detection techniques, some of them have been discussed in section 5. In this paper we are proposing an algorithm for graph decomposition (directed graph) and then trying to find out whether design pattern exists by applying graph isomorphism technique. Here we are taking two graphs, one is corresponding to the model graph (i.e. system under study) and other is corresponding to the design pattern graph. Graph Decomposition is applied on model graph, and then try to find out is there any isomorphism between the decomposed graphs (corresponding to model graph) and design patterns. The advantage of this approach is that it reduces time complexity of matching two graphs. The detailed methods are given in following sections. In section 2 graph decomposition algorithm is proposed. Condition of graph isomorphism is explained in section 3. In section 4 we have proved the algorithm with examples. Related works are discussed in section 5. Lastly we concluded in section 6. S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 108–119, 2010. © Springer-Verlag Berlin Heidelberg 2010

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2 Graph Decomposition The main idea of decomposing the directed graph is that, the smaller the graph structure, the easier the matching process and this will result in lower complexity than matching the original graph. Let G= (V, E) be a graph, where V is the set of vertices present in the graph and E is the set of edges present between the vertices. Suppose V= {n1, n2, n3…nn| ni is the nodes, i=1, 2….n}, E= {e1, e2, e3…en| ei is the edges, i=1, 2….n}, the graph G can be decomposed on the basis of the edges present between the nodes. Here we are applying decomposition algorithm on the graph (having more than one edge) for obtaining the decomposed graphs (which have one or two edges). 2.1 Relationship Graphs Representation The system under study or the system for which we have the source code is taken first, the corresponding the class diagram of UML of that code (object oriented system) is drawn. After that the relationship graphs (that exists in UML diagram) is extracted. We have taken the UML Diagram of system design as shown in Figure 1. There are three relationships (i.e. generalization, direct association and aggregation), the corresponding relationship graphs (i.e. directed graph) are shown in Figure 2, 3, 4. Generalization relationship graph (i.e. fig 2) has relationship between only three of the nodes, Direct Association relationship graph (i.e. fig 3) has relationship between 4 of the nodes so we will apply decomposition algorithm only on figure 2 and figure 3. There is no need to apply the decomposition algorithm on figure 4 (i.e. aggregation relationship graph) as it has relationship between only two nodes.

Fig. 1. UML Diagram of System Design

Fig. 2. Generalization Relationship Graph of UML Diagram of System Design

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Decomposition algorithm uses adjacency matrix representation of the corresponding relationship graphs. The adjacency matrices for figure 2 and figure 3 have been shown in figure 5 and figure 6. In adjacency matrix the entry should be 1 if there exists an edge between the two nodes, otherwise 0.

Fig. 3. Direct Association Relationship Graph of UML Diagram of System Design

Fig. 4. Aggregation Relationship Graph of UML Diagram of System Design

Fig. 5. Adjacency matrix corresponding to Generalization Relationship Graph

Fig. 6. Adjacency matrix corresponding to Direct Association Relationship Graph

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2.2 Graph Decomposition Algorithm The graph decomposition can be done using the following algorithm: DECOMPOS (Graph) For i = 1 to Number of Nodes For j = 1 to Number of Nodes if aij ≠ 0 then DECOMPOS2 {i, j} = DECOMPOS2 {i, j} ∪ {i, j, aij} For k = i+1 to Number of Nodes if ajk ≠ 0 then DECOMPOS3{i, j, k } = DECOMPOS3{i, j, k} ∪ {i, j, j, k, aijk} end if if akj ≠ 0 then DECOMPOS3{i, j, k } = DECOMPOS3{i, j, k} ∪ {i, j, k, j, aijk} end if For k = j+1 to Number of Nodes if aik ≠ 0 then DECOMPOS3{i, j, k } = DECOMPOS3{i, j, k} ∪ {i, j, i, k, aijk} end if end if End DECOMPOS The example of decomposing a graph has been shown in figure 7. Firstly, take the original graph, and apply the DECOMPOS algorithm on it. As a result, we found the 3 two order decomposition (graphs having two nodes) and 3 three order decomposition (graphs having three nodes) as shown in figure 7.

Fig. 7. Original Directed Graph; and its decomposed graphs

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The order of complexity of this decomposition algorithm is O(n3), where n is the number of nodes present in the graph. This algorithm works for only those design patterns having similar relationships among at most three classes in its UML class diagram. However this condition may not hold for only few of the design patterns. Thus this approach can be applied for almost all of the design patterns. Now this algorithm is applied on adjacency matrices of Generalization relationship and Direct Association relationship of system design. The decomposed graphs have been shown in figure 8 and figure 9 (corresponding to Generalization relationship) and figure 10 and figure 11 (corresponding to Direct Association relationship).

Fig. 8. After Decomposition of Generalization Relationship Graph (for two nodes)

Fig. 9. After Decomposition of Generalization Relationship Graph (for three nodes)

Fig. 10. After Decomposition of Direct Association Relationship Graph (for two nodes)

Fig. 11. After Decomposition of Direct Association Relationship Graph (for three nodes)

The graphs are stored after decomposition in different orders for example to store Generalization relationship graph we have order 2 (since edge is present between two nodes). There are two graphs of order 2 and one graph of order 3 (edge present among

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three nodes). But for storing Direct Association relationship graph after decomposition the order must be 2 and 3 (since edge is present for two nodes and three nodes both). There are three graphs of order 2 and three graphs of order 3.

3 Graph Isomorphism: A Graph Matching Technique Graph Matching techniques are important and very general form of pattern matching that finds realistic use in areas such as image processing, pattern recognition and computer vision, graph grammars, graph transformation, bio computing, search operation in chemical structural formulae database, etc. Graph isomorphism is a graph matching technique. In graph isomorphism, one to one correspondence between two nodes and their edges is searched out. If there is one to one correspondence, then two of the graphs are said to be isomorphic to each other. Let [5] G1 (V1, E1) and G2 (V2, E2) be two graphs, where V1, V2 are the set of vertices and E1, E2 are the set of edges. Let M1 and M2 be the adjacency matrices corresponding to G1 and G2 respectively. A permutation matrix is a square (0, 1)matrix that has exactly one entry 1 in each row and each column and 0's elsewhere. Two graphs G1 (M1, Lv, Le) and G2 (M2, Lv, Le) are said to be isomorphic [5], here the term Lv and Le represents the labeling of vertices and edges respectively. If there exist a permutation matrix P such that M2 = P M1 PT

(1)

In this paper we are assuming M1 is the matrix corresponding to the system design (i.e. the adjacency matrix of relationship after decomposition) and M2 as the design pattern adjacency matrix which should have the same order as of system design. Since we are decomposing only up to 3 order (lastly graph has only relationship between three nodes) so design pattern must have the order 2 or 3. Permutation matrix should also have the same order as of the relationship adjacency matrix of system design and design pattern.

4 Design Pattern Detection Using Graph Isomorphism There are 23 GoF (Fang of Four) [1] design patterns, corresponding UML diagrams can be drawn for them, but we are only considering those which have relationship graph of order 2 or 3. 4.1 Design Pattern Detection as Façade Design Pattern Firstly we are considering Façade design pattern, the UML diagram corresponding to it, is shown in figure 12. There is only one relationship, i.e. Direct Association relationship, relationship graph has been shown in figure 13. Now adjacency matrices corresponding to Direct Association relationship of system design (of order 2 i.e. consisting two nodes and an edge between them) and design pattern should be drawn (shown in figure 14 and 15). A 2×2 order permutation matrix is taken as shown in figure 16.

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Fig. 12. Façade Design Pattern

Fig. 13. Direct Association Relationship Graph of UML Diagram of Façade Design Pattern

Fig. 14. Adjacency matrices for Direct Association Relationship Graph of fig. 8 (M1)

Since permutation matrix is same as an identity matrix so transpose of permutation will be the same as of permutation matrix.

Fig. 15. Adjacency matrices for Direct Association Relationship Graph of fig. 11(M2)

Fig. 16. Permutation matrix (P or PT)

Now it could be easily seen that, equation 1 is satisfied. So Façade design pattern exists in system design or in model graph.

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4.2 Design Pattern Detection as Strategy Design Pattern Now consider strategy design pattern, UML as shown in figure 17. The corresponding Generalization relationship and Aggregation relationship has been shown in figure 18 and figure 19 respectively.

Fig. 17. Strategy Design Pattern

Fig. 18. Generalization Relationship Graph of UML Diagram of Strategy Design Pattern

Fig. 19. Aggregation Relationship Graph of UML Diagram of Strategy Design Pattern

Fig. 20. Adjacency matrices for Generalization Relationship Graph of fig. 8 (M1)

Fig. 21. Adjacency matrices for Generalization Relationship Graph and Aggregation Relationship graph of fig. 17 and fig. 18 (either can be taken as M2)

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Matrix M1 and M2 are shown in figure 20 and figure 21 respectively. If permutation matrix is of same as in figure 16, then by applying equation 1, we can say that strategy design pattern exists in system design for Generalization relationship. Similarly could be seen for aggregation relationship also. 4.3 Design Pattern Detection as Strategy Design Pattern Now consider composite design pattern, UML as shown in figure 22. The corresponding Generalization relationship, Direct Association relationship and Aggregation relationship has been shown in figure 23, figure 24 and figure 25 respectively. Com pone nt

Clie nt

*

+Operation() +Add(Parameter1: Component) +Remove(Parameter1: Component) +GetChild(int)

Le a f

Co m po sit e

Fig. 22. Composite Design Pattern

Fig. 23. Generalization Relationship Graph of UML Diagram of Composite Design Pattern

Fig. 24. Direct Association Relationship Graph of UML Diagram of Composite Design Pattern

Fig. 25. Aggregation Relationship Graph of UML Diagram of Composite Design Pattern

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If Generalization relationship of system design is taken as 3 order as shown in figure 8, adjacency matrix can be written as shown in figure 26. And Generalization relationship of composite design pattern is shown in figure 27. Permutation matrix and its transpose are taken as shown in figure 28.

Fig. 26. Adjacency matrix for Generalization Relationship Graph of fig. 9(M1)

Fig. 27. Adjacency matrix for Generalization Relationship Graph of fig. 23(M2)

Fig. 28. Permutation Matrix (P or PT)

Now if equation 1 is applied for composite design pattern detection for Generalization relationship, it exists. We found that both the graphs are isomorphic for generalization relationship. Similar is for Direct Association and for Aggregation relationship also. 4.4 Particular Design Pattern May or May Not Exist Above we see the examples of design pattern existence but it can be possible that a particular design pattern does not exist in system design. In this there will be no permutation matrix for which we can find out an isomorphism between adjacency matrix of system design and adjacency matrix of design pattern.

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5 Related Work The first effort towards automatically detect design pattern was achieved by Brown [6]. In this work, Smalltalk code was reverse-engineered to facilitate the detection of four well-known patterns from the catalog by Gamma et al. [1]. Antoniol et al. [7] gave a technique to identify structural patterns in a system with the purpose to observe how useful a design pattern recovery tool could be in program understanding and maintenance. Nikolaos Tsantalis [2], proposed a methodology for design pattern detection using similarity scoring. But the limitation of similarity algorithm is that it only calculates the similarity between two vertices, not the similarity between two graphs. To solve this Jing Dong [3] gave another approach called template matching, which calculates the similarity between subgraphs of two graphs instead of vertices. Wenzel [4] gave the difference calculation method works on UML models. The advantage of difference calculation method on other design pattern detecting technique is that it detects the incomplete pattern instances also. In our earlier work [8-11], we have shown how to detect design patterns using various techniques. The complexity of previous proposed techniques are very high, we are trying to reduce this complexity by introducing graph decomposition.

6 Conclusion In this paper we took the model graph and a data graph (corresponding to design pattern), and tried to find out whether design pattern exists or not in model graph. Firstly, we decompose the model graph into different orders, and then take same order design pattern. There are 23 GoF (Fang of Four) [1] design patterns. By applying the decomposition algorithm, the complexity is reduced. For isomorphism detection, only one permutation matrix (i.e. identity matrix) is required in our case. Hence the time complexity of choosing suitable permutation matrix has also been removed.

References 1. Gamma, E., Helm, R., Johnson, R., Vlissides, J.: Design Patterns Elements of Reusable Object-Oriented Software. Addison-Wesley, Reading (1995) 2. Tsantalis, N., Chatzigeorgiou, A., Stephanides, G., Halkidis, S.: Design Pattern Detection Using Similarity Scoring. IEEE transaction on software engineering 32(11) (2006) 3. Dong, J., Sun, Y., Zhao, Y.: Design Pattern Detection By Template Matching. In: The Proceedings of the 23rd Annual ACM, Symposium on Applied Computing (SAC), Ceará, Brazil, pp. 765–769 (March 2008) 4. Wenzel, S., Kelter, U.: Model-driven design pattern detection using difference calculation. In: Proc. of the 1st International Workshop on Pattern Detection For Reverse Engineering (DPD4RE), Benevento, Italy (October 2006) 5. Messmer, B.T., Bunke, H.: Subgraph isomorphism detection in polynomial time on preprocessed model graphs. In: Second Asian Conference on Computer Vision, pp. 151–155 (1995)

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6. Brown, K.: Design Reverse-Engineering and Automated Design Pattern Detection in Smalltalk, Technical Report TR-96-07, Dept. of Computer Science, North Carolina State Univ. (1996) 7. Antoniol, G., Casazza, G., Penta, M.D., Fiutem, R.: Object- Oriented Design Patterns Recovery. J. Systems and Software 59(2), 181–196 (2001) 8. Pande, A., Gupta, M.: Design Pattern Detection Using Graph Matching. International Journal of Computer Engineering and Information Technology (IJCEIT) 15(20), 59–64 (2010); Special Edition 2010 9. Pande, A., Gupta, M.: A New Approach for Design Pattern Detection Using Subgraph Isomorphism. In: Proc. of National Conference on Mathematical Techniques: Emerging Paradigm for Electronics and IT Industries (MATEIT 2010) (2010) 10. Gupta, M., Pande, A.: A New Approach for Detecting Design Patterns Using Genetic Algorithm. Presented in International Conference on Optimization and its Application, organized by Deptt. of Mathematics, Banaras Hindu University (2010) 11. Pande, A., Gupta, M., Tripathi, A.K.: Design Pattern Mining for GIS Application using Graph Matching Techniques. In: 3rd IEEE International Conference on Computer Science and Information Technology, Chengdu, China, July 9-11 (accepted, 2010)

Detection of Polymorphic Viruses in Windows Executables Abhiram Kasina, Amit Suthar, and Rajeev Kumar Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Kharagpur, WB 721302 {abhiram,aksuthar,rkumar}@cse.iitkgp.ernet.in

Abstract. Polymorphic viruses are viruses which unpack themselves at runtime and infect files with a new mutated virus body. Most of the current solutions present blacklist a set of packer. Research has shown many polymorphic viruses to go undetected. This work aims at the problem of detection of such viruses using emulation technique. The main target is to improve the detection rate and reduce false positives. Bochs is a powerful x86-64 emulator and the system has been implemented on Bochs and could successfully detect self-modifying code in test viruses. Keywords: Reverse Engineering, Code Analysis, Dynamic Analysis, Code Obfuscation, Malware Analysis, Polymorphic Virus, Malware Packing.

1

Introduction

In todays world malware is rampant, be it in the form or viruses, trojans, spyware or rootkits. And viruses form a major problem of all the malware. Traditionally viruses have spread through emails and they infect portable executables (PE) in Windows [2]. Simple viruses are generally the easiest to detect. When a user launches an infected program, the virus gains control of the computer, searches for other program ﬁles and attaches itself to that ﬁle. Subsequently, it passes the control back to the original executable. As a result the user generally does not even detect any malicious behavior. But the virus always makes an exact copy of itself. Hence, all the Anti Virus (AV) vendors need to do is just scan the executables for an exact sequence of bytes. This byte sequence is colloquially called the signature of the virus. But the virus writers release newer versions of a virus with minor modiﬁcations. In order to ﬁght that, the signature also includes patterns of a byte string. And the pattern should match family of viruses, without matching legitimate software. A database of such signatures is generally maintained and updated by the AV vendors. Therefore, in response to signature-matching algorithm [12], virus writers began encrypting viruses, so that they would be decrypted at runtime. The main idea was to make sure the AV vendors do not get a standard signature, because S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 120–130, 2010. c Springer-Verlag Berlin Heidelberg 2010

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Fig. 1. Encrypted virus contains a decryption routine, which gets executed first. Once the encrypted part is decrypted, the control is passed on to that part.

every time a new executable is infected, a new key is used. When a user launches an infected ﬁle, the virus decryption routine ﬁrst gets the control and decrypts the virus part. Next, the control is transferred to the decrypted virus code and it executes just like a simple virus. It basically ﬁnds executables and infects them. Whenever it infects a new executable, it makes a copy of virus, encrypts it with a new key and attaches it to the executable. It also attaches the corresponding decryption routine. Some more interesting strategies are implemented by virus writers. Multiple layers of encryption could be used. The direction of encryption/decryption loop could change. But whatever happens, the decryption routine remains constant in an encrypted virus. So, AV vendors have started using that as the signature. Polymorphic viruses [8,9] evolved in the early 90s as a direct threat to these AV algorithms, by mutating the decryption routine for every fresh infection. It has another component called the mutation engine, which generates random decryption routines that change each time a virus infects a new program. So, both the mutation engine and the virus body are encrypted. So, when an infected ﬁle is executed, the decryption routine ﬁrst gains control of the computer, then decrypts both the virus body and the mutation engine. Next, the decryption routine transfers control of the computer to the virus, which locates a new program to infect. Then the virus makes a copy of both itself and the mutation engine and invokes the mutation engine, which randomly generates a new decryption routine. This is diﬀerent compared to the original decryption routine, but does the same task. The virus body and the mutation engine are encrypted. These along with the new decryption routine are attached onto the new program. One of the infamous polymorphic viruses is W32.Mydoom.A@mm, which is a mass-mailing virus and installs a backdoor upon execution. W32.Polip also infects executables and tries to lower security settings of the Anti-Virus installed on the host. Our work addresses this problem of detection and analysis of polymorphic viruses. The presence of these viruses is further more increased by the availability of commercial and free packers available. With these available, all the virus writer needs to do is just write a virus and pack them with diﬀerent packers available and release them. Some of them include Yoda, UPX[29], Armadillo[26], Molebox[30], Obsidium[27], Themida[31], etc.. In this paper the

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terms unpack and decrypt have been used interchangeably, as packing involves encryption most of the time. Previous work in this direction has pointed out that dynamic analysis of the executable yields the best results in detection of polymorphic viruses. Preliminary research showed that most of the current solutions have not been able to detect a lot of polymorphic viruses present. They blacklist some packers by default, without even checking if the packed executable is malicious. We have decided to confront this problem by analyzing the executable running it in an emulator, so that the host machine is not infected during the execution. We have chosen Bochs [21] to be the base emulator, on which we built our system. Bochs (pronounced ”box”), which is a portable x86 and x86-64 IBM PC compatible emulator and debugger. It supports emulation of the processor(s) (including protected mode), memory, disks, display, Ethernet, BIOS and common hardware peripherals of PCs, which we were able to successfully detect self-modifying code present in the viruses, using this system. The reminder of the paper is organized as follows. We present overview of the problem as well as background in Section 2. In section 3, we present the design of the system, justifying the choices made. Section 4 contains the implementation details of the system. We present the results and a brief discussion in Section 5 and conclude in Section 6.

2

Overview

We have taken sample virus codes from VX Heavens [16] and tested those using suite of Anti Viruses in Virustotal [19] and the results have been that some viruses have not been detected by them. The results are shown in Table 1. One of the techniques developed to counter these kind of viruses is the X-ray technique [2]. This technique assumes the encryption technique is XOR, which is true in most of the cases. It works by attempting to ﬁnd the decryption key by using the known decryption algorithm and fragment of decrypted code, which is part of signature. For each key, an equation is written, that expresses this key as a function of the encrypted code, decrypted code and the other keys. Solving the system will produce the correct set of keys required to decrypt the virus. However, this method does not do very well with a lot of viruses. Hence, a more generic algorithm is required. 2.1

x86 Memory Management

The Intel x86 architecture [13] is the most common architecture used in personal computers today. It provides two memory management facilities, namely segmentation and paging. Segmentation can be used to divide a processor’s linear address space (on the x86 architecture: a 32-bit addressable memory space), into several, possibly smaller, isolated address spaces, to isolate code, data and stack of a single program from another, or to isolate diﬀerent programs from one another, or both.

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Table 1. Results of VX viruses on major AVs AV/Malware egypt AntiVir HEUR/Malware Avast clean AVG Win32/Small.CG BitDefender clean CAT-QuickHeal clean eSafe clean eTrust-Vet clean Ewido clean Kaspersky clean McAfee clean NOD32 clean Norman W32/FileInfector Panda clean Sophos clean Symantec W32.Gypet VirusBuster clean

omoikane rit W32/Bakaver.B TR/Crypt.XPACK Win32:Bakaver-B clean Win32.Generic. clean Win32.Bakaver.A clean clean (Suspicious) - DNAScan clean clean Win32/Bakaver clean clean clean Win32.Bakaver clean W32/Bakaver.intd clean Win32/Bakaver.A unknown WIN32 clean clean Suspicious file Suspicious file W32/Bakave-A Sus/UnkPacker W32.Bakaver.A clean clean clean

Paging provides a mechanism to provide virtual memory to the operating system and programs. The basic idea of virtual memory is to provide each program a large, contiguous address space that can even exceed the amount of available physical memory. Paging can also be used to provide some isolation between individual applications. This architecture also provides 4 Control Registers, out of which CR3 is of use to us. It enables the processor to translate virtual addresses into physical addresses by locating the page directory and page tables for the current task. So, every process corresponds to a new value in CR3. We would monitor changes in CR3 to track our process under test. 2.2

Related Work

Current state of research in this direction indicates that emulation is the method which detects malicious behavior better, but the problem is scalability and speed. Following are some of the current implementations which have been successful to some extent. Saﬀron. The ﬁrst version of Saﬀron [3] uses Intel PIN to dynamically instrument the code. It actually inserts instructions in the code ﬂow, allowing control, but it modiﬁes the integrity of the packer. The next version modiﬁes the page fault handler of Windows and traps when a written memory page is executed. It has mixed results with Molebox, Themida, Obsidium, and does not handle Armadillo correctly. It uses dynamic instrumentation, pagefault handling (with a kernel component in the host operating system). But, it modiﬁes the integrity of the code (with dynamic instrumentation) and of the host operating system. It must not work in a virtual machine. The dynamic instrumentation is very slow. The

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memory monitoring of the pagefault handler is coarse-grained and therefore some memory access can go unnoticed. Renovo. Built on TEMU [32], Renovo [4] uses full system emulation to record memory writes (and mark those memory locations as dirty). Each time a new basic block is executed, if it contains a dirty memory location, a hidden layer has been found. But, it is 8 times slower than normal execution. It seems to unpack everything correctly except Armadillo and Obsidium. It seems to only obtain partial results against Themida with the VM option on. It seems to handle most of the unknown packers as well. OmniUnpack. OmniUnpack [5] does not use an emulator-based approach, but rather a realtime monitoring approach. The executable is allowed to run and the system calls are monitored. Based on a heuristic approach, it is decided whether a system call is dangerous or otherwise. It has been proven to detect most of the packers well. It also could combat the problem of multiple levels of packing very well. TTAnalyze. This project based on emulation is currently being continued under the name Anubis [15,17]. Built on the top of QEMU, this supposedly produced better results at detecting malicious code. 2.3

Static Analysis

Static code analysis [14] is the analysis one on programs without actually executing them. This could be either on the source code or on the executable itself. This analysis is used to gather information about a specimen such as its size, cryptographic hash, its format, the compiler used to generate it or low level information gathered by disassembling or decompiling the specimen. Some of the implementation techniques of formal static analysis include: – Model checking: This considers systems that have ﬁnite state or may be reduced to ﬁnite state by abstraction; – Data-ﬂow analysis: This is a technique for gathering information about the possible set of values of objects and variables involved in the specimen – Control-ﬂow graph: A graph is constructed based on how the execution would ﬂow based on the values of diﬀerent variables. – System call analysis: A list of system calls by the program is made and based on that, malicious behavior is detected. Static analysis has several advantages over dynamic approaches. As static methods do not involve executing a potentially malicious specimen, there is a lesser risk of damaging the system that analysis is performed on.

3 3.1

Design Generic Decryption

This is a generic algorithm [2] based on emulation, in which an executable is run in a controlled environment and analyzed for malicious behavior. Whenever

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Fig. 2. System Architecture for the implementation of Generic Decryption Step Step Step Step Step Step Step Step Step Step Step Step End:

1: Executable Starts emulation 2: If the instruction writing to memory 3: Mark memory location 4: Go to Step 2 5: If the instruction branching to a modified area 6: Output an executable with the modified code 7: Statically analyze the output executable 8: Go to End 9: If this is the last instruction 10: Declare no Virus 11: Go to End 12: Go to Step 2

Fig. 3. Algorithm for Generic Decryption

it has to scan a new executable, it loads it into the emulator. Inside it, the ﬁle runs as if it is executing on a normal computer. Meanwhile the hardware of the emulator is being monitored, in order to see how the ﬁle is being executed. As it is being run in a controlled environment, no harm can be done to the host machine. The executable starts running in the emulator, one instruction at a time. For every instruction, we check if it is a memory-write. If so, we mark the addresses written to. These could be potential sites for virus decryption. Once the memory writes are over and a branch to a modiﬁed address is encountered, we try to determine if this is the end of the decryption. When it is detected that decryption is done, an image of the memory of the process is taken and a fresh executable is constructed, which could be statically analyzed by signature-matching algorithm or the like. If it is the last instruction and no malicious branch occurred, then emulation is stopped and declared that the executable is safe. 3.2

Choice of Emulator

Emulators such as JPC [24], QEMU, Simics [22] and Bochs have been considered for the purpose of the work and Bochs has ﬁnally been chosen. JPC is a good

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x86 emulator for DOS executables, but it cannot emulate Windows executables as it doesnt contain the necessary dll ﬁles. QEMU is an open source emulator running on all platforms. It is very fast, as it uses dynamic translation. Simics is a very good emulator with a lot of features, but it is very heavy and we felt that it supports too many features. It has an instrumentation interface which allows the user to deﬁne a set of functions which would be executed at the time of various hardware events such as memory read, memory write, page fault, etc. This has good APIs and helps understand the state of CPU at any point of time. A lot of the x86 optimizations have also been implemented in Bochs, which is very useful because the virus could exploit this diﬀerence and detect the emulation environment. Virtualization was one of the factors we considered while sorting out emulators. It had to be made sure that the emulator does not virtualize the code, i.e. run it directly on the host machine. This causes a potential threat to the host machine and defeats the entire purpose of running the executable in a controlled environment. Finally, we saw that both QEMU and Bochs serve our purpose decently well. Given that work has already been going on in this direction on QEMU, we have decided to implement our system on Bochs.

4

Implementation

Bochs has been compiled in a Windows environment using Cygwin. A small FAT32 hard disk image has been created for the purpose of installing Windows XP. As the operating system is quite huge, Windows XP stripped to the bone edition has been chosen to be used. The size of the CD image of this version 170MB, considerably small compared to the size of Windows XP viz. 700MB. In order to be able to insert the malicious test executables into the installed hard disk image, it has been decided to use WinImage [20]. Some sample polymorphic virus codes were taken from VX Heavens [16], compiled inserted into the hard disk image. The virus codes taken include antares, cjdisease, egypt, omokaine and seraph which could be assembled using Turbo Assembler (TASM). Spein could be assembled using Flat Assembler (FASM) and rit using The Microsoft Macro Assembler (MASM). Then, Bochs code has been taken and conﬁgured to include instrumentation and disassembly. Conﬁguration of Bochs has been quite a cumbersome task. While monitoring the emulation, the main objective is to monitor the execution of the malicious executable. A markup executable has been created, which would be run after the windows boots. When the markup executable is run, it indicates that the monitoring needs to be started now and all the tables are then initialized. For the sake of exclusivity, AAA (ASCII Adjust after Addition) has been chosen and a dummy executable is assembled using Flat Assembler (FASM). Bochs has a neat instrumentation interface with callbacks, wherever major events happen during the emulation. The interface includes branch, TLB control, instruction execution, physical write, physical read, etc... There is a macro

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/configure –enable-repeat-speedups –enable-host-specific-asms –enable-fast-function-calls –enable-instrumentation=instrument/stubs –enable-x86debugger –enable-disasm –enable-trace-cache –enable-vbe -with-rfb –enable-sb16 –enable-ne2000 –enable-cpu-level=6 –enable-sse=2 –enable-pci –enable-acpi Fig. 4. Bochs configuration

BX INSTRUMENTATION deﬁned in the code. If it is enabled, then the instrumentation callback functions are called. This allows the users an abstraction and saves the eﬀort of understanding the code in order to instrument. We have exploited this feature and wrote the instrumentation functions, which would be called. Self-modifying code is the main idea behind polymorphic viruses and detecting this is a major step in detecting polymorphism. The next step would be to extract the executable with the modiﬁed code, rather than the obfuscated code. Self-modifying processes modify the data at a particular address and then branch to it. So, in order to detect such a branch, a list of modiﬁed addresses per process needs to be maintained. A dynamic data structure in the form of a table with a process, characterized by its CR3(a Control Register) and a list of its modiﬁed addresses is created. Then this executable could be analyzed for malware using any of the static analysis techniques. Whenever a context switch occurs, the current CR3 is changed. Whenever a physical write happens, the table is modiﬁed. If the address in the CR3 is already present in the table, then the physical write address is added to the modiﬁed addresses list corresponding to the address in the CR3. And an ascending order of the list is maintained for the purpose of search eﬃciency. Otherwise, an entry is added with the new CR3. When a branch takes place in the process under test, the table is searched for the target branch address. If it is not found, the execution continues as usual. But, if the branch target address is found in the list, then it is a self-modifying code.

5

Results and Discussion

Viruses which have been compiled from VX Heavens have been subjected to analysis under the system developed. The results are being shown in Table 2. As shown in the table, all of the code samples we could get have been detected by our system. The last column in the table indicates the number of antiviruses which detected the malware. As we can see, most of the AVs could not detect it. Future work in this direction would be to expand the base of malware samples and test them using our system and make the system more robust.

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Malware Detection of Unpacking code No. of AVs which detected (16) antares Yes 6 cjdisease Yes 4 egypt Yes 3 omokaine Yes 10 seraph Yes 5 rit Yes 5 spein Yes 3

After detection of a self-modifying code, the immediate task at hand would be to be able to present another executable with the code unpacked, which should be able to run normally. This needs to be statically analyzed for malicious behavior. The whole system then needs to be integrated and automated, so that given an executable; it automatically emulates and scans for malicious behavior. And the startup of windows takes around 20-60 seconds, which is a major bottleneck. Bochs currently does not support restoring from a state of execution for non-liveCD operating systems. Added to that, even the running of Bochs is very slow. It needs to be improved by disabling modules or optimizing the data structures being used. The development of the system on Bochs has been especially diﬃcult because of the instrumentation module being based on callbacks. Every time, a small modiﬁcation has been made to the code, the whole system needed to be compiled again, as it had to be attached to every module. So, this is an area where our future work would have to be directed. The system also needs to be improved so that anti-emulation techniques could be detected and overcome. These techniques try to detect the presence of an emulator and hide themselves. For example, some try to execute something which is not supported by the emulator but is supported by the original processor. Malicious code could also be coded to decrypt only if it is say, second Friday of the year or the like. These would manifest themselves in the real environment but cannot be found out in an emulated environment using generic decryption algorithm. As a whole, Bochs is a good platform for developing this system, but a lot of optimizations for speed-up need to be done before it can be done well.

6

Conclusion

This paper presented an experience report on a malware detector. This has been developed speciﬁcally to combat the problem of Polymorphic Viruses, which unpack themselves at runtime. Having established how the current solutions leave a lot of viruses undetected, we have implemented our system on Bochs, which would detect self-modifying code. Finally, we have presented our results,

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which show 100% detection rate on our test set. In the future, we plan to expand the scope of our test set and automate the system. Further research would include countering anti-emulation tactics of various upcoming viruses.

References 1. Christodorescu, M., Jha, S., Seshia, S.A., Song, D., Bryant, R.E.: Semantics-aware malware detection. In: IEEE Symposium on Security and Privacy (May 2005) 2. Szor, P.: The Art of Computer Virus Research and Defense. Addison Wesley Professional, Reading (2005) 3. Quist, D., Valsmith.: Covert Debugging: Circumventing Software Armoring Techniques. Black Hat Briefings USA (August 2007) 4. Kang, M.G., Poosankam, P., Yin, H.: Renovo: A hidden code extractor for packed executables. In: Proceedings of the 5th ACM Workshop on Recurring Malcode, WORM (October 2007) 5. Martignoni, L., Christodorescu, M., Jha, S.: OmniUnpack: Fast, Generic, and Safe Unpacking of Malware. In: 23rd Annual Computer Security Applications Conference, ACSAC (2007) 6. Royal, P., Halpin, M., Dagon, D., Edmonds, R., Lee, W.: PolyUnpack: Automating the Hidden-Code Extraction of Unpack-Executing Malware. In: 22nd Annual Computer Security Applications Conference, ACSAC (2006) 7. Konstantinou, E.: Metamorphic Virus: Analysis and Detection Technical Report. RHUL-MA-2008-02, Royal Holloway, University of London (2008) 8. Understanding and Managing Polymorphic Viruses. The Symantec Enterprise Papers (1996) 9. Szor, P., Ferrie, P.: Hunting for Metamorphic. In: Virus Bulletin Conference (2003) 10. Tropeano, G.: Self-Modifying Code. Code Breakers Journal (2006) 11. Ludwig, M.: The Giant Black Book of Viruses. American Eagle Publications, Inc. (1995) 12. Virus-Antivirus Co-evolution. Symantec Research Labs (2001) 13. IA-32 Intel Architecture Software Developer’s Manual. Intel Corporation (March 2006) 14. Christodorescu, M., Jha, S.: Static analysis of executables to detect malicious patterns. In: Proceedings of the Usenix Security (2003) 15. Bayer, U., Kruegel, C., Kirda, E.: TTAnalyze: A Tool for Analyzing Malware. In: 15th Annual Conference of the European Institute for Computer Antivirus Research, EICAR (2006) 16. VX virus source codes, http://vx.netlux.org/src.php 17. Anubis, http://analysis.seclab.tuwien.ac.at 18. Norman SandBox Information Center, http://www.norman.com 19. Online Virus Scanner Suite, http://virustotal.com 20. WinImage, http://www.winimage.com/winimage.htm 21. Bochs emulator, http://bochs.sourceforge.net 22. Simics, http://www.simics.net 23. QEMU, http://www.qemu.org 24. JPC, http://www-jpc.physics.ox.ac.uk/home_home.html 25. Yoda’s Crypter, http://yodap.sourceforge.net/ 26. Armadillo, http://www.siliconrealms.com/ 27. Obsidium, http://www.obsidium.de

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A. Kasina, A. Suthar, and R. Kumar PECompact2, http://www.bitsum.com/ UPX, http://upx.sourceforge.net/ Molebox Pro, http://www.molebox.com/ Themida, http://www.oreans.com/ TEMU: The BitBlaze Dynamic Analysis Component, http://bitblaze.cs.berkeley.edu/temu.html

Sensitivity Measurement of Neural Hardware: A Simulation Based Study Amit Prakash Singh1, Pravin Chandra2, and Chandra Shekhar Rai3 1,3 University School of Information Technology Guru Gobind Singh Indraprastha University, Delhi – 110403, India 2 Institute of Informatics and Communication, University of Delhi, South Campus, Benito Juarez Marg, Delhi – 110021, India [email protected], [email protected], [email protected]

Abstract. Artificial Neural Networks are inherently fault tolerant. Fault tolerance properties of artificial neural networks have been investigated with reference to the hardware model of artificial neural networks. Limited precision of neural hardware lead to study the sensitivity of feedforward layered networks for weight and input errors. In this paper, we analyze the sensitivity of feedforward layered network. We propose a framework for the investigation of fault tolerance properties of a hardware model of artificial neural networks. The result obtained indicates that networks obtained by training them with the resilient back propagation algorithm are not fault tolerant. Keywords: Artificial Neural Network, Fault model, Sensitivity Measurement.

1 Introduction An Artificial Neural Network (ANN) is an information-processing paradigm that is inspired by the biological nervous system, i.e., the human brain [2]. The key element of this paradigm is the novel structure of the information processing system. It is composed of large number of highly interconnected parallel processing elements (neurons) working together to solve specific problems. An ANN is configured for specific applications, such as pattern recognition or data classification, through learning process. Artificial neural network have the potential for parallel processing due to the implementation on Application Specific Integrated Circuit (ASIC) [4] or Field Programmable Gate Array (FPGA) [5][6]. The input-output function realized by neural network is determined by the value of its weights. The sensitivity of a neural network’s output to the input and weight perturbation is a fundamental issue with both theoretical and practical view of neural network research. In the case of biological neural network, tolerance to loss of neurons has high priority, since a graceful degradation of performance is very important for survival of the organism. Fault tolerance measures the capacity of neural network to perform the desired task under given fault condition. It also maintains their computing ability when a part of the network is damaged or removed. In [9], the study of fault tolerant S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 131–141, 2010. © Springer-Verlag Berlin Heidelberg 2010

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Fig. 1. Architecture of FFANN

properties of the neurons has been reported for partial fault tolerance by replication and training and the assertion is that Triple Modular Replication (TMR) leads to a fault tolerant network. Fault tolerances of ANN have been studied in [1][19]. Fault tolerance of ANN may be characterized/categorized on the following aspects: (i) (ii) (iii)

Neuron error: Node stuck at zero Weight error: Weight stuck at zero Input pattern errors: injecting noise during the training phase.

Sensitivity of classification problems has been studied in [19]. The probability of error propagation is evaluated with respect to single neuron’s output. This error was evaluated with respect to weight error in the network. Sensitivity of MADALINE network was studied in [31]. Technique to remove redundant input from the network has been given in [32]. The method of selecting optimal inputs proposed in [32], is to analyze monotonic increasing and decreasing characteristics of weight and detect redundant inputs for pattern recognition. In [32], the author has studied the sensitivity of input for the trained network and removed the redundant inputs for pattern recognition. Hardware model(s) for artificial neural network(s) has (have) been widely implemented by various researchers for applications like image processing and controllerbased applications. In recent years, many approaches have been proposed for the implementation of different types of neural networks, such as multilayer perceptron [8], Boltzmann machine [13] and other hardware devices [11]. The emphasis of the fault tolerance investigation of ANNs has been focused on the demonstration of fault-intolerant behavior of these networks and/or the design of paradigms for making a network fault tolerant to specific faults. A complete modeling of neural faults is still lacking. This paper aims to present a set of fault models for these networks. In this paper, Section 2 discusses the related work. Section 3 explains definition of sensitivity, Section 4 discusses weight and node faults. Section 5 describes metrics for measurement of faults. Section 6 discusses the experiments and the obtained results for the fault model while conclusion is presented in Section 7.

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2 Related Works With the widespread usage of the chip-based device of the ANN as controller [11], it has become imperative to study the behavior of these circuits under various faults, i.e., the study of their fault tolerance behavior must be undertaken. The available literature on the fault-tolerance behavior of feedforward ANNs may be summarized as: 1. 2. 3. 4.

Demonstration of fault-intolerant-tolerance to specific faults [9][14]. Regularization during training [16]. Enhancement of fault tolerance by design of algorithms for embedding faulttolerance into the network, during training [17][20]. Redesigning the network architecture (after training) by replication of nodes and their associated weights and usage of majority voting [3][18].

In the literature, a complete study of fault models for ANN is still lacking. In this paper, we propose a set of faults for the characterization of neural faults. Piuri [14] asserts that the network can not be considered to be intrinsically fault tolerant. Edwards and Murray [16], use the regularization effect of weight noise to design a fault tolerant network. Chin et. al. [20] demonstrate a training algorithm that uses weight value restriction (and addition of additional nodes), fault injection during training and network pruning to achieve a fault tolerant network, while [3] and [12] redesign the trained network to achieve a fault tolerant network. Chu and Wah [35] has introduced the fault tolerant neural network with hybrid redundancy that comprised spatial redundancy, temporal redundancy, and coding. Phatak and Koren [18] devised measures to quantify the fault tolerance as a function of redundancy. In [18], a method has been presented to build fault tolerant neural networks by replicating the hidden nodes, which exploited the weighted summation operation performed by the processing nodes to overcome faults. Bolt et. al. [21] indicated that the network trained by backpropagation algorithm seldom distribute information to connection weights uniformly. Due to this few connections are key components of the computation, whose failure will cause great loss to the networks. In [36] a technique is presented to remove a node, that does not significantly affect the network output, and then added new nodes that shared the load of the critical nodes in the network to ensure that desired performance could be obtained. A method to improve the fault tolerance of backpropagation networks is presented in [37], which restrained the magnitudes of the connections during training process. Hammadi and Ito [17] demonstrate a training algorithm that reduces the relevance of weight. In [17], relevance of weight in each training epoch was estimated, and then decreases the magnitude of weight.

3 Definition of Sensitivity In sensitivity analysis, evaluation of the network can be done with reference to various input parameters of neural networks which affect performance of output of the network. A different definition of sensitivity in BP-networks has been suggested in [33] [34]. Sensitivity analysis is based on the measurement of the effect that is observed in the

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output yk due to the change that is produced in the input xi. Thus, the greater the effect observed in the output, the greater the sensitivity present with respect to input. Obtaining the sensitivity matrix [30] by the calculation of the partial derivatives of the output yk, with respect to the input xi , i.e.

S ik =

d ln y k d ln x i

(1)

(2) xi dy k y k dxi Eq.1 constitute the sensitivity analysis of the network, where Sik represents the sensitivity of the percentage change of the output yk due to percentage changes in the input variable xi (it is to be noted that the form of the expression (1) and (2) is a point measure of the sensitivity, that is sensitivity at the point xi). This expression is also known as the condition number. If the value of this number is larger than 1 at any point, then the perturbation at the point xi are amplified at the output while if it is less than 1 it is damped. That is, if this measure value is less than or equal to 1 (in general less than or near 1), we may call the network stable else unstable. The values for the sensitivity matrix [30] do not depend only on the input-output but it also depends on the value stored in a hidden node and layer connection. It also depends on the activation function of the neuron of the hidden layer. Since different input pattern can provide different values for the slope, the sensitivity is generally found by calculating Mean squared error (MSE) and Mean absolute percentage error (MAPE). The same procedure is required to be followed for the study of weight sensitivity due the fact that each input pattern provides different new weight updated value. =

4 Weight and Node Faults The removal of the interconnected weights in a network and the occurrence of stuckat faults in neurons are of two types that can serve as a test bed for the robustness of neural networks. The robustness of a backpropagation trained multilayer network to remove weights to/from the hidden layer and the influence of redundancy in the form of excess hidden neurons has been investigated in [14]. The effect of “Stuck-at-0” and “stuck-at-1” neurons on the solutions found in recurrent optimization networks is investigated in [26]. These are the faults/errors that affect the weights of the network. Following types of faults / errors are defined: (a) Weight stuck at zero (WSZ): This fault corresponds to an open fault or connection breakage between two nodes. (b) Weight stuck at maximum/minimum (WSMa/ WSMi): Weight stuck at a value of ±|W|max, where |W|max is the maximum magnitude weight in the system.A –ve weight will be pushed to −|W|max while a +ve weight will be pushed towards +|W|max and vice-versa. This allows us to model weight faults at substantially large values, which may or may not lead to node hard faults of the type NSZ or NSO depending on the weight interaction with the other weights leading to the same node as the faulted weight.

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(c) White noise in weights (WNW): The presence of white noise (zero mean gaussian with finite variance) may be taken as a reflection of thermal noise or circuit degradation. This noise is different from node output noise as it is not correlated in weights leading from the same node. There are two types of node faults namely hidden node faults and output node faults. Hidden node faults: These are the errors, which affect hidden nodes. Following types of errors are defined:

(a) (b)

(c)

Node stuck at zero (NSZ): The node output is stuck at zero. Node stuck at one (NSO): Nodes produce an output equal to ±1 (assuming that the tangent hyperbolic function, f=tanh(x) is used as the activation function), if any other activation is used, then these two values should be modified to reflect the two limiting values of the activation function used. White noise in node (WNN): The presence of additive gaussian noise in the nodes output with zero mean and fixed standard deviation. Thermal noise (then it can be parameterized by the temperature) and degradation of circuitry in time can lead to this type of noise in a FFANN hardware implementation.

Output node faults: The output node faults can be described in an analogous manner to the input node faults but only the noise contamination effects are non-catastrophic and may be considered.

5 Fault Metric To measure the effect of faults/errors on the network output enumerated above, the following types of error/fault/parameter sensitivity measures may be defined: The mean squared error (MSE) and the mean absolute percentage error (MAPE) should be used to measure the effect of all types of faults if the output of the FFANN is real. The percentage of misclassification is suggested as a measure of fault/error, for classification problem. Based on eq. 1, we propose a measure of sensitivity to network parameter fluctuation / changes as a maximum of the condition number over the complete parameter set and the input space as: ⎛ x Δy ⎞ ⎟⎟ Sensitivity = max overfault ⎜⎜ ⎝ y Δx ⎠

(3)

Where x is the parameter value without error/faults, ∆x is change in the parameter value due to error, y is the network output without error/faults and ∆y is change in the network output due to faults.

6 Experiments and Results A small experiment was conducted to demonstrate the applicability of proposed faults. Only a selected faults of Section 4 are investigated herein, specifically the

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investigated faults are NSZ, NSO (-1 and +1) and WSZ. (The choice of faults is directed by the small size of the network used and limited space consideration). Networks were trained for the following function approximation tasks [22]. y = sin( x1 × x 2 )

;x1,x2 uniform in [-2,2]

Fn1: Fn2:

y = exp( x1 × sin(π × x 2 ))

Fn3:

a = 40 × exp(8 × ( x1 − 0.5) + ( x 2 − 0.5) )

; x1,x2 uniform in [-1,1] 2

2

b = exp(8 × ( x1 − 0.2) 2 + ( x 2 − 0.7) 2 ) c = exp(8 × ( x1 − 0.7) 2 + ( x 2 − 0.2) 2 ) y = a/(b+ c) Fn4:

;x1,x2 uniform in [0,1]

y = 1.3356[1.5(1 − x1 ) + exp(2 x1 − 1) sin(3π ( x1 − 0.6) + exp(3( x 2 − 0.5)) sin( 4π ( x 2 − 0.9) 2 )]

;x1,x2 uniform in [0,1]

The data set for ANN are generated by uniform sampling of the domain of definition of the functions. The network consists of two input, one hidden layer and one output node (Figure 1). The detail of the architecture used is summarized in Table 1. The architecture was identified by exploratory experiments where the size of the hidden layer was varied from 5 to 30 (that is, the number of nodes in the hidden layer were varied from 5 to 30 in steps of 5) and the architecture that give the minimum error on training was used. All the hidden nodes use tangent hyperbolic activation function while the output nodes are linear. Table 1. Architecture of network used

Sr. No. 1. 2. 3. 4.

Function Fn1 Fn2 Fn3 Fn4

Inputs 2 2 2 2

Hidden nodes 25 15 20 10

Output nodes 1 1 1 1

No. of weight 101 061 081 041

The resilient propagation (RPROP) [23] algorithm as implemented in MATLAB 7.2 Neural Network toolbox is used with the default learning rate and momentum constant. 200 random samples were generated from the input domain of the functions for training purposes. 5000 epochs of training was conducted for each problem. For the purpose of evaluation of the fault – tolerance behavior of these networks, after the training is complete, the network output of the faulty networks is compared against the output of the network without the fault. The results of the fault tolerance experiments are summarized in Table 2-7. Various parameters of the Table 2 are defined as minimum (MIN), maximum (MAX), average (MEAN), MEDIAN, standard deviation (STD).

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Table 2. Node stuck at zero summary data

Fault (Metric) NSZ (MSE) MIN MAX MEAN MEDIAN STD NSZ (MAPE) MIN MAX MEAN MEDIAN STD

Fn1

Fn2

Fn3

Fn4

0.0243 1.2944 0.3688 0.3149 0.2984

0.0002 0.6485 0.2380 0.2414 0.1874

0.0052 2.8141 0.9577 0.8680 0.8350

0.1154 2.6287 0.7740 0.5924 0.7622

101.2557 721.1044 345.3158 340.0283 148.2128

01.5365 83.0443 43.7685 48.4535 23.0553

03.5306 82.7211 41.7659 42.3984 24.5382

024.1584 125.7720 061.4496 058.3251 029.2230

From the Table 2, it may be inferred that at least for these 4 function approximation tasks, the NSZ fault is critical and the network does not demonstrate tolerance to NSZ fault. Table 3. Node stuck at one (to +1) summary data

Fault(Metric) Fn1 NSO(=1) (MSE) MIN 0.0020 MAX 3.7407 MEAN 0.7948 MEDIAN 0.4293 STD 0.9852 NSO(=1) (MAPE) MIN 0002.7154 MAX 1225.7000 MEAN 0395.1850 MEDIAN 0328.7025 STD 0366.2974

Fn2

Fn3

Fn4

0.0000 2.6435 0.7652 0.4977 0.8425

0.0000 5.6973 1.4181 0.3287 1.7868

00.0000 11.1533 01.6378 00.4312 03.4621

0000.0000 0167.5369 0063.6947 0047.4382 0059.2644

00.0000 90.8748 32.7760 19.3168 33.1655

000.0000 263.2493 056.1995 027.4509 083.2380

From the summary data for NSO(=1) (that is the hidden node is saturated to +1)(Table 3), it may be inferred that this fault is of a critical nature and network is not tolerant to this fault. For Fn2, Fn3, and Fn4 the minimum value for the MSE as well as MAPE being zero demonstrate that at least for some nodes, where this fault occurs, the fault is tolerated.

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Fault (Metric) Fn1 NSO(=-1) (MSE) MIN 0.0250 MAX 5.3024 MEAN 0.7898 MEDIAN 0.5616 STD 1.1027 NSO(=-1) (MAPE) MIN 0017.2718 MAX 1463.6000 MEAN 0375.7986 MEDIAN 0303.2368 STD 0356.5420

Fn2

Fn3

Fn4

0.0000 1.4355 0.3111 0.1581 0.4346

00.0030 11.5123 02.7514 01.8399 03.0860

0.2680 3.7417 1.7312 1.7744 1.1655

000.2999 122.7687 036.1630 027.9786 036.6866

001.2481 166.1653 056.8794 049.3679 042.7195

016.5243 129.7886 078.4151 090.2752 044.6207

From the summary data for NSO(=-1) (that is the hidden node is saturated to -1) (Table 4), it may be inferred that this fault is of a critical nature and network is not tolerant to this fault. Table 5. Weight stuck at zero summary data

Fault (Metric) WSZ (MSE) MIN MAX MEAN MEDIAN STD WSZ (MAPE) MIN MAX MEAN MEDIAN STD

Fn1

Fn2

Fn3

Fn4

0.0000 1.8693 0.2552 0.1381 0.3347

0.0 1.0747 0.1607 0.0569 0.2154

0.0 4.7648 0.8477 0.3580 1.0661

00.0 10.1729 00.8054 00.2562 01.7184

000.3549 727.0390 187.5565 137.0938 173.5395

00.0 83.0443 24.8133 14.2932 24.7697

00.0 82.7211 26.1094 19.2399 23.6380

000.0 256.9629 041.6567 026.6869 050.4999

From the summary data of WSZ (Table 5), it may be inferred that, this fault is of critical nature and network is not tolerant to this fault. For Fn2, Fn3, and Fn4 the minimum value for the MSE as well as MAPE being zero demonstrate that at least for some weight, where this fault occurs, the fault is tolerated. Table 6. Sensitivity (equation 3) to input perturbation

Sensitivity to input 1st Input 2nd Input

Fn1 089.1330 100.6210

Fn2 1.8401 2.3608

Fn3 08.5083 10.6107

Fn4 11.4600 09.2138

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From the summary data of Table 6, it may be inferred that the network is sensitive to input perturbation, as the sensitivity values are larger than one. Table 7. Sensitivity (equation 3) to weight perturbation

Sensitivity to weight

Fn1 249.6252

Fn2 2.8223

Fn3 8.4638

Fn4 23.1517

From the summary data of Table 7, it may be inferred that the network is sensitive to weight perturbation as the sensitivity value are larger than one. From the results obtained in Table 2-7, it is apparent that these networks trained using the RPROP[23] algorithm can not be called fault tolerant to the faults reported and moreover these networks are highly sensitive to input and weight fluctuation/perturbation.

7 Conclusion This paper has introduced the concept of sensitivity analysis as a useful technique for fault tolerance studies. We propose the usage of the condition number as a measure of sensitivity. Since the condition number effectively measures whether the perturbation in the inputs and / or network parameters is amplified or damped during the network computational process, it is an effective measure of the fault – tolerance behavior of the network. From the experimental results obtained, we may assert that the networks obtained have high sensitivity (measured either by the MSE, MAPE, or the condition number), and as a result are not tolerant to faults on the whole. But, from the obtained results we may also infer that faults in some weights and /or nodes are well tolerated by the network.

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An Approach to Identify and Manage Interoperability of Class Diagrams in Visual Paradigm and MagicDraw Tools Gaurav Bansal, Deepak Vijayvargiya, Siddhant Garg, and Sandeep Kumar Singh Department of CSE and IT, Jaypee Institute of Information Technology A-10 Sector 62 Noida India {gauravbnsal,deepakvijay.1988,siddhant.88}@gmail.com, [email protected]

Abstract. Unified Modeling language (UML) is a standard language for specifying, visualizing, constructing and documenting the artifacts of software systems. UML consists of several design diagrams such as State diagram, Class diagram, Use case diagram, Activity diagram, Sequence diagram etc. These diagrams are designed using many diverse tools such as Visual Paradigm, MagicDraw, ArgoUML, Rational Rose etc. These tools store model information (both diagram and content information) in XMI files. These tools use different tags to store model information in XMI files. Due to the difference in tags of XMI files used by these tools, interoperability in these tools becomes difficult. Interoperability of modeling tools is important because it can make these tools reusable and extensible. This paper reports on an approach and algorithm for identifying and resolving the interoperability issue at content information level of UML Class diagrams between Visual Paradigm and MagicDraw. Keywords: XMI, XMI, UML, Parser, Visual Paradigm, MagicDraw, Class Diagrams.

1 Introduction Unified Modeling Language (UML) is a standard language for exchanging information between different applications [2]. UML is used for specifying, visualizing, constructing and documenting the software systems. UML is a collection of best engineering practices to model large and complex systems. UML is not dependent on a particular programming languages and development processes. In today’s world, UML is a factual standard for modeling software applications. UML modeling consists of many design diagrams such as class diagram, use case diagram, sequence diagram, activity diagram, component diagram and deployment diagram etc. These diagrams can be modeled in many tools such as Visual Paradigm, MagicDraw, ArgoUML, Rational Rose etc. These design tools provide support for editing, viewing, storing, and transforming designs. XMI is used as base method to import and export UML models. These tools use different tags in XMI file to represent these modeling diagrams. Due to different tags in XMI files of tools, a model S. Ranka et al. (Eds.): IC3 2010, Part II, CCIS 95, pp. 142–154, 2010. © Springer-Verlag Berlin Heidelberg 2010

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developed in one tool can’t be used by other tools. Lack of interoperability between these tools reduces reusability and extensibility of these design diagrams [4], so to make these models interoperable, interoperability of these tools is required. The issue of interoperability also needs to be handled due to fact that organizations often use different tools for system development which increases need of exchanging models between these tools. These tools are developed by different vendors with their own specifications. In paper [4], it is also reported that interoperability helps in coordinating software artifacts, model reuse and model extension. Thus in this paper, we have chosen to address interoperability issue between two UML tools, Visual Paradigm and MagicDraw. We propose an approach and algorithm for identifying and resolving the interoperability issue at content information level of UML Class diagrams between Visual Paradigm and MagicDraw. For this we have taken Class diagram as it is very useful building block in object oriented modeling. Class diagram serves as graphical documentations of the software system. Class diagram represents the static model of the system in terms of Attributes, behaviors and relations. XMI files of these tools store class diagram elements in different tags. In the past, authors in paper [4] have proposed a XMI parser for interconversion of UML diagrams, but their work was limited only to the proposal of the parser. The authors proposed a Parser which takes an XMI file of a model tool, parse it, and return the XMI file for the destination model tool, but authors did not elaborated on the parser. They have not discussed working of parser parts. This paper unlike paper [4] reports on an approach on interoperability of class diagrams of Visual Paradigm and MagicDraw modeling tools. The conversion process is carried out using XML and parser. This Paper includes some case studies in section 4, which are conducted to find out issues in interoperability. In this paper we discussed the entire parser, working of each part of parser, pseudo code for parser and algorithm to overcome interoperability issues. We have also implemented the parser. We extended the parser; to find the data from the XMI file without having any prior knowledge of tool to which XMI file belongs. In next section, we will discuss problems and issues related to interoperability in context of UML models and related approaches on model interoperability. Section 3 presents, Issues contributing to interoperability of UML tools. Section 4 presents, the process to identify lost information during interconversion, and algorithms. Section 5 contains results on algorithms. Section 6 gives conclusion and future work.

2 Problems and Issues Relating to Interoperability in Context of UML Tools This Section shows that interoperability is the most important issue for organizations. Many approaches were given but XMI plays an important role in model interchange. This section, further describes the relation of XMI version with successful and unsuccessful exchange of model diagrams. UML is a generalized modeling language for software engineering, managed and created by object management group. UML provides a standard way to visualize a system's architectural blueprints, including elements such as actors, business processes, logical components, activities, programming language statements, database schemas, and reusable software components. Although, UML consists of many design diagrams but class diagram is one of the mostly used design diagrams. Class diagrams

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are being used both for general modeling and detailed modeling. Classes in a Class diagram represent main objects and interactions in the application. The development and maintenance of Class diagrams is a distributed activity. UML modeling of class diagrams can be done using various tools such as Visual Paradigm, MagicDraw etc. These tools use different parameters to represent these models, so it is very important to interchange model information between these different tools; therefore, we concentrate on interoperability of UML class diagrams between Visual Paradigm and MagicDraw tools. To the best of our knowledge, we found that there is no combination of tools that supports a two-way interchange (Interchange of a model between two tools is said to be successful if all model information other than presentation information is preserved during the transfer); not even indirectly using a third tool. This is due to the fact that, different tools use different version of XMI or UML. XML Metadata Interchange (XMI) is basic concept for model interchange between various tools. We examined that to what extent XML is able to support exchange of business documents. XMI is widely used approach to make tools interoperatable. XMI enables organizations to use XML as a common fundamental language, which meet their requirements, without losing compatibility. XMI, developed by Object Management Group (OMG) is a independent format for saving and loading UML models [4]. It is an extensible Markup Language (XML) based document that represents model elements and their information in an interchangeable format [5]. XML family consists of XSL (Extensible Style sheet Language). XSLT allows definition of style-sheets for transforming from one XML vocabulary and structure into another [1]. XSL consists of three technologies- XSL- FO; an XML based formatting language, XSLT; a language for defining transformations of XML data, and XPath; a pattern language for addressing elements of XML documents [2]. On conversion, using same XMI version there is both successful and unsuccessful transfer of model information from source tool to destination tool. There are also some successful combinations for exporting and importing XMI files with tools supporting same version of UML [3]. Different versions of both UML and XMI lead to a large number of possible combinations, some of these combinations are incompatible. A contributing factor is that tools supporting different XMI versions cannot interchange their XMI documents. None of the tools analyzed has adopted the latest version of XMI (2.0) [3]. When a conversion is done using XMI version 1.x layout information is not preserved during interchange of the model. Issues mentioned above, increases need of interoperability of class diagrams between design models. Tool interoperability is implemented using XMI. Unfortunately, there is a loss of properties of the design when transforming between UML and XMI due to the compatibility of different versions of UML, XMI and add-on proprietary information. Authors studied interoperability of UML modeling tools by assessing the quality of XMI documents representing the design [4].

3 Factors Contributing to Interoperability of UML Tools In our survey, we found that when interconversion is done between various tools, there are many factors which cause information loss. These factors can be described as either use of different versions of XMI or UML, different ways for representation of XMI tag. We elaborate on these factors in the following subsections.

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3.1 Use of Different XMI Versions There are different UML tools (eg. Visual Paradigm, Rational Rose, MagicDraw, ArgoUML), which uses different versions of XML. Some of these tools uses XML version 1.0, some uses XML version 1.1 and some uses 2.1. Due to incompatibility of different versions of XML, when a class diagram is operated between different tools, there is a loss of properties of the design attributes, which reduces reuse of class diagrams. Class diagram shown in Fig 1 is exported among different tools to observe the possible problems due to different XMI versions, results are listed below: When diagram in Fig 1 is exported from Argo and imported by Rose then cardinality of relations is lost [3] as shown in Fig 2 (a). When diagram in Fig 1 is exported from Rose1.1 and imported by Artisan then all generalization relations are lost during this exchange as shown in Fig 2 (b). When diagram in Fig 1 is exported from Rose1.1 and imported by Artisan or Poseidon and vice-versa then all association relations are lost as shown in Fig 2 (c). When diagram in Fig 1 is exported from Fujaba and imported by Artisan then all relations are lost as shown in Fig 2 (d). 3.2 Use of Different Version of UML Tools supporting different versions of UML also encounter problems when exported form source tool to destination tool. A tool supporting an earlier version of UML may have problems importing documents exported from a tool supporting different version of UML [4]. Few combinations for both successful and unsuccessful conversion is listed in table 1 and 2. By successful Interchange of a model, we mean that all model information other than presentation information is preserved during the transfer. Table 1. Rational Rose enterprise edition 7.0 with the XMI patch [4]

Fig. 1. Class Diagram used for conversion

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(a)

(b)

(c)

(d)

Fig. 2. Class Diagrams after conversion [3] Table 2. ArgoUML 0.22 and 0.44 [4] UML/XMI 1.3 1.4 2.0

1.0 Y Y N

1.1 Y Y N

1.2 N Y N

Version 0.22 0.24 0.24

3.3 Different Methods for Representing a XMI Tag Import and export of the same XMI elements can be done in different ways. As XML is a extensible markup language, vendors can create their own tags to represent the model information. As an example shown below, to represent a class in class diagram, Visual Paradigm uses ‘ownedMember’ tag whereas MagicDraw uses ‘packagedElement tag’. In addition, vendors sometimes use their proprietary forms of export that cause the information loss while importing to other tools. Tag used for class in Visual Paradigm…..

isActive="false" isLeaf="false" xmi:id="5fDSX8SFYECkfQST"

Tag used for class in MagicDraw….. In next section, we describe an algorithm to handle class diagram interoperability in Visual Paradigm and MagiDraw.

4 Identifying and Managing Class Diagram Interoperability in Visual Paradigm and MagicDraw Tools UML diagrams serve as graphical documentations of the software system. The interoperability of UML modeling tools is important in supporting the class diagram

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exchange. UML have the semi-formal nature, due to this nature it is not possible to apply rigorous automated analysis or to execute a UML model in order to test its behavior. Due to these reasons, formalization of Class diagrams is now a dominant area of research, but there is no tool available to interconvert the Class Diagrams of source tools to the destination tools. Therefore, we propose to design a tool which allows user to Identify and Resolve interoperability issues occurred in exchanging Class diagram information between Magic Draw and Visual Paradigm tools. 4.1 Process to Identify Information Loss during Interconversion First step towards handling interoperability is to identify the places where information loss occur while exporting/importing class diagrams among various tools. To indentify the interoperability of different tools, we worked on several case studies. With every case study, we made a simple Class diagram using different UML tools such as Visual Paradigm, Magic draw and ArgoUML. First two tools use XMI version2.1 where as the last one uses version1.1. We did comparisons in these XMI files and found that XMI tags used for representation of diagrams is different for all tools. ArgoUML file uses the older version of XMI, which includes the older tags for representation of diagram, where as the tags are different in other tool’s XMI files. We concentrate on Visual paradigm and MagicDraw for our further work. After above comparison, we have made another class diagram (Fig3) which includes almost all relationships in a class diagram. Then, we exported this diagram in XMI format using Visual Paradigm and MagicDraw. After this, we compared the tags used to represent the model information. We found these problems:-

Fig. 3. Class Diagram used for conversion study

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When we imported the XMI of source tool in destination tool there were some common information loss, both the tools were not able to show the diagram, aggregation and composition relations, these relations were shown as simple association relations. Dependencies were also lost. When we imported XMI file of Visual Paradigm in MagicDraw these relation were imported and visible but when we imported XMI file of MagicDraw in Visual Paradigm only class name with attribute was visible and relations can be found in class specification but as association relation. We also found that, Visual Paradigm uses different Diagram elements in XML files to represent the diagrams but these tags are not used in Magic Draw. Due to this problem, Magic Draw gives following error: Element of type "uml: DiagramElement" cannot be created. and so on….. Fig. 4. XMI file for Visual Paradigm And so on…….. Fig. 5. XMI file for MagicDraw

Fig 4 shows pattern of XMI file generated by Visual Paradigm and Fig5 shows pattern of XMI generated by MagicDraw.

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4.2 Process to Manage Information Loss during Interconversion As interoperability is the very important aspect for the inter-organizational network, we tried to find out a way to make the different tools interoperable. Major problem behind the interoperability is use of different versions of UML and XMI. It decreases the compatibility of Class diagrams across the network. Therefore, we concentrate on this problem and for this, we use the latest versions of both UML and XMI in our operation tools (MagicDraw, Visual Paradigm). Latest version of XMI is 2.1 and UML is 1.4. Our work is the extension of one of the papers we surveyed [4]. In previous work, authors took ArgoUML and Rational Rose for their studies and proposed the parser. We have taken Visual Paradigm and Magic Draw tools for our study and also extended the parser. Our parser also extracts the data from the XMI file, which can be used to find out the information without availability of corresponding tool. In addition to this, we implemented complete parser, which is not reported in paper [4]. For this, we have used the DOM parser. To make these tools interoperable, we are using XMI file of source tool as a input to the parser and after parsing the tags and making tags compatible to the destination tool(by changing tags ), we get another XMI file as output of the parser. Generated XMI file is compatible with the destination tool. Parser

XMI Reader Source tool

Parsed XMI

For Destination Tool

Generated XMI

XMI Writer Fig. 6. Work Flow of Implementation [4]

Fig 6 shows the workflow of the system required for making the UML diagrams reusable by converting them to XMI, parse the XMI file, and make them compatible for interpretation by other tools. 4.2.1 Methodology to Manage Interoperability Source Tools, Destination Tools: Visual Paradigm, MagicDraw. Pseudo code involves following steps: 1. Generate XMI file for Class diagram of source tool. 2. Import the file to the parser. 3. Collect all classes, attributes, their data types and relations between classes. 4. Store these values to a temporary file. 5. Find corresponding tags for XMI of destination tool. 6. Change the tags according to the representation of that tag in the destination tool’s XMI file. 7. Remove temporary file. 8. Export newly created XMI file to destination tool.

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4.2.2 Algorithm for the Parser to Collect Data from XMI File of Source Tool Parse (XMI file name) Range

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