Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs

Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs

Jesús Ruiz-Amaya • Manuel Delgado-Restituto Ángel Rodríguez-Vázquez

Device-Level Modeling and Synthesis of HighPerformance Pipeline ADCs

2123

Jesús Ruiz-Amaya Instituto de Microelectrónica de Sevilla C/ Américo Vespucio Isla de la Cartuja 41092 Sevilla Spain [email protected]

Ángel Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla Universidad de Sevilla and CSIC C/ Américo Vespucio Isla de la Cartuja 41092 Sevilla Spain [email protected]

Manuel Delgado-Restituto Instituto de Microelectrónica de Sevilla C/ Américo Vespucio Isla de la Cartuja 41092 Sevilla Spain [email protected]

ISBN 978-1-4419-8845-4 e-ISBN 978-1-4419-8846-1 DOI 10.1007/978-1-4419-8846-1 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011930262 © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

To the memory of Fernando, Jesus’s beloved brother

Preface

Device-level modeling and synthesis of high-performance pipeline ADCs Digital computing and signal processing are present in most current communications systems. The proliferation of these systems, compared with their analog counterparts, is a result of their robustness to supply and processing variations, their low sensitivity to noise and, above all, the improvements in their technological scaling [1–5]. These properties have made the design and test automation of such systems easier, favouring the development of Computer-Aided Design (CAD) tools and automatized methodologies. In spite of the benefits of digital processing, a communications system cannot be fully digital as the actual signals are inherently analog and as a result, there is a need for circuits which can interface with the digital world. Analog-to-Digital Converters (ADCs), which acquire and digitize the signal, fall into the category of circuits required. As Fig. 1 shows, numerous approaches can be found, depending on the field of application of the converter. The design of these analog circuits is a major challenge for designers due to rapidly-evolving digital systems, which require increasingly accurate and fast converters, while the current trend to integrate them into adverse digital technologies is also a contributing factor. Hence the importance of developing design methodologies and CAD tools [6–16] which can assist designers in shortening the time-to-market of final products and reducing the complexity of such a challenge. In this monograph, a thorough design methodology for ADCs, and more specifically pipeline converters, will be presented. The main motivations for this book are that: (1) on the one hand, pipeline converters cover a wide field of broadband applications such as Digital V ideo Broadcasting (DVB), Power Line Communications (PLC) or V ery high bit-rate Digital Subscriber Line (VDSL) communications and (2) their inner structure is complex, comprising very accurate Switched-Capacitor (SC) circuits, other sub-ADC topologies such as flash architectures, digital circuits, numerous auxiliary building blocks and a meticulous timing. These two reasons make a design methodology for pipeline converters even more attractive and necessary. The main contributions of this design methodology are: vii

viii

Preface ENOB

Instrumentation

ΣΔ il e ob ,m s io tion ud ca , a ni ch mu ee m Sp co

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5

Algorithmic, ΣΔ, SAR

Biomedical applications, sensors

Pipeline Interpolative Folding

Broadband wireline communications

Ultrawideband, RF communications

Algorithmic, ΣΔ, SAR 100

1k

10k

100k

Flash

1M

10M

100M

1G

Frequency

Fig. 1 Field of application of ADCs

• The development of an accurate and fast behavioural simulator for pipeline ADCs. It includes efficient and accurate behavioural models for the basic building blocks of pipeline converters. In addition, it provides high flexibility, low computational cost, and user-friendliness since it has been integrated into the Matlab-Simulink interface. To the best of our knowledge, these behavioural models are the most accurate and thorough models reported to date, taking into account not only small-signal effects but also other important large-signal phenomena. In fact, our behavioural models show a maximum deviation of 0.3 bits of effective resolution with transistor-level simulations. • The above behavioural simulator has been combined with an optimization algorithm for synthesis purposes. Both genetic and simulated annealing approaches have been used. • A complex synthesis procedure for the mapping of the high-level converter specifications onto transistor-level specifications has been developed. This procedure is able to reduce the design parameter space to only three design variables, from which the remaining parameters are meticulously determined. This reduction of the design parameter space is combined with a set of processing routines in Matlab which optimize the sizing of remaining parameters and provide accurate estimates of transistor-level parameters. These routines use look-up table techniques for a better characterization and estimation of technology parameters. As a result, an efficient and accurate transistor-level synthesis tool of pipeline converters will be implemented. It will be able to map the high-level specifications of the pipeline converter directly onto transistor-level parameters. To do so we will combine the proposed behavioural simulator to evaluate the converter performance, and the Matlab routines to reduce the design parameter space and estimate the parasitics and dimensions of the transistors at electrical level; with an optimization algorithm for

Preface

ix

the selection of the most suitable pipeline architecture in terms of power consumption and area. Against other design methodologies and CAD tools, it will be shown that several advantages are achieved with our proposed synthesis tool: (1) the proposed behavioural modelling will extend previous approaches, considering both one- and two-stage Miller Compensated (MC) OTA macromodels and including small- and novel large-signal effects, (2) the required bottom-up iterations for the fine tuning of the converter performance will be drastically reduced thanks to actual transistor-level parameters (such as parasitic capacitances, transconductances, saturation currents, etc.) and closed-loop operation conditions will be intrinsically considered in the design flow; (3) optimum architecture selection will be guaranteed since all required architectures will be synthesized at transistor level thanks to the efficiency and speed of the proposed tool; (4) the typical oversizing carried out by most designers due to uncertainty of other design methodologies will not be necessary since the accuracy of the behavioural models proposed will allow us to estimate both the resolution and power consumption of the converter with precision. It is worth mentioning that although this design methodology will be developed specifically for pipeline ADCs, it can easily be extended to other converter approaches such as Sigma-Delta (), algorithmic or Successive Approximations Register (SAR) architectures. The book is organized into seven chapters.

Chapter 1: Pipeline ADC Overview This chapter will present a brief introduction to ADCs, offering a description of the fundamentals of analog-to-digital conversion and the main error mechanisms inherent to the conversion process. The main metrics which characterize the ADC performance will also be summarized. The basic operation principles of pipeline converters will then be described and the practical implementation of its basic building blocks discussed.

Chapter 2: Design Methodologies for Pipeline ADCs A brief review of the conventional design methodologies for analog-to-digital converters is offered in this chapter. A novel synthesis tool will be proposed for the improvement of these conventional design methodologies. This tool will be composed of a behavioural simulator, a set of Matlab routines, and an optimizer. The main advantages of this synthesis procedure will be highlighted.

Chapter 3: Pipeline ADC Electrical-Level Synthesis Tool The proposed synthesis tool, which has been integrated into the Matlab-Simulink interface, will be presented in this chapter. Brief descriptions will be offered for the

x

Preface

basic components, that is, the behavioural simulator, the set of Matlab routines and the optimizer.

Chapter 4: Behavioural Modelling of Pipeline ADCs The key to the proposed synthesis tool is a behavioural simulator which allows us to accurately estimate the performance of the ADC. This behavioural simulator includes a set of behavioural models which describe the effect of the main non-idealities of the practical implementation of the basic building blocks in the pipeline converter. This chapter will be devoted to presenting these behavioural models and illustrating the impact of these non-idealities on the performance of the ADC.

Chapter 5: Case Study: Design of a 10bit@60MS Pipeline ADC The design methodology will be applied to synthesize a 10bit@60MS/s pipelineADC in a 0.13μm 6-metal technology at 1.2 V voltage supply. The high-level converter specifications will be directly mapped to transistor-level specifications, verifying target fulfilment by means of transistor-level simulations. The design of auxiliary building blocks will also be detailed. The layouts of all basic building blocks will be presented and post-layout verifications will be carried out. The converter designed will only consume about 23 mW, including internal reference voltage generators and digital circuits, which provide excellent performance when compared with state-of-the-art pipeline converters. In addition, these specifications will be fully satisfied on all required technological corners.

Chapter 6: Experimental Results and State of the Art The prototype will be tested in the laboratory. The test procedure and the measured performance will be presented and compared with similar state-of-the-art pipeline converters in this chapter.

Chapter 7: Conclusions and Future Lines of Research The final chapter of this work draws conclusions and suggests future lines of research.

Table of Contents

1

Pipeline ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A/D Conversion: Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Sampling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 A/D Conversion Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 A/D Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pipeline Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Operation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Analog Building Blocks Implementation . . . . . . . . . . . . . . . . . 1.3 Current Trends in Pipeline Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 State-of-the-Art Technology in Pipeline Converters . . . . . . . .

1 1 1 2 3 7 11 11 13 15 20 25

2

Design Methodologies for Pipeline ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Top-Down Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Key Elements in a Top-Down Design Methodology . . . . . . . . . . . . . . 2.2.1 Simulator and Circuit Modelling . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Power and Area Estimators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Synthesis Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Proposed Synthesis Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29 29 32 32 33 33 34

3

Pipeline ADC Electrical-Level Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . 3.1 Synthesis Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Snyrcos: The Behavioural Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Low Computational Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 User-Friendliness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39 39 41 41 41 43 44

xi

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Table of Contents

3.3 Low-Level Mapping Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 One-Stage OTA Mapping Procedure . . . . . . . . . . . . . . . . . . . . 3.3.2 Two-Stage MC OTA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Optimization Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

44 46 54 62

4

Behavioural Modelling of Pipeline ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Non-Idealities in SH and MDACS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Ideal Performance of the MDAC . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Capacitors Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 Dynamic Limitations: Small-Signal Effects . . . . . . . . . . . . . . 4.1.4 Dynamic Limitations: Large-Signal Effects . . . . . . . . . . . . . . . 4.1.5 Switch-on Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 Thermal Noise in the MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 Jitter Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.8 Behavioural Model of the MDAC . . . . . . . . . . . . . . . . . . . . . . . 4.2 Non-Idealities in Sub-ADCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65 65 67 68 69 75 83 89 96 96 99

5

Case Study: Design of a 10bit@60MS Pipeline ADC . . . . . . . . . . . . . . . . 5.1 Design Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Transistor-Level Synthesis of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Redesigning for Corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Electrical-Level Design: Detailed Description . . . . . . . . . . . . . . . . . . . 5.4.1 SH Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 MDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Sub-ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Clock-Phase Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 Reference Voltage Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 Common-Mode Voltage Generator . . . . . . . . . . . . . . . . . . . . . . 5.4.7 Reference Current Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Converter Electrical-Level Verification . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 SH Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 MDAC Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Sub-ADC Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.4 Reference Current Generator Layout . . . . . . . . . . . . . . . . . . . . 5.6.5 Reference Voltage Generator Layout . . . . . . . . . . . . . . . . . . . . 5.6.6 Clock-Phase Generator Layout . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.7 ADC Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Post-Layout Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 SH & MDAC Post-Layout Verification . . . . . . . . . . . . . . . . . . 5.7.2 Remaining Building Block Post-Layout Verification . . . . . . . 5.7.3 Converter Post-Layout Verification . . . . . . . . . . . . . . . . . . . . . . 5.8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

105 105 105 106 109 113 116 116 122 123 131 134 145 148 149 151 152 153 155 156 156 158 158 160 161 163 165 166

Table of Contents

xiii

6

Experimental Results and State of the Art . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Static Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Dynamic Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

171 171 171 177 177 179

7

Conclusions and Future Lines of Research . . . . . . . . . . . . . . . . . . . . . . . . 185

Appendix A: Technology Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Appendix B: Thermal Noise in SC Circuits Overview . . . . . . . . . . . . . . . . . . 193 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Chapter 1

Pipeline ADC Overview

This chapter provides a brief introduction to pipeline converters. Before describing their inner structure and basic operation principles, a designer must know the ideas underlying the analog-to-digital conversion process. For this purpose, Sect. 1.1 provides a brief overview of the fundamentals of analog-to-digital conversion. Subsequently, pipeline converters will be introduced in Sect. 1.2, emphasizing their main characteristics and describing their basic building blocks. As conclusion to the chapter, an overview of the current trends for the enhancement of pipeline converters will be provided.

1.1 A/D Conversion: Fundamentals An analog signal is continuous in time and in amplitude. As a result, it is defined for an infinite set of values which cannot be processed by a digital system. Therefore, first it must be adapted for its subsequent digital processing. In particular, an analog signal must be discretized in time and in amplitude, or in other words, sampled and quantized respectively. These two processes are graphically illustrated in Fig. 1.1, where the resulting digital signal (vq (nT s )) is defined only for a finite set of values in time and amplitude. We will explain both processes in detail in the following subsections.

1.1.1

Sampling Theory

The sampling process converts a continuous-time signal into a discrete-time signal. According to the Nyquist theorem [17], if the signal is bandlimited to a certain frequency f b , and the samples are taken at a sampling frequency f s at least two times the signal bandwidth f b , i.e.: fs ≥ 2fb

(1.1)

the signal is uniquely determined. Therefore, the analog signal could be reconstructed from these samples without loss of information. Converters in which the J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_1, © Springer Science+Business Media, LLC 2011

1

2

1 Pipeline ADC Overview v (t)

t

Sampling vs (nTs)

t

Quantization

vq (nTs)

t

Fig. 1.1 Analog-to-digital conversion process

sampling frequency employed is up to twice the signal bandwidth are known as Nyquist converters. Pipeline converters are in fact Nyquist converters.

1.1.2

Quantization

Once the analog signal has been sampled, the samples obtained must be quantized so they can be codified digitally. As a result, the amplitudes of the analog samples are discretized. Obviously, this process entails a loss of information given that the amplitude of the samples is approximated using the closest discrete value. The difference between the actual amplitude of the sample and its discrete value is known as quantization error. The distance between the discrete amplitudes defines the so-called quantization step () or Least Significant Bit (LSB). If this distance is kept constant between all discrete amplitudes, it is said that a uniform quantization is employed. Henceforth, we will assume a uniform quantization. Frequently, quantized amplitudes are codified using an N—bit binary code. Thus, the higher the number of binary bits employed, the greater the number of discrete amplitudes that can be used. Therefore, given a certain range of continuous amplitudes,

1.1 A/D Conversion: Fundamentals

3 xq (nTs)

y FS/2

111

εq

110 101 100 –FS/2 t1

t2

t3

t4

t5

011

t6

t

t7 FS/2

t

010 001

Δ

b

–FS/2

000

εq

c t

a

FS/2

–FS/2

xs (nTs)

Fig. 1.2 3-bit uniform quantization process: a sampled input signal, b input-output quantization characteristic and c sampled and quantized signal

called input full-scale range (FS), and a certain number of binary bits N to codify them, the quantization step will be determined by the following expression: FS (1.2) 2N These concepts are graphically illustrated in Fig. 1.2 for a 3-bit quantization process. =

1.1.3 A/D Conversion Errors As shown above, however well it has been carried out, analog-to-digital conversion entails a quantization error. In general, three main error mechanisms can be distinguished in any analog-to-digital conversion depending on their nature: the quantization error, the noise error, and the static and dynamic errors. Let us consider each type of error separately. 1.1.3.1

Quantization Error

This error results from the discrepancy between the actual amplitude of the analog signal and the corresponding discrete amplitude after the quantization procedure.

4

1 Pipeline ADC Overview

Taking into account the ideal input-output characteristic of a quantization process, it is possible to determine the quantization error. For the purpose of illustration, Fig. 1.2 shows the quantization error characteristic of a 3-bit quantization process, where the input transition values which define the thresholds for changing from one output code to the next are denoted by t j . As can be inferred, the quantization error is delimited by [−/2, /2] and depends on the input signal. If the following conditions are met: a) b) c) d)

the input-output characteristic does not overload, the input-output characteristic presents a large number of levels, the quantization step is small, and the probability distribution of pair input samples is given by a smooth probability density function,

then the quantization error can be assumed to be white noise with a uniformlydistributed probability density f unction (pdf ) [18, 19]. These propositions are generally satisfied in pipeline converters, so from now on the quantization error will be assumed to be white noise. Figure 1.3 shows both an ideal input-output characteristic for a 3-bit quantization process and the quantization error. If the quantization error is assumed to be uniformly distributed, and given that it is delimited by [−/2, /2], the following definition for the quantization error can be affirmed: 

1/ if −/2 < εq < /2 0 otherwise

p(εq ) =

(1.3)

y 111 110 101 100 –FS/2

t1

t2

t3

t4

t5

011

t6

t7

FS/2

x

p(εq)

010 001 Δ

a

000

c

–Δ ⁄ 2

Δ⁄2

εq

εq Δ ⁄2 FS/2 –FS/2

x –Δ ⁄ 2

b Fig. 1.3 3-bit uniform quantization process: a input-output quantization characteristic, b quantization error and c pdf

1.1 A/D Conversion: Fundamentals

5 q

which is depicted in Fig. 1.3c. Under these assumptions, the total error power (Pn ) introduced by the quantization process can be evaluated as follows: ∞ Pnq

=

/2 εq2 p(εq )dεq

=

−∞

−/2

εq2 

dεq =

2 12

(1.4)

From Eq. (1.4) it can be inferred that the lower the quantization step, the lower the error power of the quantization noise. 1.1.3.2

Noise Error

The analog-to-digital conversion is carried out by electronic circuits. These circuits generate noise which disturbs the input analog signal. The degradation added to the input signal imposes a minimum signal level that the circuit is able to process with acceptable quality. In fact, noise is usually one of the most limiting factors affecting the performance of ADCs. Among the different types of noise, low-frequency noise such as flicker or burst noise will be ignored since these could be interpreted as an offset component when compared with the signal bandwidth in pipeline converters. Therefore, only wideband noise, that is, jitter and thermal noise, will be considered. Let us consider each component separately. Jitter Noise The sampling instant is generally determined by the edge of a clock signal. However, due to the imperfections of real circuits, the clock edge can vary from cycle to cycle. Therefore, an uncertainty presents itself in the sampling instant. This causes a sampling error as shown in Fig. 1.4, where the desired sampling instant is t but owing to circuit imperfections the actual sampling instant is t + t. The error can be approximated as follows: x(t) = x(t) − x(t + t) ≈ t

dx(t) dt

(1.5)

x(t)

Δx(t) t edge uncertainty clk t t + Δt

Fig. 1.4 Clock-jitter dependence on the clock edge

t

6

1 Pipeline ADC Overview

Assuming a sinusoidal input signal with amplitude A and frequency f i , this error is maximum at the zero crossing: x(t) |max

 d cos (2πfi t)  = t · A ·  = A · t · 2π fi dt t=0

(1.6)

The error depends on the frequency and amplitude of the input signal but is independent from the sampling frequency. If the clock signal instant is assumed to be a random noise normally distributed with zero mean and variance σjit2 , error power can be computed as [20]: Pnjit =

σj 2 (A · 2πfi )2 2

(1.7)

From Eq. (1.7) it can be inferred that the higher the input signal frequency and amplitude, the higher the jitter noise.

Thermal Noise This type of noise results from the random motion of electrons in a conductor. Therefore, it is present in all electronic circuits and must be evaluated correctly in order to determine the effective resolution of the converter. Furthermore, thermal noise acquires greater importance in data converters due to the sampling process. In these circuits, the noise sources normally present a wide-band spectrum and become undersampled by the converter. The circuit noise is therefore folded back several times in base band (aliasing), increasing the power noise considerably and limiting the resolution of the circuit. This error will be considered in detail in Chap. 4 for pipeline ADCs. We will denote the total thermal noise power by Pnth .

1.1.3.3

Static and Dynamic Errors

In addition to noise, the electronic circuits which carry out the analog-to-digital conversion can introduce other types of errors as a result of their imperfections. For instance, the input-output characteristic can be affected by a certain gain or offset error, which can be interpreted as static error. This is illustrated in Fig. 1.5, where the ideal converter input-output characteristic is affected by a factor gain α and an offset deviation voff . The limited dynamics of the real circuits can also cause a settling error which makes it impossible to achieve the final output value required in the time available. These kinds of effects can be interpreted as dynamic errors and can induce nonlinearities in the input-output characteristic of the converter. In general, these errors will be defined as static and dynamic errors and the power error introduced by them will be denoted as PS&D .

1.1 A/D Conversion: Fundamentals

7

Fig. 1.5 Gain and offset errors during the quantization process

y 111 110 101 Voff 100 –FS/2

t1

t2

t3

t4

011

t5

t6

t7

FS/2

x

010 001 α 000

1.1.4 A/D Characterization So far, the main error mechanisms in the analog-to-digital conversion process have been presented. One of them, the quantization error, is independent as an initial approach to the converter architecture and is inherent to the analog-to-digital conversion process. The remaining error mechanisms, i.e., noise, and static and dynamic errors, are dependent on the practical implementation of the converter. In any case, these error mechanisms degrade the resolution of the analog signal under conversion. In order to quantify this degradation, a set of performance metrics is required. In this section, we will define the main metrics of data converters. Depending on the nature of the characterization, it is possible to distinguish two main categories of metrics: those which characterize static performance and those which determine dynamic performance. Let us consider both categories separately.

1.1.4.1

Static Performance

Metrics which evaluate the static performance of the converter measure the deviations of the actual input-output characteristic with respect to the ideal characteristic. Generally, input waveforms at very low frequencies are used to remove the dynamic effects and to obtain the actual converter transitions from histograms or statistical analysis [21, 22].

INL/DNL Integral Non-Linearity (INL) is defined as the difference between the actual transitions (t˜j ) with respect to their ideal values (t j ), once the gain and offset errors have

8

1 Pipeline ADC Overview y

y Missing code INLj+1 INLj

tj+1 = tj+2

Δ DNLj+1 tj

a

tj

tj+1

tj+1 tj+2 tj+2

x

b

tj

tj

tj+1

tj+1 tj+2 tj+2

x

Fig. 1.6 a DNL/INL definitions and b missing code

been removed. It is usually normalized in terms of LSB, i.e.: INLk =

t˜j − tj 

(1.8)

On the other hand, Differential Non-Linearity (DNL) is defined as the difference between the actual quantization step and its ideal value. Again, it is usually normalized in terms of LSB, that is: DNLk =

t j − tj t˜j +1 − t˜j t˜j +1 − t˜j − +1 = −1   

(1.9)

Note that from the above definitions, the DNL can also be defined from the INL as follows: DNLk =

t˜j +1 − t˜j t˜j +1 − tj +1 t˜j − tj −1= − = INLj +1 − INLj   

(1.10)

When measuring the performance of data converters it is interesting to detect whether any digital code is missing. This means that two transition voltages coincide, i.e., t˜j +1 = t˜j . Taking this into account and in accordance with the definition of DNL provided in Eq. (1.9), it is possible to detect a missing code when DNL k = −1. Therefore, one method that makes it possible to speedily guarantee that no missing codes are produced is to maintain the absolute value of the DNL lower than 1. An equivalent condition could be obtained from Eq. (1.10), if the absolute value of the INL is lower than 1/2. These concepts are graphically illustrated in Fig. 1.6. 1.1.4.2

Dynamic Performance

The INL and DNL metrics are not sufficient to characterize converter performance, especially for high-speed applications. The main reason for this lies in the lowfrequency input signals which are used to characterize converter performance. This

1.1 A/D Conversion: Fundamentals

9

removes the output code dependence on the input signal and, as a result, signaldependent distortion is avoided. Spectra-based analyses are frequently used to improve the characterization of the data converter, especially dynamic performance. These analyses typically use an input full-scale sinusoidal signal, and analyze the spectrum resulting from performing a Fast Fourier T ransform (FFT ) of an output bit sequence of the data converter. Figure 1.7 displays a 1024 point FFT of a 10 bit 100 MS/s ADC converting a 48 MHz input sine wave. The spectrum includes the quantization error, the thermal noise, and static and dynamic errors caused by the converter. In accordance with the relationship between the input signal power and the different error sources, several dynamic measurements can be defined. Let us summarize the most useful dynamic metrics. SNR The Signal-to-Noise Ratio (SNR) is defined as the ratio between the input signal power (Pin ) and the error power due to the noise sources (Pn ). Therefore, this error power must include both the quantization noise and the noise contributions due to jit q converter non-idealities, such as thermal or jitter noise, i.e., Pn = Pn + Pnth + Pn . In summary: Pin Pin SNR = = q (1.11) jit Pn Pn + Pnth + Pn SFDR The Spurious-Free Dynamic Range (SFDR) is defined as the ratio between the input signal power (Pin ) and the higher spurious component (Pmax ): s SFDR =

Pin Psmax

(1.12)

–50 Power/frequency (dB/Hz)

Input sine wave

–100 Noise floor

–150

–200

Fig. 1.7 Output spectrum of a 10 bit 100 MS/s ADC

0

10

20

30

Frequency (MHz)

40

50

10

1 Pipeline ADC Overview

HDk The Harmonic Distortion with respect to the k-th harmonic (HDk ) is the power ratio between the k-th harmonic (Phk ) and the fundamental input tone (Pin ), defined as: HDk =

Pin Phk

(1.13)

THD The T otal Harmonic Distortion (THD) is defined as the ratio between the distortion harmonic components and the input signal power (Pin ), i.e.: THD =

Nh 

HDk

(1.14)

k=1

where N h stands for the number of harmonics to be considered. SNDR The Signal-to-Noise Distortion Ratio (SNDR) is defined as the ratio between the input signal power (Pin ) and all error power contributions, including both noise sources and distortion due to non-idealities. Therefore, this metric is one of the most representative specifications of converter performance. Pin

SNDR = q Pn

+

Pnth

+

jit Pn

+

Nh 

(1.15) Phk

k=1

ENOB The Effective Number Of Bits (ENOB) provides the number of bits which would be required for an ideal converter to produce the same SNDR level as the converter being characterized. Given that in an ideal converter neither distortion nor noise are presented, the SNDR will be determined only by the quantization noise and input signal powers, i.e.: SNDR |ideal ADC =

Pin Pq

(1.16)

taking into account Eq. (1.4) and assuming a full-scale input signal amplitude, the SNDR of an ideal ADC with N bits will be given by:   Pin A2 /2 (F S/2)2 /2 3 = 2 (1.17) = = · 22N SNDR ideal ADC = 2 N Pq  /12 2 (F S/2 ) /12

1.2 Pipeline Fundamentals

11

By expressing Eq. (1.17) in decibels: SNDR |ideal ADC = 6.023 · N + 1.763

(1.18)

it can be inferred from Eq. (1.17) that the SNDR of a converter is increased by 6.023 dB per additional bit. Considering this definition, the ENOB of a converter can be determined from its SNDR as follows: ENOB =

1.2

SNDRdB − 1.763 6.023

(1.19)

Pipeline Fundamentals

Once the underlying ideas of the analog-to-digital conversion have been presented, the fundamentals for the converter under discussion in this book, the pipeline converter, can be described. This kind of converter provides interesting speed and power advantages when compared with other architectures. Hence, pipeline converters are one of the most attractive approaches for medium-high resolution (8–14 bits) and medium-high speed (10–200 MHz) applications. Firstly, an initial overview of the basic operation principles of a pipeline converter will be provided. Then, their basic building blocks will be shown and typical implementations described. Finally, a brief discussion about the main trends in the design of pipeline converters will be presented.

1.2.1

Operation Principle

A pipeline converter is composed of a Sampled and Hold (SH) circuit at the front, which samples the input signal, and a cascade of basic building blocks, called stages. Each stage performs a specific nj -bit coarse quantization of the sampled input and generates the difference between this sampled value and the value obtained by encoding the solved bits back to analog domain. This difference, known as residue, is amplified so the less significant bits that follow can be extracted at the next stage. Finally, the bits solved by the stages are all re-ordered and processed by the so-called Digital Correction Logic (DCL) block to obtain the N-bit output of the converter. The pipeline architecture thus described is illustrated in the block diagram in Fig. 1.8a. As illustrated in Fig. 1.8b, the inner structure of a pipeline stage typically comprises five blocks: a sub-ADC (usually a flash A/D converter) which obtains the coarse quantization bits from the input signal, a binary encoder which codes the solved bits from the sub-ADC to binary, a sub-DAC which encodes these solved bits back to analog domain, a substractor, and an SH residue amplifier with gain Gj ≤ 2nj to obtain the residue. The last three blocks are implemented in practice by a single subcircuit which is referred to as Multiplying Digital-to-Analog Converter

12

1 Pipeline ADC Overview SH

vi

Stage 1

Stage 2

n1

Stage L

...

n2

nL

DIGITAL CORRECTION LOGIC N

a j-th Stage

+ – sub ADC Coarse quantization

b

Nj

T2B



Gj Gj

sub DAC MDAC

Amplified residue generation

nj

Fig. 1.8 Pipeline converter: a basic block diagram and b detail of a single stage

(MDAC). The usual operation of a pipeline stage requires two consecutive clock phases: • In the first phase, known as sampling phase, the input signal is sampled and stored in the MDAC while the sub-ADC obtains the N j -bit thermometric code. This thermometric code is processed by the binary encoder to generate the nj -bit length output code of the stage. • In the second phase, known as the amplification phase, the MDAC obtains the residue and amplifies it with a gain Gj to be processed by the following stage. The last stage of the pipeline ADC must only provide the least significant bits of the conversion and, therefore, does not require an MDAC. It should be noted that, because of the aforementioned timing scheme, adjacent stages must operate in opposite phases and, therefore, the time elapsed since the input signal is sampled by the first MDAC until the output word is finally obtained is L + 1 half-clock cycles. Nevertheless, the output rate of the converter coincides with the clock frequency. This timing and mode of operation of a typical pipeline converter is shown in Fig. 1.9. As can be inferred from the inner structure of a pipeline converter, the required number of analog components is approximately proportional to the number of bits resolved. Therefore, this architecture is more attractive for obtaining resolutions higher than other Nyquist approaches such as flash converters [3, 23, 24]. The latter architectures increase the number of analog components exponentially along with the number of bits. Also, higher speed can be achieved when compared with oversampled

1.2 Pipeline Fundamentals

13

SH vi

vo

Stage 1

v1

Stage 2

v2

Stage 3

(n +1⁄ 2)Ts 2nTs

Sampling vi

-------

-------

-------

Holding vo

Sampling vo

-------

-------

Residue amp. v1

Sampling v1

-------

Residue amp. v2

Sampling v2

(2n+1⁄ 2)Ts 3nTs

4 half cycles required to obtain output word

nTs

Input voltage is sampled n1 bits solved from stage 1 n2 bits solved from stage 2 n3 bits solved from stage 3 t

Fig. 1.9 Timing scheme of a 3-stage pipeline converter

or algorithmic architectures [20, 25], since their operation is extended along the entire Nyquist bandwidth.

1.2.2

Redundancy

As explained above, MDACs use a gain Gj ≤ 2nj for the residue amplification, where nj is the number of solved bits of the corresponding stage. For illustration purposes, Fig. 1.10a shows the input-output characteristic of a 2-bit MDAC with residue amplification gain equal to 4 and an FS input range of V ref . Ideally, the transition voltages of the sub-ADC are −V ref /2, 0 and V ref /2 which delimit four input voltage segments, each corresponding to a given output digital code. Assuming that the output residue voltage is coded with an ideal 3-bit sub-ADC, the Analog-to-Digital (AD) conversion characteristic in Fig. 1.10b is obtained. The non-idealities of the basic building blocks can deteriorate the ideal inputoutput characteristic of the MDAC and degrade the AD conversion characteristic considerably. For instance, the offset in the comparators of the sub-ADC can cause deviations in the transition voltages. These deviations have a disastrous impact on the input-output characteristic as shown in Fig. 1.11a, as the amplified residue voltage exceeds the input range of the next stage. As a result, the sub-ADC of the next stage saturates, causing missing codes (Fig. 1.11b).

14

1 Pipeline ADC Overview Digital output

y Vref 11xxx

10xxx 4 01xxx

00 –Vref

–Vref

01 –Vref /2

10 0

00xxx

11

Vref /2

Vref

vi –V ref

–Vref /2

0

Vref /2

Vref vi

Fig. 1.10 Input-output characteristic of a: a 2-bit MDAC with gain 4 and b resulting characteristic with a 3-bit residue codification

y

Digital output

Vref 11xxx

10xxx

01xxx

00 –Vref

–Vref

01

–Vref /2

10 0

00xxx

11 Vref /2

Vref

vi –V ref

–Vref /2

0

Vref /2

Vref vi

Fig. 1.11 Input-output characteristic of a: a 2-bit MDAC with gain 4 and and deviations on transition voltages of the sub-ADCs of Vref /4, −Vref /4 and −Vref /4; and b resulting characteristic with a 3-bit residue codification

To overcome residue saturation or overranging, a residue amplification gain lower than 2nj can be used to ensure that the residue voltage does not exceed the FS input range of the next stage. This technique is known as redundancy [26]. A typical value selected for the residue amplification gain in an nj -MDAC is 2nj −1 . A unitary redundancy is said to be applied for this value. The input-output characteristic of a 2-bit MDAC with unitary redundancy is depicted in Fig. 1.12. In addition, the unitary

1.2 Pipeline Fundamentals Fig. 1.12 Input-output characteristic of a 2-bit MDAC with unitary redundancy

15 y Vref

2

00

01

10

–Vref –Vref

–Vref ⁄ 4 0 Vref ⁄ 4

Vref

vi

redundancy allows us to remove a transition voltage, simplifying the implementation of the sub-ADC. Obviously, this redundancy requires a higher number of output bits, either increasing the number of bits-per-stage or increasing the number of stages, to obtain the same final converter resolution. Despite this disadvantage, the unitary redundancy provides several advantages: • It provides enough margin to avoid the residue overranging. • It simplifies the digital correction logic hardware implementation. In fact, it can be observed that the digital output word is built by, firstly, synchronizing the solved bits-per-stage using shifters, and, secondly, overlapping the LSB of the j-stage with the MSB of the j + 1-th stage for all stages using unitary redundancy [26]. This last operation can be performed by means of adders. A basic block diagram of the procedure carried out by the DCL block is illustrated in Fig. 1.13.

1.2.3 Analog Building Blocks Implementation The basic operation principles and fundamentals of pipeline converters have been described in the previous section. A functional description of their basic building blocks was discussed. However, no relevant information about the implementation at physical level has yet been provided. The specific aim of this section is to present the better-known architectures for the basic building blocks of a pipeline converter, which are the sub-ADC, the MDAC and the SH. Note that a physical-level knowledge of the basic building blocks is crucial for the understanding of the main error mechanisms which degrade the converter performance, as will be shown in Chap. 4.

16

1 Pipeline ADC Overview Bits from 1st stage ...

Bits from 2nd stage ...

Z–1/2

Z–1/2 ... Z–1/2

Z–1/2

Z–1/2 ... Z–1/2

Z–1/2

Z–1/2 ...

Z–1/2

Z–1/2

Z–1/2 ... Z–1/2

Z–1/2

Z–1/2 ...

Z–1/2

Bits from 3rd stage ...

Z–1/2

Z–1/2 ... Z–1/2

Bits from 4th stage ...

...

... ... ... ... ... MSB

...

...

... LSB

Fig. 1.13 Digital Correction Logic to obtain the digital output word in a 4-stage pipeline converter with unitary redundancy

1.2.3.1

Sub-ADC

As mentioned in Sect. 1.2, the sub-ADC performs a low quantization of the analog input voltage. Since the number of bits to solve per stage is generally lower than 4–5 bits, flash architectures are commonly used. Such architectures usually employ a resistor ladder to obtain the transition voltages and a comparator by each transition to determine whether the analog input voltage is above or below the corresponding tap voltage. In addition to this, a thermometer-to-binary encoder is used to translate the solved bits from comparators to binary code. Note that 2nj regions between the reference voltages (V ref ,−V ref ) can be defined with nj binary bits. These 2nj regions can be delimited by 2nj − 1 transition voltages. However, one transition voltage can be removed when unitary redundancy is used. Therefore, 2nj − 2 transition voltages are required in an nj -bit sub-ADC with unitary redundancy. For illustration purposes, both a generic nj -bit and a 2-bit sub-ADC with unitary redundancy are shown in Fig. 1.14. The comparators could be implemented with a single amplifier stage [3]. However, a regenerative comparator is usually preferred when reducing the decision time. This kind of comparator is commonly built by crosscoupling a pair of inverters to form a latch which provides fast response time thanks to positive feedback. The main disadvantage of a regenerative comparator is its high sensitivity to mismatch, which translates into a high offset. In order to reduce this sensitivity, a preamplifier is usually placed before the latch. The comparator using these components, called a preamplified regenerative comparator, is illustrated in Fig. 1.15a. Further enhancement can be achieved by using input-offset cancellation techniques as shown in Fig. 1.15b. Although this architecture is relatively more complex

1.2 Pipeline Fundamentals

Comparator Bank

Resistor ladder

btT .. . btj+1

tj+1

btj

tj

.. . bt1

Ru

a

Vref bnj

bt2

t2

. . .

bt1

t1 b2 b1

b2 b1

Ru –Vref

n

–Vref

vin Thermometer to Binary Encoder

vin

Thermometer to Binary Encoder

Vref

17

T = 2 j –2

b

Fig. 1.14 Flash architecture for implementing a: a generic nj -bit sub-ADC and b 2-bit sub-ADC using unitary redundancy Input Offset Cancellation Scheme φs tj

–

vin

+

xbtj OA

φa tj φs

btj vin latch

a

Cin –

xbtj

OA

btj

+

b Clock phases φs φa

latch

Fig. 1.15 Schematic of a: a preamplified regenerative comparator and b input-offset cancellation technique

due to the SC front-end, it introduces two additional advantages: (1) it removes the preamplifier offset contribution and (2) it capacitively decouples the input preamplifier common mode.

1.2.3.2

SH

The SH circuit carries out the sampling of the analog input signal. Conventional SH approaches are implemented using SC circuits. Three main architectures can be distinguished as shown in Fig. 1.16 [27]. For simplicity, only Single Ended (SE) configurations are depicted. In all cases, the basic operations are (1) the sampling of the input signal during one clock phase and (2) the transferring of the signal charge onto the feedback capacitor by using an opamp in feedback configuration during the

18

1 Pipeline ADC Overview CFB

vin

φs φa

φs

vin φs

Cs φs

– OTA +

CFB

Cs

vout

φs

φa

φs

φa

– OTA +

vout φs

b

a vin

φs

φa Cs φs

– OTA +

c

vout φs

Clock phases φs φa

Fig. 1.16 SC SH schematics: a Charge distribution, b Correlated Double-sampling and c Fliparound

Table 1.1 Key parameters for the SH topologies in Fig. 1.16

Topology

Gain factor

Flip-around

1

Charge distribution

Cs CFB

Correlated Double-sampling

1+

Cs CFB

Feedback factor CFB COTA + CFB CFB COTA + CFB + Cs CFB COTA + CFB + Cs

other non-overlapping clock phase. These architectures differ in the feedback and gain factor as summarized in Table 1.1†1 . The topology selection will depend on the requirements and application. For instance, flip-around topology is a good choice for high-speed applications since it provides a higher feedback factor; whereas the charge distribution or correlated double-sampling architectures are better for applications which require the input signal to be scaled. The flip-around topology is also insensitive to capacitor mismatch given its single-sampling capacitor, whereas the remaining architectures are sensitive. Regarding aperture errors, it can be observed that the flip-around and charge distribution topologies are less sensitive than the correlated double-sampling topology. The former only use a sampling SC branch, which eliminates the aperture error between different branches caused by switch imperfections and signal-dependent delays.

1

C OTA is the parasitic capacitance at the amplifier input node.

1.2 Pipeline Fundamentals

1.2.3.3

19

MDAC

The MDAC must generate and amplify the residue voltage. This operation requires the digital-to-analog conversion of the code from the sub-ADC, its substraction from the analog input signal and its amplification to cover the FS input range of the next stage. Again, SC approaches are used to implement this circuit. Depending on the digital-to-analog codification used, two categories can be distinguished: thermometer and what we will term pseudo-thermometer MDACs. Both topologies are illustrated in Fig. 1.17. For simplicity, only SE configurations are depicted. All architectures use unitary redundancy, so the residue amplification gain is reduced to 2nj −1 . As can be inferred from the schematics, the MDACs use two non-overlapping clock phases. During the first clock phase, φs , called the sampling phase, the analog input voltage is sampled by both sampling capacitors (C s ) and feedback capacitor (C FB ). During the second clock phase, φa , called the amplification phase, the sampling capacitors are connected to the reference voltages (V ref , 0, −V ref ) in accordance with the switch gate signals while the feedback capacitors establish the Operational T ransconductance Amplifier (OTA) closed-loop operation. Note that the gate signals which control the switches during the amplification phase are obtained directly from the thermometer φs

vin

φa

Vref –Vref bt1 xbt1 φs

φa

bti

bt2 xbt2 φs

Cs

φa

φs

Cs

xbti

Clock phases φs φa

CFB

φa Cs

φs

a

i = [1,…,2nj – 2]

CFB = 2Cs

T = 2 nj – 2

φs

vin Vref

+ –

vout

OA φs

φa

–Vref bu1 bm1

bd1

φa

φs Cs

buk bmk bdk φs

φa

Clock phases φs φa

CFB

Cs φs

b

k = [1,…,2nj –1 – 1]

M = 2nj –1– 1

CFB = Cs

– +

OA

vout φs

Fig. 1.17 SC MDACs schematics: a thermometer and b pseudo-thermometer approaches

20

1 Pipeline ADC Overview

Table 1.2 Output voltage for the MDACs in Fig 1.17 MDAC Therm.

Pseudo-therm.

Output voltage   T T  Vref  T Cs + CFB Cs vin − Vref Di = 2nj −1 vin − Di CFB CFB 2 i=1 i=1   M M   MCs + CFB Cs vin − Vref b¯k = 2nj −1 vin − Vref b¯k CFB CFB k=1 k=1

Code Di = bti − xbti b¯k = buk − bdk

Table 1.3 Switch gate signals for a 3-bit thermometer and pseudo-thermometer MDAC bti i ∈ [1, 6]

bdk k ∈ [1, 3]

bmk k ∈ [1, 3]

buk k ∈ [1, 3]

Di i ∈ [1, 6]

bi i ∈ [1, 3]

000000 100000 110000 111000 111100 111110 111111

111 011 011 001 001 000 000

000 100 000 010 000 001 000

000 000 100 100 110 110 111

−1 −1 −1 −1 −1 −1 +1 −1 −1 −1 −1 −1 +1 +1 −1 −1 −1 −1 +1 +1 +1 −1 −1 −1 +1 +1 +1 +1 −1 −1 +1 +1 +1 +1 +1 −1 +1 +1 +1 +1 +1 +1

−1 −1 −1 0 −1 −1 +1 −1 −1 +1 0 −1 +1 +1 −1 +1 +1 0 +1 +1 +1

bits of the sub-ADC (bt i , xbt i ) in the thermometer architecture. However, the switch gate signals in the pseudo-thermometer topology must be generated by means of a specific encoder, known as a switch encoder, as follows: buk = btj · btj +1 bmk = btj · xbtj +1 bdk = xbtj · xbtj +1

k ∈ [1, 2nj −1 − 1] j = 2k − 1

(1.20)

According to these gate signals, the final output voltage can be evaluated by applying the charge conservation principle between clock phases. This leads to the output voltages summarized in Table 1.2. Note that both MDAC architectures could be easily modified to include input-offset cancellation techniques as shown in Fig. 1.15b. For illustration purposes, the gate signals which control the amplification switches for a 3-bit MDAC are summarized in Table 1.3 both for thermometer and pseudothermometer architectures.

1.3

Current Trends in Pipeline Converters

Nowadays, there is a trend for integrating the ADCs in adverse deep sub-micron technologies with low power supplies. This makes the design of converters a major challenge since analog devices do not benefit from this technological scaling. For instance, as the supply voltage is scaled down, the voltage available for representing the signal is reduced; therefore, to maintain a specific dynamic range on a lower

1.3 Current Trends in Pipeline Converters

21

supply voltage, the thermal noise in the circuit must also be proportionately reduced. There is, however, a trade-off between noise and power consumption. In fact, this trade-off usually forces the designers to increase the power consumption of the converters. Hence, numerous techniques have been reported in the bibliography for the enhancement of pipeline converters and the reduction of the total power consumption. An overview of some of those techniques and current trends in the design of these Nyquist converters will be given here. 1) Stage Scaling-down Requirements In principle, the major design challenge is satisfied once the first stage in a pipeline converter has been designed. Thus, this first stage could be of further use when implementing the following stages. This would simplify the design of a pipeline converter considerably. However, this entails an unnecessary waste of power consumption since the requirements for the subsequent stages can be relaxed as coarse bits from the previous stages are solved. Therefore, the first technique for reducing the power consumption in a pipeline converter is to scale down the specifications of the stages according to the remaining resolution to be solved [28, 29]. In fact, most pipeline converters committed to the reduction of power consumption use this scaling-down stage technique. We have used this technique in our proposed design methodology. For illustration purposes, Fig. 1.18 plots the power consumption of the stages in the 5-stage pipeline converter prototype included in this monograph, a full description of which is provided in Chap. 5. As can be inferred, the power consumption of the stages is scaled down from the first to the last stage. 2) Opamp Sharing Technique As explained in Sect. 1.2, the MDAC operates at two non-overlapping clock phases, called sampling and amplification phases. During the sampling phase, the input voltage is sampled and the OTA is reset, whereas during the amplification phase the residue is obtained with the OTA operating in a closedloop operation. Therefore, the OTA is only really required during the amplification phase. In addition, when a given stage is sampling, the next stage is amplifying. This gives rise to the so-called opamp sharing technique [30–36]. The idea is to share the amplifier between two consecutive stages, in such a way that the same OTA is used as residue amplifier for two different stages. Thus, the OTA is always in active

Fig. 1.18 Stage scaling-down in the 5-stage pipeline converter in Chap. 5

22

1 Pipeline ADC Overview

mode and is never reset. This technique requires the addition of two more switch sets, which enable the OTA to commutate between the two stages. The advantage afforded by this is that the number of amplifiers required is halved and power consumption is significantly reduced. However, this technique has two main drawbacks. First, the additional switches introduce a series of resistances which, in combination with the amplifier input capacitance, affect the settling behaviour of the stage. Second, the non-zero input voltage of the amplifier due to the OTA finite DC gain and offset voltage is never reset. Thus, every input sample is affected by the finite-gain error component from the previous sample. This can degrade the performance of the pipeline converter. In order to overcome these problems some improvements have been proposed in the literature. In [30], a Feedback Signal Polarity Inverting (FPSI) technique was proposed, where the first residue signal is inverted during the next phase to reduce the error to 1/3 for a 2-bit MDAC with unitary redundancy. Nevertheless, the effect of the error reduction becomes less significant as the resolved number of bits-perstage increases. In [32], only the second stage in two-stage amplifiers is shared, so that the first stage can be reset. Such a partial opamp sharing scheme requires the same number of preamplifiers so it has no significant power and area advantage. In [36], the OTAs are shared between stages but are reconfigured by using dual inputs and scaling the bias currents. In this way, the non-zero input voltages can be reset. In summary, the opamp sharing technique has a high potential to reduce the power consumption of pipeline converters but some drawbacks are still to be overcome. 3) Removing the SH Circuit The main purpose of the SH circuit is to sample the input signal. However, it is possible to appreciate that both the MDAC and the sub-ADC also perform a sampling procedure. Therefore, the use of an SH circuit could be avoided [35, 37] with the MDAC and sub-ADC carrying out the sampling procedure alone. This can reduce power consumption considerably since the SH usually has a very large power dissipation and contributes substantially to the distortion and noise of the entire ADC. Nevertheless, removing the SH circuit introduces a major drawback: if a mismatch between the value sampled by the MDAC and the sub-ADC occurs, an error is induced which can drastically degrade the resolution of the whole ADC. This error, called aperture error, is more notable at high input frequencies where small discrepancies between the MDAC and sub-ADC sampling instants can induce higher discrepancies between their respective sampling values. Therefore, special care must be taken when the SH circuit is removed. In order to reduce the aperture error, a careful match between the MDAC and sub-ADC signal paths can be pursued as in [37]. Here, all input signal sampling switches are matched, using the same V gs and dimensions and controlling the RCdelay introduced by the layout parasitics. A modified sampling scheme can also be used in the first stage to avoid the matching requirement between the MDAC and sub-ADC paths as in [35]. Here, additional time between non-overlapping clock phases is generated to allow the sub-ADC to sample the value previously sampled by the MDAC during the sampling phase. Discrepancies between sampled values

1.3 Current Trends in Pipeline Converters

23

are thus removed. The drawback is that the time available for amplifying the residue is reduced and, as a result, the speed requirement for the MDAC is increased. 4) Switched-opamp Technique Analog circuits present serious limitations at low power supply voltages. For instance, the reduced voltage supply forces us to use a low input signal range and, as a result, system noise must be proportionally reduced to maintain the same dynamic range. But worse still is the fact that the functionality of some analog devices is fully degenerated at very low power supply voltages. This is the case of MOS switches which require a minimum V gs to allow the signal flow. Some techniques may be applied to overcome this problem. The first entails the use of low V T transistors as switches; however, these require special technology and may suffer leakage of the stored charge. The second is the use of bootstrapped switches [38–42] which increases the complexity and the overall on-chip capacitances. The third approach is the so-called Switched-Opamp (SO) technique [43–45] where problematic switches affected by insufficient voltage overdrive, such as the sampling switches, are removed. Obviously, this involves switching off the amplifier during the sampling phase to remove the driving capabilities over the next stage. Figure 1.19 shows an SO 2-bit MDAC with unitary redundancy [44]. As can be appreciated, all switches are connected to well-known reference voltages and do not suffer from high voltage swings. The common input and output modes of the amplifier are set to V dd and V dd /2 respectively. The SO MDAC operation is as follows: (1) during the sampling phase, the sampling capacitor (4C u ) samples the input signal provided in the previous stage, the feedback (2C u ) and reference capacitors (C u ) are reset, and the OTA outputs are in a high-impedance state and pulled to V dd by the attached switches; (2) during the amplification phase, the OTA is switched on, the preceding stage pulls its MDAC output to V ss , the reference capacitors are connected to the corresponding reference voltages and the charge is distributed to obtain the residue

Vss

Clock phases φs φs

Vref –Vref bt1 φs

xbt1 φa

Cu

bt2 φs

xbt2 2Cu

φa Cu

vi

+ –

φs

Vdd

Fig. 1.19 SO 2-bit MDAC

vo

OA

4Cu

φs

Vss

24

1 Pipeline ADC Overview

voltage. In fact, applying the charge conservation principle: 4Cu [(Vdd − Vss ) − (Vdd − vi )] + 2Cu [(Vdd − vo ) − (Vdd − Vss )] + · · · + Cu [(Vdd − b¯1 Vref ) − (Vdd − Vss )] + Cu [Vdd − b¯2 Vref ) − (Vdd − Vss )] = 0 (1.21) where b¯i = bti − xbti i = 1, 2. From Eq. (1.21), the input-output characteristic of the SO MDAC in Fig. 1.19 can be obtained as follows: vo = 2vin −

2 

b¯i Vref

b¯i = bti − xbti

(1.22)

i=1

which corresponds with the ideal input-output characteristic of a conventional 2-bit MDAC with unitary redundancy. Note that the SO MDAC, as well as operating on a very low power supply, reduces power consumption since the OTA is switched off during the sampling phase. Therefore, the SO approach can be interpreted as a power consumption reduction technique. In fact, in [32] a partially SO technique is applied simply due to the benefits of the power reduction and conventional MOS switches used. In spite of the advantages of the SO technique, several drawbacks are encountered. On the one hand, the operating speed is limited due to the slow transients from the opamp being switched on and off. In addition, the SO MDACs suffer from lower feedback factors, which makes them inherently slower. For instance, the feedback factor of the 2-bit SO MDAC in Fig. 1.19 is ideally 1/4 whereas a conventional 2-bit SC MDAC provides a feedback factor of 1/2. On the other hand, fully SO converters require specific input interface circuits to get the signal into the converter due to the lack of the series switch-connecting stages. This increases the converter complexity as well as the power consumption. 5) Pseudo-differential Architectures Fully Differential (FD) amplifiers are the preferred choice for analog designers due to their improved dynamic range, better common-noise rejection, reduced harmonic distortion and increased output voltage swing against their SE counterparts. These FD architectures are based on differential pairs with tail current sources. Thanks to these tail current sources, FD architectures provide a high Common-Mode Rejection Ratio (CMRR). However, the greatest power consumption is due to these current sources. Alternatively, PseudoDifferential (PD) architectures remove these tail current sources [46]. This makes these architectures more attractive for low voltage and low power consumption applications, given that the voltage drop across the tail current source is avoided and DC current bias disappears. In fact, PD architectures have been successfully applied in the implementation of pipeline converters [47, 48]. Nevertheless, this technique presents a major drawback: removing the tail current sources results in larger common-mode

1.3 Current Trends in Pipeline Converters

25

gain giving rise to serious problems from common-mode and offset voltages of the SE paths. 6) Calibration Techniques In recent years, numerous pipeline converters using calibration techniques to correct the non-linearities of their basic building blocks have been reported [49–60]. These calibration algorithms enable a relaxation of the requirements for the basic building blocks since their non-linearities are compensated and, as a result, power consumption is reduced. In spite of this advantage, the complexity of design and additional power consumption required by the calibration circuits can limit the use of these techniques. In fact, the calibration techniques are mainly used for resolution above 12 bits where the requirements for the analog components are difficult to satisfy without the aid of an additional technique.

1.3.1

State-of-the-Art Technology in Pipeline Converters

To conclude this chapter, a detailed review of the ICs reported in the last few years will be presented. These have been characterized in terms of ENOB, sampling rate, output bits, technology, voltage supply, active area, technique used to enhance the converter performance, publication year and a common Figure Of Merit (FOM) to quantify the ‘quality’ of the IC performance:   Power FOM pJ /conv = ENOB (1.23) 2 · fs This FOM gives some idea of the energy required per conversion step. Therefore, the lower the FOM, the better the converter performance. Regarding the techniques, abbreviations have been applied for simplicity. These are summarized in Table 1.4. The IC review is summarized in Table 1.5, where the reported ENOB has been obtained for the Nyquist frequency whenever possible. For the purpose of illustration, Fig. 1.20 shows the FOM versus the sampling rate for most of the ICs in Table 1.5. As can be inferred, the best FOM performance is about 0.5 pJ/conv.

Table 1.4 Abbreviations for the pipeline techniques

Abbreviation

Technique

CAL CONV

Calibration Conventional design using scaling down stage requirements Opamp sharing Other techniques Pseudo-differential Removing SH Switched-opamp

OPSH OTH PSD RSH SWO

Bits

14 10 15 8 10 10 10 8 13 10 10 12 10 10 10 10 5 10 14 8 13 14 10 15 11 10 10 8

Ref

[52] [37] [51] [61] [36] [35] [62] [63] [64] [65] [34] [66] [67] [68] [69] [70] [71] [33] [50] [32] [72] [53] [73] [54] [74] [75] [76] [77]

11.34 9.03 11.5 7.03 9.03 9.16 8.51 5.85 10.84 8.66 8.80 10.26 8.53 8.84 8.51 9.09 3.96 9.26 10.41 7.68 10 11.6 9.01 11.49 9.09 8.18 8.45 6.10

ENOB (bits)

100 50 20 10 100 30 50 100 43 205 50 75 100 60 25 30.4 600 170 40 200 180 20 20.48 50 70 125 12 240

fs (MS/s) 90 nm 0.18 μm 0.18 μm 90 nm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 90 nm 0.18 μm 0.35 μm 90 nm 0.35 μm 0.13 μm 0.35 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.25 μm 0.18 μm 0.35 μm 0.6 μm 0.18 μm 0.18 μm 90 nm 0.18 μm

Process

Table 1.5 Pipeline ICs reported in the last few years 1.2 1.8 1.8 0.5 1.8 1.8 1.8 1 1.8 1 1.8 3 1 1.5 1.2 3.3 1.8 3.3 2.8 1.8 3.3 2.8 1.5 5 1.8 1.8 1.2 1.8

Supply (V) 1 0.86 3.91 0.86 1.28 0.7 1.1 2.04 3.6 1 1.43 7.9 4.03 5.76 0.8 1.47 0.27 0.85 1.15 0.15 15 1.15 1.3 3 1.2 0.66 0.3 1.36

Area (mm2 ) 250 12 280 2.4 31 21.6 27 30 268 61 18 284 30 28.9 4.8 52 70 180 72.8 30 756 34.8 19.5 350 49 40 3.3 104

Power (mW) 0.97 0.46 4.83 1.83 0.59 1.26 1.48 5.19 3.41 0.74 0.81 3.1 0.81 1.05 0.53 3.13 7.50 1.73 1.34 0.73 4.10 0.56 1.85 2.44 1.28 1.10 0.79 6.30

FOM1 (pJ/conv) CAL RSH, OPSH, OTH CAL RSH OPSH RSH,OPSH RSH SWO CAL CONV OPSH CAL OTH OTH OTH CONV CAL OPSH CAL SWO RSH CAL CONV CAL CONV OTH SWO CONV

Technique

2009 2009 2008 2008 2008 2008 2008 2007 2007 2007 2007 2007 2007 2007 2006 2006 2006 2006 2006 2006 2006 2006 2006 2005 2005 2005 2005 2005

Year

26 1 Pipeline ADC Overview

Bits

15 10 8 12 12 8 12 10 15 14 10 12 13 10 15 10 12 10 10 10 14 14 9 12 10 8 10 10

Ref

[56] [31] [45] [55] [78] [79] [57] [58] [59] [60] [80] [81] [82] [83] [84] [85] [86] [47] [30] [87] [88] [89] [44] [90] [91] [92] [92] [29]

11.92 9.09 7.68 11.5 9.34 6.49 11.15 9.00 11.67 9.84 8.38 11.83 9.54 8.18 12 8.18 10.84 8.68 9.29 6.35 12.5 11.83 8.01 10.34 9.51 6.98 8.63 8.84

ENOB (bits)

Table 1.5 (continued)

40 30 200 80 110 220 20 80 40 30 150 50 16.38 100 20 220 75 30 80 25 10 75 14 54 40 80 14.3 20

fs (MS/s)

Supply (V) 2.5 3 1.8 2.5 1.8 2.5 3.3 1.5 2.1 3 1.8 2.5 1.3 1.8 3.3 1.2 3 2 3 1.4 5 3 1.5 2.5 3 3 1.5 3.3

Process 0.25 μm 0.25 μm 0.18 μm 0.25 μm 0.18 μm 0.25 μm 0.35 μm 0.13 μm 0.18 μm 0.18 μm 0.18 μm 0.25 μm 0.25 μm 0.18 μm 0.18 μm 0.13 μm 0.35 μm 0.3 μm 0.18 μm 0.35 μm 0.5 μm 0.35 μm 0.5 μm 0.25 μm 0.35 μm 0.5 μm 0.6 μm 1.2 μm 13.68 1.36 0.15 22.6 0.86 2.25 7.5 0.3 20 15.96 2.2 5.55 12.24 2.5 11.22 1.3 7.9 3.12 1.85 2.24 12.54 7.8 1.3 1 2.6 10.3 5.75 10.56

Area (mm2 ) 370 60 30 755 97 230 254 33 400 350 123 780 78 45 233 135 290 16 69 21 220 318 8.2 295 55 268 36 35

Power (mW) 2.39 3.66 0.73 3.25 1.36 11.67 5.58 0.81 3.07 12.72 2.46 4.27 6.39 1.55 2.84 2.12 2.11 1.30 1.38 10.28 3.8 1.16 2.27 4.22 1.89 26.47 6.36 3.81

FOM1 (pJ/conv) CAL OPSH SWO CAL OTH CONV CAL CAL CAL CAL CONV CAL CONV OTH CAL CONV CAL PSD SWO OTH CAL CONV SWO CAL CONV CAL CONV CONV

Technique

2005 2005 2005 2005 2005 2004 2004 2004 2004 2004 2004 2004 2004 2004 2004 2004 2003 2003 2003 2003 2003 2001 2001 2001 2001 2000 1999 1995

Year

1.3 Current Trends in Pipeline Converters 27

28

1 Pipeline ADC Overview 7 Calibration Opamp sharing Removing SH Switched opamp Pseudo-differential Conventional Others

6

FOM (pJ/conv)

5

4

3

2

1

0 0

50

100 150 Sampling Rate (MS/s)

Fig. 1.20 FOM versus sampling rate for the ICs in Table 1.5

200

Chapter 2

Design Methodologies for Pipeline ADCs

As explained in Chap. 1, the design of ADCs in adverse digital technologies is a major challenge for designers. This challenge becomes more significant with the scaling of technology which brings about new obstacles (leakage currents, increment of the relative variability of technological parameters, low power supplies, etc). In order to overcome this challenge, designers need to develop robust design methodologies or have access to CAD tools which will allow them to simplify the design procedure. This chapter deals with this issue. Firstly, a brief overview of a conventional top-down design methodology will be given, describing the different hierarchical levels into which the design procedure is split. This will be followed by an explanation of the tools required and needs for supporting the top-down design methodology. Finally, we will present our proposed design methodology, emphasizing the improvements with respect to the conventional ones.

2.1 Top-Down Design Methodology The design process of an ADC starts with the converter specifications (ENOB, f s , FS, etc.) and ends with the physical layout. During this design procedure, the designers must explore numerous alternatives, study several trade-offs, identify design constraints and dependences and optimize the design in terms of power consumption and silicon area. Obviously, this is a major challenge which generally requires the development of robust and systematic design methodologies. One of the most common approaches is what is known as the top-down design methodology, where the converter design is split into several abstraction levels. Thus, initially the design process is tackled from a functional point of view (top abstraction levels) and refined downwards (low abstraction levels). Accordingly, the converter specifications are translated from the top to the bottom abstraction levels. There are several advantages to this hierarchical decomposition [93]: (1) the possibility to perform system architectural exploration and better overall system optimization at a high level before starting detailed circuit implementations; (2) the fact that it allows the proper identification and understanding of the trade-offs and dependences between the different J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_2, © Springer Science+Business Media, LLC 2011

29

30

2 Design Methodologies for Pipeline ADCs

CONVERTER SPECIFICATIONS ENOB, fs, Vdd, FS... System Level

SPECIFICATIONS Stage 1

Number of stages, resolution-per-stage

...

Stage 2

n1

nL

N

ΣΔ

g1´

High-level specifications mapping

Circuit Level p1

Switches: ron,CP,…

Capacitors: Cu,...

High-level Performance evaluator

p2 bt2

CFB p1

– OTA + p1

bt1

tj

Ru

Low-level specifications mapping

Transistor Level

b1 b2

Bottom-up iterations

Cascade, single-loop, multibit,...

Ao,GBW,PM,CP,…

Pipeline

DIGITAL CORRECTION LOGIC

ΣΔ

OTAs:

Stage L

n2

Thermometer to Binary Encoder

Pipeline:

SH

W,L,vdsat,ib,...

Layout

Low-level Performance evaluator

Fig. 2.1 Top-down design methodology for ADCs

hierarchical levels and (3) the fact that the converter design is reduced to find the specifications for each hierarchical level, allowing a much less time-consuming modular design. Figure 2.1 shows a conventional top-down design methodology for ADCs. As can be inferred, the design procedure is split into four hierarchical levels†1 :

1

Note that more hierarchical levels could be considered.

2.1 Top-Down Design Methodology

31

• A system level, where architectural aspects such as the type of converter, the topology, etc. are discussed. At this level, the basic building blocks of the converter can be considered a black box and described at functional level. • A circuit level, where the basic building blocks are described in greater detail using simple and efficient models which take into account the major non-idealities of the actual circuit implementation. • A transistor level, where the basic building blocks are described up until electrical level by using complex non-linear differential equations and very accurate models. • A layout level, where the physical implementation of the transistors is considered. Obviously, the converter performance evaluation will be much more difficult the closer we get to the bottom hierarchical levels. In fact, specific simulators will be required at the different abstraction levels: (1) a high-level performance evaluator for circuit- and system-level simulations, providing low CPU times and medium accuracy, and (2) low-level performance evaluator for transistor and layout levels, requiring high CPU times but providing high accuracy. Let us explain the top-down design methodology in Fig. 2.1 in detail. The starting point is provided by the converter specifications, i.e., the ENOB, sampling rate, voltage supply, FS input range, etc. The objective is to satisfy these converter specifications with minimum power consumption and area. According to these specifications, the converter architecture (pipeline, , algorithmic, flash, SAR, . . .) must be selected. At this system level, we must also determine the converter topology, that is to say, the number of stages and resolution-per-stage for a pipeline converter, the single-loop, cascade or multibit approach for  converters, etc. Once the architecture has been selected, the converter specifications must be mapped onto high-level specifications for the basic building blocks of the ADC (high-level mapping procedure), such as the switch-on resistances (r on ), the values for the capacitors (C u ), the OTA DC gain (Ao ), Gain-Bandwidth Product (GBW ), phase margin (PM), etc. These circuit-level specifications must then be translated onto physical dimensions, or in other words, onto transistor-level specifications (low-level mapping procedure). To complete the top-down design methodology, the physical layout must be carried out. Although a top-down design methodology attempts to implement a modular design in which every hierarchical level is in principle independent from the remainder, some bottom-up iterations are inevitable. This is due to the trade-offs and dependences between the specifications at different hierarchical levels. For instance, the specifications at circuit level depend on the parasitics from the layout. Hence, a top-down design methodology must be refined with several bottom-up iterations and verifications to satisfy converter specifications. This procedure can therefore take a long time. The more efficient and robust the design methodology, the less time required. Note that in this design methodology, four key elements are required: (1) procedures to map the specifications from each abstraction level to the subsequent one; (2) verification tools or simulators which allow us to guarantee that the converter specifications are being satisfied; (3) a set of models to characterize converter performance in a specific way and (4) power and area estimation models. These key elements will be discussed in the next section.

32

2.2

2 Design Methodologies for Pipeline ADCs

Key Elements in a Top-Down Design Methodology

The main components required in a top-down design methodology have already been presented. This section will examine the most common approaches for the implementation of these components, emphasizing the practical aspects which limit the feasibility of the design methodology.

2.2.1

Simulator and Circuit Modelling

As explained in Sect. 2.1, performance evaluators are required to verify whether the converter specifications are satisfied, and also a set of models which allow us to characterize the operation of the converter. Depending on the abstraction level, two main categories can be distinguished: low- and high-level simulators. 2.2.1.1

Low-Level Performance Simulator

Traditionally, SPICE[94] and Spectre[95] simulators have been the most common solutions for evaluating the performance of electronic circuits at transistor level. These simulators numerically solve a system of non-linear differential-algebraic equations which characterize the electronic circuit by using conventional numerical analysis techniques such as numerical integration or Newton-Rapshon iterations. Although these are general-purpose circuit simulators, their numeric algorithms are very slow and their required CPU time quickly increases along with the size of circuit. Therefore, they are used to evaluate the performance of the ADC in the final steps of the design procedure (low abstraction levels) and not for exploration purposes or preliminary estimations. 2.2.1.2

High-Level Performance Simulator

In order to evaluate the performance of the ADC at higher abstraction levels, where fast simulations are required for exploration purposes, more specific and faster alternatives have been developed. In particular, two main types of high-level performance simulators can be distinguished: a) Equation-based simulators [13, 96], where the converter performance is evaluated by means of simple equations which refer to fundamental limits of different topologies and contemplate trade-offs between power consumption, resolution, speed, etc. Relatively short computation times are required, although the accuracy of the results depends on these equations. Furthermore, equations are obtained through exhaustive analysis of converter topologies. These therefore are closed simulators as equations must be changed every time the topology is changed. b) Behavioural modelling-based simulators [97–99], where the basic building blocks of the converter are characterized in a more abstract mathematical way by

2.2 Key Elements in a Top-Down Design Methodology

33

their input-output behaviour. These higher-level models describe the behaviour of the circuit by means of relatively simple equations which allow a fast evaluation of the performance of the circuit. Obviously, this is achieved to the detriment of the accuracy. Nevertheless, a good speed-accuracy trade-off can be obtained if the major non-idealities of the real circuit implementation are modelled with sufficient accuracy. One of the main problems encountered when using this technique is the lack of systematic methods for the creation of behavioural models and the fact that it generally requires a huge research effort.

2.2.2

Power and Area Estimators

The objective of the design methodology is to satisfy the converter specifications with minimum power consumption and area. For this purpose, power and area estimators must be developed. Again, two categories of estimators can be distinguished according to the abstraction level: low- and high-level estimators. 2.2.2.1

Low-Level Estimators

At low abstraction levels, the circuits are described at transistor level where non-linear and complex models, such as BSIM3 models [100], are used. These models provide detailed information about the power consumption and area, so highly accurate estimations can be obtained. 2.2.2.2

High-Level Estimators

At higher abstraction levels, behavioural models or macromodels are used to describe the behaviour of the circuit at a functional level. Hence, the power and area are estimated by means of simple equations based on experienced designer knowledge. For instance, the power consumption of an amplifier is commonly estimated from the required transconductance (gm ), the transistor overdrive voltage (V dsat ) and the voltage supply (V dd ) as follows [1–5]: P = (gm vdsat ) · Vdd · ηt

(2.1)

where ηt is a scaled factor which depends on the amplifier topology. Obviously, this kind of expression provides rough estimations but is enough for exploration purposes.

2.2.3

Synthesis Procedures

Apart from a simulator, a set of models for the basic building blocks and power and area estimators, synthesis procedures for carrying out high- and low-level

34

2 Design Methodologies for Pipeline ADCs

Fig. 2.2 Basic block diagram of a simulation-based optimization procedure

Specifications

Performance evaluator

Initial design point

New design point No

Optimal?

Optimization procedure

Yes

End

specifications mapping are required in a top-down design methodology. The most flexible approach consists in using an optimization core combined with an evaluation engine as shown in Fig. 2.2 [93, 101, 102]. The aim is to satisfy the specifications required by using the evaluation engine as performance evaluator and the optimization core as a search engine for the selection of design parameters. Thus, at each iteration of the optimization procedure, the circuit performance is evaluated at a given point of the design parameter space. According to such an evaluation, a movement in the design parameter space is generated and the process is repeated again until the optimum power consumption and area values for the design parameters are found. Typical optimization algorithms are simulated annealing or genetic algorithms. They can also be combined with deterministic algorithms for fine tuning. In general, simulation-based optimization procedures are used to map both the converter specifications onto circuit-level specifications (high-level specifications mapping) and those circuit-level specifications onto transistor-level specifications (low-level specifications mapping). The difference between the high-level and lowlevel synthesis procedures lies in the performance evaluator. In high-level synthesis procedures, high-level performance simulators such as behavioural [97, 101, 102] or equation-based simulators [13, 96] are used, whereas low-level performance simulators like SPICE or Spectre are used in low-level synthesis procedures [15, 103–106].

2.3

Proposed Synthesis Procedure

In this monograph, a top-down design methodology has been developed to synthesize pipelineADCs at transistor-level. It is able to map the converter specifications directly onto transistor-level specifications by combining an accurate behavioural simulator, a simulated annealing optimization core and a set of Matlab routines for the reduction

2.3 Proposed Synthesis Procedure

35

of the design parameter space, accurate estimation of parasitics, transistor dimensions and power consumption. In order to show the advantages of the design methodology proposed, we will provide a detailed explanation of how a pipeline converter can be synthesized following a conventional top-down design methodology. The main problems encountered with this design methodology will then be discussed and our proposed solutions will be presented. As shown in Fig. 2.1, the first step in a top-down design methodology is to select the most suitable converter topology in terms of power consumption and area. Specifically, in a pipeline converter we must select the number of stages and the resolution-per-stage. Typically, this task is reserved for experienced designers who decide which is the best solution in accordance with the knowledge acquired from previous designs. Once the topology has been selected, the converter specifications must be mapped onto high-level specifications for the basic building blocks (high-level specifications mapping). A simulation-based optimization procedure is normally used for this purpose. As performance evaluator, a behavioural simulator is the most common approach as it provides fast performance evaluations and an acceptable resolution. In order to achieve this speed, the basic building blocks are described using simple models and parameters. For instance, the switches are modelled by single switch-on resistances (r on ) and the OTAs are typically described by 1-pole macromodels as shown in Fig. 2.3. Thus, the OTA behaviour is characterized by a single transconductance (gm ) with a maximum output current (io ); an output resistance (1/go ) which defines the DC gain (Ao = gm /go ) and the input (C p ) and output parasitics (C o ). However, some design parameters, such as the parasitic capacitors or currents, cannot be arbitrarily sized since they are very much dependent on the OTA topology and technology. Therefore, they must be initially estimated or related together with other design parameters. Note that this can pose serious limitations since the feasibility of the design methodology can be extremely constrained by a suitable estimation of these parameters. In any case, and in accordance with these descriptions and constraints, the synthesis procedure tries to obtain the values for the design parameters which satisfy the converter specifications with the minimum power consumption and area. At this level, power consumption and area are estimated roughly since they are usually approximated by simple equations as in Eq. (2.1). Next, these high-level specifications must be translated onto transistor level (lowlevel specifications mapping). The capacitors and the switch-on resistance values can be easily mapped onto electrical dimensions. However, the transistor-level mapping of the OTA parameters is not trivial. The design parameters obtained in the vo

+

+ vi

vo

vi

– – Fig. 2.3 OTA 1-pole macromodel

Cp

gmvi

go

Co

36

2 Design Methodologies for Pipeline ADCs

high-level mapping procedure, that is, transconductances (gm ), saturation currents (io ), DC gains (Ao ) or equivalent load capacitances (C eq ), are related to the OTA closed-loop operation. However, these design parameters are traditionally translated onto open-loop specifications[1–5], such as Gain Product Bandwidth (GBW ), Margin Phase (PM), slew-rate (SR), etc. A simulation-based synthesis procedure can subsequently be used once more to map these open-loop specifications onto transistor-level specifications. In this case, a general purpose electrical simulator like SPICE or Spectre is employed as performance evaluator. Note that the simulation of these building blocks in open-loop configurations can be carried out quickly even if electrical simulators are used, since they are normally based on DC and AC analysis. Another possibility is to design the OTA by hand. However, these synthesis procedures present a serious problem: if the final transistor-level parameters differ from those estimated during the high-level specifications mapping, converter performance can be degraded and a new redesign (or bottom-up iteration) is required. In addition, the fulfilment of the open-loop specifications does not guarantee achieving the target performance when the feedback loop around the OTAs is closed. For illustration purposes, let us assume that an OTA with specific open-loop parameters Ao , GBW, PM, SR and C eq has been synthesized. If the final transistor-level implementation of the OTA presents parasitic capacitances different to those estimated from the high-level mapping procedure, the closed-loop operation can deteriorate noticeably. This is due to the fact that the parasitic capacitances can define the feedback factor to a great extent, in turn modifying the equivalent load capacitance and, as a consequence, possibly slowing down the closed-loop operation of the OTA. Furthermore, the closed-loop operation of the OTA might even become unstable if two-stage topologies are considered. Therefore, a good estimation of the transistorlevel specifications is essential when reducing bottom-up iterations and accurately predicting the converter performance. As the final step of the conventional design methodology, the layout of the basic building blocks is carried out. Against top-down design methodologies which follow the procedure described above, we propose a novel design methodology which presents several advantages: 1) The optimum topology selection is guaranteed and does not require experienced designer knowledge since all converter topologies desired can be quickly explored and synthesized at transistor level. 2) The behavioural models developed for the basic building blocks provide high accuracy and efficiency since they take into account the major non-idealities of their actual circuit-level implementation, including both small- and large-signal effects which can cause noticeable degradation of the converter performance. Hence, our behavioural simulations show a worst-case deviation from the transistor-level simulations lower than 0.3-bit accuracy. In addition, accurate descriptions have been developed both for one- and two-stage MC OTA topologies. 3) The converter specifications are directly mapped onto transistor-level specifications by intrinsically considering the closed-loop operation of the SC circuits. Therefore, intermediate open-loop design parameters are not used. Furthermore, the mapping procedure proposed reduces the design parameter space to only three

2.3 Proposed Synthesis Procedure

37

design variables. From these design variables, the remaining parameters are optimally sized and several constraints are applied. Thus, the optimization results are found quickly. 4) Transistor-level parasitics, as well as sizes for transistors and power consumption are accurately estimated thanks to a set of Matlab routines. These routines include valuable information on the technology using look-up table techniques. 5) The bottom-up iterations are drastically reduced since the parasitics and transistorlevel parameters are well estimated from the beginning. In fact, only fine tuning is required after the post-layout parasitics are established. 6) Both high- and low-level specifications mapping are combined in a single synthesis procedure, which basically allows us to consider the dependences between the different abstraction levels and improve the synthesis results. In addition, the converter design time is drastically reduced since intermediate specifications, mapping procedures or user iterations are not required.

Chapter 3

Pipeline ADC Electrical-Level Synthesis Tool

As explained in the previous chapter, the design methodology proposed consists of three key components: a behavioural simulator to evaluate the performance of the ADC, a set of Matlab routines to map the high-level specifications onto transistorlevel specifications, and an optimization algorithm to find the most suitable solution in terms of power consumption and silicon area. The chapter will be organized as follows. Firstly, the proposed design methodology to synthesize pipeline ADCs will be presented, emphasizing the role of each component. This will then be followed by a brief description of the key components of the synthesis tool.

3.1

Synthesis Procedure

Figure 3.1 illustrates the basic flow diagram of the proposed synthesis procedure, which is part of a simulation-based synthesis methodology. It uses the high-level specifications of the converter, that is, the ENOB, sampling rate (f s ), voltage supply (vdd), etc. as a starting point. In accordance with these converter specifications, a database of feasible converter candidates is generated. If desired, the design space of topologies can be restricted by imposing, for instance, a given number of pipeline stages or a maximum number of solved bits-per-stage. Then, using an iterative procedure for each candidate, the optimization algorithm will try to find the values for certain design variables which satisfy these high-level specifications with minimum power consumption and silicon area. In our proposed methodology, the design variables have been reduced to three parameters: the unitary capacitors in the MDACs and SH (C uj ), the time constants for the OTAs (τuj )†1 and the overdrive voltage of the MOS transistors that form these amplifiers (vdsat j ). Note that there is a batch of these design variables for each pipeline stage. At each iteration, a set of Matlab routines maps the values of the design variables onto transistor-level sizes and biasing conditions, extracting the values for all 1

These will be defined later on.

J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_3, © Springer Science+Business Media, LLC 2011

39

40

3 Pipeline ADC Electrical-Level Synthesis Tool Converter specifications ENOB, fs, Vdd, …

Candidate topologies

Initial design point Cuj, vdsatj, τuj

Transistor-level mapping 00 Performance evaluation

End

Yes

Fig. 3.7 Fig. 3.11

New design point Cuj, vdsatj, τuj

No

End? Optimization

OPTIMIZATION

Optimization summary

Fig. 3.1 Proposed simulation-based synthesis methodology

parameters required by the basic building block behavioural models. A performance evaluation of the ADC is carried out from these values. A new movement in the design variable space is carried out in accordance with this evaluation. The procedure is repeated until the optimization algorithm ends. After this, the final design is stored in a database and a new entry, which includes the most salient features of the converter (power consumption, effective resolution, etc.) is created in a summary file. This procedure is repeated for each of the candidate topologies. It is worth stressing that all the topologies are synthesized up to transistor level and, therefore, the optimum ADC architecture in terms of power consumption can be selected from the synthesized candidates. As can be inferred, the three basic components in this design procedure are the behavioural simulator, the Matlab routines and the optimization algorithm. In order to ensure an efficient and accurate synthesis procedure these basic components must meet certain requirements. This issue and a brief description of the basic components will be outlined in the following sections.

3.2 Snyrcos: The Behavioural Simulator

3.2

41

Snyrcos: The Behavioural Simulator

The behavioural simulator developed is SNYRCOS (Simulink-based Nyquist-Rate Converters Simulator). It acts as performance evaluator within the synthesis procedure. In order to carry out this function efficiently some properties must be fulfilled: • accuracy, to obtain suitable agreement with the electrical results; • flexibility, to easily compose arbitrary pipeline architectures or even other types of converters or topologies; • low computational cost, to reduce the CPU time required for evaluating the performance of the ADC; • user-friendliness, to ensure intuitive and easy-to-use operation for any designer not familiar with the tool. Note that there are strong trade-offs between these properties. For instance, high accuracy can usually be ensured at the expense of computational cost, that is, the more accurate the behavioural models, the more complex they are and therefore, the longer the CPU time required for their evaluation. In order to simplify these tradeoffs, we decided to develop the behavioural simulator using the Matlab-Simulink interface. The implementation on this interface provides numerous advantages: • it is a widely-used platform, familiar to a large number of engineers. • it has direct access to very powerful tools for signal processing and data manipulation. • it has full flexibility for the creation of new architectures. • it enables high flexibility for the extension of the block library. The next subsections will be devoted to highlighting the characteristics and properties of the behavioural simulator developed under the Matlab-Simulink interface.

3.2.1 Accuracy As shown above, the behavioural simulator is used to evaluate the performance of the pipeline ADC. An accurate estimation of this performance is therefore essential for suitable agreement with the electrical results. The accuracy of the behavioural simulator will be determined by the behavioural models developed. As will be shown in the next chapter, these behavioural models present excellent agreement with the electrical results, so accuracy is guaranteed.

3.2.2

Low Computational Cost

Special attention must be paid to the way in which the behavioural models are implemented. Matlab provides numerous mechanisms, but the complexity of the models developed and the iterative nature of the synthesis procedure force us to use a

42

3 Pipeline ADC Electrical-Level Synthesis Tool

mechanism which allows us to reduce the computational cost efficiently. For instance, modelling and simulation of Ms in the Matlab-Simulink platform were reported in [107, 108]. Although highly intuitive, the implementation of the behavioural models of each basic building block requires several sets of elementary Simulink blocks using Matlab functions. This implies longer computation time. To overcome this problem, our behavioural models have been implemented in Matlab using the so-called S-functions [109]. These functions are C-written general-purpose source files which allow us to model dynamic systems both in continuous and discrete time. The result is a notable saving in simulation time, compared to using Matlab functions or M-files to code the models. For example, the simulation over 256 clock periods of a pipeline architecture considering all non-idealities takes under 2 s†2 using the simulator proposed. If analogous models are implemented using M-files, the simulation time increases by almost two orders of magnitude. This low computational cost is comparable with that obtained using hard-coded dedicated simulators [13, 110, 111]. Let us explain the implementation procedure in the Matlab-Simulink interface by means of S-functions.

3.2.2.1

Implementation Procedure

Model implementation follows a set of steps, which are illustrated in Fig. 3.2: a) Definition of a computation model. Given a set of non-idealities of the building blocks, a computation model which allows us to calculate the output samples, including the effect of all these non-idealities, must be defined. For the purpose of illustration, Fig. 3.2a shows the basic flow diagram of the behavioural model for the MDAC, which will be detailed in the next chapter. b) Implementation of the computation model into an S-function. To do so, SIMULINK provides different S-function templates which can accommodate the C-coded computation model of both DT and CT systems. These templates are composed of several routines (or callbacks) which perform the different tasks required at each simulation stage. These tasks include: variable initialization, computation of output variables, update of state variables, etc. among others. Figure 3.2b shows some significant sections of the S-function file associated with the MDAC. c) Compilation of the S-function. This is done using the mex utility provided by MATLAB [112]. The resulting object files are dynamically linked into SIMULINK when needed. d) Incorporation of the model into the SIMULINK environment. This can be done by using the S-function block of the SIMULINK libraries [113]. Figure 3.2c illustrates this process for the MDAC. A block diagram containing the S-function block is created including the input/output pins. The dialogue box is used to specify the name of the underlying S-function. In addition, model parameters are also included in this box, which can be used to modify the parameter values. 2

In a 2.4GHz@3GB RAM Intel Core2Duo computer.

3.2 Snyrcos: The Behavioural Simulator

43 #define S_FUNCTION_NAME mdac_therm2

MDAC beh. model

static void mdlInitializeConditions(SimStruct *S) { ... /* Initialize Capacitors */ work[0]=0;

Initialize capacitances

for(i=M;i>=1;i--) { work[i]=cuj*gauss(1,stdc); work[0]=work[0]+work[i];

Compute parasitics, capacitances, feedback factors, time constants

}

} static void mdlOutputs(SimStruct *S, int_T tid) { ... /*COMPUTE THE MDAC OPERATION*/ if (phi==1) { /*Evaluate transient response */

Yes

No

Sampling?

if (ota==1)

/*1 pole model*/

{ trans_1p_samp(M,cuj,cij,cfj,bja,cpaj,claj,avnl1,avnl2,avnl3,...); } Δ Δ = νij + unif – , 2 2

νij,eq

else

/*2 poles MC model */

{ trans_2p_samp(M,cij,cfj,bja,bcj,cpaj,cl1aj,cl2aj,cijnext,avnl1,...);} } else { /*Evaluate transient response*/ Transient evolution

Transient evolution

if(ota==1) /*1 pole model */ { trans_1p_amp(M,cuj,cij,cfj,bja,cpaj,claj,avnl1,avnl2,avnl3,...); }

Stored sampled voltages

b

End

else

/*2 poles MC model /

a +

In

Bits

Σ

Res –

G

DAC MDAC

1 In1 2 In2 mdac1 From

1 Out 1 mdac_therm2 1 z S-Function

Unit Delay 1

mdac1 Goto

c

Fig. 3.2 Implementation procedure of the behavioural models into the Matlab-Simulink interface

3.2.3

Flexibility

The implementation in the Matlab-Simulink interface provides high flexibility since the behavioural models are compiled and integrated into Simulink blocks. Thus, arbitrary pipeline architectures can be built by simply interconnecting the Simulink blocks. For illustration purposes, Fig. 3.3a shows the implementation of a 3-stage pipeline architecture. In actual fact, other converter topologies related to pipeline architectures, such as time-interleaved ones, could be implemented. Figure 3.3b illustrates the implementation of a two-channel time-interleaved converter. In addition, the Matlab-Simulink interface provides endless extension possibilities. On the one hand, anyone who has become accustomed to the Matlab designer could add his or her own Simulink blocks to the pipeline library and extend the

44

3 Pipeline ADC Electrical-Level Synthesis Tool + In ADC

Sine Wave

Σ

Res –

+

G

In ADC

DAC

Σ

Res –

Mdac G

ADC

DAC

Bits

Bits

Bits

SH

In

Quantizer

Stage2

stage 1 1/z

1/z I-

DAC

y

ldeal DAC

1/z

a

Overlap Bits1

ADC channel 1

d1 d2 d3

d1, d2, d3... clk

DAC

y

Ideal DAC

Mux

b

ADC Channel 2

Fig. 3.3 Building architectures in Matlab-Simulink interface: a a 3-stage pipeline architecture and b a two-channel time-interleaved converter

simulation possibilities. On the other hand, new analyses can be carried out by simply programming the post-processing routine in the user-friendly Matlab language. Finally, the behavioural simulator can be integrated with numerous toolboxes from Matlab, increasing the possibilities for analysis or optimization.

3.2.4

User-Friendliness

Implementation in the Matlab-Simulink interface provides a user-friendly environment. A Graphical User Interface (GUI) has been developed in order to complement this environment. With this interface a user can create a new architecture, post-process the simulation results or even seek help online. Figure 3.4 shows some captures of this GUI.

3.3

Low-Level Mapping Routines

A set of Matlab routines has been developed to enhance the synthesis procedure. These routines have a double purpose: • On the one hand, they must map the high-level specifications of the converter onto electrical-level specifications, in other words, onto transistor sizes and biasing

3.3 Low-Level Mapping Routines

45

Fig. 3.4 GUI of the behavioural simulator

conditions. In order to estimate these electrical-level parameters accurately, the target technology is characterized using look-up tables obtained from batches of electrical-level simulations. • On the other hand, the routines must find constraints and dependences between the electrical-parameters which allow us to reduce the design variable space, thus improving the results of the optimization procedure. First let us tackle the issue of the reduction of the design variable space. In principle, any parameter which describes the performance of the basic building blocks or components of a pipeline architecture could be identified as a design variable. However, some parameters maintain strong dependences on each other. These dependences prevent them from being freely sized. For instance, the maximum output current in a MOS differential pair depends on the required transconductance and overdrive voltage; the switch parasitic capacitances depend on the switch-on resistances required, etc. Therefore, all these dependences and constraints must be identified and the remaining degrees of freedom in the design variable space determined. For this reason, the proposed Matlab routines set these constraints and dependences simply by using three design variables as reference: the unitary capacitors, the overdrive voltages and the time constant of the OTAs. These have been conscientiously selected to efficiently reduce the design parameter space, determine dependences and define constraints and admissible ranges over the remaining parameters. An improvement in the synthesis results is thus achieved. Two procedures have

46

3 Pipeline ADC Electrical-Level Synthesis Tool

been distinguished, depending on whether one- or two-stage MC OTA topologies are used. These procedures will be widely detailed below.

3.3.1

One-Stage OTA Mapping Procedure

The first step is the identification of all parameters involved in the synthesis procedure. As explained above, any parameter which describes the behaviour of the basic building blocks in the pipeline converter could be considered a design variable. According to the basic block diagram of the pipeline stage in Fig. 1.8b, two basic building blocks can be distinguished: the sub-ADC and the MDAC†3 . Both circuits are described in our proposed behavioural models with the parameters summarized in Table 3.1, where it has been assumed that OTAs are characterized by the one-stage macromodel in Fig. 3.5. Variables σr , σc , bpc and swj are technological parameters and are therefore known. Other statistic parameters such as μoff , σoff , μhys , σhys and V offj will be initially assumed to be zero. Once the synthesis procedure is finished, maximum permissible values for these parameters will be obtained using Montecarlo Table 3.1 Parameters involved in the one-stage OTA mapping procedure Building block

Component

Parameter

sub-ADC

Resistor ladders Comparators

Unitary ladder-resistor (Ru ) and std. deviation σr Offset mean (μoff ) and std. deviation (σoff ) Hysteresis mean (μhys ) and std. deviation (σhys ) Unitary capacitor (Cf u )

MDAC

Capacitors

Unitary capacitor (Cuj ) std. deviation (σc ) and bottomplate parasitic capacitances factor (bpc ) Transconductances (gmj ), saturation currents (ioj ), DC-gain (Aoj ), offset (Vofj ) and equivalent input noise (Vnj ) input OTA OTA ) and output (coj ) parasitic capacitances (CPJ Sampling (rusj ), amplification (ruaj ), input (risj ) and output (rosj ) reset switch-on resistances and switch parasitic capacitances factor (swj )

OTAs

Switches

vij

voj

+

+

ioj voj

vij

–

OTA C pj

gmj (vij–vofj)

goj

OTA

Coj

– ioj

– Fig. 3.5 One-stage macromodel for the OTA 3

Note that the SH circuit can be easily extrapolated to an MDAC by just removing the impact of the capacitive DAC.

3.3 Low-Level Mapping Routines

47

analysis. Finally, it will also be assumed that the unitary resistor (Ru ) and capacitor (C fu ) in the sub-ADC are initially determined by electrical design considerations. Therefore, only the parameters related to the MDAC circuit are to be determined. Let us consider the pseudo-thermometer MDAC circuit in Fig. 1.17b, where the amplifier will be characterized by the single-pole network in Fig. 3.5, defined by a transconductance gmj which provides a maximum output current, ioj , an output conductance goj which determines the DC gain (Aoj = gmj /goj ), an input-referred offset voltage (V ofj ), and input/output capacitances denoted as CpjOTA and CojOTA respectively. Replacing this model in Fig. 1.17b, the equivalent circuits of Fig. 3.6a, b are obtained for the sampling (φs on) and amplification phases (φa on) respectively. In these figures, switches have been replaced by their respective switch-on resistances r usj , r uaj , r isj , r osj . C ij , i = 1, . . . , M j and C fj model the sampling and feedback capacitors respectively. r us, j + 1 , C q, j + 1 and C S, j + 1 stand respectively for the switch-on resistance, overall input capacitances of the quantizer and MDAC in the following stage. C pj and C lj stand respectively for the sum of all the capacitances at the input and output terminals of the OTA. These last capacitances can be expressed as: Cpj = CpjOTA + CpjSWC Clj = CojOTA + CojSWC vij

rusj

Cfj

rusj

C1j

(3.1)

vij ...

rusj

CMj

voj

vaj

vij Cpj

risj

rosj

gmj (vaj – vofj)

goj

Clj

a

ruaj

C1j = … = CMj = Cfj = Cuj

C1j

b1j Vref ruaj

...

bMjVref

CMj

Cpj

vaj

Cfj

ruaj

voj

gmj (vaj – vofj)

goj

rus,j +1

Cq,j +1

rus,j +1

CS,j +1

Clj

b Fig. 3.6 Equivalent circuits for the MDAC in: a sampling and b amplification phases using a one-stage OTA macromodel and considering non-zero switch-on resistances

48

3 Pipeline ADC Electrical-Level Synthesis Tool

Where CpjSWC and CojSWC agglutinate the parasitics of switches and capacitors as well as any other external capacitances loading the input and output node respectively. As can be inferred, there are still plenty of parameters to be determined. However, in the proposed mapping strategy a reduced set of parameters is used to derive the remainder. These parameters selected also act as optimization variables in the synthesis procedure featured in Fig. 3.1a. These are the unitary capacitances C uj , the time constant of the OTAs τuj , and the overdrive voltages of the transistors composing these amplifiers, vdsat j . Another variable involved in the mapping process, the Least Significant Bit of the stage, LSBj , is imposed by the resolution-per-stage of the pipeline architecture to be synthesized. Based on these variables, the parameters in Fig. 3.6 should satisfy some constraints which guide the mapping algorithm to be described later. These constraints are derived below.

3.3.1.1

Mapping Constraints

Switch-on Resistances As will be explained in the next chapter, the time constants at the input and output nodes of the single-stage OTA during the sampling phase of the MDAC (Fig. 3.6a) are given to first order as: τsj ≈ rusj Cuj + risj Ceqsj τosj ≈ rosj Cij

(3.2)

where Ceqsj = Cpj +

Mj 

Cij + Cfj

(3.3)

i=1

stands for the equivalent capacitive load during the sampling phase. Analogously, the time constant of the MDAC during the amplification phase (Fig. 3.6b) is approximately given by†4 : τaj ≈

Ceqaj + ruaj Cuj + rus,j +1 Cu,j +1 gmj (1 + βj εgaj )

(3.4)

where Ceqaj = Cpj +

Mj  i=1

Cij +

Ctj βj

(3.5)

stands for the equivalent amplifier load, Ctj = Clj + CS,j + 1 + Cq,j + 1 is the total capacitance load at the output node, and εgaj , βj are a gain error factor and a feedback 4

The RC time constant introduced by the next sub-ADC is neglected.

3.3 Low-Level Mapping Routines

49

factor respectively, defined as: βj = Cfj



⎛ ⎝Cfj + Cpj +

Mj 

⎞ Cij ⎠

(3.6)

i=1

εgaj = 1/(βj Aoj )

(3.7)

The first term in Eq. (3.4) represents the time constant of the amplifier, i.e.: τuj =

Ceqaj gmj (1 + βj εgaj )

(3.8)

which is one of the control variables in the mapping algorithm. For proper operation, the time constants τsj and τosj should be much lower than τuj and the time constant τaj should also be dominated by this term. Therefore, the switch-on resistances in Fig. 3.6 can be determined as: risj = [τuj /n − rusj Cusj ]/Ceqsj rosj = τuj /(nClj ) ruaj = τuj /(2Cuj n)

(3.9)

with a scaling factor of n  1 (a value of 5–10 is enough for most practical purposes). Additionally, it has been assumed that: rusj Cuj = rua,j −1 Cua,j −1

(3.10)

where rua,j −1 and Cua,j −1 model, respectively, the switch-on resistance during the amplification phase and the unitary capacitor of the previous j − 1-th stage, and parameters r ua, 0 and C ua, 0 correspond to the SH stage at the pipeline front-end. Therefore: rusj = (rua,j −1 Cua,j −1 )/Cuj

(3.11)

Amplifier DC Gain It can be observed that the output voltage of the MDAC when only the DC-gain error is considered is as follows: ldeal voj ,n = voj −

εga,j 1 vldeal = vldeal 1 + εga,j oj 1 + εga,j oj

(3.12)

Therefore, the error introduced due to the finite DC gain of the OTA will be determined by the difference between the real and the ideal output voltage, that is:   εga,j ldeal  ldeal = vldeal ≈ εga,j voj (3.13) εvoj = voj ,n − voj 1 + εga,j oj

50

3 Pipeline ADC Electrical-Level Synthesis Tool

The error voltage resulting from the finite OTA DC gain depends on the output voltage. The worst case corresponds to the maximum output voltage, which is 2V ref , so: = 2εga,j Vref εvmax oj

(3.14)

This error must be lower than half the quantization error at the output of the stage. Note that this quantization error depends on the remaining bits determining it in the cascade of stages. Thus, given an N-bit pipeline converter with a cascade of L stages resolving b1 , b2 , b3 , . . . , bL bits and assuming unitary redundancy, the remaining bits to solve at the output of the j-th stage will be: ⎧ N j = 0 (SH) ⎨ j  Bj = (3.15) (bj − 1) j = 1, . . . , L − 1 ⎩N − k=1

According to this definition, the LSB at the j-th stage output can be determined as follows: LSBj =

2Vref 2 Bj

(3.16)

From there, the half quantization error will be: εqj =

Vref LSBj = Bj 2 2

(3.17)

From the above considerations: < εqj εvmax oj

(3.18)

Thus, taking into account Eqs. (3.7), (3.14), (3.17) and (3.18), a minimum value for the OTA DC gain is obtained: Amin oj >

2Bj +1 βj

(3.19)

Noise Requirements for the OTA The noise contribution of the amplifier (Pnoj ) must be lower than the quantization noise (Pqj ) so that its effective resolution is not noise-limited, that is: Pnoj < Pqj

(3.20)

Assuming that Bj bits must still be solved at the output of this stage, the quantization noise can be determined as follows [20]: Pqj =

LSB2j 12

(3.21)

3.3 Low-Level Mapping Routines

51

In addition, the noise contribution of the amplifier at the MDAC output can be obtained according to the following expression [114]: Pnoj = G2j BWnvn

OT Aj

Snvn

OT Aj

(3.22)

where Snvn OTAj and BWnvn OTAj stand for the amplifier noise Power Spectral Density (PSD) and noise equivalent bandwidth during the amplification phase respectively, and Gj models the amplification gain of the MDAC. According to the time constant of the amplifier τuj , the noise equivalent bandwidth can be approximated using the following expression [1, 4, 114]: BWnvn OTAj ≈ 1/(4τuj )

(3.23)

Substituting Eq. (3.23) into Eq. (3.22), a maximum value for the noise PSD of the amplifier can be extracted by establishing a relation with Eqs. (3.21) and (3.22):  OTAj max LSB2j τuj vn (3.24) Pnoj < Pqj → Sn  < 3G2j Ignoring flicker contributions, the equivalent input noise of a one-stage OTA can be modelled as [1]: Snvn

OTAj

≈ξ

8KT (1 + ηj ) 3gmj

(3.25)

where ηj is a topology-dependent noise factor and ξ amounts to 1 for single-ended and OTA 2 for fully-differential amplifiers. Hence, by compelling the upper limit on S vn n j , min a minimum value for the transconductance, gmj , can be derived: min gmj =ξ

8KTG2j LSB2j τuj

(1 + ηj )

(3.26)

It is worth emphasizing that Eqs. (3.19) and (3.25) simply impose minimum values for the amplifier gain and noise PSD respectively. Thus, they could be considered starting points for the optimization procedure. In practice, the powers relating to error gain and noise are additive so ultimately the optimization algorithm will determine the values required to satisfy the specifications.

3.3.1.2

Mapping Procedure

We must bear in mind that the objective of this procedure is to map the converter specifications onto the transistor-level parameters and extract the values required for the behavioural model parameters. To do so, the design parameter space has been efficiently reduced by means of a set of constraints and a meticulous selection of the design variables. From the resulting sizing of the mapping procedure, a behavioural

52

3 Pipeline ADC Electrical-Level Synthesis Tool

simulation will evaluate the ADC performance taking into account all non-linearities of the basic building blocks, while the optimization algorithm will solve the noisespeed-power trade-offs using a suitable selection of the design variables as explained in Fig. 3.1. Next, we will detail the mapping procedure. Figure 3.7 shows the basic flow diagram of the synthesis procedure. The input variables are the unitary capacitors, C uj , the time constant for the OTAs, τuj , and voltage

From Fig. 3.1

Design variables Cuj, τuj, νdsatj, LSBj

(Cpj, Clj)

Initialize parasitic capacitances

(βj, Ceqaj, Ceqsj, Ctj)

Compute feedback factor and eq. loads

Compute: - Switch resistances from Eq. (3.9),Eq. (3.11) - Minimum DC gain from Eq. (3.19) - Maximum noise PSD from Eq. (3.24)

Determine extrinsic parasitic capacitances

OTA sizing

(rusj, ruaj, risj, rosj) (Aoj)min v

SWC

(Cpj

(Cpj, Clj)

Determine new switch resistances, minimum DC gain and maximum noise PSD

No

Δ

<δ

Yes

Fig. 3.7 Mapping procedure for the one-stage OTA topology

SWC

, Coj

Fig. 3.8

Compute new parasitic capacitances

OTAj max

(S nn

End

)

)

3.3 Low-Level Mapping Routines

53

overdrive for the transistors, vdsat j , together with the required LSBj of the stages. The procedure begins by guessing initial values for the parasitic capacitances (C pj , C lj ). Using these values and taking into account that the remaining capacitors (sampling, feedback and load capacitances) are known, the feedback factors (βj ) and equivalent capacitances (Ceqsj , Ceqaj , Ctj ) are computed. From there, switch resistances (rusj , ruaj , risj , rosj ), minimum DC gains (Amin oj ) and maximum noise PSD for the vnOTA

OTAs (Sn j |max ) are computed according to Eqs. (3.9–3.11), (3.19) and (3.24) respectively. Once the resistance values are known, extrinsic parasitic capacitances are computed (CpjSWC , CojSWC ). The OTAs are then fully sized at electrical level. With these sizings, it is possible to obtain real values for the intrinsic parasitic capacitances (CpjOTA , CojOTA ), and new values for the parasitics initially guessed are computed. From these new values, switch resistances, required finite DC gains and noise PSD are newly computed. If discrepancies () are higher than a user-defined tolerance value (δ) the procedure is repeated until convergence is achieved. The OTA sizing routine is depicted in Fig. 3.8. The inputs for this procedure are the unitary capacitor (C uj ), the time-constant for the OTA (τuj ), the voltage overdrive for the transistors (vdsat j ), the extrinsic parasitic capacitances (CpjSWC , CojSWC ), vnOTA

j max | ). All this inthe required DC gain (Amin oj ), and maximum noise PSD (Sn formation is inherited from the loop that appears in Fig. 3.7. Each iteration in the synthesis procedure starts by guessing initial values for the inner parasitic capacitances (CpjOTA , CojOTA ), the finite DC gain (Aoj ), and selecting the minimum lengths for the MOS transistors. From these values, intermediate variables such as feedback factor (βj ), gain error factor (εgaj ), and equivalent load (Ceqaj ) are evaluated. The min minimum value for the transconductance (gmj ) is then computed by taking into account speed (Eq. (3.8)) and noise (Eq. (3.26)) requirements, whichever happens to be most restrictive. With these data, together with the previously planned overdrive voltages (vdsat j )†5 , the sizes, the currents, and the bias voltages of the OTA MOS transistors can be calculated using technology parameters. As explained above, in our routine such parameters are extracted from look-up tables obtained from batches of electrical-level simulations. At this point, it is possible to estimate the overall power consumption of the OTA. In the following step, parasitic capacitances (CpjOTA , CojOTA ), gains, and noise factor are newly calculated and compared to those previously stored. If discrepancies () are higher than a user-defined tolerance value, (δ), the iterative procedure is repeated again until convergence is reached. Finally, if the estimated DC gain (Aoj ) is lower than the required (Amin oj ), the lengths of MOS transistors are increased and the algorithm is repeated again. It is worth mentioning that despite the iterative nature of the design procedure, it only takes three or four iterations to converge. Also, it is interesting to observe that no ad-hoc fitting parameter needs to be adjusted in the design procedure.

5 For simplicity, all transistors composing the OTA are assumed to have the same overdrive voltage. Nevertheless, in general, independent overdrive voltages could also be managed by the design methodology proposed.

54

3 Pipeline ADC Electrical-Level Synthesis Tool High-level specifications

From

SWC

Fig. 3.7

Cuj, τuj, νdsatj, Cpj

SWC

, Coj

min

, Aoj

ν

OTA j max

, Sn n

Initialize parasitic capacitances and gains

Select lengths for MOS transistors

Compute βj, εgaj, Ceqaj

Determine gm1j from speed or noise req.

Amp. topology technological parameters, νdsatj

Determine sizes, currents and power

Compute new parasitic capacitances and gains

No

Δ <δ Yes End

Yes

min

Aoj > Aoj

No

Increase lengths

Fig. 3.8 One-stage OTA sizing routine

3.3.2

Two-Stage MC OTA Procedure

A similar procedure has been developed for two-stage MC OTA topologies. In this case, the parameters involved are summarized in Table 3.2, where it has been assumed that the amplifier is described by the macromodel in Fig. 3.9. There, each stage is characterized by a single-pole network defined by a transconductance

3.3 Low-Level Mapping Routines

55

Table 3.2 Parameters involved in the two-stage MC OTA mapping procedure Building block

Component

Parameter

sub-ADC

Resistor ladder Comparators

Unitary ladder-resistor (Ru ) and std. deviation (σr ) Offset mean (μoff ) and std. deviation (σoff ) Hysteresis mean (μhys ) and std. deviation (σhys ) Unitary capacitor (Cf u )

MDAC

Capacitors

Unitary capacitor (Cuj ), std. deviation (σc ) and bottomplate parasitic capacitances factor (bpc ) Transconductances (gm1j , gm2j , ) saturation currents (io1j , io2j , ), DC gains (Ao1j , Ao2j , ) offset (Vofj ) and equivalent input noise (Vnj ) input (CpjOTA ) and output OTA OTA , Co2j ) parasitic capacitances (Co1j Sampling (rusj ), amplification (ruaj ) input (risj ), and output (ros1j , ros2j ) reset switch-on resistances and switch parasitic capacitances factor (swj )

OTA

Switches

vo1j

Ccj

io1j

vij

OTA Cpj

gm1j (vij–vofj)

voj io2j

go1j

– io1j

OTA Co1j

gm2j vo1j

go2j

OTA

Co2j

– io2j

Fig. 3.9 Two-stage MC macromodel for the OTA

(gm1j , gm2j ) which provides a maximum output current (io1j , io2j ), output resistance (go1j , go2j ) which determines the stage gain (Ao1j = gm1j /go1j , Ao2j = gm2j /go2j ), OTA OTA and output capacitance (Co1j , Co2j ). Capacitor CpjOTA represents the input capacitance of the amplifier, V ofj stands for the input-referred offset voltage and the Miller capacitor C cj provides the frequency compensation mechanism. By substituing this macromodel into Fig. 1.17b, the circuits equivalent to those in Fig. 3.10a, b are obtained for the sampling (φs on) and amplification (φa on) phases of the MDAC circuit respectively. Again, the switches have been replaced by their respective switch-on resistances r usj , r uaj , r isj , r osj , r os2j . r us,j + 1 , C q,j + 1 , and C S,j + 1 stand, respectively, for the switch-on resistance, overall input capacitances of the quantizer and MDAC in the following stage. C pj ,C o1j and C lj stand for the sum of all the capacitances at the input, intermediate and output terminals of the OTA respectively. These capacitances include the parasitics associated with switches and capacitors as well as any other external capacitances loading the node. Hence, similarly to Eq. (3.1), it can be stated that: Cpj = CpjOT A + CpjSW C OT A SW C Co1j = Co1j + Co1j

Clj = CojOT A + CojSW C

(3.27)

56

3 Pipeline ADC Electrical-Level Synthesis Tool rusj

Cfj

rusj

C1j

vij

C1j = … = CMj = Cfj = Cuj

vij ...

CMj

rusj

vij risj

Cpj

Ccj

vo1j

vaj ros1j

gm1j (vaj – vofj)

go1j

Co1j

voj gm2j vo1j go2jClj

ros2j

a rus, j + 1 b1jVref

ruaj

C1j ...

bMjVref

ruaj

CMj vaj Cfj

Cq, j + 1

rus, j + 1 CS, j + 1 ruaj

Ccj

voj

Cpj

go2j

Co2j

gm2j vo1j

b

vo1j

gm1j (vaj – vofj)

go1j

Clj

Fig. 3.10 Equivalent circuits for the MDAC in: a sampling and b amplification clock phases using a two-stage MC OTA macromodel and considering non-zero switch-on resistances for the switches

Again, the optimization variables will be the unitary capacitance, C uj , the time constant of the OTA, τuj , and the overdrive voltages of the transistors making up this amplifier, vdsat j . The Least Significant Bit of the stage, LSBj , will also be considered. In addition, a set of constraints will be considered when sizing certain parameters. 3.3.2.1

Mapping Constraints

Switch-on Resistances Following similar reasoning to that of the one-stage mapping procedure, the switchon resistances in Fig. 3.10 are constrained by the expressions: risj = [τuj /n − rusj Cuj ]/Ceqsj   4β 2 cj gm2j 1 + βcj (1 + Clj /Ccj ) rosj = 1+ −1 2βcj gm2j αj nCcj [1 + βcj (1 + Clj /Ccj )]2 rusj = (rua,j −1 Cu,j −1 )/Cuj ruaj = τuj /(2Cuj n)

(3.28)

where βcj = C cj /(C o1j + C cj ). It has also been assumed that: rosj = ros1j = ros2j

(3.29)

3.3 Low-Level Mapping Routines

57

Amplifier DC Gain Following analogous reasoning, a minimum value for the OTA DC gain is obtained: Bj +1 Amin /βj oj > 2

(3.30)

Critically-Damped Response As will be explained in the next chapter, a critically damped response is imposed for the two-stage MC OTA. For this purpose, a new constraint must be considered over the pole systems. It can be demonstrated that the closed-loop poles for the MDAC during the amplification phase (Fig. 3.10), when switch-on resistances are neglected, are determined by the next expression: p1,2 = −αj ± iωdj

(3.31)

 where αj = ξj ωnj and ωdj = ωnj 1 − ξj 2 with: 

 gm2j 1 (1 + εg2j ) − gm1j (1 − εg1j ) ξj = βj 2Ceqaj ωnj g g m2j m1j 2 = (1 + εgj ) ωnj Ccj Ceqaj

(3.32)

Where εgj , εg1j , and εg2j are gain-error factors defined as: εgj = 1/(βj Ao1j Ao2j )   εg1j =

1 βj Ao1j

1 + Cpj +

Mj 





Cij + Ctj /βj /Ccj

(3.33)

i=1

εg2j = 1/(Ao2j βcj ) with ⎛ Ceqaj = ⎝Cpj +

Mj  i=1

⎞ Cij +

Co1j Ctj ⎠ 1 + βj βcj βj

(3.34)

standing for the equivalent amplifier load. In order to achieve a critically-damped response, ωdj = 0, or in other words:  ξj =

 gm2j 1 (1 + εg2j ) − gm1j (1 − εg1j ) =1 2Ceqaj ωnj βj

(3.35)

58

3 Pipeline ADC Electrical-Level Synthesis Tool

Eq. (3.35) imposes a constraint between the transconductances. In fact, Eq. (3.35) is satisfied if the transconductances ratio is: Rj =

gm2j βj (1 − εg1j ) 2βj Ceqaj (1 + εgj ) = + gm1j 1 + εg2j Ccj (1 + εg2j )2    (1 + εg2j )(1 + εg1j )Ccj × 1+ 1+ (1 + εgj )2 βj Ceqaj

(3.36)

As can be inferred, the factor Rj only depends on the capacitances and error gains. If this relation is satisfied, it can be deduced that the system poles are determined by the next expression: αj = 

2gm1j (1 + εgj )  1−ε − Rjg1j Ccj

1+εg2j βj

(3.37)

Therefore, given a certain requirement for the time constant of the amplifier, τuj , or in other words, over the system pole (αj = 1/τuj ), and assuming a critically-damped response, a specific value is required for the first-stage transconductance:   1 − εg1j 1 + εg2j Ccj αj − βj Rj (3.38) gm1j = 2(1 + εgj ) Noise Requirements for the OTA Again, the noise contribution of the amplifier (Pnoj ) must be lower than the quantization noise (Paj ). We should bear in mind the expressions for these noise powers: Pqj =

LSB2j

(3.39)

12 v

Pnoj = Gj 2 BWn n

OTA

j

Snvn

OTAj

(3.40)

Assuming a double-pole (αj ) closed-loop transfer function, i.e., a critically-damped closed-loop response, the noise equivalent bandwidth can be approximated using the following expression: BWnvn

OTAj

≈ αj /8

(3.41)

Substituing Eq. (3.41) into Eq. (3.40), a maximum value for the noise PSD of the amplifier can be extracted by relating Eqs. (3.39) and (3.40): Pnoj < Pqj → Snvn

OTAj

j max 2LSB2  <  3αj Gj 2

(3.42)

3.3 Low-Level Mapping Routines

59

Neglecting flicker noise and the contribution of the second stage, the equivalent input noise of a two-stage MC OTA can be modelled as [1]: v

Snn

OTA

j

≈

8KT (1 + ηj ) 3gm1j

(3.43)

Where ηj is a topology-dependent noise factor. Hence, by compelling the upper limit OTA min on S vn n j , a minimum value for the transconductance, gm1j , can be derived: j

min = gm1j

4KTG2 αj (1 + ηj ) LSB2j

(3.44)

Analogously, Eqs. (3.30) and (3.43) simply impose minimum values for the amplifier gain and noise PSD, respectively. Thus, they could be considered to be starting points for the optimization procedure. In practice, the powers relating to error gain and noise are additive so the optimization algorithm will ultimately determine the values required to satisfy the specifications. It is worth noticing that although mapping constraints relies on small-signal considerations, the behavioral models employed for performance evaluation and hence for guiding the optimization process, accounts for nonlinear behaviors.

3.3.2.2

Mapping Procedure

Taking into account these constraints and dependences, a complex procedure is carried out to size the pipeline stages automatically. Figure 3.11 shows the basic flow diagram of the synthesis procedure. The input variables are the unitary capacitors, C uj , the time constant for the OTAs, τuj = 1/αj , and voltage overdrive for the transistors, vdsat j , together with the required LSBj of the stages. The procedure begins by guessing initial values for the parasitic capacitances (C pj , C o1j , C lj ). From these values and taking into account that the remaining capacitors, (sampling, feedback and load capacitances) are known, the feedback factors (βj , βcj ) and equivalent capacitances (C eqsj , C eqaj , C tj ) are computed. From there, switch-on resistances (r usj , r uaj , r isj , r os1j , r os2j ), minimum DC gain (Amin oj ) and maximum noise PSD for the v

OTA

OTA (Snn j|max ) are computed according to Eqs. (3.28), (3.30) and (3.42) respectively. Once the resistance values are known, extrinsic parasitic capacitances are SWC SWC computed (CpjSWC , Co1j , Co2j ). Then, the OTAs are fully sized at electrical level. From this sizing, real values for the intrinsic parasitic capacitances can be obtained OTA OTA (CpjOTA , Co1j , Co2j ), and new values for the parasitics initially guessed are computed. From these new values, switch-on resistances, required finite DC gain, and noise PSD are computed once again. If discrepancies () are higher than a user-defined tolerance value (δ) the procedure is repeated until convergence is achieved. The OTA sizing routine is depicted in Fig. 3.12. The inputs for this procedure are the unitary capacitor (C uj ), the time constant for the OTA (τuj = 1/αj ), the voltage overdrive for the transistors (vdsat j ), the extrinsic parasitic capacitances (CpjSWC , CojSWC ),

60

3 Pipeline ADC Electrical-Level Synthesis Tool Design variables Cuj, αj, vdsatj, LSBj

From Fig. 3.1

(Cpj, Co1j, Clj)

Initialize parasitic capacitances

(βj, βcj, Ceqaj, Ceqsj, Ctj)

Compute feedback factor and eq. loads

(rusj, ruaj, risj, ros1j, ros2j)

Compute: - Switch resistances from Eq. (3.28) - Minimum DC gain from Eq. (3.30) - Maximum noise PSD from Eq. (3.42)

OTAj max

v Snn

SWC

(Cpj

Determine extrinsic parasitic capacitances

OTA sizing

min

Aoj

SWC

SWC

, Co1j , Co2j )

Fig. 3.12

Compute new parasitic capacitances

(Cpj, Co1j, Clj)

Determine new switch resistances, minimum DC gain and maximum noise PSD

No

Δ <δ

Yes End

Fig. 3.11 Mapping procedure for the two-stage MC OTA topology

vn OTAj max | ). All this inforthe required DC gain (Amin oj ), and maximum noise PSD (Sn mation is inherited from the loop in Fig. 3.11. The OTA sizing procedure consists of a computational loop with the compensation capacitor (C cj ) as running variable. Bound values (C cji and C cjf ) and discrete increments (C cj ) are user-defined. At each iteration, a new configuration (new transistor sizes and biasing currents) is obtained and the corresponding power consumption is stored. When the loop stops, the routine selects the configuration with the lowest power consumption as the final outcome of the algorithm.

3.3 Low-Level Mapping Routines

From Fig. 3.11

61 High-level specifications SWC

Cuj, αj, vdsatj, Cpj

SWC

, Coj

min

OTA

v

, Aoj , Sn, n

j max

For Ccj = Ccji : Δ Ccj : Ccfj

End

OTA

OTA

Ao1j, Ao2j, ηj

Select lengths for MOS transistors

Compute βj, βcj, εgj, εg1j, εg2j, Ceqaj, Ctj, Rj

Determine gm1j from speed or noise req.

gm2j = Rjgm1j

Amp. topology, technological parameters, vdsatj

Determine sizes, currents and power

Compute new parasitic capacitances and gains

Δ <δ

No

Yes

Yes

Fig. 3.12 Two-stage MC OTA sizing routine

min

Aoj >Aoj

OTA

Cpj , Co1j , Co2j

Initialize parasitic capacitances and gains

No

Increase lengths

62

3 Pipeline ADC Electrical-Level Synthesis Tool

Each iteration in the aforementioned loop starts by guessing initial values for OTA OTA the intrinsic parasitic capacitances (CpjOTA , Co1j , Co2j ), the finite DC gains of both amplifier stages (Ao1j , Ao2j ) and selecting the minimum lengths for the MOS transistors. From these values, intermediate variables, such as feedback (βj , βcj ) and error (εgj , εg1j , εg2j ) factors, equivalent loads (C eqaj , C tj ), and transconductance ratio (Rj ), are evaluated according to the expressions previously reported. Then, the minimum value for the transconductance of the first stage (gm1j ) is computed by taking into account speed, Eq. (3.38), and noise, Eq. (3.44), requirements, whichever happens to be most restrictive. Next, the transconductance of the second stage (gm2j ) is calculated from the calculated transconductance ratio (Rj ). With these data, and the previously planned overdrive voltages†6 , the sizes, currents, and bias voltages of the OTA MOS transistors can be calculated using technology parameters. In our routine such parameters are extracted from look-up tables obtained from batches of electrical-level simulations. At this point, the overall power consumption of the OTA OTA OTA can be estimated. In the next step, intrinsic parasitic capacitances (CpjOTA , Co1j , Co2j ) and gains are newly calculated and compared to those previously stored. If discrepancies () are higher than a user-defined tolerance value, δ, the iterative process is repeated again until convergence is reached. Finally, if the estimated DC gain (Aoj ) is lower than that required (Amin oj ), the lengths of MOS transistors are increased and the algorithm is repeated once more. It is worth mentioning that despite the iterative nature of the design procedure, it only takes three or four iterations to converge. It is also interesting to observe that no ad-hoc fitting parameter needs to be adjusted in the design procedure.

3.4

Optimization Algorithms

The objective of the optimization algorithms is to find the values for the design variables which satisfy the converter high-level specifications with minimum power consumption and silicon area. For this purpose, the proposed synthesis toolbox has been combined with two main optimization algorithms: • The Matlab genetic algorithm and direct search toolbox [115]. • A simulated annealing optimization algorithm [13]. Both algorithms lead to similar results, but the simulated annealing algorithm is the option preferred given that the formulation of the cost function is very versatile: multiple targets with various weights, constraints, dependent variables, and logarithmic grids are permitted. In addition, this optimization procedure has been extensively tested for design problems involving behavioural and electrical simulators [13, 25]. 6 Again, all transistors composing the OTA are assumed to have the same overdrive voltage. Nevertheless, in general, independent overdrive voltages could also be managed with the design methodology proposed.

3.4 Optimization Algorithms

63

Design variable space discretization Statistical optimization Main optimization

Cost function evaluation

End?

Update design variable

Deterministic optimization Local optimization

End?

Update design variable

Fig. 3.13 Simulated-annealing optimization procedure

Unlike conventional simulated annealing procedures, in which the control parameter—commonly named temperature—follows a predefined temporal evolution pattern, the global optimization algorithm implemented dynamically adapts this temperature to approximate a predefined evolution pattern of the acceptance ratio (accepted movements/total number of iterations). This idea prevents excessively high temperatures which will make convergence difficult or inappropriately low temperatures which can cause the algorithm to become stuck on a local minimum. The amplitude of parameter movements through the design space is also synchronized with the temperature for improved convergence. The optimization process is divided into two steps as shown in Fig. 3.13: • The first step explores the design space by dividing it into a multi-dimensional grid, resulting in a mesh of hypercubes (main optimization). A statistical method is applied in this step to escape from local minima, as there is a non-zero probability of accepting movements that increase the cost function. • Once the optimum hypercube has been obtained, a final optimization is performed inside this hypercube (local optimization). A deterministic method is usually applied in this step, with the calculation of the design parameter perturbations requiring information on the cost function and on their derivatives. For reasons of efficiency, this optimization core has been conceived as an independent application, whereas the behavioural simulator runs in Matlab-Simulink. In

64

3 Pipeline ADC Electrical-Level Synthesis Tool

order to integrate both processes, a special-purpose application has been developed using the MATLAB engine library [112]. This application is responsible for the communication between the optimization core and the behavioural simulator, with the optimization core running in the background while Matlab acts as a computation engine.

Chapter 4

Behavioural Modelling of Pipeline ADCs

The basic building blocks of a pipeline architecture are subjected to several non-idealities which degrade the converter performance considerably. Thus, the development of models which take into account all these non-idealities is essential for the correct evaluation of the performance of the pipeline ADC. These models must satisfy two fundamental requirements: reliability and efficiency. The former will determine the verisimilitude between the actual performance of the ADC and the prediction of the models, while the latter will determine the time required for the evaluation of this performance. It is obvious that accurate and speedy models are desirable. However, there is a strong trade-off between both requirements, that is to say, the more accurate the models, the more complex they will be, and therefore, the greater the CPU time required to evaluate the converter performance. To overcome this trade-off, the so-called behavioural modelling technique has been successfully used in recent years [101, 107, 116, 117]. This technique provides reasonable precision, as well as low CPU requirements. Hence, we have opted for developing models for the basic building blocks of the pipeline converter using this technique. This chapter proposes to describe these behavioural models. Firstly, the main non-idealities of the basic building blocks will be identified and analytical equations obtained. Simultaneously, several comparisons with transistor-level simulations will be carried out to illustrate the reliability and confidentiality of the models proposed. In conclusion, the behavioural models developed taking all non-idealities into account will be described by means of block diagrams.

4.1

Non-Idealities in SH and MDACS

As shown in Chap. 1, the core of a pipeline converter is basically composed of an SH at the front followed by an arbitrary number of stages. Each stage consists of an MDAC and a sub-ADC. Therefore, the inner structure of a pipeline ADC comprises three basic building blocks: the SH, the MDAC and the sub-ADC. In this section, we focus on the non-idealities associated with the first two circuits, e.g., the SH and the MDAC. Both circuits can be implemented in practice by means of SC circuits J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_4, © Springer Science+Business Media, LLC 2011

65

66

4 Behavioural Modelling of Pipeline ADCs φa

φs

νi

Cs

Clock phases φs

– νo

φs

φa

φs

+

a – C1

φs

CM

...

φa

...

φs

φs

νo

φs

Cf

φa

φs

+

φa

νi M = 2b –1 – 1

b

b1 Vref

...

bM Vref

C1 = … = CM = Cf = Cu

Fig. 4.1 Simplified schematics of a: a SH flip-around and b b-bits pseudothermometer MDAC using unitary redundancy

as illustrated in Fig. 4.1, where the basic components are switches, capacitors, and OTAs. These components are associated with a set of non-idealities, summarized in Table 4.1, which will degrade the ideal performance of the circuits. The aim of this section is to study the effect of all non-idealities on the ideal performance. Note that the SH circuit can be easily extrapolated to an MDAC by merely removing the impact of the capacitive DAC. Therefore, we pay attention below to the behavioural modelling of MDACs. Table 4.1 Basic components in SH and MDAC circuits and their non-idealities

Component

Non-idealities

Switches

Non-zero switch-on resistance, parasitics, thermal noise Non-linearity, bottom&plate parasitics, mismatch Output saturation voltage, finite and non-linear DC gain, slew-rate, thermal noise, offset, parasitic capacitances, dynamic limitations

Capacitors OTAs

4.1 Non-Idealities in SH and MDACS

4.1.1

67

Ideal Performance of the MDAC

The basic operation of an MDAC requires two consecutive clock phases. In the first phase φs , called the sampling phase, the input signal vi is sampled and stored in the MDAC, while in the second phase φa , called the amplification phase, the MDAC obtains the residue, i. e. the difference between the sampled input and the value obtained by encoding the bits (b1 , b2 , . . . , bM ) solved by the sub-ADC back to analog domain. Finally, this difference is amplified by the MDAC gain factor. By considering the b-bit pseudo-thermometer MDAC in Fig. 4.1b we will obtain an analytical equation. Denoting all variables relating to the MDAC under study with the subscript -j-, the charge stored in the capacitors at the end of the sampling phase will be determined by†1 : ⎞ ⎛ Mj  Qj , n−1/2 = ⎝Cfj + Cij ⎠ vij , n−1/2 (4.1) i=1

Analogously, it is possible to infer the charge stored in the capacitors at the end of the amplification phase: Qj , n = Cfj voj , n +

Mj 

Cij b¯ij , n Vref

(4.2)

i=1

where b¯ij , n and V ref stand for the output bits from the sub-ADC and the voltage reference, respectively. Therefore, the charge conservation principle leads to the next expression for the ideal output voltage of the MDAC: ldeal voj ,n

where

Mj 1  ¯ = Gj vij , n−1/2 − Cij bij , n Vref Cfj i=1

⎛ Gj = ⎝Cfj +

Mj 

⎞ Cij ⎠

Cfj

(4.3)

(4.4)

i=1

stands for the gain factor of the MDAC. Figure 4.2 depicts the input-output characteristic of a 2-bit thermometer MDAC together with the output bits from the sub-ADC. Note that unitary redundancy as explained in Chap. 1 has been assumed, so the gain factor has been halved and all capacitors are unitary, i. e.: Cfj = Cuj Cij = Cuj 1

i = 1, . . . , M

(4.5)

The notation vx,n will be used to represent vx (nT s ), where T s stands for the sampling period.

68

4 Behavioural Modelling of Pipeline ADCs

Fig. 4.2 Ideal input-output characteristic of a 2-bit thermometer MDAC

νo

Vref

2

b1 = –1

b1 = 0

b1 = 1

–Vref –Vref

–Vref /4 0 Vref /4

Vref

νi

Equation (4.3) describes the ideal performance of the MDAC. However, this ideal performance will be degraded by all the non-idealities mentioned above. The following subsections will be devoted to studying the influence of these non-idealities on the ideal performance of the MDAC.

4.1.2

Capacitors Mismatch

During the fabrication process, the capacitors are affected by gradients and errors which cause deviations of the nominal values of the capacitances. These deviations are assumed to follow a Gaussian distribution [118], so the capacitors can be defined as follows: Cfj = Cfjo (1 + εm ) Cij = Cijo (1 + εm )

i = 1, . . . , M

(4.6)

where εm is a normally-distributed random variable with zero mean and the standard deviation, σc , has a value derived from technological matching parameters; Cfjo and Cijo stand for the nominal capacitance values of the feedback and sampling capacitors respectively. It can be inferred from Eq. (4.3) that a mismatch between capacitors introduces both an error in the gain factor, and displacements of the segments, in the MDAC input-output characteristic. This is directly translated into a non-linear error in the input-output characteristic of the converter. For illustration purposes, Fig. 4.3 shows the deviations caused by the capacitor mismatch from the ideal input-output characteristic of a 2-bit MDAC with unitary redundancy.

4.1 Non-Idealities in SH and MDACS Fig. 4.3 Input-output characteristic of a 2-bit thermometer MDAC under the effect of capacitor mismatch

69 νo

Vref

b1 = –1

–Vref –Vref

4.1.3

b1 = 0 –Vref /4

0 Vref /4

b1 = 1 Vref

νi

Dynamic Limitations: Small-Signal Effects

The dynamic evolution of the SC circuits under ideal conditions is assumed to be instantaneous. However, the non-idealities of the real circuits degrades this dynamic evolution. One of the most critical elements, among others, is the OTA. This device presents a limited dynamic evolution, generally dominated by one or two poles. In addition, it introduces other non-idealities such as a finite DC gain, slew-rate, output saturation voltage, etc. There are numerous publications [119–126] where the performance of the OTAs and the impact of their non-idealities in analog applications have been reported. Herein, these studies will be complemented by a detailed description of large-signal effects and distortion mechanisms which make these behavioural models, to the best of our knowledge, the most accurate models reported up to date. In this section, behavioural models taking into account the traditional small-signal models for the OTA will be considered. Both one- and two-stage MC small-signal models for the OTA will be used. After that, the influence of some critical large-signal effects will be studied. 4.1.3.1

One-Stage OTA Model

Let us again consider the one-stage macromodel for the OTA shown in Fig. 3.5, and belonging to the j-th MDAC. By replacing this macromodel†2 in the MDAC circuit in Fig. 4.1b, the equivalent circuits depicted in Fig. 4.4a, b for the sampling and amplification phase are obtained respectively. Switch-on resistances are assumed to be null-their impact on dynamics is shown in Sect. 4.1.5. Transient evolutions can be calculated by solving the resulting dynamic system. The operation of the 2

Neglect the saturation currents at this point.

70

4 Behavioural Modelling of Pipeline ADCs Cfj vij C1j νij ...

CMj

νaj

νij

νoj

gmj (νaj – νofj )

Cpj

goj

Clj

a C1j

Cq, j + 1

b1jVref CMj

νaj

...

... bMjVref

Cfj

νoj gmj (νaj – νofj )

Cpj

CS, j + 1 goj

Clj

b Fig. 4.4 Equivalent circuits in: a sampling and b amplification clock phases using a one-pole OTA macromodel

MDAC will be analyzed in both phases. During the sampling phase, the sampling and feedback capacitors store the input voltage while the OTA is reset. If the switches are ideal, the charge transfer can be assumed to be instantaneous. However, errors in the resetting process produce residual voltages at both nodes at the end of the sampling phase (vaj, n − 1/2 , voj, n−1/2 ). Then, at the beginning of the amplification phase, a redistribution of the charge is carried out and, as a result, initial voltages are induced on the input and output nodes of the amplifier. The charge conservation principle provides these initial voltages: Cq,j +1 CS,j +1 q,j +1 S,j +1 V Cn−1/2 + V Cn−1/2 − · · · Ceqaj Ceqaj ⎞ ⎛   Mj Mj   Ctj Ctj 1 ⎠ 1 vij, n−1/2 ··· − 1 + b¯ij, n Cij Vref − ⎝ Cij + Ceqaj Cfj Ceqaj i=1 G j i=1

+ vaj , n−1/2 = vaj , n−1/2 +

(4.7) + voj , n−1/2 =





1 q,j +1 S,j +1 Cq,j +1 V Cn−1/2 + CS,j +1 V Cn−1/2 + Clj voj , n−1/2 + · · · βj Ceqaj   Mj Cpj Ctj 1 ¯ ··· + bij , n Cij Vref vij , n−1/2 + βj 1 + (4.8) Ceqaj Cfj Ceqaj i=1

q,j +1

S,j +1

where V Cn−1/2 and V Cn−1/2 stand, respectively, for the stored voltage in the load capacitances of the quantizer, and the MDAC in the j + 1-th stage in the previous

4.1 Non-Idealities in SH and MDACS Table 4.2 Relevant parameters in the amplification phase for the j-th MDAC using a one-stage OTA model

71

Parameter Nominal residue gain

Definition  Gj = Cfj + 

Feedback factor

Mj 

 Cij /Cfj

i=1

βj = Cfj / Cfj + Cpj +

Mj 

 Cij

i=1

Total load capacitance

Ctj = Ctj + CS,j +1 + Cq,j +1

Equivalent closed-loop capacitance

Ceqaj = Cpj +

Error gain factor

εgaj =

Constant time of the system

τaj =

Mj 

Cij +

i=1

Ctj βj

1 βj Aoj Ceqaj gmj (1 + βj εgaj )

clock phase. The remaining unknown parameters are defined in Table 4.2. From these initial conditions, the system evolves according to the single-pole network. By analyzing the equivalent circuit in Fig. 4.4b, the input and output voltages of the amplifier can be deduced:    vofj βj εga,j vaj, n − 1/2 + −t/τaj ldeal vaj (t) = vaj , n−1/2 e (1 − e − t/τaj ) + + − voj 1 + εgaj 1 + εga,j βj voj (t) =

1 ldeal [vaj (t) − vaj, n−1/2 ] + voj βj

(4.9)

where it has been assumed that the amplification phase starts at t = 0. From Eq. (4.9) it can be inferred that the system evolves according to a constant time τaj , which basically depends on the transconductance of the amplifier and the equivalent closed-loop capacitance. 4.1.3.2 Two-Stage MC OTA Model One-stage amplifiers are inherently stable. This characteristic makes them the option preferred by most designers. However, they present serious drawbacks in low-voltage applications where high DC-gain and output swing voltages must be simultaneously satisfied. In this case, amplifiers of at least two stages must be used, with a first stage providing high gain, and the second, large swings. Nevertheless, the multiple poles characteristic of these amplifiers require the use of compensation to warrant the stability. Herein, we focus on the well-known MC technique [1–5]. Note that the development of behavioural models for two-stage amplifiers is practically mandatory in the scope of this monograph since: (1) there is a growing trend towards low-voltage applications and deep submicron technologies and (2) high DC gain is normally required for medium-high resolution pipeline ADCs.

72

4 Behavioural Modelling of Pipeline ADCs Cfj

vij C1j vij ...

CMj

vo1j

vaj

vij

gm1j (vaj – vofj )

Cpj

voj

Ccj

go1j

Co1j

gm2j vo1j

go2j

Clj

a Cq, j +1 C1j b1jVref

CS, j +1 ...

bMjVref

CMj

vaj

Cfj

gm2j vo1j

Cpj

Ccj

voj go2j

Clj

vo1j gm1j (vaj – vofj)

go1j

Co1j

b Fig. 4.5 Equivalent circuits in: a sampling and b amplification clock phases using a two-stage MC OTA macromodel

Let us consider the two-stage MC OTA topology in Fig. 3.9 again. By replacing this macromodel in the MDAC circuit in Fig. 4.1b the equivalent circuits depicted in Fig. 4.5a, b respectively for the sampling and amplification phase are obtained. Following an approach similar to that of the single-stage OTA model, the initial voltages at the start of the amplification phase are given by Eqs. (4.10)−(4.12), q,j +1 S,j +1 where V Cn−1/2 and V Cn−1/2 stand for the stored voltage in the load capacitances of the quantizer and the MDAC in the j + 1-th stage in the previous clock phase respectively. The remaining unknown parameters are defined in Table 4.3.    1 q,j +1 q,j +1 1 + C + ··· voj, = V C + C V C q,j +1 S,j +1 n−1/2 n−1/2 n−1/2 βcj Ceqaj βj ⎡ ⎤  Mj  Clj + βcj Co1j 1 ⎣Cpj vij, n−1/2 + ··· + voj, n−1/2 b¯ij,n Cij Vref ⎦ + βcj Ceqaj βj i=1 ⎡

+ vaj, n−1/2 =

⎤

(4.10)

Mj    1 ⎣ 1 Cfj + βcj Co1j + Ctj Cij vij , n−1/2 − b¯ij, n Cij Vref ⎦ + · · · βcj Ceqaj Cfj i=1

! 1 q,j +1 q,j +1 Cq,j +1 V Cn−1/2 + CS,j +1 V Cn−1/2 · · · βcj Ceqaj " · · · − (βcj Co1j + Ctj )vij , n−1/2 + · · ·   vaj, n−1/2 Clj 1 ··· + Co1j + voj, n−1/2 + βj βcj Ceqaj βcj

··· +

(4.11)

4.1 Non-Idealities in SH and MDACS

73

Table 4.3 Relevant parameters in the amplification phase for the j-th MDAC using a two-stage MC OTA model Parameter Definition   Mj  Nominal residue gain Gj = Cfj + Cij /Cfj 

i=1

βj = Cfj / Cfj + Cpj +

Feedback factor

Mj 

 Cij

i=1

Feedback compensation factor

βcj = Ccj /(Ccj + Co1j )

Total load capacitance

Ctj = Clj + Cs,j +1 + Cq,j +1 

Mj 

Ctj = Cpj + Cij + βj i=1

Equivalent closed-loop capacitance

Ceqaj

Total error gain factor

εgj = 1/(βj Ao1j Ao2j )

1st-stage error gain factor

εg1j

1 = βj Ao1j



 1 + Cpj +

2nd-stage error gain factor

εg2j = 1/(Ao2j βcj )

Damping factor in a critically-damped evolution

αj =



+ vo1j , n−1/2

=

1 Ceqaj



Co1j 1 + βcj βj

Mj 





Cij + Ctj /βj /Ccj

i=1

 gm2j 1 (1 + εg2j ) − gm1j (1 − εg1j ) βj 2Ceqaj

  1  q,j +1 q,j +1 Cq,j +1 V Cn−1/2 + CS,j +1 V Cn−1/2 + Cpj vij , n−1/2 + · · · βj ⎡

··· +



1 Ceqaj

⎞ + C C q, j +1 S,j +1 ⎠ ⎣ Cij + b¯ij , n Cij Vref + ⎝Cpj + β j i=1 i=1 ⎤ ⎛

Mj 

Mj 

× voj, n−1/2 ⎦ + vo1j, n−1/2 /(βj βcj )

(4.12)

From these initial conditions, the system evolves according to the two-pole network in Fig. 4.5b. By analyzing the equivalent circuit it can be deduced that the poles are given by the next expression: p1,2 = −αj ± iωdj

(4.13)

where αj and ωdj are defined as follows: αj = ξj ωnj  ωdj = ωnj 1 − ξj 2

(4.14)

74

4 Behavioural Modelling of Pipeline ADCs

1.4

ξj = 0

ξj = 1.5

1.2

ξj < 1

ξj = 1 ξj = 0.7

ωdj ξj =1 αj

θ

Ouput

1

ξj = 0.4

0.8 0.6 0.4

ξj > 1

0.2 0

a

b

0

0.5

1 time

1.5

2

Fig. 4.6 System evolution: a position of the poles in s-plane and b step response

with 

 gm2j  1 + εg2j − gm1j 1 − εg1j βj gm1j gm2j = (1 + εgj ) Ccj Ceqaj

ξj = ω2 nj



1 2Ceqaj ωnj (4.15)

The constant ξj is called the damping ratio; ωnj , the natural frequency; αj , the damping factor; and ωdj , the damped or actual frequency [127]. Depending on the value of the damping ratio, the four situations summarized in Table 4.4 can be distinguished. The position of the poles in the s-plane and the step response are graphically illustrated in Fig. 4.6. As far as settling time is concerned, a damping ratio equal to 0.7 is the optimum value. Nevertheless, we will assume a damping ratio equal to unity, or in other words, a critically-damped response in the proposed design methodology. This choice still keeps a fast response, is easier to study and is more conservative in terms of stability, since the optimum situation (ξj = 0.7) is closer to the underdamped response. However, even if a critically-damped response is assumed the analytical equations which describe the transient evolution in all situations in Table 4.4 must be obtained since the large-signal effects can temporarily modify the pole positions and, as a result, the evolution mode. This aspect will be detailed in Sect. 4.1.4.2. These analytical equations are complex so the output voltages will only be reported assuming a critically-damped response and neglecting the effect of the finite DC gain Table 4.4 System evolutions according to the damping ratio

Damping ratio

Poles

Evolution

ξj = 0 0 < ξj < 1 ξj = 1 ξj > 1

Pure imaginary Complex conjugate Repeated real poles Two distinct real poles

Undamped Underdamped Critically damped Overdamped

4.1 Non-Idealities in SH and MDACS

75

of the amplifiers. Thus, assuming that the amplification phase starts at t = 0:    + + v g v /β + g g m2j aj, n−1/2 m2j j m1j o1j , n−1/2 ldeal 1+ − t− t e−αj t voj (t) = voj βj βcj Ceqaj βj 2Ceqaj     + gm2j vo1j gm2j /βj + gm1j , n−1/2 + −αj t vaj (t) = − t − 1+ t vaj , n−1/2 e βcj Ceqaj 2Ceqaj      βj Ceqaj + gm1j βcj gm2j /βj + gm1j 1+ vaj, n−1/2 t + 1 − vo1j (t) = t βj Ceqaj Ccj 2Ceqaj  + −αj t × vo1j (4.16) , n−1/2 e From Eq. (4.16) it can be inferred that the time constant of the evolution in a critically damped situation is given by τaj = 1/αj , defined in Table 4.3.

4.1.4

Dynamic Limitations: Large-Signal Effects

So far it has been assumed that the amplifiers operate linearly according to the smallsignal models proposed. However, this is not representative of the actual situation since, in practice, there are several large-signal effects which modify this linear operation. In fact, these small-signal models are obtained by linearizing the operation of the OTA around a bias point. Problems arise when this bias point is modified as a result of several effects, such as the signal level. The most critical effects are analyzed below. They can be summarized as: (a) Slew-rate effect. (b) Non-linear DC gain. We will now go on to analyze the impact of these effects on the performance of the MDAC.

4.1.4.1

Slew-Rate Effect

A pair differential exhibits a non-linear relationship between its differential drain current and the input voltage as shown in Fig. 4.7b [1, 2]. In fact, the current provided saturates in the case of the input voltage exceed a certain limit. This effect can be modelled as a transconductance with a limited current as illustrated in Fig. 4.7c. The circuits in Fig. 4.8 are obtained by incorporating this effect into the macromodels for the OTA. These new macromodels make it possible to analyze the transient evolution once again taking the current saturation possibility into account. Tables 4.5 and 4.6 list all the possible evolutions for the one-stage and two-stage MC macromodels respectively.

76

4 Behavioural Modelling of Pipeline ADCs io ib ib gm –vsat

–ib vsat

io2

io1

vi

gmvi ib

+

–ib

–

io = io1 – io2 vi

a

b

c

Fig. 4.7 Differential pair: a schematics, b drain current versus the input voltage and c small-signal model with saturation current voj

+ ioj OTA Cpj

vij + vij

a

voj

Ccj

io1j OTA

Cpj

–io1j

b

Coj

–ioj

voj

+ vij

OTA

goj

– vo1j

–

gmj (vij –vofj )

gm1j (vij –vofj )

io2j go1j

OTA

Co1j

gm2jvo1j

go2j

OTA

Co2j

–io2j

–

Fig. 4.8 New macromodels with slew-rate effect for a one-stage and b two-stage MC OTAs

4.1.4.2

Non-Linear DC Gain

Until now, the DC gain of the OTAs has been assumed to be constant. However, it maintains a non-linear dependence on the signal level. Figure 4.9a, b illustrate the variation of the DC gain for one- and two-stage MC amplifiers respectively. In both cases, the changes are greatly significant except in the first stage of a two-stage topology, given that the output voltage of the first stage is attenuated by the DC gain of the second one. For this reason, only the non-linear behaviour of the second stage is considered in the proposed behavioural model. This DC-gain non-linearity not only degrades the static resolution of the SC block but also modifies the locations of the system poles as they depend on the error factors εgaj , εgj , εg1j and εg2j , which in turn vary with Aoj , Ao1j and Ao2j . This is shown in Fig. 4.10 where it is possible to observe the dependence of the poles on the output voltage. In the one-stage topology, the system becomes faster since the system pole

Slew-rate

Linear

Evolution

Slew-rate

Linear

Evolution

gmj εgaj

+ ioj sgn(vaj , n−1/2 )

+ vaj, n−1/2 −

Expression for voj (t) 1 ldeal [vaj (t) − vaj , n−1/2 ] + voj βj

−



+ −t/τaj vaj , n−1/2 e



ldeal βj voj

vofj βj ε ga,j + + ⎣ 1 + εgaj 1 + εga,j

Expression for vaj ⎡ (t)

 1−e

ε mj gaj Ceqaj t

g

 + + vaj, n−1/2e −

⎤ vaj, n−1/2 ldeal − voj ⎦ (1 − e−t/τaj ) βj

Table 4.5 Transient evolution in amplification phase assuming a one-stage OTA macromodel

Ceqaj

gmj εgaj

t

   +  vaj ,n−1/2  > ioj /ggmj

Condition    +  vaj ,n−1/2  ≤ ioj /gmj

   +  vaj , n−1/2  > ioj /gmj

Condition     + vaj ,n−1/2  ≤ ioj /gmj

4.1 Non-Idealities in SH and MDACS 77

2nd-stage Slew-rate

1st-stage Slew-rate

Linear

m2j

t−

m2j

βcj βeqaj

+ io2j sgn(vo1j , n−1/2 )

t

⎛

⎡ gm1j t ⎞ ⎜ ⎢ + Ceqaj ⎟ v+ vo1j ⎠ aj , n−1/2 + ⎣ , n−1/2 − H ⎝1 − e

H βj gm1j

⎤ gm1j t ⎞ t ⎥ ⎜ ⎟ + C ⎝1 − e eqaj ⎠ + ⎦ io2j sgn(vo1j , n−1/2 ) Ccj

⎛

βcj H ⎜ + β C ⎟ − ⎝1 − e j eqaj ⎠ io1j sgn(vaj , n−1/2 ) gm2j

   gm1j βcj gm2j /βj + gm1j + + −αj t H vaj t vo1j , n−1/2 t + 1 − , n−1/2 e βj Ceqaj 2Ceqaj ⎛ −g t ⎞ −g t

+ βj Ceqaj vo1j , n−1/2 e



Expression for vo1j (t)

Evolution

Ceqaj

+ vaj , n−1/2 +

+ io1j sgn(vaj , n−1/2 )

⎛ gm1j t ⎞ gm1j t + sgn(v ) i o1j , n−1/2 ⎜ ⎟ + Ceqaj + o2j C vaj ⎝1 − e eqaj ⎠ , n−1/2 e βcj gm1j

Expression for vaj (t)     + gm2j vo1j gm2j /βj + gm1j , n−1/2 + − t − 1+ t vaj , n−1/2 e−αj t βcj Ceqaj 2Ceqaj ⎛ ⎛ ⎤ ⎡ −gm2j t ⎞ −gm2j t ⎞ H β β t j ⎜ ⎥ ⎢ j ⎜ + + β C ⎟ + β C ⎟ vaj ⎝1 − e j eqaj ⎠ vo1j , n−1/2 + ⎣ ⎝1 − e j eqaj ⎠ − ⎦ io1j sgn(vaj , n−1/2 ) , n−1/2 − βcj gm2j Ccj

Both stages Slew-rate

2nd-stage Slew-rate

1st-stage Slew-rate

Linear

Evolution

Table 4.6 Transient evolution in amplification phase assuming a two-stage MC OTA macromodel and a critically-damped response

    + vaj , n−1/2  > io1j /gm1j    +  vo1j , n−1/2  ≤ io2j /gm2j     + vaj , n−1/2  ≤ io1j /gm1j    +  vo1j , n−1/2  > io2j /gm2j

Condition     + vaj , n−1/2  ≤ io1j /gm1j     + vo1j , n−1/2  ≤ io2j /gm2j

Condition  +  vaj , n−1/2  ≤ io1j /gm1j    +  vo1j , n−1/2  ≤ io2j /gm2j     + vaj , n−1/2  > io1j /gm1j    +  vo1j , n−1/2  ≤ io2j /gm2j     + vaj , n−1/2  ≤ io1j /gm1j    +  vo1j , n−1/2  > io2j /gm2j     + vaj , n−1/2  > io1j /gm1j    +  vo1j , n−1/2  > io2j /gm2j

78 4 Behavioural Modelling of Pipeline ADCs

Ceqaj

t− βj Ceqaj

+ io2j sgn(vo1j , n−1/2 )

t

+ voj , n−1/2 +

βj Ceqaj

+ io2j sgn(vaj , n−1/2 )

t− βj βcj Ceqaj

+ io2j sgn(vo1j , n−1/2 )

t

gm1j t ⎞   + ) io2j sgn(vo1j 1 ⎜ ,n−1/2 ⎟ + + C voj , n−1/2 − − vaj , n−1/2 ⎝1 − e eqaj ⎠ βj βcj gm1j

⎛

⎛ ⎛ ⎤ ⎡ −gm2j t ⎞ −gm2j t ⎞ t 1 H ⎜ ⎜ ⎥ ⎢ + + β C ⎟ + β C ⎟ v0j ⎝1 − e j eqaj ⎠ vo1j , n−1/2 + ⎣ ⎝1 − e j eqaj ⎠ − ⎦ io1j sgn(vaj , n−1/2 ) , n−1/2 − βcj gm2j Ccj

Expression for Voj (t)    + + gm2j vo1j vaj gm2j /βj + gm1j , n−1/2 , n−1/2 ldeal voj − 1+ t− t e−αj t βj βcj Ceqaj βj 2Ceqaj

+ vo1j , n−1/2 +

+ βcj H io1j sgn(vaj , n−1/2 )

where H = 1 + (βj C eqaj )/C cj and sgn() is the sign function.

Both stages Slew-rate

2nd-stage Slew-rate

1st-stage Slew-rate

Linear

Evolution

Both stages Slew-rate

Table 4.6 (continued)

Condition    +  vaj , n−1/2  ≤ io1j /gm1j     + vo1j , n−1/2  ≤ io2j /gm2j     + vaj , n−1/2  > io1j /gm1j    +  vo1j , n−1/2  ≤ io2j /gm2j     + vaj ,;n−1/2  ≤ io1j /gm1j    +  vo1j , n−1/2  > io2j /gm2j     + vaj , n−1/2  > io1j /gm1j    +  vo1j , n−1/2  > io2j /gm2j

    + vaj , n−1/2  > io1j /gm1j    +  vo1j , n−1/2  > io2j /gm2j

4.1 Non-Idealities in SH and MDACS 79

4 Behavioural Modelling of Pipeline ADCs 700

500

DC-gain

40

95

35

90

30

85

25

80

20

75

15

70

10

65

5

First stage DC-gain

600

100

400 300 200 100 –0.5

a

0 Output voltage (V)

60 –0.5

0.5

0 0.5

0 Output voltage (V)

b

Second stage DC-gain

80

Fig. 4.9 DC-gain dependence on the output voltage in a: a one-stage and b two-stage amplifiers 1.01

1.8 First pole Second pole

1.4 1.005 Real(p)

Normalized pole

1.6

1

1.2 1 0.8 0.6 0.4

0.995

a

–0.5

0 Output voltage (V)

0.2

0.5

b

–0.5

0

0.5

Output voltage (V)

Fig. 4.10 Pole dependence on the output voltage in a: a one- and b two-stage amplifiers

is directly proportional to εgaj . Therefore, the DC-gain error improves the dynamics of the system. In contrast, the effect in a two-stage topology is significantly more harmful to the performance of the MDAC. As inferred in Fig. 4.10b the system is critically-damped at the nominal operating point and the poles coincide. However, as the output voltage moves from this point, the DC gain of the amplifier decreases, poles split along the real axis and the system becomes overdamped and hence slower. This effect translates into a notable increment of harmonic distortion. Therefore, it is quite obvious that this effect must be considered for accuracy of the transient response. Note that the system can evolve from a critically-damped to an overdamped situation due to the non-linearity of the DC gain. Furthermore, the transient response can be determined by an underdamped response if parameters are not exactly computed. Hence, the behavioural models proposed in this monograph include all possible situations in Table 4.4. Nevertheless, for reasons of simplicity, these have not all been reported. In order to model the non-linear behaviour of the DC gains, the following polynomial form will be used. A = Ao (1 + a1 vo + a2 vo 2 + a3 vo3 + a4 vo4 )

(4.17)

4.1 Non-Idealities in SH and MDACS

81

where Ao is the DC gain of the stage at the quiescent point, and a1 , a2 , . . . are adjustment coefficients, usually given in %/V, %/V2 , . . . .

4.1.4.3

Electrical-Level Verification

Previous sections have been devoted to the analysis of the non-idealities of the OTAs in the SC circuits of a pipeline converter. The impact on the ideal performance of the SC circuits has been characterized and analytical equations obtained. The aim of this section is to illustrate the reliability of these models. For this purpose, the following procedure will be carried out: 1. As starting points we will use some SC circuits which have previously been designed and characterized at electrical level. We therefore know the performance or resolution of these circuits a priori. These designs will be identified as scenarios. 2. The small-signal parameters will be extracted from these electrical designs and introduced into our behavioural models. A behavioural simulation will then be carried out and the results compared with the electrical-level simulations. 3. We will focus on the two-stage MC model since it is the main contribution of this monograph. This procedure has been applied in the design scenarios in Table 4.7, implemented both in a 130 nm technology and a 90 nm technology. The OTA topology, the SC architecture, and the design objectives of such scenarios differ. The SC circuit in scenarios A and B is the flip-around SH circuit of Fig. 4.1a, whereas in scenario C it is a 3-bit MDAC circuit as shown in Fig. 4.1b. Regarding the OTA topologies, we have considered a fully differential two-stage structure composed of a p-input folded-cascode first stage and a differential n-type class-A amplifier second stage. The schematic is shown in Fig. 4.11. The only difference between the OTA considered in scenario A, on the one hand, and those used in scenarios B and C, on the other, is that the former uses p-type cascode current sources in the second stage, whereas simple current sources are used in the latter, that is to say, cascode transistors M 16 and M 17 in Fig. 4.11 are simply replaced by short circuits. The electrical level parameters extracted from the MOS implementation of such scenarios are summarized in Tables 4.8 and 4.9 for the 130 nm and 90 nm technologies respectively. The corresponding behavioural simulations were carried out taking Table 4.7 Design scenarios for the verification procedure Specification

Scenario A

Scenario B

Scenario C

SC configuration OTA topology Number of bits ENOB(bits) Sampling frequency (MHz)

S/H Cascode – ∼8 100

S/H Simple – ∼12 100

MDAC Simple 3 ∼10 100

82

io2

4 Behavioural Modelling of Pipeline ADCs

io1

M12

M6

M16

M8

ib

io1

M5

M1

io2

M7

M13

M9

M17

M2

M10

M11

M14

M18

M15

M3

M4

Fig. 4.11 OTA topology used in the design scenarios; cascoded version

those values as input parameters in our behavioural models. The results are also summarized in these tables. As can be inferred, there is excellent agreement between the behavioural and electrical simulations. To conclude this section and illustrate the relevance of the large-signal effects, a transient analysis of the S/H in scenario A in the 90 nm technology is shown in Fig. 4.12. Five waveforms have been included in the plot: the ideal response, the transistor-level simulation and three behavioural simulations taking into account different effects. As shown in the figure, only the full-blown behavioural model including the DC-gain variation effect is closed to the transistor level simulation.

Table 4.8 Electrical-level parameters and simulation results in 130 nm technology Parameters

Scenario A

Scenario B

Scenario C

Unitary capacitor (Cuj ) (pF) Parasitic cap. (Cpj |Co1j |Clj )(pF) DC gains (Aoj |Ao1j |Ao2j ) Transconductances (gm1j |gm2j ) (mA/V) Currents (ib |io1 |io2 ) (mA) Non-Iinearity of the DC gain (a1 |a2 |a3 |a4 )(V −1 , V −2 , V −3 , V −4 ) j + 1 -sub-ADC load cap. (Cq,j +1 ) (pF) j + 1 -MDAC load cap. (Cs,j +1 ) (pF) Comp. capacitor (C c )(pF) ENOB(bits) (Transistor sim.) ENOB(bits) (Behavioural sim.)

3 0.06 | 0.54 | 0.47 2711 | 92.6 | 29.3 1.29 | 14.71 0.22 | 0.24 | 1.53 4.8 m | −4.18 | −16.9 m | 4.26 0.3 0.8 1.05 7.86 8.1

3 0.13 | 0.97 | 0.78 2750 | 130 | 21.2 2.31 | 26.91 0.33 | 0.42 | 2.48 1.5 m | −0.84 | 0.8 m | −1.94 0.3 0.8 1.45 11.97 12.1

0.15 0.06 | 0.37 | 0.30 2918 | 137.1 | 21.3 0.99 | 6.60 0.14 | 0.18 | 0.54 1.5 m | −0.84 | 0.8 m | −1.94 0.1 0.2 0.25 9.78 10.1

4.1 Non-Idealities in SH and MDACS

83

Table 4.9 Electrical-level parameters and simulation results in 90 nm technology Parameters

Scenario A

Scenario B

Scenario C

Unitary capacitor (Cuj ) (pF) Parasitic cap. (Cpj |Co1j |Clj )(pF) DC gains (Aoj |Ao1j |Ao2j ) Transconductances (gm1j |gm2j ) (mA/V) Currents (ib |io1 |io2 ) (mA) Non-Iinearity of the DC gain (a1 |a2 |a3 |a4 )(V −1 , V −2 , V −3 , V −4 ) j+1 -sub-ADC load cap. (Cq,j +1 ) (pF) j+1 -MDAC load cap. (Cs,j +1 ) (pF) Comp. capacitor (C c ) (pF) ENOB(bits)(Transistor sim.) ENOB(bits) (Behavioural sim.)

3 0.04 | 0.39 | 0.30 3652 | 125.8 | 29 0.94 | 11.42 0.17 | 0.19 | 1.36 3.6 m | −3.4 | −13.3 m | 1.67 0.3 0.8 1.05 7.72 8.05

3 0.10 | 0.64 | 0.42 2788 | 134.5 | 20.7 1.92 | 19.43 0.30 | 0.39 | 2.05 2.5 m | −0.53 | 5.8 m | −1.54 0.3 0.8 1.45 12.28 12.18

0.15 0.05 | 0.30 | 0.22 3200 | 151 | 21.2 0.988 | 5.293 0.16 | 0.18 | 0.54 2.5 m | −0.53 | 5.8 m | −1.54 0.1 0.2 0.25 10.20 10.11

0.4 Ideal Small–signal model Small-large sig. model Linear DC gain Small-large sig. model Non-linear DC gain Transistor–level

0.3

Output voltage (V)

0.2

0.401

0.1

0.4 0

0.399

–0.1

0.398 0.397

–0.2

0.396 –0.3

0.395

–0.4 134

136

138

140

142 144 t(ns)

146

148 148

148.5 150

149

149.5

150

Fig. 4.12 Transient evolution

4.1.5

Switch-on Resistance

In practice, a switch is usually implemented by means of MOS transistors. A simple implementation is illustrated in Fig. 4.13, where the gate of the MOS transistor is controlled by a clock signal. When the clock signal is low, the MOS transistor is off and no current is carried. In contrast, when the clock signal is high the MOS transistor usually carries current by operating in triode region. In this situation, it presents a finite resistance which can be determined by [1, 4]: Ron =

1 μCox WL (VDD − Vth − Vin )2

(4.18)

where μ and C ox are technological parameters, W and L are the MOS dimensions, and V th is the threshold voltage. This non-ideality must also be considered for accuracy in

84

4 Behavioural Modelling of Pipeline ADCs

Fig. 4.13 MOS implementation of a switch

VDD clk

Vin

VSS

Vo

Ron

the models proposed. However, the problem raised becomes extremely complex since the RC constants introduce new poles into the system. Nevertheless, it is possible to obtain some design criteria or simplified expressions. Again, the effect on the performance of the MDAC will be studied by considering both one- and two-stage MC OTAs.

4.1.5.1

One-Stage OTA Macromodel

We will now consider the one-stage macromodel for the OTA in Fig. 3.5. By replacing this macromodel in the MDAC circuit of Fig. 4.1a and considering the switch-on resistance values for the sampling r usj , amplification r uaj , and input r isj and output r osj reset switches, the equivalent circuits in Fig. 4.14a, b are obtained for the sampling and amplification clock phases respectively. The impact of these switch-on resistances on the dynamics during both clock phases is described below. Sampling Phase By assuming the switch-on resistances are null and applying the charge conservation principle, the initial voltages at input and output OTA nodes at the start of the sampling phase are: + vaj, n−1

⎡⎛ ⎞ ⎤ Mj Mj   1 ⎣⎝ Cfj + b¯ij , n−1 Cij Vref ⎦ = vaj, n−1 + Cij ⎠ vij, n−1 − Cfj voj, n−1 − Ceqsj i=1 i=1

+ voj , n−1 = voj , n−1

(4.19)

where C eqsj is the equivalent closed-loop capacitance during the sampling phase, defined in Table 4.10, and voltages vaj, n−1 , vij, n−1 and voj, n−1 are measured at the end of the previous amplification phase. As switch-on resistances are finite in practice, charge is not instantaneously distributed and the magnitude of the initial states is lower than that predicted in Eq. (4.19). However, in the proposed behavioural model, the (worst-case) values in

4.1 Non-Idealities in SH and MDACS

vij

rusj

Cfj

rusj

C1j

85

vij ...

rusj

CMj

voj

vaj

vij Cpj

risj

rosj

gmj (vaj – vofj)

goj

Clj

C1j = … = C Mj = Cfj = Cuj

a ruaj

C1j

rus, j + 1

Cq, j + 1

rus, j + 1

CS, j + 1

b1jVref ...

ruaj

CMj

bMjVref

vaj Cfj

ruaj

voj

gmj (vaj – vofj)

Cpj

goj

Clj

b Fig. 4.14 Equivalent circuits for the MDAC in: a sampling and b amplification phases using a one-pole OTA macromodel and considering non-zero switch-on resistances Table 4.10 Relevant parameters in the sampling phase for the j-th MDAC using a one-stage OTA model

Parameter

Definition

Open-loop gain of the amplifier

Aol = gmj rosj

Equivalent closed-loop capacitance Constant time of the sampling switches Constant time of the output amplifier node Constant time of the input amplifier node

Ceqsj = Cpj +

Mj 

Cij + Cfj

i=1

RCsj = rusj Cuj τosj = Clj rosj τsj = RCsj + risj Ceqsj

Eq. (4.19) have been assumed for the sake of simplicity. From these initial voltages, the system evolves as follows:   M   Cij risj RCsj Cfj + 2 risj Ceqsj −t/τsj + i=1 −t/τs j vaj (t) ≈ e v − e vaj , n−1 (4.20) ij , n−1 τ 2 sj τ 2 sj + −t/τosj voj (t) ≈ Aol (1 − e−t/τosj )vofj + voj , n−1 e

86

4 Behavioural Modelling of Pipeline ADCs

where parameters are defined in Table 4.10 and it has been assumed that a single pole dominates the dynamics of both voltages.

Amplification Phase Following a reasoning similar to the one expressed above, the initial voltages in Eqs. (4.7) and (4.8) will be assumed at the start of the amplification phase. System dynamics are determined by the amplifier pole and the different RC time constants from these values. To simplify the analysis, a common situation is assumed in which the poles introduced by the switch-on resistances are at a much higher frequency than the amplifier pole. In this case, the effect of such resistances can be accounted for by modifying the system time constant as follows: τaj ≈

Ceqaj + RCaj + RCsj +1 gmj (1 + βj εgaj )

(4.21)

where RC aj = r uaj C uj is the time constant introduced by the amplification switches and RC sj + 1 = r us, j +1 C uj+1 is the time constant introduced by the sampling switches in the following stage. Note that the time constant of the system increases due to these RC constants. Accordingly, the transient evolution of the system can be computed by simply replacing equations in Table 4.5 with Eq. (4.21).

4.1.5.2 Two-Stage MC OTA macromodel Let us now consider the two-stage MC macromodel for the OTA in Fig. 3.9. By replacing this macromodel in the MDAC circuit of Fig 4.1b and considering the switch-on resistance values for the sampling r usj , amplification r uaj , and input r isj and output r os1j , r os2j reset switches, the equivalent circuits in Fig. 4.15 are obtained. We can now analyze both clock phases separately.

Sampling Phase Analogously, the initial voltages at the start of the sampling phase can be computed applying the charge conservation principle and assuming that switch-on resistances are zero, as: ⎡⎛ ⎞ ⎤ Mj Mj   1 ⎣⎝ + Cfj + Cij⎠ vij, n−1 − Cfj voj , n−1 − b¯ij, n−1 Cij Vref ⎦ vaj , n−1 = vaj , n−1 + Ceqsj i=1 i=1 (4.22) + vo1j , n−1 = vo1j , n−1 + voj , n−1 = voj , n−1

4.1 Non-Idealities in SH and MDACS rusj

Cfj

rusj

C1j

vij

87

C1j = … = CMj = Cfj = Cuj

vij ...

CMj

rusj

risj

Cpj

Ccj

vo1j

vaj

vij

ros1j

gm1j (vaj – vofj)

go1j

Co1j

voj ros2j

gm2j vo1j g C o2j lj

a rus, j + 1 Cq,j + 1 b1jVref

ruaj

C1j ...

bMjVref

ruaj

CMj vaj Cfj Cpj

rus, j + 1 CS,j + 1 ruaj

Ccj

voj

gm2j vo1j

go2j

Co2j

vo1j

gm1j (vaj – vofj)

go1j

Clj

b Fig. 4.15 Equivalent circuits for the MDAC in: a sampling and b amplification phases using a two-stage MC OTA macromodel and considering non-zero switch-on resistances Table 4.11 Relevant parameters in the sampling phase for the j-th MDAC using a two-stage MC OTA model

Parameter

Definition

Equivalent capacitance

Ceqsj = Cpj +

mj 

Cij + Cfj

i=1

Constant time of the sampling switches Constant time of the output amplifier node Constant time of the input amplifier node

RCsj = rusj Cuj C r

τosj = cjβcjos1j + (Ccj + Clj )ros2j + gm2j ros1j ros2j Ccj τsj = RCsj + risj Ceqsj

where C eqsj is the equivalent closed-loop capacitance during the sampling phase and is defined in Table 4.11. From these initial voltages, the system evolves as follows:   Mj  risj RCsj Cfj + Cij  2 i=1 risj Ceqsj + −t/τsj vaj (t) ≈ e v − e−t/τsj vaj ij , n−1 , n−1 (4.23) τsj2 τsj2  + −t/τosj vo1j (t) ≈ gm1j ros1j 1 − e−t/τosj vofj + vo1j , n−1 e  + −t/τosj voj (t) ≈ Aolj 1 − e−t/τosj vofj + vo, n−1 e where parameters are defined in Table 4.11 and it has been assumed that a single pole dominates the dynamics of all the circuit nodes.

88

4 Behavioural Modelling of Pipeline ADCs

Amplification Phase The procedure is similar to the single-stage case. Assuming that the time constants introduced by the switch-on resistances are at high frequencies, their combined effect can be modelled by replacing the time constant of the system in Table 4.6 (τaj = 1/αj ) with the expression: τaj = αj −1 + RCaj + RCsj +1

(4.24)

where RC aj = r uaj C uj is the time constant introduced by the amplification switches and RC sj + 1 = r us,j + 1 C uj + 1 is the time constant introduced by the sampling switches in the following stage. The initial voltages at the start of the amplification phase in Eqs. (4.10)–(4.12) are assumed in the proposed behavioural model.

4.1.5.3

Electrical-Level Verification

From the above analysis it can be inferred that the system dynamic is affected by the RC time constants introduced by the switches and capacitors of the SC network. Special attention must therefore be paid to the sizing of the switches. In order to avoid deteriorating the system dynamic, we should keep the switch-on resistances as low as possible since the RC time constants increase the system’s constant time. However, large W/L MOS ratios would be necessary to reduce the switch-on resistance as shown in Eq. (4.18) and, as a result of this, significant parasitic capacitances would be added to the SC network. In practice, it is usual to size the switches so that the RC time constants of the SC branches are 5–10 times lower than the time constant of the amplifier [3, 4, 128]. According to Eqs. (4.21) and (4.24), the time constant of the amplifier considering one- and two-stage MC macromodels is: τuj =

Two-stage MC OTA macromodel

τuj = αj −1

gmj

Ceqaj 1 + βj εgaj



One-stage OTA macromodel

(4.25)

This design criterion is translated onto the following requirements in accordance with the expressions in Sects. 4.1.5.1 and 4.1.5.2: ⎧ ⎨ RCsj + risj Ceqsj < τuj /n One -stage OTA Clj rosj < τuj /n macromodel ⎩ RCaj + RCsj +1 < τuj /n ⎧ ⎪ ⎪ ⎨

RCsj + risj Ceqsj < αj −1 /n

Ccj ros1j Two -stage MC + (Ccj + Clj )ros2j + gm2j ros2j Ccj < αj −1 /n OTA macromodel ⎪ βcj ⎪ ⎩ RCaj + RCsj +1 < αj −1 /n (4.26)

4.1 Non-Idealities in SH and MDACS

89

where n is the number of times that the RC time constants must be lower than the amplifier time constant. The following requirements are obtained for the switch-on resistances from Eq. (4.26): ⎧ ( ) risj = τuj /n − rusj Cuj /Ceqsj ⎪ ⎪  ⎨ One-stage OTA rosj = τuj / nClj macromodel ⎪ r = τ / 2Cuj n ⎪ ⎩ uaj uj rusj = rua,j −1 Cua,j −1 /Cuj ( ) ⎧ risj = τuj /n − rusj Cuj /Ceqsj ⎪ ⎪ ⎪ ⎤ ⎪  ⎡ ⎪ ⎪ C ⎪ lj * ⎪ ⎪ ⎥ ⎢+ 1 + βcj 1 + ⎪ ⎪ ⎥ 4βcj2 gm2j τuj + Ccj ⎢ ⎪ ⎨ rosj = ⎢+1 +   2 − 1⎥ Two-stage MC ⎥ ⎢+ 2βcj gm2j Clj ⎦ ⎣, OTA macromodel ⎪ nCcj 1 + βcj 1 + ⎪ ⎪ C cj ⎪ ⎪  ⎪ ⎪ ⎪ rusj = rua,j −1 Cu,j −1 /Cuj ⎪ ⎪ ⎪ ⎪ ⎩ruaj = τuj /(2Cuj n) (4.27) rosj = ros1j = ros2j

Therefore, given a specific value for n, the sizes for the switches can be obtained from Eq. (4.27). For illustration purposes, the above design criterion has been applied to size the switches in the scenarios in Table 4.8†3 . The sizing and simulation results are summarized in Table 4.12. As can be inferred, n values higher than 5 guarantee good performance whereas n values lower than 5 can deteriorate the dynamic performance of the SC circuits.

4.1.6

Thermal Noise in the MDAC

Thermal noise in SC circuits becomes a limiting factor since the noise generated by the devices is undersampled by the SC network. As a result, the noise is folded Table 4.12 Transistor-level simulation results for the scenarios in Table 4.8 considering non-zero switch-on resistances Parameters Scenario A Scenario B Scenario C Factor n risj () rusj () ruaj () ros1j () ros2j () rus,j +1 () ENOB(bits)

3

∼1 115 140 140 100 100 2000 7.13

5–10 25 15 15 30 30 200 7.87

∼1 60 115 115 55 55 2000 10.55

5–10 15 15 15 20 20 175 11.99

∼1 60 4250 4250 350 350 6300 10.68

Switch-on resistances on results in Tables 4.8 and 4.9 were assumed to be zero.

5–10 15 400 400 115 115 600 10.03

90

4 Behavioural Modelling of Pipeline ADCs

back several times in the base band (aliasing), increasing the total noise contribution. Appendix B provides an overview of thermal noise in SC circuits which will be used here as an introduction to tackling the noise in MDAC circuits. In Appendix B the output PSD for a track and hold circuit was obtained by assuming a continuous time noise signal at the output. Nevertheless, this is not actually the case in a pipeline converter, where the noise signal at the output of each SC circuit (SH and MDACs) is sampled in the following stage, and the decomposition into track and sampled and hold components is therefore not necessary. Let us consider the waveforms for a track and hold circuit in Fig. 4.16. There, the track and the sampled and hold components are depicted, together with a sampled version of the noise signal. As can be inferred, this sampled noise signal can also be obtained by simply sampling the tracking signal, so: ∞ 

vCS (t) =

vCT (t)δ(t − nTs )

(4.28)

n=−∞

As a result, the noise PSD of the sampled signal can be computed as follows: SCS (f ) =

∞ 

Scn (f − nfs )

(4.29)

n=−∞

clk mTs

(m – 1)Ts

a vC (t)

Ts

t

b vTC (t)

t

c vSH C (t)

t

d t S vC (t)

e t

Fig. 4.16 Waveforms in a track and hold circuit: a clock signal, b noise signal, c track component, d sampled and hold component and e sampled noise

4.1 Non-Idealities in SH and MDACS

91

Applying the concept of equivalent noise bandwidth and assuming BW n  f s the next expression can be obtained: SCS (f ) =

2BWn Sn fs

− fs /2 < f < fs /2

(4.30)

By substituting Eqs. (B.7) and (B.13) into Eq. (4.30): Scs (f ) =

KT C s fs

− fs /2 < f < fs /2

(4.31)

Taking this result into account, the noise PSD for the SC circuits in a pipeline converter can be analyzed. Again, we will consider the noise contributions in each clock phase separately.

Sampling Phase As illustrated in Fig. 4.17a, the main noise sources in this phase are the switch resistances, given that the OTA is reset. Therefore, the equivalent circuit basically consists of a set of SC branches sampling the input. Assuming that all noise sources are uncorrelated†4 and considering the result in Eq. (4.31), the noise PSD during the sampling phase can be approximated as follows: Ssji (f ) =

KT Ceqsj fs

− fs /2 < f < fs /2

(4.32)

where C eqsj is the total equivalent capacitance of the RC network, defined in Table 4.10. Assuming a complete charge transfer and neglecting all non-idealities, the stored noise in the sampling phase is amplified by the gain factor of the MDAC (Gj ) during the amplification phase. Therefore, the noise PSD at the output of the MDAC will be given by: Ssjo (f ) = G2j

KT Ceqsj fs

− fs /2 < f < fs /2

(4.33)

Amplification Phase In the case of the equivalent circuit in Fig. 4.17b, three different noise sources must be computed: switches, OTA and noise from the reference voltage. In actual fact, 4 Actually, the noise voltages stored by the capacitors are correlated to each other since they depend on the noise voltage of amplifier input node, which in turn depends on all noise source voltages. However, this correlation can be neglected in most practical cases. In fact, Eq. (4.31) has proved to be a good approximation as reported in [102, 114, 129].

92

4 Behavioural Modelling of Pipeline ADCs

–

risj ...

CMj

C1j

voj

Cfj risj

rusj

rusj

rusj

rusj

...

vnM

vn

rusj

rosj vno

OTAj

rusj

vn1

rosj

+

vn

vnf

a

ruaj

r vnfuaj

–

ruaj

ruaj vn1

Cfj

C1j

voj

...

...

+ ruaj

ruaj vnM

OTAj vn

CMj

b Fig. 4.17 Equivalent noise schematics for a MDAC in: a sampling phase and b amplification phase

the reference voltage noise can be interpreted as a noise additional to the sampling switches, that is: r

r

vniuaj = vniuaj |o + vnref

i = 1, . . . , M

r

where vniuaj |o is the nominal noise from the sampling switches. Assuming that all noise sources are uncorrelated, the total noise at the output of the MDAC can be computed by simply adding all individual output-referred noise power. Herein, only the noise contribution generated by the OTA is derived. A similar procedure can be applied to estimate remaining contributions. From Fig. 4.17b and assuming a single-stage amplifier topology, it can be shown OTA that the transfer function from the OTA noise source, Vn j , to the output is given by: OT Aj

H vn where a = Cpj Ctj RCaj

(S) =

ps 2 + qs + r + bs 2 + cs + d

 2

(4.34)

as 3

b = Cpj Ctj + Cfj



Ctj Cpj + βj

 RCaj

(4.35)

4.1 Non-Idealities in SH and MDACS

c = Cfj (Ceqaj + gmj RCaj )

93

d = gmj Cfj

  Cfj q = gmj RCaj Cpj + βj

p = gmj Cpj RCaj 2

r=

gmj Cfj βj

Using Graeffe’s numerical method [130] the poles (p1 , p2 , p3 ) and zeros (z1 , z2 ) of the transfer function in Eq. (4.34) can be computed and the equivalent noise bandwidth of the OTA subsequently evaluated as: ∞  2  r 2 p p p (p p p (p p + · · · )) OT Aj 1 2 3 1 2 3 2 3   = H vn (f ) df = d 4(p1 + p2 )(p1 + p3 )(p2 + p3 )z12 z22

vOTA BWn nj

0

(4.36) from which the output-referred noise PSD of the OTA is given by: vn OT A j (f ) Sno

2BWnvn = fs

OT Aj

Snvn

OT Aj

− fs /2 < f < fs /2

(4.37)

OTAj

where Snvn is the OTA noise PSD. Using a similar procedure for all the noise contributions, the output-referred PSD during the amplification phase can be obtained as: o (f ) Saj

2BWnvn = fs

ruaj

OT Aj

Snvn

OT Aj

+

v M  2BWn ni

fs

i=1 v

v

ruaj

Snni

ruaj

ruaj 2BWn ni vnf + Sn − fs /2 < f < fs /2 fs

v

ruaj

v

(4.38)

ruaj

where BWn ni and BWn nf are the equivalent noise bandwidths of the switch-on resistances at the input and feedback branches of the MDAC respectively and similarly, v

ruaj

v

ruaj

Snni and Snnf represent their noise PSDs. Total Noise In order to compute the total output noise in an MDAC circuit, the noise PSD obtained in the sampling and amplification phases can be added since these are uncorrelated. Therefore, the total noise PSD is computed by adding Eqs. (4.33) and (4.38): OTAj

Sj (f ) = o

G2j

KT 2BWnvn + Ceqsj fs fs v

ruaj

OTAj

Snvn

+

v M  2BWn ni i=1

fs

v

ruaj

Snni

ruaj

2BWn nf vnfruaj + Sn − fs /2 < f < fs /2 fs

(4.39)

94

4 Behavioural Modelling of Pipeline ADCs

Thus, the total power noise will be determined by: fs /2 j Pno

 Pno = ξ

G2j

=ξ

Sjo (f )df −fs /2

ruaj ruaj ruaj ruaj  OTAj OTAj v v KT v v + 2BWnvn Snvn + 2BWn ni Snni + 2BWn nf Snnf Ceqsj i=1

M



(4.40) where ξ is a factor dependent on the topology (ξ = 2 if fully differential topologies are used).

4.1.6.1

MDAC Noise Electrical-Level Verification

The previous section has been devoted to showing the procedure for computing the total noise generated in the MDAC circuit. Here, in order to assess the accuracy and reliability of the proposed noise behavioural models, these have been compared in many different scenarios using transistor-level simulations. Two design examples, summarized in Table 4.13, are presented for illustration purposes. These design examples differ in the OTA topology used, SC circuit implemented and target specifications. Both design examples are studied below. In design example A, the SH circuit in Fig. 4.1a is considered using the onestage folded-cascode OTA topology in Fig. 4.18a. Parameters in Table 4.13 have been extracted from transistor-level simulations. These parameters were loaded into Table 4.13 Design examples for verification of the noise models Parameters

Scenario A

Scenario B

SC configuration OTA topology Number of bits Sampling and feedback cap.{Cuj , Cfj } (pF) Load cap. (pF) Compensation cap. (pF) Switch-on resistances () . rusj , ruaj , risj , ros1j , ros2j

S/H 1stg-FN – {4, –} 2 – {50, 50, 50, –, 50}

MDAC 2stg-MC 3 {0.35, 0.35} 1.45 0.8 {600, 900, 200, 250, 250}

{196, –} {2.05, –} {0.25, –} 7.71 {145, –, 510} {0, −0.97, 0.01, −3.57}

{298, 16} {2.61, 10.8} {0.3, 1.61} 4.35 {541, 706, 690} {0.03, −0.69, 0.02, −1.35}

– 60

0.6 60

OTA parameters DC gains {Ao1j , Ao2j } Transconductances {gm1j , gm2j }(mA/V) Currents {io1 , io2 } (mA) √ Eq. input noise (nV/ Hz) Parasitic cap. (pF) {Cpj , Co1j , Clj } Non-linear coeff. (a1 |a2 |a3 |a4 )(V −1 , V −2 , V −3 , V −4 ) Reference voltage Sampling frequency (MHz)

4.1 Non-Idealities in SH and MDACS

95

vbp

io2 /2

in

ip vbp

io1 /2 vcp

on

io1 /2 vcp

op

vcp

ip vcn

io2 /2

io1

Cc

op

in

op1

on1

Cc

on

vcn vcn

vbn

vbn

a

b

Fig. 4.18 OTA architectures: a one-stage folded cascode and b two-stage MC topologies

Fig. 4.19 Output noise vs. sampling capacitor for the SC circuit in example A

20 Behavioural Transistor

Output noise (nV2)

18

16

14

12 10 2

4

6

8

10

Sampling capacitor (pF)

the proposed models and a comparison then carried out between electrical and behavioural simulations. The transistor-level simulations were carried out with SpectreRF, using the so-called Pnoise analysis, which allows the analysis of noise generated in cyclostationary systems. Noise generated by MOS switches and the OTA was considered. Figure 4.19 depicts a parametric noise analysis versus the sampling capacitor. It can be observed that the behavioural simulation proposed shows close agreement with the transistor-level simulations. In design example B, the MDAC circuit in Fig. 4.1b is considered using the two-stage MC OTA topology in Fig. 4.18b. The OTA is composed of a p-input telescopic first stage and a differential n-type class-A amplifier second stage. As in

96

4 Behavioural Modelling of Pipeline ADCs Behavioural Transistor

250 200 150 100

250 Output noise (nV2)

Output noise (nV2)

300

Behavioural Transistor

200 150 100

50 0.25

a

0.3 0.35 0.4 0.45 Unitary capacitor (pF)

50 0.6

0.5

b

0.7 0.8 0.9 1 1.1 Compensation capacitor (pF)

Fig. 4.20 Output noise vs.: a unitary capacitor and b compensation capacitor for the MDAC circuit in example B

the previous example, the parameters from Table 4.13 have been taking the execution of behavioural simulations and comparisons with transistor-level simulations into account. Figure 4.20a, b show two parametric noise analyses using the unitary capacitance and the compensation capacitance as running variables respectively. Once again, agreement with transistor-level simulations is noticeable.

4.1.7

Jitter Noise

As shown in Sect. 1.1.3.2, jitter noise can be modelled as an uncertainty in the sampling time instant. The error introduced by this uncertainty can accordingly be modelled by assuming a sampling instant which is determined by this expression: ti = Ts + nrand(0, σj2 )

(4.41)

where T s is the sampling period and nrand(0, σj 2 ) is a function which generates random numbers normally distributed with variance σj 2 and zero mean.

4.1.8

Behavioural Model of the MDAC

The non-idealities reported above have been integrated into a complete behavioural model of the MDAC. Figure 4.21 shows the basic flow diagram of this behavioural model. It starts by initializing the sampling and feedback capacitors according to the match specified (Eq. (4.6)). The equivalent capacitances, feedback factors, parasitic capacitors and time constants are then computed according to the definitions in Tables 4.2, 4.3, 4.10 and 4.11. After that, it can be established whether the sampling or amplification phase must be evaluated. In the case of the sampling phase, an equivalent input noise voltage is added to the input voltage to emulate the effect of thermal noise. Once the equivalent input voltage

4.1 Non-Idealities in SH and MDACS

97 MDAC beh. model

Initialise capacitances

Compute parasitics, capacitances, feedback factors, time constants

–

2stg. OTA: Table 4.3, 4.11

No

Δ Δ , 2 2

Compute transient evolution

Store sampled voltages

1stg. OTA: Table 4.2, 4.10

Sampling?

Yes

vij, eq =vij +unif

Eq. (4.6)

Fig. 4.22

Fig. 4.23

Compute transient evolution

End

Fig. 4.21 Basic flow diagram of the behavioural model of the MDAC

has been calculated, the transient evolution of the internal nodes of the MDAC is computed according to the flow diagram in Fig. 4.22, and the sampled voltages stored. In the case of the amplification phase, the transient evolution of the internal nodes is computed taking into account the previously stored voltages sampled according to the flow diagram in Fig. 4.23. We will now consider the flow diagrams in Figs. 4.22 and 4.23, and the equivalent input noise computation in greater detail. Equivalent Input Noise Computation The aim of this exercise is to find an equivalent input noise voltage which adds a power noise equal to that previously reported for the MDAC. For this purpose, the MDAC noise is modelled as an equivalent quantization noise. As shown in Chap. 1, the quantization noise power in a converter is computed as: PQ =

2 12

(4.42)

98

4 Behavioural Modelling of Pipeline ADCs

Fig. 4.22 Transient evolution of the internal voltages of the MDAC in the sampling phase

1stg. OTA: Eq. (4.19)

Compute initial voltages

2stg. OTA: Eq. (4.22)

Compute transient evolution

1stg. OTA: Eq. (4.22)-Table 4.10 2stg. OTA: Eq. (4.23)-Table 4.11

Store sampled values

End

1stg. OTA: Eq. (4.7)-(4.8)

Compute initial voltages

2stg. OTA: Eq. (4.10)-(4.12)

i = 1, …, M

End

ti = i ⋅ Ts / (2M)

A = Ao(1 + a1voj + a2voj2 + a3voj3 + a4voj4 )

1 stg. slew

Yes

No

1 stg. linear

1stg. OTA: Table 4.5

Two-stage OTA Yes

No

2 stg. slew

2 stg. linear

2stg. OTA: Table 4.6

Compute transient evolution

Fig. 4.23 Transient evolution of the internal voltages of the MDAC in the amplification phase

where  is the LSB of the converter and defines the limits of the quantization error [−/2, /2]. This quantization error is uniformly distributed on this interval. In addition, the thermal noise power at the input of the MDAC can be computed as: j

j

Pni =

Pno G2j

(4.43)

4.2 Non-Idealities in Sub-ADCS

99

Given that the quantization noise power and the thermal noise power must be identical, an equivalent quantization noise voltage can be calculated generating uniformly distributed random numbers between [−/2, /2] with:  / j  = 12PQ = 12Pni (4.44) Therefore, the thermal noise power can be modelled by adding these random numbers to the input during each sampling phase: vij,

eq

= vij + unif([ − /2, /2])

(4.45)

Flow Diagram for the Transient Evolution During the Sampling Phase As illustrated in Fig. 4.22, the procedure starts by computing the initial voltages of the internal nodes according to Eq. (4.19) or Eq. (4.22), depending on the one-stage or two-stage MC macromodel used respectively for the OTA. The transient evolution is calculated from these initial voltages in accordance with Eqs. (4.22) or (4.23) and the definitions in Table 4.10 and 4.11. Finally, the sampled voltages are stored. Flow Diagram for the Transient Evolution During the Amplification Phase Figure 4.23 shows the basic flow charts implemented in the behavioural model proposed for the estimation of the transient response of the MDAC during the amplification phase. It is worth pointing out that the impact of the amplifier non-linear gain depends at each moment on the output voltage which, in turn is continuously evolving with time. Therefore, in order to emulate this time dependence, the amplification phase is divided into M sub-intervals (10–20 sub-intervals are enough in most practical cases), in which the gains and pole positions of the system are recalculated. The procedure starts by evaluating the initial voltages of the internal nodes of the MDAC according to Eqs. (4.7) and (4.8) or Eqs. (4.10)–(4.12), depending on whether the one-stage or two-stage MC macromodel is used for the OTA. The finite and non-linear DC gain is computed at each sub-interval according to Eq. (4.17). The system poles are evaluated from this value and the linear or slew-rate evolutions decided depending on the interval voltages. Note that for the two-stage MC OTA case, the system may eventually exhibit a different damping factor from one subinterval to another, and the set of equations describing the transient evolution may therefore also vary depending on the sub-interval. After this, the final voltages at the end of the sub-interval are computed according to the transient evolutions in Table 4.5 or Table 4.6. These final values are used as initial voltages for the next sub-interval. The procedure is repeated until all subintervals have been computed. The final voltages are then obtained at the end of the amplification phase.

4.2

Non-Idealities in Sub-ADCS

As mentioned in Chap. 1, the sub-ADC carries out a low-resolution analog-to-digital conversion of the input voltage. It is usually implemented by flash architecture and includes as many comparators as transitions in the input-output characteristic of the

100

4 Behavioural Modelling of Pipeline ADCs

Fig. 4.24 3-bit input-output characteristic of the MDAC with unitary redundancy

vo Vref

Vref / 2

0

–Vref /2

–Vref

000 001 010 011 100 101 110 –Vref

t1

t2

t3

t4

t5

t6

Vref

vi

MDAC. Figure 4.24 shows a common input-output characteristic of a 3-bit MDAC with unitary redundancy. There are six transition voltages (t i ) which define seven possible regions where the digital output bits must be properly defined. A schematic-level implementation for an n-bit sub-ADC is shown in Fig. 4.25. It consists of a resistor ladder between the reference voltages to define the transition voltages, and a set of comparators. Each comparator compares the input voltage with the reference t i and provides the output bit. The thermometer output bits are codified by the switch-encoder and the thermometer-to-binary encoder to produce the final bits for the MDAC switches and binary output bits respectively. According to this implementation, two main non-idealities can be distinguished: • Offset and hysteresis of comparators. • Mismatch between resistors. The non-idealities mentioned above modify the decision voltages of the comparators as shown in Fig. 4.26. The offset error moves the ideal threshold voltage of the comparator whereas the hysteresis defines a region of uncertainty around the new threshold voltage in which the comparator decision is not well-defined. Hysteresis is a result of the comparator keeping a memory of the previous state and needing an overdriving voltage to commute to the correct state. Various techniques are adopted to alleviate this kind of hysteresis, which could be considered deterministic. For instance, latched comparators include a reset phase to eliminate the memory effect of the comparator. However, the deficiencies on the real devices introduce certain residues from the previous state. As a result, the decision of the comparator is unknown in a given delimited region. This hysteresis is of a random nature. The mismatch between resistors impacts on the tap voltages along the resistor ladder, therefore modifying the ideal threshold voltage of the comparators.

4.2 Non-Idealities in Sub-ADCS Vref

101

vi

Ru

T = 2n – 2 k = T/2 = 2nj –1 – 1

Ru

bt1 Thermometer-to-binary enconder

vtap1 Ru bt2

Ru

...

...

...

vtap2

btT

b1 ...

Ru

bn – 1 bn

vtapT Ru Ru Switch encoder Ru ... {bu, bm, bd }k

{bu, bm, bd }1

–Vref

Fig. 4.25 Schematic-level implementation of an n-bit sub-ADC vo

vo

vo vhigh

vhigh

vi

vi

vlow

a

vhigh uncertainty region

vof

vof

vlow

b

vi

hys

vlow

hys

c

Fig. 4.26 Input-output characteristic of a comparator: a ideal, b offset and deterministic hysteresis and c offset and random hysteresis

The effect of these non-idealities is graphically illustrated in Fig. 4.27. As can be seen, the voltage transitions of the input-output characteristic of the MDAC have been displaced. If these displacements become higher than half the reference voltage, the input-output characteristic of the MDAC could saturate. As a result, the performance

102

4 Behavioural Modelling of Pipeline ADCs

Fig. 4.27 3-bit input-output characteristic of the MDAC with unitary redundancy and offset error in comparators

vo

Vref

Vref 2

0

–

Vref 2 000 001 010 011 100 101

–Vref –Vref

t1 t2

t3

t4

t5

110 t6

Vref

sub-ADC behavioural model

Initialize resistor ladder

Ru = Ruo (1 + εm )

Compute tap voltages

vtap, i = f [Ru] voff,i = norm (0, σoff )

Initialize offset and hyst. of comparators

hysi = norm (0, σhys ) vth,i = vtap, i + voff, i

Compute threshold voltages

i = 1, …, M ve = vi – vth, i

No

ve > hys / 2

Hysteresis

Yes vo = HIGH

Yes

ve > hys / 2

Deterministic

Random No

vo = LOW

Fig. 4.28 Behavioural model of the sub-ADC

vo = rnd (HIGH,LOW)

vo = vo,n – 1

vi

4.2 Non-Idealities in Sub-ADCS

103

of the pipeline converter would be drastically affected. These non-idealities must therefore be taken into consideration for accurate modelling. The behavioural model of the sub-ADC is shown in Fig. 4.28. It starts by initializing the resistor ladder according to the mismatch specified. The tap voltages along the resistor ladder are then calculated. Following this, certain offset and hysteresis errors are associated to each comparator in accordance with the statistics specified. It is assumed that the comparator offset and hysteresis are Gaussian-distributed. Once these values are known, the threshold voltages of each comparator are computed. After this, an iterative procedure evaluates the output of each comparator. To do so the input voltages are compared with the threshold voltage. If the difference is higher than the absolute value of half the hysteresis, the input voltage is out of the hysteresis region and the output can easily be determined. Otherwise, the output must be selected according to the kind of hysteresis. In the case of deterministic hysteresis, the output is selected according to the previous decision; otherwise, it is randomly selected.

Chapter 5

Case Study: Design of a 10bit@60MS Pipeline ADC

The proposed design procedure is demonstrated with the design of a 10bit@60MS pipeline ADC. The design process will be divided into several steps. The first of these is the design scenario, that is, the implementation technology, specifications, available devices and technological parameters, which will be presented. Secondly, the high-level converter specifications will be mapped onto electrical-level parameters assuming typical operation conditions and following the design procedure proposed. The design for other technological and environmental corners will then be discussed. As will be demonstrated, oversizing will be required to satisfy the converter specifications on all corners. The electrical-level design of the basic building blocks and auxiliary blocks will subsequently be described. Finally, the converter layout will be carried out. Parasitics will be extracted from this layout and the basic building blocks will be fine tuned. To conclude the chapter, the influence of the packaging parasitics on the converter performance will be evaluated. Note that this design process will be verified by electrical simulations along all design steps.

5.1

Design Scenario

The first challenge for a designer is the design scenario. This is the point at which issues as important as the technology and devices available or the converter specifications are tackled. Let us consider these issues separately.

5.1.1

Converter Specifications

A pipeline converter for high-quality wireless broadcasting systems such as Digital V ideo Broadcasting (DVB), Digital Audio Broadcasting (DAB), and Digital Multimedia Broadcasting (DMB), where resolutions around 10 bits and input signal bandwidths of about 20–40 MHz will be designed. In such applications, low supply voltage, low power and small chip area are simultaneously required. J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_5, © Springer Science+Business Media, LLC 2011

105

106

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Table 5.1 Converter specifications

Technology Voltage supply Input range Sampling rate ENOB Number of bits

130 nm 6-Metal 1.2 V 0.8 Vpp 60 MS/s 9 bits 10 bits

The converter specifications in Table 5.1 meet these requirements. Due to the reduced voltage supply and the high input range required, the use of two-stage OTAs is mandatory. These specifications must be satisfied on all technological and environmental corners with minimum power consumption. In addition, the ENOB requirement must also be satisfied over the entire Nyquist band.

5.1.2

Technology

The 10bit@60MS pipeline ADC is implemented in a 130 nm technology. Since it is a submicron technology, special attention must be paid to the layout parasitics. In addition, the substrate is conductive, which means it is necessary to take extra care when reducing the substrate coupling noise. Regarding the devices available, the target technology provides specific devices for analog applications, such as Metal-Insulator-Metal (MIM) capacitors or different kinds of resistors. High-speed general-purpose MOS transistors are also available. However, the maximum length permitted is 0.4 μm. Therefore, achieving an OTA design with simultaneous high DC gain and output-swing will be a difficult task. Once the available devices and main characteristics of the technology have been identified, some technological parameters must be extracted. These will be used throughout the ADC synthesis procedure. Next, we will consider the most relevant parameters which are the capacitor mismatch and the parasitics from the switches. 5.1.2.1

Capacitor Mismatch

As shown in the previous chapter, the capacitor mismatch can noticeably degrade the input-output characteristic of the MDACs. This error depends on the technological process and must be properly characterized. A simple matching model for the capacitors is provided by the following equation [131]: kc σc (%) = √ WL

(5.1)

where σc is the mismatch standard deviation, k c is a technological parameter and W and L are the dimensions for the capacitor. As can be inferred from Eq. (5.1), the mismatch is inversely proportional to the capacitor area, so the bigger the capacitance, the lower the mismatch error. In order to obtain the k c parameter for the MIM capacitors, several Montecarlo analyses have been carried out considering different

5.1 Design Scenario

107

Fig. 5.1 Mismatch modelling of MIM capacitors

0.12

0.1 y = 0.57*x – 2.2e – 005 σc(%)

0.08

0.06

0.04

0.02 0.05

0.1 0.15 1/√W(um)*L(um)

0.2

capacitor sizes. Figure 5.1 shows the simulation results. The k c parameters can be extracted from these: kc ≈ 0.57 (% · μm)

(5.2)

Typically, designers prefer to use to the capacitance value rather than the capacitor dimensions. Nevertheless, Eq. (5.1) can be easily manipulated to consider the capacitance value as MIM capacitors provide 2 μF/ μm2 . Thus, once a capacitance value C o is provided, the capacitor mismatch can be approximated as follows: σc (%) = √

kc Co /2

(5.3)

The mismatch standard deviation of MIM capacitors will be used throughout the design procedure to determine the minimum values for unitary capacitors.

5.1.2.2

Parasitics from Switches

Switches in SC circuits are implemented using MOS transistors. As a result, they present both non-zero switch-on resistance and parasitic capacitances. This is shown in the equivalent model in Fig. 5.2. The parasitic capacitances can increase the equivalent capacitors in closed-loop operation considerably. They must therefore be VDD clk Vin

VSS Vo

Vin Cpsw

Fig. 5.2 Equivalent model for a switch

Ron Vo Cpsw

108

5 Case Study: Design of a 10bit@60MS Pipeline ADC

taken into account for accurate estimations. These parasitics depend on the switch implementation (NMOS, PMOS or CMOS with a W/ L = 3/1 relation), the sizes for transistors, and the switch state (“ON”, “OFF”). Taking all these factors into account, a batch of electrical-level simulations has been carried out using the switchon resistance as running variable in the 130 nm technology. The results are shown in Figs. 5.3 and 5.4. From there, the parasitics are modelled by the following equation: {N, P , C}MOS

{N, P , C}MOS

Cpsw, {on, off} =

k{on, off}

(5.4)

Ron

Parasitic capacitance (pF)

Parasitic capacitance (pF)

0.06 0.08 0.07 0.06

y = 1.71* x + 0.000263

0.05 0.04 0.03 0.02 0.01 0

0

0.01

a

0.02 0.03 1/Ron (1/Ω)

0.04

0.05 0.04

0.02 0.01 0

0.05

y = 1.02* x + 0.000155

0.03

0

0.01

b

0.02 0.03 1/Ron (1/Ω)

0.04

0.05

0.02

0.025

0.02

0.025

Fig. 5.3 Parasitic modelling for CMOS switch in a “ON” and b “OFF” state

Parasitic capacitance (pF)

Parasitic capacitance (pF)

0.025 0.02 y = 0.937* x + 0.0001

0.015 0.01 0.005 0

0.005

0.01 0.015 1/Ron (1/Ω)

0.02

0.025

b

0.06

c

Parasitic capacitance (pF)

Parasitic capacitance (pF)

0.07

0.05 y = 2.48* x + 0.000107

0.04 0.03 0.02 0.01 0

y = 0.654* x + 6.95e – 005

0.01

0.005

0 0

a

0.015

0

0.005

0.01 0.015 1/Ron (1/Ω)

0.035 0.03 0.025 y = 1.37* x + 5.92e – 005 0.02 0.015 0.01 0.005 0

0

0.005

0.01

0.015

1/Ron (1/Ω)

0.02

0.025

0

d

0.005

0.01 0.015 1/Ron (1/Ω)

Fig. 5.4 Parasitic modelling for NMOS switch in a “ON” and b “OFF” state; PMOS switch in c “ON” and d “OFF” state

5.2 Transistor-Level Synthesis of the ADC Table 5.2 Some relevant technological parameters

109

Parameter CMOS (kon ,

CMOS koff )

NMOS NMOS (kon , koff ) PMOS PMOS (kon , koff )

Meaning

Value

Parasitic CMOS switch-on and -off factors (pF · ) Parasitic NMOS switch-on and -off factors (pF · ) Parasitic PMOS switch-on and -off factors (pF · )

1.71−1.02 0.937−0.654 2.48−1.37

{N , P , C}MOS

where k {on, off } is a technological parameter and Ron is the switch-on resistance. The parameters extracted from these plots are summarized in Table 5.2. The switch parasitics will be determined from these values using the switch-on resistances required.

5.2 Transistor-Level Synthesis of the ADC Once the converter specifications and the technological parameters have been identified, the transistor-level synthesis of the converter is carried out following the design procedures described in Chap. 3. As previously explained, a two-stage OTA topology is required due to the reduced voltage supply and the lengths permitted for transistors. In this ADC design, we have considered the two-stage MC OTA topology in Fig. 5.5. It is composed of a p-input telescopic first stage and a differential n-type class-A amplifier second stage. The 10bit@60MS/s pipeline ADC has been synthesized considering the pipeline architectures in Table 5.3, which also summarizes the synthesis results. We considered resolutions lower than 3 bits-per-stage since a higher resolution-per-stage value

M13

Cc

io2

ib

M5

M1

M2

M3

M4

M12

Cc

M15

M7

M6

M18

M9

M8

Fig. 5.5 OTA topology considered in the pipeline ADC

M14

110

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Table 5.3 Pipeline architectures synthesized using the design procedure proposed Stages

Resolution-per-stage

ENOB (bits)

Power (mW)

5 5 5 6 6 6 7 7 7 7 8 8 9

2-3-3-3-3 3-2-3-3-3 3-3-3-3-2 2-2-2-3-3-3 3-2-3-2-2-3 3-3-3-2-2-2 2-2-2-3-3-3-2 3-2-3-2-2-2-2 3-2-2-2-2-2-3 3-3-2-2-2-2-2 2-2-2-2-2-2-2-3 3-2-2-2-2-2-2-2 2-2-2-2-2-2-2-2-2

9 9 9 9 9 9 9 9 9 9 9 9 9

18.49 17.21 16.13 21.73 17.65 17.57 24.65 18.89 24.53 18.91 27.98 20.06 25.60

would require a low stage LSB, hindering the sub-ADC design due to the reduced voltage reference. It can be inferred from Table 5.3 that the 5-stage pipeline architecture with 3-3-3-3-2 bits-per-stage distribution is optimal in terms of power consumption. It is worth mentioning that each architecture synthesis took about 25 min of CPU time and 700 iterations. This means about 2.5 s of CPU time per iteration. The synthesis results for the optimum 5-stage pipeline architecture are summarized in Table 5.4. The sizing results and performance metrics calculated with the proposed design procedure and obtained from electrical-level simulations are shown respectively. In the latter case, the transistor dimensions have been fine tuned to guarantee that pMOS and nMOS transistors carry the same currents through the amplifier branches. This is done in order to nullify systematic offset errors. As can be seen, sizing deviations rarely exceed 10%. Table 5.4 demonstrates that there is excellent agreement between the performance metrics obtained using our approach and those obtained using electrical simulations. The total power consumption of the ADC, at electrical level, including SH, MDACs and sub-ADCs, is approximately 16.6 mW. This coincides with the power consumption estimated by our proposed synthesis tool as depicted in Table 5.4. The verification of the converter specifications was carried out taking the sizing results in Table 5.4 into account. This verification was hierarchically executed following the procedure in Fig. 5.6. This starts by individually characterizing each stage as a stand-alone device. For this purpose, we have computed the thermal noise power (Pnjth ), and the static and dynamic error power (PjS&D ) separately. The former was obtained by means of PSS analysis in SpectreRF and was input referred. The latter was obtained by means of a conventional transient analysis by introducing a Nyquist frequency sinusoidal signal at the input stage. The output bits were then combined with a binary-codified version of the residue [102]. An FFT was computed from the final combined bits to obtain the ENOBS&D . This metric translates to power as an j equivalent quantization power: PjS&D

 2 2Vref 1 = 12 2ENOBS&D j

(5.5)

Table 5.4 Sizing results for the 5-stage 3-3-3-3-2 pipeline ADC

5.2 Transistor-Level Synthesis of the ADC 111

112

5 Case Study: Design of a 10bit@60MS Pipeline ADC Individual stage characterization

Transient analysis with Spectre

PSS analysis with SpectreRF

Transient analysis with Spectre

Compute input referred noise

Compose output bits with residue

Combined output bits

FFT analysis ENOBjS&D

FFT analysis ENOB S&D

Compute PjS&D from Eq. (5.5)

Compute P S&D

Noise computation

a

ADC characterization

S&D errors computation

Compute ENOBj from Eq. (5.6)

Compute equiv. input referred noise from Eq. (5.7)

Noise computation

S&D errors computation

Compute ENOB

b

Fig. 5.6 Verification procedure: a individual stage and b whole ADC

where V ref stands for the single-ended reference voltage (400 mV). Neglecting the jitter noise contribution, the final stage effective resolution can be obtained as follows: ⎛ ⎞ 2 V 1 ref ⎠ (5.6) ENOBj = log2 ⎝  th 2 3 P + P S&D nj

j

Once the stages have been individually characterized, the cascade of stages is verified to compute the entire resolution of the ADC. Analogously, the total noise power and static and dynamic error power are computed separately. The former is obtained by calculating the equivalent noise at the input of the ADC as follows: th + Pn,theq = Pn0

1 th 1 1 th P + 2 2 Pn2 + ··· + 2 2 P th 2 n1 G0 G0 G1 G0 G1 · · · G2k−1 nk

(5.7)

where Gj is the j-stage gain factor (index 0 corresponds to the SH circuit), k is the index of the last MDAC (k = 4 for the 5-stage pipeline architecture under study) and Pnjth is the j-stage input-referred noise power. The static and dynamic errors are again computed by extracting the ENOBS&D from the FFT analysis of the ADC output bits. It is clear that the ENOBS&D includes the ADC quantization error in this case. The simulation results are summarized in Table 5.5, where, the sub-ADCs and auxiliary building blocks (reference voltage generator, digital blocks, etc) are considered to be ideal at this moment. As can be inferred, there is excellent agreement

5.3 Redesigning for Corners

113

Table 5.5 Simulation results of the 5-stage pipeline ADC under typical conditions Simulation

Metric

SH

Stage1

Stage2

Stage3

Stage4

ADC

Behavioural

ENOBS&D (bits) j PjS&D (nV2 ) Pnjth (nV2 ) ENOBj (bits)

11.74 4.55 10.56 10.88

10.46 27.08 12.63 10.18

9.95 54.80 23.13 9.69

6.34 8130 45.13 6.34

5.05 48832 42.88 5.05

9.10 165.25 24.82 9.01

(bits) ENOBS&D j PjS&D (nV2 ) Pnjth (nV2 ) ENOBj (bits)

11.64 5.24 10.42 10.85

10.44 27.64 9.56 10.23

10.03 48.79 16.94 9.82

6.00 13021 35.38 6.00

5.10 45321 36.19 5.10

9.39 134.23 21.19 9.19

Electrical

between the behavioural and electrical simulations. Indeed, deviations from the target resolution requirements remain below 0.3-bit equivalence in all cases.

5.3

Redesigning for Corners

So far we have assumed typical conditions operation for the ADC. However, a robust design must satisfy the converter specifications on all corners. Here we summarize the simulation results at electrical level of the 5-stage pipeline ADC taking static and dynamic errors into consideration and applied to the five technological and environmental corners depicted in Table 5.6. As can be inferred, converter specifications are not fully satisfied. Two main strategies could be adopted to overcome this problem: sizing the ADC on the worst case corner or oversizing the ADC on the typical corner. The former does not guarantee that converter specifications are satisfied for the remaining corners. On the other hand, we think that focusing a design on a rather unlikely corner is not a good strategy. For these reasons, we have chosen the latter strategy, that is to say, oversizing. The ADC is oversized simply by reducing the time constants required for the OTAs. Thus, if a specific stage has decreased its resolution on the worst corner by m bits, its time constant is decreased until the stage resolution on the typical corner is increased by at least these m bits. The remaining parameters such as the unitary capacitors or the overdrive voltages remain unchanged. The new sizing results are summarized in Table 5.7, from where it can be inferred that this oversizing represents an increase in consumption of about 3 mW power. Table 5.6 Corner definition and metrics of the initial design MOS models Temperature MIM cap. models Voltage supply ENOBS&D (bits)

Typical

Fast

Slow

WorstONE

WorstZERO

Typical 27◦ C Typical 1.2 V 9.39

Fast n Fast p −40◦ C Min 1.32 V 9.44

Slow n Slow p 85◦ C Max 1.08 V 7.19

Fast n Slow p 85◦ C Typical 1.08 V 8.38

Slow n Fast p 85◦ C Typical 1.08 V 9.22

Table 5.7 Oversizing results for the 5-stage 3-3-3-3-2 pipeline ADC

114 5 Case Study: Design of a 10bit@60MS Pipeline ADC

5.3 Redesigning for Corners

115

at technological corners before and after optimizing the compensation Table 5.8 ENOBS&D j capacitor Stage

Comp. cap. (pF)

SH Stage 1 Stage 2 Stage 3 Stage 4

2.4 → 2.35 1.1 → 1.1 0.7 → 0.625 0.4 → 0.3 0.4 → 0.3

Corner ENOB Typical

Fast

Slow

WorstONE

WorstZERO

11.64 → 11.48 13.49 → 13.49 10.69 → 13.45 7.97 → 9.39 5.81 → 8.89

14.02 → 13.99 11.25 → 11.25 9.44 → 10.38 8.09 → 11.97 6.31 → 9.78

10.30 → 10.73 10.69 → 10.69 10.00 → 10.22 7.05 → 8.30 4.99 → 6.40

10.70 → 10.71 13.14 → 13.14 9.59 → 12.75 7.15 → 9.68 5.27 → 6.91

10.83 → 10.66 12.07 → 12.07 11.46 → 11.67 8.11 → 8.38 5.67 → 8.56

Note that the OTAs have been sized assuming a critically-damped response, or in other words, with a damping factor ξj = 1. However, this damping factor changes with the corner conditions. Therefore, it would be interesting to find the optimum value for the best performance on all corners. For this purpose, each stage has been individually analyzed as a stand-alone device. In particular, a parametric analysis at electrical level has been carried out, taking the compensation capacitor (C cj ) as running variable. The optimum value for the compensation capacitor together with the simulation results are summarized in Table 5.8. The data collect the values obtained for ENOB on different corners. Each ENOB entry in Table 5.8 includes two numerical data linked by an arrow. These correspond with the two different values of the compensation capacitor shown in the second column of the table. The first value represents the original value obtained from the synthesis procedure whereas the second value stands for the optimum value calculated with the parametric analysis. Transistor sizes and biasing conditions remain as indicated in Table 5.7. It is worth mentioning that this oversizing will increase the resolution on the typical corner considerably. However, this increment will not be easily appreciated on the ADC performance since the quantization error will limit the resolution to under 10 bits. To overcome this limitation, we decided to use a 3-bit sub-ADC in the last stage instead of the original 2-bit sub-ADC. This change does not cause any considerable impact on the pipeline architecture (a minor increment of the power consumption) but it halves the quantization error and simplifies the layout. Table 5.9 depicts the Table 5.9 Simulation results of the oversized 5-stage pipeline ADC Last stage

Metric

Corner Typical

Fast

Slow

WorstONE

WorstZERO

2-bit sub-ADC

(bits) ENOBS&D j PjS&D (nV2 ) Pnjth (nV2 ) ENOBj (bits)

9.72 74.4 19.4 9.56

9.78 69.1 15.8 9.68

9.12 173 23.5 9.03

9.71 75.6 22.2 9.53

9.52 98.5 22.9 9.37

3-bit sub-ADC

(bits) ENOBS&D j PjS&D (nV2 ) Pnjth (nV2 ) ENOBj (bits)

10.58 22.7 19.4 10.1

10.51 24.9 15.8 10.2

9.36 124 23.5 9.23

10.44 27.7 22.2 10.0

9.84 63.7 22.9 9.62

116

5 Case Study: Design of a 10bit@60MS Pipeline ADC

simulation results for the 5-stage pipeline architecture considering the sizing results in Table 5.7 and optimum values for the compensation capacitor found with the previous parametric analysis. The sub-ADC and auxiliary building blocks are again considered to be ideal at this moment. This table shows the simulation results for both a 2-bit and 3-bit sub-ADC last stage. As can be inferred, the converter specifications are fully satisfied on all corners. In addition, the final ADC resolution is considerably increased over all corners when a 3-bit sub-ADC is used. Again, static and dynamic errors and noise powers are computed separately.

5.4

Electrical-Level Design: Detailed Description

A detailed description at electrical level of the basic building blocks in the 5-stage pipeline ADC under design will be shown in this section. The auxiliary building blocks, such as reference voltage and bias current generators, digital logic, clock phase generator, etc. will also be presented.

5.4.1

SH Circuit

A fully differential schematic of the SH circuit is shown in Fig. 5.7a. The sampling (phiS) and amplification (phiA) phases are non-overlapped as can be observed in Fig. 5.7b. In addition, a delayed version of the sampling (phiSd) and amplification

phiAd

Ts ⁄ 2

VCMi phiAdn

vip

phiS

phiS Cs

td

– +

BT phiS

vin

vop

phiSd

phiSdn + –

BT

tnov

tnov

von

Cs phiS

phiAd

Fig. 5.7 SH: a fully differential schematic and b clock phases

tnov

phiA td

VCMi phiAdn

a

td

td

phiAd

b

5.4 Electrical-Level Design: Detailed Description

117

phases (phiAd) is required in order to reduce the charge injection error due to the switches [1, 20]. The values for the delay (t d ), non-overlapping (t nov ), rising and falling times will be discussed in Sect. 5.4.4.1. We will now consider some practical issues regarding the devices which compose the SH.

5.4.1.1

Capacitors

The sampling capacitors are implemented by means of MIM capacitors. The linearity and matching of these devices is very good, so the performance of the SH circuit is not compromised by the non-idealities of the MIM capacitors.

5.4.1.2

Switches

As shown in Chap. 4, the switches can be implemented using MOS transistors. However, special attention must be paid to their non-idealities. On the one hand, MOS switches introduce parasitic capacitors which degrade the performance of the SH circuit by increasing the total load capacitance or by mechanisms such as the clock-feedthrough [1, 20]. On the other hand, the switch-on resistance maintains a non-linear dependence with the input voltage. In the case of a single MOS switch, this dependence is provided by the following expression [1]: Ron =

μCox WL (VDD

1 − Vth − Vin )2

(5.8)

where μ and C ox are technological parameters, W and L are the MOS dimensions, and V th is the threshold voltage. This non-linear dependence can introduce harmonic distortion. Analytical expressions for the harmonic distortion introduced by the single track and hold circuit in Fig. 5.8, were obtained using time-varying Volterra VDD clk

vi (t ) = A sin(ωt )

VSS

vo (t )

Ron C

Fig. 5.8 Track and hold circuit analyzed in [132]

118

5 Case Study: Design of a 10bit@60MS Pipeline ADC

series in [132]: HD2 =

A ωCRon 2 Vg − Vth

HD3 =

A2 ωCRon 4 (Vg − Vth )2

(5.9)

where A and ω are the amplitude and frequency of the input voltage respectively. As can be inferred from Eq. (5.9), the higher the amplitude and frequency of the input signal, the higher the harmonic distortion. Therefore, special attention must be paid to switches which suffer from high-input amplitudes and frequency signals. This is the case for the sampling switches in the SH circuit in Fig. 5.7a. In order to reduce the harmonic distortion, bootstrapped switches have been used. They will be presented in Sect. 5.4.1.3. Regarding the remaining switches, it is possible to use conventional MOS switches since they do not suffer from high-frequency signals. The question now is to determine whether single or CMOS switches must be used. A single MOS switch introduces less parasitics but presents a strong dependence with the input voltage. In fact, the MOS switch turns to “off” mode if the input signal is so high that the gate-source voltage is lower than the threshold voltage, that is: Vgs < Vth → vi > VDD − Vth

(5.10)

A CMOS switch can improve the admissible input voltage at the expense of increasing the parasitic capacitances. Taking these considerations into account, the reset switches have been implemented using simple MOS transistors, since they connect the OTA input and output nodes to constant voltages (to the common mode voltages). In contrast, CMOS switches are required for the implementation of the amplification switches given the high-output swing of the SH circuit.

5.4.1.3

Bootstrapped Switch

The bootstrapping technique has been widely used for rail-to-rail operation of SC circuits and high-speed high-resolution applications [38–42]. The aim is to remove the resistance dependence on the input signal by achieving a constant voltage on the gate-source of the MOS switch. For this purpose, the switch gate voltage tracks the analog input with a constant offset shifting, typically V DD . Figure 5.9 shows a

φ2

φ1

Fig. 5.9 Functional schematic of the gate-source bootstrapping technique

S3

S1

Coff

φ2

φ1

S4

S2

φ2 S5

vin Mnsw

5.4 Electrical-Level Design: Detailed Description

119

functional realization of the well-known gate-to-source bootstrapping technique. It consists of an MOS switch (M nsw ), five additional switches (S 1 –S 5 ) and an additional capacitor (C off ). During the clock phase φ2 , capacitor C off is charged to the supply voltage V DD by means of switches S 3 and S 4 , while the MOS switch M nsw is grounded using switch S 5 . Then, during the clock phase φ1 , switches S 1 and S 2 add the input voltage vin to the precharged capacitor. Applying the charge conservation principle, the gate voltage of the MOS switch at the end of the phase φ1 is given by [39]: vg =

Coff (vin + VDD ) Coff + Cp

(5.11)

where C p stands for the total parasitic capacitance on the switch gate. Neglecting the parasitic capacitance C p , the gate-source voltage of the MOS switch would be: vgs = vg − vin = VDD

(5.12)

Therefore, the gate-source voltage of the MOS switch maintains a constant value, so the switch-on resistance remains almost constant and the harmonic distortion is reduced considerably. A practical implementation of the gate-source boostrapping technique was proposed in [38]. The transistor-level implementation is depicted in Fig. 5.10, where, transistors M n1 , M p2 , M n3 , M p4 and M n5 correspond to the ideal switches S 1 –S 5 in Fig. 5.9 respectively. The remaining transistors and modified connectivity were introduced to extend all switch operations from rail to rail while keeping the maximum gate-source voltages of transistors below V DD . To ensure simplicity and performance, this topology has been chosen for the implementation of the sampling switches in the SH circuit. Before presenting the simulation results, let us summarize some practical considerations: • In accordance with Eq. (5.11), C off must be large enough to supply sufficient charge to gate M nsw when it is turned on. We must therefore try to minimize the VDD VG

Mn3

VDD

A

Coff M p6 B φ1

vin

φ1

Mp4

φ2n

φ2

Mn6w Mn6

time Mn1

Mp2

C

φ2

Mnt 5

Mn5

G

vin time

VDD

Mnsw

Fig. 5.10 Transistor-level implementation of the gate-source bootstrapping technique

120

5 Case Study: Design of a 10bit@60MS Pipeline ADC

at the technological corners for the TH circuit in Fig. 5.11 Table 5.10 ENOBS&D j Switch

Corner ENOB

Bootstrapping NMOS

Typical

Fast

Slow

WorstONE

WorstZERO

14.98 10.49

16.03 11.94

13.70 8.94

14.70 10.96

13.08 8.86

VDD

clk

VSS vip

vop Mnsw

C

C

Mnsw vin VDD

von

VSS clk

Fig. 5.11 Differential track and hold circuit considered in the switch simulations

parasitic capacitance C p at the switch gate. Accordingly, transistor sizes must be minimized as long as the RC time constant is in keeping with the settling time. • The bulk of transistors M p2 and M p4 must be tied to the highest potential, that is, to node B, and not V DD . The simulation results are summarized in Table 5.10. We considered the differential track and hold circuit in Fig. 5.11, the transistor-level implementation in Fig. 5.10 as sampling switch and a 4 pF as sampling capacitor. The transistor switch M nsw was sized to implement the 50  resistance required and a 200 fF offset capacitor (C off ) was used. Simulation results were obtained for a sinusoidal input signal with amplitude 400 mV and frequency 28.8 MHz, evaluated from 256 samples at a sampling rate of 60 MHz. For illustration purposes, the simulation results have been compared with a simple NMOS switch. As can be inferred from Table 5.10, the harmonic distortion is reduced considerably when the bootstrapping technique is used. This is better appreciated in Fig. 5.12, where the output spectra on the typical corner are compared. 5.4.1.4

OTA

As shown in Sect. 5.2, the two-stage MC topology in Fig. 5.5 was considered for the implementation of the OTAs. Figure 5.13 shows a detailed schematic with the CMFB and bias circuit. The former was implemented by the SC circuit in Fig. 5.14 and

Welch Power Spectral Density Estimate –50

Welch Power Spectral Density Estimate –50

–100

Power/frequency (dB/Hz)

121

Power/frequency (dB/Hz)

5.4 Electrical-Level Design: Detailed Description

SFDR = 91.93dB

–150 –200 –250 –300 –350

–100

SFDR = 65.4dB

–150 –200 –250 –300 –350

0

5

10 15 20 25 Frequency (MHz)

a

30

0

5

b

10 15 20 25 Frequency (MHz)

30

M1

M4

vcp

Cc vop1

vfbn

vbn

M9b M9

Cc

von1 vcn

M7

M15

M18

ip

M2

M3

M12 M12b

vfbp

in

von

vbp

M5

M13b M13

SC-CMFB

vop SC-CMFB

M6

VCMo2 vbp ibias

VCMo1 vbn

ibias

M14 vfbn

vfbp

Fig. 5.12 Output spectra considering: a bootstrapping or b NMOS switch

M8 M8b

Fig. 5.13 OTA schematic with CMFB and bias circuits phiAdn

phiSdn

vop

von

phiSdn

phiAdn

VCM

VCM

75fF phiAdn

phiSdn

vb

Fig. 5.14 SC CMFB schematic

75fF

75fF phiSdn

75fF phiAdn vb

122

5 Case Study: Design of a 10bit@60MS Pipeline ADC

the latter requires two external current biases of 50 μA. Both the power consumption of the bias circuit and the capacitors of the CMFB circuit have been considered in the synthesis procedure. The basic principle of the Common Mode FeedBack (CMFB) circuit is to sense the difference between the common mode of the stage output voltages (vop1 , von1 & vop , von ) and the required value. From this difference, a correction voltage (vfbp & vfbn ) is applied on transistors (M 13b , M 12b & M 3b , M 4b ) which partially control the current flows on the stage output nodes. Special attention must be paid to the gain and bandwidth of the CMFB circuit when their capacitors and switches are being sized. Suitable values were selected from transistor-level simulations. Specifically, PMOS switches slightly over minimum dimensions and 75 fF CMFB capacitors provided an excellent bandwidth; whereas the gain was controlled by the number of fingers into which the transistors controlling the current output flows M 13b , M 12b & M 3b , M 4b were split.

5.4.2

MDACs

The MDACs in the 5-stage pipeline ADC solve 3 bits and use unitary redundancy. A fully differential schematic of the 3-bit MDAC is shown in Fig. 5.15. The clock phases are the same as those in an SH circuit. No bootstrapping switches are required since

phiAd phiSd

phiSd phiSdn

Vrefn phiSdn

bxp1

phiSd bzn1

Vrefp

Vrefn phiSdn

Vrefp

bxp2

phiSd bzn2

phiSdn

bxp3

bzn3

Vrefp

Vrefn

vip

Cu

Cu

Cu

Cu

phiS

phiAdn

byp1

byp3

byp2

– + phiS

phiSdn

Vrefp

vin

Fig. 5.15 3-bit MDAC fully differential schematic

phiSd

Cu phiSd phiSdn

phiSdn

bxn1

phiSd bzp1

phiSdn

Cu

Vrefn

Vrefp

bxn2

phiSdn

phiSd bzp2 Vrefn

Vrefp

bxn3

bzp3 Vrefn

Cu

phiS

+ – Cu

vop

phiAd

phiAdn

von

5.4 Electrical-Level Design: Detailed Description

123

all MDAC inputs and outputs are constant voltages (references) or sampled signals (these evolve to a fixed value). Single MOS switches are used to connect reference voltages and common-mode voltages, while CMOS switches are required for input and output signals. MIM capacitors are used for the implementation of the unitary capacitors. The switches which connect with the reference voltages in the amplification phase are controlled by special digital signals (bxp3 , byp3 , bzp3 , bxn3 , byn3 , bzn3 , . . . ). These signals are generated by a digital circuit (switch encoder) which will be detailed in Sect. 5.4.3.4. The OTA is also implemented by the topology in Fig. 5.13. In fact, CMFB and bias circuits are identical to those in the SH circuit.

5.4.3

Sub-ADCs

Figure 5.16 illustrates the 3-bit sub-ADC schematic employed in the 5-stage pipeline converter under design. This consists of four basic building blocks: 1. A resistor ladder between the reference voltages to define the transitions voltages or tap voltages. 2. A set of comparators to obtain the thermometer bits. 3. A thermometer-to-binary encoder. 4. A switch encoder which obtains the digital signals which control the MDAC switches during the amplification phase. Let us explain each building block in detail.

Vrefp

Vrefn

~0.925 Ru vt6

vip vin

MS +

-

vt6 vt1

vt4

vt3

vt2

~0.525

vt1

LS btp6

+

-

vt5

btn6

vt5 vt2

b2 b1 b0

+

+

– +

–

vt4 vt3

– +

–

vt3 vt4

– +

–

btp[1:6] Thermometer-tobinary Encoder btn[1:6]

Fig. 5.16 3-bit sub-ADC schematic

+

+

vt2 vt5

– +

–

Switch Encoder

+

vt1 vt6

–

btp1

+

–

btn1

bxp-n [3:1] byp-n [3:1] bzp-n [3:1]

124

5 Case Study: Design of a 10bit@60MS Pipeline ADC

5.4.3.1

Resistor Ladder

The resistor ladder in Fig. 5.16 provides 6 voltage transitions (V t1 , . . . , V t6 ). Three basic aspects of the value selection for the unitary resistor must be considered: settling time, mismatch and power consumption. As far as power consumption is concerned, it is obvious that a high value for the unitary resistor is advisable. In fact, the power consumption of the resistor ladder is given by: PR =

2 Vref

(5.13)

N R Ru

where N R is the number of unitary resistors and Ru stands for the unitary resistor itself. Therefore, the higher the unitary resistor, the lower the power consumption. However, a high value for the unitary resistance can deteriorate the settling response [3], since the resistors together with the capacitors from the comparators form RC time constants. On the other hand, a lower value for the unitary resistor can also complicate the design of the voltage reference generator, so a suitable value must be selected for the unitary resistor. Finally, a 150  unitary resistor gave rise to a suitable power consumption-settling time trade-off. For this value, the power consumption is 67 μW, since N R = 16 and V ref = 400 mV. Another important design consideration is the resistor mismatch which is directly translated to an offset error. Once the unitary value has been selected, a proper layout can improve the mismatch by increasing the total resistor area or using improvement layout techniques (common centroid,. . . ).

5.4.3.2

Comparators

Figure 5.17 illustrates a simplified schematic of the SC comparator. This consists of a front-end SC preamplifier with offset cancellation, a dynamic latch to improve the

phiRd phiR

vtp phiRdn phiAd

vip

van vap

phiAdn

vin phiAd phiRdn

phiRn

Ccomp

Ccomp

Dynamic latch

– +

–

+

R

Q

+ –

+

–

S

xQ

OTA phiRn

strobe

RS flip-flop

btp btn phiR phiA

vtn

phiR phiRd

Fig. 5.17 Comparator schematic

5.4 Electrical-Level Design: Detailed Description

125

dynamic response, and an RS flip-flop to maintain the output bits. This topology introduces three main advantages against a conventional comparator based on a single amplifier: (1) the preamplifier offset is cancelled and the latch offset contribution is divided by the gain preamplifier; (2) the dynamic response improves considerably thanks to the positive feedback latch, and finally, (3) the input preamplifier common mode can be arbitrary selected since it is capacitively decoupled. The main disadvantage is that the load input capacitance could be higher than other topologies without an SC front-end. We will explain the basic operation principle of the basic building blocks in detail in Fig. 5.17. Front-End SC Preamplifier In the analysis of the front-end SC circuit in Fig. 5.17 we will consider the singleended circuit shown in Fig. 5.18, and the results will be extended to the differential circuit. A preamplifier with finite DC gain Ao and input-referred offset voff will be assumed. In addition, a parasitic input capacitance (C p ) in the preamplifier input node will be considered. The front-end SC preamplifier comprises two non-overlapping clock phases: the reset and amplification phases. During the reset phase, the charge stored by the capacitances connected to the negative input node of the preamplifier will be given by: Qn−1/2 = Ccomp (van, n−1 − vtp, n−1 ) + Cp van, n−1 where van, n - 1 can be obtained from the closed-loop configuration of the preamplifier: van, n−1 =

Ao voff ≈ voff Ao + 1

During the amplification phase, the charge stored will be: Qn = Ccomp (van, n − vip, n ) + Cp van, n

(5.14)

Applying the charge conservation principle: Qn−1/2 = Qn ⇒ van, n = α(vip, n − vtp, n−1 ) + voff phiRd phiR

vtp phiRdn phiAd

phiRn

Ccomp

vip

van phiAdn

Cp

Ao +

+ –

Fig. 5.18 Single-ended front-end SC schematic

–

voff

vo

126

5 Case Study: Design of a 10bit@60MS Pipeline ADC

where α is a gain factor given by: α=

Ccomp Ccomp + Cp

(5.15)

Therefore, the output voltage at the end of the amplification phase will be: vo, n = Ao (vap, n − van, n ) = Ao (voff − van, n ) = αAo (vip, n − vtp, n−1 )

(5.16)

This result can be extended to the differential circuit in Fig. 5.17 as follows: ( ) vo, n = Ao (vap, n − van, n ) = −αAo (vip, n − vtp, n−1 ) − (vin, n − vtn, n−1 ) (5.17) In order to increase the sensibility in the presence of low differential voltages, a highgain factor α and preamplifier DC gain Ao are required as can be inferred from Eq. (5.17). To maximize the former, a high ratio C comp /C p is desirable. For this purpose, the parasitic capacitance can be decreased by properly designing the preamplifier and using low dimension switches. A high comparator capacitor (C comp ) can also be used. However, these cannot be arbitrarily sized since the RC time constant must be maintained in keeping with the settling time. A 950  switch and a 100 fF comparator capacitor were selected as a good settling-gain trade-off.

Preamplifier The purpose of the preamplifier is to amplify the differential input voltage in order to improve the dynamic response and sensibility of the latch. Simultaneously, the preamplifier reduces the offset contribution of the latch and reduces kick-back noise. As shown above, a high DC gain is desirable in order to increase this differential input voltage. This amplification must also be provided to the latch with sufficient speed. The architecture in Fig. 5.19 has been employed to satisfy both

vap

van

Iss = ~100μA

Fig. 5.19 Preamplifier schematic

vop

4:1

Ibias = 25μA

von

5.4 Electrical-Level Design: Detailed Description

127

Table 5.11 Preamplifier simulation results Parameter A0 gm (mA/V) GBW (GHz) PH (0 ) CPOT A (fF) POTA (μW)

Corner Typical

Fast

Slow

WorstONE

WorstZERO

22.81 0.63 2.66 80.32 20.55 156

25.85 0.84 3.59 79.32 21.45 184

20.95 0.47 2.03 81.08 19.61 121

17.26 0.53 2.27 81.3 20.13 132

20.51 0.52 2.20 80.81 20.48 131

requirements. It combines simplicity and positive feedback in the PMOS load in order to decrease output impedance and, consequently, increase DC gain. The simulation results are summarized in Table 5.11, where a 20 fF load capacitance, representing the input capacitance of the dynamic latch, has been considered. The power consumption on the worst corner is about 184 μW. This power consumption is in keeping with that estimated in the synthesis procedure which stood at about 188 μW.

Dynamic Latch The aim of the dynamic latch is to provide the output bits resulting from the input voltage comparison with the transition voltage. Figure 5.20 shows the schematic of the latch implemented. It basically consists of two digital inverters, M 1 − 3 and M 2 − 4 , in positive feedback configuration. The operation principle is as follows: if the strobe phase is low (“0”), the latch is reset since transmission gates M t1 and M t2 open the inverter paths, and the output voltages are connected to the voltage supply by means of M 3b and M 4b . When the strobe phase is high (“1”), the differential input voltage causes an unbalanced situation on transistors M R1 and M R2 which is quickly driven to the rails thanks to the positive feedback of the inverters. Note that the time diagram of the comparator clock phases, including the strobe phase, must be meticulously defined. The comparator takes a specific length of time, t d , to decide the output bits. Therefore, if phases from the clock-phase generator were

M3b M3 vonl

vop

Mt 1

M4 M4b vopl

von

Mt 2

strobe vip Digital inverter

Fig. 5.20 Latch schematic

MR1 M1

M2 MR2

vin

128

5 Case Study: Design of a 10bit@60MS Pipeline ADC decision time

decision time

phiS = phiR phiAd = phiAd phiAn = phiAn strobe Strobe phase

Reset phase

Reset phase

Ideal sampled value

vtj vid

Ideal sampled value

vonl

Uncertainty time

vopl

Strobe phase

Correct coded ‘0’

‘1’

‘1’

‘0’

Fig. 5.21 Time diagram of the comparator clock phases

used, phiS and phiSd for the reset phase and phiAd for the strobe phase, the output bits would not be available for the MDACs at the beginning of the amplification phase. In fact, they would be available after t d seconds. Thus, the time available for the MDAC decision during the amplification phase would be reduced. To overcome this problem, the strobe phase is defined during the overlapping time between phiAn and phiAd as shown in the time diagram of Fig. 5.21. Thus, the comparator decision time must be lower than the time elapsed between the beginning of the phiAn clock phase and the beginning of the sampling clock phase phiS. As will be shown in Sect. 5.4.4, this non-overlapping time is about 800 ps. Finally, the strobe phase will be generated by means of an AND digital gate from the corresponding clock phases.

RS Flip-Flop The purpose of this building block is to maintain the output bits from the latch during a cycle time. It also regenerates the input signals. Figure 5.22 illustrates the schematic of the RS flip-flop, which basically consists of two NOR gates in positive feedback

btp btn R

Fig. 5.22 RS flip-flop schematic

S

5.4 Electrical-Level Design: Detailed Description

129

configuration. Thus, the response time required by the RS flip-flop is drastically reduced.

Comparator Electrical-Level Verification Once the basic building blocks have been designed, we must verify whether the highlevel specifications are fully satisfied. These have been extracted from behavioural simulations and can be summarized in two main requirements: 1. The offset and hysteresis standard deviations of the comparators must be lower than 15 mV. 2. The standard deviation of the resistor mismatch must be lower than 10%. A third requirement arises from the time diagram of the clock phases in the comparator. As previously explained, the comparator must determine the output bits during the time elapsed from the beginning of the phiAn—phiS clock phases, which is about 800 ps. The decision time of the comparators must therefore be lower than this value. The unitary resistor was sized at a total area of 40 μm2 . This area guarantees a mismatch lower than 0.2%, which is enough to satisfy the accuracy requirements. In order to evaluate the offset and hysteresis of the comparators, an electricallevel Montecarlo analysis was carried out introducing a small amplitude sinusoidal input signal very close to the transition voltage. A negligible hysteresis was obtained from these simulations. The standard deviations of the offset on the different corners are summarized in Table 5.12. As can be inferred, the results are always lower than 15 mV. Finally, the decision time of the comparators was evaluated by introducing small amplitude steps around the transition voltage. The simulation results are summarized in Table 5.13 for several step amplitudes and for the different corners. Both the Table 5.12 Standard deviation of the comparator offset Parameter σoff (mV)

Corner Typical

Fast

Slow

WorstONE

WorstZERO

1.30

1.58

1.17

1.59

1.32

Table 5.13 Comparator decision time against several step amplitudes Step Amplitude 10 μV 100 μV 500 μV 10 μV 100 μV 500 μV

tHL (ps) Typical

Fast

Slow

WorstONE

WorstZERO

466 366 300 459 365 299

328 267 224 335 269 225

564 447 336 563 454 371

539 432 355 562 428 336

524 422 348 530 423 349

130

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Table 5.14 Truth table of the binary-to-thermometer encoder btp6

btp5

btp4

btp3

btp2

btp1

B2

B1

B0

0 0 0 0 0 0 1

0 0 0 0 0 1 1

0 0 0 0 1 1 1

0 0 0 1 1 1 1

0 0 1 1 1 1 1

0 1 1 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 0 1

0 1 0 1 0 1 0

high-to-low (t HL ) and the low-to-high (t LH ) decision times were characterized. As can be inferred, the decision time of the comparators is lower than 800 ps in all cases. 5.4.3.3 Thermometer-to-Binary Encoder This basic building block codifies the thermometer bits provided by the sub-ADC to binary-code. The required logic function is described by the truth table in Table 5.14. In order to implement this truth table, the multiplexer-based architecture in Fig. 5.23 has been selected. This architecture provides suitable performance in terms of power

btp4

B2

1 s

B1 btp3

0 s

1 s

B0 0 s

btp6

1 s

btp2

0 s

btp5

1

btp1

0 s

s

1

s 0

btn4

Fig. 5.23 Implementation of the thermometer-to-binary encoder

S

5.4 Electrical-Level Design: Detailed Description

131

Table 5.15 Truth table of the switch encoder btp6 btp5 btp4 btp3 btp2 btp1 bxp3 bxp2 bxp1 byp3 byp2 byp1 bzp3 bzp2 bzp1 0 0 0 0 0 0 1

0 0 0 0 0 1 1

0 0 0 0 1 1 1

0 0 0 1 1 1 1

0 0 1 1 1 1 1

0 1 1 1 1 1 1

1 0 0 0 0 0 0

1 1 0 0 0 0 0

1 1 1 0 0 0 0

0 1 1 1 0 0 0

0 0 1 1 1 0 0

0 0 0 1 1 1 0

0 0 0 0 1 1 1

0 0 0 0 0 1 1

0 0 0 0 0 0 1

consumption, area efficiency and speed among other ROM-based, one-counter or 4-level folded Wallace-tree solutions [133]. 5.4.3.4

Switch Encoder

This building block generates the signals required for the activation of the MDAC switches during the amplification phase. These signals must be generated from the sub-ADC thermometer bits according to the truth table featured in Table 5.15. As can be inferred, the MDAC switch signals can be obtained using NOR gates as shown in Fig. 5.24. Note that the outputs from NOR gates must be synchronized with the amplification-phase clock signal. In addition, the complementary output signals are also required. For this purpose, AND gates have been used.

5.4.4

Clock-Phase Generator

The aim of this circuit is to generate the non-overlapped clock phases required in the SC circuits of the pipeline converter. This is composed of two main building blocks as shown in Fig. 5.25: (1) the phase generator and (2) the tree-distribution circuit. The btp1 btp2

bxp3

btp3

bxn3

btp2

btp4

byp3

btp5

btn1

byn3

btn2

btn3

bzp3

btn4

btn4

bzn3

btn5

bxp2

btp3

bxp1

btp4

bxn1

btp6

byp[1]

byn2

btn3

byn[1]

bzp2

btn5

bzp1

bzn2

btn6

bxn2

phiAd

Fig. 5.24 Implementation of the switch encoder

byp2

bzn1

132

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Fig. 5.25 Clock-phase implementation

phiS phiSn phiS clk

Phase generator

phiSd

phiSd

Clock

phiA

tree

phiA

phiAd

distribution

phiAn

phiSdn

phiAd phiAdn

former generates the non-overlapped clock phases and the latter provides the fanout required to charge the different loads of the clock phases. A detailed explanation of both circuits follows.

5.4.4.1

Phase Generator Circuit

Figure 5.26a illustrates the architecture used for the implementation of the phase generator circuit [134]. This generates the two non-overlapped clock signals (phiS, phiA) and the corresponding delay signals (phiSd, phiAd), from an external clock signal (clk), as shown in Fig. 5.26b. This basically consists of two inverter paths intertwined with each other. The first set of buffers in the cascade of inverters controls the delay between clock phases (phiS-phiSd, phiA-phiAd), whereas the second set of buffers controls the non-overlapping time between clock phases (phiS-phiA). The nominal delay between phases (t ds , t da ) as well as the nominal nonoverlapping time (t novs , t nova ) is about 400 ps. The rise and fall times of the clock phases are around 200 ps. A fast rise or fall time in the external clock signal is not required since the phase generator can regenerate its flanks. However, a duty cycle of around 50% is required for the proper generation of clock phases.

5.4.4.2

Clock-Tree Distribution Circuit

The clock phases are provided to numerous SC circuits of the pipeline converter, each requiring a specific clock phase. Therefore, each clock phase has to drive different load capacitances. This discrepancy between the clock-phase loads could distort the delay and non-overlapping times required. In order to avoid this distortion, a proper fan-out must be provided to each clock phase. The clock tree distribution circuit in Fig. 5.27 was used to this end, with the fan-out progressively duplicating at each level of the clock tree so that the last level inverter (×8) is easily able to charge a load capacitance of about 80 fF. Therefore, the greater the load capacitance needed to drive the corresponding clock phase, the greater the number of last level inverters

5.4 Electrical-Level Design: Detailed Description

Nand

Inv

Inv

Buffer

Nand

Inv

Inv

Buffer

133

Inv En

Buffer

Inv

Inv

Buffer

Inv

Inv

Buffer

Inv

Inv

Buffer

Inv

Inv

phiS

phiSd

clk

En Inv

phiAd

tnovs phiA

Control delay

Control non-overlapping

a

clk

tnovs

tds

tnovs tds

tnovs

tds

tnovs tds

phiS, phiSd phiA, phiAd

tda

tnova

tda

tnova

tda

tnova

tda

tnova

b Fig. 5.26 Phase generator: a schematic and b phase-time diagram

connected in parallel. For instance, for a 240 fF load capacitance three inverters will be connected in parallel. The load capacitance per clock phase and the number of inverters used for a proper fan-out are summarized in Table 5.16.

5.4.4.3

Electrical-Level Verification

Once the phase generator and the clock-tree distribution circuit have been designed, the electrical-level verification is carried out. A specific delay and non-overlapping

134

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Fig. 5.27 Clock-tree distribution circuit

x8 x4 x8 x2 x8 x4 x8 iphi

ophi

x1 x8 x4 x8 x2 x8 x4 x8

Table 5.16 Load capacitances and number of last level inverters per clock phase Parameter

phiS phiSn phiSd phiSdn phiA phiAn phiAd phiAdn

Load cap. (fF) 378 Number of ×8 inverters in par. 5

467 6

193 3

485 7

247 3

524 7

335 5

650 8

time must be guaranteed on all corners. In addition, clock phases must be synchronized and balanced. The simulations are based on transient analysis considering the load capacitances in Table 5.16 and an external clock signal with a 50% duty cycle and rising and falling times of 500 ps. A jitter analysis of the clock phase, which controls the sampling of the input signal converter, has also been carried out. This clock jitter is expressed in terms of standard deviation (σclk ), that is to say, the sampling instant will be affected by an uncertainty time (εclk ) which is modelled by a normal distribution of zero mean and a standard deviation σclk . The simulation results are summarized in Table 5.17. As can be observed, the time available for the decision time in the comparators, which is the sum of the delay time t ds and the nonoverlapping time t nova , is higher than the comparator decision times in Table 5.13 on all corners.

5.4.5

Reference Voltage Generator

In order to increase the chip functionality and reduce the external components, we decided to implement an on-chip reference voltage generator which provides the reference voltages required for the sub-ADCs and MDACs.

5.4 Electrical-Level Design: Detailed Description

135

Table 5.17 Clock-phase generator simulation results Parameter

Corner

phiS-phiSd t ds (ps) phiA-phiAd t da (ps) phiSd-phiAd t nova (ps) phiAd-phiSd tnovs (ps) phiS-phiSd rising time (ps) phiS-phiSd falling time (ps) phiA-phiAd rising time (ps) phiA-phiAd falling time (ps) Available time for comp. (ps) σclk (fs) Dynamic power (mW)

Typical

Fast

Slow

WONE

WZERO

321 342 323 327 65 51 69 45 648 320 0.77

231 245 233 235 47 37 49 33 466 319 0.95

457 487 460 467 91 71 96 63 924 320 0.61

394 420 400 405 83 62 88 56 799 327 0.68

390 414 390 396 76 63 80 56 786 301 0.67

– Cu

Reference generator

φs

φa

Cu

...

... φs

φa φs

Cu

φs

φs +

φs

voltage Vref φa Vref Δ

Fig. 5.28 Dynamic loading effect of SC circuits

Designing the reference voltage generator is no mean task since the voltage provided is continuously affected by the switching activity inherent to SC circuits. In fact, the SC circuits present a dynamic loading effect which is described in Fig. 5.28, where the reference voltage provided is connected to an MDAC circuit. During the amplification phase, a specific number of SC branches are connected to the reference voltage. The number of SC branches connected depends on the output bits from the switch encoder, which in turn, depend on the input voltage. Therefore, the load

136

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Fig. 5.29 Buffer amplifier-based reference voltage generator

Vbref +

Vo φ

– C1

C2

capacitance connected to the voltage reference is variable and depends on the input voltage. Hence, this issue is interpreted as a dynamic loading effect. Thus, due to the charge conservation principle a voltage drop is induced on the voltage reference when an SC branch is connected. The greater the number of SC branches connected, the greater the voltage drop on the reference voltage. If the reference voltage generator is not able to restore the voltage reference before the end of the amplification phase, an error appears. Again, this error depends on the number of SC branches connected which in turn depend on the input voltage. As a result, an irreparable distortion is introduced to the signal being converted. One approach to implementing the reference voltage generator is to use a sufficiently fast buffer amplifier like that shown in Fig. 5.29. Capacitor C 1 and C 2 stand for a parasitic capacitance and an equivalent switched capacitance on the internal reference voltage. Modelling the reference buffer response with a single dominant pole and assuming a voltage drop due to the switching, , the transient evolution of the reference voltage is given by the next expression: Vo (t) = Vref − e

m − (C g+C )t 1

(5.18)

2

The error voltage induced at the end of the amplification phase becomes: ε(Ts /2) = Vo (Ts /2) − Vref = e

m − (C g+C 1

Ts 2) 2

(5.19)

where T s is the sampling period. If an error voltage lower than LSB/2 is desired, the required transconductance must verify the following condition:     2 LSB  (5.20) gm > (C1 + C2 ) ln Ts 2  For high-speed and high-resolution circuits, the transconductance required is excessive and is only achieved with a considerable amount of power dissipation. A second approach that is substantially independent from the dynamic loading effect consists in using a huge external capacitance to reduce the voltage drops () and reducing the output impedance of the buffer amplifier to avoid static errors as shown in Fig. 5.30. The amplifier transconductance, gm , dominates the output impedance of the reference buffer at low frequencies. In fact, its output impedance is the inverse of the transconductance at DC. In order to ensure circuit stability, a load capacitance C L is usually required. In addition, the load capacitance contributes

5.4 Electrical-Level Design: Detailed Description Fig. 5.30 Buffer amplifier based on the output impedance reduction

Vbref

137

+ Vo

gm

φ

– CL

Csw

to a decrease in the output impedance at high frequencies and a reduction of the voltage drops. A practical implementation of this approach is illustrated in Fig. 5.31 [74], where the amplifier is employed to boost the transconductance of transistor M 1 . Thus, the overall transconductance of the transconductance amplifier is: Gm = Ao gm1

(5.21)

where Ao is the amplifier gain and gm1 is the transconductance of the transistor M 1 . Thus, at low frequencies, the output impedance is related to the inverse of the overall transconductance, 1/(Ao gm1 ), and at higher frequencies it is dominated by the load capacitor C L . However, this circuit presents some drawbacks. Firstly, the amplifier gain can significantly vary with the corners. In addition, a high gain is required to reduce the output impedance. This can be achieved by using multistage amplifiers, which can reduce circuit stability, or with a considerable amount of power dissipation. To overcome these problems, we adopted the solution proposed in [135]. A block diagram implementation is shown in Fig. 5.32. As can be inferred, this is based on

Ibias Vo

– M1

Ao Vbref

+

Fig. 5.31 Practical implementation of the buffer amplifier in Fig. 5.30

Vbref

+

A1

...

An

CL

gm

k1

–

Fig. 5.32 Block diagram of the buffer amplifier proposed in [135]

...

kn

Vo CL

138

5 Case Study: Design of a 10bit@60MS Pipeline ADC

the output impedance reduction approach and consists of a cascade of gain stages, followed by a transconductance amplifier and a cascade of current mirror amplifiers. Thus, the overall transconductance is given by: Gm = (A1 · . . . · An ) · gm · (k1 · . . . · kn )

(5.22)

A large load capacitance C L provides stability, reduces the output impedance at high frequencies and reduces the voltage drops on the reference voltages. In addition, the parasitic poles of the gain amplifiers can easily be designed at high frequencies, so the compensation is relatively simple (a large load capacitance). The following subsections are devoted to describing the reference voltage generator implementation. Firstly, the requirements or high-level specifications are will be extracted. Following this, a description of the electrical-level design will be given. Finally, the simulation results will be presented.

5.4.5.1

Requirements for the Reference Voltage Generator

As shown before, a reference voltage generator must provide a low output impedance. In order to obtain the maximum permissible value for the output impedance, we should consider the schematic in Fig. 5.30, where a transconductance amplifier provides the reference voltage to a switched capacitance C SW . This capacitance, which is switching at T s /2, can be modelled as an equivalent impedance given by: ZSW =

1 fs CSW

(5.23)

Therefore, assuming an ideal model for the transconductance amplifier: vo Gm Zsw − Gm (Vbref − vo ) = 0 ⇒ vo = Vbref Zsw 1 + Gm Zsw

(5.24)

From Eq. (5.24), an error voltage on the reference voltage can be deduced: εref = Vbref − vo =

1 Vbref 1 + Gm Zsw

(5.25)

If an error voltage lower than the converter LSB/2 is required: εref |max <

LSB 2

⇒

Vbref 1 Vbref < N 1 + Gm /Zsw 2

(5.26)

where N is the number of bits of the converter. A minimum value for the transconductance (Gm |min ) can be extracted from Eq. (5.26): Gm |min =

2N − 1 = (2N − 1)fs Csw Zsw

(5.27)

5.4 Electrical-Level Design: Detailed Description Fig. 5.33 Converter-effective resolution against the noisePSD of the ref. voltages

139

9.5 9

ENOB(bits)

8.5 8 7.5 7 6.5 6 5.5 5 10–18

10–14 10–16 Voltage reference noise PSD (V/√Hz)

10–12

The output impedance of the transconductance amplifier in Fig. 5.30 is the inverse of the transconductance. Therefore, the maximum value for the output impedance is obtained as follows: Zout =

1 Gm|min

=

(2N

1 − 1)fS Csw

(5.28)

Equation (5.27) provides the first requirement for the transconductance amplifier. The second requirement is related to the thermal noise. Note that the reference voltage is sampled by the MDACs during the amplification phase. There is therefore a thermal noise contribution at the output voltage of the MDAC. A set of behavioural simulations were carried out in order to obtain the maximum thermal noise permissible in the reference voltage. Figure 5.33 shows the behavioural simulation results. From this, a maximum noise PSD of 0.2 fV2 /Hz was obtained, so the in-band integrated noise had to be lower than 12 nV2 . As final requirements, a low settling time must be guaranteed and power consumption must be minimized. 5.4.5.2

Electrical-Level Implementation

Figure 5.34 illustrates a simplified schematic of the reference-voltage generator implementation. According to this implementation, the differential reference voltage at DC can be obtained as follows: Vref = Vrefp − Vref n =

Gm R22 Vbref R1 + R 2 + G m R 1 R2

(5.29)

where Gm is the overall transconductance of the transconductance amplifier. Assuming that Gm R1 R2  R1 + R2 : Vref ≈

R2 Vbref R1

(5.30)

5 Case Study: Design of a 10bit@60MS Pipeline ADC

R2 R1

–

+

Damping network

Transc. amplifier

+ Vbref

Lb

Vrefp

–

Rsub–ADCs Csw

R1

R2

Package

140

Cext

Lb

Vrefn

Chip

External

Fig. 5.34 Simplified schematic of the proposed reference voltage generator

The resistors R2 and R1 are selected to be 45 k and 20 k respectively. Note that relatively high values are required in order to satisfy the relation Gm R1 R2  R1 + R2 . According to these values, the ratio R2 /R1 is 2.5 so the external reference voltage must be around 175 mV to properly generate a differential reference voltage (V ref ) of 400 mV. This differential voltage reference is provided to the MDACs represented by a total switched capacitance C sw , and the resistor ladders of the sub-ADCs represented by a total resistance Rsub-ADCs . The external capacitor C ext has a double purpose. On the one hand, it is used as a large charge reservoir for charging and discharging the switched capacitor C sw . Since it has a large value, the transconductance amplifier does not have to supply this charge in each cycle, but merely maintain an average voltage on the external capacitor. Therefore, the OTA can be very slow. On the other hand, it is also used to compensate the transconductance amplifier. However, since this capacitor is external, the instantaneous current glitches supplied by the capacitor flow through the parasitic inductances of the bonding package, causing considerable oscillations on the reference voltages which ought to be reduced. For this purpose, a damping network has been implemented. Let us explain each building block in detail.

Transconductance Amplifier Figure 5.35 shows a block diagram of the OTA. It consists of two gain stages (A1 , A2 ) followed by a transconductance amplifier (gm ) and a current-gain amplifier (k 1 ). Thus, the overall transconductance amplifier is given by: Gm = A1 A2 gm k1

Fig. 5.35 Block diagram of the transconductance amplifier

vip vin

+ – A1 – +

+ – A2 – +

(5.31)

+ gm –

+ k1 –

vop von

5.4 Electrical-Level Design: Detailed Description

141

The aim of the gain stages and the current-gain amplifier is to boost the overall transconductance amplifier and, accordingly, to decrease the output impedance. Assuming a converter resolution of N = 10 bits, a total switched capacitance of C sw = 3 pF and a sampling rate of 60 MHz, the maximum value permissible for the output impedance is given by Eq. (5.27): Zo |max =

(2N

1 = 5.43  − 1)fs Csw

(5.32)

In addition, the output impedance at the reference voltages in Fig. 5.34 can be approximated at DC as follows: Zo =

1 + R2 /R1 1 + R2 /R1 = Gm A 1 A 2 g m k1

(5.33)

Therefore, the gains A1 , A2 and k 1 must be maximized so that the value in Eq. (5.32) is not exceeded. Low noise and power consumption is also desired. To satisfy these requirements, the architecture illustrated in Fig. 5.36a has been employed for the gain stages. This includes positive feedback in order to decrease the output impedance and, accordingly, increase the gain. A series structure of MOS transistors has also been used to increase the effective length. Moreover, the single OTA in Fig. 5.36b has been used as a transconductance amplifier. The simulation results are summarized in Table 5.18. The structure in Fig. 5.37 has been employed as a current gain amplifier [135]. It consists of two current mirrors, the first of which is formed by PMOS transistors M 2 , M 4 and M 6 , and the second by NMOS transistors M 1 , M 3 and M 5 . Note that the sub-ADC equivalent resistor is equal to: Rsub−ADCs =

vip

NR Ru 16 · 150 = = 480 nstg 5

vin

25μA von

25μA

vip

(5.34)

vin

vop vo

a

b

Fig. 5.36 Schematics of the: a gain stage and b transconductance amplifier

142

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Table 5.18 Simulation results of the gain stages and transconductance amplifier Block

Parameter

Corner Typical

Fast

Slow

WONE

WZERO

1st gain stage

Gain Transcond. (mA/V) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) Power cons. (mW)

58.8 4.77 144 88.0 2.95 0.71

62.8 5.91 174 88 2.43 0.80

51.1 4.13 125 88.2 3.39 0.63

50.4 4.21 118 88.4 3.37 0.62

32.5 4.39 138 88.8 3.20 0.64

2nd gain stage

Gain Transcond. (mA/V) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) Power cons. (mW)

61.6 0.48 15.9 90.7 9.33 0.09

63.6 0.60 18.7 90.6 7.68 0.10

60.2 0.42 13.9 90.7 10.7 0.08

50.3 0.42 12.9 91.0 10.69 0.08

55.0 0.45 15.4 90.8 9.94 0.08

Transcond. amplifier

Gain Transcond. (mA/V) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) Power cons. (mW)

19.7 1.42 1497 55.9 5.4 0.30

21.0 1.85 1940 54.5 4.3 0.36

18.4 1.19 1226 57.2 6.3 0.27

16.2 1.25 1272 57.8 6.2 0.26

14.8 1.29 1332 58.0 5.9 0.26

M6

M4

M2

833μA

10k

vop +

10k

480Ω

–

von

vi

M1

M3

M5

vcmref

833μA

Fig. 5.37 Current amplifier schematic

where nstg is the number of stages of the pipeline converter. Therefore, a specific output current must be provided by the current-gain amplifier to generate a differential reference voltage around 400 mV. This output current can be obtained as follows: io =

Vref 400mV = ≈ 833μA Rsub−ADCs 480

(5.35)

5.4 Electrical-Level Design: Detailed Description

143

As can be appreciated from Fig. 5.37, the reference voltage common mode is obtained from a resistive divider. A simple OTA is used to feedback this common-mode voltage.

Damping Network As explained above, the reference voltages generated are provided to the MDACs. During the amplification phase, the MDAC SC branches can be connected to the reference voltages depending on the switch encoder output bits. When an SC branch is connected, a charge redistribution is instantaneously induced so that the total charge is conserved. These instantaneous charge requirements are provided by the external capacitor by means of current glitches which cause voltage oscillations when flowing through the parasitic inductances of the package. A damping network is introduced to mitigate such voltage oscillations. Figure 5.38 shows the schematic of the RC damping network implemented. The resistor and capacitor values have been obtained by means of transient simulations to minimize settling time. For illustration purposes, Fig. 5.39 shows a transient evolution of the reference voltages both when the RC damping network is considered or and when it is not.

5.4.5.3

Electrical-Level Verification

Once the basic building blocks have been designed, the high-level specifications must be verified. To do so, the circuit in Fig. 5.40 has been considered. A parasitic Vrefp

Fig. 5.38 RC damping network implemented

25Ω

25Ω

20pF

20pF

25Ω

25Ω

Vrefn

5 Case Study: Design of a 10bit@60MS Pipeline ADC

0.6

0.6

0.5

0.5 Δ Vref (V)

Δ Vref (V)

144

0.4 0.3

0.4 0.3

0.2

0.2

0.1

0.1 10

a

20 t(ns)

30

40

10

b

20 t(ns)

30

40

Fig. 5.39 Transient evolution of the reference voltage: a with and b without damping network

Csw = 3pF

45k

Lb = 1nH

Vrefp

50mΩ

20k

–

+

Transc. amplifier

+ Vbref

20k

–

Fig.5.35

45k

Damping network

Rsub – ADCs = 480Ω

Fig.5.37

22uF

1.1nH

Vrefn

Lb = 1nH

Csw = 3pF

Fig. 5.40 Circuit considered for the verification of the reference voltage generator

inductance L b = 1nH has been assumed. An equivalent model for the external capacitor including parasitics, a 3 pF switched capacitor, and a 480  sub-ADC resistor has also been considered. We should remember that the requirements for the reference voltage generator are: (a) An output impedance lower than 5.43 . (b) An integrated power noise lower than 12 nV2 . (c) A fast settling time. The simulation results are summarized in Table 5.19. As can be inferred, the highlevel specifications are fully satisfied. The power consumption on the worst corner is around 2 mW.

5.4 Electrical-Level Design: Detailed Description

145

Table 5.19 Reference voltage generator simulation results Parameter

Corner

Vref (mV) Zo (DC) () Zo (60MHz) () Zo (120MHz) () Pno (nV2 ) Settling time (ns) Power cons. (mW)

5.4.6

Typical

Fast

Slow

WorstONE

WorstZERO

401.9 0.11 1.19 2.43 8.05 0.62 1.65

394.7 0.05 1.20 2.45 6.80 0.82 2.02

390.3 0.20 1.19 2.41 9.22 0.79 1.25

402.8 0.20 1.19 2.43 9.07 0.65 1.33

404.5 0.32 1.19 2.43 8.17 0.66 1.33

Common-Mode Voltage Generator

Two common-mode voltages are required for the proper operation of the differential amplifiers in the pipeline converter: VCMo1 and VCMo2 . The former is used to control the common-mode voltage at the first-stage outputs of the amplifiers whereas the latter controls the common-mode voltage at the amplifier inputs and outputs. Depending on the amplifier topology used in the pipeline converter (Fig. 5.5) and the voltage supply available (1.2 V), values of 575 and 725 mV have been considered suitable for the VCMo1 and VCMo2 voltages respectively. A converter inspection allowed us to identify a total switched capacitance of 750 F and 3 pF for the first and second common-mode voltages respectively. An approach based on a fast-settling buffer amplifier will be implemented since the switched capacitance for the first common-mode voltage is relatively low. On the other hand, an approach based on a low-output impedance transconductance amplifier will be selected for generating the second common-mode voltage. Let us consider both circuits separately. 5.4.6.1

First Common-Mode Voltage Generator

Figure 5.41a shows a simplified schematic of the first common-mode voltage generator. This consists of a resistor ladder to obtain the reference voltage, and a buffer amplifier to provide fast settling when the common-mode voltage is distorted by the glitches from the switching activity. The buffer amplifier has been implemented using a two-stage MC topology. A detailed schematic is shown in Fig. 5.41b. A resistor in series with the compensation capacitor has been incorporated to improve the performance of the amplifier. Series structure for the MOS transistors have been used to increase the effective length and consequently increase the gain amplifier. Simulation results for the buffer amplifier are summarized in Table 5.20. 5.4.6.2

Second Common-Mode Voltage Generator

Figure 5.42a illustrates a simplified schematic of the second common-mode voltage generator. As explained above, this is based on a low-output impedance buffer

146

5 Case Study: Design of a 10bit@60MS Pipeline ADC

vin

vip

– VCMo1

vo

vo

+

Csw = 750fF

a

b

Fig. 5.41 First common-mode voltage generator: a simplified schematic and b buffer amplifier Table 5.20 Buffer amplifier simulation results Parameter Gain (dB) 1stg stage trans. (mA/V) 2snd stage trans (mA/V) Comp. capacitor (pF) Comp. resistor (k) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) Power cons. (mW)

Corner Typical

Fast

Slow

WONE

WZERO

89 0.83 2.66

94 1.06 3.47

79 0.72 2.35

85 0.77 2.27

24 85 22 0.62

30 91 16 0.70

83 0.71 2.17 4.25 1 20 83 28 0.55

18 82 30 0.55

24 78 25 0.55

approach which is externally compensated. Thus, a damping network will again be required to avoid the voltage oscillations caused by the parasitic inductances. For simplicity’s sake, the damping network in Fig. 5.38 will be used again. Like the first common-mode voltage generator, the reference common-mode voltage is obtained from a resistor ladder. In fact, the same resistor ladder is used. The transconductance amplifier is once again implemented using a multistage approach. A block diagram of the implemented transconductance amplifier, which consists of two gain stages followed by a transconductance amplifier, is shown in Fig. 5.42b. In addition, the topologies in Fig. 5.36 have been reused for the implementation of the gain stages and the transconductance amplifier. The simulation results of these building blocks are summarized in Table 5.21. Note that the requirements for these common-mode voltages are significantly more relaxed than those for the reference voltages since an error voltage lower than the converter LSB/2 is not required.

5.4 Electrical-Level Design: Detailed Description

147

–

VCMo2

Lb

vo

Transc. amplifier +

Damping network

Cext

Csw = 3pF

a

+ –

–

+

+

–

–

+

+

b

–

Fig. 5.42 Second common-mode voltage generator: a schematic and b detail of the transconductance amplifier

Table 5.21 Simulation results of the gain stages and transconductance amplifier Block

Parameter

Corner Typical

Fast

Slow

WONE

WZERO

1st gain stage

Gain Transcond. (mA/V) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) Power cons. (mW)

83 0.62 20.8 90 7.6 0.11

87 0.77 24.4 90 6.2 0.13

68 0.51 17.3 90 9.0 0.10

74 0.52 15.9 90 9.0 0.10

54 0.58 19.6 91 8.2 0.11

2nd gain stage

Gain Transcond. (mA/V) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) Power cons. (mW)

72 0.65 21.4 90 7.6 0.12

74 0.82 25.4 90 6.2 0.14

76 0.49 16.4 90 9.1 0.10

66 0.56 17.1 91 8.9 0.10

63 0.58 19.6 91 8.2 0.10

Transcond. amplifier

Gain Transcond. (mA/V) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) Power cons. (mW)

23 1.03 1053 70 6.6 0.24

25 1.27 1312 69 5.3 0.27

19 0.87 883 71 7.9 0.22

20 0.93 931 71 7.5 0.22

20 0.89 919 71 7.6 0.22

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

Table 5.22 Common-mode voltage generator simulation results Parameter

Corner Typical

Fast

Slow

WONE

WZERO

1st commonmode volt. gen.

VCMo1 (mV) Settling time (ns)

575 0.74

633 0.51

517 1.03

517 0.98

517 1.06

2nd commonmode volt. gen.

Z o (DC) () Z o (60 MHz) () Z o (120 MHz) () Pno (nV2 ) Settling time (ns) Power cons. (mW)

0.63 1.2 2.4 3.4 0.45 1.08

0.47 1.2 2.4 2.8 0.44 1.22

0.87 1.2 2.4 3.9 0.47 0.94

0.86 1.2 2.4 3.8 0.47 0.95

1.25 1.2 2.4 3.6 0.47 0.96

5.4.6.3

Electrical-Level Verification

An scheme analogous to that in Fig. 5.40 has been used for the verification of the common-mode voltage generator. Thus, a parasitic inductance of 1 nH and an equivalent model for the external capacitance were assumed. The simulation results are summarized in Table 5.22.

5.4.7

Reference Current Generator

Most basic building blocks in the pipeline converter require reference currents to generate the biasing voltages properly. For instance, the operational amplifiers of the MDACs require two 50 μA current references while the preamplifiers in comparators require a 25 μA current reference. These reference currents must be independent from the technological and environmental corners. The current conveyor in Fig. 5.43 has been implemented [1] to provide these reference currents. It consists of an amplifier which boosts an NMOS transistor to induce a specific current through the external resistor. If it is assumed that the operational amplifier has a high gain, the input voltages must be practically identical, that is: vip = vin = Vbmas

(5.36)

Therefore, the current which flows through the external resistor will be given by: iRext = Vbmas /Rext

(5.37)

This output current is independent from the internal voltage supply. In fact, if external voltage and resistor keep their values the current reference is practically independent from the corners. The output current is replicated and scaled by the current mirrors at the top in order to generate the required 50 and 25 μA current references. The amplifier has been implemented by using the topology in Fig. 5.41b, with the exception that it has been self-biased by means of a resistor ladder from the voltage

5.5 Converter Electrical-Level Verification

149

... Vbmas + I50μA

I50μA

I25μA

I25μA

–

Iref

Rext

Fig. 5.43 Implemented current conveyor

Table 5.23 Current-conveyor simulation results Parameter Gain (dB) 1stg stage trans. (mA/V) 2snd stage trans (mA/V) Comp. capacitor (pF) Comp. resistor (k) GBW (MHz) PH (◦ ) Input-referred noise (nV2 ) I ref (μA) Power cons. (mW)

Corner Typical

Fast

Slow

WONE

WZERO

90.5 1.03 2.94

92.4 1.80 4.75

81.8 0.63 2.02

82.7 1.02 2.72

101 57.4 16.1 172.9 0.78

165 56.3 9.8 169.3 1.31

88.9 0.63 1.93 1.25 3 63 73.9 24.5 168.7 0.45

53 79.5 26.3 173.1 0.44

92 61.7 18.6 174.9 0.79

supply. An external resistor of 1 k and an external voltage about 175 mV have been selected to provide a current reference of about 175 μA. The simulation results are summarized in Table 5.23, where a deviation of the current reference lower than 4% is appreciated.

5.5

Converter Electrical-Level Verification

The transistor-level synthesis of the pipeline converter was discussed in Sects. 5.2 and 5.3. There, the effective resolution achieved was obtained by considering the transistor-level implementation of the MDAC circuits and ideal sub-ADC and auxiliary blocks (see Tables 5.5 and 5.9).

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

The electrical-level design of the sub-ADC and auxiliary blocks of the pipeline converter was discussed in the last section. Moreover, an individual characterization of these basic building blocks was carried out. However, the influence on the performance of the overall pipeline converter was not checked. In this section we aim to present the converter’s effective resolution considering the transistor-level implementation of all building blocks. For this purpose, a similar procedure to those showcased in Fig. 5.6b will be followed but at this point the jitter-noise contribution will also be taken into consideration. Thus, the effective number of bits of the pipeline converter can be computed as follows:   2 Vref 1 ENOB = log2 (5.38) j it 2 3(Pnth + PjS&D + Pn ) j it

where Pn is the jitter-noise power and can be calculated from Eq. (1.7). The transistor-level implementation of the basic building blocks will be considered gradually. From this it is possible to observe the influence of the corresponding block on the converter performance. A notable degradation of the converter resolution would mean that the high-level specifications for the corresponding building block were not correctly obtained. If the converter resolution is kept, the corresponding building block is validated. In order to evaluate the static and dynamic errors, a transient analysis is run considering a Nyquist frequency input signal. An FFT analysis is then carried out from 256 output samples and the ENOBS&D extracted. The simulation results are summarized in Table 5.24. As can be inferred, the converter resolution is not degraded, so all basic building blocks are validated. Note that the final resolutions considering the transistor-level implementation of all basic building blocks are slightly higher than those obtained when only the transistor-level implementation of the MDACs is considered. There are two main reasons for this: • On the one hand, when an ideal clock-phase generator is considered, a delay and non-overlapping times, and rising and falling times of 400 and 200 ps are assumed respectively. As can be seen in Table 5.17, the values obtained with the transistorlevel implementation are slightly lower than those ideally assumed. Therefore, the times available during the sampling and amplification phases are increased. Table 5.24 Converter ENOBS&D on the technological corners MDACs     

SubADCs

Ref. Volt. gen.

Ref. Cur. gen.

Clock gen.



 

  

   

   

  

 Transistor-level circuit 

Ideal circuit

 



Corner Typical

Fast

Slow

WONE

WZERO

10.58 10.63 10.55 10.55 10.68

10.51 10.51 10.16 10.24 10.65

9.36 9.84 9.88 9.88 9.94

10.44 10.26 10.21 10.20 10.56

9.84 10.22 10.25 10.14 10.56

5.6 Layout

151

Table 5.25 Simulation results of the pipeline converter considering the transistor-level implementation of all basic building blocks Metric

Corner

S&D

ENOB (bits) PS&D (nV2 ) Pnth (nV2 ) j it Pn (30MHz) (nV2 ) ENOB (bits)

Typical

Fast

Slow

WorstONE

WorstZERO

10.68 19.9 19.4 0.58 10.2

10.65 20.7 15.8 0.58 10.2

9.94 55.5 23.5 0.58 9.68

10.56 23.3 22.2 0.61 10.1

10.56 23.6 22.9 0.52 10.1

Fig. 5.44 Montecarlo analysis of the pipeline converter under typical conditions

8 7

Frequency

6 5 4 3 2 1 0 10.05

10.1

10.15 10.2 10.25 Effective resolution (bits)

10.3

• On the other hand, when the ideal implementations are considered, worst cases for the load capacitances are considered. Finally, the effective resolution must be computed using the thermal and jitter-noise contributions according to Eq. (5.38). The results are detailed in Table 5.25. In order to conclude the design verification, a Montecarlo analysis was carried out to evaluate the influence of mismatch errors. In this case, typical conditions have been considered. The transistor-level implementation of all the basic building blocks was taken into account. The simulation results are depicted in Fig. 5.44, from where a 10.19 effective resolution mean and 0.04-bit standard deviation can be deduced. Therefore, the design is fully verified and the high-level specifications fully satisfied.

5.6

Layout

Once the basic building blocks have been designed and verified at electrical level, the layout converter must be initiated. This task must be carried out carefully since the substrate is conductive. Besides, special attention must be paid to the parasitics which can noticeably degrade the performance of the ADC.

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

Fig. 5.45 Pipeline converter floor planning

Digital REF. VOLT. GEN.

SUBADC

SUBADC

SUBADC

SUBADC

SUBADC

SH

MDAC1

MDAC2

MDAC3

MDAC4

REF. CUR. GEN.

CLK GENERATOR

Analog

The overall ADC floor planning is illustrated in Fig. 5.45, where the basic building blocks have been distributed from top to bottom according to their sensitivity to substrate noise. Thus, the digital circuits, such as the clock-phase generator, are placed on the top; whereas the most sensitive circuits, such as the MDACs and SH, are placed on the bottom. Mixed-signal circuits, such as sub-ADCs, are placed in the middle. The aim is to place the most sensitive parts far away from the noisy digital circuits and reduce the coupling noise from the substrate. The following subsections will be dedicated to detailing the layout of the basic building blocks and discussing the layout techniques adopted to improve ADC performance.

5.6.1

SH Layout

Figure 5.46 shows the layout view of the SH, together with a diagram block of its building blocks. The SH layout occupies about 185 × 570 μm in the 0.13 μm and 6-metal technology. The following layout considerations have been taken into account: • As in the ADC floor planning, the building blocks have been distributed from top to bottom according to their sensitivity to substrate noise. • Separate power supplies are considered for the analog and mixed-signal parts. The analog part consists of the OTA and unitary and compensation capacitors, whereas the mixed-signal part covers the remaining blocks (see colour legend in Fig. 5.46). • Dummy transistors and dummy capacitors have been used to reduce the silicon stress effects in MOS transistors and capacitors respectively. • Deep nwells have been employed to isolate blocks from the substrate noise. • Power-supply lines and reference voltages are horizontally distributed along the ADC layout, whereas interconnecting lines between components of the SH circuit are vertically distributed. Special attention has been paid to the lines which connect the OTA input and output nodes in order to reduce coupling parasitics with other

5.6 Layout

153

Fig. 5.46 SH: a layout and b basic diagram block

interconnecting lines. Digital and analog interconnecting lines have been placed on the left- and right-hand sides of the SH layout respectively. • No centroid-common structures have been applied to capacitor array since the routing asymmetries caused a considerable mismatch between capacitors.

5.6.2

MDAC Layout

Figure 5.47 shows the layout view of the first MDAC together with a diagram block of its building blocks. The MDAC layout occupies about 240 × 535 μm in the 0.13 μm

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

Mix-signal Analogue Digital interconnecting lines References volt. lines

... SWITCHES

Vrefp Vrefn VCMo2

Analog interconnecting lines

VCMo1 MVDD

535um

CMFB circuit Power supply lines

...

MVSS

Unitary capacitors

Comp. capacitor Deep nwells

AVDD OTA

...

AVSS

a

240um

b

Fig. 5.47 First MDAC: a layout and b basic diagram block

and 6-metal technology. The same layout considerations described above have been taken into account. The remaining MDACs keep an analog layout distribution and have been placed on adjacent columns as shown in Fig. 5.45. Note that the MDACs are scaled along the cascade of stages in the pipeline architecture, and, therefore, the area required to implement the layout of a specific MDAC is generally lower than the MDAC in the previous stage. However, all of them retain the dimensions of the first stage (240 × 535 μm) for two main reasons: • Width dimension is kept because the sub-ADCs impose the minimum width (240 μm).

5.6 Layout

155

• Length dimension is kept since the reference voltage lines and power-supply lines are horizontally distributed and, as a consequence, the vertical dimension must be kept. In any case, the free layout areas can be used to implement decoupling capacitors to stabilize the power-supply lines.

5.6.3

Sub-ADC Layout

Figure 5.48 shows the layout view of the 3-bit sub-ADC together with a diagram block of its building blocks. The sub-ADC layout occupies about 240 × 235 μm in the 0.13 μm and 6-metal technology. Layout considerations analogous to the SH circuit have been taken into account: • The building blocks have been distributed from top to bottom according to their sensitivity to substrate noise. • Separate power supplies are considered for the digital and mixed-signal parts. The AND gates which provide the control signals for the MDAC switches during the amplification phase have been placed in the mixed-signal section.

Fig. 5.48 sub-ADC: a layout and b basic diagram block

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

• Decoupling capacitors have been included to reduce the power supply bouncing. • Dummy transistors and dummy capacitors have been used to reduce the stress effects in MOS transistors and capacitors respectively. • Deep nwells have been employed to isolate blocks from the substrate noise. • Power-supply lines are horizontally distributed, whereas interconnecting lines between components of the sub-ADC are vertically distributed. • No centroid-common structures have been applied to capacitor arrays since the routing asymmetries caused considerable mismatch between capacitors.

5.6.4

Reference Current Generator Layout

Figure 5.49 shows the layout view of the reference current generator together with a diagram block of its building blocks. The layout occupies about 240 × 255 μm, mainly due to the damping network which requires about 60% of the total silicon area. Layout considerations analogous to the SH circuit have been taken into account.

5.6.5

Reference Voltage Generator Layout

The layout view and basic diagram block of the reference voltage generator are depicted in Fig. 5.50. It occupies about 240 × 235 μm, mainly due to the damping network which requires about 70% of the total silicon area. Layout considerations analogous to the SH circuit have been taken into account. Special attention has been paid to the ground reference of the reference voltage generator. The schematic in Fig. 5.51a, where internal (V gi ) and external (V ge ) ground

DAMPING

255um

NETWORK

Resistor ladder Buffer amplifier for the generation of the VCMo1

a

240um

b

Fig. 5.49 Reference current generator: a layout and b basic diagram block

Transconductance amplifier for the generation of the VCMo2

5.6 Layout

157

Transconductance amplifier 235um

Resistors

DAMPING NETWORK

240um

a

b

Fig. 5.50 Reference voltage generator: a layout and b basic diagram block R2 Δip = (Ig

OTA

rp2

+ ip ) R

rp1

Vge rp

igR

R1 –

Vgi rp3

+

Vbref

–

Damping network

ΔVref

Damping network

ΔVref

R1 IgOTA

a

+

R2 R2

R Δip = ig

Vge

rp

Vge

rp4

rp2 rp1

igR

– +

rp3 Vbref

b

R1

+ –

R1

IgOTA

R2

Fig. 5.51 Reference voltage generator: a grouping ground references and b isolating ground references

references have been considered, explains this issue. The former stands for the inner ground reference of the reference voltage generator, whereas the latter is the off-chip external ground reference. Due to the routing, parasitic resistances (r p1 , r p2 , . . . ) appear from the grounds of different building blocks to the internal ground reference,

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

as well as from the internal to the external ground reference (r p ). Thus, the current flow (i) through the parasitic resistance r p would induce internal ground-reference voltage changes. As a result, the differential output voltage of the reference voltage generator would be given by: Vref ≈

R2 R2 (Vbref − ip rp ) = [Vbref − (IgOT A + ipR )rp ] R1 R1

(5.39)

This effect would considerably distort the reference voltages, and ADC performance would be drastically deteriorated. To overcome this problem, the internal ground reference is independently routed up to a specific pad as shown in Fig. 5.51b. This ground reference is also independently routed at PCB level. In this way, only the current from the resistor ladder, which is practically constant and negligible ipR ∼ 0 , flows through the parasitic resistance r p and the reference voltages remain unchanged, i.e.: Vref ≈

5.6.6

R2 R2 (Vbref − ip rp ) = [Vbref − ipR rp ] R1 R1

(5.40)

Clock-Phase Generator Layout

The distribution of the clock phases must be also carefully done. Note that the clock signals must be provided at numerous points of the pipeline ADC and, therefore, long paths must be used. However, these long paths introduce parasitic resistances and capacitances which can distort and delay the clock signals. This is illustrated in Fig. 5.52a, where an inverter provides a specific clock phase. The signal path is modelled by a set of parasitic RC stages. As can be deduced, the signal clock is distorted and delayed along the path due to the RC time constants introduced by the parasitics. To overcome this problem, the clock signal can be uniformly distributed along the path signal as shown in Fig. 5.52b. This idea has been applied to the distribution of the clock phases. Hence, the layout of the clock-phase distribution circuit has been spread along the total length of the pipeline ADC and vertically distributed as shown in Fig. 5.53. In this figure, the layout of the clock-phase generator is shown together with a diagram block of its building blocks. The layout occupies about 1080 × 135 μm. The empty layout areas can be used to include decoupling capacitors.

5.6.7 ADC Layout Figure 5.54 shows the pipeline converter layout. It occupies about 2080 × 1435 μm, which means about 3 mm2 . In general, the following layout considerations have been taken:

5.6 Layout

159

x8

x2

x2

x2

x2

a

b

135um

Fig. 5.52 Clock-signal distribution: a conventional and b vertically-uniform distribution

a

1080um

DVDD DVSS

Phase gen. Clock distribution circuit

b Fig. 5.53 Clock-phase generator: a layout and b basic diagram block

• Each metal is only used in a specific direction. Metals 2, 4 and 6 are used in a vertical direction, whereas Metals 3 and 5 are employed in a horizontal direction. • Multiple routes have been used for inter-metal connections. • Recommended rules for manufacturability have been followed as DRC rules to increase yield. • Dummy transistors and dummy capacitors have been used to reduce the stress effects in MOS transistors and capacitors respectively. • Deep nwells have been employed to isolate blocks from the substrate noise.

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

Fig. 5.54 Pipeline converter layout

• Separate power supplies have been considered for the analog, mixed-signal and digital parts. • The routing of analog and digital signals has been separated as much as possible to reduce the coupling between them. • Pads with deep nwells have been used in order to reduce the current leakage to the pipeline converter. • Clean and separate power supplies have been used to bias the deep nwells and substrate circuit. • Numerous decoupling capacitors have been included in free layout areas.

5.7

Post-Layout Verification

Once the layout of the basic building blocks has been concluded, the electricallevel performance must be newly evaluated taking the parasitics from the layout into account. These parasitics become more important (1) in submicron technologies, where the distance between metals can be greatly reduced, increasing the coupling capacitances and (2) in low-power and high-speed applications, where there is a trend to reduce the nominal values for sampling capacitors to achieve a higher speed, giving rise to parasitic capacitances comparable with these nominal values. Let us evaluate the influence of parasitics in each building block separately.

5.7 Post-Layout Verification

5.7.1

161

SH & MDAC Post-Layout Verification

Parasitics play a role which is very relevant in the SH and MDAC circuits since, to a large extent, they can determine the values for the feedback factors and equivalent loads. In fact, there are some critical nodes where the parasitics can notably degrade the performance of the ADC. For instance, the input and output nodes of the amplifiers in the SH and MDAC circuits are very sensitive to parasitics. As a first approximation, we assumed parasitic capacitances of 300 and 400 fF for the input- and output-node amplifiers respectively, when the synthesis procedure was carried out. However, the post-layout extractions led to the parasitic capacitances in Table 5.26. These new values, not very close to our estimations, can modify the amplifier equivalent loads and damping factors considerably. As a result, a degradation of the converter performance is expected. In order to confirm this assumption, a transient analysis was carried out taking into account the post-layout parasitics in the SH and MDAC circuits. The remaining building blocks, such as sub-ADCs, reference-voltage generator, clock-phase generator or the reference current generator were assumed to be ideal. The simulation results are summarized in Table 5.27 for the different corners. As can be inferred, the converter performance has been clearly degraded. To overcome this problem, a new synthesis procedure was carried out taking the post-layout parasitics in Table 5.26 into account. Only the OTAs were modified in this synthesis procedure. The remaining parameters, such as unitary capacitors or the overdrive voltages, were maintained. Note that the post-layout parasitics in Table 5.26 are slightly lower than those initially estimated, so the new synthesis procedure should lead us to a lower power consumption design. However, we decided to reduce the time constants in order to maintain power consumption. The idea was to oversize the amplifiers in order to increase their robustness against the influence of parasitics. The synthesis results are summarized in Table 5.28. As can be observed, the total power consumption was practically maintained at about 19 mW. As shown in Sect. 5.3, we are interested in obtaining the values for the OTAcompensation capacitors such as the stage performance, ensuring they are optimized Table 5.26 Post-layout parasitic capacitances at the input and output nodes of amplifiers

Stage

Cpj (fF)

Co1j (fF)

Co2j (fF)

SH MDAC1 MDAC2 MDAC3 MDAC4

175 150 150 125 125

300 250 250 200 200

450 400 350 350 300

Table 5.27 Simulation results of the pipeline converter considering post-layout parasitics in MDACs Metric ENOBS&D (bits)

Corner Typical

Fast

Slow

WorstONE

WorstZERO

10.84

9.76

8.09

10.28

9.92

Table 5.28 Synthesis results for the 5-stage 3-3-3-3-2 pipeline ADC taking into account the post-layout parasitics

162 5 Case Study: Design of a 10bit@60MS Pipeline ADC

5.7 Post-Layout Verification

163

on the technological corners before and after optimizing the compensation Table 5.29 ENOBS&D j capacitor Stage

Comp. cap. (PF)

SH Stage 1 Stage 2 Stage 3 Stage 4

1.9 → 2.2 0.9 → 1.2 0.65 → 0.75 0.4 → 0.4 0.4 → 0.35

Corner ENOB Typical

Fast

Slow

WorstONE

WorstZERO

12.39 → 11.06 12.39 → 12.52 10.39 → 10.89 9.34 → 9.34 8.75 → 8.42

13.08 → 13.35 11.98 → 11.45 11.18 → 11.09 9.54 → 9.54 9.65 → 8.98

9.29 → 11.52 9.21 → 10.77 8.74 → 10.61 8.01 → 8.01 6.44 → 8.28

10.56 → 10.68 11.61 → 10.54 9.88 → 11.44 8.76 → 8.76 7.14 → 10.20

11.08 → 10.08 11.08 → 11.67 9.89 → 9.99 8.52 → 8.52 9.48 → 7.66

over the technological and environmental corners. For this purpose, a set of parametric analyses were carried out over each stage taking the compensation capacitor as running variable. The optimum values for the compensation capacitors are summarized in Table 5.29, which also illustrates the ENOBS&D before and after the optimization. New layouts of the amplifiers and compensation capacitors were carried out, taking the sizing results in Table 5.28 into account. The parasitics were subsequently extracted from the new layout and the electrical-level performance was checked following the verification procedure in Fig. 5.6. Two parasitic extraction modes were also considered†1 : • Cc extraction mode (net-to-net coupling parasitic capacitances). In this mode, parasitic coupling capacitances are extracted between each and all related nodes. • RCc extraction mode (subnode-to-subnode coupling parasitic resistances and capacitances). In this case, parasitic resistances are also considered. The simulation results considering both extraction modes for MDACs and SH are summarized in Table 5.30, where the remaining building blocks (sub-ADCs, voltagereference generator, etc) have been assumed to be ideal at this time. As can be inferred, high-level converter specifications are fully satisfied.

5.7.2

Remaining Building Block Post-Layout Verification

The electrical-level performance of the remaining building blocks, such as the subADCs, the reference-voltage generator, the clock-phase generator or the referencecurrent generator must also be verified taking into account the parasitics from the layout. To do so, the parasitic capacitances and resistances have been extracted from the layouts of each building block and new simulations have been carried out. The post-layout simulations are summarized in Tables 5.31, 5.32, 5.33, 5.34, 5.35 and 5.36. 1

RC extraction modes (subnode-to-subnode coupling parasitic resistances and capacitances to ground) are occasionally considered.

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5 Case Study: Design of a 10bit@60MS Pipeline ADC

Table 5.30 Post-layout simulation results of the pipeline ADC Extraction

Metric

Cc

ENOBS&D (bits) j PjS&D (nV2 ) Pnjth (nV2 )

RCc

Corner Typical

Fast

Slow

WONE

WZERO

ENOBj (bits)

10.27 34.8 20.4 9.94

9.85 62.4 19.7 9.66

9.71 75.8 20.9 9.54

9.88 59.8 23 9.65

9.70 76.8 24.3 9.50

(bits) ENOBS&D j PjS&D (nV2 ) Pnjth (nV2 ) ENOBj (bits)

9.96 53.8 20.4 9.73

9.96 53.6 19.7 9.74

9.08 183 20.9 9.00

9.79 68 23 9.58

9.67 80 24.3 9.48

Table 5.31 Post-layout standard deviation of the comparator offset Extraction

Parameter

Cc RCc

σoff (mV) σoff (mV)

Corner Typical

Fast

Slow

WONE

WZERO

2.10 2.09

2.53 2.58

1.89 1.86

2.40 2.36

2.17 2.19

Table 5.32 Post-layout comparator decision time against several-step amplitudes Extraction Cc

RCc

Step Amplitude

tHL (ps) Typical

Fast

Slow

WONE

WZERO

10μV 100μV 500μV

495 418 294

383 312 257

575 511 404

570 511 350

535 482 341

10μV 100μV 500μV

504 421 299

372 311 259

585 511 401

562 507 345

538 482 341

10μV 100μV 500μV

543 494 398

481 402 333

615 554 421

604 550 463

579 524 443

10μV 100μV 500μV

539 493 402

477 396 333

614 552 417

605 548 446

575 524 449

As can be inferred from Tables 5.32 and 5.33, the sum of the non-overlapping and delay times between phases is always higher than the decision time required for the comparators, so the decision bits will be available at the beginning of the amplification phase. However, if post-layout results are compared with the values in Table 5.17 a slight increment of the rising and falling times, as well as the power

5.7 Post-Layout Verification

165

Table 5.33 Post-layout clock-phase generator simulation results Extraction

Parameter

Corner Typical

Fast

Slow

WONE

WZERO

Cc

phiS-phiSd t ds (ps) phiA-phiAd t da (ps) phiSd-phiAd t novs (ps) phiAd-phiSd t nova (ps) phiS-phiSd rising time (ps) phiS-phiSd falling time (ps) phiA-phiAd rising time (ps) phiA-phiAd falling time(ps) strobe available time (ps) σclk (fs) Dynamic power (mW)

333 306 251 241 85 82 87 94 574 161 2.08

233 213 175 168 62 60 63 70 401 118 2.59

484 447 365 350 117 114 119 130 834 272 1.66

405 373 316 304 108 99 111 114 709 215 1.88

395 363 297 285 99 103 101 118 680 214 1.83

RCc

phiS-phiSd t ds (ps) phiA-phiAd t da (ps) phiSd-phiAd t novs (ps) phiAd-phiSd t nova (ps) phiS-phiSd rising time (ps) phiS-phiSd falling time (ps) phiA-phiAd rising time (ps) phiA-phiAd falling time(ps) strobe available time (ps) σclk (fs) Dynamic power (mW)

337 308 267 257 138 124 160 130 680

239 218 190 184 115 102 137 104 423

408 375 335 324 164 143 187 153 732

398 365 311 299 153 148 174 158 697

2.01

2.46

485 446 381 367 169 156 191 168 852 – 1.62

1.82

1.78

consumption, can be appreciated. This is due to the increment of the total capacitance as a consequence of the parasitic capacitances from the layout. It can be observed that the output impedance at DC of the voltage references and common-mode generators is higher than the limit given by Eq. (5.32). However, this is not a real problem since the switched capacitance is actually switching at 60 MHz.

5.7.3

Converter Post-Layout Verification

The post-layout verification of the basic building blocks in the pipeline converter was carried out individually in the previous subsections. In order to evaluate the influence on the performance of the overall pipeline converter some verifications must still be carried out. The aim of this section is to present the effective resolution of the converter taking the post-layout parasitics from the layout implementation of all building blocks into consideration. A procedure analogous to that featured in Sect. 5.5 is followed to evaluate the converter resolution, i.e.: a transient analysis is run considering a Nyquist frequency input signal; an FFT analysis is then carried out from 256 output samples and the ENOBS&D extracted; finally, the thermal and jitternoise contributions are computed and the effective resolution evaluated according to Eq. (5.38). Due to the highly time-consuming requirements for computing the

166

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Table 5.34 Post-layout common-mode voltage generator simulation results Extraction

Parameter

Corner Typical

Fast

Slow

WONE

WZERO

Cc

1st CM volt. gen. 2nd CM volt. gen.

VCMo1 (mV) Settling time (ns) Z o (DC) () Z o (60 MHz) () Z o (120 MHz) () Pno (nV2 ) Settling time (ns) Power cons. (mW)

575 0.96 0.72 1.11 2.31 3.67 0.48 1.17

633 0.55 0.54 1.07 2.24 3.11 0.46 1.35

518 1.40 0.93 1.13 2.35 4.08 0.50 1.00

517 1.39 1.06 1.13 2.36 3.98 0.49 1.03

517 1.52 1.16 1.13 2.35 3.86 0.49 1.03

RCc

1st CM volt. gen. 2nd CM volt. gen.

VCMo1 (mV) Settling time (ns) Z o (DC) () Z o (60 MHz) () Z o (120 MHz) () Pno (nV2 ) Settling time (ns) Power cons. (mW)

575 0.95 5.74 1.08 2.24 3.21 0.82 1.17

633 0.58 5.55 1.04 2.11 2.63 0.78 1.35

518 1.45 5.95 1.11 2.30 3.63 0.85 1.00

517 1.44 6.07 1.11 2.29 3.56 0.83 1.03

517 1.58 6.19 1.10 2.28 3.47 0.84 1.03

Table 5.35 Post-layout current-conveyor simulation results Extraction

Parameter

Corner 2

Typical

Fast

Slow

WONE

WZERO

Cc

Input-referred noise (nV ) I ref (μA) Power cons. (mW)

13.6 175.1 0.90

9.11 175.1 1.67

17.6 175.2 0.37

19.2 174.9 0.38

15.0 175.5 0.71

RCc

Input-referred noise (nV2 ) I ref (μA) Power cons. (mW)

13.63 174.2 0.89

9.15 174.1 1.65

17.48 174.3 0.36

19.1 174 0.35

15.0 174.5 0.70

simulations, only the Cc extraction mode will be considered. The simulation results are summarized in Table 5.37. For illustration purposes, Fig. 5.55a shows the output spectrum for an input signal at 28 MHz under typical conditions and considering the Cc extraction mode. Figure 5.55b depicts the effective converter resolution against the input frequency. As can be inferred, the converter resolution is not degraded.

5.8

Packaging

The pipeline converter must be packaged for IC testing. We have selected a quad flat pack (QFP) solution for reliability and low cost. However, special attention must be paid to the parasitic inductances of the bonding wires. The problem arises from the switching activity of the pipeline converter which causes voltage oscillations when

5.8 Packaging

167

Table 5.36 Post-layout reference voltage generator simulation results Extraction

Parameter

Corner Typical

Fast

Slow

WONE

WZERO

Cc

V ref (mV) Z o (DC) () Z o (60 MHz) () Z o (120 MHz) () Pno (nV2 ) Settling time (ns) Power cons. (mW)

400.1 0.13 1.20 2.43 4.85 0.65 1.50

400.2 0.08 1.20 2.46 5.42 0.83 1.91

400.1 0.20 1.20 2.41 4.79 0.77 1.15

400.1 0.25 1.20 2.43 4.58 0.65 1.20

400.1 0.24 1.20 2.43 4.48 0.66 1.20

RCc

V ref (mV) Z o (DC) () Z o (60 MHz) () Z o (120 MHz) () Pno (nV2 ) Settling time (ns) Power cons. (mW)

400.2 8.44 1.19 2.40 3.58 0.91 1.50

400.3 8.39 1.20 2.41 7.45 0.76 1.91

400 8.52 1.19 2.39 3.16 1.12 1.15

400 8.56 1.19 2.40 3.17 0.91 1.20

400 8.58 1.19 2.40 3.03 0.92 1.20

Table 5.37 Post-layout simulation results of the pipeline converter Extraction

Metric S&D

ENOB (bits) PS&D (nV2 ) Pnth (nV2 ) j it Pn (30MHz) (nV2 ) ENOB (bits)

Typical

Fast

Slow

WONE

WZERO

10.76 17.7 20.4 0.15 10.2

10.49 25.8 19.7 0.08 10.1

9.10 177 20.9 0.42 9.02

10.29 34 23 0.26 9.91

10.29 34 24.3 0.26 9.91

20

11

0

10.5

–20 ENOB (bits)

Power/frequency (dB/Hz)

Cc

Corner

–40 –60 –80

9.5 9 8.5

–100

8

–120

a

10

0

5

10 15 20 Frequency (MHz)

25

0

30

b

5

10 15 20 Frequency (MHz)

25

30

Fig. 5.55 Post-layout simulations: a output spectrum for a 28 MHz input signal and b ENOBS&D against the input frequency

168

5 Case Study: Design of a 10bit@60MS Pipeline ADC

current glitches flow through the parasitic inductances. To overcome this problem, some points have been taken into consideration: (a) A minimum size for the package has been selected. Taking into account the required input and output pins, a 48-pin QFN package was the proposed solution. By minimizing the size of the package, the cavity is decreased and, the length of the bonding wires thus reduced. Since the parasitic inductances are directly proportional to the length of the bonding wires, these are also reduced. (b) Multiple decoupling capacitors have been distributed around the converter layout. These capacitors act as charge reservoirs, reducing the current glitches required from external power supplies. (c) Double bonding has been used for power supplies and reference voltages. As a result, the equivalent parasitic inductance is practically halved. (d) Multiple pins have also been used for the distribution of power supplies and reference voltages so that the current glitches are spread around the different pins. The bonding diagram of the pipeline converter using the proposed QFN48 package and 7 × 7 mm package cavity is illustrated in Fig. 5.56. A detailed diagram of the pad-to-pin connection is shown in Fig. 5.57. The pinout description is summarized in Table 5.38. In order to evaluate the influence of the packaging on the converter performance, the equivalent circuit in Fig. 5.58 has been considered for each bonding wire, where

Fig. 5.56 Bonding diagram of the pipeline converter using a QFN package

DVDD

B12

B11

B10

B9

B8

B7

B6

B4

CLK

B5

169

DVDD

5.8 Packaging

DVSS

B2 B1

PHI2

DVSS

VSSIOCO

DVDD

VDDIOCO

B12

B11

B9

B10

B8

B7

B6

B5

B4

CLK

DVDD

B1

B14

VDDIO

B15 VDDSE

AIP

GNDSUB

AIN

VREFP

VREFP

VREFP

VREFP

VREFN

PHI1 B13 B14 B15 DVDDSE DGNDSUB VREFP VREFN

VDDIOCO

AVDD

VBMAS

AVSS

REXT

AVSS

MVSS

MVSS

MVDD

MVDD

VBREF

VSSIO

VCMO2 VDDSE

VBREF GNDSUB

VCMO2

AVDD

VREFN

VREFN

AVDD

VREFN

AVSS

VREFN

B13

VBREF

VREFP

PHI1

VSSIO

AIP AIN

B3

AVSSREF

DGNDE

PHI2

B2

VCMO2

DVDDE

VDDIOCO

B3

DVSS

VSSIOCO

DVSS

VCMO2

VCMO2

AVDD

VBMAS

REXT

AVSS

MVSS

MVDD

AGNDE

AGNDSUB

AVDDSE

AVDD

AVSS

AVSS

AVDDE

Fig. 5.57 Detailed diagram of the pad-to-pin connections Table 5.38 Pinout description of the diagram in Fig. 5.56 Pin

Direction

Description

DVDD, DVSS MVDD, MVSS AVDD, AVSS B1–B15 CLK PHI1–PHI2 VREFP, VREFN VCMO2 VBREF VBMAS REXT

Bidirectional Bidirectional Bidirectional Output Input Output Bidirectional Bidirectional Input Input Bidirectional

AIP—AIN DVDDSE, DGNDSUB

Bidirectional Bidirectional

DVDDE, DGNDE AVDDSE, AGNDSUB

Bidirectional Bidirectional

AGNDE

Bidirectional

1.2 V digital power supplies 1.2 V mixed-signal power supplies 1.2 V analog power supplies Digital output bits Input clock signal Non-overlapping clock phases Reference voltages 2nd reference common-mode voltage Input voltage for the reference voltage generator Input voltage for the reference current generator External resistor for the reference current generator Input analog signal 1.2 V power supplies for substrate and deep nwells of the digital ring 1.2 V digital power supplies for digital IO cells 1.2 V power supplies for substrate and deep nwells of the analog ring 1.2 V analog ground for the analog IO cells

170

5 Case Study: Design of a 10bit@60MS Pipeline ADC

Fig. 5.58 Equivalent circuit for a bonding wire

previous bonding wire schematic

~50fF PIN

Lp

~100mΩ

PAD ~250fF

k=0.34

~50fF

next bonding wire schematic

Table 5.39 Post-layout simulation results of the converter taking into account the bonding diagram Extraction Cc

Metric S&D

ENOB (bits) PS&D (nV2 ) Pnth (nV2 ) j it Pn (30MHz) (nV2 ) ENOB (bits)

Corner Typical

Fast

Slow

WONE

WZERO

10.42 28.4 20.4 0.15 10.00

9.94 55.3 19.7 0.08 9.72

9.19 156 20.9 0.42 9.10

10.21 38 23 0.26 9.87

10.11 43.7 24.3 0.26 9.79

the parasitic inductance (L p ) is calculated from the length of the bonding wire and k is a coupling factor with the adjacent bonding wire. Thus an equivalent model for the QFN package can be obtained. The performance of the pipeline converter is evaluated once again following a similar procedure to that described in Sect. 5.7.3 and taking this equivalent model into account. The simulation results are summarized in Table 5.39, where the Cc extraction mode has been considered for the converter parasitics.

Chapter 6

Experimental Results and State of the Art

The integrated prototype introduced in the previous chapter has been characterized in the laboratory. To support the IC testing, a Printed Circuit Board (PCB) was developed and modern testing equipment employed. This chapter will describe the IC test procedure. It is organized as follows. The first part consists of a detailed description of the test setup, emphasizing both the main PCB design considerations and the basic PCB components required. Following this, the experimental results are reported. To conclude the chapter, a brief comparison with state-of-the-art pipeline converters will be offered.

6.1 Test Setup The IC test requires the development of a purpose-built PCB to interface the prototype with the external equipment. Special care must be taken with the design of the PCB since it has to guarantee the integrity of the input and output signals. The selection of suitable equipment is also essential as we must introduce and measure signals with a resolution higher than that required for the IC. Both issues will be considered separately.

6.1.1

PCB

The aim of the PCB is to support the prototype testing. In order to do so, clean voltage supplies, bias, clock, input and output signals must be provided. A simplified schematic of the PCB developed is shown in Fig. 6.1. The following features can be distinguished: • Separate ground planes have been considered for the analog, mixed-signal and digital sections. In addition, a separate plane is used for the ground of the reference voltages. J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_6, © Springer Science+Business Media, LLC 2011

171

6 Experimental Results and State of the Art

Fig. 6.1 Simplified schematic of the test PCB

172

6.1 Test Setup

173

• The ASIC power supplies are provided by a single-voltage regulator. Digital, mixed-signal, and analog supplies are later separated and filtered with passive components to reduce the coupling noise. • In order to reduce the ringing of power supplies, several decoupling capacitors were used in parallel with different values to flat the power supply impedance along a wide bandwidth. • A potentiometer was used for corner testing at the voltage regulator output. • All PCB components have been conscientiously selected to support temperatures from −40 to 85 ◦ C. • Two input signal modes are available: a single-ended transformer-coupled front end and a direct differential input signal mode. • Low-power, low-noise, and low-distortion rail-to-rail amplifiers are used to provide: (1) the external voltage reference (VBREF) for the generation of the ASIC reference voltages and (2) the ASIC common-mode voltage to the input signal paths. • Low inductance parasitic capacitors have been used for the external compensation of the voltage references in order to reduce the bouncing of internal voltages. • Output bits are directly monitored by a logic analyzer. In order to complement the PCB description, the PCB components required will be detailed next. The analog input front-end for the ADC will also be briefly explained.

6.1.1.1

Input-Signal Interfacing

The design of the front-end prior to a high-performance ADC is critical to achieve the desired system performance. Two main approaches can be distinguished in the implementation of this front end: a transformer-coupled input configuration or an amplifier. A typical transformer-coupled front end configuration is shown in Fig. 6.2a [136, 137]. There, a transformer translates the input signal from single-ended to differential. This approach provides several advantages: (1) it is inherently ac-coupled, (2) it vi VCM ADC

a vi

Fig. 6.2 Typical front-end configurations prior to an ADC: a transformer and b amplifier approaches

– + VCM + –

b

ADC

174

6 Experimental Results and State of the Art vip

vi

1:1.5

1:1.5 VCM

RC

VCM

filter

Two transformers in cascade vin

Fig. 6.3 Front-end configuration prior to our prototype

does not introduce additional thermal noise, (3) it can provide a common-mode voltage if a center-tapped transformer is used, (4) it reduces the number of components required, (5) it can provide a specific voltage gain thanks to the turns ratio (N) and (6) it consumes no power. However, real transformers suffer losses, have a limited bandwidth and are more sensitive to input imbalance. In addition, the transformer output impedance increases with the square of the voltage gain. An amplifier can be also used for implementing the ADC front end, as shown in Fig. 6.2b [138]. This approach provides gain more easily and a flatter output impedance response, free of the ripple resulting from parasitic interactions in transformers. However, an amplifier is an active element and, as a result, it consumes power and adds noise. Furthermore, the amplifier configuration can add distortion to the input signal. In our PCB, we decided to use the transformer approach. Figure 6.3 shows the schematic of the front end. It includes an RC filter before the ADC to reduce the aliasing of spurious input tones, while two cascaded transformers provide a more balanced solution for high frequencies[136]. The transformers have a 1:1.5 turn ratio to provide a specific gain. The values for resistances, inductances and capacitances are selected to match the 50 analog input source. We also provided a direct differential input path (vip , vin ) to excite the prototype from external equipment. Note that the transformer approach removes the DC component from the input signal, so this direct path could be useful in the static characterization of the ADC. 6.1.1.2

Basic Components

There are some components which have been carefully selected as they could potentially degrade the integrity of the IC testing. The most significant components are enumerated below: • External compensation capacitors A 22 μF capacitor was selected to externally compensate the voltage references and common-mode voltage. Since the parasitic inductance of this capacitor can

6.1 Test Setup

175

considerably degrade the settling of the voltage references under switching activity, a suitable capacitor must be selected. In our proposed PCB we used a capacitor which provides a parasitic inductance lower than 0.5 nH. • Low-power, low-noise and low-distortion rail-to-rail output amplifier Our prototype requires two external voltage references: VBREF and VBMAS (see pin-out description in Table 5.38). In order to avoid ground loops, the use of different external voltage sources is not advisable. Therefore, these must be generated at PCB level. The former voltage reference (VBREF) attacks a relatively low impedance node (see Fig. 5.40) so a buffer amplifier will be required. This component must not introduce significant noise or distortion. In addition, it must provide a very lowvoltage reference (VBREF ≈ 180 mV). In order to satisfy these requirements, √ we used a commercial amplifier which provides low-noise (2.1nV/ Hz), lowdistortion (−105 dBc@100 kHz), low-offset voltage (0.3 mV maximum) and an output that can swing to less than 50 mV of either rail. Figure 6.4a shows the implemented schematic for the generation of VBREF. The voltage reference VBMAS attacks a high impedance node so a resistor divider is sufficient. Figure 6.4b shows the schematic for the generation of VBMAS. Finally, it is worth noting that the common-mode voltage internally generated by the ADC must be provided to the transformers in order to set the common-mode voltage in the input signal path. To avoid overloading the on-chip common-mode voltage generator, the aforementioned buffer amplifier was used again. Figure 6.4c shows the schematic which provides the common-mode voltage. • RF transformers. The ADT1.5-1 RF transformers were selected for the front-end. This provides an insertion loss lower than 1 dB up to 320 MHz and a 1.5 turn ratio.

10k

10k

VBMAS +

VBREF Buffer

100n

100n

2k

–

2k

a

b To transformers center tap

+ VCM from prototype

Buffer –

c Fig. 6.4 Schematics for the generation of the voltage references: a VBREF, b VBMAS and c VCM

176

6.1.1.3

6 Experimental Results and State of the Art

Electrical-Level PCB Verification

A detailed layout view of the PCB is depicted in Fig. 6.5. From there, postlayout parasitics were extracted for the most critical pins (see pin-out description in Table 5.38), summarized in Table 6.1. A Cc post-layout simulation was carried

Fig. 6.5 Layout view of the test PCB

6.2 Experimental Results

177

Table 6.1 PCB parasitics Signal

Inductance (nH)

Coupling cap. (pF)

Ground cap. (pF)

Resistance (m)

AIP AIN VREFP VREFN VBREF VCMO2 VBMAS REXT

2.29 2.27 1.43 1.55 0.63 1.5 0.52 1.39

0.18

0.86 0.85 0.7 0.76 0.23 0.73 0.2 0.52

34 34 19 21 9 20 8 21

Table 6.2 Post-layout simulation results of the converter taking into account the bonding diagram, PCB parasitics and macromodels for the PCB components

0.13 – – – –

Extraction Cc

Metric S& D

ENOB (bits) PS&D (nV2 ) Pnth (nV2 ) jit Pn (30MHz) (nV2 ) ENOB (bits)

Typical corner 10.19 39.1 20.4 0.15 9.89

out to verify the performance of the test, taking into account these parasitics, equivalent models for external capacitances, and macromodels for the buffer amplifier and RF transformers. The simulation results under typical conditions are summarized in Table 6.2.

6.2

Experimental Results

Once the PCB developed was verified by means of electrical simulations and the testing equipment required was selected, the prototype was tested in the laboratory. Figure 6.6 shows a photograph of the PCB designed. The IC was tested in three environmental corners, summarized in Table 6.3. Both static and dynamic characterizations were carried out. The results are presented in the sections that follow.

6.2.1

Static Characterization

A DNL/INL analysis was carried out in order to characterize the static performance of the prototype. For this purpose, a low-input frequency signal (1 MHz) was introduced with an input level slightly higher than that of the converter FS. An output data stream of 256 kS was analyzed. The results, under typical environmental conditions (corner TT), are depicted in Fig. 6.7 both for 10- and 11-bit output words. As can be inferred, the DNL and INL for 10-bit output words are lower than 1 and 0.5 LSB respectively. These values guarantee converter monotonicity, so no missing codes are produced.

178

6 Experimental Results and State of the Art

Fig. 6.6 Photograph of the PCB

Table 6.3 Environmental corner definition for the IC testing

LSB

–2

LT

HT ◦

85 ◦ C 1.08 V

−40 C 1.32 V

INL@10bits

0 –2

0

500

1000 Code

1500

2000

0

DNL@11bits

200

0 –1

400 600 Code

800

1000

800

1000

DNL@10bits

1 LSB

1 LSB

27 C 1.2 V

2

0

0 –1

0

a

◦

Temperature Voltage supply

INL@11bits

2 LSB

TT

500

1000 Code

1500

2000

0

b

200

400 600 Code

Fig. 6.7 DNL/INL metrics considering typical conditions and: a 10- and b 11- output bits

6.2 Experimental Results

179

Fig. 6.8 SNDR vs. input amplitude for a 1 MHz input signal under typical conditions

60

SNDR (dB)

55

50

45

40 0.15 0.25 Input amplitude (V)

0.35

As part of this static characterization, the SNDR was evaluated against the input amplitude for a 1 MHz input tone. Figure 6.8 shows the result, from which it can be appreciated that the converter maintains the linearity until the voltage reference (0.4 V).

6.2.2

Dynamic Characterization

10

80

9

75 Magnitude (dB)

ENOB (bits)

In order to evaluate the dynamic performance, some spectra-based analyses were carried out. Firstly, the ENOB, SFDR and SNDR were computed against the input frequency. An input tone at almost full-scale amplitude was used and the data stream of 8192 samples analyzed. Figures 6.9, 6.10 and 6.11 illustrate the results for the environmental corners in Table 6.3.

8 7 6 5

70 65 60 55

4

50 0

a

SFDR(dB) SNDR(dB)

5

10 15 20 25 Input Frequency (MHz)

30

0

b

5

10 15 20 25 Input Frequency (MHz)

30

Fig. 6.9 TT corner (27 ◦ [email protected]) dynamic performance: a ENOB and b SFDR and SNDR vs. the input frequency

6 Experimental Results and State of the Art

10

80

9

75 Magnitude (dB)

ENOB (bits)

180

8 7 6 5 4

SFDR(dB) SNDR(dB)

70 65 60 55

0

5

a

10 15 20 25 Input Frequency (MHz)

50

30

0

5

b

10 15 20 25 Input Frequency (MHz)

30

10

80

9

75 Magnitude (dB)

ENOB (bits)

Fig. 6.10 LT corner (−40 ◦ [email protected] V) dynamic performance: a ENOB and b SFDR and SNDR vs. the input frequency

8 7 6 5 4

a

SFDR(dB) SNDR(dB)

70 65 60 55

0

5

10 15 20 25 Input Frequency (MHz)

50

30

b

0

5

10 15 20 25 Input Frequency (MHz)

30

Fig. 6.11 HT (85 ◦ [email protected] V) dynamic performance: a ENOB and b SFDR and SNDR vs. the input frequency

As can be observed, the effective resolution is over 9 bits along the entire Nyquist bandwidth both for the TT and LT corners. However, the converter performance is degraded by about 0.8 bits in the HT corner. This degradation prompted us to carry out a more precise electrical verification of the PCB since the IC performance was thoroughly verified in Chap. 5 (see Table 5.39). New post-layout verifications were therefore carried out taking into account the PCB-level parasitics in Table 6.1, equivalent models for external devices, and the remaining technological and environmental corners assumed in Chap. 5. The results are summarized in Table 6.4. As can be inferred, the converter performance is degraded in the “Worst ONE” corner (85 ◦ , 1.08 V, slow NMOS, fast PMOS), which might justify the experimental result in Fig. 6.11 (85 ◦ [email protected] V). To summarize, the main metrics obtained throughout the dynamic characterization are collected in Table 6.5. Figure 6.12 shows the output spectra for 1 MHz and

6.2 Experimental Results

181

Table 6.4 Post-layout simulation results of the converter taking into account the bonding diagram, PCB parasitics and macromodels for the PCB components Extraction

Metric

Corner

S&D

Cc

ENOB (bits) PS&D (nV2 ) Pnth (nV2 ) jit Pn (30MHz) (nV2 ) ENOB (bits)

Table 6.5 Dynamic performance summary

Typical

Fast

Slow

WONE

WZERO

10.19 39.1 20.4 0.15 9.89

9.71 76 19.7 0.08 9.54

9.13 170 20.9 0.42 9.04

8.24 583 23 0.26 8.21

9.71 76 24.3 0.26 9.51

TT

LT

HT

ENOB (95% FS) 1 MHz 15 MHz 30 MHz

9.47 bits 9.40 bits 9.15 bits

9.39 bits 9.27 bits 9.13 bits

8.47 bits 8.39 bits 8.33 bits

SNDR (95% FS) 1 MHz 15 MHz 30 MHz

58.77 dB 58.60 dB 56.84 dB

58.31 dB 57.59 dB 56.75 dB

52.74 dB 52.25 dB 51.89 dB

SFDR (95% FS) 1 MHz 15 MHz 30 MHz

67.05 dB 67.80 dB 65.60 dB

76.38 dB 66.44 dB 64.11 dB

60.86 dB 61.65 dB 60.51 dB

–60 –80

ENOB = 9.47bits

–100 –120 –140 –160 –180 –200

a

–40 Power/frequency (dB/Hz)

Power/frequency (dB/Hz)

–40

0

5

10 15 20 Frequency (MHz)

–60 –80

–120 –140 –160 –180

25

ENOB = 9.15bits

–100

0

5

b

10 15 20 Frequency (MHz)

25

Fig. 6.12 Output spectra for a: a 1 MHz and b 28 MHz input tones

29 MHz input tones under typical conditions. In addition, the ENOB has been evaluated versus the sampling rate for an input tone at 1 MHz and full-scale amplitude. Figure 6.13 depicts the results. It can be observed that the performance prototype is better for low sampling rates. However, the ENOB is quickly degraded when sampling rates are higher than 60 MS/s. This proves that the design successfully satisfied the specifications in terms of minimum power consumption.

182

6 Experimental Results and State of the Art

Fig. 6.13 ENOB vs. sampling rate

Vdd = 1.2V T = 27°C 10

ENOB (bits)

9 8 7 6 5 4

Table 6.6 Measured performance summary under typical environmental conditions

0

20

40 60 80 Sampling Frequency (MHz)

Technology Resolution Conversion rate Supply voltage Temperature Reference voltage DNL (95% FS) INL (95% FS) ENOB (95% FS) SNDR (95% FS) SFDR (95% FS) Area (with/without pads) Power (Analog/Digital+IO) FOM (95% FS)

100

0.13μm 6-Metal 11 bits 60 MS/s 1.2 V (1.08 ∼ 1.32 V) 27 ◦ C (−40 ∼ 85 ◦ C) 0.4 V −0.60/0.28 LSB −0.61/0.61 LSB 9.47 bits @ f i = 1 MHz 9.15 bits @ f i = 30 MHz 58.77 dB @ f i = 1 MHz 56.84 dB @ f i = 30 MHz 67.05 dB @ f i = 1 MHz 65.64 dB @ f i = 30 MHz 1.7/3 mm2 23 mW 0.54 pJ/conv @ f i = 1 MHz 0.67 pJ/conv @ f i = 30 MHz

Finally, a summary of the measured performance under typical conditions is reported in Table 6.6. Assuming a power consumption of about 23 mW and a worst case ENOB of 9.15 bits under typical conditions for our prototype; a FOM 1 ≈ 0.67 pJ/conv is achieved. By taking into account this result and those in Table 1.5, Fig. 6.14 is obtained. As can be inferred, our prototype achieves an excellent performance, with a FOM around 0.5 pJ/conv. In addition, our prototype does not require any additional power reduction techniques, such as opamp sharing, removing the SH, or

6.2 Experimental Results

183

7 Calibration Opamp sharing Removing SH Switched opamp Pseudo-differential Conventional Others This work

6

FOM (pJ/conv)

5

4

3

2

1

0 0

50

100 150 Sampling Rate (MS/s)

200

Fig. 6.14 FOM 1 versus sampling rate for the ICs in Table 1.5

switched-bias techniques, needed in the case of other reported state-of-the-art pipeline ADCs [36, 37, 69]. Therefore, we have demonstrated the efficiency and reliability of our proposed design methodology by obtaining a 10 bit@60 MS/s pipeline ADC over state-of-the-art converters of this sort.

Chapter 7

Conclusions and Future Lines of Research

Pipeline converters have proved to be a good approach for medium-high resolution and medium-high speed applications [29–92], covering a wide field of broadband communications such as DVB, PLC or VDSL. However, the rapid evolution of such systems, requiring increasingly fast and accurate converters, and the current trend for integrating these into adverse digital technologies make the design of pipeline ADCs a major challenge. Hence the importance of design methodologies and CAD tools which can assist designers in shortening the time-to-market of the final products and reducing the complexity of such challenges. In this monograph, we have developed a design methodology for the transistorlevel synthesis of pipeline converters which is able to map the high-level specifications of the converter directly onto transistor sizes and biasing conditions. It is based on the combination of a behavioural simulator for performance evaluation, accurate models of the converter components, a set of Matlab routines to estimate the electrical-level parameters, and an optimization algorithm to minimize the power and area consumption of the circuit solution. The main contributions of this work can be summarized as follows: • A fast and accurate behavioural simulator of pipeline converters was developed. It was integrated into the Matlab-Simulink interface, providing the tool with high flexibility, low-computation cost and user-friendliness. It includes a set of behavioural models for the basic building blocks of the pipeline converter, a set of Simulink library blocks, a GUI and a set of post-processing routines. To the best of our knowledge, these behavioural models are the most accurate reported to date, accounting not only for small-signal effects, but other important largesignal phenomena. In fact, our behavioural model estimations are very close to the transistor-level simulations, showing a maximum deviation of 0.3 bits of effective resolution. They are C-written, requiring more than five thousand C-code lines. • The above behavioural simulator has been combined with an optimization algorithm for synthesis purposes. Both simulated annealing and genetic approaches can be used. • A complex synthesis procedure has been developed for the mapping of the highlevel converter specifications onto transistor-level specifications. It is able to

J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_7, © Springer Science+Business Media, LLC 2011

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7 Conclusions and Future Lines of Research

reduce the design space of variables to three parameters. It includes a set of Matlab routines which obtain very accurate estimations of parasitics and dimensions of the transistors at electrical level. The Matlab routines use look-up table techniques for a better characterization and estimation of technology parameters. As a result, a novel, efficient, and accurate electrical-level synthesis tool of pipeline converters has been implemented. The main advantages against other design methodologies are: 1. The modelling proposed extends previous approaches in the following points: • It not only addresses single-pole amplifier topologies but also two-stage structures. One-stage amplifiers are often unsuitable in low-voltage applications where high DC gain and output swing voltages must be simultaneously satisfied. In this case, two-stage amplifiers must be used. Herein, we focus on the well-known two-stage MC technique. • Besides slewing effects, the impact of the variation of the DC gain of OTAs with the signal level is also accounted for. • The influence of the non-zero switch-on resistances on the converter dynamic response is also addressed. • An accurate model for thermal-noise contributions has been included. 2. In many design methodologies, the optimum pipeline architecture is frequently manually derived and prearranged with design plans and scripts, or even uses heuristic approaches in nature or knowledge-based strategies. These approximations can lead to non-optimum solutions since they are based on first-order approximations and are usually technology-independent. In contrast, the efficiency, flexibility and high speed of our synthesis tool allow us to synthesize arbitrary pipeline architectures until electrical-level in a few minutes. In addition, the synthesis results account for the technology parameters. Thus, numerous pipeline architectures can be quickly explored, guaranteeing optimum architecture. 3. Generally, numerous bottom-up iterations are required in the design methodologies of pipeline ADCs since they are not able to accurately estimate the parasitics and usually find specifications pertaining to the open-loop behaviour for the basic building blocks. In contrast, our proposed synthesis tool drastically reduces the bottom-up iterations and user iterations as parasitics are estimated efficiently and closed-loop operation conditions are intrinsically considered in the design flow. 4. Traditionally, two mapping procedures are used throughout the synthesis procedure. Firstly, a high-level specification mapping procedure translates the converter specifications onto specifications for the basic building blocks. For this purpose, a behavioural simulator is often combined with an optimization algorithm. Secondly, a low-level specification mapping procedure usually translates the basic building block specifications onto electrical-level parameters by combining an optimization algorithm and an electrical-level simulator such as SPICE or SPECTRE. This requires several user iterations and is extremely time-consuming. In our proposed synthesis methodology, high-level and low-level specification mapping are combined in a single mapping procedure, drastically reducing the design cycle and user iterations.

7 Conclusions and Future Lines of Research

187

5. As a consequence of the time taken and bottom-up iterations required by these design methodologies, designers usually oversize the ADC in order to satisfy the specifications and simultaneously reduce the design cycle. In our proposed synthesis procedure, oversizing is not necessary as the accuracy of our behavioural models allows us to estimate the resolution and power consumption of the converter, as well as the efficiency of our single mapping procedure, with precision. A pipeline converter was designed in order to demonstrate the usefulness and efficiency of this synthesis tool. The following features can be distinguished: • A 10bit@60MS pipeline converter was integrated into a 1.2 V and 0.13 μm technology. It comprises five stages, solving 3 bits-per-stage in each one. Two-stage MC OTA topologies were used for the implementation of the amplifiers. • It includes an on-chip reference voltage and current generators. • The prototype consumes less than 23 mW and occupies an active area around 3 mm2 . • It achieves an effective resolution higher than 9 bits in the entire Nyquist bandwidth and the INL and DNL are lower than 0.61 and 0.6 LSB, respectively. • The prototype satisfies the converter specifications on most technological corners. • The FOM 1 is lower than 0.65 pJ/conv. This puts our prototype among state-ofthe-art pipeline converters, without having to use any additional power reduction technique, and demonstrating the efficiency and accuracy of our proposed design methodology. As future work to continue the research of this book, we propose the following:  a) To extend the design methodology to other types of converters, such as  or successive approximation approaches. b) To provide the design methodology with some mechanisms to simultaneously consider all technological corners. c) To develop a complete library of one- and two-stage MC topologies in several technologies. d) To provide a tool capable of selecting the most suitable OTA topology according to specification.

Appendix A

A.1 Technology Characterization The estimation of the electrical level parameters of the basic building blocks is a fundamental task in the proposed synthesis methodology since it determines the efficiency and accuracy of our tool. Therefore, a suitable method must be developed to offer a precise estimation of the electrical level parameters required in the design flow, such as transistor sizes, parasitic capacitances, bias currents, etc. This chapter will be dedicated to describing these methods and is organized as follows. Firstly, the method applied for the estimation of electrical level parameters, based on look-up table techniques, will be explained. Then, for illustration purposes some routines to estimate the electrical level parameters by using that method will be described.

A.1.1

Electrical Parameters Estimation Methods

In our proposed design methodology, electrical level parameters such as parasitic capacitances, currents, physical dimensions, etc, must be determined. Obviously, electrical level simulators such as SPICE or SPECTRE can accurately determine these parameters. However, the iterative nature of the synthesis methodology makes this solution unfeasible due to the extended times required by electrical simulators. Among the different alternatives, the so-called look-up table technique, based on data arrays which store values for a previously simulated or computed function or parameter, offers one of the best speed-accuracy trade-offs. Therefore, the accuracy of this technique is determined by the simulator which obtains these values. However, the savings in terms of processing time can be significant, since retrieving a value from memory is often faster than undergoing an ‘expensive’ computation.The following sections will detail how this technique has been employed to obtain the electrical level parameters for the basic building blocks in pipeline converters.

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190

Appendix A

A.1.2

Routines for Obtaining the Electrical Parameters

As Sect. 3.3 shows, the specification mapping procedures require accurate estimations of certain electrical-level parameters. In particular, parasitic capacitances, transconductances, bias currents and sizes for transistors must be estimated. For this purpose, look-up table techniques have been used. Some of the routines developed to estimate these parameters will be described here. An example of 1.2 V@130 nm technology is considered.

A.1.3

Transconductances Estimation

Assuming a saturation operation for an MOS transistor and neglecting the early effect, its transconductance can be approximated as follows [143]: W (A.1) gm = kg vdsat L where k g is a technological parameter; W and L are the MOS dimensions and vdsat stands for the overdrive voltage. However, Eq. (A.1) is a first-order approximation for coarse estimations, and conventional MOS transistors are described by very high-order models with hundred of parameters†1 . Therefore, Eq. (A.1) cannot be used for accurate estimations. In order to overcome this problem, a look-up table technique will be used. The aim is to extract several k g parameters from electricallevel simulations for different bias conditions (vdsat) and lengths (L). For each vdsat and L value, the MOS transconductance can be accurately characterized by Eq. (A.1). Figure A.1 shows the simulation results for a MOS transistor considering several overdrive voltages (vdsat) and lengths (L). A linear fitting can be carried out to obtain the respective k g factors. The results obtained are presented in the following look-up table: vdsat → 0.100 0.125 0.150 0.175 0.200 ⎡ ⎤ 0.468 0.506 0.500 0.466 0.417 ⎢0.401 0.445 0.458 0.451 0.431⎥ mA ⎥ kg = ⎢ ⎣0.358 0.403 0.419 0.421 0.412⎦ V2 0.341 0.380 0.398 0.404 0.399

L 130 nm 200 nm 300 nm 400 nm

(A.2)

From the k g look-up table in Eq. (A.2) and given a certain length (L), width (W ) and overdrive voltage (vdsat), the transconductance of an MOS transistor can be accurately obtained according to Eq. (A.1). For example, an MOS transistor with L = 300 nm, W = 100 μm and overdrive voltage vdsat = 125 mV: gm = kg 1

W 100 vdsat = 0.403 · · 0.125 = 16.8 mA/V L 0.3

Level 49 BSIM3 version 3.1 MOS model includes 105 parameters.

(A.3)

A.1 Technology Characterization

191 200

vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

200 150

gm*L/vdsat (mA/V2*μm)

gm*L/vdsat (mA/V2*μm)

250

100 50 0 100

a

200

300

100

50

400

0

100

b

Width(μm) 180

200

300

400

300

400

Width(μm) 180

vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

160 140 120

gm*L/vdsat (mA/V2*μm)

gm*L/vdsat (mA/V2*μm)

150

0 0

100 80 60 40 20 0

vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

160 140 120 100 80 60 40 20 0

0

c

vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

100

200

300

400

0

d

Width(μm)

100

200 Width(μm)

Fig. A.1 Electrical-level simulations results for an MOS transistor with length: a 130 nm, b 200 nm, c 300 nm and d 400 nm

Analogously, Eq. (A.1) can be used for obtaining the width required (W ) given a specific length (L), overdrive voltage (vdsat), and transconductance (gm ). For instance, an MOS transistor with L = 200 nm, overdrive voltage vdsat = 150 mV and a required transconductance gm = 10 mA/V must have the following width: W =

A.1.4

gm L 10 · 0.2 = = 291 μm kg vdsat 0.458 · 0.15

(A.4)

Current Estimation

The current provided by an MOS transistor operating in a saturation region is approximately given by the expression: id = ki

W 2 v L dsat

(A.5)

where k i is a technological parameter, W and L are the MOS dimensions, and vdsat is the overdrive voltage. Again, Eq. (A.5) is a coarse estimation so a look-up table technique is applied for accuracy. A batch of electrical-level simulations have

192

Appendix A 180 vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

250 200 150 100 50 0

0

100

200

300

100 80 60 40

0

100

b

Width(μm)

200

300

400

300

400

Width(μm) 140

vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

120 100

id*L/vdsat2 (mA*μm/V2)

id*L/vdsat2 (mA*μm/V2)

120

0

400

140

c

140

20

a

80 60 40 20 0

vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

160 id*L/vdsat2 (mA*μm/V2)

id*L/vdsat2 (mA*μm/V2)

300

0

100

200 Width(μm)

300

100 80 60 40 20 0

400

vdsat = 0.100V vdsat = 0.125V vdsat = 0.150V vdsat = 0.175V vdsat = 0.200V

120

0

100

d

200 Width(μm)

Fig. A.2 Electrical-level simulation results for an MOS transistor with length: a 130 nm, b 200 nm, c 300 nm and d 400 nm

been carried out considering several lengths and overdrive voltages for the MOS transistors. From each L−vdsat value pair, a set of k i -parameters are extracted. The simulation results are shown in Fig. A.2. By applying a liner fitting at each plot, the following k i look-up table can be obtained: vdsat → 0.100 0.125 0.150 0.175 0.200 ⎡ ⎤ 0.403 0.479 0.552 0.619 0.669 ⎢0.300 0.346 0.384 0.418 0.448⎥ 2 ⎥ ki = ⎢ ⎣0.249 0.287 0.310 0.331 0.347⎦ mA · V 0.232 0.258 0.280 0.297 0.309

L 130 nm 200 nm 300 nm 400 nm

(A.6)

This look-up table allow us to accurately estimate the current provided by an MOS transistor given specific dimensions and overdrive voltage. For instance, for an MOS transistor with relation W/L = 200 / 0.3 and an overdrive voltage vdsat = 100 mV, the current saturation provided must be: W 2 200 vdsat = 0.249 · · 0.12 = 1.66 mA (A.7) L 0.3 Obviously, this equation can be used to obtain the width required for an MOS transistor providing a specific current saturation. id = ki

Appendix B

B.1 Thermal Noise in SC Circuits Overview Noise is present in all circuit implementations and is one of the most limiting factors, since it imposes a minimum signal level that the circuit can process with acceptable quality. Noise becomes more important in SC circuits due to the sampling process. In these circuits, the noise sources normally present a wide-band spectrum and as a result, are undersampled by the SC network. Therefore, the circuit noise is folded back several times in base band (aliasing), increasing power noise and limiting circuit resolution considerably. In this section, the thermal noise generated by a simple track and hold circuit will be analyzed as an initial approach to understand the aliasing process in a sampled circuit.

B.1.1

Thermal Noise in a Track and Hold Circuit

Let us consider the track and hold circuit in Fig. B.1. It operates in two consecutive clock phases. When the clock signal—the so-called tracking phase—is high, the MOS transistor is on, presenting a non-zero resistance (r on ). Therefore, the input voltage is transferred to the sampling capacitor (C s ) according to the RC time constant formed by the MOS switch-on resistance and the capacitor. When the clock signal— the so-called holding phase—is low, the MOS transistor is off and the capacitor maintains the sampled voltage. Thus, the noise of this SC circuit can be conceptually separated into two orthogonal components [128, 139, 140], a track and a sampled and hold component: vc (t) = vcT (t) + vcSH (t)

(B.1)

Let us consider each component separately.

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194

Appendix B VDD clk VSS

Vin

vn

ron

+

Cs

+

vc

–

a

Cs

vc

–

b

Fig. B.1 Track and hold circuit: a schematic and b equivalent noise circuit during the tracking phase

S(f ) 2KTRon Scn(f ) =

area =

KT Cs

2KTRon 1 + ( 2πfRonCs )2 –BWn =

–1 4RonCs

BWn =

1 4RonCs

f

Fig. B.2 Noise PSD of the capacitor voltage: equivalent noise bandwidth concept

B.1.2

Track Component

The equivalent circuit during the tracking phase is shown in Fig. B.1b, where zero input has been assumed and vn is the noise voltage introduced by the resistance of the MOS switch. As inferred in this figure, the track component is obtained by following the capacitor voltage during intervals of τT = mTs and holding zero voltage during intervals of (m − 1)Ts . Therefore, this component can be expressed as: vcT (t) = vc (t)gτT (t)

(B.2)

where gτT (t) is the gating function, defined as: 0 gτT (t) =

1

nTs < t < nTs + τT

0

nTs + τT < t < (n + 1) Ts + τT

(B.3)

B.1 Thermal Noise in SC Circuits Overview

195

where n is an integer. From Eq. (B.2), the noise PSD of the track component can be inferred:  ScT (f ) =

ττT Ts

2  ∞

 Scn (f − nfs )

n=−∞

sin (nπ τTf ) π τT f

2 (B.4)

where f s = 1/T s is the clock frequency and S cn (f ) is the noise PSD of the output voltage stored in the capacitor. According to the equivalent circuit in Fig. B.1, the noise PSD in the capacitor will be determined by [141]: Scn (f ) = Sn (f ) |H (f )|2

(B.5)

where S n (f ) is the noise PSD generated by the resistance and H(f ) is the transfer function from the noise source to the output, that is: H (s) =

1 1 + Ron Cs S

(B.6)

The noise PSD of a resistance is independent from the frequency (up to 1013 Hz [5]). For a double-sided representation in frequency, it can be computed as follows: Sn (f ) = 2KT Ron

(B.7)

Replacing Eqs. (B.7) and (B.6) in Eq. (B.5): Scn (f ) =

B.1.3

2KT Ron 1 + (2πf Ron Cs )2

(B.8)

Sampled and Hold Component

The sampled and hold component is obtained by sampling the track component at mT s , mT s + T s ,. . . instants and holding these samples for intervals of τSH = (m − 1)Ts . Therefore, it can be expressed as:  vCSH (t)

=

∞ 

 vCT (t)δ(t

− nTs ) ⊗ gτSH (t)

(B.9)

n=−∞

where gτSH (t) is the gating function defined for the duration of the hold phase τSH = (m − 1)Ts . Taking the Fourier transform of Eq. (B.9):  ScSH (f ) =

τSH Ts

2 

sin (πτSH f ) πτSH f

2  ∞ n=−∞

Scn (f − nfs )

(B.10)

196

B.1.4

Appendix B

Total Noise

The aim of this section is to find the noise PSD of the track and hold circuit in the band of interest ([−fs /2, fs /2]) . From this point, we will be able to compute the power noise by simply integrating this noise PSD. From the above analysis, the total noise PSD in a track and hold circuit can be computed as the sum of the track and sampled and hold components in Eqs. (B.4) and (B.10): Sc (f ) = ScT (f ) + ScSH (f )   2   ∞ τT sin (nπ τT f ) 2 Sc (f ) = Scn (f − nfs ) Ts π τT f n=−∞ 

+

τSH Ts

2 

sin (πτSH f ) πτSH f

2  ∞

Scn (f − nfs )

(B.11)

n=−∞

This expression is relatively complex but can be simplified by introducing the concept of equivalent noise bandwidth. Considering the frequency shape of Scn (f ), as illustrated in Fig. B.2, the area under Scn (f ) provides the total static noise power in the capacitor:  ∞  ∞ 2 = vcn Scn (f )df = Sn |H (f )|2 df −∞

−∞



= Sn

∞ −∞

|H (f )|2 df =

The equivalent noise bandwidth is defined as follows:  ∞ 1 BWn = |H (f )|2 df = 4R Cs on 0

KT Cs

(B.12)

(B.13)

Hence, the total static noise power can be redefined as: 2 = 2BW S vcn n n

(B.14)

Note that from the above definitions, the equivalent noise bandwidth can be interpreted as the ideal bandwidth over which a constant spectral density S n must be integrated to obtain the same total noise power. This is illustrated in Fig. B.2 as the shaded rectangular box. The introduction of the concept of equivalent noise bandwidth allows us to simplify Eq. (B.10) in the band of interest ([−fs /2, fs /2]), assuming a rectangular frequency shape for Scn (f ), and given that Scn (f ) is a stationary process which is therefore uncorrelated over the frequency [142], the summation terms () in Eq. (B.10) can be simplified by simply overlapping the rectangles and adding up their noise PSD. Therefore, two possibilities can be distinguished depending on the equivalent noise bandwidth:

B.1 Thermal Noise in SC Circuits Overview

197

a) BW n ≤ f s /2 This situation is illustrated in Fig. B.3, where there is no overlapping, that is to say, where no aliasing occurs. In this case, only the terms for n = 0 contribute to the S c (f ) in Eq. (B.11):    2   τT τSH 2 sin (π τSH f ) 2 Scn (f ) + Scn (f ) Sc (f ) = Ts Ts π τSH f − fs /2 < f < fs /2

(B.15)

b) BW n > f s /2 In this case, the noise PSD is undersampled and therefore overlapped in the band of interest ( [−fs /2, fs /2] ). The concept of equivalent bandwidth is applied here, so Scn (f ) is assumed to have rectangular frequency shape with a constant value Sn and the number of rectangles which are overlapped in the band are computed. As depicted in Fig. B.3, this number is N = (2BWn ) /fs , so the noise PSD in Eq. (B.11) can be simplified as follows:  Sc (f ) =

τT Ts 

+

2 Sn τSH Ts

 N/2   sin (nπ τT f ) 2 πτT f n=−N/2

2 

sin (πτSH f ) πτSH f

2

2BWn Sn − fs /2 < f < fs /2 fs

(B.16)

Eq. (B.16) can be simplified if the following approximation is applied [140]:  N/2   sin (nπ τT f ) 2 Ts ≈ πτT f τT n=−N/2 Therefore: τT Sn + Sc (f ) = Ts



τSH Ts

2 

BWn > 10fs

sin (πτSH f ) πτSH f

2

2BWn Sn fs

Replacing Eqs. (B.7) and (B.13) in Eq. (B.18):     τT τSH 2 sin (π τSH f ) 2 KT Sn + Sc (f ) = Ts Ts π τSH f Cs f s

(B.17)

(B.18)

(B.19)

In practice, the MOS switches are sized so that a complete charge transfer is achieved in the tracking period (τT = mTs ) . Since the charging time constant is τRC = Ron Cs , the following condition must be satisfied for a settling accuracy: τRC  τT ≡ Ron Cs < mTs

(B.20)

From Eq. (B.7), it can be inferred that the equivalent noise bandwidth must be several times higher than the sampling frequency. Therefore, aliasing is usually found in SC circuits.

198

Appendix B Scn (f ) Sn …

a

–4fs

n = –3

n = –2

–3fs

–2fs

n = –1

n=0

…

n=1

n=2

n=3

fs

2fs

3fs

4fs

f

2fs

3fs

4fs

f

2fs

3fs

4fs

f

3fs

4fs

f

–fs Scn (f )

n=0 –4fs

–3fs

–2fs

fs

–fs

n=1 n = –1 –4fs

–3fs

–2fs

–fs

fs

n=2 n=–2 –4fs

–3fs

–2fs

–fs

fs

2fs

n=3 n = –3 –4fs

–3fs

–2fs

–fs

fs

∞

3fs

Scn (f – nfs) =

n = –∞

f

4fs 2BWn fs

Sn

…

…

4 Sn

2fs

n=0 n=1 n = –1 n=2

n = –2

b

–4fs

–3fs n = –3

–2fs

–fs

fs

2fs

3fs n=3

4fs

f

Fig. B.3 Noise PSD of a track and hold circuit: a no aliasing and b aliasing for an equivalent noise bandwidth BW n = 2f S

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Index

A A/D Characterization, 7 Dynamic performance, 8 Static performance, 7 A/D Conversion Fundamentals, 1 Noise error, 5 Quantization error, 3 Quantization error Conditions to white noise assumption, 4 Static& Dynamic errors, 6 ADC Driver, 174 Aliasing, 6 Amplification phase, 12 Aperture error, 22 B Behavioural model MDAC, 96 Amplification phase, 99 Sampling phase, 99 sub-ADC, 103 Behaviural modelling, 32 Bias circuit, 120 Bootstrapped switch, 118 Bottom-up iterations, 36 C Capacitor mismatch, 68, 106 Clock-phase generator, 131 Clock distribution, 132 Phase generator, 132 Commom-mode feedback, 122 Common-mode voltage generator, 145 Comparator, 124 Converter specifications, 105 Critically-damped response, 57, 75

D Damped frequency, 74 Damping factor, 74 Damping network, 143 Damping ratio, 74 DCL, 11 Design variable space reduction, 45 Dynamic latch, 127 Dynamic loading effect, 136 E ENOB, 10 Equation based simulators, 32 Equivalent amplifier load One stage, 48 Two stage, 57 Equivalent input noise, 97 Experimental results, 177 Dynamic characterization, 179 Static characterization, 177 F Feedback factor, 48 FOM, 26 G GUI, 44 H HD, 10 Hysteresis, 100 I INL/DNL, 7 J Jitter noise, 96

J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1, © Springer Science+Business Media, LLC 2011

207

208 L Layout, 151 ADC, 158 Clock phase generator, 158 MDAC, 153 Reference current generator, 156 Reference voltage generator, 156 SH, 152 sub-ADC, 155 LSB, 2 M Mapping constraints One-stage, 48 Two-stage, 56 MDAC, 11, 19 Gain factor, 67 Ideal performance, 67 Thermometer and pseudo-thermometer architectures, 20 Missing code, 8 N Natural frequency, 74 Noise Jitter noise, 5 Thermal noise, 6 Non-linear DC gain, 76 Nyquist converters, 2 Nyquist theorem, 1 O Offset, 100 One-stage OTA mapping procedure, 46 Optimization algorithms, 62 Overdamped response, 75 Oversizing, 113 P Packaging, 166 Parasitic inductances, 166 PCB, 171 Features, 171 Input-signal interfacing, 173 Parasitics, 176 Pipeline ADC equivalent input noise, 112 Pipeline Converters, 11 Analog Building Blocks, 15 Current trends, 20 Opamp sharing, 21 Current trends Calibration, 25 Current trends Pseudo-differential arch., 24 Current trends Removing SH, 22

Index Current trends Scaling down, 21 Current trends Switched-opamp, 23 Operation Principles, 11 Redundancy, 13 State-of-the-art, 26 Timing, 12 Positive feedback, 127 Post-layout verification, 160 Preamplifier, 126 Proposed design methodology Advantages, 36 Prototype test setup, 171 Q Quantization, 2 Quantization error, 2 Quantization step, 2 R Redesigning pipeline, 113 Redundancy, 13 Advantages, 15 Reference current generator, 148 Reference voltage generator, 134 Requirements, 138 Residue, 11 Resistor ladder, 124 RS flip-flop, 128 S S-functions, 42 Sampling phase, 12 Sampling theory, 1 SFDR, 9 SH, 17 Architectures, 18 Slew-rate, 75 SNDR, 10 SNR, 9 SNYRCOS, 41 Accuracy, 41 Computational cost, 41 Flexibility, 43 Matlab-Simulink implementation, 42 User-friendliness, 44 Sub-ADC, 16 Comparators, 16 Input-offset cancellation, 16 Switch encoder, 131 Switch parasitics, 107 Switch-on resistance, 83 Harmonic distortion, 117 Synthesis procedure, 39

Index Design variables, 39 Low-level mapping routines, 44 T Technological corners, 113 THD, 10 Thermal noise in the MDAC, 89 Amplification phase, 91 References, 91 Sampling phase, 91 Total noise, 93 Thermometer-to-binary encoder, 130 Time constant, 48 Top-down design methodology, 29 Hierarchical levels, 30

209 Circuit level, 31 Layout Level, 31 System level, 30 Transistor Level, 31 Hierarchicaldecomposition, 29 Key elements, 32 Mapping specifications, 34 Simulator and circuit modelling, 32 Transformer-coupled front end, 173 U Undamped response, 75 Underdamped response, 75 Unitary redundancy, 14