Design and Modeling of Millimeter-wave CMOS Circuits for Wireless Transceivers: Era of Sub-100nm Technology

Design and Modeling of Millimeter-Wave CMOS Circuits for Wireless Transceivers

Design and Modeling of Millimeter-Wave CMOS Circuits for Wireless Transceivers Era of Sub-100nm Technology

Ivan Chee-Hong Lai Fujitsu Laboratories Ltd, Japan and

Minoru Fujishima University of Tokyo, Japan

123

Ivan Chee-Hong Lai Fujitsu Laboratories Ltd. Shin-Yokohama square building 2-3-12 Shin-Yokohama, Kohoku Kanagawa 222-0033 Japan [email protected]

ISBN: 978-1-4020-6998-7

Minoru Fujishima The University of Tokyo Dept. of Frontier Informatics 5-1-5-703 Kashiwanoha Kashiwa Chiba 277-8561 Japan [email protected]

e-ISBN: 978-1-4020-6999-4

Library of Congress Control Number: 2008923441 2008 Springer Science+Business Media B.V. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

©

Printed on acid-free paper 9 8 7 6 5 4 3 2 1 springer.com

Contents

Preface .......................................................................................................... ix Acknowledgments........................................................................................ xi

Part 1: Background ...................................................................................... 1 Chapter 1: A Short History ......................................................................... 3 1. Millimeter Waves ................................................................................ 3 2. Birth of the Transistor ......................................................................... 5 Chapter 2: State of the Art .......................................................................... 7 Chapter 3: RF CMOS IC Design .............................................................. 11 1. The Wireless Transceiver .................................................................. 12 2. Design Tools...................................................................................... 17 3. Measurement Equipment................................................................... 21

Part 2: Millimeter-Wave CMOS Passive Devices.................................... 25 Chapter 4: On-Chip Inductor ................................................................... 27 1. Physical Phenomena in the On-Chip Inductor................................... 27 2. Existing Inductor Models .................................................................. 28

v

Contents

vi 3. 4. 5. 6. 7.

Substrate-Coupled Inductor Model ................................................... 31 Equations for the Scalable Model...................................................... 33 Experimental Results......................................................................... 39 Circuit Performance........................................................................... 43 Chapter Summary .............................................................................. 46

Chapter 5: On-Chip Capacitor ................................................................. 49 1. 2. 3. 4.

Analysis of the Floating Shield ......................................................... 50 Scalable Circuit Model ...................................................................... 55 Experimental Results......................................................................... 60 Chapter Summary .............................................................................. 67

Chapter 6: Transmission Lines ................................................................. 69 1. Fundamentals..................................................................................... 69 1.1 Electric and Magnetic Field Propagations ................................. 69 1.2 Voltage and Current Wave Propagations................................... 72 1.3 Phase Velocity ........................................................................... 74 2. Slow-Wave Transmission Line (SWTL) ........................................... 75 2.1 Background on Slow-Wave Research........................................ 76 2.2 Realizing Slow-Wave Transmission Lines ................................ 77 2.2.1 The SWTL Structure........................................................ 77 2.2.2 Measurement of Fabricated Structures............................. 81 2.3 Modeling SWTL ........................................................................ 86 2.3.1 Equivalent Circuit Model................................................. 86 2.3.2 Modeling Results ............................................................. 89 3. Asymmetric Coaxial Waveguide (ACW).......................................... 92 3.1 The ACW Structure ................................................................... 93 3.2 Analysis of Inductive and Capacitive Quality Factors in Transmission Lines ................................................................ 95 3.3 Experimental Results ................................................................. 97 4. Chapter Summary ............................................................................ 100 Chapter 7: On-Chip Balun ...................................................................... 103 1. Balun Design ................................................................................... 103 2. Experimental Results....................................................................... 105 3. Derivations for Differential-Mode and Common-Mode Response Ratio ................................................................................ 110 4. Chapter Summary ............................................................................ 111

Contents

vii

Part 3: Millimeter-Wave Active CMOS Circuits .................................. 113 Chapter 8: Up-Conversion Mixers.......................................................... 115 1. Pseudo-Millimeter Wave Up-Conversion Mixer............................. 115 1.1 Up-Conversion Mixer Design Methodology ........................... 116 1.2 Stacked Marchand Balun Design ............................................. 118 1.3 Experimental Results ............................................................... 122 2. Millimeter-Wave Up-Conversion Mixer at 50 GHz........................ 127 2.1 Up-Conversion Mixer Design.................................................. 127 2.1.1 Mixer Topology ............................................................. 127 2.1.2 Passive Balun Structure ................................................. 128 2.1.3 Active IF Balun.............................................................. 129 2.2 Experimental Results ............................................................... 129 3. Chapter Summary ............................................................................ 132 Chapter 9: Down-Conversion Mixer ...................................................... 133 1. 2. 3. 4.

Mixer and Slow-Wave Transmission Lines .................................... 134 Chip Layout ..................................................................................... 137 Experimental Results....................................................................... 138 Chapter Summary ............................................................................ 140

Chapter 10: RF Amplifier........................................................................ 141 1. Review of Conventional Design Techniques .................................. 142 1.1 Stability .................................................................................... 144 1.2 Gain.......................................................................................... 147 1.3 Noise Figure............................................................................. 148 2. Current-Reuse Cascade Amplifier................................................... 150 2.1 Principles of Operation ............................................................ 151 2.2 Analytical Expression for Circuit Transconductance .............. 154 2.3 Design of 60 GHz CRCA ........................................................ 156 3. Experimental Results....................................................................... 156 4. Chapter Summary ............................................................................ 159 Chapter 11: Voltage Controlled-Oscillator............................................ 161 1. Design of 76 GHz VCO .................................................................. 161 2. Experimental Results....................................................................... 164 3. Chapter Summary ............................................................................ 167

viii

Contents

Chapter 12: Conclusion ........................................................................... 169 References ................................................................................................. 173 Index .......................................................................................................... 181

Preface

This book describes the circuit building blocks of the wireless transceiver for millimeter-wave frequency bands. Millimeter-wave frequency is commonly defined to be at least 30 GHz, if we presume wave propagation in free space. Thus, this threshold is dependent on the material in which the wave is propagating, and therefore depends on the process technology employed. There is interest to build the circuits on standard silicon process technology, or known as pure digital complementary metal oxide semiconductor (CMOS) technology due to its existing well-developed infrastructure for mass production. This infers a lower cost for materials, process and yield. Practicing high frequency designs using CMOS technology begins with difficult challenges. Firstly, a cross-disciplinary know-how of traditional separate fields of knowledge is required. Specializations on microelectronics, analog circuit techniques and microwave theory are considered necessary so it is difficult for students to embark on this area of high frequency integrated circuit (IC) design. In addition, the target application of the designs requires the circuit designer to know the technical specifications of the application, thus knowledge of communication fundamentals such as modulation schemes, may be necessary. Therefore, this book aims to serve as a starting point for researchers by discussing the most important aspects in millimeter-wave designs using CMOS technology. Part I starts with a chapter on the brief history of the development in various technological fields and their convergence. The development towards the state-of-the-art digital CMOS technology is a result of aggressive scaling for higher switching speeds for fast digital circuits. From this point however, we will use this technology for our high frequency analog needs.

ix

x

Preface

Secondly, realizing chip designs at high frequency requires an enormous amount of effort in developing, characterizing and implementing passive devices on-chip. Due to the reduced wavelength at higher frequencies, it makes a great deal of sense to design as much of the passive devices on-chip as possible. This technique can further avoid inter-chip or off-chip parasitic. Hence, in the main Part II, Chapters 4–7 discuss the challenges and designs of passive devices for millimeter-wave transceivers in detail. This includes the spiral inductor that normally operates at a relatively lower frequency, although reported works have already shown that it can be operated beyond 60 GHz. Regardless of its possibility at high frequency, the spiral inductor will at least be used at the low frequency ends of the transceiver circuits. Importantly, we wish to focus on the fundamental transmission lines, from which most of other devices can be formed, such as the balun and frequency matching network. Part III contains design details and measurement results of millimeterwave circuits implementing the devices described in Part II. These chapters explain the practical applications of the inductor, transmission lines and the on-chip balun on the circuits. Their performance is found to be comparable to the existing state-of-the-art and have been reported at major international conferences. We therefore, hope that this book can serve as a useful reference for researchers working in the area of millimeter-wave CMOS IC design, as well as for instructors to introduce these important topics to graduate students of this field. With any certain form of Moore’s law continuing to hold true, millimeter-wave CMOS design will certainly grow in the years to come. We gratefully acknowledge the support of SCOPE and STARC for selected funding of the fabrication of experimental prototypes described herein. We would also like to thank all members of the laboratory, including Koji Ishibashi for his contributions to Chapters 5 and 11 through his works on the on-chip capacitor and the 76 GHz voltage-controlled oscillator respectively.

Acknowledgments

Strategic Information and Communications R&D Promotion Programme (SCOPE), Ministry of Internal Affairs and Communications, Japan. Semiconductor Technology Academic Research Center (STARC) VLSI Development and Education Center (VDEC), The University of Tokyo

xi

PART 1

BACKGROUND

Chapter 1 A SHORT HISTORY

It is useful to begin with a brief history to serve as the background for this work. This will help to understand the attitude and context when developing the circuits in this book. This chapter may also serve as a starting point for further reading to know the history of this subject and to understand the related areas of physics and technology.

1.

MILLIMETER WAVES

The foundations of millimeter-wave technology was laid in 1864 when the Scottish mathematician and theoretical physicist, James Clerk Maxwell presented his equations on electro-magnetism to the Royal Society of London. This theory predicted the possibility of radio waves and its existence was later confirmed by the German physicist Heinrich Hertz. These developments led to the first millimeter and sub-millimeter wave activities occurring in the 1890s. Among other scientists of his era, Jagadis Chandra Bose of Residency College, India, attempted quantitative measurements at millimeter-waves. He successfully made the first measurements at wavelengths down to 5 mm,1 which corresponds to 60 GHz in free space. As a source, he used a spark gap having platinum electrodes with a special shape to emphasize the radiation at millimeter waves. He developed various components of sulfur or glass and investigated many natural crystals to obtain their birefringent properties. Bose later worked on contact conductivity of metallic particles showing nonconstant current-voltage (I–V) characteristics, and anticipating the existence of P-type and N-type semiconductors.2

3

Chapter 1

4

waveguide

L spark gap generator

(a)

(b)

Figure 1-1. An early spark gap generator for producing millimeter-waves

Figure 1-1 shows the simplified description of the spark gap generator used. Figure 1.1(a) shows the radiator used for generating the 5 mm radiation, and Fig. 1-1(b) shows the arrangement with lens (labeled ‘L’) at the exit of the waveguide. Spark gap generators were later replaced with various vacuum tube configurations, including the klystron and the cavity magnetron. These were used in the radars of the Second World War. The early practical uses of the millimeter wave were made with waveguides as a development from the discovery that attenuation decreases asymptotically toward zero as the carrier frequency increases indefinitely for circular electric mode in ideal round pipe. Bell Telephone laboratories had developed an interest in millimeter waves before the war and there was

Average atmospheric absorption of millimeter-waves Attenuation (dB/km)

100 H2O

O2 10

H2O

O2 Horizontal propagation at sea level

1 0.1

H 2O

0.01

Horizontal propagation at 9150m

10

20

30 40 50

100

200

Frequency (GHz)

Figure 1-2. Attenuation of electromagnetic signal in air4

400

A Short History

5

interest in millimeter waves for conventional radio communication. However, atmospheric attenuation due to oxygen, water vapor and rainfall was a serious disadvantage, but was not well understood at first. In 1946, Beringer made early measurements on oxygen absorption near 5 mm (60 GHz) 3 to explain the electromagnetic attenuation in air. Today, we know the causes of the attenuation at various frequencies and it is possible to avoid using certain frequency with high attenuation for long-distance transmissions. Conversely, high attenuation frequencies can be exploited in short range applications where high speed and data security is important. Figure 1-2 shows the plot of attenuation at different frequency and their respective origins.4 Wiltse5 provided a good review of the major events that have occurred in the development of millimeter and sub-millimeter wave technology from the beginnings in the 1890s until the present time.

2.

BIRTH OF THE TRANSISTOR

Another break-through development at Bell laboratories was made in 1947 when the first germanium transistor was invented by John Bardeen, William Bradford Shockley, and Walter Houser Brattain, all of whom subsequently won the Nobel Prize in Physics in 1956. Unfortunately, the invented germanium transistor suffers from large leakage currents and is unable to work at elevated temperatures. At the time of invention, however, knowledge on the workings of the transistor was poor. Earlier theoretical development of quantum mechanics played an important role. The concept of electronic band structure, due to quantum mechanics, was the key to the insight. Silicon then provided a better option because the band gap was larger so it does not become intrinsic at as low a temperature as does germanium. After silicon transistors were invented, they became popular to this day. Progressive developments in the process of fabricating transistors with reduced surface states in the silicon-silicon dioxide interface, controlling impurities and planar technology contributed to an established silicon complementary metal-oxide-semiconductor (CMOS) technology by the 1970s. Continuous improvements overcame obstacles after obstacles over the years as the feature size of the transistor scales down. Brinkman6 provides a descriptive history of the invention of the transistor.

Chapter 1

6 20 GHz 22-29GHz Automotive radar 59-66GHz License free band

70-86GHz Broadband gigabit wireless communications 77GHz Automotive collision radar 94GHz Autonomous cruise control

110-300GHz Non-ionic imaging 300 GHz

Figure 1-3. List of frequency allocation in the millimeter and sub-millimeter bands

The impact of the solid-state transistor on wireless communication is significant. The possibility of using CMOS technology for high frequency generated a lot of interest in radar, communications, missile guidance and remote sensing. Signal sources can be generated using solid-state circuits through the development of on-chip oscillators and phase-locked loops. Extensive analog functions such as frequency mixing and amplification can be realized on-chip as well as high speed digital functions. The first demonstration of the transistor product was the all-transistor radio which was made commercially successful by a Japanese company, Sony, in 1954 (formerly known as Tokyo Tsushin Kogyo). Due to the wide adoption of the CMOS process technology today, cost is relatively low and has dominated the low-frequency consumer applications. As CMOS technology continues to scale down in feature size, the operating frequency will increase. Millimeter and sub-millimeter wave circuits can be realized and provide a feasible solution for high-frequency applications of Fig. 1-3.

Chapter 2 STATE OF THE ART

Semiconductors have been used for millimeter-waves since the 1970s. The substrate materials used are the Gallium Arsenide (GaAs), Gallium Nitride (GaN), as well as Indium Phosphate (InP). Circuits built on these substrates are able to achieve high frequency and large output power. However, as silicon process technology continues to progress, it became clear that this is a cheaper option for realizing RF circuits. The silicon germanium (SiGe) process is an example of a silicon process suitable for high frequency circuits that allows bipolar junction transistors to be used. Recent micro electro-mechanical systems (MEMS) processing techniques enable high quality devices desirable for analog circuits. However, to truly take advantage of the silicon technology, pure digital CMOS technology without specific modifications for RF purposes should be employed. This refers to the standard process technology for which digital circuits such as memories and logics are built. The key driver is the cost reduction from analog-digital integration in the system, as we bear in mind that reduced cost was the main driver in using silicon technology for RF in the first place.

7

Chapter 2

8 㪈㪇㪇㪇 Transition Freq. [GHz]

ITRS2005 data

O CM

S

SiGe

InP

Overtakes SiGe in 2014

Overtakes InP in 2009

㪈㪇㪇 㪉㪇㪇㪌

㪉㪇㪈㪇

㪉㪇㪈㪌

㪉㪇㪉㪇

Year Figure 2-1. Progress in CMOS RF characteristics

The challenge in using CMOS is that this technology has not been used for millimeter-wave designs only until recently. The first commercial MOS transistors were built with a minimum size of approximately 25 μm with limited current unity-gain transition frequency fT. To realize amplification with such transistors at gigahertz frequency range was impossible as the operation frequency can only be a fraction of fT. Recent developments in CMOS technology have advanced the technology node to 32 nm. Sub-100 nm technology nodes allow fT to achieve values of 150 GHz and beyond. This makes it possible to design CMOS circuit to operate at millimeter-wave frequencies. Figure 2-1 shows the increasing CMOS fT overtaking that of InP and SiGe in the near future. This expectation is driven by the continued commitments to improve the CMOS process. Using advanced CMOS process technology, however, has some associated difficulties. Scaling requirements demand a lower supply voltage Vdd, which restricts the use of conventional circuit topologies that requires voltage stacking. New circuit techniques to overcome this problem are required.7 Other major problems include the process variations due to the finer resolution of the devices, which will degrade the matching requirements of conventional differential circuit topologies as well as the required increase in chip complexity to satisfy the density requirements. Current researches in semiconductor RF designs are broadly divided into two kinds. One of which is the improvement of the fabrication technology. This includes selecting the materials, enhancing the processing steps and providing better characterization. Digital CMOS processes have resolutions finer than 100 nm, where new materials that can provide high permittivity

State of the Art

9

for the thin gate dielectrics are needed and are being studied. Alternatives to pure digital CMOS process include CMOS processes with RF options, such as high resistivity substrate and thick metals, at the expense of higher fabrication costs. The other area of research is on the chip design technology, which is the focus of this book. The focus here, in these works, is to realize millimeter-wave circuits on pure digital CMOS process technology. The potential of dividing these two tasks has been recognized and, as a result, commercial design houses sprout independently without the need for their own foundry and focus on the issues of circuit design. Hence, it is useful and relevant to work within the constraints of a technology to optimize it, and not aim to change it. Nevertheless, it is recognized that the fabrication technology has always been changing according to some form of Moore’s law and will almost certainly continue to do so. But within the constraints of the existing state-of-the-art process and perhaps of the next two generations, we introduce and develop some specific designs. Some designs are grounded on fundamental physics and will continue to hold with minimal changes. Chip design includes designing the physical layout of the lithographic mask. A large number of masks are needed to realize circuit components such as inductors, transmission lines and transistors. In order to design the mask layout correctly, circuit simulations are performed, under a different set of constraints. These constraints are the electrical requirements of the system, such as the required output power, linearity, bandwidth, bit rate etc. In the case of analog circuits, the design of the passive devices including the inductors, capacitor, resistor and transmission lines have a direct consequence from the constraints of the mask layout. It is thus imperative to consider both the layout constraints and circuit constraints. Another major circuit constraint is the limit on power consumption. This limit is constantly being lowered in order to use the circuit in portable devices that runs with limited battery life.

Chapter 2

10 Today

Mobile phone camera

Future

HD Videocam

HDTV

Digital camera

Graphics: Multi-Mbyte

Mobile phone HD video

HD Video: Multi-Gbyte

Figure 2-2. High definition advancements in digital consumer electronics

10G

Nikkei Electronics 8/14 Issue

Data Speed (Bit/Second)

HDMI1.2(1.65Gbps/pin) 1G

1M

Millimeter-wave WirelessUSB communications (UWB) (60GHz band) 802.16a (WiMAX)

x 100

100M

10M

Multiples

USB2.0(480Mbps)

802.11b/g (WiFi)

x 30

802.11a

W-CDMA

Figure 2-3. Broadband high speed transmissions

Portable devices can be realized as millimeter-wave systems which operate at high frequency, where large bandwidths are available for high datarate transmission. Figure 2-2 illustrates more high-definition video applications for future home electronic devices that use high data rates. They can share the use of the mobile phone and video recorders. In current mobile telephony, data speeds do not exceed 10 Mbps for W-CDMA or 54 Mbps for the 802.11 wireless LAN. Shown in Fig. 2-3, using millimeter-wave bands such as the 7 GHz broadband link at 60 GHz, data rates in excess of 1 Gbps can be achieved. Consequently, the digital functions of such devices can be integrated with the RF analog functions on the same silicon chip.

Chapter 3 RF CMOS IC DESIGN

RF applications of mobile telephony, wireless LAN or ubiquitous networks require access to the wireless communication channel in free space to transmit and receive signals. Using the wireless channel has the advantage of reduced physical cablings and therefore, improves the ease of connectivity. It is therefore a key requirement in the development of the ubiquitous technology that may employ millimeter-wave bands. However, in order for the digital data and information to access the channel, it is necessary to employ transceivers. A transceiver is fundamentally a radio front end that performs high frequency analog signal conditioning to provide a two-way interface between the information source at low base-band frequency and the channel. Figure 3-1 illustrates this basic link for a general communication system. The processor at the base-band can perform various control and data functions.

Radio Front End Antenna Control Navigation Transmitter Processing Receiver BaseBase band

Channel

Radio Front End

Baseband

Air Digital Signal Processing Free space Antenna Transmitter Video Functions Audio Functions Receiver Data Processing Memory

Figure 3-1. Basic link in the communication system includes the radio front ends and the base-bands at the ends of the channel

11

Chapter 3

12

1.

THE WIRELESS TRANSCEIVER

The wireless transceiver comprises of the transmitter and the receiver, which consist of other circuit building blocks, some of which can be shared such as the antenna and the phase-locked loop. However, due to the different power requirements and interference tolerances of the transmitter and receiver circuits, the specific design of each building block may be different from each other. Figure 3-2 shows the general block diagram of a transceiver. The transmitter, as shown in the upper path, receives the input modulated signal from the base-band processor through the digital-to-analog converter (DAC) and up-converts the carrier frequency to the desired value through one or more mixing, filtering and amplification operations. A power amplifier boosts the output power to the desired level and passes through a filter to reduce out-of-band power before transmitting through the antenna. The receiver may share the same antenna with the transmitter through a duplexer that minimizes the interaction between the two signals. The received signal is then filtered before amplification by the low-noise amplifier (LNA) to remove the image signal so that the down-conversion mixer can perform the frequency conversion correctly. The filtering requirements of the image signal, however, depend on the receiver architecture. The once – abandoned direct – conversion receiver architecture has no need for this filter, which is typically implemented in the form of a bulky SAW filter. The downconverted signal is converted to its digitalized form by the analog-to-digital converter (ADC) and de-modulated. Recent developments in software

Up Conversion Power Amplifier Mixer DAC

PA

Filter

Filter duplexer

PLL

ADC

LNA

Filter

Baseband

Antenna

Filter

Down Low Conversion Noise Amplifier Mixer

Figure 3-2. RF transceiver design for the millimeter-wave band is composed of different circuit building blocks

RF CMOS IC Design

13

defined radio8 have suggested all-digital solutions to replace the front-end. However, there still exist various difficulties including the digitization of signals at high frequencies. At millimeter-wave frequencies, the conventional analog architecture is the only applicable solution at present due to the unattainable high clock speeds required for sampling signals of 30 GHz and above. In this architecture, a transceiver front-end has to perform three tasks in both receive and transmit paths: • The center frequency of the modulated wanted signal has to be changed from a low frequency to a very high frequency for transmission or from the very high frequency to a low frequency for reception. • All unwanted signals situated outside the desired signal channel must be suppressed so that they do not interfere with the correct operation of the wireless communication link and other devices. • The signal levels have to be adjusted in order to obtain the highest possible performance. The transceiver front-end does not make any change to the shape or form of the modulated signal. This is done in the base-band at low frequencies by means of the modulation and demodulation process. A receiver or transmitter will therefore almost always be realized as a string of operations where each operation is either one of these three frequency domain operations: • a filter, for the suppression of signals outside the wanted channel; • an amplifier, to adjust the signal level; • a mixer, to change the center frequency. Filters are required to block signals and spectral components outside the pass band. Conventional passive filters can be implemented using discrete

Z1

Z1

Z2

Z1

Z2

Z2

Figure 3-3. Generic structure of the electric wave-filter or ladder filter by K. W. Wagner in 1919

14

Chapter 3

inductors and capacitors, by exploiting mechanical resonance in quartz crystals or by using acoustic waves in ceramic materials. The passive L-C ladder filter that enjoys widespread use today was invented in 1915 nearly simultaneously by Wagner in Germany and Campbell in the U.S.9, 10. The basic filter topology invented by Wagner is shown in Fig. 3-3. In modern integrated circuits, one can also employ passive spiral inductors and capacitors, but the low quality factor and small inductance of integrated inductors severely limits their utility. Active filters are viable but consume power, produce distortion and noise. Recently, there have been some developments in micromechanical filters on silicon that deserves further exploration. Currently, to implement filters at millimeter-wave frequencies, interconnects operating as transmission lines are used. The transmission line replaces the discrete inductors and capacitors by the appropriate lengths to produce the required impedances. This implementation is feasible because the short wavelength of the millimeter-wave signal occupies small area on the chip. However, transmission lines have high losses when fabricated above the conductive silicon substrate. Hence, transmission line designs with high quality factors are needed. Chapters 4–6 will present details of the work on the on-chip spiral inductor, capacitor and the transmission line. Chapter 7 discusses the passive balun that is built from transmission lines. Amplifiers in a transceiver circuit perform various amplification functions. In the transmitter, the power amplifier is located before the antenna to produce the required output power. A low noise amplifier is required for the first active stage in the receiver, immediately after the antenna. There are intermediatestage amplifiers to boost the signal power levels in the transmit- and receivepath as when needed. Also for this reason, intermediate – stage amplifiers are often implemented as variable gain amplifiers whose gain can be controlled externally. All amplifier designs require careful considerations, the specification of the amplifier for gain, linearity, output power and noise figures varies according to the role of the amplifier in the transceiver as well as the application of the transceiver in which the amplifier is used. In addition, there are general design trade-offs between linearity and efficiency, gain and noise figures, gain and bandwidth as well as between power consumption and gain bandwidth product. Another trade-off between operating frequency and gain is also an important consideration in the design of millimeter-wave amplifiers. Therefore, two approaches are required: • Select and optimize an amplifier topology to satisfy the minimum requirements and in addition, achieve high performance in important parameters for the required application. • Develop new circuit topologies to push both sides of the trade-off parameters to a higher performance level.

RF CMOS IC Design

15

Either approach has to consider the challenges when advanced CMOS process technology is used. Advanced CMOS process with low supply voltages prevents many conventional circuits with high voltage overheads to be used. These conventional circuits have performed well but become unsuitable for next-generation circuits in the millimeter-wave frequency. Furthermore, designing RF amplifiers using CMOS is challenging because of the demand placed on the MOSFET for performance with high gain at high frequency. For millimeter-wave amplifiers, impedance matching lines as well as routing interconnects all play an important role in the success of the design. Finally, the mixer is a device for performing frequency conversion. For using the mixer in the receiver, there are two inputs, the RF (radio frequency) and the LO (local oscillator). The desired output is the IF (intermediate frequency). For use in the transmitter, the two inputs are the IF and the LO instead, and the output is the RF. The LO is generated by a phase-locked loop (PLL) that includes a voltage-controlled oscillator (VCO). For the design of the mixer, the number of required stages depends on the topology. In the heterodyne transceiver, more than one level of frequency conversion is required. Therefore, mixers may be cascaded with filters in between. Additional amplifiers may be needed if the mixers and filters result in too much losses. The specific mixer implementation also depends on the design specifications according to the transceiver’s application, as in the case of the amplifier. In addition, the mixer design for high millimeter-wave frequency requires an effective layout that is complemented by useful circuit techniques: • Low power demands on the transceiver will persist and designs minimizing power dissipation at the expense of other excessive performance parameters will be needed. • In the zero-IF or low-IF architecture of a receiver, the image problem is resolved through complex operations of the signal with quadrature devices. Otherwise, filters will be required. In implementing these passive devices, the geometry of the layout should be efficient to reduce chip area consumption. • Chip area consumption can be reduced with proper design of the transmission line, which is the fundamental building block of all passive devices used by the mixer. The fundamental purpose of the mixer is to reduce the carrier frequency so that signal processing can be performed. Gain is also easier to obtain using IF amplifiers at lower frequencies than at high frequencies with reduced risk of instability and oscillations. Chapters 8–9 present examples of the CMOS mixer design and implementation. Chapter 10 explains a 50 GHz RF amplifier and Chapter 11 explains a 76 GHz VCO.

Chapter 3

16 D Cgd

Rd

G

Ddb B

BSIM4

Rg

Rb Cgs

Dsb

Rs S

Figure 3-4. Simplified RF small-signal model of NMOSFET

S22

-10

8

-20

6

-30 -40

4

S12 [dB]

40 MHz

S21 [dB]

S12 10

S21 60 GHz

-50

2 0

-60 0

S11

(a)

10

20 30 40 50 Frequency [GHz]

60

(b)

Figure 3-5. S-parameters are used for comparing the MOSFET fast model, slow model and the measurement data (a) S11 and S22 (b) S21 and S12

Since the amplifier, mixer and other active circuits require the MOSFET for operations, it is useful to briefly describe the MOSFET modeling for gigahertz frequencies. Figure 3-4 shows a RF small-signal model11 of an N-channel MOSFET that consists of a simple lumped network with a BSIM

RF CMOS IC Design

17

model at its core. The BSIM model characterizes the D.C. current-voltage relationship of the MOSFET and can be expressed as a function of numerous process parameters. Besides the BSIM model, inversion charge-based or surface potential models such as the HiSIM or PSP model can be considered. The lumped network, simplified in Fig. 3-4 with only the terminal resistors, Cgd, Cgs and the diodes, models the effects of the backend metal interconnects and substrate influences. The complexity of this network generally depends on how much has already been modeled in the D.C. model. To determine how strongly these effects change the characteristics of the D.C. model at high frequency, S-parameter comparisons are used. Misfits may arise from various factors, including poor gate resistance models and output conductance models. The values of the components in the network are then determined by equations that relate to these factors as well as the geometry and other design inputs. Under limited conditions, numerical fittings may be required. Figure 3-5 shows the initial correspondence of the model S-parameter characteristics and the measured S-parameter characteristics. Improving the model can then be achieved by deriving the appropriate parameters and equations that corresponds to the physical layout of the MOSFET. To allow design confidence, the measured data should fall between the fast and slow models, which represent the limits of the process variations.

2.

DESIGN TOOLS

Millimeter-wave circuits usually employ passive devices that may be a significant fraction of the wavelength. The waves that propagate in these devices have associated electric and magnetic fields that determine the devices’ terminal characteristics as well as coupling effects on nearby components. These characteristics have to be quantified to enable device modeling, layout evaluation or new structure designs. To obtain field distributions and associated scattering parameters, it was necessary to calculate for the solutions of complex electromagnetic equations. However, this task has been greatly simplified with the use of simulation software. The EM software used in most of the works in this book is made available by Ansoft and Agilent such as the High Frequency Simulation Software (HFSS) and ADS Momentum. Sonnet’s Microwave Studio and AWR’s Microwave Office are among others that are also available. Generally, a trade-off between the different simulators is the required simulation time and the accuracy of the results. Sample screen captures of the inductor simulations used in Chapter 4 are illustrated in Figs. 3-6 and 3-7.

18

Chapter 3

Figure 3-6. Ansoft HFSS 3-D EM simulation software for designing passive structures

Figure 3-7. Agilent Momentum 2.5-D simulation software for evaluating layouts

RF CMOS IC Design

19

Figure 3-8. Agilent’s Advanced Design System (ADS) uses the harmonic balance simulator

In addition to obtaining the characteristics of devices used in circuits, it has also become necessary to use simulation software to design and evaluate the circuits itself. Various electronic design-aided (EDA) tools are available today for circuit designers and they broadly fall into one of three categories: transient, periodic steady state (PSS) and harmonic balance. The PSS algorithm is effectively an RF simulation extension to a transient simulation engine, if a periodic signal is assumed to exist in the system. This method has been implemented by the commercial SpectreRF of Cadence Design System. The harmonic-balance engine is a pure frequency-domain approach. If the input signal is small enough that nonlinear elements in the circuit do not significantly distort the signal output, then the small-signal simulation gives valid results. However, as the input signal becomes increasingly large, new frequencies appear at the output. Harmonic balance solves for each of the new frequencies. The Advanced Design System software implements this method and is used in most of the works in this book (Fig. 3-8). As a result of the diversity, the choice of the simulation software will greatly depend on the circuit the user wants to simulate, including factors such as the complexity, frequency of interest and the device models available. This book will not focus on the best choice of software. Instead, most of the works in the following chapters will aim, in part, to develop models for accurate simulations.

20

Chapter 3

Figure 3-9. Cadence layout design tool is used for the physical chip layout

Figure 3-10. Visualizing the physical structure of the IC is the key to successful analog RF layout design12

After the circuit is designed and verified by simulations, the circuit has to be placed by layout on the chip that is to be fabricated. This is done by using a layout editing software and commonly used software is the Cadence’s IC Layout Editor, with its screen-capture shown in Fig. 3-9. The layout editor processes the layers drawn into a gds file format for creating the mask used in the lithography process. The lithography process is an important step in

RF CMOS IC Design

21

the chip fabrication that eventually results in physical structures in the chip. Figure 3-10 shows the structures of the metal interconnects using the stateof-the-art 45 nm process.12 For high frequency circuit layouts, it is necessary for the designer to understand and take steps to avoid possible sources of parasitics associated with the substrate and the interaction between different metal layers. Variations in the layout from the circuit schematics should also be carefully evaluated to determine the impact on performance. To accomplish these, it may be useful to view the circuit layout as 3D physical structures.

3.

MEASUREMENT EQUIPMENT

To verify the characteristics from fabricated chips, precision measurement equipment for high frequencies are used. Since the specific type of measurements to be made depends on the circuit type, only a brief description of the most important equipment will be described here. Among these, the vector network analyzer (VNA) is used for measuring the scattering parameters. The scattering parameters are useful descriptions of the circuit’s port characteristics based on the interaction of the ports’ transmitted and reflected voltage waves. The VNA primarily makes low-power measurements in order to keep the device-under-test (DUT) linear. Figure 3-11 shows the setup of the VNA with the on-wafer probe station.

Figure 3-11. On-wafer probe station for S-parameter measurements with frequency extension up to 110 GHz

Chapter 3

22

The probe station lowers the contact probes onto the pads designed on the chip for input and output connections. The size of each pad is typically less than 150 ȝm×150 ȝm. A close-up view of the probes is shown in Fig. 3-12. For measurements of multi-port devices such as baluns, a fourport VNA can be used instead. Operation of the VNA requires an initial calibration step using one of the established standards: • Short-Open-Load-Through (SOLT) • Through-Reflection-Load (TRL) • Load-Reflection-Match (LRM)

Figure 3-12. Close-up view of a four-probe setup

The calibration is required to define the exact location of the points between where the measurement data should be taken.

Figure 3-13. (a) signal generators; (b) setup for power measurements with signal generators, spectrum analyzer and source modules connected

RF CMOS IC Design

23

Figure 3-14. Front panel of a noise figure analyzer

Measurements of power characteristics are performed on high powered devices that cannot be accurately measured by the VNA. Measurements are difficult because any “frequency sweep” in the power measurements must carefully take into account the corresponding equipment, cable and probe losses at the frequency. The setup depends on the type of circuit to be measured, but will primarily consist of signal generators, shown in Fig. 3-13(a), the spectrum analyzer, harmonic mixers, millimeter-source modules and the D.C. power supply. Measurements are conducted using the on-wafer probe station using calibrated cable lengths for connections in the setup, demonstrated in Fig. 3-13(b). Noise measurements are important for the receiver characterizations as noise contributed from the circuits affect the quality of the received signals. For noise figure measurements, the noise figure analyzer (NFA) such as the Agilent N8975A of Fig. 3-14 can be used. The NFA drives a calibrated noise source into the DUT and calculates the contribution from the DUT itself to obtain the noise figure. For high frequency measurements, a harmonic mixer to down-convert the frequency is required.

PART 2

MILLIMETER-WAVE CMOS PASSIVE DEVICES

Chapter 4 ON-CHIP INDUCTOR

On-chip inductors remain in millimeter-wave CMOS circuits since gigahertz circuits, where inductors are typically used, comprise part of the millimeterwave system. Therefore, the first passive component to be carefully studied in this work is the CMOS on-chip inductor. This component is employed in the low gigahertz parts of the transceiver and is commonly used in analog RFICs. In the design of the transceiver, accurate active and passive models are necessary to predict the real performance of the circuits. The on-chip inductor suffers from substrate losses due to the high conductivity of the silicon. This loss must be accurately modeled through detailed analysis using simulations and qualitative expressions. In particular, it is useful to clarify the factor determining the performance of inductors through an analysis based on the electrical equivalent-circuit model.13– 14

1.

PHYSICAL PHENOMENA IN THE ON-CHIP INDUCTOR

To assess the performance of inductors, simple and accurate modeling of an inductor to account for physical phenomena is imperative. Here, the major physical phenomena to be considered for on-chip inductors are as follows. 1. According to skin and proximity effects, current will not flow uniformly in wiring and resistance increases with increasing frequency.15 2. When the current flowing in wiring becomes less uniform with increasing frequency, inductance decreases.16

27

Chapter 4

28

3. In the case of a low-resistivity substrate, a large current flows in a substrate due to capacitive coupling between the wirings and the substrate with increasing frequency. Moreover, an eddy current also flows in the substrate by magnetic coupling. In particular, it is known that the influence of the eddy current cannot be disregarded when the resistivity of the substrate is below 1 ȍ·cm.17

2.

EXISTING INDUCTOR MODELS

(a)

(b)

Figure 4-1. General types of existing models to represent the on-chip inductor; (a) pi-model for skin and proximity effects (b) pi-model for the eddy currents with separate networks

A brief review of existing equivalent-circuit inductor models is presented here. Figure 4-1(a) shows the single-pi model16, 18 that considers the skin and proximity effects. In this model, the additional inductor Lsk and resistor Rsk connected in parallel to the resistor Rs model the skin and proximity effects. Figure 4-1(b) considers the eddy currents.19 Here, the substrate network separated from the wiring network models the eddy current. Both equivalent circuits are based on pi-type models as shown in Fig. 4-2(a), where í Y21 between terminals is determined by parameters such as Ls, Rs, Rsk, Lsk, and Cs for the case in Fig. 4-1(a).20 In the pi-type model, wiring resistance, increasing with frequency according to the skin and proximity effects, is considered as Re(í1/Y21), which is named equivalent terminal resistance (ETR), hereafter. However, as shown in Fig. 4-2(b), the ETR, calculated from the measurement of an inductor, begins to decrease with increasing frequency.

On-Chip Inductor

(a)

29

(b)

Figure 4-2. Single pi-model characteristics; (a) schematic block diagram of the pi-type models; (b) Comparison of Re(1/Y21) obtained by measurement and simulation of pi-model

One attempt to explain the phenomenon of the ETR decreasing with increasing frequency is a two-pi model of Fig. 4-3. It assumes distributed characteristics.17 However, the two-pi model has a singular point above the resonance frequency. This is a point where the prediction of the impedance is too low and its effect is explained through a circuit example in Section 4.6. Hence, it cannot fully explain the physical phenomenon, particularly in the case of a low-resistivity substrate. Similar variations of the above models such as those in Fig. 4-4(a) and (b) have been reported21, 22 respectively.

Figure 4-3. Extended two pi inductor model

Chapter 4

30

(a)

(b)

Figure 4-4. Alternative on-chip inductor models

The model of Fig. 4-4(a) uses a Reddy and Leddy loop to estimate the current crowding effects of the metal coil. This model is based on the two-pi topology. The model of Fig. 4-4(b) models the substrate resistance but it does not consider the reduction of the inductance due to the coupling of the eddy current. Effectively, it is based on the single-pi model. We have proposed the substrate-coupled model23 that includes a substrate network to model the eddy current as shown in Fig. 4-5. This model can account for losses generated in both the vertical and horizontal directions as the current flows through the low-resistivity substrate. This is an improved model over single-pi model because of the accurate ETR prediction at high frequency and over the more advanced two-pi model because of its simplicity in parameter extraction and the absence of the singular point. Figure 4-6 illustrates how the substrate-coupled model compares with the others.

Figure 4-5. Equivalent circuit model of an inductor based on substrate phenomena

On-Chip Inductor

31

Figure 4-6. The substrate-coupled inductor model with a substrate network has distinct advantages over the other existing models

In the following sections, the substrate-coupled model will be described in more detail by explaining the physical phenomenon of the on-chip inductor. Simulation and measurement results are then compared to verify this model. The effects of the substrate eddy current under an on-chip inductor coil have often been studied and numerically modeled. However, no closed-form expressions for a precise model are available for the resistance and inductance of this eddy current because it is a complex function of both the process parameter and geometry. Subsequent sections will describe the method to implement the model with data-fitted equations that are scalable with geometry. Finally, the impact of the model accuracy upon performance evaluation will be studied through examples of the VCO and LNA.

3.

SUBSTRATE-COUPLED INDUCTOR MODEL

In the substrate-coupled model shown in Fig. 4-5, the circuit elements enclosed with the dotted line have improved the conventional pi-model. In this circuit, Cox1 and Cox2 are the capacitances between the wiring and the substrate, and Csi1 and Csi2 are the substrate capacitances. Rsi1 and Rsi2 are the substrate resistances in the z-axis direction; Ls and Lsk are the wiring inductances; Rs and Rsk are the wiring resistances describing the skin and proximity effects. However, Rsk and Lsk can be absorbed into Rs and Ls for practical implementation reasons; and Cs is the capacitance between terminals. Here, Rsub and Lsub denote the substrate resistance and inductance in the ș-axis direction, and k is the coupling coefficient of Ls and Lsub. Since the eddy current and the current in the z-axis direction flow in the same substrate, their networks merge differently. The current that flows in the

Chapter 4

32

substrate network composing of Rsub and Lsub is in the opposite direction to the current that flows in the wiring network composing of Rs, Rsk, Ls and Lsk as a result of mutual inductance. Consequently, this current decreases the ETR of the inductor. Hence, this additional substrate network is required as previous single-pi models show a discrepancy of exceedingly high values for ETR at high frequency. At low frequency, however, since the substrate network has little linkage with the wiring network through Cox1 and Cox2, the eddy current has no discernible impact on the ETR. At high frequency, on the other hand, the linkage through Cox1 and Cox2 is strong and the reduction in ETR appears notably in spite of the skin and proximity effects.

Figure 4-7. Cross-section of an on-chip inductor

The cross-section of an on-chip inductor is shown in Fig. 4-7. In the following discussions, cylindrical coordinates are used, where the r- and ș-axes correspond to the radial and angular directions of the inductor, respectively, and the z-axis corresponds to the vertical direction of the substrate. The substrate network between each turn exists in the r-axis direction, and that between substrate surface and ground exists in the z-axis direction. Moreover, the substrate network of the eddy current flowing in the substrate exists in the ș-axis direction. When substrate resistivity is low, a large eddy current flows. Since the electric field of the negative direction of the ș-axis is larger than that of the r-axis direction, the current flow in the r-axis direction is neglected and only that in the ș-axis direction is considered for simplicity. This new inductor model of Fig. 4-5 considers the eddy current by mutual coupling between the inductances of the wiring and the substrate.

On-Chip Inductor

4.

33

EQUATIONS FOR THE SCALABLE MODEL

For simplified implementation of the substrate-coupled model, the following model is used:

Figure 4-8. Simplified substrate-coupled inductor model suitable for use in circuit simulations

Rsk and Lsk, partially representing the skin and proximity effects are absorbed into Rs and Ls without any loss in accuracy. This can be seen from the results of the fitting in the following discussion. The series inductance Ls, using monomial expression24 is given in Eq. (4-1):

L s = β 1d out a1 w b1 s c1 n d 1 d avg e1

(4-1)

dout is the outer diameter of the coil, w is the width of the conductor, s is the space between the conductors, n is the number of turns and ȕ1, a1, b1, c1, d1 and e1 are the constants depending on a fabrication process. For the 0.35 ȝm process used in this work, the coefficients are obtained and shown in Table 4-2(a). For the 0.15 ȝm SOI process, the coefficients are obtained and shown in Table 4-3(a). These coefficients have been extracted using the minimum square fitting technique by Eq. (4-2) on the logarithm of Eq. (4-1) from simulated results.

) − log β − a log(d ) ªlog (L ¦ ««− b log(w ) − c log(s ) − d log(n ) − e N

k =1

measured , k

¬

1

k

1

1

k

out , k

1

1

k

º »→0 » 1 log (d avg , k )¼

(4-2)

Chapter 4

34

N represents the number of data sets over the design range. Lsub represents the eddy current flowing in the substrate. It is noted that the induced eddy current in the substrate is effectively circulating as a coil with a certain dimension. This effective coil, however, appears as a single coil consisting of indistinguishable number of turns. Figure 4-9 shows the finite element simulations of an inductor using Ansoft HFSS showing the eddy current in the substrate.

Figure 4-9. Eddy current induced by the metal coil of inductance Ls, circulating in the lowresistivity substrate. This current loop can conceptually be viewed as an effective coil

Generally, we have to consider the effective dimensions of outer diameter, conductor width, conductor space and number of turns of the eddy current coil. Although it is difficult to determine these parameters directly, the variation of the eddy current dimensions is considered to scale with the dimensions of the conductor as shown in Fig. 4-9. Using this assumption, Lsub is approximate by Eq. (4-3). Lsub = β 2 d out a2 wb2 s c2 n d 2 Ls e2

(4-3)

The extracted coefficients are shown also in Tables 4-2(a) and 4-3(a). An expression for the substrate resistance was reported17 that describes Rsc, the resistance of the electric coupling of the lines in the substrate in Fig. 4-3, is shown in Eq. (4-4).

Rsc =

1.5 × ρ ⋅ n ⋅ ( w + s ) l ⋅t

(4-4)

On-Chip Inductor

35

In the equation, ȡ is the substrate resistivity, l is the conductor length and t is the substrate thickness. A general, monomial equation of Rsub can be fitted.

Rsub = β 3n a3 ( w + s) b3 l c3

(4-5)

Equation (4-5) provides a good approximation where the coefficients are shown in Tables 4-2 and 4-3. The coupling coefficient, k, is also difficult to be extracted directly in a closed-form function. Figure 4-10 shows the values of the k curve as a function of the number of turns.

Figure 4-10. Sample variation of k with the number of turns for dout = 250 ȝm, w =15 ȝm and s=1 ȝm

Here, k is approaching to 0 when the various dimensions fall to zero; and approaching to 1 when n increases to infinity. For practical purposes, the range of validity is limited to the span of the inductor dimensions tested. Equation (4-6) approximates this relationship.

k = 1 − e β 4n

a4

d out b4 wc4 s d 4

(4-6)

The other circuit elements are given by equations previously reported.25 A summary of the required equations for the model is shown in Table 4-1, where Ka, Kb, Kc, Kd and Ke represent the process and material constants. These values can be determined by curve fitting when no material parameters of a process are known. The sequence of the coefficient extraction steps are as follows:

Chapter 4

36

1. Simulation programs such as ASITIC13 is first set up with the correct technology parameters and verified. 2. Simulations are made over a range of inductors. 3. Using the S-parameters, the parameter values of the substrate-coupled model are each numerically extracted. This includes the values of Ls, Lsub, Rsub and k. 4. Using the values of Ls, Lsub, Rsub and k, together with their geometry, the coefficients of the expressions are extracted using linear optimizations on the least-square fitting method. Other parameters are initially predetermined by existing equations for the single-pi model. They can then subsequently be more accurately characterized by expressions involving the geometry parameters.

Table 4-1. Summary of model parameters.

Cs Rs Cox1, Cox2 Rsi1, Rsi2 Csi1, Csi2 Ls Lsub Rsub k

K an ⋅ w2

K bl / w K cl ⋅ w

K d / (lw) K el ⋅ w

β 1 d out a1 w b1 s c1 n d 1 d avg e1 β 2 d out a 2 wb2 s c 2 n d 2 Ls e2

β 3 n a ( wa 4 + sb4) b c4l cd 4 3

1− e

3

3

β 4 n d out w s

In order to obtain the coefficients of the above expressions, a range of 72 inductors with various geometries have been simulated using ASITIC that evaluates the Green’s function.26 The model parameters are then optimally extracted from the generated S-parameters. This array of geometry and the model parameters, Ls, Lsub, Rsub and k, is applied to the above equations to obtain the coefficients by numerical fitting. For example, to evaluate the expression for Ls, we first extract the circuit parameters from the Sparameters. The circuit parameters are extracted according to the following procedures. The equivalent circuit shown in Fig. 4-5 is divided into six groups as shown in Fig. 4-11.

On-Chip Inductor

37

Figure 4-11. Schematic block diagram of the substrate-coupled model

Assume that Y4 Ѧ Y6 and Y3 Ѧ Y5 in Fig. 4-11, we obtain Eq. (4-7). Y11 + Y21 = (Y3-1 + Y4-1)

(4-7)

Equation (4.7) shows that Y11 + Y21 correspond to a series combination of Y3 and Y4 comprising Cox1, Csi1, and Rsi1, as in the case of the pi-type models in Fig. 4-1(a) and (b). Similarly, Y22 +Y12 is equal to the series combination of Y5 and Y6 comprising Cox2, Csi2, and Rsi2. Using parameters from Y3 to Y6, Cox1, Cox2, Csi1, Csi2, Rsi1 and Rsi2 are extracted. After these parameters are extracted and the constraint on Ls, Rs, Lsk and Rsk is derived from the lowestfrequency data, the remaining parameters are extracted using a circuit optimizer. Then, consider the expression for Ls. L s = β 1 d out a1 w b1 s c1 n d1 d avg e1 log ( L s ) = log ( β 1 ) + a1 log ( d out ) + b1 log ( w ) + c1 log ( s ) + d 1 log ( n ) + e1 log ( d avg ) M inim ize Ÿ log ( L S ) − log ( β 1 ) − ... − e1 log( d avg )

(4-8) Through linear optimization using solvers such as Microsoft Excel or Matlab, ȕi, a1, b1, c1, d1, e1 can be obtained using N=72 different values of log(Ls) and corresponding values of log(dout), log(w), log(s), log(n) and log(davg). Consider also the simplified case if dout, w, s and davg are held constant. L s = β 1 ' n d1

log (L s ) = log (β 1 ' ) + d 1 log (n )

(4-9)

Chapter 4

38

Thus log(ȕi) and d1 can be obtained through a linear fit through log(Ls) against log(n) as in Fig. 4-12. The summary of the coefficients from fitting is given in Table 4-2 and Table 4-3 for CMOS 0.35 ȝm, Table 4-4 and Table 4-5 for SOI 0.15 ȝm processes. Table 4-2. Coefficients for data-fitted monomial expressions for CMOS 0.35 ȝm process. Model Parameter

ȕi –4

Ls Lsub Rsub k

2.50×10 6.18×10–7 156 –4.85×104

ai

bi

ci

di

ei

1.84 0.94 1.36 0.91

–0.76 4.13 0.93 –1.96

–0.14 –1.06 –1.40 –0.83

1.10 –1.90 – 0.56

– 1.35 – –

Table 4-3. Coefficients for other circuit elements for CMOS 0.35 ȝm process.

Ka [fF(ȝm)–2]

Kb [ȍ]

Kc [fF(ȝm)–2]

Kd [ȍ(ȝm)2]

Ke [fF(ȝm)–2]

0.0415

0.0302

4.28×103

8.04×106

2.10×10–4

Table 4-4. Coefficients for data-fitted monomial expressions for SOI 0.15 ȝm process. Model Parameter

Ls Lsub Rsub k

ȕi

ai

bi

ci

di

ei

10–4 10–6 39 –4.90×104

2.31 0.98 1.30 2.6

–1.47 4.39 0.93 –2.12

–0.08 –0.99 –1.40 –0.98

1.24 –1.84 – 1.60

– 0.68 – –

Table 4-5. Coefficients for other circuit elements for SOI 0.15 ȝm process.

Ka [fF(ȝm)–2]

Kb [ȍ]

Kc [fF(ȝm)–2]

Kd [ȍ(ȝm)2]

0.0895

0.0466

2.93×10–3

3.03×107

Ke [fF(ȝm)–2] 2.10×10–4

On-Chip Inductor

39

Figure 4-12. Optimal linear fitting can be used to obtain the coefficients of the multi-variable function

5.

EXPERIMENTAL RESULTS

For measuring the inductors, the Anritsu 37397 vector network analyzer is used together with the on-wafer probe station. Cascade Microtech groundsignal-ground (GSG) probes are used. Short-Open-Load-Through (SOLT) calibration method is used. To verify the proposed model, several inductors with symmetric octagonal designs have been fabricated on the basis of 0.35 ȝm CMOS process, where the inductors are formed with the top-layer metal. The dimensions of the inductors are summarized in Table 4-6 for the CMOS 0.35 ȝm process. Table 4-6. Dimensions of fabricated inductors on CMOS 0.35 ȝm process.

#1 #2 #3 #4 #5

dout [ȝm] 200 300 250 200 350

w [ȝm] 10 15 10 10 10

s [ȝm] 5 5 5 1 3

n 4 5 5 4 4

After measuring inductors using a vector network analyzer, the parasitic capacitances and resistances of pads and leads are de-embedded using the open- and short-dummy patterns to extract the S-parameters of the inductor core. The comparison results between the simulation and the measurement on ETR are shown in Fig. 4-13 for diagnosis. Here, the proposed model describes well the reduction in ETR which cannot be explained with the

Chapter 4

40

conventional model since the conventional model does not consider the eddy current adequately. The comparison results of S11 and S21 using the measurement and the simulation are shown in Fig. 4-14. The solid line indicates the simulation with the proposed model and the dashed line indicates the simulation with the conventional model. While the proposed model indicates good agreement with the measurement up to 10 GHz, the conventional model shows discrepancy above 3 GHz.

Figure 4-13. Comparison of the ETRs between the measurements and simulations using samples #1, #3 and #5. Dimensions correspond to Table 4-6 for the CMOS 0.35 μm process

Figure 4-14. Measurement and simulation results of S11 and S21 of #3

On-Chip Inductor

41

Figure 4-15. Q-factors of measured, substrate-coupled model and the two-pi model of #3

Figure 4-16. Inductances of measured, substrate-coupled model and the two-pi model of #3

Figures 4-15 and 4-16 compare the models with the measured Q-factor and inductance respectively. Shown in Fig. 4-15, the Q-factor of the substrate-coupled model corresponds closely to the measurement results. The sample data shown is taken from the 0.35 ȝm-process inductor #3. The two-pi model, on the other hand, deviates from the measured result at the singular point near 7.2 GHz. In Fig. 4-16, the inductances obtained by the substrate-coupled model are shown in the same plot with the measurement results. With the two-pi model, however, the singular point causes a slight overestimate. Figure 4-17 shows the micrograph of the symmetric inductors that are successfully characterized with the substrate-pi model of Fig. 4-8.

Chapter 4

42

din

dout

Figure 4-17. Micrograph of the inductors

Characterization is also made on inductors fabricated on Silicon-OnInsulator (SOI) 0.15 ȝm process. Table 4-7 shows the dimensions of the inductors. Table 4-7. Dimensions of fabricated inductors on SOI 0.15 ȝm process.

#1 #2 #3

dout [ȝm] 96 122 148

w [ȝm] 10 10 10

s [ȝm] 3 3 3

n 2 3 4

Figures 4-18 and 4-19 shows the results of the SOI 0.15 ȝm process inductors.

Figure 4-18. Comparison of Q-factor predicted by the measured results and the substratecoupled model of sample inductor #3 from the SOI process

On-Chip Inductor

43

Figure 4-19. Comparison of inductance predicted by the measured results and the substratecoupled model of sample inductor #3 from the SOI process

6.

CIRCUIT PERFORMANCE

The substrate-coupled inductor model is analyzed in a LC oscillator circuit. Since the tank impedance can also be accurately predicted by the conventional single-pi model, a measure of the power consumption can demonstrate the advantage of predicting the ETR correctly. The oscillator used for comparison is shown in Fig. 4-20.

Figure 4-20. Schematic of an LC oscillator

From measurement, the oscillation frequency at which the maximum Qfactor occurs is used. The output of an oscillator is adjusted by bias current so that the output amplitude may give 0.32 V, which is the amplitude of 0 dBm in the case of a 50 ȍ load. The simulation results are summarized in Table 4-8, where the power consumption estimated from numerical measurement data is listed for reference. The estimated error of power consumption is less than 20% when using the model in consideration of the

Chapter 4

44

eddy current. On the other hand, the conventional model overestimates power consumption by more than 100% of the result obtained by the measurement. Table 4-8. Power consumption as a measure of oscillator performance.

Power consumption [mW] % error

#1 #2 #3 #4 #5

Oscillation frequency [GHz]

reference

Substratecoupled model

Pi-model

7.6 4.4 5.8 5.9 3.7

0.69 0.63 0.50 0.82 0.59

0.80/+15.9% 0.75/+19% 0.55 /+10% 0.80 /–2.4% 0.69 /+16.9%

2.03/+196% 2.03/+225% 2.05/+312% 1.62 /+99% 1.88 /+221%

In order to further evaluate the performance of the inductor model, the harmonic components generated in the circuit is estimated. An amplifier is designed to operate at 2.4 GHz in the schematic diagram of Fig. 4-21. The matching inductors are chosen as 6.3 nH. The output performance of the circuit is compared by using the different inductor models and the measured inductor.

Figure 4-21. Amplifier schematics employing the use of two 6.3 nH inductor models at the input and output matching networks

On-Chip Inductor

45

Circuit using measured inductor

Circuit using two-pi model

0

Pout (dBm)

Pout (dBm)

0

Freq=7.2GHz Vout=-54.25dB

-80

Freq=7.2GHz Vout=-72.25dB

-80 1

2.4

4.8

7.2

10

2.4

1

Frequency [GHz]

4.8

7.2

10

Frequency [GHz]

Circuit using substrate-coupled model

Pout (dBm)

0

Freq=7.2GHz Vout=-58.08dB

-80 1

2.4

4.8

7.2

10

Frequency [GHz]

Figure 4-22. Spectrum outputs of the circuit employing different inductor models in the matching networks

Using the proposed extraction method allows us to obtain the equivalent substrate-coupled inductor model used in the circuit. The model parameters of the two-pi model, on the other hand, are first extracted using known methods17. The resulting output spectrum of the circuit is shown in Fig. 4-22 for both models, compared with the measured inductor. As shown in Fig. 4-22, the substrate-coupled model does not underestimate the spectral power of the third harmonics as much as the two-pi model does. For nonlinear circuits that utilize the third harmonics, this particular case demonstrates the advantage of this substrate-coupled model.

Chapter 4

46

S11

Measurement Simulation

singular point freq=7.2GHz S21

Frequency (0 to 10GHz)

Figure 4-23. The singular point can be observed at 7.2 GHz with the two-pi model

This discrepancy of the two-pi model is a result of the singular point that is observed in Fig. 4-23 when S11 is plotted on the smith chart. This singular point falls on f=7.2 GHz in this case as a result of the mid-branch of the twopi model. Since the substrate-coupled model does not contain this branch, it does not suffer from this problem. As a result, although the fundamental frequency of the amplifier is way below this singular point at 2.4 GHz, the third harmonics is adversely affected. This example shows that the singular point from the two-pi model does affect the prediction of the circuit performance. Specifically, it demonstrates the importance of predicting performance beyond the self-resonant frequency. The proposed model can predict the harmonics of the LNA accurately because the ETR, in addition to the inductance can be accurately predicted.

7.

CHAPTER SUMMARY

A substrate-couple inductor model is proposed. The model takes into account the effects of the eddy current flowing in the substrate under the metal coils. This effect is described by the reduction of the ETR with increasing frequency which cannot be explained by the conventional pimodel. The accuracy of the model has been proven with good fitting of the quality factor and inductance over a wide bandwidth. The accuracy of the inductor model affects the prediction of the power consumption of an LC

On-Chip Inductor

47

oscillator and the harmonics of the LNA. Measured results show an overestimation of more than 100% in the case of an LC oscillator when the conventional model is used. Simulation results of the LNA show an unrealistic 15 dB reduction of the third harmonics when the conventional model is used instead of the substrate-coupled model. To make practical use of this model, scalable expressions in terms of geometric parameters are required. These expressions are derived with least-square fitting methods on the coefficients of monomial expressions. The coefficients of the expressions are verified using field-solver simulations and fabricated inductors. The Q-factor and inductance of the extracted model corresponds well with measured results. Successful characterization of fabricated inductors with the substrate-coupled inductor model has been made on the CMOS 0.35 ȝm and SOI 0.15 ȝm process technology.

Chapter 5 ON-CHIP CAPACITOR

The capacitor is a device for storing electrical energy and is required for tuned resonators, D.C. blocks and various charge storing circuits. In millimeter-wave CMOS circuits, modeling of the capacitors is inevitable for robust design. With the CMOS process technology, capacitance can be obtained from the MOS and on-chip passive devices. MOS capacitors can be used to provide low capacitance but become unwieldy when large capacitance values are required. The on-chip passive capacitors include the metal-insulator-metal (MIM) capacitor that is constructed from a thin insulation film between two plane metals.27, 28 They also include the comb capacitor that uses metals in the same plane as finger structures.29–34 A MIM capacitor has the advantage of being insensitive to the silicon substrate since the electric field is largely enclosed between the upper metal layers that make up the capacitor. However, MIM capacitors do not follow process scaling because the capacitance is inversely proportional to the insulator thickness, which does not scale according to process technology. As a result, since the area occupied by capacitors become relatively large as CMOS process technology progresses, MIM capacitors using parallel metal plates will not be used in the advanced CMOS processes. On the other hand, comb capacitors can be used in the pure digital CMOS process technology at no extra cost if embedded with any accompanying digital logics. In addition, large capacitance per unit area can be obtained by feature miniaturization through process scaling. Consequently in sub-100 nm CMOS process technologies, comb capacitors will be widely employed in frequency matching circuits, D.C. blocks, analog-to-digital converters (ADC), digitalto-analog converters (DAC) and other circuits. However, comb capacitors are sensitive to the low resistance of silicon substrate through the parasitic

49

Chapter 5

50

capacitive couplings between the substrate and the metal of the comb capacitor.34 To reduce parasitic capacitances for high-frequency performance, a comb capacitor with floating shields is proposed in this work. This paper will first evaluate the effectiveness of the comb capacitor shield with results verified by simulations. With the shield, the quality factor (Q-factor) of the differential signals in the proposed comb capacitor is increased by 20% at 30–110 GHz, compared to a conventional comb capacitor. An electromagnetic 3D field simulator has been used for the evaluation. In order to use the proposed capacitors in circuits, a scalable model of up to millimeterwave frequencies has been developed. The r.m.s. errors of the model’s simulated common-mode and differential mode S-parameters are under 2.1% of their corresponding measured values. With this model, the shielded comb capacitor is expected to be useful in future millimeter-wave designs.

1.

ANALYSIS OF THE FLOATING SHIELD

Although a comb capacitor was proposed as a solution for advanced CMOS processes, performance of the capacitor is sensitive to the conductive substrate because it acts as a plate terminal of a capacitor formed across the dielectric under the bottom metal of the comb capacitor. Nevertheless, the Q-factor of the capacitor is sufficiently high in the frequency range of a several mega-hertz to low gigahertz since the effect of this parasitic element is small.28 However, the low substrate resistance and the non-negligible parasitic capacitance degrade the Q-factor of the capacitor in the millimeterwave band. To reduce the effect of the low substrate resistance, a comb capacitor with floating shields is proposed. This follows similar methods of reducing the eddy current causing the substrate effect for the inductor and the transmission line by using an electric shield under the signal path.35 A comb capacitor with floating shields that has a mesh structure is proposed, as shown in Fig. 5-1.

On-Chip Capacitor

51 Floating metal shield

丵 丵丵

丵 丵丵

Port1

Port2

Top view of shield

Figure 5-1. Comb capacitor with floating shield

Figure 5-1 shows a multi-layered comb structure. The lower metal layers provide a total large surface area for higher capacitance. Since the lower metal layers are closer to the substrate, the shield is employed to reduce the eddy current from flowing in the substrate. To prevent eddy current from flowing in the shield itself, which will lead to the reduction of the inductance of transmission lines and inductors, slits are included in the shield that are perpendicular to the direction of the eddy current flow. However, for the case of the capacitor, planar shields without slits are preferred as inductance is not desired. The undesired inductance effectively reduces the self-resonant frequency of the capacitor. Hence, mesh shields, which is similar to un-patterned plane shields, are adopted to satisfy the metal density rule of the process. In addition, the shield is made floating to minimize parasitic capacitances. Although one layer is enough for the reduction of parasitic inductance, another top layer is also used for preventing outside noise since two top layers hardly contribute to capacitance increase due to large metal spaces.

Chapter 5

52 Cs

Cs

Csub R sub’

Csub

Csub R sub’

Substrate

Rs

Csub R sub’ R sub

R sub’ R sub

(a) Cross section analysis of the comb capacitor.

The effect of the substrate

(b) Conventional circuit model of the comb capacitor.

Figure 5-2. Cross section and conventional circuit model of the comb capacitor

In Fig. 5-2, Cs is the series capacitance of comb capacitor, Rs is the series metal resistance and Cox is the parasitic capacitance between the capacitor and substrate. Rsub is the substrate resistance which affects the current flowing to the ground and Rsub’ is the substrate resistance along which the current between the two ports flows. Since the resistance of the silicon substrate is much higher than that of the metal, Rsub’ is not negligible as compared to the series resistance of the metal when differential signals are applied. This results in the degradation of the Q-value. Next, the derivation of an equivalent circuit model of the comb capacitor with a floating shield is discussed. Figure 5-3 shows the schematic crosssectional view and the equivalent circuit of the shielded capacitor. The top metal layer is used for decreasing the parasitic inductance and has no significant contribution to the substrate losses. The shield used on the lower side of the capacitor, however, is made from the bottom metal layer which is closely located to the substrate. It is therefore reasonable that the power losses in the substrate occur through this shield. In Fig. 5-3, Cshield is the parasitic capacitance between the comb capacitor and the shield. Cox' is the capacitance between the shield and the substrate. Rshield is the resistance of the shield and Rsub is the resistance of the substrate. Due to the low resistance of the copper shield, Rshield is significantly smaller than the substrate resistance Rsub and can effectively be neglected, unlike the

On-Chip Capacitor

53

Cs

Rs

Cs Cshield

Cshield

R shield

Cshield

Csub’ R sub

Csub’

Substrate

R shield㻍 0

Cshield

R sub

(a) Cross section analysis of the shielded comb capacitor.

The effect of the substrate

(b) Equivalent circuit model of the shielded comb capacitor.

Figure 5-3. Cross section and equivalent circuit model of the shielded comb capacitor

unshielded capacitor model of Fig. 5-2(b). The equivalent circuit is shown in Fig. 5-3(b). It can be seen that the derived model of Fig. 5-3(b) does not contain the substrate resistance Rsub', unlike the unshielded capacitor made of Fig. 5-2(b). Therefore, the shielded comb capacitor is not affected by the lateral substrate current which should experience the resistance Rsub'. As a result, the differential signals through this shielded capacitor suffer lower losses. To verify the improvements, the Q-factors of a shielded comb capacitor and a conventional comb capacitor are compared by using the electromagnetic 3D field simulation software, Ansoft HFSS. Qdiff =

imag (Ydiff ) real (Ydiff )

(5-1)

The Q-factor for a differential signal is defined as Eq. (5-1). Here, the Y parameters corresponding to the S parameters of the differential signals are labeled as Ydiff. In the simulations, a single-layered comb capacitor is used

Chapter 5

54

and compared with another capacitor of the same design that has floating shields placed above and below it. The single-layered comb capacitor is 0.9 ȝm above the substrate. Shields, when placed in the design, are 0.4 ȝm above and 0.2 ȝm below the single-layered comb capacitor. Figure 5-4 shows the schematic device structure for 3D electro-magnetic field simulations. Vacuum

ε r = 1, μ s = 1

15 μm 5 μm 10 μm

SiO2

ε r = 4, μ s = 1 Conductivity 1000 S/m

Si

Figure 5-4. Schematic device structure for 3D electro-magnetic field simulations

Shielded 220

Qdiff Value

Conventional

180

140

100 30

50

70

90

110

Frequency [GHz]

Figure 5-5. Comparison of proposed capacitor and conventional capacitor with Q factor of differential signal

On-Chip Capacitor

55

Shown in Fig. 5-5, the differential Q-factor of the shielded comb capacitor improves by 20% from that of the unshielded capacitor at the frequency between 30 GHz and 110 GHz. Here, the capacitances of shielded and conventional capacitor are 11.5 fF and 10.9 fF, respectively.

2.

SCALABLE CIRCUIT MODEL

Figure 5-6(a) shows the proposed shielded comb capacitor structure with representations of the circuit elements as used in the equivalent circuit model of Fig. 5-6(b).

Port2

Port1

丵丵 丵

丵 丵 丵 Via

Comb capacitor part Cs Rs Lt Lt Port1 Port2 Cox Cox Ct Ct Rsub Rsub Drawing line

(a) Proposed shielded comb capacitor structure.

(b) Implemented equivalent circuit model.

Figure 5-6. Structure and equivalent circuit model of a comb capacitor with shields

The circuit model of Fig. 5-6(b) includes extension lines at the two ports. The extension lines are used for extending the core part of the comb capacitor to make external connections. In the figure, Cs is the series capacitance of comb capacitor, Rs is the series metal resistance and Cox is the parasitic capacitance between the substrate and the capacitor. Rsub is the substrate resistance that affects the current flowing to ground, while Ct and Lt are the capacitance and the inductance, respectively, of the extension lines. The following extraction methodology is presented. In order to estimate the series capacitance accurately, equations derived using the appropriate analysis have to be employed. Consider the capacitance of infinitely large conducting plates that is be given by Eq. (5-2).

C=

εA d

(5-2)

Chapter 5

56

İ is the dielectric permittivity, A is the area of the plates and d is the distance between the plates. As the fringe capacitance of the plane metals is not included in the evaluation of Eq. (5-2), it is not appropriate to be used for estimating the capacitance of the comb capacitor structure, where the fringe capacitance may be significant. Figure 5-7 illustrates the cross-section of the comb capacitor structure using three fingers at each of the three metal layers. To obtain a more accurate estimation, the center plane between upper and lower layers is treated as a virtual ground considering the mirror image effect, as shown in Fig. 5-7. The fingers above the virtual ground are now treated as parallel signal lines above the ground as shown in Fig. 5-7(b). The expressions for estimating the capacitance of parallel lines36 are applied. Here, horizontal capacitance Ccouple between the lines and vertical capacitance Caf between each line and the ground are shown in Eqs. (5-3) and (5-4) respectively.

Port1

Virtual ground due to mirror image effect

Port2

Ccouple Caf GND Estimate as microsirip lines (a) Cross section of the multilayered comb capacitor.

(b) Estimation of the capacitance as microstrip lines.

Figure 5-7. Estimation method of the capacitance

Ccouple

T§ H · = ε ox {1.144 ¨ ¸ S © H + 2.059S ¹

0.0944

1.144

W § · + 0.7428¨ ¸ © W + 1.592S ¹ W § · + 1.158¨ ¸ W + S 1 . 874 © ¹

0.1612

(5-3) 1.179

H § · ¨ ¸ H + S 0 . 9801 © ¹

}

On-Chip Capacitor

57

W S § · Caf = ε ox { + 2.217¨ ¸ H © S + 2.059 H ¹ S § · + 1.171¨ ¸ S + H 1 . 510 © ¹

0.7642

3.193

(5-4)

T § · ¨ ¸ T H + 4 . 532 © ¹

0.1204

}

W is the line width, H is the distance from the lines to the virtual ground, S is the space between lines, and T is the thickness of the lines. Cs is estimated from the results given by Eq. (5-3) and Eq. (5-4) as given in Eq. (5-5)

C s = N f ⋅ L f ⋅ N layer ⋅ ( k1 ⋅ C af / 2 + ⋅k 2 ⋅ C couple )

(5-5)

Nf is the number of fingers, Lf is the length of a finger and Nlayer is the number of metal layers used as fingers. k1 and k2 are fitting parameters for considering process variations of metal fingers and dielectric layers. It is noted that Caf is divided by two since each vertical capacitance between two fingers is the half of Caf. For the estimation of the series resistance Rs, the comb capacitor is considered as parallel lines shown in Fig. 5-8 by applying an ac current to the capacitor. Port1

Port2

Signal current It can be considered as parallel line for alternate current

Figure 5-8. Estimation of the series resistance by considering the lines as parallel for the case when A.C. current is applied

The resistance of the parallel lines due to skin effect is estimated by Eq. (5-6).

Rs =

l ⋅ N f ⋅ N Layer wσδ 1 − e− t / δ

(

)

(5-6)

Chapter 5

58 The skin depth į can be obtained according to Eq. (5-7).

δ=

2

(5-7)

ωμσ

ǚ is the angular frequency, ȝ is the permeability and ı is the conductivity. Next, we consider the estimation of the substrate resistance Rsub and the parasitic capacitance Cox. According to Eq. (5-2), it is expected that the capacitance Cox increases in proportion with the base area of the comb capacitor. Hence, Cox can be estimated using a fitting coefficient k3 according to Eq. (5-8).

Cox = k3 ⋅ Area / N f Area = N f ⋅ L f ⋅W + Sconnector

(5-8)

W is the width of a finger and Sconnector is the area of the tapered transmission line connection between the output to the exterior and the comb capacitor core. Area refers to the area of the base of the comb capacitor. The current that flows from each finger across the vertical oxide capacitance Cox and into the substrate will experience a resistance Rsub. Recognizing that Rsub decreases in proportion to the base area of the capacitor, Rsub can be defined according to Eq. (5-9) using a fitting coefficient k4.

Rsub =

k4 ⋅ N f

(5-9)

Area

The parasitic elements due to the extension lines, Lt and Ct are estimated directly from the measurement data. This inductance and capacitance of the extension lines are fitted with constants since they are not dependent on the size of a comb capacitor. Next, the extraction of the fitting parameters from measurements will be made by considering the common mode and differential mode separately. Common-mode S parameters are obtained according to Eq. (5-10).

S common =

(S11 + S12 + S 21 + S 22 ) 2

(5-10)

On-Chip Capacitor

59

Assuming that the effects of the extension lines are small, the equivalent circuit model of the comb capacitor can be drawn according to Fig. 5-9 when common-mode signals are injected into ports 1 and 2. In this case, the substrate resistance and the oxide capacitance remain while the connection between the ports 1 and 2 can be considered open since the potential difference between them is zero. Port1

Port2

Figure 5-9. Simplified common-mode model

The admittance can be obtained from the common-mode S parameters according to Eq. (5-10). The substrate resistance and the oxide capacitance can then be obtained from the real and imaginary part of the Y parameters as shown in Eqs. (5-11) and (5-12).

§ 1 · ¸¸ Rsub = real ¨¨ © Ycommon ¹

(5-11)

imag (Ycommon ) 2πf

(5-12)

Cox =

Equation (5-13) shows the differential-mode S parameters.

S diff =

(S11 + S22 − S12 − S21 ) 2

(5-13)

The Y parameters corresponding to the S parameters of the differential signals are labeled as Ydiff. Since the series capacitance Cs is large compared with Ct and Cox, the self-resonant frequency can be approximated according to Eq. (5-14).

Chapter 5

60

fo ≅

1 2π Lt C s

(5-14)

The series inductance Lt can therefore be obtained when the self-resonant frequency f0 is known. Recall that the capacitance Cs can be obtained by estimation and fitting, as had been explained.

3.

EXPERIMENTAL RESULTS

Shielded comb capacitors are fabricated and measured to verify the validity of the proposed model. Figure 5-10 is the chip micrograph of the fabricated capacitor.

Figure 5-10. Chip micrograph of shielded comb capacitor with measurement

The process used is a 90 nm CMOS 1P9M process. The metal layers from 2 to 7 are used for the fingers of the comb capacitor, while layers 1, 8 and 9 are used as floating shields. Measurement results for comparison are obtained after de-embedding using open and short test structures fabricated on the same chip, corresponding to Y and Z-parameter subtractions respectively. The extension lines from the capacitor as described in the previous section are not de-embedded as they are a necessary part of the capacitor when used in circuits and have been modeled with values of Ct and Lt. The variable parameters for design are the number of fingers Nf and the length of fingers Lf. In the fabricated structures, the numbers of fingers are 32, 60, and 90 and the lengths of fingers are 9.5, 20.7, and 30.3 ȝm. To maximize the capacitance per unit area, the line widths and spaces are selected for their minimum values.

On-Chip Capacitor

61

Table 5-1 shows the values of parameters using in this model. In addition, capacitances and resistances calculated using in this model as a function of Lf are shown in Fig. 5-11. Table 5-1. Parameters in the models.

k1 k3 Ct

k2 k4 Lt

1.046 1.74 ˜10–3 1.86 fF

1.107 9.78 ˜10–10 7.17 pH

2.0

20

,

Values of parameter using in this model Lines of Eq. (5) and (8)

1.6

16

Cs 12

1.2 Cox

Cs [pF]

Cox [fF] 8

0.8

0.4

0

4

Nf=60

0 0

10

30

20 Lf [μm]

40

(a) Cs and Cox. 25

500

,

Values of parameter using in this model Lines of Eq. (6) and (9)

400

20

15

300 Rs

Rsub [Ω]

Rs [mΩ]

Rsub 10

200

5

Nf=60 f =10 GHz

100

0

0 0

10

20 Lf [μm]

30

40

(b) Rs and Rsub.

Figure 5-11. Capacitances and resistances calculated from the proposed model as a function of Lf

Chapter 5

62

It is noted that since Rs, being estimated from Eq. (5-6), is frequencydependent resistant, values at 10 GHz were shown in Fig. 5-11. Figures 5-12–5-14 show the comparison between the model and the measurement results. This figure shows the magnitude and the phases of the S parameters in common and differential modes when the length of finger is 9.5 ȝm for 32, 60 and 90 fingers. Figures 5-15–5-17 show the magnitude and the phases

1.05

differential 1.00

|S|

0.95 0.90

common Measurement Model

0.85 0.80 0

20

40

60

80

100

Frequency (GHz)

(a) Magnitude 0

differential

∠|S| |S|

-50

Measurement Model

-100 -150

common

-200 0

20

40

60

80

100

Frequency (GHz)

(b) Phase

Figure 5-12. Comparison between measurements and model simulations for different number of fingers at Lf =9.5 ȝm, Nf =32

On-Chip Capacitor

63

of the S parameters in common and differential modes for capacitors with 60 fingers when the length of each finger is 9.5, 20.7 and 30.3 ȝm. For both cases of varying the number of fingers and varying the length of each finger, the S parameters of the models in differential mode and common mode fit well with measurement results. Through the fabrication of capacitor test structures using a 90 nm 1P9M process, it has been verified that the r.m.s. errors between model characteristics and measurements to be within 2.1% for common mode and within 1.4% for differential mode.

1.1

differential

|S|

1.0 0.9

common 0.8

Measurement Model

0.7 0

20

40

60

80

100

Frequency (GHz)

(a) Magnitude 0

differential

∠|S| |S|

-50

Measurement Model

-100 -150

common

-200 0

20

40

60

80

100

Frequency (GHz)

(b) Phase

Figure 5-13. Comparison between measurements and model simulations for different number of fingers at Lf =9.5 ȝm, Nf =60

Chapter 5

64 1.1

differential 1.0

|S|

0.9 0.8

common

0.7

Measurement Model

0.6 0

20

40

60

80

100

Frequency (GHz)

(a) Magnitude 0

differential

∠|S| |S|

-50

Measurement Model

-100 -150

common

-200 0

20

40

60

80

100

Frequency (GHz)

(b) Phase

Figure 5-14. Comparison between measurements and model simulations for different number of fingers at Lf =9.5 ȝm, Nf =90

On-Chip Capacitor

65

1.1

differential

|S|

1.0 0.9

common 0.8

Measurement Model

0.7 0

20

40

60

80

100

Frequency (GHz)

(a) Magnitude 0

differential

∠|S| |S|

-50

Measurement Model

-100 -150

common

-200 0

20

40

60

80

100

Frequency (GHz)

(b) Phase

Figure 5-15. Comparison between measurements and model simulations for different number of fingers at Lf =9.5 ȝm, Nf =60

Chapter 5

66 1.1

differential

|S|

1.0 0.9

common 0.8

Measurement Model

0.7 0

20

40

60

80

100

Frequency (GHz)

(a) Magnitude 0

differential

∠|S| |S|

-50

Measurement Model

-100 -150

common

-200 0

20

40

60

80

100

Frequency (GHz)

(b) Phase

Figure 5-16. Comparison between measurements and model simulations for different number of fingers at Lf = 20.7 ȝm, Nf = 60

On-Chip Capacitor

67

1.1

differential 1.0

|S|

0.9

common

0.8 0.7

Measurement Model

0.6 0

20

40

60

80

100

Frequency (GHz)

(a) Magnitude 0

differential

∠|S| |S|

-50

Measurement Model

-100 -150

common

-200 0

20

40

60

80

100

Frequency (GHz)

(b) Phase

Figure 5-17. Comparison between measurements and model simulations for different number of fingers at Lf = 30.3 ȝm, Nf = 90

4.

CHAPTER SUMMARY

A shield for reducing the parasitic capacitance is proposed in order to use the comb capacitor at high frequency. Using a 3D EM simulator, the quality factor (Q-factor) of the proposed shielded comb capacitor for the differential signal is found to improve by 20% at 30–110 GHz compared to the unshielded capacitor. In addition, a scalable model is presented, which is accurate up to millimeter-wave frequencies. The accuracy is

68

Chapter 5

verified by experimental data using fabricated comb capacitors from a 90 nm 1P9M CMOS process. Compared with the experimental results, the simulated common-mode and differential-mode S parameters of the model has an r.m.s. error of under 2.1%.

Chapter 6 TRANSMISSION LINES

The most interesting feature of millimeter-wave CMOS circuits is the use of on-chip transmission lines since, fundamentally, a half-wavelength on silicon at millimeter frequency is below 1 mm. In addition, the quality factor of transmission lines is usually higher than that of on-chip inductors, allowing it as a better alternative to provide inductances. As a result, utilization of the transmission lines is inevitable for realizing highperformance millimeter-wave circuits.

1.

FUNDAMENTALS

The metal interconnect is the fundamental device in a circuit which makes up all the other passive devices found on the CMOS circuit. Since high frequency CMOS devices are primarily limited by passive devices, this chapter can therefore be considered as the most important topic of this book. For millimeter-wave CMOS circuits, the metal interconnect lines used may be a significant fraction of the wavelength and therefore have to be analyzed as transmission lines. The following analysis explains the relationship between the phase velocity of the wave propagating in the lines and the equivalent elemental inductance and capacitance. This idea will be further developed in Sections 6.2 and 6.3 in the design of new transmission line structures for higher performance on CMOS.

1.1

Electric and Magnetic Field Propagations

Maxwell’s equations in differential form are given below.

69

Chapter 6

70

~ dB ~ ∇×E = − dt

(6-1a)

~ ~ dD ~ ∇×H = +J dt

(6-1b)

~ ∇⋅D = ρ

(6-1c)

~ ∇⋅B = 0

(6-1d)

~ ~ B = μH

(6-1e)

~ ~ D = εE

(6-1f)

~ ~ J = σE

(6-1g)

Equation (6-11a) can be written in phasor form, and then substitute Eq. (6-1g) into Eq. (6-1b).

~ ~ ∇ × E = − jωμH

(6-2a)

~ ~ ~ ∇ × H = jωεE + σE

(6-2b)

Now, mathematical operations will be performed on Eqs. (6-2a) and (6-2b) to obtain the wave equation. Only the derivation for E equation will be shown since the H equation derivation will be similar. Take the curl of Eq. (6-2a).

~ ~ ∇ × ∇ × E = − jωμ∇ × H ~ ~ = − jωμ jωεE + σE

(

)

(6-3)

Transmission Lines

71

~

Use the mathematical identity of the following: ∇ × ∇ × E =

(

)

~ ~ ~ ∇ ∇ ⋅ E − ∇ 2 E and realize that ∇ ⋅ E = 0 in a source free region. Equation (6-3) becomes

§ σ ·~ ~ ¸E − ∇ 2 E = ω 2 με ¨¨1 + jωε ¸¹ ©

(6-4)

§ σ ·~ ~ ¸E = 0 ∇ 2 E + ω 2 με ¨¨1 + jωε ¸¹ ©

(6-5)

Equation (6-6) is the Helmholtz equation of the form:

~ ~ ∇2 E + k 2 E = 0

(6-6)

If the electric field propagates only in the z-direction, Eq. (6-6) can be simplified to Eq. (6-7).

∂2E + k 2E = 0 ∂z 2

(6-7)

E is a function of z and can be written as E(z). The Helmholtz equation has a general solution in Eq. (6-8)

E ( z ) = E + e − jkz + E − e jkz

(6-8)

The coefficients jk of z in Eq. (6-8) is replaced by Ȗ as the complex propagation constant, where Ȗ can be expressed as Į + jȕ.

∂2E − γ 2E = 0 2 ∂z

(6-9)

The analogy between the E and H field to the voltage and current waves of a transmission line can be seen by comparing Eq. (6-9) to a similar form of expression for the voltage V obtained from the telegrapher’s equations.

Chapter 6

72

1.2

Voltage and Current Wave Propagations N

i(z,t)

LǍz

i(z+Чz,t)

RǍz

v(z,t)

CǍz

GǍz

v(z+Чz,t)

Чz Figure 6-1. Transmission line distributed model of the telegrapher’s equations

Figure 6-1 shows the transmission line distributed model of the telegrapher’s equations. Apply Kirchoff’s Voltage Law (KVL) across R and L.

v( z, t ) − i(z , t )RΔz − LΔz

∂i ( z, t ) − v( z + Δz , t ) = 0 ∂t

(6-10a)

Apply Kirchoff’s Current Law (KCL) to node N.

i ( z , t ) − v(z + Δz , t )GΔz − CΔz

∂v( z + Δz , t ) − i ( z + Δz , t ) = 0 (6-10b) ∂t

Divide Eqs. (6-18) and (6-19) by Δz and take the limit Δz → 0 .

∂v( z , t ) ∂i (z, t ) = − Ri( z , t ) − L ∂z ∂t

(6-11a)

∂i ( z, t ) ∂v(z, t ) = −Gv( z, t ) − C ∂z ∂t

(6-11b)

Transmission Lines

73

In phasor form,

dV = −(R + jωL )I dz

(6-12a)

dI = −(G + jωC )V dz

(6-12b)

Consider the voltage wave by differentiating Eq. (6-12a) with respect to z.

d 2V dI = −(R + jωL ) 2 dz dz = (R + jωL )(G + jω C )V

d 2V − (R + jωL )(G + jω C )V = 0 dz 2

(6-13)

Equation (6-13) is a second order differential form of

d 2V − γ 2V = 0, 2 dz where γ =

(R + jω L )(G + jω C) .

(6-14)

(6-15)

A similar expression can be obtained for the current wave I. Remember, nevertheless, the assumption that z tends to an insignificant fraction of the wavelength must hold. Compare this wave equation of Eq. (6-14) to the E field propagation in Eq. (6-9).

Chapter 6

74

1.3

Phase Velocity vp

ǰ

z

Figure 6-2. Phase velocity of a wave is the speed of a phase point on the wave in the direction of propagation

Figure 6-2 illustrates the changing position of a phase point on the wave in a given direction of propagation. The condition to maintain a fixed point on the wave is given by

ω t − β z = constant . z=

ω t − constant β

(6-16)

The phase velocity in terms of the wave constant is expressed in Eq. (6-17).

vp =

dz d §ω t − constant · ω = ¨ ¸¸ = dt dt ¨© β ¹ β

(6-17)

The wave constant or wave number, ȕ can be obtained from Eq. (6-15), derived from the telegrapher’s equations:

β = Im(γ ) = Im

(

(R + jωL )(G + jω C ) )

(6-18a)

Use Eq. (6-5) from the field analysis on Eq. (6-18a).

§ § σ · ·¸ ¸ β = Im(γ ) = Im¨ jω με ¨¨1 + ¨ jωε ¸¹ ¸ © ¹ ©

(6-18b)

Transmission Lines

75

Consider the lossless case by simplifying Eqs. (6-18a) and (6-18b) by using R = G = ı = 0. From Eq. (6-18a), β = ω LC

(6-19a)

From Eq. (6-18b), β = ω με

(6-19b)

Therefore, the phase velocity can be expressed by Eqs. (6-20a) and (6-20b).

vp =

1 LC

vp =

1

με

(6-20a)

=

c

μrε r

(6-20b)

c is the speed of light. The relative permeability ȝr can assumed to be 1 for non-magnetic materials such as silicon dioxide. In using the assumptions for R, G and ı for representing metal interconnects on CMOS processes, it should be noted that R refers to the series resistive losses, G refers to the leakage losses from the signal line to ground and ı refers to the conductivity of the dielectric where the leakage losses from the signal line to ground occurs.

2.

SLOW-WAVE TRANSMISSION LINE (SWTL)

In an earlier chapter, the described on-chip inductor can effectively provide required inductances at low frequency up to several gigahertz. At higher frequencies, it cannot be used due to its associated parasitic capacitances and transmission lines are employed instead. An advantage of using transmission lines is the higher quality factor (Q-factor) that can be achieved, compared to the on-chip inductor. However, the Q-factors of conventional CMOS onchip transmission lines are still low with a typical value of approximately 5.0.37 To effectively exploit CMOS at high frequency, transmission lines with high Q-factor are required. High Q lines are characterized by a low attenuation that can reduce power consumption in a circuit. It is also desirable to have lines with high phase constant, ȕ, to reduce the phase

Chapter 6

76

velocity of the waves in the lines. The resulting slow wave has low dispersion.38 One implementation of the slow-wave transmission line in the form of the coplanar waveguide39 is to use a floating shield. This method of reducing losses is very useful because it requires no additional processing steps. It is therefore useful to further develop new transmission line structures with slow-wave characteristics through layout innovations. Currently, there are several issues that need to be addressed regarding onchip transmission lines. • Less lossy lines with superior performance at high frequency are required. Specifically, lines with high Q for low loss, high ȕ for lower phase velocity of the wave, and high obtainable impedance for easy matching are required. • Proper characterization is necessary for accurate circuit simulations. Accurate models that can explain the physical phenomenon of the structure are required. The attenuation, phase constant as well as characteristic impedance of the line should be correctly predicted. • In advanced CMOS processes, stringent design rules require minimum metal densities and limited distances between planar metals. Therefore, the loop inductance of a coplanar waveguide (CPW) cannot be large, thus resulting in low impedance lines. This makes it difficult to use transmission line matching at high frequency.

2.1

Background on Slow-Wave Research

The fundamental principle on which the improved transmission line designs are based on in this work is the slow-wave phenomenon. In 1971, the relationship between the wave propagation frequency and the resistivity of the silicon substrate on which a Si-SiO2 system were reported by Hasegawa38 and summarized in Fig. 6-3. According to the measured characteristics, a slow-wave mode of propagation was identified which has desirable characteristics such as lower dispersion and losses.

Transmission Lines

77

Figure 6-3. Three propagation modes were identified experimentally in 1971

It is, however, useful and important to achieve the slow-wave mode by using innovative layout techniques on an available process. This is possible since the structure of the transmission lines determines the effective permittivity, and therefore the propagation velocity.

2.2

Realizing Slow-Wave Transmission Lines

2.2.1

The SWTL Structure

A slow-wave transmission line (SWTL) structure that satisfies the above requirements is described in this section. The lines are fabricated using a sixmetal 90 nm CMOS process. Figure 6-4 shows the basic structure of the transmission line. The features and physics of this structure are explained in detail in the following sections.

Chapter 6

78

Figure 6-4. Composite high-Q transmission line structure for advanced CMOS designs

Figure 6-5 describes the structure which includes ground metals at both sides of the signal line. Each of the ground metal structures consist of extended metal fingers orthogonal to the direction of current flow and they are connected together at a distance wg from the signal conductor. Figure 6-6 shows the cross-section of the structure.

extended (ground) metal fingers

Rgnd Rs Ls

Lgnd

Cgnd

C

wg

Rsh

Rsub Lsub

silicon H-field

slotted ground shield

Figure 6-5. Structure of the slow-wave transmission line with the currents flowing through it

No return current flows along these finger structures but will flow at a farther distance wg from the signal conductor at where the fingers join. In this way, the return ground current flows at a distance farther away in order to increase the inductance while satisfying the density rules. The typical

Transmission Lines Point of return ground current path

79

wg

Ground

12μm

wg

Signal

Ground

0.9μm 2.9μm

vias

Silicon

Region where ground current flows

Return ground current does not flows here

Figure 6-6. Simplified cross-section of the slow-wave transmission line. The electric field from the signal line will terminate at the side grounds and the bottom shield located 2.9 ȝm below it

density requirement for advanced CMOS processes is between 20% and 60% within the given size of a checking area, depending on the metal layer. This checking area is stepped through the layout. Hence, the required condition in the design of the finger structures is to fulfill these requirements by determining the most appropriate distance between the fingers and the signal line. This region will not contain any metal and will, therefore, reduce the total metal density of the checking area. The most stringent requirements can be considered with more than one CPW in the same checking area, which can be satisfied by the proposed method while maintaining proper characterization of the complete structure. In this structure, the effects of extended metal fingers can be considered as a minor reduction in the inductance of the signal lines due to eddy current in the fingers. However, due to the narrow width of each finger, the eddy current in the extended metal fingers is small and can be reasonably neglected. The ground conductors extend towards the silicon substrate and are connected to a slotted ground shield laid underneath the signal conductor. The ground shield prevents the electric field from entering the substrate while its slotted structure minimizes return current from flowing thereby

Chapter 6

80 L=

∂B ∂B ⋅A= ⋅ wg ⋅ l ∂t ∂t

H-field A: area

l

wg

Figure 6-7. The inductance L is determined by the area enclosing the magnetic field which is a function of wg

allowing wg to be the principal parameter to determine the inductance. Figure 6-7 demonstrates how the inductance, L can be affected by wg. The proximity of the shield, further, reduces the distance of the signal line to ground potential and this result in a larger capacitance. The approximate lossless relationship between the phase velocity, vp and the unit inductance, L and capacitance, C is given by Eq. (6-20a): vp =

1 . LC

It can be deduced that a lower phase velocity can be achieved when the unit inductance and capacitance are high. In general, the propagation constant Ȗ is related to L and C according to Eq. (6-15):

γ = α + jβ =

( G + jω C )( R + jω L ) .

The real part of Ȗ, Į corresponds to the attenuation of the line, and the imaginary part, ȕ is the phase constant. G and R is the unit leakage conductance from signal to ground and the unit series resistance of the signal line respectively. Consequently, the extended metal fingers and slotted ground shields changes Į and ȕ. This is verified by the measurement results in the next section.

Transmission Lines 2.2.2

81

Measurement of Fabricated Structures

Test structures are fabricated with line length, l=900 ȝm and different values of wg. Large values of wg are included to characterize its effect on the performance of the SWTL. Table 6-1 summarizes the dimensions of the fabricated test structures. Table 6-2 lists the dimensions of the common parameters. Table 6-1. Summary of dimensions of fabricated SWTL structures.

wg [ȝm] 14.0 24.0 34.0 44.0 84.0

#1 #2 #3 #4 #5

wfinger [ȝm] 4.0 4.0 4.0 4.0 4.0

Lfinger [ȝm] 0.0 10.0 20.0 30.0 70.0

sfinger [ȝm] 8.125 8.125 8.125 8.125 8.125

Table 6-2. Dimensions of other common parameters.

12.0 ȝm 14.0 ȝm 2.9 ȝm 0.25 ȝm 0.25 ȝm 0.25 ȝm

Signal conductor width, w Signal conductor to finger distance Signal conductor to shield distance Shield metal thickness, tshield Shield slot spacing, sslot Shield slot width, wslot

wfinger and Lfinger are the width and length of the metal fingers at the top metal layers, sfinger is the space between the fingers. For comparison, a coplanar waveguide (CPW) structure of Fig. 6-8 with signal-to-ground gap of 14 ȝm is also fabricated on the same chip. 14μm

Ground

12μm

Signal

14μm

Ground

0.9μm 3.55μm

Silicon

Figure 6-8. Cross-section of the reference CPW structure

Chapter 6

82 wg

Figure 6-9. Micrograph of the fabricated structure

For measurements, an Anritsu ME7808 vector network analyzer with Anritsu 3742A-EW Transmission-Reflection modules is used on an on-wafer probe station. The Transmission-Reflection modules extend the measurement frequency from 65 to 110 GHz. Figure 6-9 is a micrograph of a fabricated transmission line for wg=44 ȝm. The lines are measured with G-S-G probes on the pads at the two ends of the lines and de-embedded. De-embedding employs the open-short-through method. From the de-embedded S-parameters obtained from measurements, Eqs. (6-21) and (6-22) are then used to obtain the propagation constant, Ȗ. 40 −1

2 2 ­°1 − S11 ½° + S 21 ± K¾ , e −γ l = ® 2 S21 ¯° ¿°

(6-21)

where 1

(

)

2 2 ­ 2 2 + 1· − 2S 2 ½° ° §¨ S11 + S 21 ¸ 11 ° °© ¹ K =® ¾ 2S 21 2 ° ° °¯ °¿

(

)

l is the length of the fabricated SWTL.

(6-22)

Transmission Lines

83 wg=14 μm

㱍 (dB/mm)

8.0

wg=34 μm wg=84 μm

6.0

CPW

4.0

2.0

0.0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-10. Real part of the propagation constant, Į plotted for structures of different wg. Į corresponds to the attenuation of the lines. The plot for CPW is included for reference

Figure 6-10 plots the measured values of Į for three of the representative SWTL as well as the conventional CPW. The results show that lower attenuations are achieved for the SWTL when compared to the CPW. Up to 60 GHz, the attenuations of these lines are approximately only 50% of the reference CPW line. The higher attenuations of some lines at 65 GHz are a result of measurement errors due to employing the Transmission-Reflection modules at the switch-over frequency of 65 GHz. Comparing the SWTL of different wg, there are relatively small variations at low frequency. However, at high frequencies, lines with smaller wg perform significantly better with lower Į with up to 20% reduction in attenuation at 100 GHz between the narrowest (wg=14 ȝm) and the widest structure (wg=84 ȝm). Lines with large wg have stronger magnetic field penetrating the substrate underneath the shield at high frequency that induces a current to flow. Further increasing wg results in attenuations which approaches that of a CPW. The high frequency effect of the signals on the CPW is manifested through the substrate parasitic as the signal line of the CPW is exposed to the silicon underneath. Some of the electric field lines terminates on the semi-conducting substrate and can induce a weak return current to flow. The plot of Fig. 6-11 shows that the slow-wave transmission lines have high phase constants ȕ. The phase velocity of the wave is related to the phase constant by Eq. (6-23).

vp =

ω β

(6-23)

Chapter 6

84 15

wg=14 μm wg=34 μm

㱎 (rad/mm)

wg=84 μm 10

5 CPW 0 0

20

40

60

80

100

120

Frequency (GHz) Figure 6-11. Imaginary (ȕ) component of the propagation constant for structures of different wg. ȕ is the phase constant of the lines. The plot for CPW is included for reference

Slow-wave transmission lines have high ȕ that result in the lowest phase velocity. Figure 6-11 also shows that reducing wg will result in a value of ȕ closer to that of the CPW. This variation with wg is different from that of Į as described earlier. For transmission line resonators that are commonly used in filters, oscillators and tuned amplifiers, the resonant cavity Q41 is shown in Eq. (6-24). Q=

β 2α

(6-24)

This definition takes into account of the average energy stored, including both magnetic energy and electric energy. Figure 6-12 plots the values of Q obtained using Eq. (6-24). From Fig. 6-12, the Q-factors of all the slow-wave transmission lines are higher than the conventional CPW. The definition of Q in Eq. (6-8) can also be understood as the inverse relationship of attenuation per phase constant. In contrast to the attenuation per physical length, given simply by Į as in Fig. 6-10, Q describes the power loss in a given phase. Since the length of a transmission line is determined by the required number of wavelengths in a RF design, it is meaningful to consider the loss in a given phase. To understand the mechanism of the Q-factor variation, it is useful to consider the inductive quality factor and the capacitive quality factor42 that limits the attainable value of Q. In the case of SWTL, it is the low inductive quality factor that prevents the structures from high values of Q.

Transmission Lines

85

For the CPW which has a larger signal-to-ground distance, the capacitive quality factor is lower and the value of Q is affected by both types of quality factor. It can be seen that all SWTL have higher Q-factors when compared with the CPW. 20 wg=14 μm wg=34 μm wg=84 μm

Quality Factor

15

10

5 CPW

0 0

20

40

60

80

100

120

Frequency (GHz) Figure 6-12. Quality factors of the measured new transmission lines have higher values as compared to the Q-factor of the measured CPW fabricated under the same process conditions

The characteristic impedances of the lines are obtained from the de-embedded S-parameters according to Eq. (6-25).

ZC = Z0

(1 + S11 )2 − S 212 (1 − S11 )2 − S 212

(6-25)

Results are shown in Fig. 6-13 with values in the range of 30–50 ȍ. It can be seen that lines with larger wg have higher impedances. For the simplified lossless case approximation, ZC is given in Eq. (6-26). ZC =

L C

(6-26)

Since lines with larger wg have a higher L, lines with larger wg will result in higher ZC.

Chapter 6

86 wg=14 μm wg=34 μm

75 Re(Z䌃)

wg=84 μm

CPW

Z䌃 (㱅)

50

25

0 Im(Z䌃) -25

0

20

40

60

80

100

120

Frequency (GHz) Figure 6-13. Real and imaginary components of the characteristic impedance of the lines

2.3

Modeling SWTL

2.3.1

Equivalent Circuit Model

To employ the new transmission line structure in circuit designs, an accurate model for circuit simulations is required. The proposed model of Fig. 6-14 considers the physics of the SWTL structure. A magnetic field loops around the current-carrying conductor and penetrates the closely located silicon substrate. Hence, substrate current is induced that results in parasitic inductance and resistance. As the operating frequency increases, this substrate effect increases and becomes substantial. The electric field that originates from the signal line terminates at ground potential located at the same metal plane and at the slotted ground shield underneath the signal line. Therefore, the return current due to the electric field in the silicon substrate is significantly reduced. The electric field lines also terminate at sidewalls of the ground metals. In this structure, the return current flows primarily along the coplanar metals at a distance wg from the signal line, which also develops an inductance and resistance along its path. The return current cannot effectively flow through the slotted ground shield dividing the signal line and the substrate because of the slot spaces that prevents the flow of the return current. However, due to capacitive coupling between the slotted metals of the shield, a small current exists at high frequency. With a description of the physical processes in the structure, an equivalent

Transmission Lines

87

distributed circuit model is developed. The model of Fig. 6-14 takes into account the important effects of the substrate and ground parasitic by using simple lumped equivalent circuit elements. Ls

Rs C Lsub

Rsub

Rsh Rgnd Lgnd

Cgnd

Figure 6-14. Distributed circuit model of the slow-wave transmission line

In the model, the series inductance and resistance are represented by Ls and Rs respectively. The parasitic components include the substrate resistance Rsub, substrate inductance Lsub, resistance of the ground metal along the return current path Rgnd, the associated inductance in the ground metal Lgnd, as well as the capacitance of the slot spaces in the shield metal Cgnd. The substrate and ground inductances are coupled to the line inductance. In addition, the capacitance between the signal line and the ground metals is considered with the capacitor C. Rsh represents the resistance of the metal slots of the shield structure. This model is transformed into an equivalent model of Fig. 6-15. This model has fewer components and it explicitly demonstrates the effect of the substrate parasitic on a shielded transmission line. The resonance loop models the increasing effects of the substrate at higher frequency. In addition, this equivalent-circuit model has kept its simplicity for the purpose of practical implementation. The proposed elements Rext, Lext, M, Cgnd, and Rsh in this equivalent circuit are described. Equations (6-27)–(6-31) provides guidance to the value of the parameters used in the model. For Eqs. (6-27)–(6-29), fitting is made to the numerical parameters of k1, k2, k3 and k4. Approximations of the other parameters can be obtained by conventional analysis of the Telegrapher’s RLGC model. Rext is approximated to the substrate resistance through which the substrate current flows. Rext = k1

R, Si w

(6-27)

Chapter 6

88

RƑ,Si is the sheet resistance of the silicon underneath the signal line and w represents the width of the signal line. Lext is a result of the magnetic field generated by the signal line and is approximated by a fraction of Ls.

Lext = k2 ⋅ Ls

(6-28)

The magnetic coupling coefficient is approximated by the parametric equation of Eq. (6-29). M = 1− e

(

− k3 wg / w

)4 k

(6-29)

Cgnd and Rsh are small due to the low values of the series capacitances linking the gaps between the slotted metals in the shield and the parallel resistances of the slotted metal, respectively. The values can be approximated by Eqs. (6-30) and (6-31).

C gnd = ε ox

tshield w m ⋅ sslot

R sh = R , slot ⋅

(6-30)

2wg + w

(6-31)

2m ⋅ wslot

İox is the effective dielectric permittivity, m is the number of metal slots per meter in the shield and RƑ,slot is the sheet resistance of the slot metal in the shield. This model of Fig. 6-15 has been simulated in 80-stage cascade to evaluate the performance. To ensure the distributed characteristics of the model, the elemental stage is ensured to have a length significantly less than a wavelength of the maximum measurement frequency. Results of the modeling are explained in the next section. Cgnd Rext Lext M Lᨯ

Rs C Rsh

Figure 6-15. Equivalent model with the substrate and ground effects externally modeled

Transmission Lines 2.3.2

89

Modeling Results

Table 6-3 shows the fitted parameters used in Eqs. (6-27), (6-28) and (6-29). Table 6-3. Values of the fitting parameters.

k1 0.56

k2 0.02

k3 0.36

k4 0.42

The new parameters of the distributed model of Fig. 6-15 are calculated by Eqs. (6-27)–(6-31). Table 6-4 provides a summary of all the parameters used in the SWTL model. Table 6-4. Parameters of the proposed model for different test structures.

wg Rs [kȍ/m] Ls [nH/m] C [pF/m] Rsh [nȍ/m] Cgnd [×10-6fF/m] Rext [kȍ/m] Lext [nH/m] M

14 ȝm 2.0 379 335 4.98 4.11 5.29 9.7 0.39

24 ȝm 2.0 459 335 7.48 4.11 5.29 10.1 0.41

34 ȝm 2.0 542 335 9.97 4.11 5.29 10.8 0.43

44 ȝm 2.0 586 335 12.5 4.11 5.29 12.8 0.46

84 ȝm 2.0 819 335 22.4 4.11 5.29 13.2 0.46

Since all the test structures have the same length, the values of Rs, C, Cgnd and Rext do not change, according to the physical equations that describe them. Lext which is a result of the coupled inductance from the signal line is shown to have a value that is only a fraction of Ls with slight increases in the coupling coefficient M. A larger M results from a larger area being coupled with increasing wg. The model characteristics, using the calculated values, are then verified with the measured results in this frequency range. The objective is to show that the proposed model can be used to represent the fabricated structures.

Chapter 6

ǩ (dB/mm)

90 5.0

Measured, wg=14 μm

4.0

Distributed model

3.0 2.0 1.0 0.0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-16. Comparison of the real component of the propagation constant of a sample measured line to the model

Measured, wg=14 μm

10

Ǫ (rad/mm)

Distributed model

5

0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-17. Comparison of the imaginary component of the propagation constant of a sample measured line to the model

Figures 6-16 and 6-17 show the comparison of the attenuation and the phase constant of the fitted model and measured sample transmission line with wg =14 ȝm. The simulated results of the distributed model generally agree well with the measured results, especially at low frequency. However, excessive attenuation is not accounted for by the model at 65 GHz due to the switching-over of the Transmission-Reflection modules of the measurement setup as described earlier. Figure 6-16 shows the results of the fitted model with a sample line wg=14 ȝm, which has the worst-case 65 GHz peaking among the results of Fig. 6-10. Figure 6-17, however, shows the excellent agreement of the phase constant of the model and measured results.

Transmission Lines

91 Measured, wg=14 μm Distributed model Model with lump elements at ports

75 Re(ZC)

Z䌃 (㱅)

50 25 0

Im(ZC)

-25

0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-18. Comparison of real and imaginary components of the characteristic impedance of a sample measured line to the model

Figure 6-18 shows the simulated impedance of the lines using the proposed model and the measured results. The peaks and troughs are not due to measurement problems but are simply caused by the length of the line which reaches half a wavelength at this frequency.43 This can be seen by the S11 of the measured SWTL showing minimum return losses and zero phases at frequencies corresponding to the half-wavelength in Figs. 6-19 and 6-20 respectively. Alternatively, this effect can be modeled by lumped circuit elements at the two ports. This results in a good fit as shown in Fig. 6-18 as well. The proposed model can be used in simulations to characterize the high-Q transmission lines. The peak occurrences of the characteristic impedance at half-wavelength can be verified by the phase velocity vp of the wave through the 900 ȝm SWTL. This can be calculated at f=46 GHz according to Eq. (6-32).

vp = f ⋅ λ

(6-32)

Hence, according to Fig. 6-11 and Eq. (6-23), an equivalent value can be obtained for the sample line wg =14 ȝm, given that the half-wavelength, Ȝ/2=900 ȝm.

Chapter 6

92

࿽ S11࿽ (dB)

0

Measured, wg=14 μm

46.0 GHz

-10

-20

-30

0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-19. Magnitude of S11 of the sample transmission line showing the high return loss at 68 GHz

Measured, wg=14 μm

∠ S11 (dB)

180

46.0 GHz

90 0 -90 -180

0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-20. The corresponding phase of S11 of the sample transmission line showing the changes in phase

3.

ASYMMETRIC COAXIAL WAVEGUIDE (ACW)

The physical length to realize a given wavelength of the propagating signal of the transmission line is an important figure of merit. It is thus desired to achieve a shorter length which would allow a smaller circuit size. In order to achieve such performances, the most practical method is to employ new designs at the layout by focusing on the wavelength reduction of the

Transmission Lines

93

slow-wave phenomenon at the structure. This design method, as explained in the previous section, also allows the slow-wave CPW39 (S-CPW) and slow-wave transmission line (SWTL) structures to exhibit high quality factors. In this section, another structure for the transmission line is explained. First, a detailed description of the new asymmetric coaxial waveguide (ACW) structure is made. This is followed by a detailed explanation of how the Q-factor is analyzed with respect to conventional transmission lines. A brief review of the preceding work on SWTL is made for performance comparisons. These comparisons will be made with measured results in Section 4.3.

3.1

The ACW Structure

This structure shown in Fig. 6-21 is designed with the pad metal as part of the ground structure which encloses a signal conductor. The signal conductor of our test structure is designed with a width of 12 ȝm surrounded by ground metals on the sides as well as its top and bottom. The side ground metals are at wg =44 ȝm from the signal conductor. The top pad metal is designed with slot patterns and grounded. This thick top pad metal layer is not suitable to be used as the signal line due to Design For Manufacturability (DFM) constraints. The bottom metal is a slotted ground shield that prevents the electric field from penetrating the conductive silicon substrate. All the ground metals are connected together using inter-metal vias. Designed for our six-metal 90 nm CMOS process, dummy ground metal strips are inserted between the signal line and the coplanar ground metal. No return current flows in these dummy ground metal strips because they are not connected together in the direction of the signal flow.

return current

Top pad metal Vias

Gnd

Silicon

Signal

Gnd

wg

Figure 6-21. Structure of the ACW

Chapter 6

94

The capacitance is determined by the distance between the signal and ground potential which increases with reducing distance. The inductance is determined by the distance between the signal path and the return current path which increases with increasing distance. To achieve slow waves for the conventional microstrip line and the coplanar waveguide (CPW), a tradeoff exists between increasing both the inductance and capacitance at the same time to decrease the phase velocity vp, according to Eq. (6-20a):

vP =

1 . LC

Equation (6-20a) is considered for a lossless case to emphasize the relation between the phase velocity and the line reactances. Through innovative designs, the return current does not necessarily have to flow in the closest metal of ground potential. The ACW achieves this by keeping the capacitance large with closely-located slot metals at the top and bottom where the return current cannot effectively flow. Instead, the return current is forced to flow at a farther distance at the sides. This results in a large inductance, as illustrated in Fig. 6-22.

L=

C =ε

∂B ⋅ A1 ∂t

Electric field Bottom of pad metal Magnetic flux B

A1

A0 d0 d0

B: Magnetic flux density İ: Dielectric permittivity

A0

Top of lower shield

Figure 6-22. Concept of the ACW; increased area A1 enclosed with farther side ground metals results in a larger inductance. d0 is the decreased distance between the signal line and ground potential which allows larger capacitance to be achieved

Transmission Lines

95

From Eqs. (6-23) and (6-32), the wavelength of the signal wave can be related to the phase constant according to Eq. (6-33).

λ=

2π

β

(6-33)

Hence, a large ȕ results in a small Ȝ and this corresponds to a shorter physical length to achieve a given fraction of the wavelength. Therefore, devices such as filters that require a determined wavelength can be fabricated using this structure to occupy a smaller the area on the chip. This concept has been used in the design of the SWTL. The SWTL structure is fundamentally similar to the S-CPW except for the use of grounded shields instead of floating shields. Compared to the ACW, it also does not use a top pad metal layer.

3.2

Analysis of Inductive and Capacitive Quality Factors in Transmission Lines

A useful measure of characterizing the transmission line is to describe its quality factor (Q-factor). Different transmission line structures result in different Q-factors. For integrated circuits, transmission lines implemented in the form of CPW and microstrip lines are commonly used. As described in the previous section, the Q-factor of a transmission line can be calculated from the propagation constant to give Q = ȕ/2Į, where Į is the attenuation constant and ȕ is the phase constant. Another useful measure of defining the Q-factor is obtained from the distributed model of the telegrapher’s equations where the series resistance R and inductance L along with the parallel conductance G representing the leakage and capacitance C are defined. This leads to the definitions of QL and QC. QL =

QC =

ωL R

ωC G

(6-34)

(6-35)

Ȧ is the angular frequency. Transmission lines store mostly magnetic energy to resonate with the intrinsic capacitance of transistors. Thus, QL is crucial in determining the loss of the lines. Nevertheless, QC dominates under certain conditions. In commonly used CPW, QC is affected by the

Chapter 6

96

coupling to the substrate and is the limiting mechanism of the Q-factor. In general, the Q-factor can be calculated from Eq. (6-36).

1 1 1 = + Q QL QC

(6-36)

Therefore, to increase Q, it is necessary to increase both QL and QC. Using the electromagnetic simulator, the 2D Extractor by Ansoft, values of the Q-factor, QL and QC of the CPW are obtained at 60 GHz. Figure 6-23(a) shows the variations in these values of the CPW when the distance between the center signal line and the coplanar ground line wg changes. This distance wg between the center signal line and the two lateral ground lines determines the inductance L. Therefore, to increase L, wg should correspondingly increase, thereby also increasing QL. However, if wg is increased, the signal capacitance to ground C reduces and the leakage conductance G will be increased, leading to a lower QC. Therefore, increasing wg will result in an increase in the Q-factor up to the point where the QL and QC curves will intersect and it will then decrease with increasing wg.

㪈㪇㪇㪇 㪈㪇㪇

100

QL

Q

QC Q

㪨

QL

10 1

Q 10 wg μm (a)

QC 100

㪈㪇 㪈

㪈㪇 wg μm

㪈㪇㪇

(b)

Figure 6-23. (a) CPW cross section and its Q-factor; (b) S-CPW structural cross section and its Q-factor

Transmission Lines

97

To evaluate the effects of the slot shield underneath the signal line, as for the case of the ACW and SWTL, an approximate floating shield structure is used for simulations. This structure is the S-CPW in Fig. 6-23(b) which is designed with a slot metal shield underneath the signal line. This slot metal shield cuts perpendicular to the flow of current in the signal line above; thus, this shield is able to effectively lower the induced current in it. The shield also reduces substrate losses because it can effectively reduce the electric field entering the silicon substrate. Having the advantages of the shield, the coplanar ground can be spaced further apart for a larger inductance without increasing substrate losses. This results in a capacitance per unit length C similar to that of the microstrip line. This follows then, that the wave speed and wavelength are lower with S-CPW, and such devices will use a smaller chip area. Also, the signal conductor is wider for the given characteristic impedance, thereby reducing copper losses. Figure 6-23(b) shows the simulation results of the Qfactor; the inductive and capacitive components QL and QC of S-CPW plotted as functions of wg. It can be seen that the S-CPW can achieve a high QC because of the shield. A high QL is also achieved which is similar to the CPW because of the higher inductive coplanar grounds.

3.3

Experimental Results

The ACW is measured up to 110 GHz with Anritsu ME7808 with transmission- reflection modules. The micrograph of the ACW is shown in Fig. 6-24. Figure 6-25 shows a high phase constant that results in a short wavelength. Compared to the conventional CPW and the microstrip line, its value is approximately 3.3 times higher. In addition, the ACW has a higher quality factor (Q-factor), compared to the conventional lines, as shown in Fig. 6-26. The Q-factor of the ACW, however, is not clearly better than that of the SWTL since it is expected that the Q-factors of substrate-shielded coplanar structures are similar since the Q-factor of both structures are not limited by any improved QC. The attenuations Į, of the different structures are shown in Fig. 6-27. Į partially determines Q since it is determined by Eq. (6-24):

Q=

β . 2α

The higher measured attenuation of the ACW is due to the increased capacitance with the pad metal layer, which explains why the quality factor of the ACW is not significantly higher despite a high phase constant. There

Chapter 6

98

is thus a trade-off for high phase constant to achieve length reduction with attenuation. However, despite higher attenuation, the quality factor improves, as shown for the case of the ACW over the microstrip line and the CPW. All the lines are fabricated using the same process with a signal line width of 12 ȝm and characteristic impedances between 20 and 50 ohms, shown in Fig. 6-28. As a result of employing ACW, circuits such as oscillators can achieve a significant area reduction as illustrated in Fig. 6-29.

slot

12 μm

wg

Signal

Ground Figure 6-24. Micrograph of the ACW

20

ACW with wg=44μm

㱎 (rad/mm)

15

10

SWTL with wg=44μm x 3.3

CPW

5

microstrip line 0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-25. Measured phase constant of the transmission lines

Transmission Lines

99 SWTL with wg=44μm

Quality Factor

15

10 ACW with wg=44μm microstrip line

5

coplanar waveguide 0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-26. Quality factor of the transmission lines

ACW with wg=44μm

㱍 (dB/mm)

8.0

6.0

coplanar waveguide

4.0

microstrip line

2.0 SWTL with wg=44μm 0.0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-27. Attenuation of the transmission lines

Chapter 6

100 coplanar waveguide microstrip line ACW with wg=44μm

75 Re(Z0)

Z0 (Ω)

50 25 0 Im(Z0)

-25 0

20

40

60

80

100

120

Frequency (GHz)

Figure 6-28. Characteristic impedance of the transmission lines

490μm

150μm

Figure 6-29. Comparison of 60-GHz oscillators with quarter-wavelength transmission lines

4.

CHAPTER SUMMARY

A new slow-wave transmission line structure for improving the Q-factor has been fabricated and characterized. This structure uses slotted ground shields for preventing the electric field from entering the substrate. The extended ground metal fingers of the transmission line allow higher inductances to be achieved while enabling the design to satisfy the stringent density requirements of advanced CMOS processes. The quality factor achieved is higher than 10 at 110 GHz, which is four times that of the conventional coplanar waveguide. The current induced in the silicon substrate by the

Transmission Lines

101

magnetic field is modeled by the proposed distributed circuit model. This model also accounts for the leakage return current along the reverse signal path in the ground shield. The model can be employed in circuit simulators to design the circuits used in the millimeter-wave transceiver. An ACW structure that uses the slow-wave concept is then presented for advanced CMOS processes which consist of a signal line surrounded by ground metals. This design increases the Q-factor and reduces the phase velocity for short wavelengths through large capacitance and inductance when compared to conventional CPW and microstrip lines. Using 2-D electromagnetic simulations, the Q-factor of the CPW and substrate-shielded S-CPW is evaluated for its inductive and capacitive components QL and QC. From the results, it is observed that the QC of the S-CPW with a slot metal shield is high as the shield suppresses the capacitive coupling to the substrate and thus minimizes the loss. In addition, the S-CPW also shows a high QL. Similar to the CPW, the high QL of the S-CPW is obtained because the ground can be placed farther from the return current path, thereby increasing the inductance per unit length. Applying this concept to the ACW, the inductance and capacitance can be varied almost independently of each other as the coplanar ground spacing controls the inductance while the shield affects capacitance. The high measured value of the phase constant confirms the short wavelength of the signal propagating in the ACW structure. Up to 110 GHz, the physical length of the new ACW is reduced down to 30% while achieving the same wavelength as conventional lines.

Chapter 7 ON-CHIP BALUN

This chapter continues the development of passive devices for the millimeter-wave transceiver circuits. The balance-unbalanced (balun) converter is a device that interchanges between a single-ended unbalanced signal and differential balanced signals. This function is frequently needed in balanced mixers and differential amplifiers in the transceiver circuit. Hence, on-chip CMOS baluns have been reported in recent works.44, 45 On-chip baluns offer high levels of integration for cost-savings and develop less parasitic due to shorter interconnections to devices. As a result, they are suitable for high frequency applications. It is, however, a challenge to obtain good performances with low losses when designing a passive balun on standard lossy silicon substrates. In addition, the balun should occupy a small area and maintain design simplicity. In this work, due to the broadband nature of the Marchand-type balun used, the design parameters can be easily estimated without complex calculations or time-consuming simulations. Section 7.1 describes the balun structure and design considerations. Section 7.2 reports the measurement results of the work.

1.

BALUN DESIGN

The objective of the design is to realize a feasible balun structure that can be implemented in a high frequency circuit. For rapid simulations and high design error tolerance, a wideband, passive Marchand-type balun is used. Figure 7-1 shows the design of the balun. The shape of the balun is optimized to reduce occupied area and minimizes the distance between the differential ports. The desired distance between the differential ports is closely affected by the layout requirements of the circuit that uses the balun. 103

Chapter 7

104

In general, a balun connects to the active devices through a minimum of interconnections, especially at high frequency. Therefore the differential ports are located close to the MOSFETs and to each other. Typical reported works of balun test structures occupy large areas without an efficient shape for realization in a circuit.45 Top pad metal Singleended

+90㫦

metal6

-90㫦 Differential signals Substrate shield (metal1)

Figure 7-1. Structure of the stacked on-chip balun includes the use of the top pad metal layer and two conductors on metal layer 6 with slotted shields placed below the metal

This Marchand-type balun uses a thick top pad metal strip of halfwavelength. The single-ended port is at one end while the other end is left open-circuited. Two metal strips are located immediately under the top pad metal strip in the next highest metal layer. One end of each lower metal strip is connected to ground while the other end connects to each of the differential ports. This stacked structure allows the use of the thick top pad metal layer available in the process technology in a useful way, which normally is not suitable for carrying signals that are directly connected to the gate of the MOSFET, in order to satisfy the antenna rules. In addition, this stacked structure provides optimal inductive coupling, as compared to planar layout of the lines on the same metal layer. In this stacked design, all lines have the same width. Slotted ground shields are laid underneath the metal structures to prevent the electric field from penetrating the silicon substrate to induce substrate eddy currents. The design of the balun requires determining of the length of the top pad metal strip and the width. Each of the two lower metal strips has half the length of the top pad metal to be at a quarter-wavelength long, less the gap distance between the differential port outputs. Determining the length requires an estimate of the effective permittivity. The effective permittivity is related to the wavelength of the propagating signal according to Eq. (7-1).

On-Chip Balun

λ=

c f εr

105 .

(7-1)

The value of the effective permittivity depends strongly on the structure of the transmission lines that forms the balun. For conventional microstrip line structure, the value is taken approximately at 4.0, using SiO2. Transmission line structures using slow-wave designs are developed which have an effective relative permittivity of up to 15, according to its wavelength reduction factor. The lines used in this work have an effective relative permittivity of 7.6 and this corresponds to a shorter wavelength with a reduction factor of 2.8 times when compared to conventional microstrip lines. Due to the broadband nature of the Marchand balun, Eq. (7-1) is sufficient to provide an estimate for design and further EM simulations can determine the width for the required impedance. In this design, the widths are 12 ȝm to obtain 50 Ω port impedances for measurements. Finally, the position of the differential ports is determined by the gap distance required between them. It is necessary to consider the trade-off between placing them closely to minimize phase imbalance and placing them apart to reduce the parasitic capacitance. This design choice also considers the layout requirements of the circuit employing this device. In this design, a value of 10 ȝm is selected that is able to maintain good phase balance as well as amplitude balance as shown in the results in the next section.

2.

EXPERIMENTAL RESULTS

The test structure is fabricated using a CMOS 90 nm 6M1P process connected to two GSGSG pads for measurements using Anritsu 37397D vector network analyzer with a SM6000 four-port test set. This setup results in one dummy port that is not used. Nevertheless, standard 4-port openshort-through calibration can be performed with the existing calibration structures without any loss of accuracy. The open-short de-embedding method is then employed to remove the effects of the pads and the additional lengths that connect to the balun ports. Ignoring the measurements of the dummy port, the 3-port S-parameter matrix of the balun is obtained. Figure 7-2 shows the balun micrographs, including the open and short structures for de-embedding.

Chapter 7

106

(a)

(b)

(c)

Figure 7-2. (a) Micrograph of the balun; (b) open structure (c) short structure

Figure 7-3 shows the transfer characteristics of the balun. Port 1 of the scattering matrix refers to the single-ended port. Ports 2 and 3 refer to the differential balanced ports. Accordingly, |S21| and |S31| are the measured attenuations through ports 2 and 3 respectively.

Figure 7-3. Transfer characteristics of the balun. Port 1 refers to the single-end port. Ports 2 and 3 the differential balanced ports

The theoretical values of | S21| and | S31| of an ideal balun are –3 dB, since each differential port divides to half of the power at the single-ended port. At 30 GHz, the measured values of | S21| and | S31| are –6.5 dB and –6.0 dB respectively. This calculates to an amplitude imbalance of 0.5 dB. Within an

On-Chip Balun

107

acceptable amplitude imbalance of ±1 dB, the frequency range is between 22.4 GHz and 44.4 GHz. This large bandwidth indicates a good broadband amplitude balance. Figure 7-4 shows the measured phase difference between the differential ports after de-embedding.

Figure 7-4. Phase difference between the differential ports of the balun. At 30 GHz, the phase imbalance between the two ports is below 5°

For the proper functioning of the balun, the desired phase difference between the differential ports is 180°. At 30 GHz, the measured phase difference is 185°. This calculates to a phase imbalance of 5.0°. This verifies the functionality of the balun at the millimeter-wave frequency. Within an acceptable phase imbalance of ±10°, the frequency range is between 11.6 GHz and 37.3 GHz. Therefore, considering the acceptable amplitude imbalance of ± 1dB in this frequency range, the balun operates well between 26.8 GHz and 37.3 GHz, confirming its broadband characteristics. In order to analyze the use of the balun as an 180˚ power splitter, the common mode rejection ratio46 (CMRR) is calculated according to Eq. (7-2), and shown in Fig. 7-5.

CMRR =

Sdm S −S = 31 21 Scm S31 + S21

(7-2)

Sdm and Scm denote the differential-mode and common-mode S-parameters respectively. Equation (7-2) gives a single measure of the effects of both magnitude and phase imbalance in a splitter that can be readily calculated from measured data. At the desired frequency band, the differential-mode

Chapter 7

108

response is larger than the common-mode response to give a large value of CMRR. In the operating frequency band, the 180° power splitter has approximately 25.0 dB CMRR. The minimum measured CMRR is 21.0 dB. 30 25.5 dB CMRR

20 10 0 -10 -20 0

10

20

30

40

50

60

70

Frequency (GHz) Figure 7-5. CMRR of the balun when operating as a splitter

When the balun is analyzed as an 180° power combiner, a rejection ratio cannot be directly applied. However, a common-mode response ratio (RCMcomb) and a differential-mode response ratio (RDMcomb) are defined by Eqs. (7-3) and (7-4), plotted for the measured results in Figs. 7-6 and 7-7. 0

RCMcomb

-10 -20 -30

-28.7 dB

-40 -50 0

10

20

30

40

50

60

70

Frequency (GHz)

Figure 7-6. Common-mode response of the balun operating as a power combiner

On-Chip Balun

109 0 -3.2 dB

RDMcomb

-10 -20 -30 -40 -50 0

10

20

30

40

50

60

70

Frequency (GHz)

Figure 7-7. Differential-mode response of the balun operating as a power combiner

RCM comb =

1 S12 + S13 2

(7-3)

RDM comb =

1 S12 − S13 2

(7-4)

The common-mode signal, measured by RCMcomb, is undesired and will affect the output of the combiner when there is an imbalance. The RDMcomb is the desired response of the combiner.46 The derivations for the equations are provided in the next section. From the measurements, the RCMcomb of the fabricated balun is –28.7 dB and the RDMcomb is –3.2 dB and these values can be verified using the identity given in Eq. (7-5).

CMRR=

RDM comb RCM comb

(7-5)

The measurement results compare well with works on reported baluns. In Ma,44 the balun operates from 25 to 40 GHz designed for 0.24 ȝm SiGe BiCMOS and occupies 285 ȝm×1333 ȝm. In O’Sullivan,45 the balun operates from 800 MHz to 2.5 GHz designed for 0.18 ȝm CMOS and occupies 250 ȝm × 250 ȝm.

Chapter 7

110

3.

DERIVATIONS FOR DIFFERENTIAL-MODE AND COMMON-MODE RESPONSE RATIO a2

b1 a1=0 a3 Figure 7-8. The output of the combiner is labeled as port 1. The inputs of the combiner are identified as ports 2 and 3

Figure 7-8 illustrates a combiner of output b1 with inputs a2 and a3.

§ b1 · § S11 ¨ ¸ ¨ Note the relationship ¨ b2 ¸ = ¨ S 21 ¨b ¸ ¨ S © 3 ¹ © 31

S13 · § a1 · ¸¨ ¸ S 23 ¸ ¨ a2 ¸ , S33 ¸¹ ¨© a3 ¸¹

S12 S 22 S32

where b1 ≠ 0, a2 = a3 ≠ 0 for this case. Hence,

b1 = S11a1 + S12 a2 + S13 a3 , a1 = 0 .

Define acm =

a2 + a3 2

and adm =

The basic definition of RCMcomb is

a2 − a3 2

b1 acm

. When adm = 0, a2 = a3 .

. Therefore, adm = 0

On-Chip Balun

RCM comb =

111

b1 ( a2 + a3 ) / 2

= 2 = 2 =

adm = 0

S11a1 + S12 a2 + S13 a3 a2 + a3

b1 ( a2 − a3 ) / 2

= 2

4.

(7-6)

1 S12 + S13 2

= 2

=

(Since a1 = 0 )

S12 + S13 1+1

The basic definition of RDMcomb is

RDM comb =

a2 = a3

b1 adm

. Therefore, acm = 0

acm = 0

S11a1 + S12 a2 − S13 a3 a2 + a3

a2 =− a3

(7-7)

S12 − S13 1+1

1 S12 − S13 2

CHAPTER SUMMARY

An on-chip stacked Marchand balun has been realized using CMOS 90 nm process technology for potential applications in the millimeter-wave frequency band. The balun structure has been optimized for the process design rules by employing the top pad metal and thin slotted ground metal shields. As a result, it consumes a small area of 229 ȝm × 229 ȝm. At 30 GHz, the measurements show an amplitude imbalance of 0.5 dB and a phase imbalance of 5.0˚. The balun operates within an amplitude imbalance of

112

Chapter 7

±1 dB and a phase imbalance of ±10˚ between 26.8 and 37.3 GHz. To evaluate the balun as a power splitter, the CMRR is calculated to be 21.0 dB at 30 GHz. For evaluation as a power combiner, the expressions for RCMcomb and the RDMcomb are derived. They are then calculated from measured results to have a value of –28.7 dB and –3.2 dB, respectively. This balun design has been successfully employed in the up-conversion mixer circuit, described in Chapter 8.

PART 3

MILLIMETER-WAVE ACTIVE CMOS CIRCUITS

Chapter 8 UP-CONVERSION MIXERS

From this chapter onwards, we will describe design examples of millimeterwave CMOS building blocks. We will begin with the millimeter-wave CMOS up-conversion mixer in this chapter. Up-conversion mixers are used for converting the frequency of the signal in a transceiver. This chapter presents details of two implemented up-conversion mixers. The first is applicable for the 22–29 GHz UWB vehicular radar. Although this bandwidth is below 30 GHz, its important practical application deserves attention and it can demonstrate the high frequency challenges. The second up-conversion mixer is implemented at a frequency of 50 GHz that uses a double-balanced architecture. Both mixers implement on-chip baluns that are explained in the previous chapter.

1.

PSEUDO-MILLIMETER WAVE UP-CONVERSION MIXER

For the ultra-wide band (UWB) vehicular radar transceiver operating in the 22–29 GHz frequency range, up-conversion mixers above 20 GHz are required. Until recent years, CMOS has not been able to achieve this operating frequency and it is necessary to employ compound semiconductors. CMOS technology, besides consuming less power, has the potential to integrate with digital technology. In addition to the design for low power consumption, it is necessary that the mixer circuit does not suffer excessive conversion losses. With advances in filtering technology,47, 48 in recent years, allowing up to 30 dB attenuations at 20 GHz with high Q, a review of the use of the up-conversion mixer topology is necessary.

115

Chapter 8

116

A double-balanced Gilbert mixer has been widely used in analog and RF circuits to implement mixers because of excellent port-to-port isolation. The single-balanced mixer can be used to reduce power consumption because less number of active devices is employed. The separate feeding ports for IF and LO in a single-balanced mixer provides good isolation between IF and LO ports. However, excellent IF-RF and LO-RF port-to-port isolation can be achieved only if a double-balanced Gilbert mixer is fed with balanced IF and LO signals and the output RF signals are taken differentially. Nevertheless, the LO-RF isolation of the single-balanced mixer is still superior to the isolation provided by a single transistor mixer. In fact, the common-mode rejection provided by the biased current source in a conventional doublebalanced Gilbert mixer deteriorates rapidly at high frequency.49 Therefore, at high frequency, it is practical to challenge the single-balanced topology for gain and reduced power consumption at high gigahertz bands while reducing the LO with advanced filtering techniques. The single-balanced topology, as used in this work, can also achieve moderate gain and a low noise figure. Less chip area is required since a balun is not required for the IF input, compared to that of the doublebalanced mixer. However, this topology has low 1-dB compression point and high input impedance. To our knowledge, existing implementations on CMOS50 have achieved 24 GHz with high gain at a power consumption of 12.5 mW, as at the time of this writing, with the current-reuse technique51 to provide more current to the transconductance FETs. In this work, a fully integrated 20–26 GHz broadband up-conversion mixer with on-chip baluns is demonstrated on 90 nm CMOS technology. The maximum power consumption is 11.1 mW from a 1.2 V dc supply.

1.1

Up-Conversion Mixer Design Methodology

The mixer topology used for this work is shown in Fig. 8-1 which uses the single-balanced design. The input and output power are transferred using the impedance match of the on-chip baluns.

Up-Conversion Mixers

117 Output RF Vdd

LO balun M2 LO Vdd

M3 M1

Balun for converting to single-ended RF output

Input IF

Figure 8-1. Schematics of the up-conversion mixer circuit

The differential output RF signal is converted to a single-ended output using a substrate-shielded Marchand-type balun. The balanced LO signal is also provided through another balun. Common-mode noise produced by the switching transistors and LO-port is rejected at the differential output. However, there remains a direct noise current path between the output terminals during a time interval around the zero-crossing of the LO voltage. Since the noise scales with the size of the transistors M2 and M3, they should not be large. Furthermore, LO signals need to be sufficiently high to fully switch the transconductance current to flow through either of M2 or M3. At low supply voltages, special considerations are necessary. M1 is usually biased in the strong inversion and saturation to achieve conversion gain, good linearity and low noise. With Vgs for the optimum transconductance gm at about 0.65 V and a threshold voltage of 0.3 V for the technology used, the minimum voltage required to turn the switching transistors on is near to 1 V. Therefore, possible voltage headroom required by de-generation resistors is avoided. Since the configuration is optimized for gain with low power, rather than linearity, inductive de-generation is not applied. Furthermore, the conventional method of operating M2 and M3 in saturation also requires significant voltage headroom, reducing the headroom available for any resistive load with broadband operations and hence limiting the achievable conversion gain. A finite external load will further reduce this limit. This problem is overcome in this design by allowing the single-ended output signal to be drawn by the capacitive coupling of the balun which appears as high impedance to the output of the mixer core.

Chapter 8

118

1.2

Stacked Marchand Balun Design

Passive baluns do not consume any power and topologies such as the Marchand-type balun provide broadband response with low losses at the pass-band. This section describes the implementation of on-chip stacked Marchand baluns in the mixer circuit, after results of its separate test structure presented in Chapter 7. The Marchand balun provides single-ended signal to differential signal conversion by using coupling across a halfwavelength line. Signal is input into the half-wavelength line at port 1 as shown in Fig. 8-2 and output is taken from the ends of two quarterwavelength lines at ports 2 and 3. -90º Input Port 2 coupling

Input Port 1 coupling

Input Port 3 +90º

Figure 8-2. Operating principle of the Marchand balun

The opposite ends of the quarter-wave lengths lines are connected to a common ground potential, hence the outputs at ports 2 and 3 have a phase difference of 180°. To ensure amplitude balance, the two quarter-wave lines are placed at the same distance away from the half-wavelength line. For sufficient power to be transferred to both the coupled lines at the LO input and the load at the RF output, sufficiently strong coupling is required. In the conventional implementations of the Marchand balun on thick dielectrics,52, 53 coupling between the coplanar half-wavelength and quarter-wavelength lines are significantly stronger than the leakage capacitance across the dielectric. However, for implementations on CMOS, large capacitive losses results from the thin dielectric between the conducting metal and the ground metal underneath (~2.9 ȝm). This distance is significantly smaller than the distance between the coplanar half-wavelength and quarter-wave length lines on the same metal layer. Therefore, to achieve the strong coupling required, the coupling is increased by reducing the distance between metals through stacking. Stacking is achieved by using the pad metal for the halfwavelength line and the next highest metal layer for the quarter-wavelength

Up-Conversion Mixers

119

lines. As illustrated in Fig. 8-3, the single-ended signal is input into thick pad metal and capacitive-coupled to the two lines on metal 6 below where the signal exits differentially. Top pad metal

Singleended

+90㫦 㱐

metal6 -90㫦 Differential signals Substrate shield (metal1)

Figure 8-3. Multi-layer stacked balun design with substrate shield

The loss in the structure can further be reduced with substrate shielding. The substrate shield is realized with slotted shield structures which are placed underneath the balun. This shield reduces the speed of the propagating wave and results in a shorter physical length that corresponds to the required wavelengths. The shield also prevents the electric field from penetrating the conductive silicon substrate. To ensure sufficient power transfer from the coupled quarter-wave lines to the input/outputs of the balun, sufficiently high impedance for matching is desired. In this implementation, the ground slot shield is located nearest to the coupled lines and thus determines the capacitance to ground. The line inductance is determined by the distance of the signal line to the return ground current, which are located further away. Thus, the inductance and the capacitance can be controlled fairly independently to achieve the required impedances, similar for the case of the slow-wave transmission lines (SWTL) as described in Chapter 6. The shape of the balun is constructed in the form of a square to minimize required chip area and to allow the differential ports to be located closely. It is necessary to locate the ports closely since they connect to the switching transistors that need to be well matched. Any extra length on the layout for the interconnections between the balun and the transistors will affect the transfer characteristics. However, due to physical layout constraints, the differential ports cannot fully couple to half the length of the half-wavelength

Chapter 8

120

line and leaves a gap with a distance of į. This distance δ between the terminals of the differential ports must be spaced closely to achieve good anti-phase. The coupling effects are illustrated by a simplified lossless model in Fig. 8-4. This model describes the balun with inductive components along the length of the half-wavelength line and the two quarter-wavelength lines. The lines are inductively coupled together with a coupling coefficient k and have capacitances, Ccoupling. The leakage capacitive losses to the ground are through Closs. The space between the output ports is represented by a parasitic capacitance Cgap. Single-ended input

k

k

Ccoupling

Cgap Closs

Differential Outputs

Figure 8-4. Simplified stacked Marchand balun equivalent circuit ignoring resistive losses illustrating the capacitive coupling and losses

From Fig. 8-4, it can be seen that the capacitive losses through Closs should be minimized and the Ccoupling maximized. However, since the width of the metal lines affects the required impedance as well as the desired capacitances for coupling, an optimized value should be used. For the case of the coplanar implementation described previously, more capacitive losses occur since both the half-wavelength line and the quarter-wavelength lines suffer capacitive losses. For the case of the stacked implementation, only the quarter-wavelength lines are directly coupled to the ground. The halfwavelength line couples to the quarter-wavelength lines through a short inter-dielectric layer distance of only 1.12 ȝm. Figure 8-5 shows the simulation results of the output balun using the proposed circuit model of Fig. 8.4 and comparing it to the results generated by 2.5-D layout simulator ADS Momentum. Port 1 refers to the singleended, while ports 2 and 3 refer to each of the differential ports. The two sets of simulation results agree fairly well. Both show an insertion-loss of less than 6 dB at the pass-band from 20 to 24 GHz while the phase difference is within 5° from the desired value of 180°.

Up-Conversion Mixers

121 ADS Momentum results Circuit model results

0

300º S31

Insertion loss (dB)

150º S21

-20

0º S21

-30

Phase (degree)

-10

-150º S31 -300º

-40 0

10

20

30

40

Frequency (GHz)

Figure 8-5. Simulation results of the output RF balun

Table 8-1. Balun design parameters.

Widths Gap distance, į Effective wavelength Elemental shield width

12 ȝm 10 ȝm 1716 ȝm (LO balun) 1460 ȝm (RF balun) 1 ȝm

Table 8-1 shows the summary of the design parameters used. The width of the balun is designed to match the LO and RF ports of the mixer to the pads for measurements. Table 8-2 shows the simulated port impedances. The pads are modeled with an impedance 45-j3.1 ȍ at the center frequency of 22 GHz. Table 8-2. Mixer design parameters at 22 GHz.

Simulated impedance at each differential LO port

12.6-j131 ȍ

Simulated impedance at each differential RF port

30.3-j0.1 ȍ

Chapter 8

122

1.3

Experimental Results

The up-conversion mixer was designed and fabricated using a six-metal 90 nm CMOS process. The additional pad metal layer available is utilized as one of the coupled lines of the baluns for the single-ended input/output. Onwafer measurements are performed because the fabricated circuit allows a GSG single-ended IF input, a GSG single-ended RF output and the LO supplied through another GSG single-ended input. The LO frequency is varied between 17.3 and 23.3 GHz. This allows an RF output of 20–26 GHz using a 2.7 GHz IF. Figure 8-6 shows the micrograph of the fabricated chip. The size is 650 ȝm × 570 ȝm.

LO Balun

RF Balun

Figure 8-6. Micrograph of mixer with on-chip baluns

The circuit has a large matching bandwidth for the LO and RF output at where the baluns are used. S-parameter measurements are taken with the circuit bias voltages. The input and output of the network analyzer are used to probe the LO and output RF ports to evaluate the balun matchings. From Fig. 8-7, the output matching, S22 has a return loss better than 10 dB for frequencies from 20 to 26 GHz. The matching to LO, S11 achieves a minimum of –14.0 dB at 19.4 GHz. Small signal S-parameters are used to determine the range of the operating frequency for low power conditions. For large power levels, linear assumptions of the S-parameter measurements do not hold. Therefore, direct power measurements are taken to verify the characteristics. In addition, since the output impedances at the drain of the switching transistors are a function of the gate voltage of the switching transistors M2 and M3, and S22 is a measure of the degree of impedance matching at the output (to 50 ȍ), S22 should be measured while the LO signal is being applied.

Up-Conversion Mixers

123

0

S11, S22 (dB)

-5

-10 S11 S22

-15

-20 0

10

20

30

40

Frequency (GHz)

Figure 8-7. Measured S11 for LO balun matchings and S22 RF output balun matchings

Power measurements were taken across the frequency band of interest. Figure 8.8 shows the measured output power at the center RF frequency of 22.1 GHz with an input IF signal at 2.7 GHz. The up-conversion mixer exhibits a conversion gain of 2 dB and achieves an input-referred 1-dB compression point of –14.8 dBm.

IF=2.7GHz, RF=22.1GHz

Pout (dBm)

0

-10 IP1dB= -14.8dBm -20

-30 -30

Conversion gain = 2.0dB

-20

-10

0

10

Pin (dBm)

Figure 8-8. Variation of output RF power with input IF power

Chapter 8

124 3

Conversion Gain [dB]

2 1 0 -1 IF = 2.7GHz IF power = -30dBm

-2 -3 20

21

22

23

24

25

26

Frequency (GHz)

Figure 8-9. Plot of conversion gain variations with RF frequency

The power consumption of the circuit varies as a function of the applied voltage and LO power. For each set of conditions, it has fairly constant power consumption at low input IF power. Conversion gain decreases as the applied voltage or LO power decreases. Figure 8-9 shows the conversion gain variations with the output frequency. The input IF is maintained at 2.7 GHz and the LO frequency is varied between 17.3 and 23.3 GHz. The results show a conversion gain with a minimum of –3 dB across the 20–26 GHz band. Figure 8-10 plots the IF-RF isolation at an input IF power of –30 dBm. The result shows a minimum of 10 dB isolation up to 26 GHz. At the designed balun frequency of 22 GHz, an isolation of 18 dB is obtained. Reduction in isolation can be caused by fabricated balun imbalances as well as poor transistor matching. It is reasonable for a narrowband power amplifier to increase the output power from the output RF signal of the mixer so that it will further increase the IF-RF isolation at the transmitter output. For vehicular radar applications, FCC limits emission to –60 dBm below 22 GHz and –40 dBm from 22 GHz onwards. It will be satisfactory if all signals keep below these limits even under weak IF-RF isolation performances.

Up-Conversion Mixers

125

20

IF-RF Isolation [dB]

18 16 14 12 IF = 2.7GHz IF power = -30dBm

10 8 20

21

22

23

24

25

26

Frequency (GHz)

Figure 8-10. Plot of IF-RF isolation variations with RF frequency

Figure 8-11 shows the 1-dB compression point of the mixer. Across the measured band, the minimum value is obtained at 25 GHz corresponding to a –16.5 dBm input power. Considering the low emission limit of –41.3 dBm/ MHz in the required bandwidth of 500 MHz for the automotive radar application,54 high 1-dB compression points are not required.

1dB Compression Point [dBm]

-13 Input-referred 1dB compression points -14

-15

-16

-17 20

21

22

23

24

25

26

Frequency (GHz)

Figure 8-11. Plot of 1-dB compression point variations with RF frequency

Chapter 8

126

Power Consumption (mW)

16.0

14.0 11.1mW, 2dB low-IF gain 12.0

10.0 8.4mW, 0dB low-IF gain 8.0

-30

-20

-10

0

Input IF Power (dBm)

Figure 8-12. Power consumption with varying IF input power

As shown in Fig. 8-12, the mixer circuit consumes 11.4 mW at low input IF when the voltage supply Vdd is at 1.2 V using an LO output of 5 dBm. This produces a conversion gain of 2 dB before compression. At a reduced Vdd of 1.0 V and LO output of 3 dBm, the gain obtained is 0 dB. When such a gain level is acceptable, the required power is only 8.4 mW. The region of high input IF power corresponds to saturated output power region and does not provide any gain. Table 8-3. Up-conversion mixer measurements.

Matched RF Frequency IF Frequency Max. Power Gain Max. Power Dissipation IF-RF Isolation Input 1-dB Compression Point

20–26 GHz 2.7 GHz 2 [email protected] GHz 11.1 mW 18 [email protected] GHz –14.8 [email protected] GHz

Table 8-3 summarizes the performance of the broadband mixer circuit. With emphasis on low power consumption, the performance is comparable to up-conversion mixers fabricated on other semiconductor technologies. Figure 8-13 makes a comparison.

Up-Conversion Mixers

127

Comparison of Reported Up-Conversion Mixers

Conversion Gain [dB]

100

10

This work [53] SiGe 1

0

30

60

SiGe [54] [55] InGaPGaAs 90

120

Power Consumption [mW]

Figure 8-13. Comparison of conversion gain and power consumption with other reported works

2.

MILLIMETER-WAVE UP-CONVERSION MIXER AT 50 GHZ

So far as shown, high frequency mixer circuits have been attempted but limited to simple topologies.56, 57 For the up-conversion mixer, simple topology cannot reject the LO and advanced processes are limited by the low supply voltage. Thus, no double-balanced Gilbert topology has been reported on 90 nm process technology to date. However, the additional advantage of using CMOS at present is also to take advantage of the improved process technology which has the potential to integrate high density digital circuits for control functions. With the unity frequency fT of the 90 nm process technology up to 150 GHz, conversion gain can be obtained and it can be compromised with high frequency amplification that has been proven difficult with previous processes.

2.1

Up-Conversion Mixer Design

2.1.1

Mixer Topology

The Gilbert double-balanced topology is used. The local oscillator (LO) signal at the output can be reduced. However, to realize good LO rejection at high frequency is difficult because of the high-speed switching of the MOSFET results in a non-ideal alternating on-off of the differential pairs. Figure 8-14 shows the schematics of the mixer circuit.

Chapter 8

128 Vdd

Output RF

Vdd

Balun 1 M3

LO

M4

W=40μm

M5

M6

W=40μm

Balun 2

Vg1 (biasing) Vdd L1

L2 C1

M1 W=60μm

Input IF

M2 W=60μm

W=40μm

M7 L3

Gnd

C2

L4

Double-balanced Gilbert Cell Mixer

Vg1 (biasing)

Figure 8-14. Circuit diagram of the up-conversion mixer

At the high frequency LO and RF ports, passive baluns can be employed due to the shorter corresponding wavelengths for reduced on-chip sizes. However, at the relatively lower frequency IF port, an active balun is used instead. The choice of the baluns in the topology has to take into considerations of the low Vdd requirements of the process technology. M1, M2 is biased for maximum transconductance and M3–M6 requires voltage headroom for switching. Any additional active components should not demand further voltage headroom. In the topology employed, a compromise is made for increased chip area by the inductors L1–L4 and capacitors C1 and C2. These components, however, serve the important function of impedance matching to the Gilbert mixer circuit. 2.1.2

Passive Balun Structure

The passive baluns used in the circuit is the on-chip stacked Marchand balun of Fig. 8-3. The additional pad metal layer is utilized as one of coupled lines of the passive baluns. The occupied areas of the baluns are 105 ȝm × 105 ȝm and 92 ȝm × 105 ȝm for the LO feed and the RF output, respectively.

Up-Conversion Mixers 2.1.3

129

Active IF Balun

The active balun of Fig. 8-15 is employed to realize the single-to-differential conversion of the input IF signal to the mixer. This topology utilizes the antisymmetry of the MOSFET current at the drain and the source node. Vg1 (biasing)

Vdd

Phase 180º Input IF

W=40μm

matching

Phase 0º

Gnd

Vg1 (biasing)

Figure 8-15. Schematics of the input IF balun

This topology is commonly employed at low frequency for its simplicity and performance. At high frequency, the non-symmetry of the MOSFET gate-drain capacitance and the gate-source capacitance causes the phase balance to degrade. At the operating frequency of 10 GHz, the simulated amplitude imbalance achieves a low value of 1.1 dB and the phase imbalance reaches 19.3°. The output signals of the balun are directly used for driving the double-balanced mixer where the results are shown in the next section.

2.2

Experimental Results

The up-conversion mixer was designed and fabricated using a six-metal 90 nm CMOS process. Figure 8-16 shows the measurement results of the balun test structure.

Chapter 8

130 Phase diff. 180˚±10˚: 11.6 GHz~37.3 GHz 0

220

S21

-10

S31

200 180

-20

160 Amp. imbalance 0±1dB: 22.4 GHz~44.4 GHz

140

-30

|S21|, |S31| (dB)

phase difference (deg)

240

120 100

-40 0

10

20

30

40

50

60

70

Frequency (GHz) Figure 8-16. Amplitude response and phase imbalance of a 22.4–37.3 GHz stacked on-chip Marchand balun

Using stacked on-chip Marchand balun designs for the 50 GHz mixer, on-wafer measurements can be performed because the fabricated circuit allows a GSG single-ended IF input, a GSG single-ended RF output and the LO supplied through another GSG single-ended input. Figure 8-17 shows the micrograph of the mixer. The chip size is 600 ȝm × 1050 ȝm.

LO

IF

RF Figure 8-17. Chip micrograph of the up-conversion

Up-Conversion Mixers

131

Due to instrument restrictions, measurements are made with an input IF of 11 GHz and an LO of 40 GHz from signal generators. The RF signal cannot be measured below 50 GHz because of the non-availability of an appropriate harmonic mixer. Figure 8-18 shows the S-parameter measurements of the circuit. The single-ended output of the balun at the RF port has an optimum match at 46.5 GHz and extends from 40 to 51 GHz for a return loss better than 5 dB.

RF, LO return loss (dB)

0

-2

-4

LO

-6

0

10

20

30

RF

40

50

60

Frequency (GHz)

output RF Power (dBm)

Figure 8-18. Return losses of the LO and RF ports where the passive baluns are located

-10

RF=51GHz, IF=11GHz LO power=0dBm IP1dB= 1.0dBm

-20

Conversion loss = 11dB

-30 -20

-15 -10 -5 0 Input IF Power (dBm)

5

Figure 8-19. Measured power compression curve of the mixer

Chapter 8

132

Figure 8-19 shows the measured power characteristics of the mixer. The circuit has a conversion loss of 11 dB at the linear region and the linearity is indicated by the 1-dB compression point at 1 dBm input power. The high conversion loss can be partly attributed to the loss of the active balun. Measurements are taken at a RF of 51 GHz and an IF of 11 GHz with an LO input power of 0 dBm. The LO leakage at the output port is –26.5 dBm and the power consumption is 13.2 mW.

3.

CHAPTER SUMMARY

With the advancement in filtering technology, the single-balanced mixer is reviewed for use in up-conversion mixing. This work demonstrates a fully integrated broadband up-conversion single-balanced mixer with on-chip stacked Marchand baluns to enable a single-ended input and a single-ended output. The baluns are constructed with the top pad metal and the next highest metal layer for increased coupling and they provide impedance matching to improve conversion gain. Slotted substrate shields are laid under the balun structures to reduce substrate losses and provide reduced physical lengths. The occupied areas of the baluns are 229 ȝm × 229 ȝm and 182 ȝm × 212 ȝm for the LO feed and the RF output, respectively. The total die size is 650 ȝm×570 ȝm. At 22.1 GHz, the integrated mixer achieves a conversion gain of 2 dB with a maximum power dissipation of 11.1 mW from a 1.2 V dc power supply at LO power of 5 dBm. These results are comparable to mixer circuits fabricated using high-performance semiconductor processes. Input referred 1-dB compression point is –14.8 dBm. The LO and RF return loss are better than 10 dB for frequencies from 20 to 26 GHz. The second mixer demonstrates the first millimeter-wave doublebalanced mixer up to 50 GHz using CMOS 90 nm technology. On-chip stacked Marchand baluns are again used to enable a single-ended LO input and a single-ended RF output. The occupied areas of the baluns are 105 ȝm × 105 ȝm and 92 ȝm × 105 ȝm for the LO feed and the RF output, respectively. The active balun employs the quasi-symmetric properties of the drain and the source of the MOSFET to allow a single-ended IF input for the doublebalanced mixer. The fabricated chip has a total size of 600 ȝm × 1050 ȝm. At 51 GHz, the measured mixer achieves a conversion loss of 11dB with a maximum power dissipation of 13.5 mW from a 1.2 V dc power supply using a LO power of 0 dBm. Input referred 1-dB compression point is 1 dBm. The LO and RF return loss are better than 5 dB for frequencies from 40 to 51 GHz.

Chapter 9 DOWN-CONVERSION MIXER

In this chapter, the down-conversion mixer is described. Consider the 57–64 GHz licensed-free band in the United States and 59–66 GHz in Japan that have been driving the development of 60 GHz systems in recent years. This includes the development of the receiver on digital CMOS technology with potential applications in wireless HDMI and WPAN. The feasibility of the CMOS transceiver has been studied and works on its building blocks are reported.58 One of these blocks is the frequency down-conversion mixer which forms a critical part of the receiver. The down-conversion mixer converts a high radio-frequency (RF) signal at the input to an intermediate frequency (IF) at the output through the use of a local oscillator signal (LO). Among the important figures of merit to consider in the design of the mixer is the linearity. The linearity is important because the mixer is the first block in the receiver to handle large power, being located immediately after the low-noise amplifier (LNA). Determining the 1-dB compression point, it gives rise to the dynamic range of the mixer. A higher 1-dB compression point allows a larger input power range, which is the difference between this point and the noise floor. A higher 1-dB compression point will also result in a higher IM3 intercept, whose value can be approximated to 10 dB above the 1-dB compression point.59 Therefore, the IM3 intercept is an alternative way to evaluate the mixer’s signal handling capability. High linearity can be achieved with passive mixers. However, its obvious drawback is the associated high conversion loss because the mixer’s zero power consumption cannot boost the strength of the frequency-converted signal. Minimizing the loss of the signal is important because sufficiently high power may be needed to drive the subsequent stages in the receiver. In fact, it is a challenge to obtain high gain at 60 GHz in the preceding LNA due to the limits in the f T of the process. It is thus necessary to provide minimum 133

Chapter 9

134

conversion loss in the subsequent down-conversion mixer stage to reduce the burden on the LNA. Thus, we focus on the design of a mixer that achieves linearity while having minimal conversion loss. In addition, designing on advanced CMOS processes can allow integration with high speed digital circuits. However, RF design on advanced CMOS processes has been challenging. One of the issues is the high cost of the chip area. This translates to a need to reduce the design area for achieving a specific function under certain performance requirements. Small chip area can be realized by using slow-wave transmission lines for impedance matching instead of using conventional microstrip lines. Simple test structures utilizing the slow-wave phenomenon have been reported in earlier works.60 In this design, the slow-wave transmission line (SWTL) is employed to realize a mixer with high linearity, low loss and small chip area.

1.

MIXER AND SLOW-WAVE TRANSMISSION LINES

The down-conversion mixer consists of the core mixer and a buffer stage. Figure 9-1 shows the schematics of the mixer circuit using on-chip transmission line for impedance matching. The core mixer is a cascode stage which is made up of a transconductance (gm) stage, M1 and a switching MOSFET, M2 which performs the frequency mixing. M1 is therefore biased to obtain a high gm while M2 is biased near threshold to enable effective switching. Vdd

Vbuffer IF M3 Transmission line

M2 LO Transmission lines

M1

RF

Core mixer

Buffer

Figure 9-1. Schematics of down-conversion mixer circuit using transmission lines for impedance matching

Down-Conversion Mixer

135

The advantage of using a cascode topology is that it allows the RF input and the LO signal to be fed into two different MOSFET gates, avoiding the need for area-consuming power combiners. Since the LO and RF rejections at the IF output are not so critical due to the large spectral differences, this topology can be employed instead of Gilbert mixers and thus avoiding the use of lossy baluns. The common-source output stage M3 in the circuit boosts the output gain while providing impedance match to the output ground-signal-ground (GSG) pad and the IF signal port. In principle, the necessity or design of this stage depends on the impedance of its subsequent stage in the receiver module. In this work, the mixer circuit is connecting directly to the GSG pads. The modeling of the MOSFET has been performed by capturing the extrinsic high frequency parasitics using on-wafer S-parameter measurements up to 65 GHz. These parasitic components are added to the BSIM model obtained by the low-frequency parameters. The SWTL is used for implementing the matching networks between the pads and the mixer inputs/output. Analysis of this structure is described in Chapter 6. Figure 9-2 shows the structure of the SWTL used. The structure of the SWTL consists of slotted ground shields underneath the signal line which are laid orthogonal to the direction of the current flow. This structure results in the propagating wave having a lower phase velocity. Therefore, the corresponding wavelength at a given frequency reduces. In the design of the matching circuit requiring a given number of wavelengths, shorter physical lengths can be realized on the layout. 14μm

Ground metal

12μm

Signal

14μm

Ground metal

2.9 μm

Slotted ground shield Silicon

Figure 9-2. Simplified structure of the slow-wave transmission line used in the circuit

Chapter 9

136 10.0 Higher phase constant, 㱎for Slow-wave transmission line

β (103 rad/mm)

7.5

SWTL

5.0

㬍1.89 2.5 Microstrip line 0.0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 9-3. Phase constantsǪof the SWTL and the microstrip line (MSL)

Figure 9-3 shows the increase in the phase constant, ȕ of the SWTL as compared to the microstrip line (MSL) to result in a shorter wavelength, Ȝ as given in Eq. (6-33):

10.0 Higher phase constant, 㱎for Slow-wave transmission line

β (103 rad/mm)

7.5

SWTL

5.0

㬍1.89 2.5 Microstrip line 0.0 0

20

40

60

80

100

120

Frequency (GHz)

Figure 9-4. S-parameters of the measured slow-wave transmission line test structures and the extracted distributed model lengths of 900 ȝm and widths 12 ȝm

Down-Conversion Mixer

λ=

2π

β

137

.

To use these lines in the mixer circuit, test structures were fabricated. They are measured and modeled. Figure 9-4 shows the measured and modeled results up to 60 GHz.

2.

CHIP LAYOUT

The down-conversion mixer was designed and fabricated using a six-metal 90 nm CMOS process. Figure 9-5 shows the micrograph of the fabricated chip. The size is 0.61 mm × 0.80 mm including the pads. LO

SWTL

RF

IF

SWTLs for RF port matching

Figure 9-5. Micrograph of the down-conversion mixer circuit

To demonstrate the advantage of the length reduction for area conservation, consider the input RF signal port matching. A simple matching network consisting of one series and one parallel open stub is used. The required length of the transmission lines for the design can be represented by mȜ and nȜ for the series and the parallel stubs, respectively, where Ȝ represents one wavelength of the propagating RF signal. The following analysis is made according to the results of Fig. 9-2 and Eq. (6-33).

Chapter 9

138 1.89ȜSWTL = ȜMSL

(9-1)

When SWTL is used, Ȝ = ȜSWTL

(9-2)

When MSL is used,Ȝ = ȜMSL

(9-3)

From design of the fabricated circuit where SWTL is used, the series stub is 564 ȝm and the parallel stub is 245 ȝm. Therefore, mȜSWTL = 564 μm and nȜMSL = 245 μm. If MSL is used instead,

§λ · m ¨ MSL ¸ = 564 ȝm Ÿ mλMSL = 1066 ȝm , © 1.89 ¹ §λ · n ¨ MSL ¸ = 245 ȝm Ÿ nλMSL = 436 ȝm . © 1.89 ¹ The longer required lengths of the MSL will occupy a larger area on the chip. Similarly, the lengths of the LO and IF matching transmission lines are reduced using SWTL.

3.

EXPERIMENTAL RESULTS

Using the line lengths determined for the matching to RF, LO and IF ports, the circuit was fabricated and measured. On-wafer measurements are performed on the fabricated circuit through a GSG single-ended RF input, a GSG single-ended IF output and the LO supplied through another GSG single-ended input. Scattering parameters are obtained using an Anritsu ME7808 vector network analyzer. In particular, the impedance match of the RF input port to 50 ȍ is important because minimal power loss of the input RF signal is critical and it is unlike the LO and IF ports which are often not 50 ȍ terminations for connecting to the phase-locked loop (PLL) output and the IF filtering. Figure 9-6 shows the comparison between the measured and simulated return loss of the RF input port. It has a return loss better than 10 dB for frequencies from 45 to 64 GHz.

Down-Conversion Mixer

139

|S11| @ RF port (dB)

10

0

-10

Simulated

-20

Measured -30 0

10

20

30

50

40

60

Frequency (GHz) Figure 9-6. Measured and simulated return loss of the RF input port

From Fig. 9-6, it can be seen that the model overestimates the matching frequency by less than 10%. Fluctuations in the measured readings at high frequency occur due to imperfect calibration. The return loss at 60 GHz achieved is –13 dB. Figure 9-7 shows the measured output power at RF

Output IF power (dBm)

5 0

RF=60GHz, IF=4GHz LO power=1.5dBm IP1dB=0.2dBm

-5 -10 -15 Conversion loss = 1.2dB

-20 -20

-15

-10

-5

0

5

10

Input RF power (dBm)

Figure 9-7. IF output power at 4 GHz plotted against the RF input power at 60 GHz

Chapter 9

140

frequency of 60 GHz and IF of 4 GHz. The down-conversion mixer exhibits a conversion loss of 1.2 dB and achieves an input-referred 1-dB compression point of 0.2 dBm. The power consumed in the mixer core is 6.4 mW and the buffer circuit is 23.0 mW although the buffer has not been optimized in this design. Table 9-1 shows the summary of performances of 60 GHz CMOS down-conversion mixers reported to date. Table 9-1. Comparison of reported CMOS down-conversion mixers. Technology RF frequency IF frequency Conversion Gain 1-dB compression p. Area

4.

Emami61 CMOS 0.13 μm 60 GHz 2 GHz –2.0 dB –3.5 dB 1.6 × 1.7 mm2

Motlagh62 CMOS 90 nm 60 GHz 2–6 GHz –11.6 dB 6.0 dB 2.0 × 2.0 mm2

This work CMOS 90 nm 60 GHz 4 GHz –1.2 dB 0.2 dB 0.61 × 0.8 mm2

CHAPTER SUMMARY

A linear 60 GHz CMOS active mixer implemented with SWTL has been achieved. The mixer employs a cascode topology with IF output boosting and is fabricated on standard digital 90 nm CMOS process. The SWTL allows physical length reductions of 47% when compared to a microstrip line of an equivalent wavelength. The resulting circuit measures only 0.61 mm × 0.80 mm. At a RF of 60 GHz, IF of 4 GHz and LO of 1.5 dBm, the conversion loss is 1.2 dB and an input-referred 1-dB compression point of 0.5 dBm is measured. The return loss at the RF input port is better than 10 dB between 46 and 64 GHz. Performance is comparable to other reported works of CMOS 60 GHz down-conversion mixers while achieving a smaller occupied area.

Chapter 10 RF AMPLIFIER

In this chapter, the design of the millimeter-wave CMOS amplifier is described. Consider CMOS circuits operating at high gigahertz frequency reported in recent years.63 The developments are driven by the availability of the 60 GHz license-free band as well as applications in the high-gigahertz bands below 30 GHz such as the automotive radar system operating at 22–29 GHz. Amplifiers for high frequency signal amplification is necessary to realize the front-end transceiver in these applications. The amplifier may be implemented at different parts of the transceiver, such as the low noise amplifier, power amplifier, IF amplifiers and variable gain amplifiers. Each type of amplifier is designed with different specifications due to the different functions they perform. Generally, sufficient gain is a requirement and low power consumption is desired. Low power consumption is especially critical for portable devices where the battery life is limited. For CMOS amplifiers to achieve high gain at high frequency with low power consumption, advanced CMOS processes with high f T is used but it requires design techniques to handle the low supply voltage. In addition to these design considerations, designing at high frequency requires considerations such as accurate active device modeling and passive device optimizations. This chapter presents the design and analysis of a gainenhanced current reuse-cascade amplifier for millimeter-wave frequencies under the aforementioned considerations. The following section will begin with a brief review of the conventional transistor amplifier design techniques for microwave frequencies, including CMOS transistor sizing and impedance matching since these may be methods applied to millimeter-wave CMOS amplifiers as well.

141

Chapter 10

142

1.

REVIEW OF CONVENTIONAL DESIGN TECHNIQUES

One challenge in designing CMOS amplifiers is to exploit the flexibility of deciding the gate width W using a given technology node with a minimum gate length L of the transistors. These choices have not been so freely available to discrete circuit designers. It is therefore important to study how this flexibility impacts the traditional design concepts of the amplifier. The amplifier can be described by several parameters that specify its performance, and the most important parameter depends on the type of amplifier. In the case of the low noise amplifier (LNA), the noise figure is naturally important. At advanced CMOS technology nodes, reduced power dissipation, under low supply voltage conditions, may be another important consideration for the design. Applying one approach to this situation, the power dissipation requirements are first defined. For example, a 10 mW power dissipation limit from a 1.0 V voltage supply will require a maximum drain current of 10 mA. Using a determined value of gate-source voltage Vgs which corresponds to the maximum transconductance gm, the saturated drain current relationship of Eq. (10-1) provides the required width W of the transistor (neglecting channel modulation effects) according to Eq. (10-2).

ID =

μCox W 2L

Wmax =

(V

gs

− VT )

2

(10-1)

2 L ⋅ I D , max

μCox (Vgs − VT )2 V

(10-2) gs =V gs , gm max

Using this calculated value of W, the required gm can be found according to Eq. (10-3).

gm =

∂I D μCoxW (Vgs − VT ) = ∂Vgs L

(10-3)

Further, by using gm from Eq. (10-3), the gain of the LNA using a common-source topology can be determined if the transistor output impedance R0 and the load impedance RL is known. For the case of MOSFETs in a common-source amplifier, the transistor output impedance is determined by the drain-source resistance and is significantly larger than a

RF Amplifier

143

typical load impedance of 50 ȍ. Therefore, the gain G, can be expressed as in Eq. (10-4).

G = g m ⋅ RL

(10-4)

If, however, a minimum gain is the design requirement imposed on the amplifier, the width of the transistor can be designed according to it instead.

gm =

Gmin RL

Wmin =

(10-5)

Gmin L

(10-6)

μCox RL (Vgs − VT )

To design the LNA according the required noise figure requirements, an established method for determining W can be used.64 In order to design for the minimum noise figure F, given in Eq. (10-7), effects of the transistor geometry on the equation’s parameters are briefly described.

F = Fmin + rn

(G

s

− Gopt ) − (Bs − Bopt ) , Gs 2

2

(10-7)

where

Fmin ≈ 1 +

rn ≈

(

ω 2 γδζ 1 − c ωT

)

γg d 0 gm

Gopt ≈

(10-8)

(10-9)

2

g mωC gs gd 0

(

δζ 1 − c γ

2

)

(10-10)

Chapter 10

144

§ g δζ ·¸ Bopt ≈ −ω C gs ¨¨1 − c m g d 0 γ ¸¹ ©

(10-11)

Gs and Bs are the real and imaginary parts of the source admittance of a common-source amplifier, which may be part of a cascode topology. gd0 is the drain output conductance under zero drain bias, and ǫ, į, ȗ, c are biasdependent factors, and independent of transistor width W. ȦT is the angular cut-off frequency which increases with gate length reduction. Therefore, the minimum gate length is always used to obtain the maximum ȦT. This will result in a minimum value of Fmin according to Eq. (10-8). gd0, gm and Cgs0 scale linearly with W. Therefore, the noise figure F also depends on W. As a result, an inverse relationship between rn and W, shown in Eq. (10-9), implies that increasing W reduces the noise. However, it is necessary to limit W to satisfy the overall power consumption requirements. Still, it is possible for the designer to increase W for a given value of the drain current by decreasing the gate biasing. The designer can make these considerations before proceeding to verify with detailed circuit simulations using accurate transistor models. After deciding the geometry of the transistor for the LNA, analysis to determine the required impedance matching networks at the input and output of the transistor amplifier can be made. The following steps have traditionally been adopted for high frequency designs using discrete transistors whose sizes are pre-determined. These steps, similarly, allow CMOS circuit designers to design the impedance matching networks for the MOSFET circuits that has been characterized through measurement of test structures or simulations. As in the case with discrete transistors, the transistor geometry and biasing have both been pre-determined and the corresponding scattering parameters obtained. Using the scattering parameters, the variations of the source and load impedances to the transistor amplifier can yield the following characteristic loci that are plotted on the smith chart. 1. Stability 2. Gain 3. Noise figure

1.1

Stability

The locus of the source and load impedances on the Smith chart that provides the limit of stability can be determined from the S parameters. |īin| and |īout| are the reflection coefficients of the input and output of the

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transistor amplifier, respectively, as illustrated in Fig. 10-1. To obtain stability, both conditions of |īin| < 1 and |īout| < 1 are required.

Γin = S11 +

S12 S 21ΓL 1 − S 22ΓL

Γout = S 22 +

(10-12)

S12 S 21ΓS 1 − S11ΓS

(10-13)

|īL| and |īS| are the reflection coefficients of the load and source impedance, respectively.

Input Impedance Matching Network

Output Impedance Matching Network

Amplifier

īS īin

īout īL

Figure 10-1. Block diagram of an amplifier indicating the reflection coefficients

When the transistor amplifier is unilateral, S12 = 0. The input and output reflection coefficients result in Eqs. (10-14) and (10-15).

Γin = S11

(10-14)

Γout = S 22

(10-15)

In this case, |S11| and |S22| alone can determine the stability of the transistor amplifier. However, for the general case, |S11| and |S22| alone cannot determine the stability of the transistor amplifier. If they have a value greater than 1, the transistor is definitely not in an unconditionally stable condition. With the proper impedance termination, it can still achieve stability. In order to obtain the boundary of stable impedance terminations on the Smith chart, Eqs. (10-12)

Chapter 10

146

and (10-13) is equated to a value of 1. The values of īL (or īS) satisfying the equation can be plotted on the Smith chart, illustrated in Fig. 10-2, with radius rL (or rS) and center CL (or CS).

rL =

CL

2

S 22 − Δ

(S =

(10-16)

2

)

∗ ∗

22

− ΔS11 2

S 22 − Δ

rS =

CS

S12 S 21

(10-17)

2

S12 S 21 2

S11 − Δ

(S =

11

− ΔS 22 2

(10-18)

2

S11 − Δ

),

∗ ∗ 2

(10-19)

rL

rs

CL

(a) Source impedance chart.

(b) Load impedance chart.

Figure 10-2. Plot of sample stability circles on the Smith chart of the source impedance

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147

where Δ = S11S 22 − S12 S 21 . The stability circles are useful analysis when the transistor is not unconditionally stable. Detailed derivations can be found in Gonzalez.65 Hence, to firstly ensure necessary and sufficient conditions for unconditional stability, 2

2

1 − S11 − S 22 + Δ K= 2 S12 S 21 Δ <1

2

> 1, and

(10-20)

(10-21)

This condition should be checked first, and if unconditional stability is not satisfied, the span of values of the input and output impedance values can be identified from the stability circles.

1.2

Gain

For maximum power transfer from the source to the load, simultaneous conjugate match is applied to the input and output of the amplifier. In this way, the maximum transducer gain, GT,max is obtained.

ΓS = Γin

∗

ΓL = Γout

(10-22)

∗

(10-23)

However, for simultaneous conjugate match to be possible, the stability condition Eq. (10-20) is required. Therefore, the procedure to achieve conjugate match is difficult since īin is a function of īL. For practical designs, a gain different from GT, max may be required. A procedure based on the operating power gain is commonly used. The operating power gain is independent of the source impedance (assumes perfect matching) and allows īL to be selected. Hence, an operating power-gain circle procedure for both unconditionally stable and potentially unstable

Chapter 10

148

transistors is simple and recommended for practical designs. Equations (10-24) and (10-25) provides the equations to determine the radius and the position of the center of the circle on the Smith chart.

rp =

(1 − 2K S

Cp =

2

12

S 21 g p + S12 S 21 g p

(

2

1 + g p S 22 − Δ g p C2

(

2

)

)

1 2 2

(10-24)

∗

2

1 + g p S 22 − Δ

2

)

,

(10-25)

where

gp =

1 − ΓL

2

2

1 − S 22ΓL − S11 − ΔΓL ∗

C2 = S 22 − ΔS11

2

(10-26)

(10-27)

S11, S12, S21, S22 are the measured S-parameters at a given frequency.

1.3

Noise Figure

The noise figure of a two-port amplifier can be alternatively expressed as Eq. (10-28).

F = Fmin +

4rn (ΓS − Γopt )

(1 − F )1 + Γ

2

2

s

2

(10-28)

opt

Fmin, rn and īopt are the noise parameters. The minimum noise figure Fmin can be obtained from the noise figure analyzer when īS =īopt, while īopt itself can be accurately obtained from the vector network analyzer. The noise resistance rn can be obtained by first measuring the noise figure F0 when īS=0 and apply Eq. (10-24).

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149

rn = (F0 − Fmin )

1 + Γopt 4 Γopt

2

(10-29)

2

Equation (10-29) can be expressed as Eq. (10-30) in the form of a circle. 2

ΓS − CFi = rFi , 2

(10-30)

where 2 Fi − Fmin 1 + Γopt 4rn

Ni =

CFi =

rFi =

(10-31)

Γopt

(10-32)

1 + Ni

1 1 + Ni

(

N i + N i 1 − Γopt 2

2

)

(10-33)

Figure 10-3 shows the gain and noise circles plotted together on the same Smith chart.

Fmin

Gmax Smith chart

Figure 10-3. Plot of sample available power gain and noise circles on the Smith chart of the source impedance using sample BJT data

150

Chapter 10

We consider other possibilities at where the amplifier is used. When an amplifier is used at the output stage of the transmitter, the output power can be relatively large and other considerations such as the power-added efficiency (PAE) will be important. Topologies with high PAE can be chosen that satisfies the requirements of the application. One approach is to start by considering the value of the required output power and the expected PAE. From them, the required power drawn from the supply can be estimated. Accordingly, the drain current flowing through the transistor of the amplifier can be calculated and the width of the transistor can be determined. For example, a 2 W high power PA for GSM applications using GMSK modulation requires a nonlinear amplifier and may be operating at 1.9 GHz. Hence, a class E amplifier having a theoretical efficiency of 100% can be considered. It may achieve 70% PAE with a good design under practical conditions. In this case, the total required ID can be calculated and Eq. (10-1) is used to determine W for each transistor used for the amplification. Other applications such as WCDMA and WiMAX supporting OFDMA modulations will require linear amplifiers that call for other specifications. In addition, to attain sufficient output power using CMOS, innovative techniques such as passive power combining66 may be used.

2.

CURRENT-REUSE CASCADE AMPLIFIER

In order to achieve a system with low power consumption operating in the 60 GHz band, the power consumption of each building block has to be minimized by focusing on the elimination of any possible power wastages. In addition, due to the high operating frequency, the millimeter-wave CMOS amplifier has to operate at a significant fraction of the cut-off frequency of the transistor. Currently, it is difficult to obtain sufficient gain using a conventional single-stage amplifier. However, increasing the number of stages in a cascade connection increases the power consumption. Therefore, the approach to optimum power usage is to improve the gain of each single-stage block. In this section, a 60 GHz amplifier has been designed to demonstrate a building block for reduced power consumption. This amplifier implements a current-reuse technique, to be explained in the following sections. Although there are other amplifiers that use an alternative current-reuse technique67–70 for boosting the gain of microwave circuits without having an accompanied increase in power consumption, the technique is difficult to apply at millimeter-wave frequencies since many passive components are required in the circuit, The passive components usually leads to high insertion losses at high frequencies. In this work, a current-reuse technique for gain-boosting without consuming additional power has been proposed through a simple topology.

RF Amplifier

2.1

151

Principles of Operation

During operation, this amplifier reuses the drain current to bias two transistors, as in the case of the cascode topology, and feeding the signal from one stage to the other through a resonance path. A review of the conventional cascode topology, shown in Fig. 10-4(a), reveals that the cascode transistor M2 does not effectively contribute to the gain. The common-gate cascode transistor may increase the output impedance by a factor of gm2⋅r02 where gm2 and r02 is the transconductance and the drainsource resistance of M2, but it does not increase the gain in the amplifier because the load impedance is always limited to a low value in a microwave circuit. The gain is provided by the common-source transistor of the topology. As a result, M2 is mainly used to improve the reverse isolation. To improve the gain, the function of the common-gate transistor M2 should be re-visited. From here, a new cascade circuit shown in Fig. 10-4(b) is proposed, where an inductor at the gate of a common-gate transistor is inserted. By using this gate inductor, the operation of M2 changes from a common-gate amplifier to that of a common-source. A cascade connection is formed by the feed-through of the high-frequency signal through the gatesource capacitor of M2, which results in gain-boosting. This circuit is referred to as a current-reuse cascade amplifier (CRCA), hereafter. The operation of the CRCA is further described below. gate inductor

Vdd ZL

Vout ids2

Vgate

M2 ids1 M1

Vin

Vdd ZL

Vout ids2

Vgate

M2 ids1 M1

Vin (b)

(a) (a)

(b)

Figure 10-4. Schematic of (a) a conventional cascode amplifier with a parallel resonator at an intermediate node and (b) a proposed current-reuse cascade amplifier

Chapter 10

152

The output voltage vout of the LNA can be obtained by Eq. (10-34).

v out = Z L ⋅ id2

(10-34)

ZL is the load impedance and id2 is the drain current through the upper transistor M2. According to Eq. (10-34), vout increases in proportion to id2. However, the cascode transistor does not boost the gain in a common-gate configuration. In addition, a part of the drain current of M1 leaks through gate-source capacitor Cgs2 and parasitic capacitor of an active area. As a result, id2 is usually smaller than id1. When a parallel inductor is added to the source of M2, the parallel resonator is formed with the parasitic capacitance that can prevent the current leak.71, 72 However, even when the ideal parallel resonator is formed, id2 cannot exceed id1. The CRCA is a technique that enables id2 > id1 by using the inductor at the gate of M2. The first order effect of the operation is explained follows. Drain current id1 of M1 is defined in Eq. (10-35).

id1 = g m1 ⋅ vin

(10-35)

The gate inductor forms the series resonator with the M2 gate-source capacitor Cgs2. Hence, the source impedance of M2 approaches to zero at the series resonant frequency, and the maximum id1 flows to the gate through Cgs2. Thus, the gate-source voltage vgs2 of M2 is determined by Eq. (10-36).

vgs2 =

id1 jωCgs2

(10-36)

From this analysis, M2, as in the case of M1, is treated as a commonsource amplifier since the gate inductor and Cgs2 are in series for the small signal. This series combination effectively reduces the impedance at the source of M2. The signal current flowing into the gate thereby results in a second-stage amplification by M2. The expression for id2 is given by Eq. (10-37).

id2 = g m2 ⋅ vgs2 =

f T2 id1 ⋅ . f j

§ g m2 · ¨ ¸ g m2 ⋅ id1 ¨© Cgs2 ¸¹ id1 ωT 2 id1 = = ⋅ = ⋅ ω ω j jωCgs2 j

(10-37)

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153

Consider the magnitude of Eq. (10-37).

id2 =

f T2 ⋅ id1 f

(10-38)

The amount of drain-current boosting using existing technology is estimated. In 90 nm CMOS process, the cutoff frequency of an NMOS with a minimum gate length is approximately 120 GHz. At 60 GHz operating frequency, id2 is doubled according to Eq. (10-37). This leads to twice the value of vout according to Eq. (10-34). Therefore, the output power increases by a factor of four, which corresponds to 6 dB gain enhancement. Figure 10-5 shows 3 topologies of the conventional cascode amplifier, the conventional cascode amplifier with a parallel resonator at an intermediate node and the proposed current-reuse cascade amplifier. Figure 10-6 shows the corresponding output current using the different topologies. The simulation shows that twice the value of id2 flows in the CRCA compared to the normal cascode topology or the cascode with a source inductor. Because the conventional technique only prevents leakage current by the parallel resonance circuit formation, id2 is approximately equal, both with and without the source inductor. On the other hand, the drain current of M2 is considerably boosted in the CRCA to become relatively large.

id2

g

id2

g

s

s

(a)

s id1

id1

id1 (b)

id2

g

(c)

Figure 10-5. Schematics of (a) a conventional cascode amplifier, (b) a conventional cascode amplifier with a parallel resonator at an intermediate node, and (c) a proposed current-reuse cascade amplifier

Chapter 10 Drain current ids2 in M2 (mA)

154 6 5

CRCA

with a parallel resonator

4

basic cascode circuit

3 2 1 0

0

20

40

60

80

100

120

Frequency (GHz) Figure 10-6. Comparison of the drain currents in M2

2.2

Analytical Expression for Circuit Transconductance

An expression for the transconductance Gm of the cascode amplifier with the gate-inductance is derived as a function of the gate inductor. This relationship enables us to understand how the gain is varied according to the inductance value. Consider the small-signal voltage gain of a typical cascode topology using a model as shown in Fig. 10-7. Applying Miller’s theorem on Cgd1 and Cgd2, new equivalent capacitance values of C´gs1, C´ds1, C´gs2 and C´ds2 are obtained. This is a result of

To output matching

Cgd2

Vout Lg

Cgs2

Cds2

ro1

Cds1

gm2.vgs2 Cgd1

Vin From input matching Cgs1

ro2

RL

X

gm1.vgs1

Figure 10-7. Small-signal model of a cascode amplifier

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155

replacing Cgd1 with an equivalent combination of C´gs1 at the gate-source nodes and C´gs1 at the drain-source nodes. Similarly, Cgd2 is replaced with C´gs2 and C´´gs2 respectively. Relating the voltage-current relationships in the circuit and applying Kirchoff’s current law to node X, Eq. (10-34) can be obtained for an infinitely large RL. Av =

g m1ro 2 ⋅ H 2 (ω ) ª 1 H (ω ) § ro 2 ⋅ H 2 (ω ) · º ′ 2 + gm2 ) ⋅ 2 − ¨1 + « − ro 2 ( jωC gs ¸» + 1 H 2 (ω ) G (ω ) © ro1 ⋅ H1 (ω ) ¹ ¼ +1 ¬ g m 2 ro 2 ⋅ G (ω ) (10-34)

Where,

H1 (ω ) =

1 1 + jωCds' 1ro1

H 2 (ω ) =

1 1 + jωCds' 2 ro 2

G (ω ) = 1 − ω 2 Lg Cgs′ 2

'' Cds' 1 = Cds1 + Cgd 1 '' Cds' 2 = Cds 2 + Cgd 2 ' Cgs' 2 = Cgs 2 + Cgd 2

Note that G(Ȧ) is a function of Lg. This provides the relationship between Av and Lg. Equation (10-34) reduces to a well-known expression for the voltage gain of a cascode topology at low frequency in Eq. (10-35).

A v = − g m1 ( g m 2 ⋅ ro1 ⋅ ro 2 + ro1 )

Since Gm =

(10-35)

I out 1 , the expression for Gm as a function of Lg can = Av ⋅ Vin RL

be obtained.

Gm =

g m1ro 2 ⋅ H 2 (ω ) ª RL H (ω ) § ro 2 ⋅ H 2 (ω ) · º −ro 2 ( jωC gs′ 2 + g m 2 ) ⋅ 2 − ¨1 + « ¸ » + RL H 2 (ω ) G ( ω ) r H ( ω ) ⋅ o 1 1 © ¹¼ ¬ g m 2 ro 2 ⋅ +1 G (ω )

(10-36)

Chapter 10

156

2.3

Design of 60 GHz CRCA

For the implementation of 60 GHz CRCA shown in Fig. 10-8, the transmission line is used for providing the required inductance. A length of the transmission line is adjusted to make the resonator at the operating frequency with the gate capacitance. In the circuit, transmission lines are also used to provide the input and output impedance matching. To reduce the physical size and insertion loss of transmission lines, slow-wave transmission lines (SWTL) are used in this work. In Chapter 6, SWTL has shown to have an improved quality-factor and its application in the mixer of Chapter 9 shows less chip area consumption due to the shorter wavelength of the signal propagating in it. The SWTL consists of a signal-carrying conductor at the center and coplanar ground metals at the sides. Slotted ground shields are placed between the signal line and the silicon substrate. In order to perform circuit simulations for the design, a distributed electrical model of the SWTL has been developed and is accurate to within 10% of the measured results. The wavelength reduction allows the SWTL to achieve a physical length reduction factor of 1.89 as have been shown in Fig. 9-3. matching circuit gate transmission line

M2

M1 matching circuit Figure 10-8. Schematic of the CRCA

3.

EXPERIMENTAL RESULTS

The millimeter-wave CRCA is fabricated using a six-metal 90 nm CMOS process. Figure 10-9 shows the micrograph of the fabricated chip. The chip size is 420×600 μm2.

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157

Figure 10-9. Chip micrograph of the CRCA

For the measurements, 1.7 V is applied from the supply voltage, where the vgs of both M1 and M2 is biased at 0.75 V and vds are biased at 0.85 V to maximize transconductances. The power consumption is 18.5 mW. Figure 10-10 shows gain comparison of the circuits. The proposed amplifier shows 7 dB more gain compared to a conventional cascode amplifier. This result corresponds to the estimation described in the previous section. It is noted that although an increase in the gain can be confirmed by adopting a parallel inductor, the effect for the gain boosting is limited. Experimental results show that the gain is 1.6 dB higher than that of the cascode topology with source inductor, though this amount of gain boosting is lower than that of the simulation. The main reason of the discrepancy is 12 CRCA (measurement)

Gain (dB)

10

CRCA (simulation) basic cascode circuit

8 6 4 2 0

with a parallel resonator 50

55

60

65

70

Frequency (GHz) Figure 10-10. Gain comparison between different topologies; measured gain of the CRCA is also shown in the graph

Chapter 10

158

that the terminal layout for the short stubs is not fully optimized, where parasitic resistance and inductance cause design errors of matching circuits and degradation of the resonator’s quality factor. Moreover, parasitic effects result from combining the transistors M1 and M2 in the layout which are not expected to be exactly the same as when the transistors are independently considered in the simulations. As a result, the gain was not sufficiently high and resonating frequency was reduced. Scattering parameters of the CRCA is measured with the network analyzer (37397D/Anritsu) as shown in Fig. 10-11. S21 is 5.1 dB at 60 GHz. S11 and S22 are below –7 dB from 52 to 60 GHz. 10 S11, S12, S21, S22 (dB)

S21

S22

0 -10 S11

-20

S12

-30 0

25

50

75

100

Frequency (GHz) Figure 10-11. Measured scattering parameters of the CRCA

Figure 10-12 shows input and output power characteristics at 60 GHz. 1-dB input-referred compression point at –11.5 dBm. In theory, the IIP3 can be estimated as –1.9 dBm which is higher by 9.6 dB than the 1-dB input-referred compression point. The value is comparable to other works.73, 74

RF Amplifier

159 12 Noise Figure (dB)

10 8 6 4 2 0

54

56

58

60

62

64

Frequency (GHz) Figure 10-12. Output power as a function of input power

4.

CHAPTER SUMMARY

With the flexibility to decide on the MOSFET size, optimized amplifier designs exist for CMOS implementations. It is therefore important to select the right geometry by considering the required specifications for gain, noise and power consumption. Using established techniques to analyze impedance matching at microwave frequencies, impedance matching at millimeter-wave frequency can be determined and implemented with effective passive devices. The design and analysis of the current reuse cascade amplifier has been presented in the chapter. During normal operations, this amplifier reuses the drain current to bias two transistors in cascade, and feeding the signal from one stage to the other through a resonance path between the source and the gate of the cascode common-gate MOSFET. Simulation results show a gain increase of 7 dB is expected using a 90 nm CMOS process without increasing power consumption. The implementation is made by connecting a SWTL distributed inductor at the gate of the common-gate MOSFET to create the resonance path. The amount of gain increase obtained is much larger than that of a conventional cascode circuit with a parallel source inductor, which shows a gain increase of only 1.4 dB. Alternatively, this technique also offers the option to reduce the power consumption under constant gain. This amplifier can be integrated into the transceiver circuit aiming for low power consumption at the 60 GHz band along with other optimized building blocks.

Chapter 11 VOLTAGE CONTROLLED-OSCILLATOR

A millimeter-wave phase-locked loop (PLL) is required to realize a singlechip millimeter-wave CMOS receiver. For the millimeter-wave PLL, a design of a voltage-controlled oscillator (VCO) is described in this section. The voltage-controlled oscillator (VCO) is an important component of the phase-locked loop (PLL) to generate a signal at a stable frequency. High frequency applications including the 76 GHz automotive radar for collision avoidance and adaptive cruise control75 (ACC) using W-band wireless transceivers have become popular. Using the recent process technology, even W-band VCOs, which are one of the essential components in transceivers, have been fabricated by the CMOS process.76–78 Nevertheless, the performances of the reported W-band CMOS VCOs are unsuitable for practical usage due to their narrow frequency-tuning range and large phase noise. In this chapter, we describe a new W-band VCO for automotive radar, using a ring-shaped transmission line to improve the frequency-tuning range and the phase noise. In the following sections, the design principles and measurement results of the W-band CMOS VCO are explained, whose performance is comparable to that of those based on compound semiconductors. In addition, the performance of this millimeter-wave VCO demonstrates the potential of the on-chip transmission lines used.

1.

DESIGN OF 76 GHZ VCO

Conventional VCOs operating in the W-band adopt small varactors and relatively large inductors to increase the resonant impedance of the LC tank for stable operation, even at W-band frequencies. With such VCOs, the tuning range is narrow due to the small varactors, and the phase noise is 161

Chapter 11

162

large due to large inductor loss. Here, let us consider the role of the inductor used for W-band differential VCOs. In the W-band VCOs, a one-turn or half-turn inductor is used. The inductor must be designed as a distributed component, since its wire length cannot be neglected when compared with the wavelength at operating frequencies. In such inductors, an input wave from one port travels to the other port with a time delay, as shown in Fig. 11-1.

resonance reflection

traveling wave

inductive line –gm

varactor

Figure 11-1. Block diagram of a differential VCO. Transmission loss in the inductive line determines resonator quality

Signal

patterned ground shield

Si (a) Conventional inductor GND Signal GND Signal GND

Si

top view (b) Ring-shape transmission line

Figure 11-2. Schematic view of a conventional inductor and a ring-shaped transmission line

Voltage Controlled-Oscillator

163

The traveling wave is reflected and returns after it is amplified by negative conductances composed of MOSFETs. When we consider these processes, transmission loss for the traveling wave in the inductor should be reduced to obtain a high-quality resonator. For this purpose, transmission lines are more suitable than inductors. In this work, the SWTL is adopted for the required low-loss transmission line to obtain a high quality factor. The transmission line is formed in a ring shape with a coaxial ground for the W-band VCO, as shown in Fig. 11-2.

1.0 0.8

Conventional inductor

|S11|, |S21|

S21

Ring-shape transmission line

0.6 0.4 S11 0.2 0.0

0

10

20 30 40 50 Frequency [GHz]

60

Figure 11-3. S-parameters of ring shape transmission line

Figure 11-3 shows the measured scattering parameters of the ring-shaped transmission line and those of a conventional inductor with the same size. The inductances of the ring-shaped transmission line and the conventional inductor are 390 pH and 610 pH, respectively. As shown in Fig. 11-3, the magnitude of S21 of the ring-shaped transmission line is higher than that of the conventional inductor, since the eddy current flowing in the silicon substrate is decreased because the return current flows in the ground metals placed near the signal line in the ring-shaped transmission line. As a result, VCOs with the ring-shaped transmission line are expected to operate with a large bandwidth, which is achieved using the small inductance and large varactors, while maintaining the high resonant impedance of the LC tank by improving the tank quality.

Chapter 11

164

2.

EXPERIMENTAL RESULTS

The proposed W-band VCO with the ring-shaped transmission line is fabricated by a 90 nm 1P6M CMOS process. Figure 11-4 shows the schematics of the VCO.

short stub

C1

Vdd half-ring transmission line

Vctrl harmonic mixer off chip

Figure 11-4. Schematic of the proposed circuit

Figure 11-5. Chip micrograph of W-band VCO

To achieve a 76 GHz VCO, the inductance of 10 pH was used. To realize such a small inductance, a half-ring transmission line is adopted, as shown in the VCO core layout in Fig. 11-5. Note that the signal line uses a top metal layer, which is removed in the ground line to decrease the parasitic capacitance between signal and ground. Additionally, the MOSFET, which

Voltage Controlled-Oscillator

165

is generally used to provide a constant current, is removed to decrease the noise. Alternatively, the current source is replaced with a short stub, which blocks the common-mode noise from the power supply. The fabricated VCO operates at a center frequency of 76.5 GHz with a frequency-tuning range of 7% and a phase noise of –110.6 dBc/Hz at 10 MHz offset at Vdd =0.7 V and Idd =19.4 mA. Figure 11-6 shows the oscillation frequency as a function of control voltage Vctrl from 0.8 to 1.9 V at Vdd =0.7 V.

Frequency [GHz]

82 80 78 76 74 72 70 0.8 1

1.2 1.4 1.6 1.8 Vctrl [V]

Figure 11-6. Oscillating frequencies as a function of control voltage

Under this condition, the oscillation frequency changes from 73.8 to 79.3 GHz. For spectrum measurement, the dedicated sub-harmonic mixer for a spectrum analyzer is used. A screenshot of spectrum measurement is shown in Fig. 11-7(a). Phase noise is measured using the same spectrum analyzer. Note that, for phase-noise measurement, another sub-harmonic mixer, the conversion loss of which is 20 dB lower than that of the dedicated mixer for the spectrum analyzer, is used with an external low-noise frequency synthesizer to convert the output signal down to approximately 5 GHz. A screenshot of phase-noise measurement is shown in Fig. 11-7(b) at Vdd = 0.7 V and Vctrl =1.9 V. The figures of merit (FOMs) and frequency-tuning ranges (FTRs) of the W-band VCOs reported up to now are shown in Fig. 11-8. The FOM is defined in Eq. (11-1).

ª§ f · 2 § ·º 1 ¸¸» FOM = 10 log«¨¨ o ¸¸ ¨¨ «¬© f m ¹ © L( f m ) ⋅ P ¹»¼

(11-1)

Chapter 11

166

Here, f0 is the oscillating frequency, fm is the offset frequency, L(fm) is the phase noise at fm, and P is the power consumption. As shown in Fig. 11-8, both FOM and FTR of the proposed VCO are the highest among the W-band CMOS VCOs, and they are comparable to those of VCOs based on compound semiconductors.

(a)

(b)

Figure 11-7. (a) Output signal spectrum and (b) phase noise spectrum

 =  ?

=  ?

 =  ?

(1/

 

=  ? =  ?

This work

=  ? CMOS

 

=  ?







 (64=?

SiGe InP





Figure 11-8. Figures of merit and frequency tuning ranges of W-band VCOs

Voltage Controlled-Oscillator

3.

167

CHAPTER SUMMARY

A new W-band VCO for automotive radar with a half-ring low-loss inductor was proposed to improve the frequency-tuning range and the phase noise. Using a 90 nm 1P6M CMOS process, the proposed VCO achieved a tuning range of 7% and a phase noise of –110.6 dBc/Hz at 10 MHz offset. The FOM of the proposed VCO is 0.8 dB higher and the tuning range is double compared with those of previously reported CMOS VCOs. These performances are expected to lead to cost and size reductions for future W-band applications.

Chapter 12 CONCLUSION

The history of millimeter-wave has been introduced from the time of Maxwell’s predictions with his famous equations. History of the silicon integrated circuit developed separately from the 1960s. These two fields merged in the 1990s when the operating frequency of silicon circuits reached high gigahertz to make possible CMOS millimeter-wave circuits today. This research focuses on the use of CMOS 90 nm process technology to implement millimeter-wave circuit building blocks for the wireless transceiver. The high frequency analog portion of the wireless transceiver consists of the amplifiers, mixers and oscillators, each performing a specific function according to their roles in either the transmitter or receiver. The design of each block is not trivial, considering the frequency and power requirements for CMOS implementation. In addition, the interconnections will severely affect the performance of the devices. Therefore, simply interconnecting the working devices is not trivial and designs have to be carefully thought over and verified with simulation software. The IC is then realized with effective layout designs for the mask. This would require layout design software and calls for verification tools to ensure that the design meets manufacturing requirements. For sub-100 nm processes, stringent design for manufacturability (DFM) rules will apply. Measured results are obtained with carefullycalibrated use of various chip measurement equipments, including a 110 GHz vector network analyzer. Each of the transceiver’s building blocks has been explained with some of the most important ones fabricated and measured. In certain parts of the transceiver that operates at lower gigahertz frequency, the on-chip spiral inductor is used. In order to use the on-chip inductor effectively, accurate and efficient models are needed. In this work, a broadband model suitable for simulation beyond the self resonant 169

170

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frequency is introduced with the use of fitting equations. These fitting equations are generated through an evaluation of the physical currents flowing in the substrate and at different parts of the inductor. Important fitting techniques using linear and geometric programming on nonlinear monomial equations are explained. Test structures to verify the model have been measured using a 0.35 ȝm CMOS process and a SOI 0.15 ȝm process. The transmission line is another integral part of the transceiver which has to operate up to very high frequency. New low loss transmission lines up to 110 GHz have been developed. The development of these structures is based on the slow-wave propagation characteristics in the SiO2-Si interface. However, instead of relying on material properties (substrate resistivity) to obtain slow waves, we used innovative layout designs to achieve it. The design of the slow-wave transmission line (SWTL) and an asymmetric coaxial waveguide (ACW) are described, fabricated and measured. Both structures are able to obtain a high quality factor and length reduction. Measurement results show that, SWTL achieves a higher quality factor, while the ACW is able to achieve a higher length reduction factor. The idea of the slow-wave phenomenon is extended to the design of an on-chip broadband balun operating from 26.8 to 37.3 GHz. This balun has been tested and characterized for the use in a 20–26 GHz up-conversion mixer. The balun can also be used as a power combiner or a power splitter. Analytical expressions to describe the combiner have been derived to correct errors in existing known equations and are verified by experimental data. Consequently, a 20–26 GHz up-conversion mixer is realized for the automotive radar application that employs two such baluns operating at different frequencies. This demonstration of a fully integrated singlebalanced mixer fabricated on CMOS 90 nm process has a measured power consumption of 11.1 mW. The results obtained are comparable to mixer circuits fabricated using high performance semiconductor processes. The down-conversion mixer is the fundamental device in the wireless receiver. A down-conversion mixer is realized for operation in the 60 GHz license-free band. Due to oxygen attenuation at 60 GHz, wireless devices at the frequency are suitable for secure short-range applications. An important concern in realizing such circuits is the chip area consumption as chip area translates to manufacturing and material cost. This circuit employs the SWTL to reduce the chip size area. The mixer employs a cascode topology with IF output boosting and is fabricated on CMOS 90-nm process. The SWTL allows physical length reductions of 47% when compared to a microstrip line of an equivalent wavelength. To boost the signal to a sufficient level in the transceiver chain, gain amplifiers are used. A 50 GHz variable gain amplifier has been realized using the CMOS 90 nm process by employing an innovative gate resonance technique on

Conclusion

171

a popular cascode circuit configuration to improve the gain. Gain at high frequency is difficult to achieve because the operating frequency for amplification should only be a fraction of f T. This technique is implemented without additional current consumption through a series resonance by using the MOSFET gate-source capacitance with an inductive element at the gate. The inductive element is realized with a transmission line that fits well on the physical layout. The dependence of the cascode transconductance on the gate has been analytically derived and simulated. As a result, this technique can be used to boost gain of the CMOS amplifier at high frequency. Recall that the receiver or transmitter will almost always be realized as a string of operations where each operation is either one of these three frequency domain operations: • a filter, for the suppression of signals outside the wanted channel • an amplifier, to adjust the signal level • a mixer, to change the center frequency

In our research that has been carried out, the critical building blocks of the millimeter-wave wireless transceiver in Fig. 12-1 are made. Future realization of low cost, short range (< 10 m) transceivers can be fully integrated using CMOS. Mid-range transceiver (10~20 m) requires high power transmission and is therefore suitable to be integrated with compound semiconductors or SiGe amplifiers. Future work is therefore expected to

Power Amplifier

Antenna

IF Filter

Filter duplexer

PLL

LNA

Filter

Baseband

PA

Up Conversion Mixer Amplifier

IF

Down Amplifier Low Conversion Noise Amplifier Mixer

Filter

Figure 12-1. The main building blocks in the RF transceiver design for the millimeter-wave band are realized

Chapter 12

172 Low cost, short-range (<10m)

CMOS All-in-One

PA LNA GaAs/SiGe

TX RX

BB

RX

BB

TX

Mid-range (10䌾20m)

CMOS

Figure 12-2. Future realization of short and long range wireless communication building blocks

include the integration of the compound semiconductor technology in addition to the continuing developments of CMOS processes and circuits as illustrated in Fig. 12-2. The future prospect of silicon CMOS for millimeter-wave depends on further scaling possibilities as predicted by Moore’s law, the drive by consumer demands and initiatives in developing the circuits for new breakthroughs. Moore’s law has consistently held true for the past 30 years and will likely continue to persist for the next decade. Process developments had overcome various obstacles and will continue to do so to sustain the infrastructure of the silicon industry. Demand for bandwidth has pushed applications to operate at a higher frequency. Hence, we can only expect the millimeter-wave frequency band uses to increase. As a start, the 60 GHz license free band is a very attractive option for consumer electronics. This will drive CMOS for millimeter-wave applications. Therefore, it is imperative to continue the development of this technology at the circuit level to meet the needs of the next decade.

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Index

1–dB compression point, 116, 123, 125, 126, 132, 133, 140

Common-mode response ratio, 108, 110, 111 Common-mode signal, 59, 109 Common mode S-parameters, 107 Conductivity, 3, 27, 54, 58, 75 Coplanar grounds, 97 Current crowding, 30

Amplifier cascade, 151, 153, 154, 157 current-reuse, 150–153 differential, 50, 52–54, 59, 67, 104, 118, 119 low-noise, 12, 133, 165 power, 12, 14, 124, 141, 171 tuned, 84 variable gain, 14, 141, 170, 171 Amplitude imbalance, 106, 107, 111, 129 Attenuation, 4, 5, 75, 76, 80, 83, 84, 90, 95, 97–99, 106, 115, 170

Density rule, 51, 78 Dielectric permittivity, 56, 88, 94 Differential-mode response ratio, 108 Differential mode S-parameters, 50 Differential signal, 50, 52–54, 59, 67, 104, 118, 119 Distributed circuit model, 87, 101 Dummy port, 105

Balun active, 128, 129, 132 passive, 14, 103, 118, 128, 131 BSIM, 16, 17, 135

Eddy current, 28, 30–32, 34, 40, 44, 46, 50, 51, 79, 104, 163 Equaivalent terminal resistane Filter, 12–15, 84, 95, 115, 116, 132, 138, 171 Floating shields, 50, 54, 60, 95

Capacitor comb, 49–60, 67, 68 MIM, 49 Characteristic impedance, 76, 85, 86, 91, 97, 98, 100 Chip layout, 8, 20, 137, 138 Common mode rejection ratio, 107

Gain, conversion, 117, 123, 124, 126, 127, 132, 140 Gain, power, 126, 147, 149 Gain circle, 147

181

182 Gate-inductance, 154 Gilbert mixer, 116, 128, 135 Green’s theorem, 36 High definition TV, 10 IF-RF isolation, 124–126 Impedance matching, 15, 122, 128, 132, 134, 141, 144, 145, 156, 159 Inductor discrete, 14, 142, 144 distributed, 159 gate, 151, 152, 154 parallel, 152, 157 source, 153, 157, 159 spiral, 14, 169 symmetric, 41 Kirchoff ’s current law, 72, 155 Kirchoff ’s voltage law, 72 License-free, 141, 170 Low-power, 21 Marchand balun, 105, 111, 118–121, 128, 130, 132 Maxwell’s equations, 69–71 Microstrip line, 56, 94, 95, 97–101, 105, 134, 136, 140, 170 Mixer down-conversion, 12, 133–140, 170 up-conversion, 112, 115–132, 170 Moore’s law, 9, 172 Mutual inductance, 32 Noise figure, 14, 23, 116, 142–144, 148, 159 Pad metal layer, 93, 95, 97, 104, 122, 128 Parasitic inductance, 51, 52, 86 Permeability, 58, 75 Phase constant, 75, 76, 80, 83, 84, 90, 95, 97, 98, 101, 136

Index imbalance, 105, 107, 111, 129, 130 locked loop, 6, 12, 15, 138, 161 velocity, 69, 74–76, 80, 83, 84, 91, 94, 101, 135 Physical equations, 89 Power dissipation, 15, 126, 132, 142 Process technology, 6–9, 15, 47, 49, 104, 111, 127, 128, 161, 169 Propagation constant, 71, 80, 82–84, 90, 95 Proximity effect, 27, 28, 31–33 Quality factor, 14, 46, 50, 67, 69, 75, 84, 85, 93, 95, 97–100, 156, 158, 163, 170 Resonance, 14, 29, 87, 151, 153, 159, 162, 170, 171 Return current, 78, 79, 83, 86, 87, 93, 94, 101, 163 Single-balanced, 116, 132 Single-pi model, 28, 30, 32, 36, 43 Singular point, 29, 30, 41, 46 Skin depth, 58 Skin effect, 57 Slot metal shield, 97, 101 Slow-wave, 75–79, 83, 84, 87, 93, 100, 101, 105, 119, 134–136, 156, 170 Stability, 144–147 Stability circle, 146, 147 Substrate resistance, 30, 31, 34, 50, 52, 53, 55, 58, 59, 87 Switching transistors, 117, 119, 122 Telegrapher’s equations, 71, 72, 74, 95 Transceiver, 11–15, 27, 101, 103, 115, 133, 141, 159, 161, 169–171 Transconductance, 116, 117, 128, 134, 142, 151, 154, 157, 171 Transmission line, 9, 14, 15, 50, 51, 58, 69–101, 105, 134–138, 156, 161–164, 170, 171 Two-pi model, 29, 30, 41, 45, 46

Index Vehicular radar, 115, 124 Voltage-controlled oscillator, 15, 161 Waveguide, asymmetric coaxial, 92, 93, 170

183 Waveguide, coplanar, 76, 81, 94, 99, 100 Wiring inductance, 31 Wiring resistance, 28, 31