HANDBOOK
OF
COMPOUND SEMICONDUCTORS Growth, Processing, Characterization, and Devices
Edited by
Paul H. Holloway University of Florida Gainesville, Florida
Gary E. McGuire Microelectronics Center of North Carolina Research Triangle Park, North Carolina
NOYES PUBLICATIONS Park Ridge, New Jersey, U.S.A.
Copyright 0 1995 by Noyes Publications No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without permission in writing from the Publisher. Library of Congress Catalog Card Number: 95-2 1450 ISBN: O-8155-1374-7 Printed in the United States Published in the United States of America by Noyes Publications Mill Road, Park Ridge, New Jersey 07656 10987654321
Library
of Congress
Cataloging-in-Publication
Data
Holloway, Paul H. Handbook of compound semiconductors /Paul H. Holloway and Gary E. McGuire. cm. P. Includes bibliographical references and index. ISBN O-8155-1374-7 1. Compound semiconductors--Handbooks, manuals, etc. I. McGuire, G. E. II. Title. QC611.8.C64H65 1995 95-21540 621.3815’2--dc20 CIP
Editors Rointan F. Bunshah, University of California, Los Angeles (Series Editor) Gary E. McGuire, Microelectronics Center of North Carolina (Series Editor) Stephen M. Rossnagel, IBM Thomas J. Watson Research Center (Consulting Editor)
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Contributors
Shin-ichi Akai Sumitomo Electric Industries Ltd. Itami, Hyogo, Japan
Sidney I. Ingrey Bell Northern Research Ottawa, Ontario, Canada
Kambiz Alavi Department of Electrical Engineering University of Texas at Arlington Arlington, TX
Nan Marie Jokerst Microelectronics Research Center Georgia Institute of Technology Atlanta, GA
Scott A. Chambers Molecular Science Research Center Pacific Northwest Laboratory Richland, WA
Kevin S. Jones Department of Materials Science & Engineering University of Florida Gainesville, FL
Eric Y. Chan Boeing Company Seattle, WA
Avishay Katz Standard Motor Products, Inc. Long Island City, NY
Stephen W. Downey AT&T Bell Laboratories Murray Hill, NJ
Richard Y. Koyama TriQuint Semiconductor Beaverton, OR
Paul H. Holloway Department of Materials Science & Engineering University of Florida Gainesville, FL
Derek L. Lile Department of Electrical Engineering Colorado State University Fort Collins, CO
ix
x
Contributors
Vinod Malhotra Department of Electrical Engineering University of Hawaii Honolulu, HI
Brian J. Skromme Department of Electrical Engineering Arizona State University Tempe, AZ
Gary E. McGuire Microelectronics Center of North Carolina Research Triangle Park, NC
Eberhard Veuhoff Siemens AG Munich, Germany Carl W. Wilmsen Department of Electrical Engineering Colorado State University Fort Collins, CO
Stephen J. Pearton AT&T Bell Laboratories Murray Hill, NJ Rajendra Singh Department of Electrical Engineering Clemson University Clemson, SC
Masamichi Yokogawa Sumitomo Electric Industries Ltd. Itami, Hyogo, Japan
NOTICE To the best of our knowledge the information in this publication is accurate; however the Publisher does not assume any responsibility or liability for the accuracy or completeness of, or consequences arising from, such information. This book is intended for informational purposes only. Mention of trade names or commercial products does not constitute endorsement or recommendation for use by the Publisher. Final determination of the suitability of any information or product for use contemplated by any user, and the manner of that use, is the sole responsibility of the user. We recommend that anyone intending to rely on any recommendation of materials or procedures mentioned in this publication should satisfy himself as to such suitability, and that he can meet all applicable safety and health standards.
Preface
This book is a state-of-the-art reference on the growth and processing of compound semiconductors. The leading experts in the important growth techniques, processing steps, characterization methods, packaging, and devices have contributed their knowledge. While the scope of the book is compound semiconductors, there are so many different semiconductors being studied and used that complete coverage of all materials is impossible in one book. Therefore the emphasis in this book is on gallium-arsenide- and indium-phosphide-based materials. Several other III-V and some II-VI compound semiconductors are discussed where they provide particular insight or illustrate specific properties and/or processes. Chapters in the book provide a complete overview of the technologies necessary to grow bulk single-crystal substrates, and grow hetero- and homoepitaxial films using molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). Technologies necessary to process compound semiconductors into test structures and devices are covered, including electrical contacts, dielectric isolation, interface passivation, ion implantation, wet and dry etching, and rapid thermal processing. Techniques to characterize the materials and devices using electrons, ions, and photons, are described. While the emphasis of the book is on materials growth and processing, the technologies are placed in perspective by a review of the important electronic and optoelectronic devices, and epitaxial lift-off, and other device packaging issues.
vii
viii
Preface
With this complete coverage of the critical topics, we believe the book will be a valuable reference for persons currently performing research on compound semiconductors. It will also be an excellent reference for advanced graduate courses in materials science, electrical engineering, and applied physics. In ourjudgement, the authors ofthe chapters have provided exceptionally comprehensive, authoritative work, and for this we are extremely grateful September,
1995
Gainesville,
Florida
Research Triangle Park, North Carolina
Paul H. Holloway Gary E. McGuire
Contents
1
Bulk Crystal Growth ............................................ Shin-ichi Akai and Masamichi
1
Yokogawa
1 INTRODUCTION ................................................................................ 1.0 REDUCTION OF DISLOCATION DENSITY ........................... .2 .4 2.0 HB GaAs ................................................................................ .4 2.1 Cooling Methods ............................................................... 2.2 Influence of Solid-Liquid Interface Shape ........................... .4 7 3.0 LEC GaAs ................................................................................. 7 3.1 History of Technology Development.. .................................. 9 3.2 Carbon Control.. ................................................................. 11 3.3 Annealing ......................................................................... 12 3.4 Vth Control ...................................................................... 15 3.5 Large-Diameter Crystal .................................................... 17 4.0 InP ............................................................................................ 17 4.1 Low-Dislocation InP ......................................................... 21 4.2 Semi-Insulating InP .......................................................... 22 5.0 SUMMARY .............................................................................. . ...................................................................................... 23 REFERENCES 23
xi
xii
Contents
2
MOCVD of Compound Semiconductor
Layers
29
INTRODUCTION ..................................................................... GROWTH PROCESS ............................................................... 2.1 Reactor Design ................................................................. 2.2 Growth Precursors ............................................................ 2.3 Safety Aspects .................................................................. 3.0 SPECIFIC MATERIAL SYSTEMS ........................................... 3.1 GaAs and InP Based Materials ......................................... 3.2 Narrow Bandgap Materials ............................................... 3.3 Wide Bandgap Materials ................................................... 4.0 SUMMARY AND FUTURE DIRECTIONS .............................. ACKNOWLEDGMENT ..................................................................... REFERENCES ...............................................................................
29 31 32 33 36 37 38 56 63 72 74 74
3
84
Eberhard
Veuhoff
1.O 2.0
Molecular Beam Epitaxy .................................... Kambiz Alavi
1.O
2.0
3 .O 4.0
INTRODUCTION 1.1 Scope of Molecular Beam Epitaxy .................................... 1.2 Major Factors in the Initial Development of MBE ............. 1.3 MBE Reference Material .................................................. 1.4 Synopsis.. ......................................................................... IMPORTANT FEATURES OF MBE ......................................... 2.1 III-IV Environment and Ultra-High Purity Source Material 2.2 In-Situ Real-Time Monitoring and Control on a Sub-Monolayer Scale.. ..................................................... 2.3 Important Features of the MBE Growth Mechanism ......... 2.4 In-Situ Processing and Lateral Patterning .......................... 2.5 Variations on the Theme of MBE ...................................... ......................................... MBE SYSTEM CONFIGURATION THE GROWTH CHAMBER COMPONENTS ........................ 4.1 The III-IV System ............................................................ 4.2 Beam Generation ............................................................ 4.3 The Substrate Holder ...................................................... 4.4 Ion Gauges: Measurement of Beam Flux, Growth Rate, and Composition .............................................................
84 88 90 91 91 92 94 .95
97 98 99 10 1 103 104 112 114
Contents
4.5 Crystal Thickness Monitor: Flux Measurement ............... 4.6 Substrate Temperature Measurement ............................... 5.0 REFLECTION HIGH ENERGY ELECTRON DIFFRACTION @HEED) ...................................................... 5.1 Surface Reconstruction: General ..................................... 5.2 Surface Reconstruction: GaAs ........................................ 5.3 RHEED Intensity Oscillation and its Application.. ........... ...................................................... 6.0 MASS SPECTROMETRY 6.1 Modulated Beam Mass Spectrometry (MBMS) ............... 6.2 Desorption Mass Spectrometry (DMS). ........................... 7.0 IN-SITU AUGER ELECTRON SPECTROSCOPY (AES) ...... 8.0 OPTICAL METHODS FOR REAL-TIME GROWTH MONITORING ....................................................................... 8.1 Optical Pyrometry .......................................................... 8.2 Transmission Spectroscopy ............................................. 8.3 Photoluminescence: Low Substrate Temperature Measurement .................................................................. 8.4 Reflectance Difference Spectrometry (RD) ...................... 8.5 Laser Light Scattering (LLS) .......................................... 8.6 Spectroscopic Ellipsometry ............................................. 9.0 GROWTH OF III-V COMPOUNDS ....................................... 9.1 Substrate Preparation Prior to Transfer to MBE .............. 9.2 Substrate Preparation in the MBE System ....................... 9.3 MBE Growth .................................................................. ............................. 10.0 POST-GROWTH CHARACTERIZATION ................................................ 10.1 Structural/Compositional ................................... 10.2 Electrical and Magneto-Transport 10.3 Optical and Infrared Spectroscopy .................................. 10.4 Structural Defects in III-V Compound Epilayers ............. 11.O BUILDING BLOCKS OF MODERN DEVICES: BANDGAP ENGINEERING IN III-V STRUCTURES ............................... 11.1 Doping ........................................................................... 11.2 Quantum Wells and Superlattices .................................... 11.3 Strained-Layer Superlattices and Quantum Wells ............ 11.4 Bandgap Grading and Chirped Superlattices.. .................. 12.0 EPILOGUE ............................................................................. ................................................................. ACKNOWLEDGMENTS REFERENCES .............................................................................
xiii
114 115 115 117 118 125 134 134 137 137 139 140 14 1 14 1 142 142 142 143 144 147 149 149 150 150 15 1 15 1 153 154 154 155 156 156 15 7 157
xiv
Contents
4
Physical and Chemical Depo Ohmic Contacts to InP and R Avishay
Katz
INTRODUCTION ............................... OHMIC CONT FUNDAMENTALS 2.1 Generic Definition of Schottky 2.2 Interface States and Fermi-Leve 2.3 Determination of Schottky Bar 2.4 Determination of Ohmic Conta and Related Materials .............. 2.5 Concepts of Formation of Ohm InP-Based Materials ................ DESIGN CONCEPTS OF PROCESS 3.0 CONTACT TO InP.. ........................... 3.1 Conceptual Assumptions ......... 3.2 Interfacial Reaction Concerns 3.3 Electrical Performance Require 3.4 Thin Film Mechanical Propertie 4.0 OHMIC CONTACT PROCESSING 4.1 Introduction ................................ 4.2 Contact Processing by Metal 4.3 Contact Processing by Chemica 5.0 CONCLUSIONS ................................. ............................ ACKNOWLEDGMENTS .......................................... REFERENCES
1.0 2.0
5
Surface Processing of III-V Sidney
1.O 2.0
I. Ingrey
INTRODUCTION .............................. REACTIONS ON CLEAVED (110) 2.1 Hydrocarbon Contamination . 2.2 Native Oxides on III-V Compo 2.3 Br/CH,OH ................................. 2.4 H,SO,/H,O, ............................... ....................................... 2.5 HCl ....................................................................... 263 2.6 NH,OH263 ....................................... 2.7 I-IF
Contents
xv
3.0
EFFECTS OF AIR-FORMED CONTAMINATION ON INTERFACE CHARACTERISTICS ................................... 3.1 Epitaxial growth ............................................................. 3.2 Schottky and Ohmic Contacts ......................................... 3.3 Dielectric Overlayers ...................................................... 4.0 CONTAMINATION REMOVAL ............................................ 4.1 Sputter Removal ............................................................. 4.2 Plasma Surface Treatments ............................................. 4.3 Thermal Desorption ........................................................ 4.4 UV/Ozone Oxidation ...................................................... 5.0 SURFACE PASSIVATION ..................................................... 6.0 APPLICATIONS ..................................................................... 7.0 SUMMARY AND CONCLUSIONS ....................................... ACKNOWLEDGMENTS ................................................................. REFERENCES .............................................................................
6
Ion Implantation Induced Extended Defects in GaAs .............................................................
263 263 264 267 270 270 270 27 1 27 1 272 276 280 28 1 28 1
285
Kevin S. Jones 1.O
2.0 3 .O 4.0 5.0 6.0
TYPE I DEFECTS ................................................................ 1.1 Type I Defect Formation ................................................. 1.2 Type I Defect Formation Thresholds ............................... 1.3 Type I Defect Density and Distribution.. .......................... 1.4 Type I Defect Stability .................................................... I.5 Effects of Type I Defects ................................................. TYPE II DEFECTS ................................................................. TYPE III DEFECTS ................................................................ TYPE IV DEFECTS ................................................................ TYPE V DEFECTS ................................................................. CONCLUSIONS .....................................................................
REFERENCES
7
.............................................................................
286 289 289 297 301 302 312 3 14 3 15 316 324 325
Passivation of GaAs and InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Vinod Malhotra and Carl FK Wilmsen
1.O 2.0
SURFACE DEFECTS, FERMI-LEVEL PINNING, AND DEFECT MODELS . . . . . . . . . . . . . . . . . . . t.. . . . . . . . . . . 33 1 NATIVE OXIDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
xvi
Contents
3 .O HYDROGEN AND NITROGEN ............................................. 4.0 SULFUR ............................................................................. 5.0 SELENIUM.. ........................................................................... 6.0 SILICON ............................................................................. 7.0 EPITAXIAL REGROWTH ..................................................... 8.0 EPILOGUE ............................................................................. ACKNOWLEDGMENTS ................................................................. REFERENCES .............................................................................
8
Wet and Dry Etching of Compound Semiconductors .................................................
3 36 342 357 358 360 361 362 362
370
Stephen J. Pearton 1.O 2.0
INTRODUCTION ................................................................... WET CHEMICAL ETCHING ................................................. 2.1 General Principles.. ......................................................... 2.2 Wet Chemical Etching of GaAs ....................................... 2.3 Wet Etching of InP ......................................................... 2.4 Wet Etching of InGaP.. ................................................... 2.5 Wet Etching of AlInP ...................................................... 2.6 Wet Etching of Other III-V Materials .............................. 3.0 PLASMA ETCHING.. ............................................................. 3.1 General Principles of RIE ............................................... 3.2 Gas Chemistries.. ............................................................ 3.3 Surface Chemistry .......................................................... 3.4 Damage.. ........................................................................ 3.5 Masking Materials .......................................................... 3.6 Electron Cyclotron Resonance Discharges ....................... 3.7 Device Processing.. ......................................................... 4.0 CONCLUSION ....................................................................... ACKNOWLEDGMENTS ................................................................. REFERENCES .............................................................................
9
Rapid Isothermal Processing (RIP) .................
370 370 371 373 377 379 380 38 1 382 384 387 397 402 4 14 42 1 426 437 437 437
442
Rajendra Singh 1.O 2.0 3.0 4.0
INTRODUCTION ................................................................... WHY RAPID ISOTHERMAL PROCESSING?. ...................... HISTORY OF RAPID ISOTHERMAL PROCESSING.. ........ SCOPE OF RAPID ISOTHERMAL PROCESSING ...............
442 443 .447 447
Contents
xvii
5.0
PRINCIPLES OF RAPID ISOTHERMAL PROCESSING ..... .448 448 5.1 Operating Principle of RIP.. ............................................ 5.2 Interaction of Radiation with the Sample ......................... 449 5.3 Thermal Dynamics and Temperature Calculations .......... ,452 5.4 Fundamental Differences Between Furnace and 453 Rapid Isothermal Processing ........................................... 454 5.5 Role of Photoeffects in RIP ............................................. 456 5.6 Thermal Stress and Control of Defects ............................ 6.0 EXPERIMENTAL RESULTS IN SUPPORT OF 458 PHOTOEFFECTS IN RIP ....................................................... 458 6.1 Surface Cleaning of Semiconductors ............................... 458 6.2 W Annealing.. ............................................................... 460 6.3 Oxidation ....................................................................... 460 6.4 MBE and Gas Source MBE ............................................ 460 6.5 Chemical Vapor Deposition ............................................ 6.6 Metalorganic Chemical Vapor Deposition ....................... 46 1 7.0 DESIGN OF EQUIPMENT AND ENGINEERING ISSUES .. .466 466 7.1 Basic Characteristics of RIP Systems .............................. 7.2 Temperature Measurement, Control, and Uniformity ...... ,472 7.3 Current Status of Commercial RIP Systems .................... 479 480 7.4 Future Direction ............................................................. 48 1 8.0 VARIOUS APPLICATIONS OF RIP ...................................... 8.1 Stand-Alone Systems for the Annealing of 48 1 Various Materials ........................................................... 8.2 Stand-Alone Systems For the Formation of Silicides ....... .49 1 8.3 Stand-Alone Systems for Shallow Junction Formation 491 and Non-Alloyed Ohmic Contacts ................................... 8.4 Chemical Vapor Deposition (CVD) and Metalorganic 493 Chemical Vapor Deposition (MOCVD) ........................... 494 8.5 In-Situ and Integrated Processing .................................... 9.0 RESULTS OF VARIOUS DEVICES AND CIRCUITS.. ........ .498 500 10.0 FUTURE APPLICATIONS ..................................................... 500 11 .O CONCLUSION ....................................................................... 50 1 ACKNOWLEDGMENT ................................................................... 50 1 REFERENCES .............................................................................
10
Epitaxial Lift-Off for Thin Film Compound Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . 518 Nan Marie Jokerst
1.O
INTRODUCTION
........... . .
........ .......... ...... ...... .... .
. . . . . . 5 18
xviii
Contents
THIN FILM DEVICE FORMATION AND BONDING ......... 2.1 Gallium Arsenide Based Thin Films ................................ 2.2 Indium Phosphide Based Thin Films ............................... 2.3 Modified Epitaxial Lift-Off Processes ............................. 3.0 CHARACTERIZATION OF EL0 THIN FILMS .................... 3.1 Photoluminescence, Hall Measurements, and Minority Carrier Lifetime ............................................... 3.2 Laser Threshold Current and Dark Current ..................... 4.0 NEW THIN FILM CHARACTERIZATION TECHNIQUES AND DEVICES.. ..................................................................... 4.1 Characterization Techniques: Absorption Coefficients and Nonlinear Refraction ................................................ 4.2 New Device Formulations: Resonant Cavity and Bottom Contacted ........................................................... 5.0 NEW INTEGRATION FORMULATIONS USING THIN FILMS .......................................................................... 5. I Thin Film Optoelectronic and Optical Devices on Host Substrates .......................................................... 5.2 Thin Film Circuits on Host Substrates ............................. 5.3 Three-Dimensional Integration ........................................ 6.0 CONCLUSIONS ..................................................................... ............................................................................. REFERENCES
.521 522 527 528 534
Packaging ..........................................................
563
2.0
11
535 536 539 540 542 544 545 552 555 558 560
Eric E Chan 1.O 2.0
3.0
563 INTRODUCTION ................................................................... III-V OPTOELECTRONIC DEVICE PACKAGES ................. 564 564 2. I Laser Diode Packages ..................................................... 578 2.2 LED Packages ................................................................ 2.3 Semiconductor Optical Amplifier (SOA) Packaging ........ 585 589 2.4 Detector Packages .......................................................... MULTICHANNEL DEVICE PACKAGES FOR OPTICAL 594 INTERCONNECT APPLICATIONS ....................................... 594 Introduction ................................................................... 3.1 5 94 3.2 LED Array Packaging .................................................... 596 3.3 PIN Detector Array Packaging.. ...................................... 3.4 Individually Addressable Laser Array Packages ............. .600 3.5 Hybrid Optoelectronic Integration Using a 603 Silicon Wafer Board ....................................................... 605 3.6 Array Issues ...................................................................
Contents
xix
4.0
HIGH FREQUENCY GaAs DIGITAL AND MICROWAVE INTEGRATED CIRCUIT PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 4.1 High Frequency GaAs Digital Integrated Circuits Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . 607 4.2 Monolithic Microwave Integrated Circuit Packaging . . . . . . .608 5 .O CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 REFERENCES . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10
I2
Chemical, Structural and Electronic Characterization of Compound Semiconductor Surfaces and Interfaces by X-ray Photoelectron Spectroscopy and Diffraction Techniques ....... 613 Scott A. Chambers
INTRODUCTION ................................................................... 1.1 Overview of the Topic .................................................... SPECTROSCOPY AND 2.0 X-RAY PHOTOELECTRON DIFFRACTION.. ..................................................................... 2.1 The Essential Experiments and Interpretations ................. 3.0 CHEMISTRY OF SURFACE AND INTERFACE FORMATION ......................................................................... 3.1 Oxide Formation and Removal from GaAs(OO1). ............. 3.2 Metal/III-V Compound Semiconductor Interface Formation ....................................................................... 4.0 DETERMINATION OF ELECTRONIC ENERGY LEVELS AT COMPOUND SEMICONDUCTOR SURFACES AND INTERFACES BY XPS .......................................................... 4.1 Measurement of Band Bending and Schottky Barrier Heights ............................................................... 4.2 Measurement of Surface State Charge Densities .............. 4.3 Measurement of Band Offsets ......................................... 5.0 STRUCTURE OF THE NEAR-SURFACE REGION ............................................................................. BY XPD 5.1 Surface Termination of HgCdTe( 111) ............................. 5.2 Surface Passivation of III-V Semiconductor Surfaces with Group VI Anions .................................................... 6.0 CONCLUSIONS ..................................................................... ................................................................... ACKNOWLEDGMENT REFERENCES ............................................................................. 1.0
6 13 613 6 14 6 14 623 623 627
632 632 636 639 646 646 648 649 650 650
xx
Contents
13
Characterization of Compound Semiconductor 653 Material by Ion Beams ..................................... Stephen K Downey
INTRODUCTION ................................................................... 1.1 RBS References .............................................................. SIMS References ............................................................ 1.2 1.3 Fundamentals of Ion-Solid Interactions .......................... RUTHERFORD BACKSCATTERING SPECTROMETRY 2.0 ................................................................... (RBS) Kinematics ................................................................... 2.1 Depth Resolution ........................................................... 2.2 2.3 Nuclear Reactions ........................................................... Channeling ..................................................................... 2.4 SECONDARY ION MASS SPECTROMETRY (SIMS) 3.0 AND RELATED TECHNIQUES ............................................ . ............................ Sputtering.. ........................................ 3.1 3.2 Depth Profiling ............................................................... Depth Resolution ............................................................ 3.3 Static SIMS .................................................................... 3.4 Preferential Sputtering .................................................... 3.5 Mass Spectrometers ........................................................ 3.6 Matrix Effects ................................................................ 3.7 Sputtered Neutral Mass Spectrometry (SNMS) ............... 3.8 Depth Profiling with SNMS ............................................ 3.9 3.10 Other Alternative Techniques .......................................... ............... ............ .......... .. ..... ...... ........ ....... . .... REFERENCES 1.0
14
Optical Characterization of Compound Semiconductors .................................................
65 3 654 654 655 656 656 659 660 660 66 1 661 662 663 666 667 667 669 672 672 675 675
678
Brian J. Skromme 1.O 2.0
................................................................... INTRODUCTION EXPERIMENTAL TECHNIQUES AND ........................................................... INSTRUMENTATION 2.1 Light Sources ................................................................. Spectrometers ................................................................. 2.2 Detectors ........................................................................ 2.3 Cryogenics ..................................................................... 2.4 Sample Mounts.. ............................................................. 2.5 Optics ............................................................................. 2.6
678 680 680 68 1 685 686 687 688
Contents
xxi
3.0
BASIC THEORY AND APPROACHES ................................. Luminescence ................................................................. 3.1 Raman Scattering ........................................................... 3.2 Reflectance and Modulated Reflectance ........................... 3.3 4.0 APPLICATIONS.. ................................................................... Intrinsic Materials Properties .......................................... 4.1 Impurities and Defects .................................................... 4.2 Strain ............................................................................. 4.3 Surfaces and Interfaces ................................................... 4.4 5.0 SUMMARY ............................................................................ ................................................................. ACKNOWLEDGMENTS LIST OF ACRONYMS.. ................................................................... ............................................................................. REFERENCES
689 689 713 7 16 720 720 726 744 748 751 752 752 754
15
Gallium Arsenide Microelectronic Devices and 772 Circuits .............................................................. Richard E Koyama
773 A BRIEF HISTORICAL PERSPECTIVE ................................ 775 GALLIUM ARSENIDE CRYSTALS ...................................... Some Basic Properties of Gallium Arsenide.. ................... 775 2.1 Some Basic Physics of Gallium Arsenide ........................ 778 2.2 LEC Crystal Growth of Gallium Arsenide.. ..................... 780 2.3 3 .O GALLIUM ARSENIDE DEVICES AND STRUCTURES ...... .783 Metal Semiconductor Field Effect Transistors ................. 784 3.1 794 Junction Field Effect Transistors ..................................... 3.2 795 High Electron Mobility Transistors ................................. 3.3 797 Heterojunction Bipolar Transistors .................................. 3.4 798 Other Advanced III-V Device Structures ......................... 3.5 ........... 799 4.0 GaAs MESFET IC FABRICATION TECHNOLOGY.. 799 Ion Implantation and Anneal ........................................... 4.1 Dielectric Deposition, Definition, and Etching ................. 803 4.2 Metal Deposition, Definition, and Etching ....................... 804 4.3 Photolithography in GaAs MESFET Fabrication ............. 806 4.4 806 GaAs MESFET IC Process Technology .......................... 4.5 809 5.0 APPLICATIONS of GaAs MESFET ICs ................................. 8 12 ............................................................................. REFERENCES 1.O 2.0
xxii
Contents
16
Optoelectronic
Devices .....................................
813
Derek L. Lile 8 13 1.O INTRODUCTION ................................................................... 8 15 2.0 THE?SOLID STATE LASER ................................................... 823 3.0 MODULATORS AND SWITCHES ........................................ 4.0 OPTOELECTRONIC INTEGRATED CIRCUITS (OEICs) .... .842 4.1 Optical Communications ................................................. 842 846 4.2 Optical Interconnects ...................................................... 849 4.3 Optical Computing ......................................................... 856 ACKNOWLEDGMENTS ................................................................. 856 REFERENCES .............................................................................
Index . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . ..*...........................
866
1 Bulk Crystal
Growth
Shin-ichi Akai and Masamichi Yokogawa
INTRODUCTION III-V compound semiconductors are widely used as substrates for optical devices such as LED’s and laser diodes and for electronic devices such as FET’s, HINT’s, HBT’s and IC’s. These applications are becoming key elements in an advanced information society. In this chapter, our focus is on GaAs and InP and recent advancements in their crystal growth technology. Horizontal Bridgman (HB) and Liquid Encapsulated Czochralski (LEC) are two representative growth methods of III-V compound crystals. The HI3 method is favorable for reducing the dislocation density and is, therefore, used in providing substrates for optical devices. The LEC method is advantageous for increasing the crystal diameter and is, therefore, used in providing substrates for electronic devices. Incorporating the advantages of both growth methods, practical applications of early hot wall crystal growth techniquestll such as Vertical Gradient Freeze (VGF)121,Vertical Bridgman (VB)131and Liquid Encapsulated Vertical Bridgman (LEVB)141have recently been tried. The basic objectives in the development of crystal growth technology are larger crystals (diameter and length), reduction of crystal defects (such as dislocation) and higher purity. In addition, stoichiometry control is important in the case of compound crystals.
1
2
Compound Semiconductors
1.0
REDUCTION OF DISLOCATION
DENSITY
Dislocations affect device performance. Therefore, the reduction of dislocation density is a very important issue in crystal growth technology. Various techniques to achieve low dislocation density are summarized in Fig. 1. Among them are the reduction of thermal stress (or reduction of temperature gradient) and the increase of critical resolved shear stress. It has been reported by Matsumoto et a1.151 that a roof-shaped thermal baffle installed on the top of a heat shield alleviated very strong gaseous convection in a chamber, thus reducing the temperature gradient in the B,O, layer to 30 - 6OWcm. This gradient is about one third of the temperature gradient in the conventional LEC method. The radiation effect becomes more significant in LEC-grown crystals having a high melting point. In a conventional single-zone heater puller, the heat outflow from the surface of growing crystals is large because of the heat radiation toward the cold chamber wall. Consequently, the temperature gradient at the solid-liquid interface becomes large. On the other hand, in a puller with a multi-zone heater, the heat inflow to the surface of a growing crystal is large because of the heat radiation from the after-heater and consequently, the temperature gradient can be reduced161 A low temperature gradient means that the
r Reduction of thermal stress Reduction of temperature gradient >
r(
9
improved hot zone Multizone heater FEC (Fully Encapsulated Czochralski)
l-
Ambient gas
I
Control of stoichiometry
Prevention of As (or P) dissociation
I
I-
L- Melt
Increase Of CRSS ___I I
composition
Isoelect,ronic doping In, B (for GaAs) t
Ga, As (for InP)
Fire 1. Various approaches to the reduction of dislocation density in III-V compound semiconductor crystals.
Bulk Crystal Growth
3
solidified crystal stays at elevated temperature longer and therefore, the group V element tends to dissociate from the crystal surface. LEC growth with a low temperature gradient requires a special measure to suppress the dissociation of group V elements. Crystal growth in an arsenic (or phosphorus) atmosphere l~[i~l and crystal growth with full encapsulation by B,O,[“l have been attempted. The stoichiometry of the crystal also affects the dislocation density.[121-[141 The effect of impurity doping on the dislocation density and dislocation mobility in semiconductor crystal is well-known. In order to obtain a semi-insulating crystal for IC applications, an isoelectronic impurity must be used. For GaAs, these dopants are N, Al, In, Sb, B and P.[i51-11*l However, to date, only indium doping has been effective for obtaining lowdislocation, semi-insulating GaAs crystals of an industrially useful size (that is, with a diameter larger than 2 inches and a lot size greater than 50 wafers). [1gl-[211 Doping with inditmr, together with the VM-FEC (Vertical Magnetic field applied, Fully Encapsulated Czochralski) method, has enabled the growth of dislocation-free and striation-free GaAs crystal~.[~il A 4” diameter dislocation-free GaAs crystal has been obtained using this method.t221 While In doping yields materials of high quality, it has the disadvantages of smaller lot sizes and higher wafer costs in comparison with conventional rmdoped crystals. This is due to the fact that a cellular structure is generated during crystal growth, thus greatly reducing material yield. This phenomenon occurs when the In concentration in the melt exceeds a critical value. The melt then goes to a compositional supercooled state. In order to retard the generation of this cellular structure, two techniques have been tried. The first method is the G/R techniqueI23l in which the temperature gradient (G) and the growth rate (R) are simultaneously controlled, and the second is a double crucible method[24l in which the segregation coefficient of In in GaAs is artificially adjusted to unity. The In doping method is also effzctive in HB GaAs crystal growth.Izl Because the HB method has a lower temperature gradient compared to the LEC method, the In concentration necessary for reducing the dislocation density is relatively small. Horizontal Zone Melting (I-IZM), which can alter an impurity segregation coefficient, has been tried in order to obtain a uniform impurity distribution along the growth direction.t261 Isoelectronic impurities for InP are Ga, As and Sb. An impurity segregation coefficient is not generally unity, and therefore, the impurity concentration changes along the growth direction. Accordingly, co-doping of two kinds of impurities, where the segregation coefficient of one impurity
4
Compound Semiconductors
is smaller than tmity and that of the other impurity is larger than unity, has been tried to obtain a uniform distribution of total impurity concentration in hlP crystal.161
2.0
HB GaAs
The HB method is extensively employed as a low dislocation density crystal growth technique. This is because reduction of the temperature gradient is relatively easy and precise control of the stoichiometry is possible in comparison with the LEC method. Basic approaches to achieve a low dislocation density have already been described in the previous section. This section addresses the methods of cooling a solidified crystal and the solid-liquid interface shape in order to obtain very low dislocation density GaAs crystals. 2.1
Cooling Methods
Figure 2 shows a schematic diagram of the HB method. An entire ingot is kept in the T2 zone after solidification at the solid-liquid interface and then gradually cooled to room temperature. A temperature distribution is generated in the crystal during this cooling process, and accordingly, thermal stress is induced in the crystal. Since GaAs is more susceptible to dislocation’s generation and propagation at low temperature by lower thermal stress in comparison with Si, optimization of the cooling process is critical for the reduction of dislocation density. Figure 3 shows the influences of the cooling process and crystal diameter on the dislocation density. When the cooling rate is 5 - 1O”C/h in the temperature range between 900°C and 1,2OO”C,the etch pit density (EPD) of 2” diameter crystals can be reduced to lower than 5,000 cmm2.However, when the cooling rate is 10 100°C/h in the same temperature range, the EPD increases to about twice this value. 2.2
Influence of Solid-Liquid Interface Shape
It has been found that the generation of lineage, which is a collection of dislocations, is related to the shape of the solid-liquid interface in LECY2’l and GF (Gradient Freeze) growth.12*l We have investigated the relation between the solid-liquid interface shape and the dislocation density by doing
Bulk Crystal Growth
5
AB etching[29]on Si-doped lIB GaAs crystals. These crystals were grown along the [ III] crystallographic direction, and samplewafers were then cut along the [211] direction, which is parallel to a free surface of the ingot. The results are shown in Fig. 4. The shapeof the solid-Iiquid interface of case (a) is nearly flat and the EPD is quite low across the wafer. On the other hand, the solid-Iiquid interface shapeof case(b) is not symmetric from right to left and shows a strong concavity toward the melt. The EPD in the corresponding region is high. Figure 5 shows the EPD maps of a 2" diameter Si-dopedlIB GaAs crystal grown in a thermal environment, which makes the solid-Iiquid interface shapesymmetric and flat. It shows that the entire ingot has an EPD of less than 400 cm-2.
Figure
2.
Schematic
crystal growth
method.
diagram
of three-temperature
zone lIB
(Horizontal
Bridgman)
6
Compound Semiconductors
DIAMETER OF WAFER [mm] Figure 3. Cooling rate dependence of EPD of HE3 grown GaAs crystal. Cooling rate in the temperature range between 900°C and 1,200T is (a) 10 - lOO”Cih, and (b) 5 - lO”C/h.
(a)
(2iT)plane
(XlO*cm*)
Ave Max
1 10cmq 700cmQ
(b) (277) plane (XlO*cm.*)
Ave 960cm” Max 5.2OOcm.*
Figure 4. Relationship between solid-liquid interface shape and dislocation Solid-liquid interface shape is (a) flat, and (7~)not symmetric from right to left.
density.
Bulk Crystal Growth
7
Wafer No.
EPD
Average
(Cm21 Maximum
3.6X102
1.6X102
0.1 x102
13.0x102
6.0X102
l.0X102
iartier Concentration (cl-n-s)
1.3x10’s
1.7x10’s
3.0x10’s
Fraction Solidified
0.10
0.37
0.70
Figure 5. EPD maps of 2” diameter Sidoped HB grown GaAs. Fraction solidified means the wafer position along the growth direction.
3.0
LEC GaAs
3.1
History of Technology Development
LEC GaAs crystal growth technology has made progress toward providing a substrate for use in GaAs IC fabrication. Figure 6 shows the trend of crystal technology for GaAs IC’s. Undoped semi-insulating GaAs crystals were developed in the late 1970’s using an LEC technique with a pyrolytic boron nitride (PBN) crucible instead of quartz.[301 Semi-insulation in undoped LEC GaAs is realized by compensating the carbon-originated shallow acceptor with the deep donor EL2.r311The EL2 concentration strongly depends on melt composition[321and it is higher in a crystal grown from an As-rich melt. It is lower in a crystal grown from a Ga-rich melt. These issues are particularly important for GaAs MESFET, a type of GaAs IC fabricated by the ion implantation technique.[331 In a wafer, the threshold voltage (Vd must be uniform in order to yield MESFETs for use in high-integration density GaAs IC’s. It was found in 1983 that dislocations af%kctthe threshold voltage of a GaAs MESFET.[341 However, soon it was reported that there is no correlation between V, and dislocations.[351 This caused great controversy in the GaAs community, which has accelerated the development of a dislocation-free GaAs crystal. As mentioned in
8
CompoundSemiconductors
the previous section, at present, large-diameter, low-dislocation semi-insulating crystals are achieved by doping with In.t1gl-[211 In parallel with progress in low-dislocation density crystal growth technology, a postgrowth annealing technique has been developed which can greatly improve the crystal quality of dislocated undoped Ga.A~l~~ll~~lIt has been shown that GaAs MESFET’s fabricated on annealed material have excellent V+,, uniformity across the wafer, and an annealed ingot seems to be adequate for use as a GaAs LSI substrate.138113gJ 1980 GaAs integration
IC Density
I
I
I
(SRAM) (Gate
I
1985
I
m
3x3 1.5 <30
1990
,,,,,,,,,
m
Array) 2-3K
Chip Size (mm”) Gate Length ( pm) aVth ImV1
I
m
1995 I[
1 OK
20-30K
70-80K
5x5 1.0 c 20
7x7 0.8 cl5
10x10 0.5 < 10
Process Wafer Size
Wafer Technologies
Flatness ( pm)
~~~~~i
LN
: 2.0
1.5
1.0
0.8
0.5
Wafer Cleanliness
Pa;i$m;ize
: o3
0.2
0.15
0.1
Figure 6. Trend in substrate technology for GaAs ICs.
Currently, GaAs digital ICs have an integration density of 20 - 30 k gate array or 16 kb SRAM. The ingot annealing technique can fully meet the requirement for uniformity of threshold voltage (aV,,J necessary for the fabrication of these GaAs LSIs. Presently, an important subject of crystal growth is the reproducibility of V,, not only from wafer-to-wafer but also from lot-to-lot. Reproducibility is indispensable for the mass-production of GaAs ICs. Moreover, parasitic effects in GaAs MESFET such as sidegating and low-frequency oscillation, must be diminished in terms of both crystal quality and IC fabrication.l4o1
Bulk Crystal Growth 3.2
9
Carbon Control
Control of carbon incorporation in a crystal is essential for obtaining highquality, semi-insulating crystal with good reproducibility. Various methods for carbon control have been reported. For example : .
PBN coating of graphite parts in a chamber.l41l
.
Replacement of graphite parts by AlN.t421
.
Reduction in volume of graphite pa.rt~3.1~~1
.
Control of water content in B2O3.r441
.
Control of melt duration time.l45l
.
Crystal growth from an arsenic rich melt.l43l
.
G%O, doping.l46l
Our results are shown in Fig. 7. It can be seen that for higher water content in B2O3 or longer melt duration time, the carbon content in the crystal is lower. The carbon concentration in the crystal relates directly to V, of MESFETs fabricated on the crystal using the direct ion implantation technique.l47l Figure 8 shows the carbon concentration distribution along the growth direction of 3” diameter undoped conventional (6 kg charge) and super-long (10 kg charge) ingots. 12q The horizontal axis shows the wafer number, representing the position along the growth direction. The carbon concentration gradually decreases toward the tail of the conventional ingot, but it remains almost constant in the super-long ingot. It can be seen from Fig. 8 that the V,,, distribution for MESFETs made on these crystals reflect the carbon concentration distribution. 100
_..-..-.._..-..-,._.. Deteotlon
Umlt
Melt duration (hr)
Figure 7. Relationship between growth conditions and carbon concentration in undoped GaAs.
10
Compound Semiconductors
m- 10’”
r ,
I
I
‘E s
E OX_ ‘F; Y e E 8 0 -0 s 10’” -
I
I
I-I
-@-Improved long (IO kg): _s_ o---Conventional (6kg) ‘Q.,
0
.. 4.-o-
o-o-.
‘0
-
E E uo
I
I
0
50
I
I
100
150
Wafer
I
I
200
250
No.
2eSi , 120 KeV, 3x1d2
-O-Improved long ( 10 kg1 ---(-J--- Conventional (6 kg) I
0
50
1
100
I
150
I
200
1
25
Wafer No. Figure 8. Distributions of carbon concentration and V+,, along the growth direction in 3” diameter undoped GaAs. The conventional ingot is grown with a 6 kg charge. The improved (super-long) ingot is grown with a 10 kg charge. Wafer number means the position along the growth direction.
As the requirement for V, uniformity is now becoming even more severe, precise control of carbon concentration is needed. In view of this, the correlation between the CO gas content in the high-pressure inert gas ambient and the carbon content in the crystal has been extensively
Bulk Crystal Growth
11
investigated.1481~t501 Boron is another representative impurity in an tmdoped LEC GaAs crystal. When a boron atom sits on a Ga site, it becomes an isoelectronic impurity and is electrically neutral. However, it has been reported that when the boron concentration increases, some of the boron atoms sit on As sites and form an acceptor.1511-1531 It has also been found that when the boron concentration increases, the short channel effect of the GaAs MESFET is enhanced.l54l 3.3
Annealing
A condition for semi-insulation in undoped LEC GaAs is given by
NELZ ’ [Cl - (Ns, - Ns7.J ’ 0 where [C] is the carbon concentration, NS% is the concentration of shallow acceptors other than carbon, N, is the concentration of shallow donors and NELzis the concentration of deep donor EL2. The quantity of ND(= Ns, - NS$J is quite sensitive to the thermal history of the crystal. It becomes about 5 x 1014cmW3 when high temperature annealing is followed by slow cooling, while it becomes about 1 x 1014crnm3when high temperature annealing is followed by rapid cooling. Figure 9 shows the change in resistivity due to rapid cooling after annealing at 850°C in an ASH, ambient. The cooling rate is 9OO”C/h over the temperature range from 850°C to 400°C. The resistivity increases after annealing. Moreover, if the initial resistivity is lower, the rate of increase of the resistivity is larger. Although the origin of ND has not yet been identified, it is plausible that the origin is a native defect EL6 which forms a donor level at about 0.4 eV below the conduction band.l55l156lThe generation and annihilation of EL6 occurs in the temperature range of 500°C - 600°C.1571When the carbon concentration is reduced to the range of 1 - 5 x 1014cms3, the crystal becomes thermally unstable and a strange phenomenon can be observed. The crystal becomes semi-insulating after rapid cooling, but becomes semiconducting after slow cooling. Both states are thermally reversible.l58l It was reported that the EL2 concentration is greatly reduced when an undoped LEC GaAs crystal is annealed at high temperature (around the melting point) followed by rapid cooling. 15gl When this crystal is subjected to annealing at 700 l,OOO°C,the EL2 concentration can increase again. This finding opened the door to EL2 engineering.
12
Compound Semiconductors
0 : Sinch undope 0
lE8 -
d
: 4inch undope
Wafer annealing condition
ki =
85V’C, 1Omln
G
-
-
Nu, ([CL] ND)
AsHa/Hz/Na atmosphere capless
k=34xlO’ NN I 14 x 10”
850°C lE7
SE7 Pbf0r0
Figure 9. atmosphere
3.4
lE8
4OlPC : 30min
5E8
(n-cm)
Resistivity change a&r wafer annealing followed by rapid cooling.
at 850°C for 10 min in an AsIX,
V,, Control
Since the carbon concentration in the crystal directly influences the V,,, of MESFETs, the measurement of the carbon is necessary in order to predict the V,. Carbon in GaAs is usually measured by a local vibrational mode absorption line using the FIIR method.l6ol As the absorption coefficient is very small, the measurement’s accuracy is not reliable in a wafer and a thick sample should be prepared. Accordingly, an alternative method is necessary. As suggested previously, the resistivity of a crystal can be a function ofthe carbon concentration, as long as the thermal history is the same. This is shown in Fig. 10. All ingots shown in this figure are tmdoped and were subjected to the same ingot annealing. The theoretical line fits well through the experimental data. Figure 11 shows the relation between the resistivity of the semi-insulating substrate and the V, of an ion-implanted layer. The V, becomes shallow when substrate resistivity becomes high, and vice versa. The substrate resistivity can be a good indicator of V,. Next let’s consider the V, uniformity in a wafer as reflected by the standard deviation of V, (crV&. It has been foundl61l that there is a good correlation between oV,,, and the standard deviation of resistiviiy (designated o/p because it is actually the standard deviation of p normalized to the average resistivity). Our results are shown in Fig. 12. The resistivity was measured at 100 l.trnpitch using the three-electrode guard-ring method.[‘j21 It is seen from the figure that the substrate with a better uniformity of microscopic resistivity can give a smaller oV,.
Bulk CrystalGrmvth
13
k.3.lxlO: Ntzuz15x10tl No= 0.5x 10"
“0
2
1
3
4
5
Carbon concentration (x 10’6cmJ)
Figure 10. Relationship between carbon concentration and resistivity in undoped GaAs. All ingots are annealed as a whole boule, and followed by slow cooling. Theoretical line is derived from a three-level model.
- 4.0
- 3.8
- 3.6 2 5
- 3.4
- 3.2
- 3.0 _ 0
1
2
Resistivity,
Figure 11. Relationship in undoped GaAs.
3 p ( x 1O’R
4 l
5
cm)
between substrate resistivity and V+,, of the ion implanted layer
14
Compound Semiconductors
Undoped LEC GaAs 8.01 7.0 -
Vbl : 0.75 eV
3‘;; E
6.0 -
s: z
5.0 -
5 fi
4.0-
b .&
3.0
E 5 g a
2.0
5
1.0
Olmm pitch n I400 pohlt*
lmm pitch n I81 pohlN
i
01 ’ 0
’
I
’
’
’
’
50
Micro p uniformity,
’
’
’
’
’
100
6 /P (%I
Figure 12. Relationship between microscopic uniformity of substrate resistivity (o/p) and V, uniformity (CV&. V, uniformity is normalized to V, - V,.
The Hall mobility (& of semi-insulating crystals should be characterized by a mixed conduction model. However, the Hall mobility becomes almost equal to the drift mobility (~3 after the ingot annealing because the electron concentration increases sufficiently and the crystal becomes n-type semi-insulating. In this case, the difference in the Hall mobility corresponds to the difference in the drift mobility of electrons. The drift mobility is infhrenced by crystal purity and crystal homogeneity. Since the concentration of total ionized impurities is at a level in the low 1015cmm3 range, the contribution to the drift mobility from ionized impurity scattering is thought to be neglected. Accordingly, the difference in drift mobility comes primarily from the difference in crystal homogeneity.163l We have investigated the relation between the Hall mobility and the uniformity of microscopic resistivity, which is thought to reflect crystal homogeneity. The results are shown in Fig. 13. It can be seen that the crystal with high Hall mobility has better uniformity of microscopic resistivity. Considering this result together with the relation shown in Fig. 12, it can be deduced that the crystal with a higher Hall mobility can produce a smaller oV,.
Bulk Crystal Growth
15
l-
_----._ , /=;
-. -.
*.
/
-. \
i
I -a\
Group I *. 8.
\
l. .
.. . i
‘.
--__
Group II
:
--__
)_w------_
#’ ----m-m-
0
l
/)
:
,‘e
l
I
*
l
I.... \\ l
l-
.
a
. . --__-- ..y ,.0, >-
I -
0
\ ;
,,I
_---_
Group Ill l ;.,
\
l l
I.
‘.
I31,000
\\
4,000
5,000
.--______---
6,000
0 0’
7,000
\
II
8,000
Hall mobility, p H (cm* /V&) Figure 13. Relationship between Hall mobility (& and microscopic substrate resistivity (o/p) in undoped semi-insulating GaAs.
3.5
uniformity
of
Large-Diameter Crystal
In the past, substrates for GaAs IC’s have increased in diameter by one inch every four years. At present, a transition to 4” diameter is rapidly taking place, especially in the US market. What diameter will we reach in the future? Figure 14 shows a 5” diameter undoped LEC GaAs crystal which we have grown. The EPD is 5 - 7 x lo4 cms2,which is slightly higher than that of a 4” diameter crystal. The EL2 concentration is around 1.3 x 1016cme3and is quite uniform, not only in a wafer but also along the growth direction. Figure 15 shows the resistivity and mobility distributions in a wafer. The mobility is as high as 7,000 cm2/vs at both the seed and the tail ends. On the other hand, the resistivity is high at the center of each wafer and gradually decreases toward the periphery. This reflects the carbon concentration distribution caused by the convex solid-liquid interface shape. This can be improved by modifying the thermal environment.l64l
16
Compound Semiconductors
Figure
14.
Five inch diameter undoped LEC grown GaAs crystal.
Figure
15.
Radial distributions
of resistivity
and mobility
in 5" diameter undoped GaAs.
Bulk Crystal Growth 4.0
17
InP
InP crystal growtb is generally divided into two processes: synthesis of InP polycrystals, and the single crystal growth. There are various methods to synthesize polycrystals, such as HB, GF,t651SSD (Synthesis from Solute Diffusion)[661and phosphorus injection.[‘jfl The HB method has a high growth rate so it is presently the most suitable method for massproduction. However, the HB method results in Si contamination from the quartz ampoule in the high temperature growth environment. Conversely, the SSD method is very suitable in terms of purity. The conventional LEC method is also employed as a growth technique for InP single crystals.[681[6gl LEC growth in a phosphorus atmosphere[g1t101[701t711 and VGF growM21 have been developed to reduce the dislocation density in InP crystals. Recent advancements in low dislocation InP and semi-insulating InP will be mentioned in this section. 4.1
Low-Dislocation InP
Figure 16 shows a schematic diagram of the VCZ (Vapor Pressure Controlled Czochralski) method, which we have developed to suppress phosphorus dissociation at elevated temperatures. Using this method, the temperature gradient in the B,O, layer can be reduced to 30 - SOT/cm, which is much lower than the 100 - 13OWcm of conventional LEC method. Figure 17 shows x-ray topographs of 2” diameter S-doped InP crystals grown by the conventional LEC and VCZ methods. In the case of conventional LEC, the dislocation density is high at the center and the periphery of the wafer. However, since the thermal stress is small in the case of VCZ, the wafer is almost dislocation-free except for a few slip lines extending from the wafer periphery. In order to suppress the S outdiffksion from the substrate into the epitaxial layer, lower S concentrations in the substrate are preferable. In view of this, lower dislocation densities at low carrier concentrations are definitely needed. The VCZ technique is a powerful tool for this purpose. Figure 18 shows the dependence of EPD on the carrier concentration in 2” diameter S-doped InP. The impurity hardening effect is observed above a carrier concentration of 4 x lo’* cmm3in the case of conventional LEC. On the other hand it is observed above a carrier concentration of 1 x lOi* cmm3in the case of VCZ. The EPDs of Sndoped and Fe-doped InP crystals grown by conventional LEC have a level of 1 - 5 x 1O4cmm2,but this level can be reduced by one order of magnitude using the
18
Compound Semiconductors
VCZ method. Dislocations in the substrate tiect the surface morphology after epitaxial growth. In view of this, low dislocation density InP crystals are useful. Two inch diameter InP wafers are widely used in current fabrication processes for InP-related devices. However, as can be seen in the case of GaAs, the need for higher yield and better device performance will require larger-size and higherquality wafers. Figure 19 shows the dependence of EPD on the carrier concentration in 3” diameter Ir1P.1~~1It can be clearly seen that both Zndoped and S-doped 3” diameter InP crystals grown by the VCZ method have low EPD at low carrier concentrations. Figure 20 shows EPD maps of Zndoped 3” diameter InP wafers. The low EPD area of VCZgrown crystals is about double that of conventional LEC-grown crystals.
p
(s)
It
P2 + P4 piziiaq
\
P4
/ B203
Figure 16. Schematic diagram of VCZ crystal growth method.
J
N () >
O w -.J ro c: 0 +-' c: a> > t: O ()
I
E
Bulk Crystal Growth
I
~M T-
CX)CJ 0 ~ x
19
.,;
~
i N
] ~ ~ . ~ ~
0 .+= ~
]
.
II
(\I
() 8 ;>0, .0
~
()
C')
~ ~ rn S ~ t)
'E (,) 00 ..-0 ~
~ r-=
>'::
I
1 "9 00 ~ "'6 ~ :a N O rn
x ("1') II . () . ()
~ ~
20
Compound Semiconductors
iI lo3
I
.
0”
\
5
I
i 2
Cl
0;
lo’*
rru,r,mmIw
EPDs
5
2
Carrier Figure 18.
I
\
!
,02c111
of 2” diameter
I
lOi
I-l 5
2
concentration S-doped
I
(cm-3)
InP crystals
as a function
of carrier
concentration.
0 Cl Conventional
LEC (S)
Carrier concentration
Figure 19. EPDs of 3” diameter S-doped, Fe-doped function of carrier concentration.
(cm-3)
and Zndoped
InP crystals as a
Bulk Crystal Growth
Conventional
vcz
LEC
13" "' Zn doped
21
InPl
EPD (cm-2 ) D <500
c.c
C.C=4.7x10'8cm-3
EPD
Low
area = 16.5cm2
20.
concentration
4.2
III
2000-5000
III
>5000
= 4.7 x 10'8 cm-3
EPD
area = 34cm2
«500cm-2)
«500cm-2)
Figure
500-2000
Ave. EPD = 0.5 x 102cm-2
Ave. EPD = 45.4 X 102cm-2 Low
D
EPD distribution
in a wafer in 3" diameter Zn-doped InP crystal.
The carrier
is p = 4.7 x 1018 cm-3 for both wafers.
Semi-Insulating InP
Semi-insulation in Fe-doped InP is achieved by compensating shallow donors with the Fe deep acceptors. Si is incorporated into InP crystals as a donor impurity because InP polycrystals, used as source material for single crystal growth, are synthesized in a quartz ampoule. It is desirable to reduce the Fe content in InP crystals since Fe impurities out-diffi1se from the substrate into the epitaxial layer. This affects the epi-Iayer's characteristics. In order to obtain semi-insulating InP with low Fe content, the concentration of background shallow donors must be decreased. Figure 21 shows the relationship between the resistivity and the Fe content in a crystal. In the case of standard purity polycrystal (n = 4- 8 x 1015cm-3), Fe must be doped to more than 0.25 wt.ppm (= 1.25 x 1016 cm-3) to obtain a semiinsulating crystal. However, in the case of a high purity polycrystal (n = 1 -4 x 1015cm-3), the Fe content necessary for a semi-insulating be reduced to 0.10 wt-ppm (= 5 x 1015cm-3).
crystal can
22
Compound Semiconductors
0 n (Source material) = 5 - 8 x lO’“cm-” El n (Source material) = 2 - 4 x lO’%m-”
10’”
10.’
Fe concentration (cme3) Figure 21. Relationship between Fe content and resistivity in Fe-doped InP. The carrier concentration of standard-purity polycrystal is 4 - 8 x 10” cmJ and that of high-purity polycrystal is 1 - 4 x lOI cm3.
It has recently been reported that a high purity undoped semiconducting InP crystal can be converted into a semi-insulating crystal by annealing it in a high-pressure phosphorus atmosphere.[731-t761 Homrann et a1.173ldid the annealing at 900°C for 80 hrs under 5 atm of phosphorus pressure. Kainosho et a1.l74ldid the annealing at 900°C for 20-40 hrs under 15 atm of phosphorus pressure. Although the mechanism for resistivity increase is not well known, there is a possibility that Fe contamination may occur during annealing, since undoped semi-insulating InP shows nearly the same activation energy as Fe doped semi-insulating InP.1751[761 However, this is not enough to fully explain the semi-insulation mechanism and it is suggested that some hind of native defect may be involved.
5.0
SUMMARY
We have reviewed several important issues in III-V compound crystal growth. As the crystal size increases, it is even more difficult to reduce the dislocation density. In order to overcome it, a low temperature gradient growth under an ambient of group V element must be necessary. In addition, a control of solid-liquid interface shape will become essential.
Bulk Crystal Growth
23
A present level of crystal quality fully meets a requirement of oV,,, for GaAs ICs with an integration density of 20 - 30 k gates. The most important subject to be grappled by a material supplier is to increase the reproducibility of carbon content (or resistivity) from wafer-to-wafer or lotto-lot. In order to further increase the integration density of GaAs ICs, one will have to clarify the influence of a dislocation on the device performance. Stoichiometry affects the crystal quality very much in compound semiconductors. Much attention should be paid to this point.
REFERENCES 1. Fischer, A. G., Crystal Growth, (EL R. Pamphn, ed.), pp. 357-393, Pergamon Press, New York (1980) 2. Gault, W. A., Monberg, E. M., and Clemans, J. E., J. Cryst. Growth, 74: 149 (1986) 3. Kremer, R. E., Frarcomano, D., Freidenreich, B., Marshall, H., and Burke, K. M., Semi-Insulating III-VMaterials, (A. G. Mihres and C. J. Miner, eds.), p. 205, Adam Hilger, Toronto (1990) 4. Hoshikawa, K., Nakanishi, H., Kohda, H., and Sasaura, M., J. Cryst. Growth, 94:643 (1989) 5. Matsumoto, K., Morishita, H., Sasaki, M., Nishine, S., Yokogawa, M., Sekinobu, M., Tada, K., and Akai, S., Semi-Insulating III-V Materials, (D. C. Look and J. S. Blakemore, eds.), p. 211, Shiva Publishing (1984) 6. Shim&u, A., Nishine, S., Morioka, M., Fujita, K., and Akai, S., Semi-Insulating IILVA4aterials, (H. Kukimoto and S. Miyazawa, cd.), p. 41, I-k&one (1986) 7. Tornizawa, K., Sassa, K., Shimanuki, Y., and Nishizawa, J., J. Electrochem. Sot., 131:2394 (1984) 8. Ozawa, S., Miyairi, H., Nakajima, M., and Fukuda, T., Int’l Symp. GaAs and Related Compounds, Inst. Phys. Conf Ser., 79:25, Karuizawa (1985) 9. Tada, K., Tatsumi, M., Nakagawa, M., Kawase, T., and Akai, S., Int’l Symp. GaAs and Related Compounds, Inst. Phys. Conz Ser., 91:439 (1987)
24
Compound Semiconductors
10. Kohiro, K., Mori, M., Yamamoto, H., and Oda, O., Ext Abst. 36th Spring Mtg. Jpn. Sot. Appl. Phys. and Related Societies, Chiba (April 1989) 11. Kohda, H., Yamada, K., Nakanishi, H., Kobayashi, T., Osaka, J., and Hoshikawa, K., J Cyst. Growth, 71:813 (1985) 12. Parsey, J. M., Jr., Nan&i, Y., Lagowski, J., and Gatos, H. C., J Elctrochem. Sot., 128:938 (1981) 13. Parsey, J. M., Nan&i, Y., Lagowski, J., and Gatos, H. C., J. Electrochem. Sot., 129:388 (1984) 14. Lagowski, J., Gatos, H. C., Aoyama, and Lin, D. G., Appl. Phys. Lett., 45:680 (1984) 15. Seki,Y., Watanabe, H., andMatsui, J.,J Appl. Phys., 49:822 (1978) 16. Mil’vidsky, M. G., Osvensky, V. B., and Shifiin, S. S., J: Cryst. Growth, 52:396(1981) 17. Jacob, G., Semi-Insulating III-VMaterials, (S. Markam-Ebeid and B. Tuck, eds.), p. 2, Shiva Publishing (1982) 18. Tada, K., Kawasaki, A., Kotani, T., Nakai, R., Takebe, T., Akai, S., and Yamaguchi, T., Semi-Insulating III-VMaterials, (S. MarkamEbeid, and B. Tuck, eds.), p. 36, Shiva Publishing (1982) 19. Tada, K., Murai, S., Akai, S., and Suzuki, T., GaAs IC Symposium, Tech. Digest, p. 49, Boston (1984) 20. Duseaux, M., and Martin, S., Semi-InsulatingIII-VMaterials, (D. C. Look and J. S. Blakemore, eds.), p. 118, Shiva Publishing (1984) 21. Hobgood, H. M., Thomas, R. N., Barrett, D. L., Eldridge, G. W., Sopira, M. M., and Driver, M. C., Semi-Insulating IiFVMaterials, (D. C. Look and J. S. Blakemore, eds.), p. 149, Shiva Publishing (1984) 22. Ibuka, T., Seta, Y., Tanamura, M., Orito, F., Okano, T., Hyuga, F., and Osaka, J., Semi-Insulating III-VMaterials, (H. Kukimoto and S. Miyazawa, eds.), p. 77, Hakone (1986) 23. Matsuura, T., Nakai, R., and Yokogawa, M., Semi-Insulating III-V Materials, (G. Grossmann and L. Ledebo, eds.), p. 453, Adam Hilger (1988)
Bulk Crystal Growth
25
24. Matsumoto, K., Yamashita, M., Nakai, R., Yazu, S., Tada, K., and Akai, S., Semi-Insulating III-V Materials, (G. Grossmann and L. Ledebo, eds.), p. 447, Adam Hilger (1988) 25. Inoue, T., Nishine, S., Shibata, M., Matsutomo, T., Yoshitake, S., Sato, Y., Shimoda, T., and Fujita, K., Int’l. Symp. GaAs and Related Compounds, Inst. Phys. ConJ: Ser., 79:25, Karuizawa (1985) 26. Mizuniwa, S., Kashiwa, M., Kurihara, T., Nakamura, K., Okubo, S., and Ikegami, K., J Cryst. Growth, 91:676 (1990) 27. Nambu, K., Nakai, R., Yokogawa, M., Matsumoto, K., Koe, K., and Tada, K., Int’l. Symp. GaAs and Related Compounds, Inst. Phys. Conf Ser., 91:141, Heraklion (1987) 28. Fujii, K., H.&a, M., Fujita, H., and Takeda, S., De$cts Control in Semiconductors, (K. Sumino, ed), p. 667, Elsevier Science Publishers (1990) 29. Abrahams, M. S., andBuiocchi, C. J.,J. Appl. Phys., 36:2855 (1965) 30. AuCoin, T. R., Ross, R. L., Wade M. J., Savage, R. O., Solid State Technol., 221569 (1979) 3 1. Martin, G. M., Farges, J. P., Jacob, G., Hallais, J. P., and Poiblaud, G., J. Appl. Phys. 51:2840 (1980) 32. Holmes, D. E., Chen, R. T., Elliott, K. R., and Kirkpatrick, C. G., Appl. Phys. Lett., 40:46 (1982) 33. Welch, B. M., and Eden, R. C., IEDMTech. Digest, p. 205 (1977) 34. Miyazawa, S., Ishii, Y., Ishida, S., andNanishi, Y., Appl. Phys. Lett., 43:853 (1983) 35. Winston, H. V., Hunter, A. T., Olsen, H. M., Bryan, R. P., and Lee, R. E., Appt. Phys. Lett., 45:447 (1984) 36. Rumsby, D., Ware, R. M., Smith, B., Tyjberg, M., Brozel, M. R., and Foulkes, E. J., GaAs IC Symp., Tech. Digest, p. 34, Phoenix (1983) 37. Miyazawa, S., Honda, T., Ishii, Y., and Ishida, S., Appl. Phys. Lett., 44:410 (1984) 38. Kasahara, J., Arai, M., and Watanabe, N., Jpn. J Appl. Phys., 25:L85 (1986)
26
Compound Semiconductors
39. Decor&k, P., Farges, J. P., Martin, G. M., Nagel, G., and Lhnert, H., Semi-Insulating III-VMaterials, (G. Grossmann and L. Ledebo, eds.), p. 505, Adam Hilger (1988) 40. Koyama, R., Odekirk, B., Vetaner, W. A., Finchem, E. P., and Beers, I. G., Semi-Insulating III-VMaterials, (G. Grossmann and L. Lcdebo, eds.), p. 203, Adam Hilger (1988) 41. Inada, T., Fujii, T., Kikuta, T., and Fukuda, T., Appl. Phys. Lett., 50:143 (1987) 42. Washizuka, S., Nishio, J., Terashima, K., and Watanabe, M., SemiInsulating III-VMaterials, (H. Kukimoto and S. Miyazawa, eds.), p. 65, Hz&one (1986) 43. Kikuta, T., Emori, H., Fukuda, T., and Ishida, K., J: Cyst. Growth, 76:517 (1986) 44. Hunter, A. T., Kimura, H., Baukus, J. P., Winston, H. V., and Marsh, 0. J., Appl. Phys. Lett., 44:74 (1984) 45. Mass, Y., Tanaka, A., Kadota, Y., and Yokoyama, T., Ext. Abstr. 31st SpringMtg. Jpn. Sot. Appl. Phys. and Related Societies, Tokyo (April 1984) 46. Kadota, Y., Kakimoto, S., Abe, T., Kazuno, T., and Yokoyama, T., Ext. Abstr. 46th Autumn Mtg Jpn. Sot. of Appl. Phys. and Related Societies, Kyoto (October 1985) 47. Chen, R. T., Holmes, D. E., and Asbeck, P. M., Appl. Phys. Lett., 45:459 (1984) 48. Nishio, J., and Nakata, Y., J. Cryst. Growth, 99:680 (1990) 49. Doering, P. J., Freidenreich, B., Tobin, R. J., Pearah, P. J., Tower, J. P., and Ware, R. M., Semi-Insulating III-VMaterials, (A. G. Mimes and C. J. Miner, eds.), p. 173, Adam Hilger, Toronto (1990) 50. Sato, N., Kakimoto, M., and Kadota, Y., Semi-Insulating III-V Materials, (A. G. Mihres and C. J. Miner, eds.), p. 212, AdamHilger, Toronto (1990) 5 1. Elliott, K. R., X Appl. Phys., 55:3856 (1984) 52. Kikuta, T. and Ishida, K., GaAs and Related Compounds, Inst. Phys. ConJ: Ser., 83:45, Las Vegas (1986) 53. Osaka, J., Hyuga, F., Kobayashi, T., Yamada, Y., and Orito, F., Appl. Phys. Left., 50:191 (1987)
Bulk Crystal Growth
27
54. Asai, S., IEICE Technical Report, ED91-129 (1990) 55. Kitagawara, Y ., Noto, N., Takahashi, T., and Takenaka, T., SemiInsulating III-VMaterials, (H. Kukimoto and S. Miyazawa, eds.), p. 273, Hakone (1986) 56. Raichhnaier, S ., Lhnert, K., and Baumgartner, M., Jpn. J Appl. Phys., 27:2329 (1988) 57. Ogawa, O., Semi-Insulating III-VMaterials, p. 237, (II. Kukimoto and S. Miyazawa, eds.), Hakone (1986) 58. Ford, W., Mathur, G., Look, D., and Yu, P., Semi-Insulating III-V Materials, (H. Kukimoto and S. Miyazawa, eds.), p. 227, Hakone (1986) 59. Lagowski, J., Gatos, H. C., Kang, C. H., Skowronski, M., Ko, K. Y., and Lin, D. G., Appl. Phys. Lett., 49:892 (1986) 60. Brozcl, M. R., and Foulkes, E. J., Appl. Phys. Lett., 49:337 (1986) 61. Asai, S., and Ohata, K., IEICE Technical Report, ED89-109 (1989) 62. Obokata, T., Matsumura, T., Terashima, K., Orito, F., Kikuta, T., and Fukuda, T., Jpn. J Appl. Phys., 23:L602 (1984) 63. Waltiewicz, W., Le Wang, Pawlowicz, L. M., Lagowski, J., and Gatos, H. C., J Appl. Phys., 59:3 144 (1986) 64. Miyajima, H., Kami&a, K., Nishiura, T., Oida, K., Nakai, R., Yokogawa, M., and Nishida, Y., Semi-Insulating III-V Materials, (A. G. Mimes and C. A. Miner, eds.), p. 219, Adam Hilger, Toronto (1990) 65. Adamski, J. A., J Cryst. Growth, 64:l (1983) 66. Kubota, E., J. Cryst. Growth, 68:639 (1984) 67. Farges, J. P., J: Cryst. Growth, 59:665 (1982) 68. Bonner, W. A., J: Cryst. Growth., 54:21 (1981) 69. Shinoyama, S., Uemura, C., Yamamoto, A., and Tohno, S., J. Electron, lo:941 (1981) 70. Tatsumi, M., Kawase, T., Arai, T., Yamabayashi, N., Iwasaki, T., Miura, S., Tada, K., and Akai, S., Int’l. Conj InP and Related MateriaZs, p. 18, Oklahoma (1989) 7 1. Kohiro, K., Kainosho, K., and Oda, O., Int% ConJ InP and Related Materials, p. 8, Cardiff (1991)
28
Compound Semiconductors 72. Hosokawa, Y., Kawarabayashi, S., Yabuhara, Y., Morioka, M., Yokogawa, M., and Akai, S., Int’l. Conf InP and RelatedMaterials, Rhode Island ( 1992) 73. Hof&mn, D., Miiller, G., and Strecffifi, N., Appl. Phys., A48:315 (1989) 74. Kainosho, K., Yamamoto, M., and Oda, O., Ext. Abstr. 52ndAutwnn Mtg. Jpn Sot. Appl. Phys. and Related Societies, Okayama, (October, 1991) 75. Oda, O., Kainosho, K., Kohiro, K., Hirano, R., Shimakura, H., Inoue, T., Yamarnoto, H., and Fukui, T., Int’l Conf: InP and Related Materials, p. 2, Cardiff (1991) 76. Hirt, G., Hof%mn, D., Mosel, F., Sctifer, N., and Miiller, G., Int’l. Conf InP and Related Materials, p. 16, Cardiff ( 199 1)
MOCVD of Compound Semiconductor Layers Eberhard Veuhoff
1.0
INTRODUCTION
Epitaxial growth of compound semiconductor layers is mandatory for the fabrication of electronic and photonic devices. The possibility of growing high quality multilayer heterostructures with excellent control of uniformity in layer thickness and composition, has led to tremendous progress in device developments in the last years. In this progress a continuous interplay between device improvements and advances in materials has taken place. The evolution of metalorganic chemical vapor deposition, MOCVD, as a growth technology for multilayer heterostructures has provided access to improved and new device concepts and facilitated the large scale fabrication of multilayer device structures. In general MOCVD (also referred to as MOVPE, metalorganic vapor phase epitaxy, in order to stress the epitaxial character in the growth process, or OMVPE) is the growth of compound semiconductor layers by metalorganic and hydride precursors in the gas phase. First experiments were reported by Didchenko, Alix and Toeniskoetter in 1960, when they investigated the formation of InP by trimetbylindium and phosphine at about 270 to 300°C.t11 Independent of these first growth studies with metalorganic compounds and hydrides, Harrison and Tompkins prepared GaAs and InSb in 1962[*1and Manasevit grew single crystal GaAs fihns on insulating substrates in 29
30
Compound Semiconductors
1968.t31 Excellent documentation of the vast development of this growth technology since then can be found in review articles [41+81 and books.tglt’Ol Though the success of the MOCW technology in device fabrication is evident, it has to be admitted that a fundamental tmderstanding of the MOCW growth process is still lacking. This was the main reason for carrying out the MOCW process under molecular beam epitaxy (MBE) conditions in order to be able to apply surface analytical tools and to distinguish between homogeneous and heterogeneous reactions. This step led to the introduction of a new growth technology in 198 l,[lll which was labelled MOMBE (metalorganic molecular beam epitaxy) shortly thereafter,ti21and later also CBE (chemical beam epitaxy).[131In the past ten years, this new MOCW related technology has successfully been established as which can be regarded as supplean independent growth technology, lr41tr51 mentary to MOC W. The objective of the present review is to give an overview on the current MOCW activities with emphasis on recent advances in this growth technology. First, some general issues on the basic MOCW growth process are presented, as reactor design and flow dynamics play an important role for large scale fabrication. Especially in manufacturing environments, the use of the MOCW technology might result in a confrontation with safety issues due to the toxic nature of several precursors; therefore, safety aspects have to be considered. In the following paragraph, the flexibility and versatility of the MOCW technology are highlighted by specific examples from different material systems. The strongest MOCW efforts have taken place in III-V material systems, mainly GaAs and InP based materials, for example, AlGaAs and GaInAsP, respectively.t5-101For these compound layers growth and dopant incorporation are outlined. The applications of these materials in electronic devices such as high speed transistors, and photonic devices such as lasers, photodiodes and optical waveguides has led to the commercialization of the MOC W technology for III-V compound layers. For monolithic integration of different devices on the same wafer, selective area epitaxy is gaining increasing importance; therefore, recent developments in this technique are discussed. The MOC W growth of narrow and wide bandgap compound layers appears to be more complex. Device applications of these materials are in in&red and, respectively, green-blue light-emitting diodes and lasers, where some breakthroughs have recently been obtained. For these materials the current status in MOCW of II-VI compounds and alternative compounds is described. Here, the increasing interest in Sbcontaining compounds is also taken into
MOCKS of Compound Semiconductor Layers
31
account. In the conclusion, the potential of this growth technology for future applications in new devices and its relationship to other growth technologies are evaluated.
2.0
GROWTH PROCESS
Theoretical models describing the MOCVD growth process are helpful for finding an appropriate design of the reactor cells and also for optimizing the epitaxial parameters. Generally, for gas phase deposition of epitaxial layers, a thermodynamic driving force has to be present in order to achieve supersaturation of the gas phase. The growth precursors are introduced into the reaction zone, and their concentration and reaction rate must be high enough in order to ensure sufficient decomposition so that this local supersaturation is produced. This shows that the stability of the precursors for example is an important parameter determining the thermodynamic driving force. In a very simple model, the MOCVD growth process can be described in four steps:181(i) mass transport of the reactants to the growth surface, (ii) reaction at or near the surface, (iii) incorporation of the new material, and (iv) removal of the reaction by-products. Of course, the slowest step in this sequence will be the growth rate limiting step. For example, for MOCVD of GaAs and InP based compounds, it has been found that under typical experimental conditions, the growth rate is determined by the mass transport of group III reactants to the growth surface.151-Ii01 While the growth rate is determined by the group III precursor flow [step (i)], the properties of the grown layers are a&cted by the gas phase and surface chemical reactions [steps (ii)-(i Jensen and coworkers established a physiochemical model that describes two- and threedimensional transport phenomena as well as gas phase and surf= reactions underlying the growth of compound semiconductors.1161 The model simulated growth rates and impurity incorporation as a function of epitaxial parameters; for example, the computations showed that the temperature of the reactor walls plays an important role in controlling uniformity. Good agreement between model predictions and experimental data was found. Two alternative routes should be mentioned plasma enhanced MOCVD (PE-MOCVD) and atomic layer epitaxy (ALE). The former technique is very promising for a growth process where relatively stable precursors are used. For example, it has been shown that for growth of the h&based compounds in PE-MOCVD, the plasma precracking of the
32
Compound Semiconductors
hydrides amine and phosphine facilitates the controlled incorporation of the different group V elements, since the phosphorus incorporation efficiency is increased and the pronounced temperature dependence of the solid alloy composition is reduced.l17l In ALE growth of compound layers, the same precursors as in conventional MOCVD can be applied; growth is achieved by the separate and alternate exposure of the substrate to the reactants containing the group III and group V elements of the compound. This leads to an ideal two-dimensional growth process offering excellent control of the growth process at the monolayer level by a self-limiting growth mechanism.ll*l In both techniques, the overall consumption of the hydrides arsine and phosphine is reduced, which is attractive for safety considerations (reduced storage, reduced toxic waste). In the present section, some practical issues for MOCVD growth are outlined. As these are discussed in full detail in recent reviews,151-liOl only a short description is given here with emphasis on latest developments. First, some recent advances in reactor design are presented. In the following subsection, the latest investigations on MOCVD precursors are discussed, and the section concludes with a brief presentation on safety aspects. 2.1
Reactor Design
In MOCVD growth of semiconductor compound layers, the different precursors are introduced via a fast switching gas manifold into a cold wall reactor. In many cases, the reaction cell is made out of quartz and the graphite susceptor is RF heated. The growth process is performed in a hydrogen carrier gas at atmospheric pressure or at reduced pressures requiring a pressure control system. Doping profiles with steep slopes and abrupt interfaces in heterostructures should be obtained. Furthermore, uniformity in layer thickness, doping concentration and composition across larger substrate areas or even among several substrates simultaneously, is the basis for large scale fabrication. To fulfill these requirements, careful design of the gas manifold and reactor cell with inlet region and mixing region is necessary to reduce any dead volumes and to fkihtak Ihst gas exchange in the reactor. Several approaches have been taken in the last years. Three different reactor types can be distinguished:l*l vertical, horizontal, and barrel reactors. In the vertical reactor, the incoming gas flow direction is perpendicular to the substrate surface, whereas in the latter two types, the gas flow is tangential to the growing surface. Vertical and horizontal reactors are mostly used in research or small fabrication facilities;
MOCKS of CompoundSemiconductorLayers
33
the barrel reactor is designed for high throughputs in large scale production.[lgj In 1988, a new type of MOCVD reactor was introduced for epitaxial growth of layers simultaneously on seven 2-inch wafers in planetary motion using a circular growth chamber with horizontal geometry and a radial gas flo~.[~~jIn levitating the wafer carrier on a gas foil, the rotation of the wafers was possible by using the momentum of the gas (gas foil rotation). This configuration led to very uniform GaAs layers with a variation of typically f 1% both in thickness and doping over a 2-inch wafer and ll % in thickness and doping between the wafers. The superior interface quality was demonstrated by a selectively doped GaArJAlGaAs heterostructure with low temperature mobilities (1.5 K) of 720,000 cm21 Vs.t201This design was successfully extended to the (Ga,In)(P,As) material system, where variations in thickness and composition of less than 1.5 % over 80 % of a 2-inch wafer were reported.t211 In a recent study, uniformity in layer thiclutess and composition of better than *1.5% were obtained for AlGaAs across 4-inch wafer areas. In conjunction with a thickness variation of less than *1.5% and an emission wavelength variation of less than f 1 nm obtained on seven 2-inch wafers in multiwafer growth of GaInP, the potential of this reactor type for growth of AlGaInP alloys can be recognized.t22j Recently, GaInAsP layers with excellent layer thickness and composition uniformity have been grown in a wide area stagnation point flow MOCVD reactor, where the stagnation point flow was obtained by a flow controlled multiple gas injector technique.[231 Layer thickness uniformities within f 1%, k2%, and lt3 % were reported for 2-inch, 3 -inch, and, respectively, for three 2-inch wafers grown simultaneously. The standard deviation in the photoluminescence wavelength was between 1.5 and 4 mu and the lattice mismatch variation was within f 100 ppm for both single and multiple wafer growth over the entire composition range. 2.2
Growth Precursors In MOCVD growth, alkyls of the group II and III metals, and
hydrides of the group V and VI elements are usually used as precursors. Generally, the search for improved and new precursors is driven by the requirement for improved layer properties, by the aim to achieve low temperature growth and to reduce premature reactions, and by the demand for improved safety conditions. Furthermore, new techniques-for example, selective area epitaxy-may require specific properties such as
34
Compound Semiconductors
comparable stability of the different precursors, which will stimulate further developments in alkyl precursors. A potential precursor candidate should fulfill several fundamental requirements: (il it should be sufficiently volatile so that acceptable growth rates can be obtained; (ii) appropriate stability of the compound should allow for efficient decomposition at the desired growth temperature without appreciable premature reactions which may result in undesirable depletion; (iii) the compound should neither contain any residual impurities (requirement of extreme purity) nor molecules leading to intrinsic contamination (e.g., carbon problem); (iv) parasitic gas phase reactions should be excluded. Based on these requirements, “design” of a suitable precursor should be accomplished. Generally, it can be stated that significant progress in the purity of the precursors has taken place in the last years. Background doping levels in GaAs and in InP layers well below 1015cmm3 with 77 K mobilities above 100,000 cm*/Vs are state-of-the-art for both materials today. A variation of these values from batch to batch, however, can still be observed. Furthermore, the development of compound layers which are less standard, such as AlGaInAs, makes precursor purity a very stringent requirement for the next years. In the following, a brief description of the application of some precursors is given; a detailed discussion on material properties (vapor pressure, stability, etc.) can be found in recent rev&7s_Pl-V01
For most group Il and III precursors in MOCVD of III-V and, respectively, II-VI compound layers, methyl or ethyl groups containing reactants are commonly chosen. The nature of these alkyles is the most important factor dete rmining the carbon incorporation in GaAs based material.l*l The importance of selecting the appropriate precursor for reduced intrinsic contaminations and reduced premature reactions has been discussed in detail before,181-1101 and is, therefore, omitted here. One recent development, however, should be mentioned: in MOCVD of AlGaAs, carbon contamination is a general problem due to incomplete elimination of methyl groups from [Al-CH,] species. In MOMBE, this problem of carbon contamination is even more severe,l15ltherefore, alternative Al precursors were studied. It was found that with trimethylamine alane, AlH3:N(CH3),, as a replacement for the conventional metalorganic Al sources, AlGaAs layers with excellent structural and optical properties could be grown by MOMBE, since this alternative aluminum compound has no direct Al-C bond. In addition, the reduced ability of this compound to form volatile alkoxides leads to lower oxygen incorporation in the AlGaAs Group II and III Precursors.
MOCKS of Compound
Semiconductor
Layers
35
layers than with the standard aluminum precursor.1241After the successfU application of this alternative Al precursor in MOMBE, it was also tested in MOCVD. A recent study on MOCVD of AlGaAs has shown that with this alternative Al source, the carbon contamination can significantly be reduced compared to growth with the standard aluminum precursor Al(CHs),.t251 The application of this alternative precursor was recently extended to MOCVD growth of Inp based compounds; the suitability of this precursor was already proven in AlInAs/GaInAs photonic and electronic devices.[261 This example clearly demonstrates how results obtained in the related growth technology MOMBE can be transferred to MOCVD, leading to similar improvements in the layer quality. In MOMBE, reaction mechanisms can be studied using surface analytical tools, and the MOCVD technology can take advantage of the MOMBE results. Another problem is the control of the concentration of the precursor in the gas phase. For growth of InP-based ternary and quaternary compounds, for example, a small variation in the concentration of the iridium precursor will lead to severe problems concerning lattice mismatch and compositional uniformity. With In(CH,), as the indium precursor, these problems are observed due to the solid nature of the precursor at the commonly used bath temperature, resulting in incomplete saturation of the carrier gas passing through a crystalline solid matrix. Several approaches have been studied to overcome this problem: the use of quite high temperatures of the precursor bath (> 88‘C), alternative liquid precursors, thermal cycling of the solid source before use, trimethylindium in a saturated solution, or bubblers with With the liquid indium precursor DAD1 special configurations. (dimethylaminopropyldimethyhndium), higb quality single layers and quantum well structures could be grown,.[27l however, the rather low vapor pressure might limit wide application of this precursor. The following two approaches appeared to be the most practical and promising: (i) with trimethylindium dissolved in an involatile solvent, InB and GaInAs layers with excellent electrical and crystalline properties were reproducibly grown;t2*l(ii) in another very recent study, it was shown that it was possible to achieve constant and reproducible indium concentrations in the reactor by the use of a configuration of double reverse precursor bubblers.[2gl These results are especially important for the commercialization of MOCVD technology. A newly developed indium precursor, triisopropylindium, was recently introduced. Compared to the standard precursor trimethylindium, it has a lower stability facilitating low temperature growth which was successfully demonstrated for growth of InAs below 500°C.[301
36
Compound Semiconductors
Group V and VI Precursors. In the past, mostly hydrides were used as group V and VI precursors because of their convenient handling.t*l In the last years, however, safety considerations (see next section) have resulted in the search for a replacement for the very toxic and, if exposed to air or other oxidizing substances, explosive group V hydrides, especially amine and phosphine. In analogy to group II and III precursors, group V methyl compounds were studied. Due to the high stability of trimethylphosphine and trimethylarsine compared to the hydrides phosphine and amine, however, successful application to MOCVD growth was not possible; fkthermore, with the methyl based arsenic compound, a significant carbon contamination in GaAs layers was observed.l31l The use of ethyl based group V precursors was not successfil either because of problems concerning stability and vapor pressure. ~1 Tertiarybutylarsine and tertiarybutylphosphine are now the leading candidates for a replacement of arsine and phosphine. These compounds exhibit convenient vapor pressures and comparable low pyrolysis temperatures; they are available in high purity quality, and yield fairly stable radicals during pyrolysis, so that carbon contamination does not appear to be a larger problem.110113111321 For low temperature growth of II-VI and of Sb based compounds, alternative precursors are o&en applied, as discussed in the following paragraphs. For doping of III-V compounds, hydride sources such as H2S and H,Se are very convenient to use.l*l
2.3
Safety Aspects
The safety considerations in MOCVD laboratories are focused on the highly toxic and flammable properties of the chemicals used in the process. As discussed in detail in the literature,110113111321 amine and phosphine are extremely dangerous because of their extreme toxicity combined with their high vapor pressures and reactivity with air; liquid alkyle sources are approximately one hundred times less hazardous due to their lower vapor pressures, resulting in a lower dispersal into the atmosphere leading to lower concentrations, but also due to the lower toxicity of the alkyle molecules.l1ol Not only the use, transportation, and storage of these gases in sufficient quantities, but also increasing public concern and the possibility of more stringent environmental regulations, raise questions concerning safety issues and even the availability of these gases in the future. The search for a replacement has briefly been outlined in the preceding section. For example, the replacement of phosphine by tertiarybutylphosphine results in a reduction of toxicity by several orders of magnitude.l1ol
MOCKS of Compound Semiconductor Layers
37
Besides the search for alternative precursors, the in-situ generation of the hydrides has been proposed as another solution of this problem of toxicity. Growth of InP layers using solid red-phosphorus and a hydrogen plasma for generation of phosphine was reported, the layers had a high quality surface morphology, though the electrical properties had still to be optimized.l33l Another approach is the electrochemical generation of arsine; the process essentially consists of the cathodic reduction of elemental arsenic in an aqueous potassium hydroxide solution.l34l GaInAs/InP structures were grown and enhanced Schottky GaInAs MBSFETs were fabricated; no significant differences in material properties or device characteristics between in-situ generated amine and tank amine were observed.l35l Growth of GaAs and AlGaAs layers with good electrical properties was recently discus~ed;l~~lthe application of this generator to long term reproducible growth of GaInAsP layers, however, has still to be demonstrated. Besides safe handling and storage of the hazardous chemicals, the safe disposal has to be considered. Wet scrubbing and dry scrubbing systems are currently used. In the former, the toxic hydrides and dangerous metalorganics are oxidized, and the reaction products subsequently neutralized.13’l In dry scrubbing systems, active charcoal or other appropriate materials, pyrolyzers, thermal oxidizers, etc. are applied.t3*l With both types of scrubbing systems, the concentration of arsine and phosphine during epitaxial growth at the outlet is below the detection limit of several ppb. The MOCVD technology has been established in research laboratories for many years already, as stated in the introduction. In addition, in the last years, this technology has been introduced to manufacturing environments requiring the design of a more fail-safe system. Lum and co-workers described in detail an integrated laboratory-reactor MOCVD safety system providing multiple-zone status monitoring and alarm warning signals for critical reactor and laboratory subsystems.[3gl This example shows how, in MOCVD laboratories, dependable fail-safe environments can be achieved.
3.0
SPECIFIC MATERIAL SYSTEMS
In this section, MOCVD of layers from specific material systems is discussed. GaAs and lnP based materials have most extensively been studied and find their applications in electronic and photonic devices, whereas, not as many studies have been carried out on MOCVD of narrow and wide gap materials; one reason for this may be the much more complex nature
38
Compound Semiconductors
ofthegrowthprocessofthelattermaterials. Thecurrentunderstandmginthe MOCVD technology ofthese compound semiconductor layers is presented. 3.1
GaAs and InP Based Materials
This section contains MOO growth lattice matched on GaAs and InP substrates; for GaAs based material, not only GaAs and AlGaAs but also growth of AlGaInP on GaAs substrates is considered; for InP based material besides MOCVD of InP, ternary (GaInAs) and quatemary (GalnAsP) layers the phosphorus-free AlGaInAs is also discussed and compared with the conventional GaInAsP system. Selective area epitaxy is described with emphasis on the InP based system, and the section concludes with some selected examples of device applications. Growth and Dopant Incorporation. One of the basic problems in MOCVD of GaAs with Ga(CH,), and ASH, was the intrinsic contamination of the layers by carbon from the metalorganic compounds.[*l The carbon incorporation rate can be afFected by the growth parameters.181[401 An intentional injection of methane (CH,) into the growth reactor, however, did not result in an increased carbon concentration, neither did a substitution of To explain these results, a hydrogen by a helium carrier gas. [81[411[421 hydrogen transfer reaction was proposed occurring at or close to the substrate surface. In this reaction, atomic hydrogen from decomposed ASH, is probably transferred to the hydrocarbons from the metalorganic precursors forming the stable methane.[421By this mechanism, the carbon concentration at the surface is decreased. These considerations were supported by 13C isotopic labeling studies t43land have to be taken into account when looking for alternative As compounds as replacement of the toxic ASH,, which is the source of atomic hydrogen. [311[32JThese investigations are mentioned here in order to demonstrate the importance of a more basic understanding of the growth chemistry for the improvement of the quality of the grown layers and also for the development of new precursors. Though MOCVD is a well established technology, there is a considerable amount of recent doping studies in the literature, both for GaAs and InP based materials, as an improvement of the material quality still appears to be desirable. Some examples of the recent developments are given here. Kuech et al. took advantage of the effect of enhanced carbon incorporation (see above) for p-type doping of MOCVD GaAs layers. Carbon levels between 1016and 10lg cmm3could be achieved by using Ga(CH,), and either As(CH,), or mixtures of As(CH,), and ASH, under typical growth conditions.[441
MOWD
of Compound Semiconductor
Layers
39
These carbon doping studies were successfully extended to AlGaAs layers.1451 In GaAs and AlGaAs, carbon is certainly the p-type dopant of choice. It has a very low diffusion coefficient, and high quality precursors, As(CH,), and Ccl,, are available.l46l147lThe other commonly used dopants are Si and Zn for n- and p-type doping, respectively.lsl The strong temperature dependence of Si incorporation with SiH, as dopant source, resulting in nommiform electron concentrations across large wafer areas, led to the introduction of a new Si dopant precursor, S&I&, which was applied first in Si doping of GaAs and later also in InP and related materials.1481-1501 Problems regarding Si redistribution or migration are not observed as long as the maximum dopant concentration is kept below a critical level, which is in GaAs and AlGaAs approximately 3 x 1018cmW3. This effect of Si concentration on Si migration is visualized in a SIMS depth profile of a AlGaAs/GaAs laser heterostructure (Fig. 1). For a better comparison, the SIMS signals corresponding to Al and Si were normalized. An increasing Si concentration in the Al cladding layer (samples 1 to 4) leads to an increased Si migration into the active GaAs zone; therefore, structures grown with Si concentrations above the critical level resulted in devices with deteriorated laser characteristics .15ll Recently, for Ga,_Jn& layers, Ccl, has successfully been applied as a p-type dopant precursor. Hole concentrations above lO*OcmW3for x < 0.12, and as high as 10lg cmq3for lattice matched layers (x = 0.53) were achieved.15*l The role of carbon in InP, however, is still not as clear as in GaAs. In carbon implanted InP, n-type conductivity is reported with carrier concentrations larger than 10lg cm-3.1531In contrast to GaAs, with Ccl, as the precursor, any incorporation of carbon in InP layers could not be observed.l54l Therefore, for p-type doping, Mg or Zn have been used as dopants.1551-1571 Because of large Zn diffusion coefficients obtained for intentional in-difl%sion after growth, similar large dopant diffusion and redistribution during growth may be suspected. However, recent studies have shown that no significant dopant diffusion takes place as long as the dopant is incorporated mainly on substitutional sites.1551-1571 Figures 2a and b demonstrate the effect of Zn concentration in InP on Zn difE.rsion.1571 Below a critical level of approximately 2 x 10i8 cmm3,the hole concentration along with the Zn concentration in the layers, exhibits a linear increase with the precursor gas flow. In this range, dopant profiles with steep slopes can be achieved, indicating negligible Zn diffusion during growth (Fig 2a). Above the critical level, the carrier concentration saturates; Zn, however, continues to be incorporated with increasing precursor flow, probably on
40
Compound Semiconductors
interstitial sites, resulting in an onset of Zn diffusion (Fig. 2b); as seen in Fig. 2c, this diffusion can markedly be reduced by co-doping with silicon (Fermi level effect of dif%sion).1571A similar effect of Si co-doping on acceptor di&sion has also been observed in MBE-grown GaAs and AlGaAs layers which were doped with Be.15*IThese results show that the dopant type and dopant level of the layer adjacent to the doped layer have a significant effect on dopant diffusion during growth, for example, an n+doped neighboring layer would be very beneficial. Similar results were found for Mgdoped InP based layers, but Zn may be preferred as p-type dopant in InP and related compounds, as discussed in Ref. 57. As in ternary and quaternary layers, the saturation level of the carrier concentration is higher ( 10lg cmm3)than in InP, the onset of diffusion takes place at higher concentrations in these layers than in InP.ls71 With Si as a donor in InP and related materials, some problems concerning doping control and efficiency have been reported. Therefore, for these materials, S or Sn have been preferred.15gl-1611
growth
lo3
direction
-. \ \ \
lo*
-
\ \ \ sample
10’
-
\
4 3 2
1,
\
/
\ . -/
27Al
___
I
I
I
1
2
3
SPUTTER Figure 1. Effect of Si concentration
TIME
[a.
u.1
on Si migration in AlGaAs/GaAs laser structures. Samples 1,2,3, and 4 exhibit Si concentrations (SIMS) in the AlGaAs cladding layer of 3 x lo’*, 4.1 x lo’*, 5.1 x lo’*, and 5.7 x lOI* cmS, respectively.[51]
UO!leJ)UWUO3
Uz
MOCVB of Compound Semiconductor
[ E UJ3/SUJOje]
Layers
41
42
Compound Semiconductors
Growth and dopant incorporation has mainly been investigated on (100) substrates with or without a slight misorient&ion only. Earlier studies have shown an effect of substrate orientation on dopant incorporation already.l8ll4gl A recent investigation has revealed that this orientation dependence is quite complex, as the variation of doping with increasing misorientation from (100) towards { 111) appears to be non-monotonic. This behavior can be applied for selective growth of alternating p/n layers and lateral p-n junction arrays on non-planar surfaces. The technique has been used to create current blocking layers in InP/GaInAsP laser structures grown in groves or on mesa ridges in one single epitaxial ~tep.1~~1 The phosphorus-free (Al,Ga,In)As system opens an interesting alternative to the conventional (Ga,In)(P,As) system because it offers several advantages with respect to material properties and MOCVD growth control. The larger conduction band offset in AlGaInAs/GaInAs structures, compared to InlVGaInAs or GaInAsP/GaImk, is expected to lead to improved device performance in high speed electronic devices (HEMTs) and in multiple quantum well lasers (MQW lasers) as well. An additional advantage is the potential of impurity-induced disordering in these phosphorusfree structures, as in AlGaAs/GaAs laser structures, for obtaining lateral optical and carrier confinement. 1631In MOCVD growth, the almost linear relationship for group III species between layer composition and gas phase composition in the phosphorus-free system, makes accurate composition control easy, not only in unstrained but also strained quaternary layers,l63l whereas in the conventional quaternary material system, the different thermal stability of arsine and phosphine might lead to problems concerning composition reproducibility and uniformity across large areas. Following these arguments, the layer composition in AlGaInAs is expected to be less sensitive to the growth temperature compared to the composition of GaInAsP layers. This effect can be used for the overgrowth of gratings, for example. It was shown that for perfect grating preservation, overgrowth by a quaternary AlGaInAs layer can be started at a temperature as low as 300°C without any deterioration of the laser structure.l64l Another example is growth of quaternary AlGaInAs layers with graded composition revealing that growth in the phosphorus-free system appears to be less complex.[651 However, ultimate pure precursors have to be chosen (especially “oxygenfree” precursors) and extreme precautions have to be taken concerning the leak tightness of the growth apparatus because of the high sensitivity of this material to moisture and oxygen contamination.l66l
MOCVD of Compound Semiconductor
Layers
43
The GaAs-based material system, (Al,Ga,In)P, has attracted considerable interest in recent years because of its potential use for light-emitting diodes (LEDs) and lasers in the visible range between red and green. As this material exhibits a direct band structure, improved brightness in LEDs is expected compared to AlGaAs and GaP LEDs. In a recent overview, the importance of high purity precursors for MOCVD growth in this material system was pointed out. An additional in-situ purification of phosphine, for example, significantly improved the optical properties of AlGaInP/GaInP quantum well structures. f6’j A detailed comparative study between Zn and Mg for p-type doping of AlGaInP showed that though the Mg incorporation efficiency is much higher, especially at elevated growth temperatures, its fast diffusion makes the control of the position of p-n junctions difficult so that Zn may be preferred.i6q So far, examples of growth and dopant incorporation in bulk layers have been given. For many applications, control of layer thickness and composition at the monolayer level in growth direction has to be achieved, such as for MQW layers. With a carefully designed reactor cell and gas manifold, the successful growth of MQW layers, for example with ternary or quaternary wells and quaternary barriers of different composition of InP based material, was demonstrated (see, for example, Ref. 68). Though there is a large number of studies in the literature on growth interruption, purging times, and valve switching sequences for obtaining high quality interfaces, a discussion here is omitted, since most of the published data are too dependent on the specific geometry of the MOCVD system used in the corresponding study. A general rule is to keep any growth interruption intervals as short as possible in order to avoid interface contamination from background impurities. Selective Area Epitaxy. For advanced devices thickness and composition control, not only the vertical (growth) direction but also the lateral direction is necessary. Examples are overgrowth of structured surfaces and growth of various multilayer device structures on the same wafer for the monolithic integration of different devices on this wafer. For this task, selective area epitaxy (SAE) has become a powerful technique in the last years.[6gl SAE can be achieved by several approaches. This discussion focuses on studies where masked substrates or surfaces were used for localized growth in order to obtain epitaxial growth on unmasked areas only. Already in 1978, Duchemin and co-workers reported that, for MOCVD of GaAs on masked substrates, the total amount of material grown on the unmasked area is comparable to that which would have grown in the
44
Compound Semiconductors
absence of the mask.1701This early experiment suggested that growth rate and composition of selectively grown layers might be infhtenced by the geometry of the mask. Indeed, studies in the following years have shown that surface morphology, planarity, and compositional inhomogeneities of selectively grown layers by MOCVD can severely limit the application of this growth technique. 1711-1731 Generally, selectivity can be improved at decreased reactor pressures, increased growth temperatures, and reduced masked areas.1711-t731In recent studies fiuther improvements have been achieved by using chlorinated group III sources,l74l by injection of small amounts of arsenic trichloride t751or HCl I761for growth of GaAs and by introduction of Ccl, for growth of InP.154117rl This section discusses the selective area growth mechanisms for InP based materials. In contrast to AlGaAs, composition inhomogeneities in GaInAs and GaInAsP result in lattice mismatch and could be detrimental to device applications. In SAE, understanding the effect of growth parameters on the shape of selectively grown structures is important for obtaining planarity in these areas. Additionally, it is important to be able to control the shape of selectively grown structures, as the dopant incorporation can be significantly affected by the surface orientation, as mentioned in the preceding section.l62l In order to avoid the formation of undesired (111) planes in SAE, growth rates on these planes have to be enhanced. From MOCVD of GaAs, it is known that kinetically limited growth rates on (111) surfaces can be affected by the V/III ratio.l78l Therefore, in a recent study, the V/III ratio was taken as the key parameter. Furthermore, a low growth rate (0.5 pm/h) and an appropriate substrate orientation [( 100) and (100) 2” off to (1 lo)] were chosenl7gl analogous to optimized growth parameters of a recent MOMBE study on SAE.lgoJ The substrate was sputtered with SiO, double stripes; the length of the 14 pm wide stripes was 500 pm with a 3 pm wide gap in between them. In these studies the masked samples were exposed to growth of InP for two hours which would lead to growth of 1 pm of InP in the case of unmasked substrates. Figure 3 focuses on the gap between the double stripes; the SEM micrograph shows the ridge cross section area with a view of the (O-l-l) plane. Though a relatively low growth temperature was chosen (6OO”C),no deposition on the masked areas could be detected, and a high quality surface morphology of the selectively grown areas was obtained. At a low III/V ratio, the formation of the typical (111) planes was observed (Fig. 3a), which was suppressed at high V/III ratios (Fig. 3b); note the vertical side walls in this figure. This effect of the V/III ratio on ridge geometry of SAE grown InP is demonstrated in Fig. 4. The rate is
MOCVD of Compound Semiconductor Layers
45
approaching the large area value for high V /lli ratios; even at the highest V / III ratio, the rate is still larger by approximately 15% than in the case of growth on unmaskedsubstrates(growth rate ~). This increasedrate, R, is certainly causedby supersaturationof the gas phase,becauseon the masked areasno material consumption takes place, whereas in MOMBE due to the absenceof a gas phase the growth rate is not affected by the presenceof a mask.[80] In addition, it can be recognizedfrom Fig. 4 that the ridge cross section area appearsto be independentof V /III ratio, since with increasing V /III ratio the effective growth rate of the ridge is decreased,but simultaneously, the growth rate in lateral direction is increased.
Figure 3. SEM micrograph of ridge cross section, view of the (0-1-1) plane; ridges were grown under V/Ill ratios of (a) 420, (b) 2800 on misoriented substrates; (c) as in (b). but on (loo) just oriented substrate.[79] (~ 1992 IEEE.)
46
Compound Semiconductors
4 ,
I
,8
I
I
p”
3.5 -
-7
h
“E 1
2 a, -l-J (d L
-
3 -
___.~____________. I____. ______
-0
iii
? 2-
\\
b-l 1.5 -
:
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-6
-
-4
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l ---_
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rl
0
0
.-: Yi
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-l
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0 ’
0
I
I
1000 V/III
2000
I
3ooo”
ratio
Figure 4. Effect of VA ratio on ridge geometry of SAE grown InP between SiO, stripes on misoriented substrates; circles and squares represent data for left and right y-axis, respectively.[79] (0 1992 IEEE.)
This constant ridge cross section area is an important parameter for establishing a qualitative model describing the mechanisms ruling SAE (Fig. 5). The adsorption flux& of the adsorbing species may be consumed as the fluxes An,, f&, and&_, which nominate the fluxes determining the incorporation on (111) planes, surface diflksion and desorption of the adatoms, respectively. At a lower group V adsorption flux, the adsorbed species are supposed to have a higher surface mobility on (111) planes [721 (largef&,n smallJ;,,), resulting in formation of these planes. As the adatoms move rapidly to the top of the ridge, an increased thickness of the ridge at the edges is obtained covering a distance Z,,fi which nominates the diffusion length of the adatoms on top of the ridge. Under this assumption, we expect a ridge shape as visualized by the solid line in Fig. 5, and actually observed in the experiments with a low V/III ratio (Fig. 3a). At a higher group V adsorption flux, however, the mobility of the adatoms may be reduced along with a reduced desorption flux (small f&+nd f&s), growth on the (111)
MOCKS
of Compound Semiconductor
Layers
47
planes should be increased (large&), i.e., growth in the lateral direction is enhanced resulting in a ridge with decreased height and improved planarity (small ldif; dashed line in Fig. 5). Note that in this model, the ridge cross section area should be the same as in the case of the lower group V adsorption flux. Our experimental results support this model (Fig. 3b).
Figure 5. Sketch (not to scale) for qualitative model describing SAE under low and high group V adsorption fluxes (solid and dashed lines, respectively).[7g] (0 1992 IEEE.)
The phosphorus sticking coefficient during MOMBE has been interpreted to be substantially higher on misoriented surfaces than on just oriented surfaces, leading to an increased group V adsorption flux, and consequently, to vertical side walls of the grown structures.[801 The results in Fig. 3c show that even at the highest V/III ratio the formation of (111) planes cannot be suppressed on surfaces without some misorientation. On substrates with a m&orientation, a higher density of steps, and consequently, more adsorption sites are available resulting in a decreased surface diffusion length ,and therefore, in an improved planarity, as explained above (Fig. 5, dashed line). Therefore, this influence of substrate orientation on SAE is not unexpected. 17gl This example of SAE in MOCVD of InP has been discussed here in more detail not only in order to elucidate some basic growth mechanisms, but also in order to demonstrate how trends found in SAE of another technology, MOMBE, are transferable to MOCVD, resulting in an improvement in SAE of MOCVD. However, it has to be mentioned that in MOCVD, both surface kinetics and gas phase diffusion play an important role, whereas in MOMBE only surface kinetics effects are present which are almost comparable to the mechanisms in MOCVD.
48
Compound Semiconductors
It is possible to take advantage of this increased growth rate in SAE in MOCVD. Growth enhancements, because of a varying supersaturation of the gas phase, can be controlled by the mask dimensions; an increasing mask stripe width, for example, will result in an increasing layer thickness adjacent to the mask. Therefore, this technique allows one to taper semiconductor structures, which can find applications in thickness modulated waveguide structures. 18il Lateral thickness variations can also be achieved by the use of a crystalline shadow masks.l82l Implementing MQW layers in the SAE grown structures with intentional thickness variation leads to a shift of the emission wavelength, due to the variation of the thickness of the quantum well so that lateral bandgap engineering can be achieved by these techniques. The drawbacks of these techniques are a broadening of the photoluminescence peaks caused by lateral thickness variations in the quantum wells and large lattice mismatches in InP based materials, induced by a variation in composition of the layers, as discussed below.l83l Not only the growth rate, but also the composition of the layers is affected by the presence of masks on the surface in SAE of MOCVD: an increase of the In content in GaInAs layers is found with decreasing d&an= to the ~&~[@‘1[7W’31W1 n ese results cannot be explained just by surface diffusion of the species, moreover, it is assumed that a frequent interaction of the precursors with the mask (adsorption/desorption processes) leads to partial decomposition; as trimethylindium is less stable than trimethylgallium, an increased concentration of partially decomposed compounds, i.e., dimethyl- and monomethylindium, should be present in the gas phase. For these species, higher gas phase diffusion rates are expected than for trimethylgallium giving rise to In-rich layers close to the masked areas.l73l Therefore, precursors for Ga and In with comparable stability should be chosen in order to obtain an improved homogeneity in SAE of MOCVD. So far, any effect of group V precursors on SAE has been neglected. In a very recent study on binary and ternary layers, however, SAE of GaInAs and GaIr# could not be related in a simple way to SAE of the corresponding binary layers. Therefore, for an interpretation of these results a catalytic effect of the decomposed group V fragments on the decomposition of group III metalorganics was postulated.l85l This example demonstrates the complexity of SAE in MOCVD of III-V compound layers.
MOCKS of Compound Semiconductor Layers
49
For several device applications, SAE around mesa structures is essential. There are not many basic studies in the literature on the SAE of InP-based material around reactive ion etched mesa ridges without mask overhang. For the sake of reproducibility, however, the dry etching technique might be preferred. It was found that planarity is significantly improved at higher growth temperatures, mainly because of lower growth rates on the (0 11) planes forming the mesa side walls; growth at 680°C and at 100 mbar was recommended for sufficient planarity and selectivity for laser fabrication.[861 In a very recent study, it was shown that by the addition of Ccl, selective and planar regrowth of InP around stripe mesas up to 5.5 pm height can be further improved.[771 With unmasked mesa ridges, remarkable differences in growth rates on ridges and on channels between ridges compared to growth rates on planar surfaces have been reported; this effect makes monolithic integration in a single epitaxial step possible, for example in laser-waveguide integration .I87l Selective area epitaxy can also be applied for the fabrication of lowdimensional semiconductor structures. Recently, it was reported that GaAs growth of tetrahedral quantum dots can be achieved resulting in zerodimensional electron-hole systems. [88l SiO,-masked (11 l)B GaAs substrates were used; the masks were partially etched to remove triangles of SiO,. First, AlGaAs truncated tetrahedral structures with three { 1 lo} facets were grown on GaAs triangular areas, and then GaAs dots were sequentially grown on top of the tetrahedral structure; finally, AlGaAs was overgrown on the whole tetrahedral structure. Photoluminescence properties showed zero-dimensional quantum confinement.[881 Another approach to SAE is to make use of different growth rates on planes with different orientations. For example, in contrast to growth of InP, GaInAs does not grow on low-index planes like { 111) or { 1lo} for certain growth conditions. With this technique, growth of buried GaInAs quantum wires and quantum dots in one epitaxial step can be achieved.l8g1l9ol These results demonstrate the potential of the MOCVD technology for the fabrication of nanometer scale quantum wires and quantum dots. A technique for SAE that has not found as many device applications yet as SAE on masked wafers is photon-assisted selective area epitaxial growth. Selectivity can be achieved either by a thermal or a photochemical effect; in the former case, a laser is used for locally heating restricted areas
50
Compound Semiconductors
of the wafer, whereas in the latter case, local decomposition of the precursors at, or close to, the substrate is obtained.t731tg11t921 However, the quality of the grown material may be limited by radiation damage. Additionally, several problems concerning surface morphology, defects and selectivity have still to be solved. Device Applications. In the preceding section, some general device applications related directly to MOCVD of compound semiconductor layers have been outlined. In the following, some selected examples will be presented with emphasis on modem MQW devices and on monolithically integrated devices. In recent overviews, the importance of advanced MOCVD technology was pointed out for electronic devices as well as for optoelectronic devices. lgsl[941GaAs based low noise HEMTs are commercially available now. Large scale fabrication has been achieved in a barrel reactor with twelve 3-inch wafers for AlGaAs/GaAs HEMT ICs with thickness uniformity off 1 % both within each wafer and among the twelve wafers, and similar results were obtained for doping uniformity. Standard deviations in threshold voltage were as small as 10.1 mV for E-HEMTs and 16.1 mV for D-HEMTs across an entire 3-inch wafer.tg51 The application of these wafers in LSI circuits has recently been demonstrated. A HEMT 64 kb SRAM with 0.6 pm gates was fabricated, in a 5 l-stage ring oscillator with an average delay time of 22.6 ps/gate with a 0.8 ps standard deviation over the 3-inch wafer and a power dissipation of 0.8 mW/gate.t%l These results demonstrate that with MOCVD technology an extremely precise and highly reproducible control of layer parameters such as thickness, composition, and carrier concentration can be achieved including superior two-dimensional electron gas characteristics. InP-based HEMTs and HBTs are promising next-generation heterostructure devices, and therefore, a topic of continuous research and development.lg31 For example, in I&based HEMT structures care has to be taken in selecting an appropriate buffer layer for good carrier confinement and low leakage. The use of n&P as a sub-channel layer has led to further device improvements; in an MOCVD grown 0.6 pm gate AlInAs/GaInAs/ n-InP HEMT an extremely high transconductance of 1290 mS/mm was achieved.lg71 For an MOCVD grown AlInAs/GaInAs HEMT using 0.1 urn T-gate technology, operation above 150 GHz was obtained. Here, the background doping in the AlInAs buffer below the channel layer, a critical parameter, has to be kept at low levels (below 5 x 1015cmm3)in order to reduce parasitic conduction through this layer.tg81
MOWD
of Compound Semiconductor
Layers
51
The GaInAsP material system has increasingly gained importance in optical telecommunication fiber systems. The incorporation of a GaInAsP/ GaInAs MQW structure as the active region in laser structures is driven by the requirements of high modulation speed, high power, high operation temperature, narrow linewidth and low threshold current. Even further improvements could be realized by introducing intentional strain into the quantum well. G~,&-,,As/GaInAsP strained-layer MQW lasers emitting at 1.55 pm with cw output powers as high as 200 mW exhibit an extremely high differential external efficiency of 82 %; threshold currents as low as 10 mA and a T, value of 97 K were reported.l99l A comparison has shown that using a confinement region with continuously graded composition leads to improved T, values compared to ungraded structures. The graded region was achieved by simultaneous gas flow ramping of the metalorganic group III and hydride group V precursors.[100l So far, mainly ternary layers for the quantum well layers have been used in both unstrained and strained MQW structures. With ternaries, however, bandgap and lattice constant (strain) cannot be chosen independently of each other, so that for a given lattice constant the emission wavelength can only be tailored by the thickness of the well layer. This leads to very thin well layers, and consequently, to an increased sensitivity of the wavelength to thickness variations. In addition, the optical confmement factor is reduced. To overcome these disadvantages in these structures, quaternary layers as quantum well layers were introduced.l1o1ll1o2l For example, for ridge waveguide lasers (emission wavelength: 1.55 pm) with 1.5% compressive strain in the quaternary well layer, improvements in device characteristics compared to unstrained MQW lasers were obtained. In 1 mm long strained devices, a high characteristic temperature, T,, of 85 K has been measured (lo-50°C) compared to 68 K for unstrained devices. The maximum cw output power at 30°C of the as-cleaved devices could be increased from 35 mW/facet to 50 mW/facet by introducing strain in the layers, and a maximum operation temperature of 140°C was reported.lioll These values are the highest yet observed for long-wavelength lasers with all-quatemary strained MQW active regions. The thickness of the strained layers has to be kept below the critical thickness in the structure. To avoid this problem of thickness restriction, the barriers can be strained in the opposite sense to the wells, resulting in a zero-net-strain structure. In a BH heterostructure laser with 16 quantum wells, the differential gain in case of zero-net-strain was 40% higher than in the case of conventionally strained and unstrained devices. Damping
52
Compound Semiconductors
coefficients imply potential modulation bandwidths in the range of 34 to 42 GHz in these devices .[lo31 An alternative technique for obtaining strained quaternary quantum well layers appears to be the use of the phosphorus-free system AlGaInAs, since the Ga in GaInAs can be partially replaced by Al resulting in a change in emission wavelength at constant well thickness and constant lattice constant. Thus, the wells can be made thicker while maintaining the strain and the emission wavelength. In addition, the emission wavelength can be adjusted either to 1.3 or 1.55 pm while keeping the strain and well thickness constant. Results on QW lasers with both compressive and tensile strain were reported.t631 The presence of the Al did not degrade the laser performance; threshold current densities as low as 96 A/cm2 were obtained in compressively strained 5 mm long 1.32 pm lasers. It was verified that the emission wavelength was TE and TM mode in case of compressive and tensile strained lasers, respectively. The first successful fabrication and operation of gain-coupled 1.55 pm A1GahuA.sMQW metal clad ridge waveguide DFB lasers, was recently reported .[‘j41Figure 6 shows the structure with a first order grating. The 40 nm thick n-GaInAs layer, which was grown in the first epitaxial step, provided the loss grating. The crucial epitaxial step in such a structure is the overgrowth of the grating. Perfect grating preservation was achieved by starting the overgrowth of the quaternary layer at 300°C, as pointed out already in a preceding section. For as-cleaved devices, the single mode yield was as high as 70 % and 95 % for 600 and 800 pm long devices, respectively; typical threshold currents were 40 and 55 mA, respectively. For 600 pm long devices, a cw output power of 10 mW and a minimum linewidth of 1.6 MHz were measured. In the conventional GaInAsP system, the fabrication of a 1.55 urn index/gaincoupled DFB laser with a strained MQW active grating was achieved .[io41The structure in Fig. 7 shows that the overgrowth of the first order grating was performed using an InP layer. The five 5.5 nm thick quaternary wells exhibited a compressive strain of 1.5 %, the four 10 nm thick quaternary barriers were unstrained. More than 90 % of the 115 ascleaved devices with 125 pm and 250 pm cavity lengths showed single longitudinal mode oscillation. A side-mode suppression ratio as high as 52 dB was obtained for 125 pm long lasers under dc operation. A maximum output power of 10 mW and a threshold current of 19 nu4 were measured, the latter value is among the best for previously reported gain-coupling type DFB lasers.
MOCKS of CompoundSemiconductorLayers
p“
53
6lnAs
p-MIAS
n-MIAs
, / I
‘-A
\
n’- InP substrate \ \
Figure 6. Layer structure of gain coupled 1.55 pm AlGaInAs MQW MCRW DFE3 laser, black triangles represent the ternary loss grating layer.[641 @I 1992 IEEE.)
54
Compound Semiconductors
0.2um l&m
cap
pt-InGaAs
cladding
plnP I
30A
O&m
p-InGaAsP plnP
etch stop buffer 7OOAInGakP(1 .Oum) SCH MQW active region: well 55A x 5 barrier IOOA x 4(1.2!5um)
Figure 7. Layer structure of index/gain coupled 1.55 pm GaInAsP MQW ridge waveguide DFB laser.[104] (Reprinted by permission of the publisher, Electronic Letters)
The importance of the GaAs-based AlGaInP material for optical devices has been mentioned in a previous section. A high-efficiency MOCVD AlGaInP surface emission LED with an AlGaAs window layer was successfully fabricated with emission at 620 nm; at 20 mA injection current the external quantum efficiency was 1.5 %. This LED was five times more efficient at 620 nm than AlGaAs and GaAsP LEDs. A 563 run green electroluminescence was also achieved with an (Al,,,Ga&,&,,P active layer.[lo51In another recent study, an MOCVD-grown AlGaInP LED structure with a lattice mismatched GaP conductive window was described.[lo61 With increasing thickness of this window layer from 5 to 15 urn, an increased efficiency due to the effect of current spreading was obtained. Green emitters (554 nm wavelength) were fabricated representing the shortest wavelength devices yet reported for the AlGaInP system. The high material quality in MOCVD grown AlGaInP/GaInP laser structures was also demonstrated by narrow index-guided ridge lasers emitting at 670
MOCKD of Compound Semiconductor Layers
55
nm, where cw operation up to 100°C was reported.16~ A study on long-term stability of strained MQW lasers in this material system (5 pm wide buried ridge stripe structure) revealed stable operation for more than 5500 h at 50°C, resulting in an estimated mean time to failure of 10,900 h.[lOq In uncoated devices, cw operation with an optical output power exceeding 3 mW was observed up to 160°C, which is the highest operation temperature reported for visible lasers. lio81 For AlGaAs/GaAs narrow oxide stripe lasers (870 run), degradation rates below low5h-l were measured at 80°C and 5 mW cw optical output/facet and at 60°C, 10 mW, operating more than 16,000 h;llogl today the operating time of these lasers is exceeding 85,000 h under these conditions.l11ol Vertical cavity surface emitting lasers (VCSEL) offer several advantages over edge emitting designs, especially in two-dimensional high density arrays, chip-to-chip optical interconnection, or for monolithic integration. For good device performance, however, very tight tolerances have to be fulfilled, for example, concerning control of the quantum well thickness. A systematic error exceeding &to.5% in thickness deviation can not be tolerated indicating the stringent requirements on for properly working devices, 11111 the growth technology. It has been demonstrated that MOCVD is a viable growth technology for AlGaAs/GaAs VCSEL structures. Room temperature optically pumped cw lasing has been observed with powers of 22 mW, power efficiencies over 45% and single fundamental transverse mode operation.[111l The monolithic integration of proven discrete devices such as lasers, photodetectors, and waveguides is gaining increasing importance for the fabrication of economic chips. As described in the preceding section, selective area epitaxy (SAE) has become a powerful technique for reaching this aim. Lateral bandgap engineering can find applications, for example, in an array of lasers emitting at different wavelengths. Though this can be achieved by different individual lasers, monolithic integration might be preferred. Recently, this was achieved in one single MOCVD run by the use of shadow masked growth in combination with MQW active regions. In GaInAs/GaInAsP strained-layer MQW Fabry-Perot lasers, it was possible to obtain a wavelength span of 130 nm centered around 1.55 pm at constant threshold current.l112l The integration of a low threshold buried ridge DFB laser with a waveguide has been realized by SAE in MOCVD. Laser threshold currents as low as 10 mA and waveguide output powers in excess of 3 mW were achieved for 1 mm long waveguide devices.l113l Laser-waveguide integra-
56
CompoundSemiconductors
tion is even possible in just a single epitaxial step using non-planar surfaces.[114l SAE was also applied for the integration of a GaInAs photodetector and butt-coupled InP/GaInAsP/InP waveguide. The device showed a fast pulse response (60-65 ps FWHM with a 3 dB bandwidth of 2.7 GHz) and appears to be easy integrable with FET receiver circuitry.l115l The integration of both GaInAsP lasers and GaInAs photodiodes with impedance matching circuits for 6 GI-Iz transmission, should be mentioned. The characteristics of integrated and discrete lasers were quite similar indicating that the more complex technology does not result in any deterioration.l116I Finally, another example of lateral bandgap engineering should be given: a butt-jointless MQW DFB laser-modulator integrated light source was fabricated.l117l The bandgap energy of the selectively grown MQW structure was controlled by the mask stripe width, as described in the preceding section. l*ll A total energy shift of 58 meV was obtained for the GaInAs/GaInAsP MQW structure grown with 3 to 10 pm wide mask stripes.l117l The threshold current of the DFB laser was 35 mA, and more than 5 mW light power was obtained at the modulator output. The coupling efficiency between laser and modulator was estimated to be approximately 100%. 3.2
Narrow Bandgap Materials
In this section, recent developments in MOCVD growth of narrow bandgap materials are outlined. The main efforts in this field have been in Because of problems in the II-VI material system Hg,,C4;Te. 11181111gl epitaxial growth and thermal stability of these compounds, increasing research activities in Sb containing compounds as a replacement of II-VI compounds can be observed in recent years. Therefore, in the second part of this section this III-V material system is described as an alternative to the IIVI material system. II-VI Compounds. The advanced state of MOCVD of GaAs and InP based systems has been described in the preceding section. Growth of the II-VI compound HgCdTe (MCT), however, is much more complicated, since the optimum growth conditions for HgTe and CdTe are quite different, as discussed in detail in a recent review.l12ol The major problem in MOCVD of MCT is the choice of an appropriate growth temperature. For deposition with the standard precursor diethyltelhuide, a temperature around 400°C has to be chosen, whereas at this temperature, high Hg pressure is required for surface stabilization. 11211Furthermore, at these high tempera-
MOCVD of Compound Semiconductor
Layers
57
trues, significant selfditfusion takes place, and large concentrations of Hg vacancies are created, acting as acceptors. Therefore, in the last few years among the most important research topics were uniformity control across larger areas and conductivity control. To solve these problems, several approaches have been proposed. In the more traditional direct alloy growth (DAG) process, all three precursors are simultaneously introduced into the reactor to grow HgCdTe of the required composition.l12oll121l In the interdiffised multilayer process (IMP), alternate layers of HgTe and CdTe are sequentially grown under conditions optimized for the respective binary layers, and then annealed immediately after the growth period for homogenizing the structure by interdif&sion.ll**l By the latter technique, improved uniformity of the layers across larger areas could be obtained, however, due to the lattice mismatch between HgTe and CdTe, the possibility of defect generation exists, and the nucleation of CdTe on HgTe might be difficult to control.[1201Another approach is to reduce the growth temperature, which can be achieved in a photon-assisted growth process 1123111241 or by the use of alternative Te precursors.l125l In MOCVD growth of the ternary GaAs and InP based material (AlGaAs and GaInAs, respectively), the growth process is mass transport limited, the growth rate of the ternaries is the summation of the rates of the corresponding binaries, and the alloy composition is directly related to the ratio of group III precursors in the gas phase. In contrast to this behavior in MOCVD of the ternary Hg,,C&Te with dimethylcadmium (DMCd), diethyltelluride (DETe) and elementary mercury (Hg) as precursors, the growth rate of HgTe is affected by the presence of the Cd precursor. A significant decrease of the total growth rate and an increase in composition x were observed, when the DMCd flow is increased.l120l Similar results were obtained with diisopropyltelluride (DIPTe) as the Te precursor, and adduct formation was proposed as an explanation for these results.l126l Hence, it is very important to avoid any depletion of DMCd over a larger area, in order to achieve good uniformity over the substrate. For device applications, the composition, x, has to be kept at 0.2 kO.005 over the area of interest, a uniformity which is difficult to achieve in the DAG process.11201In the IMP process, the significant advantage is the uniformity of the layers; here a radial uniformity (Ax) of *to.003 over a square of 9 cm* on a 2-inch GaAs substrate was reported.tlrgl Replacing the standard CdTe substrates by CdTeSe substrates has led to growth of high quality HgCdTe layers by the DAG technique; the layers were grown in a vertical reactor and had a compositional uniformity of
58
Compound Semiconductors
kO.005 over a 1 cm x 2 cm area substrate. With a rotating substrate, an improvement to values better than *to.002 is expected.l127l The FWHM value of about 47 arcsec in the x-ray rocking curve was about three times smaller than that for layers grown simultaneously on CdTe substrates. The reason for this improvement in crystal quality cannot only be found in the better lattice match, but also in the superior crystal quality of the CdTeSe substrate itself compared to CdTe. In the IMP process, growth of HgCdTe on CdTeSe and CdZnTe substrates was reported.l128l Though HgCdTe could be grown at temperatures as low as 33O”C, for improved crystal quality the temperature was raised to 420°C for x in the range of 0.19 to 0.24. This effect of growth temperature on the FWHM values ofthe rocking curves is shown in Fig. 8; it can be seen that values below 30 arcsec were obtained. This study indicated that the quality of the HgCdTe layers was still restricted by that of the CdTeSe and CdZnTe substrates. Therefore, an alternative approach would be to grow buffer layers on high quality lattice mismatched substrates such as GaAs.
Growth Temp.( W
Figure 8. Effect of growth temperature on rocking curve widths of HgCdTe layers grown on CdTeSe substrates (circles) and on CdZnTe substrates (triangles).[128] (Reprinted Sv permission of the publisher, American Institute of Physics.)
MOCKD of Compound Semiconductor
Layers
59
Recently, a vertical reactor with a multinozzle injector and a rotating susceptor was proposed for improving the uniformity; precursors were DMCd, DIPTe and Hg.t 12gl As the composition profile of the layer grown by the injection of DMCd from two nozzles was the same as the summation of the two profiles produced with one nozzle, the profile for injecting DMCd from multinozzles could be calculated. This simulation calculation showed that with 4 nozzle injectors a composition uniformity (Ax) of 0.04 should be achieved across a 3-inch wafer, and that 8 nozzle injectors are needed to achieve a compositional variation (Ax) of 0.002 over the same area demonstrating the significant improvement in composition uniformity. Compositional control has also been accomplished by photon-assisted MOCVD using a KrF excimer laser;t1241by increasing the laser repetition rate from 100 to 400 Hz, the composition x decreased from 0.8 to 0.2. This decrease in composition was associated with increased photodecomposition of the precursor DETe. It was suggested that the composition x did not necessarily increase with increased photodecomposition of the precursor DMCd. Undoped layers are p-type due to the presence of Hg vacancies. A conversion to n-type conductivity can often be observed after annealing the layers under Hg-rich conditions, probably because of the presence of residual donor impurities after elimination of the Hg vacancies.[1201 With trimethylindium, n-type doping can be achieved. The net donor concentration was found to exhibit a linear relationship with the dopant partial pressure over a range of carrier concentration from 5 x 1016 to 3 x lo’* cmm3. Saturation of the In incorporation was observed for even higher TM1 concentrations and is believed to be due to the formation of In2Tes precipitate~.t’~~1[~~~1 The In incorporation probably occurs mainly on Hg sites. High electron mobilities measured over the entire dopant range indicated a low compensation of the layers. The incorporation of acceptors in HgCdTe can be achieved by injecting arsine1131Jor alternative As precursors such as tertiarybutylarsine and diethylarsine. [1321Carrier concentrations over the range from approximately 5 x 1015to 2 x 1017 crnm3have been obtained. At increased Hg pressures an enhanced As incorporation was observed. A higher arsine flow, however, leads to a decrease in composition so that with increasing amine flow an increasing DMCd flow is required in order to keep the composition constant. This behavior suggests the formation of a DMCdASH, adduct in the gas phase.[1201
60
Compound Semiconductors
As discussed above, the stringent requirements of compositional and conductivity control in HgCdTe are beginning to be fulfilled. Recent overviews on photovoltaic detectors and photoconductors have revealed tbat MOCVD is now capable of producing HgCdTe devices with state-of-the-art performance.111gl11201 The peak responsivities of detectors fabricated with MOCVD material are comparable to those from LPE material. These accomplishments underline the significant progress that has been made in MOCVD of HgCdTe in the last few years. Sb-Containing Compounds. The interest in antimony-containing compounds in the material system (Ga,In)(As,Sb) is generated by the extremely large bandgap range which can be covered in this system resulting in many applications in optoelectronic and electronic devices. With an emission range from 0.9 to 12 pm (1.43 to 0.1 ev), this material exhibits the Optoelectronic applicasmallest bandgap of III-V semiconductors. 1133111341 tions are infrared detectors in the 2 to 4 pm range as well as in the 8- 12 pm range. Additionally, a low electron effective mass makes InSb attractive for high-speed circuits, for example. However, this alloy system is known to have a very large miscibility gap, but this makes it an ideal candidate for the study of met&able III-V alloys. [1331[1341 In spite of these interests, there has been much less MOCVD activity for this material system than for the larger bandgap GaAs and InP based materials. The problem in MOCVD growth of Sb-containing compounds is the non-volatility and the very low surface mobility of elemental antimony compared to As or P in the GaAs and InP based material systems. Therefore, only a very narrow range of V/III ratio and growth temperature can be used for obtaining layers with high quality surface morphology. For example, for growth of GaSb, a strong effect of V/III ratio on layer morphology was found; mirrorlike surfaces could be observed at V/III ratios in the range of 6 to 8 at a growth temperature of 600°C and a reactor pressure of 100 torr; bound-exciton peaks in the photoluminescence spectra only appeared in samples grown at a V/III ratio of 6.8 demonstrating the narrow window of growth parameters for high quality layers. This narrow window can also be recognized in Fig. 9, where the effect of V/III ratio on the FWHM of acceptor-band peaks is visualized: the FWHM value is smaller for V/III ratios in the range of 6-8 and increases drastically for V/III ratio larger than 10.11351Additionally, in another study, it was found that the optimum V/III ratio varies with growth pressure; at lower pressures, a decrease of this ratio was required for maintaining good morphology probably due to the reduced sticking coefficient of the gallium compounds
MOCKD of CompoundSemiconductorLayers
61
on the growing surface. A drastic decrease of the growth rate at 500°C was observed and was thought to be caused by the less efficient decomposition of the Sb precursor trimethylantimony.[1361 44.
L j 4. _
24
0
I .
100 toll 6OO*C
I 2
I 4
I 6
I 8
I IO
8
TtlSb/TEGa RATIO
Figure 9. Effect of V/m ratio on the FWHM of the acceptor bands in photoluminescence spectra measured on GaSb at 17 K .[‘351 (Reprinted by permission of the publisher, American Institute of Physics.)
For growth of InSb on GaAs substrates (lattice mismatch 14.5%), a very narrow range of V/III ratios (2 to 3) was reported for obtaining high mobility layers. Under optimized growth conditions, Hall mobilities up to 60,900 and 27,000 cm2Ns were measured at 300 and 77 K, respectively. Best surface morphologies were achieved at a V/III ratio of 3 .1137lAnother study on high mobility InSb emphasized the importance of high-purity sources and strict control of V/III ratio across the susceptor.113*l In layers grown at 450°C on InSb substrates, an optimum V/III ratio of 7.4 was found. Carrier concentration and mobility measured at 77 K were 1.4 x 1015 cms3and 2.53 x lo5 cm2Ns, respectively, whereas growth on GaAs substrates appeared to be largely affected by the lattice mismatch resulting in 77 K mobilities of 5-9 x lo4 cm2Ns.11381
62
Compound Semiconductors
The optimization of the initial growth process is important for growth of Ga,_,In$b layers on GaSb and GaAs substrates due to the large lattice mismatch. Surface morphology and electrical properties were markedly improved using graded GaInSb buffer layers, step buffer layers with 5, 15, 22.5 and 30% In for the Ga,&n,&b final layer, and strained layer superlattice buffer layers (20 nm Ga,Jn,,sSb/20 nm GaSb).113gl Due to the thermal stability of the precursor trimethylantimonide, low temperature growth in this material system is difficult to achieve. For example, in MOCVD of InSb with this Sb precursor at 4OO”C,the formation of In droplets was always observed. Therefore, for this growth temperature, it was replaced by the less stable triethylantimonide.11371 Lower growth temperatures, however, should be explored because of two main reasons. Firstly, the potential for growing metastable bismuthcontaining compounds should not be ignored, as these compounds, such as InAsSbBi, are an attractive alternative material for infrared detectors operating in the range from 8 to 12 urn. For growth of these metastable compounds, low temperatures are required.ll““l Secondly, due to the low melting point of InSb (525OC), high temperatures are not acceptable for growth of thin InSb layers with abrupt interf!ace~.l~~~lA substitution of the stable Sb alkyle by less stable Sb hydride SbH, was proposed to achieve the aim of low temperature growth.11411By inserting a buffer layer grown at 400°C, the single crystal InSb layer was grown at 300°C on an InSb substrate in a vacuum MOCVD system without carrier gas. A V/III ratio (gas flow ratio of stibine to triethylindium) higher than 8 had to be chosen. The nominally undoped epitaxial layers were n-type with a carrier concentration and a mobility at 77 K of 1.5 x 1016 cmm3and 7.6 x lo4 cm2/Vs, respectively. The instability of this Sb source, however, may prevent wider applications. With triisopropylantimony as an alternative source, InSb growth was possible at temperatures as low as 300°C. However, a high V/ III ratio had to be u~ed.1~~~11~~~1 A 77 K carrier concentration of 3.7 x 1016 cms3and mobility of 6.3 x lo4 cm2iVs were obtained for InSb layers grown on InSb substrates at 350°C.11421A recent study has shown that the most promising Sb source appears to be tertiarybutyldimethylantimony. Even at temperatures below 400°C, very low V/III ratios were acceptable, and a high growth efficiency indicated negligible parasitic reactions between the In and Sb precursors.llUl Another approach for low temperature growth was recently described. The Sb precursor triethylantimonide (TESb) was precracked in a dc plasma.l145l Growth of InSb and GaSb was performed at 20 mbar on
MOCKS
of Compound Semiconductor
Layers
63
GaAs and GaSb substrates, respectively; the plasma power was 10 W. The results indicated that at low temperatures (below SOOOC),growth of InSb is limited by the stability of the Sb precursor. For example, at 450°C, an enhancement of the InSb growth rate by about a factor of two could be achieved applying a dc plasma; best electrical data (300 K) were 2 x lOi crnv3 and 35,000 cm2/Vs for electron concentration and Hall mobility, respectively, compared to 7 x 1017cm-3 and 2000 cm2/Vs, respectively, for growth without plasma. For growth of GaSb with trimethylgallium (TMG) and TESb, additional TESb-precracking did not affect the growth kinetics; therefore, it was concluded that the thermal stability of TMG limits the GaSb growth rate. When substituting TMG by the less stable triethylgallium (TEG), a strong enhancement of the growth rate was detected, and an additional effect of TESb-precracking on the growth kinetics of GaSb could clearly be observed at growth temperatures below 53OOC. A further improvement of the electrical quality of the layers, however, was not found. Several donors have been investigated in I&b. As revealed by secondary ion mass spectrometry, with tin as the n-type dopant, sharp dopant profiles could be achieved. These SIMS results and the improved current-voltage characteristics of InSb diodes indicate that tin is a much better dopant than Te or Se. 1146l In another investigation, w,h’b4Sb/ GaSb p-n homojunctions on GaSb substrates exhibited an external quantum efficiency of 43 % at 2.6 pm, and a long wavelength cutoff up to 2.9 pm was measured. These results are the highest quantum efficiency and wavelength cutoff yet reported for GaInSb photodiodes in this wavelength range.l147l Long wavelength photodiodes were also fabricated using a p-n junction embedded in an InAs,,SbJInSb strained-layer superlattice (SLS), where a composition-graded InAs,,Sb, layer acted as a strain-relief buffer between the SLS and the p+-InSb substrate. The detectors displayed broad spectral response extending to wavelengths of 10 um.l148l Because of the difficulties in epitaxial growth and processing of the II-VI compounds, the generally more developed III-V compounds may be preferred for narrow bandgap applications. Possibly with Sb-containing compounds, problems concerning large area uniformity and dopant control are easier to overcome than with II-VI compounds. 3.3
Wide Bandgap Materials
The development of wide bandgap materials has been stimulated by the demand for optical devices such as light-emitting diodes and laser diodes
64
Compound Semiconductors
operating in the green-blue-near-UV region. For this material, the main activities have been in II-VI compounds for several years already, similar to the work on narrow bandgap material. Additionally, GaN and related compounds have attracted much interest as wide bandgap material in the recent past. Therefore, in this section, the main efforts in both material systems are described. II-VI Compounds. A significant breakthrough in wide bandgap IIVI compounds was the fabrication of the first blue-green laser diodes in 199 1. An MBE-grown &Se-based single quantum well structure was chosen, and the devices emitted coherent light at a wavelength of 490 nm under pulsed current injection at 77 K.114glThis success was made possible after the difficult problem of growing p-type material with sufficiently high carrier concentrations had been overcome. This was accomplished by doping with nitrogen from an RF plasma source with N2 gas. In MOCVD of wide bandgap II-VI compound layers, similar problems of conductivity control exist. liislli5~lli5il Growth of ZnSe on GaAs substrates has been studied most extensively. With hydrogen selenide as precursor, premature reactions were observed. Therefore, zinc and selenium alkyls were used as precursors. 115*1Decomposition of these alkyles, however, requires relatively high growth temperatures, around 5OO”C, resulting in the formation of native defects. These defects act as acceptors such as Zn vacancies in ZnSe and ZnS or as donors such as Se and S vacancies in ZnSe and ZnS, respectively.t1501 In order to reduce this selfcompensation, the growth temperature should be reduced as low as possible. It has been shown that at temperatures as low as 350°C, photo-assisted growth of ZnSe is possible with 365 run light from a high-pressure mercury arc lamp. However, the surface morphology was reported to deteriorate with increasing irradiation intensity. 1153lThe growth rate at low temperatures in the range of 300 to 400°C can also be increased by using the abovebandgap irradiation of the 458-5 15 nm lines from an Ar laser.t1541As the precursors have absorption bands at wavelengths shorter than 250 nm, direct absorption by the source materials cannot be expected. The photoassisted process is, therefore, attributed to photocatalysis in which the growing material acts as a catalyst and promotes growth reactions. This technique appears to be promising for the reduction of compensating native defects and for achieving p-type doping control. From the results published in the literature, there appears to be no problem in controlling the carrier concentration in n-type layers over a wide range of lOi to lOi cm-3, if the growth temperature is lower than about
MOCVD of Compound Semiconductor
Layers
65
350°C. At higher temperatures, the self-compensation effect becomes dominant, resulting in lower free carrier concentrations.1150j1151j The results on p-type doping, however, indicate the necessity for more research. Croup V elements as acceptors have been extensively studied in the past. As the host material is grown under group VI rich conditions, the introduction of group V acceptors in the crystal lattice substituting on group VI sites has been diflicult to achieve. Therefore, lithium as shallow acceptor substituting on an Zn site has been proposed. With lithium nitride as the doping source for growth of p-type ZnSe at 450°C, the lowest resistivity of the layers was 0.2 Szcm at the highest carrier concentration of 9 x 10” cm-3.1155jFigure 10 shows the temperature dependence of the carrier concentration for two specific samples with lower and higher carrier concentrations. For the former sample, an activation energy of about 80 meV was estimated, whereas the temperature independence for the latter sample could be explained by the formation of a degenerate impurity band at such a high acceptor concentration.l155l In another study, secondary ion mass spectrometry on Lidoped ZnSe layers revealed that the Li concentration in the layers could be varied from 4 x 1016to 4 x 1017cmm3by a variation of the carrier gas through the tertiarybutyllithium source. The growth was performed at 500°C which resulted in the electrical activity of only 1% .1i5’jlThese results suggest that these ZnSe layers may contain a high concentration of compensation centers. In addition, it was suspected that part of the dopant atoms might not be incorporated on Zn sites, but probably on interstitial sites acting as compensating donors. 11571In Lidoped ZnS layers, the lowest resistivity was about 4 x 1O2Szcm, and the highest p-type carrier conccntration was 7.5 x 1015cmm3.As revealed by x-ray rocking curves, the crystal quality appears to be improved by lithium incorporation at an appropriate level suggesting a reduction of the dislocation density in the layers .[158lIn a recent study with the new Li precursor dimethylaminolithium, well defined p-n junctions were realized in ZnSe.t15gl With lithium nitride and triethylaluminum as p-type and, respectively, n-type dopants ZnSe p-n junctions for light-emitting diodes could be fabricated. An example of the ZnSe electroltiesccncc spectrum at room temperature is given in Fig. 11. It is composed of a blue emission band peaking at about 467 nm and a broad band located in the longer wavelength region.t1551 First lasing experiments in MOCVD grown structures were performed under optical pumping. The growth temperature of the ZnSe/ ZnSSe structure was held at 515°C; a ZnSe/ZnSSe superlattice grown directly on the GaAs substrate worked as an optical confinement layer and
66
Compound Semiconductors
helped smoothen the grown surface. The sample was excited with a N, pulsed laser at the wavelength of 337 run. A high output power of 24 W was observed at room temperature. At this power, an external quantum efficiency, defined by the ratio of the output photon flux to the input photon flux, of 1.5 % was obtained. An emission wavelength of 473 run was measured.l16ol A local restriction of the photoexcitation to the active ZnSe layer only resulted in a drastic decrease of the lasing threshold.[1611 Figure 12 shows that the lowest threshold was 10 kW/cm2 at room temperature, which is equivalent to a current density of 3.6 kA/cm2. The lasing wavelength at room temperature was about 470 run, and was observed through a monochromator in order to suppress the scattered excitation light. A characteristic temperature T,of 124 K was found, as measured up to 400 K. This is the lowest threshold yet reported on II-VI photopumped lasers at room temperature. These recent advances in MOCVD of wide bandgap IIVI materials demonstrate the potential of this growth technology, so that the realization of practical devices such as current injection lasers operating at room temperature seems to be within reach. TEMPERATURE (K I ~~~~
b
0 \
I
0
103/T
(K-l)
Figure 10. Temperature dependence of carrier concentration for Li doped ZnSe layers.[~5*] (Reprinted by permission of the publisher, American Institute of Physics.)
MOCKS
600
of Compound Semiconductor
550
WAVELENGTH 500
inm
Layers
67
1 450
RT
2.0
2.2 PHOTON
2.4 2.6 ENERGY (eVI
2.6
Figure 11. Electroluminescence spectrum at room temperature of a ZnSe p-n diode.[155] (Reprinted by permission of the publisher, American Institute of Physics.)
Excitation Power (kW/crn*) Figure 12. Light output vs excitation optical power characteristics measured on a device with a cavity length of L,= 200 pm in the temperature range of 300 to 400 K. The excitation was at a wavelength of 450 nm.[ ‘6’1 (Reprinted by permission of the publisher, American Institute of Physics.)
68
Compound Semiconductors GaN and Related Compounds.
As mentioned above, the majority of the efforts for blue/UV lasers is still concentrated on ZnSe and its alloys, nevertheless, recent improvements in MOCVD growth in the material system (Al,Ga,In)N have demonstrated the potential of this material for optical devices.t1621This material system is of considerable interest, as the direct bandgap can be tuned from 2 to 6.2 eV. A major problem is the selection of an appropriate substrate; sapphire has been used most widely. The lattice mismatch, however, is as large as 22 % to InN, 14 % to GaN and 12 % to AlN.11621Another problem is the extremely high equilibrium vapor pressure of the group V elements at growth temperature, making Incontaining compounds the most difficult to grow in this material system. In addition, the high stability of the standard nitrogen source, ammonia, may lead to high growth temperatures and high V/III ratios. These problems have been attacked by introducing additional buffer layers, by growing on a lattice matched substrate, by applying hydrazine instead of ammonia as the nitrogen source, and by using excitation techniques such as an electron cyclotron resonance plasnn~l~~~l-[~~~l GaN grown directly on sapphire exhibits poor crystal quality, as expected, from the large lattice mismatch and the chemical dissimilarity between both materials. Introduction of a thin AlN buffer layer led to a significant improvement in crystal quality. The key growth parameters for high quality GaN layers were the growth temperature and thickness of the AlN layer as well as the growth temperature of the GaN layer; the growth temperature of the buffer layer had to be kept below llOO”C, and the thickness below 150 nm in order to avoid polycrystalline growth.11661[1671 Another approach for optimizing GaN growth on sapphire has been the insertion of a 20 run thick GaN buffer layer grown between 450 and 600°C and subsequent growth of the 2 pm thick GaN layer between 1000 and 1030°C resulting in better crystal quality than without a buffer layer.11681 With this technique, a maximum mobility of 3000 cm2/Vs was obtained at 70 K indicating the low impurity concentration in these layers.[1691This is the highest mobility value reported for GaN films so far. The first successful growth of InN was achieved by using low growth temperatures (550-600°C) and very high V/III ratios (above 16,000). The composition in the material system (Ga,In)N from GaN to InN could be controlled by adjusting the flow rates of the gallium and indium precursors, triethylgallium and trimethylindium, respectively.11701The growth of GaInN lattice matched to a substrate was recently accomplished by utilizing a ZnO single crystal wafer and an In content of 22% in the ternary layer.l”j31 The
MOCVD of Compound Semiconductor
Layers
69
FWHM values of the x-ray rocking curves of these layers on ZnO were about 20% smaller than that on the standard sapphire substrates. In all cases, however, the FWHM values were still quite large (about 50 min) compared to the FWHM values of the standard III-V compound layers in the GaAs and InP based material systems, suggesting that a careful optimization of the surface treatment of the ZnO substrates and the growth conditions is still required.11631These ZnO substrates are not yet commercially available. The next step then was quite recently the first growth of a quaternary alloy AlGaInN on a sapphire substrate at 800°C. It was possible to measure an optical transmission of the 0.2 urn thick AJ,74G~.231n,,,,-,3N layer.l163l Due to the high group V equilibrium vapor pressure, conductivity control is expected to be difficult to achieve in this material system. With SiH, as the dopant precursor, electron concentrations of 5 x 101*cms3have been reached in GaN.li7il Conductivity of the p-type, however, appeared to be a much larger problem. The resistivity of Mgdoped GaN layers has been found to be reduced by after-growth treatments. With low-energy electronbeam irradiation (LEEBI), the high resistivity of the as-grown layers was markedly decreased; a value as low as 0.2 !A cm was measured at room temperature, the hole concentration was 3 x 1018cm-3.11721 This resistivity value is the lowest and the carrier concentration is the highest reported for ptype GaN layers up to now. Thermal annealing of Mgdoped GaN at temperatures above 700°C resulted in a carrier concentration of 3 x 10” cmm3;the resistivity was 2 Sz cm, whereas before this heat treatment, values around lo6 n cm were measured .lI731 It should be mentioned that in both studies 1172111731 similar GaN buffer layers were used. With the LEEBI technique, however, only thin regions below the surface are affected so that, for obtaining larger p-type regions, the annealing technique may be preferred.1162111731 It appears that GaN layers grown with GaN buffer layers are superior to those grown with AlN buffer layers in terms of crystal quality and p-type conductivity control. After this success in conductivity control, p-n junctions in GaN were fabricated. In light-emitting diodes (LEDs) with a GaN buffer, a forward voltage as low as 4 V at a forward current of 20 mA was measured.l171l The schematic of the structure and the typical I-V characteristics of this p-n junction GaN LED are shown in Fig. 13. This is the lowest value of the forward voltage reported for GaN LEDs up to now, and was made possible by the significant reduction of the resistivity (0.2 Sz cm) in the p-type GaN layer.l172lThe output power ofthese GaN LEDs was almost 10 times higher
70
Compound Semiconductors
than that of commercially available SIC LEDs in the range of forward currents between 1 and 4 mA. For example, at 4 mA, the output power of GaN LEDs was 20 pW compared to 2 pW of Sic LEDs; at 20 mA, the output power of GaN LEDs was 42 pW and that of SIC LEDs was 7 pW. A peak wavelength of 430 nm was measured for the GaN LEDs.[1711 Besides this emission peak in the blue region, an additional peak in the W region (366 MI) was observed at low forward currents (below 30 mA) in GaN LEDs with an AIN buffer.[ 1741 This difference in emission spectra might be attributed to the difference in buffer layers, resulting in a lower electrical activation in the case of an AlN buffer layer.[1711
a)
P-Elcctmde
Sapphire Substrate
b)
Figure 13. (a) Structure of a p-n junction GaN LED; (b) typical I-V characteristics of the p-n junction GaN LED.[“‘] (Reprinted by permission of the publisher, Japanese Journal of Applied Physics.)
MOCKS
of Compound Semiconductor
Layers
71
The first observation of room temperature stimulated emission near UV from MOCVD grown GaN on sapphire with an AlN buffer layer was reported in 1990.f 1751 The sample was excited by a pulsed N, laser at a wavelength of 337.1 nm. The threshold for stimulated emission was determined as approximately 0.7 MW/cm*, the emission wavelength was around 373 nm, as shown in Fig. 14, where the emission spectra are plotted with the excitation power as parameter. Whereas in this study, long cavities (2.15 mm) were used and edge emission was measured, in another study, vertical-cavity stimulated emission (i.e., surface emission) from 1.5 urn thick GaN cavities was described; in spite of the large differences in the cavity lengths (1.5 pm and 2 mm, respectively), nearly identical thresholds for vertical and edge emission geometries were obtained.[1761 The near-UV emission line (around 375 mn) shifted to longer wavelengths with increasing pump power, probably due to a heating of the sample at high pump power densities.
Laser
WAVELENGTH
‘9x:.’
W/cm2
( nm>
Figure 14. Emission spectra at room temperature from a GaN layer grown on sapphire with an AIN buffer layer. The sample was excited with different power densities from an N, laser.[17s] (Reprinted by permission of the publisher, Japanese Journal of Applied Physics.)
72
Compound Semiconductors
Besides optical devices, the wide bandgap III-V compounds may find applications in electronic devices. Very recently the first observation of the presence of a two-dimensional electron gas (2DEG) in a wide bandgap GaN/Al,Ga,_a heterojunction was reported.l177l A 2DEG mobility of 834 cm2/Vs was measured in a GaN/Al,,#a,,s7N heterostructure at room temperature. The 2DEG mobility monotonically increased with decreasing temperature and saturated at a value of 2626 cm2/Vs at 77 K; it remained nearly constant for temperatures ranging from 77 to 4.2 K. The twodimensional electron gas was confirmed by the quantum Hall effect. For aluminum compositions in excess of 13 %, however, the peak mobility decreased with increasing aluminum content. These results clearly show the significant progress in MOCVD of wide bandgap III-V compound layers in recent years. The potential of GaN for the realization of carrier injection W laser diodes can be recognized.
4.0
SUMMARY AND FUTURE DIRECTIONS
In the preceding paragraphs, the application of the MOCVD technology to growth of compound semiconductor device structures has been described revealing the tremendous progress that has been made in this growth technology during the last years. Several device applications have been addressed as significant breakthroughs of this growth technology not only for GaAs and InP based materials but also for narrow and wide bandgap compound layers. In GaAs and InP based material systems, excellent uniformity of layer thickness and alloy composition combined with significant improvements in material and device properties make this technology a suitable candidate for commercialization. Besides applications in high speed electronics and long wavelength optical communication, a large commercial market can be recognized in the production of light-emitting diodes and laser diodes in the visible range (550-670 nm). For these applications, the AlGaInP alloys are gaining increasing importance, and for the production of these alloys, the MOCVD technology offers several advantages over other growth technologies. For the growth of the more complex narrow and wide bandgap materials, MOCVD technology has already opened the path to the development of new compound semiconductors, such as AlGaInN, for example. For these III-V and II-VI compounds, both conductivity control and uniformity control over larger substrate areas have been discussed as major
MOWD of Compound Semiconductor Layers
73
challenges and have successfully been attacked already. Sb-containing compounds have been described as a promising III-V alternative to narrow bandgap II-VI compounds. Several examples of device applications have been given in order to demonstrate the powerful potential of this growth technology for growth of these compounds. Based on recent advances in wide bandgap materials, for example, a blue injection current laser fabricated by MOCVD seems to be within reach. In the future, for further development of the MOCVD technology a better basic understanding of the growth process has to be accomplished. This will not only help to improve the material quality in standard multilayer structures but will also be beneficial for the design of new growth precursors. Especially the last years have brought impressive developments in improved and in new precursors, for example, for Al-containing compounds, and also for the future further advances are to be expected. Low temperature growth will be a key issue in order to minimize defect generation in narrow and wide bandgap materials; here, new precursors may also play an important role. Besides these developments in new precursors, new substrate materials have to be explored especially for growth of both narrow and wide bandgap compound layers. After the achievement of excellent thickness and composition control in the vertical direction in GaAs and InP based compounds, the next step now is to obtain this control in the lateral direction for the fabrication of advanced integrated devices. Selective area epitaxy (WE) will gain further importance for the fabrication of monolithically integrated circuits both in GaAs and InP based systems. The results of the last years are quite encouraging already, and significant improvements are to be expected for the future. The development of group III precursors with comparable stability should lead to improved composition uniformity in SAE of ternary and quaternary layers. In another approach, the combination of MOCVD with the closely related growth technology MOMBE may help to solve many problems in SAE. Integrated MOCVD and MOMBE growth technologies may be conceived for realizing advanced integrated devices. The versatility of the MOCVD technology can also be recognized in the advances in depositing superconducting materials, where superconducting transition temperatures above liquid nitrogen temperature have been measured in MOCVD films already. [17*1A combination of MOCVD of superconducting films with MOCVD of standard semiconductor layers shows great promise for modem device applications.
74
Compound Semiconductors
The examples described in this chapter clearly reveal the impressive advances in MOCVD technology for a wide range of compound semiconductor layers from narrow to wide bandgap materials (0.1 to 6 eV) in the last years. For several years, this technology had to duplicate results obtained by the well-developed LPE technology, not only for III-V, but also for II-VI compounds. MOCVD material and devices have proven to be equal or superior to LPE material and devices. Besides the well known advantages of thickness control and uniformity control, MOCVD has been used to grow semiconductor layers which are impossible to grow with LPE like AlGaInP or metastable compounds. In the future, the interaction with the related growth technology MOMBE should be very fruitful in terms of exploring new precursors and developing new techniques such as SAE. It is obvious that MOCVD technology plays a key role in device production today, and it will also have a significant impact on the development of advanced device concepts in the future.
ACKNOWLEDGMENT The author would like to acknowledge the contributions of H. Heinecke, M. Druminski, T. F. Kuech, H. Baumeister, and J. Rieger in stimulating discussions and experimental collaborations.
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80
Compound Semiconductors
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Compound Semiconductors
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(1991)
Molecular
Beam
Epitaxy
Kambiz Alavi
1.0
INTRODUCTION
1.1
Scope of Molecular Beam Epitaxy
Molecular beam epitaxy (MBE) is an ultrahigh vacuum (UHV) atomiclayer by atomic-layer crystal growth technique based on reaction of molecular or atomic beams with a heated crystalline substrate (Fig. 1). MBE is capable of producing extremely high purity and highly crystalline thin films with precise control over composition, doping, and interfaces in the fraction of nanometer range in the growth direction with precise lateral uniformity.111-1131 MBE is widely employed to grow semiconductor, metal, insulator, and ceramic thin films. The precision and control afforded by MBE has brought about remarkable advances in semiconductor thin film technology, by making possible creation of a wide variety of heterostructures with extremely abrupt composition and sharp interfaces, or precisely graded composition, as well as periodic superlattices with periods comparable to interatomic distances. Furthermore, MBE precision control and relatively low growth temperature also allows highly accurate donor and acceptor profiles in the growth direction, be it constant, graded, or planar down to an atomic layer (delta doping), or highly abrupt p-n junctions (Fig. 2).
84
Molecular Beam Epitaxy
Ultra High Vacuum Deposltion on Heated Monocrystalline Substrate
n.oopant
Gallium
Furnace
Figure
1.
Alummum
Precisely Controlled Temperatures and Shutters
Schematic diagram of geometry of molecular beam epitaxy.
85
86
Compound Semiconductors
\5
Substrate and Furnace Temperatures
Materials Flux Control + Surface Kinetics Control
Control of: Material Composltlon Doping Thickness Interfaces Crystal Quality
BAND-GAP ENGINEERING Abrupt or Graded Composition & Doping Homojunctions Heterostructures Planar Doping Multiple Quantum Wells Superlattices: Lattice-Matched Strained-Layer Chirped Doping
Figure 2. Block diagram of principles of MBE leading to bandgap engineering.
The remarkable degree of freedom in materials composition and doping profiles in the sub-nanometer range afforded by MBE directly translates into freedom to tailor bandgaps, electron and hole wavefunctions, effective masses, carrier density of states, and optical transition energies and optical density of states. Because of the fundamental properties of such microscopic and mesoscopic structures, especially prevalence of quantum
Molecular Beam Epitaxy
87
effects due to confinement of electrons, holes and photons, new physics and novel device concepts have emerged.[141-[221Examples of such quantum structures abound, including quantum wells, compositional or doping superlattices, graded composition or chirped superlattices, two-dimensional electron or hole gas, delta doping, and strained layer superlattices. These flexibilities in tailoring the microscopic properties of layered materials is referred to as bandgap engineering,[“1[241band structure engineering,t251wave function engineering,[261 or density of states engineering[271by various authors. An example of the degree of freedom afforded by MBE growth is incorporation of predetermined coherent strains, (compressional and/or tensile), which also leads to the modification of bandgap, effective mass, and the density of states especially in the valence bands.[211 This is achieved by growth of alternating layers with different lattice constants which are thin enough so as to leave the strains unrelaxed. The precision, control, flexibility, and simplicity of MBE, coupled with its ability of real time growth monitoring for understanding and optimization of growth process, has made MBE a powerful and popular technique in two respects: (i) significant improvements in standard semiconductor devices, (ii) enormous activity in conception and realization of a wide variety of novel electronic and optoelectronic devices with superior performance. The precise control of doping and compositional profile in the growth direction, together with reproducibility and lateral uniformity of *l% over a large area (demonstrated over 8 inch diameter platens for simultaneous growth on three 4-inch diameter wafers) has made MBE a technology for consumer electronics. New structures with new transport and optical properties have been achieved which are remarkably rich in physics, materials science, and technological properties and has made possible the realization of many new semiconductor high speed optoelectronic and electron devices and circuits .[281-[3 ll The many remarkable achievements of MBE range from extremely high speed or low noise transistors and integrated circuits, to extremely low threshold diode lasers and femtosecond optoelectronic switches, to the discovery of a new quantum fluid whose elementary excitations possess fractional fundamental charge. Applications range widely from lasers for CD players (3-5 million/month) and fiber-optics communications, to measurement of fundamental constants and resistance standards. MBE is truly a multifaceted and multidisciplinary endeavor fostering and benefiting from interaction among various branches of science and technology for its development and evolution, while contributing to science and technology by
88
Compound Semiconductors
allowing the control and freedom to create an endless variety of multilayer thin film crystals with tailorable properties. 1.2
Major Factors in the Initial Development of MBE
The term molecular beam describes a unidirectional kinematic flow of atoms or molecules with no collisions among them as opposed to a viscous fluid-like flow. The term epitaxy is composed of the Greek words epi meaning akin or upon, and taxis meaning arrangement or order. Epitaxy refers to ordered growth of one crystalline layer on another crystalline layer, with the same (or related) crystal arrangement. Consequently, a critical issue in MBE is the surface condition of the starting crystal (the substrate) and the subsequent layers as they are being grown. Molecular beam epitaxy is a form of vacuum evaporation technique, however it distinguishes itself from other evaporation crystal growth methods by its precise control of beam fluxes using collimated beams and rapid flux switching, more precise control of growth conditions, and the UHV environment which ensures high purity. Most importantly, it allows real time in-situ monitoring and control during the substrate preparation andfilm growth to ensure best conditions for stoichiometry and epitaxy. Excellent reviews of the prehistory and early history of MBE is given in the authoritative accounts by Cho and Arthurt and more recently by Cho.t13j An important feature of these references is that they describe the work that preceded MBE and articulate how MBE differs from the earlier evaporation techniques. There were two major factors in the initial development of molecular beam epitaxy. First was the application of in-situ real time surface analysis to the understanding and optimization of processes involved in the substrate preparation and epitaxial growth. Second was the conscious and sustained focus on applying and refining the MBE growth system and technique for successful realization of epitaxial heterostructures for various electronic and optoelectronic devices, which put a much more stringent requirement on the quality of the films beyond the question of stoichiometry and epitaxy. In late 196Os, Arthur at Bell Laboratories used a pulsed beam mass spectrometry technique to investigate the kinetics of reaction of collimated beams of As, and Ga on heated GaAs { 11 l} surfaces in IJHV.[~~] For T < 750 K, no Ga desorption was observed, with sticking coefficient of Ga being unity. Above 500 K, the sticking coefficient of As2, in contrast, was virtually zero unless excess Ga was present on the surface, in which case the sticking coefficient of As, was proportional to Ga coverage, increasing to
Molecular Beam Epitaxy
89
unity for full Ga coverage. Arthur concluded that the growth was kinetically controlled and stoichiometry could be achieved by providing sufficiently greater flux of As, to ensure that all the Ga reacted, with the excess As simply evaporating. 1331This observation formed the basis for epitaxial growth. Cho at Bell Laboratories used reflection high energy diffraction @HEED) in combination with collimated beams in UHV for the first time in 1969,1331and extensively thereafter, 1341-1371 to investigate the outermost layers of the substrate and the deposited films under different temperature and flux conditions. This was out of the conviction that in-situ real-time monitoring was critical for the establishment of proper epitaxial conditions to reproducibly grow good quality films, and that RHBED provided the ideal geometry for simultaneous growth and monitoring. Among his many important observations were oxide desorption from the substrate and subsequent surface reconstruction of the cleaned substrates, changes in surface structure and reconstruction as a function of substrate temperature and beam fluxes, changes of surface morphology and surface smoothing as a function of thickness of epilayer, and transition from polycrystalline to single crystalline for room-temperature-deposited films as a function of annealing time, temperature, and film thickness. Using systematic RHEED measurements, Cho established phase diagrams for transition from As-stabilized to Ga-stabilized surfaces as a function of V/III flux ratio and substrate temperature. Quite significantly he made the observation that certain properties of the deposited films depend significantly on the surface reconstruction during the growth.1381-13glCho observed the evolution of RHEED patterns from short spotty streaks to long narrow streaks as the growth proceeded. Pt-C replica of the surfaces at various stages of the growth showed that this corresponded to continued smoothing as the growth proceeds. 13’1 A step-growth model is consistent with these results since surface asperities would be excellent step sources. The term molecular beam epifaxy was used for the first time in 1970.1401Vigorous effort was soon spearheaded by Cho to apply and refine the MBE system and growth technique in the electronic and optoelectronic device arena. The major steps included successful incorporation of n- and p-type dopants in MBE GaAs,138113g1141j growth and optical evaluation of AlXGa,_.Js14011421 demonstrating optical absorption features that were as well defined as in LPE-grown samples, and growth of multilayer structures.14011431 These led to the first demonstration of an MBE-grown double heterostructure laser,144lvoltage varactor1451and IMPATT diode,1461all in
90
Compound Semiconductors
1974. In the early stage, MBE was employed to pursue optical and electronic devices based on quantum effects arising from confinement of electrons within dimensions comparable to the deBroglie wavelength. At IBM, superlattices were successfully grownt471[481 and resonant tunneling in double barriers observed.[4g1 Electron transport in a superlattice by Esaki and Chang of IBM,tSol and optical transitions in quantum wells by Dingle, Wiegmann and Henry of Bell Laboratoriest5il were reported in 1974. Further work on pulsed mass spectrometry techniquet521 and the elegant modulated beam mass spectrometry work of Foxon and Joyce and coworkers gave better understanding of the surface kinetic processes in the MBE growth.[531-1551 The important point is that to this date the original major factors, namely in-situ surface characterization and quest for improved and novel materials structures and devices, have remained the driving forces for the development and evolution of MBE. Significant contributions have come from many scientists and engineers internationally. 1.3
MBE Reference Material
Soon after the original work at Bell Laboratories, other research laboratories followed with important contributions. A number of articles from these various laboratories review the development and status of MBE prior to 1983 .t11-161 Two excellent books present a collection of chapters by various authorities providing pedagogical and comprehensive treatment of historical background, fundamental aspects of MBE growth, the technology of MBE systems, MBE growth and characterization of various materials systems and heterostructures, and application of MBE to devices and fundamental physics. t81tgl A more recent book with a large bibliography gives a comprehensive treatment of MBE, with special emphasis on three themes: MBE equipment, physics of growth, and characterization method~.[~~lA chronological account of principal achievements in MBE through 1983 appears in the appendix of the “Introduction” chapter of Ref. 9. A more detailed review appears in Ch. 17 of the same book.Isal A detailed bibliography has been compiled for III-V compound MBE.1571A comprehensive account of Si MBE and its application are presented in a recent two volume book which includes an extensive bibliography through 1985.1S81 More recent review chapters give an account of MBE technology with emphasis ongrowthmechanismandcharacterization ofIII-Vcompounds.tlol[lll
Molecular Beam Epitaxy
91
An annotated collection of key papers on molecular beam epitaxy spanning the last twenty-five years has been recently prepared by Cho where the criteria for selection was (i), they started a new area of research, and (ii) the sustained and successful work of the author aroused a large following.li31 Molecular beam epitaxy from materials science and thermodynamics point of view is presented by Tsao. Is91Invaluable information regarding progress in MBE growth, apparatus, materials characterization, novel physics, and device applications can be found in various volumes on proceedings of MBE workshops and international conferences,l5gl and NATO Advanced Science Institutes Series (Ser. B, and Ser. E) books.~s~~16~~1gl~25~~611-~631 In particular, Ref. 6 1 provides the latest information on the interface properties at the sub-nanometer (atomic) scale as related to growth conditions. A recent development in MBE is the use of gas sources to generate the beams. This is reviewed in a recent book.l64l 1.4
Synopsis
In this chapter, we highlight the important features of MBE, techniques for investigating the growth mechanism, system components, and their function with emphasis on in-situ real-time monitoring and control, growth mechanisms, growth procedures, ex-situ materials analysis, and the main ingredients which go into bandgap or band structure engineering. The emphasis is on the III-V compounds grown by conventional (elemental) MBE because of their technological importance and maturity of the understanding of growth issues. Brief discussions on other materials systems and variations of MBE are included.
2.0
IMPORTANT FEATURES OF MBE
Molecular beam epitaxy is unique in that it is a growth technique performed in UHV and is based on reaction of atomic and/or molecular beams with a crystalline surface relying on kinetic processes such as adsorption, desorption, dissociation, migration, reaction, and incorporation. These factors make MBE a highly controllable and versatile technique allowing the growth process itself to be probed, understood, and hence, optimized and controlled on a submonolayer scale.
92
Compound Semiconductors
2.1
UHV Environment
and Ultra-High Purity Source Material
The UHV environment ensures high purity and allows extremely clean surfaces. A 10mg torr pressure could be achieved in the early 1970s by incorporating liquid nitrogen cooled shrouds around the sources together with the UHV pumps. This is equivalent to about 10e3monolayer per second (ML/s) impingement rate of background gases at the substrate compared to 1 ML/s typical growth rates. Fortunately, most of background gases which act as contan&rants have a much smaller partial pressures and have sticking coefficients much less than unity. In modern MBE systems, base pressures of lo-lo to lo-” torr are normally achieved after bakeout. The residual gases are mainly Hz and N,, which are often benign, and a small amount of H,O, 02, CO, and CO, which are often contaminants, but have partial pressures as low as lo-r4 torr. Source materials used in conventional MBE are of extreme purity with contaminant concentrations of the order of few parts per billion. Extremely low impurity concentration in the low 1013cmm3in MBE GaAs have been reported by Chand et al.[65l Pfiffer et al. have achieved extremely high electron mobilities, in excess of lo7 cm2/Vs (below 1.5 K), in modulation-doped AlGaAs/GaAs structures grown by conventional MBE using elemental sources[661(Fig. 3). The GaAs impurity concentration is estimated to be less than 2 x 1013cmm3.This is the bigbest mobility in any materials system by any growth method. This can be attributed to extremely high purity solid sources, extreme care to achieve the best UHV environment with extensive cryopumping and bakeout, and the use of superlattice buffer layer, planar doping, and interrupted growth, all features accessible by MBE growth. With the typical growth rate of one monolayer per second (1 ML/s) and 2.83 A per ML, the 2 x 1013 ems3 impurity is equivalent to less than 6 x 1O5impurity atoms per cm2 per second sticking on the growing surface. The sheet atomic density on GaAs (001) surface is 6.25 x 1014per cm2. This means that it takes about log seconds for one monolayer of contaminants to stick to the surface of the clean substrate. Impurity levels of no more than a few times 1014crnm3can be achieved routinely with a reasonable amount of care in conventional MBE. The bigb purity is important not only for optical and electrical properties of the films but also from crystal growth point of view since surface contamination has adverse effects on the growth process itself and on the resultant morphology.
Molecular Beam Epitaxy
93
(4
D.2
0.5
I
2
5
10 20
Tcmpcmturc
SO IO0
f(K)
2 DIMENSIONAL
Cr OOPEO
GaAs
SUBSTRATE
Fire 3. An example of achievement in elemental source MBE, as exempliIkd by high mobility two-dimensional electron gas obtained at the interface of selectively doped GaAs/AlGaAs heterostructures: (a) mobility vs. temperature over the years by various authors (open circles), (b) epitaxial structure corresponding to highest mobility obtained. (Figures a and 6 are adapted from Ref. 66.) It is interesting to note that in more than one instant experimental results exceeded those predicted by theory at the time, necessitating revisions of the theory.
94
Compound Semiconductors
2.2
In-Situ Real-Time Monitoring and Control on a Sub-Monolayer Scale
The UHV growth environment allows installation of surface analytic instrnments directly in the growth chamber. This can be utilized in two crucial ways: first, to examine and optimally prepare the substrate before the growth, and second, to monitor and control the growth process on a submonolayer scale in real time as a function of beam fluxes, flux interruptions, substrate temperature, thickness, annealing, and the underlying surface composition and condition. The growth is kinetically controlled and proceeds at a slow rate (typically 1 ML/s). This leads to the understanding and real time control of epitaxial growth mechanism, growth rate, composition, and epilayer and interface morphology. This is an extremely significant advantage of the MBE. In the following, we list the most important of these UHV in-situ techniques and their role in monitoring and control of the MBE process, with the details deferred to Sets. 5-8. 1. Modulated beam mass spectrometry (MBA@) is used for identification of desorbed species, desorption rate, sticking coefficients, order of chemical reactions, thermal accommodation coefficients, surface lifetimes, and surface binding energies. W1Wl~WlWl This technique is somewhat elaborate and specialized and is not used on a routine basis. (See Sec. 6.1.) 2. Desorption mass spectroscopy can be used routinely during the growth to monitor desorbed species and can be used to monitor and control growth rate and composition in a closed loop feedback system even with substrate rotation.[681-[711 (See Sec. 6.2.) 3. Reflection high energy electron diffraction @HEED) is used for observation of oxide desorption, surface reconstruction, surface coverage, establishment of phase diagram, observation of surface steps, domains, disorder, surface smoothing, and effects associated with surface rnisorientation.[331-[361[721-[751 (See Sec. 5 .) 4. RHEED intensity oscillations are used for the observation of the time evolution of growth of each monolayer, roughening and smoothing during monolayer growth, surface mobility of adsorbed atoms and molecules, and growth mechanism and kinetics.[621[761-[861 (See Sec. 5.3.)
Molecular Beam Epitaxy
95
5. Auger electron spectroscopy is used for chemical identification of surface species especially at different stages of oxide desorption. This technique requires more elaborate arrangements and is not used routinely in every growth. However, it is a powerful technique for developing optimal surface preparation techniques for new substrate materials.1871+901(See Sec. 7.0.) 6. Scanning tunneling microscopy and atomic force spectroscopy are powerful novel techniques for atomistic observation and determination of surface reconstruction as a function of growth, surface preparation, and growth conditions.1881-1921 Surface mconsuuction has profound effects on dopant incorporation and optical and transport properties of epitaxial layers and interfaces. These elegant techniques are specialized and are not used in typical MBE studies/ growths. (See Sec. 5.2.) 7. Optical characterizations. These are powerful techniques for real time monitoring and control of substrate temperature, growth rate, composition, thickness, and surf&e morphology. Optical characterization equipment can be installed on viewports on the periphery of the growth chamber and either view the radiation from the substrate (pyrometry, pyrometric interferometry, IR transmission spectroscopy), or monitor the optical response of the wafer to an external light source (ellipsometry, reflectometry, interferometry, photoluminescence). (See Sec. 8.0.) 2.3
Important Features of the MBE Growth Mechanism
In addition to the extensive in-situ, real-time surface analysis techniques, theoretical investigations of the growth process have been pursued in two directions leading to better understanding of the growth process and doping and impurity incorporation. First are atomic scale modeling of surface processes during the growthl%l using Monte-Carlo simulations,18611g~lg81molecular dynamicslWl11ooland continuum equations of motion.l%l Second are thermodynamic investigations of the growth process and impuThese investigations are complerity and dopant incorporation. 15gl11011 mented by a variety of post-growth measurements which are categorized as
96
Compound Semiconductors
structural, electrical, and optical, which provide additional information on the various properties of the epilayers and their interfaces. These can be correlated with the growth conditions and the observation made during the growth using the in-situ real-time techniques. This has made MBE perhaps the best understood and controlled epitaxy method. A list of important features of MBE growth follows: 1. Epitaxial growth proceeds monolayer by monolayer in a two dimensional manner at relatively low growth rates, typically 0.1 to 1.5 ML/s. Step-growth or 2-D nucleation and islaudgrowth prevails over 3-D nucleation growth. Surface smoothing takes advantage of surface migration and incorporation at step edges. The sides of any nucleated island serve as new stepedges for the incorporation of newly arriving elements, leading to two dimensional growth. 2. Growth rate, composition, and doping concentration is determined mainly by arrival rate of different species in collimated beams and can be precisely controlled during the growth allowing precisely controlled, abrupt or graded composition and doping profile in the growth direction. 3. Use of growth interruption and relatively low temperature growth allows planar doping with extremely high sheet doping concentrations (Si = 1013crne2in GaAs). 4. Multilayer structures with smooth, abrupt, interfaces can be grown because:
near-ideal
a. The constituent atoms arrive at the surface as atomic or molecular beams without collision with other atoms or molecules, as opposed to viscous or diffusive flow. Growth proceeds by reaction of these species with the surface. Those that do not get incorporated leave the surface without interacting with the arriving beams and do not linger over the surface. Therefore, no stagnant layer is involved. b. Shutters can be opened and closed much faster (CO.1 set) than the time it takes to grow one monolayer (typically 1 set).
Molecular Beam Epitaxy
97
c. Normal substrate temperature is low enough that layer interdifision can be negligible (e.g., for GaAs, typical growth temperature is between 550-620°C). d. Growth mechanism is based on kinetic processes and is two dimensional. e. RHEED intensity oscillation monitoring during the growth, together with shutter sequencing, flux adjustment, and substrate temperature adjustment can be applied to ensure exact monolayer material deposition and incorporation. The above can also be used to ensures optimal surface migration and incorporation for surface smoothing on one monolayer scale (phase-locked epitaxy, migration enhanced epitaxy, atomic layer epitaxy). 5. For MBE growth of III-V compounds using elemental atomic or molecular beams, epitaxial growth can be achieved over a wide range of substrate temperatures. The growth rate and composition are independent of substrate temperature over a wide range and are determined solely by group III element fluxes (sticking coefficient near unity), provided sufficient group V flux is present. The incorporation of the group V element is self regulatory and ensures stoichiometry since the excess desorbs. For high substrate temperatures and for mixed group V compounds, this picture is somewhat modified. 2.4
In-Situ Processing and Lateral Patterning
Because of the beam nature of material delivery, removable proximity shadow masking can be performed to grow two dimensional patterns or buried structures. Growth on a crystalline substrates with amorphous dielectric patterns may also be area selective since nucleation and growth on the oxide region may be amorphous or extremely slow. In case of MOMBE (introduced below), a deposited mask may be chosen (such as Si or SiO,) which does not catalyze the decomposition of the metalorganic compounds, leading to no material deposition in that area.l64l Shadow masking can be utilized along with laterally selective growth for patterning. Since MBE is a UHV growth technique, it is natural to merge the growth of epitaxial
98
Compound Semiconductors
layers with UHV processing to allow the growth and fabrication of 3-D single devices, as well as integration of optoelectronic devices, all without breaking the vacuum. These processing techniques include metallization and plasma deposition and etching, as well as more complicated maskless writing by focused ion beams and implantations by focused ion beams. Techniques such as chemical beam assisted ion beam milling may be used to provide etched mirrors for lasers which can also be integrated through buffer chambers and interlocks to insure integrity of the UHV chambers during sample transport. 2.5
Variations on the Theme of MBE
As the success of MBE over the years became established, a number of variations on the original theme were employed to extend its applicability to new materials, or to simplify new aspects of the technique. The most basic and most common form of MBE uses elemental beams delivered from heated solid or liquid sources. This is variously referred to as conventional MBE, elemental MBE, condensed phase MBE, or simply MBE. Gas source MBE (GSMBE) is a generic name used when one or more of the beams are derived from a gas source. The simplest of GSMBE’s is hydride MBE, where As and P are derived from cracked ASH, and PH, at the source end and are delivered to the substrate as elemental dimeric or monomeric beams. In this sense, hydride MBE is very similar to conventional MBE except that the background pressure is higher. In metalorganic MBE (MOMBE) or Chemical Beam Epitaxy (CBE), the metallic elements are delivered to the substrate as volatile organometallic compounds, relying on the substrate thermal energy for decomposition and release of the metallic element. A variety of approaches are possible in this method, namely using metalorganits for some of the beams (e.g., for Ga and In), hydrides for others (e.g., ASH,), and elemental for yet others (e.g., Be for p-doping), or all fluxes can be from gas sources. The use of the word chemical in this conjunction is to emphasize that the constituents are delivered to the substrate in chemical beams and depend on surface chemical reactions to release the element before incorporation. It is important to emphasize that although the background pressure can be orders of magnitude higher in Gas Source MBE vs. conventional MBE, nevertheless, the material is delivered as collisionless kinematic beams, as opposed to the viscous flow in MOCVD.
Molecular Beam Epitaxy 3.0
99
MBE SYSTEM CONFIGURATION
MBE systems normally consist of three bakeable stainless steel UHV chambers: the load lock or entry/exit chamber, the growth chamber, and the buffer chamber which connects the two (Fig. 4). Other UHV chambers for analytic studies or processing can be connected in series or parallel via the buffer chamber. The various chambers are isolated from each other using UHV swing gate valves. The substrates are mounted on substrate blocks made of refractory metals such as molybdenum (MO) (Fig. 5) and are transferred from chamber to chamber using transfer rods, which are moved using magnetic coupling from outside, or wobble sticks using flexible bellows. Several substrate blocks could be installed on cassettes or trolleys or other multiwafer stations (Fig. 5).
Figure 4. Schematic drawing of an ME3E system (Varian Gen Il) showing load lock, preparation/analysis and growth chambers and vacuum control cabinet. Other electrical instrumentation and control cabinets and data acquisition/control and computer are not shown. (Courtey EPI.)
100
Figure
Compound
5.
Semiconductors
Wafer mounting
blocks and troUey.
Left block shows a 2 inch wafer (non-In
bonded, middle block contains an Mo plate for In bonding, inch diameter wafer, non-In bonded.
and right block contains a 3
(Courtesy EPI.)
The load lock or entry/exit chamber allows the introduction, pump down, preheating, and storage of substrates prior to growth, and their removal after the growth. The fore-pumping of the load lock is accomplished using liquid nitrogen sorption pumps and the vacuum is generated and maintained using closed cycle He cryopumps and/or ion pumps. The introduction of a load lock to the early MBE systemsgreatly improved the throughput and the purity of the growth chamber, since the load lock is the only chamber exposedto the atmosphereduring wafer loading and unloading. This leaves the growth chamber under UHV for extended periods of time, only to be openedoccasionally for source loading or repair . In modem MBE systems,a buffer chamberconnectsthe load lock and growth chamber to each other and to other processing and analysis chambers. This chamber is usually equipped with heaters for baking the substrates. In someMBE systems,this chamber also housessomeanalysis equipment, usually Auger electron spectroscopy for surface composition
Molecular Beam Epitaxy 101 analysis, and in this case, it is called the preparation/analysis chamber. Depth profiling could also be accomplished by sputtering in that chamber using Ar through a leak valve. Other chambers connected to the buffer chambers include those for metallization using ion beam sputtering, evaporation, focused ion beam for area selective deposition, reactive ion beam etching, chemical-assisted ion beam etching, or electron cyclotron resonance (ECR) plasma source for etching or deposition of dielectrics such as silicon nitride. The ECR can also be used for pre-cleaning the surface of the substrate prior to the growth. This method is much gentler and produces less heat on the substrate compared to sputtering, leaving the surface with much less damage. In some cases, two or more growth chambers are connected for the growth of incompatible materials system such as III-V and II-VI compounds with transition chambers equipped with proper buffering to prevent cross-doping of III-V elements with II or VI materials and vice versa. The swing gate seal is usually a high temperature elastomers such as Viton since gates with metal seals require higher maintenance. However, it is important that those seals that are used to secure the swing mechanism to the housing sleeve be metallic, since repeated baking of the system will eventually cause elastomer seals under compression to leak. 4.0
THE GROWTH CHAMBER COMPONENTS
The key components most commonly included in the MBE growth chamber are (see Fig. 6): 1. Vacuum pumping system to generate, maintain, and monitor an ultra high vacuum (UHV) environment. 2. Beam generators and controllers with fast shutters or valves capable of generating atomic or molecular beams with precisely controlled fluxes. These are arranged on a source flange and are aimed towards the substrate. 3. Substrate holder equipped with (a) heater and thermocouple to generate, maintain and monitor temperatures sufficient for epitaxy on atomically clean substrate, (b) continuous azimuthal rotation capability for lateral uniformity (since the beams arrive at different angles on the substrate), and (c) a manipulator to position the substrate to face towards the transfer or the growth position.
102 Compound Semiconductors 4. Ionization gauges for beam flux measurement and for background pressure monitoring. 5. In-situ characterization equipment for the real-time, in-situ monitoring, optimization, and control ofthe growth. Typically these include: (a) RHEED measurement system, and (b) quadrupole mass spectrometer for monitoring of leaks and contaminants or for mass spectrometry of desorbed species from the substrate at various stages of substrate preparation and growth 6. Optical viewports for installation of optical characterization equipment on the periphery of the growth chamber for realtime monitoring of the growth. Most common is an optical pyrometer used mainly for substrate temperature measurement. In the following subsections, details of items (l)-(4) are given. Sections 5-8 deal with items (5) and (6). LIQUID NITROGEN COOLED SHROUDS
HEED GUN
/
MAIN SHUTTER
?/I
EFFUSlOil CELL SHUTTERS
/=
FLUORESCEN? SCREEN
i/i TO VA&ABLE SPEED MOTOR ANDSUBSTRATE HEATER SUPPLY
Figure 6. Schematic of a typical MBE growth chamber (top view). AT&T Bell Laboratories.)
L6AD LOCK
(Courksy A. I’. Cho,
Molecular Beam Epitaxy 4.1
103
The UHV System
The growth chamber is the most critical element with the highest demand for UHV generation. In solid source MBE, the pumping of the growth chamber is accomplished by large capacity ion pumps and periodic Ti sublimation pumping. To achieve the best base pressure after the growth chamber is opened for source loading or maintenance, MBE systems are usually baked extensively at 180°C prior to growth. After the bakeout and cool down to room temperature, the pressure in the total system can reach as low as 2 x lo-” torr which is mostly Hz and often is benign. When high volume pumping is required in GSMBE (hydride, MOMBE or CBE), turbopumps, cryopumps, and even properly trapped diffusion pumps, are employed. For the majority of MBE systems, diffusion pumps are avoided. There are three regions in the growth chamber which have extensive cryoshrouds using liquid nitrogen or other coolants: the area surrounding each individual beam t$nace (when high temperature sources are used), the area surrounding the substrate station, and the area or the sump surrounding the Ti sublimation pump. The purpose of the cryoshrouds around the sources is to prevent excessive heating of the chamber, especially around the hot furnaces which can otherwise lead to thermal crosstalk and desorption of unwanted residual contaminant molecules. The cooling around the substrate is to condense residual gases, especially those desorbed by the substrate heater, and to provide heat dissipation. The combination of vacuum pumps and cryoshrouds keeps the partial pressure of contaminating gas molecules such as CO, CO,, and 0, or other oxygen-containing molecules below lo-l4 torr during the growth, even though the operating pressure of the growth chamber is much higher than the base pressure. For conventional solid source MBE, the base pressure is about 10mgtorr due to scattered beam species and excess group V flux. In CBE, it can be as high as 1O4torr due to the carrier gases and pyrolysis of the alkyls. Even at these pressures, the beam nature of molecules is preserved. In preparation for the growth, the cryoshrouds are normally filled with liquid nitrogen several hours before the furnace temperatures are raised. They are kept cold until the furnace temperatures are reduced after the completion of the growth. When liquid nitrogen costs are of no concern, it is preferred to continuously trap the shrouds and allow the furnaces to outgas at about 200°C below growth temperature while the growth chamber is idle overnight. This has several advantages: it helps the source material to outgas continuously; it prevents the adsorbed residual gases from desorbing
104
Compound Semiconductors
during the idle time; it saves time during the day for growth; and it avoids the risk of cracking PBN crucibles containing Al during repeated cycles from solid to liquid state. Al wets PBN and shrinks upon solidification, creating stresses high enough to crack the crucible. To avoid this, one must slowly raise and lower the Al crucible temperature while it is close to the melting temperature. Continuous trapping also allows overnight outgassing of the substrate and the substrate heater for reduction of residual impurity gasses. It is preferred that the liquid nitrogen be gravity fed in parallel to each shroud in the MBE growth chamber from a phase separator (open) reservoir above the growth chamber. It should be returned to the reservoir, through vacuum jacketed pipes. This ensures a steady flow of the liquid (containing no gas and with minimal turbulence) into each shroud, resulting in a constant low temperature on the shrouds. The return liquid/gas mixture is then phase-separated in the reservoir, and the liquid portion recycled. Temperature fluctuations in the shrouds are believed to cause sporadic release of adsorbed residual gases, which may compromise the epilayer purity. A less expensive alternative to LN, is the use of glycol/water mixture recirculated through a refrigeration station. However, water can in the long run cause corrosion of stainless steel and result in leaks. Some systems use water cooling in conjunction with liquid nitrogen around the hot furnaces or the substrate heating station. Beside the danger of corrosion, there is also a risk of water freezing in case the water pump fails while the liquid nitrogen is flowing. A burst can result in a water leak in the growth chamber. 4.2
Beam Generation
In its most basic form, the growth chamber of MBE consists of a UHV chamber fitted with several independent material sources which generate beams aimed towards a crystalline substrate mounted on a heated holder. There are generally two different types of beams leading to two somewhat different methods of material delivery to the substrate, and some differences in the details of the growth mechanism. The first type, which can be called physical beams, uses a physical transport (or deposition) technique, in which elemental atomic or molecular beams are generated from elemental sources or from polycrystalline or amorphous sources by local high temperature at the source (evaporation, sublimation, or decomposition). The second method of material delivery to the substrate is through use of chemical beams (chemical transport or deposition) in which
Molecular Beam Epitaxy
105
the element of interest is a part of a volatile chemical species delivered at lower temperatures to the substrate in a chemical beam (CBE or MOMBE). In both cases, the distance between the sources and the substrate is smaller than the mean free path of the material particles traveling towards the substrate to ensure collisionless beam nature of the material flux as opposed to viscous or diffusive flow. Those that leave the substrate surface do not interact with the arriving beams. The background pressure in the growth chamber during the growth is higher than the base pressure but is maintained sufficiently low to ensure these points. The beam fluxes are independently controlled with high precision and determine the composition, the growth rate, and the doping of the layers as they are grown. The beams can be turned on and off independently, using high speed shutters or mass flow controllers at the source end. Physical Beams. Physical beam delivery can be achieved by a number of means: (i) melting and evaporation of solid or liquid elements (e.g., Ga, Al, In, Sb, Hg) in crucibles heated by radiation from resistive heaters; (ii) sublimation of solid elemental material in crucibles heated by radiation from resistive heaters (e.g., As, or Si and Be for doping of III-V compounds); (iii) ion beam bombardment (e.g., Si, Ga, Al, refractory metals); (iv) direct current heating through the material acting as a resistor (Si, C dopants for III-V compounds); (v) high temperature cracking of elemental molecules (e.g., As, from cracking of As,); (vi) high temperature cracking of hydrides (e.g., obtain arsenic and phosphorus beams from high temperature cracking of ASH, and PH,; (vii) congruent or noncongment evaporation of binary material (e.g., GaAs, CdTe). Conventional Elemental Sources. In these sources, the beam generator is an effusion cell or oven, which is a compromise between Langmuir and Knudsen cells (Fig. 7). It consists of a furnace and a crucible containing the source material. The crucible is usually made of high purity pyrolytic boron nitride (PBN) usually conical (or trumpet) shaped, designed to give maximal uniformity profile beams at the substrate (usually 2, 3, or 4” diameter wafers located at a distance of about 10 to 20 cm). The metals used in the furnace are high purity, low reactivity, refractory metals. The furnace heaters, typically, are Ta wires going up and down in a cylinder which surrounds the crucible. Extensive Ta foil shields are used to reduce thermal leak to the surrounding. The insulators are mostly PBN in the hot region. The temperature of the crucible is usually measured using WiRe 5%-W/Re 26% junction thermocouples touching the bottom of the crucible with spring loading to ensure secure contact. The furnace is assembled on a
106
Compound Semiconductors
UHV conflat flange, with the power and thermocouple leads coming through the flange using ceramic isolators with metal to ceramic seals. Effusion cells are designed to withstand temperatures as high as 1400°C, with minimal outgassing of contaminants. For a knace with uniform heater winding, a negative temperature gradient towards the opening of the crucible is usually encountered due to the larger heat loss at the opening. In case of Ga, this can lead to the condensation of droplets near the lip of the crucible. Droplets can lead to flux variations and surface defects. In new furnace designs, this situation has been drastically reduced by either increasing the density of heater winding near the top of the crucible or by making two heater zones, independently controlled Both short term and long term temperature stability of the crucibles is of utmost importance for composition and growth rate control, and good MBE furnaces meet this requirement. Using high precision controllers, short term stability within 0. l°C and long term stability of better than a degree is achieved. In some cases, one can obtain elemental beams from evaporation of binary compounds. For example, in the early days of MBE, high fluxes of As, were generated by high temperature evaporation of GaAs in ovens of the type mentioned above. This beam was accompanied by a much smaller flux of Ga (-15%) due to noncongruent evaporation. A similar situation can also be achieved with CdTe.
Figure 7. Conventional high temperature effusion cell consisting of a furnace and a PBN crucible. (From ReJ 9.)
Molecular Beam Epitaxy
107
High Temperature Crackers. Arsenic and phosphorus sublime at low temperatures (<3OO”C) to produce a sufficiently large flux for normal MBE growth rates. The low temperature sublimation produces tetramers (As4 or P4) and negligible amount of dimers (As2 or Pz). However, since the vapor pressure is high at such low temperatures it is next to impossible to alter the arsenic or phosphorus fluxes or their ratios in an abrupt or even in a reasonably fast manner. There is also significant leakage around the conventional shutters when closed. These memory effects are a detriment to the growth of sharp interfaces or controlled compositions in the growth of the all-important III-V compound containing both As and P. In some applications involving As alone, it may be preferred to use dimers and not tetramers (see Sec. 6.1). This has prompted the use of high temperature crackers to resolve these problem in two different fashions as described below. Arsine andphosphine Crackers. As, and P, can be obtained by high temperature cracking of ASH, and PH, gases at high temperature (about 900°C, well above the substrate temperature).11021-[1051 These crackers are normally equipped with high precision mass flow controllers to obtain precise fluxes of As, or P, with precise flux ratios and with the capability to turn the beams on and off with negligible memory effect. Rapid switching is crucial for growing sharp interfaces in III-V compounds containing both As and P. In addition, ASH, and PH, ensure an inexhaustible source for arsenic and phosphorus. As a drawback, large quantities of H2 are generated in the growth chamber, raising the growth pressure to 1OS5torr which puts a large demand on the vacuum pumps. However, this pressure is sufficiently low to preserve the beam nature of the various species impinging on the substrate. The growth mechanism, thus, is identical to conventional MBE, and the growth rates do not appreciably depend on the substrate temperature. The presence of hydrogen is believed to help reduce undesirable contamination by oxygen and carbon in the epilayers. tio41 This approach does necessitate major precautionary measures for handling the extremely toxic hydrides. It is important to note that although the hydrides are considered chemical species, they are not volatile and the substrate temperature is not sufficient to crack them. As a result, cracking is accomplished at the source end and the group V elements are delivered as elemental beams. Therefore, one can argue that hydride source MBE is quite close to conventional MBE as far as the growth mechanism at the substrate is concerned.
108
Compound Semiconductors
Solid Source Valved Crackers. These crackers have evolved from earlier two zone furnaces consisting of low temperature sublimation and high temperature cracker zone (Fig. 8). The valved crackers consist of a large capacity low temperature sublimation cell containing pure As or P separated by a high precision needle valve from a high temperature high efficiency cracker zone which points towards the substrate (Fig. 9). The low and the high temperature regions are thermally isolated. The cracker can almost completely convert the tetramers to As, or P, and the needle valve is capable of fast and precise control and switching of Asz and P, fluxes (within 1 second). This attractive alternative has the advantage that no toxic gas handling is involved and no extra pumping is required since no hydrogen is generated. The approach is expected to gain in popularity as an extension of conventional MBE. Using such solid source valved crackers, rapid and precisely controllable arsenic flux switching and grading has been used in composition control of AlGaAs,r711and ~GaI_&.[1061 The details are presented in Sec. 6.2. Using solid source valved crackers, high quality and A~,&I,,~P~~~~I have been reported. Gao.Jno,,P and Aso.,Itb.,P,[ 1071[1081 Using two solid source valved crackers, GaJn,,5P/GaAs heterostructures,[l loI and strained InAsP/J.nPtl 111quantum wells have been demonstrated.
Figure 8. Conventional high temperature As cracker effusion cell consisting temperature sublimation and high temperature cracking zone. (From ReJ: 9.)
of a low
Molecular Beam Epitaxy
109
A Cracking Zone and Conductance Tube B Mounting Flange C
Bulk Evaporator
D Back flange
D
E Valve Actuator
Figure 9. Schematic
of a high capacity solid source valved cracker.
(Courtesy EPZ.)
Ion Beam Sources. An alternative method to high temperature evaporation or sublimation is the use of ion beams to locally heat a supply of elemental material to generate the require beams with sufficient flux. This is normally used in Si MBE. It has also been explored in MBE growth of IIIV compounds.11121 An advantage of this method is faster change of flux since the source material is heated locally and there is less thermal inertia. A disadvantage is possible accidental contamination of the chamber in case of failure of the beam directing mechanism. Conventional Dopant Sources. The conventional dopants are solid materials. For example, in III-V MBE Si is used for n-type and Be for ptype doping, both of which sublime at high temperatures. Since much smaller fluxes are needed compared to the constituent materials, the dopants are evaporated from smaller crucibles and smaller furnace are employed. This helps reduce the thermal load and gives better control for quicker ramping of the fluxes. Filament Dopant Sources. An alternative approach for evaporation of dopants from elemental sources is to use evaporation from filament sources by directly passing a current through the dopant filament. In this manner, a faster ramping of the dopant profile can be achieved since the filament has a small thermal mass compared to conventional furnaces. Carbon is an interesting alternative to Be for p-doping of III-V compounds since it has a smaller diffusion coefficient than Be and allows growth at higher substrate temperature without redistribution, and may lead to higher doping concentration. In conventional MBE, carbon doping from solid
110
Compound Semiconductors
sources is preferred to chemical sources. Evaporation of carbon from a solid carbon filament source for p-doping of GaAs compounds was pioneered by Malik et a1.t1131 The filament was S-shaped to accommodate thermal expansion of C and could be heated to 2500°C. Doping concentration as high as lO*Ocm3 was achieved. Experiments have shown that a reproducible doping concentration can be achieved using regulated power supplies.[~~31-[1151 & pi‘d ramping of several hundreds of degrees in ten seconds could be achieved.t114j The doping concentration could be changed from lo’* to 1O*Ocmm3by raising the filament temperature from 2 100 to 25OOOC.Doping limits of C and Si using resistive filament evaporation, and Be using conventional furnaces have been studied by Malik et al.t1161 Application of C doping to devices have been reported by Hoke et al., t1171Ito et al.,[118land Micovic et al.tligj Activated Doping Source (Free Radical Source). Until recently, the p-doping of wide bandgap II-VI compounds had been a difficult task. The problem has been solved by using plasma sources to generate atomic nitrogen and successfully dope ZnSe.t l*Ol The plasma generators are either RF discharge or compact electron cyclotron resonance plasma sources built specifically to be compatible with the MBE UHV environment. Shutters. Shutters are made of refractory, low reactivity metals to provide a means of abrupt beam interruption in conjunction with conventional sources. There are various designs and method of operation such as rotary or sliding activated by flexible feedthroughs or magnetic coupling. It is preferred that the shutters be angled so as to minimize the reflected heat radiation back into the crucible, to minimize a flux transient upon shutter opening (see, for example, Ch. 2 in Ref. 9). The shutter mechanisms using flexible bellows have a simpler design, but repeated use especially during growth of short period superlattices may eventually lead to weakening and leaks. This is not expected during the first several hundred thousand shutter operations. The magnetically coupled shutter mechanisms have a more complicated control mechanism to ensure proper acceleration and deceleration for proper shutter speed and timing, while avoiding mechanical shock to the growth chamber. Chemical Beams. There are certain advantages associated with the chemical beam deposition method involving organometallic species.[1211-t231 Organometallic gases such as alkyls may be supplied at near room temperature through high speed precision mass flow controllers, either as pure beams or using hydrogen as a carrier gas (Figs. 10 and 11). For III-V compounds, these are trimethyl (TM) and triethyl (TE) metals such as
Molecular Beam Epitaxy
111
TMGa, TMAl, TMIu, and TEAl, TEIn. Organometallic sources for group V include TEP, TMAs and TMSb. These can form individual beams or be combined together in one vapor beam perpendicular to the substrate. The latter allows excellent uniformity without substrate rotation. It is important to note that individual molecules are again delivered as beams, with no viscous flow or diffusion at the substrate. The dopants can be solid or also organometallic. One can see a variety of combinations of sources leading to several variation on the theme of MBE depending on whether all sources are organometallic gases, or some are supplied from solid sources or high temperature cracking of amine and phosphine. Associated with this, a number of different names have been used by various authors including Gas Source MBE, MOMBE, or CBE. In CBE, the growth process is more complex than in conventional MBE. The growth rate depends critically on the substrate temperature and group V to group III flux ratio. The composition in ternary and quaternary compounds also varies in a complex manner and is not simply related to binary growth rates. RHEED
GUN
LIOUID NITROGEN COOLED SHROUDS
+Hz
0
CONVENTIiNAL MBE OVEN
PRECISION ELECTRONIC FLOW METER 8
MASS
RHEED
I SCREEN
RESIDUAL GAS ANALYZER
VALVE
Figure 10. Schematic of a Gas Source h4BE (MOMBE or CBE) system (top view).[‘24]
112
Figure
Compound
11.
input lines.
4.3
A multiple
Semiconductors
input gas injector with
run/vent
high speed actuators with
four
(Courtesy EPI.)
The Substrate Holder
Another critical componentof the MBE system is the substrateholder (Fig. 12), which normally has the following componentsand capabilities: (i) a substrate mounting ring which holds the substrate block in place and is capable of continuous azimuthal rotation (CAR) to ensure lateral uniformity; (ii) a stationary resistive heater which consists of heater wires behind a PBN heat diffilser (for temperatureuniformity) radiating heat towards the substrate; (iii) a thermocouple which mayor may not be spring loaded dependingon whether the wafer is mounted on a Mo block with In or has no backing and is under direct radiation heating; (iv) a beam flux monitoring Bayard-Alpert ionization gauge in the opposite position of the substrate (directly behind the substrate heater), and (v) a manipulator v,rhich allows the substrate holder assembly to be oriented in different positions. In the loading or transfer position, the substrate faces away from the furnaces towards the transfer mechanism with the beam flux gauge in the growth
Molecular Beam Epitaxy
113
position facing the beam cells. In the growth position, this is reversed and the substrate faces the beams. Finally, the manipulator allows other positions in which the substrate may face up or down or in between. When the substrate is in the growth position, an electron beam generatedby the RHEED gun at one side of the growth chamber can be directed towards the substrate at a glancing angle (1-3°) and the specular and the diffracted beams can be intercepted and displayed by a phosphorus screen at the opposite side.
Figure PEN
12. Substrate holder, showing substrate mounting heat diffusion
throughs,
disk, CAR
and manipulator.
mechanism,
pins and springs, thermocouple,
thermocouple
and heater wires
and feed-
114 Compound Semiconductors 4.4
Ion Gauges: Measurement of Beam Flux, Growth Rate, and Composition
The flux of individual beams arriving at the substrate can be measured or inferred by swinging a Bayard-Alpert ion gauge into or near the substrate position. In this manner one can accurately measure the flux transient (if any), the steady state flux for constant cell temperature, or the evolution of the flux vs. time when the furnace temperature is varied to achieve graded compositions. The measurements obtained in this method are actually beam equivalent pressures (BEP). These can be converted to flux by obtaining the growth rate and composition on a number of epilayers which are grown for this purpose and calibrated ex-situ, or by direct in-situ measurements such as RHEED intensity oscillations. For each beam, a simple proportionality constant will relate the BEP to the flux Cp. This can be used to determine the total growth rate and percentages of different elements (i.e., the composition) using simple arithmetic. For example, in case of conventional and hydride MBE at substrate temperatures where Ga sticking coefficient is unity (T < 62O”C), the alloy composition parameter x in the growth of Al,Ga,_.@ is determined by
x=
Q(W @(Al)+ @(Ga)
or alternatively by X=
gw+=w
- l3ww
iW=W
where g stands for growth rate and 0 stands for flux. Also note that g(AlGaAs) = g(AlAs) + g(GaAs). For CBE, the relation between growth rate and composition of ternary or quaternary with the binary compounds is more complicated and does not obey the above simple relations. Currently, the RHEED intensity oscillations are used to more accurately measure the growth rates, as discussed in Sec. 5.2. 4.5
Crystal Thickness Monitor: Flux Measurement In Si MBE, often a standard quartz thickness monitor is used to
precisely measure the thickness of the Si deposited. In III-V MBE, a quartz
Molecular Beam Epitaxy 115 crystal can be used for measuring Ga and Al fluxes provided the pressure of volatile species such as As is negligible (As cell is turned off). The sensitivity is l-2 A and the quartz monitor needs to be changed for every 50-100 pm deposited material which is not too practical. 4.6
Substrate Temperature Measurement
Substrate heating plays a crucial role in MBE growth since it provides the energy for proper mobility of surface atoms at the growth interface to ensure that the growth proceeds epitaxially, and also has a direct influence on all the other kinetic processes. In chemical beam deposition, it also governs the pyrolysis of the chemical species, which can lead to several intermediate species, surface migration of these intermediates, complete dissociation, and finally incorporation. Substrate temperature measurement before and during the growth is an intricate task. The most common method has been to use a thermocouple which is spring loaded against, or imbedded in, the MO block. The MO block temperature is assumed to be a close representation of the temperature of the substrate mounted by In. For direct radiation heating of substrates with no In bonding, the thermocouple reading does not depend on contacting the substrate and is more reproducible. However, the thermocouple in this case is exposed to the radiation from the heater and reads a higher temperature than the actual substrate temperature. This can be calibrated to the actual temperature by other means such as optical pyrometry or optical absorption spectroscopy. Optical pyrometry and transmission spectroscopy are useful techniques for higher temperature measurements (>4OO”C). Below that, photohuninescence spectroscopy using external laser and detectors can be employed. Further details are given in Sec. 8.
5.0
REFLECTION HIGH ENERGY ELECTRON DIFFRACTION (RHEED)
In this technique, an electron gun at one end of the growth chamber produces a high energy collimated monoenergetic beam of electrons in the 3-50 keV range which is directed at a glancing angle (~1-3”) towards the wafer. The diffracted and the specularly reflected beams are intercepted and displayed by a fluorescent phosphorus screen at the opposite end of the chamber. Even though the electron energy is high, the normal component of
116
Compound Semiconductors
the energy for electron penetration into the solid is small (e.g., only 50 to 175 eV for normally applied 3-10 keV electrons at 1” incidence) because of the shallow angle of incidence. At this energy range, the probability of inelastic scattering is very high, therefore, mostly the electrons which are elastically scattered near the surface are able to escape without energy loss. This means that RHEED is sensitive only to the top few atomic layers on the surface, as is the case in low energy electron diffraction (LEED). One advantage of RHEED over LEED is that in RHEED the glancing angle geometry allows simultaneous molecular beam deposition and electron diffraction measurement. The deBroglie wavelength of the electron (with relativistic correction) is given by h = [ 15O/V(1 + 10” V)]” in A, where V is the accelerating voltage given in volts. For the above energy range, this varies from 0.22 to 0.05 A, which is much smaller than the monolayer distance of about 3 A and surface interatomic distance of about 4-5 A. This makes RHEED a very sensitive tool for probing the surface structure on the atomic scale both laterally and vertically. In diffraction of electrons from a 3-D crystal lattice, the ditiction pattern is obtained from the intersection of the reciprocal lattice points with the Ewald sphere. [71[1261The Ewald sphere is formed in the following manner: the head of the incident electron k-vector, h, is positioned at the reciprocal lattice point designated as the origin of reciprocal lattice space. The Ewald sphere is centered at the tail of k, and the radius is k,, = 27rlh. For example, for 5 keV electrons, the radius of the Ewald sphere is 36.4 A-’ and for 10 keV it is 5 1.6 A-l (much larger than for LEED). This is much larger than the reciprocal lattice spacing of the crystal. For example, for GaAs with a cubic lattice constant of 5.65 A, the reciprocal lattice is cubic and the spacing is 1.1 A-l. For a truly 2-D surface, the diffraction condition requires only that the projection of k,, - k,,, on the surface be equal to a 2-D reciprocal lattice spacing, where k, is the wave vector for the diffracted beam. This means that the diffraction condition is satisfied by the intersection of the Ewald sphere with rods emanating Corn the 2-D reciprocal lattice points above the surface, or so called reciprocal lattice rods (Fig. 13). Due to a small spread in the electron beam angle, the Ewald sphere is actually a thin shell, and due to thermal vibrations of surface atoms and imperfection in flatness of the surface, the reciprocal lattice rods are actually very thin cylinders. Therefore, the intersections will be elongated streaks. Note that this is exaggerated by the fact that the radius of the Ewald sphere is so large compared to the reciprocal lattice rod spacing. For a rectangular 2-D surfaces of unit cell
Molecular Beam Epitaxy
117
d, x d2 with the substrate oriented such that the grazing electron beam is perpendicular to the d, direction, the spacing D of these streaks on the phosphorus screen is related to the distance from the substrate L, by the relation D = 2hL/d,.
PLAN
EWALD
FLUOI
/SPHERE
SC
, (1;“‘(2.$ (l.$
(2&l)
t2.$1
l&l,
to331 (O&2) toi,
($2) $I)
$1
.
.
1
_---
_---
I
t2.01---(l.O)_(O.O)---
i.0)_ _
RECIPROCAL
.O)
____------
-------__
---_
---_
.O)
--.
(i
-
.O)
‘%%’
: :. ELEVATION
0.0) IllCaL
Figure 13. Schematic representation of RHEED diffraction geometry sowing reciprocal lattice rods and their intersection with the Ewald sphere, leading to streaks on the phosphorus screen.[g]
5.1
Surface Reconstruction:
General
A properly prepared crystalline substrate has a thin native oxide before introduction into the growth chamber. The corresponding diffraction pattern appearing on the RHEED screen is composed of one or more diffuse semicircles. As the oxide is removed by means such as thermal desorption, the underlying atomically clean surface emerges. An ideal surface (unreconstructed surface) is defined by clean termination of the lattice at a plane
118 Compound Semiconductors of chosen orientation by removal of all the atoms on the other side of this plane while leaving the atoms on the lattice side in their original, unchanged position.1125l In reality, this is not generally realized since the top atomic layer has lost its nearest and/or next-nearest neighbors above the surface. This leaves the topmost atoms with dangling bonds, which can result in distortion and/or rearrangement of the atoms at or near the surface. Surface reconstruction occurs to minimi ze the surface energy and to take care of the dangling bonds. This results in a new arrangement of atoms on a reconstructed surface with a new 2-D symmetry, according to substrate temperature, surface orientation, and background species impinging on the surface. As we recall, a 3-D crystal is comprised of a triperiodic lattice of points together with a basis made up of a specific arrangement of atoms which is repeated at each lattice point throughout the crystal. For example, for GaAs and InP crystals and related compounds, the 3-D lattice has a unit cell which is atbcecenteredcubeofsidea(wherea=5.653~forGaAsanda=5.869~ for InP), and the basis is a III-V pair separated by a&/4 and the orientation is along a body diagonal. Similarly, a 2-D crystal (e.g., a reconstructed surface) is made of a biperiodic or 2-D lattice, usually called a net whose 2D unit cell is usually called a unit mesh.[1261 The basis is again a specific arrangement of atoms repeated at each point of the net. The unit mesh of the reconstructed surface is larger than the corresponding unreconstructed unit mesh (unit mesh of the ideal surface). The surface reconstruction is then notated as (mxn)-RB where m and n indicate the ratio of the sides of the reconstructed unit mesh to that of the ideal unit mesh and 8 indicates the angle of rotation (in degrees) between the two meshes. 5.2
Surface Reconstruction:
GaAs
Cho was the first to use MBE to prepare GaAs surfaces prepared under well defined conditions and used RHEED to investigate reconstructions occurring on [ 11l] and (00 1) surfaces. The reconstruction was related to growth conditions and subsequent processing.1331-1401 Cho’s most fundamental work on surface structure of GaAs (001) face appeared in 1971t361 and 19761721where he performed experimental investigations of the surface reconstructions on GaAs (001) with respect to atomic-bond directions as a function of substrate temperature and As and Ga fluxes. The GaAs (00 1) is the most relevant surface for MBE, and surface reconstruction is extremely crucial to the epitaxial growth and properties of the epilayers. The ideal GaAs (001) surface has a (1 x 1) unit mesh along the [l lo] and [ 1701
Molecular Beam Epitaxy 119 directions (4.00 8, x 4.00 A), and a single As or a single Ga as its basis. To distinguish the [ 1101and [ 1lo] directions unambiguously, a thick sample of GaAs was oriented by x-ray diffraction and cut with dimensions 1.5 x 1 x 0.4 cm3 with the larger faces being parallel to (001 } and the side faces parallel to { 11I}. The end faces were {1 lo} cleavage planes. The determination of (111) and (111) planes was done by selective chemical etching which leaves the former shiny and the latter hazy. Once these two planes were determined, the exact faces of (001) and (OOi) were distinguished and on each face the [ liO] and [ 1lo] directions were distinguished (see Fig. 14). For an ideal As-terminated (001) surface, the dangling bonds of the top As atoms are in the (110) plane and the back bonds to Ga atoms (in the lower plane) are in the (110) plane. The reverse is true for the Asterminated (OOl> surface or a Ga-terminated ideal (001) surface. The sample was mounted in the MBE chamber with the (00 1) surface facing the beams. As
PO’1
iii01 -7
(Go]
Figure 14. Schematics of the arrangement of dangling bonds on (a) (00-l) and (b) (001) faces of GaAs before surface reconstruction.[72]
120
Compound Semiconductors
RHEED measurements at different azimuths revealed a number of surface reconstructions and the important symmetry structure of the reconstructed unit mesh was determined for each case. Reconstruction was observed to be dependent on the substrate temperature and arsenic pressure at the surface. The most important of these were (2 x 4) and c(2 x 8) reconstructions which were observed at lower substrate temperatures and/or higher As pressures (As-stabilized), and (4 x 2) and c(8 x 2) reconstructions which were observed at higher temperatures and/or lower As beam flux (Ga-stabilized) and are rotated 90” with respect to (2 x 4) and c(2 x 4) reconstructions. The surface coverage favoring As in the former case and Ga for the latter case was confirmed by in-situ Auger electron spectroscopy. Many transition structures were observed during the change in surface stoichiometry, such as (4 x 6), (6 x 6), (2 x 6), (3 x 6) (3 x 4), and (4 x 4). It should be pointed out that the original RHEED gun was capable of operating with up to 50 keV electrons making possible the distinction between these various reconstructions, especially (2 x 4) and c(2 x 8) reconstruction. Most current commercial MBE systems have RHEED guns which are limited to 10 keV and some reconstructions are not as clearly distinguishable. Figure 15 shows 15 keV RHEED patterns obtained for GaAs (O_Ol)c(2 x 8) (As-rich) and c(8 x 2) (Ga-rich) reconstructions for [ 1lo] and [ 1lo] azimuths, for the zeroth Laue zone. RHEED diffraction streak patterns along these two azimuths and in the zeroth Laue zone are indistinguishable for the (2 x 4) and the c(2 x 8) reconstructions, as discussed later in this section. Figure 16 shows the real space and reciprocal space unit meshes and their orientations obtained by Cho from his RHEED measurements at different azimuths. For example, for the (2 x 4) reconstruction on the (00 1) surface the RHEED pattern showed a 2x or a 4x symmetry with the electron beam along the [ 1lo] or [ 1701 directions, respectively. In other words, for the electron beam along the [ 1lo] azimuth, an additional streak was found half way between bulk-like (unreconstructed) streaks. For the case of the [ liO] azimuth, three additional streaks were found equally spaced between two adjacent bulk-like streaks. This means that the reciprocal 2-D lattice for (2 x 4) is one-half as long in the [ 1701 direction and onequarter as long in the [ 1lo] direction as the ideal (bulk-like) (1 x 1) 2-D lattice. This, in turn, means that for the (2 x 4) reconstruction on the (00 1) surface, the unit cell (in real space) is a rectangle twice as large in the [ liO] and four times as large in the [ 1 lo] direction, compared to the (1 x 1) unconstructed ideal mesh (4.00 Ax 4.00 A).
Molecular Beam Epitaxy 121
Figure 15. RHEED patterns obtained by 15 keYelectron beam from GaAs (001) surface: c(2 x 8) As-stabilized reconstruction and c(8 x 2) Ga-stabilized reconstruction as obtained in [110] azimuth (a and c) and [-110] azimuth (b and d). The arrows indicated the position of bulk-iike (unreconstructed) streaks. (Courtesy A. Y. Cho, AT&T Bell Laboratories.)
122
Compound Semiconductors REAL SPACE
b0~I
ITiol
m
-7 [ITO]
xxxx
\
CIZXBI
CIZXBI
Figure 16. Real space and reciprocal space unit meshes corresponding to (2 x 4) and c(2 x 8) reconstructions on (001) surface of G&s. The (4 x 2) and c(8 x 2) reconstructions are obtained by a 90° rotation.[72]
Based on these experimental results, Cho suggested a simple model of two d@kent mechanisms giving the (2 x 4) and c(2 x 8) reconstructions, namely, that the two fold symmetry was probably due to a bond pairing mechanism while the 4 fold or the 8 fold symmetry was due to another effect such as Fermi surface instabilities or surface vacancies.t72J. More than a decade later, Chadi used total energy calculations to suggest that the (2 x 4) unit cell arises from the formation of arsenic dimers while the 4x symmetry arises from a regular dimer vacan~y.[~~~l This was soon confirmed by scanning tunneling microscopy [g11[1281 which also showed that the c(2 x 8) is simply a different arrangement of (2 x 4) unit cells (8.0 A x 16.0 A). A detailed discussion of scanning tunneling microscopy studies of the surface structure and electronic properties of GaAs (001) surface is given by Pashley and Haberern.[921 Figure 17 shows the missing dimer model of (2 x 4) and c(2 x 8) reconstructions on (001) surfacet 12glbased on pairing of dangling bonds shown in unreconstructed (00 1) surface depicted in Fig. 14. In Fig. 17_(top and center), we see rows of dimers along [ 1lo] with bonds along the [ 1lo], with every fourth dimer missing (suggesting 75% As coverage) forming (2 x 4) unit cells. In Fig. 17 (bottom), we see staggered arrangement of (2 x 4)
Molecular Beam Epitaxy
123
unit cells resulting in c(2 x 8) reconstruction. On a real surface, different arrangements of the (2 x 4) unit cell leads to different domains of (2 x 4) and c(2 x 8) to coexist with different configuration of missing dimer rows.[gll Experimentally, the area1 ratio of between (2 x 4) to c(2 x 8) domains is statistically between 2 and 1.[12glThree different 2 x 4 phases were found to exist on GaAs (001) depending on the MBE-growth condition: a, p, y, corresponding to 1,0.75, and 0.5 ML As coverage. The /3phase is depicted in Fig. 17. The y phase is similar except that two dimers are present and two dimers are missing .[1301
.
.
.
0
m-fa
/.
.
.
.
.
;
. . . . . . . ‘7m zllzxx )
.
.
.
(
.
.
0
0
0
l
0
0
.
-
.
.
.
.
.
0
l
l
11101
~12x81 unit mesh
Figure 17. Arsenic dimer pairing leading to (2 x 4) (fop) and ~$2 x 8) @oftom) reconstruction on (001) face of III-V compound. Note that the twofold symmetry in both cases results from dimer paring with the bonds parallel to [ilO] direction as expected from Fig. 15. The 4-fold symmetry (top and confer) results from rows of missing dimer along [ilO], every fourth position. The c(2 x 8) (bottom) is formed by staggered arrangement of 2 x 4 cells. (Adapted@om Ref: 129.)
124 Compound Semiconductors Figure 18 represents the arrangement of 2-D reciprocal lattice point for bulk (1 x l), (4 x 2), and c(8 x 2) reconstructions, together with expected RHEED patterns along [fiO], [ilO], and [TOO]azimuths, for different Laue zones,l73I showing how the two different reconstructions may be distinguished. RHEED studies have also been carried out on GaAs and AlGaAs grown on vicinal GaAs substrates to study different surface reconstructions and transitions as a function of substrate temperature and arsenic flux. Phase diagrams have been generated based on these studies.1132l Finally it should be mentioned that the surface reconstruction influences the metalsemiconductor Schottky barrier height value (Table VII, Ref. 75). For example, for Al deposited on GaAs (00 l), the Schottky barrier height has a value of 0.66-0.76 eV for c(2 x 8) and 0.72-0.80 eV for c(8 x 2) GaAs surface reconstruction.
. Bulk Isltlce ” (4x2)
only
0 C(8X2) only 1 common to (4x2) and ~(8x2)
Figure 18. Representation of reciprocal lattice for unreconstructed (bulk), (4 x 2) reconstruction, and c(8 x 2) reconstruction on GaAs (001) surface, together with the RHEED patterns expected in different azimuths for different Laue zones. Note that the (4 x 2) and c(8 x 2) patterns are identical for the [EO] and [ilO] azimuths in the zeroth and first Laue zone.[‘3]
Molecular Beam Epitaxy 125 5.3
RHEED Intensity Oscillation and its Application
An exciting feature of MBE growth is that the intensity of the difficted beam (and the specular beam) in reflection high energy diffraction undergoes oscillations with the period corresponding to one monolayer growth (Fig. 19). In case of GaAs (001) surfaces, one monolayer is composed of a complete layer of Ga and a complete layer of As amounting to a total thickness of u/2 (2.83 8, at room temperature). This feature of MBE was first observed in the growth of GaAs[761-[*01 using conventional MBE but was later found to be a universal feature of the MBE growth mode. It has been found to be true for a wide variety of material systems as well as A simple picture of the oscillation of during gas source MBE growth.[811-[861 the RHEED intensity corresponds to transitions of the surf&e from smooth to rough to smooth[781[1321-[1331 (F’lg. 20). This comes about since MBE is a monolayer-by-monolayer growth process where individual layers start with random nucleation sites which grow into islands, leading to a maximum roughness due to step edge density, when the islands cover 50% of the surface. This roughness reduces the specularly reflected beam intensity to a minimum. As the growth proceeds, the islands eventually coalesce into a complete monolayer and the roughness gives way to maximum smoothness, corresponding to a minimum in step edge density, manifesting itself in a maximum specular beam intensity. In the case of growth on As-stabilized GaAs (2 x 4 reconstruction), it was observed that the amplitude of oscillation was larger for the e-beam along the [ 1lo] direction implying a larger step edge density in this direction. This is consistent with the previous discussion about surface reconstruction and direct STM results. In these studies, the islands were elongated along the [110] (separated by longer rows of missing dimers along that direction). This leads to higher step edge density as the e-beam cuts across the islands in the [ 1lo] direction (Fig. 20). Study of different features of RHEED intensity oscillations as a function of growth conditions and substrate orientation provides valuable information on monolayer formation, growth rate, surface migration, and growth kinetics and dynamics. This has led to fine adjustment to the growth process to achieve one monolayer smoothness in heterostructures, phaselocked epitaxy, and interface smoothness control to within an atomic layer. RHEED intensity oscillations also allows accurate real time determination of growth rate in a layer-by-layer manner. For the conventional MBE, the composition in the ternaries and quatemaries can also be determined from comparing the growth rate of the binary constituents with the total growth rate. This method is not compatible with substrate rotation.
126 Compound Semiconductors RHEED INTENSITY
OSCILLATIONS
Substrate 597 ‘C Al closed Ga Closed --:
--Al Opened
GaAs 1 71Mlis
I
0
I
5
I
I
Al 8 Ga Opened
AlAs 0.585 MVs
llu
AlGaAs 2 29MVs
, , , , , , , I , ,.,
I0
19
E0
25
TIIIE
Figure
-- >
30
35
40
45
50
CSECI
19. RHEED intensity oscillations during growth of GaAs, AL4s, and AlGaAs.
8 = 0.5 8 = 0.75
8= 1.25
0
m
number of monoloyers
deposited
Figure 20. Representation of the formation of the first two monolayers leading to RHEED intensity oscillations. @f&r Ref: 132.)
of GaAs (001)
Molecular Beam Epitaxy 127 Growth Rate and Composition. One direct advantage of monitoring RHEED oscillation is that the actual growth rate of any layer can be directly measured even at temperatures where the sticking coefficients are not unity, since each period corresponds to completion of one monolayer. As an example, we consider the situation for growth of GaAs, AlAs, and AlGaAs on GaAs substrate. Figure 19 shows RHEED intensity oscillations obtained by opening the Ga shutter, then closing the Ga and simultaneously opening the Al shutter, and finally opening both Ga and Al. The As shutter was left open during the growth. The growth rates of each of the three layers may be directly obtained from the corresponding frequency of oscillations, f, either directly or by a fast Fourier transform routine. Note that in this particular example f(AlGaAs) = f(GaAs) + f(AlAs) which then gives the Al fraction, x, as
f-WW
x=@lGaAs) or equivalently
This implies that the incorporation rates of Ga and Al are independent of each other. This is generally the case in conventional and hydride MBE over a wide range of substrate temperatures (<63O”C for AlGaAs). For higher substrate temperatures in conventional MBE growth of AlGaAs, the Ga incorporation rate depends on the substrate temperature, Al flux, and even As flu~.t~~1t*r1tr341 For InGaAs or InAlAs, In desorbs at a faster rate compared to Ga. In contrast, the sticking coefficient of Al remains unity for a wider temperature range (up to about 730°C). For MOMBEKBE, the growth rates can also be obtained from RHEED oscillation measurements.[841 However, even for the growth of GaAs, the growth rate is highly dependent on substrate temperature (Fig. 21).rs41 For ternary compounds, the growth rate in general is not simply obtained by adding those of the binaries. The incorporation rates have a more complicated interdependence and are governed by the arsenic beam flux as well as the substrate temperature. They are also influenced by the gas species and the intermediate products of pyrolysis at the substrate.[1351
128
Compound Semiconductors
400
so0 SUBSTRATE
600 TEMPERATURE
TOO (‘Cl
Figure 21. RHEED intensity oscillations and growth rate determination in chemical beam epitaxy (or MOMBE).[84]
Damping of the Oscillations. Another feature of the RHEED intensity oscillations is that the oscillation is accompanied by a damping; the maxima progressively get smaller, and the minima get larger until small or no oscillations are observed (Fig. 19). This implies that an equilibrium terrace length and step edge density has been reached, depending on the growth conditions. The damping is observed to be faster for higher substrate temperatures. Another factor leading to damping is variations in the growth rate across the portion of the wafer being sampled by the beam. This corresponds to a narrow but very long region since the e-beam strikes the wafer at a glancing angle. This complication is prevented by using a small sample for RHEED oscillation studies. Increase of the Amplitude. The intensity oscillations can be observed to increase when a dopant beam flux is turned on.[‘*l This indicates a larger fluctuation in step edge density with dopants and is consistent with the idea that preferential nucleation is occurring at the terraces in the presence of the dopants. [1331 A common observation is that, after the growth of GaAs has been going on for a while and the oscillations have
Molecular Beam Epitaxy 129 damped, opening of the Al shutter can renew large amplitude oscillations. This could be due to the fact that the Al surface difksion is smaller than that of Ga thereby leading to the presence of more islands of smaller sizes with a resulting increase in the step edge density. Growth Interruption and Intensity Recovery. It is also commonIy observed that after the RHEED oscillations have been damped, as in growth of GaAs over several monolayers, an interruption in the growth leads to the recovery of the intensity (Fig. 22a). The nature of the recovery depends on the growth conditions and the duration of growth time, as studied by Lewis et al.1801Sakaki and collaborators studied the effect of growth interruption on the smoothness of GaAs-AlAs interfaces by growing quantum wells of various thicknesses and as a function of duration of interruption with growth interrupted at the GaAs-AlAs interface either at a maximum of intensity oscillation or at a minimum.l136l The photoluminescence lineshape of the different wells were studied as a measure of interface smoothness, and the smaller the linewidth, the smoother the interface. It was found that the smoothness was enhanced when the growth interruption was at a RHEED intensity oscillation maximum and had a duration of 90 s. The growth interruption technique, together with photoluminescence as a probe, has been used by various authors to optimize interface smoothness.113~-11401 Phase-Locked Epitaxy. A direct application of the RHEED intensity oscillation is that one can achieve heterostructures A/B with near-perfect interfaces by terminating layer A at precisely the time when a maximum in RHEED intensity oscillation has been reached; growth of layer B should be commenced at that moment.1142J11431 Thi s ensures the completion of the top monolayer of material A, before growing the first monolayer of material B. This technique has been used to grow short period superlattices such as (GaAs),(AlAs), which signifies 3 monolayers of each (Fig. 23). The growth of each new material follows after a short interruption (about 6 s in this case) to allow for the smoothing of the interface. Details of the applications of RHEED intensity oscillations in the growth of III-V interfaces as wells as Si and WSiGe are reviewed by Sakamoto.11441 Migration Enhanced Epitaxy. An alternative approach to achieve smooth interfaces in III-V compounds is to take advantage of the fact that the surface migration of group III elements (such as Ga) is enhanced when no group V atoms are present. In this technique, the group III and group V elements are deposited alternately in a periodic manner. In each period, the group V shutter is opened for precisely half the time it takes to grow one monolayer, while group V shutter is closed, then the two shutters are
130
Compound Semiconductors
reversed for the other half cyclei 1451~1 (Fig. 24). This enhances the surface lifetime of isolated group III atoms which are quite mobile on the growing surf& resulting in longer migration distances until they reach a step edge. Step flow growth therefore dominates even for surfaces where step densities are 10w.[~~l
10 set
Time Figure 22. Effect of Growth interruption on RHEED intensity: (a) for low substrate temperature intensity recovers indicating surface smoothing, (b) for high substrate temperature a partial recovery is accompanied with intensity oscillations indicating monolayer by monolayer desorption.[144]
Molecular Beam Epitaxy
(GoAs), (AlAsI, 41 open , Al close Go open / Go close
0
131
superlattlce
1 Time (minl
( a I Non phose - locked eprtaxy
( b I Phase-locked
epitaxy
Figure 23. Shutter sequence and RHEED intensity oscillations during phase-locked epitaxy of short period GaAs-AlAs superlattice (top), and schematic comparison of surface smoothness with or without phase-lock epitaxy.[lU]
132 Compound Semiconductors
Ga Jlnn Aqq_Ofmkycle
580’c
Ga(O.SNs)+Ass I
(a) flat surface (lOO)GaAs
HlOnm
lb)
H32nm (C)
Figure 24. Shutter sequence and RJXED intensity oscillations during migration hanced epitaxy (MEE) of GaAs (001) flat and vicinal surfaces at 580°C. Note that RHEED oscillations are modulated for the flat and 0.5” off surfaces (a and c) but is modulated for the 2” off surface (b). This indicates that in case (b), the growth completely by step flow mode from the outset, and migration length of Ga is larger than nm and smaller than 32 nrn.[14’j]
enthe not is 10
Growth on Vicinal Surfaces: Adatom Migration and Step Flow Growth. The combination of growth on vi&al surfaces and RHJZED intensity oscillations gives insight regrading surface kinetic processes, as well as allows new flexibilities. Vi&al surfaces are obtained by cutting the
Molecular Beam Epitaxy 133 crystal at a small angle (a few degrees), misoriented with respect to a low index surl&e such as (100) or (110) towards a specific direction. This results in a surface comprised of large, low index terraces separated by small (usually one monolayer high) steps. The average width and length dimensions of the terraces would depend on the angle and the direction of cut. If the migration length of the group III element is larger than the step free length &of the terraces, the group III element will migrate freely over the terrace until it reaches a step edge. It then has a very high probability of being incorporated in the crystal at the step. This results in a stepflow mode of growth. In this case, the average step edge density will remain essentially constant and no appreciable RHEED oscillation will be observed. This has a number of applications, including measurement of surface migration lengths of adsorbed species, and growth of quantum wires. The observation of RHEED intensity oscillation, or lack thereof, in conjunction with growth on vi&al substrate can be used to measure the migration length of different group III atoms as a function of temperature, group III flux, and group V flux. In this manner, surface migration lengths for Ga and Al on GaAs has been studied by Neave et al.11471This technique is also used in conjunction with migration enhanced epitaxy to investigate lateral migration, and vertical replacement processes both in MBE and in MOCVD step flow growth mode, as reported and reviewed by Horikoshi et al.t1461 Another application of growth on vicinal surfaces is for the formation of laterally defined superstructures which include quantum wires and quantum boxes. These have a number of exciting properties including suppression of both optical phonon and impurity scattering for high mobilities,[148111501 and excellent laser operation with very high efficiency, good temperature stability,l151l extremely low threshold current (in the microampere r~ge),[1W[lW and higher modulation bandwidth and narrower spectral line widths.l155l Fabrication of these structures has been extremely difficult. In 1984, Petroff et al. proposed a brilliant method for deposition of laterallydefined superlattices by depositing half monolayers of GaAs and AlAs alternately on a (100) vicinal GaAs surface where terrace lengths were smaller than the migration length of group III adatoms.l156I This was realized only after use of RHEED oscillation for step-edge flow growth was well understood and implemented by Petroff and collaborators. They used lateral periods of 80-160 ~.11571-[1581 Independently, Sakaki et al. achieved similar structures with lateral periods of 40-80 A.[1591 FU-IEED Oscillations During Desorption at High Substrate Temperature. When the substrate temperature is higher than 65O”C, the
134
Compound Semiconductors
desorption rate of GaAs from the epilayer cannot be neglected compared to the deposition rate.[81J[1341[1441 F igure 22b shows that for GaAs substrate temperature of 700°C RHEED oscillations appear after the Ga shutter is closed, whereas such oscillations are absent for substrate temperature of 580°C (Fig. 22a). This indicated monolayer-by-monolayer desorption of GaAs at high substrate temperature. In case of In containing III-V compound, this desorption is more prominent.[1611This results in a decrease of the growth rate. This sublimation process proceeds in a layer-by-layer manner and is also manifested by RHEED intensity oscillations. It is seen that an increase in the As flux can suppress this desorption at high temperatures.lgll
6.0
MASS SPECTROMETRY
Modulated beam mass spectrometry has played an important role in the early development of MBE to study the kinetics of adsorption/desorption of the modulated beams of Ga and As on GaAs substrate.[321[541-1571 After these initial studies, the most common use of mass spectrometry was He leak checking and residual gas analysis to check the integrity of the UHV system, and to monitor outgassing of the growth chamber components such as furnaces, crucibles, and source materials to ensure the cleanest possible environment for the growth. In recent years, mass spectrometry of the species desorbed from the substrate during the growth has been revived as a tool for monitoring and controlling the growth process, especially to monitor In desorption during growth of In-containing III-V compounds. More recently, modulated mass spectrometry has been applied to the study of MOMBE or CBE as well. 6.1
Modulated Beam Mass Spectrometry (MBMS)
This is an elegant method for studying kinetics of beam-surface interaction. Application of this technique to the study of adsorption/ desorption kinetics of Ga and As beams on GaAs surface has played an important role in the early development of MBE, as discussed previously. In this technique, modulated molecular or atomic beams are directed onto the surface to be studied and the desorbed fluxes are detected by a mass spectrometer facing the surface at some distance within the UHV system. The modulation of the incident beam (or beams) results in a modulation of
Molecular Beam Epitaxy 135
the desorbed flux and the signals from the mass spectrometer are examined for a correlation. In another variation, the desorbed fluxes are modulated instead. The simplest version of MRMS is the transient beam method. The incident flux is changed abruptly (stepwise) and the desorbtion signal is examined as a response to this stepwise change. This is the method that Arthur used in studying the kinetics of reaction of Ga and As2 beams on heated GaAs, discussed in Sec. 1.2.t321An improved approach is based on periodic modulation of the incident beam and synchronous detection of the desorbed beam, correlating phase and amplitude of the desorbed signal to the incident beam modulation at a given frequency. The advantage of this method is that it distinguishes between background and desorbed signals even for more volatile species such as arsenic and phosphorus which do not readily stick to the walls of the chamber and can lead to memory effects and false signals. To obtain maximtmr information on the surface kinetics, it is necessary to repeat the experiment at different frequencies. An improved version of the periodic modulation has been developed by Foxon and Joyce and coworkers and was applied extensively to the study of kinetics of reaction of As, and As, on G~As.[~~~[~~I Jn this approach, data acquisition and analysis is improved by signal averaging the time varying desorption signal and then Fourier transforming the detected signal and the known time dependence of the incident flux. The attenuation and phase shift of the Fourier components of this flux due to all the events between beam modulation and detection is obtained. Information on the surface processes is extracted by deconvolution. Using the above technique, the following information can be extracted on the nature of surface kinetic processes and parameters: (i) identification of desorbed species, (ii) desorption rates, (iii) accommodation coefficient of an adsorbed species, (iv) surface lifetime of an adsorbed species, (vj sticking coefficient of incident molecules, (vi) binding energy of surface species, and (vii) order of chemical reactions. Reaction Kinetics of Ga and As, or As, on GaAs. Foxon and Joyce and coworkers applied the above technique to study the reaction kinetics of Ga and either As, or As, on GaAs (00 1).[531[671 In the following, we present the summary of these findings as reported in Ref. 12. For the case of As,, they found that these molecules were first adsorbed into a weakly bound mobile precursor state with a surface residence time of less than 10s5s. The basic process of As incorporation was found to be a simple first order dissociative chemisorption on surface Ga atoms. The sticking coefficient of As, was found to increase linearly with Ga surface coverage to a maximum
136
Compound Semiconductors
of unity when the surface was covered with a complete monolayer of Ga atoms. At relatively low substrate temperatures (<600 K) there was an additional associative reaction to form As, molecules which desorbed very slowly by a first order reaction. Above 600 K, some dissociation of GaAs could occur. A significantly more complex reaction mechanism with As, incident beam was encountered. As, molecules were first adsorbed into a mobile precursor state, with an activation energy of about 0.25 V for their surface migration. The surface residence time was temperature-dependent with a desorption energy of about 0.4 eV. A crucial finding was that the sticking coefficient of As, could never exceed 0.5, even when the Ga flux was much higher than the As, flux, or when the surface was completely covered with a monolayer of Ga atoms. This was explained by assuming painvise dissociation of As, molecules chemisorbed on adjacent Ga atoms. This second order reaction is an important feature of MBE growth of GaAs growth with As, beams. From every two As, molecules, only four As atoms are incorporated and the other four desorb. The properties of epitaxial film grown by As, vs. As, seem to have certain advantages. It has been observed that using Asz beams, the deep level state densities are decreased, the photoluminescence intensity is increased, AlGaAs morphology is less dependent on substrate temperature, oval defect densities are decreased, minority carrier lifetime is increased, interface quality is improved, and shallow donor incorporation is increased. On the other hand, in delta-doping with Si and Be, spatial confinement and carrier confinement is seen to decrease and in low temperature grown MBE layers the deep levels, carrier concentration, and PL intensity is seen to decrease, while As incorporation is seen to increase.l161l Application to MOMBE and CBE. This technique cannot be used to study intermediate species generated by pyrolysis of chemical beams at the heated substrate, since the detection is made far away from the surface under study. However, recent modulated beam mass spectrometric studies by Foxon and coworkers in CBE have shown that some intermediate volatile species such as di- and mono-methylgallium (DMGa and MMGa) were desorbed from the surface and could reach the mass spectrometer and be detected.[1351[1621-[1641 These studies also indicated that, for a fixed group III arrival rate and fixed substrate temperature, a strong dependence on As flux was observed even when group V species was supplied in excess. In fact, the growth rate was seen to decrease with an increase of group V flux. This was the case for both TMGa and TEGa.
Molecular Beam Epitaxy 6.2
Desorption Mass Spectrometry
13 7
(DMS)
In principle, a mass spectrometer in the vicinity of the growth position can be used to measure the beam fluxes before the growth, just as in the case of the ion gauge. However, this is not practical during the growth itself. On the other hand, the mass spectrometer can be placed in one of the furnace ports facing the substrate and used to monitor the desorbed fluxes from the substrate during the oxide removal before the growth, and monitor desorption of Ga during the growth at a high substrate temperature.16*l This information can be used for real time growth rate and composition monitoring, and control during the growth of different III-V compounds even with substrate rotation.1681-1711 This is an exciting development in MBE since it provides a convenient method not only for composition monitoring and control of AlGaAs compounds, but also for other III-V compounds where desorption of more volatile group III species, such as In, can be monitored and compensated to avoid compositional variation and lattice mismatch. Compositional Grading using DMS and Solid Source Valved Crackers. As mentioned at the end of Sec. 5.3, when the substrate temperature is higher than 65O”C, the desorption rate of GaAs from the epilayer cannot be neglected compared to the deposition rate.l81ll134l1144l It is seen that an increase in the As flux can suppress this desorption at high temperatures.lgll Therefore, the incorporation of Ga in AlGaAs can vary with As flux at high substrate temperatures. Taking note of this fact, Evans et al. took advantage of the highly controlled arsenic flux manipulation of a solid source valved cracker, combined with real-time monitoring of Ga desorption using DMS, to grow a parabolic Al,Ga,_& (x = 0.15 to 0.05 over 30 ML) profile1711(Figs. 25 and 26).
7.0
IN-SITU AUGER ELECTRON
SPECTROSCOPY
(AES)
In this method, a focused electron beam impinges on the surface of the solid sample creating secondary electrons near the surface. Some of these secondary electrons have energies characteristic of the elements and their chemical environment and are called Auger electrons.l87l This technique is used to analyze the topmost 10 to 30 A of the sample and has detection limit of 0.1% to 1% of a monolayer. Depth profiling can be achieved by performing AES in conjunction with Ar+ sputtering. This technique is not
138 Compound Semiconductors
Secondr
Figure 25. Variation in desorption mass spectrometry signal during growth of AlGaAs as a function of time obtained from changing the substrate temperature (a), or the arsenic flux from a valved cracker (b). Note the sharp response due to latter. The change in desorption of Ga results in a corresponding change in GsAl ratio of the composition since desorption of Al is negligible.[71]
Seconds
0.65 -w
. >o.so z 3
-0.35 3
-
go.20 l.E
-
0.05
* ’ *a
-
-
Obswwd
- - - Drrind
Monoloytn
Figure 26. Growth of a parabolic composition AlGaAs well by controlled variation of arsenic flux using a valved cracker and utilizing desorption mass spectrometry signal for composition monitoring and control.[711
Molecular Beam Epitaxy 139 sensitive enough to determine dopant concentration. In the initial development of MBE, in-situ Auger electron spectroscopy was used to study the procedure for obtaining oxygen- and carbon-free substrate surfaces prior to growtht**l and to study the relative surface compositional changes.[8gl Auger electron spectroscopy has also been used to study surface cleaning of InP by heating in the growth chamber under an arsenic beam.IgOl In those experiments, the Auger electron gun and cylindrical mirror analyzer were bellows-mounted and could be rolled in and out to measure Auger peak intensity of In, 0, P and As at any given substrate temperature. In this manner, desorption of P,05 and As,O, from the surface and onset of InP decomposition were observed as a function of temperature. From these data, optimal heating of substrate for oxide desorption with minimum damage to InP was determined. In modem MBE systems, Auger electron spectroscopy is not done in the growth chamber and is used only for surface analysis before and after the growth.
8.0
OPTICAL METHODS FOR REAL-TIME GROWTH MONITORING
Optical monitoring methods are powerful non-invasive techniques which can be used for real-time growth monitoring and control even with substrate rotating. With a few exceptions such as simple one-color pyrometry, these techniques have not found common use and are not standard equipment on MBE systems. The optical equipment can be installed on viewports on the periphery of the growth chamber and either view the radiation from the wafer (substrate plus the epitaxial layers), or monitor the response of the wafer to external light sources. These techniques can be used for real-time measurement of substrate temperature, growth rate, composition, layer thickness, and surface morphology. Among these techniques are optical pyrometry, pyrometric interferometry, *ared transmission, ellipsometry, reflection difference spectrometry (RD), dynamic optical reflectivity @OR), photoluminescence (PL), and laser light scattering (LLS). Some of these approaches depend on detailed knowledge of material optical parameters and may require sophisticated computer programs for data extraction and are not yet in common use.
140
Compound Semiconductors
8.1
Optical Pyrometry
This technique involves detecting radiation emanating from the wafer in a narrow wavelength range at one or at two different wavelengths below the band edge (for GaAs onecolor pyrometry, this is usually 940 nm f 30 nm).t1651This choice of wavelengths is important since at these wavelengths the material can be considered opaque, and the radiation from the heater filaments is excluded from the detector. This method is most accurate for higher temperature range where the grey body radiation is more copious (e.g., down to 340-380°C for GaAs). Care must be taken to interpret the data since the reflected beam from the open hot cells can lead to a somewhat higher reading. Accurate calibration depends on the knowledge of the emissivity of the wafer, which itself could change depending on the temperature and on the thickness and composition of the deposited fihns. A method for absolute calibration of the substrate temperature uses the eutectic temperature of Al-S1 system. [W Another method for compound semiconductors is the observation of changes in RHEED pattern as a function of temperature to establish the congruent sublimation temperature, which is accurately known for compound semiconductors such as GaAs and InP. Pyrometric Interferometry. The pyrometers used in MBE operate in a narrow wavelength where the substrate is opaque at the substrate temperature range of interest (e.g., 940 nm f 30 run for GaAs) and supposedly only receive the grey body radiation from the outermost surface of the epilayer. However, the grey body radiation from the substrate itself is not completely absorbed in the epilayers as the absorption length for GaAs at 600°C is about 1 pm, and is larger for AlGaAs. This radiation can then undergo multiple reflection and interference within the epilayers themselves, if suitable boundaries are present in the growing epilayers. For example, a layer of AlGaAs on GaAs provides two such boundaries: the buried AlGaAs/ GaAs interface and the exposed AlGaAs/vacuum interface. This interference results in apparent oscillations in the temperature as the growth proceeds, the oscillations being due to intensity oscillations as a result of growing optical path length These observed oscillations in a one-color pyrometer can be directly related to layer thicknesses provided the indices of refraction for different layers are known. This technique has been exploited for growth rate and compositional monitoring.t1671-[16gl This technique can be applied to large, rotating substrates. A more versatile alternative is to use two-color pyrometry, i.e., detect two different wavelengths in narrow bands to obtain some of the optical parameters directly.t1701 In our view, using a
Molecular Beam Epitaxy
141
spectrometer in conjunction with a multichannel diode array instead of a one-color or two-color pyrometer can provide high speed spectroscopic data over an entire range of wavelengths, thus, providing the ultimate flexibility and maximal information for monitoring and control of complicated multilayer structures. An alternative approach is to use an external diode laser which can penetrate the layers while growing, and monitor the reflected beam having suffered multiple reflection and interference in the multilayers as they are being grown (dynamic optical reflectivity). 8.2
Transmission Spectroscopy
Direct radiation heating of substrates in MBE allows the infrared light which heats the substrate to also serve as a light source for transmission spectroscopy. tl’ll This has two important applications: temperature measurement and growth rate measurement. In the first application, the position of the absorption edge can be measured to better than 5 meV. In the temperature range of interest to MBE growth, the bandgap of GaAs shifts to the lower energy by about 500 meV per 100°C temperature increase, giving an accuracy of 1O°C with a reproducibility off 2°C for substrate temperatures measured down to 450°C.tr7rj The second is similar to the above interferometric pyrometry but radiation from the heaters behind the substrate is used as the probe, and the wavelength range, therefore, must be in the transparency range of the substrate. This method is more suited for the growth of InGaAs on InP where the substrate has a wider bandgap than the epilayer. 8.3
Photoluminescence:
Low Substrate Temperature Measurement
For low temperature measurement, an elegant method uses photoluminescence through viewports by employing an external laser and detector system with chopper and lock-in amplifier.t1721 This has the advantage of being more sensitive at the temperatures employed for the growth of low temperature GaAs (LT-GaAs) and related compounds (<3OO”C). The thermocouple measurements, although very reproducible, are difficult to calibrate absolutely. Pyrometers fail to be effective and accurate in this application since grey body radiation is very weak with a large wavelength at low temperatures. Similarly the heater radiation in the back of the substrate is too weak and is peaked at large wavelengths and is not suitable for pyrometric interferometry.
142
Compound Semiconductors
8.4
Reflectance Difference Spectrometry (RD)
In this method, a visible/deep UV light is passed through a focusing gr&ng monochromator, is polarized along the [ 1lo] direction or along the [ 1lo] direction and is incident upon the (001) oriented wafer at normal incidence. The reflected light is monitored for the two different polarizations and the difference in reflectivity of the two different polarizations (reflectance difference, RD, signal) is recorded as a function of time.t1731 The above polarizations correspond to Ga-Ga and As-As surface dimer bond directions, respectively. Because the reflectance contributions from randomly oriented (unreacted) surface species and the bulk are nominally isotropic, only the contribution from the directed bonds and/or oriented microscopic features at the surface survive the signal subtraction.t1731 RD signal can then provide either chemical or structural information depending on the wavelength. This complements the structural information available from RHEED and may be taken simultaneously. RD signals are observed to exhibits oscillations of the same period as in RHEED. As in RHBED, RD cannot be used during substrate rotation. For structural determinations, RD dyta is more detailed than RHEED due to an extremely short surface correlation length. 8.5
Laser Light Scattering (LLS)
In this technique, a visible laser beam is incident on the substrate and the scattered light from the substrate is collected and detected. In this manner, the topography of the growing surface can be monitored over a submicron scale. The use of this technique in MBE has been demonstrated for both Si[174land Ga.A~t~~~l-1~~~1 LLS can be used to monitor oxide desorption, MBE growth, and post-growth anneal. It is sensitive to a wavy surface morphology developed during the growth, as manifested by increased scattered light intensity. This increase is geometry and wavelength dependent, and is related to the correlation length of the surface features. LLS may also be used to detect the onset of dislocation formation. Celii, et al have utilized LLS for the in-situ detection of strained epilayer relaxation in the growth of InGaAs/GaAs strained layer superlattices.[1771 8.6
Spectroscopic
Ellipsometry
Spectroscopic ellipsometry is another powerful optical method of measuring surface characteristics, and is especially suited to multilayers.
Molecular Beam Epitaxy
143
The principles and advantages of this technique are reviewed in Ref. 10. This technique has been successfully applied to real-time monitoring and control in MBE and CBE.11781-11801 Closed loop control using this technique has been successfully demonstrated in the growth of a 200 A wide Al,Ga,_.@ well parabolic (x = 0 to 0.3).117gl
9.0
GROWTH OF III-V COMPOUNDS
The III-V compounds and their heterostructures grown on GaAs and Inp substrates are the most important semiconductors for high speed integrated electronic circuits, optoelectronic devices, and optoelectronic integrated circuits (OEIC). Figure 27 shows bandgap energy vs. lattice constant for important III-V and II-VI compounds as well as Si and Ge. Extensive studies on the materials properties of these semiconductors has been reported.[1811-11841 Th e group III elements used are Ga, Al, and In and the group V elements used are typically As and P. Typical dopants are Si for n-type and Be for p-type. These materials have high electron mobility and saturation velocity, and are very efficient light emitters with direct energy bandgaps over a wide range. The AlGaAslGaAs system is nearly lattice-matched and is widely used for high speed electron devices and optoelectronic devices in the 0.65-0.86 urn region. The In,,Ga&,P,, system is lattice-matched to Inp provided 0.1896 y x = 0.4176 -0.0125 y or x E 0.47 y. This material system is extremely important for lasers and detectors operating in the 1.3 pm and 1.55 pm region. The fundamental gap in the materials lattice-matched to InP ranges from 1.35 eV for Inp to about 0.74 eV for InGaAs. An alternative to this system is Inl_x_YG~,,As latticematched to InP which spans a larger bandgap range.11851-11881 The InGaAs/ GaAs and InA1As/GaAs are lattice-mismatched. As discussed in Sec. 11.3, the mismatch can be accommodated by elastic strains by making thin superlattice layers of the ternary and binary alloys. This provides flexibility in the bandgap and lattice matching requirement, but also changes in the valence band properties occur which are beneficial to laser and optical modulator applications. The most important application is 0.9 urn lasers for pumping erbium-doped optical fiber amplifiers to produce laser
144
Compound Semiconductors
radiation in the 1.55 pm region. When Sb is used, smaller bandgaps are achieved for use in long wavelength (5-10 pm) detectors. Finally, the InGaP, InAlP and InGaAlP system can be grown lattice-matched to GaAs to achieve materials in the visible range. Four Quaternary Alloy Systems
2s 3 o.pM 5 m l-
InSb w
0
I I 1 I II I' 6.0 5.6 5.8 5.4 cuta comely 01 A ENahxy Bellcore Lattice Parameter (A) I
I 6.2
I
I 6.4
Figure 27. Energy gap vs. lattice constant of III-V and II-VI compounds.
9.1
-5
I 6.6
(Courtesy EPZ.)
Substrate Preparation Prior to Transfer to MBE
The surface of the substrate plays perhaps the most important role in the monolayer by monolayer epitaxial growth process. Study of proper surface preparation and conditions for optimal epitaxy has always been and continues to be a most important activity in the successful development and evolution of MBE. For successful MBE growth, one has to start with a substrate free of contaminants and defects. Certain contaminants absorbed on the surface during the wafer handling prior to loading are so stubborn that they cannot be removed without damaging the surface. With such contaminants present, the morphology, optical, and transport properties of the layers would be adversely affected. In some cases, epitaxy may not be possible.
Molecular Beam Epitaxy
145
To prevent these problems, the substrates must go through a rigorous preparation regimen before loading. Some wafer suppliers make available wafers already prepared and ready for loading (epi-ready), in which case no preparation is necessary before loading. In the other extreme, one may start with saw-cut wafers which require extra preparation steps. Normally, wafers are supplied with one or both sides polished after etching but require preparation before loading. The substrate preparation steps are: degreasing, chemomechanical and/or chemical treatment, protective thin oxide formation, drying, mounting on wafer carrier, and finally loading in the load-lock chamber. The solvents and chemicals used should be high purity, filtered semiconductor grade to avoid chemical and particulate contaminants. These procedures are carried out in laminar flow exhaust hoods to minimize airborne particulates and protect the operator from chemical vapors. Many of the steps involve rinsing in deionized (DI) water (about 18 lWA resistivity). Care must be taken that the deionized water is constantly recycled and filtered with submicron filters. An additional 0.2 urn filter at the point of use nnnimizs the particulates. The DI water system must be sanitized periodically to avoid the build up of bacteria. The bacteria remnants are stubborn contaminan ts that can adversely affect the MBE growth. During any wet process, care must be taken that the surface is not exposed to air at any time. Chemomechanical and chemical etching is done in dishes and on surfaces that are chemically inert, such as Teflon’s’. The drying is done using filtered, high purity dry nitrogen dispensed from a gun, or subjecting the wafer to high spin drying. In the following, we first describe degreasing procedures which are common to GaAs, InP, and Si wafers. The chemical etching and oxide formation steps depend on the substrate material and will be given accordingly. Degreasing: The degreasing usually involves boiling for 3 min in trichloroethylene or trichloroethane, followed by rinsing and a 3 min boiling in acetone, followed by rinsing and another 3 min boiling in methanol or 2propanol (isopropyl alcohol). Some workers do additional cleaning in Alconox, or sulfuric acid to eliminate other possible organic contaminants. GuAs Substrates: For saw-cut wafers, the mechanical damage is removed on both sides by chemomechanical polishing using 0.3-l% mixture of Br in methanol on an inert soft pad on a firm surface, followed by a free Br-methanol rinse, a methanol rinse, and a DI water rinse and soak. This step is usually not necessary for substrates supplied as polished wafers. After degreasing and a DI rinse, the shelf oxide is first removed by dipping
146 Compound Semiconductors in HCl followed by a DI rinse. This is followed by a free etch in H,SO,:H,O,:H,O with typical ratios varying from 3-lO:l:l, with 5:l:l being normal. The hydrogen peroxide is 30% strength. This mixture is exothermic and the etching rate is higher for higher temperatures. The etching is usually performed several minutes after the mixture has been made (at about 50-60 “C). The hydrogen peroxide can be added after the acid-water mixture has cooled and before the substrate etch. A few minutes soak results in successive formation and dissociation of oxide, resulting in the removal of about 10-25 urn of GaAs, and leaving a smooth surface. This is followed by a thorough rinse in DI water. An additional HCl etch may be followed to remove any remaining thick oxide from the previous etch. The final wet step is the DI rinse which results in the formation of a thin native oxide which remains stable when kept in stagnant water. The wafer is finally dried either using a nitrogen gun or by spin drying, as pointed out above. The substrate is then mounted on a MO block with molten In, which results in heating the substrate to 150°C for about one minute. This heating, when performed in air, results in an additional oxide layer which is more stable. Alternatively, the dried substrate is directly mounted on a MO ring supported gently on the edge either by Ta wires or a loosely fitted collar ring. This leaves the back of the substrate exposed for direct radiation heating. It is reported that heating the substrate in controlled dry N2 and 0, mixture to 300°C for 3-5 minutes results in a more reproducible oxide and helps reduce surface-related oval defects to 300 cm-* or less.t18gl In any case, the thin oxide layer is a crucial protection as it prevents bonding of the contaminants in air such as CO and CO, to the GaAs surface. (The oxide is removed in the growth chamber revealing atomically clean GaAs surface prior to the growth.) The wafers are then quickly loaded in the MBE load lock chamber. InP Substrates: In many respect InP preparation is similar to GaAs. Extra care must be exercised during polishing and handling of InP since it is much “softer” than GaAs. The Br-methanol polishing is sometimes applied even if they are already received in a polished form. To remove the shelf oxide, a free dip in dilute (0.3%) Br-methanol is used. The substrate is then rinsed in methanol and DI water, followed by an etch in H,SO,:H,O,:H,O. Some authors use a 7: 1: 1 for 30 set, followed by DI water rinse and drying.llgol Others use 10 min etch in cooled 4: 1:1 mixture followed by DI water rinse, 3 min. etch in Br-methanol and final DI water rinse and drying.171
Molecular Beam Epitaxy 147 9.2
Substrate Preparation in the MBE System
After the substrates are loaded in the load lock chamber and a reasonably high vacuum is achieved (about loss torr), the substrates and the MO blocks are outgassed to about 200°C in the load lock to desorb most of the water vapor and other gases which are loosely bonded to the protective oxide. This and subsequent steps are presented in Fig. 28. The substrates are then transferred to the buffer or preparation/analysis chamber for additional outgassing at about 300°C from 10 min to 2 hrs to f&her remove water vapor and other gases. The substrate is then transferred to the growth chamber. The GaAs substrate is heated to 580-620°C for several minutes in the presence of As beam (0.5 to 1 x 10m5torr at the substrate) to remove the thin protective oxide and reveal the atomically clean GaAs. This process is monitored with RHEED. The presence of the group V beam is to prevent the GaAs surface from thermally decomposing (thermal etching, pitting or the formation of Ga or In droplets due to preferential desorption of group V elements). As shown by in situ Auger studies,[881-[901 the oxide film consists mainly of As,O, and G+O, which decompose and desorb at around 350°C and 550-58O”C, respectively. In the case of InP, the oxide removal is achieved at a lower temperature of about 5 10°C under a higher flux of As, (>3 x IO” torr or 10” As/cm* set) or P, flux. The P20s and As,O, decompose and desorb at around 36O’C and 460°C respectively. InP substrate surface cleans up at about 500°C and its surface starts to decompose at about 550°C.[901 Initially the RHEED pattern of the oxide has a diffuse pattern characteristic of an amorphous film. As the oxide starts to desorb, a spotty pattern will appear which will gradually give way to elongated streaks characteristic of atomically clean and smooth surface. Although the degreasing and DI water rinsing steps may seem trivial, the success of the following steps and the growth depends critically on them. Before the onset of growth, the substrate has to be atomically clean, free of oxides and other contaminants, free of defects, heated to the right temperature range, and possess the proper surface reconstruction. Some residual contaminants due to previous substrate handling and packaging may prove to be too stubborn. Even in the highest resistivity DI water, there may be bacteria, their remnants, or other particulates. All of these can adversely affect the final substrate surface and render the substrate useless. If stubborn oxides or carbon contamination is present, the transition to atomically clean surface will not be complete and faceting may occur, as evidenced by a crows’ feet
148
Compound Semiconductors
pattern. For properly prepared substrates, a streaky pattern will emerge, and at this stage growth can commence. As the growth progresses, the surface becomes smoother and the streaks get longer. As discussed in Sec. 5, a great deal can be learned from RHEED and RHEED intensity oscillations about surface reconstruction and growth mechanism.
1
GROWTH CHAMBER
OSCILLATION
1
-I
GROWTH RATE AND COUPOSmON CALIBRATION
I
4
I SELECTCELL TEYPERTATURES
I HEAT SUBSTRATE TO3OOC
I OPEN & SHUTTER MONITOR 1 WITH PYROMETER
RAISE SUBSTRATE TEMPERANRE
I
CHECK/ADJUST
BEGIN GROWTH
Figure 28. compounds.
Schematic diagram of steps involved in preparation of MBE
growth of I&V
Molecular Beam Epitaxy 9.3
149
MBE Growth
After oxide removal, the substrate temperature is adjusted to the proper value and group III and the dopant shutters are opened. Computer control can be used to program desired composition and doping profiles. Real-time monitoring equipment can be used to ensure proper growth, as discussed in Sec. 8. In the initial stages of the growth, it is sometimes advantageous to grow smoothing layers, such as superlattices or MEE layers, or use growth interruptions. These layers lead to sharper RHEED patterns. Growth and composition calibrations can be done prior to the growth using RHEED intensity oscillations. After the initial stages of growth, the surface must be maintained at proper conditions for the growth to proceed as smooth monolayer-by-monolayer epitaxy. The surface reconstruction depends on the substrate material, substrate orientation, substrate temperature, and material fluxes. As different layers are grown, the group V and substrate temperature must be adjusted to optimize the growth. Realtime monitoring such as desorption mass spectrometry or optical methods can be’used to fine-tune the growth.
10.0 POST-GROWTH
CHARACTERIZATION
There are many techniques for post-growth characterization of the MBE layers. These techniques give valuable information on the various properties of the epilayers and interfaces which can then be correlated with the growth conditions. The various techniques can roughly be divided into structural, electrical, and optical. In some cases, different techniques can be used to obtain the same information. For example, the thickness of GaAs quantum wells (less than a few hundred A thick) surrounded by AlGaAs layers can be measured directly using cross-sectional TEM. This technique is cumbersome and time-consuming but gives direct and absolute values. A second method is low temperature photoluminescence which is simpler and quicker. In this method, the quantum-confined energy shift from bulk GaAs is measured and the thickness of the quantum well thickness is inferred from a model (which must include the excitons), or from direct calibration curves previously obtained from correlating this shift with the thicknesses obtained from cross-sectional TEM on a calibration set of samples. The interface roughness (between GaAs and AlGaAs) may be studied using cross-sectional TEM, chemical lattice imaging,l1g1l or high resolution
150 Compound Semiconductors photoluminescence mapping of exciton energy, linewidth, and splitting.l13gl Finally, carrier concentration can be determined either by resistivity and Hall measurement, or by studying the photoluminescence linewidth and peak shift. The most important of the post-growth characterization techniques are as follows. Excellent reviews of many of these techniques are presented by Herman and Sitter,li”I and by various experts collected in a book edited by Stradling and Klipstein.11g21 10.1 Structural/Compositional Structural information such as morphology, layer thickness, composition, crystallinity, and interface and defect structure can be obtained using phase contrast optical microscopy, scanning electron microscopy, transmission electron microscopy (both planar and cross-sectional), lattice imaging, scanning tunneling microscopy (both planar and cross-sectional), secondary ion mass spectrometry (SIMS), x-ray diffraction (single crystal, double crystal, rocking curve), Auger electron spectroscopy, x-ray photoelectron spectroscopy (XPS), Rutherford backscattering, low energy electron diffraction (LEED), and positron annihilation spectroscopy (PAS).[ig31 Perhaps the most often used technique in this category is x-ray diffraction (XRD). With XRD rocking curves, one can determine the lattice mismatch of the epilayer and the substrate (from the peak shifts) and hence the composition. From the peak width, one can get a measure of the degree of crystalhnity. For (100) wafers, the [5 1 l] di&tction geometry penetrates more and is useful for thicker layers. The [422] diffraction geometry is more at a glancing angle and is more sensitive to the crystalline quality of the upper layers. In case of small lattice mismatch, double crystal XRD is preferred. High resolution XRD, which involves double or triple crystal diffraction, is an extremely sensitive technique for measurement of multiple quantum wells and superlattices.11g4l 10.2
Electrical and Magneto-Transport
Resistivity and Hall mobility (both gated and ungated) is used extensively for the determination of carrier type, concentration, mobility, and compensation. Other magneto-transport measurements, such as Shubnikovde Haas oscillations are used to determine carrier concentration and dimensionality of carrier confinement. Capacitance-voltage (CV) measurements are used for determination of doping concentration and bandgap
Molecular Beam l?pita.xy 151 misalignments in heterostructures. llg51 A more elaborate version, namely deep level transient spectroscopy (DLTS) is used for the determination of trap energies, concentrations, and lifetimes. Photoconductivity is used for the determination of carrier transport properties. 10.3 Optical and Infrared Spectroscopy Optical and infrared spectroscopy provides a large variety of extremely powerful techniques for the characterization of thin films. These techniques include absorption, photohuninescence (PL), photoluminescence excitation (PLE), electroreflectance (ER), photoreflectance, time-resolved photoluminescence, Raman, spectroscopic ellipsometry, magnetoabsorption, magnetoreflection, magnetophotoluminescence, and photothermal deflection. These techniques provide a wide range of valuable quantitative and qualitative information about the epilayers. These include band structure (energy gaps, effective masses, band curvatures, energy vs crystal momentum dispersions in different directions, densities of state), composition, thickness, impurity identification and concentration, interface roughness, exciton binding energy, quantum confined energies, strain optical transition energies and matrix elements, optical constants, and surface and interface electric fields. Studies of excitons by high resolution spectroscopy is particularly useful for the study of quantum well interfaces.11g61~11ggl Photoreflectance and differential photoreflectance are useful tools to characterize the doping in epilayers, characterize surface electric fields or characterize buried quantum we11s.~2001-12021 Fourier transform infrared spectrometry can be used to characterize inter-subband transition energies in quantum wells for band offset measurements or characterization of photovoltaic detectors.12031-t2051It can also be used to determine minisubband transition energies and dispersions in superlattices.1206112071 Photothermal deflection spectroscopy is a sensitive method for determining quantum well energies before or after layer disordering.l2o8l Room temperature infrared absorption or photocurrent spectroscopy can be used to characterize excitonic transitions in multiple quantum well p-i-n electroabsorption modulators.l*Ogl-l*lil 10.4
Structural Defects in III-V Compound Epilayers
An important issue in epitaxial growth is the minimization or elimination of structural defects. Defects can appear in homomorphic epitaxy
152 Compound Semiconductors (lattice-matched epilayers of the same family), pseudomorphic epitaxy (lattice-mismatched compounds of the same family such as III-V/III-V, IIVI/II-VI, SiGe/Si, etc.) or heteroepitaxy (layers of different families such as III-V on Si and II-VI on III-V). No attempt is made here to give a comprehensive or quantitative account, only to list some of the important defects and their features in a qualitative manner. A comprehensive treatment of this topic appears in a recent volume of Semiconductors and Semimetals. f2121Of special interest is Ch. 9 by Liliental-Weber. Certain defects can be caused by nonuniform heating or mechanical stresses on the substrate due to improper mounting. With proper hardware design, these could easily be minimized or eliminated. The most common defects encountered in the growth of GaAs on GaAs are oval defects, which are typically 1-15 pm long along [ liO] and their density is in the range lo2 to lo5 per cm2. There are generally two groups of oval defects, one with and one without a core. The latter is believed to be due to particulates landing on the substrate during substrate preparation, loading, transferring or growth. The former group generally has a polycrystalline core. Most investigators believe that these are Ga related and are caused by Ga spitting and/or Ga oxides, and are somewhat controlled by growth conditions. Therefore, the oval defects can be minimized by proper substrate handling, by elimination of leaks and other sources of oxygen, by using Ga and In furnaces with higher temperature lips to eliminate Ga and In droplets, and by elimination of As spitting by using crackers and moderate growth rates. It appears that the Ga-related oval defect are absent in MOMBE since Ga droplets and oxides are absent. Another kind of defect is encountered in the growth of GaAs, AlGaAs, or InGaAs at low temperature (<300°C) due to excess As uniformly incorporated to form a non-stoichiometric epitaxial layer.12131-[2161 When these epilayers are annealed the excess As coalesces into metallic arsenic clusters imbedded in a III-V crystalline matrix. The tendency of the cluster formation seems to depend on doping and whether the layers contain Al or not. The nature of defects in materials grown by low temperature MBE seem to present certain advantages: they are high resistivity layers which can be grown epitaxially; under certain conditions these materials can be photoconductive with extremely short (sub-picosecond) carrier lifetimes; and depending on the heterostructure composition and doping, clusters can be engineered to appear preferentially in certain layers.
Molecular Beam Epitaxy 153 In growing heterostructures, several kinds of defects can be encountered, due to differences in lattice constants, differences in thermal expansion coefficients, and defects present on the substrate. In the growth of strained-layer III-V on III-V compounds or for Si/Ge, if the alternate layers are kept below a certain critical thickness, the strains may be elastically accommodated leading to defect-free structures with certain advantages discussed in Sec. 11.3. The most dramatic advantage is in Si/Ge superlattices where a direct bandgap structure can result from indirect bandgap material. Combining the advantages of III-V optoelectronic structures with Si electronics has motivated the growth of III-V compounds on Si substrate, which has the added advantage of higher thermal conductivity and better material strength as substrate. This is, however, complicated by the large lattice mismatch (4%), different thermal expansion coefficients, and polar on nonpolar epitaxy with the associated twinning due to anti-phase domains. Clever schemes have been implemented in overcoming some of these problems, and recent progress in this important technology is reported elsewhere.12i71 11.0 BUILDING BLOCKS OF MODERN DEVICES: BANDGAP ENGINEERING IN III-V STRUCTURES As discussed in the beginning, bandgap engineering is a powerful technique for the design of new semiconductor structures and devices. Early suggestions for using heterojunctions to improve semiconductor devices appear in the transistor patent by Shockley.12181The concept of a compositionally-graded semiconductor was proposed by Kroemer a few years later.121gl It was suggested that by spatially varying the composition, the bandgap can be varied spatially, resulting in an internal quasi-electric field. This is the simplest and earliest example of bandgap engineering. After the demonstration of the homojunction semiconductor laser in the early 1960’s, Kroemer suggested that electron and hole confinement in a narrower bandgap region clad by wider bandgap heterojunction barriers would result in population inversion and laser action at much lower current densities.l220l The advent of MBE has led to inception and implementation of many other ideas for manipulating the band structure and interface properties and thereby, transport and optical properties of semiconductors by various researchers. A number of these ideas have been described and implemented
154
Compound Semiconductors
by Capasso and coworkers. [~1[~W[2211[2221 gap engineering are listed below.
The e
ingredients
for band-
11.1 Doping The most basic is uniform p-n or p-i-n junctions in otherwise uniform semiconductors. The other is modulation doping or selective doping in conjunction with heterostructures in which case the wider bandgap material is doped and the narrower one undoped, leading to formation of a triangularshaped quantum well confining the charge carriers to move along the interface (similar to inversion layers in Si-SiO,). This results in a quantized 2-D electron (or hole) gas with much improved mobility, leading to high electron (or hole) mobility transistors. Other possibilities are n-i-p-i doping superlattices in either uniform composition or heterostructures resulting in novel optical and transport properties, such as optically tunable bandgap and long band-to-band recombination lifetime.[2231[2241Planar or delta doping,t225jas well as graded doping provide additional degrees of flexibility in bandgap engineering. An interesting concept in bandgap engineering is the elimination of conduction or valance band discontinuity by combining bandgap grading in conjunction with modulation doping.t2261 A recent account of fundamental issues and the state of the art regarding doping and its applications in bandgap engineering is presented in a pedagogical manner in a recent book by Schubert.[2271 11.2 Quantum Wells and Superlattices A semiconductor single quantum well (SQW) is formed when a thin (less than a few hundred A thick) layer of semiconductor W (well) is grown between two layers of semiconductor B (barriers) which has a larger bandgap (resulting in conduction and valance band misalignment or offset). The semiconductors W and B could be binary, ternary, quaternary or pentanary alloys. When there is a repeating sequence of W and B layers, we have a multiple quantum well (MQW). When W and B are sufficiently thin, the wavefunctions of the charge carriers (electrons and holes) in adjacent wells can penetrate the barrier layers and couple to one another forming a superlattice (SL) with new properties not available in the bulk semiconductors of W or B. Heterointerfaces, quantum wells and superlattices are generally formed by choosing W and B with the same crystal structure but different band parameters, and consequently different optical and electrical
Molecular Beam Epitaxy
155
properties. Heterointerfkces can be classified in four types leading to four different types of MQWs and SLs.l 2281For Type I, the conduction band edge of W is lower than that of B, while the opposite is true for the valance band edges. This results in the forbidden gap of W being located entirely in the forbidden gap of B, and both the electrons and the holes are confined on the W side of the W/B interface. Therefore, in Type I MQWs, both the electron and hole wavefunctions are in the W region and have a large overlap, leading to a large optical transition matrix element both for the interband and intersuband transitions. Furthermore, the index of refraction of the W layer is usually higher than that of the B layer (since B has a wider bandgap), also leading to the tendency of photons to be confined in the W layer. This dual confinement has important practical consequences for optoelectronic devices. Type I interfaces and MQWs are widely used for two-dimensional electron or two-dimensional hole gas structures, and a wide variety of optoelectronic devices such as lasers, modulators, and detectors. Type I materials systems include the important GaAs(W)/ Al,Ga,_$.s(B) (x < 0.45) and InGaAs(W)/InAlAs(B) systems. For Type II heterointerfaces, both the conduction and the valence band edges of W are lower than the values for the B semiconductor. Type I alignments result in confinement of both electrons and holes in the W side of a W/B interface, whereas in Type II, holes are confined on the B side and electrons on the W side. In Type II-staggered (e.g., GaAs/AlAs), the forbidden gaps of W and B overlap partially, whereas in Type II-misaligned (e.g., InAs/GaSb), the forbidden gaps do not overlap. In both cases, one can obtain two-dimensional electron and hole confinement at the interface simultaneously; the electrons are in the W side and the holes in the B side of the interface. In Type II-staggered at the interface, the electrons are a higher energy than the holes, whereas in Type II-misaligned the opposite is true. This results in unusual transport behavior. Type III is exemplified by HgTe-CdTe where the conduction and valance band edge of the former overlap (zero bandgap) and are in the forbidden gap of the latter. Optical properties of G&s-AlAs Type II-staggered superlattices are presented in Refs. 229 and 230. 11.3 Strained-Layer
Superlattices and Quantum Wells
Normally, W and B are chosen to have nearly identical lattice parameters (lattice-matched) to achieve perfect crystallinity. However, in recent years it has been shown that as long as the layers are sufficiently thin (less than a critical thickness), one can still maintain perfect crystallinity
156
Compound Semiconductors
without misfit dislocations even when W and B have different bulk lattice parameters. This results from coherent (elastic) in-plane biaxial strains which develop in the heterostructure to accommodate the lattice mismatch. Elastic biaxial strain (compressional or tensile) which is present in SSLs can dramatically affect the band structure (especially the valence band) in terms of energy, effective mass (and hence mobility), density of states, light hole and heavy hole splitting, interband transition matrix elements, inter-valence band transitions, and anisotropy. Optoelectronic devices such as MQW electroabsorption modulators and lasers can benefit from these effects and enhanced absorption coefficients, alteration of hole density of states, and polarization dependence in quantum wells under biaxial strain.~“~~-~u5~~21~~30~ 11.4 Bandgap Grading and Chirped Superlattices Bandgap grading offers many advantages in device performance especially for bipolar junction transistors, avalanche photodetectors,[2211[1881 and semiconductor lasers.[z61 This is achieved by changing the furnace temperatures in a precise manner to affect a desired flux and hence composition profile. This puts stringent requirements on thermal response of the furnaces and becomes impractical for large grading over small thicknesses. An alternative is to use chirped superlattices. These are short period superlattices where the period is kept constant but the thickness of GaAs is reduced while that of AlAs is increased from one period to the next (or vice versa). This was pioneered by Gossard and coworkers in the growth of a structure simulating a parabo1a.r2371 Recently we have implemented this idea to incorporate linear grading in the wells of a multiple quantum well PIN electroabsorption modulator and have observed effects associated with prepolarization of excitons, leading to higher sensitivity of the quantum confined Stark shift to external bias field.t211j
12.0 EPILOGUE
Molecular beam epitaxy is an exciting and fruitful scientific and technological activity which has drawn upon a tremendous pool of talent and vision for its longevity. Year after year exciting developments have been introduced and brought to fruition. The future looks prosperous with good prospect for development of multiwafer growth, valved crackers for precision control of group V elements, improvements in precursors for gas
Molecular Beam Epitaxy
157
source MBE, and more robust and reliable in situ monitoring techniques for closed loop control of the growth, such as desorption mass spectrometry and optical techniques. Combining the best of III-V compounds and Si using heteroepitaxy is another area of potential growth. Sophisticated interface characterization techniques, such as scanning tunneling microscopy and high resolution x-ray techniques for chemical analysis are paving the way for better understanding and control of interfaces. As mentioned earlier, the continued success of MBE depends on the same principles that started it: fundamental surface and interface science, combined with practical device development.
ACKNOWLEDGMENTS I am deeply indebted to A. Y. Cho for his guidance and advice, generously sharing of his insight and enthusiastic support over the years. I would like to thank P. Holloway for many useful suggestions. I would like to thank my family for their patience and support. Partial support of Texas Higher Education Coordinating Board Advanced Research and Advanced Technology Program, NSF, ARO, and DOE is gratefully acknowledged.
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Physical and Chemical Deposition of Metals as Ohmic Contacts to InP and Related Materials Avlshay Katz
1.0
INTRODUCTION
Practically all semiconductor electronic and photonic devices receive and transmit power and signals through metallic contacts, which connect them to the external circuitry. Furthermore, an ohmic contact performs as an electrical communication link between the active region of the semiconductor device and the external circuit, which allows for a low-energy carrier transport mechanism through the contact volume and ensures a negligible voltage drop across it. Practically, ohmic contacts are to be considered and evaluated as narrow-barrier-width metal-semiconductor Schottky barriers, through which the majority of the carriers are tunnel-injected, enhanced by high dopant concentration in the interface region. Typically, these contacts are characterized by low Schottky barrier heights (up to about 0.4 eV) and present an almost linear relationship between the measured current and the voltage applied across the contact.11112j The processing parameters and performance of the metal-semiconductor structures, such as ohmic contacts, have been thoroughly studied due to their essential role in the performance of electronic and photonic devices. 170
Deposition of Metals as Ohmic Contacts to InP
171
These tremendous efforts resulted in significant improvement, both in the processing of high-precision nanostructure, highquality contacts, and in yielding an improved physical, electronic, and mechanical properties of the metal-semiconductor joint. This progress allowed to develop and manufacture high performance and high reliable ohmic contacts, which are essential for the operation of InP-based various electronic devices, such as field effect transistor (FET),131141junction field effect transistors (JFET),t41t51 high electron mobility transistor (HEMT), and heterojunction bipolar transistor (HBT),171181as well as for photonic devices such as long-wavelength laser diodes,lgll10l light-emitting diodes (LED),llil-[I31 and solar cells.I14l Yet, in spite of the achievements in processing high-quality ohmic contacts and controlling the mechanical, metallurgical, thermodynamic, kinetics, and electrical properties of the metal-semiconductor reacted interface, a relatively slim theoretical and practical understanding has been demonstrated in actually explaining and engineering the design of the Schottky barrier height and its formation mechanism.115ll16l The lack of knowledge, and in particular, the somewhat controversial experimental results which have not provided a clear correlation between the routinely measured metal-semiconductor contact properties such as the barrier height and the metal work functions, were interpreted in some theoretical models. One of these is a well structured model suggesting the Fermi-level pining formed as a result of inter-facial electronic states induced by mechanical defects1171-11gl and metal induced gap states (MIGS),1201-122jto be the origin for the above discrepancy. 1231124jThis mechanism suggests only a weak, second-order dependence of the Schottky barrier height in the metal-semiconductor system on the interfacial atomic structure, and thus, on the overall interfacial metallurgical reactions. Recent experimental results and, in particular, the excellent studies on epitaxial metal-semiconductor interfaces opposed the above theoretical mechanism, and actually demonstrated the importance of the interface structure on the nature of the Schottky barrier.1251-1271 This approach appeals more to those individuals who have processed, hands-on, metalsemiconductor contacts and experienced the obvious influence of the various processing parameters on the inter-facial nature and, as a result, on the contact performance. The direct correlation between the interfacial shape and the Schottky barrier height, however, is a complicated matter to study and analyze, in particular, when dealing with metal III-V contacts. This is mainly due to the polycrystallinity and other crystalline imperfections at the metal and the reactive semiconductor interface, which impose severe
172
Compound Semiconductors
constraints on trying to match a theoretical model to the experimentally observed data. In addition, the reacted interface has an nonuniform structure which eliminates the direct execution of the well-discussed theoretical models. It has to be emphasized that the accumulated experimental data clearly show that the nature and properties of ohmic contacts to III-V semiconductors, and in particular the InP, depend on several variables, thus suggesting that the metallurgical reactions, which have a major role in defining the Schottky barrier height and other electrical properties of the contact, can proceed even at room temperature.t2glt301 This nonuniform interface structure suggests an inhomogeneity in the Schottky barrier height across such a metal-semiconductor interface, which may be account for the abnormal phenomena described by the various complicated theories.t311t321 Practically, the academic debate regarding the origins of the Schottky barrier height and the metal-semiconductor interfacial electrical properties does not influence the successful application of various low resistance metal-semiconductor ohmic contacts to electronic and photonic devices. Smart choice of metallurgical schemes, correct selection of doping levels of the semiconductors, and well-established processing technologies allow for the fabrication of excellent ohmic contacts to satisfy the device needs. As the dimensions of ultra large-scale integration devices continue to decrease, further stringent requirements are being imposed on the material, processing, and electrical performance of low-resistance metal-semiconductor contacts. Thus, in spite of it not being a major “show stopper” at the present, understanding of the fundamental mechanism and concepts of ohmic contact design and, in particular, the metal microprocessing demands, are essential to ensure that the metallization technology will keep up with the advanced microelectronic device design and manufacturing, and will not impose limitations on its rapid development.
2.0
FUNDAMENTALS
OF OHMIC
CONTACTS
This chapter reviews recent works that provide a summary of the current knowledge regarding the technology for manufacturing ohmic contacts to InP-based materials. Since we are interested, in particular, in improving the contact technology for I&based photo& devices, some examples from this arena are used. The correlation between the metallurgical phenomena and process parameters, and the contact electrical properties is emphasized. Other comprehensive reviews are recommended to the
Deposition of Metals as Ohmic Contacts to InP
173
reader in order to contribute to understanding the metal-InP ohmic contact fundamentals. 2.1
Generic Definition of Schottky Barrier Height
The most illustrative way of presenting the Schottky barrier phenomena is through the energy band diagram. Figure 1(a) provides an interfacial metal-nondegenerated n-type semiconductor band diagram at zero bias. The Schottky barrier height flat-band for the n-type semiconductor (On&, is the difference between the conduction band minimum (CBM) and the Fermi level, and is defined thus as %
(1)
Qnso E EC - Ef
Similarly, Schottky barrier height flat band for the p-type semiconductor ((I$& is the difference between the Fermi level and the valence band maximum (VBM), and is shown in Fig. l(b). l---W-4
n-TYPE SEMICONDUCTOR
p-TYPE SEMICONDUCTOR (W
I-w4
Figure 1. Interfacial metal-semiconductor band diagram, for (a) n-type semiconductor, and (ZJ)p-type smiconductor, in the absence of an applied bias. In (c), the Schottky barrier height, the quasi-Fermi level position, and the band diagram for a metal/n-type semiconductor under an applied forward bias are given.
174
Compound Semiconductors
It is well known that the interfacial Fermi-level position of any metalsemiconductor system is generally regarded as being independent of the dopant type and concentration of the semiconductor. Thus, the sum of the two Schottky barrier height flat bands is simply the bandgap.
Eq.(2)
@B,,o + @BPo
=
Eg
For uniformly doped n-type semiconductors, the electric potential at the metal-semiconductor interface is governed by Poisson’s equation, and the potential of the Schottky barrier height has to be defined with respect to the Fermi-level of the metal, within the depletion approximation as shown in Fig. l(c) Eq. (3)
V(z) = Vd( l- z/w)~ + Vn + Va
O
where Va is the applied bias, Vn is the difference between CBM and Fermilevel, Vd is the total band-bending, given by Eq. (4)
Vd=@n&,
-Vn-Va
and W is the depletion region width, given as
Eq. (5)
w=
= (2qVd)”
where q = &,/(qND). The maximum electrical field near the metal-semiconductor interface is given, thus, by
Eq.(6) By implementing some changes in the relevant subscripts, all these equations may be applied also to the metal/p-type semiconductor interface.
Deposition of Metals as Ohmic Contacts to InP 2.2
175
Interface States and Fermi-Level Pinning
Originally, the Schottky barrier height between a metal with a work function (@,) and an n-type semiconductor with an electron affinity of (x0) isP71
Eq. (7) as is schematically shown in Fig. 2(a). However, it was experimentally observed that the Schottky barrier heights are less dependent on the metal work function than the prediction above. These results originated the discussion about the existence of Fermi-level pinning by interface states. The lack of a metal dependence of a measured Schottky barrier height on the electronic states was first suggested by Bardeen.[231 In his view, the pinning of the Fermi-level by states in the semiconductor surface occur prior to bringing into contact the metal and the semiconductor, which will subsequently lead, simply, to a lineup of the two Fermi-levels, and then to the formation of Schottky barrier height which is independent of the metal, as shown in Fig. 2(b). Bardeen’s model involves no interaction at the interface and thus is only applicable upon formation of abrupt interfaces, which are unlikely to be formed. In addition, this model assumes another unrealistic situation of a uniform distribution of the interface states (D,) and then the expected Schottky barrier height as a function of the metal work function is given[WI401
Eq.(8) where the parameter
J%. (9)
yis is given by
yis=
(1+= %
-1 1
Following along this discussion, ~11m. is the charge neutrality level of the interface states, related to the known S-parameter.[42~[431 Since interface states are assumed to be independent of the metal, Eq. (8) suggests a dependence of the Schottky barrier height on the applied bias similar to that on the metal work function. The product D,d is a critical parameter for both the Bardeen model, while yis = 0 imposes a limited value of D, = co, and the Schottky mode (see Eq. 7), while D, gains the value of 0 for the same yis value.
176
Compound Semiconductors
(b) CBM
&J"-, +*
_
---
EF VBM
EF
‘?---tlNTERFACE LAYER
w
I--
@rn EF -I
Figure 2. Band diagrams before (left panel) and after (right panel) the metal and the ntype semiconductor are brought into contact. The diagram in (a) corresponds to the noninteracting Schottky model, and (b) represents the situation when the semiconductor Fermi level is pinned by surface states before metallization. A dielectric layer is assumed to be present at the subsequent MS interface to take up the difference in the two Fermi levels. The condition in (c) is an intimate metal-semiconductor interface, with short-range band bending due to penetration of metal-semiconductor interfacial pinning states into the semiconductor. In (c), the effective electrical interface (position of maximum electrical potential) is located in the semiconductor, at some distance from the metallurgical metalsemiconductor interface. The diagram in (c) is sometimes referred to as the negative charge model. Image-force lowering is not included in these drawings (the upward bandbending at the interface in (c) is not due to image-force lowering).
Then, the interface state charge can be calculated: [441[451
Qss=Qr[exp( -mBi’o j-l] where Qf and E, are constants.
Deposition
of Metals as Ohmic Contacts to InP
177
The interface state charge is assumed to penetrate a negligible distance into the metal, while compared to the penetration extended into the semiconductor, and thus, any potential variation inside the metal is usually ignored. Thus, by defining the single decay length h, (usually assumed to be 5-20 A) and the D,, one can determine the actual band-bending as is shown in Fig 2(~).1~~11~~1 In view of the above theories, it is interesting that, for a metalsemiconductor interfacial pinning state-derived band diagram, the interface is actually defined inside the semiconductor, away from the real metallurgical interface, as is shown in Fig. 2(c). The influenced short-range band bending, which is considered as a compound in the Schottky barrier formation mechanism, varies dependently on the executed metal in a way that apparently makes the Schottky barrier height insensitive to the metal work function. 2.3
Determination of Schottky Barrier Height An accepted definition of the junction current is
Eq.(11)
I(Va) = I, exp [ &J-l]
where I,, the saturation theory:
Eq. (12)
current,
is defined by the thermionic
= A*AT2
emission
eXp(-B@B,)
where A* is the Richardson constant, A is the area of the diode, and B = 9/ (KnT), n is the ideality factor, and n = 1 is a value predicted by the thermionic emission theory. When the Schottky barrier height is homogeneous, @nn may be identified as the Schottky barrier height for n-type semiconductors, and mu,, for p-type semiconductors.
178 Compound Semiconductors 2.4
Determination Materials
of Ohmic Contact Parameters InP and Related
As detailed in the following sections, the metal/M-related material systems are extremely reactive, leading to the formation of complicated interfacial microstructure regardless of the applied metals, through the thermal processes associated with the contact manufacturing sequence; so the commonly used simplified approach of the state independence on the interface structure is apparently not applicable for the metal&P contact properties calculation. It will be assumed through this manuscript that the carrier transport nature, particularly in the case of ohmic contacts to InP, is solely determined by the interfacial microstructure. This postulation is backed up with a large amount of experimental results, showing that the specific contact resistance can be reduced by several orders of magnitude simply by optimizing the thermal processing conditions to achieve a low-resistance microstructure.1481[491The metal/W interfacial microstructure contains various different crystalline compounds of metal and groups III or V elements, each having different carrier-conduction properties. In addition, they exhibit various geometrical shapes and distributions at the interface, and are associated with massive crystalline defects generated because of the structural incompatibility. Thus, the electrical properties of this interface cannot be described by directly applying one of the classical approaches, such as the Schottky or tunneling barrier theories, 111which are based on the assumption of a chemically abrupt and structurally uniform interface. For these, the correlation between the contact resistance and the processing parameters, such as the semiconductor carrier concentration and the sintering temperature, was defined for the two basic carrier transport mechanisms at the metal-semiconductor contact interface. For the thermionic-emission case Eq. (131
R, =
W(a*VI ex~Kq%Y(W1
and for the tunneling case
Eq. (141
R, - exp
Deposition of Metals as Ohmic Contacts to InP
179
where 0, is the Schottky barrier height at the metal-semiconductor interface, K is the Boltzmamr constant, T is the absolute temperature, N is the carrier concentration, q is the magnitude of the electrical charge, e is the semiconductor permittivity, m* is the effective mass, a* the is Richardson constant, and tt is Planck’s constant divided by 27~. By evaluating the exponential dependence of the contact resistance as a function of either the reciprocal temperature or the doping concentration, the primary mode of the carrier transport mechanisms across the interfacial barrier may be defined. However, in order to properly describe the carrier transport across the interfaces of the metal/InP contacts, it is necessary to take into account the effect of the nonuniform, degraded, and complicated inter-facial microstructure. Unless both the doped or alloyed inter-facial semiconductor layers and the metallic contacted layers are grown in-situ to complete the contact formation without exposing it to the atmosphere, by means of, for example, molecular beam epitaxy (MBE)[50J[51J or metalorganic chemical vapor deposition (MOCVD),t52J the above-mentioned approach is essential in order to understand the inter-facial transport mechanisms. Thus, a phenomenological theory, based on the existence of a simultaneous parallel carrier-conduction processes across the interface was suggested[53J-[55Jand formulated, in order to explain, in a semiquantitative manner, the temperature dependence of the specific contact resistance and the interfacial microstructure of metal/I&based materials, formed under different sintering conditions. An essential microstructure parameter was introduced in order to account for the effect of the interfacial microstructure on the carrier transport process. Based on multiple parallel carrier-transport mechanisms, the specific contact resistance of an ohmic contact is given by
where Xi = AilA is the fraction for the inter-facial area occupied by the i, compound, ji(fi) is the structural parameter of the i, compound, and T is the absolute temperature. For a nearly ideal interface, where the carrier transport mechanism is dominated by a single thermionic emission process, R, reduces to a single term, since Xi = 0 , and thus
Eq.(16)
k=
k
J(f)PT
exp 2
180
Compound Semiconductors
or hlkT=hl
Eq. (17)
k j(fN
+p6B kT
Thus, for a carrier transport process dominated by the thermionic emission mechanism,[131 linear relationship between ln(kT) and l/T should be observed, as was measured, for example, for P~R~/II+,,~G~,,,A~ as deposited contacts (see Fig. 3). For this contact, the barrier height was calculated to be 0.13 eV, and the corresponding microstructure f&tor to be 0.29 A*K-2xxn-2.
Pt(75nm)lTi
E . 104 >
@k i
(50nm)llnGaAs(Zn RTP30s
5x 10’3cm-3)
/
+tJ CI:
*ALL CONTACTS ARE OHMIC
/‘O ,O
, 0-z 3
21.25i
2.50
2.75
3.00
3.25
3.50
1000/T (K-l) Figure 3. Natural logarithm (Ln) of specific contact resistance multiplied by temperature f&T) as a function of l/T of as-deposited WTih,~~,Ga,,~,7As (Zndoped 5 x 1018cm-3) sample and after RTP at different temperatures.
Deposition
of Metals as Ohmic Contacts to InP
181
The sharp decrease in the specific contact resistance of the PVIi/ InGaAs sample, with the increase in the rapid thermal processing (RTP) temperature up to 450”C,1561 indicated the development of a new, lowcontact resistance, interfacial microstructure. The interface for elevated temperatures contains multiregime regions, and is, therefore, dominated by different carrier transport properties. Thus, the overall carrier transport mechanism could no longer be described by a single process, as for the asdeposited contact, and a deviation from the linearity in the hr(RT) vs. l/T curve was expected. Empirically, it was found that introducing only one temperature-independent component in Eq. (15) was essential in order to fit The implication was that the carrier the measured data to the theory. transport mechanism across the newly developed interfacial microstructure was dominated by the field-emission process. For simplification, the introduction of the possible existing thermionic-field emission process parameters can be avoided. If (X) and (1 - X) describe fraction of the interfacial areas occupied by the original and the newly-developed microstructures, respectively, then Eq. (15) may be written as
Eq. (18)
R,_($+y-i
where Eq. (19) and
As shown in Fig. 4, all the measured R, versus T values of all the samples sintered by RTP at different temperatures were accurately fitted by the values calculated using Eq. (18). The parameters that were used for the best fit are listed in the inserted table. As expected, the fractional area, (1 - X), of the low R, field emission regions increased from 7% after RTP at 300°C to about 30% after RTP at 450°C. A slight change in the original microstructure, which took place with the modification of the RTP temperature, was also reflected in the increase of the structure parameter j(f). The same effect was likely to have caused the slight decrease in the & values (from 6 x 10m6LJcrn* to 4 x 10” Rem*) ), which were used in fitting the measured data.
182 Compound Semiconductors
Pt (75nm)/Ti(50nm)/InGaAs(Zn RTP 30 s
5x
10”cmd)
AS-DEPOSITED
TRTP(“C)
300
x
&,(V)
j(fl) (AK-2cm-2)
350
l-x
I$, (Qcmn)
400
T (K) Figure 4. Specific contact resistance (IQ) as a function of the measuring temperature (T) of the asdeposited WTiIIn0.53Ga0.47As (Zn-doped 5 x 10%m-3) sample and after RTP at different temperatures. The measured values (dots) and fitted values, calculated from the parallel conduction mechanism phenomenological theory (continuous line) are superimposed.
2.5
Concepts of Formation of Ohmic Contacts to InP-Based Materials
The quality of the ohmic contact is frequently described in terms of contact resistance, R, (&nm), or specific contact resistivity, P, (C2*cm-2). However, since these properties depend heavily on the semiconductor doping level, these parameters are not to be defined as fundamental metalsemiconductor interface, as the (DBqOis to a Schottky junction. At the metalsemiconductor junction, where the electron transmission is dominated by field emission, in which E, >> K,T, the specific contact resistivity is expressed as[571
Deposition of Metals as Ohmic Contacts to InP
183
Eq.(21) where E,
is a measure of the importance of tunneling, given by
Eq.(22) and m*h, is the turmeling effective mass, t5*l and c = (I/E,) hr(4@n/V,J. Experimental results in good agreement with predictions of tunneling theories have been observed in many cases. However, departures from these theories have also been frequently observed, especially at high doping levels. As pointed out in Sec. 1.0, an inhomogeneous SBH is a common phenomenon for metal/semiconductor contacts, which certainly may have a strong influence on the measured pC. The most conventional ways of forming a high semiconductor surface concentration of free carriers are by incorporating a high concentration of dopants into the initially grown epitaxial semiconductor layer, or by introducing an external dopant diffusion source, from which the dopants will be driven into the semiconductor by means of a heating process, or by ion implanting the semiconductor surface. The latter approach is rarely applied to InP and related materials because of the surface damage and loss of stoichiometry associated with bombarding the InP surface. The other two methods are widely used in the manufacturing process of ohmic contacts to I&based devices. The former method does not require a heating cycle in order to enable the migration of the dopants into the semiconductors, and thus, contacts that are processed onto such materials are frequently referred to as nonalloyed ohmic contacts. The second approach requires thermal activation in order to form the heavily doped intermixed interfacial layer, and thus, contacts to these layers are termed as alloyed contacts. These two approaches differ from each other by the kind and geometry of the metalsemiconductor interfacial related layers, and are discussed in detail later in this section. A different approach to form a metal-semiconductor ohmic contact is by applying a semiconductor with an extremely narrow bandgap, such as InAs (- 0.35 eV) which can be epitaxially grown lattice-matched to an InP substrate. This semiconductor has high electron and hole mobilities (33,000
184
Compound Semiconductors
and 460 cm2/Vs, respectively, at 300 K), and has surface states pinned in the conduction bandgap; therefore it forms an ohmic contact with almost every metal that is deposited onto it.[5gj-t61j Two major concerns have to be considered when forming ohmic contacts to InP. (a) The unstable nature of the semiconductor tends to decompose through heat treatments already at temperatures as low as 350°C, while losing the group V volatile element. This is reflected in a degraded contact interface morphology, poor edge geometry definition, and uneven penetration of both the metal and the semiconductor elements. (b) There is a fundamental difference in the nature of the n-type and the p-type InP. The energy distribution of the surface states density (NJ in InP is parabolic, with its minimum positioned near the conduction band edge and increasing toward the valence band.[62] As a result, the surface of n-type InP is only slightly depleted. This is consistent with the measured low barrier height values of most metal contacts to n-W (0.4-0.5 eV)ta3j and the high barrier for p-type InP (0.7-0.8 eV). Therefore, it should be possible to realize low resistance ohmic contacts to n-type InP, while it is a much more complicated task to identify a metal that would perform as a low barrier ohmic contact to p-type InP. When designing an ohmic contact to a high-speed I&based device, operated under a high current density and elevated-temperature conditions, a few constraints and requirements have to be met in order to provide a suitable contact technology to support both short- and long-term device operation. The main issues that have to be considered when selecting the metallization scheme and the process conditions are (a) optimizing the contact design to yield an ohmic contact with the lowest possible resistance; (b) providing stable morphology over a wide temperature range, which requires the presence of only limited inter-metallic reactions, and thus, an abrupt metal-semiconductor interface through the contact processing; (c) ensuring contact stability through the device electrical and thermal operating conditions; (d) causing no excessive stresses in the metal films, the underlying dielectric patterning layer, and the underlying semiconductor; (e) being compatible with the metal system used for the interconnection technology; and &I fabricating with a robust process that fits as an integrated step into the overall device manufacturing scheme. All the above-mentioned constraints are essential in the micron-size device technology currently applied for both electronic and photonic devices, but will be more pronounced in the future for submicron and deep submicron technologies. For this future miniaturization trend, the morpho-
Deposition of Metals as Ohmic Contacts to InP
185
logical constraints in the low-resistance contacts will be even more crucial due to the higher operating current densities. This issue, however, will be harder to achieve due to the small contact geometry definition, which depends entirely on overcoming some other obstacles, such as lithography, In addition, the more complicated and etching, and testing processes. sophisticated the overall device geometry becomes, along with the more stringent market requirements, the more important issues such as process integration within the device manufacturing sequence become. Thus, the challenge is not only to design a contact metallization that will provide a sufficient stable ohmic contact, but also to choose a metallization scheme that will withstand the multistep processing sequence and that can be used to simplify the overall device fabrication process. As an example of this trend, a stable patterned metallization scheme may be deposited in the initial stages of the device manufacturing sequence, and used to assist the realization of some other process later in the manufacturing sequence. This self-aligned concept was demonstrated using the etched-mesa buried heterostructure laser device structure, in which the metal contact tops the future mesa site and serves as a selective mask for both the mesa etching and regrowth of the blocking layers surrounding it.[641[651
3.0
DESIGN CONCEPTS CONTACT TO InP
3.1
Conceptual
OF PROCESSING
OHMIC
Assumptions
InP-based electronic and optoelectronic devices are strongly influenced, both in short and long term performance and reliability, by the quality of their ohmic contacts. It is most sensitive to the contact which is in the immediate vicinity of the active layer, whether it is a p-type or n-type contact, and thus, more attention has to be paid to these contact properties. Correct design of the ohmic contacts to these devices has to take into consideration the following processing issues: selection of the metallization scheme to form pure ohmic contacts, having the lowest possible sheet resistance, and thus, contributing minimum value to the overall contact resistance; creating a stable microstructure over a large processing temperature range; and tuning the deposition and the subsequent thermal process in order to lead to the formation of narrow bandgap inter-facial compounds, while introducing the lowest possible stresses into the thin metallic films.
186
Compound Semiconductors
Furthermore, one has to define the process sequence which will yield the optimum performance of many properties from the above list and successfully incorporate them into the overall device fabrication process sequence. This contact design concept is demonstrated in Fig. 5, in which postdeposition sintering temperature of Ti/Pt common ohmic contact to the front, p-type contact, and the back, n-type contact of InP laser device, should be 450°C in order to provide the lowest contact resistance stress values and yet provide a stable contact.
Pt/Ti/n-InP -5 x t0’*cm-3
-5 x t0’ecm-3 Pt/Ti/D-InGaAs %%a’
300
400
‘1 5 x 10’gcm-3
500 TEMPERATURE
600 (“C)
Figure 5. Optimization of TiLPt contact processing conditions by measuring specific contact resistance and stress values of contacts to both ptype and n-type InP-based materials in a CMBH laser device, as a function of the sintering temperature.
Any simplification in the overall device manufacturing attributed to the utilization of correct metal scheme, is certainly as a further advantage of the executed contact. Finally, a correct selection of the doped semiconductor layer adjacent to the ohmic contact metallization has to be made
sequence, considered contacting in order to
Deposition of Metals as Ohmic Contacts to InP
187
provide the highest interfacial dopant concentration, without saturating the metal-semiconductor sintered compounds which may lead to segregation. 3.2
Interfacial Reaction Concerns
The severe geometric design demands of advanced InP-based electronic and photonic devices calls for shallow and uniform interfacial layers in between the metallization scheme of choice and the semiconductor. The metal/InP ohmic contact microstructural design concepts are very similar to those suggested for metaVGaAs systems,[66j with the exception of the InP binary system being more reactive than GaAs. Capless InP begins to decompose at 350°C when heated at atmospheric pressure, as a result of out-diffusion of the group V atoms from the bulk to the surface. Thus, InP tends to decompose at much lower temperatures than GaAs during the heating cycles applied for sintering the metal-semiconductor contact. The thermodynamic, highly-reactive nature of the InP in metal/W interfaces has been widely observed, particularly in the commonly used Aubased contacts to InP. Analogous to the work on metal/GaAs, Au-based metallization schemes provide the advantage of introducing an external dopant (either p-type or n-type) source, which is alloyed into the adjacent semiconductor through solid or liquid phase reactions; however, this is done with the involvement of the Au as a stabilizer element, which eliminates dopant precipitation formation and inter-facial defect nucleation. In order to drive the needed alloying reactions that lead to the required semiconductor doping level, heat treatments in the temperature range of 350°C to 450°C are typically required, resulting in the formation of a thick metal-semiconductor inter-facial layer in between the metal and the InP substrate. This layer is typically about three times thicker than the original deposited metal layer. Even with the lack of reported thermodynamic data for the simplest metal-InP ternary systems, a lot of information can be gained with regard to the nature of these systems by studying the metal-In and metal-P binary phase diagrams, referring to the metal system involved in the contact of interest. Due to a well-known thermodynamic theorem, a ternary system that is composed of three binary eutectic systems contains at least one ternary eutectic melting point at a temperature lower than the lowest binary eutectic melting point introduced in the system. Therefore, adding elements like Be, Ge or Au as the third element to the InP binary systems reduces the melting points to even lower temperatures and contributes to its reactive nature.
188
Compound Semiconductors
In summary, the issues involved in the metallurgical and thermal processing of highquality ohmic contacts to InP and related materials are challenging and of great interest. The metallization systems of choice and the associated heat treatments have to enable and drive the required metalsemiconductor inter-facial reactions, which accounts for the decomposition of the interfacial oxides and contaminations. In addition, this combination should provide sufficient adhesion between the metal layer and the semiconductor, intermix the dopants into the semiconductor inter-facial layer, and then possibly form a variety of narrow bandgap inter-ha&l compounds.[67jt681 These reactions, however, have to be limited and controlled in order to eliminate the formation of spiky interfaces, which leads to nonuniform current density, and, thus, to the evolution of local heated spots due to Joule effects. Figure 6 demonstrates this correlation. In this case, the electroltinescence performance measured at the AuBe/p-JnP, reflected a highly leaky CMBH laser diode as opposed to the low-leak device associated with the planar Pt/TiAnGaAs contact. Thus, it is obvious that the metal-semiconductor interface morphology depends on the metallurgical system of choice and the contact process conditions (such as deposition technique and sintering conditions). Moreover, since the contact sintering process takes place at the final stage of the device manufacturing sequence, the contact sintering process may influence the entire device performance. Thus, a moderate heat treatment is essential for minimizing enhancement of various metallurgical reactions, such as spillover of dopants into the adjoining semiconductor layers (in the case of heterostructure devices), and reducing the occurrence of different interfacial reactions and diffusion processes in between those layers. 3.3
Electrical Performance Requirements
Modem high-speed electronic and photonic devices are operated under a high current density, with realistic values in the range of 4 to 10 kA/ cm2 in a narrow contact stripe geometry, typically in the range of 2 to 150 urn wide. They require a specific contact resistance lower than about 5 x 10” 0cm2 in order to add only a negligible amount to the overall device resistance. Due to the relatively large energy bandgap of JnP (Es = 1.3 eV), some rectifying characteristic, as a result of the surface Schottky barrier, is always realized. High surface dopant concentration, higher than 5 x lo’* cmm3,is occasionally applied either by ion implantation or by incorporating the relevant dopant into an epitaxially grown structure, in order to narrow
Deposition of Metals as Ohmic Contacts to InP
189
Pt/Ti AuBe
(a)
fnGaAs(P)
InP
HI()KL"AI
ptm InGaAs{P)
(b) InP
tOW~~E
Figure
6.
performance Ti/InGaAs
laser devices, Electroluminescence of highly and lowly leaking CMBH which is referred to (a) the spiky AuBe/InGaAs contact, and (b ) the planar Pt' contact,
respectively.
the associatedSchottky barrier height and to allow for enhancedtunneling. When the device geometry allows for additional epitaxial layers, it is useful to cap the layered structure with lower energy bandgap materials, such as 1no.53Gao.47 As (Eg=0.75 eV) lattice-matchedto InP, or grade an lnxGal-xAs layer to complete it with an InAs layer (Eg = 0.35 eV to 0.45 eV).[69][70]A reasonableassumption is that with such a narrow bandgap semiconductor, the Schottky barrier values of the contacts are mainly determined by the composition of the layers, in particular when using a ternary layer. Thus, for the latter case, the specific contact resistanceis a function of the InAs
190
Compound Semiconductors
mole fraction of this layer. The heavily-doped ternary layer, formed by either alloy regrowth, creating a shallow diffusing zone, ion implantation, or heavily-doped epitaxially-grown layer, provides significant advantages over highly-doped p-type and n-type InP, because of the higher thermodynamic dopant solubility limits in the material. Furthermore, the InAs exhibits pinned surface states in the conduction band, and it is therefore used extensively as an n-type contacting layer for the formation of n-type ohmic contacts [711[721 InP
is an exception to Mead’s rule, which suggests that the barrier height (@no) of n-type semiconductors equals two-thirds of the energy bandgap (Es), and that of p-type semiconductors equals one-third Es. The InP @no as measured in n-type Schottky diodes was found to be 0.48 eV for a variety of metals, such as Au, Ti, and Al.l73l Fritzche has argued that the energy distribution of N, in InP is parabolic-like, but with its minimum positioned near the conduction band edge. Thus, the InP surface is only moderately depleted. It is, therefore, easy to achieve low-resistance ohmic contacts to n-type InP . On the other hand, formation of ohmic contacts to ptype InP is much more complicated. This, in fact, plays a major role in defining some of the device structures. While n-type contacts can be formed through alloying the contact metallization directly onto the InP substrate (typically doped to level of 2 x 1017 to 2 x 1018cm-3), the p-type contacts are frequently formed onto heavily doped epitaxial layers such as InGaAs or InGaAsP. Therefore, most two-sided contact devices, such as the majority of laser diodes, are grown on n-type InP substrates, with a simple n-type ohmic contact to the substrate, and a front p-type contact formed onto a ptype contacting semiconductor layer in the neighborhood of the active layer. In contrast to the studies on the origin and physics of Schottky barrier heights in metal contacts to GaA~,l~~l-l~*lno definitive model for the actual mechanism of the origin of Schottky barrier and the Fermi level pinning in the contacts to InP has yet been suggested. Some ideas have been discussed, such as the use of group IV or group II dopants to act as donor or acceptor, respectively, by substituting for the In to enhance the ohmic contact formation mechanism. However, some more fundamental issues, such as the Fermi-level pinning problem in InP, are rarely discussed. Since samples are invariably exposed to air prior to the metal deposition and contact processing, it may be presumed that the surface is initially pinned. However, it is not clear at this time, whether subsequent metallurgical reactions taking place prior or during the contact formation eliminate the pinning of the
Deposition of Metals as Ohmic Contacts to InP
191
Fermi level. It is agreed, however, that when the semiconductor surface is heavily doped, pinning of the Fermi level does not dominate the ohmic nature and properties of the contact. Since heavily doping the semiconductor surface is the current common technology to enhance the ohmic contact formation to InP, the issues associated with Fermi-level pinning in the InP bandgap are considered as only secondary in importance and thus as being beyond the scope of this review, and, therefore, is not discussed. 3.4
Thin Film Mechanical Properties
The stress induced into the contact metallization, semiconductor, and dielectric layers under it has an important influence on the quality of the contact properties, as well as an influence on the overall device performance. In general, this stress may be caused by a variety of intrinsic parameters, such as the film deposition conditions, film mode of growth, nature and concentration of grown-in defects, and substrate temperature during depositions.l7gl In addition, the contact quality is strongly dependent on the thermal stresses that are induced in the film during the contact sintering, which occurs as a result of one or more of the following: the difference in the coefficient of thermal expansion between the film and the substrate, interfacial interdiffusion and interaction, compound formation, grain growth, recrystallization, grain reorientation, densification, and thermal gradients induced by the source and nature of the heat treatment.l80l High stress, particularly if tensile, may stimulate a number of contact and device failure modes through an immediate loss of adhesion between the film and the substrate, which leads to contact peeling, or formation of dislocations in the substrate and the acceleration of defect migration.l81l Therefore, it is important to monitor and optimize the induced stress in the contact region, not only through the epitaxial layer growth geometry, but also through the large number of processing steps involved in the device fabrication, in particular, through the contact sintering. In order to define the origin of stress through these various processes, in-situ measurements are required.185l Selecting a highly stressed metal or an incorrect sir&ring condition for the contact formation may lead to highly stressed structure, both in the immediate vicinity of the metal/InP contact and in the bonding pads in the peripheries, and to stress discontinuity at the contact edges. The latter may act as a core for three-dimensional dislocation propagation, and as a preferred site for adhesion failures, and may, as a result, stimulate
192
Compound Semiconductors
thermal failures by interdifhrsion and interaction behavior along these defects. Therefore, stress discontinuity in the contact borders has to be considered and must be minimized while optimizing the contact formation process.
4.0
OHMIC
CONTACT
4.1
Introduction
PROCESSING
TECHNOLOGY
Traditionally, during the recent years, Au-based alloy contacts such as AuBe (0.9% Be) and AuGe (12% Ge) have been used as the standard metallization for ohmic contacts to p-type and n-type InP and related materials, respectively,t4811861-1901 as well as Ti/Pt which was used as a metallization scheme for both contacts.lgll-lg41 These metallization schemes were implemented into a variety of devices, such as light emitting diodes (LEDs), channeled substrate buried heterostructure (CSBH) and capped mesa buried heterostructure (EMBH) laser devices. The metal depositions can be executed by a variety of physical and chemical deposition techniques. Subsequent to the metallization, the devices have to be subjected to alloying or sintering heat treatment, by means of conventional quartz tub furnaces or rapid thermal processors, through heating cycles at temperatures in the range of 350 to 45O’C for durations of 30 set to 10 min. Contacts to n-type and p-type InP and related materials are becoming a major field of concern and development, because these semiconductor materials are widely employed in high-speed electronic and photo& device technology. In contrast to contacts to GaAs and related material, this technology is still premature and the understanding of the contact metallurgy and carrier transport mechanisms, and the correlation between the microstructure and electrical properties are uncompleted. Much more work has yet to be invested in these studies. However, some principles and fundamentals have been demonstrated, and the kind of metallization scheme and process conditions necessary for the required performance and device technology can be defined. The main issues that have to be considered when selecting the metallization scheme and the process conditions are: (a) optimization of the electrical properties to achieve the lowest possible contact resistance; (b) stable microstructure over a wide temperature range; (c) stability throughout the device electrical operating conditions; (d) minimization of stress in the underlying semicon-
Deposition of Metals as Ohmic Contacts to InP
193
ductor and in the metal films; (e) compatibility with the metal system used for the interconnection technology; and &I fabrication through a robust process which fits as an integrated step into the overall device manufacturing scheme. The technology trend towards the fabrication of microstructures and submicron devices renders added significance to the understanding of the nature of the metal/IS-based interfaces. Improving the quality of these interfaces and controlling a very shallow interaction will provide the desired abrupt metal/semiconductor interfaces, leading to uniform current transport via the contact and enhanced reliability, both for short- and long-term operation. Further reduction in the interfacial defect densities is necessary in order to control the contact electrical properties and to achieve reproducible characteristics. Advances in this research will require an atomistic understanding of the inter-facial reactions, in-situ characterization capabilities ofthe process in real time, and the ability to absolutely control the metal/ semiconductor diffusion and interactions. Elimination of interfacial defect and lattice-mismatch in the metal/ semiconductor system, for example, by fabrication of stable epitaxial metal contacts or metal/semiconductor heterostructures, preferably by means of an in-situ sequential process, is expected to improve the wetting and adhesion of the thin deposited layers as well as the stability and electrical performance of the contacts and devices. Furthermore, kinetic effects, bulk and grain-boundaries diffusion processes, lateral and vertical spreading of the metallization during the depositions and the subsequent sintering process, would be effectively limited by using high eutectic melting point metal/ III-V systems. Metals such as W and W-alloys are certainly suitable candidates, mainly due to their thermodynamic stability. In addition, it is necessary to consider the appropriate and suitable metallization processes for the future fabrication of multilevel devices with small (submicron) dimensions and high-aspect ratio contact windows and stripes, as well as the required shallow junctions and very thin cladding layers on top of the device active region. The above issues emphasize the need to consider the advantages and disadvantages of the variety of metal deposition techniques, such as sputtering, evaporation, CVD, or MOCVD. Each of those techniques has its own merits and drawbacks which have been widely discussed in conjunction with silicon technology. Ig51However, the severe demands and the unique requirements of future contact technology may benefit by some of the advantages of deposition techniques by means of CVD or MOCVD. Tungsten technology,
194 Compound Semiconductors
both selectively deposited,I%l-1991or blanket deposited, followed by etchback to form the required geometry,tlooltloll was well developed and reported for applications in silicon device fabrication, and the fundamentals may be adopted in conjunction with the InP technology. The most attractive characteristics of the chemical deposition technique are the films’ conformal coverage, the films’ high purity, the films being easily doped with controlled stress, and the processing benefits such as low temperature deposition, radiation-damage free, deposition selectivity, and excellent step-coverage. CVD metallization in a rapid thermal processor (RT-CVD) with load locks and cold walls, provides an attractive technique due to the improvement in the deposition selectivity, controlled deposition operation modes, availability of controlling the reaction by both gas flow or lamp intensity switching, and a short and reproducible contact sintering sequence.t1021-11041 Beyond the ohmic contact applications and issues partially covered in this review, there is a wide range of exciting research and development work necessary to provide currently needed and future projected metallization processes for IS-based electronic and photo& device manufacturing. As the understanding of the electrical, optical, mechanical, and morphological properties (and the correlations between them) of these thin metal films on InP and related materials, are improved, more exciting and advanced applications will be explored and realized to benefit the entire device manufacturing technology. Thus, the following discussions address all the above various aspects, dealing with the technology in the following manner. The first paragraph describes current existing contacts to InP deposited by means of physical deposition, while the next paragraph addresses the metal chemical deposition technique with a special emphasis on the rapid thermal low-pressure (metalorganic) chemical vapor deposition technique. 4.2
Contact Processing
by Metal Physical Deposition
Gold (Au) Based Contacts. During the recent years, a variety of Au alloys were suggested as a potential candidates to form sufficient ohmic contacts to both p-type and n-type InP and related materials. Tables 1 and 2 summarize the suggested metallization schemes and the achieved specific contact resistivity while applied to p-type and n-type semiconductors, respectively.
Deposition of Metals as Ohmic Contacts to InP
195
Table 1. Au-Based Ohmic Contacts to p&P and Related MaterialsSpecific Contact Resistance Values as a Result of the Semi-conductor Doping Level and the Metal Scheme Semiconductor Doping Specific Contact Metal Scheme Au-Zn
(cmm3)
Resistance (Qxm2)
2~10’6-5*10’6
1*10-2-F 10-3
(105,117,118,119)
Reference
7~1017-2~1018
4-10-5-l-10-6
(112,120,121,123,128)
Au-Zn-Ni
1.10’8
2.10-s
Au-Be
2.10’7-8.10’8
1.10-3-9.10-S
(6) (48,89,124,125.126)
Au-Ge
9.10’7
2-10-2
(112)
Au-Ni
2.10’7
1.10-l
Au-Cr
9.10’7-2.10’8
1*10-2-1.10-3
(127) (112,128)
Au-Cd
5.10’6
1.10-2
(118)
Au-Mg
6*1017
1.10-4
(106)
Au-Mn
2.10’8
6. 1O-4
(129)
Au-Ge-Ni
1.10’8
2*1o-5
(132)
Table 2. Au-Based Ohmic Contacts to n-1nP:Specific Contact Resistance Values as a Result of the Semiconductor Doping Level and the Metal Scheme
Metal Scheme Au
Semiconductor Doping
Specific Contact
(cmm3)
Resistance (fJ*cm2)
3~1cl’6-1*10’7
Reference
5.10-5-9.10-5
(105.106)
l*lP-5.10’8
1~10-6-4*10-7
(107)
Au-Ga
1.7*1o18
3.10-5
(107)
Au-In
1.7*1o18
3.10-S
(108)
Au-Ge-Ni
9*10”-5.10’6
3*10-5-9*10-s
(106,109)
1-10’7-5.10’8
4.10-6-2.10-7
(90,111,112,113)
Au-Ge
5.10’8
2.10-6
Au-Sn
8-10’7-3-1018
1~10-5-1~10-6
(131) (111,114,115)
Au-Sn-In
8+1017
3*10-4
(112)
Au-Ti
2.10’8
1.10-6
(116)
196
Compound Semiconductors
Among the p-type contacts, the AuZn,[1051[1211[1ul[1321-[136~ evaporated and alloyed at a temperature range of 400-450°C onto p-InP (yielding a specific contact resistivity of 2.1 o-4 to 8 1Oe5Wcm2) and onto pInGaAs (yielding a specific contact resistivity of about 1. 10m5to 5. 10m5 0cm2) and the AuBe (0.9-3 wt% Be),1126111371-[1401 also evaporated and alloyed at 420-430°C onto p-InP (yielding a specific contact resistivity of 4.10” to 8*10a 0cm2), are the most commonly used contact metallization schemes. Figure 7 provides the transmission line method (TLM)derived resistance measurements of the AuBe/p-InGaAs and AuGe/n-InP contacts. In the as-deposited form, the contact yielded specific resistance of about 5*10-4 S2cm2, whereas this value was reduced significantly after providing various heat treatments. The AuBe/p-InGaAs minimum specific contact resistivity value of 4~10~~!&cm2 was achieved as a result of rapid thermal processing (RTP) at 420°C for 30 sec. This value is much lower than the value of 4. lo6 C&cm2 which was measured after the conventional furnace heat treatment at the same temperature. RTP at higher temperatures resulted in a sharp increase of the specific contact resistance to a value of about 2*10-“ n-cm2 at 550°C. The interfacial reactions that take place in the AuBe/p-InGaAsP contact are reflected at the Auger electron spectroscopy (AES) depth profile which are shown in Fig. 8, as deposited (Fig. 8a) and after RTP at 300 (Fig. 8b), 350 (Fig. 8c), and 390°C (Fig. 8d) for 30 sec. One can see that already, after RTP at 300°C for 30 set (see Fig. 8b), a moderate reaction took place at the metal/quaternary interface, accompanied by the AuBe penetrated into the epitaxial layer and an out-diffusion of As. This enhanced diffusion may be explained by the high mobility of As at this temperature which results in a very limited apparent solubility of it in the Au. The nature of the interfacial reaction was studied by TEM and the reaction between Au and In was found to be the preferred one. The Au-In couple was reported to be a very reactive system, in which solid-state reaction may take place at temperatures as low as 250”C.l 1411 Increasing the RTP temperature to 350°C led to wider reaction. Creation of a P plateau is observed, suggesting an interaction between the P and AuBe layer (see Fig. 8c), which may only be explained by the formation of the Au2P3 met&able intermetallic phase, since these elements have only a very limited mutual solid solubility. 1142l A further development of the reaction was detected after RTP at 390°C for 30 set (see Fig. 8d) while a wider intermixed layer was formed between the quaternary layer and the metallization, and
Deposition of Metals as Ohmic Contacts to InP
197
even a deeper penetration of the Be was observed into the InGaAsP layer. This extensive reaction is reflected also from the profuse decrease in the specific contact resistance from a value of 1.6 x 10S5R*cm2 as a result of RTP at 350°C to 7.5 x 10m7Rzm2 after RTP at 390°C (see Fig. 7). Another interesting result achieved during the RTP at 400°C is the outdiffusion of the As, P, and Ga from semiconductor layer through the AuBe layer toward the surface of the contact.
42O”C, 10 min
= 350°C. 5 min
-
10-7 300
I
I
350
400
AuBelp-InGaAsP AuGeln-InP
I
I
450
TEMPERATURE
500
I 550
f IO
(“C)
Figure 7. Specific contact resistance as a function of the processing temperature AuGeln-InP and AuBeIp-InGaAsP systems.
u
(b) 300°C.
30 s 1
(d) 390°C.
30 s 1
at the
0 0
4
6
12
16
SPUTTER TIME (min)
Figure 8. AES depth profiles of (a) AuBe (80 nm)/p-InGaAsP after RTP at (a! 3OO”C, (c) 350°C, and (d) 39OT for 30 sec.
as-deposited
sample, and
198
Compound Semiconductors
Figure 9 presents the Auger depth profiles of three AuBe/InGaAsP samples after different heat treatments at temperatures higher than 400°C; RTP at 420°C for 30 set (Fig. 9a), conventional furnace heating at the standard conditions of 420°C for 10 min (Fig. 9b), and RTP at 500°C for 30 set (Fig. 9c). Comparing the results of the two different heat treatments at 420°C shows almost similar element distribution profiles. However, a narrower reacted metal-semiconductor layer and reduction in the out-diffusion of the epitaxial layer elements were achieved as a result of the RTP. The influence of this moderate deviation in the extent of interfacial reactions on the electrical properties of the contact is considerable as shown by the large difference in the specific contact resistance values of the two (see Fig. 7). Increasing the RTP temperature to 500°C resulted in degradation of the microstructure and electrical properties of the contact. This high temperature led to few different reactions in the binaryl143l and ternary 1~ thermodynamic systems which are included in the AuBe/InGaAsP contact, both in the solid and liquid state. Indeed, observing the AES depth profile of the sample after RTP in 500°C for 30 set (see Fig. SC), one can see an extremely wide expansion of all the contacts elements. While the Au and Be penetrate very deeply into the epitaxial layer, all the latter elements are spread in a homogeneous manner all through the metal layer and are found in a significant amount on the outer contact surface. Subsequent to the out-diffusion of the Ga and In, oxidation processes are initiated. This may make another contribution to the degradation of the contact electrical performance at temperatures higher than 470°C (see Fig. 7). i:
CE
6
054 Ixs am2 p” 0 0
4 SPLJlTER
6 TIME
0
12
16
0
4
4 SPUVER
6
SPUlTER
@in)
0 TIME
12
TIME
12
16
(n-tin)
16
(min)
Figure 9. AES depth profiles of (a) AuBe (80 nm)/p-In-GaAsP samples after RTP at 420°C for 30 set, (b) conventional tube furnace at 420°C for 10 min, and (c) RTP at 500°C for 30 sec.
Deposition of Metals as Ohmic Contacts to InP
199
Figure 10 gives SEM surface micrographs of the contact surface after heat treatment at 420°C, both by RTP for 30 set (see Fig. 1Oa) and conventional furnace heating for 10 min (see Fig. lob), and after RTP at 450°C for 30 set (see Fig. 10~). Explicit difference in the quality of the surface is observed between the first specimen and the other two. While the former has a smooth and shiny appearance, the latter two presents a degraded surface morphology, with only a pinhole-like damage after the conventional heat treatment at 42O”C, but with a typical melting morphology as a result of RTP at 450°C. These results agree with the AES observations presented in Fig. 8 and supply further evidence for the suggested degradation mechanism which took place at temperatures higher than 45O”C, while RTP was executed, and 42O”C, while utilizing a conventional furnace treatment. Keramides et al. have reported a similar damage observed at the AuBe/InGaAsP contact microstructure as a result of conventional heat treatment at temperatures higher than 400°C (e.g., 420°C for 7 min) and pointed out, in addition, the existence of AuBe horizontal spreading mechanism in preferred crystallographic directions. The microstructures of the AuBe/InGaAsP as deposited and after RTP at 340, 420, and 500°C for 30 set, as was observed by means of TEM, are shown in Fig. 11. The average grain sizes of the formed intermetallics phases increased from -150 A in the deposited film to -1000 A in the film that was RTP at 500°C for 30 sec. The development of the various compounds due to solid-state reactions is revealed in the The change of the diffraction-ring patterns shown in the inserts. calculated sample lattice spacings and the lattice spacing of potential existing phases and elements are summarized in Fig. 12. Since the Be content is about l%, by weight, only Au lines are observed in the asdeposited film. RTP at 350°C led to the formation of a new line in the electron ring pattern, which would not have been matched to either the pure Au or Be spacing (see Fig. 12). Indeed, the AES of this sample (see Fig. 8) shows the existence of extensive interfacial reactions. The formed compounds were identified as Au,Be and Au&,. After RTP at 420°C for 30 set, the continuous diffraction ring pattern became spotty and Au,P, and AuIn, phases were identified as well. The large change in the gram size as a result of RTP at 500°C for 30 set and the rapid formation of all the mentioned intermetallic compounds indicate the existence of an intensive solid and liquid-state reaction at the AuBe-InGaAsP structure at this high temperature.
200
Compound
Semiconductors
Figure 10. SEM surface micrographs of AuBe (80 nm)/p-InGaAsP samples after (a) RTP at 420°C for 30 sec, (b) conventional tube furnace at 420°C for 10 min, and (c) after RTP at 450°C for 30 sec.
Deposition of Metals as Ohmic Contacts to InP
201
Figure 11. Plan-view TEM micrographs of the AuBe contacts: (a) as-deposited,and after RTP at (b) 350°C, (c) 420°C, and (d) soo°C for 30 sec. The inserts show the corresponding electron diffraction patterns.
Figure 12. Schematic presentation of the calculated d spacing diffraction rings and the associated elements and compounds.
from
TEM
electron
202
Compound Semiconductors
The above process development sequence was found to take place in a very similar way in a lot of the Au-based contacts to InP and related materials, and a very detailed kinetic model, comprising 3-phase transition, Other Au-based metallizawas presented by Fatemi and Weizer. [1451-[1491 tion schemes that were reported as ohmic contacts to p&P were AuMg [lo61Au-Cd,[l l *~[1501, Au-Ni, [ 1271, and some ternary alloys such as AuBe-;r,[l511 and Au-Zn_Ni.[61[1521 For contacts to n-InP, the most commonly employed scheme is the Alloying this contact at the Au-Ge (12 wt% Ge) eutectic alloy. [1111[153H1551 eutectic melting temperature of about 360°C drives the dissolution of InP and the resolidification of the phosphide-rich InP, as a result of the high solubility of indium in the Au-Ge melt adjacent to the substrate. Germanium is likely to be incorporated preferentially on the In site in the precipitated InP. Alloying the contact at temperatures of 450°C and higher results in significant outdiffusion of P and enhanced formation of P vacancies. This leads to degradation of the contact electrical properties, as is reflected in the plots shown in Fig. 7. Other metallization schemes often used to form ohmic contacts to n-type InP are Au-Ge-Ni ternary alloy and Au-Sn.[161 All the Au-based contacts, which require an alloying thermal cycle in order to allow for the intermixing of the dopants in the metal/semiconductor interfacial layer, suffer some common deficiencies: (a) formation of wide interfacial reaction layer, typically 2 to 3 times the thickness of the initial deposited metal layer (Fig. 13 shows a typical example of the wide reaction zone of a AuBe contact on a laser device in which Au spikes, about 0.5 p m large, are observed); (b) nonuniform depth of interaction and spatial composition, leading to nonuniform current density across the contact; and (c) lack of long-term metallurgical stability. [1621[1631These deficiencies may be improved by alloying the Au-based contacts by means of RTP. As an example, the improvement in the electrical properties, reflected in a reduction of one order of magnitude in the specific content resistance of the AuBe contact, is shown in Fig. 7.ig1 Near-Noble Transition Metal Based Contacts. In order to overcome the deficiencies associated with the processing and performance of the Au-based alloyed contacts to both p-type and n-type I&based materials, in particular, their unstable nature and lateral nonuniformity, various metallization schemes have been suggested as alternative contacts. All of these solutions are based on formatting an ohmic contact using Au-free solid phase reactions, and using higher eutectic melting point systems. In these contacts, near-noble transition metals were chosen as the metallization
Deposition of Metals as Ohmic Contacts to InP
203
schemeof choice. Due to the more stable thermodynamic properties and less reactive nature of these metals, they provide a less degraded contact microstructure through heat treatments at higher temperatures.
Figure
13.
SEM cross-section
furnace alloy at 420°C
micrograph
of AuBe contact on CSBH
laser device ,after
fo! 5 min.
An excellent example of such a system is the bilayered Ti/Pt metallization which was studied thoroughly as an ohmic contact to a variety of ptype and n-type loP and related materials. (See, for example, Refs. 53,79, 86, 87.) By developing a common ohmic contact for both the p- and n-type materials, a significant technological advantage is achieved. In this case, both contacts may be depositedsimultaneously onto a single-side contacted electrical or optical device, or subsequently, to both sides of a two-side contacted device by flipping the wafer over in the deposition system without breaking the vacuum. Figure 14 shows in a schematic manner the Ti (50 om)/Pt (60 om) common contact to EMBH laser diode. This set of contacts allows for superior short and long term operations of the laser diodes. Due to the limited solid-state reaction between the contact metal and the low melting point Group III elementsand the volatile Group V elements, complicated microstructures are expectedto develop at the interface, especially after RTP at elevated temperature. Figure 15 shows an example of
204
Compound Semiconductors
the Auger depth profiles of all the elements of an as-deposited Ti/Pt contact, and contacts subjected to RTP at temperature range from 400°C to 500°C. Significant interdiffusion occurred as a result of RTP at temperature of, or above, 400’ C. The major out-diffusion elements are In and As, while the Ga profile remains relatively unchanged up to above 45OOC. The main indiffused element is Ti. Significant changes in the Auger depth profiles of In, As, and Ti occurred at 45O’C. The corresponding inter-facial microstructure of the 450°C RTP sample is shown in Figs. 16(a) and 16(b). A complicated reaction zone, about 800 A thick, was developed at the interface. The microstructure of the reacted zone consists of a defective inter-facial layer and solid-state regrown phase regions as indicated by the arrows. A cross-sectional view of the microstructure of the metal film is also shown in Fig. 16(b). The average grain size of the polycrystalline Pt/Ti film is slightly larger than the thickness of the film. The extent of the interfacial reaction is much less for a sample that was RTP’d at 350°C for 30 set as is shown in Fig. 17. Figure 17(a) shows a peeling off ofthe metal film during TEM sample preparation, indicating poor adhesion due to a limited inter-facial reaction at 350°C. The limited interfacial reacted zone is further observed in the higher magnification micrograph as indicated by the arrows in Fig. 17(b).
,-Ti
(50 nm)
I
Ti (50 nm)
I
I
Pt (60 nm)
I
Figure 14. Schematic presentation of a Ti (50 nm)Pt (60 nm) common p-type and n-type contacted Eh4BH laser device.
Deposition
of Metals as Ohmic Contacts to InP
205
Figure 15. AES depth profiles of (a) an as-depositedPt'Ti film on p-InGaAs, (b) RTP at 400°C for 30 sec, (c) RTP at 450°C for 30 sec, and (d) RTP at soo°C for 30 sec.
0.1 fJ.m
Figure
b
16. TEM cross-sectional micrographs
for 30 sec showing
(a) complicated
interfacial
ofPt/Ti
solid-state reaction (bright field), and (b) a thinner the bulk Pt/Ti film
(dark field).
films on p-InGaAs RTP'd
microstructure
at 450°C
developed due to interfacial
region revealing the microstructure
of
206
Compound
Semiconductors
Figure 17. TEM cross-sectional micrographs ofPt'Ti film on p-InGaAs RTP'd at 340°C for 30 sec showing (a) poor adhesion of the film due to the limited interfacial reaction at 350°C; and (b) a higher magnification shows two small reacted regions at the interface.
The electron diffraction patterns taken from the interfacial region were compared with those taken from the bulk Ti/Pt film and InGaAs in order to identify the dominating interfacial compound developed during RTP at 450°C. The lattice spacings measuredfrom the diffraction patterns of 450°C and 350°C heated samplesare listed in Fig. 18, along with those obtained from the diffraction pattern of pure Ti, Pt, and Ti/Pt films to unambiguously single out the diffractions from the interfacial compounds. The lattice spacing from the interfacial compounds are then compared with the available diffraction data of all the possible binary compoundsof In, Ga, Ti, Pt, As, and P. The best agreementwas found to be with InAs, where there is a match of six lattice spacings. This also agrees qualitatively with the AES profiles (seeFig. 15), which showsthat both In and As out-diffused faster than the Ga profile. Some lattice spacings also match In2Pt and GaPt3. Very similar types of reactions were observed between the Ti/Pt metallization and the n-InP. Figure 19 gives AES depth profiles of the asdeposited Pt (60 nm)rri (50 nm)/n-InP (Fig. 19a), and after RTP at 500
Deposition of Metals as Ohmic Contacts to InP
207
(Fig. 19b), 450 (Fig. SC), 500 (Fig. 19d), 550 (Fig. 19e), and 600°C (Fig. 190. One can see that heating at temperatures up to 45OOC caused only a limited reaction in the Ti/InP interface. Increasing the RTP to higher temperature caused a considerable reaction in the contact, particularly observed at the Ti original layer. Three separate reactions may be observed, between the Pt and Ti in the Ti/Pt interface, between the Ti and the P that was out diffusing from the substrate, and between the Ti and the In adjacent to the substrate (see Figs. 19e and 190. I
I
I
(4
RTP 450°C
III MI II
II
I I
I I I I I I
(b)
RTP 350°C
I
I 1
I (cl
Ti
1 ,I
1
II
Pt
(d) I (620) (511)
l"AS
(600) (422) (400) I,,(,, I
(311)
(220)
II I
I
(111)
(200)
InTi,
I
I Ga Pt,
I
I
1.
I Ga Pt
I
III
I
I
I
Ga Pt, II Ti, Ga3
I
I
I
I
In2Pt II
II
I
II
InP
I I
I
1
III
II
I
I
2
3
d -SPACINGS
(A)
Figure 18. The measured lattice spacings from the diffraction patterns taken (a) in the interfacial regions of a sample RTP’d at 450°C for 30 set, (21)at 350°C for 30 set, (c) from the Ti films, (d) from the Pt films, and the known lattice spacings of various compounds from the “Power Diffraction File” (Ref. 23).
208
Compound Semiconductors
0
5
‘1”
15
Z”
23
SPUTTER
0 TIME
5
1”
15
zo
25
(mm)
Figure 19. AES depth profiles of Pt (75 nm)/Ti (SOnm)/n-InP (a) as-deposited and after RTP at (b) 4OO”C, (c) 450°C, (d) SOOT, (e) 550°C, and (j 600°C.
sample,
In Ti/Pt contacts to both p-type and n-type InP-based materials, metal-semiconductor interfacial reactions shallower than 0.1 urn were observed, which are much thinner than the observed interactions which took place in the Au-based-semiconductor contacts. The limited reactions driven by the Ti/Pt metallization demonstrated the thermodynamic stability of metal-semiconductor contacts that can be achieved while executing high melting point metals as the contact metallization scheme of choice. The ohmic nature of these contacts is obtained by both heavily doping the semiconductor layer under the metals and by leading to the formation of narrow-bandgap intermetallic phases in the metal/semiconductor interface through a limited reaction when sintering the contacts. The most commonly used metals are the Ni and Ni-P,1110111641 and Ti and Ti/Pt ~~~~~~~,~~~1~~~1~7~1~~~1-~~~1 d epositing the metal scheme, either by electron beam evaporation or by sputtering, onto highly doped p- and n-type InPbased material (typically Zn or S doped, respectively, to the levels of 1 x lo’* to 8 x 1018cm-3). Figures 20 and 21 show the specific contact resistance of various metals to p-InGaAs(P) and n-InP, respectively, as a function of RTP temperature. For each group of contacts, the specific resistance of the standard used Au-based contact, formed through a quartz tube furnace alloying cycle, provides reference values. Thus, superiority of a certain
Deposition of Metals as Ohmic Contacts to InP
CONTACTS
1Omin
TO p-InGaAs RTP 30s
i
\ ‘\
;
-‘\
!
.\’
(4
I 300
I 400
I
I
(P)
@
Pt/Ti/InGaAs(5xlO”cm-3)
@
Pt/Ti/InGaAs(1.5x10’gcm-~)
@
Pt/Ti/InGaAsP(5~10’~cm-3)
@
Pt/Ti/loGaAsP(Sx
@
Pt/Ti/InGaAsP(l
1O”cm-3) ~lO’~crn-3)
@
Pt/Ti/InGaAsP(2x10’gcm-~)
@
W/lnGaAsP
(5x lO’*cm-3)
@
WhGaAsP
(1 x 101gcm-3)
I
500 TEMPERATURE
209
I 600
I ), I ‘800
(“C)
Figure 20. Specific contact resistance as a function of sintering temperature contacts to p-type I&based materials.
for various
contact is reflected from a lower specific resistance values. The lowest reference values are 3.8 x 10m6Rcm2 for the p-contacts and 4.5 x 1Oa Rcm2 for the n-contacts, which were achieved by alloying the AuBe/ InGaAs(P) (Zndoped, 5 x 101* cme3) at 420°C for 10 min and the AuGeIInP (S-doped, 5 x lo’* cm3) at 350°C for 5 mm, respectively. Significant improvement in the specific resistance values was achieved at the AuBe (sample No. I) and AuGe (sample No. 10) contacts by subjecting them to 30 set RTP at 350 and 450°C, respectively. These heat treatments revealed contact resistance values of 4.9 x 10q7 Rcm2 for the former and 1.6 x 10m6Rcm2 for the latter. The improvement of the contact resistance provided by the RTP heating cycles motivated the use of this technique as a preferred heating routine for sintering the contacts. For comparison, the
210
Compound Semiconductors
nature of W contacts is demonstrated as well. Refractory metal contacts to 5 x 1018 Zn-doped InGaAsP layers, however, were always inferior to the standard AuBe contact. Pt (60 nm)/Ti (50 nm) contact (sample No. 4) yielded the lowest specific resistance of 5 5 x 1O-“SZcm2 as a result of RTP at 450°C while W (100 run) contact (sample No. 8) revealed a value of 8.5 x 10m5SZ*m*as a result of RTP at 600°C. The performance of these pcontacts may generally be improved by either increasing the doping level of the InGaAsP layer, which provides a narrow Schottky barrier and enhances tunneling transport, or utilizing the ternary In,,,,Ga,,~,As, (InP latticematch film), which provides a much narrower bandgap semiconductor contacting layer adjacent to the metal film. Increasing the doping level of the InGaAsP layer to 8 x 1018 (sample No. 5) 1 x 10lg (sample No. 6) and 2 x 10lg cm” (sample No. 7) decreased the specific resistance of the Pt/Ti contacts to 7.2 x 10m6,3.5 x 10s6 and 1.1 x lOA Rem*, respectively. Increasing the doping level of the InGaAs layer to 1 x 10lg cme3 and depositing W film onto it, however, dropped the specific contact resistance to 7.5 x lo6 Qcm*. All those values are somewhat inferior to the AuBe/ InGaAsP contact resistance value, yielded after alloying in 420°C by means of RTP.
ii G k? 0
@Pt/Ti/InP(lxlO’*cm-3) 0)
, n-7 I”
I
I
,
350
400
450
0Pt/lTi/InP(5x:01’cm-3)
.
300
TEMPERATURE
500
550
GO
(“‘2)
Figure 21. Spe.cific contact resistance as a function of sintering temperature contacts to n-W.
for various
Replacing the 5 x lo’* Zndoped InGaAsP by the layer doped to the same level (sample No. 2), and applying the PVTi scheme, sintered by RTP at 450°C, revealed contact with almost similar performance to the AuBe/
Deposition of Metals as Ohmic Contacts to InP
211
InGaAsP contact alloyed by RTP at 420°C. The former yielded the lowest specific contact resistance value of 9 x 10m7L2cm2 and the latter had a value of 4.9 x low7L2cm2. Increasing the Ih,,,Gq,,,As doping level to 1.5 x 1019 cms3 (sample No. 3) dropped the specific resistance of the Pfli contact to an extremely low value of 3.4 x IO-* Rcm2, as a result of RTP at 450°C. This value is vastly lower than the lowest resistance achieved with the AuBe scheme and thus, suggested an improved p-contact to the InP-based materials. Another interesting result reflected by the specific resistance curves of the p-contacts as a function of the RTP temperature (see Fig. 20) is that there is less temperature dependence with the Pt/Ti and W contacts then with the AuBe metallization. One can see that the slope of the former curves are less steep than those of the latter, and the sintering temperature range that enable a specific resistance lower than an acceptable value (e.g., 1 x 10e6 Qcm2) is much wider with either Pt/Ti or W schemes. For the contacts to 5 x lOi* cme3 S-doped n-InP (see Fig. 2 l), both AuGe and PtiTi metal schemes revealed almost similar specific contact resistance values of 1.6 x lO-‘jand 4.2 x 10e6R-cm2 while heated by RTP to 400°C. The less stable nature, however, of the AuGe contact is reflected by the abrupt increase of the specific resistance value due to RTP at higher temperatures. The PUTi contact, on the other hand, yielded the minimum specific resistance value of 8 x 10m7Qcm2 as a result of RTP at 450°C. These results demonstrate the potential of applying both the RTP technique and a near-noble transition metal scheme in order to produce a contact to InP-based materials. These contacts revealed a stable electrical nature and yielded a very low specific resistance value. Pt(60 nm)/Ti(SO nm) metallization scheme to P-I~~~~G%.~~As layer doped by Zn to levels higher than 5 x 101* cmm3and to n-InP S-doped to the same level yield a specific contact resistance better than 9 x 10e7 and 8 x 10m7Rcm2, respectively, as a result of RTP at a temperature range of 400 to 450°C. Refractory Metal-Based Contacts. For high-speed devices operated at high temperature conditions (>600 C), the thermal stability offered by the transient metals may not be sufficient. These kinds of contacts cannot be exposed to temperatures higher than 450°C through the contact processing without suffering some severe degradation, the type of which may also be observed during operating under high-temperature and high-current density conditions. The highest level of thermodynamic stability may be achieved by using refractory metal based contacts, such as a variety of W-based alloys. In addition, high-quality mechanical properties, such as stability,
212
Compound Semiconductors
reproducibility, and low induced stress, are required at these contacts, as well. [4gl1561tg31 In the device manufacturing environment, robust fabrication and simple processing are also essential. Self-aligned processed III-Vbased electronic devices have been demonstrated to meet the above requirements. The concept is to have a stable contact metallization scheme in place during preliminary processing stages, and to use it as a mask for selective protection of the semiconductor under it, particularly during ion implantation. Tungsten-based alloys such as WxSiy,[165][168][16g]GeWSi2,11701 WN,1171111721 WSiN,11731 WTiN,11741 and PtWAg11751have been used as a self-aligned ohmic and Schottky contacting material for n-type GaAs-based devices. The W and W-alloys metallizations have been used also as highly stable contacts to n-typel168l and p-typel64l b.,,Ga,,,,As materials for the fabrication of self-aligned electronic devices. For the same reasons, W and W-alloys were also considered the metals of choice for the Schottky gate metallization in self-aligned GaAs metal-semiconductor field effect transistor (MESFET) and heterostructure In this GaAs device technolfield effect transistor (HFET) devices. 11761[1771 ogy, the W gates perform as self-aligned contacts for ion implantation into the source and drain regions, which involves high temperature (800-850°C) activation annealing, and thus, sets the major requirement for this selfaligned metal scheme, which is to form a stable and reproducible Schottky contact through the ion implantation and the subsequent severe heat-treatment. In the h&based laser device technology, however, the terminology of self-aligned devices refer to devices such as Etched Mesa Buried Heterostructure (EMBH) lasers that are processed through all the required manufacturing steps of mesa etching, regrowth of the blocking layers, and final processing, with the existence of the metal ohmic contact on top of the semiconductor base-structure. This metal pattern, therefore, has to serve as a selective mask for both the InP-based material dry or wet etching and the regrowth of the blocking material, surrounding the mesa. From the metallurgical point of view, the metal of choice has to be etchable in order to enable the geometrical definition, which serves both as the contact and as the mesa etching mask, to be inert to the semiconductor procedure, to prohibit any semiconductor growth on top of it during the regrowth of the blocking layers, to perform as an inert layer toward the InP-based material under it and to be stable through the regrowth cycle (- 650°C) to have good adhesion to the InP-based material, and thus, to produce low stress through the process, and should also be compatible with the existing patterning and intercontacting materials and techniques. Above all, the metal of choice has
Deposition of Metals as Ohmic Contacts to InP
213
to perform as a good ohmic contact to the semiconductors layer under it. Only by fulfilling theserequirementsone can benefit from using self-aligned device technology for manufacturing loP-based laser devices. Figure 22 shows a backscatteredcross-sectionmicrograph of the W/ lno.53G30.47As/InP sample after RTP at 500°C (Fig. 22a) for 120 sec taken by high resolution SEM. The latter representsthe conditions which take place in the regrowth process. These micrographs show an almost abrupt metal-semiconductor interface. which agreeswith the AES and RBS observations of these samples.[64]The tungsten layer morphology. as is revealed by meansof the SEM. looks polycrystalline and columnar. with a grain size of about 100 nm. following RTP at 700°C (seeFig. 22b). One can seethat the W contact had an almost abrupt interface with both loP and InGaAs layers.
Figure
22.
SEM high-resolution
sample after RIP
field emission cross section of the W (100 nm)/p-InGaAs
at (a) 500°C and (b) 700°C for 30 sec.
214
Compound Semiconductors
The electrical properties of these contacts and, in particular, its TLMderived resistance, were improved through sintering at temperatures as high as 600°C and are summarized in Figs. 20 and 2 1. A major concern while executing refractory metals is the usually highly mechanical stress conditions of the deposited films. Figure 23 shows the m-situ biaxial stress measurements through the heating and cooling cycles of the rfdiode-sputtered W films as a function of the Ar pressure during the deposition. Since no phase formation was observed in these films while heating up to 500°C, the changes in the film stress during the thermal cycles are attributed to a variety of parameters other then metallurgical reactions.l7gl The stress of the W films was sustained in all cases through heating of up to 280°C. This behavior is due to the very similar thermal expansion coefficient of the r-f-sputtered W films and the InP substrate, which were found to be 4.83 and 4.75 x 10” “C-l, respectively. While heating at elevated temperatures, the stress curves of all the studied samples showed the existence of plastic deformation within the films, indicating densification or stress relaxation effects. Null stress conditions were achieved while depositing the W film onto InP substrates at an Ar pressure of about 8 mtorr. The biaxial elastic modulus of this film was measured to be 0.97 x 1012 Pa and the temperature-dependent coefficient of thermal expansion was found to be a, = (5.63 x lo6 + 4.01 x 10mgT- 96.16 x 1o-‘3T2)“Ci . Figure 24 summarizes the stress measurements and the Ar-to-W SIMS signals ratio (proportional to their concentration ratio) at the asdeposited samples as a function of the Ar-induced pressure during the rf sputter deposition. In addition, it presents the RIE etching rates of these different films in a standard CF,:O, One can see that by increasing the Ar pressure, the induced biaxial stress in the W film increases from a compressive stress of about 7 x log dyn cm-’ in the film that was sputtered under Ar pressure of 2 mtorr, to a tensile stress of about 8 x log dyn cms2, when deposited under 28 mtorr of Ar. Usually, an increase in the Ar pressure corresponds to a lower density of energetic Ar reflected from the metal target, and thus the decrease in ion irradiation during the film depositions led to an increase in the tensile stress, as a result of the decrease in the ion-tovapor ratios. SIMS e xamination indicated that the amount of Ar incorporated into the W films during sputtering was inversely proportional to the Ar pressure and that its concentration throughout the film was constant. The Ar/W SIMS signal ratio was 0.0357 in the film sputtered at 5 mtorr, whereas at 28 mtorr, it was reduced to 0.00 1. The entrapment mechanism is
Deposition of Metals as Ohmic Contacts to InP
215
known to be shallow implantation of Ar neutrals reflected from the target. At higher pressures the mean free path of Ar atoms substantially decreases and the enhanced scattering lowers the energy of the incoming Ar atoms, and thus their incorporation into the film.
-101
0
100
200
MEASURING
400
300
TEMPERATURE
500
600
(“C)
Figure 23. In-situ biaxial stress measurements during heating and cooling cycles of the rf diode sputtered W films as a function of the Ar pressure through the deposition.
-6
-
W~100nm)/InP r, SP”TTERING.
24ow
8” TARGET
-8
, 0
I
40
5 ARGON
I 15 PRESSURE
I 20
t 25
30
JO
ImTorrl
Figure 24. Induced stress, Ar/W concentration ratio, and FUE etching rates of W (100 nm) film on 11s substrate as a function of the sputter-deposition Ar pressure.
216
Compound Semiconductors
The etch rate of the W films showed a nonlinear dependence on the Ar pressure presents during the deposition. Since the higher Ar pressure led to the formation of higher tensile stress films, it might be expected that the more highly stressed films would display higher etch rates due to the weaker bonding. The ion bombardment component of the RIE is therefore, able to produce more efficient desorption of the W-etched products. Figure 25 shows the self-aligned device application of a W stripe (Fig. 25a), deposited under highly tensile (Fig. 25b) and highly compressive (Fig. 2%) stress conditions, being used as a metal contact “mark-in-place,” to etch subsequently, the I&based mesa under the metal, for laser devices. Other refractory alloys have been investigated as potential candidates for ohmic contact metallization schemes. Another very attractive material is the WSi,, which was used as a Schottky gate for self-aligned GaAs heterojunction bipolar transistor (HBT), metal-semiconductor field effect These films were depostransistor (MESFET) and HFET devices. 1166j11761 ited in an amorphous form, regardless of the Ar pressure during deposition, and underwent an almost complete crystallization as a result of RTP in the temperature range of 600-650°C. At this temperature, the WSi, phase was formed and was accompanied by the W,Si, phase upon heating to 650°C. As a result of the crystallization and phase formation, an abrupt decrease of the film resistivity was observed. The crystallization was accompanied by interdifision of the metal layer and substrate elements, leading to a slight degradation of the interface, and increase in the contact resistivity. This microstructure evaluation is clearly shown in Fig. 26, which shows TEM plan-view micrographs and the corresponding selected area diffraction patterns of the WSiJInP samples asdeposited and after RTP at various temperatures. All these extensive changes took place mainly at RTP at temperatures of 650°C or higher. The WSiJnP contacts were found to be stable and performed with excellent structural and electrical properties up to temperatures of 650°C when rapid thermally processed under N, or TBP ambients at pressures as low as 10 mtorr. The advantage of using the TBP ambient, which did not lead to any degradation in the metallization and contact performance, lies in the fact that it provides a protective ambient to the bare InP surface when it is subject to self-aligned technologies that require high-temperature annealing. The almost absolutely inert roll of the WSi, is shown in Fig. 27 which gives TEM cross-sectional micrographs of the WSiJInP samples that were RTP-treated at 600 and 650°C for 30 set in a N,:H, (9: 1) ambient. From
Deposition of Metals as Ohmic Contacts to InP
217
these micrographs, it is clear that while RTP at 600°C did not cause any observable WSi,/Inp interfacial degradation, RTP at 650°C resulted in somedecompositionof the loP substrate. This decomposition is reflected in the formation of voids under the WSix layer (a few of which are marked with arrows in Fig. 24b).
(a)
(b)
(c)
Figure
25.
compressive growth
(a) Tungsten conditions,
of the EMBH
stripe
to provide laser diodes.
deposited
under
a self-aligned
(b) highly
contact
tensile
mask allowing
and
(c) highly
the etch and
218
Compound
Figure
26.
Semiconductors
TEM plan-view
micrographs
and the corresp(" ;},ing SAD patterns of the WSi,.!
InP samples as deposited and after RTP at various teIT,l'eratures for 30 sec under N2:H2 (9:1)
ambient.
Figure 27. TEM cross-sectional micrographs and the corresponding SAD patterns of the WSi/lnp samples after RTP at 600 and 650°C for 30 sec under N2:H2 (9:1) ambient.
Deposition of Metals as Ohmic Contacts to InP 4.3
219
Contact Processing by Chemical Metal Deposition
Motivation. Single wafer integrated processes (SWIP) have begun to attract much attention as an alternative to the batch processes, particularly in conjunction with Si technology. The strategy of using a so-called cluster tool is a natural approach to get around the tremendous expense associated with assembling a clean room to allow for semiconductor-based microelectronic device fabrication. By using a cluster tool, one can potentially completely process a single wafer in a high vacuum ambient by manipulating it through numerous chambers via a main load-lock. These various processes can be applied to the wafer, each in a separated chamber, without the need to handle the wafer and to remove it from the high vacuum. The more processes that can be realized by means of the cluster tool, the more efficient is the SWIP. Theoretically, almost every dry process can be executed within the SWIP cluster tool. Naturally, the major problem, and thus the process that limits the entire processing of microelectronic devices via an integrated processing sequence, is the photolithography steps associated with the definition of fine geometrical features, such as the contact stripes, via holes, and interconnection lines. Currently these are usually not carried out by means of dry processing because of unacceptable throughput and process pricing associated with the implementation of the required equipment. The I&based laser diode processing sequence, however, is an excellent candidate for being processed entirely by means of SWIP. This is due to the fact that all the processing steps which are involved in the manufacturing of the device, including the photolithography, can be realized by means of dry processes. The manufacturing sequence is typically comprised of a semiconductor pre-cleaning, dielectric film deposition, defining and etching 50-150 pm wide and 250-1000 pm long contact stripes in the dielectric, deposition of a metal line into the etched stripe to provide an ohmic contact to the I&based material, and finally blanket deposition of the bonding pad metals onto the contact stripe and the dielectric fihn.l177l One of the most attractive techniques to chemically deposit metal layers onto III-V semiconductors, and in particular onto InP, appears to be tbe rapid-thermal low-pressure (metalorganic) chemical-vapor-deposition (RT-LPMOCVD) technique. By applying this technique, one can deposit metal layers onto the semiconductor at high temperature cycles without creating any damage to the latter, due to the rapid ramp-up cycle allowed by the RT-LPMOCVD. Thus, no protective overpressure ambient has to be
220
Compound Semiconductors
established in the chamber prior to heating the wafer, as is required while applying the standard CVIYMOCVD technique, and therefore, potential cross-contamination of the group V element at the protective ambient and the subsequently deposited metal layer is not a concern. The deposition of highly stable SiO, films,11781-11821 and of selective and blanket conductors such as TiN,I i~3lli~4llis31and Wl1021films, by means of a load-locked rapid-thermal low-pressure (metalorganic) chemical-vapor-deposition (RT-LPMOCVD) technique, have already been demonstrated. In addition, a highly efficient, in-situ h&‘-based material cleaning under tertiarybutylphosphine (TBP) using the same RT-LPMOCVD reactor has also been reported. I183ll184l The fact that some of the major laser diode processing steps have already been realized using a single-chamber load-locked reactor demonstrates the feasibility of the SWIP approach carried out in a multi-chamber cluster-tool apparatus. The one more process that is necessary in order to provide a complete in-situ processing sequence is a dry etching of the contact stripes through the SiO, layer onto the InP-based material. An excellent stripe geometry definition by ECR-RIE process through a stainless steel stencil contact mask, to allow for the complete single wafer integrated process ohmic contact processing sequence, was developed and demonstrated. Since chemical deposition of metals onto III-V materials is a new area of research and development, only a relatively small volume of reported results is available. Thus, the following chapter deals solely with the results observed at only two conducting layers, the W and the TiNX,11851deposited onto InP and related materials by means of the RT-LPMOCVD technique. TiN, Metallization Ohmic Contacts Titanium nitride (TiN.J thin films are of great interest in coating metallurgy, semimetal technology and microelectronic applications. TiN, films display an interesting combination of properties such as optical properties which resemble those of gold, hardness greater than all elemental metals and sapphire, and almost as hard as diamond, a very high melting point (about 300°C) which implies high stability and excellent diffusion barrier properties, an inert nature for most of the chemicals and solvents, and finally good electrical conductivity, higher than other metals, such as titanium. For microelectronic applications the TiN, films are most commonly used in Si-based large-scale integrated circuits (LSI) technology, where they perform as an excellent diffusion barrier between the titanium silicide layer adjacent to the Si substrate and the W ohmic contacts. This novel W!TiNJ TiSi/Si structure was proposed to suppress rapid silicidation of the W
Deposition of Metals as Ohmic Contacts to InP layer, as a result of Si out-diffusion higher than 800°C~[~WU8~l~
221
from the TiSi layer, at temperatures
TiN, thin films have also been used in TiN/Ti/Pt/Au heterostructure diffusion/bonding metallization scheme for 0.5 pm gates in GaAs/AlGaAs high electron mobility transistor HEMT devices,[igOl and for generic applications in GaAs device technology both as Schottky and ohmic metallization schemes.[l91][192] TiN, films may be deposited by reactive sputtering of titanium in an Ar-N, ambient[1g3J-11g71by evaporation of titanium in the presence of N,, followed by a 700-900°C inert gas anneahng,l1g8l reduction of TiSi, layer by NH, at 900”C,l lWl and by the chemical vapor deposition (CVD) technique, either at atmospheric pressure (APCVD) or at low pressure (LPCVD).[2011-t2041 The latter technique, which was introduced during the last two years, is of great interest in conjunction with III-V compound semiconductor technology due to the sensitivity of these materials to surface degradation associated with ion beam deposition processes. Thus, while processing III-V materials, and in particular, those which include the more volatile group V elements such as GaAs and InP, the various ion bombardment TiN, deposition techniques are not appropriate. The LPCVD TiN, films were deposited with titanium tetrachloride (TiCI,) and ammonia (NH,) as the reactants in the temperature range of 450-700°C and pressure range 100-300 mtorr, at deposition rates of up to 100 run/mm. The electrical resistivity of the films varied in the range 50 to 100 usZ cm, depending solely on the amounts of carbon and oxygen that were entrapped in the layers. The films were typically stable at postdeposition annealing temperatures up to 550°C. However, since chlorine chemistry is widely used as an etching technique for InP and related materials, the use of it for layer deposition on InP is unaccepted. Recently Fixl205ll206ldemonstrated deposition of TiN, films using the earlier reported [w-w1 volatile tetrakis (dialkylamido) titanium (IV) complex as a liquid metalorganic precursor. Two ofthese compounds, the dkthylamido titanium (DMATi-Ti(NM%),) and dimethylamido titanium (Ti(NEQ4), have been used to deposit films of TiN, at temperatures as low as 300°C. These films had a stoichiometric Ti and N composition, but were heavily contaminated with oxygen and carbon. They have successfully demonstrated deposition onto glass, silicon, vitreous carbon, and boron substrates. Using the RT-LPMOCVD system, shown in a schematic manner in Fig. 28, layers of TiN, were deposited onto InP, using a combined chemistry of DMATi and NH3.1104111851
222
Compound Semiconductors
Figure
28.
Schematic representation
of the reacting RT-LPCVD
reaction chamber.
SiO, layers were deposited onto the InP by means of RT-LPCVD prior to the metal deposition in order to take advantage of the opportunity to integrate the processes associated with the dielectric spacer deposition. Subsequently, the contact windows were opened by means of reactive ion etching (RIE) and the contact metallization deposition was carried out.[1821 The SiO, films were deposited under various processing conditions, such as, temperature of 350 to 55O”C, pressures of 5 to 15 torr, durations of 5 to 600 set, and [O,]:[SiH,] ratio in the gas mixture. Pressure was identified as the dominant parameter influencing the quality of the film morphology. The best morphology was achieved while depositing the SiO, fihn under a pressure of 9.5 torr. Temperature and deposition duration were found to mainly influence the deposition kinetics. Deposition conditions of 500°C and a duration of 30 set were found to allow for film growth with a thickness in the range of 0.1 to 1 urn. The 0, to 2% diluted silane ratio in the gas mixture had the major influence on the mechanical and optical properties of the SiO, films. Table 3 provides a summary of those properties of SiO, films deposited from four different gas mixture combinations (O,:SiH,= 5, 10, IS, 20). One can see that the 10: 1 gas mixture allowed for the highest deposition rate and the lowest wet etch rates, evaluated through the wet standard p-etch solution. Diluting the SiH, concentration in the gas mixture led to lower refractive index values, but the stress sustains basically with a constant value in the low compressive range while the film density decreased. Figure 29 shows the SiO, layer growth rate as a function of the reciprocal deposition temperature for three different deposition pressures of 7.5, 8.5 and 9.5 torr. All the processes exhibited an Arrhenius behavior
Deposition of Melals as Ohmic Contacts to InP 223 from which the deposition apparent activation energies were extra&xl to be 0.12,0.14andO.15 eV. Figure30providestheentiresetofpropertiesofthe RT-LPCVD SiO, films, all as a function of the [OJ:[SiH,] ratio at the reactive gas mixture. Table 3. Properties of RT-LPCVD SiOz Films Deposited onto InP at 550°C, 9.5 Torr, for 30 Seconds, as a Function of the 0, to 2% Diluted Silane in the Gas Mixture Sii2 F*n Rupatks -lllhms Rclktivc No. fO,I:ISiH~l 1 2 3 4
5 10 P
Stress’
Density P-wclE4c!bRm
bm)
Index
(x 10’ dyne * cm-*)
(nr. cm-3
320 880 590 140
I.488 1.467 1.458 1.445
-0.4 -3.0 -4.5 -3.5
2.366 2.236 2.247 2.236
hi
EcREadlRae
. set-‘1 bun* mill-9
0.82 0.25 0.32 0.51
54 45 38 36
‘AhtRSSUm~=
Sii2 DEPOSITION TEMPERATURE (‘C) 600
550
500
450
400
I
I
I
I
I
350
1
300
.
10
1 1.1
1.2
1.3
1.4
1.5
1.6
1.7
1000/T (K-l)
Figure 29. RT-LFCVD growth rate on InP as a function of the recipracai deposition temperature, for three sets of samples that were deposited at pressures of 7.5, 8.5 and 9.5 torr. Inserted is a SE&l cross-sectional micrograph of the SiO, film deposited onto InP at 55O”C, 9.5 torr, 30 see duration.
224
Compound Semiconductors
35-
1.51
2.37 SiO2/InP RT-CVD:
‘; ln . 30E c p $
25-
2
1.50
T = 550°C t =3os P = 9.5 Torr
.
0.6
0.7 ‘;, . E 0.6 C
$49 z
F
Y g
0.5 6 Li b
z
! g
Lz
20-51.46
15-
3
s 0.4 -
El.47 2 *
IO-
1.46
5-
1.45
0.3
I 5
10
2.25 15
20
0.2
(D2MSiW
Figure 30. SO, RT-LPCVLI film properties as a function of the [0,]:[SiH4] gas mixture ratio.
Subsequent to the SiO, RT-LPCVD, the deposited wafer was RIE using a stainless-steel mask in order to process the contact window openings. These features were replicated into the SiO, layer to allow for the subsequent deposition of the contact metallization. Figure 31 shows a portion of a 2” round etched Si0.JI~~53Ga,,47As/ wafer (Fig. 31a), a close-up of a 100 pm mask opening (Fig. 3 1b) and a 100 pm etched feature in the SiOz (Fig. 3 lc). TiN, films were then deposited into the patterns in an attempt to form ohmic contacts to the InP. Those films were deposited onto InP by means of rapid-thermal-low-press-metalorganic-chemical-vapor-deposition (RTLPMOCVD) using tetrakis (dimethylamido) titanium (DMATi) as the precursor for the deposition. The influence of the deposition temperature, pressure, and duration on the growth rate and film properties has been Figure 32 shows the variation of the TiN, film widely investigated. t1031t1041 thickness deposited at six different chamber pressure conditions in the range of 5 to 35 torr, as a function of the deposition duration, which took place at constant temperature of 42O”C, while the DMATi bubbler was held at 80°C. A clear dependence of the growth rate on the deposition pressure is
Deposition of Metals as Ohmic Contacts to InP
225
observed. In addition, a nucleation period for the initial TiNx deposition to occur is observed regardless of the applied pressure, however, nucleation times decreaseas the chamber pressure is increasedfrom 5 to 35 torr. For pressuresof 10 torr or higher, two different deposition kinetics regimes are observed,both of which perfonn linearly in all the selectedpressures. The inserted table gives the actual TiNx film growth rates in the two regimes. The inserted high resolution SEM cross-sectional micrograph shows the TiN4 film deposited onto InP at 420°C and 10 torr for about 110 sec.
Figure
31.
(a) Portion
etched through
of a 2!1 round SiOx (0.5 I!m thick)/Ino.S3G80.47 As/InP
a stainless-steel stencil mask; (b) close-up of a loo
structure,
I!m opening
in the
stencil mask; and (c) the loo I!m etched feature formed in the SiOx layer.
Figure 33 shows a TEM cross-sectional (Fig. 33a), plan-view bright field (Fig. 33b), selected area diffraction (SAD) pattern (Fig. 33c), and plan-view dark field (001) reflection (Fig. 33d) micrograph of the TiNjInp sample, as-depositedat a temperatureof 450°C and a pressureof 10 torr for 80 sec. A very tine-grained polycrystalline film microstructure containing only the TiN phase was observed. From the cross-sectional micrographs it is concluded that the loP did not suffer any degradationsthrough the TiNx deposition cycles, which resulted in a sharp TiNjInp interface, regardless of the variations in the total pressure and deposition duration. Table IV gives a summary of some other TiNx film properties, such as resistivity, stress and dry etching rate, as a function of the film deposition pressure.
226
Compound
Semiconductors
TiNx/ InP AT -LPMOCVD T DMATi = 80 Oc T = 420°C
200
180 No
140 E
120
I AA .
I
(nm/s)
1
5
2 3 4
10 15 25
5 6
.s.
I 1-
p
.(Torr)
160
C/) C/) w z ~ C,)
I
30 35
AB .
(nm/s)
0.86 1.15 2.01 2.22
I
0.86 2.82 3.20 3.60 4.30 4.50
2.79 3.75
0
100 Ps = 35
~ -1
P4 = 25
= 15
2= 10
p,\ = 30
u.. x
80
z i= P1
60 1-
RA
6
I
00
20
40
60
DEPOSITION
Figure
32.
5
0
40
20
=
80 TIME
TiNx film thickness on InP substrates as a function
various chamber total pressure values.
I,
I,
100
120
140
(s)
of deposition
duration
in
Deposition
Figure
33.
TEM
(a) cross-sectional
pattern, and (d) plan-view at 450°C,
of Metals as Ohmic Contacts to InP
micrograph,
dark field micrograph
(b) plan-view
bright
field,
227
(c) SAD
of TiNx film that was deposited onto InP
10 torr, and 80 sec.
Table 4. Properties ofRT-LPMOCVD TiNx Films Deposited onto loP at 450°C and 30 SecondsUnder Different Chamber PressureConditions TiN .Film
Properties
Chamber Pressure Resistivity StresS (forr)
ECR Etch Rate (angstrom. min-I )
228
Compound
Semiconductors
Figures 34a and 34b show high resolution TEM cross-sectional micrographs of TiNx films that were deposited onto loP substrates at pressure of9 torr from 30 sec using a gas mixture ofNH3:DMATi 1:10 at temperatures of 450°C and 550°C, respectively. These micrographs provide clear evidence of the abruptness of the TiNx interface, exhibiting an interfacial disorder of about two to three atomic monolayers, regardless of the deposition temperature. As mentionedabove, someevidenceof epitaxial islands of the deposited TiNx was reflected at the XRD patterns and are observed in the high resolution TEM micrograph.
(a)
(b)
Figure
34.
TEM
high resolution cross-sectional micrographs
InP substrate at (a) 450°C and (b) 550°C.
of TiNx films deposited onto
Deposition of Metals as Ohmic Contacts to InP
229
Film stoichiometry and impurity incorporation were studied by means of AES and XPS techniques. Figure 35 gives a combination of an AES depth profile and XPS spectrum of a TiN, film that was deposited at 450°C and 10 torr for 80 sec. The XPS spectrum was taken after 6 min of sputtering and thus provided information about the bulk properties of the film. The chemical composition of the film was found to be 27% Ti, 3 1% N, 7% 0 and 35% C. Thus, a N/Ti ratio of 1.14 and C/Ti ratio of 1.3 were detected in this film. The high concentrations of both C and 0 are typical of TiN, films deposited by means of MOCVD using the DMATi precursor.t2111t2121Three main peaks in the XPS spectra were of special interest, providing information about the nature of the incorporated light-elements. These are the carbon (1s) peaks (282 and 284-286 eV), the nitrogen (1s) peak (396.9 eV), and the Ti (2~) peak (454.8 ev). The carbon and titanium peaks at 282 and 454.8 eV reflect many possible Ti-C bonding configurations, and in particular, the carbide forms. The secondary carbon peak at 284.6 eV represents the carbon incorporated into the various organic groups. The nitrogen peak at 396.9 eV reflects nitrogen incorporated in the nitride (Ti-N) form. Some other combinations of ternary bonded structures, containing these three elements, are possible as well. TiNI/ 6-
InP
P=lZTorr
BINDING ENERGY, (eV) Figure 35. XF’S spectrum and AES depth profile of TiN film that was deposited onto InP at 450°C and 10 torr for 80 sec.
230
Compound
Semiconductors
The electrical properties of TiNx contacts to P-Ino.S3Gao.47As (1.2 x 1018cm-3 Zn-doped) were measured as well. Figure 36 shows the bias current (V-I) characteristics of the TiNx/p-InGaAs (0.2 ~m) contacts. Heating the contact to 500°C resulted in a clear degradation of the ohmic behavior and led to a transition to a rectifying contact. The Schottky barrier height of this as-depositedcontact was measuredby meansofV-1 measurements at various temperatures to be 0.44 eV and its specific contact resistivity was 3 x 10-4Q.cm2. This value was decreasedby about one order of magnitude upon sintering the contact at 500°C for 30 sec. Inserted in this figure is a SEM cross-sectional micrograph of the TiN/p-Ino.s3Gao.47As sample that was post-sintered at 450°C. The film resistivity was 80-40 ~Q.mm, with the minimum value as a result of post-heating at 450°C.
-3"6~ '-
-50
c
0
5.'
,.0
CURRENT (mA} Figure 36. Bias-current characteristics of TiNx contacts on p-Ino.s3Gao.47As(I2 x 1018 cm.3), in the as-deposited condition and after sintering at various temperatures up to 550°C for 30 sec. Inserted is a SEM cross-sectional micrograph of the sample that was post-sintered at 450°C.
Tungsten (W) Ohmic Contacts. Tungsten is of special interest as an ohmic contact metallization to loP and related materials due to its relatively low resistivity (about 6 ~.0..cm) and its stability, in particular its electromigration resistance. The various W physical deposition techniques suffer some inherent deficiencies when applied to III-V compound
Deposition of Metals as Ohmic Contacti to InP 231 semiconductors. Electron-beam evaporation uses a high beam energy, which leads to surface degmdation and wide interactions and diffusion due to heating of the substrate to high temperature. Sputtering techniques may lead to some surface radiation damage. In addition, step coverage and conformity of the deposited layers, when depositing a blanket film or attempting via filling and narrow contact stripe coverage, are essential for the current device technology and cannot be achieved by the physical deposition techniques. As a result, the chemical vapor deposition (CVD) of tungsten has become a focus of interest in recent years. Tungsten can be CVD by Hz or SiH, reduction of WF, or WC6, or by the pyrolysis of W(CO),. In blanket tungsten CVD, the WF, is used ahnost exclusively as the W source, reduced by either H, as !%-I,, or a mixture of the two.[2131-[21gl Selective deposition of tungsten has been already reported, in particular, while deposited into exposed silicon regions in a Si02-masked surface.~nol-~~l The selective deposition is an extremely sensitive process to deposition conditions such as pressure and temperature, and in addition, is significantly affect& by any slight change in the substrate surface chemistry. Metallic contammation on the dielectric surface, or chemistry surface poisons (such as Cr02F9 on the semiconductor surface, may prevent the selective deposition mode. Recently, the RT-LPCVD technique was executed to deposit W films, and the influence of the various deposition parameters, such as the Ar, H2, and WF, gas flow rate, chamber pressure, deposition temperature and duration, and post-deposition sintering temperature and duration, on the film deposition kinetics and film resistivity was investigated.~“] The growth rates were calculated from the thickness of the deposited layers. From initial experiments, the optimum gas mixture of 1500 SCCM H2, 50 SCCM Ar, and 20 SCCM WF, (H,:WF, of 75:1), and total pressure of about 4.5 torr were established. Deposition was never observed for temperatures lower than 4OOOC. Temperatures higher than 500°C, however, led to sporadic and uncontrolled deposition. Figure 37 gives deposited-film thickness as a function of the substrate temperature, changing from about 20 nm for deposition at 400°, to about 400 nm for deposition at 5OO”C,all for 10 set of deposition time. The Arrhenius plot shows the W apparent film deposition energy calculated to be about 1.17 eV/mole. All these films were found to have resistivity in the range of about 8 x 103to 21 x 104 pS2cm, as deposited.
232 Compound Semiconductors W DEPOSITION TEMPERATURE 500 I
490 I
480 I
470 I
460 I
450 I
RT - LPMOCVD t=1os =1500 seem “2 Ar =5OSCClll WFg=20scrm PCHAMBER= 4.5 Ton
I 1.29
I 1.31
I 1.33
I 1.35
I 1.37
I 1.39
1000/T (K-l)
Pin 37. RT-LPCVD W film thickness as a function of the reciprocal deposition temperature.
In an attempt to reduce the high resistivity of the W films an in-situ post-deposition, sintering processes were applied subsequent to the deposition under a vacuum of better than 1 x 1o’5torr in the same chamber. Figure 38 shows the significant reduction of the W film resistivity from the initial value of about 2 x lo4 pCkcm for deposition at 450°C, to about 55 @-cm as a result of sintering this sample at 500°C. In particular, a significant reduction is observed for sintering at temperatures exceeding 45OOC. In addition, this figure shows the thickness of the reacted layer measured by means of TEM cross-section. This increased to double its as-deposited thickness for heating at 500°C for 30 sec.
Deposition of Metals as Ohmic Contacts to InP
WllrlP T DEP = tDEP = PDEP = XDEP = 300
233
RT - LPMOCVD = 500 seem P% RA‘ = 50 seem k,, = 50 seem
450°C 10 s 1.7 Torr 100 nm
POST-DEPOSITION SINTERING = 30 s
I
I
I
I
350
400
450
500
110
POST-DEPOSITION SINTERING TEMP (“C)
Figure 38.
RT-LPCVD
W film thickness and resistivity as a function of the post-
deposition sintering temperature.
Figure 39 shows the W film thickness and resistivity as a function of the WF, flow rate, for deposition at 450°C for 10 set at a total pressure of 0.75 torr. Almost a linear correlation with a slope of about 1.8 nm/SCCM is observed in the WF, flow rate range of 10 to 40 SCCM. The resistivity, however, is relatively constant at values of 68 x lo4 @*cm, with some increase for flowing WF, at rates higher than 25 SCCM. The correlation between the thickness and resistivity of W films that were post-deposition sintered at 500°C and both the Hz flow rate and the chamber pressure is given in Fig. 40, for two deposition temperatures of 400°C and 500°C, for 30 SCCM of WF, and 50 SCCM of Ar in the reactive gas mixture. A linear correlation between the thickness of the deposited layer and the total chamber pressure, regardless of the deposition temperature, is observed with a slope in the range of 60-90 nm/torr. A strong dependence of the resistivity on the total chamber deposition pressure at all
234
Compound Semiconductors
deposited temperatures was observed, revealing about a factor of two increase in the resistivity per increase of 1 mtorr in the chamber pressure.
140
W/lnP
RT - LPMOCVD
T = 450°C t =lOs p = 0.75 Torr
01103 10
20
30
40
WF6 FLOW RATE (seem)
Figure 39. RT-LPCVJI during deposition.
W film thickness and resistivity as a function of the WJ?, flow rate
The microstructure of the W RT-LPCVD films was evaluated and Fig. 41 shows the AES depth profile of a RT-LPCVD W as-deposited film, deposited at a temperature of 450°C and pressure of 4.5 torr, and of the same sample after post-deposition sintering at 500°C for 30 sec. Already, as deposited, a wide inter-facial reacted layer with a ternary W-In-P stoichiometry composition and a W top layer containing a large amount of P was observed. The post-deposition sintering at 500°C leads to the widening of this reaction with a total consumption of the W to form a ternary cap layer adjacent to the InP substrate. The thermodynamic analysis of these reactions is very complicated due to the lack of phase diagrams for both the InW and P-W binary systems. Some data, however, is available, predicting the unstable nature of the W-InP system. For the case of P-W, two of the compounds that may have been formed, the WP, and WP, , are polymorphic
Deposition of Metals as Ohmic Contacts to InP
W/InP RT - LPMOCVD
TDEP (“C) =
235
400
400 -
350 -z c
300 -
z s Y 0
250 -
F 4 IL
200 -
150 -
100 -
50 (seem)
0
= 250
I , 1
I 750
500
I CHAMBER
, 2
I PRESSURE
I 1000
I 1 3
I:,,]
I , 4
102
(lorr)
Figure 40. RT-LPCVD W film thickness and resistivity as a function of the total chamber pressure and H, flow rate during deposition.
forms which are met&able at low temperature and normal low pressure conditions. Those compounds contain 67 and 85 at.% of P, respectively, and are very reactive at the given RT-LPCVD condition of 350-5OO’C and 0.5-10 torr. For the In-W system, no information on the existence of intermetallic phases has been reported. However, a very low solubility of about 0.01 at.% of W in In was observed for the RT-LPCVD temperature range Extensive TEM work was done to evaluate the initial as-deposited layer microstructure and composition. Figure 42 shows the flat-on brightfield (left side) and dark-field (right side) images, as well as the selected area electron diffraction (SAD) pattern of W films that were deposited at the same deposition conditions ofAr:H,:WF, flow rate of 50: 1500:30 SCCM at
236
Compound Semiconductors
WnnP FIT - LPMOCVD T = 450% t =lOs P = 4.5 Torr
60
13’ -
k* f%r
= 50 seem
&F 8
= 30 seem
(a) As-DEPOSITED *---___----
s 8 f
P
(b) AFTER POST-DEPOSITION 60
= 1500 seem
SINTERING
T = 500% t =3os
60
C -*-*%~.4.._..L 20
40
I
I
I
I
60
60
100
120
SPUTTER TIME (s)
Figure 41. AES depth profile of W film RT-LPCVD onto InP substrate at 450°C (a) asdeposited, and (a) after post-deposition sintering at 500°C.
total chamber pressure of 4.5 torr, however with different temperatures of 450°C (Fig. 42a) and 500°C (Fig. 42b). In both cases, no post-deposition sintering was applied to the samples. The film that was deposited at 450°C shows an amorphous W film structure, with some spreading of a P-W binary polycrystalline unidentified phase. The sample that was deposited at 5OO”C, however, was deposited in a polycrystalline structure and comprised a preferred oriented (see SAD of Fig. 42b) polycrystalline needle-shaped phase, which was found by means of EDX to contain a significant amount of In and P in addition to W.
Deposition of Metals as Ohmic Contacts to InP
237
Figure 42. rEM plan view blight-field (left side) and dark-field (light side) images, as well as SAD patterns of W RT-LPCVD film deposited at the same conditions of Ar:H2:WF6 flow rates of 50:1500:30 SCCM and pressure of 4.5 torr at temperatures of (a) 450°C, and (b) 550°C.
Figure 43 shows bright-field (left-side), dark-field (right-side) and SAD ofW film that were depositedunder the sameconditions of Ar::Hi WF 6 flow rates of 50:2500:50 SCCM, 450°C for 10 sec and pressure of 7.25 torr. These samples, however, were sintered after deposition. The one sample (Fig. 43a) was post-deposition sintered at 450°C for 30 sec, while the other one (Fig. 43b) was post-deposition sintered at 500°C for 30 sec. Both samples show the same needle-shapeternary phase with a preferred oriented grain growth, as was observed earlier in the sample that was deposited at 500°C. Figure 44 shows the stress-temperature(0"-T) plots of three different W/InP samples as representatives of a much wider set of experiments. Those films were deposited at 450°C for 10 sec from gas mixtures that comprised 50 SCCM of Ar, 50 SCCM ofWF6, and 250 (plot 1),500 (plot
238
Compound
Semiconductors
2) or 1500 SCCM (plot 3) ofH2. The throttle valve was held at a constant opening and thus, the variations in the H2 flow rates led to different pressures of 0.8, 2.5, and 5.5 torr in the chamber during the deposition cycles. Low H2 flow rates of250 and 500 SCCM led to deposition of films with a compressivestress of -4 x 109and -2 x 109dyne.cm-2,respectively, while a higher H2 flow rate of 1500 SCCM led to the deposition of tensile films with a stress value of 1 x 109dyneocm-2.AIl these samplesdeveloped a minor plastic deformation through the heating cycles, as reflected by the very small hysteresis of the 0"-T graphs. It is interesting to emphasizethe correlation between the level and type of the stress built in the W RT LPCVD films and the overall chamber pressure, a correlation that was also observed for sputter-deposited W filmS.[18] In these given sets of deposition parameters,the zero stresscondition was achievedat an H2 flow rate of 1000 SCCM in a total chamber pressure of 4.5 torr.
Figure 43. rEM plan view bright-field (left side) and dark.field (right side) images as well as SAD patterns of W RT-LPCVD films deposited at the same conditions of Ar:HiWF6 flow rates of 50:2500:50 SCCM, pressure of 7.25 torr and temperature of 450°C, after post-deposition sintering at (a) 450°C and (b) 500°C.
Deposition of Metals as Ohmic Contacts to InP
239
WllnP RT - LPMOCVD T = 450% t =lOS
E 0
+4 _
R,
= 50 seem
=
5. $
-l-
!$
-2-
EY -3-
1500 seem
-
-4
-8
-5
I
I
I
I
I
100
200
300
400
500
MEASURING TEMPERATURE (“C)
Figure
44.
Stress of W RT-LPCVD
films on IJIP as a function
of the measuring
temperature.
The RT-LPCVD tungsten film linear expansion coefficient was found to be in the range of 5.1 to 6.1 x 1Om6 “C-l, the biaxial modulus was measured to be in the range of -1.1 x 1013 to -3.2 x 1013 dynecm-*, and the tcmperaturedependent expansion coefficient to be about 7 x 10” + 1.6 x 10m8 t - 2.2 x 10-11t*“C-1. The stability of the W film RT-LPCVD that was deposited at 450°C from a H&r:WF6 gas mixture of 1500:50:50 SCCM was evaluated by tracking the stress changes through a 800 hr thermal cycle at 300°C, as shown in Fig. 45. The film was found to be very stable as seen in the o-T plot.
5.0
CONCLUSIONS
Stable and robust metallization schemes for ohmic contacts have always been important in order to assist an excellent short and long term performance of the devices. The more advanced the devices, and in particular, the optoelectronic devices become, the more demands that are imposed on the ohmic contact technology such as low surface damage deposition, ultra-pure metal-semiconductor interfaces, high temperature
240
Compound Semiconductors
deposition of stable stress-free ultra-thin films, and excellent current conductance, which are the key features for the manufacturing of advanced device contacts. Some demonstration of advanced and new conceptual approaches was provided through this review while introducing the idea of integrated contact manufacturing process by means of rapid thermal low pressure chemical vapor deposition technique. Much more work is still required to tune-up these advanced concepts and to turn them successfully from a research and development feasibility demonstration to a real widescale manufacturing concept.
0.0
NE 0 . 2 0”
W/lnP RT - LPMOCVD DEPOSITION CONDITIONS T = 450°C =lOs P = 5.5 Torr
-0.2-t
p” -0.6
- Rn;
= 1500 seem = 50 Torr
“0
Lii
-1.4 t -1.81 0
I 400
I 200 AGING
TIME
I 600
8
(h)
Figure 45. Stress of W RT-LPCVD film on InP as a function of time while held at 300°C.
ACKNOWLEDGMENTS I gratefully acknowledge the many contributions and very close and friendly help of a lot of my AT&T Bell Laboratories colleagues. In particular, I would like to express my appreciation of the work provided by C. R. Abernathy, F. Baiocchi, U. K. Chakrabarti, S. N. G. Chu, W. C. Dautremont-Smith, M. Geva, W. Hobson, E. Lane, J. W. Lee, S. G. Napholtz, S. J. Pear-ton, P. M. Thomas, and B. G. Weir, as well as my colleagues W. Savin from NJIT, and K. S. Jones from the University of Florida.
Deposition of Metals as Ohmic Contacts to InP
241
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Compound Semiconductors
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5 Surface Processing of III-V Semiconductors Sidney I. Ingrey
1.0
INTRODUCTION
This chapter discusses the composition and sources of air-formed surface contamination with reference to the III-V surface reactivity and composition. A brief comparison is made between the resultant composition and structure of III-V surfaces exposed to the more commonly used chemical etches, followed by a discussion on the nucleation, growth and electrical properties of overlayers deposited on contaminated surfaces. Insitu contamination removal techniques are assessed and the necessity for surface passivation to reduce contamination of the semiconductor surface during air exposure is addressed. Using the experimental results obtained from different surface treatments, we develop standard surface preparation procedures which can be used prior to most III-V interface engineering processes. To conclude the chapter, we present results of applications of these surface treatments in device fabrication. Control and precision in surface and interface engineering is becoming increasingly critical in III-V device processing as more demanding applications of optoelectronics and high speed devices occur. Empirical derivation of many surface preparation procedures has been successful in the past, but the need for increased process flexibility means moving away from the empirical approach to a more complete understanding of the chemical
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Compound Semiconductors
physics involved with each process step. We discuss the use of published data and our own results in the development of simplified surface processing procedures for III-V’s which reduce our dependence on the empirical approach. Nascent semiconductor surfaces exposed to air acquire a contamination layer which influences most of the surface preparation procedures necessary prior to interface formation. In this chapter, therefore, we are primarily concerned with the formation and removal of air-formed contamination, passivation of the nascent surface and maintenance of the surface stoichiometry. The latter is required since a loss of stoichiometry can result in the formation of metal bonds (M-M), which may strongly affect the properties of subsequently formed interfaces. The cleaning of semiconductor wafers, suitable for electronic or optoelectronic device processing, involves three levels of surface treatment. The first is designed to remove gross contamination, which is primarily hydrocarbon deposits, resulting from the initial slicing procedure for producing thin wafers from the original single crystal. The second removes particulate and metal atom contamination, resulting from polishing residues and the third provides atomically clean, and for III-V semiconductors, stoichiometric surfaces. The first two procedures are usually carried out by commercial suppliers and are not discussed further here. Epi-ready wafers, which have a deliberately formed thin native oxide on the surface, can be obtained from wafer vendors and have been used successfully, but a reliance on vendors for this critical step may not be appropriate in all cases. Procedures for producing atomically clean stoichiometric III-V surfaces, whether of the starting substrate or between process steps, are often at variance and numerous recipes have been derived. Procedures used may include a dip, blow dry, squirt, spin, rinse, pre-bum, or vapor degreasing, combined with chemical treatments such as (H,0JI-I,S0,/H20), (Br/ CH,OI-I), buffered I-IF, ((NIQ2S208/H2S04) (HF/H,O), HF&H,OH or (HCl/H,O). We avoid, however, discussing the pros and cons of different published recipes because these are usually tailored to specific process steps and may not be generally applicable. Surfaces prepared for particular applications may be considered clean if they fulfill the required function, even though the surface impurity concentrations may vary by orders of magnitude. This approach is very pragmatic since the sensitivity of surface analytical techniques for submonolayer detection is limited. In addition, contamination may take place either prior to or during analysis, or the analysis technique may
Surface Processing of III-V Semiconductors
253
modify the surface in such a way that the surface composition is very different from the surface actually used in a particular process step. An example of this effect is the extreme sensitivity of the initial oxidation state of surfaces to the electron beam conditions typically used in surface analytical techniques such as Auger spectroscopy. This sensitivity can result in decomposition of the oxide and oxygen desorption, a process which can take place so rapidly that the oxide may not even be detected. Perhaps the major limitation to determining the composition and structure of surfaces actually used in many applications is that the surfaces should, ideally, be analyzed immediately prior to deposition of the overlayer. However, this approach is impractical in most processing systems. From the above considerations, we can see that the term clean is very subjective and can lead to considerable misunderstanding when comparisons are made between different surface preparation techniques. We attempt to avoid its use here and consider surface preparation as part of a process to form a reproducible, deliberately engineered interface. Surface cleaning is often as much an art form as a science and this is reflected in the effectiveness of the empirical approach in matching surface preparation procedures with subsequent processing steps such as metallization or epitaxial growth. Our understanding of the surface composition and structure, therefore, often contributes little to the effective application of the process. This situation is due not only to the difficulty of characterizing surfaces and interfaces discussed above, but also to a lack of control over the ambients to which the surfaces are exposed during real world processing. For example, the composition of cleanroom air may vary considerably from one location to another and may indeed vary considerably within the same cleanroom.lll This argument also applies to water, chemicals and process gases to which nascent surfaces are exposed. A further complication is the relationship between the surface structure of a substrate and its chemical reactivity. The chemical reactivity of a surface may depend on the density of bulk defects intersecting the surface which, in III-V compounds, can vary considerably from one single crystal boule to another, and from the seed to the tail end of the same boule. Considerable effort is being expended to eliminate these defects and recent developments using Bridgman growth methods, for example, the vertical gradient freeze (VGF)121technique for crystal growth, goes some way to achieving this. The mass of cellular dislocation networks and low-angle grain boundaries typical of device quality material is still, however, present.131In addition to the above,
254
Compound Semiconductors
any process which creates defects at the semiconductor surface will enhance the chemical reactivity of the surface. Our observations show that the surface reactivity also depends on the composition of the III-V compound; for example, AlGaAs, InGaAs, and GaAs have, in this order, decreasing reactivity on exposure to oxidizing ambients. For example, after ten minutes exposure to UV/ozone for a given set of conditions, the oxide thicknesses on GaAs, Ir+,ssGa,,s7As and Al,,,G~.&s are 2.0, 3.5 and 6.5 nm respectively. These considerations mean that the most effective procedures for producing appropriate surface structures should be designed to be insensitive to changes in surface reactivity. In practice this is difficult to achieve. A discussion on the surface preparation of each III-V compound would be prohibitively lengthy, therefore we concentrate on deriving general surface preparation techniques for the most commonly used III-V substrates, GaAs and InP. Whereas these techniques may have a wider application, they will usually have to be modified to take into account differences in surface reactivity of different materials. For example, although sacrificial oxides formed by UV/ozone exposure can be thermally desorbed in vacuum from both InP and GaAs, complete removal from InGaAs below the decomposition temperature requires the presence of atomic hydrogen.t41 We start by discussing the relationships between oxidation and hydrocarbon contamination of nascent surfaces exposed to different ambients, followed by a brief discussion of the more commonly used III-V surface treatments. Since most surfaces will be exposed to air after chemical treatments, we discuss the effect of the presence of an air-formed contamination layer on the characteristics of some typical interfaces. The necessity for using temporary surface passivation to reduce contamination due to air exposure is outlined. Finally, a surface processing procedure is proposed as a way of creating standard surface conditions in preparation for the formation of many of the interfaces generated during device processing.
2.0
REACTIONS ON CLEAVED (110) SURFACES
To prepare chemically pure III-V semiconductor substrates for surface reaction studies, it is convenient to use the (110) cleavage planes as reference substrates, since these can be readily prepared in vacuum, air, or solution. Devices are, however, fabricated on (100) surfaces and
Surface Processing of III-V Semiconductors
255
correlations between reactions on the two surface orientations must be assessed. We have attempted this correlation by comparing surface reactions on cleaved (1 IO), cut and polished (100) and epitaxial layers grown by metal organic chemical vapor deposition (MOCVD) on (100) substrates. Figure la shows Auger spectral data of a low-doped (2 x 1016 S) InP substrate which has been cleaved in the analysis chamber at 2 x lo-* Pa. The spectrum was collected while scanning the electron beam over the surface under conditions which were carefully selected to minimize contaminant desorption; the sample is tilted at 45” with respect to the electron beam. The elemental sensitivity for both C and 0 is about 0.01 monolayer (ML), but neither C nor 0 is detected. However, if a similar surface is created by cleaving in air and then placed in the Auger system, the spectrum shows the presence of both carbon (hydrocarbons) and oxygen, Fig. lb. Since there was no evidence in our studies or in published literature that indicated a time delay prior to the onset of contamination, oxidizing species and hydrocarbon condensates must compete for the surface real estate immediately when the uncontaminated cleaved surface is exposed to air. Whether or not this contamination is detected will depend on the sensitivity of the detection method used.
In
1 :
1
IGU
100
loo
KIN3IC EmcY.
ev
a,
so0
Figure 1. Auger spectra from: (a) InP cleaved in analysis chamber at 2 x lo-* Pa, (3) cleaved and exposed to air for 10 min.
256
Compound Semiconductors
It is this contamination layer, formed upon exposure to air, which influences all final surface treatments and which can seriously degrade epitaxial growth electrical properties and adhesion of deposited overlayers. An understanding of the relationship between oxidation and hydrocarbon adsorption on surfaces can be valuable in developing appropriate surface engineering procedures. It is generally observed that hydrocarbon contamination during air exposure takes place more rapidly on some surfaces than others. For example hydrocarbon contamination builds up more rapidly on a freshly cleaved surface than on an oxidized surface and, conversely, hydrocarbon-covered surfaces oxidize more slowly than freshly cleaved surfaces. We have demonstrated this by cleaving InP and GaAs in liquid hydrocarbons such as xylene, removing excess liquid, and comparing the effects of air exposure of these surfaces to that of a cleaved surface which had been W/ozone oxidized. An Auger spectrum of the ozone oxidized surface exposed to air for 10 min (Fig 2a), shows a much lower carbon signal than that of the cleaved sample exposed to air for the same time (Fig lb). This result indicates a much lower sticking coefficient for hydrocarbons on the oxidized surface, compared to the nascent cleaved surface. Angle resolved x-ray photoelectron spectroscopy (XPS) of the oxidized surface showed that the C signal was due to hydrocarbons on the surface of the oxide and that the hydrocarbon concentration at the interface was below the XPS detection limit. The Auger spectrum (Fig. 2b) shows that oxidation due to air exposure of the surface cleaved in liquid hydrocarbon has been suppressed by the presence of the adsorbed hydrocarbons, however, some oxidation has taken place and the effective protection by the overlayer is < 10 min. The signal-to-noise in these AES spectra is low because, as discussed earlier, the electron beam conditions have been chosen to limit desorption of the contaminant layer. The time dependence of hydrocarbon coverage on two partially oxidized surfaces is shown in Fig. 3. The cleaved InP (110) surfaces were initially exposed to W/ozone for 5 and 15 set, respectively, to form two different submonolayer oxide coverages. These surfaces were then exposed to lo3 Pa of organic vapor in a chamber attached to an Auger system. After each exposure, the samples were withdrawn into the analysis chamber to record Auger spectral data. The results show that for a three-hour exposure to a hydrocarbon ambient, the total hydrocarbon coverage was related to the initial surface oxide coverage. When the initial 0 signal was low, the C signal increased and reached a value which was twice that for the sample with the greater oxide
Surface Processing of III-V Semiconductors
257
coverage. Clearly, the sticking coefficient of airborne hydrocarbons is higher on the bare semiconductor surface than on the oxide. The significance of this result is made clearer in Sec. 6.
Figure 2. Auger spectra from: (a) cleaved InP (110) oxidized using UV/ozone, (b) InP cleaved in xylene and dried under nitrogen gas jet. Both samples were exposed to air for 10 min. II
I
Figure 3. Auger C and 0 peak intensities, plotted as a function of exposure time to organic ambient, of two partially oxidized InP surfaces. Oxygen I was least oxidized.
258
Compound Semiconductors
It has been shown that hydrocarbons condensed on semiconductor surfaces may, in preference to desorbing, decompose to form carbides when the substrate is heated.t5J This result indicates that simple physisorption of the molecules is unlikely and that specific surface sites may be involved. The role of active sites for adsorption of organic molecules on semiconductor surfaces has been previously investigated.161 In fact, it is easier to thermally desorb oxides than hydrocarbon decomposition products from the surface. From these considerations, it is plausible that the site specificity for adsorption of hydrocarbons, oxygen, and water molecules need not be the same, and this has, in fact, been reported.t51t61171 From our results and those in the literature cited above, a rudimentary picture can be formulated of the structure and composition of a semiconductor surface which has been exposed to air. The surface consists of localized areas of hydrocarbon and oxide, rather than being a random molecular distribution of condensates or reaction products. 2.1
Hydrocarbon
Contamination
The concentration and composition of airborne organic molecules is the largest variable in determining contamination sources. The measured concentrations of organic vapors are typically 30 ug/m3 for class 10 (CLlO) cleanrooms.181 This is not a surprising result since typical cleanroom air filtering systems do not remove organic vapors. The organic vapor composition of some typical CL10 environments, shown in Table 1 (from Ref. 1) is extremely complex with a range of aliphatic and benzene ring based molecules. Large differences in the concentration of hydrocarbons are typically obtained for CL10 environments in rural and urban locations and may differ at different locations within a CL10 room. A total surface arrival rate of all organic species is typically > 2 pg/cm2-set’. If we ignore oxidation effects and make an assumption of an average of twelve carbon atoms per molecule and a sticking coefficient of 1, an equivalent surface coverage of 1 ML may be obtained in < 30 min. Although there arre many sources of these hydrocarbons, including construction and cleaning materials, a major source has been recognized to be auto emissions. However, in some air conditioning systems where humidity control involves the addition of steam, organic chemicals may be added to reduce corrosion of the steam handling system. These chemicals are often volatile organic amines, such as morphaline, used to neutralize carbonic acid which builds up in the steam
Surface Processing of III-V Semiconductors
259
handling system. The sticking coefficient of organic molecules such as morphaline or adducts may vary widely depending on surface composition of the substrates. Table 1. Hydrocarbons Identified in a Class 10 Cleanroom Ambient Cfrom ReJ: I) Trichloroethane Trichloroethylene Tetrachloroethylene Dichlorobenzes Benzene Toluene Ethylbenzene Xylenes C3Akylbenzenes Methylcyclohexane n-Nonane (Nonane) n-Decane (Decane) n-Undecane C 12-C 16 n-alkanes
Cellosolve acetate Hexamethylcyclotrisiloxane Octamethylcyclotetrasiloxane 3-Methylhexane Trimethylhexane Dimethylcyclohexane Tetrachloroethane Propylbenzene 3-Ethyltoluene 4-Ethyltoluene 1,3,5 Trimethylbenzene 2-Ethyltoluene 1,2,4 Trimethylbenzene Butyl acetate
The complex nature of the molecular organic mixture in air and the selectivity that may occur during surface adsorption has made the actual analysis of the surface accumulation of organic contamination elusive and at this time no significant published data is available. 2.2
Native Oxides on III-V Compounds
The oxidation of III-V surfaces with or without the presence of water vapor has been extensively studied. Formation of oxides in dry oxygen,19111011111 however, are not discussed in detail since, in “real-world” processing, surfaces are almost always exposed to moist air or to aqueous solutions. Considerable differences in the formation and composition of oxides produced using these two techniques have been reported. For example, the adsorption rate of water molecules on cleaved (110) InP or
260
Compound Semiconductors
GaAs has been shown to be three orders of magnitude greater than for dry oxygen.tl*l The molecules adsorb dissociativelyl131and OH and H may be These and other studies of native oxides incorporated into the oxide. 11411151 on III-V compounds have raised extensive controversy as to the oxidation mechanism and the structure of the oxides. However, it has generally been shown that the composition of thermally grown oxides may be deficient in the more volatile group V element.1161Anodized and plasma-formed oxides are non-stoichiometric with the group V element forming metal bonds at the oxide-semiconductor i.nterIke.I1~ Oxides formed in aqueous solution or by moist air exposure are also non-stoichiometric,11s~~191 often have non-reproducible compositions and can readily incorporate impurities.t201 In addition, it is difkult to avoid microroughness when oxidizing in aqueous solutionsI*ll and the resulting creation of active sites on the surface has been shown to be a source of defects in epitaxial overlayers.l**l The temperature at which thermal removal of native oxides can take place has been shown to depend on how the oxides are formed. For example, a difference in desorption temperature of 50°C between UV/ozone and air-formed oxides on (100) GaAs has been reportedl23land this temperature difference may be critical where desorption of sacrifkial oxides are required prior to epitaxial growth. Since all chemical processing followed by air exposure results in contaminated surfaces, a brief discussion on the more commonly used III-V surface treatments and the resulting surface composition follows. 2.3
Br/CH,OH
Different compositions of Br/CH,OH solutions are widely used, in combination with mechanical removal of reaction products, to produce polished surfaces of III-V compounds.l24l Figure 4 shows Ga3d and As3d XPS data from cleaved GaAs surfaces which have undergone different chemical treatments. Included are data from a surface which has been polished using BrCH,OH and subsequently air exposed. Depletion of the group V element has occurred giving an As:Ga ratio of 0.75. This loss of the group V element is typical for most III-V compounds,l25l however, a loss of the group III element has been reported for GaSb.1261 Surfaces prepared using the Br/CH,OH etch become rapidly contaminated when exposed to air, forming a non-stoichiometric oxide with metal bonding (MM) at the interface and containing impurities such as hydrocarbons and OH groups. Apart from the case of GaSb, this etch has not been used as the final step in preparing III-V substrates for epitaxial growth; it is however,
Surface Processing of III-V Semiconductors
261
the initial step for many other surface preparation procedures. Although the Br/CH,OH treatment has not been used to prepare GaAs substrates for ohmic or Schottky contacts, several authors have reported using this treatment prior to forming metal contacts to InP.t2711281 2.4
H,SOJH,O,
Most groups active in molecular beam epitaxy (MBE) prior to 1986 used different compositions of H2S0,/H202/H20 as a final etch prior to epitaxial growth on GaAs. This surface treatment generates considerable microstructuret2611291 which contributes to the rapid oxidation that occurs on exposure to air. Removal of the surface microstructure by mass transport,t301t311 at temperatures required to desorb the oxide, is a plausible explanation for the acceptable epitaxial growths achieved; however, it has been reported that, even after extensive DI water rinsing, a trace of sulfur remained on the surface of GaAs after etching with H2SOJH202/H20.[261 There is no information on how this S is distributed or whether it is present after subsequent thermal removal of the air-formed native oxide followed by epitaxial growth. Further disadvantages of using this process to form passivating or sacrificial oxides include the possibility of hydrocarbon impurities condensing on the nascent surface and lack of control of native oxide thickness and composition. 2.5
HCl
Dilute HCl solutions are used to selectively remove thick oxide from GaAs to form hydrophobic surfaces which, initially, are free of native oxide. However, it has been shown by secondary ion mass spectroscopy (SIMS), that traces of chlorine remain on the surface even after extensive DI rinsing.t3*l Surface microstructure has been reportedt331for surfaces treated with HCl solutions and a relationship between DI rinsing times and oxide growth has been established. These experiments were carried out with the sample preparation station and analysis equipment load-lock enclosed in a nitrogen atmosphere so that samples could be transferred from one to the other with minimal air exposure. The oxide was found to be Ga rich with As-As bonds at the oxide-semiconductor interface. Similar results are shown by the XPS data, Fig. 4, although in this case, a twominute air exposure of the surface occurred during the time required to load the samples into the XPS system.
262
Compound Semiconductors
*
As/Ga 0.92
HCl/Dl-HZ0
(4
AalGa - 0.26
As/Ga - 0.75
Br/HeOH
/
Binding Energy (eV)
=
n
.,
A
\
44
As/Ga
-
0.96
11
Figure 4. Ga 3d and As 3d XF’S spectra for oxidized (100) GaAs surfaces prepared by: (a) HCVDI-H,O air-exposed, (b) HCI, static DI, (c) Br/CH,OH, (d) ozone, 10 min.
Dilute HCl is an etch for InP and, although it is not generally used as a surface preparation for this compound, it has been used in a modified form in the well-known RCA clean,(341 containing a final HCl-H,O&O treatment. In this case, reduced oxidation of air-exposed surfaces was determined using C(V,T) measurements,l35l which showed that the oxide was < 1.0 nm thick for air exposure times of < 5 min.
Surface Processing of III- V Semiconductors 2.6
263
NHIOH
Ammonium hydroxide removes native oxides from GaAs, resulting in surfaces which have been shown to contain less microstructure than hydrochloric or sulfuric acid treated surfaces, although the amount of chemisorbed (OH) was much higher.l2gl On air exposure, native oxides < 1 nrn thick are formed. Thicker native oxides (> 2 nm) have been reported to form after air exposure of NI-I,01-I/I-1202-treated InP surfaces.1351 NH,OHbased etches, however, are incompatible with many photoresists and this places restrictions on their process applications. 2.7
HF
Hydrofluoric acid solutions selectively remove native oxides to create temporary hydrogen passivated III-V surfaces. This effect is important in surface processing of semiconductors and is more appropriately discussed in Sec. 5 of this chapter.
3.0
EFFECTS OF AIR-FORMED CONTAMINATION INTERFACE CHARACTERISTICS
ON
It would be erroneous to give the impression that only atomically pure stoichiometric surfaces are suitable for successful interface formation in all applications of III-V compounds. In the following section we discuss the three major types of interfaces created, i.e., between two semiconductors, between a semiconductor and a metal and between a semiconductor and an insulator, and the tolerance that the required interface characteristics have for the presence of interfacial contaminants. 3.1
Epitaxial
Growth
Propagation of a crystal structure from a substrate into a grown layer depends on close atomic matching at the interface. Although elastic strain can accommodate a small amount of lattice mismatch due, for example, to the presence of dopants or in strained layer superlattice structures, the surface composition and structure of the substrate should be as close as possible to that of a crystal plane parallel to the surface. In order to achieve low defect epitaxial growth, substrate surfaces are treated inside the
264
Compound Semiconductors
epitaxial growth system. However, because of the extreme difficulty of removing hydrocarbon contamination, nascent semiconductor surfaces should not be exposed to air prior to placing them into the epitaxial growth chamber. Three methods are available to reduce the effects of air exposure on the substrate surface quality. 1. Sample Isolation. The surface treatment station and epitaxial growth chamber load-lock may be enclosed in an inert atmosphere.l33ll36l This procedure is difficult to carry out in practice since, even with partial pressures of oxygen or water vapor at 1 x lOa Pa, a monolayer equivalent of oxygencontaining species will contact the substrate surface in 1 sec. The sticking coefficient of these molecules will vary from site to site on the surface, however, the probability is high that the most adsorption-favored sites will be those energetically most favored for epitaxial growth. 2. Plasma Techniques. Electron Cyclotron Resonance (ECR) hydrogen plasma etching of GaAs in an ECR-MBE system has been attempted with limited success.l371 Based on SIMS results, the hydrocarbons were removed, but oxygen was always detected at the epitaxial layer-substrate interface. 3. Sacrificial Layers. The third and most widely used method is to create sacrificial layers on the semiconductor surface which can be readily thermally desorbed to yield stoichiometric surfaces free of unwanted impurities. These sacrificial layers are usually native oxides which, in the past, have been prepared by exposing the etched semiconductor surface to air. However, as explained earlier, this is an unsatisfactory procedure and a process using IN/ozone oxidation to form the native oxide has been more successfully applied, and is discussed in detail in Sec. 4.4. 3.2
Schottky and Ohmic Contacts
Deviations from expected electrical characteristics of metal contacts to air-contaminated III-V surfaces are usually ascribed to native oxide generated defects, and the role of hydrocarbons has not been studied to any significant extent. Therefore, the following discussion is exclusively directed to the presence of native oxides.
Surface Processing of III- V Semiconductors
265
Metal contacts with appropriate electrical characteristics are often created on air-contaminated surfaces. The relationship between the amount and composition of the air-formed contamination and the components of the contact are quite complex and often not understood. In work by Prunaux, i3*l the barrier heights of Au/GaAs contacts were measured as a function of air exposure time of the substrate prior to Au deposition. In addition, the GaAs native oxide thicknesses for different air exposure times were measured. Both sets of data are plotted in Fig. 5. I
1.1
-0;
1
Blil
0 /
- a- ~Thlckness
’
P ’ ’
3
I’ t F
0
-2-
I
/
/
4
/ ,
P'
0 I
I
1 elr exposure
Figure 5.
time
10 hrs
Barrier height and contamination layer thickness as a function of GaAs air
exposure prior to Au metallization.
(From ReJ: 38.)
A correlation between the apparent potential barrier height and the surface contamination layer thickness was established. It can be seen from the graph that the effect on barrier heights was small for contamination layers < 2 run thick, which formed in approximately 1 hr. Although, in these experiments, important factors such as the substrate surface structure and the relative air humidity were not measured, the results are adequate to suggest that, if air exposure of nascent GaAs surfaces is kept to a minimum prior to metallization, the effects on barrier height will be negligible. This applies to other III-V compounds where surface reactivity is not prohibitively high and air-formed contamination layers are < 2 mn thick. The potential drop across interface layers in this thickness range is negligible, since the layer is transparent to tunneling electrons from either side of the junction.
266
Compound
Semiconductors
Carefully grown oxides in the range of ~ 2 nm have been used to enhance barrier heights.[39] Submonolayers of certain impurities at the metal semiconductor interface may, however, have large effects on the electrical properties; e.g., both chlorine (CI) and sulfur (S) have beenshown to convert Schottky to ohmic contacts.[40][41] During the fabrication of ohmic contacts, it has been generally observed that thin interfacial native oxides break down and the oxygen is redistributed in the metal/semiconductor interface region.[42]This redistribution can take place at room temperature for highly reactive metals such as Ti, or during an annealing step with other less reactive metals, such as Ni. The actual redistribution mechanism is not known, but diffusionenhancedprocessesmust playa major role. However, if the contamination layer is too thick, interfacial reactions may be insufficient for redistribution. An example of this is shown in a transmission electron microscope (TEM) cross section, (Fig. 6) which clearly shows the contamination layer in a region of a Au/GaAs interface where mixing has not occurred.[43] The presence of the layer resulted in increased contact resistance and also reducedlocal doping of the interface. These are effects consistent with high interface doping levels that have beenpostulated to be a reasonfor the large decrease in metal/semiconductor contact resistance that occurs with annealing.
Figure
6.
interfacial 43.)
TEM
cross section of an alloyed Ni contact on GaAs showing
reactions where native oxide has survived
the annealing
process.
prevention
of
(From Ref
Surface Processing of III- V Semiconductors
267
The complete removal of oxide may not be necessary if the total area of contamination remaining at the interface is small relative to the total area of the contact. In general, however, since the composition and deposition rate of air-formed contamination is uncontrolled, the presence of this layer at ohmic or Schottky metal/semiconductor interfaces is to be avoided if reliable and uniform electrical characteristics are required.i41
3.3
Dielectric Overlayers
The most widely used dielectric deposition technique in III-V device processing is plasma enhanced chemical vapor deposition (PECVD) during which the semiconductor surface is exposed to a plasma discharge. Ions from the plasma reaching the substrate surface have energies in a range typically up to 50 eV, but higher energies are possible. The effect of ion flux on substrate surface composition and interacting precursors, during deposition of the first few monolayers, is complex and not well understood. At high ion fluxes, it is possible that the initial surface composition and structure is completely changed before significant nucleation has occurred; however, surface effects have been observed under certain deposition conditions. This is shown in the following example where SiN, is deposited by PECVD onto InP substrates. In these experiments, four substrates were exposed to a nonstandard, A, or standard, B, set of deposition conditions (see Table 2). Prior to deposition, each set of substrates was exposed to the following final surface treatments: (i) an oxygen plasma which produced an indium rich oxide; (ii) W/ozone exposure which produced a stoichiometric native oxide; (iii) buffered HF followed by DI rinse which, on air exposure, results in a thin native oxide and hydrocarbon covered surface; and (iv) exposure to W/ozone and removal of the native oxide with 10% I-IF solution, a treatment which results in a hydrogen-terminated surface. The substrates were all exposed to air for a short period prior to placing them in the PECVD system. All the substrates for each set of conditions in Table 2 were coated in the same deposition cycle. Silicon substrates were used to monitor the bulk properties of the SIN, films, since effects dependent on surface preparation had not been observed for this material over the range of deposition conditions used. Figure 7(a)-(d) shows scanning electron (SEM) micrographs of cross sections for SiN,deposited onto InP using the nonstandard condition (A) in Table 2. The cross sections (a) and (b) for SiN,, deposited onto the deliberately-formed native oxides, show that incomplete coverage and filamentary growth has occurred.
268
Compound Semiconductors
Table 2. Nonstandard A, and standard B, PECVD deposition conditions for SiNx on InP substrates. Refractive index, Si/N ratios, and BOE rates for A, B, and a standard CVDdeposited SiN, film are also shown.
A
B
SiI-Q seem
160
160
NH3 seem
5
5
N2 seem RF power W Pressure mtorr Ts “C
800
900
20
200
1500
650
300
300
Deposition time (min)
11
Deposition rate (n.m. set)
10
CVD standard SiN, on Si
4.6 27
Refractive index
2.07
1.92
1.95
Si/N arbitrary units
1.5
1.0
1.2
Buffered oxide etch rate/n.m. min
8.5
5.0
0.5
In the case where an air-contaminated surface was used, (Fig 7c), the SIN, film is continuous but has a grainy structure which results in a porous film and a non-specular surface. The layer grown on the hydrogenterminated surface is smooth (Fig. 7d) and no internal structure can be detected. When the above surface preparations and the B set of deposition conditions (Table 2) were used, all of the deposited films were smooth and featureless. It should be noted that there is a factor of ten difference in power density between the two sets of plasma conditions. This means that the ion flux at the surface of the substrates using condition (B) is much higher than for condition (A). This may explain the lack of surface sensitivity observed when higher power is used. This increased ion flux might also be expected to change the film composition, etch rate and refractive index as shown in Table 2. These results demonstrate that the formation of PECVD layers can, under certain conditions, depend on the initial nucleation process, which in turn depends on the state ofthe substrate surface.
Surface Processing of 111-V Semiconductors
Figure rich
7. SEM micrographs
oxide;
hydrocarbon
ofPECVD
(b) on stoichiometric
269
SiNx on lItP substrates: (a) on plasma formed In-
ozone-formed
oxide;
covered surface; (d) on hydrogen-terminated
(c) on thin surface.
native
oxide
and
270
Compound Semiconductors
From the brief discussion above, it may be concluded that surface compositions and structures formed on III-V compounds by many of the standard procedures which include air exposure, introduce a variability which may be unacceptable for the degree of process control required. It was shown earlier in the discussion on epitaxial growth (Sec.3.1) that an approach to overcome this problem is to remove, in-situ, the contamination layer from the surface immediately prior to further processing. Several techniques for achieving this have been explored. The most common techniques are plasma or ion beam sputtering and in-situ thermal desorption. These techniques and an improved process based on thermal desorption of deliberately formed oxides with hydrocarbon free interfaces are discussed below.
4.0
CONTAMINATION
4.1
Sputter Removal
REMOVAL
Sputtering can be used to remove contamination from surfaces but, for compound semiconductors, differences in elemental sputtering coefficients result in non stoichiometric surfaces.l45l Defects induced by ion bombardment may remain below the surface, even after thermal reconstruction.l46l In addition, impurity implantation and device damagel47l can occur. Ion beam sputtering should, therefore, be avoided where the above effects may be a problem. 4.2
Plasma Surface Treatments
The use of plasma techniques to remove surface contamination has raised some interest over the past few years, perhaps partly due to the development of systems where the plasma can be created upstream from the substrates, e.g., electron cyclotron resonance (ECR). However, an ion flux still reaches the substrate surface, even in ECR or upstream systems and hydrogen plasmas have been usedl48ll4gl t o reduce induced surface damage due to momentum transfer. For GaAs, partly disordered hydrogen-terminated surfaces and a general trend towards As depletion was observed.lsOl Hydrogen diffusion into the III-V substrate is rapid, and since hydrogen can passivate group III acceptorslsll and group IV donors and acceptors,15*l possible changes in electrical characteristics of the substrate must be
Surface Processing of III-V Semiconductors
271
considered before this technique is used. The electrical activity of dopants has been shown to recover when heated for short periods.ls31 Although hydrogen plasmas have been used to remove contamination from airexposed semiconductor surfaces, success has been limited. Complete removal of hydrocarbons has been reported for GaAs, but excess As and a persistent trace of oxygen was found on the surface.l37l 4.3
Thermal Desorption
Although native oxides can be desorbed from III-V semiconductor surfaces, complete desorption of hydrocarbons cannot be achieved. Usually hydrogen is lost and carbide bonds form with the substrate.l5ll54ll55l In fact, ring structures such as benzene have been found to undergo C-H bondbreaking on clean Si and Ge at room temperature,l56l and similar effects may occur on III-V semiconductors. These carbide fractions can then survive temperatures which are higher than decomposition temperatures of the III-V compounds. 4.4
UVlOzone Oxidation
Although many laboratories, including our own, had used ultraviolet light to “clean” surfaces, the relationships between UV wavelengths, ozone formation and surface reactions were not clarified until after 198515’1 In this work, it was shown that both wavelengths, 253.7 nm and 184.9 nm, emitted by a low-pressure mercury lamp, were needed to remove hydrocarbons. It was proposed that, whereas the shorter wavelength generated O,, the longer wavelength was necessary to supply energy to assist in the oxidation process. However, 0, decomposes by absorption of the 253.7 run radiation; therefore, the distance between the surfaces to be oxidized and the UV source is critical. UV/ozone units are now commercially available and are comprised of a low pressure Hg lamp UV source enclosed in a stainless steel chamber. Samples for oxidation are placed within 1 cm of the light source and l-10 nm thick oxide films formed. This is a Iow temperature process (60-90°C) which is easy to implement and hydrocarbon compounds are readily decomposed to volatile products, producing oxide/semiconductor interfaces free of C. Moreover, the oxides formed on GaAs 1581InP,1591and InGaAs141 (100) surfaces were shown to be close to stoichiometric and M-M bonds were not detected by XPS at the oxidesemiconductor interface.
272
Compound Semiconductors
A comparison of XPS data from differently treated GaAs surfaces is summarized in Fig. 4. The Ga3d and As3d spectral data for GaAs cleaved in vacuum at 2 x 1O6 Pa and for oxidized ( 100) surfaces prepared using (a) dilute HCI, (b) static DI water for 1 hr, (c) Br/CH,OH, and (d) ozone treatment (10 min) are shown. Different stages of oxidation are evident in these spectra. The ratios of total As to Ga are also included. Except for the ozone treatment, Ga and gallium oxides are more abundant than As and arsenic oxides. The worst case is the static DI rinse which gives an As/Ga ratio of 0.2. This is due to oxidation of the surface by oxygen dissolved in the water and selective dissolution of the more soluble arsenic oxides. Ozone oxidation and thermal desorption has been shown to generate surfaces which are less prone to oxidation than acid treated surfaces. A plausible explanation for this result is that microstructure is not generated by the ozone oxidation process. In fact, there is evidence that the procedure has a surface smoothing effect at the atomic leve1.t581 Although W/ozone-formed oxides have not been fully evaluated for the whole range of III-V compounds, native oxides on the more common substrates of GaAs and InP can be thermally desorbed in vacuum or gas ambients, to yield stoichiometric surfaces appropriate for epitaxial growth. Having established that W/ozone oxides could be used effectively as intermediaries in producing stoichiometric III-V surfaces, a reliable procedure had to be developed for successful application. Such procedures are necessary because oxidation during W/ozone exposure has very little effect on native oxides already present on the semiconductor surface. Since these oxides may be non-stoichiometric or contain OH groups, techniques had to be developed to introduce wafers into the W/ozone ambient with as little incidental oxidation of the surface as was practical. In order to carry this out, we developed a surface passivation technique to reduce contamination between process steps.
5.0
SURFACE
PASSIVATION
The search for appropriate chemical and electrical passivation of nascent semiconductor surfaces against contamination resulting from air exposure has been ongoing for many years with some success in a few specific areas. The techniques developed include the use of As as a sacrificial layer to protect epitaxially grown surfaces.t601t611t62~Elemental arsenic is readily deposited in MBE systems and can be thermally removed
Surface Processing of III- V Semiconductors
273
at temperatures above 300°C to yield As-rich, reconstructed surfaces. Different forms of sulfur have been used to stabilize the chemical and electrical properties of III-V surfaces ~~1However, in general, neither of these techniques can be as broadly applied to III-V semiconductors as the two passivation techniques discussed in detail below. Since the most common volatile oxides at room temperature include those of C and H, i.e., CO* and HzO, surface passivation using either or both these elements would be a favorable treatment prior to forming a more permanent passivation using UV/oxidation. Three methods are available to achieve the appropriate passivation conditions: (i) surface coverage using hydrocarbons, (ii) H saturation of the surface dangling bonds or (iii) a combination of both effects. In Sec. 2.0, we showed that a degree of passivation could be obtained for (110) III-V surfaces by cleaving the semiconductor in liquid hydrocarbons. Although passivation to air oxidation was obtained using liquids with a range of molecular weights, only the lower molecular weight alcohols were available with the low impurity level required for device processing. Electronic grade CH,OH was used for the experiments reported here. Although there was a potential for contamination of nascent surfaces due to the presence, at the ppm level, of heavy metals as impurities in the CH,OH, this does not occur with H-passivated surfaces. The possibility of preparing appropriate surfaces with passivating overlayers is considerably enhanced by two fortuitous reactions which occur when hydrofluoric acid is used to remove native oxides from semiconductor surfaces. The first is the very large selectivity for removing the oxide without over-etching the semiconductor, and the second is the passivation of the exposed dangling bonds on the semiconductor surface with atomic hydrogen. [641[a51[a61 The attachment of hydrogen to dangling bonds, created in I-IF solutions, clearly competes effectively with any heavy metal atoms as well as fluorine, since the electronic properties of these surfaces have shown them to be remarkably inactive.1651 In the case of Si, this inactivity was shown, by multiple internal reflection IR spectroscopy, to be due to a surface coverage of covalent Si-H bonds, leaving virtually no surface dangling bonds to act as recombination centers. The passivation of surface defects by hydrogen is perhaps not surprising since the use of hydrogen plasmas to passivate defects in a wide range of semiconductors has been successfully demonstrated.[671-[6gl What is surprising is the relative stability of the hydrogenated semiconductor surface to oxidation in air or water. This stability is more pronounced for elemental[701than for III-V semiconductors.
274
Compound Semiconductors
In order to measure the relative stability of III-V surfaces which have undergone different surface treatments, the photoluminescencel71l (PL) technique can often be used. The photoluminescence intensityl72ll73l depends on surface, bulk, and interface recombination rates for the photoninduced carriers, and this technique can provide information on the change in surface defect state density as a function of time. For example, the average PL intensity of an n-type InP wafer, which had oxide removed in I-IF/CH,OH, decreased by 10% over a period of 90 min in air, whereas an air-cleaved (110) surface decreased by 40% in the same time. This result indicates the passivating effect obtained from exposure of the InP surface to the hydrofluoric acid solution. Table 3 shows Auger results from a series of experiments designed to evaluate the chemical passivation by different surface treatments of InP and GaAs (100) polished and etched and (110) cleaved surfaces exposed to air. We have used the O/In or O/As Auger line intensity ratios to give a relative measure of surface oxidation. Most devices on fee semiconductors are, of necessity, fabricated on the (100) surface in order to leave the (110) cleavage planes for device separation or laser facets. Since the (100) planes are not cleavage planes, we are unable to obtain cleaved standard surfaces for air exposure experiments to compare with the (100) surface treatments in Table 3. However, an MOCVD-grown (100) InP surface exposed to air for 24 hrs gives an O/In ratio which is the same as the saturated oxide on an InP (110) surface and, to a first approximation, the oxidation for (100) and (110) surfaces may be considered similar after a lo-min air-exposure. Table 3 shows that the (110) surfaces of both InP and GaAs oxidize significantly less when exposed to air, after being cleaved in either concentrated HF or organic solvents rather than in air. Both GaAs and InP show a degree of passivation which degrades with time, oxide saturation occurring over a period of 24 hours. The data also show that surface passivation occurs when I-IF is used to remove native oxides from (100) surfaces, as well as from the cleaved (110) surfaces. The most effective passivation is obtained using concentrated HF/xylene or concentrated HF followed by a nitrogen gas jet dry. However, these procedures are not practical as process techniques. Although the results in Table 3 indicate that the I-IF/CH,OH treatment was unsuitable since it gave the same O/In ratio as that for the I-IF/D1 rinse, Auger spectroscopy showed that the surfaces contained residual organic molecules and XPS showed that neither In nor P oxides were present. These results indicate that physisorbed CH,OH may be initially present on the H-terminated surface. If this is the case, we might expect that organic molecules, physisorbed onto hydrogen-terminated
Surface Processing of III- V Semiconductors
275
surfaces, would exhibit thermal desorption properties different from surfaces without the H termination. Preliminary evaluation of this effect has been reported using silicon substrates,l74l and it is plausible that similar results may be obtained for III-V surfaces. In these experiments, hydrocarbons were thermally desorbed from hydrogen-terminated surfaces below 200°C. It was postulated that the hydrocarbons were weakly physisorbed on the hydrogen-terminated silicon surface. In effect, a double passivation layer occurred and this could explain the improved passivation observed in our experiments when HF/xylene treatments were used rather, than pure I-IF (see Table 3).
Table 3. Auger Peak Intensity Ratios for O/In and O/As as a Function of Air Exposure Times of Differently Treated (100) and (110) InP and GaAs Substrates Surface
Treatment
Air Exposure O/In- 1Omin O/In-24hr (110) InP
Cleaved Cleaved Cleaved Cleaved Cleaved Cleaved Cleaved Cleaved
2x IO-*Pa air cont. HF xylene cont. HF/Di cont. I-IF/CH,OH CH,OH W/O, cont. I-IF
0 0.4 0.2 0.17 0.3 0.3 0.3 0.17
0.4 0.4 0.3 0.4 0.3 0.4 0.3
(100) InP (a) IJVQ w/o, w/o, (a) Repeated
cont. I-IF cont. I-IF/IN cont. HF xylene twice
0.1 0.2 0.08 0.2 MOCV-Grown
Air exposed (a) Repeated twice
0.2
0.3 0.3 0.2 0.3 (100) InP 0.4 0.3
276
Compound Semiconductors
Somewhat fortuitously, the above mechanisms lend themselves to a simple sequence of process steps which incorporates some degree of passivation, as described below.
6.0
APPLICATIONS
Since air-exposed III-V surfaces are comprised of patches of hydrocarbons and air-formed oxide, neither W/ozone oxidation nor HF/CH,OH alone will generate a compositionally uniform surface. W/ozone will create surfaces covered by patches of both air-formed and ozone-formed oxides, and since the hydrocarbon contamination may not be removed by the HF/CH,OH, a continuous passivated hydrogen-terminated surface is not assured. We can avoid this problem by using the following sequence of processing steps: W/ozone-HF/CH,OH-W/ozone. A schematic crosssectional diagram of the expected surface structure, during the above treatment, is shown in Fig. 8. In Fig. 8a, the air-exposed surface is depicted to contain patches of hydrocarbons and air-formed oxide. After W/ozone oxidation, the hydrocarbons have been removed and the surface is comprised of regions of air-formed and ozone-formed oxides (Fig. Xb). After HF/CH,OH is used to remove the oxides, a hydrocarbon layer physisorbed on a hydrogen-terminated surface is obtained Fig. 8c. The final step is a W/ozone oxidation, which yields a uniform stoichiometric oxide (Fig. Sd). The oxide thickness is generally about 2 nm, although thicknesses closer to that of air-formed native oxides can be produced by controlling the exposure time. This result is important since most metallization and other semiconductor processing steps are engineered to be compatible with surfaces containing native, air-formed oxides which may have thicknesses less than 1 run. In the case where native oxides are to be kept to a minimum, the stoichiometric oxide may be removed with dilute HF solution followed by a DI rinse. This treatment results in temporary passivation due to hydrogen termination of the surface. In order to verify the effectiveness of the above process in removing hydrocarbons from interfaces, the following experiment was conducted. MOCVD InP layers were grown on (100) surfaces from which either W/ ozone, or acid/IX/air-formed, sacrificial oxides were thermally removed insitu. The interface region was then analyzed, using secondary ion mass spectroscopy (SIMS) to obtain depth profiles by monitoring PSi(59) and
Surface Processing of III- V Semiconductors
277
PCO(59) with mass resolution (M/AM) = 3000 sufficient to resolve the two peaks. A trace of Si contamination was always present at the interface and served as a marker for the interface location. Representative results are shown in Fig. 9. An increase at the interface in the PCO- peak, indicating an increase in carbon, was observed for acid/D1 air-formed sacrificial oxides (curve a) but no increase was observed (curve b) where W/ozone sacrificial oxides were used. a UV
OlONL
D
HYDROCARBONS AIR
FORflED
OZONE U
OXIDE
FORflED
AOSOREEO
OXIDE
HYDROGEN
Figure 8. A cross section schematic showing changes occurring to: (a) an air-exposed surface, for the following sequence of treatments; (b) UV/ozone; (c) HF/CH,OH; (d) UV/ ozone.
Small amounts of carbon contaminants at interfaces have been shown to affect electrical properties t751and epitaxial growth. In the latter case, defects have been observed to propagate into the epitaxial overlayer.t761 In Figs. 10(a) and (b), show scanning electron microscopy (SEM) crosssection micrographs of two samples of liquid phase epitaxial growth of GaInAsP on InP substrates. Prior to epitaxial growth, a periodic grating of 3850 A pitch had been etched into the surface and the sample surfaces, subsequently covered with sacrificial oxides using either acid/DI/air exposure (Fig. 10a) or W/ozone (Fig. lob). Typically, for the acid/D1 air
2 78
Compound Semiconductors
----
0
250
500
750
1000
Sputtering Time (set)
Figure 9. SIMS depth profiles (Cs’ ion beam) of MOCVD epitaxially grown InP layers on surfaces from which a native oxide had been thermally desorbed in-situ. The oxides were prepared as follows: (a) acid treated/D1 water rinse, air exposure; @) W/ ozone, air exposure. Si was used as an interface marker. The profiles (n) have been raised by lo3 counts so that we can include the four profiles on the same figure.
exposure treatment, incomplete growth occurred over the grating, whereas, excellent quality epitaxial layers were obtained for the W/ozone treatments. It should be pointed out that the original acid/D1 air exposure process had been developed using flat substrates and had been quite successful. Surface analysis subsequently showed, however, that the gratings became contaminated more rapidly on exposure to air than did the planar surfaces. Contamination by carbon or hydrocarbons of the nucleation sites, required for successful epitaxial overgrowth and the commensurate difficulty of thermal desorption, was considered a plausible explanation for the observed results.
Surface Processing of III-V Semiconductors 279
Figure
10.
LPE-grown
epitaxial
GaInAsP
native oxides had been in-situ thermally
(EI~)
desorbed.
on InP substrates (S1Sz} from
which
The oxides were prepared by (a) acid/
Dl water rinse, air exposed and (b) UV ozone exposure.
A further example of the role which surface structure, and hence chemical reactivity, plays in determining surface preparation procedures has been reported.[77] Fig. 11 shows PL intensity maps from an 1nP/ InGaAs/InP epitaxial layer structure grown on three (100) InP substrates. The defect densities of the single crystal boule from which wafers (a) and (c) were cut was -106 cm-2,whereaswafer (b) had a defect density of -103 cm-2. The substrates used for Figs. 11(a) and (b) had the same surface preparation procedure ofBrCH3OH, followed by a CH3OH rinse and UV/ ozone. Excess CH3OH was removed from the substrate surfaces by a nitrogenjet. The shapeand position of the "sunburst" pattern in Fig. 11(a), correlated with the angle and position of the nitrogen jet on the wafer surface. The sensitivity to the nitrogen jet removal conditions was not observed for the substrates with the lower dislocation density. Clearly, a relationship existed between the final stages of surface preparation, the density of the non-radiative recombination centres created at the surface, and the density of surface-terminated bulk defects.
280
Compound
Semiconductors
Figure
11. Photoluminescence
wafers:
(a) on "poor"
quality
substrate with
quality
intensity maps of InGaAs epitaxial structure grown on loP substrate; (b) on "good"
new surface preparation
quality
substrate; (c) on "poor"
procedure.
Fig. 11(c) shows a PL intensity scan from epitaxial layers grown on a wafer which came from an adjacent position in the samehigh defect density single crystal, as that shown in Fig. 11(a). A uniform high intensity PL distribution is observed. In this case, however, the bromine methanol step had been replaced by an acid treatment, resulting in a surface preparation procedure which was less sensitive to the substrate defect density .
7.0
SUMMARY AND CONCLUSIONS
We have stressedthat nascent III-V surfaces become contaminated on exposure to air, no matter how brief the exposure time. This exposure results in a surface of complex composition containing hydrocarbons, native oxides, OH groups, metal bonds and a loss of stoichiometry .10corporation of the contaminated layer into interfacial regions during device processing can degrade the intended interfacial properties. The need for
Surface Processing of III- V Semiconductors
281
passivation of surfaces during air exposure has been stressed and a surface processing procedure discussed which incorporates two levels of passivation. The first of these is a I-IV/ozone-formed thin, uniform, stoichiometric native oxide. The oxide affords protection of the semiconductor surface and, by careful control of thickness, can be compatible with many semiconductor processing steps, in particular, as a sacrificial layer prior to epitaxial growth. The second passivation layer can be obtained by using hydrofluoric acid to remove the stoichiometric ozone-formed native oxide. This treatment results in a hydrogen passivation layer which affords a short term, typically, < 10 min, passivation which can be used for processes
where native oxides seriously degrade the required interfacial properties. The concept of a standardization of the semiconductor surface prior to interface formation has been introduced. These standardized surfaces may be created prior to most processing steps to replace variable surface structures and compositions created by environments such as air, water, solvents, plasmas and different ambient exposure times.
ACKNOWLEDGMENTS I wish to acknowledge my co-workers at BNR for useful discussions and reviews of the manuscript. In addition, I am indebted to those authors who gave their consent to reproduce data and figures.
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6 Ion Implantation Induced Extended Defects in GaAs Kevin S. Jones
Ion implantation is the accepted method of introducing dopants in GaAs-based microelectronic devices. It is used to form gate, source, and drain regions in high speed field effect transistors (MESFETs). It has found increasing application due to the lack of n-type diffusion technology for GaAs. Implantation is also used for electrical isolation ofmicroelectronic devices by creating semi-insulating regions, and in free carrier and photon confinement in semiconductor laser structures via quantum well disordering. There have been many books and chapters written on ion implantation in generaIt’]-I51 and its applications in GaAs.161171During ion implantation of semiconductors, different amounts of radiation damage can be induced in the substrate. This damage varies from isolated point defects to complete amorphization of the semiconductor. The amount of damage depends on a variety of implant-related factors including the target, implant temperature, ion dose, ion mass, ion energy, dose rate etc. Recently, there have been many excellent articles on how these factors affect the as-implanted morphology and one is encouraged to read these articles for additional After implantation, a high temperature information on this subject. 181-1131 annealing step is necessary to remove the lattice damage and electrically activate the dopant atoms. During this annealing, a variety of extended defects (dislocations, dislocation networks, stacking faults, microtwins, etc.) may form. 285
286
Compound Semiconductors
Previous review articles have addressed how, during Si processing, the as-implanted morphology affects the final defect structure. This led to a defect classification scheme which divides the extended defects that form It has recently been shown that the during annealing into five types. 11411151 defect classification scheme developed for implant-related defects in silicon can be applied to the implantation of GaAs.l161 Briefly, Type I defects are typically extrinsic dislocation loops or voids that form upon coalescence of point defects which were created for doses below the amorphization threshold. Type II defects (or end of range damage) form after amorphization in the Type III crystalline region below the amorphous/crystalline interface. defects form when the solid phase epitaxial regrowth process of the amorphous layer is less than perfect. Type IV defects form upon annealing a buried amorphous layer. These defects form at the position where the two advancing amorphous/crystalline interfaces meet. Finally, Type V defects arise when the solid solubility of the implanted impurity is exceeded. These defects can be precipitates or extended defects that form because of the precipitation process. Figure 1 shows a general ion implantation interaction matrix, as well as one for specifically implant damage. As stated above, a variety of factors can influence the implant damage morphology and the implant damage in GaAs can have a number of effects, ranging from changing dopant and point defect diffusivities to affecting the electrical activation. Understanding the formation and annealing kinetics of extended defects and their effect on the final devices is essential for optimal device manufacture. This chapter focuses on the defects that form upon annealing implanted GaAs and how these defects influence factors such as dopant redistribution and activation.
1.0
TYPE
I DEFECTS
Type I (sub-amorphization) defects are most commonly observed upon annealing lighter ion implants. In GaAs, these defects prove to be important for several reasons. First, if GaAs is amorphized during the implant, then the electrical activation upon annealing of implanted dopants is substantially reduced.l6l117l For this reason, amorphization is avoided during GaAs processing. This is in direct contrast to silicon processing, where amorphization is used to reduce the channeling of incoming ions, thereby producing more abrupt doping profiles. To avoid amorphization of GaAs during implantation, lighter dopant ions, i.e. Be+, Mg+, Si+, are
Ion Implantation
Induced Extended Defects in GaAs
287
Electrical Actiiation
Implant Damage Formation Matrix
Figure 1.
General ion implantation interaction matrix.
typically used. The doses are kept lower than those used in silicon, and elevated temperature implants are also used. Finally, it has been observed that Type I defects are among the most stable of all types of defects in implanted GaAs.[lsl All ofthese factors combine to make Type I defects the most common class of defects in implanted GaAs. From a practical stand point, there is an interest in what effect, if any, the formation and dissolution of Type I defects has on dopant activation and dopant diffision, as well as final device parameters. At the present time, efforts are being made to produce software (SUPREM 4.5) which will model the dopant profiles This process modeling software is after implantation and annealing. essential in the development of new microelectronic devices. In order to produce accurate and physically based process simulators, the effect of Type I defects over a wide range of ions, energies, and doses must be understood. This chapter divides the discussion of Type I defects into the areas of (i) defect form a t’Ion, (ii) defect density and distribution, (iii) defect stability and (iv) the effect of defects on dopant activation and redistribution. The general discussion in each of these sections focuses on Si+ implantation first and then considers other species.
288
Compound
Semiconductors
Underfocus
In
Focus
Overtocus
Figure
2.
Examples
of void defects in GaAs.
The sample received
implant at a dose of 3 x 1014/cm2 annealed 850°C for 1 hr.
a 220 keY Si+
Ion Implantation 1.1
Induced Extended Defects in GaAs
289
Type I Defect Formation
The first questions regarding any type of defect are, What is the defect morphology? and, What are the conditions necessary for their formation? The two most common morphologies of Type I defects are voids and dislocation loops. Figure 2 shows an example of void defects. This series of cross-sectional TEM micrographs was taken in three different focusing conditions. Voids are very difficult to resolve for the “in-focus” condition. This may be one reason why their importance was not recognized until recently. In addition to voids, dislocation loops are another form of Type I defect. Figure 3 shows an example of Type I dislocation loop formation in Si+ implanted GaAs. The as-implanted cross-section shows that the sample was not amorphized during the implant After 900°C annealing for five minutes, the loops can be seen to form approximately around the projected range of the Si+ implant. The distribution of Type I defects is discussed further in the next section. More detailed studies of Type I loops have shown they are extrinsic and typically lie on { 1 lo} or { 11 l} planes. They have Burgers vectors of either a/2(1 10) or a/3 (11 l).[lg] 1.2
Type I Defect Formation Thresholds
The conditions necessary to form Type I defects (either voids or dislocation loops) depend on the implant species. The first species to be discussed is Si. Si is the preferred n-type dopant in ion implanted GaAs. This is a result of its good activation (up to 3-5 x lO%m*) and its low diffusivity. Because of the low doses typically employed (11014/cm2), Type I defects are often the only defect type that can form. Chen has shown that afier implantation, voids can form in a non-amorphized region of G~As.[*~I The threshold conditions for forming voids via room temperature Si+ implantation are energies 2 220 keV and doses 2 3 x 1014/cm2.~211[221 Decreasing the dose to 1 x 1014/cm2 resulted in no void formation. In addition, no void formation has been reported for energies less than 220 keV. These results imply there is a strong energy dependence for vacancy formation. Figure 4 is a summary of the conditions for which void formation has been observed for Si+ or Al+ implants. It is apparent that higher energies favor void formation. This is consistent with BTE simulations that suggest that as the energy increases, the separation of the net vacancies and interstitials becomes larger. Additional modeling must be done before the critical concentration of vacancies necessary for stable void formation is known.
290
Compound
Semiconductors
~
...e ~ . 0 -
:::;. ~
"'.
o o -
o
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Ion Implantation
Induced Extended Defects in GaAs
291
The defect formation threshold appears to be considerably lower for Type I dislocation loops than for voids. There have been reports that upon annealing at temperatures > 800°C, Type I dislocation loops form a&r Si+ implantation at doses as low as 3 x 1013/cm2 for implant energies of 240 keV1231and 60 keV.1241 Figure 5 shows a summary of the threshold dose for Type I dislocation loop formation as a function of implant energy and dose for a number of species. l”112411251-1271 Plotted this way, the results show that, in general, the threshold dose for dislocation loop formation is between 1 and 5 x 1013/cm2. This is as much as an order of magnitude lower than the results of Type I defect formation threshold in ion implanted silicon.l151 The difference may be due to the smaller values for the elastic constants in GaAs, which make dislocation formation easier in GaAs than Si. For a given mass, the trend appears to be that as the energy increases, the threshold dose for defect formation decreases, 10’6
t Y 0) : 0
,....,..,........,.,,.......~.............................~......~~~~~.*,:~~..... S"+ 1
10'5
I
0
I
100 Implant
10
ChencLal.~1990
200 Energy
Figure 4. Summary of the threshold conditions 9OO”C, Si+ implants, unless otherwise noted.
300
400
500
(keV) for void formation.
Annealed
at 800-
To further investigate this, a series of experiments was done in which Ge, As, and Se were implanted at energies between 40 keV and 160 keV and doses between 1 x 1013/cm2 and 1 x 1014/cm2. The implants were done at 25°C f 2°C. REKSresults after implantation indicate that the dose of 1 x
292
Compound Semiconductors
6e+13
I
I --t-
No Defects
5e+l3 -
4e+13 -
3e+13 -
2e+13 -
le+13 -
Implant Energy (keV)
Figure 5.
Type I defect formation in implanted GaAs.
1014/cm2 is sufficient to amorphize all three species at all three energies. These samples are discussed in Sect. 2.0 on Type II defects. After implantation, the samples were capped with a Si3N4 layer and annealed at 800°C or 900°C for five minutes. Figure 6 shows the plan-view TEM results from the Ge implants. It is clear that the threshold dose for Type I defect formation shows a strong energy dependence. As the energy decreases, the threshold dose increases dramatically. For example, a decrease in implant energy of only 3 1% (160 keV to 110 keV) results in an increase in the threshold dose of - 500%. In order to understand this strong energy dependence of Type I defect formation, it is helpful to examine the source of the excess interstitials for these dislocation loops. This strong energy dependence may be related to the increased separation of the net interstitial and vacancy distributions with increasing energy. Figure 7 shows Boltzmann transport equation (BTE) calculations of how the net vacancy and interstitial concentration are
Ion Implantation Induced Extended Defects in GaAs 293 predicted to vary as a function of increasing implant energy .As the energy increases, the vacancy and interstitial profiles become more separated and less recombination of point defects occurs, thus requiring a higher dose for dislocation loop formation. This model assumes that an increase in separation of as little as a few hundred angstroms in the net profiles is sufficient to result in a dramatic change in the recombination process.
I x 1013cm-2
Figure
6.
annealing
Plan-view at 900°C
TEM
micrographs
for five minutes.
s
x
1013
cm-2
of Type I defects in Ge+ implanted
GaAs, after
294
Compound
Semiconductors
!::ros$:§~c!io!!illIEM
Plan.,~!ewIEM
2Qkey
40keV
.
80keV
c. " , !J
. r
.
200keV
Figure 7. The effect of implant energy on Type I dislocation loops. Plan-view and cross-section TEM micrographs of 29Si+,1 x 1014/cm2.annealed at 800°C for 1 hr.
Ion Implantation
Induced l&tended Defects in GaAs
295
It has also been proposed in silicon, that the excess atom density introduced by the implanted ions is the source of the excess interstitials in Type I dislocation loops. 1141 Using this model, if the ion dose is kept constant, the threshold dose would be the same at different energies unless there was either a change in the competing sinks for excess interstitials or a change in the vacancy concentration. With decreasing energy, the surface may become an increasingly important sink for interstitials, which would increase the threshold dose for Type I dislocation loop formation. In addition, as discussed in the previous section on Si implantation, a decrease in implant energy appears to result in a significant increase in the vacancy concentration.l28l This has been ascribed to recoiling atoms knocking atoms out of the crystal, and may also be the reason for the strong energy dependence with these heavier ions. Additional modeling efforts are necessary to determine if the difference in mass can account for the difference in threshold energy between implants (i.e., around 40 keV for Si+ implants and 160 keV for Ge+). As and Se were also implanted under the same conditions as the Ge implants, reported above, to determine if there is a dependence on species of the dislocation loop formation thresholds. The isotopes (75As+, 76Se+) chosen have nearly the same atomic weight as the 76Ge+. To distinguish between the effect of species on the formation kinetics and the effect of species on the dissolution kinetics, annealings were done at both 800°C and 900°C. In previous studies, Type I dislocation loops appear stable at 800°C for moderate times (I 1 hr) but may dissolve during furnace annealing at 900°C. It was, therefore, necessary to do the study at both temperatures.l16l The plan-view TEM results of all three species (Ge, As, Se) after annealing at 800°C for five minutes are summarized in the table in Fig. 8. The threshold dose shows a definite species dependence prior to amorphization (5 x 1013/cm2) at the highest dose studied. Of the three species, the threshold conditions for dislocation loop formation appear to be lowest (easiest) for Ge+ implants. This apparent species dependence may be the result of the site selection of the impurity. If the dislocation loops are composed of both Ga and As interstitials, amphoteric dopant species, such as Ge which occupy both substitutional sites, may generate higher concentrations of both types of interstitials. This should facilitate the formation of dislocation loops. Species such as As, which show a strong preference for one site, may produce fewer Ga interstitials, thus making dislocation loop formation more difficult.
296
Compound Semiconductors
.-r----l cr,
0
ls-
Interslltlals
'E 2 z
EiwssGa
Cxcoeo Aa
10"
lO'$
10" 0
500
1000
1500
Depth
2000
2500
3000
(A)
Ge IlOkeV (le13) 10”
1
1 0
10" ‘-77
‘E 2 =
ExcesGa
lolS
Interotltlals 10"
,
I
0
500
I
I ,000
1600
Depth
2000
2600
I PO00
(A)
Ge 160keV (1813)
lo",
1013 0
500
1000
1553
Depth
?OOG
7530
2000
(A)
Figure 8. Boltzmann transport equation calculations of the net vacancy and interstitial distributions after 1 x 1013/cmZ Ge+ implants into G&s.
Ion Implantation
Induced &tended
Defects in GaAs
297
The doping is another factor that may be important in the determining the stability of Type I dislocation loops. Robinson et a1.[2globserved that when an Al+ implant was used to form Type I loops, if the sample was coimplanted with a low dose of Mg+, the loops were more numerous and more stable. This implies that there may also be some Fermi level dependence on the loop formation and dissolution process. More studies are obviously needed to determine the effect of Fermi level and site selection on the defect formation thresholds. 1.3
Type I Defect Density and Distribution
For Si+ implants, it has been noted that as the implant dose increases from 3 x 1013/cm2 to 1 x 1014/cm2, the density of atoms trapped in the Type I dislocation loops after 85O”C, 20 min, annealing increased from 1 x 1012/ cm2 to 3.9 x 1013/cm2, which is much faster than the increase in dose.[231 This implies there is a super linear increase in trapped atom concentration with doses at just above the defect formation threshold. Nonlinear damage accumulation in Si+ implanted GaAs prior to annealing was recently reported.[*l It was speculated that possibly a new type of defect complex forms with increasing dose. This complex traps simpler migrating defects, thus reducing their normal rate of recombination. This could also result in an increased concentration of point defects available for Type I dislocation loop formation upon annealing. The proposed trapping complex may, in fact, be the dislocation loops in their early stage of development. Listabarger et al. has shown that, in silicon, loops even in the early stages of growth are excellent trapping centers for Type I damage.r301 Finally, the loop distribution has been reported to be centered roughly around the projected range of the implanted Si+.[231 This would be consistent with the excess interstitials for the loops arising from the implanted dopant occupying substitutional sites, thus resulting in As and Ga interstitials (depending on the site occupied). However, Bellon et al. observed loops for 190 keV Si+ implants at depths of 2200 A for implants with a projected range of 1600 A.[lgl This shift is ascribed to a diffusion of the implanted ions and the Ga and As interstitials deeper into the crystal prior to loop formation. Also, the lack of dislocation loops within 1100 Bi ofthe surface is ascribed to rapid interstitial elimination at the su&ce. Our results are generally more consistent with the observations of Stewart for Si+ implants. Figure 9 is a plot of the depth of the loops produced by 1 x 1014/cm2 implants of Si at room temperature after annealing at 800°C for one hour (see Fig. 10). The depth of the loops track
298
Compound Semiconductors
well with the increase in projected range as a function of implant energy. In addition, the distribution was fairly uniform with depth.
7sGe+
-AS+
1 X 10*3/cm2 2 x 1013/cm* 5 x 1013/cmz
76Se+ no loops 40 keV
110 keV
160 keV
no loops
loops
no loops
no loops
no loops
no loops
no loops
no loops
no loops
no loops
loops
no loops
no loops
few loops
no loops
no loops
few loops
loops
loops
loops
loops
loops
loops
loops
loops
looljs
loops: 2 1 x 109/cm2 few loops: 2 1 x 108/cm2 no loops: 5 I x lO%m*
Figure 9. Table summarizing the plan-view and cross-sectional temperature implants after SOO”C, 5 min annealing.
TEM results for room
Figure 10 shows that the concentration of Type I defects does not show a strong dependence on implant energy above 40 keV for 1 x 1014/cm2 Si+ room temperature implants. However, below 40 kevthere is a significant decrease in loop concentration which correlates well with an increase in Si diffusivity.1181 The depth of the Type I loops from species other than Si has also been studied. For other species, it appears the loop position does not always follow the projected range. Figure 11 shows a cross-sectional TEM micrograph of the 160 keV, 5 x 1013/cm2 Ge, As, and Se samples after 800°C annealing for five minutes. High resolution TEM micrographs confirm the loops are extrinsic. The projected range for these implants is around 725 A. For all three species, most of the dislocation loops are centered about 675 A below the surface. Thus, it is possible to form stable loops at depths less than 1100 A. The loops are stable for annealing times
Ion Implantation
lo4
Induced kktended
299
“‘l”‘l”‘l”‘l”‘-
I”‘l”’
- -t- -+_ -++-
Defects in GaAs
Shallowest Loops Deepest Loops Projected Range
lo2’““““““““‘“‘“““““~~‘~“~’ 20 40 60
80
Implant
100
Energy
120
140
160
180
(keV)
Figure 10. The depth dependence of Type I loops implant energy. From cross-sectional TEM measurements of 1 x 10’4/cm2 Si’ implants at room temperature annealed at 800°C for 1 hour.
greater than five minutes at 900°C. The reason most of the loops are at the projected range rather than deeper may be species-related. The deepest loops for the Ge and Se implants were only 800 A and 1300 A, respectively, (less than 2 Rp). However, the As implants showed loops as deep as 5400 Hi. The reason for the difference in depth may be related to the difference in defect formation thresholds. The Ge showed the shallowest loops and the lowest defect formation thresholds. If the Ge is producing both Ga and As interstitials due to its amphoteric nature, as was speculated, then it is possible that the defects must move shorter distances prior to finding a complimentary point defect and nucleating a dislocation loop. Thus, the loops would be shallower. This is supported by the observations in Fig. 9 which indicated loop formation for the amphoteric dopant Si which is also relatively shallow (near the projected range). Jones et al. reported that in 150 keV Mg+ implants at 1 x 1014/cm2, the Type I loops that form upon 9OO*C, 15 min, annealing were centered at depths less than 1000 A despite the fact that the projected range of the ion was around 2000 A.L311 This again indicates the depth of the Type I loops does not necessarily correspond with the projected range and may be either shallower or deeper, depending on the species and implant conditions.
300
Compound
~
Semiconductors
... O.lf1m
Ge
As
SI:
Figure II. Cross-sectional TEM micrograph of 160 keY Ge, As, and Se, 5 x 1013/cm2, after annealing at 800°C for 5 min.
Ion Implantation
Induced Extended Defects in GaAs
301
In addition to the formation threshold and the depth of the Type I loops, it is also interesting to study the concentration of interstitials bound by these extrinsic loops. Bellon et al.l1gl found the density ofthe interstitials bound by the Type I loops for (2.5 x 1014/cm2) matches well within the dose (4 x 1014/cm2). This is consistent with results of Type I loops in implanted silicon.1141 The correlation between the density of loops and the dose is usually attributed to the increase in interstitial concentration in the crystal associated with implanted dose. 115111glThis model assumes that all of the net interstitials left over, after Frenkel pair recombination, are trapped by the forming Type I loops. From the previous discussion of Se, As, and Ge, there is not a direct dependence of the loop concentration on the dose, which indicates the model is oversimplified. In addition, from Fig. 6, the concentration of atoms bound by the loops for the 160 keV, 1 x 1013/cm2 Ge+ sample is between 3 and 5 x 1013/cm2. Since the trapped atom concentration is greater than the dose, there must be other sources of interstitials. There are a variety of possible mechanisms by which the interstitials can be introduced during implantation other than simply from the implanted dose. These include incomplete Frenkel pair recombination and knock-on of atoms from overlayers. Any modeling of the dependence of Type I loop density on implant conditions must account for these other sources. 1.4
Type I Defect Stability
Voids have been shown to be quite stable. They show little sign of dissolving after RTA treatment at 900°C for ten seconds132l or furnace annealing at 850°C for one hour. 12il The electrical measurements of Ko et al. indicate the voids may be coarsening during these higher temperature anneals, but, no significant void loss is reported.l32l The normal evolution of dislocation loops upon annealing would involve growth, coarsening, and dissolution phases. Stewart et al. reported that for 240 keV Si+ implants into GaAs at doses between 1 x 1013/cm2 and 1 x 1014/cm2, the concentration of atoms bound by the Type I dislocation loops decreased by an order of magnitude or more between 750°C twenty minute annealing and 850°C twenty minute annealing. This implies that the loop annealing kinetics are in the dissolution regime at temperatures above 750°C. However, it has also been reported that loops from Si+ implants are stable after ten hours at 900°C.1161 It was shown that there is a difference in defect stability for 28Si+ versus 27Al+implants. It appears Type I defects
302
Compound Semiconductors
from Si+ implants are much more stable than Type I defects from Al+ implants. Both samples were implanted under the same conditions and capped with a PECVD S&N, cap prior to annealing. The dislocation loops from the Al+ implants dissolved after only 30 min at 9OO”C, whereas the Si+ induced Type I dislocation loops were stable after 10 hrs at 900°C. Al showed no measurable redistribution by SIMS during the defect dissolution anneal. This implies that the Al diffusion process is probably controlled by vacancies. The dissolution of Type II loops has been shown in implanted silicon to depend strongly on the species.l33l For GaAs, the stability of Type I defects also appears to depend on the species, although this dependence is not well understood. Robinson et al. has also shown that Type I dislocation loops from 130 keV Al+, 1 x 1014/cm2 implants dissolve for annealing times between 15 and 30 min at 900°C.12gl However, in the presence of a low dose Mg implant (1 x 1013/cm2), the same Type I defects from the same Al implant required annealing times between 2 and 6 hrs before they dissolved. It was proposed that the p-type doping stabilizes the loops by increasing the equilibrium concentration of positively charged Ga interstitials. Annealing studies of Type I dislocation loops from Mg implants appear to support this hypothesis. Robinson et al. showed that at 9OO”C, Type I dislocation loops produced by a 150 keV Mg+, 1 x 1014/cm2 implant required over 2 hrs at 900°C to dissolve.t2gl 1.5
Effects of Type I Defects
In terms of the effect of voids on electrical properties, several studies have shown that voids can getter Si, thereby reducing Si diffision. Voids can also compensate the electrical activation of Si in GaAs possibly through the introduction of surface state deep acceptor levels.1341t351It has even been proposed that voids may be used as an implant isolation scheme because of their stability upon high temperature annealing.t3*l It appears that increasing the implant temperature results in both fewer voids and an increase in the amount of Si difI%sion. This is presumably because increasing the temperature increases the amount of point defect recombination during implantation, which reduces the critical concentration of vacancies below the concentration necessary for void formation. Without the competing vacancy sink of the voids, there are more vacancies available for Si diffusion. Voids also inhibit the intermixing of AlGaAs/GaAs superlattices that have been implanted with Si.t3’jl
Ion Implantation
303
Induced Extended Defects in GaAs
There appears to be no effect of implantation induced dislocation loops on the electrical activation of silicon in GaAs.161 This is somewhat surprising since it has also been reported that variations in the grown-in dislocation density across the GaAs wafer are responsible for shifts in the threshold voltage, due to increased Si activation near the dislocation core.l37ll38ll3gl In an effort to determine if there is a correlation between the amount of diffusion and the concentration of dislocation loops, a series of experiments was done in which semi-insulating LEC GaAs wafers were implanted with 1 x 1014/cm * 2gSi+ at various implant temperatures and energies.l18l The purpose of these studies was to determine how carefully controlled changes in the implant conditions affect the Type I dislocation loop concentrations and the difisivity. Because GaAs is very sensitive to minor changes in implant temperature around room temperature,111l the wafers in this study were mounted to the wafer holder using silver paint, and the temperature was monitored to within 2°C. Figure 12 shows SIMS plots ofthe redistribution of Si upon annealing for implants done at different temperatures. It is apparent that as the implant temperature increases, the amount of anomalous diffusion decreases. Since Si diffusion in GaAs is believed to occur via a vacancy-assisted mechanism, the increase in diffusivity with decreasing implant temperature implies the vacancy concentration is higher at lower implant temperatures. When the implant temperature was decreased to -51°C amorphization occurred. 1 ozo
0
0.1
0.3
0.2 Depth
0.4
0.5
0.6
(microns)
Figure 12. SIMS illustrating the effect of implant temperature on Si redistribution annealing 40 keV 2gSi+, 1 x 1014/cm2, annealed at 9OOT for 5 min.
upon
304
Compound
Semiconductors
Figure 13 shows plan-view and Fig. 14 shows cross-sectional TEM micrographs of the samesamplesin Fig. 12 after annealing. It is apparent that as the implant temperature increases, the concentration of extrinsic Type I dislocation loops increases. This implies that either the interstitial concentration is increasing with increasing implant temperature or the vacancy temperature. Figure 15 shows that as the implant temperature increases, the as-implanted RBS channeling yield decreases, indicating increasedpoint defect recombination. Increasingpoint defect recombination with increasing implant temperature is not consistentwith an increasein the interstitial concentration but, rather, the decreasein the total point defect concentration. The diffusion results in Fig. 12 would also imply that the vacancy concentration is decreasing with increasing implant temperature. Thus, it would appear that the dislocation loops are reacting to the same decreasein vacancy concentration which is affecting the silicon diffusion. In none of these samples were voids reported, presumably because the energy/dosecombination was too low (seeFig. 4).
Figure
13.
900°C,
5 min annealing.
Plan-view
TEM
micrographs
of the same samples in Fig. 12 after the same
Ion Implantation Induced Extended Defects in GaAs 305
20'C
40°C
80'C Figure
14.
same 900°C,
Cross-sectional
TEM
micrographs
of the same samples in Fig. 12 after the
5 min annealing.
"e ~ c .9. f c ~ c o u
in
Figure 15. SIMS results showing the redistribution of Si during 900°C annealing; 40 keY 29Si+.1 x 1014/cm2.annealed at 900°C.
306
Compound Semiconductors
Figure 16 shows the effect of annealing at 900°C on the diffusivity of silicon. It is obvious that a significant amount of diffusion is occurring at 900°C between five minutes and thirty minutes. It can also be seen that the amount of diffusion for the sample implanted at 40°C is greater than the sample implanted at -2OC. Since over the first 5 minutes, the diffusivity is higher for the sample implanted at the lower temperature, it appears that the source of the excess vacancies contributing to high silicon diffusivity between five minutes and thirty minutes is different from the vacancy source for the first five minutes. Figure 17 shows plan-view TEM results of these same samples. Cross-sectional TEM results confirm that after 30min annealing, the Type I dislocation loops have completely dissolved. It has been show@] that Type I loops for similar Si+ implants are stable for times as long as ten hours. These differences in defect stability indicate the annealing kinetics may also depend on subtle differences in the implant (wafer temperature, beam current, etc.) and annealing (cap quality, etc.) conditions. The results of Fig. 17 suggest that if the loops were strongly influencing the silicon diffusion, then one would expect the release of interstitials by the extrinsic dislocation loops to slow the diffusion down. The fact that the diffusion was high over this time interval, implies that the vacancy concentration was significantly higher than the interstitial concentration. This again is consistent with the loops reacting to an external change in the vacancy concentration. It is not presently known if there is a measurable increase in silicon diffusivity just after the loops dissolve. This might indicate if the absorption of vacancies by the loops during their dissolution significantly affects the total concentration of vacancies and thus, indirectly affects the silicon diffisivity. --t
Interstitials ----t
in Loops
RBS Xmin
9.0 10” my &
8.0 10”
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Figure 16. Effect of implant temperature on the as-implanted RE3S channeling yield and the post-annealing (SOO’C, 5 min) concentration of trapped interstitials in Type I loops for a 40 keV Si’ 1 x 1014/cm2 implant.
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Ion Implantation Induced Extended Defects in GaAs 307
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308
Compound Semiconductors
Additional experiments have been conducted while varying the implant energy for room temperature Si implants. Figs. 18 and 19 show that increasing the implant energy from 20 to 40 keV significantly decreases the diffusivity of the silicon upon annealing. In this case, the anneals were done at 800°C. The dit%sivity of implants at higher energies, up to 200 keV, were similar to the 40 keV implant. Plan-view and cross-sectional TEM results of the same samples, shown in Fig. 10, indicate there is a large increase in the Type I dislocation loop concentration with an increase in implant energy from 20 and 40 keV. Again no voids were observed for any of these implants. It appears that the vacancy concentration is higher at lower implant energies and this leads to significantly more diffusion and fewer dislocation loops. As before, when the vacancy concentration is high, the silicon diffusivity increases and the extrinsic loop concentration decreases. Recent simulation studies (TRIM) offer one possible explanation for the apparently high vacancy concentration in lower energy implants. These simulations indicate that the reason the vacancy concentration is so much greater for lower energy implants may be because of ejection of atoms from beneath the surface by recoiling atoms.l40l TRIM simulations indicate the concentration of vacancies produced by the ejection of atoms increases dramatically as the energy decreases. Additional experimental evidence appears to support these simulations. This points out an interesting conflict. Void formation would presumably be enhanced by an increase in vacancies. The dopant diffusion studies and dislocation loop studies just
0.3 0.2 Depth (W
Figure 18. Effect of implant energy on diffusion of 40 keV 2gSi+, 1 x 1014/cmZ, annealed at 8OO“C.
Ion Implantation
0
Induced Extended Defects in GaAs
0.1
0.2 Depth (pm)
0.3
309
0.4
Figure 19. Effect of implant energy on diffusion of 20 keV 2gSi+, 1 x 1014/cm2, annealed
at 800°C.
mentioned indicate the vacancy concentration increases as the energy is decreased. However, earlier it was shown in Fig. 4 that voids are not observed at lower energies, as one might expect, but at higher implant energies. One possible explanation is that stable void formation depends strongly on the depth of the vacancies below the surface, whereas dopant diffusion does not, but the reason for this is not clear. Figure 20 shows the effect of additional annealing on the Type I dislocation loop concentration in 200 keV implants. For annealing times between one hour and eight hours at 8OO”C, the loop concentration has decreased significantly. The deeper loops appear to be more stable than the shallower loops. Figure 2 1 shows the effect of this additional annealing on the Si diffusivity for the same samples. No significant Si diffusion is observed for these implants during the time the loops are dissolving. This is consistent with the results shown in Figs. 18 and 19, which indicate that increasing the implant energy decreases the amount of Si diffusion. It is also consistent with the previous observations that the dissolution of the dislocation loops is not significantly affecting the Si diffusion. However, as with the variable temperature experiment, it remains unclear if the loops are providing a sink for vacancies, and thus keeping the Si difl%.ivity low. Additional annealing experiments after the loops have completely dissolved could be done to determine if the diffusivity suddenly increased.
310
Compound Semiconductors
1 Hour
8 HOUR
Figure 20. The effect of 800°C annealing on Type I dislocation loops from a 200 keV Si+, 1 x 1014/cm2,room temperature implant.
1020
1019
"8 ~ c o
; f c .. " c 0 u
1018
rn 1017
0
0.2
0.4
0.6
0.8
Depth (j1m)
Figure 21. The effect of 800°C annealing on Si diffusion for a 200 keY Si+, 1 x 1014{ cm2, room temperature implant.
Ion Implantation
Induced Extended Defects in GaAs
311
In summary, for Si+ implants in GaAs, it has been shown Type I defects have two principle forms, voids and dislocation loops. Void formation is strongly dependent on implant energy (occurring at higher energies and doses). Voids can compensate Si doping and also appear to affect the difhrsivity of Si. It has been shown that by increasing the implant temperature or increasing the implant energy of Si+ in GaAs, the amount of diffusion decreases and the concentration of dislocation loops increases. It was also observed that, upon annealing, the silicon diffusivity was high while the dislocation loops were dissolving. All of these observations are consistent if one assumes silicon diffises via a vacancy mechanism in GaAs and the formation and dissolution of the Type I extrinsic dislocation loops does not directly affect the silicon diffkivity. Instead, the loops are reacting to the same changes in vacancy concentration that are affecting the diffusing silicon. It remains possible that the loops have an indirect affect on the silicon difhrsivity by acting as a vacancy sink. Figure 22 summarizes how defects from Si+ implantation are presently believed to affect Si activation and diffusion in GaAs.
As -Implanted Morphology
Crystalline
Amorphous
Twins, SF, Anneal 8 700°C
No Diffusion
Less Activation
Clusters
Dislocation Loops
Voids
Si Activation
Figure 22.
Summary of the effects of defects
in Si+ implanted GaAs
Clusters
Si Diffusion
312
Compound Semiconductors
In addition to Si+ implants Type, I damage can also affect other species. Implant damage from implants below the Type I dislocation loop threshold (< 1 x 1013/cm2),has been shown to result in a greatly enhanced diffusivity of the compensating impurity Cr.1411 Recently there has been much discussion on how the Type I defects (specifically dislocation loops) influence the p-type dopant diffusion process.[2pl[421[431 After implantation, there exists a large concentration of point defects which are responsible for transient diffusion process upon annealing of Be and Mg implants. Upon annealing, dislocation loops can behave either as sources or sinks for excess point defects and thus, potentially, may affect the transient diffusion process. As mentioned, the effect (if any) of Type I dislocation loops on the diffusion of Si in GaAs is not known and is still being studied. However, Si is known to diffuse in GaAs primarily via a vacancy-assisted mechanism. The effect of implant damage on interstitial diffusers such as Be and Mg is very pronounced. Be and Mg appear to go through several phases of diffusion, which represent unique states of point defect equilibrium.[431 Low dose (1 x 1013/cm2)Be+ implants exhibit no Type I dislocation loops and a well-defined diffusion transient, after which the diffusivity slows down. However, when Type I dislocation loops are introduced via 1 x 1014/ cm2 Al+ co-implantation, the loops apparently can absorb the extra interstitials from the damage and no transient diffusion is observed.
2.0
TYPE II DEFECTS
Voids have also been observed in the damaged crystalline region layer below the amorphous/crystalline interface after annealing as high as 850°C for 5 seconds.1201 These appear to be the only stable form of Type II defects. No reports on the annealing temperature necessary for Type II void dissolution has been reported. Unlike silicon, Type II dislocation loops in GaAs are very unstable. For example, when the implant temperature is decreased from -2°C to -5 1°C for 40 keV, 1 x 1014/cm2,implants into GaAs, amorphization occurs (Fig. 23). RBS results done immediately after implantation confirm this. Upon annealing, Type II dislocation loops dissolve after five minutes at 900°C. The -2’C implant, which was not amorphized, shows stable Type I loops have formed as previously discussed. In other experiments, when the dose of the Ge, As, and Se implants, discussed in Fig. 8, was
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c ~ o C .-oj ~-s:. E .§ "g .
@~ .-~ -0 0 -0; .5
0 .-"'
u o r;l e e '"" -0 u "' oj ~ 3 -0 .~ ~ ;3 ~... 8. e ,.g C oj -s:. .§ U -:S C U ~ C
Induced Extended Defects in GaAs 313
00 00
u o
N
~
u o InI
314
Compound Semiconductors
increased to 1 x 1014/cm2, amorphization occurred for all three implant energies. Upon five-minute annealing at 900°C no Type II dislocation loops were observed. A recent paper by Inada et al. also confirms that for Se+ implants, when the sample is amorphized, no Type II dislocation loops form upon rapid thermal annealing at 1000°C for 10 ~ec.1~1 The temperature at which Type II dislocation loops and clusters dissolve can be discerned from previously published work. The Type II damage, in the form of small point defect clusters from Si+ implants, dissolve for 30-set anneals between 400 and 600”C1451 and below 600°C for Zn implants.146l It is not known why Type II dislocation loops are very stable in silicon but unstable in gallium arsenide.
3.0
TYPE III DEFECTS
It is well documented that upon annealing amorphized GaAs, the solid phase epitaxial recrystallization process results in the formation of a high concentration of microtwins and stacking faults.1471-14gl The reason for the poor quality SPER process is believed to be related to local deviations in the stoichiometry induced by the implantation process.161 After annealing, the Ga and As atoms are not able to diffuse sufficient distances to maintain stoichiometry and avoid the nucleation of Type III defects.1501 Figure 24 shows a cross-sectional TEM micrograph of a 110 keV, 1 x 1015/cm2, Ge+ implant into GaAs. The sample was amorphized during implantation; however, solid phase epitaxial regrowth of the amorphous layer took place either during the implant or during the TEM sample preparation. Both Type III and Type II defects can be seen. It has been shown that high quality solid phase epitaxial regrowth in GaAs is possible for the first few hundred angstroms of regrowth.1511 This would explain the separation of the Type II and Type III defects in Fig. 24. Type III defects have been reported to anneal out by 700°C for furnace annealing (15 min)[461 and between 700 and 800°C for rapid thermal annealing (30 set). [451These defects are thus very unstable relative to Type I defects. This would favor amorphization of GaAs from the standpoint of minimizing extended defects; however, dopant activation is much lower in amorphized layers as discussed above.
Ion Implantation Induced Extended Defects in GaAs 315
Surface
Type III Defects
Type II Defects
Figure 24. As-implanted cross-sectional TEM micrograph of a 110 keV, Ge+ implant into GaAs.
4.0
x IOIS/cm2,
TYPE IV DEFECTS
Chen et al. showed that for a buried amorphous layer produced by 220 keV, 1 x 101slcm2,Si implants, no distinct Type IV dislocation loop layer formed.[20] The Type III regrowth-related defects were of such high density that no Type IV layer could be discerned. In addition, 5-sec annealing at temperaturesbetween 750°C and 850°C dissolves all Type III and any Type IV defects, if they ever existed. Whether Type IV defects form upon annealing buried amorphous layers in GaAs is not clear, but it does appear that they are no more stable than the Type III defects. Figure 25 shows a cross-sectional TEM micrograph ofa 160 keV, 1 x 1014/cm2, room temperature Ge+ implant before annealing and a plan-view TEM micrograph after annealing at 900°C for five minutes. Because of the
316
Compound
Semiconductors
instability of Types II, III and IV defects, no defects appear after annealing. Figure 8 indicated that for the same implant at a lower dose (5 x IO13/cm2), Type I dislocation loops form since this implant was below the dose necessary for amorphization.
As Implanted Cross-section
9OQ'C
5 miD
Plan-view
Figure 25. Cross-sectional TEM micrograph of a 160 keY, 1 x 1014/cm2, room temperature Ge+ implant before annealing and a plan-view TEM micrograph after annealing at 900°C for five minutes.
5.0
TYPE V DEFECTS
Type V defects form as a result of exceeding the solid solubility . These defects typically have the form of either precipitates or dislocation loops, dependingon the implanted species. Recent studies have shown that for Si+ implants, Type V defects form for doses ~l x 1015/cm2 implants.[31][45][52]Figure 26 shows plan-view TEM micrographs of 40 keV, 1 x 1015/cm2,Si+ implants after anneals of five minutes and thirty minutes at 900°C. Cross-sectional TEM analysis show that the implants, which were done at temperatures slightly above room temperature, did not amorphize the sample and the loops formed at the projected range. This raises the question as to whether the loops are Type lor Type V, since both form typically at the projected range of the ion profile.
Ion Implantation Induced Extended Defects in GaAs 317
5 minutes
30 minutes
Figure 26. Plan-view TEM micrographs of 40 keY, 1 x 101S/cm2,Si+ implants after 5 min and 30 min at 900°C.
Based on discussions in Sec. 1.4, it would be unusual for Type I defects to suddenly increase in size and density at 900°C. In fact, they should be dissolving. This suggests that the loops observed after thirty minutes are Type V defects. Since Types II, III and IV defects are unstable at this temperature, the simplest experiment to determine if the loops are Type lor V is to amorphize the sample and seeif the loops still form. For a40 keV, Si+, 1 x 101S/cm2, implant into GaAs, Fig. 27 showsthat when the implant temperature is decreasedto 20°C, amorphization occurs. Upon annealing, the loops again formed. This supports the premise that the loops are Type V defects. Above concentrationsof2-5 x 1018/cm2, Si is known to occupy both Ga and As sites. Thus, when going onto substitutional sites, Si should produce both Ga and As interstitials. These excess interstitials may be the source of point defects for the Type V dislocation loops. The concentration of interstitials bound by the loops is less than 1 x 101S/cm2.This model is, therefore, consistent. These Type V dislocation loops dissolve after annealing for 10 hrs at 900°C.
318
Compound
Semiconductors
As Implanted XTEM
900°C 5 min. PTEM
x min.
89%
19%
19%
Figure
27.
Effect of implant
temperature
on Type V dislocation
loops. Si+, 40 keV, 1 x
101S/cm2 implants.
Figure 28 shows that relative to Si+, 1 x lOIS/cm2 Al+ implants produce far fewer dislocation loops during annealing. This is presumably becauseAl forms a continuous solid solution with GaAs. Ge, like Si, is also an amphoteric dopant. Figure 29 shows that a 11OkeV, 1 x lOIS/cm2Ge+ implant at room temperature will amorphize the sample. Upon annealing, Type V dislocation loops are again observedto form. These defects have a very similar morphology to the Type V defects from the Si+ implants. This may again be the result of the amphoteric nature of the dopant.
Ion Implantation Induced Extended Defects in GaAs 319
AI
Si 1e15, Annealed
1e15, Annealed
40 keV 30m,9000C
PTEM
PTEM
Figure fonnation
28.
Plan-view
TEM
40 keV 30m,9000C
showing
the effect of implant
for 40 keY, 1 x 101S/cm2, implants
after 900°C,
species on dislocation 30-min
loop
annealing.
Some species fom1 Type V defects that consist of both precipitates and extended defects. Bhattacharya et al. observed that for 120 keV Se+ implants, Type V defects fom1 for dosesas low as 1 x 1014/cm2.[2S]Their samples were amorphized which is consistent with the results showing amorphization occurring between 5 x 1013/cm2and 1 x 1014/cm2. Upon annealing at 900°C for 15 min using a PECVD Si3N4 cap, they observed small dislocation loops and Se precipitates forming. In addition to metallic precipitates, Morita et al reported stacking fault tetrahedra formation and dislocation loop fom1ation associated with precipitation in Zn implanted GaAS.[S3] In this case, the Type V dislocation loops dissolved after ten minutes of annealing between 850°C and 950°C. The precipitates were observedto fom1 at Rp and deeperdepths. Sn+ is another species that fom1s what appears to be pure metallic precipitates. Figure 30 shows cross-sectional TEM micrographs of a 185 keV, 1 x 101S/cm2implant after annealing for thirty minutes at several temperatures. The Sn precipitates originally fom1 near the projected range of the implant, as expected.
320
Compound
Semiconductors
1021
1015
0.1
0
0.2
0.4
0.3 Depth
(I1m)
(/) Q) 5 c: °E o
C') o 8 0>
Cross-section
Figure
29.
temperature
Type V dislocation will
amorphize
Plan-view
loops from
the sample.
110 keY, I x 101S/cm2, Ge+ implant
at room
Ion Implantation Induced Extended Defects in GaAs 321
As-Implanted
700.C
800.C
900"C
Figure 30. Cross-sectional TEM micrographs of a 185 keY, 1 x 101S/cm2,Sn+ implant after annealing for 30 min.
322
Compound Semiconductors
Several authors report plan-view TEM studies from which they conclude that the small metallic Sn precipitates are decorating Type V dislocation loops that formed upon annealing high dose (1 x 10i5/cm2) Sn implants of 300 keV1541and 150 keV.IS51 These loops and metallic precipitates are stable after 1000°C annealing for 5 set, and 850°C for 15 min, respectively. The results in Fig. 30 show that the only dislocation loops that form are at a much greater depth (1700 A) than the precipitates (700 A), which would make decoration by the precipitates difficult in these samples. These dislocation loops form at depths of 1000 A below the amorphous/ crystalline (a/c) interface, which is much deeper than where Type II defects are normally observed relative to the a/c interface. They also grow in size between 700 and 8OO”C, whereas Type II defects are unstable at temperatures greater than 6OO”C, as discussed previously. The source of point defects for these loops is uncertain They are found to dissolve upon annealing for 30 min at 900°C. The metallic Sn precipitates have been observed by several authors to form either the cubicl161 or tetragonal1541 form of pure Sn. An unusual phenomenon related to annealing high dose Sn-implanted GaAs is the motion of the Sn precipitates. The precipitate layer moves to deeper depths as the annealing temperature is increased for isochronal annealing (both furnace and RTA). This can be seen in Fig. 3 1, which shows the SIMS plot before and after 900°C annealing for the same samples as in Fig. 30. The polaron measurement shows the Sn is well above the solubility limit. The bump in the SIMS corresponds to the depth of the precipitates. This motion of the precipitates has only been observed in Sn implants. It was speculated that the motion involved a form of internal liquid phase motion. Sn has a low melting point (232°C) and is an excellent solvent for liquid phase epitaxial growth of GaAs.1561 GaAs may dissolve on the deeper side of the Sn precipitates and be redeposited on the shallower side of the precipitate as the precipitate moves. The motion of the precipitate layer is plotted as a function of annealing temperature in Fig. 32. An Arrhenius plot of the peak motion yields an activation energy of around 0.1 keV, which is much less than any solid phase diffusion process. In order to discern the driving force for Sn motion, several experiments were conducted. It is found the peak motion is not gravity driven, as the Sn moves the same distance if the wafer is placed face-up or face-down.l16l The motion occurs whether the sample is capped with S&N, and furnace annealed, or rapid thermally annealed in an arsine overpressure. The driving force for the motion is still unknown.
Ion Implantation
Induced Extended Defects in GaAs Furnace
102’
323
3 0 m / 9 0 0°C
Anneal
loM 1o19 lo’*
L
10”
3
1o16 10IS
I I
I
I
I
I
I
I
0
0.1
0.2
0.3
0.4
0.5
0.6
1
Depth bm)
Figure 31. SIMS plots before and after 30 min, 900°C annealing for the samples shown
2
185 keV Sn 1 X 10 %n
800 600
600
700
800
900
1000
Anneal Temperature (“C) (30 minutes)
Figure 32. temperature.
The motion of the precipitate layer is plotted as a function of annealing Sn’, 185 keV, 1 x 10’s/cmZ implant annealed for 30 min with Si,N, cap.
324
Compound Semiconductors
6.0
CONCLUSIONS
This chapter reviewed the types of extended defects that arise from annealing ion implanted GaAs. The defects can be classified using the same scheme developed for implantation-related defects in silicon. Type I defects were shown to be the most stable form of defects. These defects consist of both voids and extrinsic dislocation loops. Voids require higher energies (>200 keV) and higher doses (21 x 1014/cm2) to form, while dislocation loops also show a strong energy dependence but form at doses as low as 1 x 10i3/cm2. The voids are very effective in compensating the electrical activity of any dopants and may affect the ditisivity of ion implanted Si+. The dislocation loops are sensitive to changes in the vacancy concentration and, as such, are good detectors of point defect perturbations. They are not observed to directly affect the ditisivity of implanted Si+. For other species which diffuse interstitially, dislocation loops may influence the diffusivity, possibly by trapping extra interstitials created by the implantation process. Type II dislocations are very unstable in GaAs, annealing out by 6OOOC. This is in marked contrast to implanted silicon, in which Type II dislocation loops are among the most stable form of damage. Type III defects in GaAs form anytime an amorphized sample is annealed. Type III defects are believed to form because of local deviations in the stoichiometry and the low diffusivity of Ga and As at the regrowth temperatures. These stacking faults and microtwins anneal out at lower temperatures (< 600°C). Type IV defects have never been observed because of the high concentration of Type III defects that form during solid phase epitaxial regrowth of buried amorphous layers. If they do form, they anneal out at temperatures < 600°C. Finally, Type V defects can consist of either precipitates, dislocation loops, or both. Amphoteric dopants such as Si and Ge tend to form only dislocation loops. Other dopants, such as Zn and Se, form both metallic precipitates and in some instances dislocation loops. The precipitates for Sn implants show unusual motion into the crystal which may be related to a form of liquid phase epitaxy on a microscopic scale. Figure 33 is a summary of the annealing kinetics of the different types of implant related defects that form in GaAs. This is a modification of the annealing kinetics published by Peat-ton et a1.157lThe figure is very general as the exact annealing kinetics have been shown to depend on the implant species and other factors. It is clear that the ability to accurately model the activation and redistribution of implanted dopants in GaAs ,depends on
Ion Implantation
Induced Extended Defects in GaAs
325
understanding the effect of the extended defects that arise during the postimplantation annealing process. Temperature 0°C
200°C
4
I
I ---)
w
loooOc I
800°C
600°C
4oo”c
I
I
1200°C
Dopant on lattice silts
Implantation *
4
Amorphous to crystalline transition
t Activation of p-type t Activation of n-type Type I defects eliminated
Type II defects eliminated 4
-Type
b
V defects eliminated
Type 1U defects eliminated 4
w
Type IV defccu eliminated
Figure 33. A summary of the annealing kinetics of the different types of implant-related defects that form in GaAs.
REFERENCES 1. Williams, J. S. and Poate, J. M., Ion Implantation Academic Press, Sidney (1984)
and Beam Processing,
2. Ziegler, J. F., Handbook of Ion Implantation Publishing, Netherlands (1992)
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6. Pearton, S. J., Sol. Stat. Phen., l&2:247-280 (1988) 7. Se&y, B. J., Inter. Mater. Rev., 33:38-52
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9. Haynes, T. E., Morton, R., and Lau, S. S., Lattice implanted compoundsemiconductors
damage in ionand its effect on electrical activation,
presented at the MRS III-V Electronic and Photo& and Performance Conference in Pittsburgh (1993)
Device Fabrication
326
Compound Semiconductors
9. Haynes, T. E., Morton, R., and Lau, S. S., Lattice damage in ionimplanted compoundsemiconductors and its eflect on electrical activation, presented at the MRS III-V Electronic and Photonic Device Fabrication and Performance Conference in Pittsburgh (1993) 10. Haynes, T. E., Holland, 0. W., and Desnica, U. V., Damage accumulation in gallium arsenide during silicon implantation near room temperature, submitted to Mat. Rex Sot. (199 1) 11. Haynes, T. E. and Holland, 0. W., Appl. Phys. Lett., 59:452454
(1991)
12. Wendler, E., Wesch, W., and Gotz, G., NIMPR, B55:789-793 (1991) 13. Wendler, E., et al., Phys. Stat. Sol. A., 126:K105-K108 (1991) 14. Jones, K. S. andRozgonyi, G. A., ExtendedDefectsfromIon Implantation andAnnealing. Rapid Thermal Processing: Science and Technology, (R. B. Fair, ed.), Academic Press, Orlando (1992) 15. Jones, K. S., Prussin, S., and Weber, E. R., Appl. Phys. A., 45: 1 (1988) 16. Jones, K. S., Bollang, M., Haynes, T. E., Deal, M. D., Allen, E. L., and Robinson, H. G.,Mat. Res. Sot. Symp. Proc., 240:785-796 (1992) 17. Donnelly, J. P., Nucl. Instr. Meth., 182/183:553-571 (1981) 18. Jones, K. S., Robinson, H. G., Haynes, T. E., Deal, M. D., Lee, D. C., and Allen, E. L., Mat. Res. Sot. Symp. Proc., 300:323-330 (1993) 19. Bellon, P., et al., Inst. Phys. Conf Ser., pp. 309-3 14 (1987) 20. Chen, S., et al.,J. Appl. Phys., 70:656-660 (1991) 21. Chen, S., et al., Jpn. J. Appl. Phys., 29:L1950-L1953
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22. Chen, S., et al., XII International Congress for Electron Microscopy, pp. 25-28 (1990) 23. Stewart, C. P., et al., Physica, 116B:635-640 (1983) 24. Frigeri, Weyher, and Potter, Appl. Sur. Sci., 50:115-l 18 (1991) 25. Bhattacharya, R. S., et al., J. Appl. Phys., 53:4821-4825 (1982) 26. Bachmann, T. and Bartsch, H., Nucl. Inst. and Meth. in Phys. Res. B., B43:529-534 (1989) 27. Gwilliam, R., et al.,Mat. Res. Sot. Symp. Proc., 92:437442
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28. Geissberger, A. E., et al., J. Vat. Sci. Tech. A., 4:3091-3094 (1986) 29. Robinson, H. G., et al., Time dependent diffusion of p-type dopants in GaAs, presented at the III-V Electronic and Photonic Device Fabrication and Performance Conference in Pittsburgh (1993) 30. Listebarger, J. K., Jones, K. S., and Slinkman, J. A., J. Appl. Phys., 73:4815-4819 (1993) 31. Jones, K. S., et al., J. Appl. Phys., 70:67906795
(1991)
32. Ko, K. Y., et al., Mat. Res. Sot. Symp. Proc., 262:1085-1090 (1992)
Ion Implantation 36. Lee, S.-T., et al.,Appl.
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Induced Extended Defects in GaAs Phys. Lett., 57:389-391 (1990)
37. Miyazawa, S. and Wada, K., Appl. Phys. Lett., 48:905-907 38. Hyuga, F., J. Appl. Phys., 64:3880-3884
(1986)
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39. Morrow, R. A., J. Appl. Phys., 64:6254--6258
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40. Lee, C., unpublished. 41. Kanber, H. and Whelan, J. M., J. Electrochem.
Sot.,
134:2596-2599
(1987) 42. Robinson, H. G., et al., Correlation ofdislocation loop formation and time dependent difision oJimplantedp-type dopants in gallium arsenide,
presented at the Advanced III-V Compound Semiconductor Processing and Devices Conference in Pittsburgh (1992).
Growth,
43. Robinson, H. G., et al.,J. Appl. Phys., 71:2615-2623 (1992) 44. Inada, T., Miyamoto, K., and Nishida, A., Mat. Res. Sot., 92:431-436 (1987) 45. Opyd, W. G., et al., Appl. Phys. Lett., 49:974-976 46. Kular, S. S., et al., Sol. Stat. Elec., 23:831-838
(1986) (1980)
47. Williams, J. S., Laser Annealing
of Semiconductors, (J. M. Poate and J. W. Mayer, eds.), p. 383, Academic Press, New York (1982) 48. Williams, J. S. and Austin, M. W., Appl. Phys. Lett., 36:994-996 (1980)
49. Sadana, D. K., Nucl. Inst. andMeth.
in Phys. Res. B., 7/8:375-386
(1985)
50. Sadana, D. K., Sands, T., and Washburn, J., Appl. Phys. Lett., 44:623625 (1984)
51. Grimaldi, M. G., et al.,Appl.
Phys. Lett., 39:70-72
(1981)
52. Bhattacharya, R. S., et al.,J. Appl. Phys., 54:2329-2337
(1983)
53. Morita, E., Kasahara, J., and Kawado, S., J. Appl. Phys., 24:1274-1281
(1985) 54. Shahid, M. A., et al., Nucl. Instr. Meth. Phys. Rex, B30:531-539 (1988) 55. Shim, T.E., Itoh, T., and Yamamoto, Y., J. Appl. Phys., 61:46354639 (1987) 56. Ghandhi, S. K., VLSI Fabrication
Principles,
John Wiley and Sons, New
York (1983) 57. Pearton, S. J., et al., Nucl. inst. Meth. Phys. Res., B19/20:369-380 (1987)
Passivation InP
of GaAs
and
Enod Malhotra and Carl FK Wlmsen
The III-V compound semiconductors, such as gallium arsenide (GaAs) and indium phosphide (InP), have been long recognized for their potential applications in high speed electronic and optoelectronic circuits. Some of the advantages of these semiconductors over silicon are high electron mobility, high-saturation drift velocity, direct energy bandgap, radiation hardness, fabrication of a variety of useful heterojunction structures, and potential monolithic integration of optical and electronic functions. However, in the list of disadvantages, probably the most severe drawback is that their surfaces are of poor “electronic” quality, and a good passivating fihn with suitable electrical, chemical, and physical properties has not yet become available. The lack of control of the surface and the metalsemiconductor (M-S) and insulator-semiconductor (I-S) interfaces have severely impeded the broader use of the materials in electronic and photonic applications. For numerous important devices, it is imperative to fabricate surfaces/interfaces with low density of states in the forbidden energy bandgap of the semiconductor. The presence of a large number of electronically active defects results in poorer device performance and reliability. The effects of these states manifest themselves in a variety of different ways, and they adversely effect a majority of devices. For example, in heterojunction bipolar transistors (HBTs), the defects may cause a high rate of
328
Passivation
of GaAs and InP
329
recombination along the mesa surfaces, resulting in lower current gain; in photodiodes; they may cause large reverse leakage currents, lower breakdown voltage, and lower responsiveness. A much more severe consequence of the interfacial defects is exhibited in the case of M-S and metal-insulatorsemiconductor (MIS) junctions. The excessive number of electronic states in the bandgap cause Fermi-level pinning and, in the case of MIS structures, prevent the surface potential from being modulated with the gate voltage; thus accumulation or inversion regions cannot be formed. Therefore, preparation of surfaces with acceptable levels of electronically active defects is essential for proper functioning of many devices. The technology of reducing the adverse effects of defects is referred to as pussivution (the term pussivution also encompasses a somewhat passive role, whereby the objective is to stabilize the properties of the surface in such a way that it becomes immune to exposure of the device to operating ambients). So that a systematic approach to developing techniques for passivation may be designed, it is desirable to have a good understanding of the nature of the states and the cause(s) of their origin. Unfortunately, the fundamental knowledge of the surfaces has been very limited. This is because of the enormous complexity of the interface both in terms of its structure and the electrical properties. Therefore, the research on passivation technology, for both Si and III-Vs, has been primarily based on empirical techniques. In silicon technology, passivation is achieved with the use of a Si02 overlayer, which is native to the semiconductor and, fortunately, also a good passivant of the states on the silicon surface. After an extensive amount of research, a genera1 framework has evolved which suggests that the following aspects of the SiO#i interface must be minimized to achieve good passivation: (i) dangling bonds on the silicon surface, (ii) bond angle disorders, (iii) dangling Si bonds and Si-Si bonds in the oxide, (iv) stretched Si-0 bonds and Si-Si bonds, (v) trivalent Si-Si bond, and (vi) silicon interstitials in the oxide. Several fundamental models have been proposed, but none of them explain all the observed experimental features satisfactorily. Clearly, the surface of III-V semiconductor is very complex because the material is a compound with a myriad of possibilities for defect generation at the free surfaces and interfaces. Although passivation of the defects may be achieved using epitaxial growth of heterojunction structures, for example AlGaAs on GaAs, these schemes are applicable to only a limited number of devices. Several attempts were made to form native oxides (analogous to the Si02/Si interface), however, none exhibited promise as a
330
Compound Semiconductors
passivation layer. A variety of different dielectric films deposited under variant conditions have been extensively investigated but, unfortunately, a commercially viable MISFET device has not yet emerged. In this chapter, we do not review the vast extant of findings in this area. However, it is important to mention that after several years of research on I-S interfaces, the issues related to dielectric deposition onto compound semiconductors have now become better understood and, as a result of this, newer approaches have been adopted for their fabrication. The techniques which appear to be promising include electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD), photoenhanced CVD, and indirect rfplasma-enhanced CVD. These methods allow the use of low substrate temperatures, minimize damage to the surface/interface during the dielectric deposition, and produce dielectrics with good electrical and chemical properties. It is evident that further advancements in dielectric growth techniques will continue to be extremely important for passivation and future growth of III-V based IC technology. Recently, there have been some significant developments in passivating the surfaces of GaAs and InP. The passivation schemes include the use of epitaxial regrowth, growth of a thin buffer layer of Si between M-S and I-S interfaces, in-situ hydrogen plasma cleaning of the native oxides, and treatments with sulfide solutions and H2S. For example, treatment with sulfide solution or hydrogen plasma, followed by dielectric deposition under “soft” plasma conditions, have resulted in superior I-S interfaces. These results indicate that the defect densities in the range of 10” cm-* eV-’ for Si02/InP, SiN/InP, and SiN/GaAs interfaces can be achieved. Since Fermi-level pinning in the bandgap occurs with defect densities typically much greater than lo’* crnm2eV-l, these values indicate that the interfaces are well-passivated. It must also be noted that the early transistors reported in the Si02/Si system had defect densities in the lo’* cm-* eV-l range, and it has taken approximately thirty years of research to reduce the defect density by approximately three orders of magnitude. Whether similar progress will occur in compound semiconductors is obviously not known but, at least for now, it appears that hopes for improved passivation have been rekindled. In this chapter, we review some of the important developments that have occurred in the last few years in InP and GaAs passivation. We also present a brief review of the proposed models for surface defects and the causes of their origin. This area continues to remain controversial, and therefore, we excuse ourselves from attempting to include everything that has been done or said in the field.
Passivation 1.0
of GaAs and InP
331
SURFACE DEFECTS, FERMI-LEVEL PINNING, AND DEFECT MODELS
In this section, we briefly summarize some salient aspects of free GaAs and InP surfaces, with respect to defects and Fermi-level pinning. A considerable amount of work has been published in this area, and readers are referred to a few publications for details.tll-llgl Typically, the clean free semiconductor surfaces do not retain their ideal bulk structure and relax in order to minimize the bond and strain energies. The most well-studied surface in this regard has been the (110) GaAs surface, in which the As and Ga revert back to their valences of five and three, respectively. Low-energy electron diffraction studies on these surfaces exhibit tilting of the surface bonds such that As atoms move outward, and the Ga atoms move inward. The breaking of bonds leads to formation of the intrinsic defect states which, in the case of (110) GaAs surfaces, are fortuitously swept out of the bandgap of the semiconductor as a result of rearrangement due to relaxation. Such a surface, when cleaved under III-IV conditions, exhibits no Fermi-energy pinning. Similar results have been obtained for InP, InAs, and GaSb. However, exposure of these surfaces to even submonolayers of oxygen and a variety of metals such as Al, Ga, In, and Au leads to strong Fermi-level pinning. As shown in Fig. l(a), in the case of n-type and p-type GaAs, the Fermi energy gets pinned at approximately 0.75 eV and 0.52 eV above the valence band maximum (VBM), respectively. In the case of InP, the pinning positions fall into two regions: one near the middle of the bandgap and another approximately 0.1 to 0.3 eV below the conduction band. An important observation has been that the pinning positions appear to exhibit little or no dependence on the type of adsorbate. The situation for (001) surfaces is structurally and electronically somewhat different. An ideal surface may contain only cations or only anions. In reality, this is never the case and reconstruction of the surface displays numerous forms which in turn depend upon the method of preparation and chemical composition of the surface. Svensson et a1.l14l reported a systematic study of (001) MBE-grown As-rich surfaces. The Fermi energy is pinned on the surface and its positions are shown in Fig. l(b). With increasing As concentration in going from (4 x 6) to C(4 x 4) reconstruction, the pinning position moves closer to the CBM. MBE-grown Ga-rich surfaces have not been studied as thoroughly, however, there is some indication that the Fermi-level moves towards the VBM.l151 Recently,
332
Compound Semiconductors
Brillson et a1.[161reported results on MBE-grown samples (with in-situ deposition of metals) and presented an argument which suggests that the Fermi level is not quite pinned in these surfaces. The Er shifts extend over 0.7 eV and evolve over 5 to 20 A cover-ages of metal. The explanation suggests that the improved properties of their samples is due to the relatively superior quality of MBE-grown material compared to the melt-grown GaAs crystals. FERMI LEVEL P I NNNG
? & z3 6
1.2 0.8
(4
0.4
I
1.0 9 * 5 >
As Ga ANTISITE
_ 0.8 0.75
-
I
I
GaAs (001) n-type -
0
-y----
0
Anneahg Deposition
0.0
’
I
(4x6)
I
o 0 n
0.75
(b)
I
c(2xa)
C(4x4)
RECONSTRUCTION INCREASING
As
Figure 1. (a) The diagram to the let? shows the pinning positions of the Fermi level, at room temperature, obtained on (0) n-type and (D) p-type (110) GaAs with very low The right diagram shows the levels of As antisite coverages of the indicated elements. defects measured at 8 K (after Ref. 7). (?I) The surface Fermi levels in MBE-grown n-type and p-type (100) GaAs. The dashed lines indicate the levels of AUDM (afier Ref. 16).
Passivation
GaAs
Figure 2.
GaP
of GaAs and InP
333
IrP
Correlation between the I-S, S-S, and M-S interfaces (after Ref. 10)
The I-S interfaces on GaAs and InP have also been studied extensively. The distribution of the density of states in the energy bandgap of the semiconductor is typically U-shaped. The minimum trap density for the insulator-InP interface has been found to be lower than the ones observed in insulator-GaAs interfaces. Hasegawa et a1.151conducted a comprehensive study on a variety of dielectric-semiconductor interfaces, and suggested that the minimum trap density and the curvature of the U-shape distribution is very strongly dependent upon the insulator species and the processing conditions. However, the energy location Eh, at which the density of defects is minimum, is nearly constant for each semiconductor and practically insensitive to the type of the insulator. They also found a strong correlation between Emi, and the Fermi level pinning positions in M-S interfaces. These energy locations lie within a narrow range as illustrated in Fig. 2.1101 Due to the extensive experimental data and the commonly held belief that pinning of the Fermi energy occurs within a narrow band of energies, there have been several proposals of diverse hypotheses which attempt to explain the phenomena using physical models. These include the (i) advanced unified defect model (AUDM),t7~181 (ii) effective work function (EWF) model,lgl (iii) disorder induced gap state (DIGS) mode1,1511611101 (iv) metal-induced gap states (MIGS) model,tl’l (v) virtual gap states model,ll*l and others.tlltlgl The AUDM attributes the Fermi-level pinning to the
334
Compound Semiconductors
defect-derived discrete deep levels; the levels at 0.75 eV and 0.5 eV above VBM are associated with As antisite defect (double donor). So that the Fermi-level could be pinned at 0.75 eV for the n-GaAs, the presence of acceptor-like levels between the 0.5 eV level of the Asoa antisite and the VF3M is also speculated. These levels have been assigned to the GaA, antisite defects. The validity of the AUDM model has been argued partly on the basis of the movement of the Fermi-level pinning position with the changing AsoJGak, ratio at the interface. In the case of InP, the Fermilevel pinning is associated with the discrete levels, due to the cation antisite defects InP (acceptor-like) and the phosphorous vacancies VP (donorlike).llil The EWF model assumes that disruption of the surface/interface occurs as a result of the overlayer which leads to mixed phase interfaces. The interface Fermi level depends upon the work function of the anion released from the substrate, due to the chemical reactions and, therefore, is independent of the bulk metallurgy. The main premise for the basis of DIGS is the formation of localized and extended energy states within the bandgap, due to the mismatch in bonding configurations, the disruption of stoichiometry, due to the chemical reactions, and the formation of point defects and misfit dislocations. The DIG state continuum is comprised of antibonding (donor-like) and bonding (acceptor-like) states. The position of the pinned Fermi level has been argued to be at the location of the charge neutrality level, Eno, determined by the hybrid orbital energies of the constituent cations and anions.l10l The Euo and the pinning position for a variety of compound semiconductors are shown in Fig. 2. For the most part, the studies of defect formation and their origins have been conducted on UHV-cleaved surfaces that are atomically clean. In the air-exposed surfaces, the situation is further complicated because of the inevitable formation of native oxides. The extent of the formation of oxides is dependent upon the details ofthe processing. In the case of GaAs, the native oxides have been identified as Ga,O, and A.s~O~.~*~~Thermodynamically, the arsenic oxide is unstable in the presence of GaAs and the reaction, 2GaAs + As203 +
Ga203 + 4As
leads to the formation of elemental As. In contrast to GaAs, InP oxidizes under ambient conditions by forming InPOd, which is relatively more stable than the native oxides of GaAs.l*ll The native oxides themselves, and the
Passivation
of GaAs and InP
335
selective buildup of the excess group V element at the interface, have been sources of traps at the M-S and I-S interfaces on GaAs and InP. Whether or not any of the proposed models prove to be correct, from the discussion presented in the following sections, it becomes evident that an essential aspect of passivating the GaAs and InP surfaces has been the removal of these native oxides. It is interesting to note that the earlier attempts to passivate the surfaces of GaAs and InP were focused on the formation of stable native oxides in a controlled manner. This was done with a hope of achieving an I-S interface which is analogous to the SiOz/Si system. Although there has been some success in this area (as discussed below), the passivation schemes have essentially relied on careful surface treatments and deposition of heteromorphic insulating overlayers. In the remainder of the chapter we attempt to summarize the prospects of passivation of GaAs and InP using treatments which involve the use of(i) native oxides, (ii) hydrogen and nitrogen, (iii) sulfur, (iv) selenium, (v) silicon, and (vi) epitaxial regrowth.
2.0
NATIVE
OXIDES
The processes used in the fabrication of native oxides themselves have led to serious problems. For example, the group V elements and their oxides are much more volatile and soluble than the group III elements and oxides. As a result, heating InP in vacuum causes P to evaporate and In to accumulate on the surface. If this treatment is excessive, then metallic In droplets will form on the InP surface. Similarly, Ga droplets can form on the GaAs surface. In growing an oxide, other problems arise (discussed below) and thus no thick passivating oxide analogous to SiOz on Si has been found for the III-V compound semiconductors. All types of oxide growths have been investigated.l**l The thermal oxide of GaAs is primarily composed of Ga oxide with metallic As nonuniformly distributed near the interface. This oxide is a poor insulator and the interface contains a high density of traps. Anodization of GaAs produces an oxide that can contain equal proportions of Ga and As oxides and an interface with very little metallic As.[*~] However, this oxide layer absorbs water and decomposes when annealed. Plasma oxides grown at near room temperature are similar to the thermal oxides.l24l In either case, the oxide does not satisfactorily passivate the surface. The water-grown oxide of GaAs is an interesting exception and appears to have the potential for passivating the surface.l25l Unfortunately,
336
Compound Semiconductors
very few investigations of this water process have been reported. It appears that the water method grows both Ga and As oxides, but the water dissolves the As oxide leaving a stable film of Ga203 on the surface without metallic As at the interface.l26l Further work is required to determine the usefulness of this technique. The InP oxides are about the same as their GaAs counterpart. The thermal and plasma oxides yield interfaces containing elemental P, although in this case, the collection of the column V element is due to slow diffusion and not thermodynamic instability as in the case of GaA~.l~~l However, the effect on the oxide and interface properties are the same. The composition of the anodic oxides are more complex and more varied than those of GaAs and are only slightly more suitable for passivation.t2*I As discussed above, the thick oxides do not form a suitable passivating layer for InP and GaAs devices, however, very thin layers are valued as blow-offlayers for MBE and MOCVD epitaxial growth. For this application, the substrate is carefully cleaned and an oxide grown on the surface. Airborne carbon and other contaminants deposit on top of this passivating oxide and are carried away when the oxide is evaporated in the epitaxial growth chamber.l29l The effects of a thin native oxide at the deposited insulator-InP interface has been a topic of much discussion; some report improved interface characteristics and others report interface degradation. The most recent work showed that the composition and preparation of the oxide is very important in forming an interface with a low surface state density. For a good interface, the oxide must be an indium phosphate, e.g., In(PO& that does not contain In203 and P20s. These oxides are thought to create trap states and degrade the electronic characteristics of the interface.l30l131l
3.0
HYDROGEN
AND NITROGEN
The role of hydrogen in passivating defects in both crystalline and amorphous silicon has been well-known for many years. H-Si bonds are stronger than Si-Si bonds, and since the binding energy manifests itself in the bandgap of the semiconductor, the H-terminated silicon surfaces have higher bandgap energies. Therefore, H is also effective in reducing the surface recombination velocity (SRV). In germanium, hydrogen is known to form complexes with shallow donor and acceptor impurities. These versatile and remarkable attributes of hydrogen have been exploited to
Passivation
of GaAs and InP
337
achieve surface or bulk defect passivation of these semiconductors in a variety of different ways. Considering the somewhat universal role of H in neutralizing defects, passivation of defects/impurities in III-V compound semiconductors using hydrogen would appear to be a reasonable expectation, and indeed annealing in Hz or Hz-plasma ambients has led to significant reduction in concentrations of EL2 in GaAs,1321 D-X centers in AlGaA.~,l~~l and energy levels due to Mn in InPl34l and N in GaP.l35j Hydrogen also electrically deactivates shallow donors in GaAs:Si, as first reported by Chevallier et al.136I In addition, H can also neutralize shallow acceptors in GaAs:Zn1371 and InP:Zn. 13*1There have been numerous experiments investigating the role of H at these bulk energy centers and, for details, the readers are referred to a recent reviewI39l and the references therein. Recently, there has been some interest in evaluating the effects of hydrogen on the electrical and structural properties of GaAs and InP surfaces, however, this is at a preliminary stage. Such experiments are particularly difficult because activated H reacts with the surface, not just to etch the native oxides and “clean” the surface of C and other contaminants, but also to induce damage which occurs due to the preferential loss of group V element from the surface. The reactions of atomic H with the native oxides, and their corresponding free-energy changes are the following: AS203
i-
2hH3
(DG = - 530 kcal/mole)
Ga20 + 2H20
(DG = - 142 kcal/mole)
12H +
Ga203 + 4H + In203 + 4H +
3H20 +
In20 + 2H20
(DG = - 138 kcal/mole)
The heats of formation are negative and the reaction by-products are volatile compounds, and therefore, H is effective in removing the oxides and cleaning the surface. However, excessive H-exposure of the surface causes formation of volatile hydrides, and depletes the surface of its group V element, thus causing severe damage to the surface stoichiometry and structure via the following reactions, InP+3H
+
GaAs+
3H +
PH, AsH3
As a result of these reactions, In clusters are formed on the surface of InP, while Ga clusters are left behind on the surface of GaAs. Since the removal of surface native oxides and the formation of plasma-induced damage are
338
Compound Semiconductors
competing reactions, careful and judicious control of the process conditions and in-situ real-time observation of the surface properties during H-exposure are important. A few promising techniques have been proposed which alleviate this problem and allow hydrogenation while maintaining reasonable surface quality. A brief description of these experiments and their results are now discussed. The need to control the reactions of H with the surface of GaAs is primarily motivated by the need to develop an in-situ cleaning technique for MBE-regrowth. The work done in this area has also benefited the researchers interested in passivation because the first step towards achieving passivation of surface defects is indeed the removal of elemental As, the native oxides, and the contaminants on the surface. Recently, ECR hydrogen plasmas have been proven to be effective in cleaning GaAs and providing a well-ordered surface at relatively low temperatures.l40l ECR plasmas are particularly suitable for such applications because of the low ion energies; typically - 25 eV. Consistent with the thermodynamic considerations, in-situ XPS analysis suggests that As-oxides are removed first, followed by the removal of Ga-oxides. Following the surface treatment, in-situ studies exhibit (1 x 1) LEED pattern indicating that the clean surface is also atomically well-ordered.1411 Direct evidence of the role of plasma-activated H2 in passivating the surface and near-surface defects in GaAs is obtained in the experiments of Gottscho et al.l42ll43l In their experiments, the GaAs surfaces were exposed to a hydrogen plasma under high pressure (and correspondingly low ion energies) and low temperature conditions in a rf capacitively-coupled parallel plate reactor. The plasma-surface interaction was monitored by observing the changes in photoluminescence signal, emitted by the sample during the plasma treatments. PL measurements, being highly sensitive to the density of defects on the surface, are especially important for such experiments. The room temperature PL intensity for treatments under different pressure conditions are shown in Fig. 3. At low pressure, irreversible damage occurs to the surface resulting in low PL yield. At higher pressure, the PL intensity is observed to increase with time. The initial decrease, and then the subsequent increase in PL intensity when the plasma is turned off, are attributed to the charging and discharging of the surface, respectively. XPS investigation of the treated surfaces, as shown in Fig. 4, shows removal of As203 as a result of the plasma treatment. These authors have suggested that the removal of excess As and its oxide leads to reduced levels of As antisite defects, and hence, an increase in PL intensity.
Passivation
I
0.00
of GaAs and InP
I
339
I
I
~~~~----z
Plasma off 1.0 Plasma on
0.5 -J . 0.0 0
I 2
I 6
I 4 Time (min)
I 8
Figure 3. GaAs PL intensity vs. time for (a) 0.2 torr and (b) 4 torr plasma treatments. Other plasma parameters: 13 MHz, 20 W, 20°C, 2 seem Hz. Note the difference in scales between (a) and (a). (after Ref. 42.)
before plasma treatent .*‘.
8-
:
z
;
I
I
I 10 -
.,
4
;‘w\ . , .
:--,; ‘-
lOz
9
8-
I
I
I
I
after plasma treatment
Y G; 4-
‘%
I
;‘: * *
. .. .
-
6 l;‘+&.+,
. * *#a .
I* :.
2I
0 1340
1335
(b)
. . * :
w++&.$~
‘I
-
:* v :,
”
20
(a)
I
I
1330
1325
C. ‘*.‘S . *“u 1320
Binding Energy (eV)
Figure 4. As (2p,,) photoelectron spectrum (a) prior to and (b) after plasma treatment. In both cases, the GaAs wafers are preprocessed by dipping in concentrated HF for 30 s. Plasma conditions are the same as reported in Fig. 3(b) (after Ref. 42).
340
Compound Semiconductors
Schottky diodes, fabricated following the H2 plasma treatment of GaAs surfaces, have also been investigated.14*l The barrier height of these diodes compared well with the barrier heights of devices obtained on UHVSchottky diodes on n-GaAs, which were fabricated cleaved samples. following an in-situ rf hydrogen plasma treatment, were also reported by Paccagnella and co-workers.[441 Diodes with an ideality factor as low as 1.Ol were achieved when the plasma treatment was carried out in the temperature range of 160 to 240°C. It was suggested that improvements in the ideal&y factor and the barrier height of the diodes were due to passivation of donor impurities, defects in the depletion region, and perhaps also due to the defects at the metal/GaAs interface. In the experiments of Omeljanovsky et al.,l45l atomic hydrogen was used to treat the prefabricated Au-GaAs Schottky diodes. Following the treatment, a decrease of approximately an order of magnitude in the reverse saturation current was observed. Recently, Callegari et al. 1461reported fabrication of SiO#i/GaAs MIS capacitors after a H-plasma clean of the GaAs surface. The C-V characteristics of the capacitors indicate good passivation of the states at the interface. These results are discussed in detail in Sec. 6.0. Surface “cleaning” using hydrogen, followed by treatments in a nitrogen plasma, as discussed by Capasso et al.,l47l has also led to improvements in the electrical properties of GaAs surfaces and interfaces. In these experiments, the motivation to use N has been to fill the As vacancies and help form a thin passivating layer of GaN. Passivation of the surface is realized because GaN has a higher bandgap than the underlying GaAs, which is analogous to the H passivation of Si and the formation of Si-IYSi heterojunction interfaces. This treatment was found to improve the sidegating on metal-semiconductor field effect transistors (MESFETs) in GaAs by an order of magnitude. 14*1Multipolar plasma in Hz, followed by a treatment in a N2 plasma, has been also used to modify the surfaces of GaInAs. An inversion layer was demonstrated on GaInAs using an in-situ SiN film deposited following the treatment. 14gl Encouraging results have also been obtained for Al/Ga02/n-GaAs MIS devices fabricated by Callegari et al.1501 These authors suggested that Terman analysis of the high-frequency capacitance-voltage data indicated an interface defect density in the range of 10” cmm2eV1. More recently, passivation of 2DEG AlGaAs/GaAs heterojunction bipolar transistors have been achieved using electron cyclotron resonance (ECR) plasmas in H2 and N2 .1511 The authors suggested that a thermally stable nitride layer was grown during the 10 min, 250°C treatment in a N2 plasma which passivates the surface defect states at the
Passivation
of GaAs and InP
341
mesa edges of the transistor. As shown in Fig. 5, in the low current regime, the base current is reduced by two orders of magnitude. The maximum current gain of the transistor increased from -720 to -1000.
10 -6 10-7'
0.7
I
I
0.8
0.9
1
1.0
I
I
I
1.1 1.2 1.3
veb(v)
Figure 5. Gummel plot of the HBT before (dashed line) and after (solid line) the ECR H and N plasma passivation (after Ref. 51).
The hydrogen plasma treatment of the InP surface has been somewhat more difficult. This is because of the formation of PH3 and the resulting disruption of the surface stoichiometry, due to the loss of P. The techniques that have been recently suggested include hydrogenation through a thin layer of SiN,1521exposure to low energy H ions,l53l hydrogen plasma with P overpressure,l54l and PH3 plasma.1551-[571 Maintaining a partial pressure of P in the chamber during processing has been particularly beneficial for the H-treatment of the free InP surface. Following hydrogen or phosphine plasma exposures, Schottky diodes have also fabricated on htP.15611571An enhancement in the Schottky barrier height up to -0.7 eV is observed as a result of the PH3-plasma treatment. In another study, a two to three times reduction in the surface state defect density at the Au/InP interface is observed as a result of a hydrogen plasma treatment.l45l It has been suggested that the damage caused by the H-treatment are self-healed by passivation of these defects by hydrogen itself. Viktorovitch et a1.[5311581 reported PL studies and C-V characteristic of MIS structures fabricated on
342
Compound Semiconductors
InP following the H treatment. Their experiments indicate that while the PL signal increases dramatically, the C-V data is flat, indicating strong pinning of the Fermi-level at the interface. It has been suggested that this apparently contradictory result is due to the different types of defects which are responsible for the non-radiative recombination and the Fermi-level pinning on InP surfaces. In view of the above results, the fundamental role of hydrogen in passivating GaAs and InP may be considered as both indirect and direct. It is indirect because it facilitates the removal of native oxides and excess As which are believed to generate states in the bandgap. It is direct because it is known to form neutral complexes with impurities in the bulk. Whether or not H forms complexes and passivates the defects on the surface is, however, not yet clear. Although there has been some evidence of formation of hydrides on the surfaces of GaAs following H treatments, whether these hydrides have any effect on passivating the electrical activity of surface defects is yet to be studied. Nevertheless, it has become evident that H can be very effective in passivating the surface defects by virtue of in-situ cleaning and providing an oxide-free surface for further processing. From the various experiments, it has also become apparent that ion energies in a hydrogen plasma have to be suitably tailored, so that damage to the surface during processing is minimized.
4.0
SULFUR
In 1964, Davis[5gl discovered that rinsing the (111) InSb in dilute Na2S solutions led to a considerable reduction in the surface state density. Furthermore, in late 1970s and early 198Os, there were also some studies involving adsorption of H2S on GaA~l~~l-1~~1 and InP surfaces.1631[64J The experiments indicated adsorption of H2S on the surface was further enhanced by elevated temperatures, induced by a high concentration of surface defects, and by the presence of hot filaments and electron beams. The reaction on the surface resulted in an exchange between the As and the S atoms. Massies et al.16*l reported dramatic changes in the electrical properties of Al/GaAs diodes due to the presence of an intervening adsorbed layer of sulfur which causes the Schottky junction to become more ohmic in nature. Montgomery et al. la31also observed significant changes in Al/W and Ag/InP Schottky diodes. The effects of sulfur in modifying the
Passivation of GaAs and InP
343
properties of an InP surface may be also be found in papers including those of Post et a1.l65land Klopfenstein et al.1661 Although some of these earlier studies had hints of the role of S in passivating surface defects, it was not until 1987 when the use of this element became a topic of significant interest. This was triggered by the results published by Yablonovitch, Sandroff and co-workers.[671[681 A dramatic enhancement in the performance of AlGaAs/GaAs HBT was achieved using sodium sulfide so1utions.16*j As a result of this sulfide treatment, the common-emitter gain of the transistors increased 60-fold; from an initial value of - 30 to about 2000. The process was found to be reversible, with the gain returning back to 30 after a brief 1:8:500 HzS04:Hz02:Hz0 etch. Following the demonstration of this remarkable enhancement in HBT performance, various research groups have successfully passivated a variety of other devices. The use of sodium sulfide was prevalent in the initial experiments; however, the focus was later shifted to other sulfide solutions, primarily to avoid potential Na contamination. Solutions containing (NH&&, P2S5 and AS& have proven to be effective in passivating the IIIV surfaces. The details of the processes and chemicals are as varied as there are number of laboratories involved in the area. Due to the lack of understanding of the detailed chemistry, we refrain from making distinctions between the various proposed processes and refer to the treated semiconductor as being suZJide-treated,or S-treated. Recently, there has also been some interest in the use of H2S for passivation; one of the major potential advantages in the use of H2S over “wet” solutions is that such a process may provide a contaminant-free source of sulfur and help facilitate uniform and reproducible S-coverage of the surface. A variety of different devices including p-n junction diodes, Schottky junction diodes, HBTs, lasers, MIS capacitors, and MISFETs exhibit superior electrical characteristics as a result of the S-treatment. The mesa edges of GaAs p-n homojunctions, passivated with sulfide solutions, exhibit a reduction in the parasitic 2kT perimeter recombination current by a factor of - 3.2.16gl Passivation of p-n junction solar cells, using Na2S + RuC& was reported by Mauk and co-workers.l70l The improvement in the spectra1 response at 400 nm increased by approximately 450 %. AS& treatments of GaAs p-n junctions1711 and AlGaAs/GaAs HBTs[~~I have shown large reductions in the surface recombination currents. Similarly, Na2S173j and (NH,J2SX1741treatments have resulted in significant improvements in AlGaAs/GaAs HBTs, and P2S5/(NH4)& solutions have been
344
Compound Semiconductors
used to passivate AlGaAs/InGaAs/GaAs heteroemitter bipolar transistors.1751 In another study, following the surface treatment with (NH&Sx of the HBT, an overlayer of silicon nitride was deposited using the ECRPECVD technique. I761 The authors observed 78% reduction in the surface recombination current density, and the base current noise at 680 MHz reduced by 75%, from a value of 10.3 PA/HZ to 2.7 PA/HZ. The effects of sulfide treatments in reducing the defect density at the M-S interface has been equally impressive. As a result of passivation of the interfacial defects, the Schottky barrier heights, which are practically invariant in unpassivated samples, exhibit a relatively strong dependence on the work function of the metal. Carpenter et al.l77l indicated reduced Fermi level pinning at the interfaces of Al/GaAs and Au/GaAs Schottky diodes. Consistent with the changes in the surface potential barrier height, the reverse leakage current decreased and increased in the Au/GaAs and Al/ GaAs diodes, respectively. Treatments with P& also indicate similar trends.l78l Enhancement in the Schottky barrier height has also been observed in InGaAs which were treated with P,S&NH,),S,-based sulfide solutions.l7gl The dependence of barrier heights on the In, Al, and Au work functions in Schottky diodes fabricated on GaAs, InP, and AlGaAs, and GaP are shown in Fig. 6.1801
-S-treated
2
0.6
0.2
4.0
5.0
6.0
O,(V) (b)
Figure 6. Dependence of the Schottky barrier height on the work function of deposited metal. Schottky barriers were fabricated on the n-type (100) surfaces of various l&V compounds: (a) Gap, GaAs and InP, and (b) GaAs, AI,,,Ga,,sAs and Al,~,Ga,,,& (after Ref. SO).
Passivation
of GaAs and InP
345
Among all the devices, MIS capacitors and MISFETs are perhaps the most challenging devices for testing any passivation scheme. These devices are profoundly infhrenced by the defects at the insulator/semiconductor interface. S-treatments, prior to the dielectric deposition, are effective in producing relatively superior quality interfaces and, hence, better MIS and MISFET devices. The most notable device in this category has been fabricated in InP by Lile and co-workers.l81Il82l The surface of InP was prepared using (NI-IJ2S, polysulfide solutions, which left a crust of elemental sulfur on the samples after the treatment. The excess sulfur from the crust was then sublimated in vacuum, immediately followed by The Si02 deposition at - 250°C in an indirect plasma CVD reactor. samples were then annealed at about 350” for 1 hr in a H2 + N2 gas ambient. The quasi-static and high frequency C-V characteristics of a MIS capacitor, prepared in such a way, are shown in Fig. 7.1811t831The figure also shows the surface state density, Nss, as a function of the surface potential. The surface state density estimated using Terman analysis ranges from lOlo to low 10” cmv2 eV-‘, with the lowest density occurring at a surface potential of about - 0.4 V. The enhancement mode MISFET, fabricated in p-type InP using a similar technique, indicated drain current drifts of less than 5% over a 12 hour testing period.
OLI-6
”
-4
n
’
VOCTAGE (b)
”
0
-2
’
0
0
2
IVCCTS)
m~
WJd -1 ’
a
’
-0.6
SURFACE
’
’
’
-0.2
POTENTIAL
’
0.2
(eV)
Figure 7. (a) High frequency (1 MHz) and quasi-static C-V behavior of sulfurized n-type InP with IPCVD SiO, as a dielectric. (b) Surface state density of sulfurized n-type InP (after Ref. 81).
346
Compound Semiconductors
Passivation of the SiN/InP interface using sulfur is reported by Malhotra and co-workers.[841 Such an interface is particularly important because a high quality SIN overlayer may function as a gate dielectric, as a passivation layer, and as an encapsulant (something not readily achievable with SiO;! because of its higher porosity) in electronic and optoelectronic integrated circuits. Following the P2SS/(NH4)2Sx treatment of the InP surface, a film of SIN, was deposited at -200°C under soft plasma conditions using the ECR-PECVD technique. A significant improvement, in both quasi-static and high frequency characteristics, is observed as a result of the sulfide-treatment. In another experiment,[851 H2S was used for treating the InP surface prior to the SIN deposition. Annealing the devices at -500°C in N2 was found to improve the electrical properties of the devices. The capacitance-voltage characteristic of the S-passivated and H$3-passivated Al/SiN/InP capacitors are shown in Fig. 8. The minimum defect density, estimated using Terman’s analysis, for these samples, is in the low 10” cm-* eV-’ range. The samples treated with H2S were found to be considerably more uniform and reproducible compared to the P2S5/ (NH4)2Sx treated samples. This is quite an important result because the use of these techniques, beyond the research laboratories, will eventually depend upon these criteria. 1.25
QUASI-STATIC
0.75
0 3
0.5
0.25
-
S-PASSIVATED
- - -
H2S-PASSIVATE[
0 0
-5
-10
5
GATE VOLTAGE
Figure 8. High frequency (1 MHz) passivated Al/SiN.JInP
and quasi-static C-V
(V) characteristics of S- and H,S-
capacitors. The silicon nitride deposition, on the sulfur-treated
surfaces, was done at -2OO’C
using ECR-PECVD
technique.
Passivation
of GaAs and InP
347
In the case of GaAs MIS, unfortunately, the success has been very limited. On n-type (100) GaAs, MIS devices were fabricated on a S-treated surface using photo-enhanced CVD silicon oxide.1861-1881A considerable amount of hysteresis was observed in the high frequency C-V data. In another experiment, the GaAs surface was treated with a H2S plasma at room temperature, followed by deposition of silicon oxide at 300°C using the rfPECVD technique. 18gl Although the high frequency C-V characteristics exhibit significant improvements, without the quasi-static C-V data, an unambiguous determination of whether inversion/accumulation truly occurs in these devices may not be established.l1gl Our preliminary result@“‘] on S-treated SiN/GaAs interfaces, where the sulfide-treatments were carried out in a manner similar to what has been reported in Ref. 84, also suggest significant improvements in the electrical properties of SiN/GaAs interfaces. At the present stage, however, such dielectric/GaAs interfaces are far from being suitable for MISFET-type applications. Nevertheless, they may perhaps become useful in passivating and encapsulating GaAs devices and circuits. The improvements in the performance of a broad range of devices are certainly testimonials for the beneficial role of S-treatments in passivating GaAs and InP surfaces. It appears that they may help to reduce the density of defects at the I-S and M-S interfaces. Although this is an excellent attribute, there is one major problem with the technique: upon exposure to air, the surface degrades with time and for long exposures the passivating aspects of sulfur are practically lost. This has been attributed to the increase in oxygen levels on the surface and the formation of native oxides as a result of exposure to air. lg111g21 It is evident that a considerable amount of work is yet to be done in order to improve the longevity of sulfurpassivated devices. One of the techniques may be to coat the S-treated device with an appropriate overlayer, which is impermeable to oxygen; As2S3 has been suggested as one suitable overlayer.171117211g31 The devices with an encapsulating layer of SIN or SiO may also have longer life, however, these issues have yet to be studied. Since the demonstration of the dramatic effects of sulfide-treatments on III-V based devices, a variety of surface-sensitive techniques including the steady state photoluminescence (PL), the time resolved PL, the transient conductivity, the deep level transient spectroscopy (DLTS), and the laser Raman spectroscopy techniques, have been used to help understand the fundamental changes on the semiconductor surface. Skromme and coworkerslg41 reported steady state PL measurements, at room temperature
348
Compound Semiconductors
and at 1.8 K, on S-treated GaAs samples. The change in room-temperature PL intensity due to the various surface treatments is shown in Fig. 9. A significant increase in the PL intensity is observed upon application of Na$, which then returns to its original value after an etch step, or decreases to a lower level after a rinse in deionized water. The data also exhibits a decrease in PL intensity with time because of the degradation of the surface due to air exposure. The low-temperature PL intensity profiles on n-type VPE-grown and p-type MBE-grown GaAs indicate disappearance of the notches in the longitudinal fiee-exciton peaks, which are believed to be due to the high surface recombination rate. Holloway and coworkers[g21 used PL measurements on bulk n-type GaAs to characterize the extent of passivation using treatments involving a variety of sulfide solutions. The GaAs surfaces were treated with different solutions containing varying amounts of S, P2Ss, and (NHJ2S. The samples that had a relatively high PL intensity and exhibited the slowest rate of degradation when exposed to air were the ones that were treated with a mixture of P2Ss/ S/(NH4)2S (0.2g/O. lg/ml). Using a similar composition of sulfide solution, the PL signal from a treated InP surface was measured in-situ in an ECRPECVD system. ig41Figure 10 shows the integrated PL intensity at different stages of processing. Following the silicon nitride deposition, there is a substantial increase in the PL intensity for the S-treated samples. The PL signal is approximately ten times as large as for the samples which did not receive the S-treatment.
n-TYPE
AlGaAs ETCHED Na2S APPLED CAP
RNSED N D.I.
GaAs
ETCHED Na2 S REAPPLIED
18hrs LATER
Figure 9. Relative PL intensities at 300 K for four different GaAs samples as a function of surface treatment. Intensities are normalized to the etched condition for each sample; the lower two curves are displaced down one decade for clarity (after Ref. 94).
Passivation
of GaAs and InP
349
PL WTENSITY (27OC) 2.0 c 9 E
5
S-PASSIVATED 1.5-
0.5-
ti UNPASSIVATED
Figure 10. Relative integrated photoluminescence intensity of InP at different stages of processing during the fabrication of SiN/InP
capacitors (after Ref. 84).
The PL measurements have been used extensively to characterize both S-treated GaAs and InP surfaces. Although the technique is quite straightforward, the interpretation of the results may be fairly complex. In some cases, the PL signal decreases immediately following the S-treatment. This has been attributed to scattering of incident light, due to the polycrystalline sulfide layer on the surface. It perhaps may also be due to the details of the processing and the formation and thickness of a sulfur crust on the surface of the sample. The measurement of the surface recombination velocity (SRV) on sulfur-treated GaAs surfaces was reported by Yablonovitch using transient conductivity measurements. 16’1 In this technique, the recombination of photogenerated carriers is monitored by the decay in conductivity of the sample. The SRV of electrons in samples that were treated with Na2S were found to be -1000 cm/s. This value is approximately three orders of magnitude smaller than the SRV of carriers in an unpassivated surface of GaAs. Mauk and co-workers170l also estimated SRV to be -1000 in their pn junction solar cells. Using the time-resolved PL measurements,lg51 which is believed to provide a relatively more accurate estimation of SRV, a value of 7 x lo4 cm/s was estimated. The position of the surface Fermi level, following the S-treatment, has been measured using a variety of different techniques. Besser et a1.1g6l1g7l used conductivity measurements of two adjacent MESFETs; one of the FETs did not have the gate metal and therefore was susceptible to
350
Compound Semiconductors
changes on the semiconductor surface. For the Na2S-treated and untreated (oxidized) samples, the surface Fermi level was found to be 0.6 eV and 0.8 to 0.85 eV above the VBM, respectively. This suggested that the Fermi level moves down in the bandgap of the semiconductor, resulting in increased band bending. DLTS measurements of Liu et a1.,lg81on untreated GaAs samples that were over-coated with reactively sputter-deposited silicon nitride films, suggest defects located at 0.58 and 1.15 eV below the conduction band edge. However, following sulfide passivation, the density of states at 0.58 eV reduced considerably when compared to the states at 1.15 eV. This result was used to suggest that the Fermi level does not get unpinned as a result of S-treatment, but that it gets repinned at an energy level closer to EC - 1.15 eV. Other studies, including those of Hasegawa et al,lWl Spindt et al,tiool and Koenders et al.,l101l have also indicated movement of the Fermi level closer to the valence band edge. An increase in band bending, accompanied with an increase in PL signal, reduction in the surface defect density, and the observed reduction in surface recombination rate are apparently contradictory results, and are addressed later in this section.. The surface potential barrier height on the treated samples have also been measured using laser Raman spectroscopy. The use of Raman spectroscopy for measurements of band bending on the surface has been well-known.11021-11041 The technique utilizes the relative changes in the intensity of the bulk plasma-coupled phonon mode (L-) and the uncoupled LO phonons excited in the surface depletion region layer. It is important that the carrier concentration of the semiconductor be relatively high and that the power density of the illuminating laser be kept low in order to avoid effects of screening by photogenerated carriers.1105l The surface barrier height in Na2S-treated GaAs samples is found to be -0.48 eV,11061and the samples treated with (NH4)2Shave a barrier height of -0.1 eV.llo71 Chen et al.11o8lreported surface barrier heights in the range of 0.45 eV to 0.48 eV for samples that were treated with (NH4)2S-and P2S5-based sulfide solutions. Similar measurements were also carried out on heavily doped n-type (100) InP samples,11081110g1 and the potential barrier in the range of 0.2 to 0.3 eV have been observed. It is interesting to note that, since the surface potential of untreated (oxidized) GaAs is -0.78 eV and that of InP is -0.48 eV, the values obtained using Raman scattering suggest that the bands A comparison become relatively flatter as a result of the sulfide-treatment. of these results with those obtained using dark conductivity measurements of an ungated FETs is not straightforward because of the fact that Raman
Passivation
of GaAs and InP
351
scattering experiments are done under illumination, and therefore, are perhaps susceptible to some light-induced flattening of the bands. The nature of the surface chemical composition of the sulfide- and H,S-treated GaAs has been studied extensively by a number of researchers. Using the results of XPS measurements on Na2S and (NH&S, treated GaAs, Sandroff et al.t1071suggest two chemically shifted peaks in the As 3d and 2p lines. They indicated that this suggests two distinct As-S phases. The XPS data of Carpenter and co-workerstllOltllll indicated a S-As peak shifted -1.7 eV, and a small shift in the Ga 2p line in (NH&S,-treated GaAs surfaces. Spindt et. a1.ti121 observed large S-As and S-Ga peaks, shifted -1.6 and -0.55 eV, respectively, using high resolution synchrotron radiation photoemission spectroscopy. Figure 11 shows the Ga 3d and As 3d spectrum of the (NI-14)2Sx sulfide-treated sample as a function of temperature. Heating at 200°C for 15 min virtually reduces the As-S peak to near zero, whereas there is no change in the S-Ga peak. Temperaturedependent changes on the sulfur-passivated GaAs (111) and (100) surfaces have also been reported by Scimeca et al.,t1131which are consistent with the above results. XPS investigation of GaAs surfaces, which were prepared using different etch processes prior to sulfidation, were also carried out by Lunt and co-workers.tg51 The sulfurization of the surface was found to be practically independent of the etchant used. XPS investigations have also been carried out on H2S-treated GaAs Massies and co-worker@] observed an exchange reaction surfaces. between As and S atoms at 700 K on samples that were exposed to unactivated H2S. Ranke and co-workersl’ 141-11 161used Auger and XPS with synchrotron radiation to investigate H2S interactions with different crystal faces of GaAs in the temperature range of 123 to 450°C. Both MBE and sputter-annealed surfaces were investigated. Tiedjell 171t1l*l prepared the sample by heating in vacuum to a temperature hot enough to desorb the surface oxides. Sulfur was adsorbed on these surfaces at room temperature from hot filament-activated H2S. This process sequence resulted in a significant amount of S-Ga bonding and a much less S-As bonding. Heating this surface to 400°C for 3 min removed the S-As bonding but the S-Ga remained, probably as a Ga sulfide. Wilmsen and co-workersl1igll120l treated GaAs surfaces with the sulfide solutions and exposed the surface to H2S in the temperature range of 30-350°C. The samples were prepared using various chemical etchants, and the As/Ga ratio was varied from 0.6 to 6.0. XPS spectra revealed S-As bonding at low temperatures and S-Ga at It was suggested that S bonds to whichever atom is high temperature.
352
Compound Semiconductors
present on the surface, as a result of the H2S exposure solution treatments.
and the sulfide-
(4
Binding Energy
(eV)
(b) -22
-21
-20
-18
-17
Binding Energy
-19
(eV)
-16
-15
(4
-44
-43
-42
-41
-40
Binding Energy
-39
-38
(eV)
Figure 11. (a) As 3d spectrum of the sulfide-treated sample. The upper curve shows the data points and the total computer tit. The lower curves are the reacted As-S and the bulk GaAs component of the fit. (b) Ga 3d spectra of the sulfide-treated sample. The lower curves are the reacted Ga-S and bulk GaAs components of the computer fit. (c) As 3d spectra taken after annealing (after Ref. 112).
Passivation
of GaAs and InP
353
From the extensive amount of data obtained under varying process conditions, it is now evident that both S-Ga and S-As bonds are formed on the surface of GaAs. Using H2S as a source of sulfur, the extent of formation of these bonds is sensitive to the microscopic structure and stoichiometry of the surface prior to HZS exposure. However, for samples that are treated in sulfide solutions, the chemistry is somewhat different. As a result of the chemical treatment, it is suggested that excess As, arsenic oxide and gallium oxides are removed, and S bonds to the surface forming S-GaAs compounds. In most cases, S-As bonding is observed with peak shifts in the As 3d and 2p spectra, which correspond to the formation of a single phase of As-S compound. With the use of a synchrotron radiation source, S-Ga bonding is also observed which may not have been seen without its high resolution capabilities. With increasing temperature, the predominant chemical composition on the surface is that due to S-Ga bonds. A pertinent question regarding sulfur passivation which must now be addressed is, does sulfur electronically passivate the surface defects and how? Furthermore, what is the nature and origin of these electronic defect states on the surface? It is perhaps the answer to such questions which will elevate the technology of passivation from empiricism to science. In an effort to address these issues, the approach, for the most part, has been focused on discovering the nature of compounds and their chemical compositions on the semiconductor surface. Passivation of the electronic defects on GaAs surfaces have been attributed to S-Aslio71 and S-Gall*ll bonds. Ohn01~*~1has carried out first principles psuedo-potential calculations and the results indicate that S-Ga bonds are responsible for the reduction in the surface state density on Ga4.s surfaces. Spindt and Spicerl’**l suggest that the alkaline sulfide solutions act as agents which remove the native GaAs oxides and terminate the surface with a layer of S in a non-disruptive manner. In such a model, passivation of the surface is not dependent upon the detailed surface structure or the composition of the overlying layer, just as long as the clean GaAs surface is protected from oxidation. Since the heats of formation of oxides are much larger than the sulfides, these surfaces will eventually degrade when exposed to oxygen. Lunt and co-workerslg5l1123l have argued that complete removal of excess As or the formation of As-S is not necessarily required to passivate the electronic defect states at the surface. The basis of this argument stems from their experiments using sulfides and a large class of organic thiols (R-
354
Compound Semiconductors
SH, where R = -CH,CH,SH or -C,H,Cl). As a result of the thiol treatment, the As 3d spectra were unchanged, and no ascribable As-S peak shifts were observed. The results, for samples that were As-rich, suggested that excess As, which was formed on the surface due to the etching process, was not removed by immersion into the thiol solution. The time resolved PL measurements on “near-stoichiometric” surfaces treated with 1 M 4-Clthiophenol in Ccl4 yielded a surface recombination velocity of 7 x lo4 cm/ s, which is identical to the one obtained for Na$-passivated samples. As a result of a comprehensive study, the authors of this work concluded the following: (i) the formation of As-S is not responsible for lowering the surface recombination at the surfaces, (ii) complete removal of excess As is not necessary to achieve passivation of the surface, and (iii) there exists a correlation between the electron donating ability of a species and the improvement in PL. The experimental observations of apparently contradictory results such as the reduction in SRV, enhancement in the PL signal accompanied with the increase in band bending due to the S-treatments, have been the focus for developing fundamental models.l124l Spindt and Spicert1221 have used the overall framework of the AUDM to postulate the nature of the electronic defects. It is suggested that the defects on GaAs are double donors (-0.65 eV and -0.9 eV from CBM) and double acceptors (-1.1 eV from CBM). The origin of these states is due to the As and Ga antisites, respectively. As a result of the S-treatment, the excess As may be removed resulting in the reduction of the density of the donor states, Nd. This reduces the SRV. Due to the accompanied lowering of the Nd/Na, the Fermi level moves towards the acceptor states, resulting in enhanced band bending, and positive charging of the donor states by +1 or +2. Furthermore, this lowers the hole capture cross-section of the donor states, making recombination via these states even less likely. Therefore, it is suggested that the PL intensity will increase by a factor even greater than what might be anticipated from the reduction in the surface state density alone. The explanation proposed by Hasegawa is based on the DIGS model.l125l Using a computer simulation which includes the necessary phenomenological equations, their results suggest that the reduction in the surface state density cannot explain the experimental observations. They propose that a negative fixed charge is formed, as a result of the Na2Streatments, on the surface either due to the formation of non-stoichiometric oxide or deposition of ionic species.
Passivation
of GaAs and InP
355
It is evident that the nature of the sulfide-treatment and the electronic defects on GaAs is fairly complex. For the most part, it is believed that removal of excess As and the native oxides is crucial for passivation. However, in light of the observations of Lunt and co-workers,l95ll123l where complete removal of As was not found to be necessary, this hypothesis may have to be carefully evaluated. In addition, it appears that there is sufficient evidence, especially due to the noticeable improvements in MIS capacitors and superior Schottky barrier versus metal work function dependence, to suggest that the S-treatments indeed reduce the surface defect density on GaAs. Although there have been extensive studies on the properties of GaAs surfaces, relatively little is known about the effects of S-treatments on InP. Analogous to what occurs on GaAs surfaces, the reaction between InP and H,S/H2 at elevated temperatures results in a gradual loss of P which is thought to be replaced with S.11261 Wilmsen and co-workersl127l have studied the surfaces of InP that were passivated using (NHJ2S sulfide treatments. These samples were heated up to 250°C in N2 and, in some cases, a layer of Si02 was deposited in an IPCVD system (this is the same technique that was used in Ref. 81 to fabricate Al/Si02/InP MIS capacitors). Auger/x-ray photoelectron spectroscopy investigation suggested the formation of In-S bonds at the interface. Tao et al.112*lhave also performed XPS measurements on S-treated InP, and the results are shown in Fig. 12. Their S 2p spectra can be fitted, using the parameters of a h2S3 standard sample, and the P 2p core-level of S-passivated sample is identical to that of the vacuum-cleaved InP, suggesting no chemical bonding between P and S. Using LEED, the authors reported a (1 x 1) structure for the passivated surface. Sundararaman and co-workersl129l studied S-treatment of InP surfaces in the temperature range of 150-3OO”C, using the angle-resolved x-ray photoelectron spectroscopy. They reported formation of -30 A thick b12S3 and PZOS. Recently, Nelson et al.11301have reported soft x-ray photoemission studies of H2S exposed (100) p-type InP using a synchrotron radiation source. Their results suggest that the top layer of the substrate converts to n-type (S being a donor in InP), thus forming a homojunction; the band bending at this junction is estimated to be -0.6 eV. Initially, sulfur bonds to both In and P, however, after long exposures a polymeric sulfur overlayer is formed.
356
Compound Semiconductors
-
cleaved S-passivated
-
-136
-134
-132
-130
-128
-
6
Binding Energy (eV)
(b)
-170
-167
-164
-161
-158
Binding Energy (eV)
Figure 12. (a) P 2p care level emission spectra from S-passivated and vacuum-cleaved (100) InP samples. (b) S 2p core level emission spectra of the S-passivated InP samples. The curve-fit to a single doublet is shown (atIer Ref. 128).
The fundamental mechanism of S-passivation of InP surfaces has also been addressed by several researchers. Wilmsen and co-workers11271 suggested that S fills the phosphorous vacancies and replaces the surface P with sulfur. It was suggested that an In2S3-InP heterojunction structure may be formed as a result of the S-treatment. The results of PL measurements have been interpreted to suggest that the Vp and phosphorous vacancy-related complexes are reduced as a result of the S-treatments.l12gl Lu et al.llsll have suggested that the adsorbed S atoms’ electronic conflguration is sp3 hybrid, with two of the electrons forming bridge-bonds with In atoms in the [Ol l] azimuth as illustrated in Fig. 13. The proposed arrangement of S leaves the passivated (1 x 1) surface with no dangling bonds.
Passivation
of GaAs and InP
f
357
[IO01
Figure 13. Structure of the S-passivated InP (100)-(1x1) surface, viewed in the [O,-l,l] direction. The atomic positions of In and P are assumed to be the same as in the bulk structure (Ref. 131).
5.0
SELENIUM
As discussed in the previous section, one of the problems with sulfide-treated surfaces is the rapid degradation of the passivation upon exposure to air. Sandroff et a1.l132lreported the use of selenium treatment of GaAs for superior stability against oxidation, and hence, degradation, of the surface. It was demonstrated that chemisorbed Se causes significant enhancement in the PL signal from the GaAs surface. The Raman scattering measurements suggest that the band bending at the Se-treated surfaces is only -0.1 eV. It is also suggested that the As-Se bonds are responsible for the improvements in the electronic properties of the surface. In another recent study,l133l where the ex-situ Se treatment was used for GaAs and AlGaAs MBE-regrowth, it is suggested that the GaAs surface is terminated with chemically stable Se/O phases. It is also interesting to note that a chemical treatment reported by Nelson et a1.l134l in 1979 reduced the surface recombination velocity on n-GaAs from 5 x lo5 to 3.5 x lo3 cm/s; the GaAs samples were immersed in K2Se + KOH solutions. There have also been some studies of I-S interfaces, where the surfaces were treated with Se prior to the deposition of the dielectric. Kikawa et a1.l135lstudied the Si02/GaAs interface, where the GaAs surface
358
Compound Semiconductors
was exposed to a flux of elemental Se followed by the photochemical vapor deposition of the SiOz. The authors reported a low density of interfacial states and negligible frequency dispersion in the C-V data. The MIS devices were stable at an anneal temperature of 400°C.
6.0
SILICON
Recently, an interesting approach whereby a few monolayers of Si were used as an intervening layer between M-S and I-S interfaces has been used for passivating the energy states at the GaAs surface.[461[1361-[13gl Unpinning of the Fermi level has been achieved using the technique, and the method also shows great promise for extraordinarily good passivation of the GaAs surface. In the work reported by Tiwari et al.,l136l good C-V characteristics of the SiOJGaAs MIS structure were obtained. MIS capacitors were fabricated on both n-type and p-type GaAs substrates. The approach used by these authors was to first grow an MBE layer of GaAs followed by in-situ deposition of a few monolayers of Si. These structures were then removed from the growth chamber and transported to a PECVD system for the deposition of a Si02 layer at -270°C. During the dielectric deposition, it was suggested that the intervening Si layer converts, at least partly, into SiOz, resulting in a relatively defect-free SiOz/GaAs interface. These devices are also capable of withstanding anneal temperatures of 650°C. Mui et al.l138ll13glalso fabricated Si3N4/Si/GaAs MIS capacitors by first depositing a 10 A Si layer, followed by in-situ deposition of 300-400 A of Si3N4 using the ECR-PECVD technique. The use of Si3N, instead of SiOz is recommended in order to keep the processes free of oxygen. The MBE-grown n-type (100) GaAs sample was also not exposed to ambient atmosphere during the steps of I-S fabrication. As shown in Fig. 14, excellent quasi-static and high frequency C-V characteristics were obtained using the technique. The quasi-static C-V characteristics exhibit the lowest dip ever observed in a GaAs-based MIS device. The interface state density, evaluated using the conductance technique, indicates a minimum trap density of 10” crnm2eV-l in the lower half of the energy bandgap. Callegari et al.l46l adopted a similar approach to passivating the airexposed LEC melt-grown GaAs samples. A few monolayers of Si were deposited on the clean GaAs surface, followed by in-situ deposition of Si02 using rf PECVD (low rf power density was used to minimize plasma
Passivation
of GaAs and InP
359
damage). Since the samples were exposed to ambient atmosphere, it was necessary to remove the native oxides using in-situ H-plasma treatments. Studies of the SiO#WGaAs structures using high-resolution transmission electron microscopy suggest that a solid phase epitaxial growth of amorphous Si, which then converts into crystalline form, occurs due to annealing at -57OOC for five minutes. An analysis of the MIS C-V data indicate the minimum trap density to be -4 x 10” cm-* eV-‘.
(4
Applied Voltage,
V
I
180 L 160 L. 140 120 : LLa 100: (5:
80:
(b)
60 : 40 _ 20 7
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 5 -4
-3
1
2
Applied Voltage,
V
-2
-1
0
3
4
Figure 14. Quasi-static and high frequency capacitance-voltage curves measured at 1 MHz, 100 kHz, and 100 Hz for Si,N,/GaAs capacitors (a) annealed at 500°C for 90 s and for samples (b) annealed at 600°C for 30 s (after Ref. 139).
360
Compound Semiconductors
It is evident from these preliminary results that the use of a few monolayers of Si to passivate the surface is very promising and that more In view of the work done on airwork in the area will be forthcoming. exposed surfaces, it is also very encouraging to note that excellent and stable passivation can be achieved on these surfaces.
7.0
EPITAXIAL
REGROWTH
Epitaxial growth or regrowth is potentially the very best technique of passivating a surface, since a clean-defect free interface can be formed. This interface should be almost perfect and should produce the smallest density of electronic gap states, since it is a continuation of the bulk crystal. One of the first attempts to capitalize on this process was reported by Casey, et al., in 1978.1 1401 They introduced oxygen into an AlGaAs overlayer on GaAs. Since the oxygen forms a deep trap, the resistivity of the AlGaAs was greatly increased, resulting in a psuedo-insulator. Solomon et a1.l141l demonstrated the effectiveness of epitaxially grown undoped AlGaAs as a quasi-gate insulator on GaAs. They did not report interface state densities, but the high quality of the FETs fabricated by this technique indicates that the interface density was low. Later, Hanson and Wieder11421used an epitaxial InAlAs overlayer on InP to form a quasi-gate insulator. They report that the surface state density for this interface was in the high lOlo to 10” cmm2eV-l range. In addition, the transistors fabricated with this insulator had good pinch-off and current saturation, all of which indicates excellent passivation of the InP surface. Altering the chemical composition of the first few surface layers of InP and GaAs, by exposing the heated substrate to a molecular beam of As or P respectively, is one way of achieving a thin epitaxial layer. This process converts the InP surface to InAs and the GaAs surface to GaP by first evaporating the P/As and replacing it with As or P. This type of surface modification can occur during the MBE growth of InGaAs or InP and InGaP on GaA.~.l~~~l It can also be done intentionally to passivate the surface. The InP surface conversion has been extensively investigated by the group at Ecole Centrale de Lyon.1 1441 They report that the best electrical properties occur when the structural order of the surface is restored and the surface arsenic is lightly oxidized. This oxide is thought to form bridge bonds between the insulator over layers that are used to complete the passivation.
Passivation
of GaAs and InP
361
We have investigated the conversion of the GaAs surface to GaP by soaking the GaAs in a P overpressure in a gas source MBE system.t1451 XPS clearly shows the formation of a phosphorous compound at the surface. However, there was no definitive experiment showing beneficial passivation effects. Lee et al.11431performed similar experiments in order to determine the interface composition of GaAs-InGaP heterojunctions, grown by gas source MBE. They found that a 6 set soak at 530°C created an 8 A layer of G~AQ~P,,~ that was smooth and highly reproducible. Increasing the soak time caused the surface to become quite rough. Thus, the conversion of the GaAs surface to GaP or GaAsP is possible using the proper technique, however, it has not been proven that this conversion reduces the surface state density.
8.0
EPILOGUE
It is apparent that, in the last five to six years, significant progress has been made in passivation of GaAs and InP surfaces. Dramatic improvements in the electrical properties of semiconductor surfaces have been achieved using a variety of techniques. These techniques range from simple chemical treatments, using sulfur- and selenium-based solutions, to sophisticated epitaxial growth/regrowth methods which include the deposition of a few monolayers of Si. It is also very encouraging to note that excellent passivation of the surface defects can be achieved even on airexposed surfaces. This is particularly true for the GaAs surface which has been relatively much harder to passivate than its InP counterpart. The much sought after MISFETs in these materials also exhibit significant improvements in their performance, and more work in the area will certainly be forthcoming. The usefulness of superior M-S and I-S interfaces are obviously numerous. However, before these techniques become practically viable, the problems associated with uniformity, reproducibility, and stability of the passivated surfaces, devices and circuits will have to be carefully evaluated. The nature of surface electronic defects and the &&mental mechanism of passivation continue to remain controversial, but nevertheless, due to the amount of experimental data now available, it appears that dos and don ‘ts of III-V surface passivation may emerge. At least for now, it appears that the demon of Fermi-level pinning and the myriad of other related consequences that have plagued GaAs and InP are removed.
362
Compound Semiconductors
ACKNOWLEDGMENTS The authors gratefully acknowledge the support provided by the Army Research Office under the grant no. DAAL03-90-G-0209. C. W. Wilmsen also acknowledges the support of NSF and CATI. The authors are thankful to A. Kapila, X. Si, and K. M. Geib for their help in preparing this manuscript.
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8 Wet and Dry Etching of Compound Semiconductors Stephen .K Pearton
1.0
INTRODUCTION
The fabrication of a typical III-V semiconductor device involves a sequence of patterning, etch, and deposition steps. This chapter describes the use of wet chemical solutions or plasmas for the etch steps. Most processing sequences involve a combination of both wet chemical and dry etching, although the trend is clearly toward the use of plasmas because of the more anisotropic features and better dimensional control that can be obtained. Typical wet and dry etch mixtures for the most common III-V semiconductors are listed in various tables throughout the chapter, and application of these mixtures for fabrication of several types of devices is detailed.
2.0
WET CHEMICAL
ETCHING
This section is concerned only with the use of acid or base solutions for patterning of features. Wafer cleaning by chemical or vapor techniques is not covered, and the reader is referred to several text books which deal with these topics.l’l-141
370
Wet and Dry Etching 2.1
371
General Principles
The basic steps involved in wet chemical etching of III-V materials involve oxidation (or reduction) of the semiconductor surface and removal of a soluble reaction product. The etching rate may, therefore, be limited by the diffusion of the active etchant species to the surface, or by the diffusion away of the soluble product. This type of etching may have a significant degree of anisotropy because of diffusion-controlled removal of new material from the undercut region under the mask edge. Diffusion-controlled etches are generally not used in device fabrication because the etch rates are highly sensitive to agitation of the mixture, and hence, are difficult to control in a reproducible fashion. The rate of dissolution of the reaction products can be increased by more vigorous agitation of the wafer or etching solution. The etch rate of diffusion-limited mixtures is usually quite insensitive to the temperature of the solution. If the chemical reaction at the semiconductor surface is the ratelimiting step, then the mixture is referred to as a reaction-limited etch. For III-V materials which involve at least two different sublattices, these types of solutions usually etch the various orientations at different rates, and therefore, can produce a degree of anisotropy during pattern transfer. For example, As faces in GaAs tend to etch faster than the Ga faces. Reactionlimited etches are generally quite insensitive to agitation, but show a marked temperature dependence of the form:
Eq.(1)
ER
= &+lkT
where ER is the semiconductor etch rate, K is a temperature-dependent constant, E, is the activation energy, k is Boltzmann’s constant, and T is the absolute temperature of the mixture. This form of etch solution is preferred for device fabrication because of its uniform nature, but the temperature and pH must be carefully controlled for reproducibility. Depending on the actual etch mixture and application, the solution may either be heated or cooled to obtain controlled etch rates. This is obviously easier to achieve than to try to control the flow of the solution over large areas with difhisioncontrolled etch mixtures. In this latter case, the agglomeration of the etch solution will vary across any given area of the water, and therefore, local variations in etch rate will occur. The degree of isotropy for any etch mixture can be obtained as illustrated in Fig. 1. In this case, the etch mixture is completely selective for
3 72 Compound Semiconductors
removal of layer 1 over layer 2, and does not attack the masking material. The thickness of layer 1 is also the vertical etch depth (ED,), and as the etch time increases, the horizontal etch depth increases from ED, to ED, for times t, and 5. The lateral etch ratio is defined as the ratio of the etch rate in the horizontal direction to that in the vertical direction. For a completely anisotropic etch this ratio is zero, while for isotropic etch the ratio is one. As shown in Fig. 1, the slope of the undercut sidewall will tend to become more vertical with over-etch time. The selectivity for etching one layer over another is simply the ratio of the etch rates ofthese respective layers-in the case in Fig. 1, the selectivity for etching layer 1 over layer 2 is infinite. Device fabrication generally requires a selectivity of more than -5: 1 if adequate process reproducibility is to be maintained.
MASK
I
LAYER 2
Figure 1. Schematic of the evolution of undercutting etching one layer from another.
I
of a mask when selectively wet-
Another factor affecting reproducibility is the question of loading effects, in which the etch rate is dependent on the amount of semiconductor If a large area is to be etched, surface area exposed to the mixture. depletion of the etchant species may occur, leading to decreased rates relative to a situation in which a small area is etched. These effects are more prevalent in dry etch processes and usually lead to a clearing pattern in the form of a bull’s_eye, caused by the edge of the wafer etching faster than the center.
Wet and Dry Etching
373
Since wet etching tends to be isotropic in nature, the undercutting of the mask makes it unsuitable for pattern transfer of small (< 2 urn) features. It is a low-cost, reliable, high-throughout process, and in III-V technology, the use of simple photoresist masks is possible. Most manufacturers have instituted a small degree of automation, such as spray etching, to their wet etch processes in order to enhance reproducibility. In addition to the inability to transfer small feature sizes, wet chemical etching suffers from a number of other disadvantages relative to dry etching, including the need to dispose of large quantities of acid solutions, increased safety hazard due to potential exposure to chemicals and fumes, and bubble formation during the etching, which can lead to local unetched regions. Wet etching of dielectric films on III-V materials is essentially nonexistent, at least for pattern transfer processes, because of the advantages of dry etching. Essentially, all of the common dielectrics (SiO,, SiN,, phosphosilicate glass [PSG], TiN) can be dry etched using fluorine-based gas mixtures (CF,, SF,, NF,) which do not etch the III-V semiconductor. Wet chemical solutions of HF will readily remove the dielectrics, but in an isotropic fashion. The concentration of I-IF typically is 49% in water, which is usually further diluted with a buffering agent such as ammonium fluoride (NI&F) which stabilizes the mixture. SiO, is typically etched in buffered HF at rates of -1000 Aminl, while S&N, can also be etched in these mixtures. An alternative formulation for silicon nitride is 85% HsPO, at elevated temperature (-150°C), but this is not attractive from a safety viewpoint or when using photoresist masks. PSG will also readily etch in HF or buffered I-IF solutions, with the etch rate being faster for higher amounts of P,O, in the glass. Among the metals typically used in III-V technology, Au can be removed in 3:l HCl:HNO, solutions (aqua regia), which also attacks the semiconductor. A KI/I,/H,O solution, which can be used with photoresist, will also etch Au but KCN solutions are most common. Platinum and palladium can be etched in aqua-regia, while Pd can be removed in the KI/ 1,/I&O formulation. Tungsten masked by photoresist may be patterned with a KI&PO,/KOH/K,Fe(ON),/H,O solution131 while a similar solution will also etch MO. 2.2
Wet Chemical Etching of GaAs
Most of the etching solutions for GaAs contain hydrogen peroxide @&O,), which is used to dissolve the oxidized products created by the acid
374
Compound
Semiconductors
component of the mixture. This acid is generally one of the common ones, such as phosphoric (H3PO4)' nitric (HNO3), sulfuric (H2S0J, hydrochloric (HCI) or citric (C3H4(OH)(COOH)3~O). Ammonium (NH4°H)-peroxide ~OJ-water mixtures are also commonly used and are very popular for device fabrication becauseof the controlled etch rate of -3000 A.min-l for a ( 1 ml NH4°H):(700 ml ~OJ solution. A controlled undercut of a GaAs epitaxial layer masked by photoresist is shown in the scanning electron micrograph (SEM) of Fig. 2. In this case, the underlying AIGaAs layer does not etch significantly in the ammonia-peroxide mixture. The shape of the edgeprofile can be understood on the basis of the differing etch rate of specific crystalline faces. Shaw[S] published such an analysis for the ~SO 4~02~O system, for which the relative etch rates of the different crystallographic planes, exposedto the solution for different mask orientations, are well known.[6] The NH4O~O2~O system has fairly stable aging characteristics, so, it is not necessaryto make up a new solution every time an etch must be performed. Somework has also been performed with another alkaline-based system, NaO~O~O.[7][8] This appears to have fairly similar characteristics to the NH4OH-based mixture. These systems are effective for GaAs because the Ga and As oxides can be dissolved in either acidic or basic formulations. In general, the sidewall profiles tend to be similar to those obtained with sulfuric acid-peroxide mixtures.
Figure etch.
2.
SEM micrograph
of undercutting
of masked GaAs layer by NH4OH/H2O2
The undercut region under the metal mask is -I
~m long.
wet
Wet and Dry Etching
375
There is an extensive literature on the I-&SO,&O&O system for etching GaAs.131171-llil Th e isoctch rate curve for 0°C etching is shown in Fig. 3. This is a reaction-limited mixture, being thermally activated with the relation described in Eq (1). At high sulfuric acid or high hydrogen peroxide concentrations, the etched surfaces have a mirror smooth appearance for a wide range of etch temperatures. For high concentrations of both &SO, and 1$02, the etching is extremely rapid and leads to rough surface morphologies. Cloudy surfaces can also result for low concentrations of these components, where slow etch rates are obtained. A 4H$O,: l&O,: 140 solution etches most GaAs crystallographic faces at -5000 Aemin-’ at room temperature and -3 pmminl at 50°C. The etch rates for various planes and the cross-sectional shape of the mask-undercut have been tabulated elsewhere.161l10l In the (011) direction, the undercut profile can be varied from essentially f 45” from the vertical.
Hz02
GaAs E%
H20
Figure 3. ketch
curves for GaAs at 0°C in H,SO&O,/H,O
RATE
H2S04
solutions (after Ref. 3).
The system H,PO,/H,O,/I-JO can be used to etch GaAs at slow controlled rates, as shown in the isoetch rate curves of Fig. 4.11211131Over most of the composition ranges, the removal rate is linearly dependent on time, but for high phosphoric acid contents there may be a square root of
3 76 Compound Semiconductors time dependence. This is due to the high viscosity of H,PO,, so that diffusion of the hydrogen peroxide to the semiconductor surface becomes the rate-limiting step. In the other regions of the isoetch plot, the etch rates are similar for all crystallographic planes except the (111) Ga face, which exhibits an etch rate approximately half that of the other planes. “20
GaAs
‘-‘3”04
Figure 4. Isoetch Ref. 3).
rate curves
ETCH RATE
“202
for GaAs at 30°C in H,P0,/H,0,/H20
solutions
(after
Citric acid-hydrogen peroxide-water solutions have also been studied for removal of GaAs, yielding rates in the range 60-6000 Amin-’ depending on the composition. 1141These mixtures do not appear to possess any particular advantages over the other solutions, and have been less studied. Similarly, HCl has been used in several mixtures, including HCqO,40 (etch rate: 0.2-5 pmmin-i), HClK&r,0,/H$04 (etch rate: 2-20 pmminl) and HClKrO, (etch rate: 0.1-0.2 ~m~min-1).~g1[10~[151-[171 Shawllo has also published details of the etch rates and cross-sectional undercut sidewall profiles for the HC~OJI-I~O system. Bromine-methanol (Br/CH,OH) solutions have very rapid etch rates for GaAs (typically > 5 um*min-’ at 25°C) and are used for polish etching. Photoresist is not a suitable mask because of attack by the bromine, but patterned etching using SiO, leads to grooves which have rounded bottoms. These mixtures are often used for V-groove formation.
Wet and Dry Etching
377
AlGaAs can be etched by the solutions described above for GaAs. For selective etching of AlGaAs from an underlying GaAs layer or substrate, HF-based solutions will work for AlAs mole fractions of 2 0.4. For lower Al contents, KID, mixtures can be made selective for AlGaAs for appropriate pH values (usually low, -0). For higher pH values, the GaAs will begin to etch. tl*l In the reverse direction, dilute mixtures of H,PO,/ %OJH,O (e.g., 3: 150) will etch GaAs with good selectivity (-10) over Al,,,Ga,,,As. Similarly NH,OHD$O, will etch GaAs with excellent selectivity over AIGaAs.tlgl Table 1 shows a compilation of etch mixtures for GaAs that have appeared in the literature.[41t61tglt201 Table 1. Wet Chemical Etch Mixtures for GaAs Comments
Mixture
HzS04/HzOz/BzO I-NO3/H, 02 /I-I, 0
etch rate up to 5 pm - min-’
for low dilution
etch rate up to 7 pm - min-’
for low dilution
HCl/H202/H20
HN03 may be substituted for Hz 02, and methanol substituted for Hz 0. ethanol or methanol may be substituted for H2 0
H3P0&4202/H2
0
CH3 COOH/HN03
/H2 O2
NH‘jOH/H2Oz/HzO HNo3/HF WW-4
0
K3Fe(CN)d&Fe(CNh
2.3
HCI often used in place of H2 02. Peroxide-ammonia (PA) etch, common fabrication rapid etch usually diluted with Hz 0. selective for AlGaAs at low pH
in device
can be made selective for GaAs or AlGaAs (18)
Wet Etching of InP
Many wet chemical solutions for InP are based on HCl.t*ll The HCl is usually combined with H,O, H,PO,, HNO,, H,O, or HBr. The etch rates are high in these mixtures, up to 5 ummin-l for high HCl concentrations. Strong dilution with water is used to provide rates in the hundreds of A-mm-l range for device fabrication. Etch rates with HCVH,PO,&O mixtures are in the range 900-10,000 Amin for 1:4 acid-to-water mixtures with varying acid concentrations of 525%. Solutions based on HBr
3 78 Compound Semiconductors with HF, CH, COOH, H3P0,, HCI, HNO, are also used for chemical polishing applications. A mixture of HEr/CH,COOH/I$Cr,O, will etch InP and InGaAsP at near equal rates for mesa fabrication. Very slow etch rates (200-600 A) may be obtained with I-I.$O,~OJI-I,O mixtures. Hot, dilute &SO, is used as a polish and removal etch.l22l For selective etching, H,P0,/H202/H20 will etch GaAs but stop on InP. Similarly, I-I$0,~02k&0 will etch InGaAs or InGaAsP, but stop on InP. In the reverse direction, HCl/H20 will etch InP, but stop on InGaAs or InGaAsP. For nonselective etching, HCliHN0,/I-120 will remove both InGaAs and InP at near equal rates. Table 2 shows a compilation of etches commonly used for InP. It should also be noted that bromine/methanol etches are used for etch-pit studies on InP, as for GaAs.
Table 2. Wet Chemical Etch Mixtures for InP Mixture
HCl/H2 0 HCl/HNO,, HCl/H2 Oz HCl/Hs P04/Hz 0 HBr/HCl I-lBr/HF HBr/Brz/HzO HEWI3
PO,
HBr/CH3 COOH
Comments
vigorous etch rate when hot etch rate increases rapidly with temperature acetig acid may be added 900A - min-’ for l/4/20 mixtures selective for InP over InGaAsP will preferentially reveal dislocations rapid rates-depend strongly on dilution KzCrzQ may be added; 2 pm - min (25°C). chemical polishing
The ternary compound InGaAs is etched by phosphoric, sulfuric or nitric acid solutions, which when mixed with HCl will also etch InP. For the ternary compound InGaAsP, almost all of the etches are based on I-&SO, or HBr, with additions of hydrochloric, phosphoric or acetic acid, or will etch hydrogen peroxide. l”l A mixture of lH2S04/lH202/10~0 InGaAsP at rates of 400- 1000 A*min-i, depending on the As content of the quatemary.l24l For the InAlAs/InGaAs heterostructure, a 3HCl/l&O mixture will selectively etch InAlAs and stop on InGaAs.
Wet and Dry Etching 2.4
379
Wet Etching of InGaP
The ternary compound In,,,G%.,P is lattice-matched to GaAs, and bas attracted great interest for both electronic and photo& device applications. Figure 5 shows the etch rates of InGaP in H3P0,/HCl/Hz0 mixtures The etch rates are seen to (25°C) as a function of the etch formulation. increase with increasing HCl concentration, although the fastest rate was achieved with a dilute H,PO, addition.
HCf
‘W’04
0
0
Figure 5. Etch rates of InGaP (in A.min-I) at 25°C in H3P0,/HCvH20
solutions.
An Arrhenius plot of tbe wet chemical etching rate of InGaP in a 1: 1: 1 H,PO,:HCl:H,O solution is shown in Fig. 6. The etching is thermally activated with an activation energy of 11.25 kcabmole-‘. This relatively strong temperature dependence is characteristic of etch solutions, in which chemical reaction at the surface is the rate-limiting step. The etching with this solution was extremely smooth, with a lack of etch-rate dependence on the degree of agitation. These are both characteristics of reaction-limited etches. The etch rates are controllable in the range 50-16,000 Amin with the H3P04/HC1/H~0 mixture.t251
380
Compound Semiconductors lot R a
Ea = 104
e-EalkT 11.25
kal/mole
0
0
0 0
O
103
0
F z a CL: 102
10
0
1
I
I
3.2
I
I
3.4
I
I
3.6
l/T x lo3 (l/K)
Figure 6. Arrhenius plot of etch rate of InGaP in H,PO&CL/H,O
2.5
solutions.
Wet Etching of AlInP
The (A&Ga,,),,h+,,P/GaAs heterostructure system has attracted a lot of attention recently. At the other extreme of composition to InGaP is Al&n,,,P. A mixture of HCVH,O has been found to selectively remove AlInP from an underlying GaAs layer.[261The etch rate of Al,,&.,P in HClB-QO solutions at 25°C as a function of the composition of the solutions is shown in Fig. 7. The etch rate increases rapidly for increasing HCl concentration, and can easily be controlled in the range 600-6000 Amin for formulations of 30-5: 1 of &O:HCl. These are convenient etch rates for device processing because typical AlInP layer thicknesses are in the range 1500-8000 A.
Wet and Dry Etching
381
7000 -
6000 AlInP 25% ‘; f
5000 -
. “9 F
4000 -
d 5 t
3000 -
2000 -
1000 0
01
I
I
I
5:l
IO:1
15:l
CONCENTRATION
1
I
2O:l
RATIO (H20
25:l
3o:i
: HCI)
Figure 7. Etch rate of AlInP at 25°C in HCXH~O solutions formulation.
as a function
of etch
The temperature-dependence of AlInP wet chemical etch rate in a 20: 1 &O:HCI solution is shown in Arrhenius form in Fig. 8. The etch is exponentially activated with an activation energy of 12.46 kcal mole-’ indicating that the rate-limiting step in the etching is chemical reaction at A selectivity of -20 for etching A~,,,IQP over the AlInP surface. Iq,sG%.sP would be obtained with a 5: 1 H,O:HCI mixture at 25°C. 2.6
Wet Etching of Other III-V Materials
GaSb can be etched in hot HC1,[271 HN0,/HF[281 or HCl&02t2g1 mixtures, and can be polished with bromine-methanol solutions. GaN can be removed with hot (80°C) NaOmO, solutions,[281 whereas GaP can be etched in the same type of mixtures as for GaAs, e.g., HNOJHF, I-MO,/ HCl, H$O,&O, or bromine-methanol.[20~
382
Compound Semiconductors
1011 3.0
I 3.1
t 3.2
1 3.3
, 3.4
I 3.5
:
1000/T WI
Figure 8. Arrhenius plot of etch rate of AlInP in 20H,O/lHCl
solutions.
In the In-based III-V semiconductors, InSb can be etched in HNO,/ HCl, HNOJHF, NaOI-I/I$O, (hot), I-I$O,k&O, or brornine-methanol.1201 InAs is typically etched in HCI based mixtures, HNOJHF, or HNO,iHCl (with water or acetic acid addition). 1201A selection of typical etches for a variety of III-V materials is shown in Table 3. Selective etches for some of the materials are also given.
3.0
PLASMA ETCHING
It is sometimes mistakenly assumed that dry etching and wet etching are direct competitors, whereas in reality, virtually any device processing sequence contains both types of pattern transfer or material removal. In
We? and Dry Etching
383
Table 3. Wet Chemical Etch Mixtures for Various III-V Semiconductors Material AlGaAs G&S IllGaP AlIti InGaAs InP InAlAs GaSb GaN GaP InSb
Etch Solution KvI2 KuI2
H3P04/HCl/H20 HCl/H2 0 H2 SO, /Hz 02 /I-I2 0 HCI/H2 0 HCl/H2 0 HCl HN03 /HF NaOH HN03 /HF or HCl H2SWH202 HN03 /HF or HCI H2
IllA.
SO,
/Hz
Comment selective over GaAs for low I2 selective over AlGaAs for high I2 highly selective over GaAs for low H3 PO4 selective over GaAs selective over InP selective over InGaAs selective over InGaAs H202 or Hz0 added must be heated (SOT) H2 0 can be added
02
HCI HN03 /HF or HCl
H2 0 can be added
general, wherever there is a choice, dry etching should prevail simply because it is more amenable to automation, has more anisotropic pattern transfer, can more readily etch small features because of an absence of surface tension or wettability effects, and in principle, should have smaller amounts of waste material to be disposed of. Plasma etching has a number of variants, and the reader is referred to textbooks or reviews on the subject. 130j140jThis chapter concentrates on the use of reactive ion etching (RIE), which is the most common dry etching method used in III-V technology. It does not cover barrel etching which is used for resist or dielectric stripping, or for patterning of very large area features (2 50 pm). In principle, a perfectly anisotropic dry etching treatment will give vertical sidewalls, with no erosion of the masking material. Figure 9 shows a comparison of features etched into an InP substrate, using either an HBr/ I-&O*&0 wet etch (at top and bottom left), or with CH,/II/Ar dry etching (at top and bottom right). Since this wet etching process is isotropic, substantial undercut of the W metal masks occurs during formation of the 4 urn deep mesas. If this etching is not well controlled, the neck of the mesa may narrow so much that the mask falls off. Similarly, since it is difficult to achieve good uniformity with this type of etching process, adjacent mesas have different widths. This is clearly seen in the micrograph at
384
Compound
Semiconductors
bottom left (Fig. 9). By contrast, the dry etchedfeatures have near-vertical sidewalls, and further processing such as deposition of a SiN confonnal layer over the features, followed by etch-back to leave it present onlyon the sidewall itself can be perfonned to passivate the sidewalls. This is illustrated in the bottom right of the figure. Mesa etching is a clear example where dry etching should be used,provided it is compatible with subsequent growth or processing.
Figure
9.
Wet (top and bottom
left) a dry (top and bottom
right)
etched laser mesa
structures.
3.1
General Principles of RIE
The term R/E is generally applied to discharges contained between two parallel plates, one of which is powered at rf frequencies through a coupling capacitor. The much higher mobility of electrons in the discharge allows them to respondto the alternating field applied across the electrodes, while the massive ions cannot, generally, be swept to the electrodes. The
Wet and Dry Etching
385
metal plates will charge up to a negative potential relative to the body of the discharge. This potential will stabilize at the value where the electron and ion fluxes are equal. When one of the electrodes is smaller than the other, a larger voltage is developed across the smaller sheath capacitance associated with the small electrode. A typical RIE configuration is shown in Fig. 10. Since the large electrode is usually the chamber itself, most of the potential difference between plasma and electrode is dropped across the sheath region above the small powered electrode. Since electrons are repelled from this electrode by its negative potential, there are fewer electron-gas molecule collisions, and therefore, less optical emission from this sheath, or space-charge region. It therefore appears as a dark space relative to the more intense glow from the body of the plasma. Ions which stray near the edge of the sheath are accelerated across it and strike the small electrode at near-vertical incidence. The sample to be etched is placed on this electrode and is subject to this ion bombardment as well as a constant flux of neutral gas atoms and molecules. GROUNDED METAL CHAMBER
FEED GAS --+
-
PUMP
-L 7
INSULATOR
-L COUPLING CAPACITOR
6 -
Figure 10.
RF GENERATOR
Typical RlE configuration.
A schematic of the RIE process is shown in Fig 11. The average electron temperature is much higher than the ion temperature because of their response to the ac field and the fact they cannot lose much energy in collisions with the much more massive neutral gas molecules. By contrast, energy transfer between ions and neutrals is much more efficient, so the
386
Compound Semiconductors
average ion temperature is much lower than that of the electrons. At a pressure of 1 mtorr, the neutral gas molecule density is 3 x 1013 cmm3,while the electron (and ion) density is usually around 101o-lO1l cm3, and may approach 1012 cm” in enhanced discharges. Reactive gas atoms (e.g., Cl) adsorb on the unmasked areas of the sample and form a volatile species, whose removal is enhanced by the ion bombardment. In general, the reactive atoms and the physical sputtering by the ions would each individually give rise to a finite etch rate of the sample, but there is a synergism between the two which leads to an etch rate faster than the sum of the two components. At high pressures and low sheath voltages, chemical etching of the substrate is dominant, whereas at low pressure and high sheath biases, ion sputtering is dominant. The former produces lower damage but poorer anisotropy relative to the latter. Almost all RIE processes involve a trade-off of these parameters. 1, - 1OeV TI - 1eV q=ne
5 1012cm-3
nN=3x1013
cm-3
vI=lOs
cm.s-l
(1 mTorr)
______fl____FiLi 1
Figure 11. Schematic of typical RIE parameters
As an example of a typical RIE process, we can examine chlorine etching of GaAs. The first step involves formation of the atomic etchant species by electron collisions with chlorine molecules, i.e., Cl, + e + 2Cl + e . Ion formation occurs in a similar fashion, i.e., Cl,, Cl + e + Cl;, Cl+ + 2e. The atomic chlorine adsorbs on the surface, i.e., Cl + GaAs + GaAs-Cl. Ion bombardment and possible participation of electrons from the substrate may lead to reaction on the surface, to form the adsorbed etch products, i.e., GaAs-Cl + GaCL, (ADS) + AsCl, (ADS). Etch product
Wet and Dry Etching
387
desorption by impinging ions then occurs, causing the removal of material, i.e., GaC&,s,, AsCl,(,,,-+GaCIX~,,, AsC$,,,. The values of x and y range from one to three. The exact plasma conditions, and especially the sample temperature, determine whether mono-, di- or trichloride species are predominant. 3.2
Gas Chemistries
The most common discharges used for dry etching of III-V semiconductors are based on chlorine, since the group III and group V fluorides are nonvolatile. This makes patterning of dielectrics on compound semiconductors particularly simple with F-containing (CF,, SF,, NF,) plasmas. Table 4 lists some of the common chlorine-containing etchants. Normally, these gases are diluted with As, He, or 0 to provide more stable operation of the discharge, easier ignition of the plasma, or to better control the etch rate. All of the gases provide relatively fast etching of GaAs, although BCl, or PCl, are often favored because of their ability to getter water vapor and immediately attack the native oxide on the semiconductor to minimize incubation time before etching commences. Under ideal conditions, Cl,, SiCl,, BCl, and PCl, provide equi-rate etching of GaAs and A&Ga,_Js over the whole range of AlAs mole fractions. In practice however, the presence of even small amounts of water vapor in the system may promote oxidation of the AlGaAs, causing slower etch rates relative to GaAs. The use of CCl,F, or any of the other chlorine-based gases, with the addition of fluorine in the discharge, provides a very high selectivity for etching GaAs over AlGaAs at low biases because of the formation of the relatively involatile AlF, species on the AlGaAs surface. The advantage of separate addition of SF, or an equivalent gas to SiCl,, BCl,, and so on, is that the ratio of Cl, to F, can be made arbitrarily large or small, depending on the application, whereas in CCl,F, the ratio is fixed. At one time it was also thought that production of Freon 12 would be stopped because of the damage it causes to the ozone layer, but it now appears as if limited but expensive quantities will be available for situations such as dry etching which largely uses up the gas during the process. Two replacements for CCl,F,, namely Freon 21 (CHCl,F) and Freon 22 (CHClF,) have similar etching characteristics to Freon 12 for III-V semiconductors.1411t421 In general, smoother, more anisotropic etching is obtained with SiCl, and BCl, relative to pure Cl, because of the smaller chemical etching component. This is obvious in Fig. 12.
388
Compound Semiconductors
Table 4. Typical Etch Mixtures for III-V Semiconductors Comments
Chemistry (a) Cl&z.red Cla. Sic&, BCls , pC13, Ccl2 F2
-
Usually have additions of Ar, He - Rough etching for In-based compounds - Poor selectivity over photoresist
(6) Cl& -Bused
CH4i2. C&/He. W-W%. c3 HB /Hz
-
(c) Bra-Based HBr, CF3 Br, Br2 (d) Iz-Based I-II,CI-h I, I2
Ar often added to enhance stability Heavy polymer deposition on mask at high pressure or CH, content CH, to H2 ratio must be in range 0.1-0.4 for smooth morphologies.
- corrosive to gas lines
- high rates for In-based compounds - no polymer deposition.
While the Cl-based mixtures work well for GaAs and related compounds, the relative nonvolatility of indium chlorides mean that these discharges are not ideal for etching InP and related materials. The relative volatilities of possible etch products from III-V materials is given in Table 5. Typical SEMs of features etched into InP using CCl,F,, CCl,F, + PC&, or PCl, alone are shown in Fig. 13. The surface becomes very rough with more chlorine in the discharge because of increasing In-enrichment of the surface. One can enhance the volatility of the indium chlorides by heating the sample above - 130°C to promote desorption, but this is not always a practical solution. 1431The CH,/H, chemistry was introduced to overcome the limitations of chlorine mixtures for In-containing compounds.1441 The role of the CH, is to remove the group III species (A) as (CH3&A,, type compounds, while the I!& removes the group V species (B) as BH,. This mixture etches all III-V materials at a slow rate, but with very smooth morphologies. The etch rate can be increased by replacing CH, with C,H,, C,Hs and other hydrocarbon gases, and at low biases, the addition of Ar also aids the etch rate by providing more ion-enhanced removal of the etch products. The CH,/I-I, discharges are remarkably forgiving of the presence
Wet and Dry Etching
389
Figure 12. SEM micrographs ofGaAs etch in a 10SiCI4/5Ar, 20 mtorr discharge with loo Vdc bias (top left and right), or in 10CI2/5Ar, 20 mtorr (at bottom left) or 100 mtorr (at bottom right).
of water vapor, which actually enhancesdissociation of the gases. The major drawback is the deposition of polymer within the reactor chamber. This can be very heavy at high pressure (>20 mtorr) or high CH4 flow rates. Under most conditions the polymer can be removed by O2 plasma cleaning after each etching run. The ratio ofCH4 to ~ must be kept between~0.10.4 to prevent excessivepolymer deposition at the high values and preferentialloss of the group V species at the low end of the range.[45][46]These effects lead to rough surface morphologies, as shown in Fig. 14.
390
Compound Semiconductors
Table 5. Normal boiling points and vapor pressures of some ofthe possible etch products.
Product
Boiling Point (“C)
AsQ
130 76 162 608 560 600 535 201 183 221 76 162 Sublimes 279 263 -55 -88 61 360 401
PC13 x15
InCl InC12 InC13 GaC12 GaC13 Alc13
AsBr3 PBr, PBrs InBr3 GaBr3 AlBr3 AsH3 PH3 P&I
AlI3 Sb13
Vapor Pressure at Stated Temperature (TOM 40 (50°C) 1(-52OC) l(56”C) 18 (25OOC) 0.08 (25°C) 1 (lOO°C) l(42”C) l(8OC) l(81”C) 760 (-62°C) 40 (- 129°C) 40 (16.1 “C) 40 (265OC) 40 (268°C)
Wet and Dry Etching
Figure
13.
SEM
micrographs
of InP etched in I mtorr,
391
250 V, 100 W (microwave)
38CC12F2/202 (top) or 20CC12F2/7PC13 (center) discharges, or in a I mtorr, 200 V, 100 W (microwave)
7PCI3 discharge
(bottom).
392
Compound
Figure
14.
SEM
5CH4/17H2/8Ar
Semiconductors
micrographs
of InP surfaces after exposure to pure H2 plasma (top),
plasma (center) or 25CH4/5H2
plasma (bottom).
Wet and Dry Etching
393
The etch rates with CH,/H, discharges are lower than with chlorinebased mixtures, as shown for some selected III-V materials in Figs. 15 and 16. The selectivity for one In-based material over another is not high with CH,/H, mixtures, although it can be enhanced in the case of etching InGaAs from an underlying AlInAs layer, by adding SF, to the discharge. Figure 17 shows the etch depth as a function of time for InGaAs/AlInAs heterostructures in CHJHJAr or CH,/ILJSF, plasmas under the same conditions of self-bias, pressure and flow rates. The major difference in the etching behavior is the much reduced rate of removal of AlInAs, when fluorine is present in the discharge. X-ray photoelectron spectroscopy showed substantial concentrations of low volatility AlF, (boiling point = 129 1°C) and InF, (boiling point > 1200°C) on the exposed AlInAs surface. Their presence is the cause of the reduced etch rate for this material, when F is a component of the discharge. Although the F-containing compounds are relatively involatile, they can be readily removed by sputtering at high biases. Figure 18 shows the time-dependence of etch depth in an InGaAs/ AlInAs heterostructure in a CH,/I-IJSF, discharge with different dc bias values on the sample. At a bias of 85 V, the etch rate of InGaAs is - 90 A*min-l and that of AlInAs is I 10 Ammin-l. As the bias is increased, the etch rates of both materials increase rapidly until, at 360 V, there is equirate etching. Under these conditions, sputter-induced desorption of the etch products is the dominant factor and chemical reactions are less important. Bromine-based discharges will also etch III-V semiconductors and CF,Br/Ar and HBr/Ar plasma etching has been reported.1481[491 The etch rates are slow and the morphologies quite smooth, but the Br-containing gases are very corrosive on plumbing. Iodine-containing mixtures, on the other hand, have proven to be very effective for etching compound semiconductors.1501 In particular, the etch rates for In-based materials are a factor of 8- 10 higher than for CH,/H, discharges under the same conditions. This is illustrated in Fig. 19 for an InP-InGaAsP heterostructure etched at either -100 V bias in a HIk&/Ar discharge or at -300 V in a CH,/H.-JAr plasma. The etching can be extremely anisotropic, as shown in the SEM micrograph of Fig. 20. Typical etch rates for different materials in the various discharges are shown in Table 6.
394
Compound Semiconductors
F
4200-
2 5
IOOO-
L g 2
600-
z
600-
-4--Q----p-
D-_--_-o-_---a
,,_-.+----e-----o
400
-
0
0
I 2
I 4
I 6 ETCH
I 6 TIME
I (0
I 12
44
(mid
Figure 15. Average etch rates of InP, InGaAs, and InAlAs as a function of time for either 2C,H,+ 18H, or 19CCI,F,: 10, discharges.
2000
I
1500
,-
I..
.E .* E I 3
1000
L 8 g z
500
0
0
I
I
I
I
I
I
2
4
6
6
(0
12
ETCH
TIME
(mid
Figure 16. Average etch rate of GaSb, InSb, and InAs as a function of time in C,H&I~ or CCl,F,/O, discharges.
Wet and Dry Etching
395
4000 CH4 /H2 /SF6
3000 InGaAs
.z
J E k 2000 0 5 L
1000
I
I
I
I
10
,
20
I
30 TIME (min)
Figure 17. Etch depth as a function of time for InGaAs/AUnAs structures in 10 mtorr, 190 V bias discharges of 2CH4/18HJlOAr or 2CH,/lSH,/lOSF,.
InGaAs/AlInAs Cti40i~f SF6
I
-
5
10
v,.SSov V,‘lSoV .y= SSV l l
15
2025
30
55
TIME (min.)
Figure 18. Etch depth as a function of time and dc bias voltage for lnGaAs-AllnAs heterostructures reactively ion etched in a 10 mtorr, 2CH,/lSH,/lOSF, discharge.
396
Compound
Semiconductors
~ ~ 1no w c ~ ~
Figure
19. Etch depth as a function
of InP-InGaAsP
of time for CH4/H2/Ar
or lll/H2/Ar
ECR-RF
etching
heterostructures.
Figure 20. SEM micrographs of deep features etched into InP using 10HI/10H2/5Ar, 10 mtorr, -150 V,200 W (ECR) discharges.
Wet and Dry Etching Table 6. Typical etch rates of GaAs, InP, Al,,,G%,7As different discharges at 4 mtorr and 0.6 W-cm-*.
Mixture
GaAs
CldAr
20,000 5,000 3,000 2,000 600 600 200 250 5,000
SiCl, /Ar PC13/Ar CClz Fz /OZ CHs Br/Ar HBr/Ar C&/H2 C2WH2 HI/H2/Ar
3.3
397
and InGaAs in
Etch Rate (A * min-‘) AlGaAs InP InCaAs 20,000 5,000 3,000 50 400 500 160 180 4,000
200 150
150 650 250 400 220 250 7,000
200 350 350 1,cQo 320 400 280 320 5,000
Surface Chemistry
One of the key parameters in dete rmining whether or not a dry etch treatment is successful is the composition of the resultant etched surface. Since subsequent growth or processing steps usually need to be performed on this surface, it is important that minimal change have taken place. Table 7 shows the average atomic composition in the top 100 A of GaAs samples etched in various composition CCl,F,/O, discharges at different power densities. Varying amounts of F and Cl containing residues are found in all cases, and high power conditions lead to substantially more carbon deposition on the GaAs surface. Similarly, higher 0, concentrations in the discharge lead to more oxidation of the surface. Results for the surface of Al,,,Ga,,,As samples after RIE in CCl,F,/ 0, discharges are summarized in Table 8. The predominant species are Ga,O,, Al,O,, AlF, and GaF,, and the relative thickness of these layers depends on the plasma conditions. Rinsing in deionized water removes 70% of the fluorinated species, while an ammonium hydroxide solution removes much of the oxides and the remainder of the fluorine.[511 Post-NE cleaning is necessary to obtain reproducible metal Schottky barrier heights for subsequently deposited gate contacts.
398
Compound Semiconductors
Table 7. Atomic concentrations on surface of GaAs samples after various RIE treatments, as determined by XPS. The CCl,F,:O, etches were performed at 4 mtorr pressure for 4 mm. The table also lists the CCl,F,:O, ratio in the gas mixture and the plasma power density in W cm-*.
Atomic Concentration % Element
Control
As 3d Ga 3d 0 1s c 1s
13.68 15.44 36.53 34.35
F 1s
0.00
Cl 20
0.00
19: LO.56
19:1, 1.31
6: 14.0.56
(W cm-*)
(W cms2)
(W cm-*)
12.92 10.84 34.69 35.24 4.39 1.91
4.35 2.18 21.83 47.69 17.92 6.02
11.35 15.70 41.81 23.7 1 5.39 2.05
Table 8. Depth of various components of the near-surface residue found after RIE of AlGaAs with a CCl,F2 discharge for 4 min at 4 mtorr (in A)
Component
Control
A
B
C
D
Fluorocarbons
none cl0 IO-20 none 60-70 none
cl0
cl0
cl0 cl0 20-30 20-30 90-100 50-60
As203
Gad& Gab Al2
03
AIF
A: CCl2F2/02, 1O:lO seem, 0.85 W cme2 B: CCIZFZ, 20 seem, 0.85 W cme2 C: CCl2F2/02,19:1
seem, 0.85 W cm-2
D: CC12F2/02, 19:l seem, 1.3 W cme2
Wet and Dry Etching
399
Small amounts of chlorine-containing residues are present after BCl,, SiCl, or Cl, RIE of Ga-containing compounds. Representative results from GaAs, AlAs and GaSb samples are given in Table 9. For the three different materials, there were more Cl-related residues after Cl,/Ar RIE compared to SiCl,/Ar etching and less of the volatile group V species, but the surfaces are considerably cleaner than for CCl,F,/O, RIE.ls21
Table 9. XPS results. Elemental composition data measured on the surface (- 100 A) of each sample and expressed in atomic percent units for the elements detected.
Sample
c
GaAs-control GaAs-SiClJAr GaAsCl*/AI AlAs-control AlAs-SiCL/Ar AlAs-C&/Ar GaSb-control GaSb-SiCL+/Ar GaSb-ClJAr
29 32.4 43 27 31.8 34 40 39 36 m
RIE conditions: 100 v.
lOSiCb/SAr,
0 30 31 33 35 37 48 39 38 37 -- B
Cl
Ga
As
Al
Sb
... 0.6 1.2 ... 0.2 0.5 ... 1.1 6.2
18 17 13 ... ... ... 13 14 14
23 19 9.5 18 13 3.5 .. . ... ...
... ... ... 20 18
. .. ... ... . .. 1..
14
...
... ... .I.
8.2 7.9 6.8
50 mTorr, 100 V and lOC12/5Ar, 50 mTorr,
As mentioned in Sec. 3.2, the low volatility of indium chlorides is a problem when etching In-based materials. Figure 2 1 shows Auger Electron Spectroscopy (AES) data for InP samples etched in SiCl,/Ar or Cl,/Ar discharges. In both cases, Cl-residues are present to a depth of - 70 A, and XPS shows these are InCl, species. Samples etched in bromine-or iodinebased discharges do not show any contamination from either chemical, and are much cleaner than chlorine-etched material. A comparison of surface composition data from InP, InGaAs, and AlInAs samples etched in either CCl,F,/O, or C,H@, discharges is given in Table 10. The latter chemistry tends to produce P-deficient surfaces on InP and As-deficient surfaces on AlInAs. Chlorine residues are present on all of these materials when etched with CCI,F2/02, and of course there is substantial fluorine on the
400
Compound Semiconductors
AlInAs. Similar data for InAs, InSb and GaSb are shown in Table 11. In these materials there is no significant preferential loss of the group V element during C,H,& RIE, with the surfaces being very clean and of similar composition to the control sample. For CCl,F,/O, RIE there are, once again, relatively high concentrations of Cl-residues on all of the surfaces.
4 InP-
CONTROL
2-
InP-SiC14/Ar
loo-
InP- C12/Ar
2-,
Cl
0
80-
5OmTorr IOOV
A0 Cl In
-4
5OmTorr ioov
P
P
-2r-
InP-Clz/Ar
0 KINETIC
I
1200
I
I
1600
ENERGY
(eV)
35
70
105 140
DEPTH
(%,
Figure 21. AES survey scans and depth profiles from control or RE InP samples etched in IOSiC14/5Ar or 10C12/5Ar (50 mtorr, 100 V) discharges.
Wet and Dry Etching
401
Table 10. XPS elemental composition data measured from the top 100 8, of each sample and expressed in atomic percent units for the units for the elements detected.
Sample
C
0
F
Al
P
Cl
Ga
As
In
InP control InP-Cz I-&/I% InP-CCl,F2/0, InGaAs-control InGaAs-CClz F2/02 InAlAs-control InAlAs-C2 I-&/Hz InAlAs-Ccl2 Fz/Oz
42.7 30.9 45.0 45.0 44.0 40.0 20.5 40.0
24.0 38.0 24.0 27.0 26.0 26.0 49.5 24.2
. .. . .. ... . .. 2.0 ... . .. 9.0
. .. . .. ... . .. . .. 6.0 17.7 8.1
17.3 4.8 16.4 .. . .. . ... ... ...
... ... 4.3 ... 2.1 . .. ... 3.0
... .. . 1.. 6.7 5.6 .. . ... .. .
. .. ... . .. 8.9 8.6 16.4 6.9 8.9
16.0 27.3 10.3 12.4 11.7 11.6 5.4 6.8
Etch Conditions
:2CzI-I,J18Hz :19CC1,F2/02
0.85 W cme2, 4 mTorr. 0.85 W cme2 4 mTorr.
Table 11. XPS results. Elemental composition data measured from the surface (-100 A) of each sample and expressed in atomic percent units for the elements detected.
Sample
C
0
F
Cl
Ga
As
In
Sb
InAs-control InAs-C2 I-&,/Hz InAs-CCI, F2/02 InSb-control InSb-C2H.JH2 InSb-CC12F2/02 GaSb-control GaSb-C2 I-&/H2 GaSb-Ccl2 F2/02
40 32 48 32 36 28 40 30 44
34 39 27 44 38 45 39 44 33
2.8
7.5 4.2 6.3
13 18 5.4
10 11 9 -
16 18 8.5 12 14 7.9 -
12 11 14.9 8.2 7.8 8.5
RIE conditions: 0.85 W * cms2.
2 Q&/l8
Hz, 0.85 W * cmm2, 4 mtorr;
19 CCl2F2/1
02.
402
Compound Semiconductors
3.4
Damage
Electrical and optical changes to the near-surface of the dry etched semiconductor surface are of particular importance in some device structures. In other instances, however, such as mesa isolation etching or laser mesa fabrication, where the sample is heated up to the growth temperature for regrowth of an overlayer, damage introduced during dry etching steps is Damage is a term used to describe usually not of critical importance. several different types of change to the semiconductor surface, including the chemical changes previously discussed. It is to be noted that this type of surface modification also affects the luminescence from the sample and parameters, such as the Schottky barrier height of metals deposited on the surface. Only a complete characterization of the surface can determine whether the observed changes are due to chemical modifications or true damage by energetic ion bombardment. Ion-induced damage has been investigated for a variety of dryetching methods using neutral ion and reactive ion bombardment. The degree of damage has been found to be inversely proportional to the ion mass and directly proportional to the ion energy.153l Sidewall damage during dry etching has also been studied .15411551 The most obvious effect of near-surface damage is a reduction in the carrier concentration up to 1000 A from the surface. This is considerably deeper than the total range of ions crossing the plasma sheath and is ascribed to channeling of these relatively low energy particles, and recombination-enhanced motion of defects. In at least some cases where H, is involved in the etch mixture, there appears also to be passivation of donors and acceptors by hydrogen association. This may even be a factor when hydrogen is not a specific part of the plasma due to small leaks, presence of water vapor or erosion of photoresist masks.156l Figure 22 shows Schottky barrier heights (+n) and ideality factors (n) from TiPtAu contacts on n-type GaAs etched at 50°C in CCl,F,/O, discharges. As the plasma power density increases, so does the bias through which the impinging ions are accelerated, the barrier height decreases because of introduction of generation-recombination centers, and 1571 This type of etching also reduces the the ideality factor worsens. photoluminescence intensity from the semiconductor. Figure 23 shows an in-situ monitoring of luminescence from an AlGaAs/GaAs heterostructure during etching. As the AlGaAs is etched away, the PL falls more quickly than expected because of damage introduction.15*l
Wet and Dry Etching
5 8
. \ 7’
I-
“\
A
l.lOt_
I-
s: 1.00
k
/
\
\
C 2
1.06
\-
x
\ ‘b
0.74
8 E
073
% m
3;
4.04
0.72
Ct3NTRO’
I.00
I 0.75 g
\\
b.
0
’
’
0.2
’
!%dMW F
’
0.4
’
’
0.6
’
403
:
%
’
0.0
’
’
10
PLASMA POWER DENSITY
’
’
1.2
’
’
1.4
’
’
Id
’
,.870
(W . cme2)
Figure 22. Schottky barrier heights and ideal@ factors from TiPtAu Schottky diodes on n-type GaAs etched at 50°C in a 19:l CCI,F,:O,, 4 mtorr discharge, as a function of the plasma power density during the RIE treatment.
2.5 -
Figure 23. Observed (solid lines) and calculated (dashed lines) GaAs and Al,~,Gas,As PL intensity induced by cw laser excitation during BCI, plasma etching. An initial layer thickness of 1 pm is assumed.
404
Compound Semiconductors
Figure 24 shows 4, and n values from Schottky diodes on n-GaAs etched in CCl,F,/O, or C,H,&/Ar plasmas as a function of post-RIE annealing temperature. ~~1 For these low power and bias conditions, the +n values for CCl,F,/O, RIE show little change with annealing, although the n values at first improve and then worsen, possibly due to surface deterioration. Similar results are seen for C,H,/Hz/Ar RIE, but in that case, the $n values are consistently lower than for the control sample due to efficient removal of free As and As,O, from the surface by atomic hydrogen. This acts to unpin the surface Fermi level. Data from Schottky diodes on n-type Al,,G%.,As are shown in Fig. 25. For CCl,F,/O, RIE, the +n is increased from its control value of 0.82 eV and stays high until annealing at 500°C, where it decreases back to its initial value, presumably because of annealing of a thin disordered region. The n values also recover at this temperature. There are less dramatic changes for C,H,/H.JAr RIE. Near-surface carrier profiles in n-type GaAs after RIE and subsequent annealing are shown in Fig. 26. For CCl,F,/O, RIE, there is a reduction in carrier concentration up to - 1500 A in depth due to the introduction of deep level defects which trap free carriers and are not thermally ionized at room temperature. These defects anneal out at - 300°C under our conditions. In the case of C,H,/IIJAr RIE, there is an added effect of inditision of hydrogen and passivation of dopants. This is the reason why, at moderate annealing temperatures, the compensation depth actually increases. These results are confirmed by secondary ion mass spectrometry profiling. One approach to reducing damage introduction is to hold the sample at elevated temperatures during the etch treatment much as is done in ion implantation of III-V semiconductors.l60ll61l Figure 27 shows a significant improvement in ideality factor for RIE performed at -150°C. This improvement parallels the situation with elevated temperature ion implantation in GaAs, in which heating the sample to 2 150°C prevents amorphization through dynamic or in-situ annealing processes. The physical mechanism in this case is the increase in mobility of lattice interstitials and vacancies at elevated temperatures, allowing them to diffuse away to the surface and thereby prevent accumulation of damage. For RIE at temperatures above -25O”C, the electrical diode characteristics worsen due to surface roughening and polymer deposition. The reduced damage at elevated temperature is confirmed by the ion channelling data in Fig. 28, which shows a lower damage peak for higher RIE temperatures.
Wet and Dry Etching
f.20 ’
405
n-GaAt
100 200 ANNEALING
300 400 500 600 TEMPERATURE (%I
Figure 24. Schottky barrier heights and ideal@ factors from TiPtAu Schottky diodes on n-type GaAs etched in either a 19:l CCI,F,:O, or 1:10:3 C,H6:H,:Ar discharge, as a function of post-RIE annealing temperature (30 s anneals).
. o CCl,F2/02 (19/O . acPH6/H2/Ar(l/10/3) I.0
I .3
4.0
I
I
400
200
ANNEALING
I
300
I
400
’
500
TEMPERATURE
’
2
-0.7
600 (‘c)
Figure 25. Schottky barrier heights and ideality factors from TiPtAu Schottky diodes on n-type AlGaAs etched in either a 19:l CCL,F,:O, or 1:10:3 C&H&r discharge, as a function of post-RIE annealing temperature (30-s anneals).
Wet and Dry Etching
120
; .
GaAs RIE 0.56 Wwt~-~,
80
2
200
3 8
160 -+
407
i . . .
50°C
2 MeV He+
;,&‘:*f$RANDOMA .&_ .
12080 -
0’
5 d 7
GaAs RIE 0.56 W wri2, MeV He+ 2
I
250
150%‘. .. 2.
-._ _
I
I
300
350
CHANNEL
400
450
500
NUMBER
Figure 28. Ion channeling spectra taken in glancing angle geometry from samples etched at 50°C (top) or 150°C (bottom) for 4 min in a 4 mtorr, 0.56-W cmT2, 19:l CCI,F,:02 discharge.
For the case of InP etched in either type of discharge, Fig. 29 shows reductions in carrier density to similar depths as for the GaAs (the self-bias is - 380 V). Reverse current-voltage characteristics (Fig. 30) show that upon RIE in C,&&, Au contacts deposited on the surface did not have any rectifying behavior due to the In-rich nature after dry etching. By contrast, CCl,F,/O, RIE produces damage which increases the reverse leakage current, but the Au contact still has a rectifying nature. Ion channelling spectra (Fig. 3 1) from an InP sample etched in C,H@I~ shows introduction of substantial lattice damage to a depth of - 400 A, with nearcomplete recovery of the original crystallinity by annealing at 400°C. The
408
Compound Semiconductors
depth of the disorder measured by channelling is much less than that determined by the electrical measurements and indicates that point defects, inaccessible to ion channelling, are predominantly responsible for the carrier removal.
E
:
-E - 10'6 3
10'0-
2
2?
I
‘ci
z” -AS-ETCHED
-As-E7cnE0 002ooT l e4oor; ---_oo~
0 l 4oov ---_*c 0
0.1
0.2 DEPLETION
0.1 OEPTH (pm)
IO"
=
10’6
0.2
Figure 29. Carrier profiles in uniformly doped, n-type (1.5 x 10” cmJ) InP etched in either a lC,&:lOH, or 19CCI,F,:lO, discharge for 4 min, as a function of post-RfE annealing temperature (30 s anneals).
0, /-
_.-.-._.-.-s-0
=0.2
.E I-
i
-
I
30.4 E s 0.6 -
I Au-InP-RIE
0.8 1.01
0.5
I 0.4
I
-
CONTROL
---
CZH</Ar
-*-
CChF2 /02
I
I
0.3 0.2 REVERSE BIAS (VR,
I
I
I 0.1
0
Figure 30. Reverse bias Z-V characteristics from Au contacted n-type M (n = 6 x 1015 cm-9 after etching in lC,H&OH, or 19CCl,F,/O, discharges prior to Au deposition. The reverse breakdown voltage on the control sample was - 2.5 V.
Wet and Dry Etching
409
6000
InP 6400
24001600 1200 *--+__
150
ww42
GRAZING ANGLE ~~~~~*CONTROL -AS-ETCHED 4DO.C. 30 s ----_
220
----a
360 260 CHANNEL NUMBER
430
500
Figure31. Ion channeling spectra from InP reactively ion etched in a lC,&:lOH, discharge for 4 min, and after annealing at 4OO’C for 30 s. All spectra were measured in glancing angle geometry to improve the depth resolution. The bottom figure shows the same spectra plotted with an expanded vertical scale.
Based on these results we can postulate the picture of dry etch damage in InP shown in Fig. 32, in which the immediate surface (150 A) is highly disordered and non-stoichiometric. Below this region there is another, ranging in depth from 150-400 A, in which there is significant lattice disorder, both defect aggregates detectable by channelling and point defects which compensate the shallow dopants. This region is stoichiometric. Below this intermediate region there is point defect introduction to occur a depth of -1000 A, which also compensates the doping. A novel method for non-destructively measuring damage depths has been described by Wong et a1.l63land As et al.l64l Figure 33 shows low temperature luminescence from a multi-quantum well structure before and after exposure to an 4 plasma with -300 Vdc bias.l65l Since each line in the spectra uniquely originates from a quantum well at a known depth, the decrease in luminescence intensity can be used to plot the apparent damage depth for each different plasma condition, as shown in Fig. 34. To gain some idea of how sensitive various device structures are to the introduction of damage during dry etching, we exposed conventional high electron
410
Compound Semiconductors
mobility transistor (HEMT) structures to oxygen plasmas, either with a 410 A GaAs capping layer in place, or with this cap removed by wet chemical etching, so that the doped AlGaAs donor layer was exposed. By having source and drain ohmic contacts in place prior to the 0, plasma exposure, we were able to measure the change in saturated drain-source current (I,,,) as a function of the dc bias on the sample during this plasma exposure. Figure 35 shows that with the GaAs cap layer in place, such as would be the case during trilevel resist pattern transfer, the threshold bias for damage introduction is - 150 V. This corresponds to the approximate ion energy which will cause defects to penetrate the GaAs cap layer and enter the AlGaAs donor layer, where they remove carriers from the conduction process. As mentioned in Sec. 3.3, the range of 150 eV O+ ions is far less than 4 10 A, and the explanation of these results must invoke diffusion of defects created at the surface deep into the semiconductor. When the GaAs cap is removed, as is the case when a gate mesa step is performed, the threshold ion energy for damage introduction is < 100 eV. To be on the safe side, our plasma processes for IIEMTs use dc biases of 150 V. Figure 36 shows the percentage change in I,,, as a function of the plasma exposure time for different dc biases on the sample. For extended times, one can see significant degradation in I,,, even at -15 0 Vdc with the cap in place. These results emphasize that over-etch times must be kept short, a need which is reinforced by the fact that resist erosion must also be avoided.
<15oti
150-4ooIj
400
Figure 32.
- 10ooA
HEAVILY DAMAGED NON-STOICHIOMETRIC
(In RICH)
HEAVILY DAMAGED STOICHIOMETRIC POINT DEFECTS ELECTRICAL COMPENSATION ANNEALED AT 500°C
Schematic of InP near-surface
region after RIE
Wet and Dry Etching
411
i fbl ECR+RF
1.4
1.6
1.6
2.0
ENERGY (6’4)
Figure 33. Low-temperature (5 K) PL spectra from GaAs-AlGaAs MQW structure before (top) and after (bottom) exposure for 2 min to a 150 w (microwave), 300 V bias Hz plasma (10 mtorr).
I
1SiWELL
30 i WELL
50 i WELL
0’ 1OW
1500
2ooo
DEPTH (A,
Figure 34. Normalized PL intensity from individual wells in the MQW structure, corresponding to different depths in the sample, after H or Ar plasma exposure with 200 or 300 V on the sample.
412
Compound Semiconductors
120 IHii
100 /-
UJ 4 _
4
80 I-
# w$ s 9
60I-
t
4cI-
O2 PLASMA 90 6CCrtl 30 mTon 5 min
_
-__
\\ ‘N, \\ ‘\ \\ \\ I ‘\ ‘\ \ ‘\ :\ ‘\ \, ‘\ ,1 ‘l \ \\ i \, ‘\, \\ ‘\ \ ‘\, 1 ‘\
ETCHED
Figure 35. Percentage change of I ass in HEMT structures exposed to an 0, plasma, either with or without the GaAs cap in place.
‘\ ‘\
CAP
. DC BIAS + MICROWAVE 2c l-
UNETCHED
CAP
0 DC BIAS ONLY 0 DC BIAS + MICROWAVE cIO
I
t
100
200 DC BIAS
(150 W)
I 300
1
,
(V)
120 I+EMT 02 PLASMA 90 seem 30 mTorr
llO-
Figure 36. Percentage change in I ass of HEMT structures as a function of the time exposed to a 30 mtorr, 90-seem 0, plasma at biases of -150, -200, or 400 V on the sample.
S $2 P S 4030 -
\
\
\
\
\
20 -
\ \
lo0
0 150 Y BIAS . 200” ot*s . 400 “BIAS \
\
\
\-
I 0
5 PLASMA
_____ 10 EXPOSURE
15 TIME (min)
Wet and Dry Etching
413
Heterojunction bipolar transistors (HBTs) require a number of patterning steps which are conveniently performed using dry etching. In particular, one must etch to the base layer and also to the sub-collector in order to deposit contacts. One would expect HBTs to be less sensitive to damage introduction during dry etching because the doping in the layers is so high (typical base doping is 2 5 x 10lg cm3 and sub-collector doping is 2 3 x lo’* cm”) and the layers are relatively thick, compared to HEMTs. Figure 37 shows a schematic of transmission line patterns on a wet etched mesa structure that was used for 0, or Hz plasma exposure experiments to determine the ion damage thresholds. P61 With this structure, an increase in base or sub-collector layer resistance can be measured as a function of the dc bias on the sample during the plasma exposure. Figure 38 shows the variation of these resistances with dc bias during 5 min exposures. For 0, ion bombardment, the collector resistance shows only minor (110%) increases for biases up to -200 V and more rapid increases thereafter. This resistance is mostly determined by the contribution from the lightly doped n-region, rather than the n+ contact layer, and indicates that bombardmentinduced defects penetrate at least 500 8, of GaAs for oxygen ion energies of 2200 eV. The base resistance displays only a minor increase (-10%) over the pre-exposure value, even for oxygen ion energies of 375 eV. This is a result ofthe very high doping in the base, which is difficult to disrupt. More significant increases in both collector and base resistances were observed for hydrogen ion @I+, v) bombardment, due to the extra effect of hydrogen passivation of both acceptor and donor dopants in the structure. 500 i, Ga&(Sn)
n = 1.5 x 10IQ IX+
7000 A GaAs(Sn) n = 1.2 x 1016 crrf3 2100 A GaAs(C) p = 6.8 x 10lg crd SI SUBSTRATE GAPS = 2.4.8.16 pm
S I SUBSTRATE
Figure 37. Schematic of transmission plasma exposure experiments.
line patterns on the mesa diode structures used for
414
Compound Semiconductors 200
500
! 857 Q/O (4tW.9
1 mTorr
5 MIN O2 PLASMA H2 PLASMA
-
;
i
/
$
/
F?l - 150 2
/
5 R
v, Y
-
loo
P g n
m
3
B 1001
Figure 38.
Variation
-1
,
- 50 I
-100 -200 -300 400 DC BIAS DURING PLASMA EXPOSURE (V)
of base (p’ GaAs) and collector (n-GaAs)
sheet resistances as a
function of the dc bias on the sample during exposure to either an 0,
or Hz discharge.
The introduction of deep-level recombination centers was evident from the increase in ideality factor for increasing dc biases on the sample during the plasma exposures. Figure 39 shows that the n values increase significantly for biases above -200 V for both types of discharge. Oxygen plasma damage was more resistant to annealing than that produced by hydrogen discharges, provided the energies of both types of ions were kept below -300 eV, annealing at 450°C for 5 min restored most of the original conductivity. For higher ion energies, irreversible damage to the GaAs was created. 3.5
Masking Materials
The choice of mask material depends on the discharge chemistry, the pressure and dc bias, all of which determine the removal rate of the mask. In the case of CH,/H,/Ar, where significant polymer deposition may occur on the masked areas, it is necessary to use a masking material from which this polymer can be removed (e.g., by 0, plasma cleaning). Figure 40 shows SEM micrographs from InP etched in CH,/H, /Ar with -150 Vdc
Wet and Dry Etching
415
1.80
1 mTon 5 MIN l
c 8
02 PLASMA
b H*PuSMA
E; 2
1.75 -
z 3
-100
-200
DC BIAS WRING
-300 PLASM4
EXPOSURE
-400 (V)
Figure 39. Ideal@ factor of an n+ np+ diode as a function of the dc bias on the sample during either 0, or I-J plasma exposure.
bias on the sample. For the case of W masks, sputtering occurs for selfbiases 2125 V, leading to micromasking and the appearance of grass on the surface. In the case of photoresist masks, substantial polymer deposition occurs, and for large etch depths (2 2 pm), so much polymer and etch products accumulate on the photoresist that it becomes difficult to lift off. Under these conditions, it is preferable to use SiO, as a mask because of a lesser amount of polymer deposition on this material. A common feature of mesa structures, formed by dry etching of III-V semiconductors, is the presence of correlations or ribbing on the mesa sidewalls. Most of this sidewall roughness results from a replication of the roughness present at the edges of the masking material on the semiconductor. Figure 4 1 shows SEM micrographs of various photoresist patterns on InP prior to any etching. The AZl35OJ, shown at left, has a very ragged sidewall with pronounced ribbing. By contrast, Hunt 1182 resist, shown at center, has much smoother sidewalls. The resist 5209E, shown at right, had sidewall roughness intermediate between the other two. Following plasma etching in CH&Q/Ar, the photoresist masks were removed in acetone, and SEM pictures taken of the resultant mesa sidewall on the semiconductor. Figure 42 shows that for a sample etched with an AZ135OJ mask, the sidewall roughness is simply a replication of the initial morphology of the resist mask. This illustrates the extreme fidelity of the pattern transfer. By contrast, the sidewall of the InP etched with a much smoother Hunt 1182 resist mask shows no visible roughness.16’l
416
Figure
Compound
40.
SEM micrographs
W (microwave) mask.
Semiconductors
from InP etched in 5CH4/17H2/8Ar
discharges with
either a W (top), photoresist
The masks are stilI in nlace.
at 1 mtorr, 150 V, 150
(center)
or SiO2 (bottom)
Wet and Dry Etching
417
Fig. 41. SEM micrographs of photoresist masked areas on InP substrates.The resist types are AZ1350J (top, center, and bottom left), Hunt 1182 (top, center, and bottom in the middle of the figure) and 5209E (top, center, and bottom right).
Figure tures
42.
SEM micrographs
etched
AZI350J
into
InP
resist (top)
resist (bottom).
using or Hunt
In both
resist has been removed.
of feaeither 1182
cases the
418
Compound
Semiconductors
An example of sidewall roughness developing during the plasma exposure is shown in Fig. 43. In this case, photoresist is being used as the mask to transfer a pattern into a 3000 A thick SiJN4 underlying layer with a CF 4/02 (4 rntorr, -500 Vdc) discharge. The initial resist profile is shown at top left, and after 1 rnin plasma exposure (top right) there is no discernible change in the resist and a slight etching of the SiJN4. After 2 min plasma exposure (bottom left), the sidewall roughnessis apparent and this continues to get worse after 3 min (bottom right). This roughness is then transferred into the SiJN4 sidewall.
1 p;m Figure
43.
SEM
micrographs
of photoresist
profiles
on a SiJN4 layer prior to plasma
exposure (top left) and after 1 min (top right), 2 min (bottom left) and 3 min (bottom right) exposure to a 4 mtorr, -500 W dc, CF4/O2 discharge.
The effect of mask erosion during semiconductor mesa etching may only be obvious in very narrow features. Figure 44 shows SEM rnicrographs of a 1 I.1mwide feature etched into InP at -150 V dc in a CH4~/ Ar plasma, using a 3000 A SiO2 mask. The narrowing of the mask during the dry etch step leads not only to a sloped sidewall, but trenching at the base of
Wet and Dry Etching
419
the mesa due to ions which follow a glancing angle trajectory off the sidewall and are concentratedat its base. For CH4~-based dry etching of deep features, we have found that At or TiAu masks display low erosion rates.
Figure
44. SEM micrographs
of features etched into InP using a I mTorr CH4/H2/Ar
(150
W ECR, -150 Vdc) discharge using an SiO2 mask, which is still in place.
For dry etching ofGaAs with chlorine-based discharges,metals such as Pt, Au, Mo and Ni make robust maski~g materials. Figure 45 shows the removal rate of various metals in PCI3/Ar dischargesas a function of the dc bias on the sample during the plasma exposure. Similar data is shown in Fig. 46 for HI/Hz/Ar discharges. In this case,Ni, Mo, Au and Pt also show the lowest erosion rates.
420 Compound Semiconductors
2% )10 PCl@Ar 10 mTon, 250 W MICROWAVE 2ocl-
Figure 45. Removal rates of various masking materials in F’CI,/Ar discharges as a function of the de bias on the sample.
WC f ,50l‘5
0 Ni 0 MO 8Al opt .Au
4 /-
50
0 0
DC BIAS IV-J
lZO# 10H1/10H2/5Ar 10 mlorr 250W MICROWAVE
loo-
. 0 A A 8 0 v V x
PHOTORESIST Au SiN SiO2 Al TI MO Ni PI
/
Figure 46. Removal rates of various masking materials in HI&/Ar discharges as a function of the dc bias on the sample.
/
.
RP
oo3
zo-
‘0
//’ /p ‘0
DC BIAS
//
/’
_-
(V)
0
-
Wet and Dv Etching 3.6
421
Electron Cyclotron Resonance Discharges
Various methods have been developed for reducing ion energies in the discharge, while trying to maintain an isotropic etching. These include the socalled triode reactor, in which a second plasma-generating electrode is included within the process chamber, or the addition of magnetic fields configured to reduce electron loss from the discharge, and thus, to reduce the potential between it and the sample. This type of magnetically enhanced etching is generally divided into two types: magnetron RIE or ECR plasma etching. The basis of ECR discharges is the principle of synchronously coupling power into electrons confined to move along particular paths by an external magnetic field.16*l In this sense it is an advance on magnetically-enhanced discharges because of the addition of an external driving force which heats up the electron distribution. Magnetically-enhanced discharges work on the principle that magnetic confinement of the discharge produces a greater degree of dissociation by forcing electrons away from the chamber walls and back into the plasma. The reduced loss of electrons to the walls also reduces the dc bias induced on the small electrode. For the case of ECR discharges, the magnetic field plays an additional role. At a magnetic field strength of 875 G, electrons within the plasma move in circular orbits with a rotational frequency of 2.45 GHz. If an electric field of 2.45 GHz radiation is now applied, it is synchronous with the electron velocity, obviating the need for a high collision frequency to couple in power. This resonant transfer of energy to the electrons leads to efficient operation at lower pressure than conventional discharges used in RIE and a high ionization efficiency. The resultant low energy (I 15 eV) ions have enough energy to activate many etching processes, but not enough to create significant damage. ECR sources also offer electrodeless operation and low sheath potentials, and hence, no sputtering. Even though the ion energies are low, an isotropic etching is maintained because of the low pressure, and the fall-off in etch rate is compensated by the higher dissociation of the ECR discharge. Figure 47 shows a multipolar, tuned-cavity source design.16*l The resonant cavity is a brass cylinder terminated at the top by an adjustable short. A variable-length launching probe enters the side of the resonant cavity, impressing microwave energy from a magnetron/waveguide assembly to an evacuated quartz cup in which the plasma resides. The brass resonant cavity is at atmosphere. Within the baseplate are eight high-strength rareearth magnets which produce the B field necessary for resonance.
422
Compound Semiconductors
f5:.::.:. 5. ::2. ::5
B FIELD
f
*.* j: .a:
Figure zones.
47.
Top cross-sectional
MAGNET
view of multipolar ECR source showing ECR heating
These highly efficient microwave plasmas can be combined with additional rf biasing of the sample position to produce a versatile dry etch system for III-V device processing. Figure 48 shows a schematic of one such system built by Plasma Therm, together with the multipolar tunedcavity microwave source (Wavemat Model 300) described above.169J170] The sample is transferred into the etching chamber from a load-lock and the system pumped with a 1500 lsec-’ turbomolecular pump. The advantage of the hybrid ECR-RF approach over conventional RIE can be stated quite simply; at any given dc bias, ECR-RF will provide a faster etch rate than RIE alone, because of the more dissociated plasma. Equivalently, ECR-RF will provide the same etch rate as RF (RIE) alone, but at a lower dc bias. Hence, one can still achieve practical etch rates, but at a lower bias, and consequently, with lower damage.
Wet and Dry Etching
423
SLIDING SHDRT --
CAVITY
_. .__ ---
k%
ROWAVE INPUT PROBE /ATER COOLING INDARY RING
VAClJtiii PUMP
DC BIAS
Figure 48.
&INPUT RF
Schematic diagram of multipolar ECR plasma-etching
TEMPERATURE CONTROLLED LOWER ELECTRODE
system.
Figure 49 shows a schematic setup for measuring the average electron density in an ECR-RF discharge, using a microwave interferometric technique.l71l The variation of average electron density is shown in Fig. 50 as a function of microwave power for 1 mtorr, 88 V (10 W rfl discharges of CH,kIJAr and CCI,F,/O,, together with the etch rates of InP and GaAs respectively, in these mixtures. The etch rates of both materials increase rapidly with increasing microwave power, as do the electron densities. This is expected since there will be a higher density of active species available for etching at high microwave powers. The high electron density values, as compared to those for RIE, are a powerful demonstration of the ability of the ECR source to enhance the etch rates at fixed dc bias. SEM micrographs of selected surface morphologies are shown in Fig. 5 1. For microwave powers of I 150 W, the InP surfaces are featureless but above 200 W become progressively rougher until, at 300 W, the morphology is particularly bad. Auger analysis showed substantial In enrichment as a result of the preferential removal of P at high microwave power levels. In the case of GaAs etching by CCl,F,/O,, the surface remains smooth even for high microwave powers.
424
Compound Semiconductors
SLIDING
n
Figure 49. Schematic measurements.
representation
m -
SHORT
MICROWAVE INPUT PROBE
of the experimental
setup for electron
,
density
10,000
1 mTorr 1OWRF A 0 A 0
10’0
5 CH4/17 Hz/8 Ar; InP 28 CC12F2/2 02; GaAs
‘; .E E
I 0
IO 100
MICROWAVE
300
200
POWER
(W)
Figure 50. Average electron densities 4 cm below the ECR source baseplate for 1 mtorr, 10 W (rt) CH&&/Ar or CCI,F,/O, discharges (total flow rate 30 seem) and etch rates of InP and GaAs, respectively, in these discharges, as a function of microwave power.
Wet and Dry Etching
425
Figure 51. SEM micrographs of InP etched in 1 mtorr, 10 W (rt), 5CH4/17H2/8Ar discharges with 150 W microwave power (top left-hand side) and 300 W microwave power (top right-hand side). The samples at bottom are GaAs etched in 1 mtorr, 10 W (rt) 28CC12F2/202discharges at 150 W (left-hand side) and 300 W (right-hand side) microwave power. The flow rate in both caseswas 30 sccm.
Lower levels of ion-induced damage are present when microwave ECR discharges are used, because of the lower ion energies relative to conventional rf plasmas. An example of the relatively benign nature of ECR etching, with regard to InP, is given by the forward I-V measurements shown in Fig. 52. Samplesetched under ECR conditions with no additional biasing gave I-V characteristics very close to those of an unetched control sample with a barrier height of 0.48 eV and ideality factor of I.1. Our past experiencewith RIE of loP using the CH4~/ Ar chemistry, has been that gold deposition onto the RIE surface results in ohmic behavior, and a rectifying characteristic is not observed until at least 100 A has been removed from the sample by wet chemical etching, prior to the Au deposition. With RIE we observe substantial In enrichment of the near-surface region, but to much greater depths than with ECR. Even with the addition of 100 V substrate bias during the ECR etching we observeonly a relatively
426
Compound Semiconductors
small reduction of the (bn to 0.44 eV, while the ideality factor shows a greater degradation, to a value of 1.6. This is a convincing demonstration of the much lower degree of disruption to the semiconductor surface, caused by ECR discharges as compared with conventional RIE.1721.
InP CH4/ H2/Ar
---
ECR + 1OOV
Figure 52. Forward current-voltage characteristics from Au-InE’ Schottky diodes etched in ECR 5CH,/15H2/7Ar discharges (0 or 100 V substrate self-bias) prior to deposition of the Au contacts. The straight lines in each case are used to give the intercept and slope of the characteristic. The ECR + 0 V sample had forward I-V curves very close to those of an unetched control sample.
3.7
Device Processing
Heterojunction bipolar transistors, based on InGaAs/AlInAs or InGaAsiInP, have attracted great attention because of their outstanding high frequency performance and lower power requirements compared to GaAs/AlGaAs devices.l73ll74l To achieve a reasonable scale of integration, it is necessary to develop a manufacturable dry-etch, self-aligned processing technology. There have been reports of fabrication of small area (2 x 4 nm2) InGaAs/AlInAs HRTs using CH,/H,/Ar ECR plasma etching.l75ll76l A schematic of the completed device structure is shown in Fig. 53. A maximum current gain of 160 was obtained for 3 x 4 pm2 devices, and up to 80 for 2 x 4 pm2 devices. Unity gain, cutoff frequency (fr) of 80 GI-Iz, and maximum frequency of oscillation (fW) of 100 GHz have been
Wet and Dry Etching
427
demonstrated with this process (Fig. 54) which features triple self-alignment of the emitter and base metals, and the base mesa in order to minimize the base-collector capacitance (C,,). To prevent sputtering of the Aubased ohmic contacts which serve as dry etch masks, a thin (2000 A) layer of Ti was evaporated on top of the Au. This layer is particularly resistant to erosion by the etch mixture. The Ti can easily be subsequently removed in dilute HF. An SEM of a nearly complete device is shown in Fig. 55.
InP SUBSTRATE
Figure 53. HBT.
Schematic cross section of the completed triply self-aligned AIinAsOnGz~4s
01 0.1
I
I
1
10 FREQUENCY
Figure 54. Microwave characteristics HBT.
I
1 IO
(GHr)
of 2 x 4 pm2 dry-etch, self aligned AlInAsRnGaAs
428
Figure
Compound
55.
Semiconductors
SEM micrograph
of AllnAs/lnGaAs
HBT
showing
dry-etched
mesas.
A self-aligned HBT processing sequencefor GaAs/AlGaAs devices is shown in Fig. 56.[77] A lift-off AuGe-based emitter metal provides a metal mask for RIB of the emitter mesa. To achieve the required sidewall profile, the emitter etch was performed with a combination of low bias (-90 V) CCI2F2 RIB, and AIGaAs selective wet etching (KI/I2) steps. The etching provided a fully depleted 300 A thick AIGaAs band around the perimeter of the emitter, as shown in Fig. 57. This thin layer serves as a guard ring to reduce the surface recombination current and maintain the dc current gain in the device, particularly at small geometries. A somewhatsimilar processcan be usedfor fabrication of pnp GaAs/ AIGaAs HBTs. The layer structure grown by metal organic molecular beam epitaxy is shown in Fig. 58. All the mesaswere defined by CH4~/ Ar ECR etching and the base mesa was self-aligned to emitter stripe by using a SiN sidewall on the emitter stripe (Fig. 59). A series of SBM micrographs showing the pnp HBT at various stages of fabrication is shown in Fig. 60.[78] Common-emitter characteristics of a 2 x 4 J.1m2 emitter dimension device are shown in Fig. 61. The Early voltage is > 150 V, with a collector-to-emitterbreakdownvoltageof -5 V. The fT is 30 GHz and fMAX is 13 GHz for these devices, the highest reported for pnp HBTs. comparable npn devices have fT values of 53 GHz and fMAXvalues of 128 GHz.
Wet and Dry Etching PROCESS
ISOLATION
FLOW OF SELF-ALIGNED
IMPLANTATION
GaAslAIGaAs
SELF ALIGNED
HBT
E-B METALLIZATION
*____
___-*
SELF ALIGNED
EMITTER
429
BASE MESA ETCHING
OHMIC METALLIZATION
A
EMITTER
MESA DRY ETCHING AND A!GaAs GUARD RING FORMATION (RIE AND SELECTIVE WET ETCHANT)
Figure 56.
Schematic
cross-section
COLLECTOR
of self-aligned
HBT
METAL CONTACT THROUGH
process
sequent:.
OHMIC METALGaAs ACGaAs / GUARD RING
Figure 57.
SEM
view
of thin
AlGaAs
guard
ring around emitter mesa periphery.
430
Compound Semiconductors
2500 A
5ooA
GaAs
p z
4 x 10ZO
AlGaAs + GaAs
D 2:
10”
8OOA
Al,.,,Ga,.,,As
2ooA
AI,.,,Ga,.,,As
p 2 3 x lOI undoped
50A
undoped
6ooA
GaAs
n z l-5 x lolP
3oooA
GaAs
p ‘c 5 x 1o16
5oooA
GaAs
D ‘v 4
X
102’
SI GaAs substrate
Figure 58. Layer structure of MOMBE-grown
pnp HBT.
S I substrate
Figure 59.
Cross-sectional
view of completed GaAs/AlGaAs
pnp HBT.
Wet and Dry Etching
431
Figure 60. SEM views of dry etched mesas on GaAs/AIGaAs pnp HBTs.
Figure
61.
Common-emitter
characteristics
of 2 x 4 J!m2 pnp HBT
(IB step = 40 j!A).
432
Compound Semiconductors
HEMTs are ideally suited for application of dry etching techniques, since the gate recess formation involves selective removal of a GaAs contact layer from an underlying doped AlGaAs donor layer. A second application is the patterning of trilevel resist masking layers used for achieving submicron gate widths. Both enhancement and depletion mode HEMTs can be reproducibly fabricated on the same wafer using thin etchstop layers inserted in the structure. An example of a direct-coupled FET logic inverter, consisting of D-mode unsaturated resistors and E-mode HEMTs, is shown schematically in Fig. 62.[7gl Control of the threshold voltage and saturation currents over the wafer was achieved by the use of two etch-stop layers of Al,,,Ga,,,As and pseudomorphic Iq,G%.,As. The dry etching was performed with CCl,F, at a dc bias of I -50 V. The InGaAs was removed with an ammonium hydroxide solution, in order to continue dry etching down to the AlGaAs etch stop.
ungated
saturated -0hmlc -
undoped sem
Figure 62.
-msubbng
buffer
metal
GaAs InGaAs GaAs AlGaAs AIGaAs
layer
substrate
Cross-sectional view of DCFL
inverter.
Pseudomorphic InGaAs HEMTs have demonstrated state-of-the-art millimeter wave power performance with respectable power amplification at frequencies as high as 94 GHz.[*~I In order to obtain high power from pseudomorphic HEMTs, short gate length and large gate periphery devices composed of multiple finger transistors are required. In order to achieve a T-gate profile, a bilayer e-beam resist system was used, which included high sensitivity resist, a copolymer of methylmethacrylate and methacrylate acid, and low sensitivity resist, polymethyl methacrylate. The gate recess
Wet and Dry Etching
433
etching was performed with CCI2F2 at pressures of 1-20 mtorr and dc biases of -15 to -50 V. Post dry etch rinsing in NH4OH solution was used to remove etch-related residues. SEMs of developede-beam resist and liftoff T -shape gate metallization after gate recess etching are shown in Fig. 63. Extrinsic transconductancesof 437 mS.mm-l and output conductances of 10 mS.mm-l were obtained for 0.25 J.lmdevices, with threshold voltage uniformities of :f: 85 mV in comparison to :f: 300 mV for conventional wet recesstechnology.[81]
Figure
63.
SEM micrographs
off T -shape gate metallization
of developed e-beam resist (right, top and bottom) and lift(left, top and bottom)
after gate-recess etching.
ECR plasma etching can also be usedin the fabrication oflno.2Gao.sArGaAs strained quantum well self-aligned, ridge waveguide lasers.[S2]The p-ohmic contact stripes are usedas the dry etch masks and are not degraded by the plasma exposure, provided the self-bias is kept low. This type of laser emits at 0.98 ~m and is currently being extensively investigated for application as pump lasers for Er-doped glass fiber amplifiers. Selfaligned ridge waveguide laser structures were fabricated using front 2- 7 ~m wide AuBerri/Au p-contacts patterned by lift-off and full area Au/Sn/ Au n-contacts. The p-contacts were used as etch masks for a PCI3/Ar, 1
434
Compound Semiconductors
mtorr, -80 Vdc discharge. Figure 64 shows the etched depth as a function of plasma exposure time for different microwave power levels. The etch depth increases linearly with time, and the etching is faster at higher microwave power levels. Lower dc biases can be used at the expense of etch rate. The advantage of the lower ion energies in ECR etching, relative to RIE, is that one can stop arbitrarily close to the multiple quantum wells without degrading the light output of the laser. SEM micrographs of small geometry structures are shown in Fig. 65. Threshold currents typically less than 5 mA were obtained at room temperature for small (2 pm) lasers with external quantum efficiencies of 60-70% for as-cleaved devices (Fig. 66). These results were obtained without further chemical cleanup of the dry etched lasers, and indicates there is no significant damage introduction into the quantum wells by the ECR discharge.
1= .. InGaAs - GaAs GRINSCH
/
0 0 W MICROWAVE n 100 W MICROWAVE A 200 W MICROWAVE
a TIME (min)
Figure 64. Etch depth in the GaAs-InGaAs GRINSCH structure as a function of time and microwave power level for dry etching in a 7PCI,/lOAr, 1 mtorr plasma with -80 V bias on the sample.
Wet
Figure
65.
SEM micrographs
of dry-etched
similar device that was stained to highlight
Figure
66.
CW light-current
room temperature.
characteristics
and
ridge waveguide the layer structure
Dry
Etching
435
structure (top) and from a (bottom).
of a 2 x 254 ~m ridge waveguide
laser at
436
Compound
Semiconductors
As a final example of the use of dry etching, Fig. 67 shows SEM cross-sectional views of small diameter, whispering gallery mode microdisk lasers fabricated by ECR CHJH2/ Ar dry etching and selective HCI wet etching of the thick loP layer under the IoGaAs/InGaAsP quantum wells. [83] This highly confined optical structure nearly optimizes the overlap of small volume quantum well gain region with high reflectivity optical modes in high index contrast disks. These lasers may form the basis of efficient photonic circuits and arrays.
Figure
67.
SEM views of whispering
gallery mode microdisk
lasers.
Wet and Dry Etching 4.0
437
CONCLUSION
Control of etch rates, etch selectivity and sidewall profile are becoming increasingly important, as processing of compound semiconductor devices is ever more exacting. Virtually all device fabrication requires a number of wet and dry etching steps. Low damage etching and deposition using enhanced plasmas is now a key feature for electronic and photonic devices. Continued work on process integration is perhaps the biggest need.
ACKNOWLEDGMENTS The collaboration in this work of F. Ren, T. R. Fullowan, J. R. Lothian, R. Esagui, C. R. Abernathy, W. S. Hobson, U. K. Chakrabarti, V. Swaminathan, A. F. J. Levi, A. Katz, R. F. Kopf and J. M. Kuo from AT&T Bell Laboratories, and C. Constantine and D. Johnson from Plasma Therm is greatly appreciated.
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438
Compound Semiconductors
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25. Lothian, J. R., Kuo, J. M., Ren, F., and Pearton, S. J., Plasma and Wet Chemical Etching of Ih.sGab.sP, J. Electron. Mater., (in press)
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40. Einspruch, N. G. and Brown, D. M., Plasma Processing for KW, Academic Press, Orlando ( 1984) 41. Pear-ton, S. J., Hobson, W. S., Chakrabarti, U. K., Derkits, G., and Perley, A., J. Electrochem. Sot., 137:3892-3901 (1990) 42. Pearton, S. J., Hobson, W. S., Chakrabarti, U. K., Derkits, G., and Perley, A.,J. Vuc. Ski. Technol., B8:1274-1281 (1990) 43. McNevin, S.,J. Vat. Sci. Technol., B4:1203-1218 (1986)
44. Niggebrugge, U., Klug, M., and Garus, G., Inst. Phys. Conf 79:367-372
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45. Hayes, T. R., Dreisbach, M., Thomas, P., Dautremont-Smith, Heimbrook, L. A., J. Vuc. Sci. Technol., B7:1130-1410 (1989)
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46. Pear-ton, S. J., Chakrabarti, U., Katz, A., Perley, A., Hobson, W. S., and Constantine, C., J. Vuc. Sci. Technol., B9:1421-1432 (1991) 47. Pearton, S. J. and Hobson, W. S., Appl. Phys. Lett., 56:2186-2188 (1990)
48 Pearton, S. J., Hobson, W. S., Geva, M., Chakrabarti, U., Lane, E., and Perley, A., Plasma Chem. Plasma Proc., 11: 295-3 11 (199 1) 49. Pearton, S. J., Chakrabarti, U., Lane, E., Perley, A., Abernathy, C. R., Hobson, W. S., and Jones, K. S., J. Electrochem. Sot. , 139:856-864 (1992) 50. Pearton, S. J., Chakrabarti, U., Katz, A., Ren, F., and Fullowan, T. R., High-Rate, Anisotropic Dry Etching of InP in HI-Based Discharges, Appl. Phys. Lett., 62:2411 (1992) 5 1. Pearton, S. J., Ren, F., Lothian, J. R., Fullowan, T. R., Kopf, R., Chakrabarti, U., Hui, S., Emerson, A., Kostelak, R., andPei, S. S.,J. Vuc. Sci. Technol., B9:2487-2496 (1991) 52. Pear-ton, S. J., Chakrabarti, U., Hobson, W. S., and Kinsella, A., J. Vuc. Sci. Technol., B8:607 (1990)
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Rapid Isothermal Processing (RIP) Rajendra Singlt
As a stand-alone system, rapid isothermal processing (RIP), based on incoherent radiation as the source of energy, is currently being used in the manufacturing of some gallium arsenide integrated circuits (IC’s). The fabrication of most advanced compound semiconductor IC’s and advanced photoelectronic integrated systems will require maskless all ultrahigh vacuum integrated sequential processing concepts. As a single-wafer processing technique, RIP will play a major role in the cost effective flexible fastcycle-time manufacturing of IC’s and photoelectronic integrated systems. Photoeffects play an important role in RIP. The use of vacuum ultraviolet (VW) and ultraviolet (W) incoherent light sources, in conjunction with tungsten halogen lamps, can further reduce the processing temperature. Measurement of thermal stress and its correlation with the heating and cooling rates can lead to the processing of material and devices with minimum defects introduced during RIP. This chapter presents an overview of RIP.
1.O
INTRODUCTION
During the last three decades, the phenomenal growth and success of the integrated circuits (IC’s) industry has been made possible by the incredible advancement in the processing technology. In addition to the development 442
Rapid Isothermal Processing (RIP)
443
of single technology based chips, in the future, system integration will require hybrid or merged technology. Such complex systems may have silicon, compound semiconductors, and even newly discovered high temperature superconducting devices on the same substrate. In the case of optoelectronic systems, the trend is toward quantum phenomena based devices, as well as the integration of optoelectronics and submicron CMOS on Si substrates.1’1 The development of full-wafer technology for largescale laser (based on single quantum well, graded index, separate confinement heterostructure) processing is one example of an advanced optoclectronic system.121 From the device performance and reliability point of view, lower thermal budget (integral of processing time and temperature) processing is a necessity for the realization of the next generation of microelectronic and optoelectronic systems. Processing time and temperature are the two basic parameters that control the thermal budget. As a short time processing technique, rapid isothermal processing (RIP)131-[*I based on incoherent radiation as the source of energy is being used by several Si and GaAs IC manufacturers for different processing steps. In several recent publications,191-1121we have shown that, due to differences in the radiation spectrum of the energy source, there are fundamental differences between RIP and furnace processing. As compared to furnace processing, the photochemical and photophysical effects associated with RIP provide lower substrate temperature processing capability. The addition of incoherent ultraviolet (UV) and vacuum ultra violet (VUV) light sources in the currently used RIP equipments can provide further reduction in the processing temperature. Thus, the well established reduced thermal mass feature (leading to short time processing) of RIP, coupled with the reduced processing temperature feature, can lead to further reduction of the thermal budget. In addition to the reduced thermal budget processing, cost effective flexible fast-cycle-time device manufacturing is also a major challenge for the microelectronic and optoelectronic industry.1131tr41 Rapid isothermal processing will play a major role in single-wafer integrated semiconductor device processing as well as the processing of large area devices such as solar cells. The objective of this chapter is to provide an overview and also to discuss future trends in RIP.
2.0
WHY RAPID ISOTHERMAL
PROCESSING?
As mentioned earlier, current trends in integrated circuit development are in the direction of devices with minimum feature sizes in the nanometer
444
Compound Semiconductors
dimension. Future devices require shallower junctions, higher doping levels, and reduced defect densities. Thermal processing is an integral part of integrated circuit fabrication and is required for a number of steps, e.g., activation of implanted dopants, annealing of implantation damage, dielectric formation, etc. In order to avoid unwanted physical phenomena that can degrade the performance and reliability of the circuit, impurity redistribution, both in horizontal and vertical directions, should be minimized. There has been considerable interest recently in reducing the thermal budget. Reduction of the processing temperature has been successful in many cases where the desired reaction can be produced below the temperature where the impurity diffusion is significant. However, certain processing steps require high temperatures and involve both desirable and undesirable phenomena. As an example, during the annealing of ion-implanted semiconductors, activation of dopants and epitaxial growth of semiconductors are desirable phenomena. On the other hand, displacement of dopant profiles is an undesirable phenomena. Diffusion displacement considerations indicate that short time processing can reduce net thermal exposure at any temperature. Also, short time processing can provide faster rates for a desired phenomena than for a possible concurrent undesired reaction (different activation energies for desired and undesired processes). Thus, the objective of short time processing is to basically reduce the process time-temperature product such that desired physical or chemical processes are completed while unwanted processes are suppressed or not given a chance to take place. Thus, short time processing ~51(-lo-*-lo2 set) is the possible solution to many processing steps. Due to the thermal mass of a boat-load of wafers, conventional furnaces cannot be used for short time processing. Also, fast heating and cooling in a conventional furnace may cause for large size wafers to warp or slip. Thus, the inadequacy of conventional furnace annealing in achieving the goal of future microelectronic and optoelectronic devices has motivated the search for alternate thermal processes. Visible and infrared lasers, electron and ion beams, incoherent light, and blackbody radiation from a resistance heater have been used as energy sources for achieving high temperature and short time annealing. These techniques vary over a wide range in the mode of energy transfer from the source to the sample. A major difference between various thermal sources is the time scale in which the energy is delivered to the semiconductor and how it compares with the thermal response time t ofthe semiconductor defined by: t151
Rapid Isothermal Processing (RIP)
Eq.(1)
445
t = &-I
where s is the thermal diffusion length or the sample thickness, whichever is smaller, and k is the thermal diffisivity. The thermal response time t varies from about micro- to milliseconds, depending on the value of k and the absorption depth of the radiation, which depends on the crystallinity and doping of the semiconductor and the wavelength of the radiation. In the case of k = 0.2 cm*/sec and s = 10 urn, t = 5 x 10s6 sec. On the other hand, for s = 375 urn and k = 0.2 cm*/sec, t = 7 x 10e3 sec. Basically, all of the thermal processes can be divided into three groups according to the processing time, with reference to the thermal response time:li51 (i) adiabatic processing, (ii) thermal flux processing, and (iii) isothermal processing. Figure 1(a) shows different types of processing systems with the time duration of various thermal processes. The temperature-depth profile of the three groupsl16l are shown in Fig. l(b). Generally, in the adiabatic processing case, a high-power laser beam is used for a time less than about lo6 set, which is less than the thermal response time of a semiconductor. Regrowth takes place mostly free of extended defects with complete activation, but the surface melts with dopant redistribution in molten regions, and the formation of ripples occurs.l151 The electron beam processing can introduce neutral traps in the dielectric layer. In the case of thermal flux processing, CW lasers or electron beams are scanned over the sample with process times comparable to thermal response times (1 O4 set). The main disadvantage of this method is that although defects are removed from the center of the scanning spot, thermal stresses are introduced at the boundary of the scanning line causing new defects. On the other hand, in rapid isothermal processing, the wafer is heated for more than about l-100 set using incoherent light sources such as tungsten halogen lamps, arc lamps, etc. The light beam is defocused and allowed to fall on the entire wafer which is thermally isolated. Since the beam is incoherent, there are no interference effects between the dielectric overlayer and the semiconductor. Thus, in properly designed systems, no thermal stress between the semiconductor and the dielectric interface is generated, as in the case of laser processing. One of the advantages of rapid isothermal processing over conventional furnace annealing, which takes time in the order of minutes, is that little diffusion of implanted atoms and previously incorporated dopant atoms takes place. Dopants are activated completely. Efficiency of the system is high as a short time is required to process the entire wafer. Low cost, along with minimum overall thermal
446
Compound Semiconductors
budget, low power consumption and high throughput, makes this technique popular not only for microelectronics and optoelectronics but also for future application in other areas such as solar cells, flat panel devices, superconducting devices and magnetic devices. Due to the demonstrated success of incoherent light sources as rapid isothermal processors, no other sources of energy are covered in this chapter.
Figure 1. Schematic showing (a) time duration (Ref. 15) and (a) definition of three heating processes-adiabatic, thermal flux, and isothermal (Ref. 16).
Rapid Isothermal Processing (RIP) 3.0
HISTORY
OF RAPID ISOTHERMAL
44 7
PROCESSING
Historically, the most interesting application of rapid isothermal processing is the Tandoori style of Indian cooking, practiced in North India and believed to be at least 3000 years old.l-‘l In Tandoori style cooking, the cooking materials like thin breads (usually called roti or chapati), nan or small picccs of meat arc prepared to have a low thermal mass. Thermal processors (ceramic dishes, clay side walls of a Tandoori pit, or black metal platters called tava) are heated at temperatures on the order of 400°C and thermal processing (heating the cooking materials by convection, conduction and radiation) occurs in a short time, on the order of 30- 150 sec. The cooking material (chapati, nan, etc.) is slapped onto the walls of the Tandoori pot in a serial fashion and is removed after the processing time is over. The Tandoori style of cooking is remarkably similar in concept, execution and processing time as the presently-used thermal processors from toasters to semiconductor device processors. The driving force behind the development of rapid isothermal processing has been the annealing of ion-implanted silicon vvafcrs. However, GaAs annealing predates Si. The first attempt to anneal ion-implanted GaAs wafers vvas made in 1977 by Surridge and his co-vvorkers.l”l Other u.orkcrsl’xl-1221used flash lamps of various designs as the pulsed source of incoherent light. Lau et al.lz31 used concentrated natural sunlight as the continuous source of incoherent light for regrowing amorphous silicon layers. In 1980, Nishiyama. Arai, and Watanabel21l n-cre the first to use halogen lamps as a continuous source of radiation to anneal boron-implanted silicon for a very short time (6 set), and they found that the activation of implanted boron was determined by maximum temperatures during the annealing process. Since 198 1, the field of rapid isothermal processing has seen phenomenal growth. Current literature is listed in ZGctrical and Electronics Abstracts under the title of “Incoherent Light Anncaling.“1251
4.0
SCOPE
OF RAPID ISOTHERMAL
PROCESSING
For the processing of semiconductor devices, photons, electrons, ions, and plasma arc generally used as energy sources. In the case of photons, the energy sources involve incoherent (various kind of lamps as
448
Compound Semiconductors
well as the resistive heaters) and coherent light sources (lasers) as well as synchrotron radiation. As a research tool, lasers have been studied extensively for rapid thermal processing. However, for commercial applications only incohcrcnt light sources have been used. Synchrotron radiation, in the x-ray to VUV region, is also being studied for semiconductor processing.l’61 Since for most atoms, ionization occurs for photon energies greater than about 10 cV,[*~I rapid isothermal processing involves only resistive heaters and incoherent light sources with photon energies less than about 10 eV. Advanced in-situ processing (physical vapor deposition, chemical vapor deposition, ion implantation, and vacuum lithography, etc.) may involve the combination of incoherent light sources with ions, electrons, and plasma. Details of these kinds of systems are discussed in Sec. 7.4. In summary, the scope of RIP includes the use of incoherent light sources (photon energy less than about 10 eV) alone or in combination with ions, electrons, and plasma energy sources. In addition to thin films, RIP can also be used for the processing of other low thermal mass systems such as ribbons. fibers, and tapes, etc.
5.0
PRINCIPLES
5.1
Operating
OF RAPID ISOTHERMAL
Principle
PROCESSING
of RIP
In rapid isothermal processing, during heating and cooling, the sample is thermally isolated and the heating and cooling is dominated by radiation. For well-designed equipment, no thermal gradients exist into the bulk, and generally no lateral thermal gradients arc experienced by the sample. The rapid isothermal processing cycle consists of three parts: heating. quasi-equilibrium and cooling. A typical RIP cycle is shown in Fig. 2. Generally, RIP is referred to a particular processing time and tcmperature. Hovvever, as shown in Fig. 3, a particular processing phenomena is operative above a certain critical temperature. Thus, in addition to the generally used thermal budget B, both A and C should also be considered in the overall thermal budget. The goal is that in addition to the thermal budget A, both B and C should be optimized in such a way that, with desired heating and cooling rates (one step or multi-steps), the overall thermal stress is minimum. This will assure minimum defect generation. The issue of defect generation is discussed in detail in See. 5.6.
Rapid Isothermal
Processing
(RIP)
449
intensity % 100
75
Peak Intensity 50
25
Time
Figure
2. A typical rapid isothermal
processing
cycle showing
heating,
quasi-equillibrium,
and cooling.
j
Dewed
ocxvating
temperature
Elelow lhbs temperature. physcal phenomena 81.3msignlficant
Figure
3.
5.2
Interaction of Radiation with the Sample
Consideration
of thermal
budget
in rapid isothermal
processing.
Rapid isothermal processing is used at various stages of device and circuit fabrication. Thus, we have to consider all the mechanisms by which the energy of the photon is coupled into the relevant physics and chemistry associated with a particular processing step. The possible mechanisms [**I
4.50 Compound Semiconductors can be divided into the following three groups: (i) direct ambient species excitation, (ii) direct excitation of the overlayer, and (iii) bulk substrate mediated excitation. The basic principles[281-[301underlying each mechanism are summarized in this section. Direct optical excitation of Direct Ambient Species Excitation. gaseous species may involve excitation to higher energy states as well as photodissociation. For typical processing conditions, excitation to an excited electronic state several electron volts above the ground state provides the gas phase species with sufficient energy to initiate subsequent surface reactions. The photodissociation of the source gas can occur in the gas phase or on the solid surface. The subsequent surface reactions are subjected to the constraints of mass transport from the point of excited-state formation of the gaseous species to the semiconductor surface. The vapor phase fragments must arrive at the surface before they are deactivated by collisions with other gas phase molecules. Thus. diffcrcnt results are expected for processing under atmospheric conditions and under ultra high vacuum (UHV) conditions. It is vvorth mentioning here that while the gas phase absorption coefficient of many gaseous molecules used in RIP are knovvn. the same molecules do not necessarily exhibit identical spectra once they are absorbed on solid surfaces.1301 Also, the absorption spectra differ according to the substrate the molecules are absorbed on. As an example, Fig. 4 shows the absorption spectra for trimethylgallium (TMG), in the gas phase as well as on different substrates. LX01It is obvious from Fig. 4 that the absorption spectra is significantly different for various substrates. Direct Excitation of the Overlayer. In the ideal case, the ovcrlaycr absorbs at a wavelength, where both the ambient gas and the substrate have negligible optical cross section, resulting in an unambiguous excitation mechanism. A photon is initially absorbed by the overlayer through electronic transitions comparable to those of the isolated gas phase molecule. The overlayer in its optically excited state can either react or it can lose its energy to the substrate without resultant chemical alteration of the surface.[281 Bulk Substrate Mediated Excitation. Except for photons below the energy gap, optical absorption of the semiconductor substrate will, in general, be significantly greater than that of a thin overlayer. Therefore, substrate mediated processes are most important for RIP. For photons with energies comparable to chemical bond energies, the initial step in the substrate photoabsorption is the creation of electron-hole pairs. The cross
Rapid Isothermal Processing (RIP)
451
section for photoabsorption will be determined by the substrate band structure and will be dominated by whether the optical transition is direct or indirect. These carriers can induce chemical reactions at the surface of the substrate.
.-E t %
z g
N;; o.3 In
.h zb
c-8
To z
0.2 0.1 0
4 0.005
s ,o L 5 . g x 6 2 a
0 0.02 0.01 0 0.02 0.01 0
5c
Figure 4. Absorption spectra for trimethyelgallium different substrates (Ref. 30).
(TMG) in the gas phase as well as on
Excess energy of energetic carriers (carriers with significant excess energy above the band edges) is drained from the system of initially photoexcited carriers principally by carrier-phonon scattering and, in some cases, ionized impurity scattering. On a time scale of about 1 ps, the initial photoexcited carrier distribution will cool to the band edges and achieve thermal equilibrium with the surrounding lattice. These carriers then diffuse until recombining via band-to-band (radiative), defect-mediated (Shockley-Read-Hall), or Auger processes.
452 Compound Semiconductors In case of heavily doped semiconductors, free carrier absorption takes place. In this case, an electron in any conduction band valley makes a transition to a higher state. Similar processes occur for holes in the valance band. For defect dominated substrates, photons with energy less than the gap energy can also create electron-hole pairs. In the case of high quality semiconductor substrates, this phenomena is negligible. In addition to the bulk effects described above, photons can also be absorbed by surface states. Optical excitation of surface states may involve transitions between two surface localized levels or transition between a surface localized state and a bulk state. As a result of photoexcitation, surface recombination and band bending may also take place. Ultimately, photon energy in excess of the energy gap is quickly dissipated into the lattice on the length scale which, typically, is of the order of, or shorter than, the inverse of the optical absorption coefficient. The substrate temperature depends on the spectrum and the intensity of incoherent light source as well as the substrate itself. 5.3
Thermal Dynamics and Temperature Calculations
As mentioned above, the rapid isothermal processing cycle consists of three parts: heating, quasi-equilibrium, and cooling. The objective of any theoretical model is to predict the variation of the temperature of the wafer as a Gmction of time and the spatial coordinate along the wafer. Reference 3 reviews the early work. Since the publication of Ref. 3, several models have appeared in the literature.1311-1411In general, the temperature across the wafer can be calculated by solving the following equation:
Eq. (2)
PC,(T) g
= V[k(T)VT]
+ P(r,T,t)
where p is the density, C, is the specific heat, k is the thermal conductivity of the sample, and P is the absorbed power distribution for the used radiation source. Equation (2) is nonlinear and can be solved subject to appropriate boundary conditions. In the case of one dimensional treatment, Eq. (2) is reduced to:
Eq. (3)
+P(x,T,t)
Rapid Isothermal Processing (RIP)
453
The power terms consist of radiative power absorbed, emitted, and lost by convection or conduction. A numerical solution of Eq. (3) neglecting heat conduction by convection is carried out in Ref. 42. The heating rates are different for different materials. The absorption coefficient of metals is higher than that of heavily doped semiconductors, although the reflectivity is also higher than semiconductors. 5.4
Fundamental Differences Between Furnace and Rapid Isothermal Processing
There are several fundamental differences between RIP and conventional furnace processing. The low thermal mass feature of RIP leads to high heating and high cooling rates. As discussed in the following section, the photon spectrum of the two energy sources are also different. A summary of the major differences between RIP and furnace processing is given in Table 1.11211431 It is worth mentioning here that the resistive heater based conventional furnaces can be modified to raise and lower a wafer (by mechanical means) to provide rapid heating and cooling of wafers.l44l Thus, the rapid heating and cooling features of lamp-based RIP systems can also be realized in resistive heater based modified furnaces. However, such systems are rarely used and are not discussed further in this chapter.
Table 1. Key Fundamental Furnace Processing.t1211431
Differences
Furnace
RIP Mostly cold-wall
Between RlP and Conventional
Mostly hot wall (also cold WA)
Single-wafer
Multiwafer
Low thermal mass
High thermal mass
Small process volume
Large process volume
Short high - T cycles
Long thermal cycles
Multiprocessing
Single-process tools
Photon spectrum
Photon spectrum OR)
(from VW
to IR)
454
Compound Semiconductors
5.5
Role of Photoeffects in RIP
As mentioned in Sec. 5.4, both furnace processing and rapid isothermal processing use thermal sources and radiate electromagnetic energy in direct relation to the temperature of the energy source. The blackbody radiation spectra depends on the source temperature (Fig. 5). In case of furnace processing, the substrate temperature and the furnace temperatures are identical. The radiation spectrum of a furnace (for processing temperatures of about 1200- 1300°C and lower) consists of photons in the infrared and longer wavelength region. Thus, radiation in the infrared region results in thermal reactions, where the ground state molecules are raised to higher vibrational levels of the electronic ground state, and dissociation occurs when sufficient energy is concentrated in the bonds to be broken. On the other hand, in case of RIP, although the substrate temperature is low (as in the case of furnace processing), the filament temperature is higher. As shown in Fig. 6, the spectrum of the incoherent sources of light145l consists of photons from vacuum ultra violet (VW) to infrared (IR) region. Photons of appropriate wavelength (from VW to visible) induce transition from the ground state to a quantized electronically excited state in the case of atoms and to a quantized rotational and vibrational level of an upper
4-
3-
000
K
2.1600K 1400K IZOOK IOOOK
I-
O_ 0
Figure 5.
The blackbody
radiation
spectra as a function
of source temperature.
Rapid Isothermal Processing (RIP)
455
I”,,Wd
(4 ;;_
a_ @I
500
600
WAVELENGTH
(m 1
SPECTRAL
DISTRIBUTION
7’OD
IOC
50
0 150
250
200 WAVELENGTH
Figure 6. The spectrum of (a) tungsten-halogen deuterium lamp. (Adapted from Ref: 45.)
1 nm 1
quartz lamp, (3) mercury lamp, and (c)
456
Compound Semiconductors
electronic state, in case of small molecules. As a result, photochemical reactions and photophysical effects differ from thermal reactions, resulting in lower temperature processing. Therefore RIP, based on the radiation spectrum from the VUV to the visible region, can provide lower temperature processing compared to furnace processing based on IR. It is worth mentioning here that the photoeffects in RIP are operating in concert with thermal reactions as well as the phenomena associated with high heating and high cooling rates. In order to simplify the complex picture, we can separate out the three effects. Section 6 focuses on the photophysical and photochemical effects and their application in the processing of electronic and optical materials and devices. 5.6
Thermal Stress and Control of Defects
The performance and the reliability of semiconductor devices depends on the overall stress of the device. Recently, Hu[~~] has published an excellent review of stress related problems in semiconductor technology. Although the coverage in Ref. 46 is restricted to Si technology, several concepts are equally valid for compound semiconductor devices. According to Ref. 46, stress related problems can be classified into following five groups: (a) stress from thermal processing, (b) intrinsic film stress and film-edge induced stress, (c) stress problems of embedded structural elements, (d) stress in planar and nonplanar dielectrics, and (e) strain and misfit dislocations in doped lattices and heteroepitaxy. Due to the role of photoeffects in RIP, the mechanisms of oxidation, silicidation, etc., and the film growth process in furnace processing and RIP are different.[‘*l A microscopic understanding of a particular process is necessary to model the photoeffects in RIP. Thus, in the context of stress related problems, we focus only on thermal stress. The origin of thermal stress is the nonuniform temperature distribution within a semiconductor wafer. Good temperature uniformity depends on the design of the rapid isothermal processor. The temperature uniformity issue and other related engineering issues are discussed in Sec. 7.2 Recently, Moslehi and co-workers[471 have demonstrated that excellent temperature uniformity can be achieved over a wide range of processing conditions. In terms of temperature uniformity, these are the best results reported in the open 1iterature.L 471 It is worth mentioning here that the RIP system described in Ref. 47 has been used in the fabrication of 0.35 micron CMOS silicon chips, using all RIP steps.[i41 The thermal stress of
Rapid Isothermal Processing (RIP)
457
semiconductor wafers processed in well-designed RIP systems can be as low as in well-designed conventional furnaces. There is no fundamental reason to believe that the thermal stress in RIP is higher than furnace processed materials. In our own work, we have optimized processing parameters, with the result that lower thermal stress has been observed in rapid isothermal processed samples.ll*l As compared to temperature calculations,1311-t411 few publications deal with the calculations of thermal stress 131113311411. The work reported by Lord1311can be extended to system designs other than the one reported in Ref. 3 1. At the present time, there is a need for improved models of thermal stress calculations. There is a direct one-to-one correlation between the thermal stress and the defects in the processed materials and devices. In case of silicon, Ohyu et a1.14*lhave shown that the perimeter component of the leakage current of shallow n+-p junctions, formed by arsenic implantation and rapid isothermal annealing (RIA), increases when the cooling rate of RIA is increased. The results of Ref. 48 show that the thermal stress, induced by high cooling rates, is responsible for the high generation-recombination velocity of minority carriers at the surface depletion layer. Deep level transient spectroscopy (DLTS),14gl perturbed 7-y angular correlation (PAC)1501-1511 and Mossbauer spectroscopy15*l have been used to study the defects introduced by rapid isothermal processing. In the absence of detailed data (e.g., heating and cooling rates, thermal stress, etc.) it is not possible to comment about the role of RIP in the generation of defects reported in Ref. 49-52. However, as shown in Sec. 8.1, RIP has been used successfully to improve the quality of as grown compound semiconductor thin films. The measurement of thermal stress can be used to minimize the defects produced during rapid isothermal processing.11211531-1551 In order to minimize the thermal stress, we have to optimize the heating and cooling rates. The thermal stress generated during cool down tends to be more severe than the stress generated during heat ~p.1~~1The thermal stress and the diode leakage current is lower in the two step ramp case.l55l Moslehi1561 has carried out a detailed study of the effect of ramp rates in controlling the formation of slip-lines. Thus, for a particular rapid isothermal processing step, the heating and cooling rates should be optimized to provide minimum change in the thermal stress.
458
Compound Semiconductors
6.0
EXPERIMENTAL PHOTOEFFECTS
RESULTS IN SUPPORT OF IN RIP
As a low temperature processing technique, W and VW photons have been used in the following areas: (a) surface cleaning of semiconductors, (b) annealing, (c) oxidation, (d) molecular beam epitaxy (MBE) and gas source MBE (GSMBE), (e) chemical vapor deposition (CVD), and v) metalorganic chemical vapor deposition (MOO). This section describes various experimental results. 6.1
Surface Cleaning of Semiconductors
In recent years, the combination of W light and ozone has been used to clean elemental and compound semiconductor surfaces.t571-t641 The early work, including the mechanism of the W/ozone cleaning, is described in Ref. 57. More recent work is reviewed in Ref. 63. Hitchens et al.[5gl have shown that W/ozone cleaning of GaAs substrates prior to MBE epitaxial growth is effective in suppressing sidegating problems otherwise encounIn a similar study, Kopf et al.t601 tered in the fabrication of MESFETs. have shown that a combination of ultraviolet-ozone treatment and chemical etching produces the lowest defect density in the MBE-grown GaAs layer. Pearton and co-worker@] have used W/ozone cleaning to remove C and 0 from GaAs prior to MOMBE and MOCVD deposition of GaAs epilayers. Figure 7 shows the SIMS profiles of C and 0 in GaAs layers grown by MOMBE and MOCVD. As shown in Fig. 7, for the MOMBE grown layers, W/ozone cleaning prior to growth reduces the carbon concentration at the interface below the SIMS detection limit. The MOCVD grown layers do not suffer from C and 0 surface contamination, regardless of whether W/ozone cleaning was used. 6.2
UV Annealing
W photons can also have beneficial effects in the annealing of various materials.1651-1681Debauche et al.16*lhave used a specially designed pulsed xenon lamp (spectrum in the range of 170 mn to 3 urn) for the CVD deposition and annealing of SiO, films on InP. A UV pulse repetition frequency of 7 Hz leads to a substrate temperature of 105°C. About 93 nm thick SiO, films were deposited in the CVD reactor using the above mentioned light source. The same reactor was used to study the annealing effect of the same light source. The infrared spectra of the annealed films
Rapid Isothermal Processing (RIP)
459
(Fig. 8) show the absence of the Si-H bond and the dominance of the Si-0 bonding. The UV-annealed films show well-behaved high frequency C-V characteristics. IO’ MOMBE
MOCVD
I
I
106 CI
5
105 8
5
to* >% 8 103 0 4
I02 z Y 3; lD 0
I
I
I
0
0.2
I
0.4
0.6
I
I
0
0.2
I
I
0.4
I
0.6
DEPTH (pm)
Figure 7. SIMS protile of carbon and oxygen in GaAs layers grown by MOMBE MOCVD on GaAs substrates. (Adaptedjom ReJ: 61.) 75
SI-0
bendmg
mode
t-810
and
cm-‘1
I S DEPOSITED
‘b ;
50
J
“UV
5
LAYERS
ANNEALED”
,”
(IOO’C,
UNDER
N,
2lOmin)
5: $j25
I 930
880
830
WAVENUMBER
780
730
(cm-‘)
Figure 8. Infrared transmission spectra in the Si-0 bending mode absorption region for an asdeposited SiO, layer and for the same sample after a UV annealing process. (Adapted J;om Ref: 68.)
460
Compound Semiconductors
6.3
Oxidation
As compared to furnace oxides, W and VW photons can be used to grow oxide layers at much lower substrate temperatures.tglt121t6gl-[701 Kazor and Boyd1701have shown that the growth rates of dry W oxides at 550°C is 50 times higher than those for conventional thermal growth. In the case of InP, W photons have been used to grow oxides at room temperature.171]-t721 6.4
MBE and Gas Source MBE
Ultraviolet photons have been used in the MBE growth of thin films of high temperature superconductors. 1731The W radiation during deposition of YBa&u307_b thin films improves the activity of ozone by at least an order of magnitude. In the case of gas source MBE, W and VW photons have been used in the growth of thin films of Si, Ge,1741t751 and GaA~.l’~l As shown in Fig. 9, the growth rate is increased even at a substrate temperature of 320°C.
Irradiated
400 ,’
/ *-.J --._
,’ t
--9
d’
Non-lrmdialed
Tsub: 320°C
100 t
OoL 5 TEGo
[x IO-’
Tow]
Figure 9. GaAs growth rate with and without photo-irradiation at a substrate temperature (Adapted from ReJ 76.)
of 320°C.
6.5
Chemical Vapor Deposition
W and VW photons have been used in the deposition of various materials by the CVD technique, also known as photoCVD.1771 In the conventional photoCVD, the substrate heating is generally provided by
Rapid Isothermal Processing
(RIP)
461
resistive heating. In this section, we cover only those examples where incoherent light sources are used for heating the substrate. It is worth mentioning here that compared to the lower energy photons at higher substrate temperature, the high energy photons at lower substrate temperature can provide less defective materials. As an example, Inoue et al.t781 used Kr (peak spectrum at about 124 nm) and Xe (peak spectrum at about 136 run) resonance lamps for the deposition of thin films of SiO,. The interface state density of SiO, films, deposited by the Kr lamp at 14YC, is lower than the films deposited by Xe lamp at 235°C.t781 These results are in concert with the theoretical expectation that the valance properties of atoms that are incorporated into the lattice, and therefore, the potential of their interaction depends on the photoexcitation. Thus, photoexcitation can control the intrinsic defects of the material.t791 6.6
Metalorganic
Chemical Vapor Deposition
In the case of MOCVD, the use of W and VW photons has several advantages. For a detailed treatment of the fundamentals of photophysical and photochemical effects of organic photochemistry, Ref. 79 is an excellent source of information. From the processing point of view, the following are the key points: (i) The absorption spectra of most of the precursors increases with the increasing photons energy. As a typical example, the room temperature W absorption spectra of gaseous tertiarybutylarsine and monoethylarsine is shown in Fig. 10.t811 Thus, excited states of the precursors in the gas phase can be obtained. (ii) The high energy W and VW photons can dissociate and ionize most of the precursors. Thus, room temperature deposition is possible.t821t831 (iii) As compared to gases, there is more flexibility in the synthesis of various precursors. In addition, all other associated photoeffects directly affect the growth kinetics, and eventually improve the quality of the grown layer. Balk and co-workerst841t851 have studied the effect of W photons on the growth of GaAs. As shown in Fig. 11, quartz halogen lamps and the low pressure mercury lamps were used. The use of a graphite susceptor permits the study of only photoeffects since no transient effects are associated. W radiation affects the growth rate (Fig. 12) as well as reduces the background doping (Fig. 13). This type of reactor has been used to grow excellent quality selective epitaxial films of InP.t861 Figure 13 shows the 77 K Hall mobility as a function of intentionally-doped localized InP structure. Recently Tang and co-workerst871 have grown antiphase-domain-free InP epitaxial layers on Si substrates.
462
Compound Semiconductors
I
I
I
I
I-&BASH,
6)
WAVELENGTH,
3.0.
,
I
I
nm
I
I
I EtAsHt
WAVELENGTH.
-
nm
Figure 10. Room temperature ultraviolet absorption spectrum of (a) gaseous tertiarybutylarsine and (6) gaseous monoethylarsine. (Adaptedfiom ReJ 81.)
low
pressure
Hg
lamp(254nm)
Figure 11. Schematic of the MOCVD reactor used to study the effect of ultraviolet radiation on the growth of GaAs. (Adaptedfiom Re_l:84.)
Rapid Isothermal Processing (RIP)
T
= 653 K
”
= IOcm/s
463
P104 = IO X104PC P1.11, = 1.7 x IO2 Pa
Figure 12. Dependence
of the growth rate on the UV irradiation.
(Adaptedji-om ReJ 84.)
with uv dark
0
l
--.
P
n
V
=
8.4cm/s
P101 =
0
IO4 Pa
pAsn3 = 270 PO 0
5
IO
I5
20
25
30
Figure 13. Dependence of the background doping on the ASHJTMG irradiation. (Adapted from Rej 84.)
ratio and the UV
464
Compound Semiconductors
60000 t ;
50000
07
;
40000
“E u 30000 \ 2 20000 k -3 10000
n(77K)
/
cm -3 -
Figure 14. IIall mobility of InP (at 77 K) as a function of carrier concentration. UVRrrf: 86.) assisted MOCVD system was used for the deposition of InP films. (ildupfedfrotn
We have used rapid isothermal processing assisted MOCVDtssj to study the role of V W photons in the growth of superconducting thin films of YBCO. The modified reactor is shown in Fig. 1.5. The heating and cooling rates are slow (maximum heating rate used is about 2.3”C/sec). Thus, we do not expect any transient effect, As shown in Fig. 16, the addition of VW photons dramatically improves the quality of YBCO films. Our own study and similar work of others,t89jt90j shows that the precursors used in the deposition of thin films of YBCO have significant absorption in the UV and VUV region. These results demonstrate that VW photons can play a major role in improving the quality of materials deposited by MOCVD. Katayama et a1.t91jhave also studied the effect of W radiation on the deposition of PbTiO, films by MOCVD. The UV radiation provided improved quality films.
NUPRO FINE VALVE
PRO FINE VALVE
TUNGSTEN
VEN
VW
HALOGEN LAMP-
::I:;
REACTOR
QUARTZ SUBSTRATE-HOLDER b! -
TEIIPERATUR CONTROLLER REP
F
I
VW
II II
\
GA!
FLANGE
MA
NIFOCD
K-TYPE ’
--\
THERMO-COUPLE
I
F’.:: ??iXd
I
I--
ROTARY -PUllP EDWARDS-EZlllB t
4-CHANNELS CONTROCLERS h READOUT
Figure 15. Schematic diagram of the RIP MOCVD system used to study the effect of VUV light on the properties of thin films of YBCO. D, lamp was used as the source of WV light.
466
Compound Semiconductors
TEMPERATURE (Kl
I
I
81
I
I
II
I
I
I
I1
100 TEMPERATURE
Figure
16.
Resistance-temperature
temperature of 640°C
11
11
200
’
”
1’
1’
”
(K)
curve of YEKO
films deposited at a substrate
(a) without and (b) with D, lamp.
7.0
DESIGN OF EQUIPMENT
7.1
Basic Characteristics
AND ENGINEERING
ISSUES
of RIP Systems
This section describes the design of RIP equipment and important engineering issues. The basic characteristics of a RIP system are described in Sec. 7.1. Temperature measurement, control, uniformity and related
Rapid Isothermal Processing
(RIP)
467
issues are described in Sec. 7.2. In Sec. 7.3, the status of commercially available equipment is described. Future directions in the area of equipment design are described in Sec. 7.4. In addition to home-built systems in various laboratories, several rapid isothermal processing systems are commercially available at the present time. Also, new systems are being developed by various manufacturers. These various systems have several similar characteristics. Essentially, the rapid isothermal processing system consists of (i) one or more sources of thermal and optical energy, (ii) a low thermal mass technique to hold the sample, (iii) a technique for transporting the sample in and out of the rapid isothermal processing system, and (iv) a controlled environment to allow the cooling of the sample. Generally, the thermal energy is coupled to the low mass sample by radiation. During the heating and cooling process, the sample is thermally isolated so that radiation is the dominant process both in heating and cooling. Figure 17 shows the schematic for a rapid isothermal processing system along with horizontal wafer handling features. By turning Fig. 17 on its side (arrows pointing downward), it is possible to have a vertical wafer handling system.lg21
0
\
0
\
0
\
HEAT TRANSDUCER L
0
I
\
WINDOW \
‘.
1 VACUUM %IENT
WAFER FOR
<
( $$$$fjwfR
_
_
Figure 17. Schematic for FUP system showning horizontal water handling. (Adaptedfiom Rej 92.)
468
Compound Semiconductors
Temperature uniformity is primarily Radiant Energy Sources. affected by the size, shape, location, and optical properties of the heating source. In most of the commercial RIP systems, there are two basic types of heating sources. Lamp heated systems use either an array of tungsten halogen larnp~,l~~Jeach generating a few KW, or a single long-arc larr1p1~~1 generating several KW. As mentioned in Sec. 5.4, the third type of heating source, the continuous resistive heat source, is rarely used. Single-Zone Heating. The tungsten filament lamp temperature is about 2800-3300 K and consists of a linear double-ended quartz tube containing a tungsten filament, which is resistively heated. The quartz tube heats up to 400°C or more and the upper permissible temperature limit is 900°C.1931 Halogen gas is used instead of inert gas because it increases the filament color temperature by about 300 K. Also, it prevents tungsten deposition on the quartz wall, due to a regenerative tungsten halide chemical transport cycle above 250°C quartz wall temperature. This suppresses the nonuniformity of light intensity due to envelope blackening.l93l The main advantage of tungsten lamps is their low price/life ratio. This is the most commonly used heating method. The long-arc noble gas discharge lamp has color temperatures of 5500-6200 K. The most commonly used one is the xenon lamp. An initially high voltage pulse between the electrodes ignites the gas discharge, which then produces high power radiation at high current densities. The main advantage of arc lamps is a shorter temperature rise time compared to the tungsten lamps. Furnace heated RIP systems use classical resistive heating. Here, there is a well-defined temperature gradient along the central axis of the chamber. The heat source has circular symmetry and is kept continuously Ramp rates for heating and cooling are at a steady state temperature. controlled by the speed of raising and lowering the wafer.144l Multi-Zone Heating. With single or multiple linear lamps, uniformity depends critically on reflections from the walls of the reactor and the chamber. Good uniformity can be obtained only for a limited set of conditions and there is no way of correcting for transient nonuniformity at any processing condition. 1951The main implication of such scalar control is that, though the net optical flux incident on the wafer can be increased or decreased, the spatial profile is fixed by the geometry and cannot be varied or controlled. An alternative approach has been developed that incorporates this flexibility. The system has tungsten-halogen point sources, which are configured in three concentric rings to provide a circularly symmetric
Rapid Isothermal Processing (RIP)
469
flux profile and multivariable control, whereby each of the rings is independently controlled to provide for control over the spatial flux profile. Figure 18[47]shows such a system. This approach has been shown to offer good temperature uniformity over transients and over a wide range of process conditions such as temperature, pressure, and gas flow rate, thereby improving reliability of individual processesand adding process flexibility. Recently, equipment using multi-zone heating methods has been manufactured[47] to allow for real-time adjustments of the radial profile of the radiant flux. Multivariable control will be especially significant in flexible IC manufacturing, where the ability to rapidly innovate and prototype processesand the multiprocessing is a requisite.[13]
Figure from
18.
Bottom
view of a four-zone
Texas Instruments
RIP heating unit.
(Adapted
Ref 47.)
Figure 19[96]shows the schematic illustration of a three-zone lamp module used with Texas Instruments' advanced automated vacuum processing reactors.[96] The module employs a single center lamp, a first ring of 12 lamps, and an outer ring of24lamps. The combination simulates a continuous optical flux ring. The zonesare concentric with the central axis and the center of the wafer. The wafer is heated via its backside during facedown wafer processing. Each lamp zone is independently controlled in
470
Compound Semiconductors
real time via its remote and computer controlled power supply. The design also provides features for multi-point real time wafer temperature measurements . Another model, the four-zone chamber module has also been developed. Both modules include capabilities for real time temperature uniformity control, which is very important due to the fact that various RIP fabrication processes are performed over an extended process parameter Figure 20tg71 shows the peak variation in a 150 mm wafer domain. temperature profile for a three-zone RIP unit. The peak error in Fig. 20 (less than l5”C) is even lower for the four-zone heating units. Process Chamber Features. Temperature uniformity is also affected by the chamber shape and dimensions, optical properties of walls and windows, location of the wafer within the chamber, etc. Also, the chamber construction materials can enhance or limit its applicability for various ambient or processes. tg31 Commercial RIP systems use either cold wall, warm wall, or hot wall designs. (a) The cold wall chamber is built from metals such as aluminum or stainless steel and is coated with a highly reflective material. The top face of the chamber is a quartz window plate (air- or water-cooled) to transmit radiant energy into the system. Since a metal chamber is a water-cooled enclosure, it is called a cold wall system. The cold wall chamber has the advantage of minimum thermal memory effects, since the chamber walls are at a fixed temperature with respect to the wafer. There is no secondary radiation source that could further complicate temperature measurements. Such a chamber can be advantageous in suppressing parasitic deposition. A schematic configuration of a cold wall chamber is shown in Fig. 2 1.tg3) (b) The warm wall chamber is usually a quartz envelope surrounding the wafer. The chamber is aircooled and is enclosed in a water-cooled metal chamber. The wafer is exposed to the chamber on all sides. The warm wall is kept at a significantly lower temperature than the wafer. The warm wall ensures that there are no condensation effects in the system, irrespective of the time between operation. The wall can have thermal memory effects, so preheat cycles are required to eliminate them. Figure 22tg31shows the configuration of a warm wall reactor. (c) The hot wall chamber basically applies to furnace-heated RIP systems. The wall is at a higher temperature than the wafer and serves as a uniform heat radiator to the wafer.
Rapid Isothermal Processing (RIP)
Figure 19.
Schematic
fldaptedfiom
Rej: 96.)
450
Figure 20.
illustration
550
of an advanced three-zone
750 950 Temp.Z%e Set-point (“C)
Peak variation in 150-mm
wafer temperature
lamp heating module.
950
profile during closed-loop
regulation versus wafer temperature set-point values for a three-zone RIP unit.
from RejT 97.)
471
(Adapted
472
Compound Semiconductors
Lamp (4 Reflector Quartz window Wafer Quartz pins Stainless steel Gases out to vacuum pump Gases in
CaF2
I
Figure 21. 96.)
IR pyrometer
I
Schematic configuration
window
of a typical cold wall chamber.
(Aduptedjkom
Rej
Lamp array
Quartz liner
Al door
Water cooled housing
I I
Quartz wafer
tray
+ Optical pyrometer
Figure 22. Schematic configuration
7.2
Temperature
of a warm wall chamber.
Measurement,
(Adaptedfrom
ReJ: 93.)
Control, and Uniformity
RIP systems have experienced severe problems with temperature control and nonunifonnities in the past. In fact, temperature nonuniformities
Rapid Isothermal Processing (RIP)
473
of *20°C were common as recently as six years ago.i31 Temperature control and uniformity were the main barriers that kept RIP from being used universally as a production tool. Temperature Measurement. Modem RIP Systems have stringent requirements for accurate and repeatable real-time control of wafer temperature. The most commonly used non-contact temperature measurement technique in semiconductor processing is optical pyrometry.t%l The use of thermocouples is limited because of their degradation with time, their incompatibility with reactive gases, and their contributed metallic contamination.[981 Therefore, pyrometers have become the device of choice for temperature monitoring. They are calibrated using thermocouples mounted on a wafer of the same type that is to be used during actual processing. Pyrometers sense the thermal radiation from a hot wafer, and the wafer temperature is determined from the electronic calibration curve. Pyrometers must be carefully calibrated to account for (a) the nonlinear emissivity vs temperature characteristics of silicon, (b) batch emissivity variations due to wafer backside textures and film structures, and (c) the wafer-to-wafer (within lot) variations due to minor surface texture differences and lack of backside control during the wafer’s process history. A schematic diagram of a two-point temperature measurement control on a three-zone lampheated RIP reactor is shown in Fig. 23.t%]
Figure 23.
Schematic of two-point temperature measurement and control on a three-zone
lamp-heated RIP reactor.
(Adaptedji-om Ref: 93.)
474
Compound Semiconductors
The advantages of pyrometry for RIP include its non-invasive nature, relatively fast measurement speed, and high temperature capability. These requirements are critical for proper control of transient heat-up and cooldown temperature ramps and accurate/repeatable temperature control. The drawbacks of conventional pyrometry include the dependence of the temperature measurement on the wafer surface and bulk conditions, namely surface roughness and emissivity, dependence on transmission, and lack of sensitivity at low temperatures. lWl Surface roughness is typically waferdependent, while emissivity depends on a range of parameters, including temperature and chamber reflectivity, as well as wafer doping characteristics and surface optical condition.l%l While pyrometers provide a convenient method for measuring temperature, innovative system design is required to eliminate some of the inherent sources of error. One source of error is the heating of any optical chamber windows through which the wafer radiance is monitored, and ensuring changes in the window index of refraction. This must be corrected in the measured radiance. Another source of error is the transparency of the silicon wafer at temperatures below 6OOOC. In this case, depending on the operating wavelength band of the pyrometer and the radiant heating source used, the pyrometer measures the radiation from the heating source. This problem has been solved in two ways:l93l 1. By avoiding overlap of the spectral wavelength distribution of the primary radiation from the heat source with bandpass wavelength range of the sensor. 2. By selective exclusion of the interfering radiation from the heat source prior to reaching the pyrometer. Commercial systems, such as Peak Systems, use the first approach by using a long-arc xenon lamp, which emits practically no radiation of wavelengths above 1.4 urn, with a pyrometer operating at 2.6-3.5 urn. Other systems such as Varian, Jipelec, Rapro, and AG use the second approach by using tungsten filament lamps operated with a quartz window plate so that, essentially no radiation beyond 4.5 urn reaches the wafer. Pyrometers with a bandpass range 24.5 urn, which is immune to the radiation from the heating source, are used. Above mentioned solutions have their limitations. First order radiation (directly emitted by the heat source or from reflection by chamber walls or reflectors) and second order radiation (primary radiation reflected off the semiconductor wafer) disturb the radiation emitted by the hot wafer. Optics
Rapid Isothermal Processing (RIP)
475
in front of or inside the detector can help to focus on the wafer and minimize the disturbances. Also, all the above sources of measurement error have not been fully addressed in conventional pyrometry. Frequent calibration against thermocouple-mounted wafers have improved temperature control for a specific process, but more work needs to be done in this area. One area in which developments have been made is real-time, in-situ, wafer emissivity measurements to allow correction for emissivity changes. Emissivity compensation techniques are discussed later (Fig. 24). The following new concepts in noncontact optical process control are being investigated:l93l 1. Infrared-laser interferometric thermometry which detects small changes in the refractive index and thermal expansion of semiconductors. 2. Light interferometric layer thickness control by detection of the phase shit? of reflected light by a multilayer stack with the aid of optical fiber sensors. 3. Photo-acoustic wave transmission thermometry, where a pulsed layer generates acoustic waves, which propagate through the wafer. Temperature Uniformity. Apart from the above issues affecting pyrometry measurement accuracy and repeatability, wafer temperature uniformity is a key requirement to prevent slip dislocations in high temperature RIP.l%l There are essentially two main reasons1100l for nonuniform temperatures across the wafers: 1. Edge loss which is a statement of the boundary conditions.
This is the reason why a uniform intensity distribution does not lead to uniform temperature across the wafer. Compensation by a nonuniform distribution of the lamp intensity is common practice with commercial RIP systems. However, it is difficult to improve this type of nonuniformity by intensity compensation. It is never possible to completely compensate the edge loss by vertically supplying additional intensity near the edge. Only a very narrow intensity distribution which is concentrated at the edge will give satisfactory uniformity, but there is great dynamic nonuniformity in this case.
476
Compound Semiconductors 2. Nonuniform distributions of the incident light flux are intentionally applied in commercial RIP equipment for the above reason. However, often more power is supplied to the edge region than is necessary to compensate the edge loss. The reason is the heat radiation of the wafer which is back-reflected nonuniformly. This causes a dramatic “dynamic” nonuniformity.
Various investigators have studied the temperature nonuniformity in RIP.t311-t411Results from a typical model show that:13*l 1. To achieve uniform temperature across the wafer, there must be increased radiation at the perimeter to offset the radiative edge loss. This amount of radiation is quantified and must be focused on a relatively narrow part of the wafer perimeter. 2. It is difficult to produce thedesired n-radiance distribution in a RIP with only flat reflectors. This is because of the requirement of increased radiation to a relatively small area at the wafer edge. Also, typical RIP geometries have the lamps spaced too close to the center to achieve uniform temperature over the wafer surface. 3. Focusing reflectors can be used to give heat flux distribution that substantially improves temperature uniformity. But, if linear lamp banks are used with a circular wafer, it is not possible to completely remove the radial thermal gradient throughout the wafer. A prerequisite to avoid dynamic temperature effects is a uniform illumination of the wafer surface.t loo1 It is preferable to avoid backreflection of heat radiation. The edge loss due to boundary conditions however, still maintains a gradient at the edge with any realistic distribution of the lamp intensity. This can be intluenced only by lateral illumination of the wafer edge. The radiation to the edge has to be uncoupled from the main radiation and must be regulated independently. Otherwise, the edge would heat up faster since it absorbs energy additionally and dynamic effects would remain large. An independently regulated illumination lateral to the edge, to counteract edge loss, can be provided by multi-zone lamp heating techniques. It has been shown thatl%l the use of multi-zone cylindrically symmetrical lamp modules along with fiber-optic multi-point temperature sensors provide excellent capabilities for real-time RIP uniformity control.
Rapid Isothermal Processing (RIP)
477
Additional in-situ sensors are described, which allow real-time RIP control and process endpoint detection. Temperature Calibration. Optical pyrometers need to be calibrated because they cannot measure absolute temperature. Calibration of RIP systems[g31can be done at two distinct levels: (a) a system level calibration where the output of the pyrometer is matched directly to that of a thermocouple in contact with a standard wafer, fij a wafer level calibration, where the effective emissivity is indirectly measured ex-situ prior to processing or in-situ during or before processing. S@em Calibration. The primary technique for system level calibration is with a cantilevered thermocouple. Although this is widely used, it has disadvantages. The thermocouple is degraded by repeated high temperature cycling. Other concerns, such as reproducible thermal contact, have been addressed by physically embedding the thermocouple in the wafer. While a thermocouple is generally used for onetime calibration, temperature recalibration and reproducibility/uniformity checks which use processes as “thermometers” are required. Pyrometers which are sensitive to drift can be regularly adjusted by using properly selected thermometric processes, designed around the temperature region of interest. For high temperature applications (1 OOO- 12OO”C),the silicon dioxide growth rate is highly sensitive to temperature. t31 For medium temperature range (6001OOO’C)the partial activation of implanted semiconductors can be used.131 Because of their reproducibility, these indirect measurements of temperature and temperature uniformity are preferred to thermocouple measurements. Wafer Level Calibration. Wafer level calibration involves emissivity compensation. Emissivity compensation can occur at the wafer batch level or at the individual wafer level. One approach is an in-situ wafer batch level measurement on a representative wafer, using an opaque susceptor consisting of silicon carbide coated graphite holding a calibration wafer in thermal contact and having a thermocouple embedded close to the wafer area.fg8) This thermocouple is irradiated only by the graphite. Figure 241g8jshows an experimental emissivity measurement setup using an emissivity/temperature calibrator. Most emissivity measurement and adjustment techniques are based on reflectivity measurements from the wafer backside. The emissivity can be obtained (from Kirchhoffs law) by measuring the reflectivity and transmissivity of a wafer. Transmissivity measurement is not required if the emitted radiation of a test wafer is compared with that of a standard wafer,
478 Compound Semiconductors with reference calibration reflectivity. Therefore, by empirically correlating these differences in reflectivity to the resulting process temperature differences, emissivity compensation is achieved.rg31 The reflectivity is measured from the reflection of a single wavelength beam, either before loading or in the reaction chamber. The measurements can be extended to certain wavelength bands. One method is the measurement at room temperature of the reflection of the radiation from a blackbody source at 300-350°C in a preload station. For each wafer, automatic measurement is done in a 4.67-S. 15 pm wavelength band matching the maximum wavelength of the blackbody radiator, and results in a remarkable improvement of accuracy and repeatability in oxide thickness grown on wafers from several vendors with different wafer backsides.tg31 Figure 25[471shows the schematic diagram of the emissivity-corrected pyrometry-based temperature sensor used in the design of various RIP units used by Texas Instruments. Another method is an in-situ measurement of the reflection of the light emitted by the system’s lower lamp array only, and measured by the pyrometer with its own wavelength band, eliminating differences related to geometry effects. New concepts in the development of in-situ real time-emissivity compensation are ratio pyrometry and optical fiber thermometry.~g3~
T/C
0
0
0
0
0
0
0 -LAMPS
VAC
Figure 24. Experimental f;om Ref: 98.)
emissivity measurement setup using a calibrator.
(Adapted
Rapid Isothermal Processing (RIP)
II
479
8
Process Control Computer
0
IR
LtdCt0r
P
PID Conlroller
Power
Lamp Module
SWY fl
Process Chamber
Microwave Plasma Discharge Tube -+@J&tj
rS I
Figure
25.
IA Detector
I
Schematic diagram of temperature sensor used in the design of RIP units.
(Adapted from ReJ 47.)
7.3
Current Status of Commercial RIP Systems
Over the last several years, the performance of commercially available RIP systems is improving. For research and development purposes, most of the commercial equipment available in the market provide satisfactory results. However, for production, only a few vendors meet the requirements.tlO1l In a recent publication, Roozeboomlio21 has summarized the general characteristics of RIP systems from twenty-two vendors. As stated earlier, commercially available systems are continuously evolving and the information given in Ref. 102 may not represent the best RIP system available on the market.
480
Compound Semiconductors
7.4
Future Direction
As described in Sec. 7.1, most of the current rapid isothermal processors use tungsten-halogen lamps as the source of the energy. As shown in Fig. 6, very few photons are available in the W region. In an earlier section, we demonstrated that the addition of W and VW photons in the energy source can provide a number of beneficial effects for the processing of virtually every material. Generally, windowless W and VW light sources use the discharge of a particular gas. However, such a W and VW photon source can also provide electrons and charged species of the gas used in the operation of light source, which may have adverse effects on the properties of the processed material; thus, we consider only the light sources that employ a window. The various W and VW light sources (mercury lamp, D, lamps, Xe lamp, etc.) generally provide low photon fluxes. However, recently high intensity incoherent excimer W and VW sources have been developed.[1021 As shown in Fig. 26, excimer light can be generated over a wide range of wave lengths. Such light sources have been used for the low temperature deposition of a number of materials.11031-11061The next major challenge is the integration of tungsten halogen lamps and the incoherent excimer VW light sources. We are in the process of developing such a hybrid energy source based RIP system.
Figure 26. Selection of excimer wavelengths from Re/: 102.)
generated in silent discharge.
(Adupfed
Rapid Isothermal Processing (RIP)
481
The RIP unit can also be integrated with plasma, ion, and electron based processing systems. The integration will involve the use of photons and other energy sources in the same processing system. As an example, we have used a RIP and plasma-assisted MOCVD system for the deposition of YBCO films at substrate temperature as low as 500”C.11071We have also integrated a focused ion beam system with a rapid isothermal proceshave studied the effect sor.11081Recently, Damlin and co-workers li”911i101 of UV radiation during ion implantation of Si and GaAs semiconductors and observed a decrease in the amount of radiation damage. The preliminary results reported here indicate the importance of developing equipment based on the integration of incoherent sources of light with other sources of energy (plasma, ions, and electrons). This kind of advanced RIP equipment provides unique opportunities for developing the most advanced microelectronics and optoelectronics devices and circuits, as well as for studying the basic and fundamental physics and chemistry of the new structures.
8.0
VARIOUS APPLICATIONS
OF RIP
As stated in the “Introduction,” virtually every processing step involving furnace processing can be replaced by RIP. Various applications of RIP can be divided in the following groups: (i) stand-alone systems for the annealing of various materials; (ii) stand-alone systems for the formation of oxides, nitrides, oxynitrides, and silicides; (iii) stand-alone systems for doping and gettering; (iv) CVD and MOCVD; and (v) in-situ and integrated processing. The following subsections describe these applications. 8.1
Stand-Alone Systems for the Annealing of Various Materials
Historically, the driving force behind the development of rapid isothermal processing has been the annealing of ion-implanted semiconductor wafers.131 However, RIP can be used for the annealing of virtually every material in the form of thin films, wires, ribbons, and tapes. Various annealing applications of RIP can be grouped as: (il annealing of ion implanted compound semiconductors, (ii) annealing of focused ion beam implanted wafers, (iii) annealing of as-deposited compound semiconductor thin films, (iv) annealing of strained superlattices and quantum wells, (v) annealing of ohmic contacts, (vi) annealing of deposited dielectrics, (vii) annealing of reactive ion etched surfaces, and (viii) annealing of superconductors, ferroelectrics, and conducting oxide semiconductors.
482
Compound Semiconductors
Annealing of Ion Implanted Compound Semiconductors. Historically, rapid isothermal annealing of ion implanted compound semiconductors predates Si.131 In recent years, RIP has been used to study the annealing of ion implanted binary (InP, GaAs, Gap, InAs, and InSb) and ternary (InGaAs, AlGaAs, and AlInAs) III-V compound semiconductors.117111111-12131 The results of GaAs, InP, and GaInAs are described as follows. Gallium Arsenide Annealing of ion-implanted GaAs is much more complex than Si. In addition to the minimization of dopant redistribution, loss of As from the wafer surface during high temperature annealing should be suppressed. The short time involved in RIP offers significant advantages over furnace annealing. The key advantages of short annealing time is that the processes of damage reduction and site equilibration, with their differing activation energies, are more likely to occur simultaneously rather than sequentially, since the heating rate of RIP is typically two orders of magnitude higher than for fmnace annealing.l118l The following approaches are generally used in the RIP of GaAs: (i) no encapsulating layer is used; (ii) an encapsulating layer of suitable dielectric material is used; (iii) ion implantation is carried out through the thin encapsulating layer and followed by the RIP step; and (iv) in the case of the proximity technique, the GaAs wafer is placed either on an Si or GaAs substrate. Due to the various approaches used in the rapid isothermal annealing of GaAs, and the lack of appropriate theoretical models, it is not possible to give definitive answers to the problem of GaAs annealing. However, there is sufficient data in the literature indicating that, for different dopants (light or heavy) and low or high dose implants, certain general trends are apparent.l123l Silicon Implants. As compared to any other ion, Si has been the most extensively studied dopant. The advantage of RIP is clearly illustrated in the work of Arai, et al.11411 Semi-insulating GaAs wafers were implanted with 3 x lo’* ions/cm* silicon at 70 keV. Furnace annealing was carried out at 850°C for 15 min with and without plasma CVD Si,N,. Rapid isothermal annealing was carried out, both with and without an encapsulating layer, at 950°C for 5 sec. Figure 27 shows the carrier profile of both fmnace annealed and rapid isothermal annealed samples. It is worth mentioning here that Fig. 27(a) shows greater than 100% implant activation, presumably there is some diffirsion from the cap. Kanber et al.lll*l reported the annealing of a low dose, silicon ion implantation (300 keV, 6-8 x lo’* ions/cm*). As compared to furnace annealing, superior performance was observed by RIP. Higher peak electron concentrations
Rapid Isothermal Processing (RIP)
483
and mobilities, as well as high performance data, were observed for power FET’s.[ll*l Seo and co-workers1 1171studied the two-step annealing of silicon implanted GaAs (100 keV, 6.5 x 1012 ions/cm2). In two-step annealing, the high temperature is followed by a second anneal at a lower temperature. A two-step annealing technique gives high mobility and activation. Multistep annealing of silicon implanted GaAs (100-300 keV, 2 x lOI to 1 x 1013 ions/cm2) is also reported by Yu, et al.[l121 As compared to single-step annealed wafers, multistep annealed wafers show not only higher activation efficiency, but also more uniform surface activation, higher electron mobility, and better device performance. At present, the physics of two-step rapid isothermal annealing of compound semiconductors is not accurately known; however, we believe that two-step annealing leads to reduced thermal stress and lower defects.
7-----l
Figure
27.
Measured in-depth the profile of the carrier concentration of (a) fumace-
annealed samples and (b) rapid isothermal annealed samples.
(AdaptedjPom
Ref: 118.)
Selenium Implants. Compared to silicon, Se has not been studied extensively. Selenium is a heavy implant, and optimum electrical characteristics are observed at about 1000-l 100”C.[31 Chapman et al.[1401studied the rapid isothermal annealing of GaAs wafers implanted with a 1 x 10” ions/cm2 dose of 400 keV Se+ ions. A peak surface concentration of about
484
Compound Semiconductors
3 x 10lg cm3 was observed for 1100°C and 10 set annealing. Sealy et al.t1151reported annealing of Se-implanted Ga4.s wafers (300 keV, 5 x 1014 ions/cm*). Annealing at 1000°C, for about 20 set of rise time and 30 set of annealing, results in a surface concentration of about 10lg cmW3. Other Donor Implants. For donor ion implantation in GaAs, sulfur, tin, and tellurium have also been studied but at a much lesser extent than silicon and selenium. Kuzuhara et al.t1381studied annealing of S implantation (150 keV, 3 x lo’* to 3 x lOI3 ions/cm*) annealed for 2 set in the temperature range of 700-l 100°C. A peak concentration of 4 x lo’* cme3 was obtained, thus indicating about three times higher peak concentration than that obtained after conventional furnace annealing.t1381 For doses higher than about 1014ions/cm*, both in- and outdifision occurs.[1361[1381 Pear-ton and Cummingst1201reported a detailed study by RIP of S-doped epitaxial GaAs wafers. Short time, high temperature cycles, rather than long time lower anneal time, were stressed to prevent mobility degradation.t120J There are several publications in the literature dealing with rapid isothermal annealing of tin-implanted GaAs.[*l The primary interest in tin implantation is for achieving a high doping level (n+ layer). Using an encapsulating layer of 300 A of Si,N, plus 600 A of AlN, rapid isothermal annealing of an Sn-implanted (300 keV, 1014-1015ions/cm*) GaAs wafer was carried out by Patel, et a1.tllgl Shahid et al.[127Jreported a comparative study of rapid isothermal annealing of Sn and Se-implanted GaAs. Electrical measurements and transmission electron microscopy results show that tin-implanted samples have comparatively higher values of electrical activity and mobility than those implanted with selenium ions. Defects in tinimplanted samples are decorated with precipitates.t127J Rapid isothermal annealing of Te[132Jt133J and Sb-implanted[1311GaAs is also reported in the literature. Johnson et a1.[1311 implanted single crystal (100) GaAs wafers at liquid nitrogen temperature with 90-keV Sb+ and lOO-keVTe+ ions in the dose range of 1 x 1014to 1 x 1016ions/cm*. About 400 A of an t-f-sputtered SiO, encapsulating layer was used to study annealing in the time range of 1O-20 set at 8OOOC.Rutherford backscattering (RBS) was used to measure the solid solubilities of Te and Sb of 6 x lO*Ocm3 and l-3 x lO*Ocme3, respectively.t1311 Nissim et al.t1331studied the rapid isothermal annealing of Te-implanted GaAs (250 keV, 1 x 1015 ions/cm*). Annealing was carried out at 1000°C for a total time (including rise time) varying between 5 and 60 sec. Raman scattering was used as a
Rapid Isothermal Processing (RIP)
485
nondestructive technique to study the lattice reconstruction and surface degradation due to oxidation.t1331 Acceptor Implants. Zinc, Be, Mg, and Cd are the acceptor dopants in GaAs. Out of these four acceptors, rapid isothermal annealing of Znimplanted GaAs has been studied the most extensively.13j Implanted p-type dopants are much more rapid diEusers than n-type dopants. Rapid isothermal annealing provides clear advantages over conventional furnace annealing. However, it does not mean that there are no redistributions during RIP; care must be exercised. Compared to n-type dopants, lower annealing temperatures are required to activate p-type dopants.[llOl The importance of preventing As loss during annealing of p-type dopants is substantiated by the behavior of encapsulated implants.[12gj Co-implanting As with Zn, in addition to short duration annealing, provides peak concentrations approaching 10zocm-3. Thus, by control of the annealing time and temperature and/or by a dual implant, it is possible to minimize Zn redistribution and achieve almost 100% activation. Because of its light mass and consequent high activation at relatively low annealing temperatures, Be is the most attractive acceptor dopant. Toxicity of Be may create an unacceptable hazard in an industrial environment.t1141 Despite this, there are several reports in the literature dealing with rapid isothermal annealing of Be-implanted GaAs.r31 Compared with furnace annealing, higher peak hole concentrations have been observed with little diffusion of Be.[lzl Recent work by Barrett et a1.[l161shows that peak hole concentrations of 10lg cm3 can be obtained for Be implants (40 keV, 1015ions/cm2) annealed at 900°C for 5 sec. Very shallow (400 A) Be implants (10 keV, 2 x 1014ions/cm2), with a peak concentration of 2 x 10lg per cm3, have been reported for 7 set, 820°C anneahng.[1211 The quasiequilibrium nature of RIP preserves the maximum defect density until the Be atoms move into substitutional sites.[121j Tabatabaie-Alavi, et a1.[161j reported the electrical characteristics of the Be-implanted GaAs diode. Rapid isothermal annealed diodes are superior to furnace annealed diodes in several aspects. The reverse leakage current is low, and the maximum electric field at breakdown is close to the theoretically predicted value.[161j Heavier ions, Zn and Cd are not ideal choices for p-type doping in GaAs. Nontoxic Mg is a better choice for acceptor doping. Surprisingly, not much work has been done on Mg doping. Blunt et a1.[1301 published the first paper on the subject of annealing of Mg implants (100 keV, 1014ions/ cm2) in GaAs, using incoherent radiation. Rapid isothermal annealing of Mg implants in GaAs produced higher electrical activation than furnace
486
Compound Semiconductors
annealing. The optimum annealing temperature is about 8OOOC. Above this temperature, the outdiffusion of Mg into the nitride encapsulating layer results in a gradual decline in the electrical activity.t1301 Recent work by others indicates that the electrical activity decreases at temperatures above 900°C and is probably due to the loss of Mg.t1221 Rapid isothermal annealing of Cd-implanted GaAs has been reported Pearton et al.t1141 Cadmium activation is lower compared to Be and Mg implants. Issue of Slip Formation. Rapid isothermal annealing of GaAs has shown superior performance in comparison to conventional furnace annealing. However, the issue of slip line formation is very important. The most important contributor to slip is the intrinsic stress in the bulk GaAs. Another factor that affects slip is the stress created by the various layers applied to the wafer during fabrication. Passivating and encapsulating layers create stresses of their own, and this must be counterbalanced by the stress created in GaAs substrates. The third element is the rapid heating and cooling rates (>lOO”C per set) during RIP. Slip lines are generally observed around the periphery of the wafer, and exceed 5-15 mm towards the center.li25l Several techniques are currently being explored for slip elimination. One such technique includes the use of a doughnut-shaped guard ring with a larger diameter than the wafer of contrast.l125l In another method, the lamps are gradually reduced in intensity rather than turned off after the high temperature plateau stage is reached. It is important to take into consideration all three factors affecting yield loss due to slip. Indium Phosphide Indium phosphide is an important semiconductor material because of its application in high speed, microwave, optoclectronic, radiation hard, and photovoltaic devices. Most of the InP publications deal with Si implantation with a few reports on Se 1150111521 and11541 and BellS21 implantation. A comparative study of furnace and rapid isothermal annealing of room temperature and hot implantation of Si was reported by Bahir et al.11451Significantly higher mobility and slightly better activation were observed in the case of RIP.l145l Soda, et al.l148l used PSG/ SiO, double-layered dielectric layers for encapsulation. For room temperature implants, greater than 80% electrical activation is achieved with peak carrier concentrations greater than about 1019 cmm3and higher mobilities (-1000 cm2N set). 11481 Raman scattering and luminescence of Si-implanted InP have been used to study the quality of annealing and activation of Si donors.[l43lIl441[1491 m e activation carrier mobilities impurity redis-
Rapid Isothermal Processing (RIP)
48 7
tribution in rapid isothermal annealing of Be and Se-implanted InP are better than those obtained from lo-15 min, 750°C furnace annealing.t1521 In addition to the creation of doped regions, ion implantation is also being studied for creating high-resistivity regions that provide device isolation. Compared to oxygen, li~i~~l the ion implantation of carbon for device isolation appears to be more promising. The use of high energy (> 1 MeV) implants is very promising for the fabrication of buried devices.Ilg51 Recently, Nadella et al.11631reported a vertical p-i-n diode in InP using mega electron volt energy ion implantation. Rapid isothermal processing was used in the annealing of ion implanted wafer as well as for the annealing of ohmic contacts.I195l Gallium Indium Arsenide. GaInAs lattice-matched to InP has important applications in the fabrication of optoelectronic devices, field effect and bipolar transistors. Penna et a1.l155l studied the rapid thermal annealing of Si- and Se-implanted InGaAs. Shallow profiles with peak carrier concentrations of about 1 x 10lg cm3 and a sheet resistivity less than 20 ohms/square were observed. 11s51 High activation and mobility were observed for Se implantation at an elevated temperature.l155l Similar results were reported by Sealy, et al.11591. Lam and FonstadllllI obtained activation of over 80% for Be-doped samples by using a two-step annealing cycle. All of these results indicate the superiority of rapid isothermal annealing as compared to conventional furnace annealing. Annealing of Focused Ion Beam Implanted Wafers. Focused ion beam processing (FIB)12141is an important technology for the realization of all ultra-high-vacuum (UHV) maskless fabrication of advanced circuits.121 5l Rapid isothermal processors have not been integrated in the UHV systems. Only stand-alone rapid isothermal annealers have been used for the annealing of III-V semiconductor quantum well based devices.12161-12181As an example, Petroff et al. 12161 have used rapid isothermal annealing (95OOC for 1 min) for the fabrication of GaAs-Al,,G%,,As quantum wires and boxes. In our opinion, the incorporation of rapid isothermal processor in the FIB processing system can further improve the devices and circuits fabricated by FIB. Annealing of As-Deposited Compound Semiconductor Thin Films. Since the early work of Chand et al.,1zi91 several researchers12201-12261have reported rapid isothermal annealing of as-deposited thin films of III-V compound semiconductors. Risez et al.l22ol have reported the RIA of InP layers grown on GaAs substrates. As shown in Fig. 28, the full-width-athalf maximum (FWHM) decreases with increasing annealing temperature.
488
Compound Semiconductors
Optimum annealing time is between 1O-30 set and the optimum annealing temperature is between 780 and 940°C. Watson et al.[**lJhave shown that InGaAs grown on patterned GaAs substrates by MOCVD possess a very small as-grown misfit dislocation density, and after rapid isothermal annealing up to 300 set at 800°C the defect density is very low. MBE grown material is less stable than the MOCVD material.[2211
450 . -
FWHM for as-grown sample
Anneoling Time = IO set
300-l 700
1 7 ’ * I . , . ’ 1 1 ’ ’ ’ 1 . * ’ . ’ ’ 750
800 850 Annealing Temperature (Celsius)
900
’ ’ 93
Figure 28. FWHM of the x-ray diffraction rocking curve of an InP layer as a function of annealing temperature. (Adapted from ReJI 220.)
In a recent publication, Bums and Fonstad[225]reported the use of RIP in obtaining high quality strain-free heteroepitaxial GaAs on Si by annealing chemically separated GaAs epitaxial layers grown by molecular beam epitaxy directly on silicon substrate. Figure 29 shows the photoluminescence spectra of as-deposited, separated, reattached, RIA and GaAsl GaAs reference samples. It is clear from Fig. 29 that the separated and reattached sample displays a photoluminescence spectra nearly identical to the reference sample.
Rapid Isothermal Processing (RIP)
_ Separated,
489
re-attached
- As Grown
J 1.38
1.4
1.42
1.44
TRANSACTION
1.46
1.48
1.5
1.52
1.54
ENERGY (eV)
Figure 29. PL spectra of as-grown, and of separated and reattached GaAs on Si (before RL4) and following RIA at 600% for 10s. The PL spectra of a GaAs/GaAs reference sample is also shown. (Adapfedfiom Rej 225.)
Annealing of Strained Superlattices and Quantum Wells. In the
processing of devices based on strained superlattices, thermal stability is a critical issue. Rapid isothermal annealing has been used in the annealing of group III-V basedt 2261-t2291 strained superlattices and quantum wells. Myers et al.l226lhave used ion implantation and FUA for the fabrication of strained quantum well heterostructure based devices. Optimum RIA has been effective in the fabrication of those devices that are particularly sensitive to process-induced defects.12261Thus, optimized time and temperature parameters of RIP can be used for the fabrication of strained superlattices and quantum well devices. As discussed in Sec. 5.1, the ramp rates should be optimized so that minimum change in the thermal stress is observed. Figure 30 shows the rapid isothermal annealing results of a single quantum well graded index (GRIN) heterostructure, grown by MOCVD, on InP substrates.12351Rapid isothermal annealing was carried out at 700°C. Minimum exciton shift is observed for the unimplanted control samples. These results show that chosen areas can be disordered selectively.t2351
490
Compound Semiconductors
60
. 60-
.“...‘.“..“.“.. q NoImplant m
I
F lmlant
-401 40
30
20
Time/s
Figure
30.
Change
in bandgap with annealing
time for the p-quartemeary
heterostructure deposited on InP substrates. RL4 temperature is 700%.
GRIN
(AdaptedJiom
Ref: 235.)
Rapid isothermal processing has been used successfully for the annealing of alloyed ohmic contacts of Si and compound semiconductor devices and circuits.[3j The short time processing feature as well as the photoeffects associated with RIP provide a controlled phase chemistry of the alloyed ohmic contacts at a much lower thermal budget than the furnace-processed ohmic contacts. Thus, the rapid isothermal annealed alloyed ohmic contacts are superior in terms of the resistance as well as structural, chemical, and mechanical properties. Yasuami, Saito, and Hojor2361were the first to report the use of RIP for alloying Au-Ge ohmic contacts to n&As. Rapid isothermal annealing of GaAs alloyed ohmic contacts has also been reported by others.[124j[2371 Annealing temperatures between 430-445OC and alloying times of l-5 set produced the optimum results for At&e contacts.[2371 Reproducible morphologically improved alloy contacts with low specific contact resistance have been obtained for both n-and p-type GaAs.[238j Halogen lamp annealed contacts show a 30-50% lower specific contact resistance and are more uniform than those obtained using the graphite hcater.[2381 The difference between the graphite heater and halogen lamp annealing can be explained on the basis of role of photoeffects in RIP. Recent work[23gl-t2411 shows that RIP can also be used in the formation of ohmic contacts of advanced optoelectronic devices, as well as strained superlattice devices. Details of recent work are described in Refs. 242 and 243. Annealing
of Ohmic Contacts.
Rapid Isothermal Processing
(RIP)
491
Annealing of Deposited Dielectrics. The performance of dielectric films deposited by low thermal budget processing techniques can be improved by the post-deposition ex-situ rapid isothermal annealing step. RIA has been used to improve the electrical characteristics of in-situ deposited Si,NJSi/n-GaAs metal-insulator-semiconductor (MIS) capacitors having the lowest interface trap density ever reported in GaAs.12441 Annealing of Ferroelectrics and Conducting Oxide-Semiconductors. RIP has been used for the post-deposition annealing of ferroelectrics12451-12481 and conducting oxide semiconductors.l24gll250l Thin films of strontium titanate, deposited by the solgel tec!mique (at 350°C), were rapid isothermal annealed at 550°C for 60 sec.t2451 The RIA annealed films exhibited good structural, dielectric, and insulating properties. The improved properties are due to a minimum interface reaction between the SrTiO, films and the substrate.l24sl Similarly, RIA has been used to improve the performance of other ferroelectric materials.12461-[2481 Conducting oxide semiconductors (e.g. indium tin oxide, tin oxide, zinc oxide, etc.) are wide-bandgap materials having high electrical conductivity. Rapid isothermal annealing (95O”C, 30 set) was used to obtain high quality indium tin oxide (ITO) films.l24gl Weijtens12501 used a two step rapid isothermal annealing technique to reduce the oxide charge and interface density in MOS capacitors with IT0 gates. 8.2
Stand-Alone
Systems For the Formation of Silicides
Titanium-silicide has been used as a Schottky contact to GaAs circuits.131 Alternate layers of Ti and Si were deposited on n-type GaAs followed by a RIP step. The annealing time was 5 set and the annealing temperature was varied from 8OOOCto 950°C. Good electrical properties were obtained for the 1:3 Ti:Si ratio. Ohinishi et a!.l251l have investigated the electrical properties of the Si-implanted n+ layer and WSi&GaAs Schottky contacts after RIP at temperatures up to 1050°C in order to apply RIP to the source-drain n+ layer of WSi,-gate self-aligned GaAs MESFET’s. This method is effective in improving MESFET’s performance at the short gate length of 1.O um.12”l 8.3
vices
Stand-Alone Systems for Shallow Junction Formation and NonAlloyed Ohmic Contacts Shallow junctions are required for a number of semiconductor desuch as metal-insulator-semiconductor-field-effect transistors
492
Compound Semiconductors
(MISFETs), solar cells, and bipolar transistors, etc. RIP is also suitable for the formation of non-alloyed ohmic contacts. In the case of compound semiconductors, several groups have reported solid state diffusion by RIP.12521-12621 Greiner and Gibbons[2521 diffused Si into GaAs from a thin elemental source. The diffusion depended on the type of encapsulant. Dobkin and Gibbonsr2541used Zn diffusion in GaAs from an electroplated elemental source. Shallow junctions (-0.1-0.2 pm) with surface concentrations of about 1 x 1020cme3can be formed by this technique.12541 Ghandi, Huang, and Borrego12551used a ZnO-SiO, layer for zinc diffusion into GaAs. Heavily doped n+ layers, grown by the metal organic chemical vapor deposition (MOCVD) method, were covered with ZnO-SiO, of 0.05 pm thickness followed by the deposition of PSG of about 0.5 pm thickness. The diffusion was carried out in the temperature range of 650-720°C for 3 set to form p+ layers. The diodes fabricated by this process are comparable in electrical properties to those made by molecular beam epitaxy (MBE).12551Gualtieri et a1.I256lused ZnF, or CdF, as a diffusion source to produce surface-doped Schottky barriers on n&P. The diffusion source of ZnF, or CdF, was covered by an encapsulation layer of SiO, or Al,O,. The Au-p+-n-InP diodes formed from ZnF,/SiO, structures showed apparent barrier enhancements of 0.2-0.34 eV with a reduction in reverse leakage of up to two orders of magnitude.[2561 Singh and co-workers [2571-[2601 have developed a new diffusion technique that does not need a capping layer or background pressure of a high vapor pressure element of the compound semiconductors. In this process, for a particular compound semiconductor, a compound is selected so that one element acts as a dopant and the other is one element of the compound semiconductor, preferably a high vapor pressure element. A thin layer of this compound is deposited, by a suitable technique, on top of the compound semiconductor and followed by the RIP step. In the case of n-InP, a thin layer of Zn,P,, was deposited. Figure 3 1 shows the secondary ion mass spectroscopy (SIMS) results on an InP diode formed by this technique. The junction depth in Fig. 3 1 is about 0.18 pm. Alloyed ohmic contacts for compound semiconductors generally result in poor interface morphology. On the other hand, non-alloyed ohmic contacts can result in an even and reproducible interface because the metal is not melted. Kepler et al.12631have used RIP for the formation of nonalloyed ohmic contacts to GaAs. A thin layer (-100 A) of Ge,,,Se,,, was deposited on GaAs, followed by the deposition of an SiO, encapsulant. The optimal diffusion time and temperature is 20 set and 950°C, respectively.
Rapid Isothermal Processing (RIP)
493
Finally, a metal layer was deposited to complete the process. Specific contact resistivities of 2.2 x IO4 ohms/cm* have been reported for nonalloyed ohmic contacts.l263l
I
0
Figure
31.
I 600
I
I
1600
I 2400
Secondary ion mass spcctroscophy (SIMS) (Aduptedfiom
formation of shallow and abrupt junction.
8.4
I
I
I 3200
data of InP diode showing the ReJ 260;)
Chemical Vapor Deposition (CVD) and Metalorganic Vapor Deposition (MOCVD)
Chemical
CVD. Rapid isothermal processing assisted CVD has been used to grow SiO, on InP,12641-12701 SiO,& on InP,12711 and tungsten on GaAs.l*‘*l RIP-assisted CVD results of various materials are fairly impressive. However, CVD equipment designs need further improvement. Licoppe et a1.t2641126611269112701 have used UV lamps, and tungsten halogen lamps assisted RIP system for the deposition of thin films of SiO, on InP. Katz et a1.1267112681 have used tungsten halogen lamp based RIP CVD system for the deposition of SiO, on InP. As expected, the UV and tungsten-halogen lamp assisted RIP systems provide good quality films at substrate temperatures as low as 200°C.12651Lebland and co-workers1*‘ll have used RIP-assisted CVD for
494
Compound Semiconductors
the deposition of stress-free silicon oxynitrides on InP. In the case of metals, RIP CVD has been used for the deposition of tungsten films on GaAs substrates.lz7*l MOCVD. As compared to CVD, only a few papers have been published in the area of RIP-assisted MOCVD.t881t2731-12781Results of superconducting thin films are described in Refs. 276-278. Several production as well as research & development III-V MOCVD reactors use incoherent lamps as the source of energy, however, due to the use of a graphite susceptor, high heating and cooling rates can not be obtained. Thus, only photoeffects play an important role in the growth of III-V semiconductors. Nissim et al.t2731have used RIP-assisted MOCVD for the deposition of Si epitaxial layers on GaAs substrates. This technique does not require arsenic overpressure to protect the GaAs substrate from thermal degradation during Si epitaxial growth. 1273l Katz et al.l274ll275ldeposited thin films of TIN, on InP. It is worth mentioning that, in the deposition ofhigh quality materials at low substrate temperatures, RIP-assisted MOCVD can play a major role. This is due to the fact that new precursors12791-12821can provide a great degree of freedom in the deposition of materials at low substrate temperatures. For a given material, new precursors can be synthesized so that the maximum absorption in the VW and W region is observed. Thus, it is possible that this technique can be used in the search for new materials (not yet invented) as well as smart-materials. In general, due to quantum and or surface effects the properties of materials in nanometer dimensions are different. As an example, the melting point of nanocrystals is lower than bulk materials.1283l Thus, the direct writing of materials (or some other suitable technique) in nanometer dimensions can provide materials which are not possible by the consideration of science and classical thermodynamics of bulk materials. The deposition of III-V semiconductors on recently reported nanochannel array glass1284l can lead to new structures. In our opinion, the low temperature processing feature of RIP will play a major role in the development of new materials and new structures. 8.5
In-Situ and Integrated Processing
For single-wafer processing and cluster tools, in-situ rapid isothermal processing 1141431t2851-12881 is a cost effective approach. Also, many unwanted physical and chemical phenomena can be suppressed or eliminated by RIP. As an alternate of batch processing, flexible manufacturing
Rapid Isothermal Processing (RIP)
495
of silicon integrated circuits, based on single-wafer processing, is considered by Texas Instruments.113l For details of their gigabit manufacturing approach, interested reader is referred to Ref. 13. The manufacturing of integrated systems based on optoelectronics and microelectronics is also possible by single-wafer processing approach.[141 Hayashil289l has advocated the use of all UHV processing for the fabrication of advanced photoelectronic integrated systems. This subsection discusses the elimination of physical and chemical phenomena associated with in-situ RIP. In conventional RIP, as-deposited films are taken out of the deposition chamber and annealed in a rapid isothermal processor. The concept of integrating the deposition equipment and the rapid isothermal processor in one unit provides the basic concept of in-situ rapid isothermal processing. Figure 32, shows the schematic diagram of the in-situ rapid isothermal processor used in this study. We have used this type of system for the solid phase epitaxial growth of II-A fluorides[2851[2861and annealing of III-V ohmic contacts.1287112881
Figure 32.
Schematic diagram of the in-situ rapid isothermal processor.
496
Compound Semiconductors
The system shown in Fig. 32 can be used for in-situ cleaning of semiconductor surfaces in the presence of hydrogen, as well as for the insitu annealing of evaporated materials. In case of epitaxial dielectrics, chemically cleaned substrates are loaded in the UHV system. In-situ cleaning of the substrates was carried out by using 5% hydrogen and 95% argon mixture and heating the substrate. SrF, films of about 1000 A were deposited at room temperature. In one case, post-deposition m-situ annealing was carried out. In another case, ex-situ annealings (both at the same time and temperature) were carried out. Only in the case of in-situ rapid isothermal annealing was solid phase epitaxial growth observed. The structural properties of SrF, films were studied by TEM, SEM, and x-ray photoelectron spectroscopy (XPS). The presence of oxygen in ex-situ annealed films hinders the epitaxial growth. Minimum thermal stress is observed in the case of in-situ annealed films. Figure 33 shows the stress-temperature curve of the ex-situ and insitu annealed SrF, films. There is a one-to-one correspondence between the stress hysteresis &d the defects in the material. 3
-t_ 0
, 100
I 200
MEASURING
I 300 TEMPERATURE
I 400
5
3
WI
2 6i ‘E
(‘d
E 0” o 0
l-
t; I 2 lb -, 0
1 loo
I 200
MEASURING
I 300 TEMPERATURE
i 400
500
WI
Figure 33. Measured thermal stress of SrF, films on InP as a function of temperature for (a) ex-situ, and (b) in-situ annealed films.
Rapid Isothermal Processing (RIP)
49 7
We have also studied the role of in-situ RIP in the metallization of InP and GaAs devices. Before depositing the ohmic contacts, in-situ cleaning of InP and GaAs wafers was carried out by heating the substrate in the presence of hydrogen. The deposition of Au-Ge at room temperature was followed by in-situ or ex-situ annealing. The performance of in-situ annealed samples was superior. The Auger compositional depth profiles for the Au-Ge contacts on InP (100) are shown in Fig. 34.
Au 0 0.0
0.2
0.4
Sputter Time (min)
Figure 34. fiottom)
AES compositional depth profiles of Au-Ge/InP,
(top) ex-situ annealed, and
in-situ annealed cases.
AES results for the in-situ annealed case show complete interdifision of the contact and substrate with no interfacial 0 present. Similar results were obtained by SEM and XPS study. Table 2 shows the stress measurement of ex-situ and in-situ annealed samples. In case of in-situ annealed samples, compressive stress with a lower magnitude than the exsitu annealed samples is observed.
498
Compound Semiconductors
Table 2. Samples
Stress Measurement
Device
Pruccssiny
SlNClUn:
Ambient
AIIGnAs/Au-Ge
In-Situ
Stress x IO’” (Dyne&d)
and In-situ RIA-Annealed
Type of SIKSS DCVdOpl
-0.11
Comprtxive
2.3
Tensile
-0.1
Compressive
3.3
Tensile
Annealed
AIIG,aAs/Au-Ge
Ex-Situ Annded
AI/hPIAu-Ge
In-Situ Annealed
AlfInPIAu-Ge
of Ex-situ
Ex-Situ Annealed
The results presented in this section indicate that in-situ rapid isothermal processing can play a major role in all maskless processing of III-V semiconductors,l290l advanced integrated electronic and optoelectronic systems,l289l as well as the fabrication of most advanced quantum structures.12911 The in-situ RIP can be beneficial in providing high quality in the top 5-6 monolayers of deposited material. The tight control on the thermal budget will permit two-dimensional growth of the desired material. Additionally, in-situ RIP systems can provide tight control on the desired phase of any given material.
9.0
RESULTS
OF VARIOUS
DEVICES
AND CIRCUITS
In the case of III-V semiconductors, RIP has been used in the fabrication of Schottky barrier diodes, various kinds of transistors, quanRapid isothermal protum well lasers, and optical waveguides. 12921-13071 cessing was used in the formation of ohmic contacts of pseudomorphic high electron mobility transistor (HEMT) devices.l297l For best HEMT devices, a cutoff frequency of 135 GHz was obtained.l297l Successful operation of the advanced III-V devices depends on the stability of the strained quantum
Rapid Isothermal Processing (RIP)
499
wel1.l2Wl Several authors have studied the effect of RIP on the performance Zhang et a1.13011 have studied the post of quantum well lasers. 1301113031-13051 growth rapid isothermal annealing (900°C/ls) and in-situ furnace annealing (640°C/90s under an arsenic overpressure) of strained-layer InGaAs/ GaAs/GaInP quantum well lasers. The improvement in PL and threshold current density is attributed to a removal of nonradiative recombination centers from the active region of the laser. However, RIA results in the reduction of characteristic temperature and external quantum efficiency of the laser.t3051 Recent work of Maurel and co-workers[3071 have shown that optimum rapid isothermal annealing is found at 800°C for 10 sec. The threshold current density of the laser decreases by a factor of 2-3 (Fig. 35a) while the internal quantum efficiency of the laser increases from 30% up to 60% (Fig. 35b). As expected, RIP performed at moderate temperature (SOOOC)reduces nonradiative traps actively without damaging the structure through excessive interdifision of group III elements.
2000
J
980
laser
“In
D
After 8oooc-10s
l
Before RTA
OW 2ao
400
600 L
800
woo
RTA
1200
1400
(pm)
(0)
0 0
.,.,.I.I’I’I’ 200 400
El
Affer @X=C-10s
.
Before RTA 600
800
1000
FITA
1200
1400
L (/Am1
Figure 35.
(a) Thershold current density and (b) inverse of differential
efficiency as a function of cavity length of as grown and 8OOWlOs. annealed lasers. (Adaptedjkom
Re/: 307.)
quantum
rapid isothermal
500
Compound Semiconductors
10.0 FUTURE APPLICATIONS The short time processing feature of RIP has been exploited in the fabrication of high performance devices and circuits. Further understanding of the relationship of heating and cooling rates and the defects produced Photoeffects play an in the material can lead to many new applications. important role in RIP. Thus, new RIP equipment based on dual light sources (one for providing VW and W and other for visible and IR radiation), can lead to new applications. As an example, the WV light source alone can be used for photoetching and cleaning of semiconductor surface. The combined energy source can be used for other applications involving annealing and deposition of materials. The in-situ rapid isothermal processing approach can provide improved performance devices at a low-cost. The fabrication of such RIP systems can open up new markets in the area of equipment manufacturing. In addition to conventional microelectronics and optoelectronics, RIP can play a major role in the area of optical computing and advanced optoelectronic integrated circuits. Proposed dual light source RIP systems can provide low temperature processing of virtually every material. For epitixial growth, such RIP systems can reduce the processing temperature of MBE and MOCVD growth. Similar reduced-temperature processing can be achieved for non-epitaxial materials. Unlike plasma processing, no damage of the interface and the surface is expected. The search for some very novel computational devices is going mainly in three different directions. In one approach, single electron electronics is being investigated.1 3081 These devices operate at very low temperatures. In another approach, biological materials are being investigated for image processing and other applications.13091-13101 The third direction involves the use of ultra high speed solid state transistors, for the implementation of artificial neural networks (ANNs). A large number of neurons are required to solve practical and challenging problems. Our analysis shows that hybrid technologies (e.g., InP on Si) can meet the challenge of ANN chips. 13**1From the processing point of view, RIP can play a major role in the realization of advanced computational systems.
11.0
CONCLUSION
This chapter presents an overview of rapid isothermal processing. In addition to the short time processing feature, there are other fundamental
Rapid Isothermal Processing (HP)
501
differences between furnace processing and RIP. An important role is played by photophysical and photochemical effects. The use of VUV and W light sources can further reduce the processing temperature of various steps used in the fabrication of semiconductor devices and circuits. Virtually, every processing step involving furnace processing can be replaced by RIP. In addition to the processing of thin wafers, this technique is equally applicable to other low thermal mass structures (e.g., ribbons, tapes, and fibers, etc.). Measurement of thermal stress and its correlation to the heating and cooling rates can lead to the reduction of defects generated during RIP. The design and manufacturing of next generation of commercial RIP equipments (involving in-situ processing, and use of dual light source systems, etc.) is a major issue. This process is ideally suited for the flexible manufacturing of integrated circuits and advanced photoelectronic integrated systems, as well as for the discovery of not invented and smart materials and devices.
ACKNOWLEDGMENT Part of this work is supported by National Science Foundation (NSF) Grant No, OSR-9 108772-o 1.
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10 Epitaxial Lift-Off for Thin Film Compound Semiconductor Devices Nan Marie Jokerst
1.0
INTRODUCTION
To achieve high-performance low-cost hardware for information applications ranging from telecommunications to computers to cable television, no one material optimally satisfies all system requirements. In fact, most information transmission and processing hardware today is comprised of a variety of materials, including silicon for circuitry, compound semiconductors for light emission, modulation and detection, glass for transmission, metals for electrical interconnection, and a host of dielectrics and polymers for functions such as insulation, isolation, and planarization. The challenge facing hardware designers is in the choice and integration of materials for optimal system function, given that there are limited fabrication and integration process options available to produce manufacturable, low cost, high performance integrated systems. This goal of materials integration, particularly the near-monolithic integration of single crystal materials which do not have equivalent lattice constants, has led researchers in the compound semiconductor area to explore a range of techniques for depositing or bonding compound semiconductor devices to host substrates. These integration schemes strive to 518
Epitaxial Lift-Off for Thin Films
519
produce high performance integrated assemblies at a low cost. To achieve high performance, these integration schemes must utilize high quality single crystal compound semiconductor material that is not degraded by the fabrication or integration process. For low cost, manufacturable integration, standard materials and processes should be maximally utilized and process steps minimized for high yield. Current integration techniques include direct nucleation and growth of compound semiconductor materials onto non-lattice-matched substrates,tll flip chip bonding of compound semiconductor devices and arrays of devices onto silicon circuits,t*) wafer bonding of compound semiconductor devices to host substrates,131 and bonding of single crystal thin film compound semiconductor devices onto arbitrary host substrates.t41 The separation of single crystal thin film epitaxial compound semiconductor layers from a lattice-matched growth substrate, through selective etching, with subsequent bonding of the epilayers onto host substrates, is a new tool for materials integration which has the potential to produce high performance, low cost integrated assemblies. This separation process, named epitaxial lift-off (ELO), utilizes single crystal device cpilaycrs which are grown lattice-matched (or near lattice-matched) to a sacrificial etch layer which has been grown lattice-matched to the growth substrate. The sacrificial layer is selectively etched, and the cpitaxial layers arc thus separated from the substrate. An alternative method of separation is to use stop-etch epilayers to completely etch the substrate away from the epilayers. Using handling layers and transfer techniques, these thin film materials can be handled with tweezers after separation, processed on both sides of the device, aligned, and bonded onto arbitrary host substrates. The quality of these thin film materials is not affected by the separation and bonding process, and the performance advantages associated with mutli-material integration is exciting. A number of investigations have examined the quality of these thin film materials and devices after separation and processing, and the material quality remains high, Lvhich is consistent with the need for high performance operation. There arc no lattice constant constraints on the host substrate, which can bc, for cxample, an amorphous glass or a polymer. There arc a significant performance advantages in multi-material systems, since the individual materials and components can be individually optimized. Epitaxial lift-off is particularly attractive from this perspective, since the host substrate and the thin film devices do not interact until the thin film has been bonded to the host substrate. This also increases the yield of systems if the host substrates and
520 Compound Semiconductors thin film devices can be tested for specification before integration. Another interesting performance enhancement is the fact that thin film devices, comprised of different materials and performing different functions, can be independently optimized and integrated onto a single host substrate. Removal of the substrate from these epitaxial layers also opens new possibilities in device design. Higher performance can often be achieved by removing the substrate. Metal-semiconductor-metal detectors, for example, can be designed with the contact fingers on the bottom of the device, where they no longer reduce the efficiency through shadowing of the incident signal. Another example of enhanced performance applies to resonant cavity devices. Lasers, light emitting diodes, detectors, and modulators can all achieve high performance through use of a resonant cavity. Current high finesse cavities are formed using compound semiconductor distributed Bragg reflectors, which are grown between the substrate and the active medium. In contrast, since both sides of thin film devices can be coated, inexpensive, more manufacturing-tolerant vacuum-deposited high- or anti-reflection coatings can replace the grown mirrors. Another potential advantage of substrate removal is efficient heat dissipation from thin film devices. An advantage for airborne applications is the weight reduction of the integrated system, due to the elimination of the growth substrate. The integration of these thin film materials also has the potential to realize manufacturable, low cost integrated assemblies. These epitaxial films are so thin that, once deposited, the thin film/host substrate stack looks essentially monolithic. Standard, low cost microelectronic processes, such as vacuum metallization and photolithography can be employed to complete the device and integration processing. In the area of reliability, vacuum-deposited metal interconnect compares favorably to bump bonding. To increase yield, devices and host substrates can be pretested before integration. Finally, researchers have demonstrated that these thin film devices can be repaired: a faulty thin film device can be removed from the host substrate and replaced with a fully functional device to increase the yield of the integrated system. The integrations which have been demonstrated include GaAs- and InP-based materials and devices bonded to host substrates such as silicon, lithium niobate, glass, and polymers. These compound semiconductor devices include detectors, light emitting diodes, lasers, modulators, passive optical components, and circuits. The advent of thin film device fabrication and integration has also led to some interesting three-dimensional integration schemes, in which layers
Epitaxial Lift-Off for Thin Films
521
of processing circuitry are interconnected not only in the plane of the devices, but also perpendicular to this plane. Two such three-dimensional integration schemes have been demonstrated: the vertical electrical interconnection and the vertical optical interconnection of device layers. The vertical electrical integration utilizes thin film devices which lie on top of a polyimide-planar&d silicon circuit. Electrical interconnection between the thin film device and the silicon circuit is made through a metallized via in the polyimide. The vertical optical interconnection demonstrates optical communication between two silicon wafers, using a thin film emitter/ detector pair. These h&based thin film devices operate at a wavelength to which the silicon is transparent. Thus, the signal from the emitter on the first substrate passes through the second silicon substrate to the detector on top of the second substrate. These three dimensional integration schemes are potentially useful for computational cubes with vertical interconnect passing from one layer to the next, which may alleviate the current interconnection bottleneck that plagues many dense integrated circuits.
2.0
THIN FILM DEVICE FORMATION
AND BONDING
Single crystal thin films can be formed using selective etches, which separate epitaxial layers from the growth substrate. These thin films, usually on the order of a micron thick, can then be bonded to arbitrary, relatively smooth host substrates. The goal of this process is highperformance low-cost thin film device formation and integration. Epitaxial lift-off (ELO) is a process in which high quality, single crystal epitaxial device layers are separated from the growth substrate. These thin film materials and devices can be processed into a thin film device without degrading the quality of the material, and bonded to a host substrate with final processing to integrate the device onto the host. Epitaxial lift-off has been demonstrated using two approaches, namely, that of selective lateral etching of a sacrificial layer which lies between the epilayers of interest and the growth substrate, and that of selectively etching the growth substrate from the epilayers by utilizing a stop-etch layer. The composition-dependent selective etching of Al,Ga,_,As-based epilayers on GaAs substrates141-I71 and In,Ga,,As,P,_,,-based epilayers on InP,l*l have been those most widely explored to date, and although a similar process has been described for silicon, this review is limited to compound semiconductors.
522
Compound Semiconductors
2.1
Gallium Arsenide Based Thin Films
The physical separation of single crystal epitaxial layers of GaAsbased material from a GaAs growth substrate using lateral selective etching of a sacrificial layer, was first reported by Konagai et al. in 1974.t51 Another epilayer separation technique, using a stop-etch layer, was reported by Antypas et al. in 1975,[*1in which the epilayer was bonded to a glass host substrate and the GaAs substrate etched away, leaving the epilayers bonded to the glass. Nearly twelve years later, Yablonovitch et al. reported lateral selective etching of a sacrificial layer to separate highquality GaAs epitaxial films from the growth substrate, using a process he named epitaxial lift-off (ELO).t41 The creation and integration of thin film compound semiconductor devices with arbitrary host substrates has since been an area of intensive research for low-cost, high-performance integrated systems. Konagai et al. reported epilayer separation for thick GaAs epilayers, which were used to form solar cells.t51 Epitaxial films of GaAs 30 urn thick were grown on a GaAs substrate with a sacrificial etch layer of Al,,Ga,,,As grown between the substrate and GaAs epilayer. After surface contacting the epitaxial layers, the surface was protected with a black wax coating, and the sample subsequently immersed in an I-IF solution to selectively etch the Al,,,G%.,As layer, thereby releasing the epitaxial layers from the GaAs growth substrate. This process is very similar to the epitaxial lift-off process demonstrated by Yablonovitch,t41 with the exception that the layers separated by Konagai were much thicker than those reported by Yablonovitch. It is unclear why this process was not pursued fm-ther by Konagai; the material quality in these thick films may have been damaged by strain-induced cracks in the film. Antypas et al. reported the first epilayer separation using stop-etch layers to preferentially dissolve the substrate, thereby releasing the epilayers.t*l Instead of a sacrificial etch layer grown between the epilayers of interest and growth substrate, stop-etch layers were grown between the epilayers of interest and the growth substrate. After growth, the epitaxial layers were fusion-bonded to a glass host substrate. This assembly was then immersed in a H,O,:NH,OH (19: 1) solution, which preferentially etched the GaAs substrate at a rate of 5 urn/minute, stopping at the first stop-etch layer, Al,,G%,,As. The Al,.,Ga,,,As stop-etch layer was then removed using an HF solution. The final structure which remained was GaAs (1.5 urn thick)/AlGaAs (6.5 urn thick)/glass.
Epitaxial Lift-Offfor
Thin Film
523
In 1987, Yablonovitch et al. reported the separation of epitaxial Al,Gai,As (x < 0.4) from the lattice-matched GaAs substrates upon which they were grown. 141 This EL0 process uses a sacrificial layer of AlAs, which lies between the epilayers of interest and the GaAs growth substrate. The key to the success of the EL0 process is the use of epilayers only microns thick coupled with an Apiezon W (black wax) coating, which supports the thin film for handling purposes and places the epilayers under tension. Placing the epilayers under tension causes the epilayers to curl away from the growth slightly, thereby allowing the exchange of etching solution and reaction products to take place without damaging the thin film. The Epitaxial Lift-Off Process. An EL0 sample is, before EL0 processing, an epitaxial sample which can be fabricated using any standard growth technique. For the GaAs material system, a sacrificial etch layer of Al,Ga,,As (x > 0.6) must be grown between the epilayers which will form the thin film device and the growth substrate. Sacrificial etch layers ranging in thickness from 20 a.ngstroms141to 0.5 umlgl have been used. The first step in the EL0 process is to apply an Apiezon W handling layer to the epitaxial sample. There are a number of approaches to the application of the Apiezon W. One process uses a solution of 2.5 g of Apiezon W dissolved in 100 ml of trichloroethylene. Trichloroethane is now commonly used as the solvent as well. Several coats of this mixture are sprayed (using an atomizer) onto the sample to achieve a thickness of about 100 pm. The sample is then air-cured for 30 minutes and then baked at 100°C for 30 minutes. A second technique utilizes a hotplate or oven which is heated to about 125°C to melt the Apiezon W. The sample is placed on a glass slide on the hotplate or placed in the oven and heated, and a pellet of Apiezon W is placed upon the semiconductor sample. The Apiezon W melts and spreads across the sample. At this point, a Teflon press heated to 75°C can be used to flatten the wax,11oland/or the sample can be cured in an oven at about 120°C for 30 minutes. Variations on this process also give satisfactory results. For the sacrificial layer to be successfully etched, it must be exposed to the etch solution. There are a number of methods to expose the sacrificial etch layer. After the Apiezon W is cured, the edges of these samples can be cleaned with trichloroethane or trichloroethylene to expose the sacrificial etch layer. Alternatively, the sample can be cleaved on all four sides or the edges can be mechanically ground. After exposure of the sacrificial etch layer, the sample is ready to be immersed in the acid etch to selectively dissolve the sacrificial etch layer.
524
Compound Semiconductors
When the GaAs-based sample is immersed in a 10% HF etch, the sacrificial Al,Ga,_.& (x > 0.6) epilayer is selectively etched laterally underneath the epilayers of interest, thereby separating the epilayers from the GaAs growth substrate. The Apiezon W layer places the epitaxial layers under tension and, while the sacrificial layer etches, the epitaxial layers curl slightly away from the growth substrate, exposing the sacrificial layer to the etchant and allowing the reaction products to escape from the etch interface. Heating the HF acid will increase and cooling will decrease the rate of reaction. Diluting the HF solution will decrease and concentrating the HF solution will increase the rate of reaction as well. The etch rate at 0°C for undercutting epitaxial films with a surface stripe width of 1 cm or less, for example, is approximately 0.3 pmIhour.[lol When the sacrificial layer has been etched through, the epilayers may float to the top of the acid solution and the GaAs substrate sink to the bottom, but more commonly, the epilayers and substrate will slide slightly relative to one another and a slight nudge will separate the epilayers from the substrate. The separated epilayers can now be handled with tweezers, due to the support of the Apiezon W. High quality EL0 thin films as large as 2 x 4 crn[‘Oland films as thin as 200 angstroms [loI and as thick as 4.5 umtlll have been reported. The EL0 process reported by Yablonovitcht41t101is limited to the separation of Al,Ga,_,As (x < 0.4) epilayers from the substrate, but further process refinements have removed this epilayer composition restriction. This composition limitation arises because all Al,Ga,_,As (x > 0.6) epitaxial layers will be etched by the HF solution. Some device structures, however, optimally contain epitaxial layers with these high Al composition layers. A simple solution to this problem is to mesa-etch the outer edges of the epitaxial layers of interest down to, but not through, the AlAs sacrificial etch layer. The Apiezon W then protects these high Al composition layers from the HF etch, while still allowing the separation of the epilayers from the growth substrate to take place. Bonding. After the epitaxial thin film has been separated from the growth substrate, it is bonded to a host substrate. Once bonded, the Apiezon W coating is removed using trichloroethane or trichloroethylene. The films are most simply bonded to a smooth host substrate through contact, or van der Waals’ bonding. Alternatively, the thin films can be glued to the host substrate using adhesives such as ultraviolet curable cement, or the films can be bonded with the aid of an interface metal such as palladium.
Epitaxial Lift-Off for Thin Films
525
Water significantly aids in the bonding of the thin film material to the host substrate. A droplet of water, optimally deionized to reduce charge, filtered to reduce particulate, and boiled to reduce dissolved gases, is placed between the thin film and the host substrate. Once the thin film has been positioned with tweezers to the desired location on the host substrate, slight pressure will engage the surface tension ofthe water and pull the film down onto the surface. The remaining water which lies between the thin film and the host substrate can be forced out through the application of further pressure to the surface ofthe thin film. Pressures less than 1.5 x lo4 dynes/ mm2t101will leave approximately 1000 angstroms of water, which will diffise out if the assembly is left to dry for several hours. Particles such as dust encapsulated between the thin film and the host substrate produce bumps in the thin film (potentially capturing water) which blossom into blisters if the assembly is subjected to thermal cycling which liberates gases in the water or boils the water. Eventually, these blistered areas will flake off, so it is essential to minimize their number and areas. A study of the contact interface of these contact-bonded thin films to host substrates such as silicon, GaAs, and lithium niobate was conducted using transmission electron microscopy. [loI In each case, an amorphous bonding interlayer 20 to 100 angstroms thick, which is hypothesized to be surface oxides, is evident. The strength of contact-bonded thin film EL0 material has been investigated, using x-ray diffraction measurements of the lattice constant of AlGaAs/InGaAs/GaAs films bonded to silicon dioxide-coated silicon substrates, as a function of temperature. tl*l These measurements utilized the difference between the thermal coefficients of expansion of the GaAs-based thin film and SiO,/Si to apply stress to the thin film. Increasing temperature placed the thin film under in-plane compressive stress, and decreasing temperature-caused tensile stress. The measured change in lattice constant, perpendicular to the plane of the interface, as a function of temperature indicates that the bonding is weak shear bonding and that there is a critical shear stress at which slip occurs between the GaAs/SiO, interface. For temperature changes less than 5O”C, the film remains rigidly bonded to the SiO,, but for temperatures outside this range, the film slips.t’*l One of the serious drawbacks to the EL0 process, as first reported by Konagai and Yablonovitch, was the inability to deposit an electrical contact between the thin film material and the host substrate. One solution to this problem is the use of palladium (Pd) as an interface metal, which is deposited onto the host substrate before the compound semiconductor thin
526
Compound Semiconductors
film is bonded.t131 Palladium reacts with both silicon and compound semiconductors at temperatures less than 2OO”C, and also exhibits penetration of native oxides such as those that have been hypothesized to lie between the EL0 layers and the host substrate. Experimental structures were fabricated with Pd used as an interfacial layer between the EL0 material and a silicon host substrate. Adhesion was demonstrated to qualitatively pass the scotch tape test and resistance measurements revealed an upper limit on the contact resistance of lo4 ncm2 for heavily doped p or n type GaAs thin films.t131 This epitaxial lift-off process is schematically depicted in Fig. 1. Figure 2 is a photograph of a GaAs metal-semiconductor-metal (MSM) thin film photodetector which has been processed using epitaxial lift-off. The epitaxial GaAs was separated from the growth substrate using sacrificial etching, was subsequently bonded to a silicon dioxide coated silicon host substrate, metal Schottky contacts were vacuum deposited, and interdigitated electrodes were photolithographically defined in the Schottky metal using standard microelectronic processes.
Epilayers Sacrificial
Etch
Layer
Figure 1.
Schematic of the epitaxial lift-off etching process.
(a) The epitaxial device
layers of interest are grown on a sacrificial etch layer which is grown on the growth substrate.
The top layer is the Apiezon
W handling layer.
(5) A post-etch diagram,
illustrates that the sacrificial layer has been selectively etched, thereby separating the thin film epitaxial layers from the growth substrate. host substrate.
(c) The thin film layers are bonded to a
EpitaxialLift-Offfor
Figure epitaxial
2.
Microphotograph
lift-off
detector
of a thin film InGaAsP
integrated
onto a silicon
Thin Films
metal-semiconductor-metal
dioxide
coated silicon
527
(MSM)
host substrate.
This detector is 100 microns in diameter and one micron thick.
2.2
Indium Phosphide Based Thin Films
The fabrication of InP-based epitaxial lift-off thin film material has developed along two paths; first, that of using a thin AlAs layer as a sacrificial etch layer to separate the epitaxial layers from the growth substrate, and second, completely dissolving the substrate using stop-etch layers and selectiveetches. The first processis essentially the sameprocess as that used for GaAs-based materials: a thin AlAs sacrificial etch layer is selectively laterally etched to separate the lnP-based epitaxial layers of interest from the InP substrate. The second approach is similar to that reported by Antypas et al.:[7] a stop-etch layer is grown between the epilayers of interest and the InP substrate, an Apiezon handling layer is applied to the epilayers, and the substrate is selectively etched away, stopping at the stop-etch epilayer. An AlAs sacrificial etch layer, which lies between the epilayers of interest and the InP growth substrate, can also be used for ELO of 1nPbased epilayers.[14] The epilayers used to demonstratethis technique were
528
Compound Semiconductors
InP (buffer)/GaInAs (buffer)/AlAs (5 nm thick)/InP (buffer)/GaInAs. The AlAs is not lattice-matched to the InP layers, so buffer layers were used to improve the quality of the epilayers. The dark current of the photodiode fabricated from these EL0 thin films was degraded in comparison to onwafer diodes without the AlAs layer, however, and the authors hypothesize that this degradation is the result of the dislocations induced by the lattice mismatch.l141 In contrast, the use of lattice-matched stop-etch layers, coupled with dissolution of the InP growth substrate, does not introduce the misfit dislocation problems associated with the AlAs sacrificial etch layer in the InP material system. Either InGaA~l~~l or InGaAsP1161 can be used as stopetch layers for InP substrate removal. In this technique, a lattice-matched stop-etch layer of InGaAs or InGaAsP is grown between the epilayers of interest and the InP growth substrate. In both cases, the epilayers of interest are coated with Apiezon W (with mesa etching, if InP epilayers are to be separated), and immersed in an HCll151 or HCL:H,PO, (3: 1)[161solution for approximately 2 hours (for a 350 urn thick InP substrate) to etch away the substrate from the epilayers. After substrate removal, the stop-etch layer can also be removed using a second selective etch. For example, to fabricate an InP thin film, an InP (substrate)/InGaAsP (stop-etch layer)/InP sample was used.l161 After mesa etching to the InGaAsP layer, the sample was immersed in HCl:H,PO, (3: 1) to remove the InP substrate. The sample was then immersed in HF:H,O,:H,O (1: 1: 10) to selectively remove the InGaAsP layer from the InP epilayer, leaving the InP thin film attached to the Apiezon W. For these InP-based thin films, the bonding techniques are the same as those for GaAs-based thin films. 2.3
Modified Epitaxial Lift-Off Processes
The epitaxial lift-off processes detailed in Sets. 2.1 and 2.2 suffer from some serious limitations. First, it would be advantageous to have the capability to coat and/or process both sides of the thin film while under substrate support, The ability to process both sides of the device also obviates the need for contact bonding, since metal/metal bonding with rapid thermal annealing can be used if both the thin film to be bonded and the host substrate are metal coated. The advantage of coating both sides of EL0 thin film devices was first explored through vacuum deposition of metallic coating onto thin film devices while they were supported by the Apiezon W
Epitaxial Lift-Off for Thin Films
529
handling layer.ll’l The Apiezon W, however, melts under standard vacuum deposition thermal conditions, and is thus not suitable as a support layer during process steps which involve temperatures over approximately 100°C. A second drawback to the aforementioned EL0 process is that Apiezon W is optically opaque to visible wavelengths. Thus, thin film devices cannot be aligned with respect to features on the host substrate. Alignment of the thin film devices is accomplished by depositing the material as a sheet onto the host substrate and etching the sheet into individual devices. A modified EL0 process, the transfer diaphragm process, enables the user to process both sides of the thin film material while under substrate support. In addition, this process allows the alignment and selective bonding of single devices from an array of devices or simultaneous alignment and bonding of an entire array of devices.ll*l This transfer diaphragm technique also utilizes the thin film material in a more cost effective manner, since many host substrates can be serviced with one thin film array of devices. The transfer diaphragm EL0 process uses epitaxial layers that are the same as those used for the GaAs and InP EL0 processes described previously. After growth of the epilayers, the thin film is mesa-etched into an array of devices. In GaAs, the mesa etch is H,SO,:H,O,:H,O (1:8: 160), used as a fast, timed etch to quickly remove the material between the devices followed by a NH,OH:H,O, (1: 100) selective etch, which stops at the AlAs epilayer. In a similar manner, for InP based materials, the mesa etch removes the material between the devices down to, but not through, the stop-etch layer. The Apiezon W is then applied and the sample is immersed in the selective etchant to separate the epilayers from the substrate. The array of thin film devices, embedded in the Apiezon W, is then contact bonded to a transparent transfer diaphragm. This transfer diaphragm is commonly polyimide or Mylar. The polyimide diaphragms are formed by spin-casting 4 urn of polyimide onto a silicon wafer. The wafer is then baked at 150°C in air for 30 minutes and cured at 400°C in nitrogen for 1 hour. The diaphragm is fabricated by etching the center of the silicon wafer. The silicon wafer is etched from the backsidellgl in aHF:HNO,:H,O (6: 1: 1) etching solution. This procedure produces a 4 pm thick polyimide diaphragm 3 to 25 mm in diameter, supported at the perimeter by the remaining silicon ring. The Mylar diaphragm is formed by gluing a piece of taut Mylar to the edges of a silicon ring. The thin film devices in the Apiezon W are contact bonded to the diaphragm, and the Apiezon W is
530
Compound
Semiconductors
removed, leaving an array of thin film devices bonded to the transparent, slightly pliable diaphragm. Figure 3 is a pair of photographs of an array of thin film devices on a poly imide diaphragm. Figure 3a shows the diaphragm under illumination from the top, and Fig. 3b, the samediaphragm in the same view illuminated from the bottom. Clearly, the diaphragm is transparent, which allows the user to align and bond the thin film devices with respect to features on the host substrate.
(a)
(b) Figure
3.
polyimide
Microphotographs transfer diaphragm.
the same diaphragm diaphragm
of an array of thin (a) The diaphragm
in the same view
film
epitaxial
under illumination
illuminated
from
lift-off
devices on the
from the top, and (b)
the bottom.
The transparent
allows the user to align and bond the thin film devices with respect to features
on the host substrate.
Epitaxial Lift-Off for Thin Films
531
The devices on the transparent transfer diaphragm are then aligned and bonded to the host substrate, followed by additional processing, if necessary, to complete the device integration. To bond the thin film devices to the host substrate, the transparent diaphragm is inverted so that the devices face the host substrate. The diaphragm is placed into the mask portion of a mask aligner, and the host substrate is placed in the substrate portion of the aligner. The thin film devices are visually aligned and then contacted to the host substrate through the contact alignment function of the mask aligner. A pressure probe is applied to the diaphragm to bond either an individual device from the array, a subarray, or the entire array of devices from the diaphragm onto the host substrate. This process inverts the devices so that the side of the device that was processed before separation is now bonded to the host substrate. This is particularly useful for the bonding process, since a metal contact on the host substrate and a metallized thin film device will form a stable electrical and mechanical bond when the metal/metal contact is rapid thermal annealed after bonding. Annealed metal bonds are, generally, better mechanical bonds than contact bonds,l20l and a metal/metal bond, generally, provides a good conductive electrical path. In this way, some of the problems associated with weak bonding, particularly as a function of temperature, can be addressed. After bonding, the exposed side of the thin film device can be processed using conventional photolithographic and coating techniques to form electrical contacts and/or optical coatings. The support of the thin film device during processing steps avoids difficulties associated with degradation of unsupported films during processing, and in particular, during thermal processes. This transfer diaphragm process is illustrated in Fig. 4. Figure 5 is an infrared photograph of a 3 x 3 array of double heterostructure AlGaAs/ GaAs/AlGaAs thin film light emitting diodes that have been integrated onto a silicon host substrate. The center device in the array is being electrically probed. Figure 5a is a photograph with no current applied, and 5b with current applied, clearly showing the infrared emission from the center diode. A useful analogy for the transfer diaphragm technique is that of the rub-on letters that were used to insert nonstandard symbols into standard text (before the advent of typeset changeable typewriters and word processors). The standard text was written using an inexpensive typewriter, which parallels the low cost mass production of complex silicon integrated circuitry in foundries today. The less often used mathematical symbols (represented by compound semiconductor devices), which were too
532
Compound Semiconductors
expensive for dedicated standard typewriter keys were applied selectively from a sheet of rub-on letters. Using this technique, a number of different symbols could be applied to a single page of text by aligning and bonding the desired symbols onto the page. In the same manner, multiple material and multiple function thin film devices can be integrated onto a single host substrate, such as a silicon circuit, using the transfer diaphragm technique. A single epitaxial growth of thin film devices can be fabricated into an array of devices, and a large number of host substrates can be integrated through selectively bonding a single device from the array of devices, thereby distributing the cost of the epitaxial growth across a large number of integrated systems.
rl (8)
If? (d
A (4
LFTJ (9
Figure 4. Illustration of the epitaxial Ii&off transfer diaphragm process: (a) starting substrate with grown epitaxial layers of interest; (ZJ)after mesa etching, (c) after contacting; (d) aRer Apiezon W handling layer application; (e) after selective etch of the sacrificial etch layer, fl atIer adhesion to silicon supported polyimide diaphragm and removal of Apiezon W, (g) after selective bonding onto a host substrate. Individual devices or the entire array can be aligned and bonded to host substrates.
EpitaxialLift-Offfor
Thin Films
533
(a)
(b) Figure emitting
5.
Infrared
microphotographs
of a 3 x 3 array of thin
diodes bonded to a silicon host substrate.
film
GaAs-based
light
The center device in the array is being
electrically probed. These are microphotographs of a device (a) with no current applied, and (b) with current applied, clearly showing the infrared emission from the center diode.
534
Compound Semiconductors
High yield and ease of wafer scale integration are two other advantages of the transfer diaphragm EL0 process. High yield can be achieved through pretest of the thin film devices and the host substrate before integration. Thin film devices bonded to a host substrate can also be repaired. If a bonded device fails or does not meet specification, it can be removed and replaced with a functional device.1211High device uniformity wafer scale integration can be achieved by aligning and bonding high uniformity, smaller subarrays of thin film devices, thereby eliminating the need for wafer scale growth uniformity to achieve wafer scale integration of compound semiconductor devices. Another interesting modification of EL0 has been reported which serves to integrate thin film GaAs material onto silicon substrates using direct growth of GaAs-based material onto Si with an AlAs sacrificial etch layer grown between the GaAs and Si. A photoresist strip or clamp is attached to the top GaAs epilayer on one end and to the silicon substrate on the other end. This photoresist clamp pulls the GaAs structure down to the silicon substrate after the sacrificial etch layer is removed.[221 After a final rapid thermal anneal of the bonded structures, the separated and bonded thin film GaAs material exhibits a nearly identical photoluminescence spectrum to a GaAs reference epilayer grown lattice-matched to a GaAs substrate. Devices which are smaller than 300 urn x 300 urn have been successfully processed using this technique.l22l
3.0
CHARACTERIZATION OF EL0 THIN FILMS
Integrated systems using thin film devices will achieve high performance only if the single crystal thin film material is not degraded by the thin film device processing. This critical issue has been investigated using a variety of material and device characterization techniques. These experiments indicate that the material is not degraded by the thin film processing, but in some instances, when processed into specific devices, the device performance is degraded. Although extensive experiments are currently underway to identify the cause of this degradation, it has been hypothesized that the separation of the thin film devices from the growth substrate may introduce an increase in the surface recombination velocity of the newly exposed surface, in comparison to the devices which remain on the latticematched growth substrate. Passivation coupled with epilayer and device
Epitaxial LijSOff for Thin Films
535
design to overcome this problem has yielded performance that is comparable to that of on-wafer devices. 3.1
Photoluminescence, Lifetime
Hall Measurements,
and Minority Carrier
Standard materials characterization techniques, including photoluminescence, Hall measurements, and minority carrier lifetime have been applied to epitaxial lift-off thin film materials to ascertain if the samples are degraded by the separation and bonding process. Photoluminescence and Hall measurements have been performed on AlGaAs/InGaAs single-strained quantum well EL0 thin film structures on glass,t121 photoluminescence measurements on InP thin films on glass,1161and minority carrier lifetime measurements on AlGaAs/GaAs/AlGaAs double heterostructure thin films on glass.t41 All of these experiments indicated that the quality of the thin film material is not degraded by the process used to separate the epitaxial layers from the host substrate. Photoluminescence Measurements. Photoluminescence measurements were performed on thin film A1,.,,Ga,s,As (50 nm thick)/ IQ,,,G%.,,As (12.5 nm thick)/GaAs (35 to 2000 nm thick) material that was separated from the GaAs growth substrate using the standard EL0 technique described in Sec. 2. 11121 and on thin film InP (1.14 urn thick) samples fabricated using the InGaAsP stop-etch EL0 process described in Sec. 2.2.1i61The GaAs-based thin film was contact bonded to SiO,-coated Si, the InP to a glass host substrate, and low temperature photoluminescence measurements were performed on the samples. The GaAs-based quantum well EL0 structures exhibited a 4-5 meV shift to lower energy in the photoluminescence peak, with the same peak intensity and full width at half maximum, all indicative of high quality material. Sample nonuniformity may also play a role in the spectral shift observed, since separate portions of the same wafer were compared. The InP photoluminescence spectra showed a shift of 2 meV to higher energy, a 2.8 meV change in full width at half maximum, and was not calibrated for a comparison of peak intensity since the same samples were measured before and after thin film processing. These shifts are consistent with the stresses placed on the thin film samples due to the differences in coefficient of thermal expansion between the thin film and the host substrate at the photoluminescence measurement temperature, and indicate that the material retains the high
536
Compound Semiconductors
quality of as-grown lattice matched material without degrading dislocation formation due to the thin film fabrication and bonding processes. Hall Measurements. The AlGaAs/InGaAs/GaAs single quantum well samples used to characterize EL0 thin films using photoluminescence were also used in Hall measurements to measure the mobility of the thin films before and after separation from the host substrate.l’*l The carrier concentrations and mobilities of samples with AuGe ohmic contacts applied before separation and bonding to glass host substrates were compared to samples from the same wafer which were not separated from the growth substrate. The carrier concentrations, measured at 77 and 300 K, were unchanged by the EL0 process, again indicating the high quality of the sample after EL0 processing. The mobilities of the samples at 300 K and were 54,000 cm*Ns and 52,000 cm*Ns before and after separation, respectively, once again indicating high quality thin film material. Minority Carrier Lifetime Measurements. Minority carrier lifetime measurements were performed on double heterostructure AlGaAs/ GaAs/AlGaAs EL0 samples.141 A contactless lifetime probe was used to measure the minority carrier lifetime before and after ELO. The minority carrier lifetime decay curves, measured before and after ELO, showed no discernible difference between the two measurements. 3.2
Laser Threshold Current and Dark Current
Thin film EL0 compound semiconductor devices have been tested in experiments before and after separation and bonding to ascertain whether the device performance is degraded by the EL0 process. Double heterostructure laser light output-current (L-I) characteristics have been measured in EL0 devices, with no measurable change in either the L-I curve or in the laser threshold current after EL0 processing.[241 Thin film p-i-n detectors, in contrast, have exhibited some degradation in the dark current of the devices after separation from the growth substrate.[i51 A similar increase in the dark current in thin film metal-semiconductor-metal (MSM) detectors has been noted. This degradation may result from an increase in surface recombination velocity at the separated surface. This hypothesis has been reinforced through preliminary experiments which demonstrate that passivation of the back surface of these devices, after separation, substantially reduces the dark current of these thin film MSM detectors.l25l
Epitaxial Lift-Off for Thin Film
53 7
Semiconductor Laser Measurements. Light output-current (L-I) measurements on a double heterostructure GaAs-based laser structure were compared before and after EL0 processing. A standard laser test structure was grown on top of an AlAs sacrificial etch layer and a heavily doped GaAs layer to provide a high conductivity bottom contact, resulting in the as-grown structure GaAs (insulating substrate)/AlAs (n’, 50 nm thick)/ GaAs (n+, 1.5 um)/Al,,3Ga,,,As (n, 1.5 um)/GaAs (active layer, 0.2 urn)/ Al,,,G%.,As (p, 1.5 um)/GaAs (p+, 0.2 urn). Before ELO, both the n+ and p+ contact layers were contacted from the top of the structure, thus enabling a clear performance comparison before and after ELO. The n+ contact (on the bottom of the structure) was formed by etching through the laser structure to expose the n+ layer, as shown schematically in Fig. 6. No change in the threshold current or L-I characteristic was noted after ELO. Using this contact structure, the same devices could be used to compare before and after EL0 performance without contacting the other side of the devices. Both the L-I measurement and the current threshold density (about 1000 A/cm2) were unchanged before and after EL0 was performed on the devices, indicating that the high quality of the thin film epitaxial material was not degraded by the EL0 process.124l
etch layer
I
I
Figure 6. Schematic of a thin film laser diode with both p and n-type contacts on the top of the device.
Detector Dark Current. Dark current in EL0 thin film photodetectors can also be used to compare thin film device performance before and after separation from the growth substrate. The interpretation of these measurements can be complicated by (and improvements demonstrated by) differences in device design which may include layer thickness, layer composition, separation layer, and passivation. Although the interpretation
538
Compound Semiconductors
and comparison of measurements are complicated by these factors, performance of thin film devices is a prime concern. Detector performance is an area in which recent research has shown a marked improvement in EL0 thin film devices, and further research is anticipated to produce equivalent, if not superior, performance to on-wafer counterparts. Detector dark current is discussed in this section, and other integrated detector performance parameters are addressed in Sec. 5.1. Research into dark current in GaAs based metal-semiconductormetal (MSM) EL0 detectors has demonstrated that passivation of the uncontacted side of the photodetector can significantly reduce the dark current of the device. Three MSM detectors were compared in these experiments: a detector on the growth substrate, an EL0 detector bonded to a nitride coated silicon wafer, and an back-passivated EL0 detector bonded to a nitride coated silicon wafer. The detectors consisted of Al,,,G%,,As (30 nm)/Al,Ga,,As (graded over 20 nm from x = 0.3 to O)/GaAs (2 pm)/ Al,Ga,_,As (graded over 20 nm from x = 0 to 0.3). All of the layers were undoped. Mesas 200 microns in diameter were defined for all devices. One of the two EL0 samples had 20 nm of plasma enhanced chemical vapor deposited silicon nitride (passivation) applied to the side of the detector which was bonded to the silicon wafer. The two EL0 devices were then inverted and bonded to the host substrate using the transfer diaphragm EL0 technique. The planarizing polyimide and interdigitated Ti/Au Schottky contacts with finger widths of 2 pm separated by 3 urn were deposited onto the detectors. At a 5 V bias, the unpassivated thin film device dark current was 40 nA, the passivated thin film device dark current was 9 nA, and the on-wafer detector dark current was 5 nA. The 3 dB detector bandwidths at a 5 V bias were 800 MHz for the unpassivated thin film device, 1.2 GHz for the passivated thin film device, and 1.3 GHz for the on-wafer detector.l25l These experiments clearly indicate that device design and processing significantly impacts the performance of the thin film devices. Measurements of detector dark currents have been performed on both InP and GaAs based p-i-n detector configurations. Device design can significantly influence the dark current of the detectors, and further research into these design factors will improve the dark current performance of thin film detectors. The InP/InGaAs p-i-n EL0 thin film detector dark current, before and after separation from the growth substrate, showed no degradation in the dark current after separation. However, an AlAs sacrificial etch layer was used in this device, and the high dark current both before and after separation (0.5 to 2 uA at a -5 V bias) was attributed to the
Epitaxial Lift-Offfor
Thin Films
539
high dislocation density, since the lattice mismatched AlAs layer was thicker than the critical thickness for dislocation creation.l141 GaInAsAnP p-i-n EL0 photodetectors have also been demonstrated, using a lattice-matched InP growth substrate coupled with the selective etches in Sec. 2.3 to remove the InP growth substrate. These detectors had a 10 nA dark current before EL0 and a 70 nA dark current after ELO, both at a -3 V bias, for both pre-EL0 and post-EL0 contacted devices.l151 Both cases had the contacts applied to the top surface of the device, with the bottom contact layer accessed through trench or mesa etching, as illustrated in the laser structure discussed in this section. Thin film p-i-n detectors, with contacts applied to both the top and the bottom of the devices, have also been demonstrated using the transfer diaphragm technique. Unfortunately, this configuration makes comparison between on and off wafer devices more difficult. InP/InGaAsP/InP p-i-n EL0 detectors used for through silicon wafer optical communication (Sec. 5.4) have been reported with a 0.9 nA dark current at the operating point, at 0 V bias, with no comparison to the on-wafer value.t”l AlGaAs/GaAs/ AlGaAs p-i-n EL0 detectors have dark currents measured to be 29 pA at 0 V bias and 40 pA at a 5 V bias.126l
4.0
NEW THIN FILM CHARACTERIZATION AND DEVICES
TECHNIQUES
The formation of high quality, single crystal, thin semiconductor films using EL0 has enabled new characterization techniques and device designs. The new characterization techniques arise from the small thickness of the EL0 films, and the new device formulations result from the ability to process both sides of a thin film device. Characterization techniques such as photoabsorption measurements at high photon energies necessitate the use of thin films, since the absorption coefficients of the thin films are high. Likewise, nonlinear refraction measurements close to the band edge with high absorption coefficients can be measured using sufficiently thin samples. New thin film device designs such as high efficiency light emitting diodes using high reflectivity back contacts have already demonstrated enhanced performance. A second thin film device, a metalsemiconductor-metal (MSM) photodetector with interdigitated finger contacts on the bottom to eliminate finger shadowing, is also expected to produce improved device performance. In addition, resonant cavity de-
540
Compound Semiconductors
vices, such as vertical cavity surface emitting lasers, resonant cavity photodetectors, and resonant cavity light emitting diodes, can be manufacturably formed using vacuum deposited multilayer dielectric and/ or metallic coatings on both sides of the thin film devices, thereby eliminating costly semiconductor Bragg reflectors. 4.1
Characterization
Techniques: Absorption Nonlinear Refraction
Coeffkients
and
Absorption coefficients are important for the optimization and modeling of devices such as photodetectors and solar cells, and can be used to derive gain spectra for emitters. Absorption coefficients can be calculated from a variety of characterization techniques such as spectroscopic ellipsometry and reflection spectra, but the most direct measurement of absorption coefficients is through phototransmission spectra. At photon energies above the bandgap energy, however, absorption coefficients in semiconductors are high, and a thin semiconductor sample must be used to detect the transmission through the sample. The transmission through the sample, in simplest form, is T = emal,where CLis the absorption coefficient, and 1 is the thickness of the sample. Absorption coefficients above the band edge are on the order of lo4 cm-l, so semiconductor samples with thicknesses on the order of 1 urn are needed for these transmission measurements. A single crystal thin film of high quality semiconductor is needed to perform transmission measurements at photon energies above the bandgap energy. Absorption coefficients as a function of doping in GaAs have been measured by etching a hole in a GaAs substrate to expose an AlGaAs/ GaAs/AlGaAs epitaxial structure. 12’1 This double heterostructure technique could not be used for InP, since InGaAsP compounds have smaller bandgap energies than InP. A series of EL0 thin film single crystal InP samples (fabricated using the selective etching techniques outlined in Sec. 2.3) with a variety of doping densities have been used in transmission measurements to detemine absorption coefficients in InP as a function of doping.l161 These results showed that the absorption coefficients are higher for more lightly doped samples than for heavily doped samples, which is consistent with the measurements performed in GaAs. Nonlinear Refraction. Changes in index of refraction as a function of stimuli, such as electric fields near the semiconductor band edge (called the Franz-Keldysh effect, or electrorefraction) or in multiple quantum Absorption
Coeffkients.
Epitaxial Lift-Off for Thin Film
541
wells (MQWs) (due to the quantum confined Stark effect), are of interest for optical modulators. Thin film EL0 devices can address some of the problems associated with the characterization of these effects and the modulators that are based upon these effects. In the GaAs materials system, for example, absorbing substrates limit MQW modulators to reflection-based modulators rather than transmission modulators. In bulk semiconductors, electrorefraction near the band edge is difficult to measure due to large absorption coefficients and because high voltages must be applied to thick (350-500 pm) samples to achieve the electric fields which will cause significant electrorefraction. As a result, electrorefiaction is usually calculated, using measured changes in the absorption coefficients (as a function of energy and electric field) and the Kramers-Kronig integral, rather than directly measured. Thin film EL0 structures have been used to demonstrate MQW modulators without absorbing substrates and to characterize electrorefiaction in bulk GaAs. These thin film epilayers form a Fabry-Perot resonant structure that can be enhanced with dielectric or metal vacuum-deposited mirrors. A particularly utilitarian aspect of this thin film structure is that the Fabry-Perot resonant structure is so thin that the coherence length of light from a standard monochromator is long enough to probe the resonances of this thin film device; a sharp contrast to the tunable lasers usually necessary to perform these measurements on thicker samples! Thin film EL0 Fabry-Perot measurements were first performed on GaAs-based EL0 multiple quantum well modulators bonded to glass.[231 The transmission measurements on these devices show a clear shift in the exciton peak toward longer wavelengths with increasing electric fields, which is consistent with measurements performed on MQWs on bulk substrates (in reflection mode) to characterize the quantum confined Stark effect.t28l The EL0 MQW modulator had a 2.9 dB maximum contrast ratio at a 12 V bias at a wavelength of 83 1 nm. Another interesting aspect of these EL0 thin film structures is the resonant peaks of the transmission characteristic of the Fabry-Perot. The resonant peaks of this thin film structure shift as a function of change in index of refraction in the sample, and can be used to quantitatively measure electrorefiaction in the thin film sample. To measure electrorefraction near the band edge in GaAs, a double heterostructure AlGaAs/GaAs/AlGaAs pi-n epitaxial structure was separated from the growth substrate and bonded to glass. Both sides of the thin film structure were coated using the transfer diaphragm EL0 process, described in Sec. 2.3, to enhance the reflectivities
542
Compound Semiconductors
of the surfaces, and hence, increase the finesse of the Fabry-Perot device. Using a monochromator and a pulsed (to minimize heating) voltage source to apply the electric field, resonance shifts as a function of applied voltage were measured. Figure 7 shows the shift in peak resonance as a function of wavelength for a variety of applied biases.t291 These are the closest to the bandgap and highest electric field measurements of Franz-Keldysh electrorefraction in GaAs to date. The change in height of the peaks is due to electroabsorption (the electric field dependence of the absorption). Noteworthy are the positive shifts in index of refraction relatively far from the band edge, which switch polarity to a negative shift as the photon energy approaches the band edge, which were theoretically predicted and directly measured for the first time. Modulators fabricated using these double heterostructure EL0 samples had a 3.3 dB maximum contrast ratio at a 10 V applied bias at 878 nn1.t3~1
g
16
‘g
14
‘g
12
z $
%
v
4
3
; &?2
874
876
8%
W30
SBt
884
Wavelength (nm) Figure 7. Data from the electroabsorption and electrorefraction characterization of thin film GaAs-based double heterostructure materials. This data shows the shift in peak resonance as a function of wavelength for a variety of applied biases. From top to bottom, traces correspond to 0 V, -2 V, -4 V, -6 V, -8 V, -10 V.
4.2
New Device Formulations: Resonant Cavity and Bottom Contacted
The capability to coat and/or contact both sides of EL0 thin films or bond these thin films to high reflectivity host substrates enables new device formulations. Bottom-contacted devices can reflect light back into the device for higher efficiency, and bottom contacts do not shadow light
Epitaxial Lift-Off for Thin Films
543
incident on detectors. Devices demonstrated to date include resonant enhanced cavity detectors, high efficiency light emitting diodes, and bottom-contacted MSM detectors. It is anticipated that low cost, high performance emitters, such as cavity enhanced light emitting diodes and vertical cavity surface emitting lasers using vacuum-deposited multilayer coatings for both front and back mirrors (in contrast to grown semiconductor Bragg mirrors), will soon be reported. Resonant Cavity Devices. The thin film resonant cavity FabryPerot structures, such as those used for characterization in Sec. 4.1, can also be used to enhance the performance of devices such as emitters and detectors. Since both sides of the EL0 epitaxial layers can be coated and/ or contacted and the substrate absorption losses have been eliminated, low cost formulations of high performance emitters and detectors are enabled, using vacuum-deposited multilayer dielectric and/or metallic coatings. Thin film resonant cavity detectors have already been demonstrated which exhibit higher quantum efficiency than is theoretically possible for conventional detectors still attached to the growth substrate. Resonant cavity detectors were fabricated using a double heterostructure p-i-n detector structure, high reflectivity coatings, and etching to tune the Fabry-Perot cavity resonance. The p-i-n thin film Al,,,,G~,,,As (p, 0.5 pm thick)/GaAs (i, 1.1 pm thick)/A1,,,,Ga,,65As (n, 0.42 pm thick) detector had metallic mirrors vacuum-deposited onto the back side of the thin film using the transfer diaphragm EL0 process. The bottom contact/ mirror was broad area and the top contact had a window defined in the metal. The cavity resonance was tuned by wet etching the thickness of the AlGaAs layer exposed through the window. The optimal depth of the controlled wet etch is determined by measurement of the total device thickness using a profilometer, and by measurement of the resonant peak photocurrent from the cavity. Conventional detectors of this design which were not optimized for resonance had a maximum theoretical quantum efficiency of 5 1%. These resonant cavity detectors had a theoretical maximum quantum efficiency of 78% and a measured quantum efficiency within 1.5% of the theoretical maximum.[311 Bottom-Contacted Devices. A thin film device can be bonded to a reflecting substrate to reflect light back into the active or absorbing region of a device. Alternatively, a high reflectivity or anti-reflection coating directly can be applied to the buck side of the thin film device, or the surface of the device which is bonded to the host substrate. A high quantum efficiency thin film light emitting diode has been reported that utilizes a high
544
Compound Semiconductors
reflectivity host substrate to reduce reflection losses.l32l Back contacts have also been used to reduce contact shadowing in metal-semiconductormetal (MSM) photodetectors and solar cell~.[~~l These interdigitated fingers can be placed on the bottom of an EL0 MSM detector or solar cell, thereby eliminating the loss due to shadowing, and potentially, increasing the overall quantum efficiency of the device. Additional efficiency enhancement can also be obtained in detectors through reflection of unabsorbed light back through the absorbing region of the device using a reflective back contact. High efficiency AlGaAs/GaAs/AlGaAs thin film light emitting diodes have been fabricated by bonding the thin film devices to high reflectivity host substrates. These double heterostructure diodes exhibited internal quantum efficiencies of 99.7% and external quantum efficiencies of 72% when optically pumped. 1321 This conversion of high internal quantum efficiency to high external quantum efficiency is achieved through the reflection, absorption and reemission of photons inside the light emitting diode, since only a small angle of emission exists for this device configuration. Back-contacted MSM detectors have been demonstrated, but not yet optimized.133l The devices reported to date were unique from the manufacturing perspective that the Schottky contacts were not deposited directly onto the thin film GaAs epitaxial layer; the epilayer was bonded to interdigitated fingers, which were vacuum deposited onto the host substrate. These fingers were 2 pm wide separated by 2 pm over a 100 pm x 100 urn area. A 100 pm x 100 pm GaAs film 1 l.trnthick was bonded onto these fingers to form the MSM detectors. Rapid thermal annealing of the devices after bonding improved both the dark current and the responsivity. The dark current at a 5 V bias before annealing was 3 nA, and after annealing was 1.3 nA. The responsivity of the MSMs before annealing was 0.0 1 A/W, and after annealing was 0.10 A/w.1331 These detectors were not optimized for responsivity; with proper device design, the responsivity of these detectors is expected to significantly increase.
5.0
NEW INTEGRATION FILMS
FORMULATIONS
USING THIN
One of the most exciting aspects of EL0 thin film devices is the potential for materials integration. Using materials integration, the key
Epitaxial Lift-Off for Thin Films 545 attributes of a particular material can be exploited in a specific device, without using that material exclusively for all electronic and optical fknctions. For example, GaAs and/or InP optoelectronic devices can be integrated with silicon integrated circuits, taking advantage of the optical properties of GaAs and/or InP and the processing capability of silicon. Materials integration has been pursued vigorously, using techniques such as GaAs-on-silicon direct growth. These growths often suffer from high dislocation densities due to lattice mismatch as well as a difference in coefficient of thermal expansion between GaAs and silicon. Related to this, an interesting use of EL0 thin films is to provide a lattice-matched nucleation area (which can be placed onto any host substrate) for subsequent growth. This procedure has been demonstrated by growing GaAsbased quantum wells on top of a GaAs EL0 thin film, which was bonded to a silicon host substrate.1341 Sharp photoluminescence peaks indicated the high quality of the quantum wells grown on the EL0 GaAs-on-silicon, demonstrating the high quality of both the grown quantum wells and the EL0 nucleation layer. For some highly desirable integration schemes, such as GaAs on glass, the host substrate does not even have a lattice constant for growth nucleation! Thin film separation and bonding to arbitrary host substrates can eliminate the need for nucleation on the host substrate. Thin film EL0 materials integration has also led to two interesting three-dimensional structures. These three-dimensional structures are multiple layers of devices connected perpendicular to the device plane, electrically and/or optically. These integration schemes enable massively parallel processing schemes and computational architectures, for applications such as imaging as well as highly efficient optical input/output paths for silicon integrated circuits. Thin film materials integration can also enhance the performance of systems through heat dissipation from thin film devices, which output a high thermal load. The performance of these devices, which include emitters and power transistors, is often degraded by thermal loading. In thin film form, these devices can be integrated onto a high thermal conductivity heat sink, thereby improving the performance of the devices. 5.1
Thin Film Optoelectronic and Optical Devices on Host Substrates
GaAs and InP based optical and optoelectronic thin fihn single crystal devices can be bonded to any relatively smooth host substrate using
546
Compound Semiconductors
ELO. Emitters, detectors, solar cells, modulators, and passive optical components have been integrated with host substrates such as glass, silicon, lithium niobate, and polymers. To achieve optimal optical coupling of the emitted or detected light when the thin film device is integrated into a waveguide structure, research into embedding thin film emitters and detectors into waveguide structures is particularly pertinent. Emitters. High efficiency light emission does not occur in silicon, glass, lithium niobate, polymers, and many other materials which may serve as host substrates for light emitting thin film InP and GaAs based devices. The capability to emit light from a thin film device that is bonded to such a host substrate is attractive for applications, including input/output from the integrated system and data transfer within the system. To date, thin film light emitting diodes in the GaAs[321[351and hW1l materials systems have been integrated onto silicon host substrates, thin film double heterostructure GaAs-based edge emitting lasers integrated onto glass,[241 and thin film graded index separate confinement heterostructure (GFUNSCH) GaAs-based edge emitting lasers integrated onto silicon.[171 Thin film GaAs-based light emitting diodes have been integrated onto silicon host substrates using ELO. The latest such demonstration was the high efficiency diode described in Sec. 4.2. The first report of GaAs light emitting diodes bonded to silicon included one of the first demonstrations that thin film devices could be contacted on both sides.[351 These light emitting diodes demonstrated output power as a function of input current which was slightly larger than that of devices which had not been separated from the growth substrate.[351 The lifetime measurements of separated and on-wafer diodes was comparable. These performance characteristics were substantially better than GaAs-based light emitting diodes which were grown directly onto silicon substrates, indicating that the material quality of the EL0 thin film devices deposited onto silicon is better than that of the GaAs material grown directly onto silicon.t351 Double heterostructure AlGaAs/GaAs/AlGaAs laser diodes were some of the first devices to be separated from the growth substrate using EL0 and bonded to glass host substrates. The laser light output-current characteristic and lasing threshold current, before and after ELO, as discussed in Sec. 3.2, were used to characterize the quality of the thin film devices, showing through these two measures of device quality that the lasers were not degraded by the EL0 separation and bonding process. Both of the contacts for these laser diodes were deposited onto the surface of the device to facilitate comparison of before and after EL0 performance. The
Epitaxial Lift-Off for Thin Films
547
epilayers were cleaved into bars of 20 lasers before separation from the growth substrate, resulting in a cavity length of 0.55 mm per laser and 20 lasers in a 5 mm bar length. Under a 1 kHz repetition rate, 400 ns duration pulsed operation, the laser threshold current was 1000 A/cm*, and differential quantum efficiency from a single laser facet was on the order of 20%.[241 The demonstration of a thin film GaAs-based graded index separate confinement heterostructure (GRIN-XII) single quantum well (SQW) laser bonded to silicon used a micromachining-type technique to cleave the thin film samples into individual lasers after separation of the epilayers from the growth substrate. A standard GRIN-SCH structure was grown with some modifications which optimized the structure for the EL0 process, which included a 10 nm AlAs sacrificial etch layer, a 1.8 pm thick Al,,,G%,,,As buffer layer grown between the n-type GaAs bottom-contact layer and the n-type cladding layer, and a 1 pm thick p-type GaAs cap layer. The buffer and cap layers were designed to compensate for the compressive AlGaAs layers used as cladding for the gain region, which could cause excessive bowing of the thin film structure after separation from the growth substrate. The devices were then stripe-contacted and mesa-etched to protect the high Al composition device layers from the I-IF substrate separation etch. The bars were separated from the growth substrate and bonded to a wax-coated GaAs intermediate carrier. Indentations, or wedges, were photolithographically defined at the edges of the thin film to define where cleave propagation would initiate when the thin film was properly stressed. These triangular wedges, 7 pm at the base and 20 pm in length, were etched down through the entire thin film GRIN-SCH structure while mounted on this GaAs carrier substrate. The sample was then removed from the GaAs carrier and mounted on a wax-coated metal carrier that was slightly flexible. This wedge-induced facet cleaving (WFC) technique was completed when the metal carrier was flexed so that the wedges induce crack-propagated cleaves in the GRIN-SCH structure, as shown in Fig. 8. The lasers were then removed from the metal intermediate carrier and mounted on a indium coated silicon wafer. Thin film laser cavity lengths as short as 50 pm were demonstrated using the WFC technique.l17l The EL0 WFC laser was tested at a duty cycle of 20 kHz and pulse duration of 1 ms. The external quantum efficiency was about 15% per facet, and the threshold current density 640 A/cm*. This structure was compared to a conventional GRIN-SCH SQW structure, namely, a structure without
548
Compound Semiconductors
the sacrificial etch, buffer and thick p-type contact layers. These lasers exhibited approximately the same single facet quantum efficiency, and a lower (460 A/cm*) threshold current, which may be attributable to structural differences.1’7 cleaves
Figure 8. Schematic of the thin tilm GRIN-SCH laser structure used for wedge-induced facet cleaving (WFC). These thin film devices were cleaved when the metal carrier was flexed so that the wedges induced crack-propagated cleaves in the laser material.
Thin film light emitting diodes in the InP materials system have been bonded to silicon host substrates, to demonstrate optical through-silicon wafer interconnectll ll as described in Sec. 5.3. These light emitting diodes were homojunction p-n ~.7,-,G~.,,As,,,P,,~~ diodes, which emit at a wavelength of 1.3 pm, to which silicon is transparent. These diodes were separated from the lattice-matched InP growth substrate using the InGaAsP stop-etch layer technique described in Sec. 2.2, contacted on both sides and bonded using the transfer diaphragm technique discussed in Sec. 2.3. Since the total thickness of the thin film device was 4.5 pm, a layer of polyimide was used to planarize the integration prior to deposition of the top electrical contact. These light emitting diodes exhibit current-voltage and light output-current characteristics which are consistent with those of their onwafer counterparts. Detectors and Solar Cells. The incorporation of thin film detectors and solar cells into processing, waveguiding and switching optoelectronic subassemblies can provide signal detection and power for integrated systems. Thin lihn p-i-n and metal-semiconductor-metal (MSM) GaAs and InP-based detectors have been bonded to host substrates such as sapphire,
Epitaxial Lift-Off for Thin Films
549
lithium niobate, glass, and silicon. These detectors have also been embedded into waveguide structures to improve the coupling efficiency of the light from the waveguide into the detector as well as to protect the detector. To date, thin film detectors and solar cells integrated onto host substrates include a GaAs MSM detector on lithium niobate and glass waveguides;t371 a three-dimensional integration scheme onto a polymer-coated silicon circuit (see Sec. 5. 3);13*1 a GaAs p-i-n detector onto a silicon host substrate;l26l a resonant cavity enhanced GaAs p-i-n detector onto silicon[311(see Sec. 4.2); GaAs solar cells onto aluminum151and silicon;l38l an InGaAsAnP p-in diode onto a sapphire substrate;1141an InGaAs/InP diode onto a glass waveguide;t151and an InP-based double heterostructure p-i-n onto a silicon host substrate.llll A back-contacted GaAs MSM has also been formed through bonding of thin film material onto metallized fingers,l33l which is discussed in Sec. 4.2. Glass and lithium niobate waveguides are attractive choices for many signal processing and switching applications. Light detection devices are difficult to fabricate in these materials, however, making these materials prime host substrate candidates for thin film EL0 device integration, once again taking advantage of the best attributes of different materials systems through materials integration. Planar lithium niobate and stripe lithium niobate and glass waveguides have served as host substrates for GaAs thin film MSM detectors.l37ll3gl After fabrication of the waveguides, a 250 mn thick GaAs EL0 film was contact-bonded to the waveguide and, on the planar waveguides, the 75 pm long, 7 urn wide detectors were defined through post-bonding etching of the GaAs to align the thin film device to the waveguide. Schottky metallization contacts 100 urn wide separated by 5 pm gaps were subsequently deposited to form the MSM detectors. Measurements of the waveguide coupling into the detector, using detector absorption, resulted in a = 40 cm-’ for the planar lithium niobate waveguide and a = 0.14 cm-’ for the stripe glass waveguide, indicating optical coupling between the waveguide and detector, although it is lower than the theoretical maximum coupling efficiency. This lower coupling has been attributed to a thin interfacial layer (see also Sec. 2.1) of low index native oxide, air, organics, or other impurities, which lies between the waveguide and the thin film detector.l3gl In a separate experiment, the transient response of thin film EL0 GaAs MSMs bonded to glass waveguides was measured. These devices were fabricated from a 0.25 urn thick undoped GaAs thin film with Ti/Au interdigitated fingers that were 2.5 urn wide separated by 3.5 pm. These detectors had a capacitance
550
Compound Semiconductors
of 20 fF and demonstrated a full width at half maximum response of about 400 ps for biases between 4 and 6 V.t3’jj To improve the optical coupling from the waveguide into the detector, thin film detectors have also been embedded in the waveguide structure to facilitate edge coupling. t36j To create this structure, a portion of the channel waveguide is formed in the host substrate, in this case, glass. The detector is bonded onto the glass waveguide host substrate, and an A&O, layer is vacuum-evaporated over the waveguide and detector, thereby embedding the detector. The index of refraction of the Al,O, matches and completes the waveguide. Using this technique, the peak of the guided mode can be positioned incident onto the detector for better optical coupling into the detector. This embedding technique has improved the optical coupling from the waveguide into the detector by a factor of 200.[36j Thin film p-i-n EL0 Al,,,,Ga,,,,As (p, 0.5 urn thick)/GaAs (i, 1.1 urn thick)/Al,.30Gq,,,As (n, 0.42 urn thick) detectors, with contacts on both sides of the device, have been demonstrated using the transfer diaphragm EL0 process. These detectors were 250 pm x 250 pm, and had dark currents of 40 pA at a 5 V bias, and responsivity of 0.53 AlW.t26j Thin film GaAs solar cells were the impetus for the first report of separation of epitaxial layers from lattice-matched growth substrates using selective etching, and have since also been demonstrated using a perforated silicon host substrate. The attractive aspects of thin film solar cells include low weight (a vital consideration for space applications), low cost with a reusable growth substrate, and the potential for ultra-high efficiency tandem solar cells through mechanical stacking of thin film solar cells. The first thin film solar cells were 30 mm thick n-type GaAs films, which were separated from the growth substrate and deposited onto an aluminum plate. The measured one sun efficiency ranged from 9% to 1 l%.t5j Thin film solar cells of Al,Ga,,As (n, 1 urn thick, x = graded 0.3 to O.S)/GaAs (p, 40-50 urn thick) were also fabricated with the graded layer acting to compensate for the bending of the GaAs layer. These solar cells produced a measured maximum one sun efficiency of 13.5% .t51 Thin film GaAs solar cells have also been bonded to silicon. To facilitate contact to the back of the thin film solar cells, a perforated silicon substrate was used as the host for thin film EL0 solar cells.t40j These p+-nn+ GaAs homojunction solar cells, with interdigitated finger contacts applied to the GaAs surface, were separated from the growth substrate and the released face was bonded onto a perforated silicon host substrate. Back
Epitaxial Lift-Off for Thin Films
551
contacts to the thin film solar cell were deposited through the holes in the silicon host substrate. InP-based detectors are particularly interesting for optical communications applications which utilize the 1.3 pm and 1.55 pm wavelengths. InGaAsAnP p-i-n detectors have been bonded to glass stripe waveguides and analyzed in the same manner as described previously in this section, for the GaAs MSM detectors on glass waveguides. The InGaAs (n+, 50 nm thick)/InP (n, 100 nm thick)/InGaAs (i, 1.5 urn thick)/InGaAs (p+, 50 mn thick) detectors were separated from the lattice-matched growth substrate, using the n+ InGaAs layer as a stop-etch layer, as described in Sec. 2.2. Both the n and p contacts were deposited from the top surface, using a trench etch to access the n+ layer. The dark current of these thin film devices was 70 nA, and the detector absorption from the waveguide was 12 cm-1.[151
InGaAsAnP detectors have also been separated from the growth substrate, using an AlAs lateral sacrificial etch layer, as described in Sec. 2.2, and bonded to a sapphire host substrate.li41 Both top and bottom contacts were applied from the surface of the device, using mesa etching of the device layers above the bottom-contact layer. These devices exhibited a high dark current of 0.5-2 uA both before and after ELO, which can be attributed to the lattice mismatch between the InP/InGaAs layers and the AlAs sacrificial etch layer. The theoretical and measured internal quantum efficiency was 90% at a wavelength of 1.3 urn, and the measured pulse response full width at half maximum (FWHM) was 46 ps at an optical peak power of 4 uW. This pulse response was independent of incident power down to 8 uW. An estimate of the intrinsic pulse response of the thin film detector, 23 ps at FWHM, is comparable to similar on-substrate photodiodes.1i41 Double heterostructure InP/lrb,,,G~.,,As,,,4P~,~~~nP thin film photodetectors have been integrated onto silicon host substrates for optical through-silicon wafer three-dimensional communication,l11l as described in Sec. 5.4. The InGaAsP epilayer absorbs at a wavelength of 1.3 urn, to which silicon is transparent. The detector was grown lattice-matched on top of an InGaAsP stop-etch layer, which was grown on an InP substrate. The substrate and stop-etch layer were removed from the thin film detector, using two selective etch steps as outlined in Sec. 2.2. These thin film p-i-n detectors were unbiased in the three-dimensional integration, and exhibited a dark current of 0.9 nA and a responsivity of 0.56 AJW at a wavelength of 1.3 um.l”l
552
Compound Semiconductors
Modulators and Passive Components. Thin film modulators and passive components have been fabricated using ELO. Quantum confined Stark effect123l and Fabry-Perot electrorefraction1301 modulators are particularly interesting in light of the promise of low cost resonant devices, and for characterization as discussed in Sec. 4.1. Passive components demonstrated using EL0 include a waveguide consisting of an EL0 AlGaAs thin film on an InP host substrate, for potential use as a optical router,l36l and a thin film high index of refraction GaAs waveguide grating coupler bonded onto a glass channel waveguide.l36l To demonstrate an EL0 waveguide, an epitaxial AlGaAs waveguide has been separated from the growth substrate and bonded to an InP host substrate using ELO. The index of refraction of Alo,,,G~~,,As in the wavelength range from 1.3 to 1.5 pm is higher than that of the InP host substrate. After bonding of the 1.4 urn thick AlGaAs thin film to the InP host substrate, a rib 0.15 urn deep and 2 to 5.5 urn in width was defined in the AlGaAs to provide lateral optical confinement. One mode was guided in the AlGaAs, as anticipated from the design, and the optical loss was comparable to similar structures in which the epitaxial AlGaAs waveguide was grown directly onto the InP substrate.l36l The high index of refraction of compound semiconductors in comparison to glass and lithium niobate invites the integration of passive thin film components with waveguides. Reflection at the semiconductor boundary, however, poses a serious loss problem that may dictate the introduction of sophisticated tapers on the thin film edges. One passive component that has been bonded to a glass channel waveguide is a GaAs thin film waveguide grating coupler. 1361A 20 nm GaAs EL0 thin film was bonded to a glass channel waveguide and a 490 nm period grating was etched into the GaAs, using holographic lithography. The 633 nm wavelength light in the 7 urn wide waveguide was strongly coupled into radiation modes by the GaAs grating over a 100 urn length.I36l 5.2
Thin Film Circuits on Host Substrates
Integration schemes can, in many cases, also benefit from the introduction of circuitry onto host substrates. High speed, high power thin film GaAs field effect transistors (FETs), such as metal-semiconductor FETs (MESFETs), for example, are currently used in high speed communications receiver front ends and transmitter driver circuits, and could be bonded to an inexpensive silicon host substrate to access the inexpensive,
Epitaxial Lift-Off for Thin Films
553
high circuit complexity available at lower speeds in silicon. Leakage currents between GaAs devices can also be eliminated, since the semiinsulating substrate is removed. To date, thin film GaAs EL0 MESFETs have been bonded to InP,14111421 glass, t431and siliconl44l host substrates, and strained quantum well modulation-doped FETs (MODFETs) have been bonded to glass.l45l The MESFET devices bonded to a glass host substrate were 500 nm thick and exhibited device performance comparable to the same on-wafer devices.l43l The MESFET structure, GaAs (427 mn thick)/GaAs (n, 77 nm thick)/GaAs (n”, 26 nm thick), was grown lattice-matched to a 60 run AlAs etch layer on a GaAs growth substrate. The MESFETs were processed using conventional techniques before separation from the growth substrate. After bonding to the glass host substrate, the 1.5 pm gate length thin film MESFET had a maximum transconductance of 155 mS/mm for a gate voltage of 0.7 V. The same MESFET before separation from the growth substrate had a maximum transconductance of 190 mS/mm for a gate voltage of 0.7 V.1431 GaAs thin film MESFETs have also been fabricated by bonding the epitaxial layers to the host substrate and processing the material into MESFETs after bonding. ~1 The epitaxial layer structure used for these experiments was GaAs (n’, 100 nm thick)/GaAs (n, 200 run thick), which was grown on a 50 nm AlAs etch layer on a GaAs substrate. After separation from the growth substrate, these thin film epilayers were bonded to a nitride or oxide coated silicon substrate. The MESFETs were then fabricated using standard MESFET processes, Thin film MESFETs with a 1.5 pm gate length exhibited a maximum transconductance of 135 mS/mm for a gate voltage of 0 V. The rf performance of these thin film MESFETs on thick thermal oxide was also evaluated. The unity current gain frequency was 12 GHz and the maximum oscillation frequency was 14 GHz for a 1.3 pm gate length and 100 pm gate width MESFET, performance which is consistent with on-wafer MESFETs of these dimensions.l44l When optical devices and circuits are integrated in monomaterial integration schemes using a series of epilayers, the performance of one or more of the devices is usually compromised through the need to accommodate the epitaxial structure and processing of all of the devices in the integrated subassembly. Using ELO, these trade-offs are eliminated, since the thin film devices and the devices on the host substrate can be independently optimized. This has been demonstrated through the bonding of a GaAs thin film MESFET to a InGaAs/GaAs/AlGaAs strained layer single
554
Compound Semiconductors
quantum well light emitting diode. 14il These devices were grown, and thus independently optimized, on separate GaAs substrates. The MESFET was grown on top of an AlAs etch layer, which enabled the separation of the MESFET device layers from the growth substrate. After the bonding of the MESFET to the host substrate containing the light emitting diode, the diode and MESFET were connected through a final vacuum AuGe/Ni metallization, coupled with conventional photolithography. The light emitting diodes had an external quantum efficiency of 1.7% with a relatively high 1 mA threshold current. The emitter/MESFET integration had an output/ input ratio of 54 pW/(V sr).1411 Due to immature device processing technology and low Schottky barrier heights in the InP material system, GaAs circuitry integration complexity is higher than in InP. To introduce higher complexity circuitry to InP integrated systems, GaAs thin film MESFETs have been bonded to InP substrates which contain optical components such as an optical switch.l42l MESFETs fabricated before separation from the growth substrate were integrated onto the InP host substrate; the MESFET epilayers were GaAs (n, 150 nm thick)/GaAs (undoped, 1.5 pm thick), grown on top of a 10 run AlAs etch layer on a GaAs growth substrate. The InP 2 x 2 waveguide switch was independently fabricated in the InP host substrate, and consisted of two colinear waveguides. Switching occurred between the waveguides through the application of a voltage to one of the waveguides. This voltage was switched by the integrated thin film GaAs MESFET. To facilitate the alignment of the GaAs EL0 MESFET to the InP optical switch, a 1.2 urn deep rectangular recess was etched next to the waveguide switch in the InP substrate. This recess was electrically insulated by depositing a 200 nm thick SiO, layer onto the InP structure. This SiO, is stripped from the buffer layer in the region above one of the waveguides to achieve optical switching. After the thin film MESFET was bonded in the recess to the InP host substrate, a final polyimide planarization, metal deposition, and photolithographic process completed the interconnection of the thin film GaAs MESFET to the InP optical switch. Preliminary tests of the optical switch demonstrates successful optical switching.142l Modulation-doped FETs (MODFETs) have also been fabricated in thin film form using EL0.1451 These AlGaAs/InGaAs/GaAs strained quantum well devices, with a gate length of 1 pm, were separated from the growth substrate and contact-bonded to a glass host substrate. The commonsource dc transfer characteristic of these devices were measured both before and after separation from the growth substrate, and demonstrate that
Epitaxial Lift-Off for Thin Films the transfer characteristic process.t451
is not changed by the separation
5.3
Integration
Three-Dimensional
555
and bonding
Complexity of wire-based interconnection in the plane of integrated circuits is currently a processing density limiting factor. Vertical, massively parallel interconnection in three dimensions between planes of circuitry may help to alleviate this interconnection bottleneck. The integration of thin film epitaxial devices directly on top of silicon circuitry in which each thin film device is electrically connected to the silicon circuitry belowt3*l heralds massively parallel processing for applications such as imaging. Likewise, the integration onto silicon host substrates of thin film InGaAsP emitters and detectors which emit at wavelengths to which these silicon host substrates are transparent, has led to the demonstration of vertical optical interconnection of layers of silicon, using the silicon as a transparent host substrate.llll Epitaxial lift-off devices offer a Vertical Electrical Integration. unique opportunity for three-dimensional vertical electrical integration of layers of devices. High quality GaAs or InP-based devices can be integrated directly on top of silicon circuitry with a layer of planarizing insulating material which lies between the thin film devices and the silicon circuitry. One example of a signal processing system which will benefit from this three dimensional connection is optical imaging arrays in which parallel connection of each detector to signal processing circuitry will increase throughput and processing speed due to the capability for parallel processing of each pixel in the imaging array. To fabricate the three-dimensional integrated circuit, a GaAs metalsemiconductor-metal (MSM) detector on top of a silicon circuit was employed. The silicon circuit was a simple transresistance amplifier, which could be inexpensively produced by a foundry. To integrate the circuit and MSM device in three dimensions, the fully fabricated circuit was spincoated with planarizing, insulating polyimide. Using standard photolithography and plasma etching, vias were defined in the polyimide, which exposed the underlying Al pads on the circuit. Gold was then vacuumdeposited to electrically connect the underlying circuit to the top of the polyimide. This gold was patterned for use as interdigitated fingers for an MSM photodetector with bottom contacts, as described in Sec. 4.2. The transfer diaphragm modified EL0 technique, described in Sec. 2.3, was
556
Compound
Semiconductors
used to form the GaAs thin film detector. The GaAs was contact-bonded to the Au fingers on the polyimide to form the MSM detector. The Schottky barrier electrical contact and a stable mechanical bond betweenthe Au and the GaAs was formed through annealing, as described in Sec. 4.2, thereby completing the three-dimensional structure. Figure 9 shows two photornicrographs of the fabricated structure. Figure 9a shows the planarized and metallized circuit, prior to the MSM deposition, with a close-up of the finger region, and illustrates the excellent planarizing properties of the poly imide. Figure 9b is a photomicrograph of the fully fabricated device, with the GaAs on top of the metal fingers shown in Fig. 9a.[38]
(a)
(b)
Figure
9.
Two photomicrographs
film detectors as the top layer. deposition
with
a closeup
properties of the polyimide.
of the fabricated three-dimensional
structure using thin
(a} The planarized and metallized circuit prior to the MSM
of the finger
region
(b} Photomicrograph
GaAs on top of the metal fingers shown in (a}.
illustrating
the excellent
of the fully fabricated
planarizing
device, with the
Epitaxial Lift-Off for Thin Films
557
The response of the circuit was tested using a 1 kHz pulsed 850 nm wavelength laser input delivered to the MSM. No illumination of the surrounding circuit occurred during this test. The output signal was a square wave, with a rise time of approximately 8 msec and a fall time of approximately 12 msec. [381 This performance is typical for such a simple, unoptimized amplifier circuit used for this demonstration. These results indicate that the amplifier circuit, interconnections, and MSM were all working properly. Vertical Optical Integration in Three Dimensions. Vertical optical communication, through stacked silicon and GaAs wafers which contain circuitry, will facilitate connection of layers of processing circuitry for input and output as well as for three-dimensional integration of processing layers toward computational cubes. Optical interconnects can be high bandwidth, low crosstalk, low capacitance, and provide isolation. The integration of InP-based thin film emitters and detectors, which emit and detect at wavelengths to which silicon and/or GaAs are transparent host substrates, enables this three-dimensional optical interconnection. Threedimensional through-silicon wafer interconnection has been demonstrated with InGaAsP-based emitters and detectors integrated onto silicon host substrates. These interconnections have been demonstrated using stacked silicon wafers[“l and using a single silicon wafer in a front to back of wafer communication scheme.1461 The thin film InGaAsP homojunction light emitting diode and InPI InGaAsP/InP p-i-n detector, described in Sec. 5.1, were used to demonstrate vertical optical communication through stacked silicon wafersIll Prior to removal of the substrate from the emitter and detector, broad area metal contacts were deposited onto the surface of the epilayers, and a window was opened in the metallization of the detector. Using selective etches and the transfer diaphragm technique discussed in Sec. 2.3, these devices were separated from the growth substrate, inverted, and bonded to two separate 650 urn thick, polished, nitride coated, metallized silicon host substrates. The window in the detector contact was aligned to a window of the same size in the silicon host substrate metallization. After device planarization, the other side of the emitter and detector were contacted. A window was opened in the top contact of the emitter, and the two silicon wafers were stacked with the detector-bonded wafer on top. Using an infrared back plane mask aligner, the emitter and detector were aligned to complete the three-dimensional integration as shown in Fig. 10. The thin film emitter bonded to the bottom silicon wafer emits through the silicon
558
Compound Semiconductors
wafer which lies above it. The light passes unabsorbed through the top silicon substrate and is detected by the detector, which is bonded to the top silicon substrate. A 2 kHz, 55 mA input square wave to the light emitting diode and a low noise transimpedance amplifier stage at the detector output were used to test the system. The input and output signals are shown in Fig. 11. This first unoptimized demonstration of vertical optical three dimensional integration demonstrated a system power conversion efficiency of 4 x 1()-7.r111
6.0
CONCLUSIONS
Techniques for the separation, transfer, and bonding of single crystal compound semiconductor thin film devices for optoelectronic integration have progressed rapidly in recent years. Materials tests demonstrate that these processes do not have a negative impact upon the material quality. Thin film device studies indicate that, with proper structural design and processing, thin film devices perform as well as or better than comparable on-wafer unseparated devices. Coupled this with the capability for independent optimization of host substrate and thin film device as well as the reduction in reactance due to the elimination of wirebonds, these thin film integrated systems are a high performance alternative to hybrid packaging. A particularly attractive option that thin film device integration opens to designers is the capability to integrate multiple functions and/or wavelength devices onto the same host substrate. Primary issues yet to be addressed in thin film integration is the reliability of these components and whether the potential cost advantage of this type of integration will be realized. The relative reliability of thin film devices has not yet been investigated, although with further maturation of this field, reliability studies will be reported. The potential cost advantages stem from pretesting before integration, additional yield enhancements through repair, and through the use of standard low cost microelectronics processing techniques. The true test of any research result is the success of products in the marketplace which arise from the technology. As products based upon thin film device integration move into the marketplace, this technology will be evaluated, and will succeed or fail based upon the performance and cost advantages that it can offer to the user.
Epitaxial Lift-Off for Thin Films
559
InGaAsP Thin Film Detector
1.3 micron wavelength light
InGaAsP Thin Film Emitter Figure 10. Schematic of the three-dimensional optically interconnected silicon system using thin film InGaAsP-based detectors and emitters operating at a wavelength of 1.3 microns. The thin tihn emitter bonded to the bottom silicon wafer emits through the silicon wafer which lies above it. The light passes unabsorbed through the top silicon substrate and is detected by the detector which is bonded to the top silicon substrate.
600nV
c
2aomv /dlV
WCg'C
-1.rv -06lls
200usIdlv
E-J
1.144ms
Figure 11. Input (lower trace) and output (upper trace) signals from the fabricated threedimensional optically-interconnected silicon system shown in Fig. 10. A 2 kHz, 55 mA input square wave to the light emitting diode and a low noise transimpedance amplifier stage at the detector output were used to test the system.
560
Compound Semiconductors
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(1988)
2. For a good review of current results, see the Special Issue on Solid State Image Sensors, IEEE Truns on Elec. Dev., vol. 38 (1991) 3. Wada, H., Ogawa, Y., Kamijoh, T., Appl. Phys. Lett., 62:738-740 4
Yablonovitch, E., Gmitter, T., Harbison, J. P., and Bhat, R., Appl. Phys. Lett., 5 1:2222-2224
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Konagai, M., Sugimoto, M., and Takahashi, K., J. Ctyst. Growth, 45:277280 (1978)
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Dumke, W. P., Woodall, J. M., and Rideout, V. L, Solid State Elect., 15:1339-1343 (1972).
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Antypas, G. A. and Edgecumbe, J., Appl. Phys. Lett., 26:371-372
8
Adachi, S., Noguchi, Y., and Kawaguchi, H., J. Electrochem. 1053-1062 (May 1982)
9
Private communication with C. Camperi-Ginestet, Technology (1992)
(1975) Sot.,
pp.
Georgia Institute of
10 Yablonovitch, E., Hwang, D. M., Gmitter, T. J., Florez, L. T., and Harbison, J. P., Appl. Phys Lett., 56:2419-2421 (1990) 11 Calhoun, K. H., Camperi-Ginestet, C., Jokerst, N. M., IEEE Phot. Tech. Lett., (Feb 1993) 12 Klem, J. F., Jones, E. D., Myers, D. R., and Lott, J. A., J. Appl. Phys., 66:459-462
(1989)
13 Yablonovitch, E., Sands, T., Hwang, D. M, Schnitzer, I., and Gmitter, T. J.,Appl. Phys. Lett., 59:3159-3161 (1991) 14 Schumacher, H., Gmitter, T. J., LeBlanc, H. P., Bhat, R., Yablonovitch, E., and Koza, M. A., Electr. Lett., 25:1653-1654 (1989) 15 Yi-Yan, A., Chan, W. K., Nguyen, C. K., Gmitter, T. J., Bhat, R., and Jackel, J. L, Elect. Lett., 27:87-89 (1991) 16 Augustine, G., Jokerst, N. M., and Rohatgi, A., Appl. Phys. Lett., 61: 14291431 (1992) 17 Pollentier, I., Buydens, L, Van Daele, P., and Demeester, P., IEEE Phot. Tech. Lett., 3:115-117 (1991) 18 Camperi-Ginestet, C., Hargis, M., Jokerst, N. M., and Allen, M., IEEE Phot. Tech. Lett., 3:1123-1126
(1991)
19 Pan, J. Y., and Senturia, S. D., Sot. Plastics Eng. Tech. Papers: ANTEC ‘91, 37:1618-1621
(1991)
20 Anderson, G. P., Bennett, S. J., and DeVries, K. L., Analysis and Testing of Adhesive Bonds, Academic Press, New York (1977)
Epitaxial Lift-Off for Thin Films 561 21 Jokerst, N. M., Defense Advanced Research Project Agency DSRC Workshop on Optoelectronic Arrays (July 1992) 22
Burns, G. F., and Fonstad, C. G., Appl. Phys Lett., 61:2199-2201 (1992)
23
Buydens, L, De Dobbelaere, P., Demeester, P., Pollentier, I., and Van Daele, P., Opt. Lett., 16:916-918, (1991)
24
Yablonovitch, E., Kapon, E., Gmitter, T. J., Yun, C. P., and Bhat, R., IEEE Phot. Tech. Lett., 1:41-42, (1989)
25
Hargis, M., Brown, J., and Jokerst, N. M., “Epitaxial Lift-off Thin Film GaAs Metal-Semiconductor-Metal Photodetectors with Back Passivation,” IEEE Lasers and Electro-Qptics Society 1992 Annual Meeting, (Nov 1992)
26 Private communication with C. Camperi-Ginestet and K. H. Calhoun, Georgia Institute of Technology (1993) 27
Sell, D. D. and Casey, H. C., Jr., J. Appl. Phys., 45:800-807
(1974)
28 Yan, R. H., Simes, R. J., and Coldren, L. A., IEEE Phot. Tech. Lett., 1:273-275
29
(1989)
Calhoun, K. H. and Jokerst, N. M., Appl. Phys. Lett., vol. 62 (May 24, 1987)
30 Calhoun, K. H. and Jokers& N. M., Opt. Lett., vol. 18 (June 1993) 31 Camper-i-Ginestet, C. and Jokers& N. M., to be submitted to IEEE Phot. Tech. Lett., (Jan 1993) 32 Schnitzer, I., Yablonovitch, E., Caneau, C., Ersen, A., Gmitter, T. J., “Ultra-High Spontaneous Emission Quantum Efficiency, 99.7% Internally and 72% Externally, From Epitaxially Lifted-Off GaAs/AlGaAs Double Heterostructure,” Post Deadline Papers for the Lasers and Electro-Qptic Society Meeting on Integrated Optoelectronics (Aug 1992) 33. Camperi-Ginestet, C., Jokerst, N. M., and Fike, S., “Manufacturable Inverted Metal-Semiconductor-Metal Thin Film III-V Compound Semiconductor Detectors,” Optical Society of America Annual Meeting (Sep 1992) 34 Yablonovitch, E., Kash, K., Gmitter, T. J., Florenz, L. T., Harbison, J. P., and Colas, E., Electr. Lett., 25: 171-172 (1989) 35 Pollentier, I., Demeester, P., Ackaert, A., Buydens, L., Van Daele, P., and Baets, R., Electr. Lett., 26:193-194 (1990) 36. Yi-Yan, A., Chart, W. K., IEEEJ. Quunt.Electr.,
27:717-725
(1991)
37. Yi-Yan, A., Chart, W. K., Gmitter, T. J., Florenz, L. T., Jackel, J. L., Yablonovitch, E., Bhat, R., and Harbison, J. P., IEEE Phot. Tech. Lett., 1:379-380 38. Camperi-Ginestet, C., Kim, Y. W., Jokerst, N. M., Allen, M. G., and Brooke, M. A., IEEE Phot. Tech. Lett., 4:1003-1006 (1992)
562
Compound Semiconductors
39. Chart, W. K., Yi-Yan, A., Gmitter, T. J., Florenz, L. T., Jackel, J. L., Hwang, D. M., Yablonovitch, E., Bhat, R., and Harbison, J. P., IEEE Phot. Tech. Lett., 2: 194-196 (1990) 40. Wilt, D. M., DeAngelo, F. L., Thomas, R. D., Bailey, S. G., Landis, G. A., and Brinker, D. J., “Peeled Film GaAs Solar Cells for Space Power,” Proc ConJ on Photovoltuics (1992) 41. Pollentier, I., Buydens, L., Ackaert, A., Demeester, P., Van Daele, P., Depestel, F., Lootens, D., and Baets, R., Elect. Lett., 26:925-927 (1990) 42. Demeester, P., Pollentier, I., DeDobbelaere, P., Brys, C., and Van Daele, P., Semicond. Sci. Tech., pp. 1124-1135 (1993) 43. Van Hoof, C., De Rae&, W., Van Rossum, M., and Borghs, G., Elect. Lett., 25:136-137, (1989) 44. Shah, D. M., Chart, W. K., Gmitter, T. J., Florenz, L. T., Schumacher, H., and Van Der Gaag, B. P., Elect. Lett., 26: 1865-1866 (1990) 45. Klem, J. F., Jones, E. D., Myers, D. R., and Lott, J. A.,“Characteristics of Lift-Off Fabricated AlGaAs/InGaAs Single-Strained-Quantum-Well Structures on Glass and Silicon Substrates, “ Proc. ofthe Inter. Symp. on GaAs and Related Cmpds, Atlanta, GA (Sep 1988) 46
Camperi-Ginestet, C., Calhoun, K., Augustine, G., and Jokerst, N., “Through Silicon Wafer Optical Communication Using Monolithic Thin Film Epitaxial Lift-Off InGaAsP Emitters and Detectors,” Proc. of the Conference on Lasers and Electra-Optics, Los Angeles, CA (May 1992)
11 Packaging Eric I! Chan
1.O INTRODUCTION As the technology of III-V compound semiconductor material and devices is maturing, very complicated device structures, such as quantum well devices and mutli-functional optoelectronic integrated circuits (OEIC), can be fabricated in a manufacturing environment.lll The technology of packaging III-V compound semiconductor devices has evolved with these new technological developments. Material systems such as GaAlAs/GaAs, InGaAsP/InP and InGaAs/InP are important for fabrication of laser diodes, optical amplifiers, LEDs, and detectors. GaAs is the material for highfrequency microwave and high speed digital integrated circuits. Modern III-V compound semiconductor device packaging is a cross-disciplinary science which combines the knowledge in optics, material science, and electronic, mechanical and thermal engineering. This chapter discusses recent developments in packaging technology for (a) III-V optoelectronic devices, (6) high density, multifunctional and multichannel devices for optical interconnect applications, and (c) GaAs digital and monolithic microwave integrated circuit.
563
564
Compound Semiconductors
2.0
III-V OPTOELECTRONIC
2.1
Laser Diode Packages
DEVICE PACKAGES
Demonstration of the first laser diode in 1960 stimulated intense interest in the technology of laser diodes for applications in many different areas. Laser diodes are used as light sources for long distance fiber optic communication, powering sensors for aerospace and military applications, pumping high power solid state lasers, and writing compact optical disc memory. In the following sections, laser diode packaging issues for fiber optic applications are discussed. These principles are applicable to packaging laser diodes for other applications. Laser Diode Package for Fiber Optic Transmitters. The basic elements of a laser diode transmitter package is shown in Fig. 1, where the laser diode is bonded to a ceramic subcarrier, which depends on the type of laser being used. The laser diode subcarrier is mounted on top of a thermoelectric cooler. Special coupling optics are placed between the fiber and the laser diode. A monitor photodiode is mounted at the back facet of the laser diode for monitoring the output power of the front facet. Another element inside the package is a thermistor, which is bonded on the surface of the laser diode subcarrier, to monitor the temperature of the laser diode during operation. The transmitter hybrid circuit is mounted very close to the laser diode subcarrier for high speed operation. Depending on the speed of the transmitter, the laser diode package can be a dual-in-line package for data rates below 600 Mbit/s. For data rates above 600 Mb/s, a butterfly package with a high speed ceramic feedthrough is preferred. In the following, the important considerations in laser diode package design are discussed. Some of these design considerations are applicable to LED packaging also. Thermal Consideration. Diode Junction Temperature. The light output power vs. current (L-I) characteristic of a laser diode depends on the junction temperature of the laser diode. In a typical laser diode packaging process, the laser diode chip is mounted on a carrier by eutectic bonding, using solder preforms as shown in Fig. 2. The electrical circuit model that describes the junction temperature of the laser diode is shown in Fig. 3. P,,, is the power dissipation and Tj is the junction temperature of the laser diode. With the diode mounted junction side up, Tj can be calculated as follows:
Packaging
565
P DLD= IV - p,(1) P DLD
Eq.
(1)
= Uj
- TJ@LD
Tj =T,+PD,x
C
@BW ’ @LD @BW +‘LD
+@AuSn
>
+ %,O,
+%d/Pb
+@A&
I
where: P DLo= Laser diode power dissipation I = Laser drive current V = Laser diode bias voltage P,(I) = Laser diode optical output power at I Tj = Laser Diode Junction temperature Tr = Temperature of the package o,, = Thermal resistance of the bond wire @Lo= Thermal resistance of the laser chip 0 Ausn= Thermal resistance of the AuSn preform 0 A12of= Thermal resistance of the alumina laser subcarrier 0 Indr’Pb = Thermal resistance of In/Pb (50/50) solder bonding the ceramic subcarrier to the package Equation (1) can be applied to an actual example such as a GaAs laser diode chip with a 600 pm cavity length, 400 pm width and thickness of 100 pm. The continuous wave (CW) light output power vs. current (L-I) and voltage vs. current (V-I) characteristics are shown in Fig. 4. The device was bonded junction side up, as shown in Fig. 2. Assume the diode is operated at point A above the threshold current. Using a first order approximation, thermal resistance is calculated as 8 =
7/(K x A)
where 8 is the thermal resistance of the material, K is the effective thermal conductivity, and r and A are the thickness and area of the material, respectively. If the package temperature (T,) is maintained at 3O”C, the laser diode junction temperature is ---h_--+ Tj=T,,+PDLD x
K L.Dx ALD
t4uS”
t,,+ KLD
tAuSn KAUS" XA~u~n
X~~
KmnXA~~n
tBW XK~uxA~~ tBW +K.&Bw
hO,
hnd/Pb
+K AI,O, x AAI,O, +K h&Pb Yhmi/Pb
566
Compound Semiconductors
Using the data provided in Table 1 and point A of Fig. 4, then Tj = 30°C + [(O.O3 X
1.7)
-5
X
1O-3] X 10.187”C
Tj = 30.5”C
Thermiater
Figure
1.
Back face
Schematic diagram of the elements inside a typical laser diode package.
Au wire
Figure 2.
bond
A laser chip die bonding schematic.
Packaging
567
%l/Pb sddw
TP
+
I
Figure 3. Electrical circuit model for the junction temperature of the laser diode shown in Fig. 2.
Figure 4. L-I and I-V characteristics
of a laser diode.
568
Compound Semiconductors
Table 1. Material Parameters Characteristics as in Figure 3 AuSn Preform
for the Diode
Laser
with Operating
Bond Wire (BW)
Alumina A&O,
WPb solder
GaAs Laser Diode
t (in)
0.001
0.02
0.01
0.001
3.94 x 10”
K (W/i#C)
6.86
8.08
0.47
0.61
1.12
A ( in2)
3.726 x lo4
10%
6.25 x 1O-2 6.25 x 1O-2 3.726 x 1O-4
Thermoelectric Cooler Requirements.
Most of the laser diode package contains a thermoelectric cooler (TEC) and a thermistor. During the laser diode operation, the TEC and the thermistor are connected to a feedback loop circuit to stabilize the junction temperature of the laser diode. Selecting the right TEC for a laser diode package depends on several parameters including the heat load capacity and performance curves of the TEC, the maximum laser diode package temperature, the maximum allowable power consumption, and the dimensional constraints of the laser diode package. Figure 1 shows a laser diode mounted on a single stage TEC inside a package. There are four sources of heat load on the thermoelectric cooler: (i) dissipation from the laser diode on the top surface of the TEC; (ii) conduction by the fibers, bond wires, and other elements on the top of the TEC; (iii) radiation from the walls of the package; and (iv) convection of heat by the inert gas between the top of the TEC and the warm elements of the package. For a typical 1.3 pm InGaAsP/InP double-channel planar buried heterostructure (DCPBH) laser diode package, the typical heat load from all four sources is about 0.5 W at 75°C. Using a model SP5007 TEC with a performance curve at 75°C as shown in Fig. 5,f21 a temperature difference (AT) of 50°C is needed to cool the laser to 25°C. Operating the TEC at point A will achieve the cooling condition for the laser diode. At this operation point, the driving current for the TEC is 1 amp at 1.25 volt. Therefore, the maximum power dissipation (Pd) to the base of the package will be: P, = (1.25 x 1 + 0.5) = 1.75 watts For a laser diode package with a copper-tungsten base, the temperature rise due to this power dissipation is negligible. Therefore, stabilization of the
Packaging
569
laser diode temperature by the thermoelectric cooler is a practical cooling method for terrestrial telecommunication applications where the maximum operating ambient temperature is about 70°C.
PERFORMANCE NITROGEN SP5007 100
(I
ATM) COP
OF TA
(C)
-
Tektronix
SP5007 75
HSR
with
(C/WI
-
0
Te-75 HEAT LOAD (Watt)
00
0.00
60
2.20 2.40
2
1
OKLJ-1 0
.4
.6
CURRENT
Figure 5. Performance Industries.[2]
1.2
116
i
(AMPS)
curves at 75°C of a model SP5007
TE cooler from Marlow
Optical Design and Fiber Feedthrough Requirements. Aligning the fiber to the laser diode to achieve maximum coupling and attaching the fiber to the package reliably after the alignment are two of the main design objectives of a laser diode package. This process is called fiberpigtailing. The following issues must be considered:
570
Compound
Semiconductors
Fiber Lensing Technique. In coupling single mode fibers to a laser diodes, there are three techniques which can be employed. First, direct coupling with a cleaved fiber is the simplest becauseno extensive lensing of the fiber is required. But the coupling loss is about -10 dB which is the highest of all approaches. The secondtechnique is to form a hemispherical microlens on the tip of the fiber. This is formed by first tapering the fiber to a point using hydrofluoric acid, and then rounding it to a radius r by melting, as shown in Fig. 6a.[3] This technique can be implemented using a commercially available fiber fusion splicer. Typical coupling loss for this technique is about -3 dB; the alignment tolerance is about 0.5 ~m. Recent progress has been reported[4]in the fiber lensing technique using CO21aser micromachining to form a hyperbolic shapeat the tip of the fiber. Coupling efficiency of over 90% with a single mode fiber was demonstrated. A photomicrograph of a hyperbolic tip single mode fiber is shown in Fig. 6b.[4] The third technique is a double lens design as shown in Fig. 7. This system consist of two lenses. The basic concept of this schemeis: the first lens magnifies the size of the laser diode at point A; the second GRIN (gradient index) lens matches the laser diode image at point A to the core size of the fiber. This scheme is also called the confocal system. This systemachievesa coupling efficiency with a typical loss of about -I dB and the alignment tolerance is about 2 to 4 ~m. This optical schemeis also more difficult to implement. Figure 8[3] summarizes the results of the four different coupling schemes. r-
-'-I 125..m
... 11 ,.11 m.
1--
(a) Figure 6. (a) Fiber with microlens tip.[4]
(b) tapered microlens.[3]
(b) Single mode fiber with
hyperbolic
Packaging Lens
5 71
1 Lens
2
I SMF
3.6 mm
4
t---* 119 vnl
l
Lz
Ll
Figure 7.
Schematic of a confocal optical design.[13] (01990
FIBER SCAN ALONG
IEEE.)
Y AXIS
0-
-?. -
i
2 2
-4
-
-0
-
.
-
.
-12
-
0 CLEAVED
-14
-
-12
. -
A 8pm MICROLENS 16pm
’
’ -0
FIBER
’
-4
’
’
’ 0
DISPLACEMENT
Figure 8.
.
.
,:
-10
l
A
9+*”
.
-
-16
d
.
-0
_
.
:
’
’ 4
’
I S
I
, 12
(MICAONSI
Comparison of three different fiber-to-laser diode coupling techniques.[3]
Fiber Attachment to Package. Attachment of the fiber to the package involves metallization of the fiber to a specific length, usually with Ti/Pt/Au metallization. The fiber is first inserted into the package through the fiber feedthrough of the package as shown in Fig. 1. Special fiber gripping tweezers and micropositioners are used to align the fiber with respect to the laser chip. Movement of the fiber in X, Y and Z directions is needed to obtain maximum coupling. Once the active alignment is finished, the fiber is first soldered in front of the laser chip, and then it is soldered to fiber feedthrough inside the package wall. Additionally, high temperature epoxy is used to attach the fiber to the part of the fiber feedthrough outside
572
Compound Semiconductors
the package for strain relief. The other method is to first solder the fiber to a ferrule tube which is then laser-welded to a miniature saddle. This saddle is welded to the laser submount as shown in Fig. 9. In addition, the fiber is partially soldered inside the ferrule tube, with the unsoldered part of the fiber functioning as a shock absorber. Large stresses introduced into the package are completely relieved. Using this technique, a coupling variation of about 1 dB over a temperature range of -20°C to 70°C and 100,000 hours of package life was reported.[51
-
Figure 9. Fiber attachmnent
CHIP
by laser welding.[51
Automuiion Tools. Automation tools are commercially available for active alignment of fibers to laser diodes or other types of optoelectronic devices. These automatic systems usually utilize computer controlled dc motors for coarse alignment and positioning of the fiber to the optoelectronic device. Fine alignment is then performed by piezoelectric motors for movement of the fiber in step sizes of 0.1 pm or less, After the alignment, the system will attach the fiber to the package by solder or epoxy. The alignment results will then be characterized automatically after the fiber bonding process is finished. Figure 10 shows a commercial automatic fiber alignment system.
Packaging
Figure
10.
Photograph
(Courtesy of the Kaptron
of a commercial
automatic
alignment
system from
573
Kaptron.
Company.)
High Speed Laser Diode Package. Laser diode packagesoperating below 600 Mb!s use 14 pin dual-in-Iine packageswith glass-to-metal sealed electrical pins. For laser diodes which operate above 600 Mb!s, butterflytype packages with multilayer ceramic electrical feedthroughs are preferred. In designing a high speedelectrical feedthrough, it is important to have proper impedance-matchingfor the transmission line going through the wall of the package. In general, the parasitic elementsassociatedwith a laser diode package are show in Fig. II, where ~ is the series resistance, Cp is the chip parasitic capacitance, and 4 is the bond wire inductance. For high data rate applications, an impedance-matching resistor, ~, is connected in series with the laser diode to reduce signal reflection. Using the analysis in Ref. 6 for the laser bias above the threshold, the responseof the laser packagecan be separatedinto two parts: intrinsic laser modulation
574
Compound Semiconductors
response, R, and parasitic modulation response, R,,. The total response which includes the test detector response, R,,, is expressed as
which may also be expressed in decibels as
With a wire bond inductance, I+,, of 1.O nH and chip parasitic capacitance, C,, of about 2 pF, the small signal modulation response of a semi-insulating buried crescent (SIBC) laser packaged with a high speed K-connector, is summarized in Fig. 12. Curve A is the laser intrinsic response, curve B is the parasitic roll-off, curve C is the test detector response, and curve D is the total response. Measured data are the solid dots. Figure 13 shows the parasitic modulation response for different values of Lt, and Cr. Results of this analysis indicate that the high frequency characteristics of a laser diode package is affected by the laser chip parasitic capacitance and bond wire inductance. Hermetic@ and Coeffkient of Thermal Expansion (CTE) Matching. Before the laser package lid is sealed, it is baked to about 100°C in a stainless steel chamber flushed with dry nitrogen. Lid sealing is done using a seam welder inside a dry box. The gas mixture during the lid sealing is 10% helium and 90% nitrogen. The hermetic&y check verifies the mechanical integrity of the package body and solder seal of the fiber to the package. Gross leak hermeticity test is performed with the package filled with inert gas. Then the package is submerged in a type 2 perfluorocarbon fluid. The gas inside the package is heated to cause expansion. If gross leaks exist, gas inside the package escapes and create a visible trail of bubbles. The fine leak hermeticity test is accomplished by using a helium leak detector with a mass spectrometer. A leak rate of less than 5 x 1O-*cc/set is required for many applications. Leak checking is done after many cycles of temperature testing from -55°C to 125°C to assure the mechanical integrity of the package. After the package passes the hermetic&y test, electrical and optical coupling tests of the laser package are needed to assure the coupling efficiency of the fiber. Other testing such as humidity, mechanical shock, and vibration are necessary to assure a good quality package.
Packaging COAXIAL
Figure
MICROSTRIP
11. Parasitic circuit elements in a high speed laser diode packageM
-26
_ A. -.- 8. -------
-25
C. D. -
5 z”
-30
-
-35 0
INTRINSIC PARASITIC
RESPONSE RESPONSE
TOTAL DETECTOR RESPONSE RESPONSE
. . . . . MEASURED
DATA
I
I
I
1
2
4
6
8
10
FREQUENCY
Figure
5 75
12
14
16
12. Small signal modulation response of a SIIK iaw
$
-2 -3-
s E: d .o
_4_
-5
-
B-
-7
26
&de pzckage.t61
-
s
,: 2 0”
1S
(GHz)
-
0.1 nH, 1 pF
--
0.1 nH. 2 pF
---
1.0 nH. 1 pF
----
l.OnH,ZpF
-
-6-
0
2
4
6
13
10
Frequency
12
14
16
16
20
iGHzt
Figure 13. The modulation response of a SIEiC laser package: with different Lb and CJ61
576
Compound Semiconductors
The operating temperature range of a laser diode package (in general for all fiber optic packages) is limited in part by the thermal expansion mismatch between the optical fiber and the package. Mismatch in expansion can cause fiber-to-laser misalignment and/or fiber breakage when the package goes through repeated temperature cycles. Copper-tungsten (CuW) and Kovar, with CTE of about 6 x 1O-‘V’C,are preferred materials because of their close CTE match to the glass fiber, which has a CTE of about 0.5 x lO?‘C. Kovar has a lower cost because it is easier to machine; but the thermal conductivity of CuW is higher than Kovar. Figure 14 shows the CTE vs. thermal conductivity for selected materials used to fabricate a laser diode package.
t i iii//I
50
100
500
l,ooo
Thermal Conductivity (W/m-K)
Figure 14. CTE vs. thermal conductivity of the material in a laser diode package. (Courtesy of Sumitomo Electric.)
Packaging
577
Laser Diode Fiber Optic Package Long Term Reliability Model. The long term reliability of a laser diode package strongly depends on the creep characteristics of the solder that bonds the fiber for optimum coupling of the laser light output. For coupling of single mode fibers to laser diodes, failure occurs when the solder creeps more than 0.1 pm. As shown in Fig. 1, the fiber forms a cantilever beam from the package wall to the solder bond. The creep rate depends on the length, L, and the deflection of the fiber after the fiber is bonded. At room temperature, the typical creep rate of Sn/Pb solder is about 5 x lo-l2 in/in/day. Assume a solder length of 0.05 in, then the absolute creep is Cso,der= (5 x 10-2)x (5 x lo-12)inches/day = 2.5 x lo-l3 inches/day
Therefore, the time to failure (fiber movement of 0.1 pm) is tf = (0.1 pm) x (3.94 x 10m5inches/pm) 2.5 x lo-l3 inches/day tf = 4.3178 x lo4 years To calculate solder creep at elevated temperature, the Arrhenius relationship is use~I:[~l
where A = constant, E, = activation energy (0.65 eV), k = Boltzmann’s Constant (8.62 x 10m5eV/OK) and T = absolute temperature in “K. Using these results, time to failure at 125°C can be calculated t,(300”K)
A=
= 4.588 x 10-3hrs
0.65 exp
8.62 x 1C5 x 300
t,(398.K) = 4.588 x 10m3x exp
0.65 = 88.59years 8.62 x lO-5 x 398
578
Compound
Semiconductors
These calculations show that proper fiber soldering provides long term fiber-to-1aserdiode coupling reliability. Figure 15 shows the inside view of a hermeticlasertransmitterpackagereportedby Figueroa,et al.[8] This package is designedfor high reliability and extendedtemperaturerangeoperation.
Figure
15.
temperature
2.2
LED
Inside vie~. c.f a prntotype
hermetic
laser transmitter
package for extended
operaiion.[8]
Packages
The LEO package design considerations are very similar to those for laser diode packages. Unlike laser diodes, LEOs are not threshold devices alld their output power is less sensitiveto temperaturevariations. Therefore, active cooling and feedbackcontrol of the device temperature is not needed. In general, LEOs emit lower power than laser diodes and LEO transmitters are generally used in low cost data links for short distance local area applications. For tbeseapplications, the data rates are below 200 Mb/s and
Packaging
5 79
the driver circuitry for the LED transmitter package is simpler than for laser diode packages. There are two types of LED structures, as shown in Fig. 16 and Fig. 17, surface-emitting and edge-emitting structures. For edge-emitting LEDs, the submount design is similar to the laser diode. For surface-emitting LEDs, the submount needs 90” electrical leads in a transmitter package so that the emitted light cone can be parallel to the package base for fiber alignment. For high reliability operation, heat dissipation and optical alignment are two important design considerations for LED packages.
n InP subslrole p InGaAsP(ocIive
Figure 16. Structure of a surface-emitting
Figure 17. An edge-emitting
LED.
layer)
(Courtesy of Sumitomo Electric.)
LED structure.[91 (01983 IEEE.)
580
Compound Semiconductors
Figure 18 shows the I-V and L-I characteristics of a 1.3 pm InGaAsP/InP surface-emitting LED. The typical operating current of this LED in a transmitter package is about 50 to 100 mA. The LED drive current is higher than that of a laser diode, and it dissipates more heat during operation. Typical power dissipation for an LED during operation is about 0.2 watt. Having a good heat sink will reduce the junction temperature of the LED which increases the output power and enhances long term reliability. LED lifetimes greater than lo7 hours at 70°C has been reported.191 Heat Dissipation Considerations.
1000
2.0 ,
I (mA)
Figure 18. I-V and L-I characteristics of a 1.3 pm surface-emitting LED.
Optical Considerations. The genera1 rule for designing an optical system for a surface-emitting LED package requires the LED emitting diameter to be smaller than the core diameter of the fiber. If the LED diameter is larger than the fiber core diameter, according to the Liouville’s theorem, lensing the fiber will not increase the coupling efficiency. The coupling efficiency of the LED is proportional to the square of the numerical aperture of the fiber if the fiber core diameter is smaller than the emitter diameter of the LED. For LEDs with an emitting diameter smaller than the fiber core diameter, lensing of the fiber or external lenses will increase the coupling efficiency. Most of the discrete LEDs are in TO 18 or TO 46
Packaging
581
packages with a double lens optical system, as shown in Fig. 19, to maximize the fiber coupled power. A miniature ball lens is attached to the chip to collimate the light. The collimated beam then passes through a focusing lens on the cap of the package. A focus spot that matches the core diameter of the fiber is formed at a distance of about 1.6 mm from the lens tip of the cap. The positional tolerance of this package design is shown in Fig. 20. Because of its manufacturability, this type of LED package is low cost and has good reliability.
Figure 19. A surface-emitting
LED in a TO 46 package.
(Courtev
of ABB HAFO.)
Figure 20. Alignment tolerance of a 50/125 pm cleaved fiber to an LED package like that shown in Fig. 19. (Courtesy of ABB HAFO.)
582
Compound
Semiconductors
Several LED transmitter packages for data link applications are shown in Fig. 21. A LED optical subassembly(OSA), used in a data link transmitter package, is shown in Fig. 22.(101 This OSA contains an InGaAsP/InP surface-emitting LED and a ball lens to increase the couple power from the LED to the fiber. The OSA is inserted through the alignment sleeve. The LED is mounted on a headerwhich also functions as a heat sink. Figure 23(9]summarizes different approachesof LED to fiber coupling. The best optical system is a device with an integral lens (formed by photo-electrochemical etching) coupled to a lensed fiber. This system has the best lateral alignment tolerance as shown in Fig. 24.[111
Figure 21. Commercial LED transmitter data link packages. (Courtesy of AT&T, Sumitomo E/ectric. and OCP.J
Packaging
583
device
\
Ball lens
Figure 22.
LED
(01987 AT&T.
optical subassembly inside a 1.3 pm fiber optic data link transmitter.[lOl Reprinted
with permission.)
0
a9
JL 0
INTEGRAL LENS
TRUNCATED LENS
LENSED FIBER
BUTT
COMPLEXITY
Figure 23.
-
Comparison of different LED to fiber coupling schemes.[9] (01983
IEEE.)
584
Compound Semiconductors
2
SOURCE-RECEIVER
Figure 21.
COUPLING
ENHANCEMENT
(RELATIVE
TO BUTT
I
LATERAL
I NON - IMAGING
SEPARATION
COUPLINGI
MICROSPHEAf
(f/O)
Lateral alignment tolerance of a lensed fiber to a surface-emitting
LED.[“l
In edge-emitting LED packages, the fiber is actively aligned to the LED in the X, Y, and Z directions. Figure 17 shows an edge-emitting LED structure. It is very similar to a stripe-geometry laser diode. Lasing is suppressed by depositing an anti-reflective coating on the laser facets. The confining layers above and below the active layer have a lower index of refraction, which provides waveguiding in the direction perpendicular to the junction plane. In the direction parallel to the junction plane, there is no waveguiding mechanism and the light emission in this direction is the same as a Lambertian source. Therefore, the emitting light cone of an edgeemitting LED is narrower in the direction perpendicular to the junction. A typical far-field angle in the direction parallel to the junction plane is about 120’; in the direction perpendicular to the junction plane, the far-field angle is about 35”. Figure 25a shows an edge-emitting LED submount design.[‘*l In this design, a beryllia block is used as a heat sink material because of its good thermal conductivity, good CTE match to GaAs, and ease of machining. Metallization is deposited over the surface of the block. An insulating standoff is attached to provide electrical contact to the n-side of the LED chip. The p-side (junction side) of the chip is eutectically bonded on the surface of the step on the Be0 block. The step is used for fiber alignment when the block is mounted into the LED package housing. Figure 25b shows the cross section of a typical edge-emitting LED package.[‘*l
Packaging
585
(4
Figure 25. (a) Submount design of an edge-emitting package?*] (Courtev of CodenoN Technology.)
2.3
Semiconductor
LEDPI
(5) An edge-emitting
LED
Optical Amplifier (SOA) Packaging
The principle of a semiconductor amplifier is shown in Fig. 26.[131 Light couples into the active semiconductor waveguide which is formed by an angle-facet semiconductor laser with an anti-reflective coating on both facets. Optical gain results from electron-hole recombination, induced by
586 Compound Semiconductors stimulated emission from the input signal. An SOA can be used to amplie weak signals due to attenuation over long distance fiber optic links, or to overcome loss due to splitting in complex optical interconnection networks. The packaging of a semiconductor amplifier requires incorporation of two single mode fiber pigtails; one fiber is aligned for each facet of the amplifier chip. There are two approaches recently reported to achieve good coupling efficiency and high gain. They are described in the following two sections.
f liizf!T TOP VIEW
P0
-- 00
_
--a
P
mm
4
ri n
Figure 26.
f
8ic 7” 0, = 22”
Basic principle of a semiconductor optical amplitier.~‘3] (01990
IEEE.)
Use of Confocal Optics with a Built-in Active Alignment Screw.
This approach, reported by Reith et al.,[131uses a dual-lens coupling system as shown in Fig. 7. The SOA is a 1.3 pm InGaAiP/InP crescent-type buried heterostructure with a 7” angle tilted facet. A sapphire ball lens about 1 mm in diameter (index of refraction, n = 1.75) is positioned to provide a 10x magnification of the 1 pm laser amplifier beam waist. The device-to-ball lens distance is about 150 pm. The second lens was a gradient-index lens attached to the end of the single mode fiber to provide a 2x magnification of the 5 pm single mode fiber beam waist. The distance between the two lenses is about 3.5 mm for optimum coupling. A fiber alignment tolerance of about f 4.5 pm in the lateral direction and f 279 pm in the axial direction was achieved. The angular alignment tolerance is about f 1.6”. Figure 27 shows the general schematic of this dual-lens SOA package. Two ball lenses are mounted directly on the chip carrier with two chamfered holes formed by electrical discharge. One ball lens is seated on each side of the amplifier’s emitting edge. The chip carrier is then inserted into the package housing. Single mode fibers are aligned at the input and
Packaging
587
output ends of the package and then clamped with set screws. After alignment, the fiber cavities are backfilled with epoxy to lock the fibers in place. This dual-lens approach has relaxed the single mode fiber to laser diode alignment tolerances from 0.1 pm to over 4 pm. Coupling efficiencies from 25% to 40% were achieved. An amplifier fiber-to-fiber gain of about 10 dB was reported.[131
eatewe
Figure 27.
A dual-lens SOA package design schematic.[‘3]
(01990
IEEE.)
Dual-Temperature-Zone Fiber Soldering Technique. This SOA packaging technique was reported by Boudreau et al.[141The schematic of this approach is shown in Fig. 28. This device is a 1.3 urn InGaAsP/InP ridge waveguide structure with a 7” angle tilted facet. Two thermoelectric coolers are used as separate temperature controllers for soldering the input and output single mode fibers. The SOA carrier was slotted to enhance the thermal isolation between the two zones. Mechanical reinforcement is incorporated near the center edge of the carrier to maintain flatness and reduce flexing of the carrier. The first fiber was aligned and soldered to the zone where the SOA was located. This zone was then cooled by the TEC to reduce the heating due to fiber soldering in the other zone. The fiber on the other zone was then bonded by the same type of solder. The heating and cooling during the
588
Compound Semiconductors
soldering processes was achieved by applying current to the TEC’s with proper polarities. The top view of this SOA is shown in Fig. 29. This package had achieved fiber-to-fiber gains of 19 to 2 1 dB and a coupling loss of less than 5 dB per facet. Because the soldering temperature is locally controlled by the TEC in each zone, reworking of a poorly aligned fiber can be accomplished very easily. Fiber blocks _
coolW#
Figure 28.
Carrier Side View
Schematic of a dual-temperature-zone SOA packageJ4]
TEC+ THERYTHERM+ N.C.
Figure 29.
KC.
@I991
IEEE.)
lEC N.C.
Top view of the dual-temperature-zone SOA package as shown in Fig. 28.[14]
N. C. designates the package pins that are not connected. TEC+ and negative pin contacts for the thermoelectric
coolers.
positive and negative pin contacts for the thermistors.
and TEC- are the positive
Therm+
(01991
and therm- are the
IEEE.)
Packaging 2.4
589
Detector Packages
InGaAs PIN Detector. Highly reliable InGaAs layered detector structures can be produced in a high-throughput manufacturing process using the mature VPE or MOCVD techniques. A high sensitivity and reliable 1.3 pm fiber optic receiver has been made using InGaAsLInP PIN detector. There are two types of PIN detectors, the front-illuminated and the back-illuminated structures, as shown in Figs. 30a and b.[151[161 The front-illuminated structure does not require alignment of the backside window to the front-side contact, therefore they are easier to fabricate. Most of the commercially available PIN detectors are front-illuminated. Figure 31 shows a front-illuminated PIN detector mounted on a ceramic header. The diameter of the light detection area of the PIN depends on the speed and sensitivity requirements; it ranges from 20 pm to a few hundred pm. The basic criteria is to select a detector with a surface area that allows for maximum collection efficiency of the optical signal without a sacrifice in capacitance and dark current. Figure 32 shows the reverse I-V and C-V characteristics of a 100 pm PIN detector. The typical operating voltage of a PIN is -5 volts. With a diameter about 100 pm, a high quality PIN has a dark current lower than 0.5 nA at this bias voltage. As compared to light emitting devices, PIN diodes dissipate negligible heat to the package. Most of the heat dissipation in a receiver package originates from the preampliFigure 33 shows several commercial fier and post-amplifier circuits. receiver packages used for data link applications. Another technique to package the PIN detector is to use the flip-chip bonding process introduced by IBM.Il’Il The advantage of this technique is that it allows the InGaAs/InP PIN detector to be connected to complex GaAs or Si integrated circuits with very short interconnection lengths. It reduces the package parasitics and improves the speed and performance of the receiver package. u*][~~] Figure 34 shows the cross section of a flip-chip bonded PIN detector.[‘*l This process relies on the confinement of a controlled volume of solder between the wettable metal pads of known area on the PIN detector and on the substrate. The pads are surrounded by a non-wettable region. Surface tension forces in the molten solder bring the PIN detector into alignment with the substrate pads. An alignment tolerance of 1 pm has been reported.1191 A theoretical model of the flip-chip process has been reported.[201[211
590
Compound
Semiconductors
(a)
(b)
Figure
30.
(a) A front-illuminated
(b) A back-illuminated
PIN.[16]
PIN.[15]
(r{;)1987 AT&T.
Reprinted
with permission.)
(r{;)1981IEEE.)
SA carrier
Figure
31.
A front-i1luminated
PIN mounted on a ceramic header.
(Courtesy of Fujitsu.)
Packaging
0
2
Figure 32. I-V and C-V characteristics
4
6
6
591
10
of a 100 pm diameter PIN detector.
High Speed Metal-Semiconductor-Metal (MSM) Detector. MSM detectors consist of an interdigitated pattern of metal fingers deposited on a semiconductor substrate as shown in Fig. 35. During operation, a bias is applied between the two alternate sets of fingers creating an electric field to sweep the photogenerated electrons and holes to the positive and negative electrodes, respectively. This process is limited by the transit time of the photogenerated carriers, therefore, a high speed response has been achieved.[221[231MSM detectors have been fabricated on both GaAs and InP. Because of its fabrication simplicity, it is easy to integrate the MSM detector with IC’s. For the top-illuminated structure, coupling of the optical signal into the device by angle lapping of the fiber, as shown in Fig. 36, has been reported on a superlattice-enhanced InGaAs/GaAs MSM structure.[241 For MSM detectors with InP substrate, backside coupling using a reflective v-groove has also been reported.[251 Using this technique, record MSM detector responsivity of over 0.9 A/W was reported.
592
Figure
Compound
33.
Semiconductors
Commercial
Hewlett Packard.
General
receiver packages for data link application. ODtronics.
and OCP.)
(Courtesy
of AT&T,
Packaging Microfens
n’- InP substrafe Undoptd GoInA,
-1nP
\Submounr
Figure 34. A flip-chip bonded PIN.I’sl (@X991 IEEE.)
,,Ti/Pt/Au
I
I:itqpx
I
I I
Figure 35. Schematic of a MSM detector structure.[24] (01990
IEEE.)
593
594
Compound
Semiconductors
Stngie MOdeFiber
Figure
36. Fiber to surface illuminated
3.0
MUL TICHANNEL INTERCONNECT
3.1
Introduction
high speed MSM
detectors.124] (rt:JJ990 JEEE.,
DEVICE PACKAGES FOR OPTICAL APPLICATIONS
As the digital signal processing speedofa computer increases,a high density of parallel interconnections at the board level with low latency and clock skew is required. In addition, as the rise time of the digital signal pulse decreases,high density electrical interconnections are constrained by crosstalk due to electromagnetic coupling between signal lines, an increase in line resistance due to the decrease in line dimensions, an increase in reflection due to impedance mismatch, and distortion of the signal due to dispersion from the skin effect. Optical interconnections using fibers and waveguides can overcome these problems and offer additional advantages of higher speed, freedom from electromagnetic interference (EMI), and lighter weight. For this type of application, multichannell11-V optoelectronic array packaging technology is being developed. In the following sections, the technology and issues related to different array packages are discussed. 3.2
LED
Array
Packaging
A monolithic linear LED array consisting of twelve 1.3 J.1mInGaAs/ loP surface-emitting LEDs has been reported.[26][27]Figure 37 shows a schematic of an LED array submount design reported by ltoh et al.[27] The LED array is a mesa structure with the p-contact of each LED bonded to a electrical fan-out pattern on the front side of the AIN submount to maximize
Packaging
595
the heat dissipation. The p-contacts of each LED are bonded to the fan-out pattern using the self-aligned solder reflow process. The LED array has an InP substrate as the common n-contact electrode which is wire bonded to the pattern near the edge of the submount. The driver circuitry for each LED is mounted on the top side of the AlN submount. An array of fibers is aligned to the LED array as shown in Fig. 38. The final LED transmitter array module is shown in Fig. 39. The uniformity in coupling efficiency of this LED array was f 0.2 dB. The average coupled power was -21 f 0.4 dBm at 15 mA with peak-to-peak (non-return-to-zero) NRZ modulation. A parallel data transmission rate of 150 h4b/s/channel with -39 dB interchannel crosstalk was demonstrated.
Swltchlng Translmlor
electmde
Figure 37. LED array design.[*‘l submount (01991 IEEE.)
Driver
Figure 38. Fiber array to LED array alignment.[27J (01991 IEEE.)
Submount
Metal Ferrule
596
Compound Semiconductors
DrlverlPreamplifler
CircultS
Flber Ferrule .
\/-----I
Fiber
LEDIPD
Array
Array
Figure 39. LED transmitter array package.rz7] (01991 IEEE.)
3.3
PIN Detector Array Packaging
The approach discussed in Sec. 3.2 had been applied to the InGaAs/ InP PIN receiver array. t2’l Figure 4012*1shows a PIN array package which utilizes a fiber array sandwiched inside a silicon v-groove array. The PIN array has center-to-center spacing matched to the center-to-center spacing of the fibers inside the silicon v-groove. The light detection surface of the PIN detectors in the array are butt-coupled directly to the individual fiber surfaces of the silicon v-groove. The p-contacts of the PIN array were connected to the package leads through vertical and horizontal fan-outs. Taking advantage of the transparency of the InP substrate to 1.3 urn photons, an alternative approach to packaging of PIN arrays uses a reflective silicon v-groove and passive alignment technique as reported by Chan, et al.129l The principle of the reflective silicon v-groove coupling technique is shown in Fig. 4 1. First, an array of v-grooves was formed by anisotropic etching on the (100) surface of a silicon wafer using a hot KOH solution. The walls of the v-groove array were oriented along the (111) surface of the crystal direction. Using a proper groove opening dimension, an array of 100/140 pm (core and cladding) diameter multimode fibers are fully embedded inside the v-grooves. At the end of the each v-groove, a 55” reflective mirror facet was formed. The optical signal from the fiber is reflected into the absorption region of the PIN detector. To enhance the reflectivity of these mirror surfaces, a high-reflectivity metal coating was sputter-deposited. During the same photolithographic step, axial and transverse alignment marks, located near the centers of the silicon v-groove mirrors, were delineated on the surfaces of the silicon v-groove substrate.
Packaging
Figure 40. A PIN array package which uses direct butt-coupling array.[z8] (01984 IEEE.)
59 7
of fiber array to detector
PIN Array
55” Mirror
(110) Fiat
Figure 41. Principle technique.
of reflective
silicon
v-groove
to PIN detector
array alignment
598
Compound
Semiconductors
After the fibers were loaded and bonded to the silicon v-groove substrate, the PIN detector array was passively aligned to the optimum position of the 55° reflective mirror surfaces, using the PIN array's top metal contacts and the transverse and axial alignment marks as references. After the alignment, the PIN array was bonded to the silicon v-groove substrate. An alumina fan-out was attached to the same silicon substrate. After wire-bonding the PIN array p-contacts to the fan-out patterns, the complete silicon substrate subassembly was attached to a package. Fig. 42(a) shows a PIN array package assembled on a standard 24 pin DIP platform. Fig. 42(b) shows the details of the interface of a six-channel fiber array aligned to the PIN array using this technique. In summary the advantages of reflective silicon v-groove technique are: (i) no angle lapping or polishing of silicon v-groove or fibers is required; (ii) since the PIN detector array is mounted directly onto a thin silicon wafer substrate, a very low profile packageheight can be achieved; and (iii) since a separate submount is not needed,the spacing between the PIN array and the receiver circuitry is reduced. The speedof the receiver array is therefore enhanced because of the reduction in parasitic lead inductance.
(a) Figure
42.
(a) A six-channel
array to fiber array interface.[29!
PIN array in a dual-in-!ine (.t:J1990 IEEE.)
package. (b) Details of the PIN
Packaging
-+
500 pm -T
L
270 pm
-i
Figure 42. (Cont ‘d)
599
600
Compound Semiconductors
3.4
Individually Addressable Laser Array Packages
Advancement in quantum well laser diode technology has resulted in threshold currents below 1 mA. High temperature operation was demonstrated using laser diodes with an InGaAs/GaAs strain layer quantum well structure. Laser arrays for high density optical interconnection have the advantages of high speed and high output power, as required by complex architectures which utilize either a star or tree-type topology. By achieving threshold currents below 1 mA, each laser in the array can be driven directly by the digital logic output signal. For single laser packages, a major cost of the packaging is aligning and pigtailing the fiber to the package. It is very expensive and impractical to package the individually addressable laser array in the same way that a single laser diode is packaged. Several approaches have been employed for individually addressable laser array transmitter packages. Direct Butt-Coupling Approach. This approach uses active alignment of an array of laser diodes to an array of fibers or waveguides. The fiber array or the waveguide array spacing is designed to match the spacing of the laser diode array’s emitting stripes. Figure 43 shows a laser array mounted junction side down on the metal pattern of a silicon submount.l30l An array of fibers in silicon v-grooves is aligned to the edge of the laser diode array bar and then bonded onto the package. In this alignment process, movement of the fiber array in X, Y, Z,8 and + are necessary to obtain good coupling results. Using this technique, Karstensen et al.1301 have achieved coupling efficiency of 10% in alignment of an array of eight AlGaAs single quantum well (SQW) laser diodes to an array of single mode waveguides. A coupling uniformity off 1.5 dB across the array was also achieved. Passive Alignment Using Indexing of Fiducial Marks. The active laser diode array alignment technique discussed in the previous section, provides better alignment accuracy, but it is a time consuming and labor intensive process. A passive alignment method using an indexing scheme, in which fiducial marks are formed on the laser array and the fiber array carrier by photolithography, was reported by Cohen, et a1.1311This technique has achieved the same coupling efficiency as active alignment for multimode fiber arrays. For single mode fiber arrays, an active-alignment coupling efficiency of 80% was achieved.
Packaging
601
Figure 43. Schematic of a laser array bonded junction side down on a fan-out pattern.[301 (81992 IEEE.)
The basic principle of this technique is shown in Fig. 44.r3’1 The laser array consisted of four laser diodes and the silicon v-groove fiber carrier contained four fibers that had a center-to-center spacing of 250 urn, which matched the laser array spacing. Cross fiducial marks and their relative position to the important features of both components were formed by photolithography during the respective component fabrication processes. A glass alignment plate with a metallized fiducial mark pattern that matched the fiducial marks on the laser array and the silicon v-groove fiber By placing the components carrier was also formed by photolithography. on the glass plate and aligning their fiducial marks to those on the glass plate, the correct alignment of the laser diode and fiber array was achieved. When the components were correctly positioned on the glass plate, they were fixed in place by application of vacuum to the components. Then both components are soldered to a metallic pedestal using a PbSn solder preform. The vacuum was released and both components were fixed to the metal substrate simultaneously. This step reduced the concern of a soldering hierarchy for each component and also minimized the displacement of the components from their relative optimum positions when the solder solidified. Figure 45 shows an SEM micrograph of a four channel laser array module fabricated by this technique.
602
Compound
Semiconductors
Figure diode array
44.
Principle
array aligning using
an
of a laser to a fiber indexing
scheme.!31] ('.{;)1992 IEEE.)
Figure
45. SEM photographs of
a four-channel ule fabricated nique.[31]
laser array modby indexing
(f:J1992 IEEE.)
tech-
Packaging 3.5
Hybrid Optoelectronic
603
Integration Using a Silicon Wafer Board
The concept of this approach is to package a laser array on a silicon wafer which functions as a mechanical, electronic, and optical platform for integrating the array’s driver and other signal processing integrated circuits on the same silicon substrate. This utilizes the maturity of III-V optoelectronic device technology and the silicon multichip module (MCM) technology, as reported by Lockwood and others.t321t33J As the complexity and density of optoelectronic and fiber optic packages increase, fabrication of all the functions using monolithic integration becomes costly. By utilizing MCM technology and integrating it with silicon v-groove for optoelectronic device alignment, package designers can integrate more electronic functions into an optoelectronic package. Using this approach, GTE Laboratory successfully fabricated a four-channel, long-wavelength laser transmitter array with an array of four single mode fibers passively aligned to the laser diode array.[341 Figure 46a shows the concept of the wafer board design, using a passive laser to single mode fiber array alignment technique. A six element, 1.3 pm, InGaAsP/InP double heterostructure laser array was flip-chip bonded to the metallization pattern on the silicon wafer board with the junction side down. The silicon wafer itself has four alignment v-grooves loaded with single mode fibers which were butt-coupled to the laser array. The laser array alignment pedestals (about 9 urn thick) were fabricated on the surface of a silicon wafer by isotropic reactive ion etching (RIE). The laser array has a notch to mate with the side alignment pedestal to monitor the laser array position in the Y direction. Two pedestals on the front of the laser array were used to monitor the array’s X direction. Below the laser array, there are two polyimide standoffs (also formed by RIE) about 5 urn in thickness located near the array’s two edges. They are used to fix the height of the laser array’s emitting surfaces so that the solder reflow bonding process will not disturb the optimum position of the laser array relative to the fiber core center. The position of the core center of the fiber is determined by the v-groove opening width and the total diameter of the fiber. The two laser array elements near the two edges are blocked by the front pedestals; only four elements are bonded in this module. The spacing of the laser array is 350 pm. The lasers had a threshold current of about 22 f 1 mA across the array. At 50 mA bias, the coupling efficiency varied between 3.5 to 6.0% across the laser array. Some diodes have a coupling efficiency as high as 7%. The average results are comparable to butt-
604
Compound
Semiconductors
coupling by active alignment. Figure 46b shows a photomicrograph flip-chip bonded four-channellaser array.
of the
(b) Figure
46.
(a) Schematic
of a laser array to single mode fiber array alignment
silicon wafer board.[341 (()1991IEEE.) array.[341 (()1991IEEE.)
(b) Photomicrograph
of the flip-chip
using a
bonded laser
Packaging 3.6
605
Array Issues
Introduction. In the previous sections, the basic array packaging techniques were discussed. As compared to single device packages, there are certain design and technical issues, which are not of concern for single element device packages, that require special attention. In the following, the technical issues related to array packaging are discussed. The technologies and design approaches that can address these concerns are presented. Uniformity and Yield. The major cause of nonuniformity in an array is due to nonuniformity of the optoelectronic device. For array production and manufacturing, nonuniformity reduces the yield of an array. With the maturity of MOCVD, VPE, and MBE growth technologies, very complicated laser, LED, and detector structures can be fabricated on a large III-V wafer with good uniformity. The advancement of in-situ monitoring techniques and improved understanding of the epitaxial growth thermodynamics provides high quality epi-wafers with uniformity better than 5%. The other technology area that can improve the uniformity of an array is the utilization of an automated wafer-level testing technique for IIIV optoelectronic devices in a way similar to the silicon integrated circuit testing process. By mapping the optoelectronic device wafers, the packaging engineer is provided with the information to screen out nonuniform arrays. Crosstalk. 7?zermaZCrosslafk. This is a special concern for LED and laser diode arrays. The thermal effect of a light-emitting element in an array is due to the heat dissipation from other elements in the array when they are turned on simultaneously. The typical drive current of a 1.3 pm surface-emitting LED is about 100 mA at 1.7 volt forward bias; the power dissipation of an array of 10 LEDs is about 1.7 watts. Thermal crosstalk changes the threshold and spectral characteristics of the laser array. For an LED array, thermal crosstalk reduces the output power and changes the spectral width and center wavelength of the individual elements in the array. Therefore, a good thermal heat sink scheme is needed for both LED and laser diode array package designs. Mounting the array in the junction-sidedown configuration and using AlN or diamond as a subcarrier are effective approaches to minimize thermal crosstalk. The other approach is to use a MESA structure for the LED’s array to improve the power efficiency, so that the drive current of the LED’s can be reduced. Using this approach, a LED array which requires 18 mA current drive for each element was reported.[351 A laser diode array, using a structure with a low threshold
606
Compound Semiconductors
current, reduces the effect of thermal crosstalk. Laser diodes with threshold current below 1 mA were reported.[361-[38JA laser array which can be directly driven by digital logic output would reduce the size and complexity of the laser array package, and therefore, would reduce the thermal crosstalk. A detailed experimental investigation of the thermal crosstalk of a 1.3 pm InGaAsP/InP distributed feedback laser array has been presented.[3gl These results confirm the importance of bonding to a laser array to high thermal conductivity material such as diamond for reducing the thermal crosstalk in the laser array. Electrical Crosstalk. This is a concern for detectors as well as LED and laser arrays. Electrical crosstalk is due to signal coupling from neighboring elements. This problem is being solved by both device design and package design. For the device design, the array structure should have trench and/or isolation grooves between adjacent elements. For the PIN detector array, devices fabricated on semi-insulating substrates have lower electrical crosstalk than devices fabricated on heavily doped n+ substrates, because the semi-insulating substrates have much lower parasitic capacitance between devices. A detail electrical crosstalk analysis is given in Ref. 40. For packaging, minimizing the length of the wire bonds and placing the high speed signal line between two ground pads will reduce the inductive coupling between adjacent lines. If the package contains hybrid electronic circuits, it is necessary to provide adequate spacing between signal lines for different frequencies. The length of the signal line should be minimized on the hybrid circuits. Careful circuit simulation and analysis are important for minimizing the electrical crosstalk. Opticaf Crosstalk. With proper spacing of device elements in the array, optical crosstalk is not a major problem for optoelectronic devices. For a detector array with element spacing about 500 pm, optical crosstalk below -40 dB can be easily achieved. For the LED and laser array packages, optical crosstalk usually occurs from reflection in the fiber and/ or waveguide in the package. Accurate alignment of the device and fiber arrays minimize optical crosstalk. In applications of optical backplanes or optical interconnects, a high density of embedded fibers or waveguides are used to interconnect printed-circuit boards (PCBs). In this case, careful calculation and modelling of the optical waveguide evanescence field coupling is important to assure that interchannel optical crosstalk does not affect the overall system performance.
Packaging
607
Hermeticity and Sealing. As compared to single device packaging technology, the sealing technique of the array packages has not been fully developed. For a single channel device, the fiber is metallized and sealed to the package body. Single channel fiber optic devices which do not use epoxy inside the package are now commercially available. For multielement devices, because the fiber pigtail is in a ribbon form, low outgassing epoxy or polyimide is generally used to hold the fiber array in a silicon v-groove subcarrier. As the epoxy technology improves, low outgassing and high temperature epoxies will be developed for different application standards. It will reduce the cost of making hermetically sealed array packages.
4.0
HIGH FREQUENCY GaAs DIGITAL AND MICROWAVE INTEGRATED CIRCUIT PACKAGES
4.1
High Frequency GaAs Digital Integrated Circuits Packages
GaAs digital circuits have important applications in high speed data and signal processing. Because of its superior radiation-hardness, GaAs is widely accepted for applications in military and space environments. The types of packages generally used for GaAs digital circuits are ceramic dualin-line packages (CERDIP), flat pack and leadless ceramic chip carriers (LCCC). CERDIP has a wider variation of parasitic capacitance between pins on the ends and the center of the package. It also has high interlead capacitance (> 1 pF) and lead series inductance (about 1 &I), therefore, it is not generally used for applications with 1 Gb/s or higher data rates. A small 16-pin flat pack typically has an interlead capacitance of about 0.5 pF and lead series inductance of about 0.3 nH. It is used in monolithic microwave integrated circuit and high data rate digital applications. A leadless ceramic chip carrier, which does not have any radial leads, allows higher packing density on the circuit board. An LCCC with a ceramic lid has low parasitic capacitance and inductance. A small 28-pad LCCC has an interlead shunt capacitance of about 0.5 pF and a lead series inductance of about 3 nH. It is used in many high speed emitter-coupled logic (ECL) and high packing density circuit board environments. More details on these GaAs digital IC packages and their interconnection technology were given by Gilbert.[411
608
Compound Semiconductors
4.2
Monolithic
Microwave Integrated Circuit Packaging
Monolithic microwave integrated circuits (MMICs) operating from 1 GHz to 30 GHz have been demonstrated.t421t431 Conventional ceramic packages will have limitations due to ring resonance caused by stray electromagnetic waves. A new metallized multilayer ceramic package has been developed to reduce this electromagnetic induction effect.rUl This package is shown in Fig. 47. The wall of the package is made of metallized multilayer ceramic. The inside and outside walls of the package are metallized and connected to the ground of the metal base. This type of package has been used for high-frequency applications up to 30 GHz. Metallized Inner Wall
Metallized Outer Wall
, Path L.ayei
Metal Base
Figure 47. A multi-layer ceramic package with metalized wa11.[44] (01990
IEEE.)
Conventional GaAs MMIC’s generally use wire bonding for packaging and interconnection. Wire bonds, however, introduce parasitic inductance which degrades the high frequency performance of the MMIC . A new bonding technique, using an impedance-matched film carrier technique, has been developed for the very high frequency GaAs MMIC packages. A diagram which demonstrates the film carrier MMIC packaging technique is shown in Fig. 48. The carrier consists of a polyimide film onto which a conductive pattern has been plated. A coplanar waveguide pattern is formed by having the middle signal leads located between two ground leads, as shown in Fig. 49.1451Gold bumps are formed at the distal end ofthe inner and outer lead. After the coplanar film carrier with the MMIC chip is
Packaging
609
mounted into the package, the outer leads with bumps and the terminal pads of the package are connected. The high frequency characteristic of this type of package is very close to the bare-chip MMIC. The coplanar film carrier is an important technology for fbture MMIC packages. Gold Bump
Figure 48. A film carrier MMIC
package.[44] (01990
IEEE.)
Figure 49. A coplanar G-S-G leads of a film carrier MMIC
package.[451 (01991
IEEE.)
610
Compound Semiconductors
5.0
CONCLUSIONS
In the previous sections, the fundamental principles and some recent development in the areas of III-V optoelectronic device and high frequency GaAs integrated circuit packaging have been reviewed. It is hoped that this information will provide a device researcher with ideas on how to build a prototype GaAs electronic and/or III-V optoelectronic device package. A package designer who has no prior experience in III-V devices will gain Common to all some insight into the technical aspects of this area. packaging designs, the three major concerns for all electronic and optoelectronic device packaging are form, fit and function. While III-V device packaging is still at its early stage of development, many standards are forthcoming. A person who designs a III-V electronic or optoelectronic package should first anticipate the probable packaging standards and the requirements for commercial or military applications. Secondly, what environment will the package experience? On what circuit boards will it be mounted? Is the height and footprint of the package appropriate for the environment? Finally, what is the function of the package? The important functions of an electronic or optoelectronic package are to provide (il a mechanical support for the electronic circuits, the optoelectronic device, the fibers, the microlenses, and other components; (ii) environmental protection for the devices; (iii) proper pin count and impedance-matching for electrical interconnection; (iv) a stable enclosure to maintain reliable alignment of all optical components; and (vj an efficient path for heat transfer from the devices inside to the ambient outside the package. III-V electronic and optoelectronic packages should be designed with these important considerations.
REFERENCES 1. Hayes, J. R., Tech. Digest, OFC 92, p. 233 2. Marlow Industries, Model SP5007 Thermoelectric Cooler 3. StakeIon, T., Optical Device Packaging, Short Course Notes, OFC (Feb. 1992) 4. Presby, M. H. and Edwards, C., Elect. Lett., 28(6):582-584 (Mar 1992) 5. Perryman, A. J., Regan, J. D. and Elliot, R. T., SPIE Proceedings, Laser Diode Technology andApplications, pp. 330-337 (Jan 1898)
Packaging
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6. Renner, D., Cheng, W. H., Pooladdej, J., Appelbaum, A., Hess, K. L. and Zehr, S. W., SPIE Proceedings, Laser Diode Technology andApplications, pp. 300-306 (Jan 1989) 7. Baker, E. and Kessler, T. J., IEEE Transactions Packaging,
PHP-9(4):243-246
on Parts, Hybrids
and
(1973)
8. Figueroa, L., Hong, C. S., Miller, G. E., Porter, C. R., and Smith, D. K., SPIE Proceedings, Laser Diode Technology and Application III, pp. 153-
161 (Jan 1991) 9. Saul, R. H., IEEE Transaction 1983)
on Electron
10. Welsh, F. S., AT7T Technical Journal,
Devices,
30:285-295
(Apr
66:65-72 (Jan/Feb 1987)
11. Ackenhusen, J. G., Applied Optics, 18(21):3694-3699
(Nov 1, 1979)
12. Scholl, F. W., Anderson, S. J. and Coden, M. H., High Power Light Emitting Diode for Fiber Optic Communication, Technology Corporation (1986)
Publication
of Codenoll
13. Reith. L. A., Mann, J. W., Andreadakis, N., Lalk, G. R. and Zah, C. E., IEEE 40th ECTC, pp. 193-199 (May 1990)
14. Boudreau, R., Morrison, R., Sargent, R., Holmstrom, R., Powazinik, W., Meland, E., Wilmot, E., and LaCourse, J., IEEE 41st ECTC, pp. 30-33 (May 1991) 15. Dixon, R. W. and Dutta, N. K., AT&T Technical Journal, pp. 73-87 (Jan/ Feb 1987) 16. Forrest, S. R., et al., IEEE Elect. Dev. Letters, 2(11):283-285 17. Miller, L. F., IBMJ.
Res. Develop.,
(Nov 1981)
pp. 239-250 (1969)
18. Wada, O., Makiuchi, M., Hamaguchi, H., Kumai, T., and Mikawa, T., IEEEJ. oflightwave Tech., 9(9):1200-1207 (Sept. 1991) 19. Moseley, A. J., Kearley, M. Q., Morris, R. C., Urquhart, J., Goodwin, M. J., and Harris, G., Elect. Lett., 27:1566-1567 (Aug 15, 1991) 20. Patra, S. K. and Lee, Y. C., ASME J. of Elect. Packaging
(1991)
21. Patra, S. K. and Lee, Y. C., IEEE 41 st ECTC, pp. 783-788 (May 1991)
22 Rogers, D. L.,J. oflightwave
Tech., 9(12):1635-1638 (Dee 1991)
23. Burroughs, J. H. and Hargis, M., IEEEPhotonic (Jun 1991)
Tech. Lett., 3(6):532-534
24. Choudhury, A. N. M., et al., IEEE LEOS Proceedings, 1990)
pp. 33-334 (Nov
25. Kim, J. H., Griem, T. H., Friedman, R. A., Chan. E. Y., and Ray, S., Photonics Technology Letters, 4(11): 1241-1244 (Nov 1992) 26. Ota, Y., et al., IEEEJ.
of Lightwave
Tech., 5(S): 1118-l 122 (Aug 1987)
27. Itoh, M., et al., IEEE list ECTC, pp. 475-478 (May 1991)
612 Compound Semiconductors 28. Brown, M.G., et al., IEDM Technical Digest, pp. 727-728
(1984)
29. Chan, E. Y., Tanielian, M., Popoff, A., Self, D., Fu, R, Burnett, A., and Hong, C. S., IEEE LEOS Proceedings, pp. 335-336 (NOV 1990) 30. Karstensen, H., Schneider, H. W., and Wieland, J., IEEE 42nd ECTC, pp. 83-87 (May 1992) 3 1. Cohen, M. S., et al., IEEE 42nd ECTC, pp. 98-107 (May 1992) 32. Lockwood, H. F., Hybrid Wafer Scale Gptoelectronic Integration, OPTCON/ SPJE, (Nov. 1990) 33. Geschwind, G. and Clay, R, Pro. ofASMInternationa1 Processing Congress, pp. 65-77 (Aug 1990) 34. Armiento, C. A., et al., Elect. Lett., 27(12):1109-l 35 Kaede, K., et al., IEEEJ. ofLightwave
‘s3rdMaterial
and
111 (June 1991)
Tech., 8(6):883-888
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36. Osinski, J. S., et al., IEEE Photonic Technology Letters, 4(12): 13 13-13 15 (Dec. 1992) 37. Thijs, P. J. A., et al., Microelectronics
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1992) 38. Derry, P. L., et al., Optoelectronics-Device
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30 @ec 1988) 39. Sato, K. and Makoto, M., IEEE Photonics Tech. Letters, 3(6):501-503 (June 199 1) 40. Kaplan, D. R. and Forrest, S. R., IEEEJ. ofLightwave 1469 (Ckt 1986) 41. Gilbert, B. K., Book Chapter in VLSI Electronics, Press (1985) 42. Sheng, N. H., et al., IEEEMicrowave 10 (Aug 1991)
Tech., 4(10):1460-
11:289-33 1, Academic
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43. Kato, H., et al., IEEE Transactions on Microwave 38(7):896-903 (July 1990)
Theory and Technique,
44. Ohsaki, T., IEEE 40th ECTC, pp.l-8 (May 1990) 45. Hideki, T., et al., IEEE 41st ECTC, pp. 479-482 (May 1991)
12 Chemical, Structural and Electronic Characterization of Compound Semiconductor Surfaces and Interfaces by X-ray Photoelectron Spectroscopy and Diffraction Techniques ScottA. Chambers
1.0
INTRODUCTION
1.1
Overview of the Topic
Surfaces of compound semiconductors exhibit a variety of chemical, structural, and electronic properties when freshly prepared and atomically clean, when exposed to air, and when put in intimate contact with other materials during device fabrication. A detailed characterization and understanding of these properties is requisite to our ability to fully utilize these materials in device and circuit applications. Possessing this kind of
613
614
Compound Semiconductors
knowledge enables the device technologist to design and fabricate device structures that are more fully optimized than would be possible in the absence of such insight. For instance, oxide formation on compound semiconductor surfaces exposed to air can create problems during subsequent metallization. Knowing what specific oxides are present on the surface and how those oxides react with atoms in the metallizing layer is of obvious benefit in characterizing the interface and understanding its behavior. Furthermore, such knowledge can be invaluable when devising engineering “matrices” oriented at process optimization. Both the dimensionality of the matrix and the detailed experiments that compose its elements can be more intelligently configured when insight into the materials properties of the relevant surfaces and interfaces is at hand. X-ray photoelectron spectroscopy (XPS) and the more recently developed derivative, x-ray photoelectron diffraction (XPD), have proven to be very useful in generating such knowledge. Both techniques are inherently surface sensitive as a result of the short escape length of electrons emitted from solid specimens (a few to a few tens of angstroms, depending on the electron kinetic energy and the material composition of the surface). Furthermore, both are readily utilized as either routine surface analytical tools for examining surfaces generated in materials growth and device processing, or as fundamental research tools oriented toward uncovering detailed understanding of systems prepared in carefully controlled environments. We include examples of both kinds of use in this chapter.
2.0
X-RAY PHOTOELECTRON DIFFRACTION
SPECTROSCOPY
2.1
The Essential Experiments and Interpretations
AND
XPS and XPD both involve absorption of soft x-rays of some energy hv by atoms in the near-surface region of a specimen under study. Photoelectrons with kinetic energies dictated by the Einstein relation (hv = Et, + E,, where E, and & are the photoelectron binding energy and kinetic energy, respectively) are ejected by the atom, propagate to the surface, and pass through the surface to the vacuum. ~1 Energy analysis is typically done with a hemispherical sector electrostatic analyzer to yield an energy distribution curve (EDC), consisting of a plot of the number of electrons emitted, N(E,J as a function of kinetic energy, as shown in Fig. 1. Here, we show Ga
Charactefization
of Sujhces
and Interfaces
615
3d EDCs measured in angle-resolved fashion for GaAs(OOl)-(2 x 4). The spectra were measured using an angle-resolving analyzer every two degrees over a full 360” azimuthal rotation at a polar angle of 35” off the surface plane. Variations in peak intensity with angle are clearly visible and are the result of elastic scattering by nearby ion cores and subsequent interference at the detector of outgoing photoelectrons.[2J-[41This phenomenon and its utility for determining surface and thin-f&n structures are discussed in more detail below.
1GqAs(OOl)-(2x4)
1
8 = 350
Ga 3d
= 360°
Iq(Ek)
0 = 00 Ek
[iii]
b ila
i
?E =
azimuthal angle, Q (degrees)
Figure
1. Crystal structure (top leff;), photoelectron energy distributions (top right), and
photoelectron angular distributions (bottom) for Ga 3d emission from GaAs(OO1)-(2x4).
616
Compound Semiconductors
We have chosen in Fig. 1 to plot angle-resolved spectra in order to demonstrate the intensity modulations that constitute photoelectron diffraction in single crystals. However, in most XPS applications, the cone of acceptance into the spectrometer lens is made as large as possible in order to obtain maximum sensitivity. For core-level photoemission obtained in either mode, E,.,and therefore E, are sensitive functions of three properties of the emitting atom: (i) the valence charge distribution surrounding the atom, which is determined by the electronegativities of the other atoms to which the emitter is bound; (ii) the extent of charge relaxation toward the core hole, which is linked to the polarizability of the media surrounding the emitting atom; and, (iii) charge accumulation in forbidden gap states that form at the surface or interface of the semiconductor, i.e., band bending.i51 Careful analysis of core- and valence-level spectra enable considerable information about these three properties to be gained. The outgoing photoelectron undergoes both elastic and inelastic scattering in the process of propagating from the emitter to the surface. Inelastic scattering leads to spectral peak attenuation that is largely independent of emission direction, even in single crystal specimens.[3) This result is due to the fact that the primary loss mechanism is plasmon excitation, and plasmons are largely delocalized in solids. Elastic scattering occurs as the photoelectron wave interacts with ion cores in the vicinity of the emitter. These scattering events lead to measurable interference at the detector point ifthe specimen is a single crystal. The interference can be observed in one of three modes: (i) scanned-angle intensity measurements at fixed photon (and, therefore, photoelectron) energy, (ii) scanned-energy intensity measurements at fixed detection angle, and, (iii) combined scannedangle/scanned-energy intensity measurements.t6) All three modes require that the acceptance cone of the analyzer be limited by either electrostatic or mechanical means, so that a single, well-defined emission direction relative to the crystal axes of the specimen is detected. Modes (ii) and (iii) require a synchrotron radiation source so the photon energy can be swept over the desired range. We limit our discussion in the present work to mode (i). The reader is referred elsewhere for detailed discussions of modes (ii) and (jii).171-[101
With regard to angle-integrated photoemission, XPS and the closelyrelated technique of synchrotron radiation photoemission spectroscopy (SRPS) have been extensively used to study surface and interface phenomena.[lll Each has particular advantages and disadvantages. One can utilize a very high degree of monochromatization in SRPS due to the higher photon
Characterization
of Surfaces and Interfaces
617
fluxes afforded by synchrotron sources, compared to most conventional lab x-ray sources. Therefore, the total energy resolution that can be realized is typically higher in SRPS than in XPS, allowing the experimenter to attain superior peak separation between closely-spaced photoelectron peaks. Typically, a total resolution (photons plus analyzer) of -0.2 eV can be attained with synchrotron radiation, whereas -0.5 eV can be achieved with most monochromatic AlKa radiation sources. An exception to this statement is one particular spectrometer system which utilizes a rotating anode source and several monochromator ~rystals.1~~1This system produces an energy resolution comparable to that available from synchrotron sources. One is limited in SRPS to photon energies of, at most, several hundred eV in order to obtain energy resolution of -0.2 eV, at least with current-generation synchrotron radiation facilities. Photon energies in this range result in photoelectron kinetic energies of -50-200 eV, for which the attenuation lengths are of the order of a few to several angstroms.l13l Therefore, it is, in general, not possible to examine interface formation for overlayer thicknesses that are in excess of several angstroms. In contrast, XPS, which typically utilizes MgKa or AlKa radiation at 1256 eV and 1487 eV, respectively, produces shallow core-level photoelectrons of kinetic energies up to approximately the energy of the excitation source. The attenuation lengths of such electrons are typically 20 to 30 A,[131allowing buried interfaces with overlayer thicknesses of up to -50 A to be studied by utilizing a normal emission geometry. However, the spectral resolution attainable with XPS is typically less than that available with synchrotron radiation, as discussed above. Finally, the use of synchrotron radiation introduces certain inconveniences and time pressures that do not exist when working in one’s home laboratory with a conventional x-ray source. We now cover some rudimentary theoretical considerations of photoelectron intensities as measured in XPS and XPD experiment. This treatment is designed to provide a basic conceptual understanding of the processes involved in XPS and XPD; the reader is referred to more detailed reviews for additional information.l*l-I51 A particularly straightforward way of viewing XPS and XPD involves the three-step model ofphotoemission, which was alluded to above.l’J In this model, the overall process is thought of in terms of (i) photoelectron emission by an isolated atom in a solid, (ii) propagation of the resulting photoelectron wave through the solid toward the surface, and (iii) passage across the potential step at the solid-vacuum interface.
618
Compound Semiconductors
Considering the first step in this process, the probability of core-level photoemission from an isolated atom is governed by the photoelectric cross section. Angle-integrated intensities depend on the total photoelectric cross section, CT,whereas angle-resolved intensities depend on the differential photoelectric expression:
cross section, da/a.
The two are related simply by the
Eq. (1) In most general terms, the differential photoelectron in the semiclassical description of electromagnetic with an N-electron system by:l141
cross section is given radiation interacting
Eq. (2) Here, Y’(N) and Yf(N) are the total electronic wave functions for the initial and final states of the emitting atom, respectively, A(rJ the vector potential associated with the incident electromagnetic wave, pi is the momentum operator for the ith electron in the atom, and C is a constant of proportionality that includes incident x-ray flux, instrument response function, and fundamental constants. The interaction Hamiltonian in Eq. 2 reduces to a simple dipole operator due to the fact that the wavelength of the x-ray is typically much larger than the dimensions of the absorbing atom, although this approximation begins to break down as one goes above x-ray energies of - 1.5 keV (the AlKa x-ray energy). Therefore, a dipole selection rule is operative. For instance, photoemission from an s orbital leads to an outgoingp wave, whereas photoemission from ap orbital leads to interfering s and d waves. In case of core-level photoemission, the total wave functions for the initial and final states of the N-electron system can be written as Y’(N) = &$(l),\y’(N-1)) and ‘I”(N) = A^($f(l),‘yf(N-l)) which involve antisymmeterization of one-electron wave functions representing a single active (i.e., photoemitting) and N-l passive orbitals of the N-electron system. The wave function for the outgoing photoelectron, +f( 1), is well represented by an outgoing wave of well-defined angular
Characterization
of Sutiaces
and Interfaces
619
momentum which is, in turn, determined by the initial state of the active orbital through the dipole selection rule. Inserting Eqs. (3a) and (3b) into Eq. 2 yields.[151
WW Eq. (4)
dR
Here we have separated the integral over spatial coordinates into two factors composed of a dipole matrix element that involves the active orbitals and an overlap integral of the passive orbitals. In the limit of no relaxation toward the core hole, the initial and final state passive orbitals are identical, and the first factor in the absolute square integrates to unity (the so-calledfrozen-orbital approximation) In the event that extra-atomic relaxation occurs, this overlap integral is less than unity, and additional terms involving different configurations of the passive electrons must be added inside the absolute square to account for the total transition probability. Such terms give rise to additional features in the spectrum at lower kinetic energy relative to the primary photoelectron peak known as shakeup peaksI This additional structure is seen, for instance, in spectra of organic polymers, and involves final-state configurations in which II electrons associated with aromatic rings are excited to K* orbitals upon photoemission from a core orbital. Once the photoelectron is excited at a particular ion core, propagation to the surface (the second step) is accompanied by elastic scattering that modulates the intensity from single-crystal specimens as the crystal is rotated relative to an angle-resolving analyzer (see Fig. 1).[21-[41[61The intensity for a given emission direction relative to the crystal axes of the specimen is the superposition ofthe unscattered photoelectron wave portion and all scattered wave portions, evaluated at the detector point. Quantitatively, this superposition is expressed a.s~:t~J-[~l
The first term, t+tJr,k), represents the unscattered wave portion along emission direction k toward the detector a distance r away. At r + 00, the unscattered wave function is well represented by its asymptotic form:
620
Compound Semiconductors
Physically, this term represents an outgoing spherical wave centered on the emitting atom that is modulated by the differential photoelectric cross section. The single sum in Eq. 5 denotes all single elastic scattering events and the double sum denotes double scattering events, the sums being over ion cores in the vicinity of the emitter, in each case. Triple, quadruple, and other multiple sums representing higher-order scattering are not included, but are straightforward to write down. The scattered wave functions, Ulj(rjA$) and Yji(rj,riAej,eg, are sensitive to the distance and spatial orientation of secondary ion cores, relative to the emitter. They are given in the asymptotic limit as exp(i[klr - r,l + r(ej,]) Eq. (7)
Wj(r$r ,ej) - w,Jr.k)lf(e$
Ir - rj
These terms represent outgoing spherical waves centered on thejth and Ith ion cores, respectively, each modulated by the amplitude of a complex atomic scattering factor (]f(0)]) associated with the atomic species at the scattering site. The term {r(e)} represents the phase shifts associated with the various scattering events, and {e} are the scattering angles. Each scattered wave function is modulated by the amplitude of the incident wave at that particular scattering site. In the case of Eq. 7, the incident wave is the primary (unscattered) photoelectron wave portion evaluated at the jth atom. In the case of Eq. 8, the incident wave is the scattered wave amplitude originating at the jth atom, as evaluated at the Ith site in the crystal. The scattering amplitudes, {]f(e)]}, typically fall off rapidly with scattering angle, 8, for kinetic energies of several hundred eV or greater.121-[41In addition, the scattering phase shifts, {r(0)}, tend to be small for small scattering angles in this energy range. Plots of these two quantities are shown in Fig. 2 for plane-wave electrons incident on a single
Characterization
of Surfaces and Interfaces
621
Ge atom at a variety of energies. The behavior of the scattering amplitude and phase at small scattering angles leads to strong constructive interference along chains of atoms, independent of both electron kinetic energy and emitter-to-scatterer distance. Thus, strong intensity maxima, which have come to be known as zeroth-order forward-scattering or forward-focussing peaks characterize intermediate- to high-energy XPD along low-index directions in solids.~2~-[4~[61~161 Th e positions of these peaks are a very sensitive function of bond orientation in a solid specimen, and can be used to detect tetragonal distortion in strained overlayers.131 They are, however, rather insensitive to electron kinetic energy and bond distance. In addition to these forward-scattering peaks, higher-order interference phenomena occur away from low-index directions. This diffraction modulation occurs as a result of the overlap of scattered wave portions that originate at several ion cores. In contrast to zeroth-order forward scattering peaks, these angular intensity variations are sensitive to both the emitter-to-scatter distance and the electron kinetic energy.
-
1440 eV
----1000eV
,.
-
500 eV
-
130 eV
-1440eV
6.
----1000eV -
500 eV
120
Angle
Figure 2. electrons
Atomic
scattering
at various
kinetic
scattering angle.
amplitudes energies
(From Ref 3.)
180
(degrees)
(top) and phase shifts incident
on a single
(bottom) for plane wave Ge atom as a function of
622
Compound Semiconductors
The various structures seen in a typical XPD scan are shown at the bottom of Fig. 1. Here, we plot peak areas of Ga 3d photoelectron spectra after linear background subtraction for the set of EDCs shown in the upper right of Fig. 1. The intensities are actually plotted as an intensity variation The relative to the maximum value, normalized to the maximum value. scan encompasses the full 360” azimuthal range at a polar angle of 35” off the surface plane. Included in the scan are the two close-packed, low-index directions involving pairs of atoms, one Ga and one As, separated by 2.45 A along (111) at 90” and 270°, respectively. The Ga atom is one layer below the As atom in each case, and each pair of atoms is separated by 9.79 A. Therefore, strong zeroth-order forward scattering of Ga 3d photoelectrons by As ion cores is expected and observed at these angular coordinates. In addition, considerably more structure is seen at other angles, corresponding to higher-order interference phenomena. These two kinds of intensity modulation are mutually complementary, and are very useful for extracting quantitative structural information about the near-surface region. Accurate measurement of the photoelectron intensity variation with k yields valuable information about the structural environment of the emitting atom. This information can be extracted from the experimental data in one of two ways. The first and most reliable method is a trial-and-error comparison with model quantum-mechanical scattering calculations in which the structural parameters are varied and optimal agreement between theory and experiment is sought. This method, while somewhat tedious, yields quantitatively accurate structural information.t21-~41 The second and much less established method is direct Fourier inversion of the experimental diffraction patterns to yield real-space images of atoms surrounding the emitter.12]-[4] This technique is hampered by anisotropies in both the amplitudes and phases associated with electron-atom scattering, by the occurrence of multiple scattering, and by the existence of multiple emission sites in complex specimens. These complicating effects add distortions and artifacts to the resulting real space images. However, considerable effort is currently being expended to overcome these difficulties. While XPD experiments have been successfully carried out and interpreted for the full range of photoelectron kinetic energies accessible with current soft x-ray sources, there are certain advantages associated with utilizing kinetic energies in excess of several hundred eV. The primary advantage is that multiple scattering can generally be neglected for all emission directions, except those coinciding with low-index directions.[21-t4J This simplification occurs because the scattering amplitudes are small for
Characterization
of Surfaces and Interfaces
623
large scattering angles. Therefore, multiple scattering events which, to first order, go as the product of atomic scattering factors for the individual scattering events, are of negligible probability for large-angle scattering. In contrast, scattering along a chain of atoms involves only small-angle scattering events. The larger scattering amplitudes that occur along lowindex directions at high kinetic energies result in larger probabilities of multiple scattering along these directions. The net effect of multiple scattering along these chains is a reduction in forward-scattering intensity, relative to what is predicted if multiple scattering is neglected. The extent to which multiple scattering is important increases with decreasing kinetic energy and it is, in general, not possible to identify a universal cutoff energy above which multiple scattering can be neglected for all systems. However, it appears that for most systems a conservative estimate is -1000 eV. In the single scattering approximation, the multiple sums in Eq. 5 can be neglected, yielding a relatively simple expression that can be readily evaluated for a range of geometries with modest computing power. Neglect of multiple scattering along low-index directions results only in an overestimation of forward-scattering peak intensities; the associated peak positions are, in general, not affected by this approximation.l17l
3.0
CHEMISTRY FORMATION
OF SURFACE
AND INTERFACE
3.1
Oxide Formation and Removal from GaAs(001)
XPS has proven to be an invaluable tool for studying the oxidation of GaAs and other III-V semiconductors, as well as for determining the effectiveness of various oxide-removal procedures.1181-1221 The presence and identity of surface oxides of Ga and As are readily determined by taking advantage of the chemical shifts induced in Ga and As core-level spectra by the formation of such oxides. The larger electronegativity of 0 compared to Ga or As causes the Ga and As core-level binding energies to increase upon oxide bond formation, relative to values exhibited by pure GaAs. This increase occurs by virtue of the increased effective nuclear charge experienced by core-level electrons as a result of valence-charge withdrawal toward 0 atoms. Chemically-shifted peaks are observed to higher binding energy by an amount ranging from a few tenths to several eV, depending on the oxidation state of the Ga or As atoms. These shifted peaks are easily
624 Compound Semiconductors measured with either nonmonochromatic MgKu x-rays (1254 eV) or monochromatic AlKu x-rays (1487 ev). We show in Fig. 3 Ga and As 3d core-level spectra excited with monochromatic AlKa radiation for atomically clean and ordered GaAs( 1lo), cleaved in ultrahigh vacuum (top two spectra), along with spectra from GaAs(OO1) with a surface oxide layer (bottom four spectra), taken from Ref. 22. The oxide layer was prepared by exposure to ozone at a substrate temperature of -60°C. The spectra for the oxidized surface were obtained at two polar angles relative to the surface plane: 0 = 66’ and 8 = 26”. The probing depth is approximately given by 3ksin0, where h is the attenuation length and 9 is the polar angle of detection. Therefore, the surface sensitivity of the spectra increases as the polar angle is reduced. Starting with the clean-surface spectra, the raw EDCs are readily fit to doublets that result from atomic spin-orbit splitting. The line-shape parameters extracted from these spectra are then used to fit the more complex spectra that result from oxide formation on the surface. Several groups have characterized oxide formation on GaAs, and we present in Table 1 the chemical shifts generally believed to accompany the formation of the oxides listed in the table. While the overall energy resolution is not sufficient to produce an incontrovertible peak fit, it appears on the basis of these assignments that exposure of the surface to ozone results in the formation of G+O, GaO, G+O,, GaAsO,, As,O,, and GaAsO,. Comparison of the spectra obtained at different polar angles allows us to qualitatively determine the distribution of the different oxides in the near-surface region. Looking first at the As 3d spectra, it is clear that the relative amounts of the three oxides of As change as surface-sensitivity is enhanced. The peaks ascribed to GaAsO, (the highest binding energy doublet) account for a larger fraction of the total oxide peak intensity at 8 = 26” than at 0 = 66’, indicating enhancement of this species at the surface. This result is consistent with the expectation that the more fully oxidized species should form closer to the surface. In addition, the peaks assigned to GaO cannot be extracted from the fit at 8 = 66”, but are clearly present at 8 = 26’, indicating that this species is more surface segregated than the other oxides of Ga. In addition to this qualitative approach, it is possible to quantitatively model the intensity variations of the various oxides with polar angle in order to extract the distribution of each species in the nearsurface region. Very high energy resolution is required so that the spectrum at each angle can be unambiguously fit, and the angular variation of the intensity of each component accurately determined.
of Surfaces and Interfaces
625
Ar 3d
Ga Id
i/:,
Energy WI
22
19
46
44
42
Figure 3. Core-level photoemission measured from cleaved, clean GaAs(ll0) (lop two specfra), and from GaAs(001) with a thin native oxide collected at two polar angles (bottom four spectra). (From ReJ 22.)
Table 1. Ga and As 3d Binding Energies for Common Oxides on GaAs
Surfaces Oxide Ga 3d chemical shift (eV) Ga20 0.4 GaO 0.9 Ga20, 1.5 *s,0, GaAsO, GaAsO, 2.0
As 3d chemical shift* (ev) 3.2 2.5 4.5
*Relative to GaAs, based on numbers reported in Refs. 18-22.
626 Compound Semiconductors The removal of oxides from the surface of GaAs by wet-chemical means is also readily verified by XPS. We show in Fig. 4 Ga and As 3d spectra for: (i) GaAs with a thin native oxide formed by exposure of the surface to laboratory air, (ii) the same surface after etching in a mixture of H,PO, and H202 and, (iii) the surface etched in H,PO, and H202 after a dip in an HCl solution. These spectra, taken from Ref. 18, were obtained with nonmonochromatic MgKa radiation. Therefore, the energy resolution is not as good as that obtained in the spectra shown in Fig. 3. However, it is clear that, while etching in H3P0, and H202 produces little change in the amount of oxide present, subsequent exposure to an HCl solution significantly reduces the total amount of oxide present. A small 0 1s peak (not shown) remains after exposure to HCl.
As 3d
(b)
BNDWG ENERGY (eV)
Figure 4. Core-level spectra for GaAs(OO1) with a thin native oxide (I), and after various wet-chemical treatments, taken from Ref. 18. See text for details of the chemical etches used.
Characterization 3.2
of Surfaces and Interfaces
627
Metal/III-V Compound Semiconductor Interface Formation
Both XPS and SRPS have been used extensively to investigate the chemistry of metal/semiconductor interface formation. In what follows, we limit our discussion to studies carried out with XPS. The reader is referred to another excellent review that discusses the application of SRPS to the formation of such interfaces.llrl Metal/semiconductor interfaces tend to exhibit some level of chemical reactivity or physical dissolution for the vast majority of couples that have been investigated. As a result, either stoichiometrically well-defined phases or solid solutions of semiconductor atoms in a metal matrix form at the interface. Chemical thermodynamics provides the driving force in some cases. Here, isolated metal atoms incident on the surface, break existing bonds, and form new compounds with the liberated semiconductor atoms so that the total free energy of the system is minimized. In other cases, energy transfer associated with condensation of metal atoms on the semiconductor surface results in substrate disruption, and freed semiconductor atoms dissolve in the metal overlayer to form a solid solution.l”l In either case, semiconductor atoms in the new bonding environment are expected to exhibit core-level binding energies different from those measured in the substrate. The magnitude of the binding energy difference depends primarily on differences in electronegativity between the semiconductor atoms and the metal atoms. In general, the chemical shifts are not as large as those observed in oxide formation. Therefore, high energy resolution is essential in order to accurately determine the binding energy shifts resulting from interface reaction or dissolution. As a first example of the kinds of information that can be gained from these studies, we discuss the growth and characterization by XPS of the epitaxial transition metal aluminide NiAl on GaAs(OO1). A very fruitful approach to the study of interface formation has been to evaporate the metal of interest in small increments, and then to use high-energy-resolution XPS (or SRPS) to monitor changes in core-level spectra that reveal atomic rearrangements at the interface. We show in Fig. 5 Ga 3d core-level spectra obtained at normal emission as a function of NiAl coverage in monolayers, taken from Ref. 23. We define a monolayer of NiAl as a single layer of either Ni or Al atoms with a density equal to twice the surface atom density of GaAs(OO1). NiAl forms a very stable CsCl phase with a lattice constant close to half that of GaAs. Inspection of the spectra reveals that reaction of the substrate with atoms in the metal deposit occurs starting at coverages of
628
Compound Semiconductors
-1.5 ML. A second spin-orbit pair at lower binding energy becomes necessary to obtain a good curve fit to the raw Ga 3d EDC. It is not presently possible to uniquely determine the identity of the interface reaction products from the core-level spectra, primarily because of the lack of complete reference spectra for the various compounds that could form. However, it is possible to determine something about the quantity and distribution of the reacted substrate species, by examining the dependence of the various peak intensities on overlayer coverage.
NiAllp-GaAs(001) Ga 3d - normal
emission
t 21
19
17
21
19
I
!
17
BINDING ENERGY (eV)
Figure 5. Core-level spectra from the Niil/pGaAs(OOl) overlayer thickness in monolayers, taken from Ref. 23.
interface as a function of Nii
Charactetization of Surfaces and Interfaces
629
We show, in the top panel of Fig. 6, the total Ga and As 3d reduced intensities, measured at lower energy resolution than the spectra shown in Fig. 5, plotted against overlayer coverage.lzl The reduced intensity is defined as ln[I(d)/I(O)], where I(0) and I(d) are the core-level intensities with 0 and d angstroms of overlayer material, respectively. Linear behavior is expected for laminar growth of the overlayer and no outdifision of substrate atoms. The positive deviation from linearity in the As 3d reduced intensity indicates that As atoms liberated from the substrate di&se into and perhaps to the surface of the overlayer. In contrast, liberated Ga atoms remain trapped at the interface, as evidenced by the fact that the Ga 3d reduced intensity is linear with coverage. This fact can be used to determine the number of layers of substrate consumed in reaction at the interface, by means of a simple model. The ratio of reacted to substrate Ga 3d intensity as a function of coverage can be modeled using a simple continuum model of the overlayer in which diffraction effects are ignored. Neglect of diffraction effects is warranted because these spectra were measured in an angle-integrated mode, and the diffraction modulation present in the intensity map is averaged out. In a continuum model, we limit the treatment of electron scattering to inelastic attenuation in the overlayer. The ratio of reacted to substrate Ga 3d intensity can be written as!231
c o c ”
ImhO> Eq. (9)
Iwbhe>
exp(-iclAsin0)
=
is)
exp[-(n + i)d/hsin0]
i=O
Here, n is the number of bilayers of GaAs consumed in the reaction, d is the GaAs(OO1) interplanar spacing, and h is the attenuation length. In the bottom panel of Fig. 6 we show values of n extracted by fitting Eq. 9 to the experimentally measured intensity ratios. The number of reacted layers monotonically increases to -2.5 by a coverage of 10 ML. As a second example, we show in Fig. 7 Ga and As 3d core-level spectra for thin overlayers of Ni, Al and NiAl on GaSe,As,,(OO l), where x s0.75.1241 The purpose of this example is to illustrate how the extent of interfacial reaction can be modified by varying the composition of the metal flux. Deposition of Al induces cation exchange with Ga, as evidenced by the appearance of a new spin-orbit doublet -1 eV, to lower binding energy from the GaSe,As,.,(OOl) doublet. These peaks are associated with Ga
630
Compound Semiconductors
metal, and the intensity, relative to that associated with substrate emission, is consistent with the liberation of -2 ML of Ga, according to Eq. 9. There is, however, no evident disruption of the As sublattice. In contrast, Ni metal reacts with GaAs much more vigorously, as evidenced by the third set of spectra shown in the figure. Although only 4 ML of Ni were evaporated, the ratio of reacted to substrate Ga is much larger than in the case of Al, indicating a greater extent of reaction. In addition, disruption of the As sublattice is evident, based on the additional spin-orbit pairs in the As 3d spectrum. Interestingly, coevaporation of Ni and Al results in significantly less reaction with the substrate than occurs when Ni is evaporated alone. The lower extent of reactivity with the substrate is a result of the high degree of reactivity of Ni with Al. The heat of formation of NiAl is -14 KcaVmol, indicating the strong thermodynamic tendency for the intermetallit phase to form. l”l Therefore, reaction of Ni and Al with each other on the surface presents an alternative pathway to reaction of Ni with the substrate. NiAl OVERLAYER
THICKNESS
(A)
30
25
20
15
10
5
NiAllp-GaAs
(0011
-2.5 -
B
0
1.0 GaAs substrate
8 0.5 B 2
0
1 0
2
4
6
8
NiAl OVERLAYER
10
12
COVERAGE
14
16
18
(ML)
Figure 6. Ga and As 3d reduced intensities (fop) and number of reacted substrate layers for the NiiGaAs(001) interface as a function of coverage. Equation (9) was used to determine the number of reacted substrate layers. (From Rej 23.) (bottom)
Characterization
of Surfaces and Interfaces
631
Ni, Al 81 NiAI/GaSe,As,_,(OOl) 9s WI
/\,
22
21
20
/?\
0.86(7)
19
18
/!I
17 ”
44
t
I
*
43
42
41
(
I
40
39
BINDING ENERGY IeVl
Figure 7. Core-level spectra for Se-passivated GaAs(001) overlayers, taken from Ref. 24.
with and without thin metal
Also shown are the Schottky barrier heights for the metal/
semiconductor interfaces extracted from the core-level photoemission spectra.
Inspection of Fig. 7 also reveals large Ga and As 3d binding energy shifts in going from the clean GaSe,As,,(OOl) surface to the metallized surface. These changes are due to changes in band bending in the substrate, and are discussed in detail in Sec. 4.1. We show in Fig. 7 the Schottky barrier height (+u) for the metal/semiconductor interface, which is directly related to band bending in the substrate. This quantity is readily determined from the absolute core-level binding energies associated with substrate emission, and is also discussed in Sec. 4.1.
632
Compound Semiconductors
4.0
DETERMINATION OF ELECTRONIC ENERGY LEVELS AT COMPOUND SEMICONDUCTOR SURFACES AND INTERFACES BY XPS
4.1
Measurement of Band Bending and Schottky Barrier Heights
Electron spectroscopic techniques have traditionally been recognized for the elemental and chemical information that can be extracted from experimental EDCs. However, XPS and SRPS are also of considerable value in determining certain key electronic properties of semiconductor surfaces and interfaces. Two such properties are the band bending at free semiconductor surfaces and the Schottky barrier height (SBH) of metal/ semiconductor interfaces. These two quantities are illustrated in Fig. 8. The band bending, A, is a result of charge accumulation in forbidden gap states at the surface that originate with the formation of the surface. Truncation of the bulk crystal to form a surface can create states in the forbidden gap. Such states are typically acceptor- (donor-) like for n- (p-) type material. The existence and population of such states by carriers from the depletion region results in an electric field across the depletion region and, therefore, a continuous change in electrostatic potential in going from the neutral bulk to the charged surface. The origin of these states has been identified by scanning tunneling microscopy as electron-accepting kink sites on highly-doped n-GaAs(OOl)-c(2 x 8)/(2 x 4) surfaces.t251 Structural defects and contamination are also expected to produce such states on free surfaces, and defects induced by reaction with metal atoms in a metallization overlayer will generate gap states at metal/semiconductor interfaces.[261 In contrast to GaAs(OOl), cleaved GaAs( 110) of high surface quality does not exhibit band bending. A surface reconstruction that occurs sweeps the surface states out of the forbidden gap. The SBH, denoted by +u, is the electrostatic barrier to charge transfer across the metal/semiconductor interface. As shown in Fig. 8, QB= A + E, for n-type material. Here, E, is the energy of the conduction band relative to the Fermi level. The SBH can be determined by XPS for a metal/ semiconductor interface via analysis of core-level binding energies in the following way.t27l First, one measures (E,, -E,)“, the energy difference between some core level and the valence band maximum for a clean surface of the semiconductor of interest. Care must be taken to separate the peak(s) originating from surface-layer atoms from those associated with subsurface emission. The presence of such surface-shifted peaks in the raw EDC can
Characterization of Surfaces and Interfaces
633
add significant error to (E,, -Ev)s, if not properly removed. The value of (ECLXv)” exhibited by the clean surface will also be appropriate for the metal/semiconductor interface. Next, the metal film is grown so that the total film thickness d is less than -3k, where h is the photoelectron attenuation length. A substrate core-level binding energy relative to the Fermi level, E,, is then measured. It is essential that the contribution from any interface reaction products that form be removed from the total EDC so that the substrate binding energy can be unambiguously determined. To this end, it is helpful to utilize core levels associated with different elements of the semiconductor in order to have independent measures of &+ By inspection of Fig. 8, it is clear that Ev = & - (ECL- Ev)“, and that +n = Es - E,.
Bulk Semiconductor
Surface Vacu;t;, or or interface overlayer
A >- L z z w f, F z: ti
(ECL - Ev)S ECL
/
Figure 8. Energy diagram of a free semiconductor surface showing the relevant quantities needed in order to determine the Schottky barrier height for a metal/semiconductor interface.
Returning to Fig. 7, we show some examples of this kind of analysis. We start with the free surface of GaSe,As,,(OOl). This surface was prepared by heating a freshly grown Se-doped GaAs(OO1) buffer layer in H,Se at 425°C in a metal organic chemical vapor deposition (MOCVD) reactor.l24l Pyrolysis of H,Se occurs on the surface, and Se atoms are incorporated into the near-surface region of the substrate.l**l The surface
634
Compound Semiconductors
possesses long-range order, exhibiting a (2 x 1) low-energy electron diffraction (LEED) pattern. XPD analysis (discussed in Sec. 5.1) reveals that the outermost layer consists of -75% Se and -25% As. Se-As anion exchange occurs for the first 3 or 4 anion layers, with the Se concentration diminishing with depth.12*l Thus, a graded ternary phase that is lattice-matched to the substrate is formed, and band bending is reduced considerably from the value of the free surface. The value of +n for the clean ternary surface is -0.26 eV, averaged over the two core levels. The analogous value for nGaAs(OOl)-(2 x 4) is 0.6-0.7 eV, indicating that the surface Fermi level is pinned near midgap for this surface. The reduction in band bending by nearly 0.5 eV is most likely the result of either highly coherent bonding across the GaSe,As,JGaAs interface, or by the creation of a (2 x 1) surface mesh, in which there are no missing dimers.12*l In either case, the density of gap states is reduced relative to the GaAs(OOl)-(2 x 4) surface. Alternatively, the inclusion of a high concentration of group VI anions, as substitutional defects in the near-surface region of a III-V semiconductor, is expected to degenerately dope the surface n-type, which could result in Fermi-level pinning near the conduction band at the surface. Changes in the band bending occur upon metallization with either Al, Ni, or NiAl. Growth of (00 l)-oriented Al at 50°C causes a modest increase in band bending, so that the SBH is -0.48 eV. In contrast, growth of either Ni or NiAl results in a substantial increase in $n, to -0.9 eV. The primary difference between the growth of Al and the growth of either Ni or NiAl has to do with disruption of the anion sublattice. Both Ni and NiAl overgrowth liberate As from the substrate, as evidenced by the additional spin-orbit pairs in the As 3d spectra. In contrast, there is apparently no disruption of As when Al is grown. Thus, it appears that the more substantial increase in Qu is related to the disruption of As from the surface. Interestingly, the value of $u that results from growth of NiAl on GaSe,As,, is the same as that measured after growth on n-GaAs(OO1). From these and other data, we conclude that the particular chemistry of interface formation between NiAl and either GaAs or GaSe,As,, leads to a unique set of defects that give rise to Fermi-level pinning rather deep in the gap. It is of interest to determine the extent of agreement between SBH values determined by XPS and those determined by other techniques, such as IV and CV measurements. Waldrop and Grant have carried out several studies in which +u was measured by these different methods for the same specimens.1291-1311 The three methods produce results in rather good mutual agreement in cases where carrier transport across the interface is well
Characterization
of Surfaces and Interfaces
635
described by the Richardson equation for thermionic emission for IV, and the standard capacitance model for CV. For instance, these authors have measured +n for thin Au, Cr, and Ti metallizations on n-GaAs(OOl) in which a p+-Si layer between the metallization and the GaAs substrate was used to increase the barrier height.t301 The barrier heights measured by means of XPS, IV, and CV are in agreement to within kO.1 eV. Furthermore, the ideal&y factors (n) extracted from fitting the Richardson equation to the IV data are within 10% of an ideal value of 1.02. In addition to increasing the SBH, the Si interlayer acts as a diffusion barrier between the metal and the GaAs substrate. Thus, significant interface chemistry, which can cause spurious results when the IV and CV methods are used, was avoided. Agreement among the three methods is not as good in cases where the thermionic emission model fails, or in cases where interface chemistry results in phases that significantly modify the series resistance or capacitance at the interface. For example, XPS measurements of W thin films on n-GaAs(OO1) by Waldrop reveal that +u is 0.9 eV for oxide-free substrates and substrates with a thin native oxide.lzgl In contrast, the values extracted by the IV and CV techniques for clean substrates were 0.66 eV (n = 1.26) and 0.98 eV, respectively. Values of -0.7 eV (IV) and 1.34 eV (CV) resulted when a thin native oxide was present on the substrate prior to metallization. Interestingly, the ideality factor could not be reliably determined for metallization on the thin native oxide because the series resistance across the interface was several MR. This high series resistance limits the current density range over which the measurement can be made, thereby reducing the reliability of both +u and n. The low $n value determined by the IV technique for the clean substrate, along with the high ideal&y factor, signals a departure from the thermionic transport model upon which extraction of +n depends. The high value of +n determined by the CV method for the substrate with a thin native oxide comes about because of the anomalous capacitance created at the interface by the presence of the oxide. Significantly, extraction of $n from the IV and CV techniques depends critically on the respective physical model employed in interpreting the data; any departures from these models exhibited by the system under study will result in erroneous results. In contrast, XPS measures Qn directly. One need only adequately separate the substrate emission peaks from those resulting from interface chemistry in order to obtain a reliable measure of +a.
636
Compound Semiconductors
4.2
Measurement of Surface State Charge Densities
Solving Poisson’s equation for boundary conditions, appropriate to the depletion region near a semiconductor surface, yields a relationship between the surface potential and the charge density associated with surface states in the forbidden gap. The relationship is given by:13*I en: CD(O)= - -
Eq.(10)
2&N Here, O(O) is the electrostatic potential evaluated at the surface (z = 0), which is numerically equal to the band bending, A, n, is tbe surface-state charge density, E is the dielectric constant for the semiconductor, and N is tbe bulk dopant density. The potential at depths beneath the depletion region is taken to be zero. The same relationship is obeyed when an overlayer is present and the Fermi level is pinned at the interface. In this case, O(O) is the interface potential and n, is the interface-state charge density. In principle, XPS should be useful for determining %, since CD(O) can be determined from core-level binding energies, as described in Sec. 4.1. However, one additional refinement is required to obtain the most precise values of the Q(O) and rg. The surface or interface potential extracted from XPS is actually a weighted average over the probing depth of the experiment, which is -3GnO. The XPS experiment will sense much of the full potential drop across the space-charge region, if the probing depth is comparable to the depletion width. Quantitatively, the relationship between the surface potential measured at a detection angle 8, (D(e), and the depth-dependent potential within the depletion region, a(z), is given for a free surface by:1331
@(z)exp(-&sin@dz
Eq. (11)
@(0) =
Oo.
J
exp(-z/hsine)dz
0
Integration over z yields:
Characterization
of Surfaces and Interfaces
637
Eq. (12)
Insertion of Co(e)as measured by XPS into Eq. (12) yields the true surface potential. The divergence between Q>(O)and
638
Compound Semiconductors
SBH values (AE,,,,) shown in the figure are averaged over the probing depth. It is of interest that there is only a slight reduction in band bending upon growth of the undoped Si overlayer. One might think that coherent bonding across the IV/III-V interface would significantly reduce surface states and, therefore, band bending. However, the reduction is very slight, if outside of experimental uncertainty at all. Therefore, it appears that the Fermi level remains pinned at -0.6 eV below the conduction-band minimum. The interface-state charge density is -2 x 1012cmm2for the tmdoped Si overlayer. In contrast, growth of a heavily Asdoped overlayer results in a considerable drop in @n relative to the clean-surface value, from 0.65 eV to 0.27 eV. In addition, n, is reduced to -1.5 x 1012 cmW2.This result suggests that the mechanism of barrier height reduction has to do with electron transfer from the n+-Si overlayer into the depletion region of the substrate. Such charge transfer would have the effect of reducing the space charge and, therefore, the interface potential. Si/n-GaAs(OO1) NORMAL EMISSION Al Ka si2Q
9A n’-Siln-GaAslOOlI
I
:
;
:
21
20
19
: 1s
102
101
100
99
98
BINDING ENERGY WI
Figure 9. Ga 3d and Si 2p XPS spectra for undoped and n+-Si overlayers on n-GaAs(OOl), taken from Ref. 34. Also shown are the energy differences between the conduction-band minimum and the Fermi level, as extracted from the absolute core-level binding energies. The interface state density can be determined from these numbers by means of Eqs. (lo)(12), as explained in the text.
Characterization 4.3
Measurement
of Surfaces and Interfaces
639
of Band Offsets
XPS has also proven to be a usefL1 way to measure band discontinuities at heterojunctions. The technique is entirely independent of, and therefore complementary to, optical and electrical techniques. Analysis of core- and valence-level spectra for the isolated semiconductors, as well as the completed heterojunction, enables the investigator to extract the valence band offset for lattice-matched systems in a straightforward way. In order to outline the procedure as originally developed by Kraut et al.,[35j[36jwe show in Fig. 10 the relevant energies that need to be measured in order to perform this analysis. The key measurement that must be performed for the isolated semiconductor surfaces is the energy difference between an appropriate core level and the valence band maximtm~, with appropriate care being taken to remove the surface core-level shift. These quantities are shown as (E,,I - EVI)Sand (Ecr.2- Ev,)” in Fig. 10 for semiconductors 1 and 2, respectively. The superscript s denotes that these quantities are measured for the free surfaces of the two semiconductors. Upon formation of the heterojunction, the quantity that must be measured is the energy difference between the two core levels, which is denoted as (E,, - EcLl)int. As in the case of metal/semiconductor interfaces, the overlayer thickness must be, limited to a value less than -3ksine in order that core-level photoemission from the substrate be detectable. By inspection, the valence band discontinuity is then given by the relation Eq. (13)
AE, = /(EC,,- EJ
- (EC,,- EJI
+ (EcL2- ECL1)int
Once AE, is determined, AEc is given by AE, - AE,. Accurate determination of these energy differences requires curve fitting of both core- and valence-band photoemission spectra. Core-level spectra are typically fit to either a linear combination of Gaussian and Lorentzian functions, or to a Voigt function. The contribution to the total core-level EDC of peaks resulting from any interface chemical reactions that occur must be carefully removed to allow the substrate binding energy to be accurately determined. The valence band spectrum can be fit to a Gaussian-broadened theoretical density of states, as described in Refs. 35 and 36, and illustrated in Fig. 11. Band ofBets can then be determined with an uncertainty as low as - HI.05 eV. We present in Table 2 a list of band offsets for a variety of lattice-matched heterojunctions determined by XPS, along with appropriate references.
640
Compound Semiconductors
Semiconduaor 1
Semiconductor 2
6~~2 - Ev2)S ECLI
(ECLZ - EcLI)~”
__1 __
1
ECU
Figure 10. Energy diagram for a heterojunction showing the relevant quantities to be measured by XPS in order to determine the band offset. See text for details.
10
GaAs VBDOS
ENERGY
(eV)
2
0 ENERGY (eV)
Figure 11. Core-level and valence-band spectra for cleaved GaAs(ll0) (inset), along with a fit of the leading edge of valence band emission to a Gaussian-broadened theoretical density of states, taken from Ref. 35. The energy difference between the core levels and the valence band maximum is needed to determine the band offset, as described in the text.
Characterization
of Surfaces and Interfaces
641
Table 2. Valence Band Offsets D_etermined by XPS for Lattice Matched Heterojunctions Heterojunction
A& (eV)
Reference
GaAs/Ge(OO1)
0.36-0.56b
37 38 39 40 40 40 40 40 41 42 42 43
Ge/GaAs( 110) Ge/GaAs(OO1) Ge/AlAs( 110) GaAs/AlAs( 110) AlAs/GaAs( 110) GaAs/AlAs(OO1) AlAs/GaAs(OO1) AlAs/GaAs(OO1) GaAs/AlAs(OO1) AlAs/GaAs(OO1) GaAs/l ML Si/AlAs(OOl) A&s/l ML WGaAs(OO1) GaAs/ 1 ML Ge/AlAs(OO1) A&s/l ML Ge/GaAs(OOl) ~~.,,Gao.‘wwOOl) Irbs3GawAsJ ~O.,,Al,,sAs(OO 1) LnP/InwAl,,,As(OO 1) JnPk,.,,A&.,sAs(OO 1) Ge/ZnSe( 110) ZnSe/Ge( 110) CuBr/Ge( 110) CuBr/GaAs( 110) ZnSe/GaAs( 110) CdSe/ZnTe(OO1) CdTe/HgTe( 111)
0.53(3) 0.60(5) 0.9 0.42 0.55 0.36 0.46 0.40(7) 0.46(7) 0.46(7) 0.68 o-o. 1 0.75 0.15 0.34
43 43 43 44
0.22 0.16 (direct) 0.11 (interpolated)
44 45 45
1.54(4) 1.31(4) 0.7 0.85
46 46 47 47 46 48 49
0.95(4) 0.64(7) 0.35(6)
(a) Numbers in parentheses represent the uncertainty in the last digit of each entry. (b) Value depends on thermal treatment after growth. See Ref. 38.
642
Compound Semiconductors
Examination of the table reveals that different values for the band offsets have been measured in some cases when the interfacial system is grown in inverted order (i.e., A/B vs. B/A). For instance, Waldrop et al. suggested in 1987 that intrinsic differences in interface formation lead to different band offsets for the AlAs/GaAs(OOl) and GaAs/AlAs(OOl) heterojunctions.1401 The cause of these differences was thought to be an asymmetric potential well resulting from inherent structural differences at the interface, which in turn depend on the growth sequence. However, more recently, Yu et al. report that there is no difference in AE, for these two systems, at least under the growth conditions employed.l42l Comparison of the results by Yu et al. with those from Waldrop et al. clearly demonstrates that the growth conditions and the resulting interface quality can have a significant effect on the measured value of AE,. Indeed, commutativity (i.e., a lack of dependence on growth sequence) in the band offset is expected for heterojunctions involving common-type semiconductors (e.g., III-V/III-V). For interfaces of uncommon-type semiconductors (e.g., IV/ III-V), commutativity is not as likely to occur, and Table 2 contains examples to this effect. The entries in Table 2 for InP/Ir@l,_~As(OOl) were obtained by two techniques-the direct method, as discussed above, and an interpolation method suggested by Waldrop et al. l45l The interpolation method centers around measuring the band offsets for the strained endpoint systems(Ga,Al)As/InP(OO 1) and InAs/InP(OO 1), and then interpolating to the intermediate, lattice-matched composition. We show in Fig. 12 a plot of AE, vs. x for the Al-based system, taken from Ref. 45, which illustrates how this procedure works. The presence of strain causes the approach outlined above to be unreliable, due to strain-induced modifications in the electronic Uniaxial strain causes a loss of structure of the overlayer material. degeneracy in the heavy-hole and light-hole valence bands. The energies of the heavy-hole (vl) and light-hole (~2) valence bands in the In,Al,,As overlayer relative to the InP valence band, as calculated at the F point assuming perfect pseudomorphic growth, are plotted as a function of x in Fig. 12 along with experimental AE, values. Although the XPSderived AEv values for the endpoints are not correct because of the neglect of strain corrections, the interpolated value at x = 0.52 is reliable. The interpolated AEv and the value of AE, measured directly (indicated by the dots at x = 0.52) agree to within 0.05 eV.
Characterization
0.6
-0.6
,
.O AlAs
,
’
’ 0.2
,
’
of Surfaces and Interfaces
I
I
I
’ 0.4
’ x
’ 0.6
I
I
’
’ 0.6
643
I
’
’ 1.0 InAs
Figure 12. Measured (dots) and experimentally extrapolated (solid line) valence band offsets for the In.&XAs/InP(OOl) interface as a function of x, along with heavy (vl) and light (~2) hole valence band energies. (Takenfiom Ref: 45.)
In addition, Table II contains entries for GaAs/Si/AlAs(OOl) and AlAs/Si/GaAs(OO l), in which it is demonstrated that the band offset can be modified by the use of thin interlayers. In this case, Bratina et al. have utilized group-IV interlayers to adjust the interfacial charge distribution at The a III-V/III-V heterojunction. 1431 The results are rather dramatic. valence-band offset can be tuned from a common value of -0.45 eV for no Si interlayer for both systems, to -0.7 eV for GaAsll ML WAlAs(00 1) and to -0.1 eV for AlAs/ ML WGaAs(OO1). The detailed mechanism of interface potential modification by the group-IV interlayer is not known at this point, due primarily to our lack of knowledge of atomic positions at the interface. However, it is clear from these results that control over the band offset can be gained by the judicious use of interlayers. The primary challenge, from the point of view of understanding how these changes occur, is to perform definitive experiments on the interfacial structure, and then to use these insights to model and correlate with the electronic structure at the interface.
644
Compound Semiconductors
The analysis outlined above for lattice-matched systems is greatly complicated by the presence of strain in the overlayer, as mentioned above. Both hydrostatic and uniaxial strain that result from lattice mismatch between the two semiconductors can cause significant changes in the electronic structure of the strained semiconductor. Hydrostatic strain typically results in a rigid shift in the energies of the light-hole, heavy-hole, and spin-orbit valence-band centroids relative to the core levels. Uniaxial, volume-conserving strain universally results in a loss in degeneracy within the valence bands. Thus, (ECL - E,), as determined for an unstrained semiconductor, cannot be used reliably for a system in which the material is strained without making a suitable correction.[441[451[501~511 Corrections have been suggested based on both theoretical and experimental results. It has been suggested that theoretical deformation potentials could be used to generate a suitable strain correction to (EcL - EV).1441145115011511 The correction is given by a(AV/V), where a is the calculated (E,, - E,) deformation potential, and AV is the volume change brought about by accommodation of the lattice-mismatched overlayer to the substrate lattice dimensions. AV is typically determined by measuring the in-plane lattice constant in the strained overlayer and then using Poisson’s ratio to estimate the perpendicular strain. This approach has predicted shifts in (ECL- E,) that are considerably larger than what is observed in certain cases such as the GaAs/InAs( 110) system. Combining a calculated loss in LMTO (linear muffin-tin orbital) deformation potential for the difference in 3d core-level binding energies between Ga and As with AV determined as described above for a thin, strained overlayer of GaAs on In&( 1lo), Christiansen predicts a shift of 0.2 eV in the Ga-As 3d core-level binding energy difference relative to the value measured for unstrained GaAs(1 lo), as referenced in the work by Grant et al.15il However, the measured difference is zero within experimental error. Somewhat better success has been achieved for the strained, elemental semiconductor heterojunctions Ge/Si(OO1) and Si/Ge(OOl). Schwartz et al. have combined experimental (E,, - EV) values derived from XPS spectra with appropriate strain corrections from LMTO theory, resulting in valence band offsets of 0.74 f 0.13 eV and 0.17 f 0.13 eV for Ge on Si(O01) and Si on Ge(OOl), respectively.l50l These values are in fair agreement with band offsets determined from first-principles calculations by Van de Walle and Martin. These authors predict valence band discontinuities of 0.84 eV and 0.31 eV, for Ge on Si(OO1) and Si on Ge(OOl),
Characterization
of Surfaces and Interfaces
645
respectively.[521The origins of the discrepancies noted for GaAs/InAs( 110) and Si/Ge(OO1) are not presently known; therefore, it seems prudent to use extreme caution when using theoretical deformation potentials to correct experimental (Ec, - E,) values in attempting to determine band offsets for strained heterojunctions. Two experimental approaches for determining strain corrections have recently been suggested in the literature. Yu et al. measured (EcL - Ev) directly for strained overlayers by growing Si on fully-relaxed Ge,Si,,, which was, in turn, grown on Ge(O01).1531Here, x was varied from 0 to 0.30. The Si overlayer thickness was sufficient to completely attenuate photoemission from the alloy, yet small enough that the critical thickness was not exceeded. Similar growths of Ge on full-relaxed Si,Ge,, on Si(OO1)(x = 0 to 0.3) were carried out to determine the strain correction for pseudomorphic Ge. In each case, (Ec, - E,) was measured as a function of x, and extrapolating (EcL- E,) to x = 1 was assumed to generate a suitable estimate for fully-strained Si and Ge. This approach resulted in valenceband offsets of 0.83 f 0.11 eV and 0.22 f 0.13 eV for Ge on Si(OO1)and Si on Ge(O0l), respectively. These values are in better agreement with theoretical expectations than those by Schwartz et al. Ni et al. introduced a different approach to determining AE, and AE, for Si on Si,Ge,, alloys from core-level XPS measurements.I54l These authors demonstrated that the surface Fermi-level could be moved to within a few tens of meV of the valence and conduction bands by doping the nearsurface region with implanted In and Sb ions, respectively. Furthermore, band bending was minimized by these treatments, as evidenced by the fact that the Si 2p binding energy could be moved by nearly the full value of the bandgap in going from In to Sb doping in Si(OO1). Therefore, it is possible to determine the valence and conduction band offsets directly from corelevel binding energies by subtracting spectra obtained after ion implantation with either In or Sb from those measured for undoped specimens. Strain-induced modifications in the valence band densities of states do not need to be considered in this approach. This procedure has led to bandgaps within 0.1 eV and band offsets within a few tens of meV of corresponding theoretical values for Si on Si,Ge,, alloys. In summary, it appears that the experimental approaches to strain correction in band offsets yield superior results, compared to the theoretical approaches that have been attempted to date.
646
Compound Semiconductors
5.0
STRUCTURE OF THE NEAR-SURFACE REGION BY XPD
5.1
Surface Termination of HgCdTe( 111)
The atom specificity inherent in the XPS and XPD techniques is of considerable value in the study of compound semiconductors. The spatial arrangements of atoms in the cation and anion sublattices differ in the zincblende structure. Thus, azimuthal angular distributions of intensities from the cationic and anionic species typically differ in a qualitative way. These differences can be used to determine the surface termination of the semiconductor, as recently demonstrated for HgCdTe( 11 1),1551 GaA~(O01),1~~1 and epitaxial overlayers of NiAl on GaAs(O0 l).1561 Figure 13 shows azimuthal scans at 0 = 35” of Hg 4f7,2,Cd 3d5,2,and Te 3d,,* intensity for H&,,C&.,,Te( 111) taken from Ref. 55. The specimen was inserted into the XPD spectrometer after growth by liquid-phase epitaxy. Once under UHV conditions, angular distributions of surfaces with and without additional surface preparation were measured. The authors report that angular distributions collected after mild AI-+ion sputtering, which resulted in preferential Hg depletion, are very similar to those measured for the surface without any UHV cleaning. Thus, XPD is a very useful tool for investigating the crystallinity of surfaces which are not perfectly clean or ordered; the longer attenuation lengths associated with photoelectrons of higher kinetic energy render the technique sensitive to subsurface layers. Scans of intensities from the two cationic species (top two solid curves) reveal significant similarities, as expected on the basis of the crystal structure. The subtle differences in the relative intensities of the Hg and Cd scans are in all likelihood due to differences in the de Broglie wavelengths of the two photoelectrons. Furthermore, these two scans are qualitatively different from that associated with photoemission from the anion (solid curve at bottom). In addition, the figure shows single scattering theory curves for the two possible surface terminations, the (111)-A (cation terminated) and (111)-B (anion terminated) surfaces. The degree of anisotropy, as measured by AI/I,, = (I,, - Imin)/Imax, is significantly lower for the experimental scans due to structural disorder at the surface which results from a lack of UHV surface cleaning and recrystallization. The disordered and contaminated layer at the surface adds an isotropic background to the anisotropic intensities from subsurface layers, thereby lowering the total anisotropy. In contrast, the theoretical scans assume perfect crystallinity. Nevertheless, agreement between the measured and calculated scans is
Characterization
of Surfaces and Interfaces
647
excellent with regard to peak positions and relative intensities when the (111)-A surface termination is assumed. A forward-scattering peak is seen in all three scans at + = 60°, corresponding to the low-index directions depicted by the solid arrows shown in the crystal structures at the top of the figure. In addition, significant higher-order interference modulations are observed and predicted at other azimuthal angles when the (111)-A surface polarity is modeled. The superior degree of agreement visually seen between experiment and theory employing the (111)-A termination is corroborated by R-factor analysis, which reveals lower R factors when the (111)-A surface is assumed in the calculations. Te emitter (0) (111)A
(1ll)B
ea.
R.
0.20
Cd 3d,.
E,+OLQeV
To 3dw
E,,#l4eV
z
Figure 13. Measured (solid curves) and calculated (dashed curves) Hg 4f,, Cd 3d,,2, and Te 3d,,, XF’D scans from Hg,,,Cd,,,,Te(ll l), taken from Ref. 55. Calculations were performed assuming the two possible surface terminations (A and B), as illustrated at the top of the figure. Also shown are the R-factors, indicating the goodness of the tit between theory and experiment.
648
Compound Semiconductors
5.2
Surface Passivation of III-V Semiconductor Group VI Anions
Surfaces with
The atom specificity inherent to XPD is also extremely valuable in determining the bonding sites of foreign atoms in the host lattice. For instance, XPD has been used to unambiguously determine that Se atoms incorporated into GaAs(O0 1) by heating the substrate in H,Se at temperatures above the pyrolytic decomposition temperature occupy anion sites.12*] This result is of technological importance because this surface exhibits considerably less band bending than clean, MBE-grown GaAs(OOl)-(2 x 4), indicating a reduction in surface states and some degree of Fermi-level unpinning. Figure 14 shows measured and calculated (single scattering) azimuthal scans of Ga, As and Se 3d intensities at a polar angle (e) of 35” off the surface plane for GaAs(O0 1) passivated with H,Se in an MOCVD reactor. These scans, as well as analogous scans at other polar angles, show a strong degree of similarity between the modulations of Se and As 3d intensities. In addition, the peaks and valleys in both scans are well reproduced by theory, in which the angular dependence of photoemission intensity from the anion sublattice is calculated (dashed curve between the experimental As and Se 3d scans). In contrast, the Ga 3d intensity scan is qualitatively different from those associated with photoemission from the anionic species. These results, in conjunction with the stoichiometry of the near-surface region as determined by XPS, establish that Se and As atoms undergo an anion exchange reaction in the near-surface region. The resulting system is a lattice-matched GaSe,As,_.JGaAs(OO1) interface in which electronic passivation occurs in all likelihood by minimization of dangling bonds and associated gap states at the interface. This study illustrates that XPS and XPD constitute a powerful combination of techniques for determining the composition, structure, and band bending at compound semiconductor surfaces and interfaces. Having these three kinds of information at hand for a particular system allows the investigator to make correlations that can yield deep insight into the interrelations between the structural and electronic properties of the system.
Characterization
of Surfaces and Interfaces
649
SehGaAs(001) 8 = 35”
-1
II -10
10
30 AZIMUTHAL
50
I 70
90
ANGLE, I$ (degrees)
Figure 14. Measured and calculated Ga 3d, Se 3d, and As 3d angular distributions for Sepassivated GaAs(OOl), calculations.
where anion site occupancy for the Se atoms was assumed in the
The quality of the fit, as well as the similarity between the Se and As 3d
scans, confirms that Se atoms occupy anion sites. (From Ref: 28,)
6.0
CONCLUSIONS
This chapter illustrates the utility of x-ray photoelectron spectroscopy and diffraction in the study of compound semiconductor surfaces and interfaces. These techniques yield a variety of useful kinds of information about the composition, chemical and electronic states, and structure of the near-surface region. It is possible to analyze atomically clean and ordered surfaces and interfaces prepared under UHV conditions, as well as surfaces generated by various growth and processing steps that are subsequently transferred into the XPS/XPD spectrometer. Thus, the techniques are useful for both fundamental studies and process development.
650
Compound Semiconductors
ACKNOWLEDGMENT The author is indebted to R. W. Grant and J. R. Waldrop for helpful comments concerning this manuscript.
REFERENCES 1. Berglund, C. N. and Spicer, W. E., Whys. Rev., A136:1030-1044, 10441058 (1964) 2. Fadley, C. S., in: Synchrotron Radiation Research: Advances in Surface Science, (R. Z. Bachrach, ed.), chap. 11, Plenum Press, NY (1990) 3. Chambers, S.A., Advances in Physics, (S. Doniach, ed.), pp. 357-415, Taylor and Francis, London (199 1) 4. Chambers, S. A., in: Surf Sci. Rep., (T. E. Madey, ed.), 16:261-331 (1992) 5. Fadley, C. S., in: Electron Spectroscopy, Theory, Techniques, and Applications, (C. R. Brundle and A. D. Baker, eds.), ch. 1, Pergamon Press (1978) 6. Fadley, C. S., Physica Scripta, T17:39 (1987) 7. Barton, J. J., Bahr, C. C., Hussain, Z., Robey, S. W., Tobin, J. G., Klebanoff, L. E., and Shirley, D. A., Phys. Rev. Lett., 51:272-275 (1983) 8. Barton, J. J., Rohey, S. W., Bahr, C. C., and Shirley, D. A., The Structure of Surfaces, (M. A. Van Hove and S. Y. Tong, eds.), p. 19 1-198, SpringerVerlag, Berlin (1985) 9. Barton, J. J. and Shirley, D. A., Phys. Rev. B32:1892-1905, (1985)(1985)
1906-1920
10. Sagurton, M., Bullock, E. L., and Fadley, C. S., Surf: Sci., 182:287 (1987) 11. Weaver, J. H., in: Electronic Materials, (J. R Cheilkowsky and A. Franciosi, eds.), ch. 7, Springer-Verlag, Berlin (1991) 12. The ESCA 300 Spectrometer from Scienta Instruments in Uppsala, Sweden features the highest x-ray intensity from a conventional lab x-ray source and the best spectral energy resolution currently commercially available. 13. Tanuma, S., Powell, C. J., and Penn, D. R., Surf. andInt. Anal., 11:577589 (1988) 14. Schiff, L. I., Quantum Mechanics, ch. 11, McGraw-Hill, New York (1968) 15. Manne, R. and Aberg, T., Chem. Phys. Lett., 7:282 (1970) 16. Egelhoff, W. F., Jr., Crit. Rev. Sol. St. Mat. Sci., 16:213-235 (1990)
Characterization
of Surfaces and Interfaces
651
17. Kadewula, A. P., Friedman, D. J., and Fadley, C. S., J. Electr. Spectros. Rel. Phen., 571223-278 (1991) 18. Lu, Z. H., Largarde, C., Sacher, E., Currie, J. F., and Yelon, A., J. Vat. Sci. Technol., A7:646650 (1989) 19. Grunthaner, F. J., Grunthaner, P. J., Vasquez, R. P., Lewis, B. F., and Maserjian, J., J. Vuc. Sci. Technol., 16:1443-1453 (1979) 20. Grunthaner, P. J., Vasquez, R. P., and Grunthaner, F. J., J. Vuc. Sci. Technol., 17:1045-1051 (1980) 21. Vasquez, R. P., Lewis, B. F., and Grunthaner, F. J., Appl. Phys. Lett., 42:293 (1983) 22. Ingrey, S., Lau, W. M., and McIntyre, N. S., J. Vat. Sci. Technol., A4:984-988 (1986) 23. Chambers, S. A. and Loebs, V. A., J. Vat. Sci. Technol. A, AIO: 19401945 (1992) 24. Chambers, S. A. and Loebs, V. A., Mat. Res. Sot. Proc., 221:283-288 (1991) 25. Pashley, M. D., Haberern, K. W., and Feenstra, R. M., J. Vat. Sci. Technol., Bl0:1874-1880 (1992) 26. Please refer to the proceedings of the Physics and Chemistry of Semiconductor Interfaces (PCSI) Conference, J. Vuc. Sci. Technol. B, from 1973 to the present for papers dealing with this subject. 27. Grant, R. W. and Waldrop, J. R., J. Vuc. Sci. Technol., B5:1015-1019 (1987) 28. Chambers, S. A. and Sundaram, V. S., Appl. Phys. Lett., 57:2342-2344 (1990), and, J. Vuc. Sci. Technol., B9:2256-2262 (1991) 29. Waldrop, J. R., Appl. Phys. Lett., 41:350-352 (1982) 30. Waldrop, J. R. and Grant, R. W., Appl. Phys. Lett., 52: 1794-1796 (1988) 3 1. Waldrop, J. R. and Grant, R. W., Appl. Phys. Lett., 50:250-252 (1987) 32. Dalven, R., Introduction to Applied Solid State Physics, pp. 145-147, Plenum Press, New York (1980) 33. Ogama, T., J. Appl. Phys., 64:6469-6476 (1988) 34. Chambers, S. A. and Loebs, V. A., Phys. Rev., Bl0:9513-9522
(1992)
35. Kraut, E. A., Grant, R. W., Waldrop, J. R., and Kowalczyk, S. P., Phys. Rev. Lett., 44: 1620-1623 (1980) 36. Kraut, E. A., Grant, R. W., Waldrop, J. R., and Kowalczyk, S. P., Phys. Rev., B28:1965-1977 (1983) 37. Waldrop, J. R., Grant, R. W., and Kraut, E. A., J. Vuc. Sci. Technol., B4:1060-1063 (1986)
652
Compound Semiconductors
38. Grant, R. W., Waldrop, J. R., and Kraut, E. A., J. Vat. Sci. Technol., 15:1451-1455 (1978) 39. Chambers, S. A., and Irwin, T. J., Phys. Rev., B38:7484-7492 (1988) 40. Waldrop, J. R., Grant, R. W., and Kraut, E. A., J. l&c. Sci. Technol., B5:1209-1214 (1987) 41. Chambers, S. A., Loebs, V. A. and Doyle, D. H., J. Vuc. Sci. Technol., B8:985-989
(1990)
42. Yu, E. T., Chow, D. H., and McGill, T. C., J. Vuc. Sci. Technol., B7:391394 (1989) 43. Bratina, G., Sorba, L., Antonini, Rev., B45:4528-453 1 (1992)
A., Biasiol, G., and Franciosi,
A., Phys.
44. Waldrop, J. R., Kraut, E. A., Farley, C. W., and Grant, R. W., J. Appl. Phys., 69:372-378 (1991) 45. Waldrop, J. R., Kraut, E. R., Farley, C. W., and Grant, R. W., J. Vuc. Sci. Technol., B8:768-772 (1990) 46. Kowalcqk, S. P., Grant, R. W., Waldrop, J. R., and Kraut, E. A., J. Vuc. Sci. Technol., 2 1:482-485 (1982) 47. Waldrop, J. R., and Grant, R. W., Phys. Rev. Lett., 43:1686-1689 48. Yu, E. T., Phillips, M. C., McCaldin, Technol., B9:2233-2237 (1991)
(1979)
J. O., and McGill, T. C., J. Vuc. Sci.
49. Grant, R. W., Kraut, E. A., Cheung, J. T., and Kowalczyk, S. P., J. Vuc. Sci. Technol., A5:3070-3073 (1987) 50. Schwartz, G. P., Hybertsen, M. S., Bevk, J., Nuzzo, R. G., Mannaerts, and Gualtieri, G. J., Phys. Rev., B39:1235-1241 (1989).
J. P.,
51. Grant, R. W., Waldrop, J. R., Kraut, E. A., and Harrison, W. A., J. Vuc. Sci. Technol., B8:736-740
(1990)
52. Van de Walle, C. G. and Martin, R .M., Phys. Rev., B34:5621-5634 (1986) 53. Yu, E. T., Croke, E. T., and McGill, T. C., Appl. Phys. Lett., 56:569-571 (1990) 54. Ni, W.-X., Knall, J., and Hansson, G. V., Surf: Sci., 189/190:379-384
(1987) 55. Herman, G. S., Friedman, D. J., Tran, T. T., Fadley, C. S., Granozzi, G., Rizzi, G. A., Osterwalder, J., and Bernardi, S., J. Vuc. Sci. Technol., B9:1870-1873
(1991)
56. Chambers, S. A., Phys. Rev., B42: 10,865 (1990)
13 Characterization of Compound Semiconductor Material by Ion Beams Stephen FKDowney
1.0
INTRODUCTION
Successful development of compound semiconductor device technology relies greatly on accurate materials characterization of the very complicated structures that produce high speed optical and electrical products. Elemental or chemical analysis of GaAs and related materials for both bulk (matrix) and minor (dopant) constituents is necessary in the research, development, and production stages of transistors, lasers, and related devices. The diagnostic techniques described in this chapter are concerned with elucidating chemical composition of layered III-V materials by detecting the results of charged particle (ion) beam interactions with solids. The discussion is separated into two parts; the detection of the (back) scattered incident ions by RBS, Rutherford Backscattering Spectrometry, and the analysis of target material sputtered during ion bombardment by SIMS, secondary ion mass spectrometry, and related techniques.
653
654
Compound Semiconductors
Because RBS and SIMS use the production, transport and detection of ions in their characterizations, the two techniques are very expensive to implement. Both techniques require high (or ultrahigh) vacuum, high voltages and/or magnetic fields, sensitive charged particle detectors, sophisticated computing, etc., so the cost of a modern instrument may easily exceed one million dollars. The knowledge gained from their use should be commensurate with the capital and operating costs of a large and complicated experiment that often needs more than one skilled operator. Hopefully it will become clear that information provided by RBS and SIMS is unavailable from any other analytical method. The sensitivity, specificity and depth resolution of matrix and dopant detection with minimal sample preparation is the hallmark of these ion beam based characterization techniques. 1.1
RBS References
An excellent introduction to RBS is found in the surface and thin film analysis textbook by Feldman and Mayer.1’1 Because virtually all III-V device substrates are prepared from single crystal material, the use of channeling in RBS requires much attention. This review draws heavily from the text by Feldman, Mayer, and Picraux121on this subject. Proceedings from the International Ion Beam Analysis meeting are found in Nuclear Instruments 1.2
andMethods,
Part B.
SIMS References
This review on SIMS characterization of III-V materials is fortunate to have a number of excellent references upon which to draw. An in depth treatise that covers the fundamentals of almost all aspects of SIMS has been written by Benninghoven, Rudenauer and Wemer.131 A more recent work, geared mainly to the practice of semiconductor analysis, is by Wilson, Stevie, and Magee. I41A similar review to this one, with an emphasis on InP materials has been written by Geva.151 The textbook by Feldman and Mayer also has an excellent section on the fundamentals and application of SIMS as well as RBS. Any similarities of this work to these excellent references is purely intentional. The proceedings of the biannual international conferences on SIMS are excellent sources for keeping up with SIMS technology and applica-
Characterization by Ion Beams 655 tions.i61 Proceedings of special topics conferences, such as the Molecular Beam Epitaxy Workshop, American Vacuum Society annual meetings, and others, are often published in the Journal of Vacuum Science and Technology. The journal Surface and Interface Analysis also contains articles pertinent to compound semiconductor characterization by SIMS. The sections of this chapter that deal with sputter-based depth profiling may seem to have an exceptionally large amount of information about sputtered neutral mass spectrometry, or post-ionization techniques, because the author has experience in this field of research. In addition,’ many of the applications of the techniques covered here will be examples ii-om his institution. This is only for the convenience of obtaining useful illustrations and is not meant to suggest that other institutions are not active in these fields of work. 1.3
Fundamentals
of Ion-Solid Interactions
When a high velocity ion strikes the a solid, the ion will transfer some, or all, of its energy to the solid. For singly charged ions, the energy is numerically the same as the acceleration voltage, (E = qv). The manner of energy transfer depends upon many parameters, including the masses of the incident ion and collisional target nuclei and the energy and angle of incidence of the incoming projectile. Low energy ions, (< 100 eV) typically stop on or near the surface, thus building thin films. Incident, or primary ions with I-20 keV of energy transfer energy to the sample’s nuclei, which leads to sputtering, the sequential removal of surface layers, which forms the basis of analysis of the solids by secondary ion mass spectrometry (SIMS). At high er energies, (100-300 keV), ions implant into the solid, modifying its elemental composition. Some sputtering occurs, but most of the ions and their energy are implanted deeply (> 1000 A) into the solid. Implantation damage and mixing of material hinders the analysis of layered samples with these high energy primary ions. However, ion implantation is widely used to control the electrical properties of semiconductors. MeV ions, especially He ions, penetrate very deeply into the solid (microns), loosing small amounts of energy to the solid’s electrons until a scattering event occurs with a nucleus. Minimal damage to the sample occurs because most of the energy remains in the backscattered ion. Accordingly, He ion backscattering affords nondestructive surface and bulk chemical analysis.
656
Compound Semiconductors
2.0
RUTHERFORD BACKSCATTERING SPECTROMETRY (RBS)
2.1
Kinematics
When a high energy (MeV) bare He or H ion moves through matter, it is so small compared to the internuclear distances in the solid that nuclear collisions are nearly unimportant in determining the energy transfer between the ion and solid. Ultimately, however, the ion has an elastic, backscattering collision with a nucleus, transferring some energy to the The energy remaining in the ion is stationary target in the process. determined by the masses of the ion and target, and the scattering angle. The ratio of the outgoing energy to the incident energy is called the kinematic factor, K.
Eq. (1)
Equation (1) is valid at 180” backscattering angle. M, is the mass of the incident ion, typically 4He, and M, is the mass of the target isotope. In this geometry, the ion experiences its greatest possible energy loss, so K is a minimum. These conditions are also where the sensitivity to changes in mass of the target is greatest, affording the best isotopic selectivity. The energy spectrum of backscattered particles will show small energy shifts for high atomic mass and greater shifts for low masses. Thus, the technique is ideally suited for determining heavy impurities in the presence of lighter atom host matrices (e.g., Ft on GaAs-see Fig. 1). Quantitative information about the number of impurity atoms on or near the surface is obtained by measuring the fraction or yield, Y, of backscattered particles from N, atoms/cm2 if the ion dose, Q, the differential scattering cross section, da/ dR, and the particle collection solid angle, M, of the detection system are known. The scattering cross section scales as (Z,Z,)2, where Z, and Z, are the charges of the incident and target nuclei, therefore larger targets have greater yields for detection.
Eq. (2)
Y=N,gAflQ
Characterization Energy 0.6 I
1.0x10’
0.6
m 0.6 z a 0 0.4
0.2
0.0
0.8 I
1.0 I
2;o
657
(MeV) 1.2 I
1
1 00
by Ion Beams
3;0
1.4 I
1.6 I
1.6
Pt
460
i
5010
Channel
Figure 1. RBS spectrum of 500 A Ti and 750 A Pt on GaAs. The energy of the incident He+ beam is 1.8 MeV. Although the Ti is above the GaAs, its lighter mass and smaller kinematic factor backscatter the He+ beam with the same energy as some of the GaAs. The Pt peak is well separated from the others because of its surface location and high kinematic factor. (Courtev o/B. Weir, AT&T Bell Laboratories.)
Thin films on surfaces produce energy spectra with peak widths, AE that are proportional to At, the films thickness. AE is the difference between the energies of particles scattered from the surface and those scattered from the film-substrate interface. Incident ions backscattered from surface atoms have energies that are defined by their K values. However, most ions penetrate the film and solid before a large angle scattering event returns them to the detector. During the traverse in and out of the material, a small amount of energy is lost to the solids electrons. The amount of energy lost by the ion per unit distance as it travels in the solid, dE/dx, has units of eV/ A. AE is therefore (dE/dx)At for the film material. In Fig. 1, AE for the Pt peak is roughly 0.1 MeV, which is consistent with an average dE/dx of 0.15 keV/A and At of 750 A. Obviously, from the measured AE, either parameter can be determined if the other is known. This simplistic picture is based on the approximation of constant dE/dx, which pertains only to very thin films. Multilayer structures, commonly found in III-V materials, can be analyzed by RBS for layer thickness or compositional determination. For example, x and At can be derived from fitting REX3spectra for AlGai_& layers.1’1 Interestingly, the lighter mass Al content is determined indirectly by the diminution of Ga signal. See Fig. 2.
658
Compound Semiconductors
0000
. _.:.
.
.,
.
6400
;
;;;;
[[AS
1600
_ 0 0.474
325;
0 3 1 OA I
.
.
..
--__
1
. .
Gods AR,,25Ga075A~ I
I
I
I
Energy
x 0.602
0.746
0.610
I 1.010
(MeV)
Figure 2. RBS spectrum from a sample with approximately 300 A of GaAs on 300 A of AlGaAs on G&s substrate. The inset line is plotted using a 2x expanded vertical scale. The signal from the Al is hard to detect because it falls on the substrate background. The Al content is inferred from the suppression of the Ga signal from the AlGaAs layer. The thickness and Al content of the AlGaAs layer can be determined from this spectrum. (From ReJ 7.)
The values of dE/dx are greatest for 4He2+ at energies around 0.5 MeV. Because dE/dx is inversely related to energy at typical RBS energies, (dE/dx), > (dE/dx),. A 2 MeV He ion loses about 22 eV/A in silicon. One MeV He looses about 28 eV/A. Thick layers (> 1 urn) or bulk specimens have a continuous energy spectrum to low energy as a result of backscattering from all depths. The scattering yield is not constant as a function of depth, for as the ions are slowed, they scatter more efficiently. The result is that more backscattered signal originates from the material deeper in the sample. Figure 1 has a broad background from a GaAs substrate. The greatest energy loss is to low mass isotopes, K I 0.75 for He backscattered from masses I 50.t11 In backscatter geometry, low mass nuclei are hard to detect. For example, at mass 23, Na, the kinematic factor, K is approximately 0.5. For B, masses 10 and 11, it is down to about 0.2. The sensitivity of the detector at these low energies is much reduced. This is especially true for light elements in heavy element matrices, e.g., Be in G&s. The scatter from the matrix at all depths produces a large energy spectrum and obscures the signal from the lighter element, even if it is on the surface. Lighter elements are usually detected by forward recoil spectroscopy, where the incoming ion mass is greater than the target mass. Measuring the energies of the recoiling nuclei is used to detect hydrogen on or near surfaces.
Characterization
by Ion Beams
659
The change in K gets smaller as mass increases. Mass resolution is thus dominated by the energy resolution of the instrumentation. If the detector’s resolution is 0.01 of the incident ion energy, differences in K of this order are detectable. Unit mass resolution may be possible below mass 40. The K values for mass 174 and 200 differ by only 0.01. RBS is therefore not well suited for qualitative analysis, especially at high mass. Mass spectrometry (SIMS) should be used to identify unknown constituents. However, RBS is typically a superior quantitative technique because the scattering is independent of the chemical environment of the atoms, whereas SIMS’s sensitivity is very dependent upon local ionization conditions. This is especially true for atoms on the surface where they may be oxidized. 2.2
Depth Resolution
The depth resolution in RBS is proportional to the energy resolution of the experiment, set by the detector. To maximize the energy lost, which gives increased depth sensitivity, grazing angle of incidence ions are used. In this way, the path length of ions through the material is increased, so the energy lost per unit depth is also increased. The incident ion energy can also be adjusted to increase energy loss in the matrix. In this geometry with fixed detector resolution, the energy, and hence depth resolution, is limited by the energy straggle, or fluctuations of the scattered ions. Ions scattered from the same depth do not necessarily have the same energy. Although dE/ dx is the same, it is an average value of a Gaussian distribution of energies. Typical depth resolution is roughly 100-500 A. When the width of this energy distribution becomes greater than the detector resolution, 15-20 keV, the factors contributing to straggle dominate the depth resolution. Grazing incidence improves depth resolution only in the near-surface region to sometimes better than 100 A. In all geometries, the deeper the ion goes into the solid, the greater the straggle, and hence, the worse the depth resolution. Also, the energy fluctuations are a function of the atomic number, Z, of the atoms in the target. This is because dE/dx is affected by electron density per unit area. RBS is not as sensitive as SIMS for determining trace impurities. The minimum detectable amount of material in the most favorable circumstances is about 10” monolayers with RBS, while with SIMS it may be 10” or lower. The detection limitations of both techniques are set by sputtering, that is, what is the smallest number of atoms that can be detected
660
Compound Semiconductors
from a film before it is eroded away? RBS is nominally a nondestructive technique, but the MeV He ions have a finite sputter yield which removes material. A comparison of Y, the yield of backscattered particles, as defined in Eq. (2), and the sputter yield will allow a calculation of the expected detection limit.lll 2.3
Nuclear Reactions
A type of depth profile can be obtained by taking advantage of the resonance-like behavior of certain nuclear reactions between target nuclei and incoming ions. The method is used most often to determine the abundance of lighter isotopes. These isotope specific, energy specific reactions produce radioactive product isotopes at depths corresponding to where the incoming ion has lost enough energy to come into resonance (increased cross section) with a particular nuclear reaction. From this location, a decay particle (typically y) is emitted. To obtain a depth profile, the ion beam’s energy is swept to change the depth where the reaction occurs. The amount of radioactivity detected gives the concentration and location of the reactive target nuclei if the cross section of the reaction and dE/dx for the material is known. This technique complements other depth profiling techniques such as SIMS, which may have more sensitivity but are somewhat difficult to calibrate. 2.4
Channeling
Compound semiconductor devices have many desirable properties, e.g., high speed, that are a result of good crystalline quality. Most devices are usually fabricated using epitaxial growth techniques of thin layers of materials. Ion backscattering can be used to determine crystal quality and structure.121 The periodic alignment of atoms in crystals produce columns of nuclei and channels of mostly empty space in between. For most analyses by RBS, the crystal axes are randomly aligned with the ion beam, thus obscuring these features and producing normal backscattered spectra. If a crystal is aligned properly to an incident collimated beam, MeV He ions are backscattered from the atomic columns but penetrate the channels very deeply, giving little signal. In general, the amount of signal in the channeling spectra relative to the nonaligned, random conditions is a measure of the crystal quality. Thus, channeling spectra give insight to
Characterization by Ion Beams 661 many crystal defects. By comparison, sputter-based depth profiling analytical techniques, such as SIMS, destroy crystallinity. Channeling, or aligned spectra are very surface sensitive because a greater fraction of the detected signal comes here. Chemical impurities or surface reconstructions are easier to detect if the backscatter from the bulk is suppressed.
3.0
SECONDARY ION MASS SPECTROMETRY RELATED TECHNIQUES
3.1
Sputtering
(SIMS) AND
Surfaces of solids erode during ion bombardment. The primary ion’s energy is deposited in the target and some portion of the atoms on or near the surface will recoil with enough energy to break their bonds and escape into the vacuum. A 1 PA, 10 keV ion beam impinging on a 100 pm diameter spot delivers more than 10 kW/cm2 to the target material. The energy transfers between the atoms in the matrix is usually referred to as the collisional cascade, where many nuclei exchange energy and momenta. Most (> 90%) of the particles are neutral but some will be ionized as the